WebKit Bugzilla
Attachment 339527 Details for
Bug 185283
: [JSC][GTK][JSCONLY] Use capstone disassembler
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[patch]
Patch
bug-185283-20180504164856.patch (text/plain), 17.10 MB, created by
Yusuke Suzuki
on 2018-05-04 00:49:04 PDT
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Description:
Patch
Filename:
MIME Type:
Creator:
Yusuke Suzuki
Created:
2018-05-04 00:49:04 PDT
Size:
17.10 MB
patch
obsolete
>Subversion Revision: 231347 >diff --git a/Source/JavaScriptCore/ChangeLog b/Source/JavaScriptCore/ChangeLog >index 2dbcc93bbae000f7075903cc393d4e5ef6c67545..c7058e833fc0820d56fd07d7aff9f32c8f4e517c 100644 >--- a/Source/JavaScriptCore/ChangeLog >+++ b/Source/JavaScriptCore/ChangeLog >@@ -1,3 +1,20 @@ >+2018-05-04 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by NOBODY (OOPS!). >+ >+ Instead of adding MIPS disassembler baked by ourselves, we import capstone disassembler. >+ And use capstone disassembler for all the JIT architectures in GTK, WPE, WinCairo and JSCOnly ports. >+ >+ Capstone is licensed under 3-clause BSD, which is acceptable in WebKit tree. >+ >+ * CMakeLists.txt: >+ * Sources.txt: >+ * disassembler/CapstoneDisassembler.cpp: Added. >+ (JSC::tryToDisassemble): >+ > 2018-05-03 Yusuke Suzuki <utatane.tea@gmail.com> > > Remove std::random_shuffle >diff --git a/Source/ThirdParty/ChangeLog b/Source/ThirdParty/ChangeLog >index 153819de1414589b4f8a48aaf66313b4bdbc281a..5ad96fe9173c3a14ad4dae59e440a15fd97339bc 100644 >--- a/Source/ThirdParty/ChangeLog >+++ b/Source/ThirdParty/ChangeLog >@@ -1,3 +1,20 @@ >+2018-05-04 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by NOBODY (OOPS!). >+ >+ Add capstone to ThirdParty. We build capstone as a static library, >+ and link it against JSC. We only build disassembler for target architecture. >+ So for X86_64 target, we only enable x86 part of capstone. >+ >+ We also remove unnecessary architectures in capstone, XCore, PowerPC, SystemZ, >+ and Sparc. This is simply done by deleting these architecture directories. >+ >+ * capstone/CMakeLists.txt: Added. >+ * capstone/capstone-Revision.txt: Added. >+ > 2018-03-05 Don Olmstead <don.olmstead@sony.com> > > [CMake] Split JSC header copying into public and private targets >diff --git a/Source/WTF/ChangeLog b/Source/WTF/ChangeLog >index 106a12a8d9cb8a84af20048b2999ec99c918aebd..5d09e941505d6c6f65f2c125b4ee9138de41feee 100644 >--- a/Source/WTF/ChangeLog >+++ b/Source/WTF/ChangeLog >@@ -1,3 +1,14 @@ >+2018-05-04 Yusuke Suzuki <utatane.tea@gmail.com> >+ >+ [JSC][GTK][JSCONLY] Use capstone disassembler >+ https://bugs.webkit.org/show_bug.cgi?id=185283 >+ >+ Reviewed by NOBODY (OOPS!). >+ >+ Add USE_CAPSTONE. In GTK, WPE, JSCONLY, and WinCairo, we always prefer capstone disassembler. >+ >+ * wtf/Platform.h: >+ > 2018-05-03 Yusuke Suzuki <utatane.tea@gmail.com> > > Use default std::optional if it is provided >diff --git a/Source/CMakeLists.txt b/Source/CMakeLists.txt >index 05d820721cee0c39b5b6e20093f0a4166b85f366..54fe4a2d2bc583c39f64851dff7541ee5c74665c 100644 >--- a/Source/CMakeLists.txt >+++ b/Source/CMakeLists.txt >@@ -7,6 +7,10 @@ endif () > > add_subdirectory(WTF) > >+if (USE_CAPSTONE) >+ add_subdirectory(ThirdParty/capstone) >+endif () >+ > add_subdirectory(JavaScriptCore) > > if (WIN32 AND ENABLE_GRAPHICS_CONTEXT_3D) >diff --git a/Source/JavaScriptCore/CMakeLists.txt b/Source/JavaScriptCore/CMakeLists.txt >index 7080962a66d1ddbba0ea53eb77d76a25e9c71d74..0c05953e02fc6bd8376e191dfe7e9f38c7cb7c2c 100644 >--- a/Source/JavaScriptCore/CMakeLists.txt >+++ b/Source/JavaScriptCore/CMakeLists.txt >@@ -50,6 +50,10 @@ set(JavaScriptCore_PRIVATE_INCLUDE_DIRECTORIES > "${DERIVED_SOURCES_JAVASCRIPTCORE_DIR}/yarr" > ) > >+if (USE_CAPSTONE) >+ list(APPEND JavaScriptCore_PRIVATE_INCLUDE_DIRECTORIES "${THIRDPARTY_DIR}/capstone/Source/include") >+endif () >+ > set(JavaScriptCore_SYSTEM_INCLUDE_DIRECTORIES > "${ICU_INCLUDE_DIRS}" > ) >@@ -118,6 +122,10 @@ set(JavaScriptCore_LIBRARIES > ${LLVM_LIBRARIES} > ) > >+if (USE_CAPSTONE) >+ list(APPEND JavaScriptCore_LIBRARIES capstone) >+endif () >+ > # Since r228149, on MIPS we need to link with -latomic, because > # __atomic_fetch_add_8 is not available as a compiler intrinsic. It is > # available on other platforms (including 32-bit Arm), so the link with >diff --git a/Source/JavaScriptCore/Sources.txt b/Source/JavaScriptCore/Sources.txt >index 5229f3b10421357bd926cc379185bd194a48f873..ebd790c7a78fa52296be9865344570d198ae5d04 100644 >--- a/Source/JavaScriptCore/Sources.txt >+++ b/Source/JavaScriptCore/Sources.txt >@@ -412,6 +412,7 @@ dfg/DFGWorklist.cpp > disassembler/ARM64Disassembler.cpp > disassembler/ARMLLVMDisassembler.cpp > disassembler/ARMv7Disassembler.cpp >+disassembler/CapstoneDisassembler.cpp > disassembler/Disassembler.cpp > disassembler/UDis86Disassembler.cpp > disassembler/X86Disassembler.cpp >diff --git a/Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp b/Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp >new file mode 100644 >index 0000000000000000000000000000000000000000..0bc7b0f12b98492d63dcc8156dfe73cb9dcfc0b8 >--- /dev/null >+++ b/Source/JavaScriptCore/disassembler/CapstoneDisassembler.cpp >@@ -0,0 +1,84 @@ >+/* >+ * Copyright (C) 2018 Yusuke Suzuki <utatane.tea@gmail.com>. >+ * >+ * Redistribution and use in source and binary forms, with or without >+ * modification, are permitted provided that the following conditions >+ * are met: >+ * 1. Redistributions of source code must retain the above copyright >+ * notice, this list of conditions and the following disclaimer. >+ * 2. Redistributions in binary form must reproduce the above copyright >+ * notice, this list of conditions and the following disclaimer in the >+ * documentation and/or other materials provided with the distribution. >+ * >+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY >+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE >+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR >+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR >+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, >+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, >+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR >+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY >+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE >+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >+ */ >+ >+#include "config.h" >+ >+#if USE(CAPSTONE) >+ >+#include "capstone.h" >+#include "MacroAssemblerCodeRef.h" >+#include "Options.h" >+ >+namespace JSC { >+ >+bool tryToDisassemble(const MacroAssemblerCodePtr<DisassemblyPtrTag>& codePtr, size_t size, const char* prefix, PrintStream& out) >+{ >+ csh handle; >+ cs_insn* instructions; >+ >+#if CPU(X86) >+ if (cs_open(CS_ARCH_X86, CS_MODE_32, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(X86_64) >+ if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM_TRADITIONAL) >+ if (cs_open(CS_ARCH_ARM, CS_MODE_ARM, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM_THUMB2) >+ if (cs_open(CS_ARCH_ARM, CS_MODE_THUMB, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(ARM64) >+ if (cs_open(CS_ARCH_ARM64, CS_MODE_ARM, &handle) != CS_ERR_OK) >+ return false; >+#elif CPU(MIPS) >+ if (cs_open(CS_ARCH_MIPS, CS_MODE_MIPS32, &handle) != CS_ERR_OK) >+ return false; >+#endif >+ >+#if CPU(X86) || CPU(X86_64) >+ if (cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT) != CS_ERR_OK) { >+ cs_close(&handle); >+ return false; >+ } >+#endif >+ >+ size_t count = cs_disasm(handle, codePtr.untaggedExecutableAddress<unsigned char*>(), size, codePtr.untaggedExecutableAddress<uintptr_t>(), 0, &instructions); >+ if (count > 0) { >+ for (size_t i = 0; i < count; ++i) { >+ auto& instruction = instructions[i]; >+ char pcString[20]; >+ snprintf(pcString, sizeof(pcString), "0x%lx", reinterpret_cast<unsigned long>(instruction.address)); >+ out.printf("%s%16s: %s %s\n", prefix, pcString, instruction.mnemonic, instruction.op_str); >+ } >+ cs_free(instructions, count); >+ } >+ cs_close(&handle); >+ return true; >+} >+ >+} // namespace JSC >+ >+#endif // USE(CAPSTONE) >diff --git a/Source/ThirdParty/capstone/CMakeLists.txt b/Source/ThirdParty/capstone/CMakeLists.txt >new file mode 100644 >index 0000000000000000000000000000000000000000..4e09fc1647dc32f453edd44b8af90e4143fb132b >--- /dev/null >+++ b/Source/ThirdParty/capstone/CMakeLists.txt >@@ -0,0 +1,169 @@ >+if (MSVC) >+ set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT") >+ set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd") >+endif () >+ >+add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) >+ >+## sources >+set(SOURCES_ENGINE >+ Source/cs.c >+ Source/MCInst.c >+ Source/MCInstrDesc.c >+ Source/MCRegisterInfo.c >+ Source/SStream.c >+ Source/utils.c >+ ) >+ >+set(HEADERS_ENGINE >+ Source/include/capstone.h >+ Source/utils.h >+ Source/MCRegisterInfo.h >+ Source/MCInst.h >+ Source/MCInstrDesc.h >+ Source/SStream.h >+ Source/cs_priv.h >+ Source/include/platform.h >+ ) >+ >+set(HEADERS_COMMON >+ Source/include/arm64.h >+ Source/include/arm.h >+ Source/include/capstone.h >+ Source/include/mips.h >+ Source/include/ppc.h >+ Source/include/x86.h >+ Source/include/sparc.h >+ Source/include/systemz.h >+ Source/include/xcore.h >+ Source/include/platform.h >+ ) >+ >+ >+## architecture support >+if (WTF_CPU_ARM) >+ add_definitions(-DCAPSTONE_HAS_ARM) >+ set(SOURCES_ARM >+ Source/arch/ARM/ARMDisassembler.c >+ Source/arch/ARM/ARMInstPrinter.c >+ Source/arch/ARM/ARMMapping.c >+ Source/arch/ARM/ARMModule.c >+ ) >+ set(HEADERS_ARM >+ Source/arch/ARM/ARMAddressingModes.h >+ Source/arch/ARM/ARMBaseInfo.h >+ Source/arch/ARM/ARMDisassembler.h >+ Source/arch/ARM/ARMGenAsmWriter.inc >+ Source/arch/ARM/ARMGenDisassemblerTables.inc >+ Source/arch/ARM/ARMGenInstrInfo.inc >+ Source/arch/ARM/ARMGenRegisterInfo.inc >+ Source/arch/ARM/ARMGenSubtargetInfo.inc >+ Source/arch/ARM/ARMInstPrinter.h >+ Source/arch/ARM/ARMMapping.h >+ ) >+endif () >+ >+if (WTF_CPU_ARM64) >+ add_definitions(-DCAPSTONE_HAS_ARM64) >+ set(SOURCES_ARM64 >+ Source/arch/AArch64/AArch64BaseInfo.c >+ Source/arch/AArch64/AArch64Disassembler.c >+ Source/arch/AArch64/AArch64InstPrinter.c >+ Source/arch/AArch64/AArch64Mapping.c >+ Source/arch/AArch64/AArch64Module.c >+ ) >+ set(HEADERS_ARM64 >+ Source/arch/AArch64/AArch64AddressingModes.h >+ Source/arch/AArch64/AArch64BaseInfo.h >+ Source/arch/AArch64/AArch64Disassembler.h >+ Source/arch/AArch64/AArch64GenAsmWriter.inc >+ Source/arch/AArch64/AArch64GenDisassemblerTables.inc >+ Source/arch/AArch64/AArch64GenInstrInfo.inc >+ Source/arch/AArch64/AArch64GenRegisterInfo.inc >+ Source/arch/AArch64/AArch64GenSubtargetInfo.inc >+ Source/arch/AArch64/AArch64InstPrinter.h >+ Source/arch/AArch64/AArch64Mapping.h >+ ) >+endif () >+ >+if (WTF_CPU_MIPS) >+ add_definitions(-DCAPSTONE_HAS_MIPS) >+ set(SOURCES_MIPS >+ Source/arch/Mips/MipsDisassembler.c >+ Source/arch/Mips/MipsInstPrinter.c >+ Source/arch/Mips/MipsMapping.c >+ Source/arch/Mips/MipsModule.c >+ ) >+ set(HEADERS_MIPS >+ Source/arch/Mips/MipsDisassembler.h >+ Source/arch/Mips/MipsGenAsmWriter.inc >+ Source/arch/Mips/MipsGenDisassemblerTables.inc >+ Source/arch/Mips/MipsGenInstrInfo.inc >+ Source/arch/Mips/MipsGenRegisterInfo.inc >+ Source/arch/Mips/MipsGenSubtargetInfo.inc >+ Source/arch/Mips/MipsInstPrinter.h >+ Source/arch/Mips/MipsMapping.h >+ ) >+endif () >+ >+if (WTF_CPU_X86 OR WTF_CPU_X86_64) >+ add_definitions(-DCAPSTONE_HAS_X86) >+ set(SOURCES_X86 >+ Source/arch/X86/X86ATTInstPrinter.c >+ Source/arch/X86/X86Disassembler.c >+ Source/arch/X86/X86DisassemblerDecoder.c >+ Source/arch/X86/X86IntelInstPrinter.c >+ Source/arch/X86/X86Mapping.c >+ Source/arch/X86/X86Module.c >+ ) >+ set(HEADERS_X86 >+ Source/arch/X86/X86BaseInfo.h >+ Source/arch/X86/X86Disassembler.h >+ Source/arch/X86/X86DisassemblerDecoder.h >+ Source/arch/X86/X86DisassemblerDecoderCommon.h >+ Source/arch/X86/X86GenAsmWriter.inc >+ Source/arch/X86/X86GenAsmWriter1.inc >+ Source/arch/X86/X86GenAsmWriter1_reduce.inc >+ Source/arch/X86/X86GenAsmWriter_reduce.inc >+ Source/arch/X86/X86GenDisassemblerTables.inc >+ Source/arch/X86/X86GenDisassemblerTables_reduce.inc >+ Source/arch/X86/X86GenInstrInfo.inc >+ Source/arch/X86/X86GenInstrInfo_reduce.inc >+ Source/arch/X86/X86GenRegisterInfo.inc >+ Source/arch/X86/X86InstPrinter.h >+ Source/arch/X86/X86Mapping.h >+ ) >+endif () >+ >+set(capstone_SOURCES >+ ${SOURCES_ENGINE} >+ ${SOURCES_ARM} >+ ${SOURCES_ARM64} >+ ${SOURCES_MIPS} >+ ${SOURCES_X86} >+ ) >+ >+set(capstone_HEADERS >+ ${HEADERS_COMMON} >+ ${HEADERS_ENGINE} >+ ${HEADERS_ARM} >+ ${HEADERS_ARM64} >+ ${HEADERS_MIPS} >+ ${HEADERS_X86} >+ ) >+ >+set(capstone_INCLUDE_DIRECTORIES "${THIRDPARTY_DIR}/capstone/Source/include") >+ >+## targets >+add_library(capstone STATIC ${capstone_SOURCES} ${capstone_HEADERS}) >+set_property(TARGET capstone PROPERTY OUTPUT_NAME capstone) >+target_include_directories(capstone PRIVATE ${capstone_INCLUDE_DIRECTORIES}) >+ >+if (COMPILER_IS_GCC_OR_CLANG) >+ WEBKIT_ADD_TARGET_C_FLAGS(capstone >+ -Wno-sign-compare >+ -Wno-unused-parameter >+ -Wno-implicit-fallthrough >+ -Wno-missing-format-attribute >+ ) >+endif () >diff --git a/Source/ThirdParty/capstone/Source/.appveyor.yml b/Source/ThirdParty/capstone/Source/.appveyor.yml >new file mode 100644 >index 0000000000000000000000000000000000000000..7626808e851e166c68277f938b2a74a3479a0dfa >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/.appveyor.yml >@@ -0,0 +1,14 @@ >+version: 3.0.4-{build} >+ >+os: >+ - Visual Studio 2015 >+ >+before_build: >+ - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64 >+ >+build_script: >+ - mkdir build >+ - cd build >+ - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" .. >+ - nmake >+ >diff --git a/Source/ThirdParty/capstone/Source/.gitattributes b/Source/ThirdParty/capstone/Source/.gitattributes >new file mode 100644 >index 0000000000000000000000000000000000000000..03e638de6912237fdb150d57d5faa368ee0b30e0 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/.gitattributes >@@ -0,0 +1 @@ >+/arch/**/*.inc linguist-language=C >diff --git a/Source/ThirdParty/capstone/Source/.gitignore b/Source/ThirdParty/capstone/Source/.gitignore >new file mode 100644 >index 0000000000000000000000000000000000000000..24ecacd644e43e6d63254f578a1c049d155a9073 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/.gitignore >@@ -0,0 +1,116 @@ >+# Object files >+*.o >+*.ko >+ >+# Gcc dependency-tracking files >+*.d >+ >+# Libraries >+*.lib >+*.a >+ >+# Shared objects (inc. Windows DLLs) >+*.dll >+*.so >+*.so.* >+*.dylib >+ >+# Executables >+*.exe >+*.out >+*.app >+ >+# python >+bindings/python/build/ >+bindings/python/capstone.egg-info/ >+*.pyc >+ >+# java >+bindings/java/capstone.jar >+ >+# ocaml >+bindings/ocaml/*.cmi >+bindings/ocaml/*.cmx >+bindings/ocaml/*.cmxa >+bindings/ocaml/*.mli >+bindings/ocaml/test >+bindings/ocaml/test_arm >+bindings/ocaml/test_arm64 >+bindings/ocaml/test_mips >+bindings/ocaml/test_x86 >+bindings/ocaml/test_detail >+bindings/ocaml/test_ppc >+bindings/ocaml/test_sparc >+bindings/ocaml/test_systemz >+bindings/ocaml/test_xcore >+ >+ >+# test binaries >+tests/test >+tests/test_detail >+tests/test_iter >+tests/test_arm >+tests/test_arm64 >+tests/test_mips >+tests/test_x86 >+tests/test_ppc >+tests/test_skipdata >+tests/test_sparc >+tests/test_systemz >+tests/test_xcore >+tests/*.static >+tests/test_basic >+tests/test_customized_mnem >+ >+tests/test_m680x >+tests/test_m68k >+tests/test_tms320c64x >+tests/test_evm >+ >+# regress binaries >+suite/regress/invalid_read_in_print_operand >+ >+ >+# vim tmp file >+*.swp >+*~ >+ >+capstone.pc >+ >+# local files >+_* >+ >+# freebsd ports: generated file with "make makesum" command >+packages/freebsd/ports/devel/capstone/distinfo >+ >+# VisualStudio >+ProjectUpgradeLog.log >+Debug/ >+Release/ >+ipch/ >+*.sdf >+*.opensdf >+*.suo >+*.user >+*.backup >+*.VC.db >+*.VC.opendb >+ >+# CMake build directories >+build*/ >+ >+# Xcode >+xcode/Capstone.xcodeproj/xcuserdata >+xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata >+ >+# suite/ >+test_arm_regression >+test_arm_regression.o >+fuzz_harness >+test_iter_benchmark >+ >+ >+*.s >+.DS_Store >+ >+cstool/cstool >diff --git a/Source/ThirdParty/capstone/Source/.travis.yml b/Source/ThirdParty/capstone/Source/.travis.yml >new file mode 100644 >index 0000000000000000000000000000000000000000..4e323fa46ae25bcea932ea389d90e7b0690547fd >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/.travis.yml >@@ -0,0 +1,26 @@ >+language: cpp >+sudo: false >+env: >+ global: >+ - LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tests/:$TRAVIS_BUILD_DIR:$LD_LIBRARY_PATH >+ - DYLD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tests/:$TRAVIS_BUILD_DIR:$DYLD_LIBRARY_PATH >+script: >+ - ./make.sh >+ - make check >+ - cd bindings/python && make check >+compiler: >+ - clang >+ - gcc >+os: >+ - linux >+ - osx >+matrix: >+ include: >+ - if: branch = master >+ os: osx >+ script: brew update && brew install --HEAD capstone && brew test capstone >+ compiler: gcc >+ - if: branch = master >+ os: osx >+ script: brew update && brew install --HEAD capstone && brew test capstone >+ compiler: clang >diff --git a/Source/ThirdParty/capstone/Source/CMakeLists.txt b/Source/ThirdParty/capstone/Source/CMakeLists.txt >new file mode 100644 >index 0000000000000000000000000000000000000000..be5060f061dd9e28d7c8f3150d8d523228b29d80 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/CMakeLists.txt >@@ -0,0 +1,423 @@ >+cmake_minimum_required(VERSION 2.6) >+project(capstone) >+ >+set(VERSION_MAJOR 3) >+set(VERSION_MINOR 0) >+set(VERSION_PATCH 5) >+ >+# to configure the options specify them in in the command line or change them in the cmake UI. >+# Don't edit the makefile! >+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" OFF) >+option(CAPSTONE_BUILD_STATIC "Build static library" ON) >+option(CAPSTONE_BUILD_SHARED "Build shared library" ON) >+option(CAPSTONE_BUILD_DIET "Build diet library" OFF) >+option(CAPSTONE_BUILD_TESTS "Build tests" ON) >+option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) >+option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) >+ >+option(CAPSTONE_ARM_SUPPORT "ARM support" ON) >+option(CAPSTONE_ARM64_SUPPORT "ARM64 support" ON) >+option(CAPSTONE_MIPS_SUPPORT "MIPS support" ON) >+option(CAPSTONE_PPC_SUPPORT "PowerPC support" ON) >+option(CAPSTONE_SPARC_SUPPORT "Sparc support" ON) >+option(CAPSTONE_SYSZ_SUPPORT "SystemZ support" ON) >+option(CAPSTONE_XCORE_SUPPORT "XCore support" ON) >+option(CAPSTONE_X86_SUPPORT "x86 support" ON) >+option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF) >+option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF) >+option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF) >+ >+if (MSVC) >+ set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT") >+ set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd") >+endif () >+ >+if (CAPSTONE_BUILD_DIET) >+ add_definitions(-DCAPSTONE_DIET) >+endif () >+ >+if (CAPSTONE_USE_DEFAULT_ALLOC) >+ add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM) >+endif () >+ >+if (CAPSTONE_X86_REDUCE) >+ add_definitions(-DCAPSTONE_X86_REDUCE) >+endif () >+ >+if (CAPSTONE_X86_ATT_DISABLE) >+ add_definitions(-DCAPSTONE_X86_ATT_DISABLE) >+endif () >+ >+## sources >+set(SOURCES_ENGINE >+ cs.c >+ MCInst.c >+ MCInstrDesc.c >+ MCRegisterInfo.c >+ SStream.c >+ utils.c >+ ) >+ >+set(HEADERS_ENGINE >+ include/capstone.h >+ utils.h >+ MCRegisterInfo.h >+ MCInst.h >+ MCInstrDesc.h >+ SStream.h >+ cs_priv.h >+ include/platform.h >+ ) >+ >+set(HEADERS_COMMON >+ include/arm64.h >+ include/arm.h >+ include/capstone.h >+ include/mips.h >+ include/ppc.h >+ include/x86.h >+ include/sparc.h >+ include/systemz.h >+ include/xcore.h >+ include/platform.h >+ ) >+ >+ >+set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) >+ >+## architecture support >+if (CAPSTONE_ARM_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_ARM) >+ set(SOURCES_ARM >+ arch/ARM/ARMDisassembler.c >+ arch/ARM/ARMInstPrinter.c >+ arch/ARM/ARMMapping.c >+ arch/ARM/ARMModule.c >+ ) >+ set(HEADERS_ARM >+ arch/ARM/ARMAddressingModes.h >+ arch/ARM/ARMBaseInfo.h >+ arch/ARM/ARMDisassembler.h >+ arch/ARM/ARMGenAsmWriter.inc >+ arch/ARM/ARMGenDisassemblerTables.inc >+ arch/ARM/ARMGenInstrInfo.inc >+ arch/ARM/ARMGenRegisterInfo.inc >+ arch/ARM/ARMGenSubtargetInfo.inc >+ arch/ARM/ARMInstPrinter.h >+ arch/ARM/ARMMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_arm.c) >+endif () >+ >+if (CAPSTONE_ARM64_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_ARM64) >+ set(SOURCES_ARM64 >+ arch/AArch64/AArch64BaseInfo.c >+ arch/AArch64/AArch64Disassembler.c >+ arch/AArch64/AArch64InstPrinter.c >+ arch/AArch64/AArch64Mapping.c >+ arch/AArch64/AArch64Module.c >+ ) >+ set(HEADERS_ARM64 >+ arch/AArch64/AArch64AddressingModes.h >+ arch/AArch64/AArch64BaseInfo.h >+ arch/AArch64/AArch64Disassembler.h >+ arch/AArch64/AArch64GenAsmWriter.inc >+ arch/AArch64/AArch64GenDisassemblerTables.inc >+ arch/AArch64/AArch64GenInstrInfo.inc >+ arch/AArch64/AArch64GenRegisterInfo.inc >+ arch/AArch64/AArch64GenSubtargetInfo.inc >+ arch/AArch64/AArch64InstPrinter.h >+ arch/AArch64/AArch64Mapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c) >+endif () >+ >+if (CAPSTONE_MIPS_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_MIPS) >+ set(SOURCES_MIPS >+ arch/Mips/MipsDisassembler.c >+ arch/Mips/MipsInstPrinter.c >+ arch/Mips/MipsMapping.c >+ arch/Mips/MipsModule.c >+ ) >+ set(HEADERS_MIPS >+ arch/Mips/MipsDisassembler.h >+ arch/Mips/MipsGenAsmWriter.inc >+ arch/Mips/MipsGenDisassemblerTables.inc >+ arch/Mips/MipsGenInstrInfo.inc >+ arch/Mips/MipsGenRegisterInfo.inc >+ arch/Mips/MipsGenSubtargetInfo.inc >+ arch/Mips/MipsInstPrinter.h >+ arch/Mips/MipsMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_mips.c) >+endif () >+ >+if (CAPSTONE_PPC_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_POWERPC) >+ set(SOURCES_PPC >+ arch/PowerPC/PPCDisassembler.c >+ arch/PowerPC/PPCInstPrinter.c >+ arch/PowerPC/PPCMapping.c >+ arch/PowerPC/PPCModule.c >+ ) >+ set(HEADERS_PPC >+ arch/PowerPC/PPCDisassembler.h >+ arch/PowerPC/PPCGenAsmWriter.inc >+ arch/PowerPC/PPCGenDisassemblerTables.inc >+ arch/PowerPC/PPCGenInstrInfo.inc >+ arch/PowerPC/PPCGenRegisterInfo.inc >+ arch/PowerPC/PPCGenSubtargetInfo.inc >+ arch/PowerPC/PPCInstPrinter.h >+ arch/PowerPC/PPCMapping.h >+ arch/PowerPC/PPCPredicates.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c) >+endif () >+ >+if (CAPSTONE_X86_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_X86) >+ set(SOURCES_X86 >+ arch/X86/X86Disassembler.c >+ arch/X86/X86DisassemblerDecoder.c >+ arch/X86/X86IntelInstPrinter.c >+ arch/X86/X86Mapping.c >+ arch/X86/X86Module.c >+ ) >+ set(HEADERS_X86 >+ arch/X86/X86BaseInfo.h >+ arch/X86/X86Disassembler.h >+ arch/X86/X86DisassemblerDecoder.h >+ arch/X86/X86DisassemblerDecoderCommon.h >+ arch/X86/X86GenAsmWriter.inc >+ arch/X86/X86GenAsmWriter1.inc >+ arch/X86/X86GenAsmWriter1_reduce.inc >+ arch/X86/X86GenAsmWriter_reduce.inc >+ arch/X86/X86GenDisassemblerTables.inc >+ arch/X86/X86GenDisassemblerTables_reduce.inc >+ arch/X86/X86GenInstrInfo.inc >+ arch/X86/X86GenInstrInfo_reduce.inc >+ arch/X86/X86GenRegisterInfo.inc >+ arch/X86/X86InstPrinter.h >+ arch/X86/X86Mapping.h >+ ) >+ if (NOT CAPSTONE_BUILD_DIET) >+ set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c) >+ endif () >+ set(TEST_SOURCES ${TEST_SOURCES} test_x86.c) >+endif () >+ >+if (CAPSTONE_SPARC_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_SPARC) >+ set(SOURCES_SPARC >+ arch/Sparc/SparcDisassembler.c >+ arch/Sparc/SparcInstPrinter.c >+ arch/Sparc/SparcMapping.c >+ arch/Sparc/SparcModule.c >+ ) >+ set(HEADERS_SPARC >+ arch/Sparc/Sparc.h >+ arch/Sparc/SparcDisassembler.h >+ arch/Sparc/SparcGenAsmWriter.inc >+ arch/Sparc/SparcGenDisassemblerTables.inc >+ arch/Sparc/SparcGenInstrInfo.inc >+ arch/Sparc/SparcGenRegisterInfo.inc >+ arch/Sparc/SparcGenSubtargetInfo.inc >+ arch/Sparc/SparcInstPrinter.h >+ arch/Sparc/SparcMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c) >+endif () >+ >+if (CAPSTONE_SYSZ_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_SYSZ) >+ set(SOURCES_SYSZ >+ arch/SystemZ/SystemZDisassembler.c >+ arch/SystemZ/SystemZInstPrinter.c >+ arch/SystemZ/SystemZMapping.c >+ arch/SystemZ/SystemZModule.c >+ arch/SystemZ/SystemZMCTargetDesc.c >+ ) >+ set(HEADERS_SYSZ >+ arch/SystemZ/SystemZDisassembler.h >+ arch/SystemZ/SystemZGenAsmWriter.inc >+ arch/SystemZ/SystemZGenDisassemblerTables.inc >+ arch/SystemZ/SystemZGenInstrInfo.inc >+ arch/SystemZ/SystemZGenRegisterInfo.inc >+ arch/SystemZ/SystemZGenSubtargetInfo.inc >+ arch/SystemZ/SystemZInstPrinter.h >+ arch/SystemZ/SystemZMCTargetDesc.h >+ arch/SystemZ/SystemZMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c) >+endif () >+ >+if (CAPSTONE_XCORE_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_XCORE) >+ set(SOURCES_XCORE >+ arch/XCore/XCoreDisassembler.c >+ arch/XCore/XCoreInstPrinter.c >+ arch/XCore/XCoreMapping.c >+ arch/XCore/XCoreModule.c >+ ) >+ set(HEADERS_XCORE >+ arch/XCore/XCoreDisassembler.h >+ arch/XCore/XCoreGenAsmWriter.inc >+ arch/XCore/XCoreGenDisassemblerTables.inc >+ arch/XCore/XCoreGenInstrInfo.inc >+ arch/XCore/XCoreGenRegisterInfo.inc >+ arch/XCore/XCoreInstPrinter.h >+ arch/XCore/XCoreMapping.h >+ ) >+ set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c) >+endif () >+ >+if (CAPSTONE_OSXKERNEL_SUPPORT) >+ add_definitions(-DCAPSTONE_HAS_OSXKERNEL) >+endif () >+ >+set(ALL_SOURCES >+ ${SOURCES_ENGINE} >+ ${SOURCES_ARM} >+ ${SOURCES_ARM64} >+ ${SOURCES_MIPS} >+ ${SOURCES_PPC} >+ ${SOURCES_X86} >+ ${SOURCES_SPARC} >+ ${SOURCES_SYSZ} >+ ${SOURCES_XCORE} >+ ) >+ >+set(ALL_HEADERS >+ ${HEADERS_COMMON} >+ ${HEADERS_ENGINE} >+ ${HEADERS_ARM} >+ ${HEADERS_ARM64} >+ ${HEADERS_MIPS} >+ ${HEADERS_PPC} >+ ${HEADERS_X86} >+ ${HEADERS_SPARC} >+ ${HEADERS_SYSZ} >+ ${HEADERS_XCORE} >+ ) >+ >+include_directories("${PROJECT_SOURCE_DIR}/include") >+ >+## properties >+# version info >+set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) >+ >+## targets >+if (CAPSTONE_BUILD_STATIC) >+ add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS}) >+ set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone) >+ set(default-target capstone-static) >+endif () >+ >+# Force static runtime libraries >+if (CAPSTONE_BUILD_STATIC_RUNTIME) >+ FOREACH(flag >+ CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO >+ CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT >+ CMAKE_CXX_FLAGS_RELEASE CMAKE_CXX_FLAGS_RELWITHDEBINFO >+ CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_DEBUG_INIT) >+ if (MSVC) >+ STRING(REPLACE "/MD" "/MT" "${flag}" "${${flag}}") >+ SET("${flag}" "${${flag}} /EHsc") >+ endif (MSVC) >+ ENDFOREACH() >+endif () >+ >+if (CAPSTONE_BUILD_SHARED) >+ add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS}) >+ set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone) >+ set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED) >+ >+ if (MSVC) >+ set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib) >+ else() >+ set_target_properties(capstone-shared PROPERTIES >+ VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} >+ SOVERSION ${VERSION_MAJOR}) >+ endif () >+ >+ if(NOT DEFINED default-target) # honor `capstone-static` for tests first. >+ set(default-target capstone-shared) >+ add_definitions(-DCAPSTONE_SHARED) >+ endif () >+endif () >+ >+if (CAPSTONE_BUILD_TESTS) >+ foreach (TSRC ${TEST_SOURCES}) >+ STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) >+ add_executable(${TBIN} "tests/${TSRC}") >+ target_link_libraries(${TBIN} ${default-target}) >+ endforeach () >+ if (CAPSTONE_ARM_SUPPORT) >+ set(ARM_REGRESS_TEST test_arm_regression.c) >+ STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) >+ add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") >+ target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) >+ endif() >+endif () >+ >+source_group("Source\\Engine" FILES ${SOURCES_ENGINE}) >+source_group("Source\\ARM" FILES ${SOURCES_ARM}) >+source_group("Source\\ARM64" FILES ${SOURCES_ARM64}) >+source_group("Source\\Mips" FILES ${SOURCES_MIPS}) >+source_group("Source\\PowerPC" FILES ${SOURCES_PPC}) >+source_group("Source\\Sparc" FILES ${SOURCES_SPARC}) >+source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ}) >+source_group("Source\\X86" FILES ${SOURCES_X86}) >+source_group("Source\\XCore" FILES ${SOURCES_XCORE}) >+ >+source_group("Include\\Common" FILES ${HEADERS_COMMON}) >+source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) >+source_group("Include\\ARM" FILES ${HEADERS_ARM}) >+source_group("Include\\ARM64" FILES ${HEADERS_ARM64}) >+source_group("Include\\Mips" FILES ${HEADERS_MIPS}) >+source_group("Include\\PowerPC" FILES ${HEADERS_PPC}) >+source_group("Include\\Sparc" FILES ${HEADERS_SPARC}) >+source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ}) >+source_group("Include\\X86" FILES ${HEADERS_X86}) >+source_group("Include\\XCore" FILES ${HEADERS_XCORE}) >+ >+### test library 64bit routine: >+get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS) >+ >+if (NOT APPLE AND "${LIB64}" STREQUAL "TRUE") >+ set(LIBSUFFIX 64) >+else() >+ set(LIBSUFFIX "") >+endif() >+ >+set(INSTALL_LIB_DIR lib${LIBSUFFIX} CACHE PATH "Installation directory for libraries") >+mark_as_advanced(INSTALL_LIB_DIR) >+ >+## installation >+install(FILES ${HEADERS_COMMON} DESTINATION include/capstone) >+configure_file(capstone.pc.in capstone.pc @ONLY) >+ >+if (CAPSTONE_BUILD_STATIC) >+ install(TARGETS capstone-static >+ RUNTIME DESTINATION bin >+ LIBRARY DESTINATION ${INSTALL_LIB_DIR} >+ ARCHIVE DESTINATION ${INSTALL_LIB_DIR}) >+endif () >+ >+if (CAPSTONE_BUILD_SHARED) >+ install(TARGETS capstone-shared >+ RUNTIME DESTINATION bin >+ LIBRARY DESTINATION ${INSTALL_LIB_DIR} >+ ARCHIVE DESTINATION ${INSTALL_LIB_DIR}) >+endif () >+ >+if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL) >+FILE(GLOB CSTOOL_SRC cstool/*.c) >+add_executable(cstool ${CSTOOL_SRC}) >+target_link_libraries(cstool ${default-target}) >+ >+install(TARGETS cstool DESTINATION bin) >+install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION lib/pkgconfig) >+endif () >diff --git a/Source/ThirdParty/capstone/Source/COMPILE.TXT b/Source/ThirdParty/capstone/Source/COMPILE.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..6c7f948a964dacf8f44680929008bde0c17b6994 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/COMPILE.TXT >@@ -0,0 +1,193 @@ >+This documentation explains how to compile, install & run Capstone on MacOSX, >+Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows. >+ >+To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT. >+ >+To compile using CMake, see COMPILE_CMAKE.TXT. >+ >+To compile using XCode on MacOSX, see xcode/README.md. >+ >+ *-*-*-*-*-* >+ >+Capstone requires no prerequisite packages, so it is easy to compile & install. >+ >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc, >+ SystemZ, XCore & X86), if you just need several selected archs, choose which >+ ones you want to compile in by editing "config.mk" before going to next steps. >+ >+ By default, all 8 architectures are compiled. >+ >+ The other way of customize Capstone without having to edit config.mk is to >+ pass the desired options on the commandline to ./make.sh. Currently, >+ Capstone supports 5 options, as followings. >+ >+ - CAPSTONE_ARCHS: specify list of architectures to compiled in. >+ - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management. >+ - CAPSTONE_DIET: use this to make the output binaries more compact. >+ - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86. >+ - CAPSTONE_STATIC: build static library. >+ - CAPSTONE_SHARED: build dynamic (shared) library. >+ >+ By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE >+ modes are disable, and builds all the static & shared libraries. >+ >+ To avoid editing config.mk for these customization, we can pass their values to >+ make.sh, as followings. >+ >+ $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh >+ >+ NOTE: on commandline, put these values in front of ./make.sh, not after it. >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) Compile from source >+ >+ On *nix (such as MacOSX, Linux, *BSD, Solaris): >+ >+ - To compile for current platform, run: >+ >+ $ ./make.sh >+ >+ - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary: >+ >+ $ ./make.sh nix32 >+ >+ >+ >+(2) Install Capstone on *nix >+ >+ To install Capstone, run: >+ >+ $ sudo ./make.sh install >+ >+ For FreeBSD/OpenBSD, where sudo is unavailable, run: >+ >+ $ su; ./make.sh install >+ >+ Users are then required to enter root password to copy Capstone into machine >+ system directories. >+ >+ Afterwards, run ./tests/test* to see the tests disassembling sample code. >+ >+ >+ NOTE: The core framework installed by "./make.sh install" consist of >+ following files: >+ >+ /usr/include/capstone/capstone.h >+ /usr/include/capstone/x86.h >+ /usr/include/capstone/arm.h >+ /usr/include/capstone/arm64.h >+ /usr/include/capstone/mips.h >+ /usr/include/capstone/ppc.h >+ /usr/include/capstone/sparc.h >+ /usr/include/capstone/systemz.h >+ /usr/include/capstone/xcore.h >+ /usr/include/capstone/platform.h >+ /usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX) >+ /usr/lib/libcapstone.a >+ >+ >+ >+(3) Cross-compile for Windows from *nix >+ >+ To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64 >+ for 64-bit binaries) are required. >+ >+ - To cross-compile Windows 32-bit binary, simply run: >+ >+ $ ./make.sh cross-win32 >+ >+ - To cross-compile Windows 64-bit binary, run: >+ >+ $ ./make.sh cross-win64 >+ >+ Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then >+ be used on Windows machine. >+ >+ >+ >+(4) Cross-compile for iOS from Mac OSX. >+ >+ To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required. >+ >+ - To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run: >+ $ ./make.sh ios_armv7 >+ >+ - To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run: >+ $ ./make.sh ios_armv7s >+ >+ - To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run: >+ $ ./make.sh ios_arm64 >+ >+ - To cross-compile for all iDevices (armv7 + armv7s + arm64), run: >+ $ ./make.sh ios >+ >+ Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then >+ be used on iOS devices. >+ >+ >+ >+(5) Cross-compile for Android >+ >+ To cross-compile for Android (smartphone/tablet), Android NDK is required. >+ NOTE: Only ARM and ARM64 are currently supported. >+ >+ $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm >+ or >+ $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64 >+ >+ Resulted files libcapstone.so, libcapstone.a & tests/test* can then >+ be used on Android devices. >+ >+ >+ >+(6) Compile on Windows with Cygwin >+ >+ To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run: >+ >+ - To compile Windows 32-bit binary under Cygwin, run: >+ >+ $ ./make.sh cygwin-mingw32 >+ >+ - To compile Windows 64-bit binary under Cygwin, run: >+ >+ $ ./make.sh cygwin-mingw64 >+ >+ Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then >+ be used on Windows machine. >+ >+ >+ >+(7) By default, "cc" (default C compiler on the system) is used as compiler. >+ >+ - To use "clang" compiler instead, run the command below: >+ >+ $ ./make.sh clang >+ >+ - To use "gcc" compiler instead, run: >+ >+ $ ./make.sh gcc >+ >+ >+ >+(8) To uninstall Capstone, run the command below: >+ >+ $ sudo ./make.sh uninstall >+ >+ >+ >+(9) Language bindings >+ >+ So far, Python, Ocaml & Java are supported by bindings in the main code. >+ Look for the bindings under directory bindings/, and refer to README file >+ of corresponding languages. >+ >+ Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to >+ these can be found at address http://capstone-engine.org/download.html >diff --git a/Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT b/Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..57d5f5e1b4d3231ae85fb1e6fb5c85a53f8ed72a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/COMPILE_CMAKE.TXT >@@ -0,0 +1,80 @@ >+This documentation explains how to compile Capstone with CMake, focus on >+using Microsoft Visual C as the compiler. >+ >+To compile Capstone on *nix, see COMPILE.TXT. >+ >+To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT. >+ >+ *-*-*-*-*-* >+ >+This documentation requires CMake & Windows SDK or MS Visual Studio installed on >+your machine. >+ >+Get CMake for free from http://www.cmake.org. >+ >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc, >+ SystemZ, X86 & XCore), if you just need several selected archs, run "cmake" >+ with the unwanted archs disabled (set to 0) as followings. >+ >+ - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. >+ - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64. >+ - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. >+ - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC. >+ - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc. >+ - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ. >+ - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore. >+ - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86. >+ >+ By default, all 8 architectures are compiled in. >+ >+ >+ Besides, Capstone also allows some more customization via following macros. >+ >+ - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management. >+ - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact. >+ - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. >+ >+ By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE >+ modes are disabled. To use your own memory allocations, turn ON both DIET & >+ X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1 >+ >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) CMake allows you to generate different generators to build Capstone. Below is >+ some examples on how to build Capstone on Windows with CMake. >+ >+ >+ (*) To build Capstone using Nmake of Windows SDK, do: >+ >+ mkdir build >+ cd build >+ ..\nmake.bat >+ >+ After this, find the samples test*.exe, capstone.lib & capstone.dll >+ in the same directory. >+ >+ >+ >+ (*) To build Capstone using Visual Studio, choose the generator accordingly to the >+ version of Visual Studio on your machine. For example, with Visual Studio 2013, do: >+ >+ mkdir build >+ cd build >+ cmake -G "Visual Studio 12" .. >+ >+ After this, find capstone.sln in the same directory. Open it with Visual Studio >+ and build the solution including libraries & all test as usual. >+ >+ >+ >+(2) You can make sure the prior steps successfully worked by launching one of the >+ testing binary (test*.exe). >+ >diff --git a/Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT b/Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..f54b95b900e928080370748fd80112fe960027eb >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/COMPILE_MSVC.TXT >@@ -0,0 +1,107 @@ >+This documentation explains how to compile Capstone on Windows using >+Microsoft Visual Studio version 2010 or newer. >+ >+To compile Capstone on *nix, see COMPILE.TXT >+ >+To compile Capstone with CMake, see COMPILE_CMAKE.TXT >+ >+ *-*-*-*-*-* >+ >+Capstone requires no prerequisite packages with default configurations, so it is >+easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln" >+and follow the instructions below. >+ >+NOTE: This requires Visual Studio 2010 or newer versions. >+ >+If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer >+versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required. >+ >+ >+(0) Tailor Capstone to your need. >+ >+ Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc, >+ SystemZ, X86 & XCore), if you just need several selected archs, choose the ones >+ you want to compile in by opening Visual Studio solution "msvc\capstone.sln", >+ then directly editing the projects "capstone_static" & "capstone_dll" for static >+ and dynamic libraries, respectively. This must be done before going to the next >+ steps. >+ >+ In VisualStudio interface, modify the preprocessor definitions via >+ "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor" >+ to customize Capstone library, as followings. >+ >+ - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. >+ - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support. >+ - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. >+ - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support. >+ - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support. >+ - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support. >+ - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support. >+ - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support. >+ >+ By default, all 8 architectures are compiled in. >+ >+ >+ Besides, Capstone also allows some more customization via following macros. >+ >+ - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management. >+ - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact. >+ - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller. >+ - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable >+ AT&T syntax on x86. >+ >+ By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE >+ modes are disable. >+ >+ >+ For each option, refer to docs/README for more details. >+ >+ >+ >+(1) Compile from source on Windows with Visual Studio >+ >+ - Choose the configuration and the platform you want: Release/Debug & Win32/Win64. >+ - Build only the libraries, or the libraries along with all the tests. >+ - "capstone_static_winkernel" is for compiling Capstone for a driver and >+ "test_winkernel" is a test for a driver, and those are excluded from build by >+ default. To compile them, open the Configuration Manager through the [Build] >+ menu and check "Build" check boxes for those project. >+ >+ >+ >+(2) You can make sure the prior steps successfully worked by launching one of the >+ testing binary (test*.exe). >+ >+ The testing binary for a driver "test_winkernel.sys" is made up of all tests for >+ supported architectures configured with the step (0) along side its own tests. >+ Below explains a procedure to run the test driver and check test results. >+ >+ On the x64 platform, the test signing mode has to be enabled to install the test >+ driver. To do it, open the command prompt with the administrator privileges and >+ type the following command, and then restart the system to activate the change: >+ >+ >bcdedit /set testsigning on >+ >+ Test results from the test driver is sent to kernel debug buffer. In order to >+ see those results, download DebugView and run it with the administrator >+ privileges, then check [Capture Kernel] through the [Capture] menu. >+ >+ DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx >+ >+ To install and uninstall the driver, use the 'sc' command. For installing and >+ executing test_winkernel.sys, execute the following commands with the >+ administrator privileges: >+ >+ >sc create test_winkernel type= kernel binPath= <full path to test_winkernel.sys> >+ [SC] CreateService SUCCESS >+ >+ >sc start test_winkernel >+ [SC] StartService FAILED 995: >+ >+ The I/O operation has been aborted because of either a thread exit or an application request. >+ >+ To uninstall the driver, execute the following commands with the administrator >+ privileges: >+ >+ >sc delete test_winkernel >+ >bcdedit /deletevalue testsigning >diff --git a/Source/ThirdParty/capstone/Source/CREDITS.TXT b/Source/ThirdParty/capstone/Source/CREDITS.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..2038ef62c6b8766ab3f341cf4d7023a7fc9e2b8a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/CREDITS.TXT >@@ -0,0 +1,65 @@ >+This file credits all the contributors of the Capstone engine project. >+ >+Key developers >+============== >+1. Nguyen Anh Quynh <aquynh -at- gmail.com> >+ - Core engine >+ - Bindings: Python, Ruby, OCaml, Java, C# >+ >+2. Tan Sheng Di <shengdi -at- coseinc.com> >+ - Bindings: Ruby >+ >+3. Ben Nagy <ben -at- coseinc.com> >+ - Bindings: Ruby, Go >+ >+4. Dang Hoang Vu <dang.hvu -at- gmail.com> >+ - Bindings: Java >+ >+ >+Beta testers (in random order) >+============================== >+Pancake >+Van Hauser >+FX of Phenoelit >+The Grugq, The Grugq <-- our hero for submitting the first ever patch! >+Isaac Dawson, Veracode Inc >+Patroklos Argyroudis, Census Inc. (http://census-labs.com) >+Attila Suszter >+Le Dinh Long >+Nicolas Ruff >+Gunther >+Alex Ionescu, Winsider Seminars & Solutions Inc. >+Snare >+Daniel Godas-Lopez >+Joshua J. Drake >+Edgar Barbosa >+Ralf-Philipp Weinmann >+Hugo Fortier >+Joxean Koret >+Bruce Dang >+Andrew Dunham >+ >+ >+Contributors (in no particular order) >+===================================== >+(Please let us know if you want to have your name here) >+ >+Ole André Vadla RavnÃ¥s (author of the 100th Pull-Request in our Github repo, thanks!) >+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC. >+Daniel Pistelli: Cmake support. >+Peter Hlavaty: integrate Capstone for Windows kernel drivers. >+Guillaume Jeanne: Ocaml binding. >+Martin Tofall, Obsidium Software: Optimize X86 performance & size. >+David MartÃnez Moreno & Hilko Bengen: Debian package. >+Félix Cloutier: Xcode project. >+Benoit Lecocq: OpenBSD package. >+Christophe Avoinne (Hlide): Improve memory management for better performance. >+Michael Cohen & Nguyen Tan Cong: Python module installer. >+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package. >+Felix Gröbert (Google): fuzz testing harness. >+Xipiter LLC: Capstone logo redesigned. >+Satoshi Tanda: Support Windows kernel driver. >+Tang Yuhang: cstool. >+Andrew Dutcher: better Python setup. >+Ruben Boonen: PowerShell binding. >+David Zimmer: VB6 binding. >diff --git a/Source/ThirdParty/capstone/Source/ChangeLog-capstone b/Source/ThirdParty/capstone/Source/ChangeLog-capstone >new file mode 100644 >index 0000000000000000000000000000000000000000..8bd7086f993a7e94df00af541a7fb9444d7ef052 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/ChangeLog-capstone >@@ -0,0 +1,554 @@ >+This file details the changelog of Capstone. >+ >+--------------------------------- >+Version 3.0.5-rc3: July 31st, 2017 >+ >+ >+[ Core ] >+ >+- Fix compilation for MacOS kernel extension >+- cstool to support armbe and arm64be modes >+- Add nmake.bat for Windows build >+- Fix an integer overflow for Windows kernel driver >+- Support to embedded Capstone into MacOS kernel >+- cstool: fix mips64 mode >+- Fix a compiling error in MS Visual Studio 2015 >+- Install pkgconfig file with CMake build >+- Fix SOVERSION property of CMake build >+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc >+- Fix MingW build >+- Better handle CMake installation for Linux 64bit >+ >+ >+[ X86 ] >+ >+- Support BND prefix of Intel MPX extension >+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66 >+- LOCK NOP is a valid instruction >+- Fix ATT syntax for instruction with zero offset segment register >+- LES/LDS are invalid in 64bit mode >+- Fix number of operands for some MOV instructions >+ >+ >+[ ARM ] >+ >+- Fix POP reg to update SP register >+- Update flags for UADD8 instruction >+ >+ >+[ ARM64 ] >+ >+- Better performance with new lookup table >+- Handle system registers added in ARMv8.1/2 >+ >+ >+[ Java binding ] >+ >+- Better handle input with invalid code >+ >+ >+[ Visual Basic binding ] >+ >+- New binding >+ >+--------------------------------- >+Version 3.0.5-rc2: March 2nd, 2017 >+ >+ >+[ Core ] >+ >+- Fix build for Visual Studio 2012 >+- Fix X86_REL_ADDR macro >+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA >+- Better support for embedding Capstone into Windows kernel drivers >+- Support to embedded Capstone into MacOS kernel >+- Support MacOS 10.11 and up >+- Better support for Cygwin >+- Support build packages for FreeBSD & DragonflyBSD >+- Add a command-line tool "cstool" >+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc >+ >+ >+[ X86 ] >+ >+- Some random 16-bit code can be handled wrongly. >+- Remove abundant operand type X86_OP_FP >+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL >+- Add X86_REG_EFLAGS for STC and STD >+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT >+- Rename registers ST0-ST7 to be consistent with asm output >+ >+ >+[ ARM ] >+ >+- Properly handle IT instruction >+- Fix LDRSB >+- Fix writeback for LDR >+- Fix Thumb BigEndian setup >+ >+ >+[ ARM64 ] >+ >+- Fix arith extender >+- Fix writeback for LDR >+- Rename enum arm64_mrs_reg to arm64_sysreg >+ >+ >+[ PowerPC ] >+ >+- Print 0 offset for memory operand >+ >+ >+[ Sparc ] >+ >+- Fix POPC instruction >+ >+ >+[ Python binding ] >+ >+- Better PyPy support >+- Add __version__ >+- Better support for Python 3 >+- Fix CS_SKIPDATA_CALLBACK prototype >+- Cast skipdata function inside binding to simplify the API >+ >+ >+[ Java binding ] >+ >+- Better handle input with invalid code >+ >+ >+[ PowerShell ] >+ >+- New binding >+ >+--------------------------------- >+Version 3.0.4: July 15th, 2015 >+ >+ >+[ Library ] >+ >+- Improve cross-compile for Android using Android NDK. >+- Support cross-compile for AArch64 Android (with Linux GCC). >+- Removed osxkernel_inttypes.h that is incompatible with BSD license. >+- Make it possible to compile with CC having a space inside (like "ccache gcc"). >+ >+ >+[ X86 ] >+ >+- Fix a null pointer dereference bug on handling code with special prefixes. >+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax. >+- Print immediate operand in positive form in some algorithm instructions. >+- Properly decode some SSE instructions. >+ >+ >+[ PowerPC ] >+ >+- Fixed a memory corruption bug. >+- Fixed a memory corruption bug for the engine built in DIET mode. >+ >+ >+[ Mips ] >+ >+- Fixed instruction ID of SUBU instruction. >+- Fixed a memory corruption bug. >+ >+ >+[ Arm ] >+ >+- Fixed a memory corruption bug on IT instruction. >+ >+ >+[ XCore ] >+ >+- Fixed a memory corruption bug when instruction has a memory operand. >+ >+ >+[ Python ] >+ >+- Support Virtualenv. >+- setup.py supports option --user if not in a virtualenv to allow for local usage. >+- Properly handle the destruction of Cs object in the case the shared library >+ was already unloaded. >+ >+--------------------------------- >+Version 3.0.3: May 08th, 2015 >+ >+ >+[ Library ] >+ >+- Support to embed into Mac OS X kernel extensions. >+- Now it is possible to compile Capstone with older C compilers, such as >+ GCC 4.8 on Ubuntu 12.04. >+- Add "test_iter" to MSVC project. >+ >+ >+[ X86 ] >+ >+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support >+ $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of >+ "rcll %edx"). >+- CMPXCHG16B is a valid instruction with LOCK prefix. >+- Fixed a segfault on the input of 0xF3. >+ >+ >+[ Arm ] >+ >+- BLX instruction modifies PC & LR registers. >+ >+ >+[ Sparc ] >+ >+- Improved displacement decoding for sparc banching instructions. >+ >+ >+[ Python binding ] >+ >+- Fix for Cython so it can properly initialize. >+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type. >+- Properly support compile with Cygwin & install binding (setup.py). >+ >+--------------------------------- >+Version 3.0.2: March 11th, 2015 >+ >+ >+[ Library ] >+ >+- On *nix, only export symbols that are part of the API (instead of all >+ the internal symbols). >+ >+ >+[ X86 ] >+ >+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding. >+- Fix implicit registers read/written & instruction groups of some instructions. >+- More flexible on the order of prefixes, so better handle some tricky >+ instructions. >+- REPNE prefix can go with STOS & MOVS instructions. >+- Fix a compilation bug for X86_REDUCE mode. >+- Fix operand size of instructions with operand PTR [] >+ >+ >+[ Arm ] >+ >+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode). >+- Fix a bug on handling the If-Then block. >+ >+ >+[ Mips ] >+ >+- Sanity check for the input size for MIPS64 mode. >+ >+ >+[ MSVC ] >+ >+- Compile capstone.dll with static runtime MSVCR built in. >+ >+ >+[ Python binding ] >+ >+- Fix a compiling issue of Cython binding with gcc 4.9. >+ >+--------------------------------- >+Version 3.0.1: February 03rd, 2015 >+ >+[ X86 ] >+ >+- Properly handle LOCK, REP, REPE & REPNE prefixes. >+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions. >+- Print LJUMP/LCALL without * as prefix for Intel syntax. >+- Handle REX prefix properly for segment/MMX related instructions (x86_64). >+- Instruction with length > 15 is consider invalid. >+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, >+ FSTP, FSTPNCE, NOP. >+- Handle some tricky code for some X86_64 instructions with REX prefix. >+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg >+- MOV32ms & MOV32sm should reference word rather than dword. >+ >+ >+[ Arm64 ] >+ >+- BL & BLR instructions do not read SP register. >+- Print absolute (rather than relative) address for instructions B, BL, >+ CBNZ, ADR. >+ >+ >+[ Arm ] >+ >+- Instructions ADC & SBC do not update flags. >+- BL & BLX do not read SP, but PC register. >+- Alias LDR instruction with operands [sp], 4 to POP. >+- Print immediate operand of MVN instruction in positive hexadecimal form. >+ >+ >+[ PowerPC ] >+ >+- Fix some compilation bugs when DIET mode is enable. >+- Populate SLWI/SRWI instruction details with SH operand. >+ >+ >+[ Python binding ] >+ >+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes. >+- Fixed a memory leak for Cython disasm functions when we immaturely quit >+ the enumeration of disassembled instructions. >+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable >+ at the same time. >+- Fix a memory leaking bug when when we stop enumeration over the disassembled >+ instructions prematurely. >+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx). >+ >+--------------------------------- >+Version 3.0: November 19th, 2014 >+ >+[ API ] >+ >+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials. >+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but >+ marked obsolete to be removed in future) >+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going >+ from the next legitimate instruction. See docs/README for tutorials. >+- More details provided in cs_detail struct for all architectures. >+- API version was bumped to 3.0. >+ >+ >+[ Bindings ] >+ >+- Python binding supports Python3 (besides Python2). >+- Support Ocaml binding. >+- Java: add close() method to be used to deinitialize a Capstone object when >+ no longer use it. >+ >+ >+[ Architectures ] >+ >+- New architectures: Sparc, SystemZ & XCore. >+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86. >+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86. >+- Always expose absolute addresses rather than relative addresses (Arm, Arm64, >+ Mips, PPC, Sparc, X86). >+- Use common instruction operand types REG, IMM, MEM & FP across all >+ architectures (to enable cross-architecture analysis). >+- Use common instruction group types across all architectures (to enable >+ cross-architecture analysis). >+ >+ >+[ X86 ] >+ >+- X86 engine is mature & handles all the malware tricks (that we are aware of). >+- Added a lot of new instructions (such as AVX512, 3DNow, etc). >+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE. >+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions. >+- More friendly disassembly for JMP16i (in the form segment:offset) >+ >+ >+[ Mips ] >+ >+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) & >+ MipsGP64 (CS_MODE_MIPSGP64). >+- Removed the ABI-only mode CS_MODE_N64. >+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 & >+ CS_MODE_64). >+ >+ >+[ ARM ] >+ >+- Support new mode CS_MODE_V8 for Armv8 A32 encodings. >+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions >+ >+ >+[ ARM64 ] >+ >+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions. >+ >+ >+[ PowerPC ] >+ >+- Do not print a dot in front of absolute address. >+ >+ >+[ Other features ] >+ >+- Support for Microsoft Visual Studio (so enable Windows native compilation). >+- Support CMake compilation. >+- Cross-compile for Android. >+- Build libraries/tests using XCode project >+- Much faster, while consuming less memory for all architectures. >+ >+--------------------------------- >+Version 2.1.2: April 3rd, 2014 >+ >+This is a stable release to fix some bugs deep in the core. There is no update >+to any architectures or bindings, so bindings version 2.1 can be used with this >+version 2.1.2 just fine. >+ >+[ Core changes] >+ >+- Support cross-compilation for all iDevices (iPhone/iPad/iPod). >+- X86: do not print memory offset in negative form. >+- Fix a bug in X86 when Capstone cannot handle short instruction. >+- Print negative number above -9 without prefix 0x (arm64, mips, arm). >+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris). >+- Set library versioning for dylib of OSX. >+ >+--------------------------------- >+Version 2.1.1: March 13th, 2014 >+ >+This is a stable release to fix some bugs deep in the core. There is no update >+to any architectures or bindings, so bindings version 2.1 can be used with this >+version 2.1.1 just fine. >+ >+[ Core changes] >+ >+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can >+ trigger this flaw. >+- Fix a crash issue when embedding Capstone into OSX kernel. This should >+ also enable Capstone to be embedded into other systems with limited stack >+ memory size such as Linux kernel or some firmwares. >+- Use a proper SONAME for library versioning (Linux). >+ >+--------------------------------- >+Version 2.1: March 5th, 2014 >+ >+[ API changes ] >+ >+- API version has been bumped to 2.1. >+- Change prototype of cs_close() to be able to invalidate closed handle. >+ See http://capstone-engine.org/version_2.1_API.html for more information. >+- Extend cs_support() to handle more query types, not only about supported >+ architectures. This change is backward compatible, however, so existent code >+ do not need to be modified to support this. >+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of >+ the engine. >+- New error code CS_ERR_DIET to report errors about newly added diet mode. >+- New error code CS_ERR_VERSION to report issue of incompatible versions between >+ bindings & core engine. >+ >+ >+[ Core changes ] >+ >+- On memory usage, Capstone uses about 40% less memory, while still faster >+ than version 2.0. >+- All architectures are much smaller: binaries size reduce at least 30%. >+ Especially, X86-only binary reduces from 1.9MB to just 720KB. >+- Support "diet" mode, in which engine size is further reduced (by around 40%) >+ for embedding purpose. The price to pay is that we have to sacrifice some >+ non-critical data fields. See http://capstone-engine.org/diet.html for more >+ details. >+ >+ >+[ Architectures ] >+ >+- Update all 5 architectures to fix bugs. >+- PowerPC: >+ - New instructions: FMR & MSYNC. >+- Mips: >+ - New instruction: DLSA >+- X86: >+ - Properly handle AVX-512 instructions. >+ - New instructions: PSETPM, SALC, INT1, GETSEC. >+ - Fix some memory leaking issues in case of prefixed instructions such >+ as LOCK, REP, REPNE. >+ >+ >+[ Python binding ] >+ >+- Verify the core version at initialization time. Refuse to run if its version >+ is different from the core's version. >+- New API disasm_lite() added to Cs class. This light API only returns tuples of >+ (address, size, mnemonic, op_str), rather than list of CsInsn objects. This >+ improves performance by around 30% in some benchmarks. >+- New API version_bind() returns binding's version, which might differ from >+ the core's API version if the binding is out-of-date. >+- New API debug() returns information on Cython support, diet status & archs >+ compiled in. >+- Fixed some memory leaking bugs for Cython binding. >+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups. >+- Support diet mode. >+ >+ >+[ Java binding ] >+ >+- Fix some memory leaking bugs. >+- New API version() returns combined version. >+- Support diet mode. >+- Better support for detail option. >+ >+ >+[ Miscellaneous ] >+ >+- make.sh now can uninstall the core engine. This is done with: >+ >+ $ sudo ./make.sh uninstall >+ >+---------------------------------- >+Version 2.0: January 22nd, 2014 >+ >+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. >+ >+[ API changes ] >+ >+- API version has been bumped to 2.0 (see cs_version() API) >+- New API cs_strerror(errno) returns a string describing error code given >+ in its only argument. >+- cs_version() now returns combined version encoding both major & minor versions. >+- New option CS_OPT_MODE allows to change engineâs mode at run-time with >+ cs_option(). >+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically >+ memory management used internally by Capstone. This is useful to embed Capstone >+ into special environments such as kernel or firware. >+- New API cs_support() can be used to check if this lib supports a particular >+ architecture (this is necessary since we now allow to choose which architectures >+ to compile in). >+- The detail option is OFF by default now. To get detail information, it should be >+ explicitly turned ON. The details then can be accessed using cs_insn.detail >+ pointer (to newly added structure cs_detail) >+ >+ >+[ Core changes ] >+ >+- On memory usage, Capstone uses much less memory, but a lot faster now. >+- User now can choose which architectures to be supported by modifying config.mk >+ before compiling/installing. >+ >+ >+[ Architectures ] >+ >+- Arm >+ - Support Big-Endian mode (besides Little-Endian mode). >+ - Support friendly register, so instead of output sub "r12,r11,0x14", >+ we have "sub ip,fp,0x14". >+- Arm64: support Big-Endian mode (besides Little-Endian mode). >+- PowerPC: newly added. >+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f", >+ we have "srl $v0,$at,0x1f". >+- X86: bug fixes. >+ >+ >+[ Python binding ] >+ >+- Python binding is vastly improved in performance: around 3 ~ 4 times faster >+ than in 1.0. >+- Cython support has been added, which can further speed up over the default >+ pure Python binding (up to 30% in some cases) >+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) >+ to return succesfully disassembled instructions. This improves the performance >+ and reduces memory usage. >+ >+ >+[ Java binding ] >+ >+- Better performance & bug fixes. >+ >+ >+[ Miscellaneous ] >+ >+- Fixed some installation issues with Gentoo Linux. >+- Capstone now can easily compile/install on all *nix, including Linux, OSX, >+ {Net, Free, Open}BSD & Solaris. >+ >+---------------------------------- >+[Version 1.0]: December 18th, 2013 >+ >+- Initial public release. >+ >diff --git a/Source/ThirdParty/capstone/Source/HACK.TXT b/Source/ThirdParty/capstone/Source/HACK.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..5864bff280c5dda6b9ca4864df7bd61bc1f94fc8 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/HACK.TXT >@@ -0,0 +1,46 @@ >+Capstone source is organized as followings. >+ >+ >+. <- core engine + README + COMPILE.TXT etc >+âââ arch <- code handling disasm engine for each arch >+â  âââ AArch64 <- ARM64 (aka ARMv8) engine >+â  âââ ARM <- ARM engine >+â  âââ Mips <- Mips engine >+â  âââ PowerPC <- PowerPC engine >+â  âââ Sparc <- Sparc engine >+â  âââ SystemZ <- SystemZ engine >+â  âââ X86 <- X86 engine >+â  âââ XCore <- XCore engine >+âââ bindings <- all bindings are under this dir >+â  âââ java <- Java bindings + test code >+â  âââ ocaml <- Ocaml bindings + test code >+â  âââ python <- Python bindings + test code >+âââ contrib <- Code contributed by community to help Capstone integration >+âââ cstool <- Cstool >+âââ docs <- Documentation >+âââ include <- API headers in C language (*.h) >+âââ msvc <- Microsoft Visual Studio support (for Windows compile) >+âââ packages <- Packages for Linux/OSX/BSD. >+âââ windows <- Windows support (for Windows kernel driver compile) >+âââ suite <- Development test tools - for Capstone developers only >+âââ tests <- Test code (in C language) >+âââ xcode <- Xcode support (for MacOSX compile) >+ >+ >+Follow instructions in COMPILE.TXT for how to compile and run test code. >+ >+Note: if you find some strange bugs, it is recommended to firstly clean >+the code and try to recompile/reinstall again. This can be done with: >+ >+ $ ./make.sh >+ $ sudo ./make.sh install >+ >+Then test Capstone with cstool, for example: >+ >+ $ cstool x32 "90 91" >+ >+At the same time, for Java/Ocaml/Python bindings, be sure to always use >+the bindings coming with the core to avoid potential incompatibility issue >+with older versions. >+See bindings/<language>/README for detail instructions on how to compile & >+install the bindings. >diff --git a/Source/ThirdParty/capstone/Source/LEB128.h b/Source/ThirdParty/capstone/Source/LEB128.h >new file mode 100644 >index 0000000000000000000000000000000000000000..6a452740a379194a7e452ca676261aac1e4c0b8f >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/LEB128.h >@@ -0,0 +1,40 @@ >+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file declares some utility functions for encoding SLEB128 and >+// ULEB128 values. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_SUPPORT_LEB128_H >+#define CS_LLVM_SUPPORT_LEB128_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+/// Utility function to decode a ULEB128 value. >+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n) >+{ >+ const uint8_t *orig_p = p; >+ uint64_t Value = 0; >+ unsigned Shift = 0; >+ do { >+ Value += (*p & 0x7f) << Shift; >+ Shift += 7; >+ } while (*p++ >= 128); >+ if (n) >+ *n = (unsigned)(p - orig_p); >+ return Value; >+} >+ >+#endif // LLVM_SYSTEM_LEB128_H >diff --git a/Source/ThirdParty/capstone/Source/LICENSE.TXT b/Source/ThirdParty/capstone/Source/LICENSE.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..0dabdc749eee9faeaa358ecd831064463cd756bc >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/LICENSE.TXT >@@ -0,0 +1,31 @@ >+This is the software license for Capstone disassembly framework. >+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com> >+ >+See http://www.capstone-engine.org for further information. >+ >+Copyright (c) 2013, COSEINC. >+All rights reserved. >+ >+Redistribution and use in source and binary forms, with or without >+modification, are permitted provided that the following conditions are met: >+ >+* Redistributions of source code must retain the above copyright notice, >+ this list of conditions and the following disclaimer. >+* Redistributions in binary form must reproduce the above copyright notice, >+ this list of conditions and the following disclaimer in the documentation >+ and/or other materials provided with the distribution. >+* Neither the name of the developer(s) nor the names of its >+ contributors may be used to endorse or promote products derived from this >+ software without specific prior written permission. >+ >+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" >+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE >+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE >+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE >+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR >+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF >+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS >+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN >+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) >+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE >+POSSIBILITY OF SUCH DAMAGE. >diff --git a/Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT b/Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT >new file mode 100644 >index 0000000000000000000000000000000000000000..66d6647ffd70292fb8e74d17dd97d5605c5f9757 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/LICENSE_LLVM.TXT >@@ -0,0 +1,71 @@ >+============================================================================== >+LLVM Release License >+============================================================================== >+University of Illinois/NCSA >+Open Source License >+ >+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign. >+All rights reserved. >+ >+Developed by: >+ >+ LLVM Team >+ >+ University of Illinois at Urbana-Champaign >+ >+ http://llvm.org >+ >+Permission is hereby granted, free of charge, to any person obtaining a copy of >+this software and associated documentation files (the "Software"), to deal with >+the Software without restriction, including without limitation the rights to >+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies >+of the Software, and to permit persons to whom the Software is furnished to do >+so, subject to the following conditions: >+ >+ * Redistributions of source code must retain the above copyright notice, >+ this list of conditions and the following disclaimers. >+ >+ * Redistributions in binary form must reproduce the above copyright notice, >+ this list of conditions and the following disclaimers in the >+ documentation and/or other materials provided with the distribution. >+ >+ * Neither the names of the LLVM Team, University of Illinois at >+ Urbana-Champaign, nor the names of its contributors may be used to >+ endorse or promote products derived from this Software without specific >+ prior written permission. >+ >+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS >+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE >+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE >+SOFTWARE. >+ >+============================================================================== >+Copyrights and Licenses for Third Party Software Distributed with LLVM: >+============================================================================== >+The LLVM software contains code written by third parties. Such software will >+have its own individual LICENSE.TXT file in the directory in which it appears. >+This file will describe the copyrights, license, and restrictions which apply >+to that code. >+ >+The disclaimer of warranty in the University of Illinois Open Source License >+applies to all code in the LLVM Distribution, and nothing in any of the >+other licenses gives permission to use the names of the LLVM Team or the >+University of Illinois to endorse or promote products derived from this >+Software. >+ >+The following pieces of software have additional or alternate copyrights, >+licenses, and/or restrictions: >+ >+Program Directory >+------- --------- >+Autoconf llvm/autoconf >+ llvm/projects/ModuleMaker/autoconf >+ llvm/projects/sample/autoconf >+Google Test llvm/utils/unittest/googletest >+OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} >+pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} >+ARM contributions llvm/lib/Target/ARM/LICENSE.TXT >+md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h >diff --git a/Source/ThirdParty/capstone/Source/MCDisassembler.h b/Source/ThirdParty/capstone/Source/MCDisassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..bbbd38a07ea921ba3388cfa37f236495883c925b >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCDisassembler.h >@@ -0,0 +1,14 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_MCDISASSEMBLER_H >+#define CS_MCDISASSEMBLER_H >+ >+typedef enum DecodeStatus { >+ MCDisassembler_Fail = 0, >+ MCDisassembler_SoftFail = 1, >+ MCDisassembler_Success = 3, >+} DecodeStatus; >+ >+#endif >+ >diff --git a/Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h b/Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..ab8b96892908e824bc597da77afdb96e0e5c0fc4 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCFixedLenDisassembler.h >@@ -0,0 +1,30 @@ >+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// Fixed length disassembler decoder state machine driver. >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H >+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H >+ >+// Disassembler state machine opcodes. >+enum DecoderOps { >+ MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len) >+ MCD_OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip) >+ MCD_OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len, >+ // uleb128 Val, uint16_t NumToSkip) >+ MCD_OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip) >+ MCD_OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx) >+ MCD_OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask) >+ MCD_OPC_Fail // OPC_Fail() >+}; >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/MCInst.c b/Source/ThirdParty/capstone/Source/MCInst.c >new file mode 100644 >index 0000000000000000000000000000000000000000..bdbb82d6c68b4295fe0e149d2c2a6e5a61faf4fc >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCInst.c >@@ -0,0 +1,176 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#include <stdlib.h> >+#endif >+#include <string.h> >+ >+#include "MCInst.h" >+#include "utils.h" >+ >+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1) >+ >+void MCInst_Init(MCInst *inst) >+{ >+ inst->OpcodePub = 0; >+ inst->size = 0; >+ inst->has_imm = false; >+ inst->op1_size = 0; >+ inst->writeback = false; >+} >+ >+void MCInst_clear(MCInst *inst) >+{ >+ inst->size = 0; >+} >+ >+// do not free @Op >+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) >+{ >+ int i; >+ >+ for(i = inst->size; i > index; i--) >+ //memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand)); >+ inst->Operands[i] = inst->Operands[i-1]; >+ >+ inst->Operands[index] = *Op; >+ inst->size++; >+} >+ >+void MCInst_setOpcode(MCInst *inst, unsigned Op) >+{ >+ inst->Opcode = Op; >+} >+ >+void MCInst_setOpcodePub(MCInst *inst, unsigned Op) >+{ >+ inst->OpcodePub = Op; >+} >+ >+unsigned MCInst_getOpcode(const MCInst *inst) >+{ >+ return inst->Opcode; >+} >+ >+unsigned MCInst_getOpcodePub(const MCInst *inst) >+{ >+ return inst->OpcodePub; >+} >+ >+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) >+{ >+ return &inst->Operands[i]; >+} >+ >+unsigned MCInst_getNumOperands(const MCInst *inst) >+{ >+ return inst->size; >+} >+ >+// This addOperand2 function doesnt free Op >+void MCInst_addOperand2(MCInst *inst, MCOperand *Op) >+{ >+ inst->Operands[inst->size] = *Op; >+ >+ inst->size++; >+} >+ >+void MCOperand_Init(MCOperand *op) >+{ >+ op->Kind = kInvalid; >+ op->FPImmVal = 0.0; >+} >+ >+bool MCOperand_isValid(const MCOperand *op) >+{ >+ return op->Kind != kInvalid; >+} >+ >+bool MCOperand_isReg(const MCOperand *op) >+{ >+ return op->Kind == kRegister; >+} >+ >+bool MCOperand_isImm(const MCOperand *op) >+{ >+ return op->Kind == kImmediate; >+} >+ >+bool MCOperand_isFPImm(const MCOperand *op) >+{ >+ return op->Kind == kFPImmediate; >+} >+ >+/// getReg - Returns the register number. >+unsigned MCOperand_getReg(const MCOperand *op) >+{ >+ return op->RegVal; >+} >+ >+/// setReg - Set the register number. >+void MCOperand_setReg(MCOperand *op, unsigned Reg) >+{ >+ op->RegVal = Reg; >+} >+ >+int64_t MCOperand_getImm(MCOperand *op) >+{ >+ return op->ImmVal; >+} >+ >+void MCOperand_setImm(MCOperand *op, int64_t Val) >+{ >+ op->ImmVal = Val; >+} >+ >+double MCOperand_getFPImm(const MCOperand *op) >+{ >+ return op->FPImmVal; >+} >+ >+void MCOperand_setFPImm(MCOperand *op, double Val) >+{ >+ op->FPImmVal = Val; >+} >+ >+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg) >+{ >+ MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); >+ >+ op->Kind = kRegister; >+ op->RegVal = Reg; >+ >+ return op; >+} >+ >+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg) >+{ >+ MCOperand *op = &(mcInst->Operands[mcInst->size]); >+ mcInst->size++; >+ >+ op->Kind = kRegister; >+ op->RegVal = Reg; >+} >+ >+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val) >+{ >+ MCOperand *op = &(mcInst->Operands[MCINST_CACHE]); >+ >+ op->Kind = kImmediate; >+ op->ImmVal = Val; >+ >+ return op; >+} >+ >+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val) >+{ >+ MCOperand *op = &(mcInst->Operands[mcInst->size]); >+ mcInst->size++; >+ >+ op->Kind = kImmediate; >+ op->ImmVal = Val; >+} >diff --git a/Source/ThirdParty/capstone/Source/MCInst.h b/Source/ThirdParty/capstone/Source/MCInst.h >new file mode 100644 >index 0000000000000000000000000000000000000000..b98f37f42961b6c2bb6053e99174c7cfcb782ce1 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCInst.h >@@ -0,0 +1,133 @@ >+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the declaration of the MCInst and MCOperand classes, which >+// is the basic representation used to represent low-level machine code >+// instructions. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_MCINST_H >+#define CS_MCINST_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+#include "include/capstone.h" >+ >+typedef struct MCInst MCInst; >+typedef struct cs_struct cs_struct; >+typedef struct MCOperand MCOperand; >+ >+/// MCOperand - Instances of this class represent operands of the MCInst class. >+/// This is a simple discriminated union. >+struct MCOperand { >+ enum { >+ kInvalid = 0, ///< Uninitialized. >+ kRegister, ///< Register operand. >+ kImmediate, ///< Immediate operand. >+ kFPImmediate, ///< Floating-point immediate operand. >+ } MachineOperandType; >+ unsigned char Kind; >+ >+ union { >+ unsigned RegVal; >+ int64_t ImmVal; >+ double FPImmVal; >+ }; >+}; >+ >+bool MCOperand_isValid(const MCOperand *op); >+ >+bool MCOperand_isReg(const MCOperand *op); >+ >+bool MCOperand_isImm(const MCOperand *op); >+ >+bool MCOperand_isFPImm(const MCOperand *op); >+ >+bool MCOperand_isInst(const MCOperand *op); >+ >+/// getReg - Returns the register number. >+unsigned MCOperand_getReg(const MCOperand *op); >+ >+/// setReg - Set the register number. >+void MCOperand_setReg(MCOperand *op, unsigned Reg); >+ >+int64_t MCOperand_getImm(MCOperand *op); >+ >+void MCOperand_setImm(MCOperand *op, int64_t Val); >+ >+double MCOperand_getFPImm(const MCOperand *op); >+ >+void MCOperand_setFPImm(MCOperand *op, double Val); >+ >+const MCInst *MCOperand_getInst(const MCOperand *op); >+ >+void MCOperand_setInst(MCOperand *op, const MCInst *Val); >+ >+// create Reg operand in the next slot >+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg); >+ >+// create Reg operand use the last-unused slot >+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg); >+ >+// create Imm operand in the next slot >+void MCOperand_CreateImm0(MCInst *inst, int64_t Val); >+ >+// create Imm operand in the last-unused slot >+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val); >+ >+/// MCInst - Instances of this class represent a single low-level machine >+/// instruction. >+struct MCInst { >+ unsigned OpcodePub; >+ uint8_t size; // number of operands >+ bool has_imm; // indicate this instruction has an X86_OP_IMM operand - used for ATT syntax >+ uint8_t op1_size; // size of 1st operand - for X86 Intel syntax >+ unsigned Opcode; >+ MCOperand Operands[48]; >+ cs_insn *flat_insn; // insn to be exposed to public >+ uint64_t address; // address of this insn >+ cs_struct *csh; // save the main csh >+ uint8_t x86opsize; // opsize for [mem] operand >+ >+ // (Optional) instruction prefix, which can be up to 4 bytes. >+ // A prefix byte gets value 0 when irrelevant. >+ // This is copied from cs_x86 struct >+ uint8_t x86_prefix[4]; >+ uint8_t imm_size; // immediate size for X86_OP_IMM operand >+ bool writeback; // writeback for ARM >+}; >+ >+void MCInst_Init(MCInst *inst); >+ >+void MCInst_clear(MCInst *inst); >+ >+// do not free operand after inserting >+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op); >+ >+void MCInst_setOpcode(MCInst *inst, unsigned Op); >+ >+unsigned MCInst_getOpcode(const MCInst*); >+ >+void MCInst_setOpcodePub(MCInst *inst, unsigned Op); >+ >+unsigned MCInst_getOpcodePub(const MCInst*); >+ >+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); >+ >+unsigned MCInst_getNumOperands(const MCInst *inst); >+ >+// This addOperand2 function doesnt free Op >+void MCInst_addOperand2(MCInst *inst, MCOperand *Op); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/MCInstrDesc.c b/Source/ThirdParty/capstone/Source/MCInstrDesc.c >new file mode 100644 >index 0000000000000000000000000000000000000000..aae91ba55dd92e13a259df8dbeb4c10d0f4d9092 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCInstrDesc.c >@@ -0,0 +1,18 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#include "MCInstrDesc.h" >+ >+/// isPredicate - Set if this is one of the operands that made up of >+/// the predicate operand that controls an isPredicable() instruction. >+bool MCOperandInfo_isPredicate(const MCOperandInfo *m) >+{ >+ return m->Flags & (1 << MCOI_Predicate); >+} >+ >+/// isOptionalDef - Set if this operand is a optional def. >+/// >+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m) >+{ >+ return m->Flags & (1 << MCOI_OptionalDef); >+} >diff --git a/Source/ThirdParty/capstone/Source/MCInstrDesc.h b/Source/ThirdParty/capstone/Source/MCInstrDesc.h >new file mode 100644 >index 0000000000000000000000000000000000000000..730f21861ba837ed98c8ca2abf5ee946c7a11a80 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCInstrDesc.h >@@ -0,0 +1,145 @@ >+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file defines the MCOperandInfo and MCInstrDesc classes, which >+// are used to describe target instructions and their operands. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_MC_MCINSTRDESC_H >+#define CS_LLVM_MC_MCINSTRDESC_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+#include "include/platform.h" >+ >+//===----------------------------------------------------------------------===// >+// Machine Operand Flags and Description >+//===----------------------------------------------------------------------===// >+ >+// Operand constraints >+enum MCOI_OperandConstraint { >+ MCOI_TIED_TO = 0, // Must be allocated the same register as. >+ MCOI_EARLY_CLOBBER // Operand is an early clobber register operand >+}; >+ >+/// OperandFlags - These are flags set on operands, but should be considered >+/// private, all access should go through the MCOperandInfo accessors. >+/// See the accessors for a description of what these are. >+enum MCOI_OperandFlags { >+ MCOI_LookupPtrRegClass = 0, >+ MCOI_Predicate, >+ MCOI_OptionalDef >+}; >+ >+/// Operand Type - Operands are tagged with one of the values of this enum. >+enum MCOI_OperandType { >+ MCOI_OPERAND_UNKNOWN, >+ MCOI_OPERAND_IMMEDIATE, >+ MCOI_OPERAND_REGISTER, >+ MCOI_OPERAND_MEMORY, >+ MCOI_OPERAND_PCREL >+}; >+ >+ >+/// MCOperandInfo - This holds information about one operand of a machine >+/// instruction, indicating the register class for register operands, etc. >+/// >+typedef struct MCOperandInfo { >+ /// RegClass - This specifies the register class enumeration of the operand >+ /// if the operand is a register. If isLookupPtrRegClass is set, then this is >+ /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to >+ /// get a dynamic register class. >+ int16_t RegClass; >+ >+ /// Flags - These are flags from the MCOI::OperandFlags enum. >+ uint8_t Flags; >+ >+ /// OperandType - Information about the type of the operand. >+ uint8_t OperandType; >+ >+ /// Lower 16 bits are used to specify which constraints are set. The higher 16 >+ /// bits are used to specify the value of constraints (4 bits each). >+ uint32_t Constraints; >+ /// Currently no other information. >+} MCOperandInfo; >+ >+ >+//===----------------------------------------------------------------------===// >+// Machine Instruction Flags and Description >+//===----------------------------------------------------------------------===// >+ >+/// MCInstrDesc flags - These should be considered private to the >+/// implementation of the MCInstrDesc class. Clients should use the predicate >+/// methods on MCInstrDesc, not use these directly. These all correspond to >+/// bitfields in the MCInstrDesc::Flags field. >+enum { >+ MCID_Variadic = 0, >+ MCID_HasOptionalDef, >+ MCID_Pseudo, >+ MCID_Return, >+ MCID_Call, >+ MCID_Barrier, >+ MCID_Terminator, >+ MCID_Branch, >+ MCID_IndirectBranch, >+ MCID_Compare, >+ MCID_MoveImm, >+ MCID_Bitcast, >+ MCID_Select, >+ MCID_DelaySlot, >+ MCID_FoldableAsLoad, >+ MCID_MayLoad, >+ MCID_MayStore, >+ MCID_Predicable, >+ MCID_NotDuplicable, >+ MCID_UnmodeledSideEffects, >+ MCID_Commutable, >+ MCID_ConvertibleTo3Addr, >+ MCID_UsesCustomInserter, >+ MCID_HasPostISelHook, >+ MCID_Rematerializable, >+ MCID_CheapAsAMove, >+ MCID_ExtraSrcRegAllocReq, >+ MCID_ExtraDefRegAllocReq, >+ MCID_RegSequence, >+}; >+ >+/// MCInstrDesc - Describe properties that are true of each instruction in the >+/// target description file. This captures information about side effects, >+/// register use and many other things. There is one instance of this struct >+/// for each target instruction class, and the MachineInstr class points to >+/// this struct directly to describe itself. >+typedef struct MCInstrDesc { >+ unsigned short Opcode; // The opcode number >+ unsigned char NumOperands; // Num of args (may be more if variable_ops) >+ unsigned char NumDefs; // Num of args that are definitions >+ unsigned short SchedClass; // enum identifying instr sched class >+ unsigned char Size; // Number of bytes in encoding. >+ unsigned Flags; // Flags identifying machine instr class >+ uint64_t TSFlags; // Target Specific Flag values >+ char ImplicitUses; // Registers implicitly read by this instr >+ char ImplicitDefs; // Registers implicitly defined by this instr >+ const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands >+ uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any >+ // A complex method to determine is a certain is deprecated or not, and return >+ // the reason for deprecation. >+ //bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &); >+ unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer >+} MCInstrDesc; >+ >+bool MCOperandInfo_isPredicate(const MCOperandInfo *m); >+ >+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/MCRegisterInfo.c b/Source/ThirdParty/capstone/Source/MCRegisterInfo.c >new file mode 100644 >index 0000000000000000000000000000000000000000..b6f6289c006ee5f23276a2063a2b95783fd8c9de >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCRegisterInfo.c >@@ -0,0 +1,143 @@ >+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file implements MCRegisterInfo functions. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#include "MCRegisterInfo.h" >+ >+/// DiffListIterator - Base iterator class that can traverse the >+/// differentially encoded register and regunit lists in DiffLists. >+/// Don't use this class directly, use one of the specialized sub-classes >+/// defined below. >+typedef struct DiffListIterator { >+ uint16_t Val; >+ const MCPhysReg *List; >+} DiffListIterator; >+ >+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, >+ const MCRegisterDesc *D, unsigned NR, >+ unsigned RA, unsigned PC, >+ const MCRegisterClass *C, unsigned NC, >+ uint16_t (*RURoots)[2], unsigned NRU, >+ const MCPhysReg *DL, >+ const char *Strings, >+ const uint16_t *SubIndices, unsigned NumIndices, >+ const uint16_t *RET) >+{ >+ RI->Desc = D; >+ RI->NumRegs = NR; >+ RI->RAReg = RA; >+ RI->PCReg = PC; >+ RI->Classes = C; >+ RI->DiffLists = DL; >+ RI->RegStrings = Strings; >+ RI->NumClasses = NC; >+ RI->RegUnitRoots = RURoots; >+ RI->NumRegUnits = NRU; >+ RI->SubRegIndices = SubIndices; >+ RI->NumSubRegIndices = NumIndices; >+ RI->RegEncodingTable = RET; >+} >+ >+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList) >+{ >+ d->Val = InitVal; >+ d->List = DiffList; >+} >+ >+static uint16_t DiffListIterator_getVal(DiffListIterator *d) >+{ >+ return d->Val; >+} >+ >+static bool DiffListIterator_next(DiffListIterator *d) >+{ >+ MCPhysReg D; >+ >+ if (d->List == 0) >+ return false; >+ >+ D = *d->List; >+ d->List++; >+ d->Val += D; >+ >+ if (!D) >+ d->List = 0; >+ >+ return (D != 0); >+} >+ >+static bool DiffListIterator_isValid(DiffListIterator *d) >+{ >+ return (d->List != 0); >+} >+ >+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) >+{ >+ DiffListIterator iter; >+ >+ if (Reg >= RI->NumRegs) { >+ return 0; >+ } >+ >+ DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); >+ DiffListIterator_next(&iter); >+ >+ while(DiffListIterator_isValid(&iter)) { >+ uint16_t val = DiffListIterator_getVal(&iter); >+ if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) >+ return val; >+ >+ DiffListIterator_next(&iter); >+ } >+ >+ return 0; >+} >+ >+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx) >+{ >+ DiffListIterator iter; >+ const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; >+ >+ DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); >+ DiffListIterator_next(&iter); >+ >+ while(DiffListIterator_isValid(&iter)) { >+ if (*SRI == Idx) >+ return DiffListIterator_getVal(&iter); >+ DiffListIterator_next(&iter); >+ ++SRI; >+ } >+ >+ return 0; >+} >+ >+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i) >+{ >+ //assert(i < getNumRegClasses() && "Register Class ID out of range"); >+ if (i >= RI->NumClasses) >+ return 0; >+ return &(RI->Classes[i]); >+} >+ >+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg) >+{ >+ unsigned InByte = Reg % 8; >+ unsigned Byte = Reg / 8; >+ >+ if (Byte >= c->RegSetSize) >+ return false; >+ >+ return (c->RegSet[Byte] & (1 << InByte)) != 0; >+} >diff --git a/Source/ThirdParty/capstone/Source/MCRegisterInfo.h b/Source/ThirdParty/capstone/Source/MCRegisterInfo.h >new file mode 100644 >index 0000000000000000000000000000000000000000..4348dbcd2f4d9065dd46fd957390812bd6fc4b79 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MCRegisterInfo.h >@@ -0,0 +1,116 @@ >+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file describes an abstract interface used to get information about a >+// target machines register file. This information is used for a variety of >+// purposed, especially register allocation. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_MC_MCREGISTERINFO_H >+#define CS_LLVM_MC_MCREGISTERINFO_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+#include "include/platform.h" >+ >+/// An unsigned integer type large enough to represent all physical registers, >+/// but not necessarily virtual registers. >+typedef uint16_t MCPhysReg; >+typedef const MCPhysReg* iterator; >+ >+typedef struct MCRegisterClass { >+ const char *Name; >+ iterator RegsBegin; >+ const uint8_t *RegSet; >+ uint16_t RegsSize; >+ uint16_t RegSetSize; >+ uint16_t ID; >+ uint16_t RegSize, Alignment; // Size & Alignment of register in bytes >+ int8_t CopyCost; >+ bool Allocatable; >+} MCRegisterClass; >+ >+/// MCRegisterDesc - This record contains information about a particular >+/// register. The SubRegs field is a zero terminated array of registers that >+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers >+/// of AX. The SuperRegs field is a zero terminated array of registers that are >+/// super-registers of the specific register, e.g. RAX, EAX, are >+/// super-registers of AX. >+/// >+typedef struct MCRegisterDesc { >+ uint32_t Name; // Printable name for the reg (for debugging) >+ uint32_t SubRegs; // Sub-register set, described above >+ uint32_t SuperRegs; // Super-register set, described above >+ >+ // Offset into MCRI::SubRegIndices of a list of sub-register indices for each >+ // sub-register in SubRegs. >+ uint32_t SubRegIndices; >+ >+ // RegUnits - Points to the list of register units. The low 4 bits holds the >+ // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. >+ uint32_t RegUnits; >+} MCRegisterDesc; >+ >+/// MCRegisterInfo base class - We assume that the target defines a static >+/// array of MCRegisterDesc objects that represent all of the machine >+/// registers that the target has. As such, we simply have to track a pointer >+/// to this array so that we can turn register number into a register >+/// descriptor. >+/// >+/// Note this class is designed to be a base class of TargetRegisterInfo, which >+/// is the interface used by codegen. However, specific targets *should never* >+/// specialize this class. MCRegisterInfo should only contain getters to access >+/// TableGen generated physical register data. It must not be extended with >+/// virtual methods. >+/// >+typedef struct MCRegisterInfo { >+ const MCRegisterDesc *Desc; // Pointer to the descriptor array >+ unsigned NumRegs; // Number of entries in the array >+ unsigned RAReg; // Return address register >+ unsigned PCReg; // Program counter register >+ const MCRegisterClass *Classes; // Pointer to the regclass array >+ unsigned NumClasses; // Number of entries in the array >+ unsigned NumRegUnits; // Number of regunits. >+ uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. >+ const MCPhysReg *DiffLists; // Pointer to the difflists array >+ const char *RegStrings; // Pointer to the string table. >+ const uint16_t *SubRegIndices; // Pointer to the subreg lookup >+ // array. >+ unsigned NumSubRegIndices; // Number of subreg indices. >+ const uint16_t *RegEncodingTable; // Pointer to array of register >+ // encodings. >+} MCRegisterInfo; >+ >+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, >+ const MCRegisterDesc *D, unsigned NR, unsigned RA, >+ unsigned PC, >+ const MCRegisterClass *C, unsigned NC, >+ uint16_t (*RURoots)[2], >+ unsigned NRU, >+ const MCPhysReg *DL, >+ const char *Strings, >+ const uint16_t *SubIndices, >+ unsigned NumIndices, >+ const uint16_t *RET); >+ >+ >+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC); >+ >+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx); >+ >+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i); >+ >+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/Makefile b/Source/ThirdParty/capstone/Source/Makefile >new file mode 100644 >index 0000000000000000000000000000000000000000..063f50dbb72c0c4abab62e0a7bb04da935eda7ae >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/Makefile >@@ -0,0 +1,493 @@ >+# Capstone Disassembly Engine >+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 >+ >+include config.mk >+include pkgconfig.mk # package version >+include functions.mk >+ >+# Verbose output? >+V ?= 0 >+ >+ifeq ($(PKG_EXTRA),) >+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR) >+else >+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) >+endif >+ >+ifeq ($(CROSS),) >+CC ?= cc >+AR ?= ar >+RANLIB ?= ranlib >+STRIP ?= strip >+else >+CC = $(CROSS)gcc >+AR = $(CROSS)ar >+RANLIB = $(CROSS)ranlib >+STRIP = $(CROSS)strip >+endif >+ >+ifneq (,$(findstring yes,$(CAPSTONE_DIET))) >+CFLAGS ?= -Os >+CFLAGS += -DCAPSTONE_DIET >+else >+CFLAGS ?= -O3 >+endif >+ >+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) >+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE >+endif >+ >+CFLAGS += -fPIC -Wall -Wwrite-strings -Iinclude >+ >+ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) >+CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM >+endif >+ >+ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes) >+CFLAGS += -DCAPSTONE_HAS_OSXKERNEL >+SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path) >+CFLAGS += -mmacosx-version-min=10.5 \ >+ -isysroot$(SDKROOT) \ >+ -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \ >+ -mkernel \ >+ -fno-builtin >+endif >+ >+PREFIX ?= /usr >+DESTDIR ?= >+ifndef BUILDDIR >+BLDIR = . >+OBJDIR = . >+else >+BLDIR = $(abspath $(BUILDDIR)) >+OBJDIR = $(BLDIR)/obj >+endif >+INCDIR = $(DESTDIR)$(PREFIX)/include >+ >+UNAME_S := $(shell uname -s) >+ >+LIBDIRARCH ?= lib >+# Uncomment the below line to installs x86_64 libs to lib64/ directory. >+# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'. >+#LIBDIRARCH ?= lib64 >+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH) >+BINDIR = $(DESTDIR)$(PREFIX)/bin >+ >+LIBDATADIR = $(LIBDIR) >+ >+# Don't redefine $LIBDATADIR when global environment variable >+# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework. >+ >+ifndef USE_GENERIC_LIBDATADIR >+ifeq ($(UNAME_S), FreeBSD) >+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata >+endif >+ifeq ($(UNAME_S), DragonFly) >+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata >+endif >+endif >+ >+INSTALL_BIN ?= install >+INSTALL_DATA ?= $(INSTALL_BIN) -m0644 >+INSTALL_LIB ?= $(INSTALL_BIN) -m0755 >+ >+LIBNAME = capstone >+ >+ >+DEP_ARM = >+DEP_ARM += arch/ARM/ARMGenAsmWriter.inc >+DEP_ARM += arch/ARM/ARMGenDisassemblerTables.inc >+DEP_ARM += arch/ARM/ARMGenInstrInfo.inc >+DEP_ARM += arch/ARM/ARMGenRegisterInfo.inc >+DEP_ARM += arch/ARM/ARMGenSubtargetInfo.inc >+ >+LIBOBJ_ARM = >+ifneq (,$(findstring arm,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_ARM >+ LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMDisassembler.o >+ LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMInstPrinter.o >+ LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMMapping.o >+ LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMModule.o >+endif >+ >+DEP_ARM64 = >+DEP_ARM64 += arch/AArch64/AArch64GenAsmWriter.inc >+DEP_ARM64 += arch/AArch64/AArch64GenInstrInfo.inc >+DEP_ARM64 += arch/AArch64/AArch64GenSubtargetInfo.inc >+DEP_ARM64 += arch/AArch64/AArch64GenDisassemblerTables.inc >+DEP_ARM64 += arch/AArch64/AArch64GenRegisterInfo.inc >+ >+LIBOBJ_ARM64 = >+ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_ARM64 >+ LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64BaseInfo.o >+ LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Disassembler.o >+ LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64InstPrinter.o >+ LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Mapping.o >+ LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Module.o >+endif >+ >+ >+DEP_MIPS = >+DEP_MIPS += arch/Mips/MipsGenAsmWriter.inc >+DEP_MIPS += arch/Mips/MipsGenDisassemblerTables.inc >+DEP_MIPS += arch/Mips/MipsGenInstrInfo.inc >+DEP_MIPS += arch/Mips/MipsGenRegisterInfo.inc >+DEP_MIPS += arch/Mips/MipsGenSubtargetInfo.inc >+ >+LIBOBJ_MIPS = >+ifneq (,$(findstring mips,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_MIPS >+ LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsDisassembler.o >+ LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsInstPrinter.o >+ LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsMapping.o >+ LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsModule.o >+endif >+ >+ >+DEP_PPC = >+DEP_PPC += arch/PowerPC/PPCGenAsmWriter.inc >+DEP_PPC += arch/PowerPC/PPCGenInstrInfo.inc >+DEP_PPC += arch/PowerPC/PPCGenSubtargetInfo.inc >+DEP_PPC += arch/PowerPC/PPCGenDisassemblerTables.inc >+DEP_PPC += arch/PowerPC/PPCGenRegisterInfo.inc >+ >+LIBOBJ_PPC = >+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_POWERPC >+ LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCDisassembler.o >+ LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCInstPrinter.o >+ LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCMapping.o >+ LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCModule.o >+endif >+ >+ >+DEP_SPARC = >+DEP_SPARC += arch/Sparc/SparcGenAsmWriter.inc >+DEP_SPARC += arch/Sparc/SparcGenInstrInfo.inc >+DEP_SPARC += arch/Sparc/SparcGenSubtargetInfo.inc >+DEP_SPARC += arch/Sparc/SparcGenDisassemblerTables.inc >+DEP_SPARC += arch/Sparc/SparcGenRegisterInfo.inc >+ >+LIBOBJ_SPARC = >+ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_SPARC >+ LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcDisassembler.o >+ LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcInstPrinter.o >+ LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcMapping.o >+ LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcModule.o >+endif >+ >+ >+DEP_SYSZ = >+DEP_SYSZ += arch/SystemZ/SystemZGenAsmWriter.inc >+DEP_SYSZ += arch/SystemZ/SystemZGenInstrInfo.inc >+DEP_SYSZ += arch/SystemZ/SystemZGenSubtargetInfo.inc >+DEP_SYSZ += arch/SystemZ/SystemZGenDisassemblerTables.inc >+DEP_SYSZ += arch/SystemZ/SystemZGenRegisterInfo.inc >+ >+LIBOBJ_SYSZ = >+ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_SYSZ >+ LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZDisassembler.o >+ LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZInstPrinter.o >+ LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMapping.o >+ LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZModule.o >+ LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMCTargetDesc.o >+endif >+ >+ >+# by default, we compile full X86 instruction sets >+X86_REDUCE = >+ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE))) >+X86_REDUCE = _reduce >+CFLAGS += -DCAPSTONE_X86_REDUCE -Os >+endif >+ >+DEP_X86 = >+DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc >+DEP_X86 += arch/X86/X86GenRegisterInfo.inc >+ >+LIBOBJ_X86 = >+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_X86 >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o >+# assembly syntax is irrelevant in Diet mode, when this info is suppressed >+ifeq (,$(findstring yes,$(CAPSTONE_DIET))) >+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE))) >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o >+endif >+endif >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o >+ LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o >+endif >+ >+ >+DEP_XCORE = >+DEP_XCORE += arch/XCore/XCoreGenAsmWriter.inc >+DEP_XCORE += arch/XCore/XCoreGenInstrInfo.inc >+DEP_XCORE += arch/XCore/XCoreGenDisassemblerTables.inc >+DEP_XCORE += arch/XCore/XCoreGenRegisterInfo.inc >+ >+LIBOBJ_XCORE = >+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS))) >+ CFLAGS += -DCAPSTONE_HAS_XCORE >+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreDisassembler.o >+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreInstPrinter.o >+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreMapping.o >+ LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreModule.o >+endif >+ >+ >+LIBOBJ = >+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o >+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE) >+LIBOBJ += $(OBJDIR)/MCInst.o >+ >+ >+PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig >+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}') >+VERSION_EXT = >+ >+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep -cm 1 -e __apple_build_version__ -e __APPLE_CC__) >+ifeq ($(IS_APPLE),1) >+# on MacOS, compile in Universal format by default >+MACOS_UNIVERSAL ?= yes >+ifeq ($(MACOS_UNIVERSAL),yes) >+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+endif >+EXT = dylib >+VERSION_EXT = $(API_MAJOR).$(EXT) >+$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR) >+AR_EXT = a >+# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE >+# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default >+ifneq ($(HOMEBREW_CAPSTONE),1) >+ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes) >+# remove string check because OSX kernel complains about missing symbols >+CFLAGS += -D_FORTIFY_SOURCE=0 >+endif >+endif >+else >+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch)) >+$(LIBNAME)_LDFLAGS += -shared >+# Cygwin? >+IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l) >+ifeq ($(IS_CYGWIN),1) >+EXT = dll >+AR_EXT = lib >+# Cygwin doesn't like -fPIC >+CFLAGS := $(CFLAGS:-fPIC=) >+# On Windows we need the shared library to be executable >+else >+# mingw? >+IS_MINGW := $(shell $(CC) --version | grep -i mingw | wc -l) >+ifeq ($(IS_MINGW),1) >+EXT = dll >+AR_EXT = lib >+# mingw doesn't like -fPIC either >+CFLAGS := $(CFLAGS:-fPIC=) >+# On Windows we need the shared library to be executable >+else >+# Linux, *BSD >+EXT = so >+VERSION_EXT = $(EXT).$(API_MAJOR) >+AR_EXT = a >+$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT) >+endif >+endif >+endif >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+ifeq ($(IS_MINGW),1) >+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT) >+else ifeq ($(IS_CYGWIN),1) >+LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT) >+else # *nix >+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(EXT) >+CFLAGS += -fvisibility=hidden >+endif >+endif >+ >+ifeq ($(CAPSTONE_STATIC),yes) >+ifeq ($(IS_MINGW),1) >+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) >+else ifeq ($(IS_CYGWIN),1) >+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT) >+else >+ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT) >+endif >+endif >+ >+PKGCFGF = $(BLDIR)/$(LIBNAME).pc >+ >+.PHONY: all clean install uninstall dist >+ >+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF) >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ @V=$(V) CC=$(CC) $(MAKE) -C cstool >+ifndef BUILDDIR >+ cd tests && $(MAKE) >+else >+ cd tests && $(MAKE) BUILDDIR=$(BLDIR) >+endif >+ $(call install-library,$(BLDIR)/tests/) >+endif >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+$(LIBRARY): $(LIBOBJ) >+ifeq ($(V),0) >+ $(call log,LINK,$(@:$(BLDIR)/%=%)) >+ @$(create-library) >+else >+ $(create-library) >+endif >+endif >+ >+$(LIBOBJ): *.h include/*.h config.mk >+ >+$(LIBOBJ_ARM): $(DEP_ARM) >+$(LIBOBJ_ARM64): $(DEP_ARM64) >+$(LIBOBJ_MIPS): $(DEP_MIPS) >+$(LIBOBJ_PPC): $(DEP_PPC) >+$(LIBOBJ_SPARC): $(DEP_SPARC) >+$(LIBOBJ_SYSZ): $(DEP_SYSZ) >+$(LIBOBJ_X86): $(DEP_X86) >+$(LIBOBJ_XCORE): $(DEP_XCORE) >+ >+ifeq ($(CAPSTONE_STATIC),yes) >+$(ARCHIVE): $(LIBOBJ) >+ @rm -f $(ARCHIVE) >+ifeq ($(V),0) >+ $(call log,AR,$(@:$(BLDIR)/%=%)) >+ @$(create-archive) >+else >+ $(create-archive) >+endif >+endif >+ >+$(PKGCFGF): >+ifeq ($(V),0) >+ $(call log,GEN,$(@:$(BLDIR)/%=%)) >+ @$(generate-pkgcfg) >+else >+ $(generate-pkgcfg) >+endif >+ >+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY) >+ mkdir -p $(LIBDIR) >+ $(call install-library,$(LIBDIR)) >+ifeq ($(CAPSTONE_STATIC),yes) >+ $(INSTALL_DATA) $(ARCHIVE) $(LIBDIR) >+endif >+ mkdir -p $(INCDIR)/$(LIBNAME) >+ $(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME) >+ mkdir -p $(PKGCFGDIR) >+ $(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)/ >+ mkdir -p $(BINDIR) >+ $(INSTALL_LIB) cstool/cstool $(BINDIR) >+ >+uninstall: >+ rm -rf $(INCDIR)/$(LIBNAME) >+ rm -f $(LIBDIR)/lib$(LIBNAME).* >+ rm -f $(PKGCFGDIR)/$(LIBNAME).pc >+ rm -f $(BINDIR)/cstool >+ >+clean: >+ rm -f $(LIBOBJ) >+ rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc >+ rm -f $(PKGCFGF) >+ $(MAKE) -C cstool clean >+ >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ cd tests && $(MAKE) clean >+ rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT) >+endif >+ >+ifdef BUILDDIR >+ rm -rf $(BUILDDIR) >+endif >+ >+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY))) >+ cd bindings/python && $(MAKE) clean >+ cd bindings/java && $(MAKE) clean >+ cd bindings/ocaml && $(MAKE) clean >+endif >+ >+ >+TAG ?= HEAD >+ifeq ($(TAG), HEAD) >+DIST_VERSION = latest >+else >+DIST_VERSION = $(TAG) >+endif >+ >+dist: >+ git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz >+ git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip >+ >+ >+TESTS = test_basic test_detail test_arm test_arm64 test_mips test_ppc test_sparc >+TESTS += test_systemz test_x86 test_xcore test_iter >+TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static >+TESTS += test_mips.static test_ppc.static test_sparc.static >+TESTS += test_systemz.static test_x86.static test_xcore.static >+TESTS += test_skipdata test_skipdata.static test_iter.static >+check: >+ @for t in $(TESTS); do \ >+ echo Check $$t ... ; \ >+ LD_LIBRARY_PATH=./tests ./tests/$$t > /dev/null && echo OK || echo FAILED; \ >+ done >+ >+$(OBJDIR)/%.o: %.c >+ @mkdir -p $(@D) >+ifeq ($(V),0) >+ $(call log,CC,$(@:$(OBJDIR)/%=%)) >+ @$(compile) >+else >+ $(compile) >+endif >+ >+ >+ifeq ($(CAPSTONE_SHARED),yes) >+define install-library >+ $(INSTALL_LIB) $(LIBRARY) $1 >+ $(if $(VERSION_EXT), >+ cd $1 && \ >+ mv lib$(LIBNAME).$(EXT) lib$(LIBNAME).$(VERSION_EXT) && \ >+ ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT)) >+endef >+else >+define install-library >+endef >+endif >+ >+ >+define create-archive >+ $(AR) q $(ARCHIVE) $(LIBOBJ) >+ $(RANLIB) $(ARCHIVE) >+endef >+ >+ >+define create-library >+ $(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY) >+endef >+ >+ >+define generate-pkgcfg >+ echo 'Name: capstone' > $(PKGCFGF) >+ echo 'Description: Capstone disassembly engine' >> $(PKGCFGF) >+ echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF) >+ echo 'libdir=$(LIBDIR)' >> $(PKGCFGF) >+ echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF) >+ echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF) >+ echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF) >+ echo 'Cflags: -I$${includedir}' >> $(PKGCFGF) >+endef >diff --git a/Source/ThirdParty/capstone/Source/MathExtras.h b/Source/ThirdParty/capstone/Source/MathExtras.h >new file mode 100644 >index 0000000000000000000000000000000000000000..db98a2f7702843903e2421ae68ee27d766eb2803 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/MathExtras.h >@@ -0,0 +1,441 @@ >+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains some functions that are useful for math stuff. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H >+#define CS_LLVM_SUPPORT_MATHEXTRAS_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+#ifdef _MSC_VER >+# include <intrin.h> >+#endif >+ >+#ifndef __cplusplus >+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) >+#define inline /* inline */ >+#endif >+#endif >+ >+// NOTE: The following support functions use the _32/_64 extensions instead of >+// type overloading so that signed and unsigned integers can be used without >+// ambiguity. >+ >+/// Hi_32 - This function returns the high 32 bits of a 64 bit value. >+static inline uint32_t Hi_32(uint64_t Value) { >+ return (uint32_t)(Value >> 32); >+} >+ >+/// Lo_32 - This function returns the low 32 bits of a 64 bit value. >+static inline uint32_t Lo_32(uint64_t Value) { >+ return (uint32_t)(Value); >+} >+ >+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic) >+/// bit width. >+static inline bool isUIntN(unsigned N, uint64_t x) { >+ return x == (x & (~0ULL >> (64 - N))); >+} >+ >+/// isIntN - Checks if an signed integer fits into the given (dynamic) >+/// bit width. >+//static inline bool isIntN(unsigned N, int64_t x) { >+// return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1))); >+//} >+ >+/// isMask_32 - This function returns true if the argument is a sequence of ones >+/// starting at the least significant bit with the remainder zero (32 bit >+/// version). Ex. isMask_32(0x0000FFFFU) == true. >+static inline bool isMask_32(uint32_t Value) { >+ return Value && ((Value + 1) & Value) == 0; >+} >+ >+/// isMask_64 - This function returns true if the argument is a sequence of ones >+/// starting at the least significant bit with the remainder zero (64 bit >+/// version). >+static inline bool isMask_64(uint64_t Value) { >+ return Value && ((Value + 1) & Value) == 0; >+} >+ >+/// isShiftedMask_32 - This function returns true if the argument contains a >+/// sequence of ones with the remainder zero (32 bit version.) >+/// Ex. isShiftedMask_32(0x0000FF00U) == true. >+static inline bool isShiftedMask_32(uint32_t Value) { >+ return isMask_32((Value - 1) | Value); >+} >+ >+/// isShiftedMask_64 - This function returns true if the argument contains a >+/// sequence of ones with the remainder zero (64 bit version.) >+static inline bool isShiftedMask_64(uint64_t Value) { >+ return isMask_64((Value - 1) | Value); >+} >+ >+/// isPowerOf2_32 - This function returns true if the argument is a power of >+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) >+static inline bool isPowerOf2_32(uint32_t Value) { >+ return Value && !(Value & (Value - 1)); >+} >+ >+/// CountLeadingZeros_32 - this function performs the platform optimal form of >+/// counting the number of zeros from the most significant bit to the first one >+/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8. >+/// Returns 32 if the word is zero. >+static inline unsigned CountLeadingZeros_32(uint32_t Value) { >+ unsigned Count; // result >+#if __GNUC__ >= 4 >+ // PowerPC is defined for __builtin_clz(0) >+#if !defined(__ppc__) && !defined(__ppc64__) >+ if (!Value) return 32; >+#endif >+ Count = __builtin_clz(Value); >+#else >+ unsigned Shift; >+ if (!Value) return 32; >+ Count = 0; >+ // bisection method for count leading zeros >+ for (Shift = 32 >> 1; Shift; Shift >>= 1) { >+ uint32_t Tmp = Value >> Shift; >+ if (Tmp) { >+ Value = Tmp; >+ } else { >+ Count |= Shift; >+ } >+ } >+#endif >+ return Count; >+} >+ >+/// CountLeadingOnes_32 - this function performs the operation of >+/// counting the number of ones from the most significant bit to the first zero >+/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8. >+/// Returns 32 if the word is all ones. >+static inline unsigned CountLeadingOnes_32(uint32_t Value) { >+ return CountLeadingZeros_32(~Value); >+} >+ >+/// CountLeadingZeros_64 - This function performs the platform optimal form >+/// of counting the number of zeros from the most significant bit to the first >+/// one bit (64 bit edition.) >+/// Returns 64 if the word is zero. >+static inline unsigned CountLeadingZeros_64(uint64_t Value) { >+ unsigned Count; // result >+#if __GNUC__ >= 4 >+ // PowerPC is defined for __builtin_clzll(0) >+#if !defined(__ppc__) && !defined(__ppc64__) >+ if (!Value) return 64; >+#endif >+ Count = __builtin_clzll(Value); >+#else >+#ifndef _MSC_VER >+ unsigned Shift; >+ if (sizeof(long) == sizeof(int64_t)) >+ { >+ if (!Value) return 64; >+ Count = 0; >+ // bisection method for count leading zeros >+ for (Shift = 64 >> 1; Shift; Shift >>= 1) { >+ uint64_t Tmp = Value >> Shift; >+ if (Tmp) { >+ Value = Tmp; >+ } else { >+ Count |= Shift; >+ } >+ } >+ } >+ else >+#endif >+ { >+ // get hi portion >+ uint32_t Hi = Hi_32(Value); >+ >+ // if some bits in hi portion >+ if (Hi) { >+ // leading zeros in hi portion plus all bits in lo portion >+ Count = CountLeadingZeros_32(Hi); >+ } else { >+ // get lo portion >+ uint32_t Lo = Lo_32(Value); >+ // same as 32 bit value >+ Count = CountLeadingZeros_32(Lo)+32; >+ } >+ } >+#endif >+ return Count; >+} >+ >+/// CountLeadingOnes_64 - This function performs the operation >+/// of counting the number of ones from the most significant bit to the first >+/// zero bit (64 bit edition.) >+/// Returns 64 if the word is all ones. >+static inline unsigned CountLeadingOnes_64(uint64_t Value) { >+ return CountLeadingZeros_64(~Value); >+} >+ >+/// CountTrailingZeros_32 - this function performs the platform optimal form of >+/// counting the number of zeros from the least significant bit to the first one >+/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8. >+/// Returns 32 if the word is zero. >+static inline unsigned CountTrailingZeros_32(uint32_t Value) { >+#if __GNUC__ >= 4 >+ return Value ? __builtin_ctz(Value) : 32; >+#else >+ static const unsigned Mod37BitPosition[] = { >+ 32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, >+ 4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, >+ 5, 20, 8, 19, 18 >+ }; >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return Mod37BitPosition[(-Value & Value) % 37]; >+ return Mod37BitPosition[((1 + ~Value) & Value) % 37]; >+#endif >+} >+ >+/// CountTrailingOnes_32 - this function performs the operation of >+/// counting the number of ones from the least significant bit to the first zero >+/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8. >+/// Returns 32 if the word is all ones. >+static inline unsigned CountTrailingOnes_32(uint32_t Value) { >+ return CountTrailingZeros_32(~Value); >+} >+ >+/// CountTrailingZeros_64 - This function performs the platform optimal form >+/// of counting the number of zeros from the least significant bit to the first >+/// one bit (64 bit edition.) >+/// Returns 64 if the word is zero. >+static inline unsigned CountTrailingZeros_64(uint64_t Value) { >+#if __GNUC__ >= 4 >+ return Value ? __builtin_ctzll(Value) : 64; >+#else >+ static const unsigned Mod67Position[] = { >+ 64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54, >+ 4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55, >+ 47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27, >+ 29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56, >+ 7, 48, 35, 6, 34, 33, 0 >+ }; >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return Mod67Position[(-Value & Value) % 67]; >+ return Mod67Position[((1 + ~Value) & Value) % 67]; >+#endif >+} >+ >+/// CountTrailingOnes_64 - This function performs the operation >+/// of counting the number of ones from the least significant bit to the first >+/// zero bit (64 bit edition.) >+/// Returns 64 if the word is all ones. >+static inline unsigned CountTrailingOnes_64(uint64_t Value) { >+ return CountTrailingZeros_64(~Value); >+} >+ >+/// CountPopulation_32 - this function counts the number of set bits in a value. >+/// Ex. CountPopulation(0xF000F000) = 8 >+/// Returns 0 if the word is zero. >+static inline unsigned CountPopulation_32(uint32_t Value) { >+#if __GNUC__ >= 4 >+ return __builtin_popcount(Value); >+#else >+ uint32_t v = Value - ((Value >> 1) & 0x55555555); >+ v = (v & 0x33333333) + ((v >> 2) & 0x33333333); >+ return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24; >+#endif >+} >+ >+/// CountPopulation_64 - this function counts the number of set bits in a value, >+/// (64 bit edition.) >+static inline unsigned CountPopulation_64(uint64_t Value) { >+#if __GNUC__ >= 4 >+ return __builtin_popcountll(Value); >+#else >+ uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL); >+ v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); >+ v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; >+ return (uint64_t)((v * 0x0101010101010101ULL) >> 56); >+#endif >+} >+ >+/// Log2_32 - This function returns the floor log base 2 of the specified value, >+/// -1 if the value is zero. (32 bit edition.) >+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 >+static inline unsigned Log2_32(uint32_t Value) { >+ return 31 - CountLeadingZeros_32(Value); >+} >+ >+/// Log2_64 - This function returns the floor log base 2 of the specified value, >+/// -1 if the value is zero. (64 bit edition.) >+static inline unsigned Log2_64(uint64_t Value) { >+ return 63 - CountLeadingZeros_64(Value); >+} >+ >+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified >+/// value, 32 if the value is zero. (32 bit edition). >+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 >+static inline unsigned Log2_32_Ceil(uint32_t Value) { >+ return 32-CountLeadingZeros_32(Value-1); >+} >+ >+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified >+/// value, 64 if the value is zero. (64 bit edition.) >+static inline unsigned Log2_64_Ceil(uint64_t Value) { >+ return 64-CountLeadingZeros_64(Value-1); >+} >+ >+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two >+/// values using Euclid's algorithm. >+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { >+ while (B) { >+ uint64_t T = B; >+ B = A % B; >+ A = T; >+ } >+ return A; >+} >+ >+/// BitsToDouble - This function takes a 64-bit integer and returns the bit >+/// equivalent double. >+static inline double BitsToDouble(uint64_t Bits) { >+ union { >+ uint64_t L; >+ double D; >+ } T; >+ T.L = Bits; >+ return T.D; >+} >+ >+/// BitsToFloat - This function takes a 32-bit integer and returns the bit >+/// equivalent float. >+static inline float BitsToFloat(uint32_t Bits) { >+ union { >+ uint32_t I; >+ float F; >+ } T; >+ T.I = Bits; >+ return T.F; >+} >+ >+/// DoubleToBits - This function takes a double and returns the bit >+/// equivalent 64-bit integer. Note that copying doubles around >+/// changes the bits of NaNs on some hosts, notably x86, so this >+/// routine cannot be used if these bits are needed. >+static inline uint64_t DoubleToBits(double Double) { >+ union { >+ uint64_t L; >+ double D; >+ } T; >+ T.D = Double; >+ return T.L; >+} >+ >+/// FloatToBits - This function takes a float and returns the bit >+/// equivalent 32-bit integer. Note that copying floats around >+/// changes the bits of NaNs on some hosts, notably x86, so this >+/// routine cannot be used if these bits are needed. >+static inline uint32_t FloatToBits(float Float) { >+ union { >+ uint32_t I; >+ float F; >+ } T; >+ T.F = Float; >+ return T.I; >+} >+ >+/// MinAlign - A and B are either alignments or offsets. Return the minimum >+/// alignment that may be assumed after adding the two together. >+static inline uint64_t MinAlign(uint64_t A, uint64_t B) { >+ // The largest power of 2 that divides both A and B. >+ // >+ // Replace "-Value" by "1+~Value" in the following commented code to avoid >+ // MSVC warning C4146 >+ // return (A | B) & -(A | B); >+ return (A | B) & (1 + ~(A | B)); >+} >+ >+/// NextPowerOf2 - Returns the next power of two (in 64-bits) >+/// that is strictly greater than A. Returns zero on overflow. >+static inline uint64_t NextPowerOf2(uint64_t A) { >+ A |= (A >> 1); >+ A |= (A >> 2); >+ A |= (A >> 4); >+ A |= (A >> 8); >+ A |= (A >> 16); >+ A |= (A >> 32); >+ return A + 1; >+} >+ >+/// Returns the next integer (mod 2**64) that is greater than or equal to >+/// \p Value and is a multiple of \p Align. \p Align must be non-zero. >+/// >+/// Examples: >+/// \code >+/// RoundUpToAlignment(5, 8) = 8 >+/// RoundUpToAlignment(17, 8) = 24 >+/// RoundUpToAlignment(~0LL, 8) = 0 >+/// \endcode >+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) { >+ return ((Value + Align - 1) / Align) * Align; >+} >+ >+/// Returns the offset to the next integer (mod 2**64) that is greater than >+/// or equal to \p Value and is a multiple of \p Align. \p Align must be >+/// non-zero. >+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) { >+ return RoundUpToAlignment(Value, Align) - Value; >+} >+ >+/// abs64 - absolute value of a 64-bit int. Not all environments support >+/// "abs" on whatever their name for the 64-bit int type is. The absolute >+/// value of the largest negative number is undefined, as with "abs". >+static inline int64_t abs64(int64_t x) { >+ return (x < 0) ? -x : x; >+} >+ >+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int. >+/// Requires 0 < B <= 32. >+static inline int32_t SignExtend32(uint32_t X, unsigned B) { >+ return (int32_t)(X << (32 - B)) >> (32 - B); >+} >+ >+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int. >+/// Requires 0 < B <= 64. >+static inline int64_t SignExtend64(uint64_t X, unsigned B) { >+ return (int64_t)(X << (64 - B)) >> (64 - B); >+} >+ >+/// \brief Count number of 0's from the most significant bit to the least >+/// stopping at the first 1. >+/// >+/// Only unsigned integral types are allowed. >+/// >+/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are >+/// valid arguments. >+static inline unsigned int countLeadingZeros(int x) >+{ >+ unsigned count = 0; >+ int i; >+ const unsigned bits = sizeof(x) * 8; >+ >+ for (i = bits; --i; ) { >+ if (x < 0) break; >+ count++; >+ x <<= 1; >+ } >+ >+ return count; >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/README b/Source/ThirdParty/capstone/Source/README >new file mode 100644 >index 0000000000000000000000000000000000000000..d9682364eb888a881d590c57b6b4b3095bd950df >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/README >@@ -0,0 +1,55 @@ >+Capstone is a disassembly framework with the target of becoming the ultimate >+disasm engine for binary analysis and reversing in the security community. >+ >+Created by Nguyen Anh Quynh, then developed and maintained by a small community, >+Capstone offers some unparalleled features: >+ >+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc, >+ SystemZ, XCore and X86 (including X86_64). >+ >+- Having clean/simple/lightweight/intuitive architecture-neutral API. >+ >+- Provide details on disassembled instruction (called âdecomposerâ by others). >+ >+- Provide semantics of the disassembled instruction, such as list of implicit >+ registers read & written. >+ >+- Implemented in pure C language, with lightweight bindings for Visual Basic, PHP, >+ PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, >+ Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided >+ externally by the community). >+ >+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android, >+ Linux, *BSD, Solaris, etc. >+ >+- Thread-safe by design. >+ >+- Special support for embedding into firmware or OS kernel. >+ >+- High performance & suitable for malware analysis (capable of handling various >+ X86 malware tricks). >+ >+- Distributed under the open source BSD license. >+ >+Further information is available at http://www.capstone-engine.org >+ >+ >+[Compile] >+ >+See COMPILE.TXT file for how to compile and install Capstone. >+ >+ >+[Documentation] >+ >+See docs/README for how to customize & program your own tools with Capstone. >+ >+ >+[Hack] >+ >+See HACK.TXT file for the structure of the source code. >+ >+ >+[License] >+ >+This project is released under the BSD license. If you redistribute the binary >+or source code of Capstone, please attach file LICENSE.TXT with your products. >diff --git a/Source/ThirdParty/capstone/Source/RELEASE_NOTES b/Source/ThirdParty/capstone/Source/RELEASE_NOTES >new file mode 100644 >index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 >diff --git a/Source/ThirdParty/capstone/Source/SStream.c b/Source/ThirdParty/capstone/Source/SStream.c >new file mode 100644 >index 0000000000000000000000000000000000000000..4850bbbb942be8b9d6e24f802e7407d1285b6072 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/SStream.c >@@ -0,0 +1,190 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+#include <stdarg.h> >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#endif >+#include <string.h> >+#include <limits.h> >+ >+#include <platform.h> >+ >+#include "SStream.h" >+#include "cs_priv.h" >+#include "utils.h" >+ >+#ifdef _MSC_VER >+#pragma warning(disable: 4996) // disable MSVC's warning on strcpy() >+#endif >+ >+void SStream_Init(SStream *ss) >+{ >+ ss->index = 0; >+ ss->buffer[0] = '\0'; >+} >+ >+void SStream_concat0(SStream *ss, const char *s) >+{ >+#ifndef CAPSTONE_DIET >+ unsigned int len = (unsigned int) strlen(s); >+ >+ memcpy(ss->buffer + ss->index, s, len); >+ ss->index += len; >+ ss->buffer[ss->index] = '\0'; >+#endif >+} >+ >+void SStream_concat(SStream *ss, const char *fmt, ...) >+{ >+#ifndef CAPSTONE_DIET >+ va_list ap; >+ int ret; >+ >+ va_start(ap, fmt); >+ ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap); >+ va_end(ap); >+ ss->index += ret; >+#endif >+} >+ >+// print number with prefix # >+void printInt64Bang(SStream *O, int64_t val) >+{ >+ if (val == LONG_MIN) { >+ return; >+ } >+ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, val); >+ else >+ SStream_concat(O, "#%"PRIu64, val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%"PRIx64, -val); >+ else >+ SStream_concat(O, "#-%"PRIu64, -val); >+ } >+} >+ >+void printUInt64Bang(SStream *O, uint64_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, val); >+ else >+ SStream_concat(O, "#%"PRIu64, val); >+} >+ >+// print number >+void printInt64(SStream *O, int64_t val) >+{ >+ if (val == LONG_MIN) { >+ return; >+ } >+ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, val); >+ else >+ SStream_concat(O, "%"PRIu64, val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -val); >+ else >+ SStream_concat(O, "-%"PRIu64, -val); >+ } >+} >+ >+// print number in decimal mode >+void printInt32BangDec(SStream *O, int32_t val) >+{ >+ if (val == INT_MIN) { >+ return; >+ } >+ >+ if (val >= 0) >+ SStream_concat(O, "#%u", val); >+ else >+ SStream_concat(O, "#-%u", -val); >+} >+ >+void printInt32Bang(SStream *O, int32_t val) >+{ >+ if (val == INT_MIN) { >+ return; >+ } >+ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", val); >+ else >+ SStream_concat(O, "#%u", val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%x", -val); >+ else >+ SStream_concat(O, "#-%u", -val); >+ } >+} >+ >+void printInt32(SStream *O, int32_t val) >+{ >+ if (val == INT_MIN) { >+ return; >+ } >+ >+ if (val >= 0) { >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", val); >+ else >+ SStream_concat(O, "%u", val); >+ } else { >+ if (val <- HEX_THRESHOLD) >+ SStream_concat(O, "-0x%x", -val); >+ else >+ SStream_concat(O, "-%u", -val); >+ } >+} >+ >+void printUInt32Bang(SStream *O, uint32_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", val); >+ else >+ SStream_concat(O, "#%u", val); >+} >+ >+void printUInt32(SStream *O, uint32_t val) >+{ >+ if (val > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", val); >+ else >+ SStream_concat(O, "%u", val); >+} >+ >+/* >+ int main() >+ { >+ SStream ss; >+ int64_t i; >+ >+ SStream_Init(&ss); >+ >+ SStream_concat(&ss, "hello "); >+ SStream_concat(&ss, "%d - 0x%x", 200, 16); >+ >+ i = 123; >+ SStream_concat(&ss, " + %ld", i); >+ SStream_concat(&ss, "%s", "haaaaa"); >+ >+ printf("%s\n", ss.buffer); >+ >+ return 0; >+ } >+ */ >diff --git a/Source/ThirdParty/capstone/Source/SStream.h b/Source/ThirdParty/capstone/Source/SStream.h >new file mode 100644 >index 0000000000000000000000000000000000000000..46f105188f0044eae4e09f6f423db1b98a54fb14 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/SStream.h >@@ -0,0 +1,35 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_SSTREAM_H_ >+#define CS_SSTREAM_H_ >+ >+typedef struct SStream { >+ char buffer[512]; >+ int index; >+} SStream; >+ >+void SStream_Init(SStream *ss); >+ >+void SStream_concat(SStream *ss, const char *fmt, ...); >+ >+void SStream_concat0(SStream *ss, const char *s); >+ >+void printInt64Bang(SStream *O, int64_t val); >+ >+void printUInt64Bang(SStream *O, uint64_t val); >+ >+void printInt64(SStream *O, int64_t val); >+ >+void printInt32Bang(SStream *O, int32_t val); >+ >+void printInt32(SStream *O, int32_t val); >+ >+void printUInt32Bang(SStream *O, uint32_t val); >+ >+void printUInt32(SStream *O, uint32_t val); >+ >+// print number in decimal mode >+void printInt32BangDec(SStream *O, int32_t val); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/TODO b/Source/ThirdParty/capstone/Source/TODO >new file mode 100644 >index 0000000000000000000000000000000000000000..e7117ee99a5a5b59fba09481e4a7af40cd55ecca >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/TODO >@@ -0,0 +1,16 @@ >+Issues to be solved in next versions >+ >+ >+[Core] >+ >+- X86 can already handle all the malware tricks we are aware of. If you find >+ any such instruction sequence that Capstone disassembles wrongly or fails >+ completely, please report. Fixing this issue is always the top priority of >+ our project. >+ >+- More optimization for better performance. >+ >+ >+[Bindings] >+ >+- OCaml binding is working, but still needs to support the core API better. >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64AddressingModes.h b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64AddressingModes.h >new file mode 100644 >index 0000000000000000000000000000000000000000..e162fda29afc6b76639d5ad1c91b689b65cd1601 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64AddressingModes.h >@@ -0,0 +1,225 @@ >+//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the AArch64 addressing mode implementation stuff. >+// >+//===----------------------------------------------------------------------===// >+ >+#ifndef CS_AARCH64_ADDRESSINGMODES_H >+#define CS_AARCH64_ADDRESSINGMODES_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */ >+ >+#include "../../MathExtras.h" >+ >+/// AArch64_AM - AArch64 Addressing Mode Stuff >+ >+//===----------------------------------------------------------------------===// >+// Shifts >+// >+ >+typedef enum AArch64_AM_ShiftExtendType { >+ AArch64_AM_InvalidShiftExtend = -1, >+ AArch64_AM_LSL = 0, >+ AArch64_AM_LSR, >+ AArch64_AM_ASR, >+ AArch64_AM_ROR, >+ AArch64_AM_MSL, >+ >+ AArch64_AM_UXTB, >+ AArch64_AM_UXTH, >+ AArch64_AM_UXTW, >+ AArch64_AM_UXTX, >+ >+ AArch64_AM_SXTB, >+ AArch64_AM_SXTH, >+ AArch64_AM_SXTW, >+ AArch64_AM_SXTX, >+} AArch64_AM_ShiftExtendType; >+ >+/// getShiftName - Get the string encoding for the shift type. >+static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST) >+{ >+ switch (ST) { >+ default: return NULL; // never reach >+ case AArch64_AM_LSL: return "lsl"; >+ case AArch64_AM_LSR: return "lsr"; >+ case AArch64_AM_ASR: return "asr"; >+ case AArch64_AM_ROR: return "ror"; >+ case AArch64_AM_MSL: return "msl"; >+ case AArch64_AM_UXTB: return "uxtb"; >+ case AArch64_AM_UXTH: return "uxth"; >+ case AArch64_AM_UXTW: return "uxtw"; >+ case AArch64_AM_UXTX: return "uxtx"; >+ case AArch64_AM_SXTB: return "sxtb"; >+ case AArch64_AM_SXTH: return "sxth"; >+ case AArch64_AM_SXTW: return "sxtw"; >+ case AArch64_AM_SXTX: return "sxtx"; >+ } >+} >+ >+/// getShiftType - Extract the shift type. >+static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) >+{ >+ switch ((Imm >> 6) & 0x7) { >+ default: return AArch64_AM_InvalidShiftExtend; >+ case 0: return AArch64_AM_LSL; >+ case 1: return AArch64_AM_LSR; >+ case 2: return AArch64_AM_ASR; >+ case 3: return AArch64_AM_ROR; >+ case 4: return AArch64_AM_MSL; >+ } >+} >+ >+/// getShiftValue - Extract the shift value. >+static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) >+{ >+ return Imm & 0x3f; >+} >+ >+//===----------------------------------------------------------------------===// >+// Extends >+// >+ >+/// getArithShiftValue - get the arithmetic shift value. >+static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) >+{ >+ return Imm & 0x7; >+} >+ >+/// getExtendType - Extract the extend type for operands of arithmetic ops. >+static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) >+{ >+ // assert((Imm & 0x7) == Imm && "invalid immediate!"); >+ switch (Imm) { >+ default: // llvm_unreachable("Compiler bug!"); >+ case 0: return AArch64_AM_UXTB; >+ case 1: return AArch64_AM_UXTH; >+ case 2: return AArch64_AM_UXTW; >+ case 3: return AArch64_AM_UXTX; >+ case 4: return AArch64_AM_SXTB; >+ case 5: return AArch64_AM_SXTH; >+ case 6: return AArch64_AM_SXTW; >+ case 7: return AArch64_AM_SXTX; >+ } >+} >+ >+static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm) >+{ >+ return AArch64_AM_getExtendType((Imm >> 3) & 0x7); >+} >+ >+static inline uint64_t ror(uint64_t elt, unsigned size) >+{ >+ return ((elt & 1) << (size-1)) | (elt >> 1); >+} >+ >+/// decodeLogicalImmediate - Decode a logical immediate value in the form >+/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the >+/// integer value it represents with regSize bits. >+static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize) >+{ >+ // Extract the N, imms, and immr fields. >+ unsigned N = (val >> 12) & 1; >+ unsigned immr = (val >> 6) & 0x3f; >+ unsigned imms = val & 0x3f; >+ unsigned i; >+ >+ // assert((regSize == 64 || N == 0) && "undefined logical immediate encoding"); >+ int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); >+ // assert(len >= 0 && "undefined logical immediate encoding"); >+ unsigned size = (1 << len); >+ unsigned R = immr & (size - 1); >+ unsigned S = imms & (size - 1); >+ // assert(S != size - 1 && "undefined logical immediate encoding"); >+ uint64_t pattern = (1ULL << (S + 1)) - 1; >+ for (i = 0; i < R; ++i) >+ pattern = ror(pattern, size); >+ >+ // Replicate the pattern to fill the regSize. >+ while (size != regSize) { >+ pattern |= (pattern << size); >+ size *= 2; >+ } >+ >+ return pattern; >+} >+ >+/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value >+/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) >+/// is a valid encoding for an integer value with regSize bits. >+static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize) >+{ >+ unsigned size; >+ unsigned S; >+ int len; >+ // Extract the N and imms fields needed for checking. >+ unsigned N = (val >> 12) & 1; >+ unsigned imms = val & 0x3f; >+ >+ if (regSize == 32 && N != 0) // undefined logical immediate encoding >+ return false; >+ len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); >+ if (len < 0) // undefined logical immediate encoding >+ return false; >+ size = (1 << len); >+ S = imms & (size - 1); >+ if (S == size - 1) // undefined logical immediate encoding >+ return false; >+ >+ return true; >+} >+ >+//===----------------------------------------------------------------------===// >+// Floating-point Immediates >+// >+static inline float AArch64_AM_getFPImmFloat(unsigned Imm) >+{ >+ // We expect an 8-bit binary encoding of a floating-point number here. >+ union { >+ uint32_t I; >+ float F; >+ } FPUnion; >+ >+ uint8_t Sign = (Imm >> 7) & 0x1; >+ uint8_t Exp = (Imm >> 4) & 0x7; >+ uint8_t Mantissa = Imm & 0xf; >+ >+ // 8-bit FP iEEEE Float Encoding >+ // abcd efgh aBbbbbbc defgh000 00000000 00000000 >+ // >+ // where B = NOT(b); >+ >+ FPUnion.I = 0; >+ FPUnion.I |= Sign << 31; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; >+ FPUnion.I |= (Exp & 0x3) << 23; >+ FPUnion.I |= Mantissa << 19; >+ >+ return FPUnion.F; >+} >+ >+//===--------------------------------------------------------------------===// >+// AdvSIMD Modified Immediates >+//===--------------------------------------------------------------------===// >+ >+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) >+{ >+ static const uint32_t lookup[16] = { >+ 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, >+ 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, >+ 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, >+ 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff >+ }; >+ return lookup[Imm & 0x0f] | ((uint64_t)lookup[Imm >> 4] << 32); >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.c b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.c >new file mode 100644 >index 0000000000000000000000000000000000000000..255ef31bce0623dba405a610592e9b1d4e6743d0 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.c >@@ -0,0 +1,999 @@ >+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file provides basic encoding and assembly information for AArch64. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM64 >+ >+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) >+#pragma warning(disable:4996) // disable MSVC's warning on strcpy() >+#pragma warning(disable:28719) // disable MSVC's warning on strcpy() >+#endif >+ >+#include "../../utils.h" >+ >+#include <stdio.h> >+#include <stdlib.h> >+ >+#include "AArch64BaseInfo.h" >+ >+const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid) >+{ >+ unsigned i; >+ for (i = 0; i < N->NumPairs; ++i) { >+ if (N->Pairs[i].Value == Value) { >+ *Valid = true; >+ return N->Pairs[i].Name; >+ } >+ } >+ >+ *Valid = false; >+ return 0; >+} >+ >+// compare s1 with lower(s2) >+// return true if s1 == lower(f2), and false otherwise >+static bool compare_lower_str(const char *s1, const char *s2) >+{ >+ bool res; >+ char *lower = cs_strdup(s2), *c; >+ for (c = lower; *c; c++) >+ *c = (char)tolower((int) *c); >+ >+ res = (strcmp(s1, lower) == 0); >+ cs_mem_free(lower); >+ >+ return res; >+} >+ >+uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid) >+{ >+ unsigned i; >+ for (i = 0; i < N->NumPairs; ++i) { >+ if (compare_lower_str(N->Pairs[i].Name, Name)) { >+ *Valid = true; >+ return N->Pairs[i].Value; >+ } >+ } >+ >+ *Valid = false; >+ return (uint32_t)-1; >+} >+ >+bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value) >+{ >+ return Value < N->TooBigImm; >+} >+ >+// return a string representing the number X >+// NOTE: caller must free() the result itself to avoid memory leak >+static char *utostr(uint64_t X, bool isNeg) >+{ >+ char Buffer[22]; >+ char *BufPtr = Buffer+21; >+ char *result; >+ >+ Buffer[21] = '\0'; >+ if (X == 0) *--BufPtr = '0'; // Handle special case... >+ >+ while (X) { >+ *--BufPtr = X % 10 + '0'; >+ X /= 10; >+ } >+ >+ if (isNeg) *--BufPtr = '-'; // Add negative sign... >+ >+ result = cs_strdup(BufPtr); >+ return result; >+} >+ >+static const A64NamedImmMapper_Mapping SysRegPairs[] = { >+ {"pan", A64SysReg_PAN}, >+ {"uao", A64SysReg_UAO}, >+ {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1}, >+ {"osdtrtx_el1", A64SysReg_OSDTRTX_EL1}, >+ {"teecr32_el1", A64SysReg_TEECR32_EL1}, >+ {"mdccint_el1", A64SysReg_MDCCINT_EL1}, >+ {"mdscr_el1", A64SysReg_MDSCR_EL1}, >+ {"dbgdtr_el0", A64SysReg_DBGDTR_EL0}, >+ {"oseccr_el1", A64SysReg_OSECCR_EL1}, >+ {"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2}, >+ {"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1}, >+ {"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1}, >+ {"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1}, >+ {"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1}, >+ {"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1}, >+ {"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1}, >+ {"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1}, >+ {"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1}, >+ {"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1}, >+ {"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1}, >+ {"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1}, >+ {"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1}, >+ {"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1}, >+ {"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1}, >+ {"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1}, >+ {"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1}, >+ {"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1}, >+ {"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1}, >+ {"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1}, >+ {"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1}, >+ {"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1}, >+ {"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1}, >+ {"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1}, >+ {"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1}, >+ {"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1}, >+ {"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1}, >+ {"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1}, >+ {"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1}, >+ {"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1}, >+ {"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1}, >+ {"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1}, >+ {"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1}, >+ {"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1}, >+ {"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1}, >+ {"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1}, >+ {"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1}, >+ {"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1}, >+ {"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1}, >+ {"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1}, >+ {"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1}, >+ {"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1}, >+ {"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1}, >+ {"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1}, >+ {"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1}, >+ {"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1}, >+ {"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1}, >+ {"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1}, >+ {"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1}, >+ {"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1}, >+ {"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1}, >+ {"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1}, >+ {"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1}, >+ {"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1}, >+ {"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1}, >+ {"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1}, >+ {"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1}, >+ {"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1}, >+ {"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1}, >+ {"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1}, >+ {"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1}, >+ {"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1}, >+ {"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1}, >+ {"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1}, >+ {"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1}, >+ {"teehbr32_el1", A64SysReg_TEEHBR32_EL1}, >+ {"osdlr_el1", A64SysReg_OSDLR_EL1}, >+ {"dbgprcr_el1", A64SysReg_DBGPRCR_EL1}, >+ {"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1}, >+ {"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1}, >+ {"csselr_el1", A64SysReg_CSSELR_EL1}, >+ {"vpidr_el2", A64SysReg_VPIDR_EL2}, >+ {"vmpidr_el2", A64SysReg_VMPIDR_EL2}, >+ {"sctlr_el1", A64SysReg_SCTLR_EL1}, >+ {"sctlr_el12", A64SysReg_SCTLR_EL12}, >+ {"sctlr_el2", A64SysReg_SCTLR_EL2}, >+ {"sctlr_el3", A64SysReg_SCTLR_EL3}, >+ {"actlr_el1", A64SysReg_ACTLR_EL1}, >+ {"actlr_el2", A64SysReg_ACTLR_EL2}, >+ {"actlr_el3", A64SysReg_ACTLR_EL3}, >+ {"cpacr_el1", A64SysReg_CPACR_EL1}, >+ {"cpacr_el12", A64SysReg_CPACR_EL12}, >+ {"hcr_el2", A64SysReg_HCR_EL2}, >+ {"scr_el3", A64SysReg_SCR_EL3}, >+ {"mdcr_el2", A64SysReg_MDCR_EL2}, >+ {"sder32_el3", A64SysReg_SDER32_EL3}, >+ {"cptr_el2", A64SysReg_CPTR_EL2}, >+ {"cptr_el3", A64SysReg_CPTR_EL3}, >+ {"hstr_el2", A64SysReg_HSTR_EL2}, >+ {"hacr_el2", A64SysReg_HACR_EL2}, >+ {"mdcr_el3", A64SysReg_MDCR_EL3}, >+ {"ttbr0_el1", A64SysReg_TTBR0_EL1}, >+ {"ttbr0_el12", A64SysReg_TTBR0_EL12}, >+ {"ttbr0_el2", A64SysReg_TTBR0_EL2}, >+ {"ttbr0_el3", A64SysReg_TTBR0_EL3}, >+ {"ttbr1_el1", A64SysReg_TTBR1_EL1}, >+ {"ttbr1_el12", A64SysReg_TTBR1_EL12}, >+ {"ttbr1_el2", A64SysReg_TTBR1_EL2}, >+ {"tcr_el1", A64SysReg_TCR_EL1}, >+ {"tcr_el12", A64SysReg_TCR_EL12}, >+ {"tcr_el2", A64SysReg_TCR_EL2}, >+ {"tcr_el3", A64SysReg_TCR_EL3}, >+ {"vttbr_el2", A64SysReg_VTTBR_EL2}, >+ {"vtcr_el2", A64SysReg_VTCR_EL2}, >+ {"dacr32_el2", A64SysReg_DACR32_EL2}, >+ {"spsr_el1", A64SysReg_SPSR_EL1}, >+ {"spsr_el12", A64SysReg_SPSR_EL12}, >+ {"spsr_el2", A64SysReg_SPSR_EL2}, >+ {"spsr_el3", A64SysReg_SPSR_EL3}, >+ {"elr_el1", A64SysReg_ELR_EL1}, >+ {"elr_el12", A64SysReg_ELR_EL12}, >+ {"elr_el2", A64SysReg_ELR_EL2}, >+ {"elr_el3", A64SysReg_ELR_EL3}, >+ {"sp_el0", A64SysReg_SP_EL0}, >+ {"sp_el1", A64SysReg_SP_EL1}, >+ {"sp_el2", A64SysReg_SP_EL2}, >+ {"spsel", A64SysReg_SPSel}, >+ {"nzcv", A64SysReg_NZCV}, >+ {"daif", A64SysReg_DAIF}, >+ {"currentel", A64SysReg_CurrentEL}, >+ {"spsr_irq", A64SysReg_SPSR_irq}, >+ {"spsr_abt", A64SysReg_SPSR_abt}, >+ {"spsr_und", A64SysReg_SPSR_und}, >+ {"spsr_fiq", A64SysReg_SPSR_fiq}, >+ {"fpcr", A64SysReg_FPCR}, >+ {"fpsr", A64SysReg_FPSR}, >+ {"dspsr_el0", A64SysReg_DSPSR_EL0}, >+ {"dlr_el0", A64SysReg_DLR_EL0}, >+ {"ifsr32_el2", A64SysReg_IFSR32_EL2}, >+ {"afsr0_el1", A64SysReg_AFSR0_EL1}, >+ {"afsr0_el12", A64SysReg_AFSR0_EL12}, >+ {"afsr0_el2", A64SysReg_AFSR0_EL2}, >+ {"afsr0_el3", A64SysReg_AFSR0_EL3}, >+ {"afsr1_el1", A64SysReg_AFSR1_EL1}, >+ {"afsr1_el12", A64SysReg_AFSR1_EL12}, >+ {"afsr1_el2", A64SysReg_AFSR1_EL2}, >+ {"afsr1_el3", A64SysReg_AFSR1_EL3}, >+ {"esr_el1", A64SysReg_ESR_EL1}, >+ {"esr_el12", A64SysReg_ESR_EL12}, >+ {"esr_el2", A64SysReg_ESR_EL2}, >+ {"esr_el3", A64SysReg_ESR_EL3}, >+ {"fpexc32_el2", A64SysReg_FPEXC32_EL2}, >+ {"far_el1", A64SysReg_FAR_EL1}, >+ {"far_el12", A64SysReg_FAR_EL12}, >+ {"far_el2", A64SysReg_FAR_EL2}, >+ {"far_el3", A64SysReg_FAR_EL3}, >+ {"hpfar_el2", A64SysReg_HPFAR_EL2}, >+ {"par_el1", A64SysReg_PAR_EL1}, >+ {"pmcr_el0", A64SysReg_PMCR_EL0}, >+ {"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0}, >+ {"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0}, >+ {"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0}, >+ {"pmselr_el0", A64SysReg_PMSELR_EL0}, >+ {"pmccntr_el0", A64SysReg_PMCCNTR_EL0}, >+ {"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0}, >+ {"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0}, >+ {"pmuserenr_el0", A64SysReg_PMUSERENR_EL0}, >+ {"pmintenset_el1", A64SysReg_PMINTENSET_EL1}, >+ {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1}, >+ {"pmovsset_el0", A64SysReg_PMOVSSET_EL0}, >+ {"mair_el1", A64SysReg_MAIR_EL1}, >+ {"mair_el12", A64SysReg_MAIR_EL12}, >+ {"mair_el2", A64SysReg_MAIR_EL2}, >+ {"mair_el3", A64SysReg_MAIR_EL3}, >+ {"amair_el1", A64SysReg_AMAIR_EL1}, >+ {"amair_el12", A64SysReg_AMAIR_EL12}, >+ {"amair_el2", A64SysReg_AMAIR_EL2}, >+ {"amair_el3", A64SysReg_AMAIR_EL3}, >+ {"vbar_el1", A64SysReg_VBAR_EL1}, >+ {"vbar_el12", A64SysReg_VBAR_EL12}, >+ {"vbar_el2", A64SysReg_VBAR_EL2}, >+ {"vbar_el3", A64SysReg_VBAR_EL3}, >+ {"rmr_el1", A64SysReg_RMR_EL1}, >+ {"rmr_el2", A64SysReg_RMR_EL2}, >+ {"rmr_el3", A64SysReg_RMR_EL3}, >+ {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1}, >+ {"contextidr_el12", A64SysReg_CONTEXTIDR_EL12}, >+ {"contextidr_el2", A64SysReg_CONTEXTIDR_EL2}, >+ {"tpidr_el0", A64SysReg_TPIDR_EL0}, >+ {"tpidr_el2", A64SysReg_TPIDR_EL2}, >+ {"tpidr_el3", A64SysReg_TPIDR_EL3}, >+ {"tpidrro_el0", A64SysReg_TPIDRRO_EL0}, >+ {"tpidr_el1", A64SysReg_TPIDR_EL1}, >+ {"cntfrq_el0", A64SysReg_CNTFRQ_EL0}, >+ {"cntvoff_el2", A64SysReg_CNTVOFF_EL2}, >+ {"cntkctl_el1", A64SysReg_CNTKCTL_EL1}, >+ {"cntkctl_el12", A64SysReg_CNTKCTL_EL12}, >+ {"cnthctl_el2", A64SysReg_CNTHCTL_EL2}, >+ {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0}, >+ {"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02}, >+ {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2}, >+ {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1}, >+ {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0}, >+ {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2}, >+ {"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2}, >+ {"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2}, >+ {"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2}, >+ {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1}, >+ {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0}, >+ {"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02}, >+ {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2}, >+ {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1}, >+ {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0}, >+ {"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02}, >+ {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0}, >+ {"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02}, >+ {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0}, >+ {"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02}, >+ {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0}, >+ {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0}, >+ {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0}, >+ {"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0}, >+ {"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0}, >+ {"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0}, >+ {"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0}, >+ {"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0}, >+ {"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0}, >+ {"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0}, >+ {"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0}, >+ {"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0}, >+ {"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0}, >+ {"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0}, >+ {"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0}, >+ {"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0}, >+ {"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0}, >+ {"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0}, >+ {"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0}, >+ {"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0}, >+ {"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0}, >+ {"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0}, >+ {"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0}, >+ {"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0}, >+ {"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0}, >+ {"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0}, >+ {"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0}, >+ {"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0}, >+ {"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0}, >+ {"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0}, >+ {"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0}, >+ {"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0}, >+ {"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0}, >+ {"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0}, >+ {"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0}, >+ {"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0}, >+ {"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0}, >+ {"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0}, >+ {"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0}, >+ {"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0}, >+ {"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0}, >+ {"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0}, >+ {"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0}, >+ {"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0}, >+ {"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0}, >+ {"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0}, >+ {"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0}, >+ {"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0}, >+ {"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0}, >+ {"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0}, >+ {"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0}, >+ {"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0}, >+ {"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0}, >+ {"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0}, >+ {"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0}, >+ {"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0}, >+ {"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0}, >+ {"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0}, >+ {"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0}, >+ {"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0}, >+ {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0}, >+ {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0}, >+ {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0}, >+ {"lorc_el1", A64SysReg_LORC_EL1}, >+ {"lorea_el1", A64SysReg_LOREA_EL1}, >+ {"lorn_el1", A64SysReg_LORN_EL1}, >+ {"lorsa_el1", A64SysReg_LORSA_EL1}, >+ >+ // Trace registers >+ {"trcprgctlr", A64SysReg_TRCPRGCTLR}, >+ {"trcprocselr", A64SysReg_TRCPROCSELR}, >+ {"trcconfigr", A64SysReg_TRCCONFIGR}, >+ {"trcauxctlr", A64SysReg_TRCAUXCTLR}, >+ {"trceventctl0r", A64SysReg_TRCEVENTCTL0R}, >+ {"trceventctl1r", A64SysReg_TRCEVENTCTL1R}, >+ {"trcstallctlr", A64SysReg_TRCSTALLCTLR}, >+ {"trctsctlr", A64SysReg_TRCTSCTLR}, >+ {"trcsyncpr", A64SysReg_TRCSYNCPR}, >+ {"trcccctlr", A64SysReg_TRCCCCTLR}, >+ {"trcbbctlr", A64SysReg_TRCBBCTLR}, >+ {"trctraceidr", A64SysReg_TRCTRACEIDR}, >+ {"trcqctlr", A64SysReg_TRCQCTLR}, >+ {"trcvictlr", A64SysReg_TRCVICTLR}, >+ {"trcviiectlr", A64SysReg_TRCVIIECTLR}, >+ {"trcvissctlr", A64SysReg_TRCVISSCTLR}, >+ {"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR}, >+ {"trcvdctlr", A64SysReg_TRCVDCTLR}, >+ {"trcvdsacctlr", A64SysReg_TRCVDSACCTLR}, >+ {"trcvdarcctlr", A64SysReg_TRCVDARCCTLR}, >+ {"trcseqevr0", A64SysReg_TRCSEQEVR0}, >+ {"trcseqevr1", A64SysReg_TRCSEQEVR1}, >+ {"trcseqevr2", A64SysReg_TRCSEQEVR2}, >+ {"trcseqrstevr", A64SysReg_TRCSEQRSTEVR}, >+ {"trcseqstr", A64SysReg_TRCSEQSTR}, >+ {"trcextinselr", A64SysReg_TRCEXTINSELR}, >+ {"trccntrldvr0", A64SysReg_TRCCNTRLDVR0}, >+ {"trccntrldvr1", A64SysReg_TRCCNTRLDVR1}, >+ {"trccntrldvr2", A64SysReg_TRCCNTRLDVR2}, >+ {"trccntrldvr3", A64SysReg_TRCCNTRLDVR3}, >+ {"trccntctlr0", A64SysReg_TRCCNTCTLR0}, >+ {"trccntctlr1", A64SysReg_TRCCNTCTLR1}, >+ {"trccntctlr2", A64SysReg_TRCCNTCTLR2}, >+ {"trccntctlr3", A64SysReg_TRCCNTCTLR3}, >+ {"trccntvr0", A64SysReg_TRCCNTVR0}, >+ {"trccntvr1", A64SysReg_TRCCNTVR1}, >+ {"trccntvr2", A64SysReg_TRCCNTVR2}, >+ {"trccntvr3", A64SysReg_TRCCNTVR3}, >+ {"trcimspec0", A64SysReg_TRCIMSPEC0}, >+ {"trcimspec1", A64SysReg_TRCIMSPEC1}, >+ {"trcimspec2", A64SysReg_TRCIMSPEC2}, >+ {"trcimspec3", A64SysReg_TRCIMSPEC3}, >+ {"trcimspec4", A64SysReg_TRCIMSPEC4}, >+ {"trcimspec5", A64SysReg_TRCIMSPEC5}, >+ {"trcimspec6", A64SysReg_TRCIMSPEC6}, >+ {"trcimspec7", A64SysReg_TRCIMSPEC7}, >+ {"trcrsctlr2", A64SysReg_TRCRSCTLR2}, >+ {"trcrsctlr3", A64SysReg_TRCRSCTLR3}, >+ {"trcrsctlr4", A64SysReg_TRCRSCTLR4}, >+ {"trcrsctlr5", A64SysReg_TRCRSCTLR5}, >+ {"trcrsctlr6", A64SysReg_TRCRSCTLR6}, >+ {"trcrsctlr7", A64SysReg_TRCRSCTLR7}, >+ {"trcrsctlr8", A64SysReg_TRCRSCTLR8}, >+ {"trcrsctlr9", A64SysReg_TRCRSCTLR9}, >+ {"trcrsctlr10", A64SysReg_TRCRSCTLR10}, >+ {"trcrsctlr11", A64SysReg_TRCRSCTLR11}, >+ {"trcrsctlr12", A64SysReg_TRCRSCTLR12}, >+ {"trcrsctlr13", A64SysReg_TRCRSCTLR13}, >+ {"trcrsctlr14", A64SysReg_TRCRSCTLR14}, >+ {"trcrsctlr15", A64SysReg_TRCRSCTLR15}, >+ {"trcrsctlr16", A64SysReg_TRCRSCTLR16}, >+ {"trcrsctlr17", A64SysReg_TRCRSCTLR17}, >+ {"trcrsctlr18", A64SysReg_TRCRSCTLR18}, >+ {"trcrsctlr19", A64SysReg_TRCRSCTLR19}, >+ {"trcrsctlr20", A64SysReg_TRCRSCTLR20}, >+ {"trcrsctlr21", A64SysReg_TRCRSCTLR21}, >+ {"trcrsctlr22", A64SysReg_TRCRSCTLR22}, >+ {"trcrsctlr23", A64SysReg_TRCRSCTLR23}, >+ {"trcrsctlr24", A64SysReg_TRCRSCTLR24}, >+ {"trcrsctlr25", A64SysReg_TRCRSCTLR25}, >+ {"trcrsctlr26", A64SysReg_TRCRSCTLR26}, >+ {"trcrsctlr27", A64SysReg_TRCRSCTLR27}, >+ {"trcrsctlr28", A64SysReg_TRCRSCTLR28}, >+ {"trcrsctlr29", A64SysReg_TRCRSCTLR29}, >+ {"trcrsctlr30", A64SysReg_TRCRSCTLR30}, >+ {"trcrsctlr31", A64SysReg_TRCRSCTLR31}, >+ {"trcssccr0", A64SysReg_TRCSSCCR0}, >+ {"trcssccr1", A64SysReg_TRCSSCCR1}, >+ {"trcssccr2", A64SysReg_TRCSSCCR2}, >+ {"trcssccr3", A64SysReg_TRCSSCCR3}, >+ {"trcssccr4", A64SysReg_TRCSSCCR4}, >+ {"trcssccr5", A64SysReg_TRCSSCCR5}, >+ {"trcssccr6", A64SysReg_TRCSSCCR6}, >+ {"trcssccr7", A64SysReg_TRCSSCCR7}, >+ {"trcsscsr0", A64SysReg_TRCSSCSR0}, >+ {"trcsscsr1", A64SysReg_TRCSSCSR1}, >+ {"trcsscsr2", A64SysReg_TRCSSCSR2}, >+ {"trcsscsr3", A64SysReg_TRCSSCSR3}, >+ {"trcsscsr4", A64SysReg_TRCSSCSR4}, >+ {"trcsscsr5", A64SysReg_TRCSSCSR5}, >+ {"trcsscsr6", A64SysReg_TRCSSCSR6}, >+ {"trcsscsr7", A64SysReg_TRCSSCSR7}, >+ {"trcsspcicr0", A64SysReg_TRCSSPCICR0}, >+ {"trcsspcicr1", A64SysReg_TRCSSPCICR1}, >+ {"trcsspcicr2", A64SysReg_TRCSSPCICR2}, >+ {"trcsspcicr3", A64SysReg_TRCSSPCICR3}, >+ {"trcsspcicr4", A64SysReg_TRCSSPCICR4}, >+ {"trcsspcicr5", A64SysReg_TRCSSPCICR5}, >+ {"trcsspcicr6", A64SysReg_TRCSSPCICR6}, >+ {"trcsspcicr7", A64SysReg_TRCSSPCICR7}, >+ {"trcpdcr", A64SysReg_TRCPDCR}, >+ {"trcacvr0", A64SysReg_TRCACVR0}, >+ {"trcacvr1", A64SysReg_TRCACVR1}, >+ {"trcacvr2", A64SysReg_TRCACVR2}, >+ {"trcacvr3", A64SysReg_TRCACVR3}, >+ {"trcacvr4", A64SysReg_TRCACVR4}, >+ {"trcacvr5", A64SysReg_TRCACVR5}, >+ {"trcacvr6", A64SysReg_TRCACVR6}, >+ {"trcacvr7", A64SysReg_TRCACVR7}, >+ {"trcacvr8", A64SysReg_TRCACVR8}, >+ {"trcacvr9", A64SysReg_TRCACVR9}, >+ {"trcacvr10", A64SysReg_TRCACVR10}, >+ {"trcacvr11", A64SysReg_TRCACVR11}, >+ {"trcacvr12", A64SysReg_TRCACVR12}, >+ {"trcacvr13", A64SysReg_TRCACVR13}, >+ {"trcacvr14", A64SysReg_TRCACVR14}, >+ {"trcacvr15", A64SysReg_TRCACVR15}, >+ {"trcacatr0", A64SysReg_TRCACATR0}, >+ {"trcacatr1", A64SysReg_TRCACATR1}, >+ {"trcacatr2", A64SysReg_TRCACATR2}, >+ {"trcacatr3", A64SysReg_TRCACATR3}, >+ {"trcacatr4", A64SysReg_TRCACATR4}, >+ {"trcacatr5", A64SysReg_TRCACATR5}, >+ {"trcacatr6", A64SysReg_TRCACATR6}, >+ {"trcacatr7", A64SysReg_TRCACATR7}, >+ {"trcacatr8", A64SysReg_TRCACATR8}, >+ {"trcacatr9", A64SysReg_TRCACATR9}, >+ {"trcacatr10", A64SysReg_TRCACATR10}, >+ {"trcacatr11", A64SysReg_TRCACATR11}, >+ {"trcacatr12", A64SysReg_TRCACATR12}, >+ {"trcacatr13", A64SysReg_TRCACATR13}, >+ {"trcacatr14", A64SysReg_TRCACATR14}, >+ {"trcacatr15", A64SysReg_TRCACATR15}, >+ {"trcdvcvr0", A64SysReg_TRCDVCVR0}, >+ {"trcdvcvr1", A64SysReg_TRCDVCVR1}, >+ {"trcdvcvr2", A64SysReg_TRCDVCVR2}, >+ {"trcdvcvr3", A64SysReg_TRCDVCVR3}, >+ {"trcdvcvr4", A64SysReg_TRCDVCVR4}, >+ {"trcdvcvr5", A64SysReg_TRCDVCVR5}, >+ {"trcdvcvr6", A64SysReg_TRCDVCVR6}, >+ {"trcdvcvr7", A64SysReg_TRCDVCVR7}, >+ {"trcdvcmr0", A64SysReg_TRCDVCMR0}, >+ {"trcdvcmr1", A64SysReg_TRCDVCMR1}, >+ {"trcdvcmr2", A64SysReg_TRCDVCMR2}, >+ {"trcdvcmr3", A64SysReg_TRCDVCMR3}, >+ {"trcdvcmr4", A64SysReg_TRCDVCMR4}, >+ {"trcdvcmr5", A64SysReg_TRCDVCMR5}, >+ {"trcdvcmr6", A64SysReg_TRCDVCMR6}, >+ {"trcdvcmr7", A64SysReg_TRCDVCMR7}, >+ {"trccidcvr0", A64SysReg_TRCCIDCVR0}, >+ {"trccidcvr1", A64SysReg_TRCCIDCVR1}, >+ {"trccidcvr2", A64SysReg_TRCCIDCVR2}, >+ {"trccidcvr3", A64SysReg_TRCCIDCVR3}, >+ {"trccidcvr4", A64SysReg_TRCCIDCVR4}, >+ {"trccidcvr5", A64SysReg_TRCCIDCVR5}, >+ {"trccidcvr6", A64SysReg_TRCCIDCVR6}, >+ {"trccidcvr7", A64SysReg_TRCCIDCVR7}, >+ {"trcvmidcvr0", A64SysReg_TRCVMIDCVR0}, >+ {"trcvmidcvr1", A64SysReg_TRCVMIDCVR1}, >+ {"trcvmidcvr2", A64SysReg_TRCVMIDCVR2}, >+ {"trcvmidcvr3", A64SysReg_TRCVMIDCVR3}, >+ {"trcvmidcvr4", A64SysReg_TRCVMIDCVR4}, >+ {"trcvmidcvr5", A64SysReg_TRCVMIDCVR5}, >+ {"trcvmidcvr6", A64SysReg_TRCVMIDCVR6}, >+ {"trcvmidcvr7", A64SysReg_TRCVMIDCVR7}, >+ {"trccidcctlr0", A64SysReg_TRCCIDCCTLR0}, >+ {"trccidcctlr1", A64SysReg_TRCCIDCCTLR1}, >+ {"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0}, >+ {"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1}, >+ {"trcitctrl", A64SysReg_TRCITCTRL}, >+ {"trcclaimset", A64SysReg_TRCCLAIMSET}, >+ {"trcclaimclr", A64SysReg_TRCCLAIMCLR}, >+ >+ // GICv3 registers >+ {"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1}, >+ {"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1}, >+ {"icc_pmr_el1", A64SysReg_ICC_PMR_EL1}, >+ {"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1}, >+ {"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3}, >+ {"icc_sre_el1", A64SysReg_ICC_SRE_EL1}, >+ {"icc_sre_el2", A64SysReg_ICC_SRE_EL2}, >+ {"icc_sre_el3", A64SysReg_ICC_SRE_EL3}, >+ {"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1}, >+ {"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1}, >+ {"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3}, >+ {"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1}, >+ {"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1}, >+ {"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1}, >+ {"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1}, >+ {"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1}, >+ {"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1}, >+ {"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1}, >+ {"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1}, >+ {"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1}, >+ {"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2}, >+ {"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2}, >+ {"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2}, >+ {"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2}, >+ {"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2}, >+ {"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2}, >+ {"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2}, >+ {"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2}, >+ {"ich_hcr_el2", A64SysReg_ICH_HCR_EL2}, >+ {"ich_misr_el2", A64SysReg_ICH_MISR_EL2}, >+ {"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2}, >+ {"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2}, >+ {"ich_lr0_el2", A64SysReg_ICH_LR0_EL2}, >+ {"ich_lr1_el2", A64SysReg_ICH_LR1_EL2}, >+ {"ich_lr2_el2", A64SysReg_ICH_LR2_EL2}, >+ {"ich_lr3_el2", A64SysReg_ICH_LR3_EL2}, >+ {"ich_lr4_el2", A64SysReg_ICH_LR4_EL2}, >+ {"ich_lr5_el2", A64SysReg_ICH_LR5_EL2}, >+ {"ich_lr6_el2", A64SysReg_ICH_LR6_EL2}, >+ {"ich_lr7_el2", A64SysReg_ICH_LR7_EL2}, >+ {"ich_lr8_el2", A64SysReg_ICH_LR8_EL2}, >+ {"ich_lr9_el2", A64SysReg_ICH_LR9_EL2}, >+ {"ich_lr10_el2", A64SysReg_ICH_LR10_EL2}, >+ {"ich_lr11_el2", A64SysReg_ICH_LR11_EL2}, >+ {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2}, >+ {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2}, >+ {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2}, >+ {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2}, >+ >+ // Statistical profiling registers >+ {"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1}, >+ {"pmbptr_el1", A64SysReg_PMBPTR_EL1}, >+ {"pmbsr_el1", A64SysReg_PMBSR_EL1}, >+ {"pmscr_el1", A64SysReg_PMSCR_EL1}, >+ {"pmscr_el12", A64SysReg_PMSCR_EL12}, >+ {"pmscr_el2", A64SysReg_PMSCR_EL2}, >+ {"pmsicr_el1", A64SysReg_PMSICR_EL1}, >+ {"pmsirr_el1", A64SysReg_PMSIRR_EL1}, >+ {"pmsfcr_el1", A64SysReg_PMSFCR_EL1}, >+ {"pmsevfr_el1", A64SysReg_PMSEVFR_EL1}, >+ {"pmslatfr_el1", A64SysReg_PMSLATFR_EL1} >+}; >+ >+static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = { >+ {"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3} >+}; >+ >+// result must be a big enough buffer: 128 bytes is more than enough >+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result) >+{ >+ int dummy; >+ uint32_t Op0, Op1, CRn, CRm, Op2; >+ char *Op1S, *CRnS, *CRmS, *Op2S; >+ unsigned i; >+ >+ // First search the registers shared by all >+ for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) { >+ if (SysRegPairs[i].Value == Bits) { >+ *Valid = true; >+ strcpy(result, SysRegPairs[i].Name); >+ return; >+ } >+ } >+ >+ // Next search for target specific registers >+ // if (FeatureBits & AArch64_ProcCyclone) { >+ if (true) { >+ for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) { >+ if (CycloneSysRegPairs[i].Value == Bits) { >+ *Valid = true; >+ strcpy(result, CycloneSysRegPairs[i].Name); >+ return; >+ } >+ } >+ } >+ >+ // Now try the instruction-specific registers (either read-only or >+ // write-only). >+ for (i = 0; i < S->NumInstPairs; ++i) { >+ if (S->InstPairs[i].Value == Bits) { >+ *Valid = true; >+ strcpy(result, S->InstPairs[i].Name); >+ return; >+ } >+ } >+ >+ Op0 = (Bits >> 14) & 0x3; >+ Op1 = (Bits >> 11) & 0x7; >+ CRn = (Bits >> 7) & 0xf; >+ CRm = (Bits >> 3) & 0xf; >+ Op2 = Bits & 0x7; >+ >+ // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic >+ // name. >+ if (Op0 != 3 || (CRn != 11 && CRn != 15)) { >+ *Valid = false; >+ return; >+ } >+ >+ //assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg"); >+ >+ *Valid = true; >+ >+ Op1S = utostr(Op1, false); >+ CRnS = utostr(CRn, false); >+ CRmS = utostr(CRm, false); >+ Op2S = utostr(Op2, false); >+ >+ //printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S); >+ dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S); >+ (void)dummy; >+ >+ cs_mem_free(Op1S); >+ cs_mem_free(CRnS); >+ cs_mem_free(CRmS); >+ cs_mem_free(Op2S); >+} >+ >+static const A64NamedImmMapper_Mapping TLBIPairs[] = { >+ {"ipas2e1is", A64TLBI_IPAS2E1IS}, >+ {"ipas2le1is", A64TLBI_IPAS2LE1IS}, >+ {"vmalle1is", A64TLBI_VMALLE1IS}, >+ {"alle2is", A64TLBI_ALLE2IS}, >+ {"alle3is", A64TLBI_ALLE3IS}, >+ {"vae1is", A64TLBI_VAE1IS}, >+ {"vae2is", A64TLBI_VAE2IS}, >+ {"vae3is", A64TLBI_VAE3IS}, >+ {"aside1is", A64TLBI_ASIDE1IS}, >+ {"vaae1is", A64TLBI_VAAE1IS}, >+ {"alle1is", A64TLBI_ALLE1IS}, >+ {"vale1is", A64TLBI_VALE1IS}, >+ {"vale2is", A64TLBI_VALE2IS}, >+ {"vale3is", A64TLBI_VALE3IS}, >+ {"vmalls12e1is", A64TLBI_VMALLS12E1IS}, >+ {"vaale1is", A64TLBI_VAALE1IS}, >+ {"ipas2e1", A64TLBI_IPAS2E1}, >+ {"ipas2le1", A64TLBI_IPAS2LE1}, >+ {"vmalle1", A64TLBI_VMALLE1}, >+ {"alle2", A64TLBI_ALLE2}, >+ {"alle3", A64TLBI_ALLE3}, >+ {"vae1", A64TLBI_VAE1}, >+ {"vae2", A64TLBI_VAE2}, >+ {"vae3", A64TLBI_VAE3}, >+ {"aside1", A64TLBI_ASIDE1}, >+ {"vaae1", A64TLBI_VAAE1}, >+ {"alle1", A64TLBI_ALLE1}, >+ {"vale1", A64TLBI_VALE1}, >+ {"vale2", A64TLBI_VALE2}, >+ {"vale3", A64TLBI_VALE3}, >+ {"vmalls12e1", A64TLBI_VMALLS12E1}, >+ {"vaale1", A64TLBI_VAALE1} >+}; >+ >+const A64NamedImmMapper A64TLBI_TLBIMapper = { >+ TLBIPairs, >+ ARR_SIZE(TLBIPairs), >+ 0, >+}; >+ >+static const A64NamedImmMapper_Mapping ATPairs[] = { >+ {"s1e1r", A64AT_S1E1R}, >+ {"s1e2r", A64AT_S1E2R}, >+ {"s1e3r", A64AT_S1E3R}, >+ {"s1e1w", A64AT_S1E1W}, >+ {"s1e2w", A64AT_S1E2W}, >+ {"s1e3w", A64AT_S1E3W}, >+ {"s1e0r", A64AT_S1E0R}, >+ {"s1e0w", A64AT_S1E0W}, >+ {"s12e1r", A64AT_S12E1R}, >+ {"s12e1w", A64AT_S12E1W}, >+ {"s12e0r", A64AT_S12E0R}, >+ {"s12e0w", A64AT_S12E0W} >+}; >+ >+const A64NamedImmMapper A64AT_ATMapper = { >+ ATPairs, >+ ARR_SIZE(ATPairs), >+ 0, >+}; >+ >+static const A64NamedImmMapper_Mapping DBarrierPairs[] = { >+ {"oshld", A64DB_OSHLD}, >+ {"oshst", A64DB_OSHST}, >+ {"osh", A64DB_OSH}, >+ {"nshld", A64DB_NSHLD}, >+ {"nshst", A64DB_NSHST}, >+ {"nsh", A64DB_NSH}, >+ {"ishld", A64DB_ISHLD}, >+ {"ishst", A64DB_ISHST}, >+ {"ish", A64DB_ISH}, >+ {"ld", A64DB_LD}, >+ {"st", A64DB_ST}, >+ {"sy", A64DB_SY} >+}; >+ >+const A64NamedImmMapper A64DB_DBarrierMapper = { >+ DBarrierPairs, >+ ARR_SIZE(DBarrierPairs), >+ 16, >+}; >+ >+static const A64NamedImmMapper_Mapping DCPairs[] = { >+ {"zva", A64DC_ZVA}, >+ {"ivac", A64DC_IVAC}, >+ {"isw", A64DC_ISW}, >+ {"cvac", A64DC_CVAC}, >+ {"csw", A64DC_CSW}, >+ {"cvau", A64DC_CVAU}, >+ {"civac", A64DC_CIVAC}, >+ {"cisw", A64DC_CISW} >+}; >+ >+const A64NamedImmMapper A64DC_DCMapper = { >+ DCPairs, >+ ARR_SIZE(DCPairs), >+ 0, >+}; >+ >+static const A64NamedImmMapper_Mapping ICPairs[] = { >+ {"ialluis", A64IC_IALLUIS}, >+ {"iallu", A64IC_IALLU}, >+ {"ivau", A64IC_IVAU} >+}; >+ >+const A64NamedImmMapper A64IC_ICMapper = { >+ ICPairs, >+ ARR_SIZE(ICPairs), >+ 0, >+}; >+ >+static const A64NamedImmMapper_Mapping ISBPairs[] = { >+ {"sy", A64DB_SY}, >+}; >+ >+const A64NamedImmMapper A64ISB_ISBMapper = { >+ ISBPairs, >+ ARR_SIZE(ISBPairs), >+ 16, >+}; >+ >+static const A64NamedImmMapper_Mapping PRFMPairs[] = { >+ {"pldl1keep", A64PRFM_PLDL1KEEP}, >+ {"pldl1strm", A64PRFM_PLDL1STRM}, >+ {"pldl2keep", A64PRFM_PLDL2KEEP}, >+ {"pldl2strm", A64PRFM_PLDL2STRM}, >+ {"pldl3keep", A64PRFM_PLDL3KEEP}, >+ {"pldl3strm", A64PRFM_PLDL3STRM}, >+ {"plil1keep", A64PRFM_PLIL1KEEP}, >+ {"plil1strm", A64PRFM_PLIL1STRM}, >+ {"plil2keep", A64PRFM_PLIL2KEEP}, >+ {"plil2strm", A64PRFM_PLIL2STRM}, >+ {"plil3keep", A64PRFM_PLIL3KEEP}, >+ {"plil3strm", A64PRFM_PLIL3STRM}, >+ {"pstl1keep", A64PRFM_PSTL1KEEP}, >+ {"pstl1strm", A64PRFM_PSTL1STRM}, >+ {"pstl2keep", A64PRFM_PSTL2KEEP}, >+ {"pstl2strm", A64PRFM_PSTL2STRM}, >+ {"pstl3keep", A64PRFM_PSTL3KEEP}, >+ {"pstl3strm", A64PRFM_PSTL3STRM} >+}; >+ >+const A64NamedImmMapper A64PRFM_PRFMMapper = { >+ PRFMPairs, >+ ARR_SIZE(PRFMPairs), >+ 32, >+}; >+ >+static const A64NamedImmMapper_Mapping PStatePairs[] = { >+ {"spsel", A64PState_SPSel}, >+ {"daifset", A64PState_DAIFSet}, >+ {"daifclr", A64PState_DAIFClr}, >+ {"pan", A64PState_PAN}, >+ {"uao", A64PState_UAO} >+}; >+ >+const A64NamedImmMapper A64PState_PStateMapper = { >+ PStatePairs, >+ ARR_SIZE(PStatePairs), >+ 0, >+}; >+ >+static const A64NamedImmMapper_Mapping MRSPairs[] = { >+ {"mdccsr_el0", A64SysReg_MDCCSR_EL0}, >+ {"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0}, >+ {"mdrar_el1", A64SysReg_MDRAR_EL1}, >+ {"oslsr_el1", A64SysReg_OSLSR_EL1}, >+ {"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1}, >+ {"pmceid0_el0", A64SysReg_PMCEID0_EL0}, >+ {"pmceid1_el0", A64SysReg_PMCEID1_EL0}, >+ {"midr_el1", A64SysReg_MIDR_EL1}, >+ {"ccsidr_el1", A64SysReg_CCSIDR_EL1}, >+ {"clidr_el1", A64SysReg_CLIDR_EL1}, >+ {"ctr_el0", A64SysReg_CTR_EL0}, >+ {"mpidr_el1", A64SysReg_MPIDR_EL1}, >+ {"revidr_el1", A64SysReg_REVIDR_EL1}, >+ {"aidr_el1", A64SysReg_AIDR_EL1}, >+ {"dczid_el0", A64SysReg_DCZID_EL0}, >+ {"id_pfr0_el1", A64SysReg_ID_PFR0_EL1}, >+ {"id_pfr1_el1", A64SysReg_ID_PFR1_EL1}, >+ {"id_dfr0_el1", A64SysReg_ID_DFR0_EL1}, >+ {"id_afr0_el1", A64SysReg_ID_AFR0_EL1}, >+ {"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1}, >+ {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1}, >+ {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1}, >+ {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1}, >+ {"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1}, >+ {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1}, >+ {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1}, >+ {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1}, >+ {"id_isar3_el1", A64SysReg_ID_ISAR3_EL1}, >+ {"id_isar4_el1", A64SysReg_ID_ISAR4_EL1}, >+ {"id_isar5_el1", A64SysReg_ID_ISAR5_EL1}, >+ {"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1}, >+ {"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1}, >+ {"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1}, >+ {"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1}, >+ {"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1}, >+ {"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1}, >+ {"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1}, >+ {"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1}, >+ {"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1}, >+ {"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1}, >+ {"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1}, >+ {"lorid_el1", A64SysReg_LORID_EL1}, >+ {"mvfr0_el1", A64SysReg_MVFR0_EL1}, >+ {"mvfr1_el1", A64SysReg_MVFR1_EL1}, >+ {"mvfr2_el1", A64SysReg_MVFR2_EL1}, >+ {"rvbar_el1", A64SysReg_RVBAR_EL1}, >+ {"rvbar_el2", A64SysReg_RVBAR_EL2}, >+ {"rvbar_el3", A64SysReg_RVBAR_EL3}, >+ {"isr_el1", A64SysReg_ISR_EL1}, >+ {"cntpct_el0", A64SysReg_CNTPCT_EL0}, >+ {"cntvct_el0", A64SysReg_CNTVCT_EL0}, >+ >+ // Trace registers >+ {"trcstatr", A64SysReg_TRCSTATR}, >+ {"trcidr8", A64SysReg_TRCIDR8}, >+ {"trcidr9", A64SysReg_TRCIDR9}, >+ {"trcidr10", A64SysReg_TRCIDR10}, >+ {"trcidr11", A64SysReg_TRCIDR11}, >+ {"trcidr12", A64SysReg_TRCIDR12}, >+ {"trcidr13", A64SysReg_TRCIDR13}, >+ {"trcidr0", A64SysReg_TRCIDR0}, >+ {"trcidr1", A64SysReg_TRCIDR1}, >+ {"trcidr2", A64SysReg_TRCIDR2}, >+ {"trcidr3", A64SysReg_TRCIDR3}, >+ {"trcidr4", A64SysReg_TRCIDR4}, >+ {"trcidr5", A64SysReg_TRCIDR5}, >+ {"trcidr6", A64SysReg_TRCIDR6}, >+ {"trcidr7", A64SysReg_TRCIDR7}, >+ {"trcoslsr", A64SysReg_TRCOSLSR}, >+ {"trcpdsr", A64SysReg_TRCPDSR}, >+ {"trcdevaff0", A64SysReg_TRCDEVAFF0}, >+ {"trcdevaff1", A64SysReg_TRCDEVAFF1}, >+ {"trclsr", A64SysReg_TRCLSR}, >+ {"trcauthstatus", A64SysReg_TRCAUTHSTATUS}, >+ {"trcdevarch", A64SysReg_TRCDEVARCH}, >+ {"trcdevid", A64SysReg_TRCDEVID}, >+ {"trcdevtype", A64SysReg_TRCDEVTYPE}, >+ {"trcpidr4", A64SysReg_TRCPIDR4}, >+ {"trcpidr5", A64SysReg_TRCPIDR5}, >+ {"trcpidr6", A64SysReg_TRCPIDR6}, >+ {"trcpidr7", A64SysReg_TRCPIDR7}, >+ {"trcpidr0", A64SysReg_TRCPIDR0}, >+ {"trcpidr1", A64SysReg_TRCPIDR1}, >+ {"trcpidr2", A64SysReg_TRCPIDR2}, >+ {"trcpidr3", A64SysReg_TRCPIDR3}, >+ {"trccidr0", A64SysReg_TRCCIDR0}, >+ {"trccidr1", A64SysReg_TRCCIDR1}, >+ {"trccidr2", A64SysReg_TRCCIDR2}, >+ {"trccidr3", A64SysReg_TRCCIDR3}, >+ >+ // GICv3 registers >+ {"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1}, >+ {"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1}, >+ {"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1}, >+ {"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1}, >+ {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1}, >+ {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2}, >+ {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2}, >+ {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2}, >+ >+ // Statistical profiling registers >+ {"pmsidr_el1", A64SysReg_PMSIDR_EL1}, >+ {"pmbidr_el1", A64SysReg_PMBIDR_EL1} >+}; >+ >+const A64SysRegMapper AArch64_MRSMapper = { >+ NULL, >+ MRSPairs, >+ ARR_SIZE(MRSPairs), >+}; >+ >+static const A64NamedImmMapper_Mapping MSRPairs[] = { >+ {"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0}, >+ {"oslar_el1", A64SysReg_OSLAR_EL1}, >+ {"pmswinc_el0", A64SysReg_PMSWINC_EL0}, >+ >+ // Trace registers >+ {"trcoslar", A64SysReg_TRCOSLAR}, >+ {"trclar", A64SysReg_TRCLAR}, >+ >+ // GICv3 registers >+ {"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1}, >+ {"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1}, >+ {"icc_dir_el1", A64SysReg_ICC_DIR_EL1}, >+ {"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1}, >+ {"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1}, >+ {"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1} >+}; >+ >+const A64SysRegMapper AArch64_MSRMapper = { >+ NULL, >+ MSRPairs, >+ ARR_SIZE(MSRPairs), >+}; >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.h b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.h >new file mode 100644 >index 0000000000000000000000000000000000000000..a4d72b21dd41cdd80945b5da8f8b076b504d4618 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64BaseInfo.h >@@ -0,0 +1,1013 @@ >+//===-- AArch64BaseInfo.h - Top level definitions for AArch64- --*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains small standalone helper functions and enum definitions for >+// the AArch64 target useful for the compiler back-end and the MC libraries. >+// As such, it deliberately does not include references to LLVM core >+// code gen types, passes, etc.. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_AARCH64_BASEINFO_H >+#define CS_LLVM_AARCH64_BASEINFO_H >+ >+#include <ctype.h> >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+#include <string.h> >+ >+#ifndef __cplusplus >+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) >+#define inline /* inline */ >+#endif >+#endif >+ >+inline static unsigned getWRegFromXReg(unsigned Reg) >+{ >+ switch (Reg) { >+ case ARM64_REG_X0: return ARM64_REG_W0; >+ case ARM64_REG_X1: return ARM64_REG_W1; >+ case ARM64_REG_X2: return ARM64_REG_W2; >+ case ARM64_REG_X3: return ARM64_REG_W3; >+ case ARM64_REG_X4: return ARM64_REG_W4; >+ case ARM64_REG_X5: return ARM64_REG_W5; >+ case ARM64_REG_X6: return ARM64_REG_W6; >+ case ARM64_REG_X7: return ARM64_REG_W7; >+ case ARM64_REG_X8: return ARM64_REG_W8; >+ case ARM64_REG_X9: return ARM64_REG_W9; >+ case ARM64_REG_X10: return ARM64_REG_W10; >+ case ARM64_REG_X11: return ARM64_REG_W11; >+ case ARM64_REG_X12: return ARM64_REG_W12; >+ case ARM64_REG_X13: return ARM64_REG_W13; >+ case ARM64_REG_X14: return ARM64_REG_W14; >+ case ARM64_REG_X15: return ARM64_REG_W15; >+ case ARM64_REG_X16: return ARM64_REG_W16; >+ case ARM64_REG_X17: return ARM64_REG_W17; >+ case ARM64_REG_X18: return ARM64_REG_W18; >+ case ARM64_REG_X19: return ARM64_REG_W19; >+ case ARM64_REG_X20: return ARM64_REG_W20; >+ case ARM64_REG_X21: return ARM64_REG_W21; >+ case ARM64_REG_X22: return ARM64_REG_W22; >+ case ARM64_REG_X23: return ARM64_REG_W23; >+ case ARM64_REG_X24: return ARM64_REG_W24; >+ case ARM64_REG_X25: return ARM64_REG_W25; >+ case ARM64_REG_X26: return ARM64_REG_W26; >+ case ARM64_REG_X27: return ARM64_REG_W27; >+ case ARM64_REG_X28: return ARM64_REG_W28; >+ case ARM64_REG_FP: return ARM64_REG_W29; >+ case ARM64_REG_LR: return ARM64_REG_W30; >+ case ARM64_REG_SP: return ARM64_REG_WSP; >+ case ARM64_REG_XZR: return ARM64_REG_WZR; >+ } >+ >+ // For anything else, return it unchanged. >+ return Reg; >+} >+ >+// // Enums corresponding to AArch64 condition codes >+// The CondCodes constants map directly to the 4-bit encoding of the >+// condition field for predicated instructions. >+typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point) >+ A64CC_EQ = 0, // Equal Equal >+ A64CC_NE, // Not equal Not equal, or unordered >+ A64CC_HS, // Unsigned higher or same >, ==, or unordered >+ A64CC_LO, // Unsigned lower or same Less than >+ A64CC_MI, // Minus, negative Less than >+ A64CC_PL, // Plus, positive or zero >, ==, or unordered >+ A64CC_VS, // Overflow Unordered >+ A64CC_VC, // No overflow Ordered >+ A64CC_HI, // Unsigned higher Greater than, or unordered >+ A64CC_LS, // Unsigned lower or same Less than or equal >+ A64CC_GE, // Greater than or equal Greater than or equal >+ A64CC_LT, // Less than Less than, or unordered >+ A64CC_GT, // Signed greater than Greater than >+ A64CC_LE, // Signed less than or equal <, ==, or unordered >+ A64CC_AL, // Always (unconditional) Always (unconditional) >+ A64CC_NV, // Always (unconditional) Always (unconditional) >+ // Note the NV exists purely to disassemble 0b1111. Execution is "always". >+ A64CC_Invalid >+} A64CC_CondCode; >+ >+inline static const char *getCondCodeName(A64CC_CondCode CC) >+{ >+ switch (CC) { >+ default: return NULL; // never reach >+ case A64CC_EQ: return "eq"; >+ case A64CC_NE: return "ne"; >+ case A64CC_HS: return "hs"; >+ case A64CC_LO: return "lo"; >+ case A64CC_MI: return "mi"; >+ case A64CC_PL: return "pl"; >+ case A64CC_VS: return "vs"; >+ case A64CC_VC: return "vc"; >+ case A64CC_HI: return "hi"; >+ case A64CC_LS: return "ls"; >+ case A64CC_GE: return "ge"; >+ case A64CC_LT: return "lt"; >+ case A64CC_GT: return "gt"; >+ case A64CC_LE: return "le"; >+ case A64CC_AL: return "al"; >+ case A64CC_NV: return "nv"; >+ } >+} >+ >+inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code) >+{ >+ // To reverse a condition it's necessary to only invert the low bit: >+ return (A64CC_CondCode)((unsigned)Code ^ 0x1); >+} >+ >+/// Instances of this class can perform bidirectional mapping from random >+/// identifier strings to operand encodings. For example "MSR" takes a named >+/// system-register which must be encoded somehow and decoded for printing. This >+/// central location means that the information for those transformations is not >+/// duplicated and remains in sync. >+/// >+/// FIXME: currently the algorithm is a completely unoptimised linear >+/// search. Obviously this could be improved, but we would probably want to work >+/// out just how often these instructions are emitted before working on it. It >+/// might even be optimal to just reorder the tables for the common instructions >+/// rather than changing the algorithm. >+typedef struct A64NamedImmMapper_Mapping { >+ const char *Name; >+ uint32_t Value; >+} A64NamedImmMapper_Mapping; >+ >+typedef struct A64NamedImmMapper { >+ const A64NamedImmMapper_Mapping *Pairs; >+ size_t NumPairs; >+ uint32_t TooBigImm; >+} A64NamedImmMapper; >+ >+typedef struct A64SysRegMapper { >+ const A64NamedImmMapper_Mapping *SysRegPairs; >+ const A64NamedImmMapper_Mapping *InstPairs; >+ size_t NumInstPairs; >+} A64SysRegMapper; >+ >+extern const A64SysRegMapper AArch64_MSRMapper; >+extern const A64SysRegMapper AArch64_MRSMapper; >+ >+extern const A64NamedImmMapper A64DB_DBarrierMapper; >+extern const A64NamedImmMapper A64AT_ATMapper; >+extern const A64NamedImmMapper A64DC_DCMapper; >+extern const A64NamedImmMapper A64IC_ICMapper; >+extern const A64NamedImmMapper A64ISB_ISBMapper; >+extern const A64NamedImmMapper A64PRFM_PRFMMapper; >+extern const A64NamedImmMapper A64PState_PStateMapper; >+extern const A64NamedImmMapper A64TLBI_TLBIMapper; >+ >+enum { >+ A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2 >+ A64AT_S1E1R = 0x43c0, // 01 000 0111 1000 000 >+ A64AT_S1E2R = 0x63c0, // 01 100 0111 1000 000 >+ A64AT_S1E3R = 0x73c0, // 01 110 0111 1000 000 >+ A64AT_S1E1W = 0x43c1, // 01 000 0111 1000 001 >+ A64AT_S1E2W = 0x63c1, // 01 100 0111 1000 001 >+ A64AT_S1E3W = 0x73c1, // 01 110 0111 1000 001 >+ A64AT_S1E0R = 0x43c2, // 01 000 0111 1000 010 >+ A64AT_S1E0W = 0x43c3, // 01 000 0111 1000 011 >+ A64AT_S12E1R = 0x63c4, // 01 100 0111 1000 100 >+ A64AT_S12E1W = 0x63c5, // 01 100 0111 1000 101 >+ A64AT_S12E0R = 0x63c6, // 01 100 0111 1000 110 >+ A64AT_S12E0W = 0x63c7 // 01 100 0111 1000 111 >+}; >+ >+enum A64DBValues { >+ A64DB_Invalid = -1, >+ A64DB_OSHLD = 0x1, >+ A64DB_OSHST = 0x2, >+ A64DB_OSH = 0x3, >+ A64DB_NSHLD = 0x5, >+ A64DB_NSHST = 0x6, >+ A64DB_NSH = 0x7, >+ A64DB_ISHLD = 0x9, >+ A64DB_ISHST = 0xa, >+ A64DB_ISH = 0xb, >+ A64DB_LD = 0xd, >+ A64DB_ST = 0xe, >+ A64DB_SY = 0xf >+}; >+ >+enum A64DCValues { >+ A64DC_Invalid = -1, // Op1 CRn CRm Op2 >+ A64DC_ZVA = 0x5ba1, // 01 011 0111 0100 001 >+ A64DC_IVAC = 0x43b1, // 01 000 0111 0110 001 >+ A64DC_ISW = 0x43b2, // 01 000 0111 0110 010 >+ A64DC_CVAC = 0x5bd1, // 01 011 0111 1010 001 >+ A64DC_CSW = 0x43d2, // 01 000 0111 1010 010 >+ A64DC_CVAU = 0x5bd9, // 01 011 0111 1011 001 >+ A64DC_CIVAC = 0x5bf1, // 01 011 0111 1110 001 >+ A64DC_CISW = 0x43f2 // 01 000 0111 1110 010 >+}; >+ >+enum A64ICValues { >+ A64IC_Invalid = -1, // Op1 CRn CRm Op2 >+ A64IC_IALLUIS = 0x0388, // 000 0111 0001 000 >+ A64IC_IALLU = 0x03a8, // 000 0111 0101 000 >+ A64IC_IVAU = 0x1ba9 // 011 0111 0101 001 >+}; >+ >+enum A64ISBValues { >+ A64ISB_Invalid = -1, >+ A64ISB_SY = 0xf >+}; >+ >+enum A64PRFMValues { >+ A64PRFM_Invalid = -1, >+ A64PRFM_PLDL1KEEP = 0x00, >+ A64PRFM_PLDL1STRM = 0x01, >+ A64PRFM_PLDL2KEEP = 0x02, >+ A64PRFM_PLDL2STRM = 0x03, >+ A64PRFM_PLDL3KEEP = 0x04, >+ A64PRFM_PLDL3STRM = 0x05, >+ A64PRFM_PLIL1KEEP = 0x08, >+ A64PRFM_PLIL1STRM = 0x09, >+ A64PRFM_PLIL2KEEP = 0x0a, >+ A64PRFM_PLIL2STRM = 0x0b, >+ A64PRFM_PLIL3KEEP = 0x0c, >+ A64PRFM_PLIL3STRM = 0x0d, >+ A64PRFM_PSTL1KEEP = 0x10, >+ A64PRFM_PSTL1STRM = 0x11, >+ A64PRFM_PSTL2KEEP = 0x12, >+ A64PRFM_PSTL2STRM = 0x13, >+ A64PRFM_PSTL3KEEP = 0x14, >+ A64PRFM_PSTL3STRM = 0x15 >+}; >+ >+enum A64PStateValues { >+ A64PState_Invalid = -1, >+ A64PState_SPSel = 0x05, >+ A64PState_DAIFSet = 0x1e, >+ A64PState_DAIFClr = 0x1f, >+ A64PState_PAN = 0x4, >+ A64PState_UAO = 0x3 >+}; >+ >+typedef enum A64SE_ShiftExtSpecifiers { >+ A64SE_Invalid = -1, >+ A64SE_LSL, >+ A64SE_MSL, >+ A64SE_LSR, >+ A64SE_ASR, >+ A64SE_ROR, >+ >+ A64SE_UXTB, >+ A64SE_UXTH, >+ A64SE_UXTW, >+ A64SE_UXTX, >+ >+ A64SE_SXTB, >+ A64SE_SXTH, >+ A64SE_SXTW, >+ A64SE_SXTX >+} A64SE_ShiftExtSpecifiers; >+ >+typedef enum A64Layout_VectorLayout { >+ A64Layout_Invalid = -1, >+ A64Layout_VL_8B, >+ A64Layout_VL_4H, >+ A64Layout_VL_2S, >+ A64Layout_VL_1D, >+ >+ A64Layout_VL_16B, >+ A64Layout_VL_8H, >+ A64Layout_VL_4S, >+ A64Layout_VL_2D, >+ >+ // Bare layout for the 128-bit vector >+ // (only show ".b", ".h", ".s", ".d" without vector number) >+ A64Layout_VL_B, >+ A64Layout_VL_H, >+ A64Layout_VL_S, >+ A64Layout_VL_D >+} A64Layout_VectorLayout; >+ >+inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout) >+{ >+ switch (Layout) { >+ case A64Layout_VL_8B: return ".8b"; >+ case A64Layout_VL_4H: return ".4h"; >+ case A64Layout_VL_2S: return ".2s"; >+ case A64Layout_VL_1D: return ".1d"; >+ case A64Layout_VL_16B: return ".16b"; >+ case A64Layout_VL_8H: return ".8h"; >+ case A64Layout_VL_4S: return ".4s"; >+ case A64Layout_VL_2D: return ".2d"; >+ case A64Layout_VL_B: return ".b"; >+ case A64Layout_VL_H: return ".h"; >+ case A64Layout_VL_S: return ".s"; >+ case A64Layout_VL_D: return ".d"; >+ default: return NULL; // never reach >+ } >+} >+ >+enum A64SysRegROValues { >+ A64SysReg_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 >+ A64SysReg_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 >+ A64SysReg_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 >+ A64SysReg_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 >+ A64SysReg_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 >+ A64SysReg_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 >+ A64SysReg_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 >+ A64SysReg_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 >+ A64SysReg_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 >+ A64SysReg_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 >+ A64SysReg_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 >+ A64SysReg_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 >+ A64SysReg_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 >+ A64SysReg_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 >+ A64SysReg_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 >+ A64SysReg_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 >+ A64SysReg_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 >+ A64SysReg_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 >+ A64SysReg_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 >+ A64SysReg_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 >+ A64SysReg_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 >+ A64SysReg_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 >+ A64SysReg_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 >+ A64SysReg_ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110 >+ A64SysReg_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 >+ A64SysReg_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 >+ A64SysReg_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 >+ A64SysReg_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 >+ A64SysReg_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 >+ A64SysReg_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 >+ A64SysReg_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 >+ A64SysReg_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 >+ A64SysReg_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 >+ A64SysReg_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 >+ A64SysReg_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 >+ A64SysReg_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 >+ A64SysReg_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 >+ A64SysReg_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 >+ A64SysReg_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 >+ A64SysReg_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 >+ A64SysReg_ID_A64MMFR2_EL1 = 0xC03A, // 11 000 0000 0111 010 >+ A64SysReg_LORC_EL1 = 0xc523, // 11 000 1010 0100 011 >+ A64SysReg_LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 >+ A64SysReg_LORID_EL1 = 0xc527, // 11 000 1010 0100 111 >+ A64SysReg_LORN_EL1 = 0xc522, // 11 000 1010 0100 010 >+ A64SysReg_LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 >+ A64SysReg_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 >+ A64SysReg_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 >+ A64SysReg_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 >+ A64SysReg_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 >+ A64SysReg_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 >+ A64SysReg_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 >+ A64SysReg_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 >+ A64SysReg_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 >+ A64SysReg_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 >+ >+ // Trace registers >+ A64SysReg_TRCSTATR = 0x8818, // 10 001 0000 0011 000 >+ A64SysReg_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 >+ A64SysReg_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 >+ A64SysReg_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 >+ A64SysReg_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 >+ A64SysReg_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 >+ A64SysReg_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 >+ A64SysReg_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 >+ A64SysReg_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 >+ A64SysReg_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 >+ A64SysReg_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 >+ A64SysReg_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 >+ A64SysReg_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 >+ A64SysReg_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 >+ A64SysReg_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 >+ A64SysReg_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 >+ A64SysReg_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 >+ A64SysReg_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 >+ A64SysReg_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 >+ A64SysReg_TRCLSR = 0x8bee, // 10 001 0111 1101 110 >+ A64SysReg_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 >+ A64SysReg_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 >+ A64SysReg_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 >+ A64SysReg_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 >+ A64SysReg_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 >+ A64SysReg_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 >+ A64SysReg_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 >+ A64SysReg_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 >+ A64SysReg_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 >+ A64SysReg_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 >+ A64SysReg_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 >+ A64SysReg_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 >+ A64SysReg_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 >+ A64SysReg_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 >+ A64SysReg_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 >+ A64SysReg_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 >+ >+ // GICv3 registers >+ A64SysReg_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 >+ A64SysReg_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 >+ A64SysReg_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 >+ A64SysReg_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 >+ A64SysReg_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 >+ A64SysReg_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 >+ A64SysReg_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 >+ A64SysReg_ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 >+}; >+ >+enum A64SysRegWOValues { >+ A64SysReg_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 >+ A64SysReg_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 >+ A64SysReg_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 >+ >+ // Trace Registers >+ A64SysReg_TRCOSLAR = 0x8884, // 10 001 0001 0000 100 >+ A64SysReg_TRCLAR = 0x8be6, // 10 001 0111 1100 110 >+ >+ // GICv3 registers >+ A64SysReg_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 >+ A64SysReg_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 >+ A64SysReg_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 >+ A64SysReg_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 >+ A64SysReg_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 >+ A64SysReg_ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 >+}; >+ >+enum A64SysRegValues { >+ A64SysReg_Invalid = -1, // Op0 Op1 CRn CRm Op2 >+ A64SysReg_PAN = 0xc213, // 11 000 0100 0010 011 >+ A64SysReg_UAO = 0xc214, // 11 000 0100 0010 100 >+ A64SysReg_OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 >+ A64SysReg_OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 >+ A64SysReg_TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 >+ A64SysReg_MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 >+ A64SysReg_MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 >+ A64SysReg_DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 >+ A64SysReg_OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 >+ A64SysReg_DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 >+ A64SysReg_DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 >+ A64SysReg_DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 >+ A64SysReg_DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 >+ A64SysReg_DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 >+ A64SysReg_DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 >+ A64SysReg_DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 >+ A64SysReg_DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 >+ A64SysReg_DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 >+ A64SysReg_DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 >+ A64SysReg_DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 >+ A64SysReg_DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 >+ A64SysReg_DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 >+ A64SysReg_DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 >+ A64SysReg_DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 >+ A64SysReg_DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 >+ A64SysReg_DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 >+ A64SysReg_DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 >+ A64SysReg_DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 >+ A64SysReg_DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 >+ A64SysReg_DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 >+ A64SysReg_DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 >+ A64SysReg_DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 >+ A64SysReg_DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 >+ A64SysReg_DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 >+ A64SysReg_DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 >+ A64SysReg_DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 >+ A64SysReg_DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 >+ A64SysReg_DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 >+ A64SysReg_DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 >+ A64SysReg_DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 >+ A64SysReg_DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 >+ A64SysReg_DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 >+ A64SysReg_DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 >+ A64SysReg_DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 >+ A64SysReg_DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 >+ A64SysReg_DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 >+ A64SysReg_DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 >+ A64SysReg_DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 >+ A64SysReg_DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 >+ A64SysReg_DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 >+ A64SysReg_DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 >+ A64SysReg_DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 >+ A64SysReg_DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 >+ A64SysReg_DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 >+ A64SysReg_DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 >+ A64SysReg_DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 >+ A64SysReg_DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 >+ A64SysReg_DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 >+ A64SysReg_DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 >+ A64SysReg_DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 >+ A64SysReg_DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 >+ A64SysReg_DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 >+ A64SysReg_DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 >+ A64SysReg_DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 >+ A64SysReg_DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 >+ A64SysReg_DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 >+ A64SysReg_DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 >+ A64SysReg_DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 >+ A64SysReg_DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 >+ A64SysReg_DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 >+ A64SysReg_DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 >+ A64SysReg_DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 >+ A64SysReg_DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 >+ A64SysReg_DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 >+ A64SysReg_TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 >+ A64SysReg_OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 >+ A64SysReg_DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 >+ A64SysReg_DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 >+ A64SysReg_DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 >+ A64SysReg_CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 >+ A64SysReg_VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 >+ A64SysReg_VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 >+ A64SysReg_CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 >+ A64SysReg_CPACR_EL12 = 0xe882, // 11 101 0001 0000 010 >+ A64SysReg_SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 >+ A64SysReg_SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000 >+ A64SysReg_SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 >+ A64SysReg_SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 >+ A64SysReg_ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 >+ A64SysReg_ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 >+ A64SysReg_ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 >+ A64SysReg_HCR_EL2 = 0xe088, // 11 100 0001 0001 000 >+ A64SysReg_SCR_EL3 = 0xf088, // 11 110 0001 0001 000 >+ A64SysReg_MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 >+ A64SysReg_SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 >+ A64SysReg_CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 >+ A64SysReg_CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 >+ A64SysReg_HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 >+ A64SysReg_HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 >+ A64SysReg_MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 >+ A64SysReg_TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 >+ A64SysReg_TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000 >+ A64SysReg_TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 >+ A64SysReg_TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 >+ A64SysReg_TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 >+ A64SysReg_TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001 >+ A64SysReg_TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001 >+ A64SysReg_TCR_EL1 = 0xc102, // 11 000 0010 0000 010 >+ A64SysReg_TCR_EL12 = 0xe902, // 11 101 0010 0000 010 >+ A64SysReg_TCR_EL2 = 0xe102, // 11 100 0010 0000 010 >+ A64SysReg_TCR_EL3 = 0xf102, // 11 110 0010 0000 010 >+ A64SysReg_VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 >+ A64SysReg_VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 >+ A64SysReg_DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 >+ A64SysReg_SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 >+ A64SysReg_SPSR_EL12 = 0xea00, // 11 101 0100 0000 000 >+ A64SysReg_SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 >+ A64SysReg_SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 >+ A64SysReg_ELR_EL1 = 0xc201, // 11 000 0100 0000 001 >+ A64SysReg_ELR_EL12 = 0xea01, // 11 101 0100 0000 001 >+ A64SysReg_ELR_EL2 = 0xe201, // 11 100 0100 0000 001 >+ A64SysReg_ELR_EL3 = 0xf201, // 11 110 0100 0000 001 >+ A64SysReg_SP_EL0 = 0xc208, // 11 000 0100 0001 000 >+ A64SysReg_SP_EL1 = 0xe208, // 11 100 0100 0001 000 >+ A64SysReg_SP_EL2 = 0xf208, // 11 110 0100 0001 000 >+ A64SysReg_SPSel = 0xc210, // 11 000 0100 0010 000 >+ A64SysReg_NZCV = 0xda10, // 11 011 0100 0010 000 >+ A64SysReg_DAIF = 0xda11, // 11 011 0100 0010 001 >+ A64SysReg_CurrentEL = 0xc212, // 11 000 0100 0010 010 >+ A64SysReg_SPSR_irq = 0xe218, // 11 100 0100 0011 000 >+ A64SysReg_SPSR_abt = 0xe219, // 11 100 0100 0011 001 >+ A64SysReg_SPSR_und = 0xe21a, // 11 100 0100 0011 010 >+ A64SysReg_SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 >+ A64SysReg_FPCR = 0xda20, // 11 011 0100 0100 000 >+ A64SysReg_FPSR = 0xda21, // 11 011 0100 0100 001 >+ A64SysReg_DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 >+ A64SysReg_DLR_EL0 = 0xda29, // 11 011 0100 0101 001 >+ A64SysReg_IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 >+ A64SysReg_AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 >+ A64SysReg_AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000 >+ A64SysReg_AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 >+ A64SysReg_AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 >+ A64SysReg_AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 >+ A64SysReg_AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001 >+ A64SysReg_AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 >+ A64SysReg_AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 >+ A64SysReg_ESR_EL1 = 0xc290, // 11 000 0101 0010 000 >+ A64SysReg_ESR_EL12 = 0xea90, // 11 101 0101 0010 000 >+ A64SysReg_ESR_EL2 = 0xe290, // 11 100 0101 0010 000 >+ A64SysReg_ESR_EL3 = 0xf290, // 11 110 0101 0010 000 >+ A64SysReg_FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 >+ A64SysReg_FAR_EL1 = 0xc300, // 11 000 0110 0000 000 >+ A64SysReg_FAR_EL12 = 0xeb00, // 11 101 0110 0000 000 >+ A64SysReg_FAR_EL2 = 0xe300, // 11 100 0110 0000 000 >+ A64SysReg_FAR_EL3 = 0xf300, // 11 110 0110 0000 000 >+ A64SysReg_HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 >+ A64SysReg_PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 >+ A64SysReg_PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 >+ A64SysReg_PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 >+ A64SysReg_PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 >+ A64SysReg_PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 >+ A64SysReg_PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 >+ A64SysReg_PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 >+ A64SysReg_PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 >+ A64SysReg_PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 >+ A64SysReg_PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 >+ A64SysReg_PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 >+ A64SysReg_PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 >+ A64SysReg_PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 >+ A64SysReg_MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 >+ A64SysReg_MAIR_EL12 = 0xed10, // 11 101 1010 0010 000 >+ A64SysReg_MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 >+ A64SysReg_MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 >+ A64SysReg_AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 >+ A64SysReg_AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000 >+ A64SysReg_AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 >+ A64SysReg_AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 >+ A64SysReg_VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 >+ A64SysReg_VBAR_EL12 = 0xee00, // 11 101 1100 0000 000 >+ A64SysReg_VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 >+ A64SysReg_VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 >+ A64SysReg_RMR_EL1 = 0xc602, // 11 000 1100 0000 010 >+ A64SysReg_RMR_EL2 = 0xe602, // 11 100 1100 0000 010 >+ A64SysReg_RMR_EL3 = 0xf602, // 11 110 1100 0000 010 >+ A64SysReg_CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 >+ A64SysReg_CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001 >+ A64SysReg_CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001 >+ A64SysReg_TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 >+ A64SysReg_TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 >+ A64SysReg_TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 >+ A64SysReg_TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 >+ A64SysReg_TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 >+ A64SysReg_CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 >+ A64SysReg_CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 >+ A64SysReg_CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 >+ A64SysReg_CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000 >+ A64SysReg_CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 >+ A64SysReg_CNTHVCTL_EL2 = 0xe719, // 11 100 1110 0011 001 >+ A64SysReg_CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010 >+ A64SysReg_CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000 >+ A64SysReg_CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 >+ A64SysReg_CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000 >+ A64SysReg_CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 >+ A64SysReg_CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 >+ A64SysReg_CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 >+ A64SysReg_CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 >+ A64SysReg_CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 >+ A64SysReg_CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 >+ A64SysReg_CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010 >+ A64SysReg_CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 >+ A64SysReg_CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 >+ A64SysReg_CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 >+ A64SysReg_CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000 >+ A64SysReg_CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 >+ A64SysReg_CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001 >+ A64SysReg_CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 >+ A64SysReg_CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010 >+ A64SysReg_PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 >+ A64SysReg_PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 >+ A64SysReg_PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 >+ A64SysReg_PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 >+ A64SysReg_PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 >+ A64SysReg_PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 >+ A64SysReg_PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 >+ A64SysReg_PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 >+ A64SysReg_PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 >+ A64SysReg_PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 >+ A64SysReg_PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 >+ A64SysReg_PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 >+ A64SysReg_PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 >+ A64SysReg_PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 >+ A64SysReg_PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 >+ A64SysReg_PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 >+ A64SysReg_PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 >+ A64SysReg_PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 >+ A64SysReg_PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 >+ A64SysReg_PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 >+ A64SysReg_PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 >+ A64SysReg_PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 >+ A64SysReg_PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 >+ A64SysReg_PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 >+ A64SysReg_PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 >+ A64SysReg_PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 >+ A64SysReg_PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 >+ A64SysReg_PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 >+ A64SysReg_PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 >+ A64SysReg_PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 >+ A64SysReg_PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 >+ A64SysReg_PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 >+ A64SysReg_PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 >+ A64SysReg_PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 >+ A64SysReg_PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 >+ A64SysReg_PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 >+ A64SysReg_PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 >+ A64SysReg_PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 >+ A64SysReg_PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 >+ A64SysReg_PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 >+ A64SysReg_PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 >+ A64SysReg_PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 >+ A64SysReg_PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 >+ A64SysReg_PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 >+ A64SysReg_PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 >+ A64SysReg_PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 >+ A64SysReg_PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 >+ A64SysReg_PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 >+ A64SysReg_PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 >+ A64SysReg_PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 >+ A64SysReg_PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 >+ A64SysReg_PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 >+ A64SysReg_PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 >+ A64SysReg_PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 >+ A64SysReg_PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 >+ A64SysReg_PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 >+ A64SysReg_PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 >+ A64SysReg_PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 >+ A64SysReg_PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 >+ A64SysReg_PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 >+ A64SysReg_PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 >+ A64SysReg_PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 >+ A64SysReg_PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 >+ >+ // Trace registers >+ A64SysReg_TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 >+ A64SysReg_TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 >+ A64SysReg_TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 >+ A64SysReg_TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 >+ A64SysReg_TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 >+ A64SysReg_TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 >+ A64SysReg_TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 >+ A64SysReg_TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 >+ A64SysReg_TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 >+ A64SysReg_TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 >+ A64SysReg_TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 >+ A64SysReg_TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 >+ A64SysReg_TRCQCTLR = 0x8809, // 10 001 0000 0001 001 >+ A64SysReg_TRCVICTLR = 0x8802, // 10 001 0000 0000 010 >+ A64SysReg_TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 >+ A64SysReg_TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 >+ A64SysReg_TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 >+ A64SysReg_TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 >+ A64SysReg_TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 >+ A64SysReg_TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 >+ A64SysReg_TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 >+ A64SysReg_TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 >+ A64SysReg_TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 >+ A64SysReg_TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 >+ A64SysReg_TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 >+ A64SysReg_TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 >+ A64SysReg_TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 >+ A64SysReg_TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 >+ A64SysReg_TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 >+ A64SysReg_TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 >+ A64SysReg_TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 >+ A64SysReg_TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 >+ A64SysReg_TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 >+ A64SysReg_TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 >+ A64SysReg_TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 >+ A64SysReg_TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 >+ A64SysReg_TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 >+ A64SysReg_TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 >+ A64SysReg_TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 >+ A64SysReg_TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 >+ A64SysReg_TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 >+ A64SysReg_TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 >+ A64SysReg_TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 >+ A64SysReg_TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 >+ A64SysReg_TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 >+ A64SysReg_TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 >+ A64SysReg_TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 >+ A64SysReg_TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 >+ A64SysReg_TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 >+ A64SysReg_TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 >+ A64SysReg_TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 >+ A64SysReg_TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 >+ A64SysReg_TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 >+ A64SysReg_TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 >+ A64SysReg_TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 >+ A64SysReg_TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 >+ A64SysReg_TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 >+ A64SysReg_TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 >+ A64SysReg_TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 >+ A64SysReg_TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 >+ A64SysReg_TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 >+ A64SysReg_TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 >+ A64SysReg_TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 >+ A64SysReg_TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 >+ A64SysReg_TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 >+ A64SysReg_TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 >+ A64SysReg_TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 >+ A64SysReg_TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 >+ A64SysReg_TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 >+ A64SysReg_TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 >+ A64SysReg_TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 >+ A64SysReg_TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 >+ A64SysReg_TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 >+ A64SysReg_TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 >+ A64SysReg_TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 >+ A64SysReg_TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 >+ A64SysReg_TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 >+ A64SysReg_TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 >+ A64SysReg_TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 >+ A64SysReg_TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 >+ A64SysReg_TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 >+ A64SysReg_TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 >+ A64SysReg_TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 >+ A64SysReg_TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 >+ A64SysReg_TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 >+ A64SysReg_TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 >+ A64SysReg_TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 >+ A64SysReg_TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 >+ A64SysReg_TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 >+ A64SysReg_TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 >+ A64SysReg_TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 >+ A64SysReg_TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 >+ A64SysReg_TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 >+ A64SysReg_TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 >+ A64SysReg_TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 >+ A64SysReg_TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 >+ A64SysReg_TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 >+ A64SysReg_TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 >+ A64SysReg_TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 >+ A64SysReg_TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 >+ A64SysReg_TRCPDCR = 0x88a4, // 10 001 0001 0100 100 >+ A64SysReg_TRCACVR0 = 0x8900, // 10 001 0010 0000 000 >+ A64SysReg_TRCACVR1 = 0x8910, // 10 001 0010 0010 000 >+ A64SysReg_TRCACVR2 = 0x8920, // 10 001 0010 0100 000 >+ A64SysReg_TRCACVR3 = 0x8930, // 10 001 0010 0110 000 >+ A64SysReg_TRCACVR4 = 0x8940, // 10 001 0010 1000 000 >+ A64SysReg_TRCACVR5 = 0x8950, // 10 001 0010 1010 000 >+ A64SysReg_TRCACVR6 = 0x8960, // 10 001 0010 1100 000 >+ A64SysReg_TRCACVR7 = 0x8970, // 10 001 0010 1110 000 >+ A64SysReg_TRCACVR8 = 0x8901, // 10 001 0010 0000 001 >+ A64SysReg_TRCACVR9 = 0x8911, // 10 001 0010 0010 001 >+ A64SysReg_TRCACVR10 = 0x8921, // 10 001 0010 0100 001 >+ A64SysReg_TRCACVR11 = 0x8931, // 10 001 0010 0110 001 >+ A64SysReg_TRCACVR12 = 0x8941, // 10 001 0010 1000 001 >+ A64SysReg_TRCACVR13 = 0x8951, // 10 001 0010 1010 001 >+ A64SysReg_TRCACVR14 = 0x8961, // 10 001 0010 1100 001 >+ A64SysReg_TRCACVR15 = 0x8971, // 10 001 0010 1110 001 >+ A64SysReg_TRCACATR0 = 0x8902, // 10 001 0010 0000 010 >+ A64SysReg_TRCACATR1 = 0x8912, // 10 001 0010 0010 010 >+ A64SysReg_TRCACATR2 = 0x8922, // 10 001 0010 0100 010 >+ A64SysReg_TRCACATR3 = 0x8932, // 10 001 0010 0110 010 >+ A64SysReg_TRCACATR4 = 0x8942, // 10 001 0010 1000 010 >+ A64SysReg_TRCACATR5 = 0x8952, // 10 001 0010 1010 010 >+ A64SysReg_TRCACATR6 = 0x8962, // 10 001 0010 1100 010 >+ A64SysReg_TRCACATR7 = 0x8972, // 10 001 0010 1110 010 >+ A64SysReg_TRCACATR8 = 0x8903, // 10 001 0010 0000 011 >+ A64SysReg_TRCACATR9 = 0x8913, // 10 001 0010 0010 011 >+ A64SysReg_TRCACATR10 = 0x8923, // 10 001 0010 0100 011 >+ A64SysReg_TRCACATR11 = 0x8933, // 10 001 0010 0110 011 >+ A64SysReg_TRCACATR12 = 0x8943, // 10 001 0010 1000 011 >+ A64SysReg_TRCACATR13 = 0x8953, // 10 001 0010 1010 011 >+ A64SysReg_TRCACATR14 = 0x8963, // 10 001 0010 1100 011 >+ A64SysReg_TRCACATR15 = 0x8973, // 10 001 0010 1110 011 >+ A64SysReg_TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 >+ A64SysReg_TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 >+ A64SysReg_TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 >+ A64SysReg_TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 >+ A64SysReg_TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 >+ A64SysReg_TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 >+ A64SysReg_TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 >+ A64SysReg_TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 >+ A64SysReg_TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 >+ A64SysReg_TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 >+ A64SysReg_TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 >+ A64SysReg_TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 >+ A64SysReg_TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 >+ A64SysReg_TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 >+ A64SysReg_TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 >+ A64SysReg_TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 >+ A64SysReg_TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 >+ A64SysReg_TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 >+ A64SysReg_TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 >+ A64SysReg_TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 >+ A64SysReg_TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 >+ A64SysReg_TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 >+ A64SysReg_TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 >+ A64SysReg_TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 >+ A64SysReg_TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 >+ A64SysReg_TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 >+ A64SysReg_TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 >+ A64SysReg_TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 >+ A64SysReg_TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 >+ A64SysReg_TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 >+ A64SysReg_TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 >+ A64SysReg_TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 >+ A64SysReg_TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 >+ A64SysReg_TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 >+ A64SysReg_TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 >+ A64SysReg_TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 >+ A64SysReg_TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 >+ A64SysReg_TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 >+ A64SysReg_TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 >+ >+ // GICv3 registers >+ A64SysReg_ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 >+ A64SysReg_ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 >+ A64SysReg_ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 >+ A64SysReg_ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 >+ A64SysReg_ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 >+ A64SysReg_ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 >+ A64SysReg_ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 >+ A64SysReg_ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 >+ A64SysReg_ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 >+ A64SysReg_ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 >+ A64SysReg_ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 >+ A64SysReg_ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 >+ A64SysReg_ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 >+ A64SysReg_ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 >+ A64SysReg_ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 >+ A64SysReg_ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 >+ A64SysReg_ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 >+ A64SysReg_ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 >+ A64SysReg_ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 >+ A64SysReg_ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 >+ A64SysReg_ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 >+ A64SysReg_ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 >+ A64SysReg_ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 >+ A64SysReg_ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 >+ A64SysReg_ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 >+ A64SysReg_ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 >+ A64SysReg_ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 >+ A64SysReg_ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 >+ A64SysReg_ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 >+ A64SysReg_ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 >+ A64SysReg_ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 >+ A64SysReg_ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 >+ A64SysReg_ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 >+ A64SysReg_ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 >+ A64SysReg_ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 >+ A64SysReg_ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 >+ A64SysReg_ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 >+ A64SysReg_ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 >+ A64SysReg_ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 >+ A64SysReg_ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 >+ A64SysReg_ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 >+ A64SysReg_ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 >+ A64SysReg_ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 >+ A64SysReg_ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 >+ A64SysReg_ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 >+ A64SysReg_ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 >+ A64SysReg_ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 >+ A64SysReg_ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 >+ >+ // Statistical profiling registers >+ A64SysReg_PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111 >+ A64SysReg_PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111 >+ A64SysReg_PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000 >+ A64SysReg_PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001 >+ A64SysReg_PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011 >+ A64SysReg_PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000 >+ A64SysReg_PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000 >+ A64SysReg_PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000 >+ A64SysReg_PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010 >+ A64SysReg_PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011 >+ A64SysReg_PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100 >+ A64SysReg_PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101 >+ A64SysReg_PMSLATFR_EL1 = 0xc4ce // 11 000 1001 1001 110 >+}; >+ >+// Cyclone specific system registers >+enum A64CycloneSysRegValues { >+ A64SysReg_CPM_IOACC_CTL_EL3 = 0xff90 >+}; >+ >+enum A64TLBIValues { >+ A64TLBI_Invalid = -1, // Op0 Op1 CRn CRm Op2 >+ A64TLBI_IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 >+ A64TLBI_IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 >+ A64TLBI_VMALLE1IS = 0x4418, // 01 000 1000 0011 000 >+ A64TLBI_ALLE2IS = 0x6418, // 01 100 1000 0011 000 >+ A64TLBI_ALLE3IS = 0x7418, // 01 110 1000 0011 000 >+ A64TLBI_VAE1IS = 0x4419, // 01 000 1000 0011 001 >+ A64TLBI_VAE2IS = 0x6419, // 01 100 1000 0011 001 >+ A64TLBI_VAE3IS = 0x7419, // 01 110 1000 0011 001 >+ A64TLBI_ASIDE1IS = 0x441a, // 01 000 1000 0011 010 >+ A64TLBI_VAAE1IS = 0x441b, // 01 000 1000 0011 011 >+ A64TLBI_ALLE1IS = 0x641c, // 01 100 1000 0011 100 >+ A64TLBI_VALE1IS = 0x441d, // 01 000 1000 0011 101 >+ A64TLBI_VALE2IS = 0x641d, // 01 100 1000 0011 101 >+ A64TLBI_VALE3IS = 0x741d, // 01 110 1000 0011 101 >+ A64TLBI_VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 >+ A64TLBI_VAALE1IS = 0x441f, // 01 000 1000 0011 111 >+ A64TLBI_IPAS2E1 = 0x6421, // 01 100 1000 0100 001 >+ A64TLBI_IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 >+ A64TLBI_VMALLE1 = 0x4438, // 01 000 1000 0111 000 >+ A64TLBI_ALLE2 = 0x6438, // 01 100 1000 0111 000 >+ A64TLBI_ALLE3 = 0x7438, // 01 110 1000 0111 000 >+ A64TLBI_VAE1 = 0x4439, // 01 000 1000 0111 001 >+ A64TLBI_VAE2 = 0x6439, // 01 100 1000 0111 001 >+ A64TLBI_VAE3 = 0x7439, // 01 110 1000 0111 001 >+ A64TLBI_ASIDE1 = 0x443a, // 01 000 1000 0111 010 >+ A64TLBI_VAAE1 = 0x443b, // 01 000 1000 0111 011 >+ A64TLBI_ALLE1 = 0x643c, // 01 100 1000 0111 100 >+ A64TLBI_VALE1 = 0x443d, // 01 000 1000 0111 101 >+ A64TLBI_VALE2 = 0x643d, // 01 100 1000 0111 101 >+ A64TLBI_VALE3 = 0x743d, // 01 110 1000 0111 101 >+ A64TLBI_VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 >+ A64TLBI_VAALE1 = 0x443f // 01 000 1000 0111 111 >+}; >+ >+bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm); >+ >+const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid); >+ >+uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid); >+ >+bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value); >+ >+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.c b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.c >new file mode 100644 >index 0000000000000000000000000000000000000000..a05970f01ebe5d3a858638735a8012160cf8dee2 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.c >@@ -0,0 +1,1680 @@ >+//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the functions necessary to decode AArch64 instruction >+// bitpatterns into MCInsts (with the help of TableGenerated information from >+// the instruction definitions). >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM64 >+ >+#include <stdio.h> // DEBUG >+#include <stdlib.h> >+ >+#include "../../cs_priv.h" >+#include "../../utils.h" >+ >+#include "../../MCInst.h" >+#include "../../MCInstrDesc.h" >+#include "../../MCFixedLenDisassembler.h" >+#include "../../MCRegisterInfo.h" >+#include "../../MCDisassembler.h" >+ >+#include "AArch64BaseInfo.h" >+#include "AArch64AddressingModes.h" >+ >+ >+// Forward declare these because the autogenerated code will reference them. >+// Definitions are further down. >+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, >+ unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, >+ const void *Decoder); >+ >+static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, >+ uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, >+ uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, >+ uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, >+ uint32_t insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, >+ uint64_t Address, const void *Decoder); >+ >+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, >+ const void *Decoder); >+static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder); >+static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder); >+static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder); >+static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder); >+ >+static bool Check(DecodeStatus *Out, DecodeStatus In) >+{ >+ switch (In) { >+ default: // never reach >+ return true; >+ case MCDisassembler_Success: >+ // Out stays the same. >+ return true; >+ case MCDisassembler_SoftFail: >+ *Out = In; >+ return true; >+ case MCDisassembler_Fail: >+ *Out = In; >+ return false; >+ } >+ // llvm_unreachable("Invalid DecodeStatus!"); >+} >+ >+// Hacky: enable all features for disassembler >+static uint64_t getFeatureBits(int feature) >+{ >+ // enable all features >+ return (uint64_t)-1; >+} >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "AArch64GenSubtargetInfo.inc" >+ >+#include "AArch64GenDisassemblerTables.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "AArch64GenInstrInfo.inc" >+ >+#define GET_REGINFO_ENUM >+#define GET_REGINFO_MC_DESC >+#include "AArch64GenRegisterInfo.inc" >+ >+#define Success MCDisassembler_Success >+#define Fail MCDisassembler_Fail >+#define SoftFail MCDisassembler_SoftFail >+ >+static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, >+ const uint8_t *code, size_t code_len, >+ uint16_t *Size, >+ uint64_t Address, MCRegisterInfo *MRI) >+{ >+ uint32_t insn; >+ DecodeStatus result; >+ size_t i; >+ >+ if (code_len < 4) { >+ // not enough data >+ *Size = 0; >+ return MCDisassembler_Fail; >+ } >+ >+ if (MI->flat_insn->detail) { >+ memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); >+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++) >+ MI->flat_insn->detail->arm64.operands[i].vector_index = -1; >+ } >+ >+ if (MODE_IS_BIG_ENDIAN(ud->mode)) >+ insn = (code[3] << 0) | (code[2] << 8) | >+ (code[1] << 16) | (code[0] << 24); >+ else >+ insn = (code[3] << 24) | (code[2] << 16) | >+ (code[1] << 8) | (code[0] << 0); >+ >+ // Calling the auto-generated decoder function. >+ result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ *Size = 0; >+ return MCDisassembler_Fail; >+} >+ >+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info) >+{ >+ DecodeStatus status = _getInstruction((cs_struct *)ud, instr, >+ code, code_len, >+ size, >+ address, (MCRegisterInfo *)info); >+ >+ return status == MCDisassembler_Success; >+} >+ >+static const unsigned FPR128DecoderTable[] = { >+ AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, >+ AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, >+ AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, >+ AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, >+ AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, >+ AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, >+ AArch64_Q30, AArch64_Q31 >+}; >+ >+static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = FPR128DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ if (RegNo > 15) >+ return Fail; >+ >+ return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); >+} >+ >+static const unsigned FPR64DecoderTable[] = { >+ AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, >+ AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, >+ AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, >+ AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, >+ AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, >+ AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, >+ AArch64_D30, AArch64_D31 >+}; >+ >+static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = FPR64DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned FPR32DecoderTable[] = { >+ AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, >+ AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, >+ AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, >+ AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, >+ AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, >+ AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, >+ AArch64_S30, AArch64_S31 >+}; >+ >+static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = FPR32DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned FPR16DecoderTable[] = { >+ AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, >+ AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, >+ AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, >+ AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, >+ AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, >+ AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, >+ AArch64_H30, AArch64_H31 >+}; >+ >+static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = FPR16DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned FPR8DecoderTable[] = { >+ AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, >+ AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, >+ AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, >+ AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, >+ AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, >+ AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, >+ AArch64_B30, AArch64_B31 >+}; >+ >+static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = FPR8DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned GPR64DecoderTable[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, >+ AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, >+ AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, >+ AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, >+ AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, >+ AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, >+ AArch64_LR, AArch64_XZR >+}; >+ >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = GPR64DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = GPR64DecoderTable[RegNo]; >+ if (Register == AArch64_XZR) >+ Register = AArch64_SP; >+ >+ MCOperand_CreateReg0(Inst, Register); >+ >+ return Success; >+} >+ >+static const unsigned GPR32DecoderTable[] = { >+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, >+ AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, >+ AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, >+ AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, >+ AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, >+ AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, >+ AArch64_W30, AArch64_WZR >+}; >+ >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = GPR32DecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = GPR32DecoderTable[RegNo]; >+ if (Register == AArch64_WZR) >+ Register = AArch64_WSP; >+ >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned VectorDecoderTable[] = { >+ AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, >+ AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, >+ AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, >+ AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, >+ AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, >+ AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, >+ AArch64_Q30, AArch64_Q31 >+}; >+ >+static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = VectorDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned QQDecoderTable[] = { >+ AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, >+ AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, >+ AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, >+ AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, >+ AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, >+ AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, >+ AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, >+ AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0 >+}; >+ >+static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = QQDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned QQQDecoderTable[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, >+ AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, >+ AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, >+ AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, >+ AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, >+ AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, >+ AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, >+ AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, >+ AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, >+ AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, >+ AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1 >+}; >+ >+static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = QQQDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned QQQQDecoderTable[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, >+ AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, >+ AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, >+ AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, >+ AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, >+ AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, >+ AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, >+ AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, >+ AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, >+ AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, >+ AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2 >+}; >+ >+static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = QQQQDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned DDDecoderTable[] = { >+ AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, >+ AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, >+ AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, >+ AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, >+ AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, >+ AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, >+ AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, >+ AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0 >+}; >+ >+static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = DDDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned DDDDecoderTable[] = { >+ AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, >+ AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, >+ AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, >+ AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, >+ AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, >+ AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, >+ AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, >+ AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, >+ AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, >+ AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, >+ AArch64_D30_D31_D0, AArch64_D31_D0_D1 >+}; >+ >+static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = DDDDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static const unsigned DDDDDecoderTable[] = { >+ AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, >+ AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, >+ AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, >+ AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, >+ AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, >+ AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, >+ AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, >+ AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, >+ AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, >+ AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, >+ AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2 >+}; >+ >+static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Register; >+ >+ if (RegNo > 31) >+ return Fail; >+ >+ Register = DDDDDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return Success; >+} >+ >+static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ // scale{5} is asserted as 1 in tblgen. >+ Imm |= 0x20; >+ MCOperand_CreateImm0(Inst, 64 - Imm); >+ return Success; >+} >+ >+static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 64 - Imm); >+ return Success; >+} >+ >+static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ int64_t ImmVal = Imm; >+ >+ // Sign-extend 19-bit immediate. >+ if (ImmVal & (1 << (19 - 1))) >+ ImmVal |= ~((1LL << 19) - 1); >+ >+ MCOperand_CreateImm0(Inst, ImmVal); >+ return Success; >+} >+ >+static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); >+ MCOperand_CreateImm0(Inst, Imm & 1); >+ return Success; >+} >+ >+static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, >+ uint64_t Address, const void *Decoder) >+{ >+ bool ValidNamed; >+ char result[128]; >+ >+ Imm |= 0x8000; >+ MCOperand_CreateImm0(Inst, Imm); >+ >+ A64SysRegMapper_toString(&AArch64_MRSMapper, Imm, &ValidNamed, result); >+ >+ return ValidNamed ? Success : Fail; >+} >+ >+static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, >+ uint64_t Address, >+ const void *Decoder) >+{ >+ bool ValidNamed; >+ char result[128]; >+ >+ Imm |= 0x8000; >+ MCOperand_CreateImm0(Inst, Imm); >+ >+ A64SysRegMapper_toString(&AArch64_MSRMapper, Imm, &ValidNamed, result); >+ >+ return ValidNamed ? Success : Fail; >+} >+ >+static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, >+ const void *Decoder) >+{ >+ // This decoder exists to add the dummy Lane operand to the MCInst, which must >+ // be 1 in assembly but has no other real manifestation. >+ unsigned Rd = fieldFromInstruction(Insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(Insn, 5, 5); >+ unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); >+ >+ if (IsToVec) { >+ DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); >+ } else { >+ DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); >+ DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); >+ } >+ >+ // Add the lane >+ MCOperand_CreateImm0(Inst, 1); >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, >+ unsigned Add) >+{ >+ MCOperand_CreateImm0(Inst, Add - Imm); >+ return Success; >+} >+ >+static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, >+ unsigned Add) >+{ >+ MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); >+ return Success; >+} >+ >+static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm, 64); >+} >+ >+static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); >+} >+ >+static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm, 32); >+} >+ >+static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); >+} >+ >+static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm, 16); >+} >+ >+static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); >+} >+ >+static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftRImm(Inst, Imm, 8); >+} >+ >+static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftLImm(Inst, Imm, 64); >+} >+ >+static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftLImm(Inst, Imm, 32); >+} >+ >+static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftLImm(Inst, Imm, 16); >+} >+ >+static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, >+ uint64_t Addr, const void *Decoder) >+{ >+ return DecodeVecShiftLImm(Inst, Imm, 8); >+} >+ >+static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned Rm = fieldFromInstruction(insn, 16, 5); >+ unsigned shiftHi = fieldFromInstruction(insn, 22, 2); >+ unsigned shiftLo = fieldFromInstruction(insn, 10, 6); >+ unsigned shift = (shiftHi << 6) | shiftLo; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ return Fail; >+ case AArch64_ADDWrs: >+ case AArch64_ADDSWrs: >+ case AArch64_SUBWrs: >+ case AArch64_SUBSWrs: >+ // if shift == '11' then ReservedValue() >+ if (shiftHi == 0x3) >+ return Fail; >+ // Deliberate fallthrough >+ case AArch64_ANDWrs: >+ case AArch64_ANDSWrs: >+ case AArch64_BICWrs: >+ case AArch64_BICSWrs: >+ case AArch64_ORRWrs: >+ case AArch64_ORNWrs: >+ case AArch64_EORWrs: >+ case AArch64_EONWrs: { >+ // if sf == '0' and imm6<5> == '1' then ReservedValue() >+ if (shiftLo >> 5 == 1) >+ return Fail; >+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ } >+ case AArch64_ADDXrs: >+ case AArch64_ADDSXrs: >+ case AArch64_SUBXrs: >+ case AArch64_SUBSXrs: >+ // if shift == '11' then ReservedValue() >+ if (shiftHi == 0x3) >+ return Fail; >+ // Deliberate fallthrough >+ case AArch64_ANDXrs: >+ case AArch64_ANDSXrs: >+ case AArch64_BICXrs: >+ case AArch64_BICSXrs: >+ case AArch64_ORRXrs: >+ case AArch64_ORNXrs: >+ case AArch64_EORXrs: >+ case AArch64_EONXrs: >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, shift); >+ return Success; >+} >+ >+static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned imm = fieldFromInstruction(insn, 5, 16); >+ unsigned shift = fieldFromInstruction(insn, 21, 2); >+ >+ shift <<= 4; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ return Fail; >+ case AArch64_MOVZWi: >+ case AArch64_MOVNWi: >+ case AArch64_MOVKWi: >+ if (shift & (1U << 5)) >+ return Fail; >+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); >+ break; >+ case AArch64_MOVZXi: >+ case AArch64_MOVNXi: >+ case AArch64_MOVKXi: >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ break; >+ } >+ >+ if (MCInst_getOpcode(Inst) == AArch64_MOVKWi || >+ MCInst_getOpcode(Inst) == AArch64_MOVKXi) >+ MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0)); >+ >+ MCOperand_CreateImm0(Inst, imm); >+ MCOperand_CreateImm0(Inst, shift); >+ return Success; >+} >+ >+static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rt = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned offset = fieldFromInstruction(insn, 10, 12); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ return Fail; >+ case AArch64_PRFMui: >+ // Rt is an immediate in prefetch. >+ MCOperand_CreateImm0(Inst, Rt); >+ break; >+ case AArch64_STRBBui: >+ case AArch64_LDRBBui: >+ case AArch64_LDRSBWui: >+ case AArch64_STRHHui: >+ case AArch64_LDRHHui: >+ case AArch64_LDRSHWui: >+ case AArch64_STRWui: >+ case AArch64_LDRWui: >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRSBXui: >+ case AArch64_LDRSHXui: >+ case AArch64_LDRSWui: >+ case AArch64_STRXui: >+ case AArch64_LDRXui: >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRQui: >+ case AArch64_STRQui: >+ DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRDui: >+ case AArch64_STRDui: >+ DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRSui: >+ case AArch64_STRSui: >+ DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRHui: >+ case AArch64_STRHui: >+ DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDRBui: >+ case AArch64_STRBui: >+ DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ } >+ >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) >+ MCOperand_CreateImm0(Inst, offset); >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ bool IsLoad; >+ bool IsIndexed; >+ bool IsFP; >+ unsigned Rt = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ int64_t offset = fieldFromInstruction(insn, 12, 9); >+ >+ // offset is a 9-bit signed immediate, so sign extend it to >+ // fill the unsigned. >+ if (offset & (1 << (9 - 1))) >+ offset |= ~((1LL << 9) - 1); >+ >+ // First operand is always the writeback to the address register, if needed. >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ break; >+ case AArch64_LDRSBWpre: >+ case AArch64_LDRSHWpre: >+ case AArch64_STRBBpre: >+ case AArch64_LDRBBpre: >+ case AArch64_STRHHpre: >+ case AArch64_LDRHHpre: >+ case AArch64_STRWpre: >+ case AArch64_LDRWpre: >+ case AArch64_LDRSBWpost: >+ case AArch64_LDRSHWpost: >+ case AArch64_STRBBpost: >+ case AArch64_LDRBBpost: >+ case AArch64_STRHHpost: >+ case AArch64_LDRHHpost: >+ case AArch64_STRWpost: >+ case AArch64_LDRWpost: >+ case AArch64_LDRSBXpre: >+ case AArch64_LDRSHXpre: >+ case AArch64_STRXpre: >+ case AArch64_LDRSWpre: >+ case AArch64_LDRXpre: >+ case AArch64_LDRSBXpost: >+ case AArch64_LDRSHXpost: >+ case AArch64_STRXpost: >+ case AArch64_LDRSWpost: >+ case AArch64_LDRXpost: >+ case AArch64_LDRQpre: >+ case AArch64_STRQpre: >+ case AArch64_LDRQpost: >+ case AArch64_STRQpost: >+ case AArch64_LDRDpre: >+ case AArch64_STRDpre: >+ case AArch64_LDRDpost: >+ case AArch64_STRDpost: >+ case AArch64_LDRSpre: >+ case AArch64_STRSpre: >+ case AArch64_LDRSpost: >+ case AArch64_STRSpost: >+ case AArch64_LDRHpre: >+ case AArch64_STRHpre: >+ case AArch64_LDRHpost: >+ case AArch64_STRHpost: >+ case AArch64_LDRBpre: >+ case AArch64_STRBpre: >+ case AArch64_LDRBpost: >+ case AArch64_STRBpost: >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ break; >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ return Fail; >+ case AArch64_PRFUMi: >+ // Rt is an immediate in prefetch. >+ MCOperand_CreateImm0(Inst, Rt); >+ break; >+ case AArch64_STURBBi: >+ case AArch64_LDURBBi: >+ case AArch64_LDURSBWi: >+ case AArch64_STURHHi: >+ case AArch64_LDURHHi: >+ case AArch64_LDURSHWi: >+ case AArch64_STURWi: >+ case AArch64_LDURWi: >+ case AArch64_LDTRSBWi: >+ case AArch64_LDTRSHWi: >+ case AArch64_STTRWi: >+ case AArch64_LDTRWi: >+ case AArch64_STTRHi: >+ case AArch64_LDTRHi: >+ case AArch64_LDTRBi: >+ case AArch64_STTRBi: >+ case AArch64_LDRSBWpre: >+ case AArch64_LDRSHWpre: >+ case AArch64_STRBBpre: >+ case AArch64_LDRBBpre: >+ case AArch64_STRHHpre: >+ case AArch64_LDRHHpre: >+ case AArch64_STRWpre: >+ case AArch64_LDRWpre: >+ case AArch64_LDRSBWpost: >+ case AArch64_LDRSHWpost: >+ case AArch64_STRBBpost: >+ case AArch64_LDRBBpost: >+ case AArch64_STRHHpost: >+ case AArch64_LDRHHpost: >+ case AArch64_STRWpost: >+ case AArch64_LDRWpost: >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURSBXi: >+ case AArch64_LDURSHXi: >+ case AArch64_LDURSWi: >+ case AArch64_STURXi: >+ case AArch64_LDURXi: >+ case AArch64_LDTRSBXi: >+ case AArch64_LDTRSHXi: >+ case AArch64_LDTRSWi: >+ case AArch64_STTRXi: >+ case AArch64_LDTRXi: >+ case AArch64_LDRSBXpre: >+ case AArch64_LDRSHXpre: >+ case AArch64_STRXpre: >+ case AArch64_LDRSWpre: >+ case AArch64_LDRXpre: >+ case AArch64_LDRSBXpost: >+ case AArch64_LDRSHXpost: >+ case AArch64_STRXpost: >+ case AArch64_LDRSWpost: >+ case AArch64_LDRXpost: >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURQi: >+ case AArch64_STURQi: >+ case AArch64_LDRQpre: >+ case AArch64_STRQpre: >+ case AArch64_LDRQpost: >+ case AArch64_STRQpost: >+ DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURDi: >+ case AArch64_STURDi: >+ case AArch64_LDRDpre: >+ case AArch64_STRDpre: >+ case AArch64_LDRDpost: >+ case AArch64_STRDpost: >+ DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURSi: >+ case AArch64_STURSi: >+ case AArch64_LDRSpre: >+ case AArch64_STRSpre: >+ case AArch64_LDRSpost: >+ case AArch64_STRSpost: >+ DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURHi: >+ case AArch64_STURHi: >+ case AArch64_LDRHpre: >+ case AArch64_STRHpre: >+ case AArch64_LDRHpost: >+ case AArch64_STRHpost: >+ DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_LDURBi: >+ case AArch64_STURBi: >+ case AArch64_LDRBpre: >+ case AArch64_STRBpre: >+ case AArch64_LDRBpost: >+ case AArch64_STRBpost: >+ DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ } >+ >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ MCOperand_CreateImm0(Inst, offset); >+ >+ IsLoad = fieldFromInstruction(insn, 22, 1) != 0; >+ IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; >+ IsFP = fieldFromInstruction(insn, 26, 1) != 0; >+ >+ // Cannot write back to a transfer register (but xzr != sp). >+ if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) >+ return SoftFail; >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rt = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned Rt2 = fieldFromInstruction(insn, 10, 5); >+ unsigned Rs = fieldFromInstruction(insn, 16, 5); >+ unsigned Opcode = MCInst_getOpcode(Inst); >+ >+ switch (Opcode) { >+ default: >+ return Fail; >+ case AArch64_STLXRW: >+ case AArch64_STLXRB: >+ case AArch64_STLXRH: >+ case AArch64_STXRW: >+ case AArch64_STXRB: >+ case AArch64_STXRH: >+ DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); >+ // FALLTHROUGH >+ case AArch64_LDARW: >+ case AArch64_LDARB: >+ case AArch64_LDARH: >+ case AArch64_LDAXRW: >+ case AArch64_LDAXRB: >+ case AArch64_LDAXRH: >+ case AArch64_LDXRW: >+ case AArch64_LDXRB: >+ case AArch64_LDXRH: >+ case AArch64_STLRW: >+ case AArch64_STLRB: >+ case AArch64_STLRH: >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_STLXRX: >+ case AArch64_STXRX: >+ DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); >+ // FALLTHROUGH >+ case AArch64_LDARX: >+ case AArch64_LDAXRX: >+ case AArch64_LDXRX: >+ case AArch64_STLRX: >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ break; >+ case AArch64_STLXPW: >+ case AArch64_STXPW: >+ DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); >+ // FALLTHROUGH >+ case AArch64_LDAXPW: >+ case AArch64_LDXPW: >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ case AArch64_STLXPX: >+ case AArch64_STXPX: >+ DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); >+ // FALLTHROUGH >+ case AArch64_LDAXPX: >+ case AArch64_LDXPX: >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ } >+ >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ >+ // You shouldn't load to the same register twice in an instruction... >+ if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || >+ Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && >+ Rt == Rt2) >+ return SoftFail; >+ >+ return Success; >+} >+ >+static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rt = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned Rt2 = fieldFromInstruction(insn, 10, 5); >+ int64_t offset = fieldFromInstruction(insn, 15, 7); >+ bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0; >+ unsigned Opcode = MCInst_getOpcode(Inst); >+ bool NeedsDisjointWritebackTransfer = false; >+ >+ // offset is a 7-bit signed immediate, so sign extend it to >+ // fill the unsigned. >+ if (offset & (1 << (7 - 1))) >+ offset |= ~((1LL << 7) - 1); >+ >+ // First operand is always writeback of base register. >+ switch (Opcode) { >+ default: >+ break; >+ case AArch64_LDPXpost: >+ case AArch64_STPXpost: >+ case AArch64_LDPSWpost: >+ case AArch64_LDPXpre: >+ case AArch64_STPXpre: >+ case AArch64_LDPSWpre: >+ case AArch64_LDPWpost: >+ case AArch64_STPWpost: >+ case AArch64_LDPWpre: >+ case AArch64_STPWpre: >+ case AArch64_LDPQpost: >+ case AArch64_STPQpost: >+ case AArch64_LDPQpre: >+ case AArch64_STPQpre: >+ case AArch64_LDPDpost: >+ case AArch64_STPDpost: >+ case AArch64_LDPDpre: >+ case AArch64_STPDpre: >+ case AArch64_LDPSpost: >+ case AArch64_STPSpost: >+ case AArch64_LDPSpre: >+ case AArch64_STPSpre: >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ break; >+ } >+ >+ switch (Opcode) { >+ default: >+ return Fail; >+ case AArch64_LDPXpost: >+ case AArch64_STPXpost: >+ case AArch64_LDPSWpost: >+ case AArch64_LDPXpre: >+ case AArch64_STPXpre: >+ case AArch64_LDPSWpre: >+ NeedsDisjointWritebackTransfer = true; >+ // Fallthrough >+ case AArch64_LDNPXi: >+ case AArch64_STNPXi: >+ case AArch64_LDPXi: >+ case AArch64_STPXi: >+ case AArch64_LDPSWi: >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ case AArch64_LDPWpost: >+ case AArch64_STPWpost: >+ case AArch64_LDPWpre: >+ case AArch64_STPWpre: >+ NeedsDisjointWritebackTransfer = true; >+ // Fallthrough >+ case AArch64_LDNPWi: >+ case AArch64_STNPWi: >+ case AArch64_LDPWi: >+ case AArch64_STPWi: >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ case AArch64_LDNPQi: >+ case AArch64_STNPQi: >+ case AArch64_LDPQpost: >+ case AArch64_STPQpost: >+ case AArch64_LDPQi: >+ case AArch64_STPQi: >+ case AArch64_LDPQpre: >+ case AArch64_STPQpre: >+ DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ case AArch64_LDNPDi: >+ case AArch64_STNPDi: >+ case AArch64_LDPDpost: >+ case AArch64_STPDpost: >+ case AArch64_LDPDi: >+ case AArch64_STPDi: >+ case AArch64_LDPDpre: >+ case AArch64_STPDpre: >+ DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ case AArch64_LDNPSi: >+ case AArch64_STNPSi: >+ case AArch64_LDPSpost: >+ case AArch64_STPSpost: >+ case AArch64_LDPSi: >+ case AArch64_STPSi: >+ case AArch64_LDPSpre: >+ case AArch64_STPSpre: >+ DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); >+ break; >+ } >+ >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ MCOperand_CreateImm0(Inst, offset); >+ >+ // You shouldn't load to the same register twice in an instruction... >+ if (IsLoad && Rt == Rt2) >+ return SoftFail; >+ >+ // ... or do any operation that writes-back to a transfer register. But note >+ // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. >+ if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) >+ return SoftFail; >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd, Rn, Rm; >+ unsigned extend = fieldFromInstruction(insn, 10, 6); >+ unsigned shift = extend & 0x7; >+ >+ if (shift > 4) >+ return Fail; >+ >+ Rd = fieldFromInstruction(insn, 0, 5); >+ Rn = fieldFromInstruction(insn, 5, 5); >+ Rm = fieldFromInstruction(insn, 16, 5); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ return Fail; >+ case AArch64_ADDWrx: >+ case AArch64_SUBWrx: >+ DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ case AArch64_ADDSWrx: >+ case AArch64_SUBSWrx: >+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ case AArch64_ADDXrx: >+ case AArch64_SUBXrx: >+ DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ case AArch64_ADDSXrx: >+ case AArch64_SUBSXrx: >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ case AArch64_ADDXrx64: >+ case AArch64_SUBXrx64: >+ DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ case AArch64_SUBSXrx64: >+ case AArch64_ADDSXrx64: >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, extend); >+ return Success; >+} >+ >+static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned Datasize = fieldFromInstruction(insn, 31, 1); >+ unsigned imm; >+ >+ if (Datasize) { >+ if (MCInst_getOpcode(Inst) == AArch64_ANDSXri) >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ else >+ DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); >+ imm = fieldFromInstruction(insn, 10, 13); >+ if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) >+ return Fail; >+ } else { >+ if (MCInst_getOpcode(Inst) == AArch64_ANDSWri) >+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); >+ else >+ DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); >+ imm = fieldFromInstruction(insn, 10, 12); >+ if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) >+ return Fail; >+ } >+ >+ MCOperand_CreateImm0(Inst, imm); >+ return Success; >+} >+ >+static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned cmode = fieldFromInstruction(insn, 12, 4); >+ unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; >+ imm |= fieldFromInstruction(insn, 5, 5); >+ >+ if (MCInst_getOpcode(Inst) == AArch64_MOVID) >+ DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ else >+ DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ break; >+ case AArch64_MOVIv4i16: >+ case AArch64_MOVIv8i16: >+ case AArch64_MVNIv4i16: >+ case AArch64_MVNIv8i16: >+ case AArch64_MOVIv2i32: >+ case AArch64_MOVIv4i32: >+ case AArch64_MVNIv2i32: >+ case AArch64_MVNIv4i32: >+ MCOperand_CreateImm0(Inst, (cmode & 6) << 2); >+ break; >+ case AArch64_MOVIv2s_msl: >+ case AArch64_MOVIv4s_msl: >+ case AArch64_MVNIv2s_msl: >+ case AArch64_MVNIv4s_msl: >+ MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108); >+ break; >+ } >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned cmode = fieldFromInstruction(insn, 12, 4); >+ unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; >+ imm |= fieldFromInstruction(insn, 5, 5); >+ >+ // Tied operands added twice. >+ DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); >+ >+ MCOperand_CreateImm0(Inst, imm); >+ MCOperand_CreateImm0(Inst, (cmode & 6) << 2); >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; >+ imm |= fieldFromInstruction(insn, 29, 2); >+ >+ // Sign-extend the 21-bit immediate. >+ if (imm & (1 << (21 - 1))) >+ imm |= ~((1LL << 21) - 1); >+ >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, const void *Decoder) >+{ >+ unsigned Rd = fieldFromInstruction(insn, 0, 5); >+ unsigned Rn = fieldFromInstruction(insn, 5, 5); >+ unsigned Imm = fieldFromInstruction(insn, 10, 14); >+ unsigned S = fieldFromInstruction(insn, 29, 1); >+ unsigned Datasize = fieldFromInstruction(insn, 31, 1); >+ >+ unsigned ShifterVal = (Imm >> 12) & 3; >+ unsigned ImmVal = Imm & 0xFFF; >+ >+ if (ShifterVal != 0 && ShifterVal != 1) >+ return Fail; >+ >+ if (Datasize) { >+ if (Rd == 31 && !S) >+ DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); >+ else >+ DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); >+ } else { >+ if (Rd == 31 && !S) >+ DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); >+ else >+ DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); >+ DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); >+ } >+ >+ //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) >+ MCOperand_CreateImm0(Inst, ImmVal); >+ MCOperand_CreateImm0(Inst, 12 * ShifterVal); >+ return Success; >+} >+ >+static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, >+ const void *Decoder) >+{ >+ int64_t imm = fieldFromInstruction(insn, 0, 26); >+ >+ // Sign-extend the 26-bit immediate. >+ if (imm & (1 << (26 - 1))) >+ imm |= ~((1LL << 26) - 1); >+ >+ // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4)) >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return Success; >+} >+ >+static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, >+ uint32_t insn, uint64_t Addr, >+ const void *Decoder) >+{ >+ uint32_t op1 = fieldFromInstruction(insn, 16, 3); >+ uint32_t op2 = fieldFromInstruction(insn, 5, 3); >+ uint32_t crm = fieldFromInstruction(insn, 8, 4); >+ bool ValidNamed; >+ uint32_t pstate_field = (op1 << 3) | op2; >+ >+ MCOperand_CreateImm0(Inst, pstate_field); >+ MCOperand_CreateImm0(Inst, crm); >+ >+ A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed); >+ >+ return ValidNamed ? Success : Fail; >+} >+ >+static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, >+ uint64_t Addr, const void *Decoder) >+{ >+ uint32_t Rt = fieldFromInstruction(insn, 0, 5); >+ uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5; >+ uint32_t dst = fieldFromInstruction(insn, 5, 14); >+ >+ bit |= fieldFromInstruction(insn, 19, 5); >+ >+ // Sign-extend 14-bit immediate. >+ if (dst & (1 << (14 - 1))) >+ dst |= ~((1LL << 14) - 1); >+ >+ if (fieldFromInstruction(insn, 31, 1) == 0) >+ DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); >+ else >+ DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); >+ >+ MCOperand_CreateImm0(Inst, bit); >+ //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) >+ MCOperand_CreateImm0(Inst, dst); >+ >+ return Success; >+} >+ >+void AArch64_init(MCRegisterInfo *MRI) >+{ >+ /* >+ InitMCRegisterInfo(AArch64RegDesc, 420, >+ RA, PC, >+ AArch64MCRegisterClasses, 43, >+ AArch64RegUnitRoots, 66, AArch64RegDiffLists, >+ AArch64RegStrings, >+ AArch64SubRegIdxLists, 53, >+ AArch64SubRegIdxRanges, >+ AArch64RegEncodingTable); >+ */ >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420, >+ 0, 0, >+ AArch64MCRegisterClasses, 43, >+ 0, 0, AArch64RegDiffLists, >+ 0, >+ AArch64SubRegIdxLists, 53, >+ 0); >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.h b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..9879d7c250731d1f542cd45a3a7fae189c14b9db >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Disassembler.h >@@ -0,0 +1,20 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_AARCH64_DISASSEMBLER_H >+#define CS_AARCH64_DISASSEMBLER_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+#include "../../include/capstone.h" >+#include "../../MCRegisterInfo.h" >+#include "../../MCInst.h" >+ >+void AArch64_init(MCRegisterInfo *MRI); >+ >+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenAsmWriter.inc b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenAsmWriter.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..ac189b1837b82a7cfa95a46320641d3562758e53 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenAsmWriter.inc >@@ -0,0 +1,12607 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 2694U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 2687U, // BUNDLE >+ 2704U, // LIFETIME_START >+ 2674U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 6182U, // ABSv16i8 >+ 553920550U, // ABSv1i64 >+ 1074272294U, // ABSv2i32 >+ 1611405350U, // ABSv2i64 >+ 2148538406U, // ABSv4i16 >+ 2685671462U, // ABSv4i32 >+ 3222804518U, // ABSv8i16 >+ 3759937574U, // ABSv8i8 >+ 17049662U, // ADCSWr >+ 17049662U, // ADCSXr >+ 17048298U, // ADCWr >+ 17048298U, // ADCXr >+ 537400863U, // ADDHNv2i64_v2i32 >+ 571748634U, // ADDHNv2i64_v4i32 >+ 1074796063U, // ADDHNv4i32_v4i16 >+ 1108881690U, // ADDHNv4i32_v8i16 >+ 1644179738U, // ADDHNv8i16_v16i8 >+ 1612453407U, // ADDHNv8i16_v8i8 >+ 2147489464U, // ADDPv16i8 >+ 2684884664U, // ADDPv2i32 >+ 537663160U, // ADDPv2i64 >+ 1610884792U, // ADDPv2i64p >+ 3222279864U, // ADDPv4i16 >+ 1075058360U, // ADDPv4i32 >+ 1612191416U, // ADDPv8i16 >+ 3759937208U, // ADDPv8i8 >+ 17049674U, // ADDSWri >+ 0U, // ADDSWrr >+ 17049674U, // ADDSWrs >+ 17049674U, // ADDSWrx >+ 17049674U, // ADDSXri >+ 0U, // ADDSXrr >+ 17049674U, // ADDSXrs >+ 17049674U, // ADDSXrx >+ 17049674U, // ADDSXrx64 >+ 272671U, // ADDVv16i8v >+ 2147756319U, // ADDVv4i16v >+ 2684627231U, // ADDVv4i32v >+ 3221498143U, // ADDVv8i16v >+ 3758369055U, // ADDVv8i8v >+ 17048359U, // ADDWri >+ 0U, // ADDWrr >+ 17048359U, // ADDWrs >+ 17048359U, // ADDWrx >+ 17048359U, // ADDXri >+ 0U, // ADDXrr >+ 17048359U, // ADDXrs >+ 17048359U, // ADDXrx >+ 17048359U, // ADDXrx64 >+ 2147488551U, // ADDv16i8 >+ 17048359U, // ADDv1i64 >+ 2684883751U, // ADDv2i32 >+ 537662247U, // ADDv2i64 >+ 3222278951U, // ADDv4i16 >+ 1075057447U, // ADDv4i32 >+ 1612190503U, // ADDv8i16 >+ 3759936295U, // ADDv8i8 >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 553920403U, // ADR >+ 50603811U, // ADRP >+ 33567598U, // AESDrr >+ 33567656U, // AESErr >+ 4852U, // AESIMCrr >+ 4860U, // AESMCrr >+ 17049680U, // ANDSWri >+ 0U, // ANDSWrr >+ 17049680U, // ANDSWrs >+ 17049680U, // ANDSXri >+ 0U, // ANDSXrr >+ 17049680U, // ANDSXrs >+ 17048425U, // ANDWri >+ 0U, // ANDWrr >+ 17048425U, // ANDWrs >+ 17048425U, // ANDXri >+ 0U, // ANDXrr >+ 17048425U, // ANDXrs >+ 2147488617U, // ANDv16i8 >+ 3759936361U, // ANDv8i8 >+ 17049553U, // ASRVWr >+ 17049553U, // ASRVXr >+ 16935U, // B >+ 67380710U, // BFMWri >+ 67380710U, // BFMXri >+ 0U, // BICSWrr >+ 17049668U, // BICSWrs >+ 0U, // BICSXrr >+ 17049668U, // BICSXrs >+ 0U, // BICWrr >+ 17048303U, // BICWrs >+ 0U, // BICXrr >+ 17048303U, // BICXrs >+ 2147488495U, // BICv16i8 >+ 84423407U, // BICv2i32 >+ 84947695U, // BICv4i16 >+ 85209839U, // BICv4i32 >+ 85471983U, // BICv8i16 >+ 3759936239U, // BICv8i8 >+ 2147488704U, // BIFv16i8 >+ 3759936448U, // BIFv8i8 >+ 2181052603U, // BITv16i8 >+ 3793500347U, // BITv8i8 >+ 17641U, // BL >+ 2107319U, // BLR >+ 2107279U, // BR >+ 21688U, // BRK >+ 2181051810U, // BSLv16i8 >+ 3793499554U, // BSLv8i8 >+ 27247U, // Bcc >+ 100936257U, // CBNZW >+ 100936257U, // CBNZX >+ 100936242U, // CBZW >+ 100936242U, // CBZX >+ 17049144U, // CCMNWi >+ 17049144U, // CCMNWr >+ 17049144U, // CCMNXi >+ 17049144U, // CCMNXr >+ 17049316U, // CCMPWi >+ 17049316U, // CCMPWr >+ 17049316U, // CCMPXi >+ 17049316U, // CCMPXr >+ 2107924U, // CLREX >+ 553920604U, // CLSWr >+ 553920604U, // CLSXr >+ 6236U, // CLSv16i8 >+ 1074272348U, // CLSv2i32 >+ 2148538460U, // CLSv4i16 >+ 2685671516U, // CLSv4i32 >+ 3222804572U, // CLSv8i16 >+ 3759937628U, // CLSv8i8 >+ 553921084U, // CLZWr >+ 553921084U, // CLZXr >+ 6716U, // CLZv16i8 >+ 1074272828U, // CLZv2i32 >+ 2148538940U, // CLZv4i16 >+ 2685671996U, // CLZv4i32 >+ 3222805052U, // CLZv8i16 >+ 3759938108U, // CLZv8i8 >+ 2147489643U, // CMEQv16i8 >+ 5995U, // CMEQv16i8rz >+ 17049451U, // CMEQv1i64 >+ 553920363U, // CMEQv1i64rz >+ 2684884843U, // CMEQv2i32 >+ 1074272107U, // CMEQv2i32rz >+ 537663339U, // CMEQv2i64 >+ 1611405163U, // CMEQv2i64rz >+ 3222280043U, // CMEQv4i16 >+ 2148538219U, // CMEQv4i16rz >+ 1075058539U, // CMEQv4i32 >+ 2685671275U, // CMEQv4i32rz >+ 1612191595U, // CMEQv8i16 >+ 3222804331U, // CMEQv8i16rz >+ 3759937387U, // CMEQv8i8 >+ 3759937387U, // CMEQv8i8rz >+ 2147488636U, // CMGEv16i8 >+ 4988U, // CMGEv16i8rz >+ 17048444U, // CMGEv1i64 >+ 553919356U, // CMGEv1i64rz >+ 2684883836U, // CMGEv2i32 >+ 1074271100U, // CMGEv2i32rz >+ 537662332U, // CMGEv2i64 >+ 1611404156U, // CMGEv2i64rz >+ 3222279036U, // CMGEv4i16 >+ 2148537212U, // CMGEv4i16rz >+ 1075057532U, // CMGEv4i32 >+ 2685670268U, // CMGEv4i32rz >+ 1612190588U, // CMGEv8i16 >+ 3222803324U, // CMGEv8i16rz >+ 3759936380U, // CMGEv8i8 >+ 3759936380U, // CMGEv8i8rz >+ 2147489972U, // CMGTv16i8 >+ 6324U, // CMGTv16i8rz >+ 17049780U, // CMGTv1i64 >+ 553920692U, // CMGTv1i64rz >+ 2684885172U, // CMGTv2i32 >+ 1074272436U, // CMGTv2i32rz >+ 537663668U, // CMGTv2i64 >+ 1611405492U, // CMGTv2i64rz >+ 3222280372U, // CMGTv4i16 >+ 2148538548U, // CMGTv4i16rz >+ 1075058868U, // CMGTv4i32 >+ 2685671604U, // CMGTv4i32rz >+ 1612191924U, // CMGTv8i16 >+ 3222804660U, // CMGTv8i16rz >+ 3759937716U, // CMGTv8i8 >+ 3759937716U, // CMGTv8i8rz >+ 2147488916U, // CMHIv16i8 >+ 17048724U, // CMHIv1i64 >+ 2684884116U, // CMHIv2i32 >+ 537662612U, // CMHIv2i64 >+ 3222279316U, // CMHIv4i16 >+ 1075057812U, // CMHIv4i32 >+ 1612190868U, // CMHIv8i16 >+ 3759936660U, // CMHIv8i8 >+ 2147489878U, // CMHSv16i8 >+ 17049686U, // CMHSv1i64 >+ 2684885078U, // CMHSv2i32 >+ 537663574U, // CMHSv2i64 >+ 3222280278U, // CMHSv4i16 >+ 1075058774U, // CMHSv4i32 >+ 1612191830U, // CMHSv8i16 >+ 3759937622U, // CMHSv8i8 >+ 4995U, // CMLEv16i8rz >+ 553919363U, // CMLEv1i64rz >+ 1074271107U, // CMLEv2i32rz >+ 1611404163U, // CMLEv2i64rz >+ 2148537219U, // CMLEv4i16rz >+ 2685670275U, // CMLEv4i32rz >+ 3222803331U, // CMLEv8i16rz >+ 3759936387U, // CMLEv8i8rz >+ 6342U, // CMLTv16i8rz >+ 553920710U, // CMLTv1i64rz >+ 1074272454U, // CMLTv2i32rz >+ 1611405510U, // CMLTv2i64rz >+ 2148538566U, // CMLTv4i16rz >+ 2685671622U, // CMLTv4i32rz >+ 3222804678U, // CMLTv8i16rz >+ 3759937734U, // CMLTv8i8rz >+ 2147490013U, // CMTSTv16i8 >+ 17049821U, // CMTSTv1i64 >+ 2684885213U, // CMTSTv2i32 >+ 537663709U, // CMTSTv2i64 >+ 3222280413U, // CMTSTv4i16 >+ 1075058909U, // CMTSTv4i32 >+ 1612191965U, // CMTSTv8i16 >+ 3759937757U, // CMTSTv8i8 >+ 6348U, // CNTv16i8 >+ 3759937740U, // CNTv8i8 >+ 272763U, // CPYi16 >+ 537143675U, // CPYi32 >+ 1074014587U, // CPYi64 >+ 1610885499U, // CPYi8 >+ 17048098U, // CRC32Brr >+ 17048106U, // CRC32CBrr >+ 17048575U, // CRC32CHrr >+ 17050039U, // CRC32CWrr >+ 17050123U, // CRC32CXrr >+ 17048558U, // CRC32Hrr >+ 17050017U, // CRC32Wrr >+ 17050092U, // CRC32Xrr >+ 17048888U, // CSELWr >+ 17048888U, // CSELXr >+ 17048323U, // CSINCWr >+ 17048323U, // CSINCXr >+ 17049971U, // CSINVWr >+ 17049971U, // CSINVXr >+ 17048544U, // CSNEGWr >+ 17048544U, // CSNEGXr >+ 20524U, // DCPS1 >+ 20889U, // DCPS2 >+ 20938U, // DCPS3 >+ 29235U, // DMB >+ 2719U, // DRPS >+ 29324U, // DSB >+ 553654070U, // DUPv16i8gpr >+ 1610618678U, // DUPv16i8lane >+ 554178358U, // DUPv2i32gpr >+ 537401142U, // DUPv2i32lane >+ 554440502U, // DUPv2i64gpr >+ 1074534198U, // DUPv2i64lane >+ 554702646U, // DUPv4i16gpr >+ 1054518U, // DUPv4i16lane >+ 554964790U, // DUPv4i32gpr >+ 538187574U, // DUPv4i32lane >+ 555226934U, // DUPv8i16gpr >+ 1578806U, // DUPv8i16lane >+ 555489078U, // DUPv8i8gpr >+ 1612453686U, // DUPv8i8lane >+ 0U, // EONWrr >+ 17049150U, // EONWrs >+ 0U, // EONXrr >+ 17049150U, // EONXrs >+ 17049538U, // EORWri >+ 0U, // EORWrr >+ 17049538U, // EORWrs >+ 17049538U, // EORXri >+ 0U, // EORXrr >+ 17049538U, // EORXrs >+ 2147489730U, // EORv16i8 >+ 3759937474U, // EORv8i8 >+ 2724U, // ERET >+ 17049585U, // EXTRWrri >+ 17049585U, // EXTRXrri >+ 2147490026U, // EXTv16i8 >+ 3759937770U, // EXTv8i8 >+ 0U, // F128CSEL >+ 17048340U, // FABD32 >+ 17048340U, // FABD64 >+ 2684883732U, // FABDv2f32 >+ 537662228U, // FABDv2f64 >+ 1075057428U, // FABDv4f32 >+ 553920549U, // FABSDr >+ 553920549U, // FABSSr >+ 1074272293U, // FABSv2f32 >+ 1611405349U, // FABSv2f64 >+ 2685671461U, // FABSv4f32 >+ 17048436U, // FACGE32 >+ 17048436U, // FACGE64 >+ 2684883828U, // FACGEv2f32 >+ 537662324U, // FACGEv2f64 >+ 1075057524U, // FACGEv4f32 >+ 17049772U, // FACGT32 >+ 17049772U, // FACGT64 >+ 2684885164U, // FACGTv2f32 >+ 537663660U, // FACGTv2f64 >+ 1075058860U, // FACGTv4f32 >+ 17048358U, // FADDDrr >+ 2684884663U, // FADDPv2f32 >+ 537663159U, // FADDPv2f64 >+ 1074013879U, // FADDPv2i32p >+ 1610884791U, // FADDPv2i64p >+ 1075058359U, // FADDPv4f32 >+ 17048358U, // FADDSrr >+ 2684883750U, // FADDv2f32 >+ 537662246U, // FADDv2f64 >+ 1075057446U, // FADDv4f32 >+ 17049315U, // FCCMPDrr >+ 17048473U, // FCCMPEDrr >+ 17048473U, // FCCMPESrr >+ 17049315U, // FCCMPSrr >+ 17049450U, // FCMEQ32 >+ 17049450U, // FCMEQ64 >+ 2164533098U, // FCMEQv1i32rz >+ 2164533098U, // FCMEQv1i64rz >+ 2684884842U, // FCMEQv2f32 >+ 537663338U, // FCMEQv2f64 >+ 2684884842U, // FCMEQv2i32rz >+ 3222017898U, // FCMEQv2i64rz >+ 1075058538U, // FCMEQv4f32 >+ 3759413098U, // FCMEQv4i32rz >+ 17048443U, // FCMGE32 >+ 17048443U, // FCMGE64 >+ 2164532091U, // FCMGEv1i32rz >+ 2164532091U, // FCMGEv1i64rz >+ 2684883835U, // FCMGEv2f32 >+ 537662331U, // FCMGEv2f64 >+ 2684883835U, // FCMGEv2i32rz >+ 3222016891U, // FCMGEv2i64rz >+ 1075057531U, // FCMGEv4f32 >+ 3759412091U, // FCMGEv4i32rz >+ 17049779U, // FCMGT32 >+ 17049779U, // FCMGT64 >+ 2164533427U, // FCMGTv1i32rz >+ 2164533427U, // FCMGTv1i64rz >+ 2684885171U, // FCMGTv2f32 >+ 537663667U, // FCMGTv2f64 >+ 2684885171U, // FCMGTv2i32rz >+ 3222018227U, // FCMGTv2i64rz >+ 1075058867U, // FCMGTv4f32 >+ 3759413427U, // FCMGTv4i32rz >+ 2164532098U, // FCMLEv1i32rz >+ 2164532098U, // FCMLEv1i64rz >+ 2684883842U, // FCMLEv2i32rz >+ 3222016898U, // FCMLEv2i64rz >+ 3759412098U, // FCMLEv4i32rz >+ 2164533445U, // FCMLTv1i32rz >+ 2164533445U, // FCMLTv1i64rz >+ 2684885189U, // FCMLTv2i32rz >+ 3222018245U, // FCMLTv2i64rz >+ 3759413445U, // FCMLTv4i32rz >+ 2369258U, // FCMPDri >+ 553920234U, // FCMPDrr >+ 2368417U, // FCMPEDri >+ 553919393U, // FCMPEDrr >+ 2368417U, // FCMPESri >+ 553919393U, // FCMPESrr >+ 2369258U, // FCMPSri >+ 553920234U, // FCMPSrr >+ 17048887U, // FCSELDrrr >+ 17048887U, // FCSELSrrr >+ 553920541U, // FCVTASUWDr >+ 553920541U, // FCVTASUWSr >+ 553920541U, // FCVTASUXDr >+ 553920541U, // FCVTASUXSr >+ 553920541U, // FCVTASv1i32 >+ 553920541U, // FCVTASv1i64 >+ 1074272285U, // FCVTASv2f32 >+ 1611405341U, // FCVTASv2f64 >+ 2685671453U, // FCVTASv4f32 >+ 553920751U, // FCVTAUUWDr >+ 553920751U, // FCVTAUUWSr >+ 553920751U, // FCVTAUUXDr >+ 553920751U, // FCVTAUUXSr >+ 553920751U, // FCVTAUv1i32 >+ 553920751U, // FCVTAUv1i64 >+ 1074272495U, // FCVTAUv2f32 >+ 1611405551U, // FCVTAUv2f64 >+ 2685671663U, // FCVTAUv4f32 >+ 553920740U, // FCVTDHr >+ 553920740U, // FCVTDSr >+ 553920740U, // FCVTHDr >+ 553920740U, // FCVTHSr >+ 1074533828U, // FCVTLv2i32 >+ 2148799940U, // FCVTLv4i16 >+ 2685145352U, // FCVTLv4i32 >+ 3222540552U, // FCVTLv8i16 >+ 553920615U, // FCVTMSUWDr >+ 553920615U, // FCVTMSUWSr >+ 553920615U, // FCVTMSUXDr >+ 553920615U, // FCVTMSUXSr >+ 553920615U, // FCVTMSv1i32 >+ 553920615U, // FCVTMSv1i64 >+ 1074272359U, // FCVTMSv2f32 >+ 1611405415U, // FCVTMSv2f64 >+ 2685671527U, // FCVTMSv4f32 >+ 553920767U, // FCVTMUUWDr >+ 553920767U, // FCVTMUUWSr >+ 553920767U, // FCVTMUUXDr >+ 553920767U, // FCVTMUUXSr >+ 553920767U, // FCVTMUv1i32 >+ 553920767U, // FCVTMUv1i64 >+ 1074272511U, // FCVTMUv2f32 >+ 1611405567U, // FCVTMUv2f64 >+ 2685671679U, // FCVTMUv4f32 >+ 553920628U, // FCVTNSUWDr >+ 553920628U, // FCVTNSUWSr >+ 553920628U, // FCVTNSUXDr >+ 553920628U, // FCVTNSUXSr >+ 553920628U, // FCVTNSv1i32 >+ 553920628U, // FCVTNSv1i64 >+ 1074272372U, // FCVTNSv2f32 >+ 1611405428U, // FCVTNSv2f64 >+ 2685671540U, // FCVTNSv4f32 >+ 553920775U, // FCVTNUUWDr >+ 553920775U, // FCVTNUUWSr >+ 553920775U, // FCVTNUUXDr >+ 553920775U, // FCVTNUUXSr >+ 553920775U, // FCVTNUv1i32 >+ 553920775U, // FCVTNUv1i64 >+ 1074272519U, // FCVTNUv2f32 >+ 1611405575U, // FCVTNUv2f64 >+ 2685671687U, // FCVTNUv4f32 >+ 1611142770U, // FCVTNv2i32 >+ 2685408882U, // FCVTNv4i16 >+ 1645490510U, // FCVTNv4i32 >+ 2719494478U, // FCVTNv8i16 >+ 553920644U, // FCVTPSUWDr >+ 553920644U, // FCVTPSUWSr >+ 553920644U, // FCVTPSUXDr >+ 553920644U, // FCVTPSUXSr >+ 553920644U, // FCVTPSv1i32 >+ 553920644U, // FCVTPSv1i64 >+ 1074272388U, // FCVTPSv2f32 >+ 1611405444U, // FCVTPSv2f64 >+ 2685671556U, // FCVTPSv4f32 >+ 553920783U, // FCVTPUUWDr >+ 553920783U, // FCVTPUUWSr >+ 553920783U, // FCVTPUUXDr >+ 553920783U, // FCVTPUUXSr >+ 553920783U, // FCVTPUv1i32 >+ 553920783U, // FCVTPUv1i64 >+ 1074272527U, // FCVTPUv2f32 >+ 1611405583U, // FCVTPUv2f64 >+ 2685671695U, // FCVTPUv4f32 >+ 553920740U, // FCVTSDr >+ 553920740U, // FCVTSHr >+ 553920168U, // FCVTXNv1i64 >+ 1611142824U, // FCVTXNv2f32 >+ 1645490564U, // FCVTXNv4f32 >+ 17049759U, // FCVTZSSWDri >+ 17049759U, // FCVTZSSWSri >+ 17049759U, // FCVTZSSXDri >+ 17049759U, // FCVTZSSXSri >+ 553920671U, // FCVTZSUWDr >+ 553920671U, // FCVTZSUWSr >+ 553920671U, // FCVTZSUXDr >+ 553920671U, // FCVTZSUXSr >+ 17049759U, // FCVTZS_IntSWDri >+ 17049759U, // FCVTZS_IntSWSri >+ 17049759U, // FCVTZS_IntSXDri >+ 17049759U, // FCVTZS_IntSXSri >+ 553920671U, // FCVTZS_IntUWDr >+ 553920671U, // FCVTZS_IntUWSr >+ 553920671U, // FCVTZS_IntUXDr >+ 553920671U, // FCVTZS_IntUXSr >+ 1074272415U, // FCVTZS_Intv2f32 >+ 1611405471U, // FCVTZS_Intv2f64 >+ 2685671583U, // FCVTZS_Intv4f32 >+ 17049759U, // FCVTZSd >+ 17049759U, // FCVTZSs >+ 553920671U, // FCVTZSv1i32 >+ 553920671U, // FCVTZSv1i64 >+ 1074272415U, // FCVTZSv2f32 >+ 1611405471U, // FCVTZSv2f64 >+ 2684885151U, // FCVTZSv2i32_shift >+ 537663647U, // FCVTZSv2i64_shift >+ 2685671583U, // FCVTZSv4f32 >+ 1075058847U, // FCVTZSv4i32_shift >+ 17049879U, // FCVTZUSWDri >+ 17049879U, // FCVTZUSWSri >+ 17049879U, // FCVTZUSXDri >+ 17049879U, // FCVTZUSXSri >+ 553920791U, // FCVTZUUWDr >+ 553920791U, // FCVTZUUWSr >+ 553920791U, // FCVTZUUXDr >+ 553920791U, // FCVTZUUXSr >+ 17049879U, // FCVTZU_IntSWDri >+ 17049879U, // FCVTZU_IntSWSri >+ 17049879U, // FCVTZU_IntSXDri >+ 17049879U, // FCVTZU_IntSXSri >+ 553920791U, // FCVTZU_IntUWDr >+ 553920791U, // FCVTZU_IntUWSr >+ 553920791U, // FCVTZU_IntUXDr >+ 553920791U, // FCVTZU_IntUXSr >+ 1074272535U, // FCVTZU_Intv2f32 >+ 1611405591U, // FCVTZU_Intv2f64 >+ 2685671703U, // FCVTZU_Intv4f32 >+ 17049879U, // FCVTZUd >+ 17049879U, // FCVTZUs >+ 553920791U, // FCVTZUv1i32 >+ 553920791U, // FCVTZUv1i64 >+ 1074272535U, // FCVTZUv2f32 >+ 1611405591U, // FCVTZUv2f64 >+ 2684885271U, // FCVTZUv2i32_shift >+ 537663767U, // FCVTZUv2i64_shift >+ 2685671703U, // FCVTZUv4f32 >+ 1075058967U, // FCVTZUv4i32_shift >+ 17049898U, // FDIVDrr >+ 17049898U, // FDIVSrr >+ 2684885290U, // FDIVv2f32 >+ 537663786U, // FDIVv2f64 >+ 1075058986U, // FDIVv4f32 >+ 17048394U, // FMADDDrrr >+ 17048394U, // FMADDSrrr >+ 17050100U, // FMAXDrr >+ 17049087U, // FMAXNMDrr >+ 2684884729U, // FMAXNMPv2f32 >+ 537663225U, // FMAXNMPv2f64 >+ 1074013945U, // FMAXNMPv2i32p >+ 1610884857U, // FMAXNMPv2i64p >+ 1075058425U, // FMAXNMPv4f32 >+ 17049087U, // FMAXNMSrr >+ 2684627285U, // FMAXNMVv4i32v >+ 2684884479U, // FMAXNMv2f32 >+ 537662975U, // FMAXNMv2f64 >+ 1075058175U, // FMAXNMv4f32 >+ 2684884802U, // FMAXPv2f32 >+ 537663298U, // FMAXPv2f64 >+ 1074014018U, // FMAXPv2i32p >+ 1610884930U, // FMAXPv2i64p >+ 1075058498U, // FMAXPv4f32 >+ 17050100U, // FMAXSrr >+ 2684627340U, // FMAXVv4i32v >+ 2684885492U, // FMAXv2f32 >+ 537663988U, // FMAXv2f64 >+ 1075059188U, // FMAXv4f32 >+ 17049126U, // FMINDrr >+ 17049079U, // FMINNMDrr >+ 2684884720U, // FMINNMPv2f32 >+ 537663216U, // FMINNMPv2f64 >+ 1074013936U, // FMINNMPv2i32p >+ 1610884848U, // FMINNMPv2i64p >+ 1075058416U, // FMINNMPv4f32 >+ 17049079U, // FMINNMSrr >+ 2684627276U, // FMINNMVv4i32v >+ 2684884471U, // FMINNMv2f32 >+ 537662967U, // FMINNMv2f64 >+ 1075058167U, // FMINNMv4f32 >+ 2684884744U, // FMINPv2f32 >+ 537663240U, // FMINPv2f64 >+ 1074013960U, // FMINPv2i32p >+ 1610884872U, // FMINPv2i64p >+ 1075058440U, // FMINPv4f32 >+ 17049126U, // FMINSrr >+ 2684627294U, // FMINVv4i32v >+ 2684884518U, // FMINv2f32 >+ 537663014U, // FMINv2f64 >+ 1075058214U, // FMINv4f32 >+ 67404282U, // FMLAv1i32_indexed >+ 67404282U, // FMLAv1i64_indexed >+ 2718446074U, // FMLAv2f32 >+ 571224570U, // FMLAv2f64 >+ 2718446074U, // FMLAv2i32_indexed >+ 571224570U, // FMLAv2i64_indexed >+ 1108619770U, // FMLAv4f32 >+ 1108619770U, // FMLAv4i32_indexed >+ 67405921U, // FMLSv1i32_indexed >+ 67405921U, // FMLSv1i64_indexed >+ 2718447713U, // FMLSv2f32 >+ 571226209U, // FMLSv2f64 >+ 2718447713U, // FMLSv2i32_indexed >+ 571226209U, // FMLSv2i64_indexed >+ 1108621409U, // FMLSv4f32 >+ 1108621409U, // FMLSv4i32_indexed >+ 1074014586U, // FMOVDXHighr >+ 553920890U, // FMOVDXr >+ 117713274U, // FMOVDi >+ 553920890U, // FMOVDr >+ 553920890U, // FMOVSWr >+ 117713274U, // FMOVSi >+ 553920890U, // FMOVSr >+ 553920890U, // FMOVWSr >+ 556276090U, // FMOVXDHighr >+ 553920890U, // FMOVXDr >+ 117971322U, // FMOVv2f32_ns >+ 118233466U, // FMOVv2f64_ns >+ 118757754U, // FMOVv4f32_ns >+ 17048257U, // FMSUBDrrr >+ 17048257U, // FMSUBSrrr >+ 17049035U, // FMULDrr >+ 17049035U, // FMULSrr >+ 17050139U, // FMULX32 >+ 17050139U, // FMULX64 >+ 17050139U, // FMULXv1i32_indexed >+ 17050139U, // FMULXv1i64_indexed >+ 2684885531U, // FMULXv2f32 >+ 537664027U, // FMULXv2f64 >+ 2684885531U, // FMULXv2i32_indexed >+ 537664027U, // FMULXv2i64_indexed >+ 1075059227U, // FMULXv4f32 >+ 1075059227U, // FMULXv4i32_indexed >+ 17049035U, // FMULv1i32_indexed >+ 17049035U, // FMULv1i64_indexed >+ 2684884427U, // FMULv2f32 >+ 537662923U, // FMULv2f64 >+ 2684884427U, // FMULv2i32_indexed >+ 537662923U, // FMULv2i64_indexed >+ 1075058123U, // FMULv4f32 >+ 1075058123U, // FMULv4i32_indexed >+ 553919443U, // FNEGDr >+ 553919443U, // FNEGSr >+ 1074271187U, // FNEGv2f32 >+ 1611404243U, // FNEGv2f64 >+ 2685670355U, // FNEGv4f32 >+ 17048401U, // FNMADDDrrr >+ 17048401U, // FNMADDSrrr >+ 17048264U, // FNMSUBDrrr >+ 17048264U, // FNMSUBSrrr >+ 17049041U, // FNMULDrr >+ 17049041U, // FNMULSrr >+ 553919369U, // FRECPEv1i32 >+ 553919369U, // FRECPEv1i64 >+ 1074271113U, // FRECPEv2f32 >+ 1611404169U, // FRECPEv2f64 >+ 2685670281U, // FRECPEv4f32 >+ 17049724U, // FRECPS32 >+ 17049724U, // FRECPS64 >+ 2684885116U, // FRECPSv2f32 >+ 537663612U, // FRECPSv2f64 >+ 1075058812U, // FRECPSv4f32 >+ 553921058U, // FRECPXv1i32 >+ 553921058U, // FRECPXv1i64 >+ 553919002U, // FRINTADr >+ 553919002U, // FRINTASr >+ 1074270746U, // FRINTAv2f32 >+ 1611403802U, // FRINTAv2f64 >+ 2685669914U, // FRINTAv4f32 >+ 553919658U, // FRINTIDr >+ 553919658U, // FRINTISr >+ 1074271402U, // FRINTIv2f32 >+ 1611404458U, // FRINTIv2f64 >+ 2685670570U, // FRINTIv4f32 >+ 553920007U, // FRINTMDr >+ 553920007U, // FRINTMSr >+ 1074271751U, // FRINTMv2f32 >+ 1611404807U, // FRINTMv2f64 >+ 2685670919U, // FRINTMv4f32 >+ 553920106U, // FRINTNDr >+ 553920106U, // FRINTNSr >+ 1074271850U, // FRINTNv2f32 >+ 1611404906U, // FRINTNv2f64 >+ 2685671018U, // FRINTNv4f32 >+ 553920297U, // FRINTPDr >+ 553920297U, // FRINTPSr >+ 1074272041U, // FRINTPv2f32 >+ 1611405097U, // FRINTPv2f64 >+ 2685671209U, // FRINTPv4f32 >+ 553921066U, // FRINTXDr >+ 553921066U, // FRINTXSr >+ 1074272810U, // FRINTXv2f32 >+ 1611405866U, // FRINTXv2f64 >+ 2685671978U, // FRINTXv4f32 >+ 553921101U, // FRINTZDr >+ 553921101U, // FRINTZSr >+ 1074272845U, // FRINTZv2f32 >+ 1611405901U, // FRINTZv2f64 >+ 2685672013U, // FRINTZv4f32 >+ 553919406U, // FRSQRTEv1i32 >+ 553919406U, // FRSQRTEv1i64 >+ 1074271150U, // FRSQRTEv2f32 >+ 1611404206U, // FRSQRTEv2f64 >+ 2685670318U, // FRSQRTEv4f32 >+ 17049745U, // FRSQRTS32 >+ 17049745U, // FRSQRTS64 >+ 2684885137U, // FRSQRTSv2f32 >+ 537663633U, // FRSQRTSv2f64 >+ 1075058833U, // FRSQRTSv4f32 >+ 553920726U, // FSQRTDr >+ 553920726U, // FSQRTSr >+ 1074272470U, // FSQRTv2f32 >+ 1611405526U, // FSQRTv2f64 >+ 2685671638U, // FSQRTv4f32 >+ 17048237U, // FSUBDrr >+ 17048237U, // FSUBSrr >+ 2684883629U, // FSUBv2f32 >+ 537662125U, // FSUBv2f64 >+ 1075057325U, // FSUBv4f32 >+ 23145U, // HINT >+ 22720U, // HLT >+ 21258U, // HVC >+ 137115759U, // INSvi16gpr >+ 153892975U, // INSvi16lane >+ 137377903U, // INSvi32gpr >+ 691026031U, // INSvi32lane >+ 136853615U, // INSvi64gpr >+ 1227372655U, // INSvi64lane >+ 137640047U, // INSvi8gpr >+ 1765029999U, // INSvi8lane >+ 29329U, // ISB >+ 36885U, // LD1Fourv16b >+ 3710997U, // LD1Fourv16b_POST >+ 45077U, // LD1Fourv1d >+ 3981333U, // LD1Fourv1d_POST >+ 53269U, // LD1Fourv2d >+ 3727381U, // LD1Fourv2d_POST >+ 61461U, // LD1Fourv2s >+ 3997717U, // LD1Fourv2s_POST >+ 69653U, // LD1Fourv4h >+ 4005909U, // LD1Fourv4h_POST >+ 77845U, // LD1Fourv4s >+ 3751957U, // LD1Fourv4s_POST >+ 86037U, // LD1Fourv8b >+ 4022293U, // LD1Fourv8b_POST >+ 94229U, // LD1Fourv8h >+ 3768341U, // LD1Fourv8h_POST >+ 36885U, // LD1Onev16b >+ 4235285U, // LD1Onev16b_POST >+ 45077U, // LD1Onev1d >+ 4505621U, // LD1Onev1d_POST >+ 53269U, // LD1Onev2d >+ 4251669U, // LD1Onev2d_POST >+ 61461U, // LD1Onev2s >+ 4522005U, // LD1Onev2s_POST >+ 69653U, // LD1Onev4h >+ 4530197U, // LD1Onev4h_POST >+ 77845U, // LD1Onev4s >+ 4276245U, // LD1Onev4s_POST >+ 86037U, // LD1Onev8b >+ 4546581U, // LD1Onev8b_POST >+ 94229U, // LD1Onev8h >+ 4292629U, // LD1Onev8h_POST >+ 38769U, // LD1Rv16b >+ 4761457U, // LD1Rv16b_POST >+ 46961U, // LD1Rv1d >+ 4507505U, // LD1Rv1d_POST >+ 55153U, // LD1Rv2d >+ 4515697U, // LD1Rv2d_POST >+ 63345U, // LD1Rv2s >+ 5048177U, // LD1Rv2s_POST >+ 71537U, // LD1Rv4h >+ 5318513U, // LD1Rv4h_POST >+ 79729U, // LD1Rv4s >+ 5064561U, // LD1Rv4s_POST >+ 87921U, // LD1Rv8b >+ 4810609U, // LD1Rv8b_POST >+ 96113U, // LD1Rv8h >+ 5343089U, // LD1Rv8h_POST >+ 36885U, // LD1Threev16b >+ 5546005U, // LD1Threev16b_POST >+ 45077U, // LD1Threev1d >+ 5816341U, // LD1Threev1d_POST >+ 53269U, // LD1Threev2d >+ 5562389U, // LD1Threev2d_POST >+ 61461U, // LD1Threev2s >+ 5832725U, // LD1Threev2s_POST >+ 69653U, // LD1Threev4h >+ 5840917U, // LD1Threev4h_POST >+ 77845U, // LD1Threev4s >+ 5586965U, // LD1Threev4s_POST >+ 86037U, // LD1Threev8b >+ 5857301U, // LD1Threev8b_POST >+ 94229U, // LD1Threev8h >+ 5603349U, // LD1Threev8h_POST >+ 36885U, // LD1Twov16b >+ 3973141U, // LD1Twov16b_POST >+ 45077U, // LD1Twov1d >+ 4243477U, // LD1Twov1d_POST >+ 53269U, // LD1Twov2d >+ 3989525U, // LD1Twov2d_POST >+ 61461U, // LD1Twov2s >+ 4259861U, // LD1Twov2s_POST >+ 69653U, // LD1Twov4h >+ 4268053U, // LD1Twov4h_POST >+ 77845U, // LD1Twov4s >+ 4014101U, // LD1Twov4s_POST >+ 86037U, // LD1Twov8b >+ 4284437U, // LD1Twov8b_POST >+ 94229U, // LD1Twov8h >+ 4030485U, // LD1Twov8h_POST >+ 6131733U, // LD1i16 >+ 6397973U, // LD1i16_POST >+ 6139925U, // LD1i32 >+ 6668309U, // LD1i32_POST >+ 6148117U, // LD1i64 >+ 6938645U, // LD1i64_POST >+ 6156309U, // LD1i8 >+ 7208981U, // LD1i8_POST >+ 38775U, // LD2Rv16b >+ 5285751U, // LD2Rv16b_POST >+ 46967U, // LD2Rv1d >+ 4245367U, // LD2Rv1d_POST >+ 55159U, // LD2Rv2d >+ 4253559U, // LD2Rv2d_POST >+ 63351U, // LD2Rv2s >+ 4523895U, // LD2Rv2s_POST >+ 71543U, // LD2Rv4h >+ 5056375U, // LD2Rv4h_POST >+ 79735U, // LD2Rv4s >+ 4540279U, // LD2Rv4s_POST >+ 87927U, // LD2Rv8b >+ 5334903U, // LD2Rv8b_POST >+ 96119U, // LD2Rv8h >+ 5080951U, // LD2Rv8h_POST >+ 36947U, // LD2Twov16b >+ 3973203U, // LD2Twov16b_POST >+ 53331U, // LD2Twov2d >+ 3989587U, // LD2Twov2d_POST >+ 61523U, // LD2Twov2s >+ 4259923U, // LD2Twov2s_POST >+ 69715U, // LD2Twov4h >+ 4268115U, // LD2Twov4h_POST >+ 77907U, // LD2Twov4s >+ 4014163U, // LD2Twov4s_POST >+ 86099U, // LD2Twov8b >+ 4284499U, // LD2Twov8b_POST >+ 94291U, // LD2Twov8h >+ 4030547U, // LD2Twov8h_POST >+ 6131795U, // LD2i16 >+ 6660179U, // LD2i16_POST >+ 6139987U, // LD2i32 >+ 6930515U, // LD2i32_POST >+ 6148179U, // LD2i64 >+ 7462995U, // LD2i64_POST >+ 6156371U, // LD2i8 >+ 6422611U, // LD2i8_POST >+ 38781U, // LD3Rv16b >+ 7645053U, // LD3Rv16b_POST >+ 46973U, // LD3Rv1d >+ 5818237U, // LD3Rv1d_POST >+ 55165U, // LD3Rv2d >+ 5826429U, // LD3Rv2d_POST >+ 63357U, // LD3Rv2s >+ 7931773U, // LD3Rv2s_POST >+ 71549U, // LD3Rv4h >+ 8202109U, // LD3Rv4h_POST >+ 79741U, // LD3Rv4s >+ 7948157U, // LD3Rv4s_POST >+ 87933U, // LD3Rv8b >+ 7694205U, // LD3Rv8b_POST >+ 96125U, // LD3Rv8h >+ 8226685U, // LD3Rv8h_POST >+ 37317U, // LD3Threev16b >+ 5546437U, // LD3Threev16b_POST >+ 53701U, // LD3Threev2d >+ 5562821U, // LD3Threev2d_POST >+ 61893U, // LD3Threev2s >+ 5833157U, // LD3Threev2s_POST >+ 70085U, // LD3Threev4h >+ 5841349U, // LD3Threev4h_POST >+ 78277U, // LD3Threev4s >+ 5587397U, // LD3Threev4s_POST >+ 86469U, // LD3Threev8b >+ 5857733U, // LD3Threev8b_POST >+ 94661U, // LD3Threev8h >+ 5603781U, // LD3Threev8h_POST >+ 6132165U, // LD3i16 >+ 8495557U, // LD3i16_POST >+ 6140357U, // LD3i32 >+ 8765893U, // LD3i32_POST >+ 6148549U, // LD3i64 >+ 9036229U, // LD3i64_POST >+ 6156741U, // LD3i8 >+ 9306565U, // LD3i8_POST >+ 37341U, // LD4Fourv16b >+ 3711453U, // LD4Fourv16b_POST >+ 53725U, // LD4Fourv2d >+ 3727837U, // LD4Fourv2d_POST >+ 61917U, // LD4Fourv2s >+ 3998173U, // LD4Fourv2s_POST >+ 70109U, // LD4Fourv4h >+ 4006365U, // LD4Fourv4h_POST >+ 78301U, // LD4Fourv4s >+ 3752413U, // LD4Fourv4s_POST >+ 86493U, // LD4Fourv8b >+ 4022749U, // LD4Fourv8b_POST >+ 94685U, // LD4Fourv8h >+ 3768797U, // LD4Fourv8h_POST >+ 38787U, // LD4Rv16b >+ 5023619U, // LD4Rv16b_POST >+ 46979U, // LD4Rv1d >+ 3983235U, // LD4Rv1d_POST >+ 55171U, // LD4Rv2d >+ 3991427U, // LD4Rv2d_POST >+ 63363U, // LD4Rv2s >+ 4261763U, // LD4Rv2s_POST >+ 71555U, // LD4Rv4h >+ 4532099U, // LD4Rv4h_POST >+ 79747U, // LD4Rv4s >+ 4278147U, // LD4Rv4s_POST >+ 87939U, // LD4Rv8b >+ 5072771U, // LD4Rv8b_POST >+ 96131U, // LD4Rv8h >+ 4556675U, // LD4Rv8h_POST >+ 6132189U, // LD4i16 >+ 6922717U, // LD4i16_POST >+ 6140381U, // LD4i32 >+ 7455197U, // LD4i32_POST >+ 6148573U, // LD4i64 >+ 9560541U, // LD4i64_POST >+ 6156765U, // LD4i8 >+ 6685149U, // LD4i8_POST >+ 26485304U, // LDARB >+ 26485801U, // LDARH >+ 26486665U, // LDARW >+ 26486665U, // LDARX >+ 553920315U, // LDAXPW >+ 553920315U, // LDAXPX >+ 26485358U, // LDAXRB >+ 26485855U, // LDAXRH >+ 26486787U, // LDAXRW >+ 26486787U, // LDAXRX >+ 553920258U, // LDNPDi >+ 553920258U, // LDNPQi >+ 553920258U, // LDNPSi >+ 553920258U, // LDNPWi >+ 553920258U, // LDNPXi >+ 553920190U, // LDPDi >+ 604276414U, // LDPDpost >+ 604276414U, // LDPDpre >+ 553920190U, // LDPQi >+ 604276414U, // LDPQpost >+ 604276414U, // LDPQpre >+ 553920974U, // LDPSWi >+ 604277198U, // LDPSWpost >+ 604277198U, // LDPSWpre >+ 553920190U, // LDPSi >+ 604276414U, // LDPSpost >+ 604276414U, // LDPSpre >+ 553920190U, // LDPWi >+ 604276414U, // LDPWpost >+ 604276414U, // LDPWpre >+ 553920190U, // LDPXi >+ 604276414U, // LDPXpost >+ 604276414U, // LDPXpre >+ 1150583359U, // LDRBBpost >+ 76841535U, // LDRBBpre >+ 26485311U, // LDRBBroW >+ 26485311U, // LDRBBroX >+ 26485311U, // LDRBBui >+ 1150584728U, // LDRBpost >+ 76842904U, // LDRBpre >+ 26486680U, // LDRBroW >+ 26486680U, // LDRBroX >+ 26486680U, // LDRBui >+ 100935576U, // LDRDl >+ 1150584728U, // LDRDpost >+ 76842904U, // LDRDpre >+ 26486680U, // LDRDroW >+ 26486680U, // LDRDroX >+ 26486680U, // LDRDui >+ 1150583856U, // LDRHHpost >+ 76842032U, // LDRHHpre >+ 26485808U, // LDRHHroW >+ 26485808U, // LDRHHroX >+ 26485808U, // LDRHHui >+ 1150584728U, // LDRHpost >+ 76842904U, // LDRHpre >+ 26486680U, // LDRHroW >+ 26486680U, // LDRHroX >+ 26486680U, // LDRHui >+ 100935576U, // LDRQl >+ 1150584728U, // LDRQpost >+ 76842904U, // LDRQpre >+ 26486680U, // LDRQroW >+ 26486680U, // LDRQroX >+ 26486680U, // LDRQui >+ 1150583446U, // LDRSBWpost >+ 76841622U, // LDRSBWpre >+ 26485398U, // LDRSBWroW >+ 26485398U, // LDRSBWroX >+ 26485398U, // LDRSBWui >+ 1150583446U, // LDRSBXpost >+ 76841622U, // LDRSBXpre >+ 26485398U, // LDRSBXroW >+ 26485398U, // LDRSBXroX >+ 26485398U, // LDRSBXui >+ 1150583933U, // LDRSHWpost >+ 76842109U, // LDRSHWpre >+ 26485885U, // LDRSHWroW >+ 26485885U, // LDRSHWroX >+ 26485885U, // LDRSHWui >+ 1150583933U, // LDRSHXpost >+ 76842109U, // LDRSHXpre >+ 26485885U, // LDRSHXroW >+ 26485885U, // LDRSHXroX >+ 26485885U, // LDRSHXui >+ 100936149U, // LDRSWl >+ 1150585301U, // LDRSWpost >+ 76843477U, // LDRSWpre >+ 26487253U, // LDRSWroW >+ 26487253U, // LDRSWroX >+ 26487253U, // LDRSWui >+ 100935576U, // LDRSl >+ 1150584728U, // LDRSpost >+ 76842904U, // LDRSpre >+ 26486680U, // LDRSroW >+ 26486680U, // LDRSroX >+ 26486680U, // LDRSui >+ 100935576U, // LDRWl >+ 1150584728U, // LDRWpost >+ 76842904U, // LDRWpre >+ 26486680U, // LDRWroW >+ 26486680U, // LDRWroX >+ 26486680U, // LDRWui >+ 100935576U, // LDRXl >+ 1150584728U, // LDRXpost >+ 76842904U, // LDRXpre >+ 26486680U, // LDRXroW >+ 26486680U, // LDRXroX >+ 26486680U, // LDRXui >+ 26485324U, // LDTRBi >+ 26485821U, // LDTRHi >+ 26485405U, // LDTRSBWi >+ 26485405U, // LDTRSBXi >+ 26485892U, // LDTRSHWi >+ 26485892U, // LDTRSHXi >+ 26487260U, // LDTRSWi >+ 26486752U, // LDTRWi >+ 26486752U, // LDTRXi >+ 26485344U, // LDURBBi >+ 26486775U, // LDURBi >+ 26486775U, // LDURDi >+ 26485841U, // LDURHHi >+ 26486775U, // LDURHi >+ 26486775U, // LDURQi >+ 26485413U, // LDURSBWi >+ 26485413U, // LDURSBXi >+ 26485900U, // LDURSHWi >+ 26485900U, // LDURSHXi >+ 26487268U, // LDURSWi >+ 26486775U, // LDURSi >+ 26486775U, // LDURWi >+ 26486775U, // LDURXi >+ 553920343U, // LDXPW >+ 553920343U, // LDXPX >+ 26485366U, // LDXRB >+ 26485863U, // LDXRH >+ 26486794U, // LDXRW >+ 26486794U, // LDXRX >+ 0U, // LOADgot >+ 17049003U, // LSLVWr >+ 17049003U, // LSLVXr >+ 17049558U, // LSRVWr >+ 17049558U, // LSRVXr >+ 17048395U, // MADDWrrr >+ 17048395U, // MADDXrrr >+ 2181050875U, // MLAv16i8 >+ 2718446075U, // MLAv2i32 >+ 2718446075U, // MLAv2i32_indexed >+ 3255841275U, // MLAv4i16 >+ 3255841275U, // MLAv4i16_indexed >+ 1108619771U, // MLAv4i32 >+ 1108619771U, // MLAv4i32_indexed >+ 1645752827U, // MLAv8i16 >+ 1645752827U, // MLAv8i16_indexed >+ 3793498619U, // MLAv8i8 >+ 2181052514U, // MLSv16i8 >+ 2718447714U, // MLSv2i32 >+ 2718447714U, // MLSv2i32_indexed >+ 3255842914U, // MLSv4i16 >+ 3255842914U, // MLSv4i16_indexed >+ 1108621410U, // MLSv4i32 >+ 1108621410U, // MLSv4i32_indexed >+ 1645754466U, // MLSv8i16 >+ 1645754466U, // MLSv8i16_indexed >+ 3793500258U, // MLSv8i8 >+ 168043698U, // MOVID >+ 721425586U, // MOVIv16b_ns >+ 168563890U, // MOVIv2d_ns >+ 1795691698U, // MOVIv2i32 >+ 1795691698U, // MOVIv2s_msl >+ 1796215986U, // MOVIv4i16 >+ 1796478130U, // MOVIv4i32 >+ 1796478130U, // MOVIv4s_msl >+ 723260594U, // MOVIv8b_ns >+ 1796740274U, // MOVIv8i16 >+ 84157629U, // MOVKWi >+ 84157629U, // MOVKXi >+ 1795434146U, // MOVNWi >+ 1795434146U, // MOVNXi >+ 1795435093U, // MOVZWi >+ 1795435093U, // MOVZXi >+ 0U, // MOVaddr >+ 0U, // MOVaddrBA >+ 0U, // MOVaddrCP >+ 0U, // MOVaddrEXT >+ 0U, // MOVaddrJT >+ 0U, // MOVaddrTLS >+ 0U, // MOVi32imm >+ 0U, // MOVi64imm >+ 201599116U, // MRS >+ 137179U, // MSR >+ 141275U, // MSRpstate >+ 17048258U, // MSUBWrrr >+ 17048258U, // MSUBXrrr >+ 2147489228U, // MULv16i8 >+ 2684884428U, // MULv2i32 >+ 2684884428U, // MULv2i32_indexed >+ 3222279628U, // MULv4i16 >+ 3222279628U, // MULv4i16_indexed >+ 1075058124U, // MULv4i32 >+ 1075058124U, // MULv4i32_indexed >+ 1612191180U, // MULv8i16 >+ 1612191180U, // MULv8i16_indexed >+ 3759936972U, // MULv8i8 >+ 1795691679U, // MVNIv2i32 >+ 1795691679U, // MVNIv2s_msl >+ 1796215967U, // MVNIv4i16 >+ 1796478111U, // MVNIv4i32 >+ 1796478111U, // MVNIv4s_msl >+ 1796740255U, // MVNIv8i16 >+ 5076U, // NEGv16i8 >+ 553919444U, // NEGv1i64 >+ 1074271188U, // NEGv2i32 >+ 1611404244U, // NEGv2i64 >+ 2148537300U, // NEGv4i16 >+ 2685670356U, // NEGv4i32 >+ 3222803412U, // NEGv8i16 >+ 3759936468U, // NEGv8i8 >+ 6353U, // NOTv16i8 >+ 3759937745U, // NOTv8i8 >+ 0U, // ORNWrr >+ 17049189U, // ORNWrs >+ 0U, // ORNXrr >+ 17049189U, // ORNXrs >+ 2147489381U, // ORNv16i8 >+ 3759937125U, // ORNv8i8 >+ 17049548U, // ORRWri >+ 0U, // ORRWrr >+ 17049548U, // ORRWrs >+ 17049548U, // ORRXri >+ 0U, // ORRXrr >+ 17049548U, // ORRXrs >+ 2147489740U, // ORRv16i8 >+ 84424652U, // ORRv2i32 >+ 84948940U, // ORRv4i16 >+ 85211084U, // ORRv4i32 >+ 85473228U, // ORRv8i16 >+ 3759937484U, // ORRv8i8 >+ 2149060822U, // PMULLv16i8 >+ 228070797U, // PMULLv1i64 >+ 244846806U, // PMULLv2i64 >+ 3759674765U, // PMULLv8i8 >+ 2147489240U, // PMULv16i8 >+ 3759936984U, // PMULv8i8 >+ 101070321U, // PRFMl >+ 26621425U, // PRFMroW >+ 26621425U, // PRFMroX >+ 26621425U, // PRFMui >+ 26621455U, // PRFUMi >+ 537400862U, // RADDHNv2i64_v2i32 >+ 571748633U, // RADDHNv2i64_v4i32 >+ 1074796062U, // RADDHNv4i32_v4i16 >+ 1108881689U, // RADDHNv4i32_v8i16 >+ 1644179737U, // RADDHNv8i16_v16i8 >+ 1612453406U, // RADDHNv8i16_v8i8 >+ 553920698U, // RBITWr >+ 553920698U, // RBITXr >+ 6330U, // RBITv16i8 >+ 3759937722U, // RBITv8i8 >+ 2107559U, // RET >+ 0U, // RET_ReallyLR >+ 553918951U, // REV16Wr >+ 553918951U, // REV16Xr >+ 4583U, // REV16v16i8 >+ 3759935975U, // REV16v8i8 >+ 553918540U, // REV32Xr >+ 4172U, // REV32v16i8 >+ 2148536396U, // REV32v4i16 >+ 3222802508U, // REV32v8i16 >+ 3759935564U, // REV32v8i8 >+ 4566U, // REV64v16i8 >+ 1074270678U, // REV64v2i32 >+ 2148536790U, // REV64v4i16 >+ 2685669846U, // REV64v4i32 >+ 3222802902U, // REV64v8i16 >+ 3759935958U, // REV64v8i8 >+ 553920805U, // REVWr >+ 553920805U, // REVXr >+ 17049543U, // RORVWr >+ 17049543U, // RORVXr >+ 1644179766U, // RSHRNv16i8_shift >+ 537400917U, // RSHRNv2i32_shift >+ 1074796117U, // RSHRNv4i16_shift >+ 571748662U, // RSHRNv4i32_shift >+ 1108881718U, // RSHRNv8i16_shift >+ 1612453461U, // RSHRNv8i8_shift >+ 537400854U, // RSUBHNv2i64_v2i32 >+ 571748624U, // RSUBHNv2i64_v4i32 >+ 1074796054U, // RSUBHNv4i32_v4i16 >+ 1108881680U, // RSUBHNv4i32_v8i16 >+ 1644179728U, // RSUBHNv8i16_v16i8 >+ 1612453398U, // RSUBHNv8i16_v8i8 >+ 2182623330U, // SABALv16i8_v8i16 >+ 2718708931U, // SABALv2i32_v2i64 >+ 3256104131U, // SABALv4i16_v4i32 >+ 1108095074U, // SABALv4i32_v2i64 >+ 1645490274U, // SABALv8i16_v4i32 >+ 3793237187U, // SABALv8i8_v8i16 >+ 2181050862U, // SABAv16i8 >+ 2718446062U, // SABAv2i32 >+ 3255841262U, // SABAv4i16 >+ 1108619758U, // SABAv4i32 >+ 1645752814U, // SABAv8i16 >+ 3793498606U, // SABAv8i8 >+ 2149060764U, // SABDLv16i8_v8i16 >+ 2685146379U, // SABDLv2i32_v2i64 >+ 3222541579U, // SABDLv4i16_v4i32 >+ 1074532508U, // SABDLv4i32_v2i64 >+ 1611927708U, // SABDLv8i16_v4i32 >+ 3759674635U, // SABDLv8i8_v8i16 >+ 2147488538U, // SABDv16i8 >+ 2684883738U, // SABDv2i32 >+ 3222278938U, // SABDv4i16 >+ 1075057434U, // SABDv4i32 >+ 1612190490U, // SABDv8i16 >+ 3759936282U, // SABDv8i8 >+ 35141315U, // SADALPv16i8_v8i16 >+ 1117533891U, // SADALPv2i32_v1i64 >+ 2181576387U, // SADALPv4i16_v2i32 >+ 2718709443U, // SADALPv4i32_v2i64 >+ 3256104643U, // SADALPv8i16_v4i32 >+ 3792713411U, // SADALPv8i8_v4i16 >+ 1578707U, // SADDLPv16i8_v8i16 >+ 1083971283U, // SADDLPv2i32_v1i64 >+ 2148013779U, // SADDLPv4i16_v2i32 >+ 2685146835U, // SADDLPv4i32_v2i64 >+ 3222542035U, // SADDLPv8i16_v4i32 >+ 3759150803U, // SADDLPv8i8_v4i16 >+ 272700U, // SADDLVv16i8v >+ 2147756348U, // SADDLVv4i16v >+ 2684627260U, // SADDLVv4i32v >+ 3221498172U, // SADDLVv8i16v >+ 3758369084U, // SADDLVv8i8v >+ 2149060780U, // SADDLv16i8_v8i16 >+ 2685146409U, // SADDLv2i32_v2i64 >+ 3222541609U, // SADDLv4i16_v4i32 >+ 1074532524U, // SADDLv4i32_v2i64 >+ 1611927724U, // SADDLv8i16_v4i32 >+ 3759674665U, // SADDLv8i8_v8i16 >+ 1612190133U, // SADDWv16i8_v8i16 >+ 537663936U, // SADDWv2i32_v2i64 >+ 1075059136U, // SADDWv4i16_v4i32 >+ 537661877U, // SADDWv4i32_v2i64 >+ 1075057077U, // SADDWv8i16_v4i32 >+ 1612192192U, // SADDWv8i8_v8i16 >+ 17049656U, // SBCSWr >+ 17049656U, // SBCSXr >+ 17048293U, // SBCWr >+ 17048293U, // SBCXr >+ 17049061U, // SBFMWri >+ 17049061U, // SBFMXri >+ 17048517U, // SCVTFSWDri >+ 17048517U, // SCVTFSWSri >+ 17048517U, // SCVTFSXDri >+ 17048517U, // SCVTFSXSri >+ 553919429U, // SCVTFUWDri >+ 553919429U, // SCVTFUWSri >+ 553919429U, // SCVTFUXDri >+ 553919429U, // SCVTFUXSri >+ 17048517U, // SCVTFd >+ 17048517U, // SCVTFs >+ 553919429U, // SCVTFv1i32 >+ 553919429U, // SCVTFv1i64 >+ 1074271173U, // SCVTFv2f32 >+ 1611404229U, // SCVTFv2f64 >+ 2684883909U, // SCVTFv2i32_shift >+ 537662405U, // SCVTFv2i64_shift >+ 2685670341U, // SCVTFv4f32 >+ 1075057605U, // SCVTFv4i32_shift >+ 17049904U, // SDIVWr >+ 17049904U, // SDIVXr >+ 17049904U, // SDIV_IntWr >+ 17049904U, // SDIV_IntXr >+ 67404510U, // SHA1Crrr >+ 553919463U, // SHA1Hrr >+ 67405278U, // SHA1Mrrr >+ 67405488U, // SHA1Prrr >+ 1108619265U, // SHA1SU0rrr >+ 2719232056U, // SHA1SU1rr >+ 67403864U, // SHA256H2rrr >+ 67404790U, // SHA256Hrrr >+ 2719232010U, // SHA256SU0rr >+ 1108619329U, // SHA256SU1rrr >+ 2147488572U, // SHADDv16i8 >+ 2684883772U, // SHADDv2i32 >+ 3222278972U, // SHADDv4i16 >+ 1075057468U, // SHADDv4i32 >+ 1612190524U, // SHADDv8i16 >+ 3759936316U, // SHADDv8i8 >+ 2149060797U, // SHLLv16i8 >+ 2685146487U, // SHLLv2i32 >+ 3222541687U, // SHLLv4i16 >+ 3758887101U, // SHLLv4i32 >+ 1315005U, // SHLLv8i16 >+ 538449271U, // SHLLv8i8 >+ 17048896U, // SHLd >+ 2147489088U, // SHLv16i8_shift >+ 2684884288U, // SHLv2i32_shift >+ 537662784U, // SHLv2i64_shift >+ 3222279488U, // SHLv4i16_shift >+ 1075057984U, // SHLv4i32_shift >+ 1612191040U, // SHLv8i16_shift >+ 3759936832U, // SHLv8i8_shift >+ 1644179748U, // SHRNv16i8_shift >+ 537400901U, // SHRNv2i32_shift >+ 1074796101U, // SHRNv4i16_shift >+ 571748644U, // SHRNv4i32_shift >+ 1108881700U, // SHRNv8i16_shift >+ 1612453445U, // SHRNv8i8_shift >+ 2147488435U, // SHSUBv16i8 >+ 2684883635U, // SHSUBv2i32 >+ 3222278835U, // SHSUBv4i16 >+ 1075057331U, // SHSUBv4i32 >+ 1612190387U, // SHSUBv8i16 >+ 3759936179U, // SHSUBv8i8 >+ 67404954U, // SLId >+ 2181051546U, // SLIv16i8_shift >+ 2718446746U, // SLIv2i32_shift >+ 571225242U, // SLIv2i64_shift >+ 3255841946U, // SLIv4i16_shift >+ 1108620442U, // SLIv4i32_shift >+ 1645753498U, // SLIv8i16_shift >+ 3793499290U, // SLIv8i8_shift >+ 17048857U, // SMADDLrrr >+ 2147489609U, // SMAXPv16i8 >+ 2684884809U, // SMAXPv2i32 >+ 3222280009U, // SMAXPv4i16 >+ 1075058505U, // SMAXPv4i32 >+ 1612191561U, // SMAXPv8i16 >+ 3759937353U, // SMAXPv8i8 >+ 272787U, // SMAXVv16i8v >+ 2147756435U, // SMAXVv4i16v >+ 2684627347U, // SMAXVv4i32v >+ 3221498259U, // SMAXVv8i16v >+ 3758369171U, // SMAXVv8i8v >+ 2147490298U, // SMAXv16i8 >+ 2684885498U, // SMAXv2i32 >+ 3222280698U, // SMAXv4i16 >+ 1075059194U, // SMAXv4i32 >+ 1612192250U, // SMAXv8i16 >+ 3759938042U, // SMAXv8i8 >+ 21246U, // SMC >+ 2147489551U, // SMINPv16i8 >+ 2684884751U, // SMINPv2i32 >+ 3222279951U, // SMINPv4i16 >+ 1075058447U, // SMINPv4i32 >+ 1612191503U, // SMINPv8i16 >+ 3759937295U, // SMINPv8i8 >+ 272741U, // SMINVv16i8v >+ 2147756389U, // SMINVv4i16v >+ 2684627301U, // SMINVv4i32v >+ 3221498213U, // SMINVv8i16v >+ 3758369125U, // SMINVv8i8v >+ 2147489324U, // SMINv16i8 >+ 2684884524U, // SMINv2i32 >+ 3222279724U, // SMINv4i16 >+ 1075058220U, // SMINv4i32 >+ 1612191276U, // SMINv8i16 >+ 3759937068U, // SMINv8i8 >+ 2182623356U, // SMLALv16i8_v8i16 >+ 2718708954U, // SMLALv2i32_indexed >+ 2718708954U, // SMLALv2i32_v2i64 >+ 3256104154U, // SMLALv4i16_indexed >+ 3256104154U, // SMLALv4i16_v4i32 >+ 1108095100U, // SMLALv4i32_indexed >+ 1108095100U, // SMLALv4i32_v2i64 >+ 1645490300U, // SMLALv8i16_indexed >+ 1645490300U, // SMLALv8i16_v4i32 >+ 3793237210U, // SMLALv8i8_v8i16 >+ 2182623480U, // SMLSLv16i8_v8i16 >+ 2718709168U, // SMLSLv2i32_indexed >+ 2718709168U, // SMLSLv2i32_v2i64 >+ 3256104368U, // SMLSLv4i16_indexed >+ 3256104368U, // SMLSLv4i16_v4i32 >+ 1108095224U, // SMLSLv4i32_indexed >+ 1108095224U, // SMLSLv4i32_v2i64 >+ 1645490424U, // SMLSLv8i16_indexed >+ 1645490424U, // SMLSLv8i16_v4i32 >+ 3793237424U, // SMLSLv8i8_v8i16 >+ 272768U, // SMOVvi16to32 >+ 272768U, // SMOVvi16to64 >+ 537143680U, // SMOVvi32to64 >+ 1610885504U, // SMOVvi8to32 >+ 1610885504U, // SMOVvi8to64 >+ 17048813U, // SMSUBLrrr >+ 17048603U, // SMULHrr >+ 2149060830U, // SMULLv16i8_v8i16 >+ 2685146516U, // SMULLv2i32_indexed >+ 2685146516U, // SMULLv2i32_v2i64 >+ 3222541716U, // SMULLv4i16_indexed >+ 3222541716U, // SMULLv4i16_v4i32 >+ 1074532574U, // SMULLv4i32_indexed >+ 1074532574U, // SMULLv4i32_v2i64 >+ 1611927774U, // SMULLv8i16_indexed >+ 1611927774U, // SMULLv8i16_v4i32 >+ 3759674772U, // SMULLv8i8_v8i16 >+ 6187U, // SQABSv16i8 >+ 553920555U, // SQABSv1i16 >+ 553920555U, // SQABSv1i32 >+ 553920555U, // SQABSv1i64 >+ 553920555U, // SQABSv1i8 >+ 1074272299U, // SQABSv2i32 >+ 1611405355U, // SQABSv2i64 >+ 2148538411U, // SQABSv4i16 >+ 2685671467U, // SQABSv4i32 >+ 3222804523U, // SQABSv8i16 >+ 3759937579U, // SQABSv8i8 >+ 2147488602U, // SQADDv16i8 >+ 17048410U, // SQADDv1i16 >+ 17048410U, // SQADDv1i32 >+ 17048410U, // SQADDv1i64 >+ 17048410U, // SQADDv1i8 >+ 2684883802U, // SQADDv2i32 >+ 537662298U, // SQADDv2i64 >+ 3222279002U, // SQADDv4i16 >+ 1075057498U, // SQADDv4i32 >+ 1612190554U, // SQADDv8i16 >+ 3759936346U, // SQADDv8i8 >+ 67405009U, // SQDMLALi16 >+ 67405009U, // SQDMLALi32 >+ 67405009U, // SQDMLALv1i32_indexed >+ 67405009U, // SQDMLALv1i64_indexed >+ 2718708945U, // SQDMLALv2i32_indexed >+ 2718708945U, // SQDMLALv2i32_v2i64 >+ 3256104145U, // SQDMLALv4i16_indexed >+ 3256104145U, // SQDMLALv4i16_v4i32 >+ 1108095090U, // SQDMLALv4i32_indexed >+ 1108095090U, // SQDMLALv4i32_v2i64 >+ 1645490290U, // SQDMLALv8i16_indexed >+ 1645490290U, // SQDMLALv8i16_v4i32 >+ 67405223U, // SQDMLSLi16 >+ 67405223U, // SQDMLSLi32 >+ 67405223U, // SQDMLSLv1i32_indexed >+ 67405223U, // SQDMLSLv1i64_indexed >+ 2718709159U, // SQDMLSLv2i32_indexed >+ 2718709159U, // SQDMLSLv2i32_v2i64 >+ 3256104359U, // SQDMLSLv4i16_indexed >+ 3256104359U, // SQDMLSLv4i16_v4i32 >+ 1108095214U, // SQDMLSLv4i32_indexed >+ 1108095214U, // SQDMLSLv4i32_v2i64 >+ 1645490414U, // SQDMLSLv8i16_indexed >+ 1645490414U, // SQDMLSLv8i16_v4i32 >+ 17048584U, // SQDMULHv1i16 >+ 17048584U, // SQDMULHv1i16_indexed >+ 17048584U, // SQDMULHv1i32 >+ 17048584U, // SQDMULHv1i32_indexed >+ 2684883976U, // SQDMULHv2i32 >+ 2684883976U, // SQDMULHv2i32_indexed >+ 3222279176U, // SQDMULHv4i16 >+ 3222279176U, // SQDMULHv4i16_indexed >+ 1075057672U, // SQDMULHv4i32 >+ 1075057672U, // SQDMULHv4i32_indexed >+ 1612190728U, // SQDMULHv8i16 >+ 1612190728U, // SQDMULHv8i16_indexed >+ 17048964U, // SQDMULLi16 >+ 17048964U, // SQDMULLi32 >+ 17048964U, // SQDMULLv1i32_indexed >+ 17048964U, // SQDMULLv1i64_indexed >+ 2685146500U, // SQDMULLv2i32_indexed >+ 2685146500U, // SQDMULLv2i32_v2i64 >+ 3222541700U, // SQDMULLv4i16_indexed >+ 3222541700U, // SQDMULLv4i16_v4i32 >+ 1074532556U, // SQDMULLv4i32_indexed >+ 1074532556U, // SQDMULLv4i32_v2i64 >+ 1611927756U, // SQDMULLv8i16_indexed >+ 1611927756U, // SQDMULLv8i16_v4i32 >+ 5081U, // SQNEGv16i8 >+ 553919449U, // SQNEGv1i16 >+ 553919449U, // SQNEGv1i32 >+ 553919449U, // SQNEGv1i64 >+ 553919449U, // SQNEGv1i8 >+ 1074271193U, // SQNEGv2i32 >+ 1611404249U, // SQNEGv2i64 >+ 2148537305U, // SQNEGv4i16 >+ 2685670361U, // SQNEGv4i32 >+ 3222803417U, // SQNEGv8i16 >+ 3759936473U, // SQNEGv8i8 >+ 17048593U, // SQRDMULHv1i16 >+ 17048593U, // SQRDMULHv1i16_indexed >+ 17048593U, // SQRDMULHv1i32 >+ 17048593U, // SQRDMULHv1i32_indexed >+ 2684883985U, // SQRDMULHv2i32 >+ 2684883985U, // SQRDMULHv2i32_indexed >+ 3222279185U, // SQRDMULHv4i16 >+ 3222279185U, // SQRDMULHv4i16_indexed >+ 1075057681U, // SQRDMULHv4i32 >+ 1075057681U, // SQRDMULHv4i32_indexed >+ 1612190737U, // SQRDMULHv8i16 >+ 1612190737U, // SQRDMULHv8i16_indexed >+ 2147489100U, // SQRSHLv16i8 >+ 17048908U, // SQRSHLv1i16 >+ 17048908U, // SQRSHLv1i32 >+ 17048908U, // SQRSHLv1i64 >+ 17048908U, // SQRSHLv1i8 >+ 2684884300U, // SQRSHLv2i32 >+ 537662796U, // SQRSHLv2i64 >+ 3222279500U, // SQRSHLv4i16 >+ 1075057996U, // SQRSHLv4i32 >+ 1612191052U, // SQRSHLv8i16 >+ 3759936844U, // SQRSHLv8i8 >+ 17049171U, // SQRSHRNb >+ 17049171U, // SQRSHRNh >+ 17049171U, // SQRSHRNs >+ 1644179764U, // SQRSHRNv16i8_shift >+ 537400915U, // SQRSHRNv2i32_shift >+ 1074796115U, // SQRSHRNv4i16_shift >+ 571748660U, // SQRSHRNv4i32_shift >+ 1108881716U, // SQRSHRNv8i16_shift >+ 1612453459U, // SQRSHRNv8i8_shift >+ 17049232U, // SQRSHRUNb >+ 17049232U, // SQRSHRUNh >+ 17049232U, // SQRSHRUNs >+ 1644179824U, // SQRSHRUNv16i8_shift >+ 537400976U, // SQRSHRUNv2i32_shift >+ 1074796176U, // SQRSHRUNv4i16_shift >+ 571748720U, // SQRSHRUNv4i32_shift >+ 1108881776U, // SQRSHRUNv8i16_shift >+ 1612453520U, // SQRSHRUNv8i8_shift >+ 17049847U, // SQSHLUb >+ 17049847U, // SQSHLUd >+ 17049847U, // SQSHLUh >+ 17049847U, // SQSHLUs >+ 2147490039U, // SQSHLUv16i8_shift >+ 2684885239U, // SQSHLUv2i32_shift >+ 537663735U, // SQSHLUv2i64_shift >+ 3222280439U, // SQSHLUv4i16_shift >+ 1075058935U, // SQSHLUv4i32_shift >+ 1612191991U, // SQSHLUv8i16_shift >+ 3759937783U, // SQSHLUv8i8_shift >+ 17048894U, // SQSHLb >+ 17048894U, // SQSHLd >+ 17048894U, // SQSHLh >+ 17048894U, // SQSHLs >+ 2147489086U, // SQSHLv16i8 >+ 2147489086U, // SQSHLv16i8_shift >+ 17048894U, // SQSHLv1i16 >+ 17048894U, // SQSHLv1i32 >+ 17048894U, // SQSHLv1i64 >+ 17048894U, // SQSHLv1i8 >+ 2684884286U, // SQSHLv2i32 >+ 2684884286U, // SQSHLv2i32_shift >+ 537662782U, // SQSHLv2i64 >+ 537662782U, // SQSHLv2i64_shift >+ 3222279486U, // SQSHLv4i16 >+ 3222279486U, // SQSHLv4i16_shift >+ 1075057982U, // SQSHLv4i32 >+ 1075057982U, // SQSHLv4i32_shift >+ 1612191038U, // SQSHLv8i16 >+ 1612191038U, // SQSHLv8i16_shift >+ 3759936830U, // SQSHLv8i8 >+ 3759936830U, // SQSHLv8i8_shift >+ 17049155U, // SQSHRNb >+ 17049155U, // SQSHRNh >+ 17049155U, // SQSHRNs >+ 1644179746U, // SQSHRNv16i8_shift >+ 537400899U, // SQSHRNv2i32_shift >+ 1074796099U, // SQSHRNv4i16_shift >+ 571748642U, // SQSHRNv4i32_shift >+ 1108881698U, // SQSHRNv8i16_shift >+ 1612453443U, // SQSHRNv8i8_shift >+ 17049223U, // SQSHRUNb >+ 17049223U, // SQSHRUNh >+ 17049223U, // SQSHRUNs >+ 1644179814U, // SQSHRUNv16i8_shift >+ 537400967U, // SQSHRUNv2i32_shift >+ 1074796167U, // SQSHRUNv4i16_shift >+ 571748710U, // SQSHRUNv4i32_shift >+ 1108881766U, // SQSHRUNv8i16_shift >+ 1612453511U, // SQSHRUNv8i8_shift >+ 2147488464U, // SQSUBv16i8 >+ 17048272U, // SQSUBv1i16 >+ 17048272U, // SQSUBv1i32 >+ 17048272U, // SQSUBv1i64 >+ 17048272U, // SQSUBv1i8 >+ 2684883664U, // SQSUBv2i32 >+ 537662160U, // SQSUBv2i64 >+ 3222278864U, // SQSUBv4i16 >+ 1075057360U, // SQSUBv4i32 >+ 1612190416U, // SQSUBv8i16 >+ 3759936208U, // SQSUBv8i8 >+ 3254792534U, // SQXTNv16i8 >+ 553920121U, // SQXTNv1i16 >+ 553920121U, // SQXTNv1i32 >+ 553920121U, // SQXTNv1i8 >+ 1611142777U, // SQXTNv2i32 >+ 2685408889U, // SQXTNv4i16 >+ 1645490518U, // SQXTNv4i32 >+ 2719494486U, // SQXTNv8i16 >+ 3223066233U, // SQXTNv8i8 >+ 3254792571U, // SQXTUNv16i8 >+ 553920154U, // SQXTUNv1i16 >+ 553920154U, // SQXTUNv1i32 >+ 553920154U, // SQXTUNv1i8 >+ 1611142810U, // SQXTUNv2i32 >+ 2685408922U, // SQXTUNv4i16 >+ 1645490555U, // SQXTUNv4i32 >+ 2719494523U, // SQXTUNv8i16 >+ 3223066266U, // SQXTUNv8i8 >+ 2147488556U, // SRHADDv16i8 >+ 2684883756U, // SRHADDv2i32 >+ 3222278956U, // SRHADDv4i16 >+ 1075057452U, // SRHADDv4i32 >+ 1612190508U, // SRHADDv8i16 >+ 3759936300U, // SRHADDv8i8 >+ 67404965U, // SRId >+ 2181051557U, // SRIv16i8_shift >+ 2718446757U, // SRIv2i32_shift >+ 571225253U, // SRIv2i64_shift >+ 3255841957U, // SRIv4i16_shift >+ 1108620453U, // SRIv4i32_shift >+ 1645753509U, // SRIv8i16_shift >+ 3793499301U, // SRIv8i8_shift >+ 2147489116U, // SRSHLv16i8 >+ 17048924U, // SRSHLv1i64 >+ 2684884316U, // SRSHLv2i32 >+ 537662812U, // SRSHLv2i64 >+ 3222279516U, // SRSHLv4i16 >+ 1075058012U, // SRSHLv4i32 >+ 1612191068U, // SRSHLv8i16 >+ 3759936860U, // SRSHLv8i8 >+ 17049501U, // SRSHRd >+ 2147489693U, // SRSHRv16i8_shift >+ 2684884893U, // SRSHRv2i32_shift >+ 537663389U, // SRSHRv2i64_shift >+ 3222280093U, // SRSHRv4i16_shift >+ 1075058589U, // SRSHRv4i32_shift >+ 1612191645U, // SRSHRv8i16_shift >+ 3759937437U, // SRSHRv8i8_shift >+ 67404288U, // SRSRAd >+ 2181050880U, // SRSRAv16i8_shift >+ 2718446080U, // SRSRAv2i32_shift >+ 571224576U, // SRSRAv2i64_shift >+ 3255841280U, // SRSRAv4i16_shift >+ 1108619776U, // SRSRAv4i32_shift >+ 1645752832U, // SRSRAv8i16_shift >+ 3793498624U, // SRSRAv8i8_shift >+ 2149060796U, // SSHLLv16i8_shift >+ 2685146486U, // SSHLLv2i32_shift >+ 3222541686U, // SSHLLv4i16_shift >+ 1074532540U, // SSHLLv4i32_shift >+ 1611927740U, // SSHLLv8i16_shift >+ 3759674742U, // SSHLLv8i8_shift >+ 2147489130U, // SSHLv16i8 >+ 17048938U, // SSHLv1i64 >+ 2684884330U, // SSHLv2i32 >+ 537662826U, // SSHLv2i64 >+ 3222279530U, // SSHLv4i16 >+ 1075058026U, // SSHLv4i32 >+ 1612191082U, // SSHLv8i16 >+ 3759936874U, // SSHLv8i8 >+ 17049515U, // SSHRd >+ 2147489707U, // SSHRv16i8_shift >+ 2684884907U, // SSHRv2i32_shift >+ 537663403U, // SSHRv2i64_shift >+ 3222280107U, // SSHRv4i16_shift >+ 1075058603U, // SSHRv4i32_shift >+ 1612191659U, // SSHRv8i16_shift >+ 3759937451U, // SSHRv8i8_shift >+ 67404302U, // SSRAd >+ 2181050894U, // SSRAv16i8_shift >+ 2718446094U, // SSRAv2i32_shift >+ 571224590U, // SSRAv2i64_shift >+ 3255841294U, // SSRAv4i16_shift >+ 1108619790U, // SSRAv4i32_shift >+ 1645752846U, // SSRAv8i16_shift >+ 3793498638U, // SSRAv8i8_shift >+ 2149060748U, // SSUBLv16i8_v8i16 >+ 2685146365U, // SSUBLv2i32_v2i64 >+ 3222541565U, // SSUBLv4i16_v4i32 >+ 1074532492U, // SSUBLv4i32_v2i64 >+ 1611927692U, // SSUBLv8i16_v4i32 >+ 3759674621U, // SSUBLv8i8_v8i16 >+ 1612190117U, // SSUBWv16i8_v8i16 >+ 537663913U, // SSUBWv2i32_v2i64 >+ 1075059113U, // SSUBWv4i16_v4i32 >+ 537661861U, // SSUBWv4i32_v2i64 >+ 1075057061U, // SSUBWv8i16_v4i32 >+ 1612192169U, // SSUBWv8i8_v8i16 >+ 36915U, // ST1Fourv16b >+ 3711027U, // ST1Fourv16b_POST >+ 45107U, // ST1Fourv1d >+ 3981363U, // ST1Fourv1d_POST >+ 53299U, // ST1Fourv2d >+ 3727411U, // ST1Fourv2d_POST >+ 61491U, // ST1Fourv2s >+ 3997747U, // ST1Fourv2s_POST >+ 69683U, // ST1Fourv4h >+ 4005939U, // ST1Fourv4h_POST >+ 77875U, // ST1Fourv4s >+ 3751987U, // ST1Fourv4s_POST >+ 86067U, // ST1Fourv8b >+ 4022323U, // ST1Fourv8b_POST >+ 94259U, // ST1Fourv8h >+ 3768371U, // ST1Fourv8h_POST >+ 36915U, // ST1Onev16b >+ 4235315U, // ST1Onev16b_POST >+ 45107U, // ST1Onev1d >+ 4505651U, // ST1Onev1d_POST >+ 53299U, // ST1Onev2d >+ 4251699U, // ST1Onev2d_POST >+ 61491U, // ST1Onev2s >+ 4522035U, // ST1Onev2s_POST >+ 69683U, // ST1Onev4h >+ 4530227U, // ST1Onev4h_POST >+ 77875U, // ST1Onev4s >+ 4276275U, // ST1Onev4s_POST >+ 86067U, // ST1Onev8b >+ 4546611U, // ST1Onev8b_POST >+ 94259U, // ST1Onev8h >+ 4292659U, // ST1Onev8h_POST >+ 36915U, // ST1Threev16b >+ 5546035U, // ST1Threev16b_POST >+ 45107U, // ST1Threev1d >+ 5816371U, // ST1Threev1d_POST >+ 53299U, // ST1Threev2d >+ 5562419U, // ST1Threev2d_POST >+ 61491U, // ST1Threev2s >+ 5832755U, // ST1Threev2s_POST >+ 69683U, // ST1Threev4h >+ 5840947U, // ST1Threev4h_POST >+ 77875U, // ST1Threev4s >+ 5586995U, // ST1Threev4s_POST >+ 86067U, // ST1Threev8b >+ 5857331U, // ST1Threev8b_POST >+ 94259U, // ST1Threev8h >+ 5603379U, // ST1Threev8h_POST >+ 36915U, // ST1Twov16b >+ 3973171U, // ST1Twov16b_POST >+ 45107U, // ST1Twov1d >+ 4243507U, // ST1Twov1d_POST >+ 53299U, // ST1Twov2d >+ 3989555U, // ST1Twov2d_POST >+ 61491U, // ST1Twov2s >+ 4259891U, // ST1Twov2s_POST >+ 69683U, // ST1Twov4h >+ 4268083U, // ST1Twov4h_POST >+ 77875U, // ST1Twov4s >+ 4014131U, // ST1Twov4s_POST >+ 86067U, // ST1Twov8b >+ 4284467U, // ST1Twov8b_POST >+ 94259U, // ST1Twov8h >+ 4030515U, // ST1Twov8h_POST >+ 147507U, // ST1i16 >+ 262246451U, // ST1i16_POST >+ 151603U, // ST1i32 >+ 279031859U, // ST1i32_POST >+ 155699U, // ST1i64 >+ 295817267U, // ST1i64_POST >+ 159795U, // ST1i8 >+ 312602675U, // ST1i8_POST >+ 37280U, // ST2Twov16b >+ 3973536U, // ST2Twov16b_POST >+ 53664U, // ST2Twov2d >+ 3989920U, // ST2Twov2d_POST >+ 61856U, // ST2Twov2s >+ 4260256U, // ST2Twov2s_POST >+ 70048U, // ST2Twov4h >+ 4268448U, // ST2Twov4h_POST >+ 78240U, // ST2Twov4s >+ 4014496U, // ST2Twov4s_POST >+ 86432U, // ST2Twov8b >+ 4284832U, // ST2Twov8b_POST >+ 94624U, // ST2Twov8h >+ 4030880U, // ST2Twov8h_POST >+ 147872U, // ST2i16 >+ 279024032U, // ST2i16_POST >+ 151968U, // ST2i32 >+ 295809440U, // ST2i32_POST >+ 156064U, // ST2i64 >+ 329372064U, // ST2i64_POST >+ 160160U, // ST2i8 >+ 262271392U, // ST2i8_POST >+ 37329U, // ST3Threev16b >+ 5546449U, // ST3Threev16b_POST >+ 53713U, // ST3Threev2d >+ 5562833U, // ST3Threev2d_POST >+ 61905U, // ST3Threev2s >+ 5833169U, // ST3Threev2s_POST >+ 70097U, // ST3Threev4h >+ 5841361U, // ST3Threev4h_POST >+ 78289U, // ST3Threev4s >+ 5587409U, // ST3Threev4s_POST >+ 86481U, // ST3Threev8b >+ 5857745U, // ST3Threev8b_POST >+ 94673U, // ST3Threev8h >+ 5603793U, // ST3Threev8h_POST >+ 147921U, // ST3i16 >+ 346132945U, // ST3i16_POST >+ 152017U, // ST3i32 >+ 362918353U, // ST3i32_POST >+ 156113U, // ST3i64 >+ 379703761U, // ST3i64_POST >+ 160209U, // ST3i8 >+ 396489169U, // ST3i8_POST >+ 37346U, // ST4Fourv16b >+ 3711458U, // ST4Fourv16b_POST >+ 53730U, // ST4Fourv2d >+ 3727842U, // ST4Fourv2d_POST >+ 61922U, // ST4Fourv2s >+ 3998178U, // ST4Fourv2s_POST >+ 70114U, // ST4Fourv4h >+ 4006370U, // ST4Fourv4h_POST >+ 78306U, // ST4Fourv4s >+ 3752418U, // ST4Fourv4s_POST >+ 86498U, // ST4Fourv8b >+ 4022754U, // ST4Fourv8b_POST >+ 94690U, // ST4Fourv8h >+ 3768802U, // ST4Fourv8h_POST >+ 147938U, // ST4i16 >+ 295801314U, // ST4i16_POST >+ 152034U, // ST4i32 >+ 329363938U, // ST4i32_POST >+ 156130U, // ST4i64 >+ 413258210U, // ST4i64_POST >+ 160226U, // ST4i8 >+ 279048674U, // ST4i8_POST >+ 26485317U, // STLRB >+ 26485814U, // STLRH >+ 26486716U, // STLRW >+ 26486716U, // STLRX >+ 17049437U, // STLXPW >+ 17049437U, // STLXPX >+ 553919101U, // STLXRB >+ 553919598U, // STLXRH >+ 553920528U, // STLXRW >+ 553920528U, // STLXRX >+ 553920285U, // STNPDi >+ 553920285U, // STNPQi >+ 553920285U, // STNPSi >+ 553920285U, // STNPWi >+ 553920285U, // STNPXi >+ 553920305U, // STPDi >+ 604276529U, // STPDpost >+ 604276529U, // STPDpre >+ 553920305U, // STPQi >+ 604276529U, // STPQpost >+ 604276529U, // STPQpre >+ 553920305U, // STPSi >+ 604276529U, // STPSpost >+ 604276529U, // STPSpre >+ 553920305U, // STPWi >+ 604276529U, // STPWpost >+ 604276529U, // STPWpre >+ 553920305U, // STPXi >+ 604276529U, // STPXpost >+ 604276529U, // STPXpre >+ 1150583379U, // STRBBpost >+ 76841555U, // STRBBpre >+ 26485331U, // STRBBroW >+ 26485331U, // STRBBroX >+ 26485331U, // STRBBui >+ 1150584806U, // STRBpost >+ 76842982U, // STRBpre >+ 26486758U, // STRBroW >+ 26486758U, // STRBroX >+ 26486758U, // STRBui >+ 1150584806U, // STRDpost >+ 76842982U, // STRDpre >+ 26486758U, // STRDroW >+ 26486758U, // STRDroX >+ 26486758U, // STRDui >+ 1150583876U, // STRHHpost >+ 76842052U, // STRHHpre >+ 26485828U, // STRHHroW >+ 26485828U, // STRHHroX >+ 26485828U, // STRHHui >+ 1150584806U, // STRHpost >+ 76842982U, // STRHpre >+ 26486758U, // STRHroW >+ 26486758U, // STRHroX >+ 26486758U, // STRHui >+ 1150584806U, // STRQpost >+ 76842982U, // STRQpre >+ 26486758U, // STRQroW >+ 26486758U, // STRQroX >+ 26486758U, // STRQui >+ 1150584806U, // STRSpost >+ 76842982U, // STRSpre >+ 26486758U, // STRSroW >+ 26486758U, // STRSroX >+ 26486758U, // STRSui >+ 1150584806U, // STRWpost >+ 76842982U, // STRWpre >+ 26486758U, // STRWroW >+ 26486758U, // STRWroX >+ 26486758U, // STRWui >+ 1150584806U, // STRXpost >+ 76842982U, // STRXpre >+ 26486758U, // STRXroW >+ 26486758U, // STRXroX >+ 26486758U, // STRXui >+ 26485337U, // STTRBi >+ 26485834U, // STTRHi >+ 26486763U, // STTRWi >+ 26486763U, // STTRXi >+ 26485351U, // STURBBi >+ 26486781U, // STURBi >+ 26486781U, // STURDi >+ 26485848U, // STURHHi >+ 26486781U, // STURHi >+ 26486781U, // STURQi >+ 26486781U, // STURSi >+ 26486781U, // STURWi >+ 26486781U, // STURXi >+ 17049444U, // STXPW >+ 17049444U, // STXPX >+ 553919109U, // STXRB >+ 553919606U, // STXRH >+ 553920535U, // STXRW >+ 553920535U, // STXRX >+ 537400855U, // SUBHNv2i64_v2i32 >+ 571748625U, // SUBHNv2i64_v4i32 >+ 1074796055U, // SUBHNv4i32_v4i16 >+ 1108881681U, // SUBHNv4i32_v8i16 >+ 1644179729U, // SUBHNv8i16_v16i8 >+ 1612453399U, // SUBHNv8i16_v8i8 >+ 17049650U, // SUBSWri >+ 0U, // SUBSWrr >+ 17049650U, // SUBSWrs >+ 17049650U, // SUBSWrx >+ 17049650U, // SUBSXri >+ 0U, // SUBSXrr >+ 17049650U, // SUBSXrs >+ 17049650U, // SUBSXrx >+ 17049650U, // SUBSXrx64 >+ 17048238U, // SUBWri >+ 0U, // SUBWrr >+ 17048238U, // SUBWrs >+ 17048238U, // SUBWrx >+ 17048238U, // SUBXri >+ 0U, // SUBXrr >+ 17048238U, // SUBXrs >+ 17048238U, // SUBXrx >+ 17048238U, // SUBXrx64 >+ 2147488430U, // SUBv16i8 >+ 17048238U, // SUBv1i64 >+ 2684883630U, // SUBv2i32 >+ 537662126U, // SUBv2i64 >+ 3222278830U, // SUBv4i16 >+ 1075057326U, // SUBv4i32 >+ 1612190382U, // SUBv8i16 >+ 3759936174U, // SUBv8i8 >+ 33567585U, // SUQADDv16i8 >+ 604275553U, // SUQADDv1i16 >+ 604275553U, // SUQADDv1i32 >+ 604275553U, // SUQADDv1i64 >+ 604275553U, // SUQADDv1i8 >+ 1107833697U, // SUQADDv2i32 >+ 1644966753U, // SUQADDv2i64 >+ 2182099809U, // SUQADDv4i16 >+ 2719232865U, // SUQADDv4i32 >+ 3256365921U, // SUQADDv8i16 >+ 3793498977U, // SUQADDv8i8 >+ 21263U, // SVC >+ 17049022U, // SYSLxt >+ 419702938U, // SYSxt >+ 436212968U, // TBLv16i8Four >+ 436212968U, // TBLv16i8One >+ 436212968U, // TBLv16i8Three >+ 436212968U, // TBLv16i8Two >+ 4196144360U, // TBLv8i8Four >+ 4196144360U, // TBLv8i8One >+ 4196144360U, // TBLv8i8Three >+ 4196144360U, // TBLv8i8Two >+ 17050183U, // TBNZW >+ 17050183U, // TBNZX >+ 452999686U, // TBXv16i8Four >+ 452999686U, // TBXv16i8One >+ 452999686U, // TBXv16i8Three >+ 452999686U, // TBXv16i8Two >+ 4212931078U, // TBXv8i8Four >+ 4212931078U, // TBXv8i8One >+ 4212931078U, // TBXv8i8Three >+ 4212931078U, // TBXv8i8Two >+ 17050167U, // TBZW >+ 17050167U, // TBZX >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 2107995U, // TLSDESCCALL >+ 0U, // TLSDESC_BLR >+ 2147487770U, // TRN1v16i8 >+ 2684882970U, // TRN1v2i32 >+ 537661466U, // TRN1v2i64 >+ 3222278170U, // TRN1v4i16 >+ 1075056666U, // TRN1v4i32 >+ 1612189722U, // TRN1v8i16 >+ 3759935514U, // TRN1v8i8 >+ 2147488072U, // TRN2v16i8 >+ 2684883272U, // TRN2v2i32 >+ 537661768U, // TRN2v2i64 >+ 3222278472U, // TRN2v4i16 >+ 1075056968U, // TRN2v4i32 >+ 1612190024U, // TRN2v8i16 >+ 3759935816U, // TRN2v8i8 >+ 2182623338U, // UABALv16i8_v8i16 >+ 2718708938U, // UABALv2i32_v2i64 >+ 3256104138U, // UABALv4i16_v4i32 >+ 1108095082U, // UABALv4i32_v2i64 >+ 1645490282U, // UABALv8i16_v4i32 >+ 3793237194U, // UABALv8i8_v8i16 >+ 2181050868U, // UABAv16i8 >+ 2718446068U, // UABAv2i32 >+ 3255841268U, // UABAv4i16 >+ 1108619764U, // UABAv4i32 >+ 1645752820U, // UABAv8i16 >+ 3793498612U, // UABAv8i8 >+ 2149060772U, // UABDLv16i8_v8i16 >+ 2685146386U, // UABDLv2i32_v2i64 >+ 3222541586U, // UABDLv4i16_v4i32 >+ 1074532516U, // UABDLv4i32_v2i64 >+ 1611927716U, // UABDLv8i16_v4i32 >+ 3759674642U, // UABDLv8i8_v8i16 >+ 2147488544U, // UABDv16i8 >+ 2684883744U, // UABDv2i32 >+ 3222278944U, // UABDv4i16 >+ 1075057440U, // UABDv4i32 >+ 1612190496U, // UABDv8i16 >+ 3759936288U, // UABDv8i8 >+ 35141323U, // UADALPv16i8_v8i16 >+ 1117533899U, // UADALPv2i32_v1i64 >+ 2181576395U, // UADALPv4i16_v2i32 >+ 2718709451U, // UADALPv4i32_v2i64 >+ 3256104651U, // UADALPv8i16_v4i32 >+ 3792713419U, // UADALPv8i8_v4i16 >+ 1578715U, // UADDLPv16i8_v8i16 >+ 1083971291U, // UADDLPv2i32_v1i64 >+ 2148013787U, // UADDLPv4i16_v2i32 >+ 2685146843U, // UADDLPv4i32_v2i64 >+ 3222542043U, // UADDLPv8i16_v4i32 >+ 3759150811U, // UADDLPv8i8_v4i16 >+ 272708U, // UADDLVv16i8v >+ 2147756356U, // UADDLVv4i16v >+ 2684627268U, // UADDLVv4i32v >+ 3221498180U, // UADDLVv8i16v >+ 3758369092U, // UADDLVv8i8v >+ 2149060788U, // UADDLv16i8_v8i16 >+ 2685146416U, // UADDLv2i32_v2i64 >+ 3222541616U, // UADDLv4i16_v4i32 >+ 1074532532U, // UADDLv4i32_v2i64 >+ 1611927732U, // UADDLv8i16_v4i32 >+ 3759674672U, // UADDLv8i8_v8i16 >+ 1612190141U, // UADDWv16i8_v8i16 >+ 537663943U, // UADDWv2i32_v2i64 >+ 1075059143U, // UADDWv4i16_v4i32 >+ 537661885U, // UADDWv4i32_v2i64 >+ 1075057085U, // UADDWv8i16_v4i32 >+ 1612192199U, // UADDWv8i8_v8i16 >+ 17049067U, // UBFMWri >+ 17049067U, // UBFMXri >+ 17048524U, // UCVTFSWDri >+ 17048524U, // UCVTFSWSri >+ 17048524U, // UCVTFSXDri >+ 17048524U, // UCVTFSXSri >+ 553919436U, // UCVTFUWDri >+ 553919436U, // UCVTFUWSri >+ 553919436U, // UCVTFUXDri >+ 553919436U, // UCVTFUXSri >+ 17048524U, // UCVTFd >+ 17048524U, // UCVTFs >+ 553919436U, // UCVTFv1i32 >+ 553919436U, // UCVTFv1i64 >+ 1074271180U, // UCVTFv2f32 >+ 1611404236U, // UCVTFv2f64 >+ 2684883916U, // UCVTFv2i32_shift >+ 537662412U, // UCVTFv2i64_shift >+ 2685670348U, // UCVTFv4f32 >+ 1075057612U, // UCVTFv4i32_shift >+ 17049910U, // UDIVWr >+ 17049910U, // UDIVXr >+ 17049910U, // UDIV_IntWr >+ 17049910U, // UDIV_IntXr >+ 2147488579U, // UHADDv16i8 >+ 2684883779U, // UHADDv2i32 >+ 3222278979U, // UHADDv4i16 >+ 1075057475U, // UHADDv4i32 >+ 1612190531U, // UHADDv8i16 >+ 3759936323U, // UHADDv8i8 >+ 2147488442U, // UHSUBv16i8 >+ 2684883642U, // UHSUBv2i32 >+ 3222278842U, // UHSUBv4i16 >+ 1075057338U, // UHSUBv4i32 >+ 1612190394U, // UHSUBv8i16 >+ 3759936186U, // UHSUBv8i8 >+ 17048865U, // UMADDLrrr >+ 2147489616U, // UMAXPv16i8 >+ 2684884816U, // UMAXPv2i32 >+ 3222280016U, // UMAXPv4i16 >+ 1075058512U, // UMAXPv4i32 >+ 1612191568U, // UMAXPv8i16 >+ 3759937360U, // UMAXPv8i8 >+ 272794U, // UMAXVv16i8v >+ 2147756442U, // UMAXVv4i16v >+ 2684627354U, // UMAXVv4i32v >+ 3221498266U, // UMAXVv8i16v >+ 3758369178U, // UMAXVv8i8v >+ 2147490304U, // UMAXv16i8 >+ 2684885504U, // UMAXv2i32 >+ 3222280704U, // UMAXv4i16 >+ 1075059200U, // UMAXv4i32 >+ 1612192256U, // UMAXv8i16 >+ 3759938048U, // UMAXv8i8 >+ 2147489558U, // UMINPv16i8 >+ 2684884758U, // UMINPv2i32 >+ 3222279958U, // UMINPv4i16 >+ 1075058454U, // UMINPv4i32 >+ 1612191510U, // UMINPv8i16 >+ 3759937302U, // UMINPv8i8 >+ 272748U, // UMINVv16i8v >+ 2147756396U, // UMINVv4i16v >+ 2684627308U, // UMINVv4i32v >+ 3221498220U, // UMINVv8i16v >+ 3758369132U, // UMINVv8i8v >+ 2147489330U, // UMINv16i8 >+ 2684884530U, // UMINv2i32 >+ 3222279730U, // UMINv4i16 >+ 1075058226U, // UMINv4i32 >+ 1612191282U, // UMINv8i16 >+ 3759937074U, // UMINv8i8 >+ 2182623364U, // UMLALv16i8_v8i16 >+ 2718708961U, // UMLALv2i32_indexed >+ 2718708961U, // UMLALv2i32_v2i64 >+ 3256104161U, // UMLALv4i16_indexed >+ 3256104161U, // UMLALv4i16_v4i32 >+ 1108095108U, // UMLALv4i32_indexed >+ 1108095108U, // UMLALv4i32_v2i64 >+ 1645490308U, // UMLALv8i16_indexed >+ 1645490308U, // UMLALv8i16_v4i32 >+ 3793237217U, // UMLALv8i8_v8i16 >+ 2182623488U, // UMLSLv16i8_v8i16 >+ 2718709175U, // UMLSLv2i32_indexed >+ 2718709175U, // UMLSLv2i32_v2i64 >+ 3256104375U, // UMLSLv4i16_indexed >+ 3256104375U, // UMLSLv4i16_v4i32 >+ 1108095232U, // UMLSLv4i32_indexed >+ 1108095232U, // UMLSLv4i32_v2i64 >+ 1645490432U, // UMLSLv8i16_indexed >+ 1645490432U, // UMLSLv8i16_v4i32 >+ 3793237431U, // UMLSLv8i8_v8i16 >+ 272774U, // UMOVvi16 >+ 537143686U, // UMOVvi32 >+ 1074014598U, // UMOVvi64 >+ 1610885510U, // UMOVvi8 >+ 17048821U, // UMSUBLrrr >+ 17048610U, // UMULHrr >+ 2149060838U, // UMULLv16i8_v8i16 >+ 2685146523U, // UMULLv2i32_indexed >+ 2685146523U, // UMULLv2i32_v2i64 >+ 3222541723U, // UMULLv4i16_indexed >+ 3222541723U, // UMULLv4i16_v4i32 >+ 1074532582U, // UMULLv4i32_indexed >+ 1074532582U, // UMULLv4i32_v2i64 >+ 1611927782U, // UMULLv8i16_indexed >+ 1611927782U, // UMULLv8i16_v4i32 >+ 3759674779U, // UMULLv8i8_v8i16 >+ 2147488610U, // UQADDv16i8 >+ 17048418U, // UQADDv1i16 >+ 17048418U, // UQADDv1i32 >+ 17048418U, // UQADDv1i64 >+ 17048418U, // UQADDv1i8 >+ 2684883810U, // UQADDv2i32 >+ 537662306U, // UQADDv2i64 >+ 3222279010U, // UQADDv4i16 >+ 1075057506U, // UQADDv4i32 >+ 1612190562U, // UQADDv8i16 >+ 3759936354U, // UQADDv8i8 >+ 2147489108U, // UQRSHLv16i8 >+ 17048916U, // UQRSHLv1i16 >+ 17048916U, // UQRSHLv1i32 >+ 17048916U, // UQRSHLv1i64 >+ 17048916U, // UQRSHLv1i8 >+ 2684884308U, // UQRSHLv2i32 >+ 537662804U, // UQRSHLv2i64 >+ 3222279508U, // UQRSHLv4i16 >+ 1075058004U, // UQRSHLv4i32 >+ 1612191060U, // UQRSHLv8i16 >+ 3759936852U, // UQRSHLv8i8 >+ 17049180U, // UQRSHRNb >+ 17049180U, // UQRSHRNh >+ 17049180U, // UQRSHRNs >+ 1644179774U, // UQRSHRNv16i8_shift >+ 537400924U, // UQRSHRNv2i32_shift >+ 1074796124U, // UQRSHRNv4i16_shift >+ 571748670U, // UQRSHRNv4i32_shift >+ 1108881726U, // UQRSHRNv8i16_shift >+ 1612453468U, // UQRSHRNv8i8_shift >+ 17048901U, // UQSHLb >+ 17048901U, // UQSHLd >+ 17048901U, // UQSHLh >+ 17048901U, // UQSHLs >+ 2147489093U, // UQSHLv16i8 >+ 2147489093U, // UQSHLv16i8_shift >+ 17048901U, // UQSHLv1i16 >+ 17048901U, // UQSHLv1i32 >+ 17048901U, // UQSHLv1i64 >+ 17048901U, // UQSHLv1i8 >+ 2684884293U, // UQSHLv2i32 >+ 2684884293U, // UQSHLv2i32_shift >+ 537662789U, // UQSHLv2i64 >+ 537662789U, // UQSHLv2i64_shift >+ 3222279493U, // UQSHLv4i16 >+ 3222279493U, // UQSHLv4i16_shift >+ 1075057989U, // UQSHLv4i32 >+ 1075057989U, // UQSHLv4i32_shift >+ 1612191045U, // UQSHLv8i16 >+ 1612191045U, // UQSHLv8i16_shift >+ 3759936837U, // UQSHLv8i8 >+ 3759936837U, // UQSHLv8i8_shift >+ 17049163U, // UQSHRNb >+ 17049163U, // UQSHRNh >+ 17049163U, // UQSHRNs >+ 1644179755U, // UQSHRNv16i8_shift >+ 537400907U, // UQSHRNv2i32_shift >+ 1074796107U, // UQSHRNv4i16_shift >+ 571748651U, // UQSHRNv4i32_shift >+ 1108881707U, // UQSHRNv8i16_shift >+ 1612453451U, // UQSHRNv8i8_shift >+ 2147488471U, // UQSUBv16i8 >+ 17048279U, // UQSUBv1i16 >+ 17048279U, // UQSUBv1i32 >+ 17048279U, // UQSUBv1i64 >+ 17048279U, // UQSUBv1i8 >+ 2684883671U, // UQSUBv2i32 >+ 537662167U, // UQSUBv2i64 >+ 3222278871U, // UQSUBv4i16 >+ 1075057367U, // UQSUBv4i32 >+ 1612190423U, // UQSUBv8i16 >+ 3759936215U, // UQSUBv8i8 >+ 3254792542U, // UQXTNv16i8 >+ 553920128U, // UQXTNv1i16 >+ 553920128U, // UQXTNv1i32 >+ 553920128U, // UQXTNv1i8 >+ 1611142784U, // UQXTNv2i32 >+ 2685408896U, // UQXTNv4i16 >+ 1645490526U, // UQXTNv4i32 >+ 2719494494U, // UQXTNv8i16 >+ 3223066240U, // UQXTNv8i8 >+ 1074271121U, // URECPEv2i32 >+ 2685670289U, // URECPEv4i32 >+ 2147488564U, // URHADDv16i8 >+ 2684883764U, // URHADDv2i32 >+ 3222278964U, // URHADDv4i16 >+ 1075057460U, // URHADDv4i32 >+ 1612190516U, // URHADDv8i16 >+ 3759936308U, // URHADDv8i8 >+ 2147489123U, // URSHLv16i8 >+ 17048931U, // URSHLv1i64 >+ 2684884323U, // URSHLv2i32 >+ 537662819U, // URSHLv2i64 >+ 3222279523U, // URSHLv4i16 >+ 1075058019U, // URSHLv4i32 >+ 1612191075U, // URSHLv8i16 >+ 3759936867U, // URSHLv8i8 >+ 17049508U, // URSHRd >+ 2147489700U, // URSHRv16i8_shift >+ 2684884900U, // URSHRv2i32_shift >+ 537663396U, // URSHRv2i64_shift >+ 3222280100U, // URSHRv4i16_shift >+ 1075058596U, // URSHRv4i32_shift >+ 1612191652U, // URSHRv8i16_shift >+ 3759937444U, // URSHRv8i8_shift >+ 1074271159U, // URSQRTEv2i32 >+ 2685670327U, // URSQRTEv4i32 >+ 67404295U, // URSRAd >+ 2181050887U, // URSRAv16i8_shift >+ 2718446087U, // URSRAv2i32_shift >+ 571224583U, // URSRAv2i64_shift >+ 3255841287U, // URSRAv4i16_shift >+ 1108619783U, // URSRAv4i32_shift >+ 1645752839U, // URSRAv8i16_shift >+ 3793498631U, // URSRAv8i8_shift >+ 2149060804U, // USHLLv16i8_shift >+ 2685146493U, // USHLLv2i32_shift >+ 3222541693U, // USHLLv4i16_shift >+ 1074532548U, // USHLLv4i32_shift >+ 1611927748U, // USHLLv8i16_shift >+ 3759674749U, // USHLLv8i8_shift >+ 2147489136U, // USHLv16i8 >+ 17048944U, // USHLv1i64 >+ 2684884336U, // USHLv2i32 >+ 537662832U, // USHLv2i64 >+ 3222279536U, // USHLv4i16 >+ 1075058032U, // USHLv4i32 >+ 1612191088U, // USHLv8i16 >+ 3759936880U, // USHLv8i8 >+ 17049521U, // USHRd >+ 2147489713U, // USHRv16i8_shift >+ 2684884913U, // USHRv2i32_shift >+ 537663409U, // USHRv2i64_shift >+ 3222280113U, // USHRv4i16_shift >+ 1075058609U, // USHRv4i32_shift >+ 1612191665U, // USHRv8i16_shift >+ 3759937457U, // USHRv8i8_shift >+ 33567577U, // USQADDv16i8 >+ 604275545U, // USQADDv1i16 >+ 604275545U, // USQADDv1i32 >+ 604275545U, // USQADDv1i64 >+ 604275545U, // USQADDv1i8 >+ 1107833689U, // USQADDv2i32 >+ 1644966745U, // USQADDv2i64 >+ 2182099801U, // USQADDv4i16 >+ 2719232857U, // USQADDv4i32 >+ 3256365913U, // USQADDv8i16 >+ 3793498969U, // USQADDv8i8 >+ 67404308U, // USRAd >+ 2181050900U, // USRAv16i8_shift >+ 2718446100U, // USRAv2i32_shift >+ 571224596U, // USRAv2i64_shift >+ 3255841300U, // USRAv4i16_shift >+ 1108619796U, // USRAv4i32_shift >+ 1645752852U, // USRAv8i16_shift >+ 3793498644U, // USRAv8i8_shift >+ 2149060756U, // USUBLv16i8_v8i16 >+ 2685146372U, // USUBLv2i32_v2i64 >+ 3222541572U, // USUBLv4i16_v4i32 >+ 1074532500U, // USUBLv4i32_v2i64 >+ 1611927700U, // USUBLv8i16_v4i32 >+ 3759674628U, // USUBLv8i8_v8i16 >+ 1612190125U, // USUBWv16i8_v8i16 >+ 537663920U, // USUBWv2i32_v2i64 >+ 1075059120U, // USUBWv4i16_v4i32 >+ 537661869U, // USUBWv4i32_v2i64 >+ 1075057069U, // USUBWv8i16_v4i32 >+ 1612192176U, // USUBWv8i8_v8i16 >+ 2147487782U, // UZP1v16i8 >+ 2684882982U, // UZP1v2i32 >+ 537661478U, // UZP1v2i64 >+ 3222278182U, // UZP1v4i16 >+ 1075056678U, // UZP1v4i32 >+ 1612189734U, // UZP1v8i16 >+ 3759935526U, // UZP1v8i8 >+ 2147488147U, // UZP2v16i8 >+ 2684883347U, // UZP2v2i32 >+ 537661843U, // UZP2v2i64 >+ 3222278547U, // UZP2v4i16 >+ 1075057043U, // UZP2v4i32 >+ 1612190099U, // UZP2v8i16 >+ 3759935891U, // UZP2v8i8 >+ 3254792536U, // XTNv16i8 >+ 1611142779U, // XTNv2i32 >+ 2685408891U, // XTNv4i16 >+ 1645490520U, // XTNv4i32 >+ 2719494488U, // XTNv8i16 >+ 3223066235U, // XTNv8i8 >+ 2147487776U, // ZIP1v16i8 >+ 2684882976U, // ZIP1v2i32 >+ 537661472U, // ZIP1v2i64 >+ 3222278176U, // ZIP1v4i16 >+ 1075056672U, // ZIP1v4i32 >+ 1612189728U, // ZIP1v8i16 >+ 3759935520U, // ZIP1v8i8 >+ 2147488141U, // ZIP2v16i8 >+ 2684883341U, // ZIP2v2i32 >+ 537661837U, // ZIP2v2i64 >+ 3222278541U, // ZIP2v4i16 >+ 1075057037U, // ZIP2v4i32 >+ 1612190093U, // ZIP2v8i16 >+ 3759935885U, // ZIP2v8i8 >+ 0U >+ }; >+ >+ static const uint32_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // ABSv16i8 >+ 0U, // ABSv1i64 >+ 0U, // ABSv2i32 >+ 0U, // ABSv2i64 >+ 0U, // ABSv4i16 >+ 0U, // ABSv4i32 >+ 0U, // ABSv8i16 >+ 0U, // ABSv8i8 >+ 1U, // ADCSWr >+ 1U, // ADCSXr >+ 1U, // ADCWr >+ 1U, // ADCXr >+ 265U, // ADDHNv2i64_v2i32 >+ 273U, // ADDHNv2i64_v4i32 >+ 521U, // ADDHNv4i32_v4i16 >+ 529U, // ADDHNv4i32_v8i16 >+ 785U, // ADDHNv8i16_v16i8 >+ 777U, // ADDHNv8i16_v8i8 >+ 1033U, // ADDPv16i8 >+ 1289U, // ADDPv2i32 >+ 265U, // ADDPv2i64 >+ 0U, // ADDPv2i64p >+ 1545U, // ADDPv4i16 >+ 521U, // ADDPv4i32 >+ 777U, // ADDPv8i16 >+ 1801U, // ADDPv8i8 >+ 25U, // ADDSWri >+ 0U, // ADDSWrr >+ 33U, // ADDSWrs >+ 41U, // ADDSWrx >+ 25U, // ADDSXri >+ 0U, // ADDSXrr >+ 33U, // ADDSXrs >+ 41U, // ADDSXrx >+ 2049U, // ADDSXrx64 >+ 0U, // ADDVv16i8v >+ 0U, // ADDVv4i16v >+ 0U, // ADDVv4i32v >+ 0U, // ADDVv8i16v >+ 0U, // ADDVv8i8v >+ 25U, // ADDWri >+ 0U, // ADDWrr >+ 33U, // ADDWrs >+ 41U, // ADDWrx >+ 25U, // ADDXri >+ 0U, // ADDXrr >+ 33U, // ADDXrs >+ 41U, // ADDXrx >+ 2049U, // ADDXrx64 >+ 1033U, // ADDv16i8 >+ 1U, // ADDv1i64 >+ 1289U, // ADDv2i32 >+ 265U, // ADDv2i64 >+ 1545U, // ADDv4i16 >+ 521U, // ADDv4i32 >+ 777U, // ADDv8i16 >+ 1801U, // ADDv8i8 >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 0U, // ADR >+ 0U, // ADRP >+ 0U, // AESDrr >+ 0U, // AESErr >+ 0U, // AESIMCrr >+ 0U, // AESMCrr >+ 49U, // ANDSWri >+ 0U, // ANDSWrr >+ 33U, // ANDSWrs >+ 57U, // ANDSXri >+ 0U, // ANDSXrr >+ 33U, // ANDSXrs >+ 49U, // ANDWri >+ 0U, // ANDWrr >+ 33U, // ANDWrs >+ 57U, // ANDXri >+ 0U, // ANDXrr >+ 33U, // ANDXrs >+ 1033U, // ANDv16i8 >+ 1801U, // ANDv8i8 >+ 1U, // ASRVWr >+ 1U, // ASRVXr >+ 0U, // B >+ 2369U, // BFMWri >+ 2369U, // BFMXri >+ 0U, // BICSWrr >+ 33U, // BICSWrs >+ 0U, // BICSXrr >+ 33U, // BICSXrs >+ 0U, // BICWrr >+ 33U, // BICWrs >+ 0U, // BICXrr >+ 33U, // BICXrs >+ 1033U, // BICv16i8 >+ 0U, // BICv2i32 >+ 0U, // BICv4i16 >+ 0U, // BICv4i32 >+ 0U, // BICv8i16 >+ 1801U, // BICv8i8 >+ 1033U, // BIFv16i8 >+ 1801U, // BIFv8i8 >+ 1041U, // BITv16i8 >+ 1809U, // BITv8i8 >+ 0U, // BL >+ 0U, // BLR >+ 0U, // BR >+ 0U, // BRK >+ 1041U, // BSLv16i8 >+ 1809U, // BSLv8i8 >+ 0U, // Bcc >+ 0U, // CBNZW >+ 0U, // CBNZX >+ 0U, // CBZW >+ 0U, // CBZX >+ 10497U, // CCMNWi >+ 10497U, // CCMNWr >+ 10497U, // CCMNXi >+ 10497U, // CCMNXr >+ 10497U, // CCMPWi >+ 10497U, // CCMPWr >+ 10497U, // CCMPXi >+ 10497U, // CCMPXr >+ 0U, // CLREX >+ 0U, // CLSWr >+ 0U, // CLSXr >+ 0U, // CLSv16i8 >+ 0U, // CLSv2i32 >+ 0U, // CLSv4i16 >+ 0U, // CLSv4i32 >+ 0U, // CLSv8i16 >+ 0U, // CLSv8i8 >+ 0U, // CLZWr >+ 0U, // CLZXr >+ 0U, // CLZv16i8 >+ 0U, // CLZv2i32 >+ 0U, // CLZv4i16 >+ 0U, // CLZv4i32 >+ 0U, // CLZv8i16 >+ 0U, // CLZv8i8 >+ 1033U, // CMEQv16i8 >+ 2U, // CMEQv16i8rz >+ 1U, // CMEQv1i64 >+ 2U, // CMEQv1i64rz >+ 1289U, // CMEQv2i32 >+ 2U, // CMEQv2i32rz >+ 265U, // CMEQv2i64 >+ 2U, // CMEQv2i64rz >+ 1545U, // CMEQv4i16 >+ 2U, // CMEQv4i16rz >+ 521U, // CMEQv4i32 >+ 2U, // CMEQv4i32rz >+ 777U, // CMEQv8i16 >+ 2U, // CMEQv8i16rz >+ 1801U, // CMEQv8i8 >+ 2U, // CMEQv8i8rz >+ 1033U, // CMGEv16i8 >+ 2U, // CMGEv16i8rz >+ 1U, // CMGEv1i64 >+ 2U, // CMGEv1i64rz >+ 1289U, // CMGEv2i32 >+ 2U, // CMGEv2i32rz >+ 265U, // CMGEv2i64 >+ 2U, // CMGEv2i64rz >+ 1545U, // CMGEv4i16 >+ 2U, // CMGEv4i16rz >+ 521U, // CMGEv4i32 >+ 2U, // CMGEv4i32rz >+ 777U, // CMGEv8i16 >+ 2U, // CMGEv8i16rz >+ 1801U, // CMGEv8i8 >+ 2U, // CMGEv8i8rz >+ 1033U, // CMGTv16i8 >+ 2U, // CMGTv16i8rz >+ 1U, // CMGTv1i64 >+ 2U, // CMGTv1i64rz >+ 1289U, // CMGTv2i32 >+ 2U, // CMGTv2i32rz >+ 265U, // CMGTv2i64 >+ 2U, // CMGTv2i64rz >+ 1545U, // CMGTv4i16 >+ 2U, // CMGTv4i16rz >+ 521U, // CMGTv4i32 >+ 2U, // CMGTv4i32rz >+ 777U, // CMGTv8i16 >+ 2U, // CMGTv8i16rz >+ 1801U, // CMGTv8i8 >+ 2U, // CMGTv8i8rz >+ 1033U, // CMHIv16i8 >+ 1U, // CMHIv1i64 >+ 1289U, // CMHIv2i32 >+ 265U, // CMHIv2i64 >+ 1545U, // CMHIv4i16 >+ 521U, // CMHIv4i32 >+ 777U, // CMHIv8i16 >+ 1801U, // CMHIv8i8 >+ 1033U, // CMHSv16i8 >+ 1U, // CMHSv1i64 >+ 1289U, // CMHSv2i32 >+ 265U, // CMHSv2i64 >+ 1545U, // CMHSv4i16 >+ 521U, // CMHSv4i32 >+ 777U, // CMHSv8i16 >+ 1801U, // CMHSv8i8 >+ 2U, // CMLEv16i8rz >+ 2U, // CMLEv1i64rz >+ 2U, // CMLEv2i32rz >+ 2U, // CMLEv2i64rz >+ 2U, // CMLEv4i16rz >+ 2U, // CMLEv4i32rz >+ 2U, // CMLEv8i16rz >+ 2U, // CMLEv8i8rz >+ 2U, // CMLTv16i8rz >+ 2U, // CMLTv1i64rz >+ 2U, // CMLTv2i32rz >+ 2U, // CMLTv2i64rz >+ 2U, // CMLTv4i16rz >+ 2U, // CMLTv4i32rz >+ 2U, // CMLTv8i16rz >+ 2U, // CMLTv8i8rz >+ 1033U, // CMTSTv16i8 >+ 1U, // CMTSTv1i64 >+ 1289U, // CMTSTv2i32 >+ 265U, // CMTSTv2i64 >+ 1545U, // CMTSTv4i16 >+ 521U, // CMTSTv4i32 >+ 777U, // CMTSTv8i16 >+ 1801U, // CMTSTv8i8 >+ 0U, // CNTv16i8 >+ 0U, // CNTv8i8 >+ 75U, // CPYi16 >+ 75U, // CPYi32 >+ 75U, // CPYi64 >+ 75U, // CPYi8 >+ 1U, // CRC32Brr >+ 1U, // CRC32CBrr >+ 1U, // CRC32CHrr >+ 1U, // CRC32CWrr >+ 1U, // CRC32CXrr >+ 1U, // CRC32Hrr >+ 1U, // CRC32Wrr >+ 1U, // CRC32Xrr >+ 10497U, // CSELWr >+ 10497U, // CSELXr >+ 10497U, // CSINCWr >+ 10497U, // CSINCXr >+ 10497U, // CSINVWr >+ 10497U, // CSINVXr >+ 10497U, // CSNEGWr >+ 10497U, // CSNEGXr >+ 0U, // DCPS1 >+ 0U, // DCPS2 >+ 0U, // DCPS3 >+ 0U, // DMB >+ 0U, // DRPS >+ 0U, // DSB >+ 0U, // DUPv16i8gpr >+ 75U, // DUPv16i8lane >+ 0U, // DUPv2i32gpr >+ 75U, // DUPv2i32lane >+ 0U, // DUPv2i64gpr >+ 75U, // DUPv2i64lane >+ 0U, // DUPv4i16gpr >+ 75U, // DUPv4i16lane >+ 0U, // DUPv4i32gpr >+ 75U, // DUPv4i32lane >+ 0U, // DUPv8i16gpr >+ 75U, // DUPv8i16lane >+ 0U, // DUPv8i8gpr >+ 75U, // DUPv8i8lane >+ 0U, // EONWrr >+ 33U, // EONWrs >+ 0U, // EONXrr >+ 33U, // EONXrs >+ 49U, // EORWri >+ 0U, // EORWrr >+ 33U, // EORWrs >+ 57U, // EORXri >+ 0U, // EORXrr >+ 33U, // EORXrs >+ 1033U, // EORv16i8 >+ 1801U, // EORv8i8 >+ 0U, // ERET >+ 18689U, // EXTRWrri >+ 18689U, // EXTRXrri >+ 2569U, // EXTv16i8 >+ 2825U, // EXTv8i8 >+ 0U, // F128CSEL >+ 1U, // FABD32 >+ 1U, // FABD64 >+ 1289U, // FABDv2f32 >+ 265U, // FABDv2f64 >+ 521U, // FABDv4f32 >+ 0U, // FABSDr >+ 0U, // FABSSr >+ 0U, // FABSv2f32 >+ 0U, // FABSv2f64 >+ 0U, // FABSv4f32 >+ 1U, // FACGE32 >+ 1U, // FACGE64 >+ 1289U, // FACGEv2f32 >+ 265U, // FACGEv2f64 >+ 521U, // FACGEv4f32 >+ 1U, // FACGT32 >+ 1U, // FACGT64 >+ 1289U, // FACGTv2f32 >+ 265U, // FACGTv2f64 >+ 521U, // FACGTv4f32 >+ 1U, // FADDDrr >+ 1289U, // FADDPv2f32 >+ 265U, // FADDPv2f64 >+ 0U, // FADDPv2i32p >+ 0U, // FADDPv2i64p >+ 521U, // FADDPv4f32 >+ 1U, // FADDSrr >+ 1289U, // FADDv2f32 >+ 265U, // FADDv2f64 >+ 521U, // FADDv4f32 >+ 10497U, // FCCMPDrr >+ 10497U, // FCCMPEDrr >+ 10497U, // FCCMPESrr >+ 10497U, // FCCMPSrr >+ 1U, // FCMEQ32 >+ 1U, // FCMEQ64 >+ 3U, // FCMEQv1i32rz >+ 3U, // FCMEQv1i64rz >+ 1289U, // FCMEQv2f32 >+ 265U, // FCMEQv2f64 >+ 3U, // FCMEQv2i32rz >+ 3U, // FCMEQv2i64rz >+ 521U, // FCMEQv4f32 >+ 3U, // FCMEQv4i32rz >+ 1U, // FCMGE32 >+ 1U, // FCMGE64 >+ 3U, // FCMGEv1i32rz >+ 3U, // FCMGEv1i64rz >+ 1289U, // FCMGEv2f32 >+ 265U, // FCMGEv2f64 >+ 3U, // FCMGEv2i32rz >+ 3U, // FCMGEv2i64rz >+ 521U, // FCMGEv4f32 >+ 3U, // FCMGEv4i32rz >+ 1U, // FCMGT32 >+ 1U, // FCMGT64 >+ 3U, // FCMGTv1i32rz >+ 3U, // FCMGTv1i64rz >+ 1289U, // FCMGTv2f32 >+ 265U, // FCMGTv2f64 >+ 3U, // FCMGTv2i32rz >+ 3U, // FCMGTv2i64rz >+ 521U, // FCMGTv4f32 >+ 3U, // FCMGTv4i32rz >+ 3U, // FCMLEv1i32rz >+ 3U, // FCMLEv1i64rz >+ 3U, // FCMLEv2i32rz >+ 3U, // FCMLEv2i64rz >+ 3U, // FCMLEv4i32rz >+ 3U, // FCMLTv1i32rz >+ 3U, // FCMLTv1i64rz >+ 3U, // FCMLTv2i32rz >+ 3U, // FCMLTv2i64rz >+ 3U, // FCMLTv4i32rz >+ 0U, // FCMPDri >+ 0U, // FCMPDrr >+ 0U, // FCMPEDri >+ 0U, // FCMPEDrr >+ 0U, // FCMPESri >+ 0U, // FCMPESrr >+ 0U, // FCMPSri >+ 0U, // FCMPSrr >+ 10497U, // FCSELDrrr >+ 10497U, // FCSELSrrr >+ 0U, // FCVTASUWDr >+ 0U, // FCVTASUWSr >+ 0U, // FCVTASUXDr >+ 0U, // FCVTASUXSr >+ 0U, // FCVTASv1i32 >+ 0U, // FCVTASv1i64 >+ 0U, // FCVTASv2f32 >+ 0U, // FCVTASv2f64 >+ 0U, // FCVTASv4f32 >+ 0U, // FCVTAUUWDr >+ 0U, // FCVTAUUWSr >+ 0U, // FCVTAUUXDr >+ 0U, // FCVTAUUXSr >+ 0U, // FCVTAUv1i32 >+ 0U, // FCVTAUv1i64 >+ 0U, // FCVTAUv2f32 >+ 0U, // FCVTAUv2f64 >+ 0U, // FCVTAUv4f32 >+ 0U, // FCVTDHr >+ 0U, // FCVTDSr >+ 0U, // FCVTHDr >+ 0U, // FCVTHSr >+ 0U, // FCVTLv2i32 >+ 0U, // FCVTLv4i16 >+ 0U, // FCVTLv4i32 >+ 0U, // FCVTLv8i16 >+ 0U, // FCVTMSUWDr >+ 0U, // FCVTMSUWSr >+ 0U, // FCVTMSUXDr >+ 0U, // FCVTMSUXSr >+ 0U, // FCVTMSv1i32 >+ 0U, // FCVTMSv1i64 >+ 0U, // FCVTMSv2f32 >+ 0U, // FCVTMSv2f64 >+ 0U, // FCVTMSv4f32 >+ 0U, // FCVTMUUWDr >+ 0U, // FCVTMUUWSr >+ 0U, // FCVTMUUXDr >+ 0U, // FCVTMUUXSr >+ 0U, // FCVTMUv1i32 >+ 0U, // FCVTMUv1i64 >+ 0U, // FCVTMUv2f32 >+ 0U, // FCVTMUv2f64 >+ 0U, // FCVTMUv4f32 >+ 0U, // FCVTNSUWDr >+ 0U, // FCVTNSUWSr >+ 0U, // FCVTNSUXDr >+ 0U, // FCVTNSUXSr >+ 0U, // FCVTNSv1i32 >+ 0U, // FCVTNSv1i64 >+ 0U, // FCVTNSv2f32 >+ 0U, // FCVTNSv2f64 >+ 0U, // FCVTNSv4f32 >+ 0U, // FCVTNUUWDr >+ 0U, // FCVTNUUWSr >+ 0U, // FCVTNUUXDr >+ 0U, // FCVTNUUXSr >+ 0U, // FCVTNUv1i32 >+ 0U, // FCVTNUv1i64 >+ 0U, // FCVTNUv2f32 >+ 0U, // FCVTNUv2f64 >+ 0U, // FCVTNUv4f32 >+ 0U, // FCVTNv2i32 >+ 0U, // FCVTNv4i16 >+ 0U, // FCVTNv4i32 >+ 0U, // FCVTNv8i16 >+ 0U, // FCVTPSUWDr >+ 0U, // FCVTPSUWSr >+ 0U, // FCVTPSUXDr >+ 0U, // FCVTPSUXSr >+ 0U, // FCVTPSv1i32 >+ 0U, // FCVTPSv1i64 >+ 0U, // FCVTPSv2f32 >+ 0U, // FCVTPSv2f64 >+ 0U, // FCVTPSv4f32 >+ 0U, // FCVTPUUWDr >+ 0U, // FCVTPUUWSr >+ 0U, // FCVTPUUXDr >+ 0U, // FCVTPUUXSr >+ 0U, // FCVTPUv1i32 >+ 0U, // FCVTPUv1i64 >+ 0U, // FCVTPUv2f32 >+ 0U, // FCVTPUv2f64 >+ 0U, // FCVTPUv4f32 >+ 0U, // FCVTSDr >+ 0U, // FCVTSHr >+ 0U, // FCVTXNv1i64 >+ 0U, // FCVTXNv2f32 >+ 0U, // FCVTXNv4f32 >+ 1U, // FCVTZSSWDri >+ 1U, // FCVTZSSWSri >+ 1U, // FCVTZSSXDri >+ 1U, // FCVTZSSXSri >+ 0U, // FCVTZSUWDr >+ 0U, // FCVTZSUWSr >+ 0U, // FCVTZSUXDr >+ 0U, // FCVTZSUXSr >+ 1U, // FCVTZS_IntSWDri >+ 1U, // FCVTZS_IntSWSri >+ 1U, // FCVTZS_IntSXDri >+ 1U, // FCVTZS_IntSXSri >+ 0U, // FCVTZS_IntUWDr >+ 0U, // FCVTZS_IntUWSr >+ 0U, // FCVTZS_IntUXDr >+ 0U, // FCVTZS_IntUXSr >+ 0U, // FCVTZS_Intv2f32 >+ 0U, // FCVTZS_Intv2f64 >+ 0U, // FCVTZS_Intv4f32 >+ 1U, // FCVTZSd >+ 1U, // FCVTZSs >+ 0U, // FCVTZSv1i32 >+ 0U, // FCVTZSv1i64 >+ 0U, // FCVTZSv2f32 >+ 0U, // FCVTZSv2f64 >+ 1U, // FCVTZSv2i32_shift >+ 1U, // FCVTZSv2i64_shift >+ 0U, // FCVTZSv4f32 >+ 1U, // FCVTZSv4i32_shift >+ 1U, // FCVTZUSWDri >+ 1U, // FCVTZUSWSri >+ 1U, // FCVTZUSXDri >+ 1U, // FCVTZUSXSri >+ 0U, // FCVTZUUWDr >+ 0U, // FCVTZUUWSr >+ 0U, // FCVTZUUXDr >+ 0U, // FCVTZUUXSr >+ 1U, // FCVTZU_IntSWDri >+ 1U, // FCVTZU_IntSWSri >+ 1U, // FCVTZU_IntSXDri >+ 1U, // FCVTZU_IntSXSri >+ 0U, // FCVTZU_IntUWDr >+ 0U, // FCVTZU_IntUWSr >+ 0U, // FCVTZU_IntUXDr >+ 0U, // FCVTZU_IntUXSr >+ 0U, // FCVTZU_Intv2f32 >+ 0U, // FCVTZU_Intv2f64 >+ 0U, // FCVTZU_Intv4f32 >+ 1U, // FCVTZUd >+ 1U, // FCVTZUs >+ 0U, // FCVTZUv1i32 >+ 0U, // FCVTZUv1i64 >+ 0U, // FCVTZUv2f32 >+ 0U, // FCVTZUv2f64 >+ 1U, // FCVTZUv2i32_shift >+ 1U, // FCVTZUv2i64_shift >+ 0U, // FCVTZUv4f32 >+ 1U, // FCVTZUv4i32_shift >+ 1U, // FDIVDrr >+ 1U, // FDIVSrr >+ 1289U, // FDIVv2f32 >+ 265U, // FDIVv2f64 >+ 521U, // FDIVv4f32 >+ 18689U, // FMADDDrrr >+ 18689U, // FMADDSrrr >+ 1U, // FMAXDrr >+ 1U, // FMAXNMDrr >+ 1289U, // FMAXNMPv2f32 >+ 265U, // FMAXNMPv2f64 >+ 0U, // FMAXNMPv2i32p >+ 0U, // FMAXNMPv2i64p >+ 521U, // FMAXNMPv4f32 >+ 1U, // FMAXNMSrr >+ 0U, // FMAXNMVv4i32v >+ 1289U, // FMAXNMv2f32 >+ 265U, // FMAXNMv2f64 >+ 521U, // FMAXNMv4f32 >+ 1289U, // FMAXPv2f32 >+ 265U, // FMAXPv2f64 >+ 0U, // FMAXPv2i32p >+ 0U, // FMAXPv2i64p >+ 521U, // FMAXPv4f32 >+ 1U, // FMAXSrr >+ 0U, // FMAXVv4i32v >+ 1289U, // FMAXv2f32 >+ 265U, // FMAXv2f64 >+ 521U, // FMAXv4f32 >+ 1U, // FMINDrr >+ 1U, // FMINNMDrr >+ 1289U, // FMINNMPv2f32 >+ 265U, // FMINNMPv2f64 >+ 0U, // FMINNMPv2i32p >+ 0U, // FMINNMPv2i64p >+ 521U, // FMINNMPv4f32 >+ 1U, // FMINNMSrr >+ 0U, // FMINNMVv4i32v >+ 1289U, // FMINNMv2f32 >+ 265U, // FMINNMv2f64 >+ 521U, // FMINNMv4f32 >+ 1289U, // FMINPv2f32 >+ 265U, // FMINPv2f64 >+ 0U, // FMINPv2i32p >+ 0U, // FMINPv2i64p >+ 521U, // FMINPv4f32 >+ 1U, // FMINSrr >+ 0U, // FMINVv4i32v >+ 1289U, // FMINv2f32 >+ 265U, // FMINv2f64 >+ 521U, // FMINv4f32 >+ 27665U, // FMLAv1i32_indexed >+ 27921U, // FMLAv1i64_indexed >+ 1297U, // FMLAv2f32 >+ 273U, // FMLAv2f64 >+ 27665U, // FMLAv2i32_indexed >+ 27921U, // FMLAv2i64_indexed >+ 529U, // FMLAv4f32 >+ 27665U, // FMLAv4i32_indexed >+ 27665U, // FMLSv1i32_indexed >+ 27921U, // FMLSv1i64_indexed >+ 1297U, // FMLSv2f32 >+ 273U, // FMLSv2f64 >+ 27665U, // FMLSv2i32_indexed >+ 27921U, // FMLSv2i64_indexed >+ 529U, // FMLSv4f32 >+ 27665U, // FMLSv4i32_indexed >+ 75U, // FMOVDXHighr >+ 0U, // FMOVDXr >+ 0U, // FMOVDi >+ 0U, // FMOVDr >+ 0U, // FMOVSWr >+ 0U, // FMOVSi >+ 0U, // FMOVSr >+ 0U, // FMOVWSr >+ 0U, // FMOVXDHighr >+ 0U, // FMOVXDr >+ 0U, // FMOVv2f32_ns >+ 0U, // FMOVv2f64_ns >+ 0U, // FMOVv4f32_ns >+ 18689U, // FMSUBDrrr >+ 18689U, // FMSUBSrrr >+ 1U, // FMULDrr >+ 1U, // FMULSrr >+ 1U, // FMULX32 >+ 1U, // FMULX64 >+ 35849U, // FMULXv1i32_indexed >+ 36105U, // FMULXv1i64_indexed >+ 1289U, // FMULXv2f32 >+ 265U, // FMULXv2f64 >+ 35849U, // FMULXv2i32_indexed >+ 36105U, // FMULXv2i64_indexed >+ 521U, // FMULXv4f32 >+ 35849U, // FMULXv4i32_indexed >+ 35849U, // FMULv1i32_indexed >+ 36105U, // FMULv1i64_indexed >+ 1289U, // FMULv2f32 >+ 265U, // FMULv2f64 >+ 35849U, // FMULv2i32_indexed >+ 36105U, // FMULv2i64_indexed >+ 521U, // FMULv4f32 >+ 35849U, // FMULv4i32_indexed >+ 0U, // FNEGDr >+ 0U, // FNEGSr >+ 0U, // FNEGv2f32 >+ 0U, // FNEGv2f64 >+ 0U, // FNEGv4f32 >+ 18689U, // FNMADDDrrr >+ 18689U, // FNMADDSrrr >+ 18689U, // FNMSUBDrrr >+ 18689U, // FNMSUBSrrr >+ 1U, // FNMULDrr >+ 1U, // FNMULSrr >+ 0U, // FRECPEv1i32 >+ 0U, // FRECPEv1i64 >+ 0U, // FRECPEv2f32 >+ 0U, // FRECPEv2f64 >+ 0U, // FRECPEv4f32 >+ 1U, // FRECPS32 >+ 1U, // FRECPS64 >+ 1289U, // FRECPSv2f32 >+ 265U, // FRECPSv2f64 >+ 521U, // FRECPSv4f32 >+ 0U, // FRECPXv1i32 >+ 0U, // FRECPXv1i64 >+ 0U, // FRINTADr >+ 0U, // FRINTASr >+ 0U, // FRINTAv2f32 >+ 0U, // FRINTAv2f64 >+ 0U, // FRINTAv4f32 >+ 0U, // FRINTIDr >+ 0U, // FRINTISr >+ 0U, // FRINTIv2f32 >+ 0U, // FRINTIv2f64 >+ 0U, // FRINTIv4f32 >+ 0U, // FRINTMDr >+ 0U, // FRINTMSr >+ 0U, // FRINTMv2f32 >+ 0U, // FRINTMv2f64 >+ 0U, // FRINTMv4f32 >+ 0U, // FRINTNDr >+ 0U, // FRINTNSr >+ 0U, // FRINTNv2f32 >+ 0U, // FRINTNv2f64 >+ 0U, // FRINTNv4f32 >+ 0U, // FRINTPDr >+ 0U, // FRINTPSr >+ 0U, // FRINTPv2f32 >+ 0U, // FRINTPv2f64 >+ 0U, // FRINTPv4f32 >+ 0U, // FRINTXDr >+ 0U, // FRINTXSr >+ 0U, // FRINTXv2f32 >+ 0U, // FRINTXv2f64 >+ 0U, // FRINTXv4f32 >+ 0U, // FRINTZDr >+ 0U, // FRINTZSr >+ 0U, // FRINTZv2f32 >+ 0U, // FRINTZv2f64 >+ 0U, // FRINTZv4f32 >+ 0U, // FRSQRTEv1i32 >+ 0U, // FRSQRTEv1i64 >+ 0U, // FRSQRTEv2f32 >+ 0U, // FRSQRTEv2f64 >+ 0U, // FRSQRTEv4f32 >+ 1U, // FRSQRTS32 >+ 1U, // FRSQRTS64 >+ 1289U, // FRSQRTSv2f32 >+ 265U, // FRSQRTSv2f64 >+ 521U, // FRSQRTSv4f32 >+ 0U, // FSQRTDr >+ 0U, // FSQRTSr >+ 0U, // FSQRTv2f32 >+ 0U, // FSQRTv2f64 >+ 0U, // FSQRTv4f32 >+ 1U, // FSUBDrr >+ 1U, // FSUBSrr >+ 1289U, // FSUBv2f32 >+ 265U, // FSUBv2f64 >+ 521U, // FSUBv4f32 >+ 0U, // HINT >+ 0U, // HLT >+ 0U, // HVC >+ 0U, // INSvi16gpr >+ 83U, // INSvi16lane >+ 0U, // INSvi32gpr >+ 83U, // INSvi32lane >+ 0U, // INSvi64gpr >+ 83U, // INSvi64lane >+ 0U, // INSvi8gpr >+ 83U, // INSvi8lane >+ 0U, // ISB >+ 0U, // LD1Fourv16b >+ 0U, // LD1Fourv16b_POST >+ 0U, // LD1Fourv1d >+ 0U, // LD1Fourv1d_POST >+ 0U, // LD1Fourv2d >+ 0U, // LD1Fourv2d_POST >+ 0U, // LD1Fourv2s >+ 0U, // LD1Fourv2s_POST >+ 0U, // LD1Fourv4h >+ 0U, // LD1Fourv4h_POST >+ 0U, // LD1Fourv4s >+ 0U, // LD1Fourv4s_POST >+ 0U, // LD1Fourv8b >+ 0U, // LD1Fourv8b_POST >+ 0U, // LD1Fourv8h >+ 0U, // LD1Fourv8h_POST >+ 0U, // LD1Onev16b >+ 0U, // LD1Onev16b_POST >+ 0U, // LD1Onev1d >+ 0U, // LD1Onev1d_POST >+ 0U, // LD1Onev2d >+ 0U, // LD1Onev2d_POST >+ 0U, // LD1Onev2s >+ 0U, // LD1Onev2s_POST >+ 0U, // LD1Onev4h >+ 0U, // LD1Onev4h_POST >+ 0U, // LD1Onev4s >+ 0U, // LD1Onev4s_POST >+ 0U, // LD1Onev8b >+ 0U, // LD1Onev8b_POST >+ 0U, // LD1Onev8h >+ 0U, // LD1Onev8h_POST >+ 0U, // LD1Rv16b >+ 0U, // LD1Rv16b_POST >+ 0U, // LD1Rv1d >+ 0U, // LD1Rv1d_POST >+ 0U, // LD1Rv2d >+ 0U, // LD1Rv2d_POST >+ 0U, // LD1Rv2s >+ 0U, // LD1Rv2s_POST >+ 0U, // LD1Rv4h >+ 0U, // LD1Rv4h_POST >+ 0U, // LD1Rv4s >+ 0U, // LD1Rv4s_POST >+ 0U, // LD1Rv8b >+ 0U, // LD1Rv8b_POST >+ 0U, // LD1Rv8h >+ 0U, // LD1Rv8h_POST >+ 0U, // LD1Threev16b >+ 0U, // LD1Threev16b_POST >+ 0U, // LD1Threev1d >+ 0U, // LD1Threev1d_POST >+ 0U, // LD1Threev2d >+ 0U, // LD1Threev2d_POST >+ 0U, // LD1Threev2s >+ 0U, // LD1Threev2s_POST >+ 0U, // LD1Threev4h >+ 0U, // LD1Threev4h_POST >+ 0U, // LD1Threev4s >+ 0U, // LD1Threev4s_POST >+ 0U, // LD1Threev8b >+ 0U, // LD1Threev8b_POST >+ 0U, // LD1Threev8h >+ 0U, // LD1Threev8h_POST >+ 0U, // LD1Twov16b >+ 0U, // LD1Twov16b_POST >+ 0U, // LD1Twov1d >+ 0U, // LD1Twov1d_POST >+ 0U, // LD1Twov2d >+ 0U, // LD1Twov2d_POST >+ 0U, // LD1Twov2s >+ 0U, // LD1Twov2s_POST >+ 0U, // LD1Twov4h >+ 0U, // LD1Twov4h_POST >+ 0U, // LD1Twov4s >+ 0U, // LD1Twov4s_POST >+ 0U, // LD1Twov8b >+ 0U, // LD1Twov8b_POST >+ 0U, // LD1Twov8h >+ 0U, // LD1Twov8h_POST >+ 0U, // LD1i16 >+ 0U, // LD1i16_POST >+ 0U, // LD1i32 >+ 0U, // LD1i32_POST >+ 0U, // LD1i64 >+ 0U, // LD1i64_POST >+ 0U, // LD1i8 >+ 0U, // LD1i8_POST >+ 0U, // LD2Rv16b >+ 0U, // LD2Rv16b_POST >+ 0U, // LD2Rv1d >+ 0U, // LD2Rv1d_POST >+ 0U, // LD2Rv2d >+ 0U, // LD2Rv2d_POST >+ 0U, // LD2Rv2s >+ 0U, // LD2Rv2s_POST >+ 0U, // LD2Rv4h >+ 0U, // LD2Rv4h_POST >+ 0U, // LD2Rv4s >+ 0U, // LD2Rv4s_POST >+ 0U, // LD2Rv8b >+ 0U, // LD2Rv8b_POST >+ 0U, // LD2Rv8h >+ 0U, // LD2Rv8h_POST >+ 0U, // LD2Twov16b >+ 0U, // LD2Twov16b_POST >+ 0U, // LD2Twov2d >+ 0U, // LD2Twov2d_POST >+ 0U, // LD2Twov2s >+ 0U, // LD2Twov2s_POST >+ 0U, // LD2Twov4h >+ 0U, // LD2Twov4h_POST >+ 0U, // LD2Twov4s >+ 0U, // LD2Twov4s_POST >+ 0U, // LD2Twov8b >+ 0U, // LD2Twov8b_POST >+ 0U, // LD2Twov8h >+ 0U, // LD2Twov8h_POST >+ 0U, // LD2i16 >+ 0U, // LD2i16_POST >+ 0U, // LD2i32 >+ 0U, // LD2i32_POST >+ 0U, // LD2i64 >+ 0U, // LD2i64_POST >+ 0U, // LD2i8 >+ 0U, // LD2i8_POST >+ 0U, // LD3Rv16b >+ 0U, // LD3Rv16b_POST >+ 0U, // LD3Rv1d >+ 0U, // LD3Rv1d_POST >+ 0U, // LD3Rv2d >+ 0U, // LD3Rv2d_POST >+ 0U, // LD3Rv2s >+ 0U, // LD3Rv2s_POST >+ 0U, // LD3Rv4h >+ 0U, // LD3Rv4h_POST >+ 0U, // LD3Rv4s >+ 0U, // LD3Rv4s_POST >+ 0U, // LD3Rv8b >+ 0U, // LD3Rv8b_POST >+ 0U, // LD3Rv8h >+ 0U, // LD3Rv8h_POST >+ 0U, // LD3Threev16b >+ 0U, // LD3Threev16b_POST >+ 0U, // LD3Threev2d >+ 0U, // LD3Threev2d_POST >+ 0U, // LD3Threev2s >+ 0U, // LD3Threev2s_POST >+ 0U, // LD3Threev4h >+ 0U, // LD3Threev4h_POST >+ 0U, // LD3Threev4s >+ 0U, // LD3Threev4s_POST >+ 0U, // LD3Threev8b >+ 0U, // LD3Threev8b_POST >+ 0U, // LD3Threev8h >+ 0U, // LD3Threev8h_POST >+ 0U, // LD3i16 >+ 0U, // LD3i16_POST >+ 0U, // LD3i32 >+ 0U, // LD3i32_POST >+ 0U, // LD3i64 >+ 0U, // LD3i64_POST >+ 0U, // LD3i8 >+ 0U, // LD3i8_POST >+ 0U, // LD4Fourv16b >+ 0U, // LD4Fourv16b_POST >+ 0U, // LD4Fourv2d >+ 0U, // LD4Fourv2d_POST >+ 0U, // LD4Fourv2s >+ 0U, // LD4Fourv2s_POST >+ 0U, // LD4Fourv4h >+ 0U, // LD4Fourv4h_POST >+ 0U, // LD4Fourv4s >+ 0U, // LD4Fourv4s_POST >+ 0U, // LD4Fourv8b >+ 0U, // LD4Fourv8b_POST >+ 0U, // LD4Fourv8h >+ 0U, // LD4Fourv8h_POST >+ 0U, // LD4Rv16b >+ 0U, // LD4Rv16b_POST >+ 0U, // LD4Rv1d >+ 0U, // LD4Rv1d_POST >+ 0U, // LD4Rv2d >+ 0U, // LD4Rv2d_POST >+ 0U, // LD4Rv2s >+ 0U, // LD4Rv2s_POST >+ 0U, // LD4Rv4h >+ 0U, // LD4Rv4h_POST >+ 0U, // LD4Rv4s >+ 0U, // LD4Rv4s_POST >+ 0U, // LD4Rv8b >+ 0U, // LD4Rv8b_POST >+ 0U, // LD4Rv8h >+ 0U, // LD4Rv8h_POST >+ 0U, // LD4i16 >+ 0U, // LD4i16_POST >+ 0U, // LD4i32 >+ 0U, // LD4i32_POST >+ 0U, // LD4i64 >+ 0U, // LD4i64_POST >+ 0U, // LD4i8 >+ 0U, // LD4i8_POST >+ 4U, // LDARB >+ 4U, // LDARH >+ 4U, // LDARW >+ 4U, // LDARX >+ 3588U, // LDAXPW >+ 3588U, // LDAXPX >+ 4U, // LDAXRB >+ 4U, // LDAXRH >+ 4U, // LDAXRW >+ 4U, // LDAXRX >+ 43268U, // LDNPDi >+ 51460U, // LDNPQi >+ 59652U, // LDNPSi >+ 59652U, // LDNPWi >+ 43268U, // LDNPXi >+ 43268U, // LDPDi >+ 69444U, // LDPDpost >+ 330052U, // LDPDpre >+ 51460U, // LDPQi >+ 77636U, // LDPQpost >+ 338244U, // LDPQpre >+ 59652U, // LDPSWi >+ 85828U, // LDPSWpost >+ 346436U, // LDPSWpre >+ 59652U, // LDPSi >+ 85828U, // LDPSpost >+ 346436U, // LDPSpre >+ 59652U, // LDPWi >+ 85828U, // LDPWpost >+ 346436U, // LDPWpre >+ 43268U, // LDPXi >+ 69444U, // LDPXpost >+ 330052U, // LDPXpre >+ 4U, // LDRBBpost >+ 4161U, // LDRBBpre >+ 92417U, // LDRBBroW >+ 100609U, // LDRBBroX >+ 89U, // LDRBBui >+ 4U, // LDRBpost >+ 4161U, // LDRBpre >+ 92417U, // LDRBroW >+ 100609U, // LDRBroX >+ 89U, // LDRBui >+ 0U, // LDRDl >+ 4U, // LDRDpost >+ 4161U, // LDRDpre >+ 108801U, // LDRDroW >+ 116993U, // LDRDroX >+ 97U, // LDRDui >+ 4U, // LDRHHpost >+ 4161U, // LDRHHpre >+ 125185U, // LDRHHroW >+ 133377U, // LDRHHroX >+ 105U, // LDRHHui >+ 4U, // LDRHpost >+ 4161U, // LDRHpre >+ 125185U, // LDRHroW >+ 133377U, // LDRHroX >+ 105U, // LDRHui >+ 0U, // LDRQl >+ 4U, // LDRQpost >+ 4161U, // LDRQpre >+ 141569U, // LDRQroW >+ 149761U, // LDRQroX >+ 113U, // LDRQui >+ 4U, // LDRSBWpost >+ 4161U, // LDRSBWpre >+ 92417U, // LDRSBWroW >+ 100609U, // LDRSBWroX >+ 89U, // LDRSBWui >+ 4U, // LDRSBXpost >+ 4161U, // LDRSBXpre >+ 92417U, // LDRSBXroW >+ 100609U, // LDRSBXroX >+ 89U, // LDRSBXui >+ 4U, // LDRSHWpost >+ 4161U, // LDRSHWpre >+ 125185U, // LDRSHWroW >+ 133377U, // LDRSHWroX >+ 105U, // LDRSHWui >+ 4U, // LDRSHXpost >+ 4161U, // LDRSHXpre >+ 125185U, // LDRSHXroW >+ 133377U, // LDRSHXroX >+ 105U, // LDRSHXui >+ 0U, // LDRSWl >+ 4U, // LDRSWpost >+ 4161U, // LDRSWpre >+ 157953U, // LDRSWroW >+ 166145U, // LDRSWroX >+ 121U, // LDRSWui >+ 0U, // LDRSl >+ 4U, // LDRSpost >+ 4161U, // LDRSpre >+ 157953U, // LDRSroW >+ 166145U, // LDRSroX >+ 121U, // LDRSui >+ 0U, // LDRWl >+ 4U, // LDRWpost >+ 4161U, // LDRWpre >+ 157953U, // LDRWroW >+ 166145U, // LDRWroX >+ 121U, // LDRWui >+ 0U, // LDRXl >+ 4U, // LDRXpost >+ 4161U, // LDRXpre >+ 108801U, // LDRXroW >+ 116993U, // LDRXroX >+ 97U, // LDRXui >+ 3585U, // LDTRBi >+ 3585U, // LDTRHi >+ 3585U, // LDTRSBWi >+ 3585U, // LDTRSBXi >+ 3585U, // LDTRSHWi >+ 3585U, // LDTRSHXi >+ 3585U, // LDTRSWi >+ 3585U, // LDTRWi >+ 3585U, // LDTRXi >+ 3585U, // LDURBBi >+ 3585U, // LDURBi >+ 3585U, // LDURDi >+ 3585U, // LDURHHi >+ 3585U, // LDURHi >+ 3585U, // LDURQi >+ 3585U, // LDURSBWi >+ 3585U, // LDURSBXi >+ 3585U, // LDURSHWi >+ 3585U, // LDURSHXi >+ 3585U, // LDURSWi >+ 3585U, // LDURSi >+ 3585U, // LDURWi >+ 3585U, // LDURXi >+ 3588U, // LDXPW >+ 3588U, // LDXPX >+ 4U, // LDXRB >+ 4U, // LDXRH >+ 4U, // LDXRW >+ 4U, // LDXRX >+ 0U, // LOADgot >+ 1U, // LSLVWr >+ 1U, // LSLVXr >+ 1U, // LSRVWr >+ 1U, // LSRVXr >+ 18689U, // MADDWrrr >+ 18689U, // MADDXrrr >+ 1041U, // MLAv16i8 >+ 1297U, // MLAv2i32 >+ 27665U, // MLAv2i32_indexed >+ 1553U, // MLAv4i16 >+ 28945U, // MLAv4i16_indexed >+ 529U, // MLAv4i32 >+ 27665U, // MLAv4i32_indexed >+ 785U, // MLAv8i16 >+ 28945U, // MLAv8i16_indexed >+ 1809U, // MLAv8i8 >+ 1041U, // MLSv16i8 >+ 1297U, // MLSv2i32 >+ 27665U, // MLSv2i32_indexed >+ 1553U, // MLSv4i16 >+ 28945U, // MLSv4i16_indexed >+ 529U, // MLSv4i32 >+ 27665U, // MLSv4i32_indexed >+ 785U, // MLSv8i16 >+ 28945U, // MLSv8i16_indexed >+ 1809U, // MLSv8i8 >+ 0U, // MOVID >+ 0U, // MOVIv16b_ns >+ 0U, // MOVIv2d_ns >+ 4U, // MOVIv2i32 >+ 4U, // MOVIv2s_msl >+ 4U, // MOVIv4i16 >+ 4U, // MOVIv4i32 >+ 4U, // MOVIv4s_msl >+ 0U, // MOVIv8b_ns >+ 4U, // MOVIv8i16 >+ 0U, // MOVKWi >+ 0U, // MOVKXi >+ 4U, // MOVNWi >+ 4U, // MOVNXi >+ 4U, // MOVZWi >+ 4U, // MOVZXi >+ 0U, // MOVaddr >+ 0U, // MOVaddrBA >+ 0U, // MOVaddrCP >+ 0U, // MOVaddrEXT >+ 0U, // MOVaddrJT >+ 0U, // MOVaddrTLS >+ 0U, // MOVi32imm >+ 0U, // MOVi64imm >+ 0U, // MRS >+ 0U, // MSR >+ 0U, // MSRpstate >+ 18689U, // MSUBWrrr >+ 18689U, // MSUBXrrr >+ 1033U, // MULv16i8 >+ 1289U, // MULv2i32 >+ 35849U, // MULv2i32_indexed >+ 1545U, // MULv4i16 >+ 37129U, // MULv4i16_indexed >+ 521U, // MULv4i32 >+ 35849U, // MULv4i32_indexed >+ 777U, // MULv8i16 >+ 37129U, // MULv8i16_indexed >+ 1801U, // MULv8i8 >+ 4U, // MVNIv2i32 >+ 4U, // MVNIv2s_msl >+ 4U, // MVNIv4i16 >+ 4U, // MVNIv4i32 >+ 4U, // MVNIv4s_msl >+ 4U, // MVNIv8i16 >+ 0U, // NEGv16i8 >+ 0U, // NEGv1i64 >+ 0U, // NEGv2i32 >+ 0U, // NEGv2i64 >+ 0U, // NEGv4i16 >+ 0U, // NEGv4i32 >+ 0U, // NEGv8i16 >+ 0U, // NEGv8i8 >+ 0U, // NOTv16i8 >+ 0U, // NOTv8i8 >+ 0U, // ORNWrr >+ 33U, // ORNWrs >+ 0U, // ORNXrr >+ 33U, // ORNXrs >+ 1033U, // ORNv16i8 >+ 1801U, // ORNv8i8 >+ 49U, // ORRWri >+ 0U, // ORRWrr >+ 33U, // ORRWrs >+ 57U, // ORRXri >+ 0U, // ORRXrr >+ 33U, // ORRXrs >+ 1033U, // ORRv16i8 >+ 0U, // ORRv2i32 >+ 0U, // ORRv4i16 >+ 0U, // ORRv4i32 >+ 0U, // ORRv8i16 >+ 1801U, // ORRv8i8 >+ 1033U, // PMULLv16i8 >+ 0U, // PMULLv1i64 >+ 0U, // PMULLv2i64 >+ 1801U, // PMULLv8i8 >+ 1033U, // PMULv16i8 >+ 1801U, // PMULv8i8 >+ 0U, // PRFMl >+ 108801U, // PRFMroW >+ 116993U, // PRFMroX >+ 97U, // PRFMui >+ 3585U, // PRFUMi >+ 265U, // RADDHNv2i64_v2i32 >+ 273U, // RADDHNv2i64_v4i32 >+ 521U, // RADDHNv4i32_v4i16 >+ 529U, // RADDHNv4i32_v8i16 >+ 785U, // RADDHNv8i16_v16i8 >+ 777U, // RADDHNv8i16_v8i8 >+ 0U, // RBITWr >+ 0U, // RBITXr >+ 0U, // RBITv16i8 >+ 0U, // RBITv8i8 >+ 0U, // RET >+ 0U, // RET_ReallyLR >+ 0U, // REV16Wr >+ 0U, // REV16Xr >+ 0U, // REV16v16i8 >+ 0U, // REV16v8i8 >+ 0U, // REV32Xr >+ 0U, // REV32v16i8 >+ 0U, // REV32v4i16 >+ 0U, // REV32v8i16 >+ 0U, // REV32v8i8 >+ 0U, // REV64v16i8 >+ 0U, // REV64v2i32 >+ 0U, // REV64v4i16 >+ 0U, // REV64v4i32 >+ 0U, // REV64v8i16 >+ 0U, // REV64v8i8 >+ 0U, // REVWr >+ 0U, // REVXr >+ 1U, // RORVWr >+ 1U, // RORVXr >+ 65U, // RSHRNv16i8_shift >+ 1U, // RSHRNv2i32_shift >+ 1U, // RSHRNv4i16_shift >+ 65U, // RSHRNv4i32_shift >+ 65U, // RSHRNv8i16_shift >+ 1U, // RSHRNv8i8_shift >+ 265U, // RSUBHNv2i64_v2i32 >+ 273U, // RSUBHNv2i64_v4i32 >+ 521U, // RSUBHNv4i32_v4i16 >+ 529U, // RSUBHNv4i32_v8i16 >+ 785U, // RSUBHNv8i16_v16i8 >+ 777U, // RSUBHNv8i16_v8i8 >+ 1041U, // SABALv16i8_v8i16 >+ 1297U, // SABALv2i32_v2i64 >+ 1553U, // SABALv4i16_v4i32 >+ 529U, // SABALv4i32_v2i64 >+ 785U, // SABALv8i16_v4i32 >+ 1809U, // SABALv8i8_v8i16 >+ 1041U, // SABAv16i8 >+ 1297U, // SABAv2i32 >+ 1553U, // SABAv4i16 >+ 529U, // SABAv4i32 >+ 785U, // SABAv8i16 >+ 1809U, // SABAv8i8 >+ 1033U, // SABDLv16i8_v8i16 >+ 1289U, // SABDLv2i32_v2i64 >+ 1545U, // SABDLv4i16_v4i32 >+ 521U, // SABDLv4i32_v2i64 >+ 777U, // SABDLv8i16_v4i32 >+ 1801U, // SABDLv8i8_v8i16 >+ 1033U, // SABDv16i8 >+ 1289U, // SABDv2i32 >+ 1545U, // SABDv4i16 >+ 521U, // SABDv4i32 >+ 777U, // SABDv8i16 >+ 1801U, // SABDv8i8 >+ 0U, // SADALPv16i8_v8i16 >+ 0U, // SADALPv2i32_v1i64 >+ 0U, // SADALPv4i16_v2i32 >+ 0U, // SADALPv4i32_v2i64 >+ 0U, // SADALPv8i16_v4i32 >+ 0U, // SADALPv8i8_v4i16 >+ 0U, // SADDLPv16i8_v8i16 >+ 0U, // SADDLPv2i32_v1i64 >+ 0U, // SADDLPv4i16_v2i32 >+ 0U, // SADDLPv4i32_v2i64 >+ 0U, // SADDLPv8i16_v4i32 >+ 0U, // SADDLPv8i8_v4i16 >+ 0U, // SADDLVv16i8v >+ 0U, // SADDLVv4i16v >+ 0U, // SADDLVv4i32v >+ 0U, // SADDLVv8i16v >+ 0U, // SADDLVv8i8v >+ 1033U, // SADDLv16i8_v8i16 >+ 1289U, // SADDLv2i32_v2i64 >+ 1545U, // SADDLv4i16_v4i32 >+ 521U, // SADDLv4i32_v2i64 >+ 777U, // SADDLv8i16_v4i32 >+ 1801U, // SADDLv8i8_v8i16 >+ 1033U, // SADDWv16i8_v8i16 >+ 1289U, // SADDWv2i32_v2i64 >+ 1545U, // SADDWv4i16_v4i32 >+ 521U, // SADDWv4i32_v2i64 >+ 777U, // SADDWv8i16_v4i32 >+ 1801U, // SADDWv8i8_v8i16 >+ 1U, // SBCSWr >+ 1U, // SBCSXr >+ 1U, // SBCWr >+ 1U, // SBCXr >+ 18689U, // SBFMWri >+ 18689U, // SBFMXri >+ 1U, // SCVTFSWDri >+ 1U, // SCVTFSWSri >+ 1U, // SCVTFSXDri >+ 1U, // SCVTFSXSri >+ 0U, // SCVTFUWDri >+ 0U, // SCVTFUWSri >+ 0U, // SCVTFUXDri >+ 0U, // SCVTFUXSri >+ 1U, // SCVTFd >+ 1U, // SCVTFs >+ 0U, // SCVTFv1i32 >+ 0U, // SCVTFv1i64 >+ 0U, // SCVTFv2f32 >+ 0U, // SCVTFv2f64 >+ 1U, // SCVTFv2i32_shift >+ 1U, // SCVTFv2i64_shift >+ 0U, // SCVTFv4f32 >+ 1U, // SCVTFv4i32_shift >+ 1U, // SDIVWr >+ 1U, // SDIVXr >+ 1U, // SDIV_IntWr >+ 1U, // SDIV_IntXr >+ 529U, // SHA1Crrr >+ 0U, // SHA1Hrr >+ 529U, // SHA1Mrrr >+ 529U, // SHA1Prrr >+ 529U, // SHA1SU0rrr >+ 0U, // SHA1SU1rr >+ 529U, // SHA256H2rrr >+ 529U, // SHA256Hrrr >+ 0U, // SHA256SU0rr >+ 529U, // SHA256SU1rrr >+ 1033U, // SHADDv16i8 >+ 1289U, // SHADDv2i32 >+ 1545U, // SHADDv4i16 >+ 521U, // SHADDv4i32 >+ 777U, // SHADDv8i16 >+ 1801U, // SHADDv8i8 >+ 4U, // SHLLv16i8 >+ 4U, // SHLLv2i32 >+ 4U, // SHLLv4i16 >+ 4U, // SHLLv4i32 >+ 5U, // SHLLv8i16 >+ 5U, // SHLLv8i8 >+ 1U, // SHLd >+ 1U, // SHLv16i8_shift >+ 1U, // SHLv2i32_shift >+ 1U, // SHLv2i64_shift >+ 1U, // SHLv4i16_shift >+ 1U, // SHLv4i32_shift >+ 1U, // SHLv8i16_shift >+ 1U, // SHLv8i8_shift >+ 65U, // SHRNv16i8_shift >+ 1U, // SHRNv2i32_shift >+ 1U, // SHRNv4i16_shift >+ 65U, // SHRNv4i32_shift >+ 65U, // SHRNv8i16_shift >+ 1U, // SHRNv8i8_shift >+ 1033U, // SHSUBv16i8 >+ 1289U, // SHSUBv2i32 >+ 1545U, // SHSUBv4i16 >+ 521U, // SHSUBv4i32 >+ 777U, // SHSUBv8i16 >+ 1801U, // SHSUBv8i8 >+ 65U, // SLId >+ 65U, // SLIv16i8_shift >+ 65U, // SLIv2i32_shift >+ 65U, // SLIv2i64_shift >+ 65U, // SLIv4i16_shift >+ 65U, // SLIv4i32_shift >+ 65U, // SLIv8i16_shift >+ 65U, // SLIv8i8_shift >+ 18689U, // SMADDLrrr >+ 1033U, // SMAXPv16i8 >+ 1289U, // SMAXPv2i32 >+ 1545U, // SMAXPv4i16 >+ 521U, // SMAXPv4i32 >+ 777U, // SMAXPv8i16 >+ 1801U, // SMAXPv8i8 >+ 0U, // SMAXVv16i8v >+ 0U, // SMAXVv4i16v >+ 0U, // SMAXVv4i32v >+ 0U, // SMAXVv8i16v >+ 0U, // SMAXVv8i8v >+ 1033U, // SMAXv16i8 >+ 1289U, // SMAXv2i32 >+ 1545U, // SMAXv4i16 >+ 521U, // SMAXv4i32 >+ 777U, // SMAXv8i16 >+ 1801U, // SMAXv8i8 >+ 0U, // SMC >+ 1033U, // SMINPv16i8 >+ 1289U, // SMINPv2i32 >+ 1545U, // SMINPv4i16 >+ 521U, // SMINPv4i32 >+ 777U, // SMINPv8i16 >+ 1801U, // SMINPv8i8 >+ 0U, // SMINVv16i8v >+ 0U, // SMINVv4i16v >+ 0U, // SMINVv4i32v >+ 0U, // SMINVv8i16v >+ 0U, // SMINVv8i8v >+ 1033U, // SMINv16i8 >+ 1289U, // SMINv2i32 >+ 1545U, // SMINv4i16 >+ 521U, // SMINv4i32 >+ 777U, // SMINv8i16 >+ 1801U, // SMINv8i8 >+ 1041U, // SMLALv16i8_v8i16 >+ 27665U, // SMLALv2i32_indexed >+ 1297U, // SMLALv2i32_v2i64 >+ 28945U, // SMLALv4i16_indexed >+ 1553U, // SMLALv4i16_v4i32 >+ 27665U, // SMLALv4i32_indexed >+ 529U, // SMLALv4i32_v2i64 >+ 28945U, // SMLALv8i16_indexed >+ 785U, // SMLALv8i16_v4i32 >+ 1809U, // SMLALv8i8_v8i16 >+ 1041U, // SMLSLv16i8_v8i16 >+ 27665U, // SMLSLv2i32_indexed >+ 1297U, // SMLSLv2i32_v2i64 >+ 28945U, // SMLSLv4i16_indexed >+ 1553U, // SMLSLv4i16_v4i32 >+ 27665U, // SMLSLv4i32_indexed >+ 529U, // SMLSLv4i32_v2i64 >+ 28945U, // SMLSLv8i16_indexed >+ 785U, // SMLSLv8i16_v4i32 >+ 1809U, // SMLSLv8i8_v8i16 >+ 75U, // SMOVvi16to32 >+ 75U, // SMOVvi16to64 >+ 75U, // SMOVvi32to64 >+ 75U, // SMOVvi8to32 >+ 75U, // SMOVvi8to64 >+ 18689U, // SMSUBLrrr >+ 1U, // SMULHrr >+ 1033U, // SMULLv16i8_v8i16 >+ 35849U, // SMULLv2i32_indexed >+ 1289U, // SMULLv2i32_v2i64 >+ 37129U, // SMULLv4i16_indexed >+ 1545U, // SMULLv4i16_v4i32 >+ 35849U, // SMULLv4i32_indexed >+ 521U, // SMULLv4i32_v2i64 >+ 37129U, // SMULLv8i16_indexed >+ 777U, // SMULLv8i16_v4i32 >+ 1801U, // SMULLv8i8_v8i16 >+ 0U, // SQABSv16i8 >+ 0U, // SQABSv1i16 >+ 0U, // SQABSv1i32 >+ 0U, // SQABSv1i64 >+ 0U, // SQABSv1i8 >+ 0U, // SQABSv2i32 >+ 0U, // SQABSv2i64 >+ 0U, // SQABSv4i16 >+ 0U, // SQABSv4i32 >+ 0U, // SQABSv8i16 >+ 0U, // SQABSv8i8 >+ 1033U, // SQADDv16i8 >+ 1U, // SQADDv1i16 >+ 1U, // SQADDv1i32 >+ 1U, // SQADDv1i64 >+ 1U, // SQADDv1i8 >+ 1289U, // SQADDv2i32 >+ 265U, // SQADDv2i64 >+ 1545U, // SQADDv4i16 >+ 521U, // SQADDv4i32 >+ 777U, // SQADDv8i16 >+ 1801U, // SQADDv8i8 >+ 65U, // SQDMLALi16 >+ 65U, // SQDMLALi32 >+ 28945U, // SQDMLALv1i32_indexed >+ 27665U, // SQDMLALv1i64_indexed >+ 27665U, // SQDMLALv2i32_indexed >+ 1297U, // SQDMLALv2i32_v2i64 >+ 28945U, // SQDMLALv4i16_indexed >+ 1553U, // SQDMLALv4i16_v4i32 >+ 27665U, // SQDMLALv4i32_indexed >+ 529U, // SQDMLALv4i32_v2i64 >+ 28945U, // SQDMLALv8i16_indexed >+ 785U, // SQDMLALv8i16_v4i32 >+ 65U, // SQDMLSLi16 >+ 65U, // SQDMLSLi32 >+ 28945U, // SQDMLSLv1i32_indexed >+ 27665U, // SQDMLSLv1i64_indexed >+ 27665U, // SQDMLSLv2i32_indexed >+ 1297U, // SQDMLSLv2i32_v2i64 >+ 28945U, // SQDMLSLv4i16_indexed >+ 1553U, // SQDMLSLv4i16_v4i32 >+ 27665U, // SQDMLSLv4i32_indexed >+ 529U, // SQDMLSLv4i32_v2i64 >+ 28945U, // SQDMLSLv8i16_indexed >+ 785U, // SQDMLSLv8i16_v4i32 >+ 1U, // SQDMULHv1i16 >+ 37129U, // SQDMULHv1i16_indexed >+ 1U, // SQDMULHv1i32 >+ 35849U, // SQDMULHv1i32_indexed >+ 1289U, // SQDMULHv2i32 >+ 35849U, // SQDMULHv2i32_indexed >+ 1545U, // SQDMULHv4i16 >+ 37129U, // SQDMULHv4i16_indexed >+ 521U, // SQDMULHv4i32 >+ 35849U, // SQDMULHv4i32_indexed >+ 777U, // SQDMULHv8i16 >+ 37129U, // SQDMULHv8i16_indexed >+ 1U, // SQDMULLi16 >+ 1U, // SQDMULLi32 >+ 37129U, // SQDMULLv1i32_indexed >+ 35849U, // SQDMULLv1i64_indexed >+ 35849U, // SQDMULLv2i32_indexed >+ 1289U, // SQDMULLv2i32_v2i64 >+ 37129U, // SQDMULLv4i16_indexed >+ 1545U, // SQDMULLv4i16_v4i32 >+ 35849U, // SQDMULLv4i32_indexed >+ 521U, // SQDMULLv4i32_v2i64 >+ 37129U, // SQDMULLv8i16_indexed >+ 777U, // SQDMULLv8i16_v4i32 >+ 0U, // SQNEGv16i8 >+ 0U, // SQNEGv1i16 >+ 0U, // SQNEGv1i32 >+ 0U, // SQNEGv1i64 >+ 0U, // SQNEGv1i8 >+ 0U, // SQNEGv2i32 >+ 0U, // SQNEGv2i64 >+ 0U, // SQNEGv4i16 >+ 0U, // SQNEGv4i32 >+ 0U, // SQNEGv8i16 >+ 0U, // SQNEGv8i8 >+ 1U, // SQRDMULHv1i16 >+ 37129U, // SQRDMULHv1i16_indexed >+ 1U, // SQRDMULHv1i32 >+ 35849U, // SQRDMULHv1i32_indexed >+ 1289U, // SQRDMULHv2i32 >+ 35849U, // SQRDMULHv2i32_indexed >+ 1545U, // SQRDMULHv4i16 >+ 37129U, // SQRDMULHv4i16_indexed >+ 521U, // SQRDMULHv4i32 >+ 35849U, // SQRDMULHv4i32_indexed >+ 777U, // SQRDMULHv8i16 >+ 37129U, // SQRDMULHv8i16_indexed >+ 1033U, // SQRSHLv16i8 >+ 1U, // SQRSHLv1i16 >+ 1U, // SQRSHLv1i32 >+ 1U, // SQRSHLv1i64 >+ 1U, // SQRSHLv1i8 >+ 1289U, // SQRSHLv2i32 >+ 265U, // SQRSHLv2i64 >+ 1545U, // SQRSHLv4i16 >+ 521U, // SQRSHLv4i32 >+ 777U, // SQRSHLv8i16 >+ 1801U, // SQRSHLv8i8 >+ 1U, // SQRSHRNb >+ 1U, // SQRSHRNh >+ 1U, // SQRSHRNs >+ 65U, // SQRSHRNv16i8_shift >+ 1U, // SQRSHRNv2i32_shift >+ 1U, // SQRSHRNv4i16_shift >+ 65U, // SQRSHRNv4i32_shift >+ 65U, // SQRSHRNv8i16_shift >+ 1U, // SQRSHRNv8i8_shift >+ 1U, // SQRSHRUNb >+ 1U, // SQRSHRUNh >+ 1U, // SQRSHRUNs >+ 65U, // SQRSHRUNv16i8_shift >+ 1U, // SQRSHRUNv2i32_shift >+ 1U, // SQRSHRUNv4i16_shift >+ 65U, // SQRSHRUNv4i32_shift >+ 65U, // SQRSHRUNv8i16_shift >+ 1U, // SQRSHRUNv8i8_shift >+ 1U, // SQSHLUb >+ 1U, // SQSHLUd >+ 1U, // SQSHLUh >+ 1U, // SQSHLUs >+ 1U, // SQSHLUv16i8_shift >+ 1U, // SQSHLUv2i32_shift >+ 1U, // SQSHLUv2i64_shift >+ 1U, // SQSHLUv4i16_shift >+ 1U, // SQSHLUv4i32_shift >+ 1U, // SQSHLUv8i16_shift >+ 1U, // SQSHLUv8i8_shift >+ 1U, // SQSHLb >+ 1U, // SQSHLd >+ 1U, // SQSHLh >+ 1U, // SQSHLs >+ 1033U, // SQSHLv16i8 >+ 1U, // SQSHLv16i8_shift >+ 1U, // SQSHLv1i16 >+ 1U, // SQSHLv1i32 >+ 1U, // SQSHLv1i64 >+ 1U, // SQSHLv1i8 >+ 1289U, // SQSHLv2i32 >+ 1U, // SQSHLv2i32_shift >+ 265U, // SQSHLv2i64 >+ 1U, // SQSHLv2i64_shift >+ 1545U, // SQSHLv4i16 >+ 1U, // SQSHLv4i16_shift >+ 521U, // SQSHLv4i32 >+ 1U, // SQSHLv4i32_shift >+ 777U, // SQSHLv8i16 >+ 1U, // SQSHLv8i16_shift >+ 1801U, // SQSHLv8i8 >+ 1U, // SQSHLv8i8_shift >+ 1U, // SQSHRNb >+ 1U, // SQSHRNh >+ 1U, // SQSHRNs >+ 65U, // SQSHRNv16i8_shift >+ 1U, // SQSHRNv2i32_shift >+ 1U, // SQSHRNv4i16_shift >+ 65U, // SQSHRNv4i32_shift >+ 65U, // SQSHRNv8i16_shift >+ 1U, // SQSHRNv8i8_shift >+ 1U, // SQSHRUNb >+ 1U, // SQSHRUNh >+ 1U, // SQSHRUNs >+ 65U, // SQSHRUNv16i8_shift >+ 1U, // SQSHRUNv2i32_shift >+ 1U, // SQSHRUNv4i16_shift >+ 65U, // SQSHRUNv4i32_shift >+ 65U, // SQSHRUNv8i16_shift >+ 1U, // SQSHRUNv8i8_shift >+ 1033U, // SQSUBv16i8 >+ 1U, // SQSUBv1i16 >+ 1U, // SQSUBv1i32 >+ 1U, // SQSUBv1i64 >+ 1U, // SQSUBv1i8 >+ 1289U, // SQSUBv2i32 >+ 265U, // SQSUBv2i64 >+ 1545U, // SQSUBv4i16 >+ 521U, // SQSUBv4i32 >+ 777U, // SQSUBv8i16 >+ 1801U, // SQSUBv8i8 >+ 0U, // SQXTNv16i8 >+ 0U, // SQXTNv1i16 >+ 0U, // SQXTNv1i32 >+ 0U, // SQXTNv1i8 >+ 0U, // SQXTNv2i32 >+ 0U, // SQXTNv4i16 >+ 0U, // SQXTNv4i32 >+ 0U, // SQXTNv8i16 >+ 0U, // SQXTNv8i8 >+ 0U, // SQXTUNv16i8 >+ 0U, // SQXTUNv1i16 >+ 0U, // SQXTUNv1i32 >+ 0U, // SQXTUNv1i8 >+ 0U, // SQXTUNv2i32 >+ 0U, // SQXTUNv4i16 >+ 0U, // SQXTUNv4i32 >+ 0U, // SQXTUNv8i16 >+ 0U, // SQXTUNv8i8 >+ 1033U, // SRHADDv16i8 >+ 1289U, // SRHADDv2i32 >+ 1545U, // SRHADDv4i16 >+ 521U, // SRHADDv4i32 >+ 777U, // SRHADDv8i16 >+ 1801U, // SRHADDv8i8 >+ 65U, // SRId >+ 65U, // SRIv16i8_shift >+ 65U, // SRIv2i32_shift >+ 65U, // SRIv2i64_shift >+ 65U, // SRIv4i16_shift >+ 65U, // SRIv4i32_shift >+ 65U, // SRIv8i16_shift >+ 65U, // SRIv8i8_shift >+ 1033U, // SRSHLv16i8 >+ 1U, // SRSHLv1i64 >+ 1289U, // SRSHLv2i32 >+ 265U, // SRSHLv2i64 >+ 1545U, // SRSHLv4i16 >+ 521U, // SRSHLv4i32 >+ 777U, // SRSHLv8i16 >+ 1801U, // SRSHLv8i8 >+ 1U, // SRSHRd >+ 1U, // SRSHRv16i8_shift >+ 1U, // SRSHRv2i32_shift >+ 1U, // SRSHRv2i64_shift >+ 1U, // SRSHRv4i16_shift >+ 1U, // SRSHRv4i32_shift >+ 1U, // SRSHRv8i16_shift >+ 1U, // SRSHRv8i8_shift >+ 65U, // SRSRAd >+ 65U, // SRSRAv16i8_shift >+ 65U, // SRSRAv2i32_shift >+ 65U, // SRSRAv2i64_shift >+ 65U, // SRSRAv4i16_shift >+ 65U, // SRSRAv4i32_shift >+ 65U, // SRSRAv8i16_shift >+ 65U, // SRSRAv8i8_shift >+ 1U, // SSHLLv16i8_shift >+ 1U, // SSHLLv2i32_shift >+ 1U, // SSHLLv4i16_shift >+ 1U, // SSHLLv4i32_shift >+ 1U, // SSHLLv8i16_shift >+ 1U, // SSHLLv8i8_shift >+ 1033U, // SSHLv16i8 >+ 1U, // SSHLv1i64 >+ 1289U, // SSHLv2i32 >+ 265U, // SSHLv2i64 >+ 1545U, // SSHLv4i16 >+ 521U, // SSHLv4i32 >+ 777U, // SSHLv8i16 >+ 1801U, // SSHLv8i8 >+ 1U, // SSHRd >+ 1U, // SSHRv16i8_shift >+ 1U, // SSHRv2i32_shift >+ 1U, // SSHRv2i64_shift >+ 1U, // SSHRv4i16_shift >+ 1U, // SSHRv4i32_shift >+ 1U, // SSHRv8i16_shift >+ 1U, // SSHRv8i8_shift >+ 65U, // SSRAd >+ 65U, // SSRAv16i8_shift >+ 65U, // SSRAv2i32_shift >+ 65U, // SSRAv2i64_shift >+ 65U, // SSRAv4i16_shift >+ 65U, // SSRAv4i32_shift >+ 65U, // SSRAv8i16_shift >+ 65U, // SSRAv8i8_shift >+ 1033U, // SSUBLv16i8_v8i16 >+ 1289U, // SSUBLv2i32_v2i64 >+ 1545U, // SSUBLv4i16_v4i32 >+ 521U, // SSUBLv4i32_v2i64 >+ 777U, // SSUBLv8i16_v4i32 >+ 1801U, // SSUBLv8i8_v8i16 >+ 1033U, // SSUBWv16i8_v8i16 >+ 1289U, // SSUBWv2i32_v2i64 >+ 1545U, // SSUBWv4i16_v4i32 >+ 521U, // SSUBWv4i32_v2i64 >+ 777U, // SSUBWv8i16_v4i32 >+ 1801U, // SSUBWv8i8_v8i16 >+ 0U, // ST1Fourv16b >+ 0U, // ST1Fourv16b_POST >+ 0U, // ST1Fourv1d >+ 0U, // ST1Fourv1d_POST >+ 0U, // ST1Fourv2d >+ 0U, // ST1Fourv2d_POST >+ 0U, // ST1Fourv2s >+ 0U, // ST1Fourv2s_POST >+ 0U, // ST1Fourv4h >+ 0U, // ST1Fourv4h_POST >+ 0U, // ST1Fourv4s >+ 0U, // ST1Fourv4s_POST >+ 0U, // ST1Fourv8b >+ 0U, // ST1Fourv8b_POST >+ 0U, // ST1Fourv8h >+ 0U, // ST1Fourv8h_POST >+ 0U, // ST1Onev16b >+ 0U, // ST1Onev16b_POST >+ 0U, // ST1Onev1d >+ 0U, // ST1Onev1d_POST >+ 0U, // ST1Onev2d >+ 0U, // ST1Onev2d_POST >+ 0U, // ST1Onev2s >+ 0U, // ST1Onev2s_POST >+ 0U, // ST1Onev4h >+ 0U, // ST1Onev4h_POST >+ 0U, // ST1Onev4s >+ 0U, // ST1Onev4s_POST >+ 0U, // ST1Onev8b >+ 0U, // ST1Onev8b_POST >+ 0U, // ST1Onev8h >+ 0U, // ST1Onev8h_POST >+ 0U, // ST1Threev16b >+ 0U, // ST1Threev16b_POST >+ 0U, // ST1Threev1d >+ 0U, // ST1Threev1d_POST >+ 0U, // ST1Threev2d >+ 0U, // ST1Threev2d_POST >+ 0U, // ST1Threev2s >+ 0U, // ST1Threev2s_POST >+ 0U, // ST1Threev4h >+ 0U, // ST1Threev4h_POST >+ 0U, // ST1Threev4s >+ 0U, // ST1Threev4s_POST >+ 0U, // ST1Threev8b >+ 0U, // ST1Threev8b_POST >+ 0U, // ST1Threev8h >+ 0U, // ST1Threev8h_POST >+ 0U, // ST1Twov16b >+ 0U, // ST1Twov16b_POST >+ 0U, // ST1Twov1d >+ 0U, // ST1Twov1d_POST >+ 0U, // ST1Twov2d >+ 0U, // ST1Twov2d_POST >+ 0U, // ST1Twov2s >+ 0U, // ST1Twov2s_POST >+ 0U, // ST1Twov4h >+ 0U, // ST1Twov4h_POST >+ 0U, // ST1Twov4s >+ 0U, // ST1Twov4s_POST >+ 0U, // ST1Twov8b >+ 0U, // ST1Twov8b_POST >+ 0U, // ST1Twov8h >+ 0U, // ST1Twov8h_POST >+ 0U, // ST1i16 >+ 0U, // ST1i16_POST >+ 0U, // ST1i32 >+ 0U, // ST1i32_POST >+ 0U, // ST1i64 >+ 0U, // ST1i64_POST >+ 0U, // ST1i8 >+ 0U, // ST1i8_POST >+ 0U, // ST2Twov16b >+ 0U, // ST2Twov16b_POST >+ 0U, // ST2Twov2d >+ 0U, // ST2Twov2d_POST >+ 0U, // ST2Twov2s >+ 0U, // ST2Twov2s_POST >+ 0U, // ST2Twov4h >+ 0U, // ST2Twov4h_POST >+ 0U, // ST2Twov4s >+ 0U, // ST2Twov4s_POST >+ 0U, // ST2Twov8b >+ 0U, // ST2Twov8b_POST >+ 0U, // ST2Twov8h >+ 0U, // ST2Twov8h_POST >+ 0U, // ST2i16 >+ 0U, // ST2i16_POST >+ 0U, // ST2i32 >+ 0U, // ST2i32_POST >+ 0U, // ST2i64 >+ 0U, // ST2i64_POST >+ 0U, // ST2i8 >+ 0U, // ST2i8_POST >+ 0U, // ST3Threev16b >+ 0U, // ST3Threev16b_POST >+ 0U, // ST3Threev2d >+ 0U, // ST3Threev2d_POST >+ 0U, // ST3Threev2s >+ 0U, // ST3Threev2s_POST >+ 0U, // ST3Threev4h >+ 0U, // ST3Threev4h_POST >+ 0U, // ST3Threev4s >+ 0U, // ST3Threev4s_POST >+ 0U, // ST3Threev8b >+ 0U, // ST3Threev8b_POST >+ 0U, // ST3Threev8h >+ 0U, // ST3Threev8h_POST >+ 0U, // ST3i16 >+ 0U, // ST3i16_POST >+ 0U, // ST3i32 >+ 0U, // ST3i32_POST >+ 0U, // ST3i64 >+ 0U, // ST3i64_POST >+ 0U, // ST3i8 >+ 0U, // ST3i8_POST >+ 0U, // ST4Fourv16b >+ 0U, // ST4Fourv16b_POST >+ 0U, // ST4Fourv2d >+ 0U, // ST4Fourv2d_POST >+ 0U, // ST4Fourv2s >+ 0U, // ST4Fourv2s_POST >+ 0U, // ST4Fourv4h >+ 0U, // ST4Fourv4h_POST >+ 0U, // ST4Fourv4s >+ 0U, // ST4Fourv4s_POST >+ 0U, // ST4Fourv8b >+ 0U, // ST4Fourv8b_POST >+ 0U, // ST4Fourv8h >+ 0U, // ST4Fourv8h_POST >+ 0U, // ST4i16 >+ 0U, // ST4i16_POST >+ 0U, // ST4i32 >+ 0U, // ST4i32_POST >+ 0U, // ST4i64 >+ 0U, // ST4i64_POST >+ 0U, // ST4i8 >+ 0U, // ST4i8_POST >+ 4U, // STLRB >+ 4U, // STLRH >+ 4U, // STLRW >+ 4U, // STLRX >+ 4609U, // STLXPW >+ 4609U, // STLXPX >+ 3588U, // STLXRB >+ 3588U, // STLXRH >+ 3588U, // STLXRW >+ 3588U, // STLXRX >+ 43268U, // STNPDi >+ 51460U, // STNPQi >+ 59652U, // STNPSi >+ 59652U, // STNPWi >+ 43268U, // STNPXi >+ 43268U, // STPDi >+ 69444U, // STPDpost >+ 330052U, // STPDpre >+ 51460U, // STPQi >+ 77636U, // STPQpost >+ 338244U, // STPQpre >+ 59652U, // STPSi >+ 85828U, // STPSpost >+ 346436U, // STPSpre >+ 59652U, // STPWi >+ 85828U, // STPWpost >+ 346436U, // STPWpre >+ 43268U, // STPXi >+ 69444U, // STPXpost >+ 330052U, // STPXpre >+ 4U, // STRBBpost >+ 4161U, // STRBBpre >+ 92417U, // STRBBroW >+ 100609U, // STRBBroX >+ 89U, // STRBBui >+ 4U, // STRBpost >+ 4161U, // STRBpre >+ 92417U, // STRBroW >+ 100609U, // STRBroX >+ 89U, // STRBui >+ 4U, // STRDpost >+ 4161U, // STRDpre >+ 108801U, // STRDroW >+ 116993U, // STRDroX >+ 97U, // STRDui >+ 4U, // STRHHpost >+ 4161U, // STRHHpre >+ 125185U, // STRHHroW >+ 133377U, // STRHHroX >+ 105U, // STRHHui >+ 4U, // STRHpost >+ 4161U, // STRHpre >+ 125185U, // STRHroW >+ 133377U, // STRHroX >+ 105U, // STRHui >+ 4U, // STRQpost >+ 4161U, // STRQpre >+ 141569U, // STRQroW >+ 149761U, // STRQroX >+ 113U, // STRQui >+ 4U, // STRSpost >+ 4161U, // STRSpre >+ 157953U, // STRSroW >+ 166145U, // STRSroX >+ 121U, // STRSui >+ 4U, // STRWpost >+ 4161U, // STRWpre >+ 157953U, // STRWroW >+ 166145U, // STRWroX >+ 121U, // STRWui >+ 4U, // STRXpost >+ 4161U, // STRXpre >+ 108801U, // STRXroW >+ 116993U, // STRXroX >+ 97U, // STRXui >+ 3585U, // STTRBi >+ 3585U, // STTRHi >+ 3585U, // STTRWi >+ 3585U, // STTRXi >+ 3585U, // STURBBi >+ 3585U, // STURBi >+ 3585U, // STURDi >+ 3585U, // STURHHi >+ 3585U, // STURHi >+ 3585U, // STURQi >+ 3585U, // STURSi >+ 3585U, // STURWi >+ 3585U, // STURXi >+ 4609U, // STXPW >+ 4609U, // STXPX >+ 3588U, // STXRB >+ 3588U, // STXRH >+ 3588U, // STXRW >+ 3588U, // STXRX >+ 265U, // SUBHNv2i64_v2i32 >+ 273U, // SUBHNv2i64_v4i32 >+ 521U, // SUBHNv4i32_v4i16 >+ 529U, // SUBHNv4i32_v8i16 >+ 785U, // SUBHNv8i16_v16i8 >+ 777U, // SUBHNv8i16_v8i8 >+ 25U, // SUBSWri >+ 0U, // SUBSWrr >+ 33U, // SUBSWrs >+ 41U, // SUBSWrx >+ 25U, // SUBSXri >+ 0U, // SUBSXrr >+ 33U, // SUBSXrs >+ 41U, // SUBSXrx >+ 2049U, // SUBSXrx64 >+ 25U, // SUBWri >+ 0U, // SUBWrr >+ 33U, // SUBWrs >+ 41U, // SUBWrx >+ 25U, // SUBXri >+ 0U, // SUBXrr >+ 33U, // SUBXrs >+ 41U, // SUBXrx >+ 2049U, // SUBXrx64 >+ 1033U, // SUBv16i8 >+ 1U, // SUBv1i64 >+ 1289U, // SUBv2i32 >+ 265U, // SUBv2i64 >+ 1545U, // SUBv4i16 >+ 521U, // SUBv4i32 >+ 777U, // SUBv8i16 >+ 1801U, // SUBv8i8 >+ 0U, // SUQADDv16i8 >+ 0U, // SUQADDv1i16 >+ 0U, // SUQADDv1i32 >+ 0U, // SUQADDv1i64 >+ 0U, // SUQADDv1i8 >+ 0U, // SUQADDv2i32 >+ 0U, // SUQADDv2i64 >+ 0U, // SUQADDv4i16 >+ 0U, // SUQADDv4i32 >+ 0U, // SUQADDv8i16 >+ 0U, // SUQADDv8i8 >+ 0U, // SVC >+ 129U, // SYSLxt >+ 0U, // SYSxt >+ 0U, // TBLv16i8Four >+ 0U, // TBLv16i8One >+ 0U, // TBLv16i8Three >+ 0U, // TBLv16i8Two >+ 0U, // TBLv8i8Four >+ 0U, // TBLv8i8One >+ 0U, // TBLv8i8Three >+ 0U, // TBLv8i8Two >+ 137U, // TBNZW >+ 137U, // TBNZX >+ 0U, // TBXv16i8Four >+ 0U, // TBXv16i8One >+ 0U, // TBXv16i8Three >+ 0U, // TBXv16i8Two >+ 0U, // TBXv8i8Four >+ 0U, // TBXv8i8One >+ 0U, // TBXv8i8Three >+ 0U, // TBXv8i8Two >+ 137U, // TBZW >+ 137U, // TBZX >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 0U, // TLSDESCCALL >+ 0U, // TLSDESC_BLR >+ 1033U, // TRN1v16i8 >+ 1289U, // TRN1v2i32 >+ 265U, // TRN1v2i64 >+ 1545U, // TRN1v4i16 >+ 521U, // TRN1v4i32 >+ 777U, // TRN1v8i16 >+ 1801U, // TRN1v8i8 >+ 1033U, // TRN2v16i8 >+ 1289U, // TRN2v2i32 >+ 265U, // TRN2v2i64 >+ 1545U, // TRN2v4i16 >+ 521U, // TRN2v4i32 >+ 777U, // TRN2v8i16 >+ 1801U, // TRN2v8i8 >+ 1041U, // UABALv16i8_v8i16 >+ 1297U, // UABALv2i32_v2i64 >+ 1553U, // UABALv4i16_v4i32 >+ 529U, // UABALv4i32_v2i64 >+ 785U, // UABALv8i16_v4i32 >+ 1809U, // UABALv8i8_v8i16 >+ 1041U, // UABAv16i8 >+ 1297U, // UABAv2i32 >+ 1553U, // UABAv4i16 >+ 529U, // UABAv4i32 >+ 785U, // UABAv8i16 >+ 1809U, // UABAv8i8 >+ 1033U, // UABDLv16i8_v8i16 >+ 1289U, // UABDLv2i32_v2i64 >+ 1545U, // UABDLv4i16_v4i32 >+ 521U, // UABDLv4i32_v2i64 >+ 777U, // UABDLv8i16_v4i32 >+ 1801U, // UABDLv8i8_v8i16 >+ 1033U, // UABDv16i8 >+ 1289U, // UABDv2i32 >+ 1545U, // UABDv4i16 >+ 521U, // UABDv4i32 >+ 777U, // UABDv8i16 >+ 1801U, // UABDv8i8 >+ 0U, // UADALPv16i8_v8i16 >+ 0U, // UADALPv2i32_v1i64 >+ 0U, // UADALPv4i16_v2i32 >+ 0U, // UADALPv4i32_v2i64 >+ 0U, // UADALPv8i16_v4i32 >+ 0U, // UADALPv8i8_v4i16 >+ 0U, // UADDLPv16i8_v8i16 >+ 0U, // UADDLPv2i32_v1i64 >+ 0U, // UADDLPv4i16_v2i32 >+ 0U, // UADDLPv4i32_v2i64 >+ 0U, // UADDLPv8i16_v4i32 >+ 0U, // UADDLPv8i8_v4i16 >+ 0U, // UADDLVv16i8v >+ 0U, // UADDLVv4i16v >+ 0U, // UADDLVv4i32v >+ 0U, // UADDLVv8i16v >+ 0U, // UADDLVv8i8v >+ 1033U, // UADDLv16i8_v8i16 >+ 1289U, // UADDLv2i32_v2i64 >+ 1545U, // UADDLv4i16_v4i32 >+ 521U, // UADDLv4i32_v2i64 >+ 777U, // UADDLv8i16_v4i32 >+ 1801U, // UADDLv8i8_v8i16 >+ 1033U, // UADDWv16i8_v8i16 >+ 1289U, // UADDWv2i32_v2i64 >+ 1545U, // UADDWv4i16_v4i32 >+ 521U, // UADDWv4i32_v2i64 >+ 777U, // UADDWv8i16_v4i32 >+ 1801U, // UADDWv8i8_v8i16 >+ 18689U, // UBFMWri >+ 18689U, // UBFMXri >+ 1U, // UCVTFSWDri >+ 1U, // UCVTFSWSri >+ 1U, // UCVTFSXDri >+ 1U, // UCVTFSXSri >+ 0U, // UCVTFUWDri >+ 0U, // UCVTFUWSri >+ 0U, // UCVTFUXDri >+ 0U, // UCVTFUXSri >+ 1U, // UCVTFd >+ 1U, // UCVTFs >+ 0U, // UCVTFv1i32 >+ 0U, // UCVTFv1i64 >+ 0U, // UCVTFv2f32 >+ 0U, // UCVTFv2f64 >+ 1U, // UCVTFv2i32_shift >+ 1U, // UCVTFv2i64_shift >+ 0U, // UCVTFv4f32 >+ 1U, // UCVTFv4i32_shift >+ 1U, // UDIVWr >+ 1U, // UDIVXr >+ 1U, // UDIV_IntWr >+ 1U, // UDIV_IntXr >+ 1033U, // UHADDv16i8 >+ 1289U, // UHADDv2i32 >+ 1545U, // UHADDv4i16 >+ 521U, // UHADDv4i32 >+ 777U, // UHADDv8i16 >+ 1801U, // UHADDv8i8 >+ 1033U, // UHSUBv16i8 >+ 1289U, // UHSUBv2i32 >+ 1545U, // UHSUBv4i16 >+ 521U, // UHSUBv4i32 >+ 777U, // UHSUBv8i16 >+ 1801U, // UHSUBv8i8 >+ 18689U, // UMADDLrrr >+ 1033U, // UMAXPv16i8 >+ 1289U, // UMAXPv2i32 >+ 1545U, // UMAXPv4i16 >+ 521U, // UMAXPv4i32 >+ 777U, // UMAXPv8i16 >+ 1801U, // UMAXPv8i8 >+ 0U, // UMAXVv16i8v >+ 0U, // UMAXVv4i16v >+ 0U, // UMAXVv4i32v >+ 0U, // UMAXVv8i16v >+ 0U, // UMAXVv8i8v >+ 1033U, // UMAXv16i8 >+ 1289U, // UMAXv2i32 >+ 1545U, // UMAXv4i16 >+ 521U, // UMAXv4i32 >+ 777U, // UMAXv8i16 >+ 1801U, // UMAXv8i8 >+ 1033U, // UMINPv16i8 >+ 1289U, // UMINPv2i32 >+ 1545U, // UMINPv4i16 >+ 521U, // UMINPv4i32 >+ 777U, // UMINPv8i16 >+ 1801U, // UMINPv8i8 >+ 0U, // UMINVv16i8v >+ 0U, // UMINVv4i16v >+ 0U, // UMINVv4i32v >+ 0U, // UMINVv8i16v >+ 0U, // UMINVv8i8v >+ 1033U, // UMINv16i8 >+ 1289U, // UMINv2i32 >+ 1545U, // UMINv4i16 >+ 521U, // UMINv4i32 >+ 777U, // UMINv8i16 >+ 1801U, // UMINv8i8 >+ 1041U, // UMLALv16i8_v8i16 >+ 27665U, // UMLALv2i32_indexed >+ 1297U, // UMLALv2i32_v2i64 >+ 28945U, // UMLALv4i16_indexed >+ 1553U, // UMLALv4i16_v4i32 >+ 27665U, // UMLALv4i32_indexed >+ 529U, // UMLALv4i32_v2i64 >+ 28945U, // UMLALv8i16_indexed >+ 785U, // UMLALv8i16_v4i32 >+ 1809U, // UMLALv8i8_v8i16 >+ 1041U, // UMLSLv16i8_v8i16 >+ 27665U, // UMLSLv2i32_indexed >+ 1297U, // UMLSLv2i32_v2i64 >+ 28945U, // UMLSLv4i16_indexed >+ 1553U, // UMLSLv4i16_v4i32 >+ 27665U, // UMLSLv4i32_indexed >+ 529U, // UMLSLv4i32_v2i64 >+ 28945U, // UMLSLv8i16_indexed >+ 785U, // UMLSLv8i16_v4i32 >+ 1809U, // UMLSLv8i8_v8i16 >+ 75U, // UMOVvi16 >+ 75U, // UMOVvi32 >+ 75U, // UMOVvi64 >+ 75U, // UMOVvi8 >+ 18689U, // UMSUBLrrr >+ 1U, // UMULHrr >+ 1033U, // UMULLv16i8_v8i16 >+ 35849U, // UMULLv2i32_indexed >+ 1289U, // UMULLv2i32_v2i64 >+ 37129U, // UMULLv4i16_indexed >+ 1545U, // UMULLv4i16_v4i32 >+ 35849U, // UMULLv4i32_indexed >+ 521U, // UMULLv4i32_v2i64 >+ 37129U, // UMULLv8i16_indexed >+ 777U, // UMULLv8i16_v4i32 >+ 1801U, // UMULLv8i8_v8i16 >+ 1033U, // UQADDv16i8 >+ 1U, // UQADDv1i16 >+ 1U, // UQADDv1i32 >+ 1U, // UQADDv1i64 >+ 1U, // UQADDv1i8 >+ 1289U, // UQADDv2i32 >+ 265U, // UQADDv2i64 >+ 1545U, // UQADDv4i16 >+ 521U, // UQADDv4i32 >+ 777U, // UQADDv8i16 >+ 1801U, // UQADDv8i8 >+ 1033U, // UQRSHLv16i8 >+ 1U, // UQRSHLv1i16 >+ 1U, // UQRSHLv1i32 >+ 1U, // UQRSHLv1i64 >+ 1U, // UQRSHLv1i8 >+ 1289U, // UQRSHLv2i32 >+ 265U, // UQRSHLv2i64 >+ 1545U, // UQRSHLv4i16 >+ 521U, // UQRSHLv4i32 >+ 777U, // UQRSHLv8i16 >+ 1801U, // UQRSHLv8i8 >+ 1U, // UQRSHRNb >+ 1U, // UQRSHRNh >+ 1U, // UQRSHRNs >+ 65U, // UQRSHRNv16i8_shift >+ 1U, // UQRSHRNv2i32_shift >+ 1U, // UQRSHRNv4i16_shift >+ 65U, // UQRSHRNv4i32_shift >+ 65U, // UQRSHRNv8i16_shift >+ 1U, // UQRSHRNv8i8_shift >+ 1U, // UQSHLb >+ 1U, // UQSHLd >+ 1U, // UQSHLh >+ 1U, // UQSHLs >+ 1033U, // UQSHLv16i8 >+ 1U, // UQSHLv16i8_shift >+ 1U, // UQSHLv1i16 >+ 1U, // UQSHLv1i32 >+ 1U, // UQSHLv1i64 >+ 1U, // UQSHLv1i8 >+ 1289U, // UQSHLv2i32 >+ 1U, // UQSHLv2i32_shift >+ 265U, // UQSHLv2i64 >+ 1U, // UQSHLv2i64_shift >+ 1545U, // UQSHLv4i16 >+ 1U, // UQSHLv4i16_shift >+ 521U, // UQSHLv4i32 >+ 1U, // UQSHLv4i32_shift >+ 777U, // UQSHLv8i16 >+ 1U, // UQSHLv8i16_shift >+ 1801U, // UQSHLv8i8 >+ 1U, // UQSHLv8i8_shift >+ 1U, // UQSHRNb >+ 1U, // UQSHRNh >+ 1U, // UQSHRNs >+ 65U, // UQSHRNv16i8_shift >+ 1U, // UQSHRNv2i32_shift >+ 1U, // UQSHRNv4i16_shift >+ 65U, // UQSHRNv4i32_shift >+ 65U, // UQSHRNv8i16_shift >+ 1U, // UQSHRNv8i8_shift >+ 1033U, // UQSUBv16i8 >+ 1U, // UQSUBv1i16 >+ 1U, // UQSUBv1i32 >+ 1U, // UQSUBv1i64 >+ 1U, // UQSUBv1i8 >+ 1289U, // UQSUBv2i32 >+ 265U, // UQSUBv2i64 >+ 1545U, // UQSUBv4i16 >+ 521U, // UQSUBv4i32 >+ 777U, // UQSUBv8i16 >+ 1801U, // UQSUBv8i8 >+ 0U, // UQXTNv16i8 >+ 0U, // UQXTNv1i16 >+ 0U, // UQXTNv1i32 >+ 0U, // UQXTNv1i8 >+ 0U, // UQXTNv2i32 >+ 0U, // UQXTNv4i16 >+ 0U, // UQXTNv4i32 >+ 0U, // UQXTNv8i16 >+ 0U, // UQXTNv8i8 >+ 0U, // URECPEv2i32 >+ 0U, // URECPEv4i32 >+ 1033U, // URHADDv16i8 >+ 1289U, // URHADDv2i32 >+ 1545U, // URHADDv4i16 >+ 521U, // URHADDv4i32 >+ 777U, // URHADDv8i16 >+ 1801U, // URHADDv8i8 >+ 1033U, // URSHLv16i8 >+ 1U, // URSHLv1i64 >+ 1289U, // URSHLv2i32 >+ 265U, // URSHLv2i64 >+ 1545U, // URSHLv4i16 >+ 521U, // URSHLv4i32 >+ 777U, // URSHLv8i16 >+ 1801U, // URSHLv8i8 >+ 1U, // URSHRd >+ 1U, // URSHRv16i8_shift >+ 1U, // URSHRv2i32_shift >+ 1U, // URSHRv2i64_shift >+ 1U, // URSHRv4i16_shift >+ 1U, // URSHRv4i32_shift >+ 1U, // URSHRv8i16_shift >+ 1U, // URSHRv8i8_shift >+ 0U, // URSQRTEv2i32 >+ 0U, // URSQRTEv4i32 >+ 65U, // URSRAd >+ 65U, // URSRAv16i8_shift >+ 65U, // URSRAv2i32_shift >+ 65U, // URSRAv2i64_shift >+ 65U, // URSRAv4i16_shift >+ 65U, // URSRAv4i32_shift >+ 65U, // URSRAv8i16_shift >+ 65U, // URSRAv8i8_shift >+ 1U, // USHLLv16i8_shift >+ 1U, // USHLLv2i32_shift >+ 1U, // USHLLv4i16_shift >+ 1U, // USHLLv4i32_shift >+ 1U, // USHLLv8i16_shift >+ 1U, // USHLLv8i8_shift >+ 1033U, // USHLv16i8 >+ 1U, // USHLv1i64 >+ 1289U, // USHLv2i32 >+ 265U, // USHLv2i64 >+ 1545U, // USHLv4i16 >+ 521U, // USHLv4i32 >+ 777U, // USHLv8i16 >+ 1801U, // USHLv8i8 >+ 1U, // USHRd >+ 1U, // USHRv16i8_shift >+ 1U, // USHRv2i32_shift >+ 1U, // USHRv2i64_shift >+ 1U, // USHRv4i16_shift >+ 1U, // USHRv4i32_shift >+ 1U, // USHRv8i16_shift >+ 1U, // USHRv8i8_shift >+ 0U, // USQADDv16i8 >+ 0U, // USQADDv1i16 >+ 0U, // USQADDv1i32 >+ 0U, // USQADDv1i64 >+ 0U, // USQADDv1i8 >+ 0U, // USQADDv2i32 >+ 0U, // USQADDv2i64 >+ 0U, // USQADDv4i16 >+ 0U, // USQADDv4i32 >+ 0U, // USQADDv8i16 >+ 0U, // USQADDv8i8 >+ 65U, // USRAd >+ 65U, // USRAv16i8_shift >+ 65U, // USRAv2i32_shift >+ 65U, // USRAv2i64_shift >+ 65U, // USRAv4i16_shift >+ 65U, // USRAv4i32_shift >+ 65U, // USRAv8i16_shift >+ 65U, // USRAv8i8_shift >+ 1033U, // USUBLv16i8_v8i16 >+ 1289U, // USUBLv2i32_v2i64 >+ 1545U, // USUBLv4i16_v4i32 >+ 521U, // USUBLv4i32_v2i64 >+ 777U, // USUBLv8i16_v4i32 >+ 1801U, // USUBLv8i8_v8i16 >+ 1033U, // USUBWv16i8_v8i16 >+ 1289U, // USUBWv2i32_v2i64 >+ 1545U, // USUBWv4i16_v4i32 >+ 521U, // USUBWv4i32_v2i64 >+ 777U, // USUBWv8i16_v4i32 >+ 1801U, // USUBWv8i8_v8i16 >+ 1033U, // UZP1v16i8 >+ 1289U, // UZP1v2i32 >+ 265U, // UZP1v2i64 >+ 1545U, // UZP1v4i16 >+ 521U, // UZP1v4i32 >+ 777U, // UZP1v8i16 >+ 1801U, // UZP1v8i8 >+ 1033U, // UZP2v16i8 >+ 1289U, // UZP2v2i32 >+ 265U, // UZP2v2i64 >+ 1545U, // UZP2v4i16 >+ 521U, // UZP2v4i32 >+ 777U, // UZP2v8i16 >+ 1801U, // UZP2v8i8 >+ 0U, // XTNv16i8 >+ 0U, // XTNv2i32 >+ 0U, // XTNv4i16 >+ 0U, // XTNv4i32 >+ 0U, // XTNv8i16 >+ 0U, // XTNv8i8 >+ 1033U, // ZIP1v16i8 >+ 1289U, // ZIP1v2i32 >+ 265U, // ZIP1v2i64 >+ 1545U, // ZIP1v4i16 >+ 521U, // ZIP1v4i32 >+ 777U, // ZIP1v8i16 >+ 1801U, // ZIP1v8i8 >+ 1033U, // ZIP2v16i8 >+ 1289U, // ZIP2v2i32 >+ 265U, // ZIP2v2i64 >+ 1545U, // ZIP2v4i16 >+ 521U, // ZIP2v4i32 >+ 777U, // ZIP2v8i16 >+ 1801U, // ZIP2v8i8 >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, >+ /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, >+ /* 20 */ 'l', 'd', '1', 9, 0, >+ /* 25 */ 't', 'r', 'n', '1', 9, 0, >+ /* 31 */ 'z', 'i', 'p', '1', 9, 0, >+ /* 37 */ 'u', 'z', 'p', '1', 9, 0, >+ /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0, >+ /* 50 */ 's', 't', '1', 9, 0, >+ /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, >+ /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, >+ /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0, >+ /* 82 */ 'l', 'd', '2', 9, 0, >+ /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, >+ /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, >+ /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, >+ /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, >+ /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, >+ /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, >+ /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, >+ /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, >+ /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, >+ /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, >+ /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, >+ /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, >+ /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, >+ /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, >+ /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, >+ /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, >+ /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, >+ /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, >+ /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, >+ /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, >+ /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, >+ /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, >+ /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, >+ /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, >+ /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, >+ /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, >+ /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, >+ /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, >+ /* 327 */ 't', 'r', 'n', '2', 9, 0, >+ /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, >+ /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, >+ /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, >+ /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, >+ /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, >+ /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, >+ /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, >+ /* 396 */ 'z', 'i', 'p', '2', 9, 0, >+ /* 402 */ 'u', 'z', 'p', '2', 9, 0, >+ /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0, >+ /* 415 */ 's', 't', '2', 9, 0, >+ /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, >+ /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, >+ /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, >+ /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, >+ /* 452 */ 'l', 'd', '3', 9, 0, >+ /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0, >+ /* 464 */ 's', 't', '3', 9, 0, >+ /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0, >+ /* 476 */ 'l', 'd', '4', 9, 0, >+ /* 481 */ 's', 't', '4', 9, 0, >+ /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0, >+ /* 493 */ 's', 'a', 'b', 'a', 9, 0, >+ /* 499 */ 'u', 'a', 'b', 'a', 9, 0, >+ /* 505 */ 'f', 'm', 'l', 'a', 9, 0, >+ /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0, >+ /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0, >+ /* 525 */ 's', 's', 'r', 'a', 9, 0, >+ /* 531 */ 'u', 's', 'r', 'a', 9, 0, >+ /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, >+ /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, >+ /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, >+ /* 562 */ 'd', 'm', 'b', 9, 0, >+ /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0, >+ /* 574 */ 'l', 'd', 'r', 'b', 9, 0, >+ /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0, >+ /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0, >+ /* 594 */ 's', 't', 'r', 'b', 9, 0, >+ /* 600 */ 's', 't', 't', 'r', 'b', 9, 0, >+ /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0, >+ /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0, >+ /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, >+ /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0, >+ /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, >+ /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0, >+ /* 651 */ 'd', 's', 'b', 9, 0, >+ /* 656 */ 'i', 's', 'b', 9, 0, >+ /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0, >+ /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, >+ /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, >+ /* 684 */ 'f', 's', 'u', 'b', 9, 0, >+ /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0, >+ /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0, >+ /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0, >+ /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, >+ /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0, >+ /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0, >+ /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0, >+ /* 740 */ 's', 'b', 'c', 9, 0, >+ /* 745 */ 'a', 'd', 'c', 9, 0, >+ /* 750 */ 'b', 'i', 'c', 9, 0, >+ /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, >+ /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0, >+ /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0, >+ /* 777 */ 'h', 'v', 'c', 9, 0, >+ /* 782 */ 's', 'v', 'c', 9, 0, >+ /* 787 */ 'f', 'a', 'b', 'd', 9, 0, >+ /* 793 */ 's', 'a', 'b', 'd', 9, 0, >+ /* 799 */ 'u', 'a', 'b', 'd', 9, 0, >+ /* 805 */ 'f', 'a', 'd', 'd', 9, 0, >+ /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, >+ /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, >+ /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0, >+ /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0, >+ /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0, >+ /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, >+ /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, >+ /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, >+ /* 872 */ 'a', 'n', 'd', 9, 0, >+ /* 877 */ 'a', 'e', 's', 'd', 9, 0, >+ /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0, >+ /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0, >+ /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0, >+ /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, >+ /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, >+ /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, >+ /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0, >+ /* 935 */ 'a', 'e', 's', 'e', 9, 0, >+ /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, >+ /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, >+ /* 959 */ 'b', 'i', 'f', 9, 0, >+ /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0, >+ /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0, >+ /* 978 */ 'f', 'n', 'e', 'g', 9, 0, >+ /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0, >+ /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0, >+ /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0, >+ /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, >+ /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, >+ /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, >+ /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, >+ /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, >+ /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0, >+ /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0, >+ /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0, >+ /* 1071 */ 'l', 'd', 'r', 'h', 9, 0, >+ /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0, >+ /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0, >+ /* 1091 */ 's', 't', 'r', 'h', 9, 0, >+ /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0, >+ /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0, >+ /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0, >+ /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, >+ /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0, >+ /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, >+ /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0, >+ /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0, >+ /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, >+ /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, >+ /* 1171 */ 'c', 'm', 'h', 'i', 9, 0, >+ /* 1177 */ 's', 'l', 'i', 9, 0, >+ /* 1182 */ 'm', 'v', 'n', 'i', 9, 0, >+ /* 1188 */ 's', 'r', 'i', 9, 0, >+ /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, >+ /* 1201 */ 'm', 'o', 'v', 'i', 9, 0, >+ /* 1207 */ 'b', 'r', 'k', 9, 0, >+ /* 1212 */ 'm', 'o', 'v', 'k', 9, 0, >+ /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0, >+ /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0, >+ /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, >+ /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0, >+ /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0, >+ /* 1255 */ 't', 'b', 'l', 9, 0, >+ /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, >+ /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, >+ /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0, >+ /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0, >+ /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0, >+ /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0, >+ /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, >+ /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, >+ /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0, >+ /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0, >+ /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0, >+ /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0, >+ /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0, >+ /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, >+ /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, >+ /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0, >+ /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0, >+ /* 1385 */ 's', 's', 'h', 'l', 9, 0, >+ /* 1391 */ 'u', 's', 'h', 'l', 9, 0, >+ /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0, >+ /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0, >+ /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, >+ /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0, >+ /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0, >+ /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0, >+ /* 1441 */ 'b', 's', 'l', 9, 0, >+ /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, >+ /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0, >+ /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0, >+ /* 1469 */ 's', 'y', 's', 'l', 9, 0, >+ /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0, >+ /* 1482 */ 'f', 'm', 'u', 'l', 9, 0, >+ /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0, >+ /* 1495 */ 'p', 'm', 'u', 'l', 9, 0, >+ /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0, >+ /* 1508 */ 's', 'b', 'f', 'm', 9, 0, >+ /* 1514 */ 'u', 'b', 'f', 'm', 9, 0, >+ /* 1520 */ 'p', 'r', 'f', 'm', 9, 0, >+ /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, >+ /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, >+ /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, >+ /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0, >+ /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, >+ /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, >+ /* 1573 */ 'f', 'm', 'i', 'n', 9, 0, >+ /* 1579 */ 's', 'm', 'i', 'n', 9, 0, >+ /* 1585 */ 'u', 'm', 'i', 'n', 9, 0, >+ /* 1591 */ 'c', 'c', 'm', 'n', 9, 0, >+ /* 1597 */ 'e', 'o', 'n', 9, 0, >+ /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, >+ /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, >+ /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, >+ /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, >+ /* 1636 */ 'o', 'r', 'n', 9, 0, >+ /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, >+ /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0, >+ /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0, >+ /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0, >+ /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, >+ /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, >+ /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, >+ /* 1697 */ 'm', 'o', 'v', 'n', 9, 0, >+ /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, >+ /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0, >+ /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0, >+ /* 1725 */ 'l', 'd', 'p', 9, 0, >+ /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, >+ /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, >+ /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, >+ /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, >+ /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0, >+ /* 1769 */ 'f', 'c', 'm', 'p', 9, 0, >+ /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, >+ /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, >+ /* 1793 */ 'l', 'd', 'n', 'p', 9, 0, >+ /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0, >+ /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0, >+ /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0, >+ /* 1820 */ 's', 't', 'n', 'p', 9, 0, >+ /* 1826 */ 'a', 'd', 'r', 'p', 9, 0, >+ /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, >+ /* 1840 */ 's', 't', 'p', 9, 0, >+ /* 1845 */ 'd', 'u', 'p', 9, 0, >+ /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0, >+ /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0, >+ /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0, >+ /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0, >+ /* 1878 */ 'l', 'd', 'x', 'p', 9, 0, >+ /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0, >+ /* 1891 */ 's', 't', 'x', 'p', 9, 0, >+ /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0, >+ /* 1904 */ 'l', 'd', '1', 'r', 9, 0, >+ /* 1910 */ 'l', 'd', '2', 'r', 9, 0, >+ /* 1916 */ 'l', 'd', '3', 'r', 9, 0, >+ /* 1922 */ 'l', 'd', '4', 'r', 9, 0, >+ /* 1928 */ 'l', 'd', 'a', 'r', 9, 0, >+ /* 1934 */ 'b', 'r', 9, 0, >+ /* 1938 */ 'a', 'd', 'r', 9, 0, >+ /* 1943 */ 'l', 'd', 'r', 9, 0, >+ /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0, >+ /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0, >+ /* 1962 */ 's', 's', 'h', 'r', 9, 0, >+ /* 1968 */ 'u', 's', 'h', 'r', 9, 0, >+ /* 1974 */ 'b', 'l', 'r', 9, 0, >+ /* 1979 */ 's', 't', 'l', 'r', 9, 0, >+ /* 1985 */ 'e', 'o', 'r', 9, 0, >+ /* 1990 */ 'r', 'o', 'r', 9, 0, >+ /* 1995 */ 'o', 'r', 'r', 9, 0, >+ /* 2000 */ 'a', 's', 'r', 9, 0, >+ /* 2005 */ 'l', 's', 'r', 9, 0, >+ /* 2010 */ 'm', 's', 'r', 9, 0, >+ /* 2015 */ 'l', 'd', 't', 'r', 9, 0, >+ /* 2021 */ 's', 't', 'r', 9, 0, >+ /* 2026 */ 's', 't', 't', 'r', 9, 0, >+ /* 2032 */ 'e', 'x', 't', 'r', 9, 0, >+ /* 2038 */ 'l', 'd', 'u', 'r', 9, 0, >+ /* 2044 */ 's', 't', 'u', 'r', 9, 0, >+ /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0, >+ /* 2057 */ 'l', 'd', 'x', 'r', 9, 0, >+ /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0, >+ /* 2070 */ 's', 't', 'x', 'r', 9, 0, >+ /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, >+ /* 2084 */ 'f', 'a', 'b', 's', 9, 0, >+ /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0, >+ /* 2097 */ 's', 'u', 'b', 's', 9, 0, >+ /* 2103 */ 's', 'b', 'c', 's', 9, 0, >+ /* 2109 */ 'a', 'd', 'c', 's', 9, 0, >+ /* 2115 */ 'b', 'i', 'c', 's', 9, 0, >+ /* 2121 */ 'a', 'd', 'd', 's', 9, 0, >+ /* 2127 */ 'a', 'n', 'd', 's', 9, 0, >+ /* 2133 */ 'c', 'm', 'h', 's', 9, 0, >+ /* 2139 */ 'c', 'l', 's', 9, 0, >+ /* 2144 */ 'f', 'm', 'l', 's', 9, 0, >+ /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, >+ /* 2158 */ 'i', 'n', 's', 9, 0, >+ /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, >+ /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, >+ /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, >+ /* 2187 */ 'm', 'r', 's', 9, 0, >+ /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, >+ /* 2201 */ 's', 'y', 's', 9, 0, >+ /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, >+ /* 2214 */ 'r', 'e', 't', 9, 0, >+ /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0, >+ /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0, >+ /* 2233 */ 'r', 'b', 'i', 't', 9, 0, >+ /* 2239 */ 'h', 'l', 't', 9, 0, >+ /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0, >+ /* 2251 */ 'c', 'n', 't', 9, 0, >+ /* 2256 */ 'n', 'o', 't', 9, 0, >+ /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0, >+ /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0, >+ /* 2275 */ 'f', 'c', 'v', 't', 9, 0, >+ /* 2281 */ 'e', 'x', 't', 9, 0, >+ /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, >+ /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, >+ /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, >+ /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, >+ /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, >+ /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, >+ /* 2334 */ 'a', 'd', 'd', 'v', 9, 0, >+ /* 2340 */ 'r', 'e', 'v', 9, 0, >+ /* 2345 */ 'f', 'd', 'i', 'v', 9, 0, >+ /* 2351 */ 's', 'd', 'i', 'v', 9, 0, >+ /* 2357 */ 'u', 'd', 'i', 'v', 9, 0, >+ /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, >+ /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, >+ /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, >+ /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, >+ /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0, >+ /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0, >+ /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0, >+ /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0, >+ /* 2425 */ 'f', 'm', 'o', 'v', 9, 0, >+ /* 2431 */ 's', 'm', 'o', 'v', 9, 0, >+ /* 2437 */ 'u', 'm', 'o', 'v', 9, 0, >+ /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0, >+ /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0, >+ /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0, >+ /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, >+ /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0, >+ /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0, >+ /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, >+ /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0, >+ /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0, >+ /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0, >+ /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0, >+ /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, >+ /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, >+ /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, >+ /* 2547 */ 'f', 'm', 'a', 'x', 9, 0, >+ /* 2553 */ 's', 'm', 'a', 'x', 9, 0, >+ /* 2559 */ 'u', 'm', 'a', 'x', 9, 0, >+ /* 2565 */ 't', 'b', 'x', 9, 0, >+ /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, >+ /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0, >+ /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0, >+ /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, >+ /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, >+ /* 2609 */ 'c', 'b', 'z', 9, 0, >+ /* 2614 */ 't', 'b', 'z', 9, 0, >+ /* 2619 */ 'c', 'l', 'z', 9, 0, >+ /* 2624 */ 'c', 'b', 'n', 'z', 9, 0, >+ /* 2630 */ 't', 'b', 'n', 'z', 9, 0, >+ /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, >+ /* 2644 */ 'm', 'o', 'v', 'z', 9, 0, >+ /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, >+ /* 2664 */ 'h', 'i', 'n', 't', 32, 0, >+ /* 2670 */ 'b', '.', 0, >+ /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 2718 */ 'd', 'r', 'p', 's', 0, >+ /* 2723 */ 'e', 'r', 'e', 't', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; >+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 4095)-1); >+#endif >+ >+ >+ // Fragment 0 encoded into 6 bits for 40 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63); >+ switch ((Bits >> 12) & 63) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET >+ return; >+ break; >+ case 1: >+ // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... >+ printVRegOperand(MI, 0, O); >+ break; >+ case 2: >+ // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... >+ printOperand(MI, 0, O); >+ break; >+ case 3: >+ // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... >+ printVRegOperand(MI, 1, O); >+ break; >+ case 4: >+ // B, BL >+ printAlignedLabel(MI, 0, O); >+ return; >+ break; >+ case 5: >+ // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC >+ printHexImm(MI, 0, O); >+ return; >+ break; >+ case 6: >+ // Bcc >+ printCondCode(MI, 0, O); >+ SStream_concat0(O, "\t"); >+ printAlignedLabel(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // DMB, DSB, ISB >+ printBarrierOption(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind... >+ printOperand(MI, 1, O); >+ break; >+ case 9: >+ // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... >+ printTypedVectorList(MI, 0, O, 16, 'b', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 10: >+ // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... >+ printTypedVectorList(MI, 1, O, 16, 'b', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 11: >+ // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... >+ printTypedVectorList(MI, 0, O, 1, 'd', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 12: >+ // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 1, 'd', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 13: >+ // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... >+ printTypedVectorList(MI, 0, O, 2, 'd', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 14: >+ // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 2, 'd', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 15: >+ // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... >+ printTypedVectorList(MI, 0, O, 2, 's', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 16: >+ // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 2, 's', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 17: >+ // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... >+ printTypedVectorList(MI, 0, O, 4, 'h', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 18: >+ // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 4, 'h', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 19: >+ // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... >+ printTypedVectorList(MI, 0, O, 4, 's', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 20: >+ // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 4, 's', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 21: >+ // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... >+ printTypedVectorList(MI, 0, O, 8, 'b', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 22: >+ // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 8, 'b', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 23: >+ // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... >+ printTypedVectorList(MI, 0, O, 8, 'h', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 24: >+ // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... >+ printTypedVectorList(MI, 1, O, 8, 'h', MRI); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 25: >+ // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... >+ printTypedVectorList(MI, 1, O, 0, 'h', MRI); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 3, O); >+ break; >+ case 26: >+ // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST >+ printTypedVectorList(MI, 2, O, 0, 'h', MRI); >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 27: >+ // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... >+ printTypedVectorList(MI, 1, O, 0, 's', MRI); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 3, O); >+ break; >+ case 28: >+ // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST >+ printTypedVectorList(MI, 2, O, 0, 's', MRI); >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 29: >+ // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... >+ printTypedVectorList(MI, 1, O, 0, 'd', MRI); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 3, O); >+ break; >+ case 30: >+ // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST >+ printTypedVectorList(MI, 2, O, 0, 'd', MRI); >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 31: >+ // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... >+ printTypedVectorList(MI, 1, O, 0, 'b', MRI); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 3, O); >+ break; >+ case 32: >+ // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST >+ printTypedVectorList(MI, 2, O, 0, 'b', MRI); >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 33: >+ // MSR >+ printMSRSystemRegister(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 34: >+ // MSRpstate >+ printSystemPStateField(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 35: >+ // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi >+ printPrefetchOp(MI, 0, O); >+ break; >+ case 36: >+ // ST1i16, ST2i16, ST3i16, ST4i16 >+ printTypedVectorList(MI, 0, O, 0, 'h', MRI); >+ printVectorIndex(MI, 1, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 37: >+ // ST1i32, ST2i32, ST3i32, ST4i32 >+ printTypedVectorList(MI, 0, O, 0, 's', MRI); >+ printVectorIndex(MI, 1, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 38: >+ // ST1i64, ST2i64, ST3i64, ST4i64 >+ printTypedVectorList(MI, 0, O, 0, 'd', MRI); >+ printVectorIndex(MI, 1, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 39: >+ // ST1i8, ST2i8, ST3i8, ST4i8 >+ printTypedVectorList(MI, 0, O, 0, 'b', MRI); >+ printVectorIndex(MI, 1, O); >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 6 bits for 41 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63); >+ switch ((Bits >> 18) & 63) { >+ default: // unreachable. >+ case 0: >+ // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... >+ SStream_concat0(O, ".16b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ break; >+ case 1: >+ // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... >+ SStream_concat0(O, ".2s, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ break; >+ case 3: >+ // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... >+ SStream_concat0(O, ".2d, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ break; >+ case 4: >+ // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... >+ SStream_concat0(O, ".4h, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ break; >+ case 5: >+ // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... >+ SStream_concat0(O, ".4s, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ break; >+ case 6: >+ // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... >+ SStream_concat0(O, ".8h, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ break; >+ case 7: >+ // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... >+ SStream_concat0(O, ".8b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ break; >+ case 8: >+ // BLR, BR, CLREX, RET, TLSDESCCALL >+ return; >+ break; >+ case 9: >+ // FCMPDri, FCMPEDri, FCMPESri, FCMPSri >+ SStream_concat0(O, ", #0.0"); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 10: >+ // FMOVXDHighr, INSvi64gpr, INSvi64lane >+ SStream_concat0(O, ".d"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 11: >+ // INSvi16gpr, INSvi16lane >+ SStream_concat0(O, ".h"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 12: >+ // INSvi32gpr, INSvi32lane >+ SStream_concat0(O, ".s"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 13: >+ // INSvi8gpr, INSvi8lane >+ SStream_concat0(O, ".b"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); >+ printVectorIndex(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 14: >+ // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... >+ printPostIncOperand2(MI, 3, O, 64); >+ return; >+ break; >+ case 15: >+ // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... >+ printPostIncOperand2(MI, 3, O, 32); >+ return; >+ break; >+ case 16: >+ // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... >+ printPostIncOperand2(MI, 3, O, 16); >+ return; >+ break; >+ case 17: >+ // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... >+ printPostIncOperand2(MI, 3, O, 8); >+ return; >+ break; >+ case 18: >+ // LD1Rv16b_POST, LD1Rv8b_POST >+ printPostIncOperand2(MI, 3, O, 1); >+ return; >+ break; >+ case 19: >+ // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... >+ printPostIncOperand2(MI, 3, O, 4); >+ return; >+ break; >+ case 20: >+ // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST >+ printPostIncOperand2(MI, 3, O, 2); >+ return; >+ break; >+ case 21: >+ // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... >+ printPostIncOperand2(MI, 3, O, 48); >+ return; >+ break; >+ case 22: >+ // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... >+ printPostIncOperand2(MI, 3, O, 24); >+ return; >+ break; >+ case 23: >+ // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 24: >+ // LD1i16_POST, LD2i8_POST >+ printPostIncOperand2(MI, 5, O, 2); >+ return; >+ break; >+ case 25: >+ // LD1i32_POST, LD2i16_POST, LD4i8_POST >+ printPostIncOperand2(MI, 5, O, 4); >+ return; >+ break; >+ case 26: >+ // LD1i64_POST, LD2i32_POST, LD4i16_POST >+ printPostIncOperand2(MI, 5, O, 8); >+ return; >+ break; >+ case 27: >+ // LD1i8_POST >+ printPostIncOperand2(MI, 5, O, 1); >+ return; >+ break; >+ case 28: >+ // LD2i64_POST, LD4i32_POST >+ printPostIncOperand2(MI, 5, O, 16); >+ return; >+ break; >+ case 29: >+ // LD3Rv16b_POST, LD3Rv8b_POST >+ printPostIncOperand2(MI, 3, O, 3); >+ return; >+ break; >+ case 30: >+ // LD3Rv2s_POST, LD3Rv4s_POST >+ printPostIncOperand2(MI, 3, O, 12); >+ return; >+ break; >+ case 31: >+ // LD3Rv4h_POST, LD3Rv8h_POST >+ printPostIncOperand2(MI, 3, O, 6); >+ return; >+ break; >+ case 32: >+ // LD3i16_POST >+ printPostIncOperand2(MI, 5, O, 6); >+ return; >+ break; >+ case 33: >+ // LD3i32_POST >+ printPostIncOperand2(MI, 5, O, 12); >+ return; >+ break; >+ case 34: >+ // LD3i64_POST >+ printPostIncOperand2(MI, 5, O, 24); >+ return; >+ break; >+ case 35: >+ // LD3i8_POST >+ printPostIncOperand2(MI, 5, O, 3); >+ return; >+ break; >+ case 36: >+ // LD4i64_POST >+ printPostIncOperand2(MI, 5, O, 32); >+ return; >+ break; >+ case 37: >+ // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,... >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ break; >+ case 38: >+ // PMULLv1i64, PMULLv2i64 >+ SStream_concat0(O, ".1q, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); >+ printVRegOperand(MI, 1, O); >+ break; >+ case 39: >+ // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... >+ SStream_concat0(O, ".1d, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); >+ break; >+ case 40: >+ // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 5 bits for 28 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); >+ switch ((Bits >> 24) & 31) { >+ default: // unreachable. >+ case 0: >+ // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... >+ printVRegOperand(MI, 1, O); >+ break; >+ case 1: >+ // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD... >+ printOperand(MI, 1, O); >+ break; >+ case 2: >+ // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... >+ printVRegOperand(MI, 2, O); >+ break; >+ case 3: >+ // ADRP >+ printAdrpLabel(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe... >+ printOperand(MI, 2, O); >+ break; >+ case 5: >+ // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... >+ printHexImm(MI, 2, O); >+ printShifter(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... >+ printAlignedLabel(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns >+ printFPImmOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 9: >+ // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane >+ printVRegOperand(MI, 3, O); >+ break; >+ case 10: >+ // MOVID, MOVIv2d_ns >+ printSIMDType10Operand(MI, 1, O); >+ return; >+ break; >+ case 11: >+ // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... >+ printHexImm(MI, 1, O); >+ break; >+ case 12: >+ // MRS >+ printMRSSystemRegister(MI, 1, O); >+ return; >+ break; >+ case 13: >+ // PMULLv1i64 >+ SStream_concat0(O, ".1d, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); >+ printVRegOperand(MI, 2, O); >+ SStream_concat0(O, ".1d"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); >+ return; >+ break; >+ case 14: >+ // PMULLv2i64 >+ SStream_concat0(O, ".2d, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ printVRegOperand(MI, 2, O); >+ SStream_concat0(O, ".2d"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ return; >+ break; >+ case 15: >+ // ST1i16_POST, ST2i8_POST >+ printPostIncOperand2(MI, 4, O, 2); >+ return; >+ break; >+ case 16: >+ // ST1i32_POST, ST2i16_POST, ST4i8_POST >+ printPostIncOperand2(MI, 4, O, 4); >+ return; >+ break; >+ case 17: >+ // ST1i64_POST, ST2i32_POST, ST4i16_POST >+ printPostIncOperand2(MI, 4, O, 8); >+ return; >+ break; >+ case 18: >+ // ST1i8_POST >+ printPostIncOperand2(MI, 4, O, 1); >+ return; >+ break; >+ case 19: >+ // ST2i64_POST, ST4i32_POST >+ printPostIncOperand2(MI, 4, O, 16); >+ return; >+ break; >+ case 20: >+ // ST3i16_POST >+ printPostIncOperand2(MI, 4, O, 6); >+ return; >+ break; >+ case 21: >+ // ST3i32_POST >+ printPostIncOperand2(MI, 4, O, 12); >+ return; >+ break; >+ case 22: >+ // ST3i64_POST >+ printPostIncOperand2(MI, 4, O, 24); >+ return; >+ break; >+ case 23: >+ // ST3i8_POST >+ printPostIncOperand2(MI, 4, O, 3); >+ return; >+ break; >+ case 24: >+ // ST4i64_POST >+ printPostIncOperand2(MI, 4, O, 32); >+ return; >+ break; >+ case 25: >+ // SYSxt >+ printSysCROperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printSysCROperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 4, O); >+ return; >+ break; >+ case 26: >+ // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... >+ printTypedVectorList(MI, 1, O, 16, 'b', MRI); >+ SStream_concat0(O, ", "); >+ printVRegOperand(MI, 2, O); >+ break; >+ case 27: >+ // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... >+ printTypedVectorList(MI, 2, O, 16, 'b', MRI); >+ SStream_concat0(O, ", "); >+ printVRegOperand(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 6 bits for 42 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63); >+ switch ((Bits >> 29) & 63) { >+ default: // unreachable. >+ case 0: >+ // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... >+ SStream_concat0(O, ".16b"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ return; >+ break; >+ case 1: >+ // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D... >+ return; >+ break; >+ case 2: >+ // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... >+ SStream_concat0(O, ".2s"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ return; >+ break; >+ case 3: >+ // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... >+ SStream_concat0(O, ".2d"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ return; >+ break; >+ case 4: >+ // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v... >+ SStream_concat0(O, ".4h"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ return; >+ break; >+ case 5: >+ // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... >+ SStream_concat0(O, ".4s"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ return; >+ break; >+ case 6: >+ // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v... >+ SStream_concat0(O, ".8h"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ return; >+ break; >+ case 7: >+ // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... >+ SStream_concat0(O, ".8b"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ return; >+ break; >+ case 8: >+ // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS... >+ SStream_concat0(O, ", "); >+ break; >+ case 9: >+ // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... >+ SStream_concat0(O, ".2d, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ break; >+ case 10: >+ // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... >+ SStream_concat0(O, ".4s, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ break; >+ case 11: >+ // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... >+ SStream_concat0(O, ".8h, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ break; >+ case 12: >+ // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... >+ SStream_concat0(O, ".16b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ break; >+ case 13: >+ // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... >+ SStream_concat0(O, ".2s, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ break; >+ case 14: >+ // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... >+ SStream_concat0(O, ".4h, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ break; >+ case 15: >+ // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... >+ SStream_concat0(O, ".8b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ break; >+ case 16: >+ // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz >+ SStream_concat0(O, ".16b, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 17: >+ // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz >+ SStream_concat0(O, ", #0"); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 18: >+ // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz >+ SStream_concat0(O, ".2s, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 19: >+ // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz >+ SStream_concat0(O, ".2d, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 20: >+ // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz >+ SStream_concat0(O, ".4h, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 21: >+ // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz >+ SStream_concat0(O, ".4s, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 22: >+ // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz >+ SStream_concat0(O, ".8h, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 23: >+ // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz >+ SStream_concat0(O, ".8b, #0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ arm64_op_addImm(MI, 0); >+ return; >+ break; >+ case 24: >+ // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... >+ SStream_concat0(O, ".h"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); >+ break; >+ case 25: >+ // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... >+ SStream_concat0(O, ".s"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); >+ break; >+ case 26: >+ // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 >+ SStream_concat0(O, ".d"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); >+ break; >+ case 27: >+ // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... >+ SStream_concat0(O, ".b"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); >+ break; >+ case 28: >+ // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ... >+ SStream_concat0(O, ", #0.0"); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 29: >+ // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz >+ SStream_concat0(O, ".2s, #0.0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 30: >+ // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz >+ SStream_concat0(O, ".2d, #0.0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 31: >+ // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz >+ SStream_concat0(O, ".4s, #0.0"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ arm64_op_addFP(MI, 0.0); >+ return; >+ break; >+ case 32: >+ // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX... >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 33: >+ // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos... >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ break; >+ case 34: >+ // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 35: >+ // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... >+ printShifter(MI, 2, O); >+ return; >+ break; >+ case 36: >+ // SHLLv16i8 >+ SStream_concat0(O, ".16b, #8"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ arm64_op_addImm(MI, 8); >+ return; >+ break; >+ case 37: >+ // SHLLv2i32 >+ SStream_concat0(O, ".2s, #32"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ arm64_op_addImm(MI, 32); >+ return; >+ break; >+ case 38: >+ // SHLLv4i16 >+ SStream_concat0(O, ".4h, #16"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ arm64_op_addImm(MI, 16); >+ return; >+ break; >+ case 39: >+ // SHLLv4i32 >+ SStream_concat0(O, ".4s, #32"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ arm64_op_addImm(MI, 32); >+ return; >+ break; >+ case 40: >+ // SHLLv8i16 >+ SStream_concat0(O, ".8h, #16"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ arm64_op_addImm(MI, 16); >+ return; >+ break; >+ case 41: >+ // SHLLv8i8 >+ SStream_concat0(O, ".8b, #8"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ arm64_op_addImm(MI, 8); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 5 bits for 18 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); >+ switch ((Bits >> 35) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A... >+ printOperand(MI, 2, O); >+ break; >+ case 1: >+ // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... >+ printVRegOperand(MI, 2, O); >+ break; >+ case 2: >+ // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... >+ printVRegOperand(MI, 3, O); >+ break; >+ case 3: >+ // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri >+ printAddSubImm(MI, 2, O); >+ return; >+ break; >+ case 4: >+ // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... >+ printShiftedRegister(MI, 2, O); >+ return; >+ break; >+ case 5: >+ // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx >+ printExtendedRegister(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // ANDSWri, ANDWri, EORWri, ORRWri >+ printLogicalImm32(MI, 2, O); >+ return; >+ break; >+ case 7: >+ // ANDSXri, ANDXri, EORXri, ORRXri >+ printLogicalImm64(MI, 2, O); >+ return; >+ break; >+ case 8: >+ // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW... >+ printOperand(MI, 3, O); >+ break; >+ case 9: >+ // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... >+ printVectorIndex(MI, 2, O); >+ return; >+ break; >+ case 10: >+ // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 11: >+ // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui >+ printUImm12Offset2(MI, 2, O, 1); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 12: >+ // LDRDui, LDRXui, PRFMui, STRDui, STRXui >+ printUImm12Offset2(MI, 2, O, 8); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 13: >+ // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui >+ printUImm12Offset2(MI, 2, O, 2); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 14: >+ // LDRQui, STRQui >+ printUImm12Offset2(MI, 2, O, 16); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 15: >+ // LDRSWui, LDRSui, LDRWui, STRSui, STRWui >+ printUImm12Offset2(MI, 2, O, 4); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 16: >+ // SYSLxt >+ printSysCROperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printSysCROperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 4, O); >+ return; >+ break; >+ case 17: >+ // TBNZW, TBNZX, TBZW, TBZX >+ printAlignedLabel(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 5 bits for 19 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31); >+ switch ((Bits >> 40) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG... >+ return; >+ break; >+ case 1: >+ // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... >+ SStream_concat0(O, ".2d"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); >+ return; >+ break; >+ case 2: >+ // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... >+ SStream_concat0(O, ".4s"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); >+ return; >+ break; >+ case 3: >+ // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... >+ SStream_concat0(O, ".8h"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); >+ return; >+ break; >+ case 4: >+ // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... >+ SStream_concat0(O, ".16b"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ return; >+ break; >+ case 5: >+ // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... >+ SStream_concat0(O, ".2s"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); >+ return; >+ break; >+ case 6: >+ // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... >+ SStream_concat0(O, ".4h"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); >+ return; >+ break; >+ case 7: >+ // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... >+ SStream_concat0(O, ".8b"); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ return; >+ break; >+ case 8: >+ // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 >+ printArithExtend(MI, 3, O); >+ return; >+ break; >+ case 9: >+ // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi... >+ SStream_concat0(O, ", "); >+ break; >+ case 10: >+ // EXTv16i8 >+ SStream_concat0(O, ".16b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 11: >+ // EXTv8i8 >+ SStream_concat0(O, ".8b, "); >+ arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 12: >+ // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind... >+ SStream_concat0(O, ".s"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); >+ break; >+ case 13: >+ // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... >+ SStream_concat0(O, ".d"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); >+ break; >+ case 14: >+ // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi... >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 15: >+ // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 16: >+ // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... >+ SStream_concat0(O, "]!"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 17: >+ // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed... >+ SStream_concat0(O, ".h"); >+ arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); >+ break; >+ case 18: >+ // STLXPW, STLXPX, STXPW, STXPX >+ SStream_concat0(O, ", ["); >+ set_mem_access(MI, true); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 5 bits for 21 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31); >+ switch ((Bits >> 45) & 31) { >+ default: // unreachable. >+ case 0: >+ // BFMWri, BFMXri >+ printOperand(MI, 4, O); >+ return; >+ break; >+ case 1: >+ // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... >+ printCondCode(MI, 3, O); >+ return; >+ break; >+ case 2: >+ // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD... >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 3: >+ // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind... >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 4: >+ // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64... >+ printVectorIndex(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi >+ printImmScale(MI, 3, O, 8); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 6: >+ // LDNPQi, LDPQi, STNPQi, STPQi >+ printImmScale(MI, 3, O, 16); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 7: >+ // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi >+ printImmScale(MI, 3, O, 4); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 8: >+ // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... >+ printImmScale(MI, 4, O, 8); >+ break; >+ case 9: >+ // LDPQpost, LDPQpre, STPQpost, STPQpre >+ printImmScale(MI, 4, O, 16); >+ break; >+ case 10: >+ // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... >+ printImmScale(MI, 4, O, 4); >+ break; >+ case 11: >+ // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW >+ printMemExtend(MI, 3, O, 'w', 8); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 12: >+ // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX >+ printMemExtend(MI, 3, O, 'x', 8); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 13: >+ // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW >+ printMemExtend(MI, 3, O, 'w', 64); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 14: >+ // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX >+ printMemExtend(MI, 3, O, 'x', 64); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 15: >+ // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW >+ printMemExtend(MI, 3, O, 'w', 16); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 16: >+ // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX >+ printMemExtend(MI, 3, O, 'x', 16); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 17: >+ // LDRQroW, STRQroW >+ printMemExtend(MI, 3, O, 'w', 128); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 18: >+ // LDRQroX, STRQroX >+ printMemExtend(MI, 3, O, 'x', 128); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 19: >+ // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW >+ printMemExtend(MI, 3, O, 'w', 32); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ case 20: >+ // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX >+ printMemExtend(MI, 3, O, 'x', 32); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 7 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1); >+ if ((Bits >> 50) & 1) { >+ // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... >+ SStream_concat0(O, "]!"); >+ set_mem_access(MI, false); >+ return; >+ } else { >+ // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo, int AltIdx) >+{ >+ // assert(RegNo && RegNo < 420 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrsNoRegAltName[] = { >+ /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, >+ /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, >+ /* 26 */ 'b', '1', '0', 0, >+ /* 30 */ 'd', '1', '0', 0, >+ /* 34 */ 'h', '1', '0', 0, >+ /* 38 */ 'q', '1', '0', 0, >+ /* 42 */ 's', '1', '0', 0, >+ /* 46 */ 'w', '1', '0', 0, >+ /* 50 */ 'x', '1', '0', 0, >+ /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, >+ /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, >+ /* 86 */ 'b', '2', '0', 0, >+ /* 90 */ 'd', '2', '0', 0, >+ /* 94 */ 'h', '2', '0', 0, >+ /* 98 */ 'q', '2', '0', 0, >+ /* 102 */ 's', '2', '0', 0, >+ /* 106 */ 'w', '2', '0', 0, >+ /* 110 */ 'x', '2', '0', 0, >+ /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, >+ /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, >+ /* 146 */ 'b', '3', '0', 0, >+ /* 150 */ 'd', '3', '0', 0, >+ /* 154 */ 'h', '3', '0', 0, >+ /* 158 */ 'q', '3', '0', 0, >+ /* 162 */ 's', '3', '0', 0, >+ /* 166 */ 'w', '3', '0', 0, >+ /* 170 */ 'x', '3', '0', 0, >+ /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, >+ /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, >+ /* 204 */ 'b', '0', 0, >+ /* 207 */ 'd', '0', 0, >+ /* 210 */ 'h', '0', 0, >+ /* 213 */ 'q', '0', 0, >+ /* 216 */ 's', '0', 0, >+ /* 219 */ 'w', '0', 0, >+ /* 222 */ 'x', '0', 0, >+ /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, >+ /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, >+ /* 253 */ 'b', '1', '1', 0, >+ /* 257 */ 'd', '1', '1', 0, >+ /* 261 */ 'h', '1', '1', 0, >+ /* 265 */ 'q', '1', '1', 0, >+ /* 269 */ 's', '1', '1', 0, >+ /* 273 */ 'w', '1', '1', 0, >+ /* 277 */ 'x', '1', '1', 0, >+ /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, >+ /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, >+ /* 313 */ 'b', '2', '1', 0, >+ /* 317 */ 'd', '2', '1', 0, >+ /* 321 */ 'h', '2', '1', 0, >+ /* 325 */ 'q', '2', '1', 0, >+ /* 329 */ 's', '2', '1', 0, >+ /* 333 */ 'w', '2', '1', 0, >+ /* 337 */ 'x', '2', '1', 0, >+ /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, >+ /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, >+ /* 373 */ 'b', '3', '1', 0, >+ /* 377 */ 'd', '3', '1', 0, >+ /* 381 */ 'h', '3', '1', 0, >+ /* 385 */ 'q', '3', '1', 0, >+ /* 389 */ 's', '3', '1', 0, >+ /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, >+ /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, >+ /* 421 */ 'b', '1', 0, >+ /* 424 */ 'd', '1', 0, >+ /* 427 */ 'h', '1', 0, >+ /* 430 */ 'q', '1', 0, >+ /* 433 */ 's', '1', 0, >+ /* 436 */ 'w', '1', 0, >+ /* 439 */ 'x', '1', 0, >+ /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, >+ /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, >+ /* 472 */ 'b', '1', '2', 0, >+ /* 476 */ 'd', '1', '2', 0, >+ /* 480 */ 'h', '1', '2', 0, >+ /* 484 */ 'q', '1', '2', 0, >+ /* 488 */ 's', '1', '2', 0, >+ /* 492 */ 'w', '1', '2', 0, >+ /* 496 */ 'x', '1', '2', 0, >+ /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, >+ /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, >+ /* 532 */ 'b', '2', '2', 0, >+ /* 536 */ 'd', '2', '2', 0, >+ /* 540 */ 'h', '2', '2', 0, >+ /* 544 */ 'q', '2', '2', 0, >+ /* 548 */ 's', '2', '2', 0, >+ /* 552 */ 'w', '2', '2', 0, >+ /* 556 */ 'x', '2', '2', 0, >+ /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, >+ /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, >+ /* 586 */ 'b', '2', 0, >+ /* 589 */ 'd', '2', 0, >+ /* 592 */ 'h', '2', 0, >+ /* 595 */ 'q', '2', 0, >+ /* 598 */ 's', '2', 0, >+ /* 601 */ 'w', '2', 0, >+ /* 604 */ 'x', '2', 0, >+ /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, >+ /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, >+ /* 639 */ 'b', '1', '3', 0, >+ /* 643 */ 'd', '1', '3', 0, >+ /* 647 */ 'h', '1', '3', 0, >+ /* 651 */ 'q', '1', '3', 0, >+ /* 655 */ 's', '1', '3', 0, >+ /* 659 */ 'w', '1', '3', 0, >+ /* 663 */ 'x', '1', '3', 0, >+ /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, >+ /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, >+ /* 699 */ 'b', '2', '3', 0, >+ /* 703 */ 'd', '2', '3', 0, >+ /* 707 */ 'h', '2', '3', 0, >+ /* 711 */ 'q', '2', '3', 0, >+ /* 715 */ 's', '2', '3', 0, >+ /* 719 */ 'w', '2', '3', 0, >+ /* 723 */ 'x', '2', '3', 0, >+ /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, >+ /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, >+ /* 751 */ 'b', '3', 0, >+ /* 754 */ 'd', '3', 0, >+ /* 757 */ 'h', '3', 0, >+ /* 760 */ 'q', '3', 0, >+ /* 763 */ 's', '3', 0, >+ /* 766 */ 'w', '3', 0, >+ /* 769 */ 'x', '3', 0, >+ /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, >+ /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, >+ /* 804 */ 'b', '1', '4', 0, >+ /* 808 */ 'd', '1', '4', 0, >+ /* 812 */ 'h', '1', '4', 0, >+ /* 816 */ 'q', '1', '4', 0, >+ /* 820 */ 's', '1', '4', 0, >+ /* 824 */ 'w', '1', '4', 0, >+ /* 828 */ 'x', '1', '4', 0, >+ /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, >+ /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, >+ /* 864 */ 'b', '2', '4', 0, >+ /* 868 */ 'd', '2', '4', 0, >+ /* 872 */ 'h', '2', '4', 0, >+ /* 876 */ 'q', '2', '4', 0, >+ /* 880 */ 's', '2', '4', 0, >+ /* 884 */ 'w', '2', '4', 0, >+ /* 888 */ 'x', '2', '4', 0, >+ /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, >+ /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, >+ /* 916 */ 'b', '4', 0, >+ /* 919 */ 'd', '4', 0, >+ /* 922 */ 'h', '4', 0, >+ /* 925 */ 'q', '4', 0, >+ /* 928 */ 's', '4', 0, >+ /* 931 */ 'w', '4', 0, >+ /* 934 */ 'x', '4', 0, >+ /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, >+ /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, >+ /* 969 */ 'b', '1', '5', 0, >+ /* 973 */ 'd', '1', '5', 0, >+ /* 977 */ 'h', '1', '5', 0, >+ /* 981 */ 'q', '1', '5', 0, >+ /* 985 */ 's', '1', '5', 0, >+ /* 989 */ 'w', '1', '5', 0, >+ /* 993 */ 'x', '1', '5', 0, >+ /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, >+ /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, >+ /* 1029 */ 'b', '2', '5', 0, >+ /* 1033 */ 'd', '2', '5', 0, >+ /* 1037 */ 'h', '2', '5', 0, >+ /* 1041 */ 'q', '2', '5', 0, >+ /* 1045 */ 's', '2', '5', 0, >+ /* 1049 */ 'w', '2', '5', 0, >+ /* 1053 */ 'x', '2', '5', 0, >+ /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, >+ /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, >+ /* 1081 */ 'b', '5', 0, >+ /* 1084 */ 'd', '5', 0, >+ /* 1087 */ 'h', '5', 0, >+ /* 1090 */ 'q', '5', 0, >+ /* 1093 */ 's', '5', 0, >+ /* 1096 */ 'w', '5', 0, >+ /* 1099 */ 'x', '5', 0, >+ /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, >+ /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, >+ /* 1134 */ 'b', '1', '6', 0, >+ /* 1138 */ 'd', '1', '6', 0, >+ /* 1142 */ 'h', '1', '6', 0, >+ /* 1146 */ 'q', '1', '6', 0, >+ /* 1150 */ 's', '1', '6', 0, >+ /* 1154 */ 'w', '1', '6', 0, >+ /* 1158 */ 'x', '1', '6', 0, >+ /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, >+ /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, >+ /* 1194 */ 'b', '2', '6', 0, >+ /* 1198 */ 'd', '2', '6', 0, >+ /* 1202 */ 'h', '2', '6', 0, >+ /* 1206 */ 'q', '2', '6', 0, >+ /* 1210 */ 's', '2', '6', 0, >+ /* 1214 */ 'w', '2', '6', 0, >+ /* 1218 */ 'x', '2', '6', 0, >+ /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, >+ /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, >+ /* 1246 */ 'b', '6', 0, >+ /* 1249 */ 'd', '6', 0, >+ /* 1252 */ 'h', '6', 0, >+ /* 1255 */ 'q', '6', 0, >+ /* 1258 */ 's', '6', 0, >+ /* 1261 */ 'w', '6', 0, >+ /* 1264 */ 'x', '6', 0, >+ /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, >+ /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, >+ /* 1299 */ 'b', '1', '7', 0, >+ /* 1303 */ 'd', '1', '7', 0, >+ /* 1307 */ 'h', '1', '7', 0, >+ /* 1311 */ 'q', '1', '7', 0, >+ /* 1315 */ 's', '1', '7', 0, >+ /* 1319 */ 'w', '1', '7', 0, >+ /* 1323 */ 'x', '1', '7', 0, >+ /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, >+ /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, >+ /* 1359 */ 'b', '2', '7', 0, >+ /* 1363 */ 'd', '2', '7', 0, >+ /* 1367 */ 'h', '2', '7', 0, >+ /* 1371 */ 'q', '2', '7', 0, >+ /* 1375 */ 's', '2', '7', 0, >+ /* 1379 */ 'w', '2', '7', 0, >+ /* 1383 */ 'x', '2', '7', 0, >+ /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, >+ /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, >+ /* 1411 */ 'b', '7', 0, >+ /* 1414 */ 'd', '7', 0, >+ /* 1417 */ 'h', '7', 0, >+ /* 1420 */ 'q', '7', 0, >+ /* 1423 */ 's', '7', 0, >+ /* 1426 */ 'w', '7', 0, >+ /* 1429 */ 'x', '7', 0, >+ /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, >+ /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, >+ /* 1464 */ 'b', '1', '8', 0, >+ /* 1468 */ 'd', '1', '8', 0, >+ /* 1472 */ 'h', '1', '8', 0, >+ /* 1476 */ 'q', '1', '8', 0, >+ /* 1480 */ 's', '1', '8', 0, >+ /* 1484 */ 'w', '1', '8', 0, >+ /* 1488 */ 'x', '1', '8', 0, >+ /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, >+ /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, >+ /* 1524 */ 'b', '2', '8', 0, >+ /* 1528 */ 'd', '2', '8', 0, >+ /* 1532 */ 'h', '2', '8', 0, >+ /* 1536 */ 'q', '2', '8', 0, >+ /* 1540 */ 's', '2', '8', 0, >+ /* 1544 */ 'w', '2', '8', 0, >+ /* 1548 */ 'x', '2', '8', 0, >+ /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, >+ /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, >+ /* 1576 */ 'b', '8', 0, >+ /* 1579 */ 'd', '8', 0, >+ /* 1582 */ 'h', '8', 0, >+ /* 1585 */ 'q', '8', 0, >+ /* 1588 */ 's', '8', 0, >+ /* 1591 */ 'w', '8', 0, >+ /* 1594 */ 'x', '8', 0, >+ /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, >+ /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, >+ /* 1629 */ 'b', '1', '9', 0, >+ /* 1633 */ 'd', '1', '9', 0, >+ /* 1637 */ 'h', '1', '9', 0, >+ /* 1641 */ 'q', '1', '9', 0, >+ /* 1645 */ 's', '1', '9', 0, >+ /* 1649 */ 'w', '1', '9', 0, >+ /* 1653 */ 'x', '1', '9', 0, >+ /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, >+ /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, >+ /* 1689 */ 'b', '2', '9', 0, >+ /* 1693 */ 'd', '2', '9', 0, >+ /* 1697 */ 'h', '2', '9', 0, >+ /* 1701 */ 'q', '2', '9', 0, >+ /* 1705 */ 's', '2', '9', 0, >+ /* 1709 */ 'w', '2', '9', 0, >+ /* 1713 */ 'x', '2', '9', 0, >+ /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, >+ /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, >+ /* 1741 */ 'b', '9', 0, >+ /* 1744 */ 'd', '9', 0, >+ /* 1747 */ 'h', '9', 0, >+ /* 1750 */ 'q', '9', 0, >+ /* 1753 */ 's', '9', 0, >+ /* 1756 */ 'w', '9', 0, >+ /* 1759 */ 'x', '9', 0, >+ /* 1762 */ 'w', 's', 'p', 0, >+ /* 1766 */ 'w', 'z', 'r', 0, >+ /* 1770 */ 'x', 'z', 'r', 0, >+ /* 1774 */ 'n', 'z', 'c', 'v', 0, >+ }; >+ >+ static const uint32_t RegAsmOffsetNoRegAltName[] = { >+ 1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, >+ 1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, >+ 313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, >+ 754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, >+ 1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, >+ 377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, >+ 647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, >+ 1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, >+ 1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, >+ 711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, >+ 1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, >+ 1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, >+ 436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, >+ 989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, >+ 1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, >+ 496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, >+ 1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, >+ 449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, >+ 1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, >+ 0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, >+ 832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, >+ 1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, >+ 1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, >+ 397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, >+ 796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, >+ 1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, >+ 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, >+ 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, >+ 1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, >+ 301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, >+ }; >+ >+ static const char AsmStrsvreg[] = { >+ /* 0 */ 'v', '1', '0', 0, >+ /* 4 */ 'v', '2', '0', 0, >+ /* 8 */ 'v', '3', '0', 0, >+ /* 12 */ 'v', '0', 0, >+ /* 15 */ 'v', '1', '1', 0, >+ /* 19 */ 'v', '2', '1', 0, >+ /* 23 */ 'v', '3', '1', 0, >+ /* 27 */ 'v', '1', 0, >+ /* 30 */ 'v', '1', '2', 0, >+ /* 34 */ 'v', '2', '2', 0, >+ /* 38 */ 'v', '2', 0, >+ /* 41 */ 'v', '1', '3', 0, >+ /* 45 */ 'v', '2', '3', 0, >+ /* 49 */ 'v', '3', 0, >+ /* 52 */ 'v', '1', '4', 0, >+ /* 56 */ 'v', '2', '4', 0, >+ /* 60 */ 'v', '4', 0, >+ /* 63 */ 'v', '1', '5', 0, >+ /* 67 */ 'v', '2', '5', 0, >+ /* 71 */ 'v', '5', 0, >+ /* 74 */ 'v', '1', '6', 0, >+ /* 78 */ 'v', '2', '6', 0, >+ /* 82 */ 'v', '6', 0, >+ /* 85 */ 'v', '1', '7', 0, >+ /* 89 */ 'v', '2', '7', 0, >+ /* 93 */ 'v', '7', 0, >+ /* 96 */ 'v', '1', '8', 0, >+ /* 100 */ 'v', '2', '8', 0, >+ /* 104 */ 'v', '8', 0, >+ /* 107 */ 'v', '1', '9', 0, >+ /* 111 */ 'v', '2', '9', 0, >+ /* 115 */ 'v', '9', 0, >+ }; >+ >+ static const uint32_t RegAsmOffsetvreg[] = { >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, >+ 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, >+ 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, >+ 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, >+ 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, >+ 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, >+ 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, >+ 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, >+ 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, >+ 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, >+ 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, >+ 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, >+ 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, >+ 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, >+ 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, >+ 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, >+ 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, >+ 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, >+ 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, >+ 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, >+ }; >+ >+ const uint32_t *RegAsmOffset; >+ const char *AsmStrs; >+ >+ switch(AltIdx) { >+ default: // llvm_unreachable("Invalid register alt name index!"); >+ case AArch64_NoRegAltName: >+ AsmStrs = AsmStrsNoRegAltName; >+ RegAsmOffset = RegAsmOffsetNoRegAltName; >+ break; >+ case AArch64_vreg: >+ AsmStrs = AsmStrsvreg; >+ RegAsmOffset = RegAsmOffsetvreg; >+ break; >+ } >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/4; i++) >+ // printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1); >+ //printf("*************************\n"); >+ //for (i = 0; i < sizeof(RegAsmOffsetvreg)/4; i++) >+ // printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1); >+ //printf("-------------------------\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI) >+{ >+ // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx); >+ switch (PrintMethodIdx) { >+ default: >+ // llvm_unreachable("Unknown PrintMethod kind"); >+ break; >+ case 0: >+ printAddSubImm(MI, OpIdx, OS); >+ break; >+ case 1: >+ printShifter(MI, OpIdx, OS); >+ break; >+ case 2: >+ printArithExtend(MI, OpIdx, OS); >+ break; >+ case 3: >+ printLogicalImm32(MI, OpIdx, OS); >+ break; >+ case 4: >+ printLogicalImm64(MI, OpIdx, OS); >+ break; >+ case 5: >+ printVRegOperand(MI, OpIdx, OS); >+ break; >+ case 6: >+ printHexImm(MI, OpIdx, OS); >+ break; >+ case 7: >+ printInverseCondCode(MI, OpIdx, OS); >+ break; >+ case 8: >+ printVectorIndex(MI, OpIdx, OS); >+ break; >+ case 9: >+ printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI); >+ break; >+ case 10: >+ printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI); >+ break; >+ case 11: >+ printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI); >+ break; >+ case 12: >+ printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI); >+ break; >+ case 13: >+ printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI); >+ break; >+ case 14: >+ printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI); >+ break; >+ case 15: >+ printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI); >+ break; >+ case 16: >+ printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI); >+ break; >+ case 17: >+ printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI); >+ break; >+ case 18: >+ printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI); >+ break; >+ case 19: >+ printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI); >+ break; >+ case 20: >+ printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI); >+ break; >+ case 21: >+ printPrefetchOp(MI, OpIdx, OS); >+ break; >+ case 22: >+ printSysCROperand(MI, OpIdx, OS); >+ break; >+ } >+} >+ >+static bool AArch64InstPrinterValidateMCOperand( >+ MCOperand *MCOp, unsigned PredicateIndex) >+{ >+ switch (PredicateIndex) { >+ default: >+ // llvm_unreachable("Unknown MCOperandPredicate kind"); >+ case 1: { >+ return (MCOperand_isImm(MCOp) && >+ MCOperand_getImm(MCOp) != ARM64_CC_AL && >+ MCOperand_getImm(MCOp) != ARM64_CC_NV); >+ } >+ } >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case AArch64_ADDSWri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { >+ // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) >+ AsmString = "cmn $\x02, $\xFF\x03\x01"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "cmn $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) >+ AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "adds $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSWrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "cmn $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) >+ AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "adds $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSXri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { >+ // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) >+ AsmString = "cmn $\x02, $\xFF\x03\x01"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "cmn $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) >+ AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "adds $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSXrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) >+ AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDSXrx64: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "cmn $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) >+ AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "adds $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDWri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) >+ AsmString = "mov $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) >+ AsmString = "mov $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDWrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDXri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) >+ AsmString = "mov $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) >+ AsmString = "mov $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ADDXrx64: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "add $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDSWri: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1)) { >+ // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) >+ AsmString = "tst $\x02, $\xFF\x03\x04"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDSWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "tst $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) >+ AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "ands $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDSXri: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1)) { >+ // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) >+ AsmString = "tst $\x02, $\xFF\x03\x05"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDSXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "tst $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) >+ AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "ands $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "and $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ANDXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "and $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICSWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "bics $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICSXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "bics $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "bic $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "bic $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICv2i32: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (BICv2i32 V64:$Vd, imm0_255:$imm, 0) >+ AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICv4i16: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (BICv4i16 V64:$Vd, imm0_255:$imm, 0) >+ AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICv4i32: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (BICv4i32 V128:$Vd, imm0_255:$imm, 0) >+ AsmString = "bic $\xFF\x01\x06.4s, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_BICv8i16: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (BICv8i16 V128:$Vd, imm0_255:$imm, 0) >+ AsmString = "bic $\xFF\x01\x06.8h, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_CLREX: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (CLREX 15) >+ AsmString = "clrex"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSINCWr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) >+ AsmString = "cset $\x01, $\xFF\x04\x08"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) >+ AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSINCXr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) >+ AsmString = "cset $\x01, $\xFF\x04\x08"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) >+ AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSINVWr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) >+ AsmString = "csetm $\x01, $\xFF\x04\x08"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) >+ AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSINVXr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) >+ AsmString = "csetm $\x01, $\xFF\x04\x08"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) >+ AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSNEGWr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) >+ AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_CSNEGXr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && >+ AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { >+ // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) >+ AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; >+ break; >+ } >+ return NULL; >+ case AArch64_DCPS1: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (DCPS1 0) >+ AsmString = "dcps1"; >+ break; >+ } >+ return NULL; >+ case AArch64_DCPS2: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (DCPS2 0) >+ AsmString = "dcps2"; >+ break; >+ } >+ return NULL; >+ case AArch64_DCPS3: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (DCPS3 0) >+ AsmString = "dcps3"; >+ break; >+ } >+ return NULL; >+ case AArch64_EONWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "eon $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_EONXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "eon $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_EORWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "eor $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_EORXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "eor $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_EXTRWrri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { >+ // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) >+ AsmString = "ror $\x01, $\x02, $\x04"; >+ break; >+ } >+ return NULL; >+ case AArch64_EXTRXrri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { >+ // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) >+ AsmString = "ror $\x01, $\x02, $\x04"; >+ break; >+ } >+ return NULL; >+ case AArch64_HINT: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (HINT { 0, 0, 0 }) >+ AsmString = "nop"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (HINT { 0, 0, 1 }) >+ AsmString = "yield"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (HINT { 0, 1, 0 }) >+ AsmString = "wfe"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (HINT { 0, 1, 1 }) >+ AsmString = "wfi"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (HINT { 1, 0, 0 }) >+ AsmString = "sev"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (HINT { 1, 0, 1 }) >+ AsmString = "sevl"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi16gpr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) >+ AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi16lane: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { >+ // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) >+ AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\xFF\x03\x06.h$\xFF\x04\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi32gpr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) >+ AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi32lane: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { >+ // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) >+ AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\xFF\x03\x06.s$\xFF\x04\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi64gpr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) >+ AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi64lane: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { >+ // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) >+ AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\xFF\x03\x06.d$\xFF\x04\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi8gpr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) >+ AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_INSvi8lane: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { >+ // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) >+ AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\xFF\x03\x06.b$\xFF\x04\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_ISB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (ISB 15) >+ AsmString = "isb"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x10, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Fourv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x11, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x10, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Onev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x11, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0A, [$\x01], #1"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0B, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0C, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0D, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0E, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x0F, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x10, [$\x01], #1"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Rv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) >+ AsmString = "ld1r $\xFF\x02\x11, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x10, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Threev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x11, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x10, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1Twov8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) >+ AsmString = "ld1 $\xFF\x02\x11, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "ld1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "ld1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "ld1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD1i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "ld1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0A, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0B, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0C, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0D, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0E, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x0F, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x10, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Rv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) >+ AsmString = "ld2r $\xFF\x02\x11, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x0A, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x0C, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x0D, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x0E, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x0F, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x10, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2Twov8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) >+ AsmString = "ld2 $\xFF\x02\x11, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "ld2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "ld2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "ld2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD2i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "ld2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0A, [$\x01], #3"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0B, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0C, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0D, [$\x01], #12"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0E, [$\x01], #6"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x0F, [$\x01], #12"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x10, [$\x01], #3"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Rv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) >+ AsmString = "ld3r $\xFF\x02\x11, [$\x01], #6"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x0A, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x0C, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x0D, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x0E, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x0F, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x10, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3Threev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) >+ AsmString = "ld3 $\xFF\x02\x11, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "ld3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "ld3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "ld3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD3i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "ld3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x0A, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x0C, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x0D, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x0E, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x0F, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x10, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Fourv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) >+ AsmString = "ld4 $\xFF\x02\x11, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0A, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0B, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0C, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0D, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0E, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x0F, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x10, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4Rv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) >+ AsmString = "ld4r $\xFF\x02\x11, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "ld4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "ld4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "ld4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_LD4i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "ld4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDNPDi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDNPQi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDNPSi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDNPWi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDNPXi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPDi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPQi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPSWi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPSWi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldpsw $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPSi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPWi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDPXi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (LDPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "ldp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRBBroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrb $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRBBui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRBroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRBui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRBui FPR8:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRDroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRDui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRDui FPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRHHroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrh $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRHHui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRHroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRHui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRHui FPR16:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRQroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRQui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRQui FPR128:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSBWroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrsb $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSBWui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrsb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSBXroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrsb $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSBXui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrsb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSHWroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrsh $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSHWui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrsh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSHXroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrsh $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSHXui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrsh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSWroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldrsw $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSWui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldrsw $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRSui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRSui FPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRWroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRWui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRWui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRXroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "ldr $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDRXui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDRXui GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRSBWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrsb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRSBXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrsb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRSHWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrsh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRSHXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrsh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRSWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtrsw $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDTRXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldtr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURBBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldurb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURBi FPR8:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURDi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURDi FPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURHHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldurh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURHi FPR16:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURQi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURQi FPR128:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSBWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldursb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSBXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldursb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSHWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldursh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSHXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldursh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldursw $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURSi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURSi FPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_LDURXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (LDURXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "ldur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_MADDWrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { >+ // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) >+ AsmString = "mul $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_MADDXrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) >+ AsmString = "mul $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_MOVKWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { >+ // (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16) >+ AsmString = "movk $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_MOVKXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) { >+ // (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48) >+ AsmString = "movk $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) { >+ // (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32) >+ AsmString = "movk $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { >+ // (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16) >+ AsmString = "movk $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_MSUBWrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { >+ // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) >+ AsmString = "mneg $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_MSUBXrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) >+ AsmString = "mneg $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_NOTv16i8: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { >+ // (NOTv16i8 V128:$Vd, V128:$Vn) >+ AsmString = "mvn $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; >+ break; >+ } >+ return NULL; >+ case AArch64_NOTv8i8: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { >+ // (NOTv8i8 V64:$Vd, V64:$Vn) >+ AsmString = "mvn $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORNWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) >+ AsmString = "mvn $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) >+ AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "orn $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORNXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) >+ AsmString = "mvn $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) >+ AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "orn $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) >+ AsmString = "mov $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "orr $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) >+ AsmString = "mov $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "orr $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv16i8: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { >+ // (ORRv16i8 V128:$dst, V128:$src, V128:$src) >+ AsmString = "mov $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv2i32: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (ORRv2i32 V64:$Vd, imm0_255:$imm, 0) >+ AsmString = "orr $\xFF\x01\x06.2s, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv4i16: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (ORRv4i16 V64:$Vd, imm0_255:$imm, 0) >+ AsmString = "orr $\xFF\x01\x06.4h, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv4i32: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (ORRv4i32 V128:$Vd, imm0_255:$imm, 0) >+ AsmString = "orr $\xFF\x01\x06.4s, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv8i16: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (ORRv8i16 V128:$Vd, imm0_255:$imm, 0) >+ AsmString = "orr $\xFF\x01\x06.8h, $\xFF\x02\x07"; >+ break; >+ } >+ return NULL; >+ case AArch64_ORRv8i8: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { >+ // (ORRv8i8 V64:$dst, V64:$src, V64:$src) >+ AsmString = "mov $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; >+ break; >+ } >+ return NULL; >+ case AArch64_PRFMroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "prfm $\xFF\x01\x16, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_PRFMui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "prfm $\xFF\x01\x16, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_PRFUMi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "prfum $\xFF\x01\x16, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_RET: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_LR) { >+ // (RET LR) >+ AsmString = "ret"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBCSWr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SBCSWr GPR32:$dst, WZR, GPR32:$src) >+ AsmString = "ngcs $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBCSXr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SBCSXr GPR64:$dst, XZR, GPR64:$src) >+ AsmString = "ngcs $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBCWr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SBCWr GPR32:$dst, WZR, GPR32:$src) >+ AsmString = "ngc $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBCXr: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SBCXr GPR64:$dst, XZR, GPR64:$src) >+ AsmString = "ngc $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBFMWri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { >+ // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) >+ AsmString = "asr $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { >+ // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) >+ AsmString = "sxtb $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { >+ // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) >+ AsmString = "sxth $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_SBFMXri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { >+ // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) >+ AsmString = "asr $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { >+ // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) >+ AsmString = "sxtb $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { >+ // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) >+ AsmString = "sxth $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { >+ // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) >+ AsmString = "sxtw $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_SMADDLrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) >+ AsmString = "smull $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SMSUBLrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) >+ AsmString = "smnegl $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0A, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0B, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0C, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0D, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0E, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0F, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x10, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Fourv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x11, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0A, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0B, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0C, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0D, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0E, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0F, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x10, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Onev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x11, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0A, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0B, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0C, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0D, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0E, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0F, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x10, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Threev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x11, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0A, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov1d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0B, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0C, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0D, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0E, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x0F, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x10, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1Twov8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) >+ AsmString = "st1 $\xFF\x02\x11, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "st1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "st1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "st1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST1i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "st1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x0A, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x0C, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x0D, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x0E, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x0F, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x10, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2Twov8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) >+ AsmString = "st2 $\xFF\x02\x11, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "st2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "st2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "st2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST2i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "st2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x0A, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x0C, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x0D, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x0E, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x0F, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x10, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3Threev8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) >+ AsmString = "st3 $\xFF\x02\x11, [$\x01], #48"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "st3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "st3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "st3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST3i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "st3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv16b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x0A, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv2d_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x0C, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv2s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x0D, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv4h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x0E, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv4s_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x0F, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv8b_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x10, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4Fourv8h_POST: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { >+ // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) >+ AsmString = "st4 $\xFF\x02\x11, [$\x01], #64"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4i16_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) >+ AsmString = "st4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4i32_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) >+ AsmString = "st4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4i64_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) >+ AsmString = "st4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; >+ break; >+ } >+ return NULL; >+ case AArch64_ST4i8_POST: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) >+ AsmString = "st4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; >+ break; >+ } >+ return NULL; >+ case AArch64_STNPDi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STNPQi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STNPSi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STNPWi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STNPXi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stnp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STPDi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STPQi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STPSi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STPWi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STPXi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (STPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) >+ AsmString = "stp $\x01, $\x02, [$\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRBBroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "strb $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRBBui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRBBui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "strb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRBroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRBui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRBui FPR8:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRDroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRDui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRDui FPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRHHroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "strh $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRHHui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRHHui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "strh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRHroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRHui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRHui FPR16:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRQroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRQui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRQui FPR128:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRSroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRSui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRSui FPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRWroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRWui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRWui GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRXroX: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) >+ AsmString = "str $\x01, [$\x02, $\x03]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STRXui: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STRXui GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "str $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STTRBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sttrb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STTRHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sttrh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STTRWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sttr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STTRXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sttr $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURBBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURBBi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sturb $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURBi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURBi FPR8:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURDi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURDi FPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURHHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURHHi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "sturh $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURHi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURHi FPR16:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURQi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURQi FPR128:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURSi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURSi FPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURWi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURWi GPR32:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_STURXi: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (STURXi GPR64:$Rt, GPR64sp:$Rn, 0) >+ AsmString = "stur $\x01, [$\x02]"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSWri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { >+ // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) >+ AsmString = "cmp $\x02, $\xFF\x03\x01"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "cmp $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) >+ AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) >+ AsmString = "negs $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) >+ AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "subs $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSWrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "cmp $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) >+ AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "subs $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSXri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { >+ // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) >+ AsmString = "cmp $\x02, $\xFF\x03\x01"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "cmp $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) >+ AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) >+ AsmString = "negs $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) >+ AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "subs $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSXrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) >+ AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBSXrx64: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "cmp $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) >+ AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "subs $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBWrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) >+ AsmString = "neg $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { >+ // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) >+ AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBWrx: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { >+ // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBXrs: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) >+ AsmString = "neg $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { >+ // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) >+ AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SUBXrx64: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64sponlyRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { >+ // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) >+ AsmString = "sub $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_SYSxt: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { >+ // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) >+ AsmString = "sys $\x01, $\xFF\x02\x17, $\xFF\x03\x17, $\x04"; >+ break; >+ } >+ return NULL; >+ case AArch64_UBFMWri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { >+ // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) >+ AsmString = "lsr $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { >+ // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) >+ AsmString = "uxtb $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { >+ // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) >+ AsmString = "uxth $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_UBFMXri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 63) { >+ // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) >+ AsmString = "lsr $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { >+ // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) >+ AsmString = "uxtb $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) { >+ // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) >+ AsmString = "uxth $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 31) { >+ // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) >+ AsmString = "uxtw $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case AArch64_UMADDLrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) >+ AsmString = "umull $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case AArch64_UMOVvi32: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { >+ // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) >+ AsmString = "mov $\x01, $\xFF\x02\x06.s$\xFF\x03\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_UMOVvi64: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { >+ // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) >+ AsmString = "mov $\x01, $\xFF\x02\x06.d$\xFF\x03\x09"; >+ break; >+ } >+ return NULL; >+ case AArch64_UMSUBLrrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && >+ MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { >+ // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) >+ AsmString = "umnegl $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '[') { >+ SStream_concat0(OS, "["); >+ set_mem_access(MI, true); >+ } >+ else if (*c == ']') { >+ SStream_concat0(OS, "]"); >+ set_mem_access(MI, false); >+ } >+ else if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS, MRI); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenDisassemblerTables.inc b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenDisassemblerTables.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..8612b38b0f42a3063bdc84d3c7e17870527eef01 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenDisassemblerTables.inc >@@ -0,0 +1,12750 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * AArch64 Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#include "../../MCInst.h" >+#include "../../LEB128.h" >+ >+// Helper function for extracting fields from encoded instructions. >+#define FieldFromInstruction(fname, InsnType) \ >+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ >+{ \ >+ InsnType fieldMask; \ >+ if (numBits == sizeof(InsnType)*8) \ >+ fieldMask = (InsnType)(-1LL); \ >+ else \ >+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ >+ return (insn & fieldMask) >> startBit; \ >+} >+ >+static const uint8_t DecoderTable32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ... >+/* 3 */ MCD_OPC_FilterValue, 2, 86, 4, // Skip to: 1117 >+/* 7 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 146 >+/* 14 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 98 >+/* 21 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 47 >+/* 28 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 31 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 39 >+/* 35 */ MCD_OPC_Decode, 145, 15, 0, // Opcode: STXRB >+/* 39 */ MCD_OPC_FilterValue, 1, 178, 158, // Skip to: 40669 >+/* 43 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: STLXRB >+/* 47 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 70 >+/* 51 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 54 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 62 >+/* 58 */ MCD_OPC_Decode, 169, 8, 0, // Opcode: LDXRB >+/* 62 */ MCD_OPC_FilterValue, 1, 155, 158, // Skip to: 40669 >+/* 66 */ MCD_OPC_Decode, 169, 7, 0, // Opcode: LDAXRB >+/* 70 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 84 >+/* 74 */ MCD_OPC_CheckField, 15, 1, 1, 141, 158, // Skip to: 40669 >+/* 80 */ MCD_OPC_Decode, 183, 14, 0, // Opcode: STLRB >+/* 84 */ MCD_OPC_FilterValue, 6, 133, 158, // Skip to: 40669 >+/* 88 */ MCD_OPC_CheckField, 15, 1, 1, 127, 158, // Skip to: 40669 >+/* 94 */ MCD_OPC_Decode, 163, 7, 0, // Opcode: LDARB >+/* 98 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 119 >+/* 102 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 105 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 112 >+/* 109 */ MCD_OPC_Decode, 93, 1, // Opcode: ANDWrs >+/* 112 */ MCD_OPC_FilterValue, 1, 105, 158, // Skip to: 40669 >+/* 116 */ MCD_OPC_Decode, 109, 1, // Opcode: BICWrs >+/* 119 */ MCD_OPC_FilterValue, 3, 98, 158, // Skip to: 40669 >+/* 123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 126 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 133 >+/* 130 */ MCD_OPC_Decode, 62, 1, // Opcode: ADDWrs >+/* 133 */ MCD_OPC_FilterValue, 1, 84, 158, // Skip to: 40669 >+/* 137 */ MCD_OPC_CheckField, 22, 2, 0, 78, 158, // Skip to: 40669 >+/* 143 */ MCD_OPC_Decode, 63, 2, // Opcode: ADDWrx >+/* 146 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 281 >+/* 150 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 153 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 192 >+/* 157 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 160 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 168 >+/* 164 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: STNPWi >+/* 168 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 176 >+/* 172 */ MCD_OPC_Decode, 176, 7, 3, // Opcode: LDNPWi >+/* 176 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 184 >+/* 180 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: STPWpost >+/* 184 */ MCD_OPC_FilterValue, 3, 33, 158, // Skip to: 40669 >+/* 188 */ MCD_OPC_Decode, 191, 7, 3, // Opcode: LDPWpost >+/* 192 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 231 >+/* 196 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 199 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 207 >+/* 203 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: STPWi >+/* 207 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 215 >+/* 211 */ MCD_OPC_Decode, 190, 7, 3, // Opcode: LDPWi >+/* 215 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 223 >+/* 219 */ MCD_OPC_Decode, 209, 14, 3, // Opcode: STPWpre >+/* 223 */ MCD_OPC_FilterValue, 3, 250, 157, // Skip to: 40669 >+/* 227 */ MCD_OPC_Decode, 192, 7, 3, // Opcode: LDPWpre >+/* 231 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 254 >+/* 235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 238 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 246 >+/* 242 */ MCD_OPC_Decode, 135, 9, 1, // Opcode: ORRWrs >+/* 246 */ MCD_OPC_FilterValue, 1, 227, 157, // Skip to: 40669 >+/* 250 */ MCD_OPC_Decode, 128, 9, 1, // Opcode: ORNWrs >+/* 254 */ MCD_OPC_FilterValue, 3, 219, 157, // Skip to: 40669 >+/* 258 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 261 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 268 >+/* 265 */ MCD_OPC_Decode, 48, 1, // Opcode: ADDSWrs >+/* 268 */ MCD_OPC_FilterValue, 1, 205, 157, // Skip to: 40669 >+/* 272 */ MCD_OPC_CheckField, 22, 2, 0, 199, 157, // Skip to: 40669 >+/* 278 */ MCD_OPC_Decode, 49, 2, // Opcode: ADDSWrx >+/* 281 */ MCD_OPC_FilterValue, 2, 136, 0, // Skip to: 421 >+/* 285 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 288 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 369 >+/* 292 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 295 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 318 >+/* 299 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 302 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 310 >+/* 306 */ MCD_OPC_Decode, 146, 15, 0, // Opcode: STXRH >+/* 310 */ MCD_OPC_FilterValue, 1, 163, 157, // Skip to: 40669 >+/* 314 */ MCD_OPC_Decode, 190, 14, 0, // Opcode: STLXRH >+/* 318 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 341 >+/* 322 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 325 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 333 >+/* 329 */ MCD_OPC_Decode, 170, 8, 0, // Opcode: LDXRH >+/* 333 */ MCD_OPC_FilterValue, 1, 140, 157, // Skip to: 40669 >+/* 337 */ MCD_OPC_Decode, 170, 7, 0, // Opcode: LDAXRH >+/* 341 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 355 >+/* 345 */ MCD_OPC_CheckField, 15, 1, 1, 126, 157, // Skip to: 40669 >+/* 351 */ MCD_OPC_Decode, 184, 14, 0, // Opcode: STLRH >+/* 355 */ MCD_OPC_FilterValue, 6, 118, 157, // Skip to: 40669 >+/* 359 */ MCD_OPC_CheckField, 15, 1, 1, 112, 157, // Skip to: 40669 >+/* 365 */ MCD_OPC_Decode, 164, 7, 0, // Opcode: LDARH >+/* 369 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 392 >+/* 373 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 376 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 384 >+/* 380 */ MCD_OPC_Decode, 166, 2, 1, // Opcode: EORWrs >+/* 384 */ MCD_OPC_FilterValue, 1, 89, 157, // Skip to: 40669 >+/* 388 */ MCD_OPC_Decode, 161, 2, 1, // Opcode: EONWrs >+/* 392 */ MCD_OPC_FilterValue, 3, 81, 157, // Skip to: 40669 >+/* 396 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 399 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 407 >+/* 403 */ MCD_OPC_Decode, 166, 15, 1, // Opcode: SUBWrs >+/* 407 */ MCD_OPC_FilterValue, 1, 66, 157, // Skip to: 40669 >+/* 411 */ MCD_OPC_CheckField, 22, 2, 0, 60, 157, // Skip to: 40669 >+/* 417 */ MCD_OPC_Decode, 167, 15, 2, // Opcode: SUBWrx >+/* 421 */ MCD_OPC_FilterValue, 3, 90, 0, // Skip to: 515 >+/* 425 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 428 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 442 >+/* 432 */ MCD_OPC_CheckField, 22, 2, 3, 39, 157, // Skip to: 40669 >+/* 438 */ MCD_OPC_Decode, 185, 7, 3, // Opcode: LDPSWpost >+/* 442 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 465 >+/* 446 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 449 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 457 >+/* 453 */ MCD_OPC_Decode, 184, 7, 3, // Opcode: LDPSWi >+/* 457 */ MCD_OPC_FilterValue, 3, 16, 157, // Skip to: 40669 >+/* 461 */ MCD_OPC_Decode, 186, 7, 3, // Opcode: LDPSWpre >+/* 465 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 486 >+/* 469 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 472 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 479 >+/* 476 */ MCD_OPC_Decode, 87, 1, // Opcode: ANDSWrs >+/* 479 */ MCD_OPC_FilterValue, 1, 250, 156, // Skip to: 40669 >+/* 483 */ MCD_OPC_Decode, 105, 1, // Opcode: BICSWrs >+/* 486 */ MCD_OPC_FilterValue, 3, 243, 156, // Skip to: 40669 >+/* 490 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 493 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 501 >+/* 497 */ MCD_OPC_Decode, 157, 15, 1, // Opcode: SUBSWrs >+/* 501 */ MCD_OPC_FilterValue, 1, 228, 156, // Skip to: 40669 >+/* 505 */ MCD_OPC_CheckField, 22, 2, 0, 222, 156, // Skip to: 40669 >+/* 511 */ MCD_OPC_Decode, 158, 15, 2, // Opcode: SUBSWrx >+/* 515 */ MCD_OPC_FilterValue, 4, 188, 0, // Skip to: 707 >+/* 519 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 522 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 649 >+/* 526 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 529 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 552 >+/* 533 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 536 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 544 >+/* 540 */ MCD_OPC_Decode, 147, 15, 0, // Opcode: STXRW >+/* 544 */ MCD_OPC_FilterValue, 1, 185, 156, // Skip to: 40669 >+/* 548 */ MCD_OPC_Decode, 191, 14, 0, // Opcode: STLXRW >+/* 552 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 575 >+/* 556 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 559 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 567 >+/* 563 */ MCD_OPC_Decode, 143, 15, 0, // Opcode: STXPW >+/* 567 */ MCD_OPC_FilterValue, 1, 162, 156, // Skip to: 40669 >+/* 571 */ MCD_OPC_Decode, 187, 14, 0, // Opcode: STLXPW >+/* 575 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 598 >+/* 579 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 582 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 590 >+/* 586 */ MCD_OPC_Decode, 171, 8, 0, // Opcode: LDXRW >+/* 590 */ MCD_OPC_FilterValue, 1, 139, 156, // Skip to: 40669 >+/* 594 */ MCD_OPC_Decode, 171, 7, 0, // Opcode: LDAXRW >+/* 598 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 621 >+/* 602 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 605 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 613 >+/* 609 */ MCD_OPC_Decode, 167, 8, 0, // Opcode: LDXPW >+/* 613 */ MCD_OPC_FilterValue, 1, 116, 156, // Skip to: 40669 >+/* 617 */ MCD_OPC_Decode, 167, 7, 0, // Opcode: LDAXPW >+/* 621 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 635 >+/* 625 */ MCD_OPC_CheckField, 15, 1, 1, 102, 156, // Skip to: 40669 >+/* 631 */ MCD_OPC_Decode, 185, 14, 0, // Opcode: STLRW >+/* 635 */ MCD_OPC_FilterValue, 6, 94, 156, // Skip to: 40669 >+/* 639 */ MCD_OPC_CheckField, 15, 1, 1, 88, 156, // Skip to: 40669 >+/* 645 */ MCD_OPC_Decode, 165, 7, 0, // Opcode: LDARW >+/* 649 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 670 >+/* 653 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 656 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 663 >+/* 660 */ MCD_OPC_Decode, 96, 1, // Opcode: ANDXrs >+/* 663 */ MCD_OPC_FilterValue, 1, 66, 156, // Skip to: 40669 >+/* 667 */ MCD_OPC_Decode, 111, 1, // Opcode: BICXrs >+/* 670 */ MCD_OPC_FilterValue, 3, 59, 156, // Skip to: 40669 >+/* 674 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 677 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 684 >+/* 681 */ MCD_OPC_Decode, 66, 1, // Opcode: ADDXrs >+/* 684 */ MCD_OPC_FilterValue, 1, 45, 156, // Skip to: 40669 >+/* 688 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 691 */ MCD_OPC_FilterValue, 0, 38, 156, // Skip to: 40669 >+/* 695 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 704 >+/* 701 */ MCD_OPC_Decode, 68, 2, // Opcode: ADDXrx64 >+/* 704 */ MCD_OPC_Decode, 67, 2, // Opcode: ADDXrx >+/* 707 */ MCD_OPC_FilterValue, 5, 141, 0, // Skip to: 852 >+/* 711 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 714 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 753 >+/* 718 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 721 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 729 >+/* 725 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: STNPXi >+/* 729 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 737 >+/* 733 */ MCD_OPC_Decode, 177, 7, 3, // Opcode: LDNPXi >+/* 737 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 745 >+/* 741 */ MCD_OPC_Decode, 211, 14, 3, // Opcode: STPXpost >+/* 745 */ MCD_OPC_FilterValue, 3, 240, 155, // Skip to: 40669 >+/* 749 */ MCD_OPC_Decode, 194, 7, 3, // Opcode: LDPXpost >+/* 753 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 792 >+/* 757 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 760 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 768 >+/* 764 */ MCD_OPC_Decode, 210, 14, 3, // Opcode: STPXi >+/* 768 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 776 >+/* 772 */ MCD_OPC_Decode, 193, 7, 3, // Opcode: LDPXi >+/* 776 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 784 >+/* 780 */ MCD_OPC_Decode, 212, 14, 3, // Opcode: STPXpre >+/* 784 */ MCD_OPC_FilterValue, 3, 201, 155, // Skip to: 40669 >+/* 788 */ MCD_OPC_Decode, 195, 7, 3, // Opcode: LDPXpre >+/* 792 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 815 >+/* 796 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 799 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 807 >+/* 803 */ MCD_OPC_Decode, 138, 9, 1, // Opcode: ORRXrs >+/* 807 */ MCD_OPC_FilterValue, 1, 178, 155, // Skip to: 40669 >+/* 811 */ MCD_OPC_Decode, 130, 9, 1, // Opcode: ORNXrs >+/* 815 */ MCD_OPC_FilterValue, 3, 170, 155, // Skip to: 40669 >+/* 819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 822 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 829 >+/* 826 */ MCD_OPC_Decode, 52, 1, // Opcode: ADDSXrs >+/* 829 */ MCD_OPC_FilterValue, 1, 156, 155, // Skip to: 40669 >+/* 833 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 836 */ MCD_OPC_FilterValue, 0, 149, 155, // Skip to: 40669 >+/* 840 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 849 >+/* 846 */ MCD_OPC_Decode, 54, 2, // Opcode: ADDSXrx64 >+/* 849 */ MCD_OPC_Decode, 53, 2, // Opcode: ADDSXrx >+/* 852 */ MCD_OPC_FilterValue, 6, 193, 0, // Skip to: 1049 >+/* 856 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 859 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 986 >+/* 863 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 866 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 889 >+/* 870 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 873 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 881 >+/* 877 */ MCD_OPC_Decode, 148, 15, 0, // Opcode: STXRX >+/* 881 */ MCD_OPC_FilterValue, 1, 104, 155, // Skip to: 40669 >+/* 885 */ MCD_OPC_Decode, 192, 14, 0, // Opcode: STLXRX >+/* 889 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 912 >+/* 893 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 896 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 904 >+/* 900 */ MCD_OPC_Decode, 144, 15, 0, // Opcode: STXPX >+/* 904 */ MCD_OPC_FilterValue, 1, 81, 155, // Skip to: 40669 >+/* 908 */ MCD_OPC_Decode, 188, 14, 0, // Opcode: STLXPX >+/* 912 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 935 >+/* 916 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 919 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 927 >+/* 923 */ MCD_OPC_Decode, 172, 8, 0, // Opcode: LDXRX >+/* 927 */ MCD_OPC_FilterValue, 1, 58, 155, // Skip to: 40669 >+/* 931 */ MCD_OPC_Decode, 172, 7, 0, // Opcode: LDAXRX >+/* 935 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 958 >+/* 939 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 942 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 950 >+/* 946 */ MCD_OPC_Decode, 168, 8, 0, // Opcode: LDXPX >+/* 950 */ MCD_OPC_FilterValue, 1, 35, 155, // Skip to: 40669 >+/* 954 */ MCD_OPC_Decode, 168, 7, 0, // Opcode: LDAXPX >+/* 958 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 972 >+/* 962 */ MCD_OPC_CheckField, 15, 1, 1, 21, 155, // Skip to: 40669 >+/* 968 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: STLRX >+/* 972 */ MCD_OPC_FilterValue, 6, 13, 155, // Skip to: 40669 >+/* 976 */ MCD_OPC_CheckField, 15, 1, 1, 7, 155, // Skip to: 40669 >+/* 982 */ MCD_OPC_Decode, 166, 7, 0, // Opcode: LDARX >+/* 986 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1009 >+/* 990 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 993 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1001 >+/* 997 */ MCD_OPC_Decode, 169, 2, 1, // Opcode: EORXrs >+/* 1001 */ MCD_OPC_FilterValue, 1, 240, 154, // Skip to: 40669 >+/* 1005 */ MCD_OPC_Decode, 163, 2, 1, // Opcode: EONXrs >+/* 1009 */ MCD_OPC_FilterValue, 3, 232, 154, // Skip to: 40669 >+/* 1013 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 1016 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1024 >+/* 1020 */ MCD_OPC_Decode, 170, 15, 1, // Opcode: SUBXrs >+/* 1024 */ MCD_OPC_FilterValue, 1, 217, 154, // Skip to: 40669 >+/* 1028 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 1031 */ MCD_OPC_FilterValue, 0, 210, 154, // Skip to: 40669 >+/* 1035 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1045 >+/* 1041 */ MCD_OPC_Decode, 172, 15, 2, // Opcode: SUBXrx64 >+/* 1045 */ MCD_OPC_Decode, 171, 15, 2, // Opcode: SUBXrx >+/* 1049 */ MCD_OPC_FilterValue, 7, 192, 154, // Skip to: 40669 >+/* 1053 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 1056 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1078 >+/* 1060 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 1063 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1070 >+/* 1067 */ MCD_OPC_Decode, 90, 1, // Opcode: ANDSXrs >+/* 1070 */ MCD_OPC_FilterValue, 3, 171, 154, // Skip to: 40669 >+/* 1074 */ MCD_OPC_Decode, 161, 15, 1, // Opcode: SUBSXrs >+/* 1078 */ MCD_OPC_FilterValue, 1, 163, 154, // Skip to: 40669 >+/* 1082 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 1085 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1092 >+/* 1089 */ MCD_OPC_Decode, 107, 1, // Opcode: BICSXrs >+/* 1092 */ MCD_OPC_FilterValue, 3, 149, 154, // Skip to: 40669 >+/* 1096 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 1099 */ MCD_OPC_FilterValue, 0, 142, 154, // Skip to: 40669 >+/* 1103 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1113 >+/* 1109 */ MCD_OPC_Decode, 163, 15, 2, // Opcode: SUBSXrx64 >+/* 1113 */ MCD_OPC_Decode, 162, 15, 2, // Opcode: SUBSXrx >+/* 1117 */ MCD_OPC_FilterValue, 3, 234, 110, // Skip to: 29515 >+/* 1121 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 1124 */ MCD_OPC_FilterValue, 0, 165, 2, // Skip to: 1805 >+/* 1128 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 1131 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 1438 >+/* 1135 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... >+/* 1138 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1150 >+/* 1142 */ MCD_OPC_CheckPredicate, 0, 99, 154, // Skip to: 40669 >+/* 1146 */ MCD_OPC_Decode, 171, 14, 4, // Opcode: ST4Fourv8b >+/* 1150 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1162 >+/* 1154 */ MCD_OPC_CheckPredicate, 0, 87, 154, // Skip to: 40669 >+/* 1158 */ MCD_OPC_Decode, 167, 14, 4, // Opcode: ST4Fourv4h >+/* 1162 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1174 >+/* 1166 */ MCD_OPC_CheckPredicate, 0, 75, 154, // Skip to: 40669 >+/* 1170 */ MCD_OPC_Decode, 165, 14, 4, // Opcode: ST4Fourv2s >+/* 1174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1186 >+/* 1178 */ MCD_OPC_CheckPredicate, 0, 63, 154, // Skip to: 40669 >+/* 1182 */ MCD_OPC_Decode, 185, 13, 4, // Opcode: ST1Fourv8b >+/* 1186 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1198 >+/* 1190 */ MCD_OPC_CheckPredicate, 0, 51, 154, // Skip to: 40669 >+/* 1194 */ MCD_OPC_Decode, 181, 13, 4, // Opcode: ST1Fourv4h >+/* 1198 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1210 >+/* 1202 */ MCD_OPC_CheckPredicate, 0, 39, 154, // Skip to: 40669 >+/* 1206 */ MCD_OPC_Decode, 179, 13, 4, // Opcode: ST1Fourv2s >+/* 1210 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1222 >+/* 1214 */ MCD_OPC_CheckPredicate, 0, 27, 154, // Skip to: 40669 >+/* 1218 */ MCD_OPC_Decode, 175, 13, 4, // Opcode: ST1Fourv1d >+/* 1222 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1234 >+/* 1226 */ MCD_OPC_CheckPredicate, 0, 15, 154, // Skip to: 40669 >+/* 1230 */ MCD_OPC_Decode, 149, 14, 5, // Opcode: ST3Threev8b >+/* 1234 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1246 >+/* 1238 */ MCD_OPC_CheckPredicate, 0, 3, 154, // Skip to: 40669 >+/* 1242 */ MCD_OPC_Decode, 145, 14, 5, // Opcode: ST3Threev4h >+/* 1246 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1258 >+/* 1250 */ MCD_OPC_CheckPredicate, 0, 247, 153, // Skip to: 40669 >+/* 1254 */ MCD_OPC_Decode, 143, 14, 5, // Opcode: ST3Threev2s >+/* 1258 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1270 >+/* 1262 */ MCD_OPC_CheckPredicate, 0, 235, 153, // Skip to: 40669 >+/* 1266 */ MCD_OPC_Decode, 217, 13, 5, // Opcode: ST1Threev8b >+/* 1270 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1282 >+/* 1274 */ MCD_OPC_CheckPredicate, 0, 223, 153, // Skip to: 40669 >+/* 1278 */ MCD_OPC_Decode, 213, 13, 5, // Opcode: ST1Threev4h >+/* 1282 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1294 >+/* 1286 */ MCD_OPC_CheckPredicate, 0, 211, 153, // Skip to: 40669 >+/* 1290 */ MCD_OPC_Decode, 211, 13, 5, // Opcode: ST1Threev2s >+/* 1294 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1306 >+/* 1298 */ MCD_OPC_CheckPredicate, 0, 199, 153, // Skip to: 40669 >+/* 1302 */ MCD_OPC_Decode, 207, 13, 5, // Opcode: ST1Threev1d >+/* 1306 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1318 >+/* 1310 */ MCD_OPC_CheckPredicate, 0, 187, 153, // Skip to: 40669 >+/* 1314 */ MCD_OPC_Decode, 201, 13, 6, // Opcode: ST1Onev8b >+/* 1318 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1330 >+/* 1322 */ MCD_OPC_CheckPredicate, 0, 175, 153, // Skip to: 40669 >+/* 1326 */ MCD_OPC_Decode, 197, 13, 6, // Opcode: ST1Onev4h >+/* 1330 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1342 >+/* 1334 */ MCD_OPC_CheckPredicate, 0, 163, 153, // Skip to: 40669 >+/* 1338 */ MCD_OPC_Decode, 195, 13, 6, // Opcode: ST1Onev2s >+/* 1342 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1354 >+/* 1346 */ MCD_OPC_CheckPredicate, 0, 151, 153, // Skip to: 40669 >+/* 1350 */ MCD_OPC_Decode, 191, 13, 6, // Opcode: ST1Onev1d >+/* 1354 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1366 >+/* 1358 */ MCD_OPC_CheckPredicate, 0, 139, 153, // Skip to: 40669 >+/* 1362 */ MCD_OPC_Decode, 255, 13, 7, // Opcode: ST2Twov8b >+/* 1366 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1378 >+/* 1370 */ MCD_OPC_CheckPredicate, 0, 127, 153, // Skip to: 40669 >+/* 1374 */ MCD_OPC_Decode, 251, 13, 7, // Opcode: ST2Twov4h >+/* 1378 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1390 >+/* 1382 */ MCD_OPC_CheckPredicate, 0, 115, 153, // Skip to: 40669 >+/* 1386 */ MCD_OPC_Decode, 249, 13, 7, // Opcode: ST2Twov2s >+/* 1390 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1402 >+/* 1394 */ MCD_OPC_CheckPredicate, 0, 103, 153, // Skip to: 40669 >+/* 1398 */ MCD_OPC_Decode, 233, 13, 7, // Opcode: ST1Twov8b >+/* 1402 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1414 >+/* 1406 */ MCD_OPC_CheckPredicate, 0, 91, 153, // Skip to: 40669 >+/* 1410 */ MCD_OPC_Decode, 229, 13, 7, // Opcode: ST1Twov4h >+/* 1414 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1426 >+/* 1418 */ MCD_OPC_CheckPredicate, 0, 79, 153, // Skip to: 40669 >+/* 1422 */ MCD_OPC_Decode, 227, 13, 7, // Opcode: ST1Twov2s >+/* 1426 */ MCD_OPC_FilterValue, 43, 71, 153, // Skip to: 40669 >+/* 1430 */ MCD_OPC_CheckPredicate, 0, 67, 153, // Skip to: 40669 >+/* 1434 */ MCD_OPC_Decode, 223, 13, 7, // Opcode: ST1Twov1d >+/* 1438 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1446 >+/* 1442 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: STNPSi >+/* 1446 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 1789 >+/* 1450 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... >+/* 1453 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1465 >+/* 1457 */ MCD_OPC_CheckPredicate, 0, 40, 153, // Skip to: 40669 >+/* 1461 */ MCD_OPC_Decode, 161, 14, 8, // Opcode: ST4Fourv16b >+/* 1465 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1477 >+/* 1469 */ MCD_OPC_CheckPredicate, 0, 28, 153, // Skip to: 40669 >+/* 1473 */ MCD_OPC_Decode, 173, 14, 8, // Opcode: ST4Fourv8h >+/* 1477 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1489 >+/* 1481 */ MCD_OPC_CheckPredicate, 0, 16, 153, // Skip to: 40669 >+/* 1485 */ MCD_OPC_Decode, 169, 14, 8, // Opcode: ST4Fourv4s >+/* 1489 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1501 >+/* 1493 */ MCD_OPC_CheckPredicate, 0, 4, 153, // Skip to: 40669 >+/* 1497 */ MCD_OPC_Decode, 163, 14, 8, // Opcode: ST4Fourv2d >+/* 1501 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1513 >+/* 1505 */ MCD_OPC_CheckPredicate, 0, 248, 152, // Skip to: 40669 >+/* 1509 */ MCD_OPC_Decode, 173, 13, 8, // Opcode: ST1Fourv16b >+/* 1513 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1525 >+/* 1517 */ MCD_OPC_CheckPredicate, 0, 236, 152, // Skip to: 40669 >+/* 1521 */ MCD_OPC_Decode, 187, 13, 8, // Opcode: ST1Fourv8h >+/* 1525 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1537 >+/* 1529 */ MCD_OPC_CheckPredicate, 0, 224, 152, // Skip to: 40669 >+/* 1533 */ MCD_OPC_Decode, 183, 13, 8, // Opcode: ST1Fourv4s >+/* 1537 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1549 >+/* 1541 */ MCD_OPC_CheckPredicate, 0, 212, 152, // Skip to: 40669 >+/* 1545 */ MCD_OPC_Decode, 177, 13, 8, // Opcode: ST1Fourv2d >+/* 1549 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1561 >+/* 1553 */ MCD_OPC_CheckPredicate, 0, 200, 152, // Skip to: 40669 >+/* 1557 */ MCD_OPC_Decode, 139, 14, 9, // Opcode: ST3Threev16b >+/* 1561 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1573 >+/* 1565 */ MCD_OPC_CheckPredicate, 0, 188, 152, // Skip to: 40669 >+/* 1569 */ MCD_OPC_Decode, 151, 14, 9, // Opcode: ST3Threev8h >+/* 1573 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1585 >+/* 1577 */ MCD_OPC_CheckPredicate, 0, 176, 152, // Skip to: 40669 >+/* 1581 */ MCD_OPC_Decode, 147, 14, 9, // Opcode: ST3Threev4s >+/* 1585 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1597 >+/* 1589 */ MCD_OPC_CheckPredicate, 0, 164, 152, // Skip to: 40669 >+/* 1593 */ MCD_OPC_Decode, 141, 14, 9, // Opcode: ST3Threev2d >+/* 1597 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1609 >+/* 1601 */ MCD_OPC_CheckPredicate, 0, 152, 152, // Skip to: 40669 >+/* 1605 */ MCD_OPC_Decode, 205, 13, 9, // Opcode: ST1Threev16b >+/* 1609 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1621 >+/* 1613 */ MCD_OPC_CheckPredicate, 0, 140, 152, // Skip to: 40669 >+/* 1617 */ MCD_OPC_Decode, 219, 13, 9, // Opcode: ST1Threev8h >+/* 1621 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1633 >+/* 1625 */ MCD_OPC_CheckPredicate, 0, 128, 152, // Skip to: 40669 >+/* 1629 */ MCD_OPC_Decode, 215, 13, 9, // Opcode: ST1Threev4s >+/* 1633 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1645 >+/* 1637 */ MCD_OPC_CheckPredicate, 0, 116, 152, // Skip to: 40669 >+/* 1641 */ MCD_OPC_Decode, 209, 13, 9, // Opcode: ST1Threev2d >+/* 1645 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1657 >+/* 1649 */ MCD_OPC_CheckPredicate, 0, 104, 152, // Skip to: 40669 >+/* 1653 */ MCD_OPC_Decode, 189, 13, 10, // Opcode: ST1Onev16b >+/* 1657 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1669 >+/* 1661 */ MCD_OPC_CheckPredicate, 0, 92, 152, // Skip to: 40669 >+/* 1665 */ MCD_OPC_Decode, 203, 13, 10, // Opcode: ST1Onev8h >+/* 1669 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1681 >+/* 1673 */ MCD_OPC_CheckPredicate, 0, 80, 152, // Skip to: 40669 >+/* 1677 */ MCD_OPC_Decode, 199, 13, 10, // Opcode: ST1Onev4s >+/* 1681 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1693 >+/* 1685 */ MCD_OPC_CheckPredicate, 0, 68, 152, // Skip to: 40669 >+/* 1689 */ MCD_OPC_Decode, 193, 13, 10, // Opcode: ST1Onev2d >+/* 1693 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1705 >+/* 1697 */ MCD_OPC_CheckPredicate, 0, 56, 152, // Skip to: 40669 >+/* 1701 */ MCD_OPC_Decode, 245, 13, 11, // Opcode: ST2Twov16b >+/* 1705 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1717 >+/* 1709 */ MCD_OPC_CheckPredicate, 0, 44, 152, // Skip to: 40669 >+/* 1713 */ MCD_OPC_Decode, 129, 14, 11, // Opcode: ST2Twov8h >+/* 1717 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1729 >+/* 1721 */ MCD_OPC_CheckPredicate, 0, 32, 152, // Skip to: 40669 >+/* 1725 */ MCD_OPC_Decode, 253, 13, 11, // Opcode: ST2Twov4s >+/* 1729 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 1741 >+/* 1733 */ MCD_OPC_CheckPredicate, 0, 20, 152, // Skip to: 40669 >+/* 1737 */ MCD_OPC_Decode, 247, 13, 11, // Opcode: ST2Twov2d >+/* 1741 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1753 >+/* 1745 */ MCD_OPC_CheckPredicate, 0, 8, 152, // Skip to: 40669 >+/* 1749 */ MCD_OPC_Decode, 221, 13, 11, // Opcode: ST1Twov16b >+/* 1753 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1765 >+/* 1757 */ MCD_OPC_CheckPredicate, 0, 252, 151, // Skip to: 40669 >+/* 1761 */ MCD_OPC_Decode, 235, 13, 11, // Opcode: ST1Twov8h >+/* 1765 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1777 >+/* 1769 */ MCD_OPC_CheckPredicate, 0, 240, 151, // Skip to: 40669 >+/* 1773 */ MCD_OPC_Decode, 231, 13, 11, // Opcode: ST1Twov4s >+/* 1777 */ MCD_OPC_FilterValue, 43, 232, 151, // Skip to: 40669 >+/* 1781 */ MCD_OPC_CheckPredicate, 0, 228, 151, // Skip to: 40669 >+/* 1785 */ MCD_OPC_Decode, 225, 13, 11, // Opcode: ST1Twov2d >+/* 1789 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1797 >+/* 1793 */ MCD_OPC_Decode, 193, 14, 3, // Opcode: STNPDi >+/* 1797 */ MCD_OPC_FilterValue, 5, 212, 151, // Skip to: 40669 >+/* 1801 */ MCD_OPC_Decode, 194, 14, 3, // Opcode: STNPQi >+/* 1805 */ MCD_OPC_FilterValue, 1, 165, 2, // Skip to: 2486 >+/* 1809 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 1812 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 2119 >+/* 1816 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... >+/* 1819 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1831 >+/* 1823 */ MCD_OPC_CheckPredicate, 0, 186, 151, // Skip to: 40669 >+/* 1827 */ MCD_OPC_Decode, 135, 7, 4, // Opcode: LD4Fourv8b >+/* 1831 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1843 >+/* 1835 */ MCD_OPC_CheckPredicate, 0, 174, 151, // Skip to: 40669 >+/* 1839 */ MCD_OPC_Decode, 131, 7, 4, // Opcode: LD4Fourv4h >+/* 1843 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1855 >+/* 1847 */ MCD_OPC_CheckPredicate, 0, 162, 151, // Skip to: 40669 >+/* 1851 */ MCD_OPC_Decode, 129, 7, 4, // Opcode: LD4Fourv2s >+/* 1855 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1867 >+/* 1859 */ MCD_OPC_CheckPredicate, 0, 150, 151, // Skip to: 40669 >+/* 1863 */ MCD_OPC_Decode, 229, 5, 4, // Opcode: LD1Fourv8b >+/* 1867 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1879 >+/* 1871 */ MCD_OPC_CheckPredicate, 0, 138, 151, // Skip to: 40669 >+/* 1875 */ MCD_OPC_Decode, 225, 5, 4, // Opcode: LD1Fourv4h >+/* 1879 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1891 >+/* 1883 */ MCD_OPC_CheckPredicate, 0, 126, 151, // Skip to: 40669 >+/* 1887 */ MCD_OPC_Decode, 223, 5, 4, // Opcode: LD1Fourv2s >+/* 1891 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1903 >+/* 1895 */ MCD_OPC_CheckPredicate, 0, 114, 151, // Skip to: 40669 >+/* 1899 */ MCD_OPC_Decode, 219, 5, 4, // Opcode: LD1Fourv1d >+/* 1903 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1915 >+/* 1907 */ MCD_OPC_CheckPredicate, 0, 102, 151, // Skip to: 40669 >+/* 1911 */ MCD_OPC_Decode, 241, 6, 5, // Opcode: LD3Threev8b >+/* 1915 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1927 >+/* 1919 */ MCD_OPC_CheckPredicate, 0, 90, 151, // Skip to: 40669 >+/* 1923 */ MCD_OPC_Decode, 237, 6, 5, // Opcode: LD3Threev4h >+/* 1927 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1939 >+/* 1931 */ MCD_OPC_CheckPredicate, 0, 78, 151, // Skip to: 40669 >+/* 1935 */ MCD_OPC_Decode, 235, 6, 5, // Opcode: LD3Threev2s >+/* 1939 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1951 >+/* 1943 */ MCD_OPC_CheckPredicate, 0, 66, 151, // Skip to: 40669 >+/* 1947 */ MCD_OPC_Decode, 149, 6, 5, // Opcode: LD1Threev8b >+/* 1951 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1963 >+/* 1955 */ MCD_OPC_CheckPredicate, 0, 54, 151, // Skip to: 40669 >+/* 1959 */ MCD_OPC_Decode, 145, 6, 5, // Opcode: LD1Threev4h >+/* 1963 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1975 >+/* 1967 */ MCD_OPC_CheckPredicate, 0, 42, 151, // Skip to: 40669 >+/* 1971 */ MCD_OPC_Decode, 143, 6, 5, // Opcode: LD1Threev2s >+/* 1975 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1987 >+/* 1979 */ MCD_OPC_CheckPredicate, 0, 30, 151, // Skip to: 40669 >+/* 1983 */ MCD_OPC_Decode, 139, 6, 5, // Opcode: LD1Threev1d >+/* 1987 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1999 >+/* 1991 */ MCD_OPC_CheckPredicate, 0, 18, 151, // Skip to: 40669 >+/* 1995 */ MCD_OPC_Decode, 245, 5, 6, // Opcode: LD1Onev8b >+/* 1999 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2011 >+/* 2003 */ MCD_OPC_CheckPredicate, 0, 6, 151, // Skip to: 40669 >+/* 2007 */ MCD_OPC_Decode, 241, 5, 6, // Opcode: LD1Onev4h >+/* 2011 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2023 >+/* 2015 */ MCD_OPC_CheckPredicate, 0, 250, 150, // Skip to: 40669 >+/* 2019 */ MCD_OPC_Decode, 239, 5, 6, // Opcode: LD1Onev2s >+/* 2023 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2035 >+/* 2027 */ MCD_OPC_CheckPredicate, 0, 238, 150, // Skip to: 40669 >+/* 2031 */ MCD_OPC_Decode, 235, 5, 6, // Opcode: LD1Onev1d >+/* 2035 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2047 >+/* 2039 */ MCD_OPC_CheckPredicate, 0, 226, 150, // Skip to: 40669 >+/* 2043 */ MCD_OPC_Decode, 203, 6, 7, // Opcode: LD2Twov8b >+/* 2047 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2059 >+/* 2051 */ MCD_OPC_CheckPredicate, 0, 214, 150, // Skip to: 40669 >+/* 2055 */ MCD_OPC_Decode, 199, 6, 7, // Opcode: LD2Twov4h >+/* 2059 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2071 >+/* 2063 */ MCD_OPC_CheckPredicate, 0, 202, 150, // Skip to: 40669 >+/* 2067 */ MCD_OPC_Decode, 197, 6, 7, // Opcode: LD2Twov2s >+/* 2071 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2083 >+/* 2075 */ MCD_OPC_CheckPredicate, 0, 190, 150, // Skip to: 40669 >+/* 2079 */ MCD_OPC_Decode, 165, 6, 7, // Opcode: LD1Twov8b >+/* 2083 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2095 >+/* 2087 */ MCD_OPC_CheckPredicate, 0, 178, 150, // Skip to: 40669 >+/* 2091 */ MCD_OPC_Decode, 161, 6, 7, // Opcode: LD1Twov4h >+/* 2095 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2107 >+/* 2099 */ MCD_OPC_CheckPredicate, 0, 166, 150, // Skip to: 40669 >+/* 2103 */ MCD_OPC_Decode, 159, 6, 7, // Opcode: LD1Twov2s >+/* 2107 */ MCD_OPC_FilterValue, 43, 158, 150, // Skip to: 40669 >+/* 2111 */ MCD_OPC_CheckPredicate, 0, 154, 150, // Skip to: 40669 >+/* 2115 */ MCD_OPC_Decode, 155, 6, 7, // Opcode: LD1Twov1d >+/* 2119 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2127 >+/* 2123 */ MCD_OPC_Decode, 175, 7, 3, // Opcode: LDNPSi >+/* 2127 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 2470 >+/* 2131 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... >+/* 2134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2146 >+/* 2138 */ MCD_OPC_CheckPredicate, 0, 127, 150, // Skip to: 40669 >+/* 2142 */ MCD_OPC_Decode, 253, 6, 8, // Opcode: LD4Fourv16b >+/* 2146 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2158 >+/* 2150 */ MCD_OPC_CheckPredicate, 0, 115, 150, // Skip to: 40669 >+/* 2154 */ MCD_OPC_Decode, 137, 7, 8, // Opcode: LD4Fourv8h >+/* 2158 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2170 >+/* 2162 */ MCD_OPC_CheckPredicate, 0, 103, 150, // Skip to: 40669 >+/* 2166 */ MCD_OPC_Decode, 133, 7, 8, // Opcode: LD4Fourv4s >+/* 2170 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2182 >+/* 2174 */ MCD_OPC_CheckPredicate, 0, 91, 150, // Skip to: 40669 >+/* 2178 */ MCD_OPC_Decode, 255, 6, 8, // Opcode: LD4Fourv2d >+/* 2182 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 2194 >+/* 2186 */ MCD_OPC_CheckPredicate, 0, 79, 150, // Skip to: 40669 >+/* 2190 */ MCD_OPC_Decode, 217, 5, 8, // Opcode: LD1Fourv16b >+/* 2194 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 2206 >+/* 2198 */ MCD_OPC_CheckPredicate, 0, 67, 150, // Skip to: 40669 >+/* 2202 */ MCD_OPC_Decode, 231, 5, 8, // Opcode: LD1Fourv8h >+/* 2206 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 2218 >+/* 2210 */ MCD_OPC_CheckPredicate, 0, 55, 150, // Skip to: 40669 >+/* 2214 */ MCD_OPC_Decode, 227, 5, 8, // Opcode: LD1Fourv4s >+/* 2218 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 2230 >+/* 2222 */ MCD_OPC_CheckPredicate, 0, 43, 150, // Skip to: 40669 >+/* 2226 */ MCD_OPC_Decode, 221, 5, 8, // Opcode: LD1Fourv2d >+/* 2230 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 2242 >+/* 2234 */ MCD_OPC_CheckPredicate, 0, 31, 150, // Skip to: 40669 >+/* 2238 */ MCD_OPC_Decode, 231, 6, 9, // Opcode: LD3Threev16b >+/* 2242 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 2254 >+/* 2246 */ MCD_OPC_CheckPredicate, 0, 19, 150, // Skip to: 40669 >+/* 2250 */ MCD_OPC_Decode, 243, 6, 9, // Opcode: LD3Threev8h >+/* 2254 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2266 >+/* 2258 */ MCD_OPC_CheckPredicate, 0, 7, 150, // Skip to: 40669 >+/* 2262 */ MCD_OPC_Decode, 239, 6, 9, // Opcode: LD3Threev4s >+/* 2266 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2278 >+/* 2270 */ MCD_OPC_CheckPredicate, 0, 251, 149, // Skip to: 40669 >+/* 2274 */ MCD_OPC_Decode, 233, 6, 9, // Opcode: LD3Threev2d >+/* 2278 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 2290 >+/* 2282 */ MCD_OPC_CheckPredicate, 0, 239, 149, // Skip to: 40669 >+/* 2286 */ MCD_OPC_Decode, 137, 6, 9, // Opcode: LD1Threev16b >+/* 2290 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 2302 >+/* 2294 */ MCD_OPC_CheckPredicate, 0, 227, 149, // Skip to: 40669 >+/* 2298 */ MCD_OPC_Decode, 151, 6, 9, // Opcode: LD1Threev8h >+/* 2302 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 2314 >+/* 2306 */ MCD_OPC_CheckPredicate, 0, 215, 149, // Skip to: 40669 >+/* 2310 */ MCD_OPC_Decode, 147, 6, 9, // Opcode: LD1Threev4s >+/* 2314 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 2326 >+/* 2318 */ MCD_OPC_CheckPredicate, 0, 203, 149, // Skip to: 40669 >+/* 2322 */ MCD_OPC_Decode, 141, 6, 9, // Opcode: LD1Threev2d >+/* 2326 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 2338 >+/* 2330 */ MCD_OPC_CheckPredicate, 0, 191, 149, // Skip to: 40669 >+/* 2334 */ MCD_OPC_Decode, 233, 5, 10, // Opcode: LD1Onev16b >+/* 2338 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2350 >+/* 2342 */ MCD_OPC_CheckPredicate, 0, 179, 149, // Skip to: 40669 >+/* 2346 */ MCD_OPC_Decode, 247, 5, 10, // Opcode: LD1Onev8h >+/* 2350 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2362 >+/* 2354 */ MCD_OPC_CheckPredicate, 0, 167, 149, // Skip to: 40669 >+/* 2358 */ MCD_OPC_Decode, 243, 5, 10, // Opcode: LD1Onev4s >+/* 2362 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2374 >+/* 2366 */ MCD_OPC_CheckPredicate, 0, 155, 149, // Skip to: 40669 >+/* 2370 */ MCD_OPC_Decode, 237, 5, 10, // Opcode: LD1Onev2d >+/* 2374 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2386 >+/* 2378 */ MCD_OPC_CheckPredicate, 0, 143, 149, // Skip to: 40669 >+/* 2382 */ MCD_OPC_Decode, 193, 6, 11, // Opcode: LD2Twov16b >+/* 2386 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2398 >+/* 2390 */ MCD_OPC_CheckPredicate, 0, 131, 149, // Skip to: 40669 >+/* 2394 */ MCD_OPC_Decode, 205, 6, 11, // Opcode: LD2Twov8h >+/* 2398 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2410 >+/* 2402 */ MCD_OPC_CheckPredicate, 0, 119, 149, // Skip to: 40669 >+/* 2406 */ MCD_OPC_Decode, 201, 6, 11, // Opcode: LD2Twov4s >+/* 2410 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 2422 >+/* 2414 */ MCD_OPC_CheckPredicate, 0, 107, 149, // Skip to: 40669 >+/* 2418 */ MCD_OPC_Decode, 195, 6, 11, // Opcode: LD2Twov2d >+/* 2422 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2434 >+/* 2426 */ MCD_OPC_CheckPredicate, 0, 95, 149, // Skip to: 40669 >+/* 2430 */ MCD_OPC_Decode, 153, 6, 11, // Opcode: LD1Twov16b >+/* 2434 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2446 >+/* 2438 */ MCD_OPC_CheckPredicate, 0, 83, 149, // Skip to: 40669 >+/* 2442 */ MCD_OPC_Decode, 167, 6, 11, // Opcode: LD1Twov8h >+/* 2446 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2458 >+/* 2450 */ MCD_OPC_CheckPredicate, 0, 71, 149, // Skip to: 40669 >+/* 2454 */ MCD_OPC_Decode, 163, 6, 11, // Opcode: LD1Twov4s >+/* 2458 */ MCD_OPC_FilterValue, 43, 63, 149, // Skip to: 40669 >+/* 2462 */ MCD_OPC_CheckPredicate, 0, 59, 149, // Skip to: 40669 >+/* 2466 */ MCD_OPC_Decode, 157, 6, 11, // Opcode: LD1Twov2d >+/* 2470 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2478 >+/* 2474 */ MCD_OPC_Decode, 173, 7, 3, // Opcode: LDNPDi >+/* 2478 */ MCD_OPC_FilterValue, 5, 43, 149, // Skip to: 40669 >+/* 2482 */ MCD_OPC_Decode, 174, 7, 3, // Opcode: LDNPQi >+/* 2486 */ MCD_OPC_FilterValue, 2, 227, 3, // Skip to: 3485 >+/* 2490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 2493 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 2950 >+/* 2497 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 2500 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2518 >+/* 2504 */ MCD_OPC_CheckPredicate, 0, 17, 149, // Skip to: 40669 >+/* 2508 */ MCD_OPC_CheckField, 21, 1, 0, 11, 149, // Skip to: 40669 >+/* 2514 */ MCD_OPC_Decode, 172, 14, 12, // Opcode: ST4Fourv8b_POST >+/* 2518 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2536 >+/* 2522 */ MCD_OPC_CheckPredicate, 0, 255, 148, // Skip to: 40669 >+/* 2526 */ MCD_OPC_CheckField, 21, 1, 0, 249, 148, // Skip to: 40669 >+/* 2532 */ MCD_OPC_Decode, 168, 14, 12, // Opcode: ST4Fourv4h_POST >+/* 2536 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2554 >+/* 2540 */ MCD_OPC_CheckPredicate, 0, 237, 148, // Skip to: 40669 >+/* 2544 */ MCD_OPC_CheckField, 21, 1, 0, 231, 148, // Skip to: 40669 >+/* 2550 */ MCD_OPC_Decode, 166, 14, 12, // Opcode: ST4Fourv2s_POST >+/* 2554 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 2572 >+/* 2558 */ MCD_OPC_CheckPredicate, 0, 219, 148, // Skip to: 40669 >+/* 2562 */ MCD_OPC_CheckField, 21, 1, 0, 213, 148, // Skip to: 40669 >+/* 2568 */ MCD_OPC_Decode, 186, 13, 12, // Opcode: ST1Fourv8b_POST >+/* 2572 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 2590 >+/* 2576 */ MCD_OPC_CheckPredicate, 0, 201, 148, // Skip to: 40669 >+/* 2580 */ MCD_OPC_CheckField, 21, 1, 0, 195, 148, // Skip to: 40669 >+/* 2586 */ MCD_OPC_Decode, 182, 13, 12, // Opcode: ST1Fourv4h_POST >+/* 2590 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2608 >+/* 2594 */ MCD_OPC_CheckPredicate, 0, 183, 148, // Skip to: 40669 >+/* 2598 */ MCD_OPC_CheckField, 21, 1, 0, 177, 148, // Skip to: 40669 >+/* 2604 */ MCD_OPC_Decode, 180, 13, 12, // Opcode: ST1Fourv2s_POST >+/* 2608 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2626 >+/* 2612 */ MCD_OPC_CheckPredicate, 0, 165, 148, // Skip to: 40669 >+/* 2616 */ MCD_OPC_CheckField, 21, 1, 0, 159, 148, // Skip to: 40669 >+/* 2622 */ MCD_OPC_Decode, 176, 13, 12, // Opcode: ST1Fourv1d_POST >+/* 2626 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 2644 >+/* 2630 */ MCD_OPC_CheckPredicate, 0, 147, 148, // Skip to: 40669 >+/* 2634 */ MCD_OPC_CheckField, 21, 1, 0, 141, 148, // Skip to: 40669 >+/* 2640 */ MCD_OPC_Decode, 150, 14, 13, // Opcode: ST3Threev8b_POST >+/* 2644 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 2662 >+/* 2648 */ MCD_OPC_CheckPredicate, 0, 129, 148, // Skip to: 40669 >+/* 2652 */ MCD_OPC_CheckField, 21, 1, 0, 123, 148, // Skip to: 40669 >+/* 2658 */ MCD_OPC_Decode, 146, 14, 13, // Opcode: ST3Threev4h_POST >+/* 2662 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 2680 >+/* 2666 */ MCD_OPC_CheckPredicate, 0, 111, 148, // Skip to: 40669 >+/* 2670 */ MCD_OPC_CheckField, 21, 1, 0, 105, 148, // Skip to: 40669 >+/* 2676 */ MCD_OPC_Decode, 144, 14, 13, // Opcode: ST3Threev2s_POST >+/* 2680 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 2698 >+/* 2684 */ MCD_OPC_CheckPredicate, 0, 93, 148, // Skip to: 40669 >+/* 2688 */ MCD_OPC_CheckField, 21, 1, 0, 87, 148, // Skip to: 40669 >+/* 2694 */ MCD_OPC_Decode, 218, 13, 13, // Opcode: ST1Threev8b_POST >+/* 2698 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 2716 >+/* 2702 */ MCD_OPC_CheckPredicate, 0, 75, 148, // Skip to: 40669 >+/* 2706 */ MCD_OPC_CheckField, 21, 1, 0, 69, 148, // Skip to: 40669 >+/* 2712 */ MCD_OPC_Decode, 214, 13, 13, // Opcode: ST1Threev4h_POST >+/* 2716 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 2734 >+/* 2720 */ MCD_OPC_CheckPredicate, 0, 57, 148, // Skip to: 40669 >+/* 2724 */ MCD_OPC_CheckField, 21, 1, 0, 51, 148, // Skip to: 40669 >+/* 2730 */ MCD_OPC_Decode, 212, 13, 13, // Opcode: ST1Threev2s_POST >+/* 2734 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 2752 >+/* 2738 */ MCD_OPC_CheckPredicate, 0, 39, 148, // Skip to: 40669 >+/* 2742 */ MCD_OPC_CheckField, 21, 1, 0, 33, 148, // Skip to: 40669 >+/* 2748 */ MCD_OPC_Decode, 208, 13, 13, // Opcode: ST1Threev1d_POST >+/* 2752 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 2770 >+/* 2756 */ MCD_OPC_CheckPredicate, 0, 21, 148, // Skip to: 40669 >+/* 2760 */ MCD_OPC_CheckField, 21, 1, 0, 15, 148, // Skip to: 40669 >+/* 2766 */ MCD_OPC_Decode, 202, 13, 14, // Opcode: ST1Onev8b_POST >+/* 2770 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 2788 >+/* 2774 */ MCD_OPC_CheckPredicate, 0, 3, 148, // Skip to: 40669 >+/* 2778 */ MCD_OPC_CheckField, 21, 1, 0, 253, 147, // Skip to: 40669 >+/* 2784 */ MCD_OPC_Decode, 198, 13, 14, // Opcode: ST1Onev4h_POST >+/* 2788 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 2806 >+/* 2792 */ MCD_OPC_CheckPredicate, 0, 241, 147, // Skip to: 40669 >+/* 2796 */ MCD_OPC_CheckField, 21, 1, 0, 235, 147, // Skip to: 40669 >+/* 2802 */ MCD_OPC_Decode, 196, 13, 14, // Opcode: ST1Onev2s_POST >+/* 2806 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 2824 >+/* 2810 */ MCD_OPC_CheckPredicate, 0, 223, 147, // Skip to: 40669 >+/* 2814 */ MCD_OPC_CheckField, 21, 1, 0, 217, 147, // Skip to: 40669 >+/* 2820 */ MCD_OPC_Decode, 192, 13, 14, // Opcode: ST1Onev1d_POST >+/* 2824 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2842 >+/* 2828 */ MCD_OPC_CheckPredicate, 0, 205, 147, // Skip to: 40669 >+/* 2832 */ MCD_OPC_CheckField, 21, 1, 0, 199, 147, // Skip to: 40669 >+/* 2838 */ MCD_OPC_Decode, 128, 14, 15, // Opcode: ST2Twov8b_POST >+/* 2842 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2860 >+/* 2846 */ MCD_OPC_CheckPredicate, 0, 187, 147, // Skip to: 40669 >+/* 2850 */ MCD_OPC_CheckField, 21, 1, 0, 181, 147, // Skip to: 40669 >+/* 2856 */ MCD_OPC_Decode, 252, 13, 15, // Opcode: ST2Twov4h_POST >+/* 2860 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 2878 >+/* 2864 */ MCD_OPC_CheckPredicate, 0, 169, 147, // Skip to: 40669 >+/* 2868 */ MCD_OPC_CheckField, 21, 1, 0, 163, 147, // Skip to: 40669 >+/* 2874 */ MCD_OPC_Decode, 250, 13, 15, // Opcode: ST2Twov2s_POST >+/* 2878 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 2896 >+/* 2882 */ MCD_OPC_CheckPredicate, 0, 151, 147, // Skip to: 40669 >+/* 2886 */ MCD_OPC_CheckField, 21, 1, 0, 145, 147, // Skip to: 40669 >+/* 2892 */ MCD_OPC_Decode, 234, 13, 15, // Opcode: ST1Twov8b_POST >+/* 2896 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 2914 >+/* 2900 */ MCD_OPC_CheckPredicate, 0, 133, 147, // Skip to: 40669 >+/* 2904 */ MCD_OPC_CheckField, 21, 1, 0, 127, 147, // Skip to: 40669 >+/* 2910 */ MCD_OPC_Decode, 230, 13, 15, // Opcode: ST1Twov4h_POST >+/* 2914 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 2932 >+/* 2918 */ MCD_OPC_CheckPredicate, 0, 115, 147, // Skip to: 40669 >+/* 2922 */ MCD_OPC_CheckField, 21, 1, 0, 109, 147, // Skip to: 40669 >+/* 2928 */ MCD_OPC_Decode, 228, 13, 15, // Opcode: ST1Twov2s_POST >+/* 2932 */ MCD_OPC_FilterValue, 43, 101, 147, // Skip to: 40669 >+/* 2936 */ MCD_OPC_CheckPredicate, 0, 97, 147, // Skip to: 40669 >+/* 2940 */ MCD_OPC_CheckField, 21, 1, 0, 91, 147, // Skip to: 40669 >+/* 2946 */ MCD_OPC_Decode, 224, 13, 15, // Opcode: ST1Twov1d_POST >+/* 2950 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2958 >+/* 2954 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: STPSpost >+/* 2958 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 3469 >+/* 2962 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 2965 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2983 >+/* 2969 */ MCD_OPC_CheckPredicate, 0, 64, 147, // Skip to: 40669 >+/* 2973 */ MCD_OPC_CheckField, 21, 1, 0, 58, 147, // Skip to: 40669 >+/* 2979 */ MCD_OPC_Decode, 162, 14, 16, // Opcode: ST4Fourv16b_POST >+/* 2983 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3001 >+/* 2987 */ MCD_OPC_CheckPredicate, 0, 46, 147, // Skip to: 40669 >+/* 2991 */ MCD_OPC_CheckField, 21, 1, 0, 40, 147, // Skip to: 40669 >+/* 2997 */ MCD_OPC_Decode, 174, 14, 16, // Opcode: ST4Fourv8h_POST >+/* 3001 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3019 >+/* 3005 */ MCD_OPC_CheckPredicate, 0, 28, 147, // Skip to: 40669 >+/* 3009 */ MCD_OPC_CheckField, 21, 1, 0, 22, 147, // Skip to: 40669 >+/* 3015 */ MCD_OPC_Decode, 170, 14, 16, // Opcode: ST4Fourv4s_POST >+/* 3019 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3037 >+/* 3023 */ MCD_OPC_CheckPredicate, 0, 10, 147, // Skip to: 40669 >+/* 3027 */ MCD_OPC_CheckField, 21, 1, 0, 4, 147, // Skip to: 40669 >+/* 3033 */ MCD_OPC_Decode, 164, 14, 16, // Opcode: ST4Fourv2d_POST >+/* 3037 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3055 >+/* 3041 */ MCD_OPC_CheckPredicate, 0, 248, 146, // Skip to: 40669 >+/* 3045 */ MCD_OPC_CheckField, 21, 1, 0, 242, 146, // Skip to: 40669 >+/* 3051 */ MCD_OPC_Decode, 174, 13, 16, // Opcode: ST1Fourv16b_POST >+/* 3055 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3073 >+/* 3059 */ MCD_OPC_CheckPredicate, 0, 230, 146, // Skip to: 40669 >+/* 3063 */ MCD_OPC_CheckField, 21, 1, 0, 224, 146, // Skip to: 40669 >+/* 3069 */ MCD_OPC_Decode, 188, 13, 16, // Opcode: ST1Fourv8h_POST >+/* 3073 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3091 >+/* 3077 */ MCD_OPC_CheckPredicate, 0, 212, 146, // Skip to: 40669 >+/* 3081 */ MCD_OPC_CheckField, 21, 1, 0, 206, 146, // Skip to: 40669 >+/* 3087 */ MCD_OPC_Decode, 184, 13, 16, // Opcode: ST1Fourv4s_POST >+/* 3091 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3109 >+/* 3095 */ MCD_OPC_CheckPredicate, 0, 194, 146, // Skip to: 40669 >+/* 3099 */ MCD_OPC_CheckField, 21, 1, 0, 188, 146, // Skip to: 40669 >+/* 3105 */ MCD_OPC_Decode, 178, 13, 16, // Opcode: ST1Fourv2d_POST >+/* 3109 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3127 >+/* 3113 */ MCD_OPC_CheckPredicate, 0, 176, 146, // Skip to: 40669 >+/* 3117 */ MCD_OPC_CheckField, 21, 1, 0, 170, 146, // Skip to: 40669 >+/* 3123 */ MCD_OPC_Decode, 140, 14, 17, // Opcode: ST3Threev16b_POST >+/* 3127 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3145 >+/* 3131 */ MCD_OPC_CheckPredicate, 0, 158, 146, // Skip to: 40669 >+/* 3135 */ MCD_OPC_CheckField, 21, 1, 0, 152, 146, // Skip to: 40669 >+/* 3141 */ MCD_OPC_Decode, 152, 14, 17, // Opcode: ST3Threev8h_POST >+/* 3145 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3163 >+/* 3149 */ MCD_OPC_CheckPredicate, 0, 140, 146, // Skip to: 40669 >+/* 3153 */ MCD_OPC_CheckField, 21, 1, 0, 134, 146, // Skip to: 40669 >+/* 3159 */ MCD_OPC_Decode, 148, 14, 17, // Opcode: ST3Threev4s_POST >+/* 3163 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 3181 >+/* 3167 */ MCD_OPC_CheckPredicate, 0, 122, 146, // Skip to: 40669 >+/* 3171 */ MCD_OPC_CheckField, 21, 1, 0, 116, 146, // Skip to: 40669 >+/* 3177 */ MCD_OPC_Decode, 142, 14, 17, // Opcode: ST3Threev2d_POST >+/* 3181 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3199 >+/* 3185 */ MCD_OPC_CheckPredicate, 0, 104, 146, // Skip to: 40669 >+/* 3189 */ MCD_OPC_CheckField, 21, 1, 0, 98, 146, // Skip to: 40669 >+/* 3195 */ MCD_OPC_Decode, 206, 13, 17, // Opcode: ST1Threev16b_POST >+/* 3199 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3217 >+/* 3203 */ MCD_OPC_CheckPredicate, 0, 86, 146, // Skip to: 40669 >+/* 3207 */ MCD_OPC_CheckField, 21, 1, 0, 80, 146, // Skip to: 40669 >+/* 3213 */ MCD_OPC_Decode, 220, 13, 17, // Opcode: ST1Threev8h_POST >+/* 3217 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3235 >+/* 3221 */ MCD_OPC_CheckPredicate, 0, 68, 146, // Skip to: 40669 >+/* 3225 */ MCD_OPC_CheckField, 21, 1, 0, 62, 146, // Skip to: 40669 >+/* 3231 */ MCD_OPC_Decode, 216, 13, 17, // Opcode: ST1Threev4s_POST >+/* 3235 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3253 >+/* 3239 */ MCD_OPC_CheckPredicate, 0, 50, 146, // Skip to: 40669 >+/* 3243 */ MCD_OPC_CheckField, 21, 1, 0, 44, 146, // Skip to: 40669 >+/* 3249 */ MCD_OPC_Decode, 210, 13, 17, // Opcode: ST1Threev2d_POST >+/* 3253 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3271 >+/* 3257 */ MCD_OPC_CheckPredicate, 0, 32, 146, // Skip to: 40669 >+/* 3261 */ MCD_OPC_CheckField, 21, 1, 0, 26, 146, // Skip to: 40669 >+/* 3267 */ MCD_OPC_Decode, 190, 13, 18, // Opcode: ST1Onev16b_POST >+/* 3271 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3289 >+/* 3275 */ MCD_OPC_CheckPredicate, 0, 14, 146, // Skip to: 40669 >+/* 3279 */ MCD_OPC_CheckField, 21, 1, 0, 8, 146, // Skip to: 40669 >+/* 3285 */ MCD_OPC_Decode, 204, 13, 18, // Opcode: ST1Onev8h_POST >+/* 3289 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3307 >+/* 3293 */ MCD_OPC_CheckPredicate, 0, 252, 145, // Skip to: 40669 >+/* 3297 */ MCD_OPC_CheckField, 21, 1, 0, 246, 145, // Skip to: 40669 >+/* 3303 */ MCD_OPC_Decode, 200, 13, 18, // Opcode: ST1Onev4s_POST >+/* 3307 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3325 >+/* 3311 */ MCD_OPC_CheckPredicate, 0, 234, 145, // Skip to: 40669 >+/* 3315 */ MCD_OPC_CheckField, 21, 1, 0, 228, 145, // Skip to: 40669 >+/* 3321 */ MCD_OPC_Decode, 194, 13, 18, // Opcode: ST1Onev2d_POST >+/* 3325 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3343 >+/* 3329 */ MCD_OPC_CheckPredicate, 0, 216, 145, // Skip to: 40669 >+/* 3333 */ MCD_OPC_CheckField, 21, 1, 0, 210, 145, // Skip to: 40669 >+/* 3339 */ MCD_OPC_Decode, 246, 13, 19, // Opcode: ST2Twov16b_POST >+/* 3343 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3361 >+/* 3347 */ MCD_OPC_CheckPredicate, 0, 198, 145, // Skip to: 40669 >+/* 3351 */ MCD_OPC_CheckField, 21, 1, 0, 192, 145, // Skip to: 40669 >+/* 3357 */ MCD_OPC_Decode, 130, 14, 19, // Opcode: ST2Twov8h_POST >+/* 3361 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3379 >+/* 3365 */ MCD_OPC_CheckPredicate, 0, 180, 145, // Skip to: 40669 >+/* 3369 */ MCD_OPC_CheckField, 21, 1, 0, 174, 145, // Skip to: 40669 >+/* 3375 */ MCD_OPC_Decode, 254, 13, 19, // Opcode: ST2Twov4s_POST >+/* 3379 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 3397 >+/* 3383 */ MCD_OPC_CheckPredicate, 0, 162, 145, // Skip to: 40669 >+/* 3387 */ MCD_OPC_CheckField, 21, 1, 0, 156, 145, // Skip to: 40669 >+/* 3393 */ MCD_OPC_Decode, 248, 13, 19, // Opcode: ST2Twov2d_POST >+/* 3397 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3415 >+/* 3401 */ MCD_OPC_CheckPredicate, 0, 144, 145, // Skip to: 40669 >+/* 3405 */ MCD_OPC_CheckField, 21, 1, 0, 138, 145, // Skip to: 40669 >+/* 3411 */ MCD_OPC_Decode, 222, 13, 19, // Opcode: ST1Twov16b_POST >+/* 3415 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3433 >+/* 3419 */ MCD_OPC_CheckPredicate, 0, 126, 145, // Skip to: 40669 >+/* 3423 */ MCD_OPC_CheckField, 21, 1, 0, 120, 145, // Skip to: 40669 >+/* 3429 */ MCD_OPC_Decode, 236, 13, 19, // Opcode: ST1Twov8h_POST >+/* 3433 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3451 >+/* 3437 */ MCD_OPC_CheckPredicate, 0, 108, 145, // Skip to: 40669 >+/* 3441 */ MCD_OPC_CheckField, 21, 1, 0, 102, 145, // Skip to: 40669 >+/* 3447 */ MCD_OPC_Decode, 232, 13, 19, // Opcode: ST1Twov4s_POST >+/* 3451 */ MCD_OPC_FilterValue, 43, 94, 145, // Skip to: 40669 >+/* 3455 */ MCD_OPC_CheckPredicate, 0, 90, 145, // Skip to: 40669 >+/* 3459 */ MCD_OPC_CheckField, 21, 1, 0, 84, 145, // Skip to: 40669 >+/* 3465 */ MCD_OPC_Decode, 226, 13, 19, // Opcode: ST1Twov2d_POST >+/* 3469 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3477 >+/* 3473 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: STPDpost >+/* 3477 */ MCD_OPC_FilterValue, 5, 68, 145, // Skip to: 40669 >+/* 3481 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: STPQpost >+/* 3485 */ MCD_OPC_FilterValue, 3, 227, 3, // Skip to: 4484 >+/* 3489 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 3492 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 3949 >+/* 3496 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 3499 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3517 >+/* 3503 */ MCD_OPC_CheckPredicate, 0, 42, 145, // Skip to: 40669 >+/* 3507 */ MCD_OPC_CheckField, 21, 1, 0, 36, 145, // Skip to: 40669 >+/* 3513 */ MCD_OPC_Decode, 136, 7, 12, // Opcode: LD4Fourv8b_POST >+/* 3517 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3535 >+/* 3521 */ MCD_OPC_CheckPredicate, 0, 24, 145, // Skip to: 40669 >+/* 3525 */ MCD_OPC_CheckField, 21, 1, 0, 18, 145, // Skip to: 40669 >+/* 3531 */ MCD_OPC_Decode, 132, 7, 12, // Opcode: LD4Fourv4h_POST >+/* 3535 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3553 >+/* 3539 */ MCD_OPC_CheckPredicate, 0, 6, 145, // Skip to: 40669 >+/* 3543 */ MCD_OPC_CheckField, 21, 1, 0, 0, 145, // Skip to: 40669 >+/* 3549 */ MCD_OPC_Decode, 130, 7, 12, // Opcode: LD4Fourv2s_POST >+/* 3553 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3571 >+/* 3557 */ MCD_OPC_CheckPredicate, 0, 244, 144, // Skip to: 40669 >+/* 3561 */ MCD_OPC_CheckField, 21, 1, 0, 238, 144, // Skip to: 40669 >+/* 3567 */ MCD_OPC_Decode, 230, 5, 12, // Opcode: LD1Fourv8b_POST >+/* 3571 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3589 >+/* 3575 */ MCD_OPC_CheckPredicate, 0, 226, 144, // Skip to: 40669 >+/* 3579 */ MCD_OPC_CheckField, 21, 1, 0, 220, 144, // Skip to: 40669 >+/* 3585 */ MCD_OPC_Decode, 226, 5, 12, // Opcode: LD1Fourv4h_POST >+/* 3589 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3607 >+/* 3593 */ MCD_OPC_CheckPredicate, 0, 208, 144, // Skip to: 40669 >+/* 3597 */ MCD_OPC_CheckField, 21, 1, 0, 202, 144, // Skip to: 40669 >+/* 3603 */ MCD_OPC_Decode, 224, 5, 12, // Opcode: LD1Fourv2s_POST >+/* 3607 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3625 >+/* 3611 */ MCD_OPC_CheckPredicate, 0, 190, 144, // Skip to: 40669 >+/* 3615 */ MCD_OPC_CheckField, 21, 1, 0, 184, 144, // Skip to: 40669 >+/* 3621 */ MCD_OPC_Decode, 220, 5, 12, // Opcode: LD1Fourv1d_POST >+/* 3625 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3643 >+/* 3629 */ MCD_OPC_CheckPredicate, 0, 172, 144, // Skip to: 40669 >+/* 3633 */ MCD_OPC_CheckField, 21, 1, 0, 166, 144, // Skip to: 40669 >+/* 3639 */ MCD_OPC_Decode, 242, 6, 13, // Opcode: LD3Threev8b_POST >+/* 3643 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3661 >+/* 3647 */ MCD_OPC_CheckPredicate, 0, 154, 144, // Skip to: 40669 >+/* 3651 */ MCD_OPC_CheckField, 21, 1, 0, 148, 144, // Skip to: 40669 >+/* 3657 */ MCD_OPC_Decode, 238, 6, 13, // Opcode: LD3Threev4h_POST >+/* 3661 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3679 >+/* 3665 */ MCD_OPC_CheckPredicate, 0, 136, 144, // Skip to: 40669 >+/* 3669 */ MCD_OPC_CheckField, 21, 1, 0, 130, 144, // Skip to: 40669 >+/* 3675 */ MCD_OPC_Decode, 236, 6, 13, // Opcode: LD3Threev2s_POST >+/* 3679 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3697 >+/* 3683 */ MCD_OPC_CheckPredicate, 0, 118, 144, // Skip to: 40669 >+/* 3687 */ MCD_OPC_CheckField, 21, 1, 0, 112, 144, // Skip to: 40669 >+/* 3693 */ MCD_OPC_Decode, 150, 6, 13, // Opcode: LD1Threev8b_POST >+/* 3697 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3715 >+/* 3701 */ MCD_OPC_CheckPredicate, 0, 100, 144, // Skip to: 40669 >+/* 3705 */ MCD_OPC_CheckField, 21, 1, 0, 94, 144, // Skip to: 40669 >+/* 3711 */ MCD_OPC_Decode, 146, 6, 13, // Opcode: LD1Threev4h_POST >+/* 3715 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3733 >+/* 3719 */ MCD_OPC_CheckPredicate, 0, 82, 144, // Skip to: 40669 >+/* 3723 */ MCD_OPC_CheckField, 21, 1, 0, 76, 144, // Skip to: 40669 >+/* 3729 */ MCD_OPC_Decode, 144, 6, 13, // Opcode: LD1Threev2s_POST >+/* 3733 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3751 >+/* 3737 */ MCD_OPC_CheckPredicate, 0, 64, 144, // Skip to: 40669 >+/* 3741 */ MCD_OPC_CheckField, 21, 1, 0, 58, 144, // Skip to: 40669 >+/* 3747 */ MCD_OPC_Decode, 140, 6, 13, // Opcode: LD1Threev1d_POST >+/* 3751 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3769 >+/* 3755 */ MCD_OPC_CheckPredicate, 0, 46, 144, // Skip to: 40669 >+/* 3759 */ MCD_OPC_CheckField, 21, 1, 0, 40, 144, // Skip to: 40669 >+/* 3765 */ MCD_OPC_Decode, 246, 5, 14, // Opcode: LD1Onev8b_POST >+/* 3769 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3787 >+/* 3773 */ MCD_OPC_CheckPredicate, 0, 28, 144, // Skip to: 40669 >+/* 3777 */ MCD_OPC_CheckField, 21, 1, 0, 22, 144, // Skip to: 40669 >+/* 3783 */ MCD_OPC_Decode, 242, 5, 14, // Opcode: LD1Onev4h_POST >+/* 3787 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3805 >+/* 3791 */ MCD_OPC_CheckPredicate, 0, 10, 144, // Skip to: 40669 >+/* 3795 */ MCD_OPC_CheckField, 21, 1, 0, 4, 144, // Skip to: 40669 >+/* 3801 */ MCD_OPC_Decode, 240, 5, 14, // Opcode: LD1Onev2s_POST >+/* 3805 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3823 >+/* 3809 */ MCD_OPC_CheckPredicate, 0, 248, 143, // Skip to: 40669 >+/* 3813 */ MCD_OPC_CheckField, 21, 1, 0, 242, 143, // Skip to: 40669 >+/* 3819 */ MCD_OPC_Decode, 236, 5, 14, // Opcode: LD1Onev1d_POST >+/* 3823 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3841 >+/* 3827 */ MCD_OPC_CheckPredicate, 0, 230, 143, // Skip to: 40669 >+/* 3831 */ MCD_OPC_CheckField, 21, 1, 0, 224, 143, // Skip to: 40669 >+/* 3837 */ MCD_OPC_Decode, 204, 6, 15, // Opcode: LD2Twov8b_POST >+/* 3841 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3859 >+/* 3845 */ MCD_OPC_CheckPredicate, 0, 212, 143, // Skip to: 40669 >+/* 3849 */ MCD_OPC_CheckField, 21, 1, 0, 206, 143, // Skip to: 40669 >+/* 3855 */ MCD_OPC_Decode, 200, 6, 15, // Opcode: LD2Twov4h_POST >+/* 3859 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3877 >+/* 3863 */ MCD_OPC_CheckPredicate, 0, 194, 143, // Skip to: 40669 >+/* 3867 */ MCD_OPC_CheckField, 21, 1, 0, 188, 143, // Skip to: 40669 >+/* 3873 */ MCD_OPC_Decode, 198, 6, 15, // Opcode: LD2Twov2s_POST >+/* 3877 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3895 >+/* 3881 */ MCD_OPC_CheckPredicate, 0, 176, 143, // Skip to: 40669 >+/* 3885 */ MCD_OPC_CheckField, 21, 1, 0, 170, 143, // Skip to: 40669 >+/* 3891 */ MCD_OPC_Decode, 166, 6, 15, // Opcode: LD1Twov8b_POST >+/* 3895 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3913 >+/* 3899 */ MCD_OPC_CheckPredicate, 0, 158, 143, // Skip to: 40669 >+/* 3903 */ MCD_OPC_CheckField, 21, 1, 0, 152, 143, // Skip to: 40669 >+/* 3909 */ MCD_OPC_Decode, 162, 6, 15, // Opcode: LD1Twov4h_POST >+/* 3913 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3931 >+/* 3917 */ MCD_OPC_CheckPredicate, 0, 140, 143, // Skip to: 40669 >+/* 3921 */ MCD_OPC_CheckField, 21, 1, 0, 134, 143, // Skip to: 40669 >+/* 3927 */ MCD_OPC_Decode, 160, 6, 15, // Opcode: LD1Twov2s_POST >+/* 3931 */ MCD_OPC_FilterValue, 43, 126, 143, // Skip to: 40669 >+/* 3935 */ MCD_OPC_CheckPredicate, 0, 122, 143, // Skip to: 40669 >+/* 3939 */ MCD_OPC_CheckField, 21, 1, 0, 116, 143, // Skip to: 40669 >+/* 3945 */ MCD_OPC_Decode, 156, 6, 15, // Opcode: LD1Twov1d_POST >+/* 3949 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3957 >+/* 3953 */ MCD_OPC_Decode, 188, 7, 3, // Opcode: LDPSpost >+/* 3957 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 4468 >+/* 3961 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 3964 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3982 >+/* 3968 */ MCD_OPC_CheckPredicate, 0, 89, 143, // Skip to: 40669 >+/* 3972 */ MCD_OPC_CheckField, 21, 1, 0, 83, 143, // Skip to: 40669 >+/* 3978 */ MCD_OPC_Decode, 254, 6, 16, // Opcode: LD4Fourv16b_POST >+/* 3982 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4000 >+/* 3986 */ MCD_OPC_CheckPredicate, 0, 71, 143, // Skip to: 40669 >+/* 3990 */ MCD_OPC_CheckField, 21, 1, 0, 65, 143, // Skip to: 40669 >+/* 3996 */ MCD_OPC_Decode, 138, 7, 16, // Opcode: LD4Fourv8h_POST >+/* 4000 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 4018 >+/* 4004 */ MCD_OPC_CheckPredicate, 0, 53, 143, // Skip to: 40669 >+/* 4008 */ MCD_OPC_CheckField, 21, 1, 0, 47, 143, // Skip to: 40669 >+/* 4014 */ MCD_OPC_Decode, 134, 7, 16, // Opcode: LD4Fourv4s_POST >+/* 4018 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 4036 >+/* 4022 */ MCD_OPC_CheckPredicate, 0, 35, 143, // Skip to: 40669 >+/* 4026 */ MCD_OPC_CheckField, 21, 1, 0, 29, 143, // Skip to: 40669 >+/* 4032 */ MCD_OPC_Decode, 128, 7, 16, // Opcode: LD4Fourv2d_POST >+/* 4036 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 4054 >+/* 4040 */ MCD_OPC_CheckPredicate, 0, 17, 143, // Skip to: 40669 >+/* 4044 */ MCD_OPC_CheckField, 21, 1, 0, 11, 143, // Skip to: 40669 >+/* 4050 */ MCD_OPC_Decode, 218, 5, 16, // Opcode: LD1Fourv16b_POST >+/* 4054 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 4072 >+/* 4058 */ MCD_OPC_CheckPredicate, 0, 255, 142, // Skip to: 40669 >+/* 4062 */ MCD_OPC_CheckField, 21, 1, 0, 249, 142, // Skip to: 40669 >+/* 4068 */ MCD_OPC_Decode, 232, 5, 16, // Opcode: LD1Fourv8h_POST >+/* 4072 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 4090 >+/* 4076 */ MCD_OPC_CheckPredicate, 0, 237, 142, // Skip to: 40669 >+/* 4080 */ MCD_OPC_CheckField, 21, 1, 0, 231, 142, // Skip to: 40669 >+/* 4086 */ MCD_OPC_Decode, 228, 5, 16, // Opcode: LD1Fourv4s_POST >+/* 4090 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 4108 >+/* 4094 */ MCD_OPC_CheckPredicate, 0, 219, 142, // Skip to: 40669 >+/* 4098 */ MCD_OPC_CheckField, 21, 1, 0, 213, 142, // Skip to: 40669 >+/* 4104 */ MCD_OPC_Decode, 222, 5, 16, // Opcode: LD1Fourv2d_POST >+/* 4108 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 4126 >+/* 4112 */ MCD_OPC_CheckPredicate, 0, 201, 142, // Skip to: 40669 >+/* 4116 */ MCD_OPC_CheckField, 21, 1, 0, 195, 142, // Skip to: 40669 >+/* 4122 */ MCD_OPC_Decode, 232, 6, 17, // Opcode: LD3Threev16b_POST >+/* 4126 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 4144 >+/* 4130 */ MCD_OPC_CheckPredicate, 0, 183, 142, // Skip to: 40669 >+/* 4134 */ MCD_OPC_CheckField, 21, 1, 0, 177, 142, // Skip to: 40669 >+/* 4140 */ MCD_OPC_Decode, 244, 6, 17, // Opcode: LD3Threev8h_POST >+/* 4144 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 4162 >+/* 4148 */ MCD_OPC_CheckPredicate, 0, 165, 142, // Skip to: 40669 >+/* 4152 */ MCD_OPC_CheckField, 21, 1, 0, 159, 142, // Skip to: 40669 >+/* 4158 */ MCD_OPC_Decode, 240, 6, 17, // Opcode: LD3Threev4s_POST >+/* 4162 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 4180 >+/* 4166 */ MCD_OPC_CheckPredicate, 0, 147, 142, // Skip to: 40669 >+/* 4170 */ MCD_OPC_CheckField, 21, 1, 0, 141, 142, // Skip to: 40669 >+/* 4176 */ MCD_OPC_Decode, 234, 6, 17, // Opcode: LD3Threev2d_POST >+/* 4180 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 4198 >+/* 4184 */ MCD_OPC_CheckPredicate, 0, 129, 142, // Skip to: 40669 >+/* 4188 */ MCD_OPC_CheckField, 21, 1, 0, 123, 142, // Skip to: 40669 >+/* 4194 */ MCD_OPC_Decode, 138, 6, 17, // Opcode: LD1Threev16b_POST >+/* 4198 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 4216 >+/* 4202 */ MCD_OPC_CheckPredicate, 0, 111, 142, // Skip to: 40669 >+/* 4206 */ MCD_OPC_CheckField, 21, 1, 0, 105, 142, // Skip to: 40669 >+/* 4212 */ MCD_OPC_Decode, 152, 6, 17, // Opcode: LD1Threev8h_POST >+/* 4216 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 4234 >+/* 4220 */ MCD_OPC_CheckPredicate, 0, 93, 142, // Skip to: 40669 >+/* 4224 */ MCD_OPC_CheckField, 21, 1, 0, 87, 142, // Skip to: 40669 >+/* 4230 */ MCD_OPC_Decode, 148, 6, 17, // Opcode: LD1Threev4s_POST >+/* 4234 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 4252 >+/* 4238 */ MCD_OPC_CheckPredicate, 0, 75, 142, // Skip to: 40669 >+/* 4242 */ MCD_OPC_CheckField, 21, 1, 0, 69, 142, // Skip to: 40669 >+/* 4248 */ MCD_OPC_Decode, 142, 6, 17, // Opcode: LD1Threev2d_POST >+/* 4252 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 4270 >+/* 4256 */ MCD_OPC_CheckPredicate, 0, 57, 142, // Skip to: 40669 >+/* 4260 */ MCD_OPC_CheckField, 21, 1, 0, 51, 142, // Skip to: 40669 >+/* 4266 */ MCD_OPC_Decode, 234, 5, 18, // Opcode: LD1Onev16b_POST >+/* 4270 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 4288 >+/* 4274 */ MCD_OPC_CheckPredicate, 0, 39, 142, // Skip to: 40669 >+/* 4278 */ MCD_OPC_CheckField, 21, 1, 0, 33, 142, // Skip to: 40669 >+/* 4284 */ MCD_OPC_Decode, 248, 5, 18, // Opcode: LD1Onev8h_POST >+/* 4288 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 4306 >+/* 4292 */ MCD_OPC_CheckPredicate, 0, 21, 142, // Skip to: 40669 >+/* 4296 */ MCD_OPC_CheckField, 21, 1, 0, 15, 142, // Skip to: 40669 >+/* 4302 */ MCD_OPC_Decode, 244, 5, 18, // Opcode: LD1Onev4s_POST >+/* 4306 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 4324 >+/* 4310 */ MCD_OPC_CheckPredicate, 0, 3, 142, // Skip to: 40669 >+/* 4314 */ MCD_OPC_CheckField, 21, 1, 0, 253, 141, // Skip to: 40669 >+/* 4320 */ MCD_OPC_Decode, 238, 5, 18, // Opcode: LD1Onev2d_POST >+/* 4324 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 4342 >+/* 4328 */ MCD_OPC_CheckPredicate, 0, 241, 141, // Skip to: 40669 >+/* 4332 */ MCD_OPC_CheckField, 21, 1, 0, 235, 141, // Skip to: 40669 >+/* 4338 */ MCD_OPC_Decode, 194, 6, 19, // Opcode: LD2Twov16b_POST >+/* 4342 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 4360 >+/* 4346 */ MCD_OPC_CheckPredicate, 0, 223, 141, // Skip to: 40669 >+/* 4350 */ MCD_OPC_CheckField, 21, 1, 0, 217, 141, // Skip to: 40669 >+/* 4356 */ MCD_OPC_Decode, 206, 6, 19, // Opcode: LD2Twov8h_POST >+/* 4360 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 4378 >+/* 4364 */ MCD_OPC_CheckPredicate, 0, 205, 141, // Skip to: 40669 >+/* 4368 */ MCD_OPC_CheckField, 21, 1, 0, 199, 141, // Skip to: 40669 >+/* 4374 */ MCD_OPC_Decode, 202, 6, 19, // Opcode: LD2Twov4s_POST >+/* 4378 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 4396 >+/* 4382 */ MCD_OPC_CheckPredicate, 0, 187, 141, // Skip to: 40669 >+/* 4386 */ MCD_OPC_CheckField, 21, 1, 0, 181, 141, // Skip to: 40669 >+/* 4392 */ MCD_OPC_Decode, 196, 6, 19, // Opcode: LD2Twov2d_POST >+/* 4396 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 4414 >+/* 4400 */ MCD_OPC_CheckPredicate, 0, 169, 141, // Skip to: 40669 >+/* 4404 */ MCD_OPC_CheckField, 21, 1, 0, 163, 141, // Skip to: 40669 >+/* 4410 */ MCD_OPC_Decode, 154, 6, 19, // Opcode: LD1Twov16b_POST >+/* 4414 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 4432 >+/* 4418 */ MCD_OPC_CheckPredicate, 0, 151, 141, // Skip to: 40669 >+/* 4422 */ MCD_OPC_CheckField, 21, 1, 0, 145, 141, // Skip to: 40669 >+/* 4428 */ MCD_OPC_Decode, 168, 6, 19, // Opcode: LD1Twov8h_POST >+/* 4432 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 4450 >+/* 4436 */ MCD_OPC_CheckPredicate, 0, 133, 141, // Skip to: 40669 >+/* 4440 */ MCD_OPC_CheckField, 21, 1, 0, 127, 141, // Skip to: 40669 >+/* 4446 */ MCD_OPC_Decode, 164, 6, 19, // Opcode: LD1Twov4s_POST >+/* 4450 */ MCD_OPC_FilterValue, 43, 119, 141, // Skip to: 40669 >+/* 4454 */ MCD_OPC_CheckPredicate, 0, 115, 141, // Skip to: 40669 >+/* 4458 */ MCD_OPC_CheckField, 21, 1, 0, 109, 141, // Skip to: 40669 >+/* 4464 */ MCD_OPC_Decode, 158, 6, 19, // Opcode: LD1Twov2d_POST >+/* 4468 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 4476 >+/* 4472 */ MCD_OPC_Decode, 179, 7, 3, // Opcode: LDPDpost >+/* 4476 */ MCD_OPC_FilterValue, 5, 93, 141, // Skip to: 40669 >+/* 4480 */ MCD_OPC_Decode, 182, 7, 3, // Opcode: LDPQpost >+/* 4484 */ MCD_OPC_FilterValue, 4, 155, 1, // Skip to: 4899 >+/* 4488 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... >+/* 4491 */ MCD_OPC_FilterValue, 0, 117, 1, // Skip to: 4868 >+/* 4495 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... >+/* 4498 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4516 >+/* 4502 */ MCD_OPC_CheckPredicate, 0, 67, 141, // Skip to: 40669 >+/* 4506 */ MCD_OPC_CheckField, 31, 1, 0, 61, 141, // Skip to: 40669 >+/* 4512 */ MCD_OPC_Decode, 243, 13, 20, // Opcode: ST1i8 >+/* 4516 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4534 >+/* 4520 */ MCD_OPC_CheckPredicate, 0, 49, 141, // Skip to: 40669 >+/* 4524 */ MCD_OPC_CheckField, 31, 1, 0, 43, 141, // Skip to: 40669 >+/* 4530 */ MCD_OPC_Decode, 159, 14, 21, // Opcode: ST3i8 >+/* 4534 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4558 >+/* 4538 */ MCD_OPC_CheckPredicate, 0, 31, 141, // Skip to: 40669 >+/* 4542 */ MCD_OPC_CheckField, 31, 1, 0, 25, 141, // Skip to: 40669 >+/* 4548 */ MCD_OPC_CheckField, 10, 1, 0, 19, 141, // Skip to: 40669 >+/* 4554 */ MCD_OPC_Decode, 237, 13, 22, // Opcode: ST1i16 >+/* 4558 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4582 >+/* 4562 */ MCD_OPC_CheckPredicate, 0, 7, 141, // Skip to: 40669 >+/* 4566 */ MCD_OPC_CheckField, 31, 1, 0, 1, 141, // Skip to: 40669 >+/* 4572 */ MCD_OPC_CheckField, 10, 1, 0, 251, 140, // Skip to: 40669 >+/* 4578 */ MCD_OPC_Decode, 153, 14, 23, // Opcode: ST3i16 >+/* 4582 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 4631 >+/* 4586 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4589 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4607 >+/* 4593 */ MCD_OPC_CheckPredicate, 0, 232, 140, // Skip to: 40669 >+/* 4597 */ MCD_OPC_CheckField, 31, 1, 0, 226, 140, // Skip to: 40669 >+/* 4603 */ MCD_OPC_Decode, 239, 13, 24, // Opcode: ST1i32 >+/* 4607 */ MCD_OPC_FilterValue, 1, 218, 140, // Skip to: 40669 >+/* 4611 */ MCD_OPC_CheckPredicate, 0, 214, 140, // Skip to: 40669 >+/* 4615 */ MCD_OPC_CheckField, 31, 1, 0, 208, 140, // Skip to: 40669 >+/* 4621 */ MCD_OPC_CheckField, 12, 1, 0, 202, 140, // Skip to: 40669 >+/* 4627 */ MCD_OPC_Decode, 241, 13, 25, // Opcode: ST1i64 >+/* 4631 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 4680 >+/* 4635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4638 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4656 >+/* 4642 */ MCD_OPC_CheckPredicate, 0, 183, 140, // Skip to: 40669 >+/* 4646 */ MCD_OPC_CheckField, 31, 1, 0, 177, 140, // Skip to: 40669 >+/* 4652 */ MCD_OPC_Decode, 155, 14, 26, // Opcode: ST3i32 >+/* 4656 */ MCD_OPC_FilterValue, 1, 169, 140, // Skip to: 40669 >+/* 4660 */ MCD_OPC_CheckPredicate, 0, 165, 140, // Skip to: 40669 >+/* 4664 */ MCD_OPC_CheckField, 31, 1, 0, 159, 140, // Skip to: 40669 >+/* 4670 */ MCD_OPC_CheckField, 12, 1, 0, 153, 140, // Skip to: 40669 >+/* 4676 */ MCD_OPC_Decode, 157, 14, 27, // Opcode: ST3i64 >+/* 4680 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 4699 >+/* 4685 */ MCD_OPC_CheckPredicate, 0, 140, 140, // Skip to: 40669 >+/* 4689 */ MCD_OPC_CheckField, 31, 1, 0, 134, 140, // Skip to: 40669 >+/* 4695 */ MCD_OPC_Decode, 137, 14, 28, // Opcode: ST2i8 >+/* 4699 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 4718 >+/* 4704 */ MCD_OPC_CheckPredicate, 0, 121, 140, // Skip to: 40669 >+/* 4708 */ MCD_OPC_CheckField, 31, 1, 0, 115, 140, // Skip to: 40669 >+/* 4714 */ MCD_OPC_Decode, 181, 14, 29, // Opcode: ST4i8 >+/* 4718 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 4743 >+/* 4723 */ MCD_OPC_CheckPredicate, 0, 102, 140, // Skip to: 40669 >+/* 4727 */ MCD_OPC_CheckField, 31, 1, 0, 96, 140, // Skip to: 40669 >+/* 4733 */ MCD_OPC_CheckField, 10, 1, 0, 90, 140, // Skip to: 40669 >+/* 4739 */ MCD_OPC_Decode, 131, 14, 30, // Opcode: ST2i16 >+/* 4743 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 4768 >+/* 4748 */ MCD_OPC_CheckPredicate, 0, 77, 140, // Skip to: 40669 >+/* 4752 */ MCD_OPC_CheckField, 31, 1, 0, 71, 140, // Skip to: 40669 >+/* 4758 */ MCD_OPC_CheckField, 10, 1, 0, 65, 140, // Skip to: 40669 >+/* 4764 */ MCD_OPC_Decode, 175, 14, 31, // Opcode: ST4i16 >+/* 4768 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 4818 >+/* 4773 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4776 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4794 >+/* 4780 */ MCD_OPC_CheckPredicate, 0, 45, 140, // Skip to: 40669 >+/* 4784 */ MCD_OPC_CheckField, 31, 1, 0, 39, 140, // Skip to: 40669 >+/* 4790 */ MCD_OPC_Decode, 133, 14, 32, // Opcode: ST2i32 >+/* 4794 */ MCD_OPC_FilterValue, 1, 31, 140, // Skip to: 40669 >+/* 4798 */ MCD_OPC_CheckPredicate, 0, 27, 140, // Skip to: 40669 >+/* 4802 */ MCD_OPC_CheckField, 31, 1, 0, 21, 140, // Skip to: 40669 >+/* 4808 */ MCD_OPC_CheckField, 12, 1, 0, 15, 140, // Skip to: 40669 >+/* 4814 */ MCD_OPC_Decode, 135, 14, 33, // Opcode: ST2i64 >+/* 4818 */ MCD_OPC_FilterValue, 133, 2, 6, 140, // Skip to: 40669 >+/* 4823 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4826 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4844 >+/* 4830 */ MCD_OPC_CheckPredicate, 0, 251, 139, // Skip to: 40669 >+/* 4834 */ MCD_OPC_CheckField, 31, 1, 0, 245, 139, // Skip to: 40669 >+/* 4840 */ MCD_OPC_Decode, 177, 14, 34, // Opcode: ST4i32 >+/* 4844 */ MCD_OPC_FilterValue, 1, 237, 139, // Skip to: 40669 >+/* 4848 */ MCD_OPC_CheckPredicate, 0, 233, 139, // Skip to: 40669 >+/* 4852 */ MCD_OPC_CheckField, 31, 1, 0, 227, 139, // Skip to: 40669 >+/* 4858 */ MCD_OPC_CheckField, 12, 1, 0, 221, 139, // Skip to: 40669 >+/* 4864 */ MCD_OPC_Decode, 179, 14, 35, // Opcode: ST4i64 >+/* 4868 */ MCD_OPC_FilterValue, 1, 213, 139, // Skip to: 40669 >+/* 4872 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 4875 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 4883 >+/* 4879 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: STPSi >+/* 4883 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 4891 >+/* 4887 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: STPDi >+/* 4891 */ MCD_OPC_FilterValue, 2, 190, 139, // Skip to: 40669 >+/* 4895 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: STPQi >+/* 4899 */ MCD_OPC_FilterValue, 5, 169, 3, // Skip to: 5840 >+/* 4903 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... >+/* 4906 */ MCD_OPC_FilterValue, 0, 131, 3, // Skip to: 5809 >+/* 4910 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... >+/* 4913 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4931 >+/* 4917 */ MCD_OPC_CheckPredicate, 0, 164, 139, // Skip to: 40669 >+/* 4921 */ MCD_OPC_CheckField, 31, 1, 0, 158, 139, // Skip to: 40669 >+/* 4927 */ MCD_OPC_Decode, 175, 6, 36, // Opcode: LD1i8 >+/* 4931 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4949 >+/* 4935 */ MCD_OPC_CheckPredicate, 0, 146, 139, // Skip to: 40669 >+/* 4939 */ MCD_OPC_CheckField, 31, 1, 0, 140, 139, // Skip to: 40669 >+/* 4945 */ MCD_OPC_Decode, 251, 6, 37, // Opcode: LD3i8 >+/* 4949 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4973 >+/* 4953 */ MCD_OPC_CheckPredicate, 0, 128, 139, // Skip to: 40669 >+/* 4957 */ MCD_OPC_CheckField, 31, 1, 0, 122, 139, // Skip to: 40669 >+/* 4963 */ MCD_OPC_CheckField, 10, 1, 0, 116, 139, // Skip to: 40669 >+/* 4969 */ MCD_OPC_Decode, 169, 6, 38, // Opcode: LD1i16 >+/* 4973 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4997 >+/* 4977 */ MCD_OPC_CheckPredicate, 0, 104, 139, // Skip to: 40669 >+/* 4981 */ MCD_OPC_CheckField, 31, 1, 0, 98, 139, // Skip to: 40669 >+/* 4987 */ MCD_OPC_CheckField, 10, 1, 0, 92, 139, // Skip to: 40669 >+/* 4993 */ MCD_OPC_Decode, 245, 6, 39, // Opcode: LD3i16 >+/* 4997 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 5046 >+/* 5001 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 5004 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5022 >+/* 5008 */ MCD_OPC_CheckPredicate, 0, 73, 139, // Skip to: 40669 >+/* 5012 */ MCD_OPC_CheckField, 31, 1, 0, 67, 139, // Skip to: 40669 >+/* 5018 */ MCD_OPC_Decode, 171, 6, 40, // Opcode: LD1i32 >+/* 5022 */ MCD_OPC_FilterValue, 1, 59, 139, // Skip to: 40669 >+/* 5026 */ MCD_OPC_CheckPredicate, 0, 55, 139, // Skip to: 40669 >+/* 5030 */ MCD_OPC_CheckField, 31, 1, 0, 49, 139, // Skip to: 40669 >+/* 5036 */ MCD_OPC_CheckField, 12, 1, 0, 43, 139, // Skip to: 40669 >+/* 5042 */ MCD_OPC_Decode, 173, 6, 41, // Opcode: LD1i64 >+/* 5046 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 5095 >+/* 5050 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 5053 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5071 >+/* 5057 */ MCD_OPC_CheckPredicate, 0, 24, 139, // Skip to: 40669 >+/* 5061 */ MCD_OPC_CheckField, 31, 1, 0, 18, 139, // Skip to: 40669 >+/* 5067 */ MCD_OPC_Decode, 247, 6, 42, // Opcode: LD3i32 >+/* 5071 */ MCD_OPC_FilterValue, 1, 10, 139, // Skip to: 40669 >+/* 5075 */ MCD_OPC_CheckPredicate, 0, 6, 139, // Skip to: 40669 >+/* 5079 */ MCD_OPC_CheckField, 31, 1, 0, 0, 139, // Skip to: 40669 >+/* 5085 */ MCD_OPC_CheckField, 12, 1, 0, 250, 138, // Skip to: 40669 >+/* 5091 */ MCD_OPC_Decode, 249, 6, 43, // Opcode: LD3i64 >+/* 5095 */ MCD_OPC_FilterValue, 6, 127, 0, // Skip to: 5226 >+/* 5099 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 5102 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5133 >+/* 5106 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5109 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5121 >+/* 5113 */ MCD_OPC_CheckPredicate, 0, 224, 138, // Skip to: 40669 >+/* 5117 */ MCD_OPC_Decode, 133, 6, 6, // Opcode: LD1Rv8b >+/* 5121 */ MCD_OPC_FilterValue, 1, 216, 138, // Skip to: 40669 >+/* 5125 */ MCD_OPC_CheckPredicate, 0, 212, 138, // Skip to: 40669 >+/* 5129 */ MCD_OPC_Decode, 249, 5, 10, // Opcode: LD1Rv16b >+/* 5133 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5164 >+/* 5137 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5140 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5152 >+/* 5144 */ MCD_OPC_CheckPredicate, 0, 193, 138, // Skip to: 40669 >+/* 5148 */ MCD_OPC_Decode, 129, 6, 6, // Opcode: LD1Rv4h >+/* 5152 */ MCD_OPC_FilterValue, 1, 185, 138, // Skip to: 40669 >+/* 5156 */ MCD_OPC_CheckPredicate, 0, 181, 138, // Skip to: 40669 >+/* 5160 */ MCD_OPC_Decode, 135, 6, 10, // Opcode: LD1Rv8h >+/* 5164 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5195 >+/* 5168 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5183 >+/* 5175 */ MCD_OPC_CheckPredicate, 0, 162, 138, // Skip to: 40669 >+/* 5179 */ MCD_OPC_Decode, 255, 5, 6, // Opcode: LD1Rv2s >+/* 5183 */ MCD_OPC_FilterValue, 1, 154, 138, // Skip to: 40669 >+/* 5187 */ MCD_OPC_CheckPredicate, 0, 150, 138, // Skip to: 40669 >+/* 5191 */ MCD_OPC_Decode, 131, 6, 10, // Opcode: LD1Rv4s >+/* 5195 */ MCD_OPC_FilterValue, 3, 142, 138, // Skip to: 40669 >+/* 5199 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5202 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5214 >+/* 5206 */ MCD_OPC_CheckPredicate, 0, 131, 138, // Skip to: 40669 >+/* 5210 */ MCD_OPC_Decode, 251, 5, 6, // Opcode: LD1Rv1d >+/* 5214 */ MCD_OPC_FilterValue, 1, 123, 138, // Skip to: 40669 >+/* 5218 */ MCD_OPC_CheckPredicate, 0, 119, 138, // Skip to: 40669 >+/* 5222 */ MCD_OPC_Decode, 253, 5, 10, // Opcode: LD1Rv2d >+/* 5226 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 5357 >+/* 5230 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 5233 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5264 >+/* 5237 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5240 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5252 >+/* 5244 */ MCD_OPC_CheckPredicate, 0, 93, 138, // Skip to: 40669 >+/* 5248 */ MCD_OPC_Decode, 227, 6, 5, // Opcode: LD3Rv8b >+/* 5252 */ MCD_OPC_FilterValue, 1, 85, 138, // Skip to: 40669 >+/* 5256 */ MCD_OPC_CheckPredicate, 0, 81, 138, // Skip to: 40669 >+/* 5260 */ MCD_OPC_Decode, 215, 6, 9, // Opcode: LD3Rv16b >+/* 5264 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5295 >+/* 5268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5271 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5283 >+/* 5275 */ MCD_OPC_CheckPredicate, 0, 62, 138, // Skip to: 40669 >+/* 5279 */ MCD_OPC_Decode, 223, 6, 5, // Opcode: LD3Rv4h >+/* 5283 */ MCD_OPC_FilterValue, 1, 54, 138, // Skip to: 40669 >+/* 5287 */ MCD_OPC_CheckPredicate, 0, 50, 138, // Skip to: 40669 >+/* 5291 */ MCD_OPC_Decode, 229, 6, 9, // Opcode: LD3Rv8h >+/* 5295 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5326 >+/* 5299 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5302 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5314 >+/* 5306 */ MCD_OPC_CheckPredicate, 0, 31, 138, // Skip to: 40669 >+/* 5310 */ MCD_OPC_Decode, 221, 6, 5, // Opcode: LD3Rv2s >+/* 5314 */ MCD_OPC_FilterValue, 1, 23, 138, // Skip to: 40669 >+/* 5318 */ MCD_OPC_CheckPredicate, 0, 19, 138, // Skip to: 40669 >+/* 5322 */ MCD_OPC_Decode, 225, 6, 9, // Opcode: LD3Rv4s >+/* 5326 */ MCD_OPC_FilterValue, 3, 11, 138, // Skip to: 40669 >+/* 5330 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5345 >+/* 5337 */ MCD_OPC_CheckPredicate, 0, 0, 138, // Skip to: 40669 >+/* 5341 */ MCD_OPC_Decode, 217, 6, 5, // Opcode: LD3Rv1d >+/* 5345 */ MCD_OPC_FilterValue, 1, 248, 137, // Skip to: 40669 >+/* 5349 */ MCD_OPC_CheckPredicate, 0, 244, 137, // Skip to: 40669 >+/* 5353 */ MCD_OPC_Decode, 219, 6, 9, // Opcode: LD3Rv2d >+/* 5357 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 5376 >+/* 5362 */ MCD_OPC_CheckPredicate, 0, 231, 137, // Skip to: 40669 >+/* 5366 */ MCD_OPC_CheckField, 31, 1, 0, 225, 137, // Skip to: 40669 >+/* 5372 */ MCD_OPC_Decode, 213, 6, 44, // Opcode: LD2i8 >+/* 5376 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 5395 >+/* 5381 */ MCD_OPC_CheckPredicate, 0, 212, 137, // Skip to: 40669 >+/* 5385 */ MCD_OPC_CheckField, 31, 1, 0, 206, 137, // Skip to: 40669 >+/* 5391 */ MCD_OPC_Decode, 161, 7, 45, // Opcode: LD4i8 >+/* 5395 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 5420 >+/* 5400 */ MCD_OPC_CheckPredicate, 0, 193, 137, // Skip to: 40669 >+/* 5404 */ MCD_OPC_CheckField, 31, 1, 0, 187, 137, // Skip to: 40669 >+/* 5410 */ MCD_OPC_CheckField, 10, 1, 0, 181, 137, // Skip to: 40669 >+/* 5416 */ MCD_OPC_Decode, 207, 6, 46, // Opcode: LD2i16 >+/* 5420 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 5445 >+/* 5425 */ MCD_OPC_CheckPredicate, 0, 168, 137, // Skip to: 40669 >+/* 5429 */ MCD_OPC_CheckField, 31, 1, 0, 162, 137, // Skip to: 40669 >+/* 5435 */ MCD_OPC_CheckField, 10, 1, 0, 156, 137, // Skip to: 40669 >+/* 5441 */ MCD_OPC_Decode, 155, 7, 47, // Opcode: LD4i16 >+/* 5445 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 5495 >+/* 5450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 5453 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5471 >+/* 5457 */ MCD_OPC_CheckPredicate, 0, 136, 137, // Skip to: 40669 >+/* 5461 */ MCD_OPC_CheckField, 31, 1, 0, 130, 137, // Skip to: 40669 >+/* 5467 */ MCD_OPC_Decode, 209, 6, 48, // Opcode: LD2i32 >+/* 5471 */ MCD_OPC_FilterValue, 1, 122, 137, // Skip to: 40669 >+/* 5475 */ MCD_OPC_CheckPredicate, 0, 118, 137, // Skip to: 40669 >+/* 5479 */ MCD_OPC_CheckField, 31, 1, 0, 112, 137, // Skip to: 40669 >+/* 5485 */ MCD_OPC_CheckField, 12, 1, 0, 106, 137, // Skip to: 40669 >+/* 5491 */ MCD_OPC_Decode, 211, 6, 49, // Opcode: LD2i64 >+/* 5495 */ MCD_OPC_FilterValue, 133, 2, 45, 0, // Skip to: 5545 >+/* 5500 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 5503 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5521 >+/* 5507 */ MCD_OPC_CheckPredicate, 0, 86, 137, // Skip to: 40669 >+/* 5511 */ MCD_OPC_CheckField, 31, 1, 0, 80, 137, // Skip to: 40669 >+/* 5517 */ MCD_OPC_Decode, 157, 7, 50, // Opcode: LD4i32 >+/* 5521 */ MCD_OPC_FilterValue, 1, 72, 137, // Skip to: 40669 >+/* 5525 */ MCD_OPC_CheckPredicate, 0, 68, 137, // Skip to: 40669 >+/* 5529 */ MCD_OPC_CheckField, 31, 1, 0, 62, 137, // Skip to: 40669 >+/* 5535 */ MCD_OPC_CheckField, 12, 1, 0, 56, 137, // Skip to: 40669 >+/* 5541 */ MCD_OPC_Decode, 159, 7, 51, // Opcode: LD4i64 >+/* 5545 */ MCD_OPC_FilterValue, 134, 2, 127, 0, // Skip to: 5677 >+/* 5550 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 5553 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5584 >+/* 5557 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5560 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5572 >+/* 5564 */ MCD_OPC_CheckPredicate, 0, 29, 137, // Skip to: 40669 >+/* 5568 */ MCD_OPC_Decode, 189, 6, 7, // Opcode: LD2Rv8b >+/* 5572 */ MCD_OPC_FilterValue, 1, 21, 137, // Skip to: 40669 >+/* 5576 */ MCD_OPC_CheckPredicate, 0, 17, 137, // Skip to: 40669 >+/* 5580 */ MCD_OPC_Decode, 177, 6, 11, // Opcode: LD2Rv16b >+/* 5584 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5615 >+/* 5588 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5591 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5603 >+/* 5595 */ MCD_OPC_CheckPredicate, 0, 254, 136, // Skip to: 40669 >+/* 5599 */ MCD_OPC_Decode, 185, 6, 7, // Opcode: LD2Rv4h >+/* 5603 */ MCD_OPC_FilterValue, 1, 246, 136, // Skip to: 40669 >+/* 5607 */ MCD_OPC_CheckPredicate, 0, 242, 136, // Skip to: 40669 >+/* 5611 */ MCD_OPC_Decode, 191, 6, 11, // Opcode: LD2Rv8h >+/* 5615 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5646 >+/* 5619 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5622 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5634 >+/* 5626 */ MCD_OPC_CheckPredicate, 0, 223, 136, // Skip to: 40669 >+/* 5630 */ MCD_OPC_Decode, 183, 6, 7, // Opcode: LD2Rv2s >+/* 5634 */ MCD_OPC_FilterValue, 1, 215, 136, // Skip to: 40669 >+/* 5638 */ MCD_OPC_CheckPredicate, 0, 211, 136, // Skip to: 40669 >+/* 5642 */ MCD_OPC_Decode, 187, 6, 11, // Opcode: LD2Rv4s >+/* 5646 */ MCD_OPC_FilterValue, 3, 203, 136, // Skip to: 40669 >+/* 5650 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5653 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5665 >+/* 5657 */ MCD_OPC_CheckPredicate, 0, 192, 136, // Skip to: 40669 >+/* 5661 */ MCD_OPC_Decode, 179, 6, 7, // Opcode: LD2Rv1d >+/* 5665 */ MCD_OPC_FilterValue, 1, 184, 136, // Skip to: 40669 >+/* 5669 */ MCD_OPC_CheckPredicate, 0, 180, 136, // Skip to: 40669 >+/* 5673 */ MCD_OPC_Decode, 181, 6, 11, // Opcode: LD2Rv2d >+/* 5677 */ MCD_OPC_FilterValue, 135, 2, 171, 136, // Skip to: 40669 >+/* 5682 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 5685 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5716 >+/* 5689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5692 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5704 >+/* 5696 */ MCD_OPC_CheckPredicate, 0, 153, 136, // Skip to: 40669 >+/* 5700 */ MCD_OPC_Decode, 151, 7, 4, // Opcode: LD4Rv8b >+/* 5704 */ MCD_OPC_FilterValue, 1, 145, 136, // Skip to: 40669 >+/* 5708 */ MCD_OPC_CheckPredicate, 0, 141, 136, // Skip to: 40669 >+/* 5712 */ MCD_OPC_Decode, 139, 7, 8, // Opcode: LD4Rv16b >+/* 5716 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5747 >+/* 5720 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5723 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5735 >+/* 5727 */ MCD_OPC_CheckPredicate, 0, 122, 136, // Skip to: 40669 >+/* 5731 */ MCD_OPC_Decode, 147, 7, 4, // Opcode: LD4Rv4h >+/* 5735 */ MCD_OPC_FilterValue, 1, 114, 136, // Skip to: 40669 >+/* 5739 */ MCD_OPC_CheckPredicate, 0, 110, 136, // Skip to: 40669 >+/* 5743 */ MCD_OPC_Decode, 153, 7, 8, // Opcode: LD4Rv8h >+/* 5747 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5778 >+/* 5751 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5754 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5766 >+/* 5758 */ MCD_OPC_CheckPredicate, 0, 91, 136, // Skip to: 40669 >+/* 5762 */ MCD_OPC_Decode, 145, 7, 4, // Opcode: LD4Rv2s >+/* 5766 */ MCD_OPC_FilterValue, 1, 83, 136, // Skip to: 40669 >+/* 5770 */ MCD_OPC_CheckPredicate, 0, 79, 136, // Skip to: 40669 >+/* 5774 */ MCD_OPC_Decode, 149, 7, 8, // Opcode: LD4Rv4s >+/* 5778 */ MCD_OPC_FilterValue, 3, 71, 136, // Skip to: 40669 >+/* 5782 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5785 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5797 >+/* 5789 */ MCD_OPC_CheckPredicate, 0, 60, 136, // Skip to: 40669 >+/* 5793 */ MCD_OPC_Decode, 141, 7, 4, // Opcode: LD4Rv1d >+/* 5797 */ MCD_OPC_FilterValue, 1, 52, 136, // Skip to: 40669 >+/* 5801 */ MCD_OPC_CheckPredicate, 0, 48, 136, // Skip to: 40669 >+/* 5805 */ MCD_OPC_Decode, 143, 7, 8, // Opcode: LD4Rv2d >+/* 5809 */ MCD_OPC_FilterValue, 1, 40, 136, // Skip to: 40669 >+/* 5813 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 5816 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5824 >+/* 5820 */ MCD_OPC_Decode, 187, 7, 3, // Opcode: LDPSi >+/* 5824 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 5832 >+/* 5828 */ MCD_OPC_Decode, 178, 7, 3, // Opcode: LDPDi >+/* 5832 */ MCD_OPC_FilterValue, 2, 17, 136, // Skip to: 40669 >+/* 5836 */ MCD_OPC_Decode, 181, 7, 3, // Opcode: LDPQi >+/* 5840 */ MCD_OPC_FilterValue, 6, 191, 1, // Skip to: 6291 >+/* 5844 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... >+/* 5847 */ MCD_OPC_FilterValue, 0, 153, 1, // Skip to: 6260 >+/* 5851 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 5854 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5897 >+/* 5858 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5861 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5879 >+/* 5865 */ MCD_OPC_CheckPredicate, 0, 240, 135, // Skip to: 40669 >+/* 5869 */ MCD_OPC_CheckField, 31, 1, 0, 234, 135, // Skip to: 40669 >+/* 5875 */ MCD_OPC_Decode, 244, 13, 52, // Opcode: ST1i8_POST >+/* 5879 */ MCD_OPC_FilterValue, 1, 226, 135, // Skip to: 40669 >+/* 5883 */ MCD_OPC_CheckPredicate, 0, 222, 135, // Skip to: 40669 >+/* 5887 */ MCD_OPC_CheckField, 31, 1, 0, 216, 135, // Skip to: 40669 >+/* 5893 */ MCD_OPC_Decode, 138, 14, 53, // Opcode: ST2i8_POST >+/* 5897 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 5940 >+/* 5901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5904 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5922 >+/* 5908 */ MCD_OPC_CheckPredicate, 0, 197, 135, // Skip to: 40669 >+/* 5912 */ MCD_OPC_CheckField, 31, 1, 0, 191, 135, // Skip to: 40669 >+/* 5918 */ MCD_OPC_Decode, 160, 14, 54, // Opcode: ST3i8_POST >+/* 5922 */ MCD_OPC_FilterValue, 1, 183, 135, // Skip to: 40669 >+/* 5926 */ MCD_OPC_CheckPredicate, 0, 179, 135, // Skip to: 40669 >+/* 5930 */ MCD_OPC_CheckField, 31, 1, 0, 173, 135, // Skip to: 40669 >+/* 5936 */ MCD_OPC_Decode, 182, 14, 55, // Opcode: ST4i8_POST >+/* 5940 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 5995 >+/* 5944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5947 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5971 >+/* 5951 */ MCD_OPC_CheckPredicate, 0, 154, 135, // Skip to: 40669 >+/* 5955 */ MCD_OPC_CheckField, 31, 1, 0, 148, 135, // Skip to: 40669 >+/* 5961 */ MCD_OPC_CheckField, 10, 1, 0, 142, 135, // Skip to: 40669 >+/* 5967 */ MCD_OPC_Decode, 238, 13, 56, // Opcode: ST1i16_POST >+/* 5971 */ MCD_OPC_FilterValue, 1, 134, 135, // Skip to: 40669 >+/* 5975 */ MCD_OPC_CheckPredicate, 0, 130, 135, // Skip to: 40669 >+/* 5979 */ MCD_OPC_CheckField, 31, 1, 0, 124, 135, // Skip to: 40669 >+/* 5985 */ MCD_OPC_CheckField, 10, 1, 0, 118, 135, // Skip to: 40669 >+/* 5991 */ MCD_OPC_Decode, 132, 14, 57, // Opcode: ST2i16_POST >+/* 5995 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6050 >+/* 5999 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6002 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6026 >+/* 6006 */ MCD_OPC_CheckPredicate, 0, 99, 135, // Skip to: 40669 >+/* 6010 */ MCD_OPC_CheckField, 31, 1, 0, 93, 135, // Skip to: 40669 >+/* 6016 */ MCD_OPC_CheckField, 10, 1, 0, 87, 135, // Skip to: 40669 >+/* 6022 */ MCD_OPC_Decode, 154, 14, 58, // Opcode: ST3i16_POST >+/* 6026 */ MCD_OPC_FilterValue, 1, 79, 135, // Skip to: 40669 >+/* 6030 */ MCD_OPC_CheckPredicate, 0, 75, 135, // Skip to: 40669 >+/* 6034 */ MCD_OPC_CheckField, 31, 1, 0, 69, 135, // Skip to: 40669 >+/* 6040 */ MCD_OPC_CheckField, 10, 1, 0, 63, 135, // Skip to: 40669 >+/* 6046 */ MCD_OPC_Decode, 176, 14, 59, // Opcode: ST4i16_POST >+/* 6050 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6155 >+/* 6054 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 6057 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6100 >+/* 6061 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6064 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6082 >+/* 6068 */ MCD_OPC_CheckPredicate, 0, 37, 135, // Skip to: 40669 >+/* 6072 */ MCD_OPC_CheckField, 31, 1, 0, 31, 135, // Skip to: 40669 >+/* 6078 */ MCD_OPC_Decode, 240, 13, 60, // Opcode: ST1i32_POST >+/* 6082 */ MCD_OPC_FilterValue, 1, 23, 135, // Skip to: 40669 >+/* 6086 */ MCD_OPC_CheckPredicate, 0, 19, 135, // Skip to: 40669 >+/* 6090 */ MCD_OPC_CheckField, 31, 1, 0, 13, 135, // Skip to: 40669 >+/* 6096 */ MCD_OPC_Decode, 134, 14, 61, // Opcode: ST2i32_POST >+/* 6100 */ MCD_OPC_FilterValue, 1, 5, 135, // Skip to: 40669 >+/* 6104 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6107 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6131 >+/* 6111 */ MCD_OPC_CheckPredicate, 0, 250, 134, // Skip to: 40669 >+/* 6115 */ MCD_OPC_CheckField, 31, 1, 0, 244, 134, // Skip to: 40669 >+/* 6121 */ MCD_OPC_CheckField, 12, 1, 0, 238, 134, // Skip to: 40669 >+/* 6127 */ MCD_OPC_Decode, 242, 13, 62, // Opcode: ST1i64_POST >+/* 6131 */ MCD_OPC_FilterValue, 1, 230, 134, // Skip to: 40669 >+/* 6135 */ MCD_OPC_CheckPredicate, 0, 226, 134, // Skip to: 40669 >+/* 6139 */ MCD_OPC_CheckField, 31, 1, 0, 220, 134, // Skip to: 40669 >+/* 6145 */ MCD_OPC_CheckField, 12, 1, 0, 214, 134, // Skip to: 40669 >+/* 6151 */ MCD_OPC_Decode, 136, 14, 63, // Opcode: ST2i64_POST >+/* 6155 */ MCD_OPC_FilterValue, 5, 206, 134, // Skip to: 40669 >+/* 6159 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 6162 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6205 >+/* 6166 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6169 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6187 >+/* 6173 */ MCD_OPC_CheckPredicate, 0, 188, 134, // Skip to: 40669 >+/* 6177 */ MCD_OPC_CheckField, 31, 1, 0, 182, 134, // Skip to: 40669 >+/* 6183 */ MCD_OPC_Decode, 156, 14, 64, // Opcode: ST3i32_POST >+/* 6187 */ MCD_OPC_FilterValue, 1, 174, 134, // Skip to: 40669 >+/* 6191 */ MCD_OPC_CheckPredicate, 0, 170, 134, // Skip to: 40669 >+/* 6195 */ MCD_OPC_CheckField, 31, 1, 0, 164, 134, // Skip to: 40669 >+/* 6201 */ MCD_OPC_Decode, 178, 14, 65, // Opcode: ST4i32_POST >+/* 6205 */ MCD_OPC_FilterValue, 1, 156, 134, // Skip to: 40669 >+/* 6209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6212 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6236 >+/* 6216 */ MCD_OPC_CheckPredicate, 0, 145, 134, // Skip to: 40669 >+/* 6220 */ MCD_OPC_CheckField, 31, 1, 0, 139, 134, // Skip to: 40669 >+/* 6226 */ MCD_OPC_CheckField, 12, 1, 0, 133, 134, // Skip to: 40669 >+/* 6232 */ MCD_OPC_Decode, 158, 14, 66, // Opcode: ST3i64_POST >+/* 6236 */ MCD_OPC_FilterValue, 1, 125, 134, // Skip to: 40669 >+/* 6240 */ MCD_OPC_CheckPredicate, 0, 121, 134, // Skip to: 40669 >+/* 6244 */ MCD_OPC_CheckField, 31, 1, 0, 115, 134, // Skip to: 40669 >+/* 6250 */ MCD_OPC_CheckField, 12, 1, 0, 109, 134, // Skip to: 40669 >+/* 6256 */ MCD_OPC_Decode, 180, 14, 67, // Opcode: ST4i64_POST >+/* 6260 */ MCD_OPC_FilterValue, 1, 101, 134, // Skip to: 40669 >+/* 6264 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6267 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6275 >+/* 6271 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: STPSpre >+/* 6275 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 6283 >+/* 6279 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: STPDpre >+/* 6283 */ MCD_OPC_FilterValue, 2, 78, 134, // Skip to: 40669 >+/* 6287 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: STPQpre >+/* 6291 */ MCD_OPC_FilterValue, 7, 245, 3, // Skip to: 7308 >+/* 6295 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... >+/* 6298 */ MCD_OPC_FilterValue, 0, 207, 3, // Skip to: 7277 >+/* 6302 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 6305 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6348 >+/* 6309 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6312 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6330 >+/* 6316 */ MCD_OPC_CheckPredicate, 0, 45, 134, // Skip to: 40669 >+/* 6320 */ MCD_OPC_CheckField, 31, 1, 0, 39, 134, // Skip to: 40669 >+/* 6326 */ MCD_OPC_Decode, 176, 6, 68, // Opcode: LD1i8_POST >+/* 6330 */ MCD_OPC_FilterValue, 1, 31, 134, // Skip to: 40669 >+/* 6334 */ MCD_OPC_CheckPredicate, 0, 27, 134, // Skip to: 40669 >+/* 6338 */ MCD_OPC_CheckField, 31, 1, 0, 21, 134, // Skip to: 40669 >+/* 6344 */ MCD_OPC_Decode, 214, 6, 69, // Opcode: LD2i8_POST >+/* 6348 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 6391 >+/* 6352 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6355 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6373 >+/* 6359 */ MCD_OPC_CheckPredicate, 0, 2, 134, // Skip to: 40669 >+/* 6363 */ MCD_OPC_CheckField, 31, 1, 0, 252, 133, // Skip to: 40669 >+/* 6369 */ MCD_OPC_Decode, 252, 6, 70, // Opcode: LD3i8_POST >+/* 6373 */ MCD_OPC_FilterValue, 1, 244, 133, // Skip to: 40669 >+/* 6377 */ MCD_OPC_CheckPredicate, 0, 240, 133, // Skip to: 40669 >+/* 6381 */ MCD_OPC_CheckField, 31, 1, 0, 234, 133, // Skip to: 40669 >+/* 6387 */ MCD_OPC_Decode, 162, 7, 71, // Opcode: LD4i8_POST >+/* 6391 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6446 >+/* 6395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6398 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6422 >+/* 6402 */ MCD_OPC_CheckPredicate, 0, 215, 133, // Skip to: 40669 >+/* 6406 */ MCD_OPC_CheckField, 31, 1, 0, 209, 133, // Skip to: 40669 >+/* 6412 */ MCD_OPC_CheckField, 10, 1, 0, 203, 133, // Skip to: 40669 >+/* 6418 */ MCD_OPC_Decode, 170, 6, 72, // Opcode: LD1i16_POST >+/* 6422 */ MCD_OPC_FilterValue, 1, 195, 133, // Skip to: 40669 >+/* 6426 */ MCD_OPC_CheckPredicate, 0, 191, 133, // Skip to: 40669 >+/* 6430 */ MCD_OPC_CheckField, 31, 1, 0, 185, 133, // Skip to: 40669 >+/* 6436 */ MCD_OPC_CheckField, 10, 1, 0, 179, 133, // Skip to: 40669 >+/* 6442 */ MCD_OPC_Decode, 208, 6, 73, // Opcode: LD2i16_POST >+/* 6446 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6501 >+/* 6450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6453 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6477 >+/* 6457 */ MCD_OPC_CheckPredicate, 0, 160, 133, // Skip to: 40669 >+/* 6461 */ MCD_OPC_CheckField, 31, 1, 0, 154, 133, // Skip to: 40669 >+/* 6467 */ MCD_OPC_CheckField, 10, 1, 0, 148, 133, // Skip to: 40669 >+/* 6473 */ MCD_OPC_Decode, 246, 6, 74, // Opcode: LD3i16_POST >+/* 6477 */ MCD_OPC_FilterValue, 1, 140, 133, // Skip to: 40669 >+/* 6481 */ MCD_OPC_CheckPredicate, 0, 136, 133, // Skip to: 40669 >+/* 6485 */ MCD_OPC_CheckField, 31, 1, 0, 130, 133, // Skip to: 40669 >+/* 6491 */ MCD_OPC_CheckField, 10, 1, 0, 124, 133, // Skip to: 40669 >+/* 6497 */ MCD_OPC_Decode, 156, 7, 75, // Opcode: LD4i16_POST >+/* 6501 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6606 >+/* 6505 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 6508 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6551 >+/* 6512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6515 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6533 >+/* 6519 */ MCD_OPC_CheckPredicate, 0, 98, 133, // Skip to: 40669 >+/* 6523 */ MCD_OPC_CheckField, 31, 1, 0, 92, 133, // Skip to: 40669 >+/* 6529 */ MCD_OPC_Decode, 172, 6, 76, // Opcode: LD1i32_POST >+/* 6533 */ MCD_OPC_FilterValue, 1, 84, 133, // Skip to: 40669 >+/* 6537 */ MCD_OPC_CheckPredicate, 0, 80, 133, // Skip to: 40669 >+/* 6541 */ MCD_OPC_CheckField, 31, 1, 0, 74, 133, // Skip to: 40669 >+/* 6547 */ MCD_OPC_Decode, 210, 6, 77, // Opcode: LD2i32_POST >+/* 6551 */ MCD_OPC_FilterValue, 1, 66, 133, // Skip to: 40669 >+/* 6555 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6558 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6582 >+/* 6562 */ MCD_OPC_CheckPredicate, 0, 55, 133, // Skip to: 40669 >+/* 6566 */ MCD_OPC_CheckField, 31, 1, 0, 49, 133, // Skip to: 40669 >+/* 6572 */ MCD_OPC_CheckField, 12, 1, 0, 43, 133, // Skip to: 40669 >+/* 6578 */ MCD_OPC_Decode, 174, 6, 78, // Opcode: LD1i64_POST >+/* 6582 */ MCD_OPC_FilterValue, 1, 35, 133, // Skip to: 40669 >+/* 6586 */ MCD_OPC_CheckPredicate, 0, 31, 133, // Skip to: 40669 >+/* 6590 */ MCD_OPC_CheckField, 31, 1, 0, 25, 133, // Skip to: 40669 >+/* 6596 */ MCD_OPC_CheckField, 12, 1, 0, 19, 133, // Skip to: 40669 >+/* 6602 */ MCD_OPC_Decode, 212, 6, 79, // Opcode: LD2i64_POST >+/* 6606 */ MCD_OPC_FilterValue, 5, 101, 0, // Skip to: 6711 >+/* 6610 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 6613 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6656 >+/* 6617 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6620 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6638 >+/* 6624 */ MCD_OPC_CheckPredicate, 0, 249, 132, // Skip to: 40669 >+/* 6628 */ MCD_OPC_CheckField, 31, 1, 0, 243, 132, // Skip to: 40669 >+/* 6634 */ MCD_OPC_Decode, 248, 6, 80, // Opcode: LD3i32_POST >+/* 6638 */ MCD_OPC_FilterValue, 1, 235, 132, // Skip to: 40669 >+/* 6642 */ MCD_OPC_CheckPredicate, 0, 231, 132, // Skip to: 40669 >+/* 6646 */ MCD_OPC_CheckField, 31, 1, 0, 225, 132, // Skip to: 40669 >+/* 6652 */ MCD_OPC_Decode, 158, 7, 81, // Opcode: LD4i32_POST >+/* 6656 */ MCD_OPC_FilterValue, 1, 217, 132, // Skip to: 40669 >+/* 6660 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6663 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6687 >+/* 6667 */ MCD_OPC_CheckPredicate, 0, 206, 132, // Skip to: 40669 >+/* 6671 */ MCD_OPC_CheckField, 31, 1, 0, 200, 132, // Skip to: 40669 >+/* 6677 */ MCD_OPC_CheckField, 12, 1, 0, 194, 132, // Skip to: 40669 >+/* 6683 */ MCD_OPC_Decode, 250, 6, 82, // Opcode: LD3i64_POST >+/* 6687 */ MCD_OPC_FilterValue, 1, 186, 132, // Skip to: 40669 >+/* 6691 */ MCD_OPC_CheckPredicate, 0, 182, 132, // Skip to: 40669 >+/* 6695 */ MCD_OPC_CheckField, 31, 1, 0, 176, 132, // Skip to: 40669 >+/* 6701 */ MCD_OPC_CheckField, 12, 1, 0, 170, 132, // Skip to: 40669 >+/* 6707 */ MCD_OPC_Decode, 160, 7, 83, // Opcode: LD4i64_POST >+/* 6711 */ MCD_OPC_FilterValue, 6, 23, 1, // Skip to: 6994 >+/* 6715 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 6718 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 6787 >+/* 6722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6725 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6756 >+/* 6729 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6732 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6744 >+/* 6736 */ MCD_OPC_CheckPredicate, 0, 137, 132, // Skip to: 40669 >+/* 6740 */ MCD_OPC_Decode, 134, 6, 14, // Opcode: LD1Rv8b_POST >+/* 6744 */ MCD_OPC_FilterValue, 1, 129, 132, // Skip to: 40669 >+/* 6748 */ MCD_OPC_CheckPredicate, 0, 125, 132, // Skip to: 40669 >+/* 6752 */ MCD_OPC_Decode, 250, 5, 18, // Opcode: LD1Rv16b_POST >+/* 6756 */ MCD_OPC_FilterValue, 1, 117, 132, // Skip to: 40669 >+/* 6760 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6763 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6775 >+/* 6767 */ MCD_OPC_CheckPredicate, 0, 106, 132, // Skip to: 40669 >+/* 6771 */ MCD_OPC_Decode, 190, 6, 15, // Opcode: LD2Rv8b_POST >+/* 6775 */ MCD_OPC_FilterValue, 1, 98, 132, // Skip to: 40669 >+/* 6779 */ MCD_OPC_CheckPredicate, 0, 94, 132, // Skip to: 40669 >+/* 6783 */ MCD_OPC_Decode, 178, 6, 19, // Opcode: LD2Rv16b_POST >+/* 6787 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 6856 >+/* 6791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6794 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6825 >+/* 6798 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6801 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6813 >+/* 6805 */ MCD_OPC_CheckPredicate, 0, 68, 132, // Skip to: 40669 >+/* 6809 */ MCD_OPC_Decode, 130, 6, 14, // Opcode: LD1Rv4h_POST >+/* 6813 */ MCD_OPC_FilterValue, 1, 60, 132, // Skip to: 40669 >+/* 6817 */ MCD_OPC_CheckPredicate, 0, 56, 132, // Skip to: 40669 >+/* 6821 */ MCD_OPC_Decode, 136, 6, 18, // Opcode: LD1Rv8h_POST >+/* 6825 */ MCD_OPC_FilterValue, 1, 48, 132, // Skip to: 40669 >+/* 6829 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6832 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6844 >+/* 6836 */ MCD_OPC_CheckPredicate, 0, 37, 132, // Skip to: 40669 >+/* 6840 */ MCD_OPC_Decode, 186, 6, 15, // Opcode: LD2Rv4h_POST >+/* 6844 */ MCD_OPC_FilterValue, 1, 29, 132, // Skip to: 40669 >+/* 6848 */ MCD_OPC_CheckPredicate, 0, 25, 132, // Skip to: 40669 >+/* 6852 */ MCD_OPC_Decode, 192, 6, 19, // Opcode: LD2Rv8h_POST >+/* 6856 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 6925 >+/* 6860 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6863 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6894 >+/* 6867 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6882 >+/* 6874 */ MCD_OPC_CheckPredicate, 0, 255, 131, // Skip to: 40669 >+/* 6878 */ MCD_OPC_Decode, 128, 6, 14, // Opcode: LD1Rv2s_POST >+/* 6882 */ MCD_OPC_FilterValue, 1, 247, 131, // Skip to: 40669 >+/* 6886 */ MCD_OPC_CheckPredicate, 0, 243, 131, // Skip to: 40669 >+/* 6890 */ MCD_OPC_Decode, 132, 6, 18, // Opcode: LD1Rv4s_POST >+/* 6894 */ MCD_OPC_FilterValue, 1, 235, 131, // Skip to: 40669 >+/* 6898 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6901 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6913 >+/* 6905 */ MCD_OPC_CheckPredicate, 0, 224, 131, // Skip to: 40669 >+/* 6909 */ MCD_OPC_Decode, 184, 6, 15, // Opcode: LD2Rv2s_POST >+/* 6913 */ MCD_OPC_FilterValue, 1, 216, 131, // Skip to: 40669 >+/* 6917 */ MCD_OPC_CheckPredicate, 0, 212, 131, // Skip to: 40669 >+/* 6921 */ MCD_OPC_Decode, 188, 6, 19, // Opcode: LD2Rv4s_POST >+/* 6925 */ MCD_OPC_FilterValue, 3, 204, 131, // Skip to: 40669 >+/* 6929 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 6932 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6963 >+/* 6936 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6939 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6951 >+/* 6943 */ MCD_OPC_CheckPredicate, 0, 186, 131, // Skip to: 40669 >+/* 6947 */ MCD_OPC_Decode, 252, 5, 14, // Opcode: LD1Rv1d_POST >+/* 6951 */ MCD_OPC_FilterValue, 1, 178, 131, // Skip to: 40669 >+/* 6955 */ MCD_OPC_CheckPredicate, 0, 174, 131, // Skip to: 40669 >+/* 6959 */ MCD_OPC_Decode, 254, 5, 18, // Opcode: LD1Rv2d_POST >+/* 6963 */ MCD_OPC_FilterValue, 1, 166, 131, // Skip to: 40669 >+/* 6967 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 6970 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6982 >+/* 6974 */ MCD_OPC_CheckPredicate, 0, 155, 131, // Skip to: 40669 >+/* 6978 */ MCD_OPC_Decode, 180, 6, 15, // Opcode: LD2Rv1d_POST >+/* 6982 */ MCD_OPC_FilterValue, 1, 147, 131, // Skip to: 40669 >+/* 6986 */ MCD_OPC_CheckPredicate, 0, 143, 131, // Skip to: 40669 >+/* 6990 */ MCD_OPC_Decode, 182, 6, 19, // Opcode: LD2Rv2d_POST >+/* 6994 */ MCD_OPC_FilterValue, 7, 135, 131, // Skip to: 40669 >+/* 6998 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... >+/* 7001 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 7070 >+/* 7005 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7008 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7039 >+/* 7012 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7015 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7027 >+/* 7019 */ MCD_OPC_CheckPredicate, 0, 110, 131, // Skip to: 40669 >+/* 7023 */ MCD_OPC_Decode, 228, 6, 13, // Opcode: LD3Rv8b_POST >+/* 7027 */ MCD_OPC_FilterValue, 1, 102, 131, // Skip to: 40669 >+/* 7031 */ MCD_OPC_CheckPredicate, 0, 98, 131, // Skip to: 40669 >+/* 7035 */ MCD_OPC_Decode, 216, 6, 17, // Opcode: LD3Rv16b_POST >+/* 7039 */ MCD_OPC_FilterValue, 1, 90, 131, // Skip to: 40669 >+/* 7043 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7046 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7058 >+/* 7050 */ MCD_OPC_CheckPredicate, 0, 79, 131, // Skip to: 40669 >+/* 7054 */ MCD_OPC_Decode, 152, 7, 12, // Opcode: LD4Rv8b_POST >+/* 7058 */ MCD_OPC_FilterValue, 1, 71, 131, // Skip to: 40669 >+/* 7062 */ MCD_OPC_CheckPredicate, 0, 67, 131, // Skip to: 40669 >+/* 7066 */ MCD_OPC_Decode, 140, 7, 16, // Opcode: LD4Rv16b_POST >+/* 7070 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 7139 >+/* 7074 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7077 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7108 >+/* 7081 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7084 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7096 >+/* 7088 */ MCD_OPC_CheckPredicate, 0, 41, 131, // Skip to: 40669 >+/* 7092 */ MCD_OPC_Decode, 224, 6, 13, // Opcode: LD3Rv4h_POST >+/* 7096 */ MCD_OPC_FilterValue, 1, 33, 131, // Skip to: 40669 >+/* 7100 */ MCD_OPC_CheckPredicate, 0, 29, 131, // Skip to: 40669 >+/* 7104 */ MCD_OPC_Decode, 230, 6, 17, // Opcode: LD3Rv8h_POST >+/* 7108 */ MCD_OPC_FilterValue, 1, 21, 131, // Skip to: 40669 >+/* 7112 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7115 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7127 >+/* 7119 */ MCD_OPC_CheckPredicate, 0, 10, 131, // Skip to: 40669 >+/* 7123 */ MCD_OPC_Decode, 148, 7, 12, // Opcode: LD4Rv4h_POST >+/* 7127 */ MCD_OPC_FilterValue, 1, 2, 131, // Skip to: 40669 >+/* 7131 */ MCD_OPC_CheckPredicate, 0, 254, 130, // Skip to: 40669 >+/* 7135 */ MCD_OPC_Decode, 154, 7, 16, // Opcode: LD4Rv8h_POST >+/* 7139 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 7208 >+/* 7143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7146 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7177 >+/* 7150 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7165 >+/* 7157 */ MCD_OPC_CheckPredicate, 0, 228, 130, // Skip to: 40669 >+/* 7161 */ MCD_OPC_Decode, 222, 6, 13, // Opcode: LD3Rv2s_POST >+/* 7165 */ MCD_OPC_FilterValue, 1, 220, 130, // Skip to: 40669 >+/* 7169 */ MCD_OPC_CheckPredicate, 0, 216, 130, // Skip to: 40669 >+/* 7173 */ MCD_OPC_Decode, 226, 6, 17, // Opcode: LD3Rv4s_POST >+/* 7177 */ MCD_OPC_FilterValue, 1, 208, 130, // Skip to: 40669 >+/* 7181 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7184 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7196 >+/* 7188 */ MCD_OPC_CheckPredicate, 0, 197, 130, // Skip to: 40669 >+/* 7192 */ MCD_OPC_Decode, 146, 7, 12, // Opcode: LD4Rv2s_POST >+/* 7196 */ MCD_OPC_FilterValue, 1, 189, 130, // Skip to: 40669 >+/* 7200 */ MCD_OPC_CheckPredicate, 0, 185, 130, // Skip to: 40669 >+/* 7204 */ MCD_OPC_Decode, 150, 7, 16, // Opcode: LD4Rv4s_POST >+/* 7208 */ MCD_OPC_FilterValue, 3, 177, 130, // Skip to: 40669 >+/* 7212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7215 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7246 >+/* 7219 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7222 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7234 >+/* 7226 */ MCD_OPC_CheckPredicate, 0, 159, 130, // Skip to: 40669 >+/* 7230 */ MCD_OPC_Decode, 218, 6, 13, // Opcode: LD3Rv1d_POST >+/* 7234 */ MCD_OPC_FilterValue, 1, 151, 130, // Skip to: 40669 >+/* 7238 */ MCD_OPC_CheckPredicate, 0, 147, 130, // Skip to: 40669 >+/* 7242 */ MCD_OPC_Decode, 220, 6, 17, // Opcode: LD3Rv2d_POST >+/* 7246 */ MCD_OPC_FilterValue, 1, 139, 130, // Skip to: 40669 >+/* 7250 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7253 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7265 >+/* 7257 */ MCD_OPC_CheckPredicate, 0, 128, 130, // Skip to: 40669 >+/* 7261 */ MCD_OPC_Decode, 142, 7, 12, // Opcode: LD4Rv1d_POST >+/* 7265 */ MCD_OPC_FilterValue, 1, 120, 130, // Skip to: 40669 >+/* 7269 */ MCD_OPC_CheckPredicate, 0, 116, 130, // Skip to: 40669 >+/* 7273 */ MCD_OPC_Decode, 144, 7, 16, // Opcode: LD4Rv2d_POST >+/* 7277 */ MCD_OPC_FilterValue, 1, 108, 130, // Skip to: 40669 >+/* 7281 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... >+/* 7284 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7292 >+/* 7288 */ MCD_OPC_Decode, 189, 7, 3, // Opcode: LDPSpre >+/* 7292 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 7300 >+/* 7296 */ MCD_OPC_Decode, 180, 7, 3, // Opcode: LDPDpre >+/* 7300 */ MCD_OPC_FilterValue, 2, 85, 130, // Skip to: 40669 >+/* 7304 */ MCD_OPC_Decode, 183, 7, 3, // Opcode: LDPQpre >+/* 7308 */ MCD_OPC_FilterValue, 8, 171, 21, // Skip to: 12859 >+/* 7312 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 7315 */ MCD_OPC_FilterValue, 0, 36, 6, // Skip to: 8891 >+/* 7319 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 7322 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7353 >+/* 7326 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7329 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7341 >+/* 7333 */ MCD_OPC_CheckPredicate, 0, 52, 130, // Skip to: 40669 >+/* 7337 */ MCD_OPC_Decode, 200, 15, 84, // Opcode: TBLv8i8One >+/* 7341 */ MCD_OPC_FilterValue, 1, 44, 130, // Skip to: 40669 >+/* 7345 */ MCD_OPC_CheckPredicate, 0, 40, 130, // Skip to: 40669 >+/* 7349 */ MCD_OPC_Decode, 245, 9, 85, // Opcode: SADDLv8i8_v8i16 >+/* 7353 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 7428 >+/* 7357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7360 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7416 >+/* 7364 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7367 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7404 >+/* 7371 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7374 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7392 >+/* 7378 */ MCD_OPC_CheckPredicate, 0, 7, 130, // Skip to: 40669 >+/* 7382 */ MCD_OPC_CheckField, 18, 1, 1, 1, 130, // Skip to: 40669 >+/* 7388 */ MCD_OPC_Decode, 149, 2, 86, // Opcode: DUPv2i32lane >+/* 7392 */ MCD_OPC_FilterValue, 1, 249, 129, // Skip to: 40669 >+/* 7396 */ MCD_OPC_CheckPredicate, 0, 245, 129, // Skip to: 40669 >+/* 7400 */ MCD_OPC_Decode, 153, 2, 87, // Opcode: DUPv4i16lane >+/* 7404 */ MCD_OPC_FilterValue, 1, 237, 129, // Skip to: 40669 >+/* 7408 */ MCD_OPC_CheckPredicate, 0, 233, 129, // Skip to: 40669 >+/* 7412 */ MCD_OPC_Decode, 159, 2, 88, // Opcode: DUPv8i8lane >+/* 7416 */ MCD_OPC_FilterValue, 1, 225, 129, // Skip to: 40669 >+/* 7420 */ MCD_OPC_CheckPredicate, 0, 221, 129, // Skip to: 40669 >+/* 7424 */ MCD_OPC_Decode, 167, 10, 89, // Opcode: SHADDv8i8 >+/* 7428 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7446 >+/* 7432 */ MCD_OPC_CheckPredicate, 0, 209, 129, // Skip to: 40669 >+/* 7436 */ MCD_OPC_CheckField, 16, 6, 32, 203, 129, // Skip to: 40669 >+/* 7442 */ MCD_OPC_Decode, 182, 9, 90, // Opcode: REV64v8i8 >+/* 7446 */ MCD_OPC_FilterValue, 3, 58, 0, // Skip to: 7508 >+/* 7450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7453 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 7496 >+/* 7457 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 7460 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7472 >+/* 7464 */ MCD_OPC_CheckPredicate, 0, 177, 129, // Skip to: 40669 >+/* 7468 */ MCD_OPC_Decode, 158, 2, 91, // Opcode: DUPv8i8gpr >+/* 7472 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7484 >+/* 7476 */ MCD_OPC_CheckPredicate, 0, 165, 129, // Skip to: 40669 >+/* 7480 */ MCD_OPC_Decode, 152, 2, 91, // Opcode: DUPv4i16gpr >+/* 7484 */ MCD_OPC_FilterValue, 4, 157, 129, // Skip to: 40669 >+/* 7488 */ MCD_OPC_CheckPredicate, 0, 153, 129, // Skip to: 40669 >+/* 7492 */ MCD_OPC_Decode, 148, 2, 91, // Opcode: DUPv2i32gpr >+/* 7496 */ MCD_OPC_FilterValue, 1, 145, 129, // Skip to: 40669 >+/* 7500 */ MCD_OPC_CheckPredicate, 0, 141, 129, // Skip to: 40669 >+/* 7504 */ MCD_OPC_Decode, 168, 11, 89, // Opcode: SQADDv8i8 >+/* 7508 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 7539 >+/* 7512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7515 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7527 >+/* 7519 */ MCD_OPC_CheckPredicate, 0, 122, 129, // Skip to: 40669 >+/* 7523 */ MCD_OPC_Decode, 210, 15, 92, // Opcode: TBXv8i8One >+/* 7527 */ MCD_OPC_FilterValue, 1, 114, 129, // Skip to: 40669 >+/* 7531 */ MCD_OPC_CheckPredicate, 0, 110, 129, // Skip to: 40669 >+/* 7535 */ MCD_OPC_Decode, 251, 9, 93, // Opcode: SADDWv8i8_v8i16 >+/* 7539 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 7557 >+/* 7543 */ MCD_OPC_CheckPredicate, 0, 98, 129, // Skip to: 40669 >+/* 7547 */ MCD_OPC_CheckField, 21, 1, 1, 92, 129, // Skip to: 40669 >+/* 7553 */ MCD_OPC_Decode, 226, 12, 89, // Opcode: SRHADDv8i8 >+/* 7557 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 7594 >+/* 7561 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7564 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7576 >+/* 7568 */ MCD_OPC_CheckPredicate, 0, 73, 129, // Skip to: 40669 >+/* 7572 */ MCD_OPC_Decode, 184, 18, 89, // Opcode: UZP1v8i8 >+/* 7576 */ MCD_OPC_FilterValue, 1, 65, 129, // Skip to: 40669 >+/* 7580 */ MCD_OPC_CheckPredicate, 0, 61, 129, // Skip to: 40669 >+/* 7584 */ MCD_OPC_CheckField, 16, 5, 0, 55, 129, // Skip to: 40669 >+/* 7590 */ MCD_OPC_Decode, 171, 9, 90, // Opcode: REV16v8i8 >+/* 7594 */ MCD_OPC_FilterValue, 7, 13, 0, // Skip to: 7611 >+/* 7598 */ MCD_OPC_CheckPredicate, 0, 43, 129, // Skip to: 40669 >+/* 7602 */ MCD_OPC_CheckField, 21, 1, 1, 37, 129, // Skip to: 40669 >+/* 7608 */ MCD_OPC_Decode, 98, 89, // Opcode: ANDv8i8 >+/* 7611 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 7642 >+/* 7615 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7618 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7630 >+/* 7622 */ MCD_OPC_CheckPredicate, 0, 19, 129, // Skip to: 40669 >+/* 7626 */ MCD_OPC_Decode, 202, 15, 94, // Opcode: TBLv8i8Two >+/* 7630 */ MCD_OPC_FilterValue, 1, 11, 129, // Skip to: 40669 >+/* 7634 */ MCD_OPC_CheckPredicate, 0, 7, 129, // Skip to: 40669 >+/* 7638 */ MCD_OPC_Decode, 166, 13, 85, // Opcode: SSUBLv8i8_v8i16 >+/* 7642 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 7660 >+/* 7646 */ MCD_OPC_CheckPredicate, 0, 251, 128, // Skip to: 40669 >+/* 7650 */ MCD_OPC_CheckField, 21, 1, 1, 245, 128, // Skip to: 40669 >+/* 7656 */ MCD_OPC_Decode, 193, 10, 89, // Opcode: SHSUBv8i8 >+/* 7660 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 7710 >+/* 7664 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7679 >+/* 7671 */ MCD_OPC_CheckPredicate, 0, 226, 128, // Skip to: 40669 >+/* 7675 */ MCD_OPC_Decode, 225, 15, 89, // Opcode: TRN1v8i8 >+/* 7679 */ MCD_OPC_FilterValue, 1, 218, 128, // Skip to: 40669 >+/* 7683 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 7686 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7698 >+/* 7690 */ MCD_OPC_CheckPredicate, 0, 207, 128, // Skip to: 40669 >+/* 7694 */ MCD_OPC_Decode, 234, 9, 90, // Opcode: SADDLPv8i8_v4i16 >+/* 7698 */ MCD_OPC_FilterValue, 1, 199, 128, // Skip to: 40669 >+/* 7702 */ MCD_OPC_CheckPredicate, 0, 195, 128, // Skip to: 40669 >+/* 7706 */ MCD_OPC_Decode, 197, 18, 95, // Opcode: XTNv8i8 >+/* 7710 */ MCD_OPC_FilterValue, 11, 52, 0, // Skip to: 7766 >+/* 7714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7717 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7754 >+/* 7721 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7742 >+/* 7728 */ MCD_OPC_CheckPredicate, 0, 169, 128, // Skip to: 40669 >+/* 7732 */ MCD_OPC_CheckField, 17, 1, 1, 163, 128, // Skip to: 40669 >+/* 7738 */ MCD_OPC_Decode, 130, 11, 96, // Opcode: SMOVvi16to32 >+/* 7742 */ MCD_OPC_FilterValue, 1, 155, 128, // Skip to: 40669 >+/* 7746 */ MCD_OPC_CheckPredicate, 0, 151, 128, // Skip to: 40669 >+/* 7750 */ MCD_OPC_Decode, 133, 11, 97, // Opcode: SMOVvi8to32 >+/* 7754 */ MCD_OPC_FilterValue, 1, 143, 128, // Skip to: 40669 >+/* 7758 */ MCD_OPC_CheckPredicate, 0, 139, 128, // Skip to: 40669 >+/* 7762 */ MCD_OPC_Decode, 202, 12, 89, // Opcode: SQSUBv8i8 >+/* 7766 */ MCD_OPC_FilterValue, 12, 27, 0, // Skip to: 7797 >+/* 7770 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7773 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7785 >+/* 7777 */ MCD_OPC_CheckPredicate, 0, 120, 128, // Skip to: 40669 >+/* 7781 */ MCD_OPC_Decode, 212, 15, 98, // Opcode: TBXv8i8Two >+/* 7785 */ MCD_OPC_FilterValue, 1, 112, 128, // Skip to: 40669 >+/* 7789 */ MCD_OPC_CheckPredicate, 0, 108, 128, // Skip to: 40669 >+/* 7793 */ MCD_OPC_Decode, 172, 13, 93, // Opcode: SSUBWv8i8_v8i16 >+/* 7797 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 7815 >+/* 7801 */ MCD_OPC_CheckPredicate, 0, 96, 128, // Skip to: 40669 >+/* 7805 */ MCD_OPC_CheckField, 21, 1, 1, 90, 128, // Skip to: 40669 >+/* 7811 */ MCD_OPC_Decode, 204, 1, 89, // Opcode: CMGTv8i8 >+/* 7815 */ MCD_OPC_FilterValue, 14, 46, 0, // Skip to: 7865 >+/* 7819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7822 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7834 >+/* 7826 */ MCD_OPC_CheckPredicate, 0, 71, 128, // Skip to: 40669 >+/* 7830 */ MCD_OPC_Decode, 204, 18, 89, // Opcode: ZIP1v8i8 >+/* 7834 */ MCD_OPC_FilterValue, 1, 63, 128, // Skip to: 40669 >+/* 7838 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 7841 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7853 >+/* 7845 */ MCD_OPC_CheckPredicate, 0, 52, 128, // Skip to: 40669 >+/* 7849 */ MCD_OPC_Decode, 191, 15, 99, // Opcode: SUQADDv8i8 >+/* 7853 */ MCD_OPC_FilterValue, 16, 44, 128, // Skip to: 40669 >+/* 7857 */ MCD_OPC_CheckPredicate, 0, 40, 128, // Skip to: 40669 >+/* 7861 */ MCD_OPC_Decode, 239, 9, 100, // Opcode: SADDLVv8i8v >+/* 7865 */ MCD_OPC_FilterValue, 15, 71, 0, // Skip to: 7940 >+/* 7869 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7872 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7928 >+/* 7876 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7879 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7916 >+/* 7883 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7886 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7904 >+/* 7890 */ MCD_OPC_CheckPredicate, 0, 7, 128, // Skip to: 40669 >+/* 7894 */ MCD_OPC_CheckField, 18, 1, 1, 1, 128, // Skip to: 40669 >+/* 7900 */ MCD_OPC_Decode, 250, 16, 101, // Opcode: UMOVvi32 >+/* 7904 */ MCD_OPC_FilterValue, 1, 249, 127, // Skip to: 40669 >+/* 7908 */ MCD_OPC_CheckPredicate, 0, 245, 127, // Skip to: 40669 >+/* 7912 */ MCD_OPC_Decode, 249, 16, 96, // Opcode: UMOVvi16 >+/* 7916 */ MCD_OPC_FilterValue, 1, 237, 127, // Skip to: 40669 >+/* 7920 */ MCD_OPC_CheckPredicate, 0, 233, 127, // Skip to: 40669 >+/* 7924 */ MCD_OPC_Decode, 252, 16, 97, // Opcode: UMOVvi8 >+/* 7928 */ MCD_OPC_FilterValue, 1, 225, 127, // Skip to: 40669 >+/* 7932 */ MCD_OPC_CheckPredicate, 0, 221, 127, // Skip to: 40669 >+/* 7936 */ MCD_OPC_Decode, 188, 1, 89, // Opcode: CMGEv8i8 >+/* 7940 */ MCD_OPC_FilterValue, 16, 26, 0, // Skip to: 7970 >+/* 7944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 7947 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7959 >+/* 7951 */ MCD_OPC_CheckPredicate, 0, 202, 127, // Skip to: 40669 >+/* 7955 */ MCD_OPC_Decode, 201, 15, 102, // Opcode: TBLv8i8Three >+/* 7959 */ MCD_OPC_FilterValue, 1, 194, 127, // Skip to: 40669 >+/* 7963 */ MCD_OPC_CheckPredicate, 0, 190, 127, // Skip to: 40669 >+/* 7967 */ MCD_OPC_Decode, 37, 103, // Opcode: ADDHNv8i16_v8i8 >+/* 7970 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 7988 >+/* 7974 */ MCD_OPC_CheckPredicate, 0, 179, 127, // Skip to: 40669 >+/* 7978 */ MCD_OPC_CheckField, 21, 1, 1, 173, 127, // Skip to: 40669 >+/* 7984 */ MCD_OPC_Decode, 144, 13, 89, // Opcode: SSHLv8i8 >+/* 7988 */ MCD_OPC_FilterValue, 18, 27, 0, // Skip to: 8019 >+/* 7992 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 7995 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8007 >+/* 7999 */ MCD_OPC_CheckPredicate, 0, 154, 127, // Skip to: 40669 >+/* 8003 */ MCD_OPC_Decode, 149, 1, 90, // Opcode: CLSv8i8 >+/* 8007 */ MCD_OPC_FilterValue, 33, 146, 127, // Skip to: 40669 >+/* 8011 */ MCD_OPC_CheckPredicate, 0, 142, 127, // Skip to: 40669 >+/* 8015 */ MCD_OPC_Decode, 211, 12, 95, // Opcode: SQXTNv8i8 >+/* 8019 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 8037 >+/* 8023 */ MCD_OPC_CheckPredicate, 0, 130, 127, // Skip to: 40669 >+/* 8027 */ MCD_OPC_CheckField, 21, 1, 1, 124, 127, // Skip to: 40669 >+/* 8033 */ MCD_OPC_Decode, 172, 12, 89, // Opcode: SQSHLv8i8 >+/* 8037 */ MCD_OPC_FilterValue, 20, 27, 0, // Skip to: 8068 >+/* 8041 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8044 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8056 >+/* 8048 */ MCD_OPC_CheckPredicate, 0, 105, 127, // Skip to: 40669 >+/* 8052 */ MCD_OPC_Decode, 211, 15, 104, // Opcode: TBXv8i8Three >+/* 8056 */ MCD_OPC_FilterValue, 1, 97, 127, // Skip to: 40669 >+/* 8060 */ MCD_OPC_CheckPredicate, 0, 93, 127, // Skip to: 40669 >+/* 8064 */ MCD_OPC_Decode, 204, 9, 105, // Opcode: SABALv8i8_v8i16 >+/* 8068 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 8086 >+/* 8072 */ MCD_OPC_CheckPredicate, 0, 81, 127, // Skip to: 40669 >+/* 8076 */ MCD_OPC_CheckField, 21, 1, 1, 75, 127, // Skip to: 40669 >+/* 8082 */ MCD_OPC_Decode, 242, 12, 89, // Opcode: SRSHLv8i8 >+/* 8086 */ MCD_OPC_FilterValue, 22, 33, 0, // Skip to: 8123 >+/* 8090 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8105 >+/* 8097 */ MCD_OPC_CheckPredicate, 0, 56, 127, // Skip to: 40669 >+/* 8101 */ MCD_OPC_Decode, 191, 18, 89, // Opcode: UZP2v8i8 >+/* 8105 */ MCD_OPC_FilterValue, 1, 48, 127, // Skip to: 40669 >+/* 8109 */ MCD_OPC_CheckPredicate, 0, 44, 127, // Skip to: 40669 >+/* 8113 */ MCD_OPC_CheckField, 16, 5, 0, 38, 127, // Skip to: 40669 >+/* 8119 */ MCD_OPC_Decode, 247, 1, 90, // Opcode: CNTv8i8 >+/* 8123 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 8141 >+/* 8127 */ MCD_OPC_CheckPredicate, 0, 26, 127, // Skip to: 40669 >+/* 8131 */ MCD_OPC_CheckField, 21, 1, 1, 20, 127, // Skip to: 40669 >+/* 8137 */ MCD_OPC_Decode, 250, 11, 89, // Opcode: SQRSHLv8i8 >+/* 8141 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 8172 >+/* 8145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8148 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8160 >+/* 8152 */ MCD_OPC_CheckPredicate, 0, 1, 127, // Skip to: 40669 >+/* 8156 */ MCD_OPC_Decode, 199, 15, 106, // Opcode: TBLv8i8Four >+/* 8160 */ MCD_OPC_FilterValue, 1, 249, 126, // Skip to: 40669 >+/* 8164 */ MCD_OPC_CheckPredicate, 0, 245, 126, // Skip to: 40669 >+/* 8168 */ MCD_OPC_Decode, 154, 15, 103, // Opcode: SUBHNv8i16_v8i8 >+/* 8172 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 8190 >+/* 8176 */ MCD_OPC_CheckPredicate, 0, 233, 126, // Skip to: 40669 >+/* 8180 */ MCD_OPC_CheckField, 21, 1, 1, 227, 126, // Skip to: 40669 >+/* 8186 */ MCD_OPC_Decode, 219, 10, 89, // Opcode: SMAXv8i8 >+/* 8190 */ MCD_OPC_FilterValue, 26, 46, 0, // Skip to: 8240 >+/* 8194 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8197 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8209 >+/* 8201 */ MCD_OPC_CheckPredicate, 0, 208, 126, // Skip to: 40669 >+/* 8205 */ MCD_OPC_Decode, 232, 15, 89, // Opcode: TRN2v8i8 >+/* 8209 */ MCD_OPC_FilterValue, 1, 200, 126, // Skip to: 40669 >+/* 8213 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 8216 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8228 >+/* 8220 */ MCD_OPC_CheckPredicate, 0, 189, 126, // Skip to: 40669 >+/* 8224 */ MCD_OPC_Decode, 228, 9, 99, // Opcode: SADALPv8i8_v4i16 >+/* 8228 */ MCD_OPC_FilterValue, 1, 181, 126, // Skip to: 40669 >+/* 8232 */ MCD_OPC_CheckPredicate, 0, 177, 126, // Skip to: 40669 >+/* 8236 */ MCD_OPC_Decode, 197, 3, 95, // Opcode: FCVTNv4i16 >+/* 8240 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 8258 >+/* 8244 */ MCD_OPC_CheckPredicate, 0, 165, 126, // Skip to: 40669 >+/* 8248 */ MCD_OPC_CheckField, 21, 1, 1, 159, 126, // Skip to: 40669 >+/* 8254 */ MCD_OPC_Decode, 237, 10, 89, // Opcode: SMINv8i8 >+/* 8258 */ MCD_OPC_FilterValue, 28, 27, 0, // Skip to: 8289 >+/* 8262 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8265 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8277 >+/* 8269 */ MCD_OPC_CheckPredicate, 0, 140, 126, // Skip to: 40669 >+/* 8273 */ MCD_OPC_Decode, 209, 15, 107, // Opcode: TBXv8i8Four >+/* 8277 */ MCD_OPC_FilterValue, 1, 132, 126, // Skip to: 40669 >+/* 8281 */ MCD_OPC_CheckPredicate, 0, 128, 126, // Skip to: 40669 >+/* 8285 */ MCD_OPC_Decode, 216, 9, 85, // Opcode: SABDLv8i8_v8i16 >+/* 8289 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 8307 >+/* 8293 */ MCD_OPC_CheckPredicate, 0, 116, 126, // Skip to: 40669 >+/* 8297 */ MCD_OPC_CheckField, 21, 1, 1, 110, 126, // Skip to: 40669 >+/* 8303 */ MCD_OPC_Decode, 222, 9, 89, // Opcode: SABDv8i8 >+/* 8307 */ MCD_OPC_FilterValue, 30, 46, 0, // Skip to: 8357 >+/* 8311 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8314 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8326 >+/* 8318 */ MCD_OPC_CheckPredicate, 0, 91, 126, // Skip to: 40669 >+/* 8322 */ MCD_OPC_Decode, 211, 18, 89, // Opcode: ZIP2v8i8 >+/* 8326 */ MCD_OPC_FilterValue, 1, 83, 126, // Skip to: 40669 >+/* 8330 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 8333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8345 >+/* 8337 */ MCD_OPC_CheckPredicate, 0, 72, 126, // Skip to: 40669 >+/* 8341 */ MCD_OPC_Decode, 157, 11, 90, // Opcode: SQABSv8i8 >+/* 8345 */ MCD_OPC_FilterValue, 1, 64, 126, // Skip to: 40669 >+/* 8349 */ MCD_OPC_CheckPredicate, 0, 60, 126, // Skip to: 40669 >+/* 8353 */ MCD_OPC_Decode, 157, 3, 108, // Opcode: FCVTLv4i16 >+/* 8357 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 8375 >+/* 8361 */ MCD_OPC_CheckPredicate, 0, 48, 126, // Skip to: 40669 >+/* 8365 */ MCD_OPC_CheckField, 21, 1, 1, 42, 126, // Skip to: 40669 >+/* 8371 */ MCD_OPC_Decode, 210, 9, 109, // Opcode: SABAv8i8 >+/* 8375 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 8393 >+/* 8379 */ MCD_OPC_CheckPredicate, 0, 30, 126, // Skip to: 40669 >+/* 8383 */ MCD_OPC_CheckField, 21, 1, 1, 24, 126, // Skip to: 40669 >+/* 8389 */ MCD_OPC_Decode, 247, 10, 105, // Opcode: SMLALv8i8_v8i16 >+/* 8393 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 8410 >+/* 8397 */ MCD_OPC_CheckPredicate, 0, 12, 126, // Skip to: 40669 >+/* 8401 */ MCD_OPC_CheckField, 21, 1, 1, 6, 126, // Skip to: 40669 >+/* 8407 */ MCD_OPC_Decode, 76, 89, // Opcode: ADDv8i8 >+/* 8410 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 8441 >+/* 8414 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 8417 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8429 >+/* 8421 */ MCD_OPC_CheckPredicate, 0, 244, 125, // Skip to: 40669 >+/* 8425 */ MCD_OPC_Decode, 205, 1, 90, // Opcode: CMGTv8i8rz >+/* 8429 */ MCD_OPC_FilterValue, 33, 236, 125, // Skip to: 40669 >+/* 8433 */ MCD_OPC_CheckPredicate, 0, 232, 125, // Skip to: 40669 >+/* 8437 */ MCD_OPC_Decode, 167, 5, 90, // Opcode: FRINTNv2f32 >+/* 8441 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 8459 >+/* 8445 */ MCD_OPC_CheckPredicate, 0, 220, 125, // Skip to: 40669 >+/* 8449 */ MCD_OPC_CheckField, 21, 1, 1, 214, 125, // Skip to: 40669 >+/* 8455 */ MCD_OPC_Decode, 245, 1, 89, // Opcode: CMTSTv8i8 >+/* 8459 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 8477 >+/* 8463 */ MCD_OPC_CheckPredicate, 0, 202, 125, // Skip to: 40669 >+/* 8467 */ MCD_OPC_CheckField, 21, 1, 1, 196, 125, // Skip to: 40669 >+/* 8473 */ MCD_OPC_Decode, 189, 8, 109, // Opcode: MLAv8i8 >+/* 8477 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 8508 >+/* 8481 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 8484 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8496 >+/* 8488 */ MCD_OPC_CheckPredicate, 0, 177, 125, // Skip to: 40669 >+/* 8492 */ MCD_OPC_Decode, 173, 1, 90, // Opcode: CMEQv8i8rz >+/* 8496 */ MCD_OPC_FilterValue, 33, 169, 125, // Skip to: 40669 >+/* 8500 */ MCD_OPC_CheckPredicate, 0, 165, 125, // Skip to: 40669 >+/* 8504 */ MCD_OPC_Decode, 162, 5, 90, // Opcode: FRINTMv2f32 >+/* 8508 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 8526 >+/* 8512 */ MCD_OPC_CheckPredicate, 0, 153, 125, // Skip to: 40669 >+/* 8516 */ MCD_OPC_CheckField, 21, 1, 1, 147, 125, // Skip to: 40669 >+/* 8522 */ MCD_OPC_Decode, 238, 8, 89, // Opcode: MULv8i8 >+/* 8526 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 8544 >+/* 8530 */ MCD_OPC_CheckPredicate, 0, 135, 125, // Skip to: 40669 >+/* 8534 */ MCD_OPC_CheckField, 21, 1, 1, 129, 125, // Skip to: 40669 >+/* 8540 */ MCD_OPC_Decode, 129, 11, 105, // Opcode: SMLSLv8i8_v8i16 >+/* 8544 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 8562 >+/* 8548 */ MCD_OPC_CheckPredicate, 0, 117, 125, // Skip to: 40669 >+/* 8552 */ MCD_OPC_CheckField, 21, 1, 1, 111, 125, // Skip to: 40669 >+/* 8558 */ MCD_OPC_Decode, 208, 10, 89, // Opcode: SMAXPv8i8 >+/* 8562 */ MCD_OPC_FilterValue, 42, 51, 0, // Skip to: 8617 >+/* 8566 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 8569 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8581 >+/* 8573 */ MCD_OPC_CheckPredicate, 0, 92, 125, // Skip to: 40669 >+/* 8577 */ MCD_OPC_Decode, 237, 1, 90, // Opcode: CMLTv8i8rz >+/* 8581 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8593 >+/* 8585 */ MCD_OPC_CheckPredicate, 0, 80, 125, // Skip to: 40669 >+/* 8589 */ MCD_OPC_Decode, 184, 3, 90, // Opcode: FCVTNSv2f32 >+/* 8593 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 8605 >+/* 8597 */ MCD_OPC_CheckPredicate, 0, 68, 125, // Skip to: 40669 >+/* 8601 */ MCD_OPC_Decode, 213, 10, 110, // Opcode: SMAXVv8i8v >+/* 8605 */ MCD_OPC_FilterValue, 49, 60, 125, // Skip to: 40669 >+/* 8609 */ MCD_OPC_CheckPredicate, 0, 56, 125, // Skip to: 40669 >+/* 8613 */ MCD_OPC_Decode, 231, 10, 110, // Opcode: SMINVv8i8v >+/* 8617 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 8635 >+/* 8621 */ MCD_OPC_CheckPredicate, 0, 44, 125, // Skip to: 40669 >+/* 8625 */ MCD_OPC_CheckField, 21, 1, 1, 38, 125, // Skip to: 40669 >+/* 8631 */ MCD_OPC_Decode, 226, 10, 89, // Opcode: SMINPv8i8 >+/* 8635 */ MCD_OPC_FilterValue, 46, 37, 0, // Skip to: 8676 >+/* 8639 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 8642 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 8653 >+/* 8646 */ MCD_OPC_CheckPredicate, 0, 19, 125, // Skip to: 40669 >+/* 8650 */ MCD_OPC_Decode, 27, 90, // Opcode: ABSv8i8 >+/* 8653 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8665 >+/* 8657 */ MCD_OPC_CheckPredicate, 0, 8, 125, // Skip to: 40669 >+/* 8661 */ MCD_OPC_Decode, 166, 3, 90, // Opcode: FCVTMSv2f32 >+/* 8665 */ MCD_OPC_FilterValue, 49, 0, 125, // Skip to: 40669 >+/* 8669 */ MCD_OPC_CheckPredicate, 0, 252, 124, // Skip to: 40669 >+/* 8673 */ MCD_OPC_Decode, 59, 110, // Opcode: ADDVv8i8v >+/* 8676 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 8693 >+/* 8680 */ MCD_OPC_CheckPredicate, 0, 241, 124, // Skip to: 40669 >+/* 8684 */ MCD_OPC_CheckField, 21, 1, 1, 235, 124, // Skip to: 40669 >+/* 8690 */ MCD_OPC_Decode, 45, 89, // Opcode: ADDPv8i8 >+/* 8693 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 8711 >+/* 8697 */ MCD_OPC_CheckPredicate, 0, 224, 124, // Skip to: 40669 >+/* 8701 */ MCD_OPC_CheckField, 21, 1, 1, 218, 124, // Skip to: 40669 >+/* 8707 */ MCD_OPC_Decode, 146, 11, 85, // Opcode: SMULLv8i8_v8i16 >+/* 8711 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 8729 >+/* 8715 */ MCD_OPC_CheckPredicate, 0, 206, 124, // Skip to: 40669 >+/* 8719 */ MCD_OPC_CheckField, 21, 1, 1, 200, 124, // Skip to: 40669 >+/* 8725 */ MCD_OPC_Decode, 169, 4, 89, // Opcode: FMAXNMv2f32 >+/* 8729 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 8747 >+/* 8733 */ MCD_OPC_CheckPredicate, 0, 188, 124, // Skip to: 40669 >+/* 8737 */ MCD_OPC_CheckField, 16, 6, 33, 182, 124, // Skip to: 40669 >+/* 8743 */ MCD_OPC_Decode, 140, 3, 90, // Opcode: FCVTASv2f32 >+/* 8747 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 8765 >+/* 8751 */ MCD_OPC_CheckPredicate, 0, 170, 124, // Skip to: 40669 >+/* 8755 */ MCD_OPC_CheckField, 21, 1, 1, 164, 124, // Skip to: 40669 >+/* 8761 */ MCD_OPC_Decode, 206, 4, 109, // Opcode: FMLAv2f32 >+/* 8765 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 8783 >+/* 8769 */ MCD_OPC_CheckPredicate, 0, 152, 124, // Skip to: 40669 >+/* 8773 */ MCD_OPC_CheckField, 21, 1, 1, 146, 124, // Skip to: 40669 >+/* 8779 */ MCD_OPC_Decode, 205, 2, 89, // Opcode: FADDv2f32 >+/* 8783 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 8801 >+/* 8787 */ MCD_OPC_CheckPredicate, 0, 134, 124, // Skip to: 40669 >+/* 8791 */ MCD_OPC_CheckField, 16, 6, 33, 128, 124, // Skip to: 40669 >+/* 8797 */ MCD_OPC_Decode, 142, 10, 90, // Opcode: SCVTFv2f32 >+/* 8801 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 8819 >+/* 8805 */ MCD_OPC_CheckPredicate, 0, 116, 124, // Skip to: 40669 >+/* 8809 */ MCD_OPC_CheckField, 21, 1, 1, 110, 124, // Skip to: 40669 >+/* 8815 */ MCD_OPC_Decode, 241, 4, 89, // Opcode: FMULXv2f32 >+/* 8819 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 8837 >+/* 8823 */ MCD_OPC_CheckPredicate, 0, 98, 124, // Skip to: 40669 >+/* 8827 */ MCD_OPC_CheckField, 21, 1, 1, 92, 124, // Skip to: 40669 >+/* 8833 */ MCD_OPC_Decode, 148, 9, 85, // Opcode: PMULLv8i8 >+/* 8837 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 8855 >+/* 8841 */ MCD_OPC_CheckPredicate, 0, 80, 124, // Skip to: 40669 >+/* 8845 */ MCD_OPC_CheckField, 21, 1, 1, 74, 124, // Skip to: 40669 >+/* 8851 */ MCD_OPC_Decode, 216, 2, 89, // Opcode: FCMEQv2f32 >+/* 8855 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 8873 >+/* 8859 */ MCD_OPC_CheckPredicate, 0, 62, 124, // Skip to: 40669 >+/* 8863 */ MCD_OPC_CheckField, 21, 1, 1, 56, 124, // Skip to: 40669 >+/* 8869 */ MCD_OPC_Decode, 179, 4, 89, // Opcode: FMAXv2f32 >+/* 8873 */ MCD_OPC_FilterValue, 63, 48, 124, // Skip to: 40669 >+/* 8877 */ MCD_OPC_CheckPredicate, 0, 44, 124, // Skip to: 40669 >+/* 8881 */ MCD_OPC_CheckField, 21, 1, 1, 38, 124, // Skip to: 40669 >+/* 8887 */ MCD_OPC_Decode, 145, 5, 89, // Opcode: FRECPSv2f32 >+/* 8891 */ MCD_OPC_FilterValue, 1, 85, 4, // Skip to: 10004 >+/* 8895 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... >+/* 8898 */ MCD_OPC_FilterValue, 0, 64, 1, // Skip to: 9222 >+/* 8902 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 8905 */ MCD_OPC_FilterValue, 0, 162, 0, // Skip to: 9071 >+/* 8909 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 8912 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8924 >+/* 8916 */ MCD_OPC_CheckPredicate, 0, 5, 124, // Skip to: 40669 >+/* 8920 */ MCD_OPC_Decode, 176, 2, 111, // Opcode: EXTv8i8 >+/* 8924 */ MCD_OPC_FilterValue, 1, 253, 123, // Skip to: 40669 >+/* 8928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... >+/* 8931 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8943 >+/* 8935 */ MCD_OPC_CheckPredicate, 0, 242, 123, // Skip to: 40669 >+/* 8939 */ MCD_OPC_Decode, 151, 16, 85, // Opcode: UADDLv8i8_v8i16 >+/* 8943 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8961 >+/* 8947 */ MCD_OPC_CheckPredicate, 0, 230, 123, // Skip to: 40669 >+/* 8951 */ MCD_OPC_CheckField, 16, 5, 0, 224, 123, // Skip to: 40669 >+/* 8957 */ MCD_OPC_Decode, 176, 9, 90, // Opcode: REV32v8i8 >+/* 8961 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8973 >+/* 8965 */ MCD_OPC_CheckPredicate, 0, 212, 123, // Skip to: 40669 >+/* 8969 */ MCD_OPC_Decode, 157, 16, 93, // Opcode: UADDWv8i8_v8i16 >+/* 8973 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8985 >+/* 8977 */ MCD_OPC_CheckPredicate, 0, 200, 123, // Skip to: 40669 >+/* 8981 */ MCD_OPC_Decode, 171, 18, 85, // Opcode: USUBLv8i8_v8i16 >+/* 8985 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 9016 >+/* 8989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 8992 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9004 >+/* 8996 */ MCD_OPC_CheckPredicate, 0, 181, 123, // Skip to: 40669 >+/* 9000 */ MCD_OPC_Decode, 140, 16, 90, // Opcode: UADDLPv8i8_v4i16 >+/* 9004 */ MCD_OPC_FilterValue, 1, 173, 123, // Skip to: 40669 >+/* 9008 */ MCD_OPC_CheckPredicate, 0, 169, 123, // Skip to: 40669 >+/* 9012 */ MCD_OPC_Decode, 220, 12, 95, // Opcode: SQXTUNv8i8 >+/* 9016 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9028 >+/* 9020 */ MCD_OPC_CheckPredicate, 0, 157, 123, // Skip to: 40669 >+/* 9024 */ MCD_OPC_Decode, 177, 18, 93, // Opcode: USUBWv8i8_v8i16 >+/* 9028 */ MCD_OPC_FilterValue, 7, 149, 123, // Skip to: 40669 >+/* 9032 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 9035 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9047 >+/* 9039 */ MCD_OPC_CheckPredicate, 0, 138, 123, // Skip to: 40669 >+/* 9043 */ MCD_OPC_Decode, 157, 18, 99, // Opcode: USQADDv8i8 >+/* 9047 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 9059 >+/* 9051 */ MCD_OPC_CheckPredicate, 0, 126, 123, // Skip to: 40669 >+/* 9055 */ MCD_OPC_Decode, 173, 10, 108, // Opcode: SHLLv8i8 >+/* 9059 */ MCD_OPC_FilterValue, 16, 118, 123, // Skip to: 40669 >+/* 9063 */ MCD_OPC_CheckPredicate, 0, 114, 123, // Skip to: 40669 >+/* 9067 */ MCD_OPC_Decode, 145, 16, 100, // Opcode: UADDLVv8i8v >+/* 9071 */ MCD_OPC_FilterValue, 1, 106, 123, // Skip to: 40669 >+/* 9075 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... >+/* 9078 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9096 >+/* 9082 */ MCD_OPC_CheckPredicate, 0, 95, 123, // Skip to: 40669 >+/* 9086 */ MCD_OPC_CheckField, 21, 1, 1, 89, 123, // Skip to: 40669 >+/* 9092 */ MCD_OPC_Decode, 187, 16, 89, // Opcode: UHADDv8i8 >+/* 9096 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9114 >+/* 9100 */ MCD_OPC_CheckPredicate, 0, 77, 123, // Skip to: 40669 >+/* 9104 */ MCD_OPC_CheckField, 21, 1, 1, 71, 123, // Skip to: 40669 >+/* 9110 */ MCD_OPC_Decode, 147, 17, 89, // Opcode: UQADDv8i8 >+/* 9114 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9132 >+/* 9118 */ MCD_OPC_CheckPredicate, 0, 59, 123, // Skip to: 40669 >+/* 9122 */ MCD_OPC_CheckField, 21, 1, 1, 53, 123, // Skip to: 40669 >+/* 9128 */ MCD_OPC_Decode, 226, 17, 89, // Opcode: URHADDv8i8 >+/* 9132 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9150 >+/* 9136 */ MCD_OPC_CheckPredicate, 0, 41, 123, // Skip to: 40669 >+/* 9140 */ MCD_OPC_CheckField, 21, 1, 1, 35, 123, // Skip to: 40669 >+/* 9146 */ MCD_OPC_Decode, 171, 2, 89, // Opcode: EORv8i8 >+/* 9150 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9168 >+/* 9154 */ MCD_OPC_CheckPredicate, 0, 23, 123, // Skip to: 40669 >+/* 9158 */ MCD_OPC_CheckField, 21, 1, 1, 17, 123, // Skip to: 40669 >+/* 9164 */ MCD_OPC_Decode, 193, 16, 89, // Opcode: UHSUBv8i8 >+/* 9168 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9186 >+/* 9172 */ MCD_OPC_CheckPredicate, 0, 5, 123, // Skip to: 40669 >+/* 9176 */ MCD_OPC_CheckField, 21, 1, 1, 255, 122, // Skip to: 40669 >+/* 9182 */ MCD_OPC_Decode, 209, 17, 89, // Opcode: UQSUBv8i8 >+/* 9186 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9204 >+/* 9190 */ MCD_OPC_CheckPredicate, 0, 243, 122, // Skip to: 40669 >+/* 9194 */ MCD_OPC_CheckField, 21, 1, 1, 237, 122, // Skip to: 40669 >+/* 9200 */ MCD_OPC_Decode, 213, 1, 89, // Opcode: CMHIv8i8 >+/* 9204 */ MCD_OPC_FilterValue, 7, 229, 122, // Skip to: 40669 >+/* 9208 */ MCD_OPC_CheckPredicate, 0, 225, 122, // Skip to: 40669 >+/* 9212 */ MCD_OPC_CheckField, 21, 1, 1, 219, 122, // Skip to: 40669 >+/* 9218 */ MCD_OPC_Decode, 221, 1, 89, // Opcode: CMHSv8i8 >+/* 9222 */ MCD_OPC_FilterValue, 1, 48, 1, // Skip to: 9530 >+/* 9226 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... >+/* 9229 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9247 >+/* 9233 */ MCD_OPC_CheckPredicate, 0, 200, 122, // Skip to: 40669 >+/* 9237 */ MCD_OPC_CheckField, 21, 1, 1, 194, 122, // Skip to: 40669 >+/* 9243 */ MCD_OPC_Decode, 161, 9, 103, // Opcode: RADDHNv8i16_v8i8 >+/* 9247 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9265 >+/* 9251 */ MCD_OPC_CheckPredicate, 0, 182, 122, // Skip to: 40669 >+/* 9255 */ MCD_OPC_CheckField, 21, 1, 1, 176, 122, // Skip to: 40669 >+/* 9261 */ MCD_OPC_Decode, 138, 18, 89, // Opcode: USHLv8i8 >+/* 9265 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9296 >+/* 9269 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 9272 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9284 >+/* 9276 */ MCD_OPC_CheckPredicate, 0, 157, 122, // Skip to: 40669 >+/* 9280 */ MCD_OPC_Decode, 157, 1, 90, // Opcode: CLZv8i8 >+/* 9284 */ MCD_OPC_FilterValue, 33, 149, 122, // Skip to: 40669 >+/* 9288 */ MCD_OPC_CheckPredicate, 0, 145, 122, // Skip to: 40669 >+/* 9292 */ MCD_OPC_Decode, 218, 17, 95, // Opcode: UQXTNv8i8 >+/* 9296 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9314 >+/* 9300 */ MCD_OPC_CheckPredicate, 0, 133, 122, // Skip to: 40669 >+/* 9304 */ MCD_OPC_CheckField, 21, 1, 1, 127, 122, // Skip to: 40669 >+/* 9310 */ MCD_OPC_Decode, 188, 17, 89, // Opcode: UQSHLv8i8 >+/* 9314 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9332 >+/* 9318 */ MCD_OPC_CheckPredicate, 0, 115, 122, // Skip to: 40669 >+/* 9322 */ MCD_OPC_CheckField, 21, 1, 1, 109, 122, // Skip to: 40669 >+/* 9328 */ MCD_OPC_Decode, 238, 15, 105, // Opcode: UABALv8i8_v8i16 >+/* 9332 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9350 >+/* 9336 */ MCD_OPC_CheckPredicate, 0, 97, 122, // Skip to: 40669 >+/* 9340 */ MCD_OPC_CheckField, 21, 1, 1, 91, 122, // Skip to: 40669 >+/* 9346 */ MCD_OPC_Decode, 234, 17, 89, // Opcode: URSHLv8i8 >+/* 9350 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9368 >+/* 9354 */ MCD_OPC_CheckPredicate, 0, 79, 122, // Skip to: 40669 >+/* 9358 */ MCD_OPC_CheckField, 16, 6, 32, 73, 122, // Skip to: 40669 >+/* 9364 */ MCD_OPC_Decode, 254, 8, 90, // Opcode: NOTv8i8 >+/* 9368 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9386 >+/* 9372 */ MCD_OPC_CheckPredicate, 0, 61, 122, // Skip to: 40669 >+/* 9376 */ MCD_OPC_CheckField, 21, 1, 1, 55, 122, // Skip to: 40669 >+/* 9382 */ MCD_OPC_Decode, 158, 17, 89, // Opcode: UQRSHLv8i8 >+/* 9386 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9404 >+/* 9390 */ MCD_OPC_CheckPredicate, 0, 43, 122, // Skip to: 40669 >+/* 9394 */ MCD_OPC_CheckField, 21, 1, 1, 37, 122, // Skip to: 40669 >+/* 9400 */ MCD_OPC_Decode, 198, 9, 103, // Opcode: RSUBHNv8i16_v8i8 >+/* 9404 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9422 >+/* 9408 */ MCD_OPC_CheckPredicate, 0, 25, 122, // Skip to: 40669 >+/* 9412 */ MCD_OPC_CheckField, 21, 1, 1, 19, 122, // Skip to: 40669 >+/* 9418 */ MCD_OPC_Decode, 211, 16, 89, // Opcode: UMAXv8i8 >+/* 9422 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 9440 >+/* 9426 */ MCD_OPC_CheckPredicate, 0, 7, 122, // Skip to: 40669 >+/* 9430 */ MCD_OPC_CheckField, 16, 6, 32, 1, 122, // Skip to: 40669 >+/* 9436 */ MCD_OPC_Decode, 134, 16, 99, // Opcode: UADALPv8i8_v4i16 >+/* 9440 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9458 >+/* 9444 */ MCD_OPC_CheckPredicate, 0, 245, 121, // Skip to: 40669 >+/* 9448 */ MCD_OPC_CheckField, 21, 1, 1, 239, 121, // Skip to: 40669 >+/* 9454 */ MCD_OPC_Decode, 228, 16, 89, // Opcode: UMINv8i8 >+/* 9458 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 9476 >+/* 9462 */ MCD_OPC_CheckPredicate, 0, 227, 121, // Skip to: 40669 >+/* 9466 */ MCD_OPC_CheckField, 21, 1, 1, 221, 121, // Skip to: 40669 >+/* 9472 */ MCD_OPC_Decode, 250, 15, 85, // Opcode: UABDLv8i8_v8i16 >+/* 9476 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9494 >+/* 9480 */ MCD_OPC_CheckPredicate, 0, 209, 121, // Skip to: 40669 >+/* 9484 */ MCD_OPC_CheckField, 21, 1, 1, 203, 121, // Skip to: 40669 >+/* 9490 */ MCD_OPC_Decode, 128, 16, 89, // Opcode: UABDv8i8 >+/* 9494 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 9512 >+/* 9498 */ MCD_OPC_CheckPredicate, 0, 191, 121, // Skip to: 40669 >+/* 9502 */ MCD_OPC_CheckField, 16, 6, 32, 185, 121, // Skip to: 40669 >+/* 9508 */ MCD_OPC_Decode, 227, 11, 90, // Opcode: SQNEGv8i8 >+/* 9512 */ MCD_OPC_FilterValue, 15, 177, 121, // Skip to: 40669 >+/* 9516 */ MCD_OPC_CheckPredicate, 0, 173, 121, // Skip to: 40669 >+/* 9520 */ MCD_OPC_CheckField, 21, 1, 1, 167, 121, // Skip to: 40669 >+/* 9526 */ MCD_OPC_Decode, 244, 15, 109, // Opcode: UABAv8i8 >+/* 9530 */ MCD_OPC_FilterValue, 2, 27, 1, // Skip to: 9817 >+/* 9534 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... >+/* 9537 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9555 >+/* 9541 */ MCD_OPC_CheckPredicate, 0, 148, 121, // Skip to: 40669 >+/* 9545 */ MCD_OPC_CheckField, 21, 1, 1, 142, 121, // Skip to: 40669 >+/* 9551 */ MCD_OPC_Decode, 238, 16, 105, // Opcode: UMLALv8i8_v8i16 >+/* 9555 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9573 >+/* 9559 */ MCD_OPC_CheckPredicate, 0, 130, 121, // Skip to: 40669 >+/* 9563 */ MCD_OPC_CheckField, 21, 1, 1, 124, 121, // Skip to: 40669 >+/* 9569 */ MCD_OPC_Decode, 180, 15, 89, // Opcode: SUBv8i8 >+/* 9573 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9604 >+/* 9577 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 9580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9592 >+/* 9584 */ MCD_OPC_CheckPredicate, 0, 105, 121, // Skip to: 40669 >+/* 9588 */ MCD_OPC_Decode, 189, 1, 90, // Opcode: CMGEv8i8rz >+/* 9592 */ MCD_OPC_FilterValue, 33, 97, 121, // Skip to: 40669 >+/* 9596 */ MCD_OPC_CheckPredicate, 0, 93, 121, // Skip to: 40669 >+/* 9600 */ MCD_OPC_Decode, 152, 5, 90, // Opcode: FRINTAv2f32 >+/* 9604 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9622 >+/* 9608 */ MCD_OPC_CheckPredicate, 0, 81, 121, // Skip to: 40669 >+/* 9612 */ MCD_OPC_CheckField, 21, 1, 1, 75, 121, // Skip to: 40669 >+/* 9618 */ MCD_OPC_Decode, 172, 1, 89, // Opcode: CMEQv8i8 >+/* 9622 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9640 >+/* 9626 */ MCD_OPC_CheckPredicate, 0, 63, 121, // Skip to: 40669 >+/* 9630 */ MCD_OPC_CheckField, 21, 1, 1, 57, 121, // Skip to: 40669 >+/* 9636 */ MCD_OPC_Decode, 199, 8, 109, // Opcode: MLSv8i8 >+/* 9640 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 9671 >+/* 9644 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 9647 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9659 >+/* 9651 */ MCD_OPC_CheckPredicate, 0, 38, 121, // Skip to: 40669 >+/* 9655 */ MCD_OPC_Decode, 229, 1, 90, // Opcode: CMLEv8i8rz >+/* 9659 */ MCD_OPC_FilterValue, 33, 30, 121, // Skip to: 40669 >+/* 9663 */ MCD_OPC_CheckPredicate, 0, 26, 121, // Skip to: 40669 >+/* 9667 */ MCD_OPC_Decode, 177, 5, 90, // Opcode: FRINTXv2f32 >+/* 9671 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9689 >+/* 9675 */ MCD_OPC_CheckPredicate, 0, 14, 121, // Skip to: 40669 >+/* 9679 */ MCD_OPC_CheckField, 21, 1, 1, 8, 121, // Skip to: 40669 >+/* 9685 */ MCD_OPC_Decode, 150, 9, 89, // Opcode: PMULv8i8 >+/* 9689 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9707 >+/* 9693 */ MCD_OPC_CheckPredicate, 0, 252, 120, // Skip to: 40669 >+/* 9697 */ MCD_OPC_CheckField, 21, 1, 1, 246, 120, // Skip to: 40669 >+/* 9703 */ MCD_OPC_Decode, 248, 16, 105, // Opcode: UMLSLv8i8_v8i16 >+/* 9707 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9725 >+/* 9711 */ MCD_OPC_CheckPredicate, 0, 234, 120, // Skip to: 40669 >+/* 9715 */ MCD_OPC_CheckField, 21, 1, 1, 228, 120, // Skip to: 40669 >+/* 9721 */ MCD_OPC_Decode, 200, 16, 89, // Opcode: UMAXPv8i8 >+/* 9725 */ MCD_OPC_FilterValue, 10, 39, 0, // Skip to: 9768 >+/* 9729 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 9732 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 9744 >+/* 9736 */ MCD_OPC_CheckPredicate, 0, 209, 120, // Skip to: 40669 >+/* 9740 */ MCD_OPC_Decode, 193, 3, 90, // Opcode: FCVTNUv2f32 >+/* 9744 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 9756 >+/* 9748 */ MCD_OPC_CheckPredicate, 0, 197, 120, // Skip to: 40669 >+/* 9752 */ MCD_OPC_Decode, 205, 16, 110, // Opcode: UMAXVv8i8v >+/* 9756 */ MCD_OPC_FilterValue, 49, 189, 120, // Skip to: 40669 >+/* 9760 */ MCD_OPC_CheckPredicate, 0, 185, 120, // Skip to: 40669 >+/* 9764 */ MCD_OPC_Decode, 222, 16, 110, // Opcode: UMINVv8i8v >+/* 9768 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9786 >+/* 9772 */ MCD_OPC_CheckPredicate, 0, 173, 120, // Skip to: 40669 >+/* 9776 */ MCD_OPC_CheckField, 21, 1, 1, 167, 120, // Skip to: 40669 >+/* 9782 */ MCD_OPC_Decode, 217, 16, 89, // Opcode: UMINPv8i8 >+/* 9786 */ MCD_OPC_FilterValue, 14, 159, 120, // Skip to: 40669 >+/* 9790 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 9793 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9805 >+/* 9797 */ MCD_OPC_CheckPredicate, 0, 148, 120, // Skip to: 40669 >+/* 9801 */ MCD_OPC_Decode, 252, 8, 90, // Opcode: NEGv8i8 >+/* 9805 */ MCD_OPC_FilterValue, 33, 140, 120, // Skip to: 40669 >+/* 9809 */ MCD_OPC_CheckPredicate, 0, 136, 120, // Skip to: 40669 >+/* 9813 */ MCD_OPC_Decode, 175, 3, 90, // Opcode: FCVTMUv2f32 >+/* 9817 */ MCD_OPC_FilterValue, 3, 128, 120, // Skip to: 40669 >+/* 9821 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... >+/* 9824 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9842 >+/* 9828 */ MCD_OPC_CheckPredicate, 0, 117, 120, // Skip to: 40669 >+/* 9832 */ MCD_OPC_CheckField, 21, 1, 1, 111, 120, // Skip to: 40669 >+/* 9838 */ MCD_OPC_Decode, 136, 17, 85, // Opcode: UMULLv8i8_v8i16 >+/* 9842 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9860 >+/* 9846 */ MCD_OPC_CheckPredicate, 0, 99, 120, // Skip to: 40669 >+/* 9850 */ MCD_OPC_CheckField, 21, 1, 1, 93, 120, // Skip to: 40669 >+/* 9856 */ MCD_OPC_Decode, 162, 4, 89, // Opcode: FMAXNMPv2f32 >+/* 9860 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9878 >+/* 9864 */ MCD_OPC_CheckPredicate, 0, 81, 120, // Skip to: 40669 >+/* 9868 */ MCD_OPC_CheckField, 16, 6, 33, 75, 120, // Skip to: 40669 >+/* 9874 */ MCD_OPC_Decode, 149, 3, 90, // Opcode: FCVTAUv2f32 >+/* 9878 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9896 >+/* 9882 */ MCD_OPC_CheckPredicate, 0, 63, 120, // Skip to: 40669 >+/* 9886 */ MCD_OPC_CheckField, 21, 1, 1, 57, 120, // Skip to: 40669 >+/* 9892 */ MCD_OPC_Decode, 199, 2, 89, // Opcode: FADDPv2f32 >+/* 9896 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9914 >+/* 9900 */ MCD_OPC_CheckPredicate, 0, 45, 120, // Skip to: 40669 >+/* 9904 */ MCD_OPC_CheckField, 16, 6, 33, 39, 120, // Skip to: 40669 >+/* 9910 */ MCD_OPC_Decode, 172, 16, 90, // Opcode: UCVTFv2f32 >+/* 9914 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9932 >+/* 9918 */ MCD_OPC_CheckPredicate, 0, 27, 120, // Skip to: 40669 >+/* 9922 */ MCD_OPC_CheckField, 21, 1, 1, 21, 120, // Skip to: 40669 >+/* 9928 */ MCD_OPC_Decode, 249, 4, 89, // Opcode: FMULv2f32 >+/* 9932 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9950 >+/* 9936 */ MCD_OPC_CheckPredicate, 0, 9, 120, // Skip to: 40669 >+/* 9940 */ MCD_OPC_CheckField, 21, 1, 1, 3, 120, // Skip to: 40669 >+/* 9946 */ MCD_OPC_Decode, 226, 2, 89, // Opcode: FCMGEv2f32 >+/* 9950 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9968 >+/* 9954 */ MCD_OPC_CheckPredicate, 0, 247, 119, // Skip to: 40669 >+/* 9958 */ MCD_OPC_CheckField, 21, 1, 1, 241, 119, // Skip to: 40669 >+/* 9964 */ MCD_OPC_Decode, 190, 2, 89, // Opcode: FACGEv2f32 >+/* 9968 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9986 >+/* 9972 */ MCD_OPC_CheckPredicate, 0, 229, 119, // Skip to: 40669 >+/* 9976 */ MCD_OPC_CheckField, 21, 1, 1, 223, 119, // Skip to: 40669 >+/* 9982 */ MCD_OPC_Decode, 172, 4, 89, // Opcode: FMAXPv2f32 >+/* 9986 */ MCD_OPC_FilterValue, 15, 215, 119, // Skip to: 40669 >+/* 9990 */ MCD_OPC_CheckPredicate, 0, 211, 119, // Skip to: 40669 >+/* 9994 */ MCD_OPC_CheckField, 21, 1, 1, 205, 119, // Skip to: 40669 >+/* 10000 */ MCD_OPC_Decode, 155, 4, 89, // Opcode: FDIVv2f32 >+/* 10004 */ MCD_OPC_FilterValue, 2, 181, 6, // Skip to: 11725 >+/* 10008 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 10011 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 10042 >+/* 10015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10018 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10030 >+/* 10022 */ MCD_OPC_CheckPredicate, 0, 179, 119, // Skip to: 40669 >+/* 10026 */ MCD_OPC_Decode, 196, 15, 112, // Opcode: TBLv16i8One >+/* 10030 */ MCD_OPC_FilterValue, 1, 171, 119, // Skip to: 40669 >+/* 10034 */ MCD_OPC_CheckPredicate, 0, 167, 119, // Skip to: 40669 >+/* 10038 */ MCD_OPC_Decode, 240, 9, 112, // Opcode: SADDLv16i8_v8i16 >+/* 10042 */ MCD_OPC_FilterValue, 1, 90, 0, // Skip to: 10136 >+/* 10046 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10049 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10124 >+/* 10053 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 10056 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10112 >+/* 10060 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 10063 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10100 >+/* 10067 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 10070 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10088 >+/* 10074 */ MCD_OPC_CheckPredicate, 0, 127, 119, // Skip to: 40669 >+/* 10078 */ MCD_OPC_CheckField, 19, 1, 1, 121, 119, // Skip to: 40669 >+/* 10084 */ MCD_OPC_Decode, 151, 2, 113, // Opcode: DUPv2i64lane >+/* 10088 */ MCD_OPC_FilterValue, 1, 113, 119, // Skip to: 40669 >+/* 10092 */ MCD_OPC_CheckPredicate, 0, 109, 119, // Skip to: 40669 >+/* 10096 */ MCD_OPC_Decode, 155, 2, 114, // Opcode: DUPv4i32lane >+/* 10100 */ MCD_OPC_FilterValue, 1, 101, 119, // Skip to: 40669 >+/* 10104 */ MCD_OPC_CheckPredicate, 0, 97, 119, // Skip to: 40669 >+/* 10108 */ MCD_OPC_Decode, 157, 2, 115, // Opcode: DUPv8i16lane >+/* 10112 */ MCD_OPC_FilterValue, 1, 89, 119, // Skip to: 40669 >+/* 10116 */ MCD_OPC_CheckPredicate, 0, 85, 119, // Skip to: 40669 >+/* 10120 */ MCD_OPC_Decode, 147, 2, 116, // Opcode: DUPv16i8lane >+/* 10124 */ MCD_OPC_FilterValue, 1, 77, 119, // Skip to: 40669 >+/* 10128 */ MCD_OPC_CheckPredicate, 0, 73, 119, // Skip to: 40669 >+/* 10132 */ MCD_OPC_Decode, 162, 10, 112, // Opcode: SHADDv16i8 >+/* 10136 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10154 >+/* 10140 */ MCD_OPC_CheckPredicate, 0, 61, 119, // Skip to: 40669 >+/* 10144 */ MCD_OPC_CheckField, 16, 6, 32, 55, 119, // Skip to: 40669 >+/* 10150 */ MCD_OPC_Decode, 177, 9, 117, // Opcode: REV64v16i8 >+/* 10154 */ MCD_OPC_FilterValue, 3, 70, 0, // Skip to: 10228 >+/* 10158 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10161 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 10216 >+/* 10165 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10168 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 10180 >+/* 10172 */ MCD_OPC_CheckPredicate, 0, 29, 119, // Skip to: 40669 >+/* 10176 */ MCD_OPC_Decode, 146, 2, 118, // Opcode: DUPv16i8gpr >+/* 10180 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 10192 >+/* 10184 */ MCD_OPC_CheckPredicate, 0, 17, 119, // Skip to: 40669 >+/* 10188 */ MCD_OPC_Decode, 156, 2, 118, // Opcode: DUPv8i16gpr >+/* 10192 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 10204 >+/* 10196 */ MCD_OPC_CheckPredicate, 0, 5, 119, // Skip to: 40669 >+/* 10200 */ MCD_OPC_Decode, 154, 2, 118, // Opcode: DUPv4i32gpr >+/* 10204 */ MCD_OPC_FilterValue, 8, 253, 118, // Skip to: 40669 >+/* 10208 */ MCD_OPC_CheckPredicate, 0, 249, 118, // Skip to: 40669 >+/* 10212 */ MCD_OPC_Decode, 150, 2, 119, // Opcode: DUPv2i64gpr >+/* 10216 */ MCD_OPC_FilterValue, 1, 241, 118, // Skip to: 40669 >+/* 10220 */ MCD_OPC_CheckPredicate, 0, 237, 118, // Skip to: 40669 >+/* 10224 */ MCD_OPC_Decode, 158, 11, 112, // Opcode: SQADDv16i8 >+/* 10228 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 10259 >+/* 10232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10235 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10247 >+/* 10239 */ MCD_OPC_CheckPredicate, 0, 218, 118, // Skip to: 40669 >+/* 10243 */ MCD_OPC_Decode, 206, 15, 120, // Opcode: TBXv16i8One >+/* 10247 */ MCD_OPC_FilterValue, 1, 210, 118, // Skip to: 40669 >+/* 10251 */ MCD_OPC_CheckPredicate, 0, 206, 118, // Skip to: 40669 >+/* 10255 */ MCD_OPC_Decode, 246, 9, 112, // Opcode: SADDWv16i8_v8i16 >+/* 10259 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 10277 >+/* 10263 */ MCD_OPC_CheckPredicate, 0, 194, 118, // Skip to: 40669 >+/* 10267 */ MCD_OPC_CheckField, 21, 1, 1, 188, 118, // Skip to: 40669 >+/* 10273 */ MCD_OPC_Decode, 221, 12, 112, // Opcode: SRHADDv16i8 >+/* 10277 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 10314 >+/* 10281 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10284 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10296 >+/* 10288 */ MCD_OPC_CheckPredicate, 0, 169, 118, // Skip to: 40669 >+/* 10292 */ MCD_OPC_Decode, 178, 18, 112, // Opcode: UZP1v16i8 >+/* 10296 */ MCD_OPC_FilterValue, 1, 161, 118, // Skip to: 40669 >+/* 10300 */ MCD_OPC_CheckPredicate, 0, 157, 118, // Skip to: 40669 >+/* 10304 */ MCD_OPC_CheckField, 16, 5, 0, 151, 118, // Skip to: 40669 >+/* 10310 */ MCD_OPC_Decode, 170, 9, 117, // Opcode: REV16v16i8 >+/* 10314 */ MCD_OPC_FilterValue, 7, 89, 0, // Skip to: 10407 >+/* 10318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10321 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10396 >+/* 10325 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 10328 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10384 >+/* 10332 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 10335 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10372 >+/* 10339 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 10342 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10360 >+/* 10346 */ MCD_OPC_CheckPredicate, 0, 111, 118, // Skip to: 40669 >+/* 10350 */ MCD_OPC_CheckField, 19, 1, 1, 105, 118, // Skip to: 40669 >+/* 10356 */ MCD_OPC_Decode, 212, 5, 121, // Opcode: INSvi64gpr >+/* 10360 */ MCD_OPC_FilterValue, 1, 97, 118, // Skip to: 40669 >+/* 10364 */ MCD_OPC_CheckPredicate, 0, 93, 118, // Skip to: 40669 >+/* 10368 */ MCD_OPC_Decode, 210, 5, 122, // Opcode: INSvi32gpr >+/* 10372 */ MCD_OPC_FilterValue, 1, 85, 118, // Skip to: 40669 >+/* 10376 */ MCD_OPC_CheckPredicate, 0, 81, 118, // Skip to: 40669 >+/* 10380 */ MCD_OPC_Decode, 208, 5, 123, // Opcode: INSvi16gpr >+/* 10384 */ MCD_OPC_FilterValue, 1, 73, 118, // Skip to: 40669 >+/* 10388 */ MCD_OPC_CheckPredicate, 0, 69, 118, // Skip to: 40669 >+/* 10392 */ MCD_OPC_Decode, 214, 5, 124, // Opcode: INSvi8gpr >+/* 10396 */ MCD_OPC_FilterValue, 1, 61, 118, // Skip to: 40669 >+/* 10400 */ MCD_OPC_CheckPredicate, 0, 57, 118, // Skip to: 40669 >+/* 10404 */ MCD_OPC_Decode, 97, 112, // Opcode: ANDv16i8 >+/* 10407 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 10438 >+/* 10411 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10414 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10426 >+/* 10418 */ MCD_OPC_CheckPredicate, 0, 39, 118, // Skip to: 40669 >+/* 10422 */ MCD_OPC_Decode, 198, 15, 125, // Opcode: TBLv16i8Two >+/* 10426 */ MCD_OPC_FilterValue, 1, 31, 118, // Skip to: 40669 >+/* 10430 */ MCD_OPC_CheckPredicate, 0, 27, 118, // Skip to: 40669 >+/* 10434 */ MCD_OPC_Decode, 161, 13, 112, // Opcode: SSUBLv16i8_v8i16 >+/* 10438 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 10456 >+/* 10442 */ MCD_OPC_CheckPredicate, 0, 15, 118, // Skip to: 40669 >+/* 10446 */ MCD_OPC_CheckField, 21, 1, 1, 9, 118, // Skip to: 40669 >+/* 10452 */ MCD_OPC_Decode, 188, 10, 112, // Opcode: SHSUBv16i8 >+/* 10456 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 10506 >+/* 10460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10475 >+/* 10467 */ MCD_OPC_CheckPredicate, 0, 246, 117, // Skip to: 40669 >+/* 10471 */ MCD_OPC_Decode, 219, 15, 112, // Opcode: TRN1v16i8 >+/* 10475 */ MCD_OPC_FilterValue, 1, 238, 117, // Skip to: 40669 >+/* 10479 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10482 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10494 >+/* 10486 */ MCD_OPC_CheckPredicate, 0, 227, 117, // Skip to: 40669 >+/* 10490 */ MCD_OPC_Decode, 229, 9, 117, // Opcode: SADDLPv16i8_v8i16 >+/* 10494 */ MCD_OPC_FilterValue, 1, 219, 117, // Skip to: 40669 >+/* 10498 */ MCD_OPC_CheckPredicate, 0, 215, 117, // Skip to: 40669 >+/* 10502 */ MCD_OPC_Decode, 192, 18, 126, // Opcode: XTNv16i8 >+/* 10506 */ MCD_OPC_FilterValue, 11, 73, 0, // Skip to: 10583 >+/* 10510 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10513 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 10571 >+/* 10517 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 10520 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 10558 >+/* 10524 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 10527 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10545 >+/* 10531 */ MCD_OPC_CheckPredicate, 0, 182, 117, // Skip to: 40669 >+/* 10535 */ MCD_OPC_CheckField, 18, 1, 1, 176, 117, // Skip to: 40669 >+/* 10541 */ MCD_OPC_Decode, 132, 11, 127, // Opcode: SMOVvi32to64 >+/* 10545 */ MCD_OPC_FilterValue, 1, 168, 117, // Skip to: 40669 >+/* 10549 */ MCD_OPC_CheckPredicate, 0, 164, 117, // Skip to: 40669 >+/* 10553 */ MCD_OPC_Decode, 131, 11, 128, 1, // Opcode: SMOVvi16to64 >+/* 10558 */ MCD_OPC_FilterValue, 1, 155, 117, // Skip to: 40669 >+/* 10562 */ MCD_OPC_CheckPredicate, 0, 151, 117, // Skip to: 40669 >+/* 10566 */ MCD_OPC_Decode, 134, 11, 129, 1, // Opcode: SMOVvi8to64 >+/* 10571 */ MCD_OPC_FilterValue, 1, 142, 117, // Skip to: 40669 >+/* 10575 */ MCD_OPC_CheckPredicate, 0, 138, 117, // Skip to: 40669 >+/* 10579 */ MCD_OPC_Decode, 192, 12, 112, // Opcode: SQSUBv16i8 >+/* 10583 */ MCD_OPC_FilterValue, 12, 28, 0, // Skip to: 10615 >+/* 10587 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10590 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10603 >+/* 10594 */ MCD_OPC_CheckPredicate, 0, 119, 117, // Skip to: 40669 >+/* 10598 */ MCD_OPC_Decode, 208, 15, 130, 1, // Opcode: TBXv16i8Two >+/* 10603 */ MCD_OPC_FilterValue, 1, 110, 117, // Skip to: 40669 >+/* 10607 */ MCD_OPC_CheckPredicate, 0, 106, 117, // Skip to: 40669 >+/* 10611 */ MCD_OPC_Decode, 167, 13, 112, // Opcode: SSUBWv16i8_v8i16 >+/* 10615 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 10633 >+/* 10619 */ MCD_OPC_CheckPredicate, 0, 94, 117, // Skip to: 40669 >+/* 10623 */ MCD_OPC_CheckField, 21, 1, 1, 88, 117, // Skip to: 40669 >+/* 10629 */ MCD_OPC_Decode, 190, 1, 112, // Opcode: CMGTv16i8 >+/* 10633 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 10684 >+/* 10637 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10640 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10652 >+/* 10644 */ MCD_OPC_CheckPredicate, 0, 69, 117, // Skip to: 40669 >+/* 10648 */ MCD_OPC_Decode, 198, 18, 112, // Opcode: ZIP1v16i8 >+/* 10652 */ MCD_OPC_FilterValue, 1, 61, 117, // Skip to: 40669 >+/* 10656 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10659 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10671 >+/* 10663 */ MCD_OPC_CheckPredicate, 0, 50, 117, // Skip to: 40669 >+/* 10667 */ MCD_OPC_Decode, 181, 15, 126, // Opcode: SUQADDv16i8 >+/* 10671 */ MCD_OPC_FilterValue, 16, 42, 117, // Skip to: 40669 >+/* 10675 */ MCD_OPC_CheckPredicate, 0, 38, 117, // Skip to: 40669 >+/* 10679 */ MCD_OPC_Decode, 235, 9, 131, 1, // Opcode: SADDLVv16i8v >+/* 10684 */ MCD_OPC_FilterValue, 15, 34, 0, // Skip to: 10722 >+/* 10688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10691 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10710 >+/* 10695 */ MCD_OPC_CheckPredicate, 0, 18, 117, // Skip to: 40669 >+/* 10699 */ MCD_OPC_CheckField, 16, 4, 8, 12, 117, // Skip to: 40669 >+/* 10705 */ MCD_OPC_Decode, 251, 16, 132, 1, // Opcode: UMOVvi64 >+/* 10710 */ MCD_OPC_FilterValue, 1, 3, 117, // Skip to: 40669 >+/* 10714 */ MCD_OPC_CheckPredicate, 0, 255, 116, // Skip to: 40669 >+/* 10718 */ MCD_OPC_Decode, 174, 1, 112, // Opcode: CMGEv16i8 >+/* 10722 */ MCD_OPC_FilterValue, 16, 27, 0, // Skip to: 10753 >+/* 10726 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10729 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10742 >+/* 10733 */ MCD_OPC_CheckPredicate, 0, 236, 116, // Skip to: 40669 >+/* 10737 */ MCD_OPC_Decode, 197, 15, 133, 1, // Opcode: TBLv16i8Three >+/* 10742 */ MCD_OPC_FilterValue, 1, 227, 116, // Skip to: 40669 >+/* 10746 */ MCD_OPC_CheckPredicate, 0, 223, 116, // Skip to: 40669 >+/* 10750 */ MCD_OPC_Decode, 36, 120, // Opcode: ADDHNv8i16_v16i8 >+/* 10753 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 10771 >+/* 10757 */ MCD_OPC_CheckPredicate, 0, 212, 116, // Skip to: 40669 >+/* 10761 */ MCD_OPC_CheckField, 21, 1, 1, 206, 116, // Skip to: 40669 >+/* 10767 */ MCD_OPC_Decode, 137, 13, 112, // Opcode: SSHLv16i8 >+/* 10771 */ MCD_OPC_FilterValue, 18, 38, 0, // Skip to: 10813 >+/* 10775 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 10778 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 10790 >+/* 10782 */ MCD_OPC_CheckPredicate, 0, 187, 116, // Skip to: 40669 >+/* 10786 */ MCD_OPC_Decode, 144, 1, 117, // Opcode: CLSv16i8 >+/* 10790 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 10802 >+/* 10794 */ MCD_OPC_CheckPredicate, 0, 175, 116, // Skip to: 40669 >+/* 10798 */ MCD_OPC_Decode, 203, 12, 126, // Opcode: SQXTNv16i8 >+/* 10802 */ MCD_OPC_FilterValue, 40, 167, 116, // Skip to: 40669 >+/* 10806 */ MCD_OPC_CheckPredicate, 1, 163, 116, // Skip to: 40669 >+/* 10810 */ MCD_OPC_Decode, 82, 126, // Opcode: AESErr >+/* 10813 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 10831 >+/* 10817 */ MCD_OPC_CheckPredicate, 0, 152, 116, // Skip to: 40669 >+/* 10821 */ MCD_OPC_CheckField, 21, 1, 1, 146, 116, // Skip to: 40669 >+/* 10827 */ MCD_OPC_Decode, 156, 12, 112, // Opcode: SQSHLv16i8 >+/* 10831 */ MCD_OPC_FilterValue, 20, 28, 0, // Skip to: 10863 >+/* 10835 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10838 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10851 >+/* 10842 */ MCD_OPC_CheckPredicate, 0, 127, 116, // Skip to: 40669 >+/* 10846 */ MCD_OPC_Decode, 207, 15, 134, 1, // Opcode: TBXv16i8Three >+/* 10851 */ MCD_OPC_FilterValue, 1, 118, 116, // Skip to: 40669 >+/* 10855 */ MCD_OPC_CheckPredicate, 0, 114, 116, // Skip to: 40669 >+/* 10859 */ MCD_OPC_Decode, 199, 9, 120, // Opcode: SABALv16i8_v8i16 >+/* 10863 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 10881 >+/* 10867 */ MCD_OPC_CheckPredicate, 0, 102, 116, // Skip to: 40669 >+/* 10871 */ MCD_OPC_CheckField, 21, 1, 1, 96, 116, // Skip to: 40669 >+/* 10877 */ MCD_OPC_Decode, 235, 12, 112, // Opcode: SRSHLv16i8 >+/* 10881 */ MCD_OPC_FilterValue, 22, 45, 0, // Skip to: 10930 >+/* 10885 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10888 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10900 >+/* 10892 */ MCD_OPC_CheckPredicate, 0, 77, 116, // Skip to: 40669 >+/* 10896 */ MCD_OPC_Decode, 185, 18, 112, // Opcode: UZP2v16i8 >+/* 10900 */ MCD_OPC_FilterValue, 1, 69, 116, // Skip to: 40669 >+/* 10904 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10907 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10919 >+/* 10911 */ MCD_OPC_CheckPredicate, 0, 58, 116, // Skip to: 40669 >+/* 10915 */ MCD_OPC_Decode, 246, 1, 117, // Opcode: CNTv16i8 >+/* 10919 */ MCD_OPC_FilterValue, 8, 50, 116, // Skip to: 40669 >+/* 10923 */ MCD_OPC_CheckPredicate, 1, 46, 116, // Skip to: 40669 >+/* 10927 */ MCD_OPC_Decode, 81, 126, // Opcode: AESDrr >+/* 10930 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 10948 >+/* 10934 */ MCD_OPC_CheckPredicate, 0, 35, 116, // Skip to: 40669 >+/* 10938 */ MCD_OPC_CheckField, 21, 1, 1, 29, 116, // Skip to: 40669 >+/* 10944 */ MCD_OPC_Decode, 240, 11, 112, // Opcode: SQRSHLv16i8 >+/* 10948 */ MCD_OPC_FilterValue, 24, 28, 0, // Skip to: 10980 >+/* 10952 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10955 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10968 >+/* 10959 */ MCD_OPC_CheckPredicate, 0, 10, 116, // Skip to: 40669 >+/* 10963 */ MCD_OPC_Decode, 195, 15, 135, 1, // Opcode: TBLv16i8Four >+/* 10968 */ MCD_OPC_FilterValue, 1, 1, 116, // Skip to: 40669 >+/* 10972 */ MCD_OPC_CheckPredicate, 0, 253, 115, // Skip to: 40669 >+/* 10976 */ MCD_OPC_Decode, 153, 15, 120, // Opcode: SUBHNv8i16_v16i8 >+/* 10980 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 10998 >+/* 10984 */ MCD_OPC_CheckPredicate, 0, 241, 115, // Skip to: 40669 >+/* 10988 */ MCD_OPC_CheckField, 21, 1, 1, 235, 115, // Skip to: 40669 >+/* 10994 */ MCD_OPC_Decode, 214, 10, 112, // Opcode: SMAXv16i8 >+/* 10998 */ MCD_OPC_FilterValue, 26, 57, 0, // Skip to: 11059 >+/* 11002 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 11005 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11017 >+/* 11009 */ MCD_OPC_CheckPredicate, 0, 216, 115, // Skip to: 40669 >+/* 11013 */ MCD_OPC_Decode, 226, 15, 112, // Opcode: TRN2v16i8 >+/* 11017 */ MCD_OPC_FilterValue, 1, 208, 115, // Skip to: 40669 >+/* 11021 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 11024 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11036 >+/* 11028 */ MCD_OPC_CheckPredicate, 0, 197, 115, // Skip to: 40669 >+/* 11032 */ MCD_OPC_Decode, 223, 9, 126, // Opcode: SADALPv16i8_v8i16 >+/* 11036 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11048 >+/* 11040 */ MCD_OPC_CheckPredicate, 0, 185, 115, // Skip to: 40669 >+/* 11044 */ MCD_OPC_Decode, 199, 3, 126, // Opcode: FCVTNv8i16 >+/* 11048 */ MCD_OPC_FilterValue, 8, 177, 115, // Skip to: 40669 >+/* 11052 */ MCD_OPC_CheckPredicate, 1, 173, 115, // Skip to: 40669 >+/* 11056 */ MCD_OPC_Decode, 84, 117, // Opcode: AESMCrr >+/* 11059 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 11077 >+/* 11063 */ MCD_OPC_CheckPredicate, 0, 162, 115, // Skip to: 40669 >+/* 11067 */ MCD_OPC_CheckField, 21, 1, 1, 156, 115, // Skip to: 40669 >+/* 11073 */ MCD_OPC_Decode, 232, 10, 112, // Opcode: SMINv16i8 >+/* 11077 */ MCD_OPC_FilterValue, 28, 28, 0, // Skip to: 11109 >+/* 11081 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 11084 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11097 >+/* 11088 */ MCD_OPC_CheckPredicate, 0, 137, 115, // Skip to: 40669 >+/* 11092 */ MCD_OPC_Decode, 205, 15, 136, 1, // Opcode: TBXv16i8Four >+/* 11097 */ MCD_OPC_FilterValue, 1, 128, 115, // Skip to: 40669 >+/* 11101 */ MCD_OPC_CheckPredicate, 0, 124, 115, // Skip to: 40669 >+/* 11105 */ MCD_OPC_Decode, 211, 9, 112, // Opcode: SABDLv16i8_v8i16 >+/* 11109 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 11127 >+/* 11113 */ MCD_OPC_CheckPredicate, 0, 112, 115, // Skip to: 40669 >+/* 11117 */ MCD_OPC_CheckField, 21, 1, 1, 106, 115, // Skip to: 40669 >+/* 11123 */ MCD_OPC_Decode, 217, 9, 112, // Opcode: SABDv16i8 >+/* 11127 */ MCD_OPC_FilterValue, 30, 57, 0, // Skip to: 11188 >+/* 11131 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 11134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11146 >+/* 11138 */ MCD_OPC_CheckPredicate, 0, 87, 115, // Skip to: 40669 >+/* 11142 */ MCD_OPC_Decode, 205, 18, 112, // Opcode: ZIP2v16i8 >+/* 11146 */ MCD_OPC_FilterValue, 1, 79, 115, // Skip to: 40669 >+/* 11150 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 11153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11165 >+/* 11157 */ MCD_OPC_CheckPredicate, 0, 68, 115, // Skip to: 40669 >+/* 11161 */ MCD_OPC_Decode, 147, 11, 117, // Opcode: SQABSv16i8 >+/* 11165 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11177 >+/* 11169 */ MCD_OPC_CheckPredicate, 0, 56, 115, // Skip to: 40669 >+/* 11173 */ MCD_OPC_Decode, 159, 3, 117, // Opcode: FCVTLv8i16 >+/* 11177 */ MCD_OPC_FilterValue, 8, 48, 115, // Skip to: 40669 >+/* 11181 */ MCD_OPC_CheckPredicate, 1, 44, 115, // Skip to: 40669 >+/* 11185 */ MCD_OPC_Decode, 83, 117, // Opcode: AESIMCrr >+/* 11188 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 11206 >+/* 11192 */ MCD_OPC_CheckPredicate, 0, 33, 115, // Skip to: 40669 >+/* 11196 */ MCD_OPC_CheckField, 21, 1, 1, 27, 115, // Skip to: 40669 >+/* 11202 */ MCD_OPC_Decode, 205, 9, 120, // Opcode: SABAv16i8 >+/* 11206 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 11224 >+/* 11210 */ MCD_OPC_CheckPredicate, 0, 15, 115, // Skip to: 40669 >+/* 11214 */ MCD_OPC_CheckField, 21, 1, 1, 9, 115, // Skip to: 40669 >+/* 11220 */ MCD_OPC_Decode, 238, 10, 120, // Opcode: SMLALv16i8_v8i16 >+/* 11224 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 11241 >+/* 11228 */ MCD_OPC_CheckPredicate, 0, 253, 114, // Skip to: 40669 >+/* 11232 */ MCD_OPC_CheckField, 21, 1, 1, 247, 114, // Skip to: 40669 >+/* 11238 */ MCD_OPC_Decode, 69, 112, // Opcode: ADDv16i8 >+/* 11241 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 11272 >+/* 11245 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 11248 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11260 >+/* 11252 */ MCD_OPC_CheckPredicate, 0, 229, 114, // Skip to: 40669 >+/* 11256 */ MCD_OPC_Decode, 191, 1, 117, // Opcode: CMGTv16i8rz >+/* 11260 */ MCD_OPC_FilterValue, 33, 221, 114, // Skip to: 40669 >+/* 11264 */ MCD_OPC_CheckPredicate, 0, 217, 114, // Skip to: 40669 >+/* 11268 */ MCD_OPC_Decode, 169, 5, 117, // Opcode: FRINTNv4f32 >+/* 11272 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 11290 >+/* 11276 */ MCD_OPC_CheckPredicate, 0, 205, 114, // Skip to: 40669 >+/* 11280 */ MCD_OPC_CheckField, 21, 1, 1, 199, 114, // Skip to: 40669 >+/* 11286 */ MCD_OPC_Decode, 238, 1, 112, // Opcode: CMTSTv16i8 >+/* 11290 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 11308 >+/* 11294 */ MCD_OPC_CheckPredicate, 0, 187, 114, // Skip to: 40669 >+/* 11298 */ MCD_OPC_CheckField, 21, 1, 1, 181, 114, // Skip to: 40669 >+/* 11304 */ MCD_OPC_Decode, 180, 8, 120, // Opcode: MLAv16i8 >+/* 11308 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 11339 >+/* 11312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 11315 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11327 >+/* 11319 */ MCD_OPC_CheckPredicate, 0, 162, 114, // Skip to: 40669 >+/* 11323 */ MCD_OPC_Decode, 159, 1, 117, // Opcode: CMEQv16i8rz >+/* 11327 */ MCD_OPC_FilterValue, 33, 154, 114, // Skip to: 40669 >+/* 11331 */ MCD_OPC_CheckPredicate, 0, 150, 114, // Skip to: 40669 >+/* 11335 */ MCD_OPC_Decode, 164, 5, 117, // Opcode: FRINTMv4f32 >+/* 11339 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 11357 >+/* 11343 */ MCD_OPC_CheckPredicate, 0, 138, 114, // Skip to: 40669 >+/* 11347 */ MCD_OPC_CheckField, 21, 1, 1, 132, 114, // Skip to: 40669 >+/* 11353 */ MCD_OPC_Decode, 229, 8, 112, // Opcode: MULv16i8 >+/* 11357 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 11375 >+/* 11361 */ MCD_OPC_CheckPredicate, 0, 120, 114, // Skip to: 40669 >+/* 11365 */ MCD_OPC_CheckField, 21, 1, 1, 114, 114, // Skip to: 40669 >+/* 11371 */ MCD_OPC_Decode, 248, 10, 120, // Opcode: SMLSLv16i8_v8i16 >+/* 11375 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 11393 >+/* 11379 */ MCD_OPC_CheckPredicate, 0, 102, 114, // Skip to: 40669 >+/* 11383 */ MCD_OPC_CheckField, 21, 1, 1, 96, 114, // Skip to: 40669 >+/* 11389 */ MCD_OPC_Decode, 203, 10, 112, // Opcode: SMAXPv16i8 >+/* 11393 */ MCD_OPC_FilterValue, 42, 53, 0, // Skip to: 11450 >+/* 11397 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 11400 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11412 >+/* 11404 */ MCD_OPC_CheckPredicate, 0, 77, 114, // Skip to: 40669 >+/* 11408 */ MCD_OPC_Decode, 230, 1, 117, // Opcode: CMLTv16i8rz >+/* 11412 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11424 >+/* 11416 */ MCD_OPC_CheckPredicate, 0, 65, 114, // Skip to: 40669 >+/* 11420 */ MCD_OPC_Decode, 186, 3, 117, // Opcode: FCVTNSv4f32 >+/* 11424 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 11437 >+/* 11428 */ MCD_OPC_CheckPredicate, 0, 53, 114, // Skip to: 40669 >+/* 11432 */ MCD_OPC_Decode, 209, 10, 137, 1, // Opcode: SMAXVv16i8v >+/* 11437 */ MCD_OPC_FilterValue, 49, 44, 114, // Skip to: 40669 >+/* 11441 */ MCD_OPC_CheckPredicate, 0, 40, 114, // Skip to: 40669 >+/* 11445 */ MCD_OPC_Decode, 227, 10, 137, 1, // Opcode: SMINVv16i8v >+/* 11450 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 11468 >+/* 11454 */ MCD_OPC_CheckPredicate, 0, 27, 114, // Skip to: 40669 >+/* 11458 */ MCD_OPC_CheckField, 21, 1, 1, 21, 114, // Skip to: 40669 >+/* 11464 */ MCD_OPC_Decode, 221, 10, 112, // Opcode: SMINPv16i8 >+/* 11468 */ MCD_OPC_FilterValue, 46, 38, 0, // Skip to: 11510 >+/* 11472 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 11475 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 11486 >+/* 11479 */ MCD_OPC_CheckPredicate, 0, 2, 114, // Skip to: 40669 >+/* 11483 */ MCD_OPC_Decode, 20, 117, // Opcode: ABSv16i8 >+/* 11486 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11498 >+/* 11490 */ MCD_OPC_CheckPredicate, 0, 247, 113, // Skip to: 40669 >+/* 11494 */ MCD_OPC_Decode, 168, 3, 117, // Opcode: FCVTMSv4f32 >+/* 11498 */ MCD_OPC_FilterValue, 49, 239, 113, // Skip to: 40669 >+/* 11502 */ MCD_OPC_CheckPredicate, 0, 235, 113, // Skip to: 40669 >+/* 11506 */ MCD_OPC_Decode, 55, 137, 1, // Opcode: ADDVv16i8v >+/* 11510 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 11527 >+/* 11514 */ MCD_OPC_CheckPredicate, 0, 223, 113, // Skip to: 40669 >+/* 11518 */ MCD_OPC_CheckField, 21, 1, 1, 217, 113, // Skip to: 40669 >+/* 11524 */ MCD_OPC_Decode, 38, 112, // Opcode: ADDPv16i8 >+/* 11527 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 11545 >+/* 11531 */ MCD_OPC_CheckPredicate, 0, 206, 113, // Skip to: 40669 >+/* 11535 */ MCD_OPC_CheckField, 21, 1, 1, 200, 113, // Skip to: 40669 >+/* 11541 */ MCD_OPC_Decode, 137, 11, 112, // Opcode: SMULLv16i8_v8i16 >+/* 11545 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 11563 >+/* 11549 */ MCD_OPC_CheckPredicate, 0, 188, 113, // Skip to: 40669 >+/* 11553 */ MCD_OPC_CheckField, 21, 1, 1, 182, 113, // Skip to: 40669 >+/* 11559 */ MCD_OPC_Decode, 171, 4, 112, // Opcode: FMAXNMv4f32 >+/* 11563 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 11581 >+/* 11567 */ MCD_OPC_CheckPredicate, 0, 170, 113, // Skip to: 40669 >+/* 11571 */ MCD_OPC_CheckField, 16, 6, 33, 164, 113, // Skip to: 40669 >+/* 11577 */ MCD_OPC_Decode, 142, 3, 117, // Opcode: FCVTASv4f32 >+/* 11581 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 11599 >+/* 11585 */ MCD_OPC_CheckPredicate, 0, 152, 113, // Skip to: 40669 >+/* 11589 */ MCD_OPC_CheckField, 21, 1, 1, 146, 113, // Skip to: 40669 >+/* 11595 */ MCD_OPC_Decode, 210, 4, 120, // Opcode: FMLAv4f32 >+/* 11599 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 11617 >+/* 11603 */ MCD_OPC_CheckPredicate, 0, 134, 113, // Skip to: 40669 >+/* 11607 */ MCD_OPC_CheckField, 21, 1, 1, 128, 113, // Skip to: 40669 >+/* 11613 */ MCD_OPC_Decode, 207, 2, 112, // Opcode: FADDv4f32 >+/* 11617 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 11635 >+/* 11621 */ MCD_OPC_CheckPredicate, 0, 116, 113, // Skip to: 40669 >+/* 11625 */ MCD_OPC_CheckField, 16, 6, 33, 110, 113, // Skip to: 40669 >+/* 11631 */ MCD_OPC_Decode, 146, 10, 117, // Opcode: SCVTFv4f32 >+/* 11635 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 11653 >+/* 11639 */ MCD_OPC_CheckPredicate, 0, 98, 113, // Skip to: 40669 >+/* 11643 */ MCD_OPC_CheckField, 21, 1, 1, 92, 113, // Skip to: 40669 >+/* 11649 */ MCD_OPC_Decode, 245, 4, 112, // Opcode: FMULXv4f32 >+/* 11653 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 11671 >+/* 11657 */ MCD_OPC_CheckPredicate, 0, 80, 113, // Skip to: 40669 >+/* 11661 */ MCD_OPC_CheckField, 21, 1, 1, 74, 113, // Skip to: 40669 >+/* 11667 */ MCD_OPC_Decode, 145, 9, 112, // Opcode: PMULLv16i8 >+/* 11671 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 11689 >+/* 11675 */ MCD_OPC_CheckPredicate, 0, 62, 113, // Skip to: 40669 >+/* 11679 */ MCD_OPC_CheckField, 21, 1, 1, 56, 113, // Skip to: 40669 >+/* 11685 */ MCD_OPC_Decode, 220, 2, 112, // Opcode: FCMEQv4f32 >+/* 11689 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 11707 >+/* 11693 */ MCD_OPC_CheckPredicate, 0, 44, 113, // Skip to: 40669 >+/* 11697 */ MCD_OPC_CheckField, 21, 1, 1, 38, 113, // Skip to: 40669 >+/* 11703 */ MCD_OPC_Decode, 181, 4, 112, // Opcode: FMAXv4f32 >+/* 11707 */ MCD_OPC_FilterValue, 63, 30, 113, // Skip to: 40669 >+/* 11711 */ MCD_OPC_CheckPredicate, 0, 26, 113, // Skip to: 40669 >+/* 11715 */ MCD_OPC_CheckField, 21, 1, 1, 20, 113, // Skip to: 40669 >+/* 11721 */ MCD_OPC_Decode, 147, 5, 112, // Opcode: FRECPSv4f32 >+/* 11725 */ MCD_OPC_FilterValue, 3, 12, 113, // Skip to: 40669 >+/* 11729 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 11732 */ MCD_OPC_FilterValue, 0, 60, 2, // Skip to: 12308 >+/* 11736 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 11739 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 12040 >+/* 11743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 11746 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11759 >+/* 11750 */ MCD_OPC_CheckPredicate, 0, 243, 112, // Skip to: 40669 >+/* 11754 */ MCD_OPC_Decode, 175, 2, 138, 1, // Opcode: EXTv16i8 >+/* 11759 */ MCD_OPC_FilterValue, 1, 234, 112, // Skip to: 40669 >+/* 11763 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... >+/* 11766 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11778 >+/* 11770 */ MCD_OPC_CheckPredicate, 0, 223, 112, // Skip to: 40669 >+/* 11774 */ MCD_OPC_Decode, 146, 16, 112, // Opcode: UADDLv16i8_v8i16 >+/* 11778 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11796 >+/* 11782 */ MCD_OPC_CheckPredicate, 0, 211, 112, // Skip to: 40669 >+/* 11786 */ MCD_OPC_CheckField, 16, 5, 0, 205, 112, // Skip to: 40669 >+/* 11792 */ MCD_OPC_Decode, 173, 9, 117, // Opcode: REV32v16i8 >+/* 11796 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 11808 >+/* 11800 */ MCD_OPC_CheckPredicate, 0, 193, 112, // Skip to: 40669 >+/* 11804 */ MCD_OPC_Decode, 152, 16, 112, // Opcode: UADDWv16i8_v8i16 >+/* 11808 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11820 >+/* 11812 */ MCD_OPC_CheckPredicate, 0, 181, 112, // Skip to: 40669 >+/* 11816 */ MCD_OPC_Decode, 166, 18, 112, // Opcode: USUBLv16i8_v8i16 >+/* 11820 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 11851 >+/* 11824 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 11827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11839 >+/* 11831 */ MCD_OPC_CheckPredicate, 0, 162, 112, // Skip to: 40669 >+/* 11835 */ MCD_OPC_Decode, 135, 16, 117, // Opcode: UADDLPv16i8_v8i16 >+/* 11839 */ MCD_OPC_FilterValue, 1, 154, 112, // Skip to: 40669 >+/* 11843 */ MCD_OPC_CheckPredicate, 0, 150, 112, // Skip to: 40669 >+/* 11847 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: SQXTUNv16i8 >+/* 11851 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 11863 >+/* 11855 */ MCD_OPC_CheckPredicate, 0, 138, 112, // Skip to: 40669 >+/* 11859 */ MCD_OPC_Decode, 172, 18, 112, // Opcode: USUBWv16i8_v8i16 >+/* 11863 */ MCD_OPC_FilterValue, 7, 40, 0, // Skip to: 11907 >+/* 11867 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 11870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11882 >+/* 11874 */ MCD_OPC_CheckPredicate, 0, 119, 112, // Skip to: 40669 >+/* 11878 */ MCD_OPC_Decode, 147, 18, 126, // Opcode: USQADDv16i8 >+/* 11882 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11894 >+/* 11886 */ MCD_OPC_CheckPredicate, 0, 107, 112, // Skip to: 40669 >+/* 11890 */ MCD_OPC_Decode, 168, 10, 117, // Opcode: SHLLv16i8 >+/* 11894 */ MCD_OPC_FilterValue, 16, 99, 112, // Skip to: 40669 >+/* 11898 */ MCD_OPC_CheckPredicate, 0, 95, 112, // Skip to: 40669 >+/* 11902 */ MCD_OPC_Decode, 141, 16, 131, 1, // Opcode: UADDLVv16i8v >+/* 11907 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11919 >+/* 11911 */ MCD_OPC_CheckPredicate, 0, 82, 112, // Skip to: 40669 >+/* 11915 */ MCD_OPC_Decode, 160, 9, 120, // Opcode: RADDHNv8i16_v16i8 >+/* 11919 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 11950 >+/* 11923 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 11926 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11938 >+/* 11930 */ MCD_OPC_CheckPredicate, 0, 63, 112, // Skip to: 40669 >+/* 11934 */ MCD_OPC_Decode, 152, 1, 117, // Opcode: CLZv16i8 >+/* 11938 */ MCD_OPC_FilterValue, 1, 55, 112, // Skip to: 40669 >+/* 11942 */ MCD_OPC_CheckPredicate, 0, 51, 112, // Skip to: 40669 >+/* 11946 */ MCD_OPC_Decode, 210, 17, 126, // Opcode: UQXTNv16i8 >+/* 11950 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11962 >+/* 11954 */ MCD_OPC_CheckPredicate, 0, 39, 112, // Skip to: 40669 >+/* 11958 */ MCD_OPC_Decode, 233, 15, 120, // Opcode: UABALv16i8_v8i16 >+/* 11962 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 11980 >+/* 11966 */ MCD_OPC_CheckPredicate, 0, 27, 112, // Skip to: 40669 >+/* 11970 */ MCD_OPC_CheckField, 16, 5, 0, 21, 112, // Skip to: 40669 >+/* 11976 */ MCD_OPC_Decode, 253, 8, 117, // Opcode: NOTv16i8 >+/* 11980 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11992 >+/* 11984 */ MCD_OPC_CheckPredicate, 0, 9, 112, // Skip to: 40669 >+/* 11988 */ MCD_OPC_Decode, 197, 9, 120, // Opcode: RSUBHNv8i16_v16i8 >+/* 11992 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12010 >+/* 11996 */ MCD_OPC_CheckPredicate, 0, 253, 111, // Skip to: 40669 >+/* 12000 */ MCD_OPC_CheckField, 16, 5, 0, 247, 111, // Skip to: 40669 >+/* 12006 */ MCD_OPC_Decode, 129, 16, 126, // Opcode: UADALPv16i8_v8i16 >+/* 12010 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12022 >+/* 12014 */ MCD_OPC_CheckPredicate, 0, 235, 111, // Skip to: 40669 >+/* 12018 */ MCD_OPC_Decode, 245, 15, 112, // Opcode: UABDLv16i8_v8i16 >+/* 12022 */ MCD_OPC_FilterValue, 15, 227, 111, // Skip to: 40669 >+/* 12026 */ MCD_OPC_CheckPredicate, 0, 223, 111, // Skip to: 40669 >+/* 12030 */ MCD_OPC_CheckField, 16, 5, 0, 217, 111, // Skip to: 40669 >+/* 12036 */ MCD_OPC_Decode, 217, 11, 117, // Opcode: SQNEGv16i8 >+/* 12040 */ MCD_OPC_FilterValue, 1, 209, 111, // Skip to: 40669 >+/* 12044 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... >+/* 12047 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12065 >+/* 12051 */ MCD_OPC_CheckPredicate, 0, 198, 111, // Skip to: 40669 >+/* 12055 */ MCD_OPC_CheckField, 21, 1, 1, 192, 111, // Skip to: 40669 >+/* 12061 */ MCD_OPC_Decode, 229, 16, 120, // Opcode: UMLALv16i8_v8i16 >+/* 12065 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 12096 >+/* 12069 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 12072 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12084 >+/* 12076 */ MCD_OPC_CheckPredicate, 0, 173, 111, // Skip to: 40669 >+/* 12080 */ MCD_OPC_Decode, 175, 1, 117, // Opcode: CMGEv16i8rz >+/* 12084 */ MCD_OPC_FilterValue, 33, 165, 111, // Skip to: 40669 >+/* 12088 */ MCD_OPC_CheckPredicate, 0, 161, 111, // Skip to: 40669 >+/* 12092 */ MCD_OPC_Decode, 154, 5, 117, // Opcode: FRINTAv4f32 >+/* 12096 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 12127 >+/* 12100 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 12103 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12115 >+/* 12107 */ MCD_OPC_CheckPredicate, 0, 142, 111, // Skip to: 40669 >+/* 12111 */ MCD_OPC_Decode, 222, 1, 117, // Opcode: CMLEv16i8rz >+/* 12115 */ MCD_OPC_FilterValue, 33, 134, 111, // Skip to: 40669 >+/* 12119 */ MCD_OPC_CheckPredicate, 0, 130, 111, // Skip to: 40669 >+/* 12123 */ MCD_OPC_Decode, 179, 5, 117, // Opcode: FRINTXv4f32 >+/* 12127 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12145 >+/* 12131 */ MCD_OPC_CheckPredicate, 0, 118, 111, // Skip to: 40669 >+/* 12135 */ MCD_OPC_CheckField, 21, 1, 1, 112, 111, // Skip to: 40669 >+/* 12141 */ MCD_OPC_Decode, 239, 16, 120, // Opcode: UMLSLv16i8_v8i16 >+/* 12145 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 12190 >+/* 12149 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 12152 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12164 >+/* 12156 */ MCD_OPC_CheckPredicate, 0, 93, 111, // Skip to: 40669 >+/* 12160 */ MCD_OPC_Decode, 195, 3, 117, // Opcode: FCVTNUv4f32 >+/* 12164 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 12177 >+/* 12168 */ MCD_OPC_CheckPredicate, 0, 81, 111, // Skip to: 40669 >+/* 12172 */ MCD_OPC_Decode, 201, 16, 137, 1, // Opcode: UMAXVv16i8v >+/* 12177 */ MCD_OPC_FilterValue, 49, 72, 111, // Skip to: 40669 >+/* 12181 */ MCD_OPC_CheckPredicate, 0, 68, 111, // Skip to: 40669 >+/* 12185 */ MCD_OPC_Decode, 218, 16, 137, 1, // Opcode: UMINVv16i8v >+/* 12190 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 12221 >+/* 12194 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 12197 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12209 >+/* 12201 */ MCD_OPC_CheckPredicate, 0, 48, 111, // Skip to: 40669 >+/* 12205 */ MCD_OPC_Decode, 245, 8, 117, // Opcode: NEGv16i8 >+/* 12209 */ MCD_OPC_FilterValue, 33, 40, 111, // Skip to: 40669 >+/* 12213 */ MCD_OPC_CheckPredicate, 0, 36, 111, // Skip to: 40669 >+/* 12217 */ MCD_OPC_Decode, 177, 3, 117, // Opcode: FCVTMUv4f32 >+/* 12221 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12239 >+/* 12225 */ MCD_OPC_CheckPredicate, 0, 24, 111, // Skip to: 40669 >+/* 12229 */ MCD_OPC_CheckField, 21, 1, 1, 18, 111, // Skip to: 40669 >+/* 12235 */ MCD_OPC_Decode, 255, 16, 112, // Opcode: UMULLv16i8_v8i16 >+/* 12239 */ MCD_OPC_FilterValue, 9, 28, 0, // Skip to: 12271 >+/* 12243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 12246 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12258 >+/* 12250 */ MCD_OPC_CheckPredicate, 0, 255, 110, // Skip to: 40669 >+/* 12254 */ MCD_OPC_Decode, 151, 3, 117, // Opcode: FCVTAUv4f32 >+/* 12258 */ MCD_OPC_FilterValue, 48, 247, 110, // Skip to: 40669 >+/* 12262 */ MCD_OPC_CheckPredicate, 0, 243, 110, // Skip to: 40669 >+/* 12266 */ MCD_OPC_Decode, 168, 4, 139, 1, // Opcode: FMAXNMVv4i32v >+/* 12271 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12289 >+/* 12275 */ MCD_OPC_CheckPredicate, 0, 230, 110, // Skip to: 40669 >+/* 12279 */ MCD_OPC_CheckField, 16, 6, 33, 224, 110, // Skip to: 40669 >+/* 12285 */ MCD_OPC_Decode, 176, 16, 117, // Opcode: UCVTFv4f32 >+/* 12289 */ MCD_OPC_FilterValue, 15, 216, 110, // Skip to: 40669 >+/* 12293 */ MCD_OPC_CheckPredicate, 0, 212, 110, // Skip to: 40669 >+/* 12297 */ MCD_OPC_CheckField, 16, 6, 48, 206, 110, // Skip to: 40669 >+/* 12303 */ MCD_OPC_Decode, 178, 4, 139, 1, // Opcode: FMAXVv4i32v >+/* 12308 */ MCD_OPC_FilterValue, 1, 197, 110, // Skip to: 40669 >+/* 12312 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 12315 */ MCD_OPC_FilterValue, 0, 43, 1, // Skip to: 12618 >+/* 12319 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 12322 */ MCD_OPC_FilterValue, 0, 93, 0, // Skip to: 12419 >+/* 12326 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 12329 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 12406 >+/* 12333 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 12336 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 12387 >+/* 12340 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 12343 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 12368 >+/* 12347 */ MCD_OPC_CheckPredicate, 0, 158, 110, // Skip to: 40669 >+/* 12351 */ MCD_OPC_CheckField, 19, 1, 1, 152, 110, // Skip to: 40669 >+/* 12357 */ MCD_OPC_CheckField, 11, 3, 0, 146, 110, // Skip to: 40669 >+/* 12363 */ MCD_OPC_Decode, 213, 5, 140, 1, // Opcode: INSvi64lane >+/* 12368 */ MCD_OPC_FilterValue, 1, 137, 110, // Skip to: 40669 >+/* 12372 */ MCD_OPC_CheckPredicate, 0, 133, 110, // Skip to: 40669 >+/* 12376 */ MCD_OPC_CheckField, 11, 2, 0, 127, 110, // Skip to: 40669 >+/* 12382 */ MCD_OPC_Decode, 211, 5, 141, 1, // Opcode: INSvi32lane >+/* 12387 */ MCD_OPC_FilterValue, 1, 118, 110, // Skip to: 40669 >+/* 12391 */ MCD_OPC_CheckPredicate, 0, 114, 110, // Skip to: 40669 >+/* 12395 */ MCD_OPC_CheckField, 11, 1, 0, 108, 110, // Skip to: 40669 >+/* 12401 */ MCD_OPC_Decode, 209, 5, 142, 1, // Opcode: INSvi16lane >+/* 12406 */ MCD_OPC_FilterValue, 1, 99, 110, // Skip to: 40669 >+/* 12410 */ MCD_OPC_CheckPredicate, 0, 95, 110, // Skip to: 40669 >+/* 12414 */ MCD_OPC_Decode, 215, 5, 143, 1, // Opcode: INSvi8lane >+/* 12419 */ MCD_OPC_FilterValue, 1, 86, 110, // Skip to: 40669 >+/* 12423 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... >+/* 12426 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12438 >+/* 12430 */ MCD_OPC_CheckPredicate, 0, 75, 110, // Skip to: 40669 >+/* 12434 */ MCD_OPC_Decode, 182, 16, 112, // Opcode: UHADDv16i8 >+/* 12438 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 12450 >+/* 12442 */ MCD_OPC_CheckPredicate, 0, 63, 110, // Skip to: 40669 >+/* 12446 */ MCD_OPC_Decode, 137, 17, 112, // Opcode: UQADDv16i8 >+/* 12450 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12462 >+/* 12454 */ MCD_OPC_CheckPredicate, 0, 51, 110, // Skip to: 40669 >+/* 12458 */ MCD_OPC_Decode, 221, 17, 112, // Opcode: URHADDv16i8 >+/* 12462 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 12474 >+/* 12466 */ MCD_OPC_CheckPredicate, 0, 39, 110, // Skip to: 40669 >+/* 12470 */ MCD_OPC_Decode, 170, 2, 112, // Opcode: EORv16i8 >+/* 12474 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 12486 >+/* 12478 */ MCD_OPC_CheckPredicate, 0, 27, 110, // Skip to: 40669 >+/* 12482 */ MCD_OPC_Decode, 188, 16, 112, // Opcode: UHSUBv16i8 >+/* 12486 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 12498 >+/* 12490 */ MCD_OPC_CheckPredicate, 0, 15, 110, // Skip to: 40669 >+/* 12494 */ MCD_OPC_Decode, 199, 17, 112, // Opcode: UQSUBv16i8 >+/* 12498 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 12510 >+/* 12502 */ MCD_OPC_CheckPredicate, 0, 3, 110, // Skip to: 40669 >+/* 12506 */ MCD_OPC_Decode, 206, 1, 112, // Opcode: CMHIv16i8 >+/* 12510 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 12522 >+/* 12514 */ MCD_OPC_CheckPredicate, 0, 247, 109, // Skip to: 40669 >+/* 12518 */ MCD_OPC_Decode, 214, 1, 112, // Opcode: CMHSv16i8 >+/* 12522 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12534 >+/* 12526 */ MCD_OPC_CheckPredicate, 0, 235, 109, // Skip to: 40669 >+/* 12530 */ MCD_OPC_Decode, 131, 18, 112, // Opcode: USHLv16i8 >+/* 12534 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 12546 >+/* 12538 */ MCD_OPC_CheckPredicate, 0, 223, 109, // Skip to: 40669 >+/* 12542 */ MCD_OPC_Decode, 172, 17, 112, // Opcode: UQSHLv16i8 >+/* 12546 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12558 >+/* 12550 */ MCD_OPC_CheckPredicate, 0, 211, 109, // Skip to: 40669 >+/* 12554 */ MCD_OPC_Decode, 227, 17, 112, // Opcode: URSHLv16i8 >+/* 12558 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 12570 >+/* 12562 */ MCD_OPC_CheckPredicate, 0, 199, 109, // Skip to: 40669 >+/* 12566 */ MCD_OPC_Decode, 148, 17, 112, // Opcode: UQRSHLv16i8 >+/* 12570 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 12582 >+/* 12574 */ MCD_OPC_CheckPredicate, 0, 187, 109, // Skip to: 40669 >+/* 12578 */ MCD_OPC_Decode, 206, 16, 112, // Opcode: UMAXv16i8 >+/* 12582 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 12594 >+/* 12586 */ MCD_OPC_CheckPredicate, 0, 175, 109, // Skip to: 40669 >+/* 12590 */ MCD_OPC_Decode, 223, 16, 112, // Opcode: UMINv16i8 >+/* 12594 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12606 >+/* 12598 */ MCD_OPC_CheckPredicate, 0, 163, 109, // Skip to: 40669 >+/* 12602 */ MCD_OPC_Decode, 251, 15, 112, // Opcode: UABDv16i8 >+/* 12606 */ MCD_OPC_FilterValue, 15, 155, 109, // Skip to: 40669 >+/* 12610 */ MCD_OPC_CheckPredicate, 0, 151, 109, // Skip to: 40669 >+/* 12614 */ MCD_OPC_Decode, 239, 15, 120, // Opcode: UABAv16i8 >+/* 12618 */ MCD_OPC_FilterValue, 1, 143, 109, // Skip to: 40669 >+/* 12622 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... >+/* 12625 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12643 >+/* 12629 */ MCD_OPC_CheckPredicate, 0, 132, 109, // Skip to: 40669 >+/* 12633 */ MCD_OPC_CheckField, 21, 1, 1, 126, 109, // Skip to: 40669 >+/* 12639 */ MCD_OPC_Decode, 173, 15, 112, // Opcode: SUBv16i8 >+/* 12643 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12661 >+/* 12647 */ MCD_OPC_CheckPredicate, 0, 114, 109, // Skip to: 40669 >+/* 12651 */ MCD_OPC_CheckField, 21, 1, 1, 108, 109, // Skip to: 40669 >+/* 12657 */ MCD_OPC_Decode, 158, 1, 112, // Opcode: CMEQv16i8 >+/* 12661 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12679 >+/* 12665 */ MCD_OPC_CheckPredicate, 0, 96, 109, // Skip to: 40669 >+/* 12669 */ MCD_OPC_CheckField, 21, 1, 1, 90, 109, // Skip to: 40669 >+/* 12675 */ MCD_OPC_Decode, 190, 8, 120, // Opcode: MLSv16i8 >+/* 12679 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12697 >+/* 12683 */ MCD_OPC_CheckPredicate, 0, 78, 109, // Skip to: 40669 >+/* 12687 */ MCD_OPC_CheckField, 21, 1, 1, 72, 109, // Skip to: 40669 >+/* 12693 */ MCD_OPC_Decode, 149, 9, 112, // Opcode: PMULv16i8 >+/* 12697 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12715 >+/* 12701 */ MCD_OPC_CheckPredicate, 0, 60, 109, // Skip to: 40669 >+/* 12705 */ MCD_OPC_CheckField, 21, 1, 1, 54, 109, // Skip to: 40669 >+/* 12711 */ MCD_OPC_Decode, 195, 16, 112, // Opcode: UMAXPv16i8 >+/* 12715 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12733 >+/* 12719 */ MCD_OPC_CheckPredicate, 0, 42, 109, // Skip to: 40669 >+/* 12723 */ MCD_OPC_CheckField, 21, 1, 1, 36, 109, // Skip to: 40669 >+/* 12729 */ MCD_OPC_Decode, 212, 16, 112, // Opcode: UMINPv16i8 >+/* 12733 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12751 >+/* 12737 */ MCD_OPC_CheckPredicate, 0, 24, 109, // Skip to: 40669 >+/* 12741 */ MCD_OPC_CheckField, 21, 1, 1, 18, 109, // Skip to: 40669 >+/* 12747 */ MCD_OPC_Decode, 166, 4, 112, // Opcode: FMAXNMPv4f32 >+/* 12751 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 12769 >+/* 12755 */ MCD_OPC_CheckPredicate, 0, 6, 109, // Skip to: 40669 >+/* 12759 */ MCD_OPC_CheckField, 21, 1, 1, 0, 109, // Skip to: 40669 >+/* 12765 */ MCD_OPC_Decode, 203, 2, 112, // Opcode: FADDPv4f32 >+/* 12769 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12787 >+/* 12773 */ MCD_OPC_CheckPredicate, 0, 244, 108, // Skip to: 40669 >+/* 12777 */ MCD_OPC_CheckField, 21, 1, 1, 238, 108, // Skip to: 40669 >+/* 12783 */ MCD_OPC_Decode, 253, 4, 112, // Opcode: FMULv4f32 >+/* 12787 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12805 >+/* 12791 */ MCD_OPC_CheckPredicate, 0, 226, 108, // Skip to: 40669 >+/* 12795 */ MCD_OPC_CheckField, 21, 1, 1, 220, 108, // Skip to: 40669 >+/* 12801 */ MCD_OPC_Decode, 230, 2, 112, // Opcode: FCMGEv4f32 >+/* 12805 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12823 >+/* 12809 */ MCD_OPC_CheckPredicate, 0, 208, 108, // Skip to: 40669 >+/* 12813 */ MCD_OPC_CheckField, 21, 1, 1, 202, 108, // Skip to: 40669 >+/* 12819 */ MCD_OPC_Decode, 192, 2, 112, // Opcode: FACGEv4f32 >+/* 12823 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 12841 >+/* 12827 */ MCD_OPC_CheckPredicate, 0, 190, 108, // Skip to: 40669 >+/* 12831 */ MCD_OPC_CheckField, 21, 1, 1, 184, 108, // Skip to: 40669 >+/* 12837 */ MCD_OPC_Decode, 176, 4, 112, // Opcode: FMAXPv4f32 >+/* 12841 */ MCD_OPC_FilterValue, 15, 176, 108, // Skip to: 40669 >+/* 12845 */ MCD_OPC_CheckPredicate, 0, 172, 108, // Skip to: 40669 >+/* 12849 */ MCD_OPC_CheckField, 21, 1, 1, 166, 108, // Skip to: 40669 >+/* 12855 */ MCD_OPC_Decode, 157, 4, 112, // Opcode: FDIVv4f32 >+/* 12859 */ MCD_OPC_FilterValue, 9, 129, 18, // Skip to: 17600 >+/* 12863 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 12866 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 12945 >+/* 12870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 12873 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12891 >+/* 12877 */ MCD_OPC_CheckPredicate, 0, 140, 108, // Skip to: 40669 >+/* 12881 */ MCD_OPC_CheckField, 21, 1, 1, 134, 108, // Skip to: 40669 >+/* 12887 */ MCD_OPC_Decode, 242, 9, 85, // Opcode: SADDLv4i16_v4i32 >+/* 12891 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12909 >+/* 12895 */ MCD_OPC_CheckPredicate, 0, 122, 108, // Skip to: 40669 >+/* 12899 */ MCD_OPC_CheckField, 21, 1, 1, 116, 108, // Skip to: 40669 >+/* 12905 */ MCD_OPC_Decode, 148, 16, 85, // Opcode: UADDLv4i16_v4i32 >+/* 12909 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12927 >+/* 12913 */ MCD_OPC_CheckPredicate, 0, 104, 108, // Skip to: 40669 >+/* 12917 */ MCD_OPC_CheckField, 21, 1, 1, 98, 108, // Skip to: 40669 >+/* 12923 */ MCD_OPC_Decode, 244, 9, 112, // Opcode: SADDLv8i16_v4i32 >+/* 12927 */ MCD_OPC_FilterValue, 3, 90, 108, // Skip to: 40669 >+/* 12931 */ MCD_OPC_CheckPredicate, 0, 86, 108, // Skip to: 40669 >+/* 12935 */ MCD_OPC_CheckField, 21, 1, 1, 80, 108, // Skip to: 40669 >+/* 12941 */ MCD_OPC_Decode, 150, 16, 112, // Opcode: UADDLv8i16_v4i32 >+/* 12945 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13024 >+/* 12949 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 12952 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12970 >+/* 12956 */ MCD_OPC_CheckPredicate, 0, 61, 108, // Skip to: 40669 >+/* 12960 */ MCD_OPC_CheckField, 21, 1, 1, 55, 108, // Skip to: 40669 >+/* 12966 */ MCD_OPC_Decode, 164, 10, 89, // Opcode: SHADDv4i16 >+/* 12970 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12988 >+/* 12974 */ MCD_OPC_CheckPredicate, 0, 43, 108, // Skip to: 40669 >+/* 12978 */ MCD_OPC_CheckField, 21, 1, 1, 37, 108, // Skip to: 40669 >+/* 12984 */ MCD_OPC_Decode, 184, 16, 89, // Opcode: UHADDv4i16 >+/* 12988 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13006 >+/* 12992 */ MCD_OPC_CheckPredicate, 0, 25, 108, // Skip to: 40669 >+/* 12996 */ MCD_OPC_CheckField, 21, 1, 1, 19, 108, // Skip to: 40669 >+/* 13002 */ MCD_OPC_Decode, 166, 10, 112, // Opcode: SHADDv8i16 >+/* 13006 */ MCD_OPC_FilterValue, 3, 11, 108, // Skip to: 40669 >+/* 13010 */ MCD_OPC_CheckPredicate, 0, 7, 108, // Skip to: 40669 >+/* 13014 */ MCD_OPC_CheckField, 21, 1, 1, 1, 108, // Skip to: 40669 >+/* 13020 */ MCD_OPC_Decode, 186, 16, 112, // Opcode: UHADDv8i16 >+/* 13024 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 13103 >+/* 13028 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13031 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13049 >+/* 13035 */ MCD_OPC_CheckPredicate, 0, 238, 107, // Skip to: 40669 >+/* 13039 */ MCD_OPC_CheckField, 16, 6, 32, 232, 107, // Skip to: 40669 >+/* 13045 */ MCD_OPC_Decode, 179, 9, 90, // Opcode: REV64v4i16 >+/* 13049 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13067 >+/* 13053 */ MCD_OPC_CheckPredicate, 0, 220, 107, // Skip to: 40669 >+/* 13057 */ MCD_OPC_CheckField, 16, 6, 32, 214, 107, // Skip to: 40669 >+/* 13063 */ MCD_OPC_Decode, 174, 9, 90, // Opcode: REV32v4i16 >+/* 13067 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13085 >+/* 13071 */ MCD_OPC_CheckPredicate, 0, 202, 107, // Skip to: 40669 >+/* 13075 */ MCD_OPC_CheckField, 16, 6, 32, 196, 107, // Skip to: 40669 >+/* 13081 */ MCD_OPC_Decode, 181, 9, 117, // Opcode: REV64v8i16 >+/* 13085 */ MCD_OPC_FilterValue, 3, 188, 107, // Skip to: 40669 >+/* 13089 */ MCD_OPC_CheckPredicate, 0, 184, 107, // Skip to: 40669 >+/* 13093 */ MCD_OPC_CheckField, 16, 6, 32, 178, 107, // Skip to: 40669 >+/* 13099 */ MCD_OPC_Decode, 175, 9, 117, // Opcode: REV32v8i16 >+/* 13103 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 13182 >+/* 13107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13110 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13128 >+/* 13114 */ MCD_OPC_CheckPredicate, 0, 159, 107, // Skip to: 40669 >+/* 13118 */ MCD_OPC_CheckField, 21, 1, 1, 153, 107, // Skip to: 40669 >+/* 13124 */ MCD_OPC_Decode, 165, 11, 89, // Opcode: SQADDv4i16 >+/* 13128 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13146 >+/* 13132 */ MCD_OPC_CheckPredicate, 0, 141, 107, // Skip to: 40669 >+/* 13136 */ MCD_OPC_CheckField, 21, 1, 1, 135, 107, // Skip to: 40669 >+/* 13142 */ MCD_OPC_Decode, 144, 17, 89, // Opcode: UQADDv4i16 >+/* 13146 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13164 >+/* 13150 */ MCD_OPC_CheckPredicate, 0, 123, 107, // Skip to: 40669 >+/* 13154 */ MCD_OPC_CheckField, 21, 1, 1, 117, 107, // Skip to: 40669 >+/* 13160 */ MCD_OPC_Decode, 167, 11, 112, // Opcode: SQADDv8i16 >+/* 13164 */ MCD_OPC_FilterValue, 3, 109, 107, // Skip to: 40669 >+/* 13168 */ MCD_OPC_CheckPredicate, 0, 105, 107, // Skip to: 40669 >+/* 13172 */ MCD_OPC_CheckField, 21, 1, 1, 99, 107, // Skip to: 40669 >+/* 13178 */ MCD_OPC_Decode, 146, 17, 112, // Opcode: UQADDv8i16 >+/* 13182 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 13261 >+/* 13186 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13189 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13207 >+/* 13193 */ MCD_OPC_CheckPredicate, 0, 80, 107, // Skip to: 40669 >+/* 13197 */ MCD_OPC_CheckField, 21, 1, 1, 74, 107, // Skip to: 40669 >+/* 13203 */ MCD_OPC_Decode, 248, 9, 93, // Opcode: SADDWv4i16_v4i32 >+/* 13207 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13225 >+/* 13211 */ MCD_OPC_CheckPredicate, 0, 62, 107, // Skip to: 40669 >+/* 13215 */ MCD_OPC_CheckField, 21, 1, 1, 56, 107, // Skip to: 40669 >+/* 13221 */ MCD_OPC_Decode, 154, 16, 93, // Opcode: UADDWv4i16_v4i32 >+/* 13225 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13243 >+/* 13229 */ MCD_OPC_CheckPredicate, 0, 44, 107, // Skip to: 40669 >+/* 13233 */ MCD_OPC_CheckField, 21, 1, 1, 38, 107, // Skip to: 40669 >+/* 13239 */ MCD_OPC_Decode, 250, 9, 112, // Opcode: SADDWv8i16_v4i32 >+/* 13243 */ MCD_OPC_FilterValue, 3, 30, 107, // Skip to: 40669 >+/* 13247 */ MCD_OPC_CheckPredicate, 0, 26, 107, // Skip to: 40669 >+/* 13251 */ MCD_OPC_CheckField, 21, 1, 1, 20, 107, // Skip to: 40669 >+/* 13257 */ MCD_OPC_Decode, 156, 16, 112, // Opcode: UADDWv8i16_v4i32 >+/* 13261 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 13340 >+/* 13265 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13268 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13286 >+/* 13272 */ MCD_OPC_CheckPredicate, 0, 1, 107, // Skip to: 40669 >+/* 13276 */ MCD_OPC_CheckField, 21, 1, 1, 251, 106, // Skip to: 40669 >+/* 13282 */ MCD_OPC_Decode, 223, 12, 89, // Opcode: SRHADDv4i16 >+/* 13286 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13304 >+/* 13290 */ MCD_OPC_CheckPredicate, 0, 239, 106, // Skip to: 40669 >+/* 13294 */ MCD_OPC_CheckField, 21, 1, 1, 233, 106, // Skip to: 40669 >+/* 13300 */ MCD_OPC_Decode, 223, 17, 89, // Opcode: URHADDv4i16 >+/* 13304 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13322 >+/* 13308 */ MCD_OPC_CheckPredicate, 0, 221, 106, // Skip to: 40669 >+/* 13312 */ MCD_OPC_CheckField, 21, 1, 1, 215, 106, // Skip to: 40669 >+/* 13318 */ MCD_OPC_Decode, 225, 12, 112, // Opcode: SRHADDv8i16 >+/* 13322 */ MCD_OPC_FilterValue, 3, 207, 106, // Skip to: 40669 >+/* 13326 */ MCD_OPC_CheckPredicate, 0, 203, 106, // Skip to: 40669 >+/* 13330 */ MCD_OPC_CheckField, 21, 1, 1, 197, 106, // Skip to: 40669 >+/* 13336 */ MCD_OPC_Decode, 225, 17, 112, // Opcode: URHADDv8i16 >+/* 13340 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 13383 >+/* 13344 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13347 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13365 >+/* 13351 */ MCD_OPC_CheckPredicate, 0, 178, 106, // Skip to: 40669 >+/* 13355 */ MCD_OPC_CheckField, 21, 1, 0, 172, 106, // Skip to: 40669 >+/* 13361 */ MCD_OPC_Decode, 181, 18, 89, // Opcode: UZP1v4i16 >+/* 13365 */ MCD_OPC_FilterValue, 2, 164, 106, // Skip to: 40669 >+/* 13369 */ MCD_OPC_CheckPredicate, 0, 160, 106, // Skip to: 40669 >+/* 13373 */ MCD_OPC_CheckField, 21, 1, 0, 154, 106, // Skip to: 40669 >+/* 13379 */ MCD_OPC_Decode, 183, 18, 112, // Opcode: UZP1v8i16 >+/* 13383 */ MCD_OPC_FilterValue, 7, 71, 0, // Skip to: 13458 >+/* 13387 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13390 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 13407 >+/* 13394 */ MCD_OPC_CheckPredicate, 0, 135, 106, // Skip to: 40669 >+/* 13398 */ MCD_OPC_CheckField, 21, 1, 1, 129, 106, // Skip to: 40669 >+/* 13404 */ MCD_OPC_Decode, 117, 89, // Opcode: BICv8i8 >+/* 13407 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 13424 >+/* 13411 */ MCD_OPC_CheckPredicate, 0, 118, 106, // Skip to: 40669 >+/* 13415 */ MCD_OPC_CheckField, 21, 1, 1, 112, 106, // Skip to: 40669 >+/* 13421 */ MCD_OPC_Decode, 127, 109, // Opcode: BSLv8i8 >+/* 13424 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 13441 >+/* 13428 */ MCD_OPC_CheckPredicate, 0, 101, 106, // Skip to: 40669 >+/* 13432 */ MCD_OPC_CheckField, 21, 1, 1, 95, 106, // Skip to: 40669 >+/* 13438 */ MCD_OPC_Decode, 112, 112, // Opcode: BICv16i8 >+/* 13441 */ MCD_OPC_FilterValue, 3, 88, 106, // Skip to: 40669 >+/* 13445 */ MCD_OPC_CheckPredicate, 0, 84, 106, // Skip to: 40669 >+/* 13449 */ MCD_OPC_CheckField, 21, 1, 1, 78, 106, // Skip to: 40669 >+/* 13455 */ MCD_OPC_Decode, 126, 120, // Opcode: BSLv16i8 >+/* 13458 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 13537 >+/* 13462 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13465 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13483 >+/* 13469 */ MCD_OPC_CheckPredicate, 0, 60, 106, // Skip to: 40669 >+/* 13473 */ MCD_OPC_CheckField, 21, 1, 1, 54, 106, // Skip to: 40669 >+/* 13479 */ MCD_OPC_Decode, 163, 13, 85, // Opcode: SSUBLv4i16_v4i32 >+/* 13483 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13501 >+/* 13487 */ MCD_OPC_CheckPredicate, 0, 42, 106, // Skip to: 40669 >+/* 13491 */ MCD_OPC_CheckField, 21, 1, 1, 36, 106, // Skip to: 40669 >+/* 13497 */ MCD_OPC_Decode, 168, 18, 85, // Opcode: USUBLv4i16_v4i32 >+/* 13501 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13519 >+/* 13505 */ MCD_OPC_CheckPredicate, 0, 24, 106, // Skip to: 40669 >+/* 13509 */ MCD_OPC_CheckField, 21, 1, 1, 18, 106, // Skip to: 40669 >+/* 13515 */ MCD_OPC_Decode, 165, 13, 112, // Opcode: SSUBLv8i16_v4i32 >+/* 13519 */ MCD_OPC_FilterValue, 3, 10, 106, // Skip to: 40669 >+/* 13523 */ MCD_OPC_CheckPredicate, 0, 6, 106, // Skip to: 40669 >+/* 13527 */ MCD_OPC_CheckField, 21, 1, 1, 0, 106, // Skip to: 40669 >+/* 13533 */ MCD_OPC_Decode, 170, 18, 112, // Opcode: USUBLv8i16_v4i32 >+/* 13537 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 13616 >+/* 13541 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13544 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13562 >+/* 13548 */ MCD_OPC_CheckPredicate, 0, 237, 105, // Skip to: 40669 >+/* 13552 */ MCD_OPC_CheckField, 21, 1, 1, 231, 105, // Skip to: 40669 >+/* 13558 */ MCD_OPC_Decode, 190, 10, 89, // Opcode: SHSUBv4i16 >+/* 13562 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13580 >+/* 13566 */ MCD_OPC_CheckPredicate, 0, 219, 105, // Skip to: 40669 >+/* 13570 */ MCD_OPC_CheckField, 21, 1, 1, 213, 105, // Skip to: 40669 >+/* 13576 */ MCD_OPC_Decode, 190, 16, 89, // Opcode: UHSUBv4i16 >+/* 13580 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13598 >+/* 13584 */ MCD_OPC_CheckPredicate, 0, 201, 105, // Skip to: 40669 >+/* 13588 */ MCD_OPC_CheckField, 21, 1, 1, 195, 105, // Skip to: 40669 >+/* 13594 */ MCD_OPC_Decode, 192, 10, 112, // Opcode: SHSUBv8i16 >+/* 13598 */ MCD_OPC_FilterValue, 3, 187, 105, // Skip to: 40669 >+/* 13602 */ MCD_OPC_CheckPredicate, 0, 183, 105, // Skip to: 40669 >+/* 13606 */ MCD_OPC_CheckField, 21, 1, 1, 177, 105, // Skip to: 40669 >+/* 13612 */ MCD_OPC_Decode, 192, 16, 112, // Opcode: UHSUBv8i16 >+/* 13616 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 13785 >+/* 13620 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13623 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 13673 >+/* 13627 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13630 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13642 >+/* 13634 */ MCD_OPC_CheckPredicate, 0, 151, 105, // Skip to: 40669 >+/* 13638 */ MCD_OPC_Decode, 222, 15, 89, // Opcode: TRN1v4i16 >+/* 13642 */ MCD_OPC_FilterValue, 1, 143, 105, // Skip to: 40669 >+/* 13646 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 13649 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13661 >+/* 13653 */ MCD_OPC_CheckPredicate, 0, 132, 105, // Skip to: 40669 >+/* 13657 */ MCD_OPC_Decode, 231, 9, 90, // Opcode: SADDLPv4i16_v2i32 >+/* 13661 */ MCD_OPC_FilterValue, 1, 124, 105, // Skip to: 40669 >+/* 13665 */ MCD_OPC_CheckPredicate, 0, 120, 105, // Skip to: 40669 >+/* 13669 */ MCD_OPC_Decode, 194, 18, 95, // Opcode: XTNv4i16 >+/* 13673 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 13704 >+/* 13677 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 13680 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13692 >+/* 13684 */ MCD_OPC_CheckPredicate, 0, 101, 105, // Skip to: 40669 >+/* 13688 */ MCD_OPC_Decode, 137, 16, 90, // Opcode: UADDLPv4i16_v2i32 >+/* 13692 */ MCD_OPC_FilterValue, 33, 93, 105, // Skip to: 40669 >+/* 13696 */ MCD_OPC_CheckPredicate, 0, 89, 105, // Skip to: 40669 >+/* 13700 */ MCD_OPC_Decode, 217, 12, 95, // Opcode: SQXTUNv4i16 >+/* 13704 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 13754 >+/* 13708 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13711 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13723 >+/* 13715 */ MCD_OPC_CheckPredicate, 0, 70, 105, // Skip to: 40669 >+/* 13719 */ MCD_OPC_Decode, 224, 15, 112, // Opcode: TRN1v8i16 >+/* 13723 */ MCD_OPC_FilterValue, 1, 62, 105, // Skip to: 40669 >+/* 13727 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 13730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13742 >+/* 13734 */ MCD_OPC_CheckPredicate, 0, 51, 105, // Skip to: 40669 >+/* 13738 */ MCD_OPC_Decode, 233, 9, 117, // Opcode: SADDLPv8i16_v4i32 >+/* 13742 */ MCD_OPC_FilterValue, 1, 43, 105, // Skip to: 40669 >+/* 13746 */ MCD_OPC_CheckPredicate, 0, 39, 105, // Skip to: 40669 >+/* 13750 */ MCD_OPC_Decode, 196, 18, 126, // Opcode: XTNv8i16 >+/* 13754 */ MCD_OPC_FilterValue, 3, 31, 105, // Skip to: 40669 >+/* 13758 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 13761 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13773 >+/* 13765 */ MCD_OPC_CheckPredicate, 0, 20, 105, // Skip to: 40669 >+/* 13769 */ MCD_OPC_Decode, 139, 16, 117, // Opcode: UADDLPv8i16_v4i32 >+/* 13773 */ MCD_OPC_FilterValue, 33, 12, 105, // Skip to: 40669 >+/* 13777 */ MCD_OPC_CheckPredicate, 0, 8, 105, // Skip to: 40669 >+/* 13781 */ MCD_OPC_Decode, 219, 12, 126, // Opcode: SQXTUNv8i16 >+/* 13785 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 13864 >+/* 13789 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13792 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13810 >+/* 13796 */ MCD_OPC_CheckPredicate, 0, 245, 104, // Skip to: 40669 >+/* 13800 */ MCD_OPC_CheckField, 21, 1, 1, 239, 104, // Skip to: 40669 >+/* 13806 */ MCD_OPC_Decode, 199, 12, 89, // Opcode: SQSUBv4i16 >+/* 13810 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13828 >+/* 13814 */ MCD_OPC_CheckPredicate, 0, 227, 104, // Skip to: 40669 >+/* 13818 */ MCD_OPC_CheckField, 21, 1, 1, 221, 104, // Skip to: 40669 >+/* 13824 */ MCD_OPC_Decode, 206, 17, 89, // Opcode: UQSUBv4i16 >+/* 13828 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13846 >+/* 13832 */ MCD_OPC_CheckPredicate, 0, 209, 104, // Skip to: 40669 >+/* 13836 */ MCD_OPC_CheckField, 21, 1, 1, 203, 104, // Skip to: 40669 >+/* 13842 */ MCD_OPC_Decode, 201, 12, 112, // Opcode: SQSUBv8i16 >+/* 13846 */ MCD_OPC_FilterValue, 3, 195, 104, // Skip to: 40669 >+/* 13850 */ MCD_OPC_CheckPredicate, 0, 191, 104, // Skip to: 40669 >+/* 13854 */ MCD_OPC_CheckField, 21, 1, 1, 185, 104, // Skip to: 40669 >+/* 13860 */ MCD_OPC_Decode, 208, 17, 112, // Opcode: UQSUBv8i16 >+/* 13864 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 13943 >+/* 13868 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13871 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13889 >+/* 13875 */ MCD_OPC_CheckPredicate, 0, 166, 104, // Skip to: 40669 >+/* 13879 */ MCD_OPC_CheckField, 21, 1, 1, 160, 104, // Skip to: 40669 >+/* 13885 */ MCD_OPC_Decode, 169, 13, 93, // Opcode: SSUBWv4i16_v4i32 >+/* 13889 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13907 >+/* 13893 */ MCD_OPC_CheckPredicate, 0, 148, 104, // Skip to: 40669 >+/* 13897 */ MCD_OPC_CheckField, 21, 1, 1, 142, 104, // Skip to: 40669 >+/* 13903 */ MCD_OPC_Decode, 174, 18, 93, // Opcode: USUBWv4i16_v4i32 >+/* 13907 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13925 >+/* 13911 */ MCD_OPC_CheckPredicate, 0, 130, 104, // Skip to: 40669 >+/* 13915 */ MCD_OPC_CheckField, 21, 1, 1, 124, 104, // Skip to: 40669 >+/* 13921 */ MCD_OPC_Decode, 171, 13, 112, // Opcode: SSUBWv8i16_v4i32 >+/* 13925 */ MCD_OPC_FilterValue, 3, 116, 104, // Skip to: 40669 >+/* 13929 */ MCD_OPC_CheckPredicate, 0, 112, 104, // Skip to: 40669 >+/* 13933 */ MCD_OPC_CheckField, 21, 1, 1, 106, 104, // Skip to: 40669 >+/* 13939 */ MCD_OPC_Decode, 176, 18, 112, // Opcode: USUBWv8i16_v4i32 >+/* 13943 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 14022 >+/* 13947 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 13950 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13968 >+/* 13954 */ MCD_OPC_CheckPredicate, 0, 87, 104, // Skip to: 40669 >+/* 13958 */ MCD_OPC_CheckField, 21, 1, 1, 81, 104, // Skip to: 40669 >+/* 13964 */ MCD_OPC_Decode, 198, 1, 89, // Opcode: CMGTv4i16 >+/* 13968 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13986 >+/* 13972 */ MCD_OPC_CheckPredicate, 0, 69, 104, // Skip to: 40669 >+/* 13976 */ MCD_OPC_CheckField, 21, 1, 1, 63, 104, // Skip to: 40669 >+/* 13982 */ MCD_OPC_Decode, 210, 1, 89, // Opcode: CMHIv4i16 >+/* 13986 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14004 >+/* 13990 */ MCD_OPC_CheckPredicate, 0, 51, 104, // Skip to: 40669 >+/* 13994 */ MCD_OPC_CheckField, 21, 1, 1, 45, 104, // Skip to: 40669 >+/* 14000 */ MCD_OPC_Decode, 202, 1, 112, // Opcode: CMGTv8i16 >+/* 14004 */ MCD_OPC_FilterValue, 3, 37, 104, // Skip to: 40669 >+/* 14008 */ MCD_OPC_CheckPredicate, 0, 33, 104, // Skip to: 40669 >+/* 14012 */ MCD_OPC_CheckField, 21, 1, 1, 27, 104, // Skip to: 40669 >+/* 14018 */ MCD_OPC_Decode, 212, 1, 112, // Opcode: CMHIv8i16 >+/* 14022 */ MCD_OPC_FilterValue, 14, 193, 0, // Skip to: 14219 >+/* 14026 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14029 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 14080 >+/* 14033 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 14036 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14048 >+/* 14040 */ MCD_OPC_CheckPredicate, 0, 1, 104, // Skip to: 40669 >+/* 14044 */ MCD_OPC_Decode, 201, 18, 89, // Opcode: ZIP1v4i16 >+/* 14048 */ MCD_OPC_FilterValue, 1, 249, 103, // Skip to: 40669 >+/* 14052 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 14055 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14067 >+/* 14059 */ MCD_OPC_CheckPredicate, 0, 238, 103, // Skip to: 40669 >+/* 14063 */ MCD_OPC_Decode, 188, 15, 99, // Opcode: SUQADDv4i16 >+/* 14067 */ MCD_OPC_FilterValue, 16, 230, 103, // Skip to: 40669 >+/* 14071 */ MCD_OPC_CheckPredicate, 0, 226, 103, // Skip to: 40669 >+/* 14075 */ MCD_OPC_Decode, 236, 9, 144, 1, // Opcode: SADDLVv4i16v >+/* 14080 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 14124 >+/* 14084 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14087 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14099 >+/* 14091 */ MCD_OPC_CheckPredicate, 0, 206, 103, // Skip to: 40669 >+/* 14095 */ MCD_OPC_Decode, 154, 18, 99, // Opcode: USQADDv4i16 >+/* 14099 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14111 >+/* 14103 */ MCD_OPC_CheckPredicate, 0, 194, 103, // Skip to: 40669 >+/* 14107 */ MCD_OPC_Decode, 170, 10, 108, // Opcode: SHLLv4i16 >+/* 14111 */ MCD_OPC_FilterValue, 48, 186, 103, // Skip to: 40669 >+/* 14115 */ MCD_OPC_CheckPredicate, 0, 182, 103, // Skip to: 40669 >+/* 14119 */ MCD_OPC_Decode, 142, 16, 144, 1, // Opcode: UADDLVv4i16v >+/* 14124 */ MCD_OPC_FilterValue, 2, 47, 0, // Skip to: 14175 >+/* 14128 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 14131 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14143 >+/* 14135 */ MCD_OPC_CheckPredicate, 0, 162, 103, // Skip to: 40669 >+/* 14139 */ MCD_OPC_Decode, 203, 18, 112, // Opcode: ZIP1v8i16 >+/* 14143 */ MCD_OPC_FilterValue, 1, 154, 103, // Skip to: 40669 >+/* 14147 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 14150 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14162 >+/* 14154 */ MCD_OPC_CheckPredicate, 0, 143, 103, // Skip to: 40669 >+/* 14158 */ MCD_OPC_Decode, 190, 15, 126, // Opcode: SUQADDv8i16 >+/* 14162 */ MCD_OPC_FilterValue, 16, 135, 103, // Skip to: 40669 >+/* 14166 */ MCD_OPC_CheckPredicate, 0, 131, 103, // Skip to: 40669 >+/* 14170 */ MCD_OPC_Decode, 238, 9, 139, 1, // Opcode: SADDLVv8i16v >+/* 14175 */ MCD_OPC_FilterValue, 3, 122, 103, // Skip to: 40669 >+/* 14179 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14182 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14194 >+/* 14186 */ MCD_OPC_CheckPredicate, 0, 111, 103, // Skip to: 40669 >+/* 14190 */ MCD_OPC_Decode, 156, 18, 126, // Opcode: USQADDv8i16 >+/* 14194 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14206 >+/* 14198 */ MCD_OPC_CheckPredicate, 0, 99, 103, // Skip to: 40669 >+/* 14202 */ MCD_OPC_Decode, 172, 10, 117, // Opcode: SHLLv8i16 >+/* 14206 */ MCD_OPC_FilterValue, 48, 91, 103, // Skip to: 40669 >+/* 14210 */ MCD_OPC_CheckPredicate, 0, 87, 103, // Skip to: 40669 >+/* 14214 */ MCD_OPC_Decode, 144, 16, 139, 1, // Opcode: UADDLVv8i16v >+/* 14219 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 14298 >+/* 14223 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14226 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14244 >+/* 14230 */ MCD_OPC_CheckPredicate, 0, 67, 103, // Skip to: 40669 >+/* 14234 */ MCD_OPC_CheckField, 21, 1, 1, 61, 103, // Skip to: 40669 >+/* 14240 */ MCD_OPC_Decode, 182, 1, 89, // Opcode: CMGEv4i16 >+/* 14244 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14262 >+/* 14248 */ MCD_OPC_CheckPredicate, 0, 49, 103, // Skip to: 40669 >+/* 14252 */ MCD_OPC_CheckField, 21, 1, 1, 43, 103, // Skip to: 40669 >+/* 14258 */ MCD_OPC_Decode, 218, 1, 89, // Opcode: CMHSv4i16 >+/* 14262 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14280 >+/* 14266 */ MCD_OPC_CheckPredicate, 0, 31, 103, // Skip to: 40669 >+/* 14270 */ MCD_OPC_CheckField, 21, 1, 1, 25, 103, // Skip to: 40669 >+/* 14276 */ MCD_OPC_Decode, 186, 1, 112, // Opcode: CMGEv8i16 >+/* 14280 */ MCD_OPC_FilterValue, 3, 17, 103, // Skip to: 40669 >+/* 14284 */ MCD_OPC_CheckPredicate, 0, 13, 103, // Skip to: 40669 >+/* 14288 */ MCD_OPC_CheckField, 21, 1, 1, 7, 103, // Skip to: 40669 >+/* 14294 */ MCD_OPC_Decode, 220, 1, 112, // Opcode: CMHSv8i16 >+/* 14298 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 14375 >+/* 14302 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14305 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 14322 >+/* 14309 */ MCD_OPC_CheckPredicate, 0, 244, 102, // Skip to: 40669 >+/* 14313 */ MCD_OPC_CheckField, 21, 1, 1, 238, 102, // Skip to: 40669 >+/* 14319 */ MCD_OPC_Decode, 34, 103, // Opcode: ADDHNv4i32_v4i16 >+/* 14322 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14340 >+/* 14326 */ MCD_OPC_CheckPredicate, 0, 227, 102, // Skip to: 40669 >+/* 14330 */ MCD_OPC_CheckField, 21, 1, 1, 221, 102, // Skip to: 40669 >+/* 14336 */ MCD_OPC_Decode, 158, 9, 103, // Opcode: RADDHNv4i32_v4i16 >+/* 14340 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 14357 >+/* 14344 */ MCD_OPC_CheckPredicate, 0, 209, 102, // Skip to: 40669 >+/* 14348 */ MCD_OPC_CheckField, 21, 1, 1, 203, 102, // Skip to: 40669 >+/* 14354 */ MCD_OPC_Decode, 35, 120, // Opcode: ADDHNv4i32_v8i16 >+/* 14357 */ MCD_OPC_FilterValue, 3, 196, 102, // Skip to: 40669 >+/* 14361 */ MCD_OPC_CheckPredicate, 0, 192, 102, // Skip to: 40669 >+/* 14365 */ MCD_OPC_CheckField, 21, 1, 1, 186, 102, // Skip to: 40669 >+/* 14371 */ MCD_OPC_Decode, 159, 9, 120, // Opcode: RADDHNv4i32_v8i16 >+/* 14375 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 14454 >+/* 14379 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14382 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14400 >+/* 14386 */ MCD_OPC_CheckPredicate, 0, 167, 102, // Skip to: 40669 >+/* 14390 */ MCD_OPC_CheckField, 21, 1, 1, 161, 102, // Skip to: 40669 >+/* 14396 */ MCD_OPC_Decode, 141, 13, 89, // Opcode: SSHLv4i16 >+/* 14400 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14418 >+/* 14404 */ MCD_OPC_CheckPredicate, 0, 149, 102, // Skip to: 40669 >+/* 14408 */ MCD_OPC_CheckField, 21, 1, 1, 143, 102, // Skip to: 40669 >+/* 14414 */ MCD_OPC_Decode, 135, 18, 89, // Opcode: USHLv4i16 >+/* 14418 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14436 >+/* 14422 */ MCD_OPC_CheckPredicate, 0, 131, 102, // Skip to: 40669 >+/* 14426 */ MCD_OPC_CheckField, 21, 1, 1, 125, 102, // Skip to: 40669 >+/* 14432 */ MCD_OPC_Decode, 143, 13, 112, // Opcode: SSHLv8i16 >+/* 14436 */ MCD_OPC_FilterValue, 3, 117, 102, // Skip to: 40669 >+/* 14440 */ MCD_OPC_CheckPredicate, 0, 113, 102, // Skip to: 40669 >+/* 14444 */ MCD_OPC_CheckField, 21, 1, 1, 107, 102, // Skip to: 40669 >+/* 14450 */ MCD_OPC_Decode, 137, 18, 112, // Opcode: USHLv8i16 >+/* 14454 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 14585 >+/* 14458 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14461 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 14492 >+/* 14465 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14468 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14480 >+/* 14472 */ MCD_OPC_CheckPredicate, 0, 81, 102, // Skip to: 40669 >+/* 14476 */ MCD_OPC_Decode, 146, 1, 90, // Opcode: CLSv4i16 >+/* 14480 */ MCD_OPC_FilterValue, 33, 73, 102, // Skip to: 40669 >+/* 14484 */ MCD_OPC_CheckPredicate, 0, 69, 102, // Skip to: 40669 >+/* 14488 */ MCD_OPC_Decode, 208, 12, 95, // Opcode: SQXTNv4i16 >+/* 14492 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 14523 >+/* 14496 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14499 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14511 >+/* 14503 */ MCD_OPC_CheckPredicate, 0, 50, 102, // Skip to: 40669 >+/* 14507 */ MCD_OPC_Decode, 154, 1, 90, // Opcode: CLZv4i16 >+/* 14511 */ MCD_OPC_FilterValue, 33, 42, 102, // Skip to: 40669 >+/* 14515 */ MCD_OPC_CheckPredicate, 0, 38, 102, // Skip to: 40669 >+/* 14519 */ MCD_OPC_Decode, 215, 17, 95, // Opcode: UQXTNv4i16 >+/* 14523 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 14554 >+/* 14527 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14530 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14542 >+/* 14534 */ MCD_OPC_CheckPredicate, 0, 19, 102, // Skip to: 40669 >+/* 14538 */ MCD_OPC_Decode, 148, 1, 117, // Opcode: CLSv8i16 >+/* 14542 */ MCD_OPC_FilterValue, 33, 11, 102, // Skip to: 40669 >+/* 14546 */ MCD_OPC_CheckPredicate, 0, 7, 102, // Skip to: 40669 >+/* 14550 */ MCD_OPC_Decode, 210, 12, 126, // Opcode: SQXTNv8i16 >+/* 14554 */ MCD_OPC_FilterValue, 3, 255, 101, // Skip to: 40669 >+/* 14558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 14561 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14573 >+/* 14565 */ MCD_OPC_CheckPredicate, 0, 244, 101, // Skip to: 40669 >+/* 14569 */ MCD_OPC_Decode, 156, 1, 117, // Opcode: CLZv8i16 >+/* 14573 */ MCD_OPC_FilterValue, 33, 236, 101, // Skip to: 40669 >+/* 14577 */ MCD_OPC_CheckPredicate, 0, 232, 101, // Skip to: 40669 >+/* 14581 */ MCD_OPC_Decode, 217, 17, 126, // Opcode: UQXTNv8i16 >+/* 14585 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 14664 >+/* 14589 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14592 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14610 >+/* 14596 */ MCD_OPC_CheckPredicate, 0, 213, 101, // Skip to: 40669 >+/* 14600 */ MCD_OPC_CheckField, 21, 1, 1, 207, 101, // Skip to: 40669 >+/* 14606 */ MCD_OPC_Decode, 166, 12, 89, // Opcode: SQSHLv4i16 >+/* 14610 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14628 >+/* 14614 */ MCD_OPC_CheckPredicate, 0, 195, 101, // Skip to: 40669 >+/* 14618 */ MCD_OPC_CheckField, 21, 1, 1, 189, 101, // Skip to: 40669 >+/* 14624 */ MCD_OPC_Decode, 182, 17, 89, // Opcode: UQSHLv4i16 >+/* 14628 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14646 >+/* 14632 */ MCD_OPC_CheckPredicate, 0, 177, 101, // Skip to: 40669 >+/* 14636 */ MCD_OPC_CheckField, 21, 1, 1, 171, 101, // Skip to: 40669 >+/* 14642 */ MCD_OPC_Decode, 170, 12, 112, // Opcode: SQSHLv8i16 >+/* 14646 */ MCD_OPC_FilterValue, 3, 163, 101, // Skip to: 40669 >+/* 14650 */ MCD_OPC_CheckPredicate, 0, 159, 101, // Skip to: 40669 >+/* 14654 */ MCD_OPC_CheckField, 21, 1, 1, 153, 101, // Skip to: 40669 >+/* 14660 */ MCD_OPC_Decode, 186, 17, 112, // Opcode: UQSHLv8i16 >+/* 14664 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 14743 >+/* 14668 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14671 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14689 >+/* 14675 */ MCD_OPC_CheckPredicate, 0, 134, 101, // Skip to: 40669 >+/* 14679 */ MCD_OPC_CheckField, 21, 1, 1, 128, 101, // Skip to: 40669 >+/* 14685 */ MCD_OPC_Decode, 201, 9, 105, // Opcode: SABALv4i16_v4i32 >+/* 14689 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14707 >+/* 14693 */ MCD_OPC_CheckPredicate, 0, 116, 101, // Skip to: 40669 >+/* 14697 */ MCD_OPC_CheckField, 21, 1, 1, 110, 101, // Skip to: 40669 >+/* 14703 */ MCD_OPC_Decode, 235, 15, 105, // Opcode: UABALv4i16_v4i32 >+/* 14707 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14725 >+/* 14711 */ MCD_OPC_CheckPredicate, 0, 98, 101, // Skip to: 40669 >+/* 14715 */ MCD_OPC_CheckField, 21, 1, 1, 92, 101, // Skip to: 40669 >+/* 14721 */ MCD_OPC_Decode, 203, 9, 120, // Opcode: SABALv8i16_v4i32 >+/* 14725 */ MCD_OPC_FilterValue, 3, 84, 101, // Skip to: 40669 >+/* 14729 */ MCD_OPC_CheckPredicate, 0, 80, 101, // Skip to: 40669 >+/* 14733 */ MCD_OPC_CheckField, 21, 1, 1, 74, 101, // Skip to: 40669 >+/* 14739 */ MCD_OPC_Decode, 237, 15, 120, // Opcode: UABALv8i16_v4i32 >+/* 14743 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 14822 >+/* 14747 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14750 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14768 >+/* 14754 */ MCD_OPC_CheckPredicate, 0, 55, 101, // Skip to: 40669 >+/* 14758 */ MCD_OPC_CheckField, 21, 1, 1, 49, 101, // Skip to: 40669 >+/* 14764 */ MCD_OPC_Decode, 239, 12, 89, // Opcode: SRSHLv4i16 >+/* 14768 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14786 >+/* 14772 */ MCD_OPC_CheckPredicate, 0, 37, 101, // Skip to: 40669 >+/* 14776 */ MCD_OPC_CheckField, 21, 1, 1, 31, 101, // Skip to: 40669 >+/* 14782 */ MCD_OPC_Decode, 231, 17, 89, // Opcode: URSHLv4i16 >+/* 14786 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14804 >+/* 14790 */ MCD_OPC_CheckPredicate, 0, 19, 101, // Skip to: 40669 >+/* 14794 */ MCD_OPC_CheckField, 21, 1, 1, 13, 101, // Skip to: 40669 >+/* 14800 */ MCD_OPC_Decode, 241, 12, 112, // Opcode: SRSHLv8i16 >+/* 14804 */ MCD_OPC_FilterValue, 3, 5, 101, // Skip to: 40669 >+/* 14808 */ MCD_OPC_CheckPredicate, 0, 1, 101, // Skip to: 40669 >+/* 14812 */ MCD_OPC_CheckField, 21, 1, 1, 251, 100, // Skip to: 40669 >+/* 14818 */ MCD_OPC_Decode, 233, 17, 112, // Opcode: URSHLv8i16 >+/* 14822 */ MCD_OPC_FilterValue, 22, 75, 0, // Skip to: 14901 >+/* 14826 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14829 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14847 >+/* 14833 */ MCD_OPC_CheckPredicate, 0, 232, 100, // Skip to: 40669 >+/* 14837 */ MCD_OPC_CheckField, 21, 1, 0, 226, 100, // Skip to: 40669 >+/* 14843 */ MCD_OPC_Decode, 188, 18, 89, // Opcode: UZP2v4i16 >+/* 14847 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14865 >+/* 14851 */ MCD_OPC_CheckPredicate, 0, 214, 100, // Skip to: 40669 >+/* 14855 */ MCD_OPC_CheckField, 16, 6, 32, 208, 100, // Skip to: 40669 >+/* 14861 */ MCD_OPC_Decode, 165, 9, 90, // Opcode: RBITv8i8 >+/* 14865 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14883 >+/* 14869 */ MCD_OPC_CheckPredicate, 0, 196, 100, // Skip to: 40669 >+/* 14873 */ MCD_OPC_CheckField, 21, 1, 0, 190, 100, // Skip to: 40669 >+/* 14879 */ MCD_OPC_Decode, 190, 18, 112, // Opcode: UZP2v8i16 >+/* 14883 */ MCD_OPC_FilterValue, 3, 182, 100, // Skip to: 40669 >+/* 14887 */ MCD_OPC_CheckPredicate, 0, 178, 100, // Skip to: 40669 >+/* 14891 */ MCD_OPC_CheckField, 16, 6, 32, 172, 100, // Skip to: 40669 >+/* 14897 */ MCD_OPC_Decode, 164, 9, 117, // Opcode: RBITv16i8 >+/* 14901 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 14980 >+/* 14905 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14908 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14926 >+/* 14912 */ MCD_OPC_CheckPredicate, 0, 153, 100, // Skip to: 40669 >+/* 14916 */ MCD_OPC_CheckField, 21, 1, 1, 147, 100, // Skip to: 40669 >+/* 14922 */ MCD_OPC_Decode, 247, 11, 89, // Opcode: SQRSHLv4i16 >+/* 14926 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14944 >+/* 14930 */ MCD_OPC_CheckPredicate, 0, 135, 100, // Skip to: 40669 >+/* 14934 */ MCD_OPC_CheckField, 21, 1, 1, 129, 100, // Skip to: 40669 >+/* 14940 */ MCD_OPC_Decode, 155, 17, 89, // Opcode: UQRSHLv4i16 >+/* 14944 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14962 >+/* 14948 */ MCD_OPC_CheckPredicate, 0, 117, 100, // Skip to: 40669 >+/* 14952 */ MCD_OPC_CheckField, 21, 1, 1, 111, 100, // Skip to: 40669 >+/* 14958 */ MCD_OPC_Decode, 249, 11, 112, // Opcode: SQRSHLv8i16 >+/* 14962 */ MCD_OPC_FilterValue, 3, 103, 100, // Skip to: 40669 >+/* 14966 */ MCD_OPC_CheckPredicate, 0, 99, 100, // Skip to: 40669 >+/* 14970 */ MCD_OPC_CheckField, 21, 1, 1, 93, 100, // Skip to: 40669 >+/* 14976 */ MCD_OPC_Decode, 157, 17, 112, // Opcode: UQRSHLv8i16 >+/* 14980 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 15059 >+/* 14984 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 14987 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15005 >+/* 14991 */ MCD_OPC_CheckPredicate, 0, 74, 100, // Skip to: 40669 >+/* 14995 */ MCD_OPC_CheckField, 21, 1, 1, 68, 100, // Skip to: 40669 >+/* 15001 */ MCD_OPC_Decode, 151, 15, 103, // Opcode: SUBHNv4i32_v4i16 >+/* 15005 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15023 >+/* 15009 */ MCD_OPC_CheckPredicate, 0, 56, 100, // Skip to: 40669 >+/* 15013 */ MCD_OPC_CheckField, 21, 1, 1, 50, 100, // Skip to: 40669 >+/* 15019 */ MCD_OPC_Decode, 195, 9, 103, // Opcode: RSUBHNv4i32_v4i16 >+/* 15023 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15041 >+/* 15027 */ MCD_OPC_CheckPredicate, 0, 38, 100, // Skip to: 40669 >+/* 15031 */ MCD_OPC_CheckField, 21, 1, 1, 32, 100, // Skip to: 40669 >+/* 15037 */ MCD_OPC_Decode, 152, 15, 120, // Opcode: SUBHNv4i32_v8i16 >+/* 15041 */ MCD_OPC_FilterValue, 3, 24, 100, // Skip to: 40669 >+/* 15045 */ MCD_OPC_CheckPredicate, 0, 20, 100, // Skip to: 40669 >+/* 15049 */ MCD_OPC_CheckField, 21, 1, 1, 14, 100, // Skip to: 40669 >+/* 15055 */ MCD_OPC_Decode, 196, 9, 120, // Opcode: RSUBHNv4i32_v8i16 >+/* 15059 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 15138 >+/* 15063 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15066 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15084 >+/* 15070 */ MCD_OPC_CheckPredicate, 0, 251, 99, // Skip to: 40669 >+/* 15074 */ MCD_OPC_CheckField, 21, 1, 1, 245, 99, // Skip to: 40669 >+/* 15080 */ MCD_OPC_Decode, 216, 10, 89, // Opcode: SMAXv4i16 >+/* 15084 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15102 >+/* 15088 */ MCD_OPC_CheckPredicate, 0, 233, 99, // Skip to: 40669 >+/* 15092 */ MCD_OPC_CheckField, 21, 1, 1, 227, 99, // Skip to: 40669 >+/* 15098 */ MCD_OPC_Decode, 208, 16, 89, // Opcode: UMAXv4i16 >+/* 15102 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15120 >+/* 15106 */ MCD_OPC_CheckPredicate, 0, 215, 99, // Skip to: 40669 >+/* 15110 */ MCD_OPC_CheckField, 21, 1, 1, 209, 99, // Skip to: 40669 >+/* 15116 */ MCD_OPC_Decode, 218, 10, 112, // Opcode: SMAXv8i16 >+/* 15120 */ MCD_OPC_FilterValue, 3, 201, 99, // Skip to: 40669 >+/* 15124 */ MCD_OPC_CheckPredicate, 0, 197, 99, // Skip to: 40669 >+/* 15128 */ MCD_OPC_CheckField, 21, 1, 1, 191, 99, // Skip to: 40669 >+/* 15134 */ MCD_OPC_Decode, 210, 16, 112, // Opcode: UMAXv8i16 >+/* 15138 */ MCD_OPC_FilterValue, 26, 165, 0, // Skip to: 15307 >+/* 15142 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15145 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15195 >+/* 15149 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 15152 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15164 >+/* 15156 */ MCD_OPC_CheckPredicate, 0, 165, 99, // Skip to: 40669 >+/* 15160 */ MCD_OPC_Decode, 229, 15, 89, // Opcode: TRN2v4i16 >+/* 15164 */ MCD_OPC_FilterValue, 1, 157, 99, // Skip to: 40669 >+/* 15168 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 15171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15183 >+/* 15175 */ MCD_OPC_CheckPredicate, 0, 146, 99, // Skip to: 40669 >+/* 15179 */ MCD_OPC_Decode, 225, 9, 99, // Opcode: SADALPv4i16_v2i32 >+/* 15183 */ MCD_OPC_FilterValue, 1, 138, 99, // Skip to: 40669 >+/* 15187 */ MCD_OPC_CheckPredicate, 0, 134, 99, // Skip to: 40669 >+/* 15191 */ MCD_OPC_Decode, 196, 3, 95, // Opcode: FCVTNv2i32 >+/* 15195 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 15226 >+/* 15199 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 15202 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15214 >+/* 15206 */ MCD_OPC_CheckPredicate, 0, 115, 99, // Skip to: 40669 >+/* 15210 */ MCD_OPC_Decode, 131, 16, 99, // Opcode: UADALPv4i16_v2i32 >+/* 15214 */ MCD_OPC_FilterValue, 33, 107, 99, // Skip to: 40669 >+/* 15218 */ MCD_OPC_CheckPredicate, 0, 103, 99, // Skip to: 40669 >+/* 15222 */ MCD_OPC_Decode, 221, 3, 95, // Opcode: FCVTXNv2f32 >+/* 15226 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15276 >+/* 15230 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 15233 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15245 >+/* 15237 */ MCD_OPC_CheckPredicate, 0, 84, 99, // Skip to: 40669 >+/* 15241 */ MCD_OPC_Decode, 231, 15, 112, // Opcode: TRN2v8i16 >+/* 15245 */ MCD_OPC_FilterValue, 1, 76, 99, // Skip to: 40669 >+/* 15249 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 15252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15264 >+/* 15256 */ MCD_OPC_CheckPredicate, 0, 65, 99, // Skip to: 40669 >+/* 15260 */ MCD_OPC_Decode, 227, 9, 126, // Opcode: SADALPv8i16_v4i32 >+/* 15264 */ MCD_OPC_FilterValue, 1, 57, 99, // Skip to: 40669 >+/* 15268 */ MCD_OPC_CheckPredicate, 0, 53, 99, // Skip to: 40669 >+/* 15272 */ MCD_OPC_Decode, 198, 3, 126, // Opcode: FCVTNv4i32 >+/* 15276 */ MCD_OPC_FilterValue, 3, 45, 99, // Skip to: 40669 >+/* 15280 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 15283 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15295 >+/* 15287 */ MCD_OPC_CheckPredicate, 0, 34, 99, // Skip to: 40669 >+/* 15291 */ MCD_OPC_Decode, 133, 16, 126, // Opcode: UADALPv8i16_v4i32 >+/* 15295 */ MCD_OPC_FilterValue, 33, 26, 99, // Skip to: 40669 >+/* 15299 */ MCD_OPC_CheckPredicate, 0, 22, 99, // Skip to: 40669 >+/* 15303 */ MCD_OPC_Decode, 222, 3, 126, // Opcode: FCVTXNv4f32 >+/* 15307 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 15386 >+/* 15311 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15314 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15332 >+/* 15318 */ MCD_OPC_CheckPredicate, 0, 3, 99, // Skip to: 40669 >+/* 15322 */ MCD_OPC_CheckField, 21, 1, 1, 253, 98, // Skip to: 40669 >+/* 15328 */ MCD_OPC_Decode, 234, 10, 89, // Opcode: SMINv4i16 >+/* 15332 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15350 >+/* 15336 */ MCD_OPC_CheckPredicate, 0, 241, 98, // Skip to: 40669 >+/* 15340 */ MCD_OPC_CheckField, 21, 1, 1, 235, 98, // Skip to: 40669 >+/* 15346 */ MCD_OPC_Decode, 225, 16, 89, // Opcode: UMINv4i16 >+/* 15350 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15368 >+/* 15354 */ MCD_OPC_CheckPredicate, 0, 223, 98, // Skip to: 40669 >+/* 15358 */ MCD_OPC_CheckField, 21, 1, 1, 217, 98, // Skip to: 40669 >+/* 15364 */ MCD_OPC_Decode, 236, 10, 112, // Opcode: SMINv8i16 >+/* 15368 */ MCD_OPC_FilterValue, 3, 209, 98, // Skip to: 40669 >+/* 15372 */ MCD_OPC_CheckPredicate, 0, 205, 98, // Skip to: 40669 >+/* 15376 */ MCD_OPC_CheckField, 21, 1, 1, 199, 98, // Skip to: 40669 >+/* 15382 */ MCD_OPC_Decode, 227, 16, 112, // Opcode: UMINv8i16 >+/* 15386 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 15465 >+/* 15390 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15393 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15411 >+/* 15397 */ MCD_OPC_CheckPredicate, 0, 180, 98, // Skip to: 40669 >+/* 15401 */ MCD_OPC_CheckField, 21, 1, 1, 174, 98, // Skip to: 40669 >+/* 15407 */ MCD_OPC_Decode, 213, 9, 85, // Opcode: SABDLv4i16_v4i32 >+/* 15411 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15429 >+/* 15415 */ MCD_OPC_CheckPredicate, 0, 162, 98, // Skip to: 40669 >+/* 15419 */ MCD_OPC_CheckField, 21, 1, 1, 156, 98, // Skip to: 40669 >+/* 15425 */ MCD_OPC_Decode, 247, 15, 85, // Opcode: UABDLv4i16_v4i32 >+/* 15429 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15447 >+/* 15433 */ MCD_OPC_CheckPredicate, 0, 144, 98, // Skip to: 40669 >+/* 15437 */ MCD_OPC_CheckField, 21, 1, 1, 138, 98, // Skip to: 40669 >+/* 15443 */ MCD_OPC_Decode, 215, 9, 112, // Opcode: SABDLv8i16_v4i32 >+/* 15447 */ MCD_OPC_FilterValue, 3, 130, 98, // Skip to: 40669 >+/* 15451 */ MCD_OPC_CheckPredicate, 0, 126, 98, // Skip to: 40669 >+/* 15455 */ MCD_OPC_CheckField, 21, 1, 1, 120, 98, // Skip to: 40669 >+/* 15461 */ MCD_OPC_Decode, 249, 15, 112, // Opcode: UABDLv8i16_v4i32 >+/* 15465 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 15544 >+/* 15469 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15472 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15490 >+/* 15476 */ MCD_OPC_CheckPredicate, 0, 101, 98, // Skip to: 40669 >+/* 15480 */ MCD_OPC_CheckField, 21, 1, 1, 95, 98, // Skip to: 40669 >+/* 15486 */ MCD_OPC_Decode, 219, 9, 89, // Opcode: SABDv4i16 >+/* 15490 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15508 >+/* 15494 */ MCD_OPC_CheckPredicate, 0, 83, 98, // Skip to: 40669 >+/* 15498 */ MCD_OPC_CheckField, 21, 1, 1, 77, 98, // Skip to: 40669 >+/* 15504 */ MCD_OPC_Decode, 253, 15, 89, // Opcode: UABDv4i16 >+/* 15508 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15526 >+/* 15512 */ MCD_OPC_CheckPredicate, 0, 65, 98, // Skip to: 40669 >+/* 15516 */ MCD_OPC_CheckField, 21, 1, 1, 59, 98, // Skip to: 40669 >+/* 15522 */ MCD_OPC_Decode, 221, 9, 112, // Opcode: SABDv8i16 >+/* 15526 */ MCD_OPC_FilterValue, 3, 51, 98, // Skip to: 40669 >+/* 15530 */ MCD_OPC_CheckPredicate, 0, 47, 98, // Skip to: 40669 >+/* 15534 */ MCD_OPC_CheckField, 21, 1, 1, 41, 98, // Skip to: 40669 >+/* 15540 */ MCD_OPC_Decode, 255, 15, 112, // Opcode: UABDv8i16 >+/* 15544 */ MCD_OPC_FilterValue, 30, 139, 0, // Skip to: 15687 >+/* 15548 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15551 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15601 >+/* 15555 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 15558 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15570 >+/* 15562 */ MCD_OPC_CheckPredicate, 0, 15, 98, // Skip to: 40669 >+/* 15566 */ MCD_OPC_Decode, 208, 18, 89, // Opcode: ZIP2v4i16 >+/* 15570 */ MCD_OPC_FilterValue, 1, 7, 98, // Skip to: 40669 >+/* 15574 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 15577 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15589 >+/* 15581 */ MCD_OPC_CheckPredicate, 0, 252, 97, // Skip to: 40669 >+/* 15585 */ MCD_OPC_Decode, 154, 11, 90, // Opcode: SQABSv4i16 >+/* 15589 */ MCD_OPC_FilterValue, 1, 244, 97, // Skip to: 40669 >+/* 15593 */ MCD_OPC_CheckPredicate, 0, 240, 97, // Skip to: 40669 >+/* 15597 */ MCD_OPC_Decode, 156, 3, 108, // Opcode: FCVTLv2i32 >+/* 15601 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15619 >+/* 15605 */ MCD_OPC_CheckPredicate, 0, 228, 97, // Skip to: 40669 >+/* 15609 */ MCD_OPC_CheckField, 16, 6, 32, 222, 97, // Skip to: 40669 >+/* 15615 */ MCD_OPC_Decode, 224, 11, 90, // Opcode: SQNEGv4i16 >+/* 15619 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15669 >+/* 15623 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 15626 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15638 >+/* 15630 */ MCD_OPC_CheckPredicate, 0, 203, 97, // Skip to: 40669 >+/* 15634 */ MCD_OPC_Decode, 210, 18, 112, // Opcode: ZIP2v8i16 >+/* 15638 */ MCD_OPC_FilterValue, 1, 195, 97, // Skip to: 40669 >+/* 15642 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 15645 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15657 >+/* 15649 */ MCD_OPC_CheckPredicate, 0, 184, 97, // Skip to: 40669 >+/* 15653 */ MCD_OPC_Decode, 156, 11, 117, // Opcode: SQABSv8i16 >+/* 15657 */ MCD_OPC_FilterValue, 1, 176, 97, // Skip to: 40669 >+/* 15661 */ MCD_OPC_CheckPredicate, 0, 172, 97, // Skip to: 40669 >+/* 15665 */ MCD_OPC_Decode, 158, 3, 117, // Opcode: FCVTLv4i32 >+/* 15669 */ MCD_OPC_FilterValue, 3, 164, 97, // Skip to: 40669 >+/* 15673 */ MCD_OPC_CheckPredicate, 0, 160, 97, // Skip to: 40669 >+/* 15677 */ MCD_OPC_CheckField, 16, 6, 32, 154, 97, // Skip to: 40669 >+/* 15683 */ MCD_OPC_Decode, 226, 11, 117, // Opcode: SQNEGv8i16 >+/* 15687 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 15766 >+/* 15691 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15694 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15712 >+/* 15698 */ MCD_OPC_CheckPredicate, 0, 135, 97, // Skip to: 40669 >+/* 15702 */ MCD_OPC_CheckField, 21, 1, 1, 129, 97, // Skip to: 40669 >+/* 15708 */ MCD_OPC_Decode, 207, 9, 109, // Opcode: SABAv4i16 >+/* 15712 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15730 >+/* 15716 */ MCD_OPC_CheckPredicate, 0, 117, 97, // Skip to: 40669 >+/* 15720 */ MCD_OPC_CheckField, 21, 1, 1, 111, 97, // Skip to: 40669 >+/* 15726 */ MCD_OPC_Decode, 241, 15, 109, // Opcode: UABAv4i16 >+/* 15730 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15748 >+/* 15734 */ MCD_OPC_CheckPredicate, 0, 99, 97, // Skip to: 40669 >+/* 15738 */ MCD_OPC_CheckField, 21, 1, 1, 93, 97, // Skip to: 40669 >+/* 15744 */ MCD_OPC_Decode, 209, 9, 120, // Opcode: SABAv8i16 >+/* 15748 */ MCD_OPC_FilterValue, 3, 85, 97, // Skip to: 40669 >+/* 15752 */ MCD_OPC_CheckPredicate, 0, 81, 97, // Skip to: 40669 >+/* 15756 */ MCD_OPC_CheckField, 21, 1, 1, 75, 97, // Skip to: 40669 >+/* 15762 */ MCD_OPC_Decode, 243, 15, 120, // Opcode: UABAv8i16 >+/* 15766 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 15845 >+/* 15770 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15773 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15791 >+/* 15777 */ MCD_OPC_CheckPredicate, 0, 56, 97, // Skip to: 40669 >+/* 15781 */ MCD_OPC_CheckField, 21, 1, 1, 50, 97, // Skip to: 40669 >+/* 15787 */ MCD_OPC_Decode, 242, 10, 105, // Opcode: SMLALv4i16_v4i32 >+/* 15791 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15809 >+/* 15795 */ MCD_OPC_CheckPredicate, 0, 38, 97, // Skip to: 40669 >+/* 15799 */ MCD_OPC_CheckField, 21, 1, 1, 32, 97, // Skip to: 40669 >+/* 15805 */ MCD_OPC_Decode, 233, 16, 105, // Opcode: UMLALv4i16_v4i32 >+/* 15809 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15827 >+/* 15813 */ MCD_OPC_CheckPredicate, 0, 20, 97, // Skip to: 40669 >+/* 15817 */ MCD_OPC_CheckField, 21, 1, 1, 14, 97, // Skip to: 40669 >+/* 15823 */ MCD_OPC_Decode, 246, 10, 120, // Opcode: SMLALv8i16_v4i32 >+/* 15827 */ MCD_OPC_FilterValue, 3, 6, 97, // Skip to: 40669 >+/* 15831 */ MCD_OPC_CheckPredicate, 0, 2, 97, // Skip to: 40669 >+/* 15835 */ MCD_OPC_CheckField, 21, 1, 1, 252, 96, // Skip to: 40669 >+/* 15841 */ MCD_OPC_Decode, 237, 16, 120, // Opcode: UMLALv8i16_v4i32 >+/* 15845 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 15922 >+/* 15849 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15852 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 15869 >+/* 15856 */ MCD_OPC_CheckPredicate, 0, 233, 96, // Skip to: 40669 >+/* 15860 */ MCD_OPC_CheckField, 21, 1, 1, 227, 96, // Skip to: 40669 >+/* 15866 */ MCD_OPC_Decode, 73, 89, // Opcode: ADDv4i16 >+/* 15869 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15887 >+/* 15873 */ MCD_OPC_CheckPredicate, 0, 216, 96, // Skip to: 40669 >+/* 15877 */ MCD_OPC_CheckField, 21, 1, 1, 210, 96, // Skip to: 40669 >+/* 15883 */ MCD_OPC_Decode, 177, 15, 89, // Opcode: SUBv4i16 >+/* 15887 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 15904 >+/* 15891 */ MCD_OPC_CheckPredicate, 0, 198, 96, // Skip to: 40669 >+/* 15895 */ MCD_OPC_CheckField, 21, 1, 1, 192, 96, // Skip to: 40669 >+/* 15901 */ MCD_OPC_Decode, 75, 112, // Opcode: ADDv8i16 >+/* 15904 */ MCD_OPC_FilterValue, 3, 185, 96, // Skip to: 40669 >+/* 15908 */ MCD_OPC_CheckPredicate, 0, 181, 96, // Skip to: 40669 >+/* 15912 */ MCD_OPC_CheckField, 21, 1, 1, 175, 96, // Skip to: 40669 >+/* 15918 */ MCD_OPC_Decode, 179, 15, 112, // Opcode: SUBv8i16 >+/* 15922 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 16027 >+/* 15926 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 15929 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15947 >+/* 15933 */ MCD_OPC_CheckPredicate, 0, 156, 96, // Skip to: 40669 >+/* 15937 */ MCD_OPC_CheckField, 16, 6, 32, 150, 96, // Skip to: 40669 >+/* 15943 */ MCD_OPC_Decode, 199, 1, 90, // Opcode: CMGTv4i16rz >+/* 15947 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15965 >+/* 15951 */ MCD_OPC_CheckPredicate, 0, 138, 96, // Skip to: 40669 >+/* 15955 */ MCD_OPC_CheckField, 16, 6, 32, 132, 96, // Skip to: 40669 >+/* 15961 */ MCD_OPC_Decode, 183, 1, 90, // Opcode: CMGEv4i16rz >+/* 15965 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 15996 >+/* 15969 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 15972 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15984 >+/* 15976 */ MCD_OPC_CheckPredicate, 0, 113, 96, // Skip to: 40669 >+/* 15980 */ MCD_OPC_Decode, 203, 1, 117, // Opcode: CMGTv8i16rz >+/* 15984 */ MCD_OPC_FilterValue, 33, 105, 96, // Skip to: 40669 >+/* 15988 */ MCD_OPC_CheckPredicate, 0, 101, 96, // Skip to: 40669 >+/* 15992 */ MCD_OPC_Decode, 168, 5, 117, // Opcode: FRINTNv2f64 >+/* 15996 */ MCD_OPC_FilterValue, 3, 93, 96, // Skip to: 40669 >+/* 16000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16003 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16015 >+/* 16007 */ MCD_OPC_CheckPredicate, 0, 82, 96, // Skip to: 40669 >+/* 16011 */ MCD_OPC_Decode, 187, 1, 117, // Opcode: CMGEv8i16rz >+/* 16015 */ MCD_OPC_FilterValue, 33, 74, 96, // Skip to: 40669 >+/* 16019 */ MCD_OPC_CheckPredicate, 0, 70, 96, // Skip to: 40669 >+/* 16023 */ MCD_OPC_Decode, 153, 5, 117, // Opcode: FRINTAv2f64 >+/* 16027 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 16106 >+/* 16031 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16034 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16052 >+/* 16038 */ MCD_OPC_CheckPredicate, 0, 51, 96, // Skip to: 40669 >+/* 16042 */ MCD_OPC_CheckField, 21, 1, 1, 45, 96, // Skip to: 40669 >+/* 16048 */ MCD_OPC_Decode, 242, 1, 89, // Opcode: CMTSTv4i16 >+/* 16052 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16070 >+/* 16056 */ MCD_OPC_CheckPredicate, 0, 33, 96, // Skip to: 40669 >+/* 16060 */ MCD_OPC_CheckField, 21, 1, 1, 27, 96, // Skip to: 40669 >+/* 16066 */ MCD_OPC_Decode, 166, 1, 89, // Opcode: CMEQv4i16 >+/* 16070 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16088 >+/* 16074 */ MCD_OPC_CheckPredicate, 0, 15, 96, // Skip to: 40669 >+/* 16078 */ MCD_OPC_CheckField, 21, 1, 1, 9, 96, // Skip to: 40669 >+/* 16084 */ MCD_OPC_Decode, 244, 1, 112, // Opcode: CMTSTv8i16 >+/* 16088 */ MCD_OPC_FilterValue, 3, 1, 96, // Skip to: 40669 >+/* 16092 */ MCD_OPC_CheckPredicate, 0, 253, 95, // Skip to: 40669 >+/* 16096 */ MCD_OPC_CheckField, 21, 1, 1, 247, 95, // Skip to: 40669 >+/* 16102 */ MCD_OPC_Decode, 170, 1, 112, // Opcode: CMEQv8i16 >+/* 16106 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 16149 >+/* 16110 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16113 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16131 >+/* 16117 */ MCD_OPC_CheckPredicate, 0, 228, 95, // Skip to: 40669 >+/* 16121 */ MCD_OPC_CheckField, 21, 1, 1, 222, 95, // Skip to: 40669 >+/* 16127 */ MCD_OPC_Decode, 176, 11, 105, // Opcode: SQDMLALv4i16_v4i32 >+/* 16131 */ MCD_OPC_FilterValue, 2, 214, 95, // Skip to: 40669 >+/* 16135 */ MCD_OPC_CheckPredicate, 0, 210, 95, // Skip to: 40669 >+/* 16139 */ MCD_OPC_CheckField, 21, 1, 1, 204, 95, // Skip to: 40669 >+/* 16145 */ MCD_OPC_Decode, 180, 11, 120, // Opcode: SQDMLALv8i16_v4i32 >+/* 16149 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 16228 >+/* 16153 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16156 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16174 >+/* 16160 */ MCD_OPC_CheckPredicate, 0, 185, 95, // Skip to: 40669 >+/* 16164 */ MCD_OPC_CheckField, 21, 1, 1, 179, 95, // Skip to: 40669 >+/* 16170 */ MCD_OPC_Decode, 183, 8, 109, // Opcode: MLAv4i16 >+/* 16174 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16192 >+/* 16178 */ MCD_OPC_CheckPredicate, 0, 167, 95, // Skip to: 40669 >+/* 16182 */ MCD_OPC_CheckField, 21, 1, 1, 161, 95, // Skip to: 40669 >+/* 16188 */ MCD_OPC_Decode, 193, 8, 109, // Opcode: MLSv4i16 >+/* 16192 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16210 >+/* 16196 */ MCD_OPC_CheckPredicate, 0, 149, 95, // Skip to: 40669 >+/* 16200 */ MCD_OPC_CheckField, 21, 1, 1, 143, 95, // Skip to: 40669 >+/* 16206 */ MCD_OPC_Decode, 187, 8, 120, // Opcode: MLAv8i16 >+/* 16210 */ MCD_OPC_FilterValue, 3, 135, 95, // Skip to: 40669 >+/* 16214 */ MCD_OPC_CheckPredicate, 0, 131, 95, // Skip to: 40669 >+/* 16218 */ MCD_OPC_CheckField, 21, 1, 1, 125, 95, // Skip to: 40669 >+/* 16224 */ MCD_OPC_Decode, 197, 8, 120, // Opcode: MLSv8i16 >+/* 16228 */ MCD_OPC_FilterValue, 38, 101, 0, // Skip to: 16333 >+/* 16232 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16235 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16253 >+/* 16239 */ MCD_OPC_CheckPredicate, 0, 106, 95, // Skip to: 40669 >+/* 16243 */ MCD_OPC_CheckField, 16, 6, 32, 100, 95, // Skip to: 40669 >+/* 16249 */ MCD_OPC_Decode, 167, 1, 90, // Opcode: CMEQv4i16rz >+/* 16253 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16271 >+/* 16257 */ MCD_OPC_CheckPredicate, 0, 88, 95, // Skip to: 40669 >+/* 16261 */ MCD_OPC_CheckField, 16, 6, 32, 82, 95, // Skip to: 40669 >+/* 16267 */ MCD_OPC_Decode, 226, 1, 90, // Opcode: CMLEv4i16rz >+/* 16271 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 16302 >+/* 16275 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16278 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16290 >+/* 16282 */ MCD_OPC_CheckPredicate, 0, 63, 95, // Skip to: 40669 >+/* 16286 */ MCD_OPC_Decode, 171, 1, 117, // Opcode: CMEQv8i16rz >+/* 16290 */ MCD_OPC_FilterValue, 33, 55, 95, // Skip to: 40669 >+/* 16294 */ MCD_OPC_CheckPredicate, 0, 51, 95, // Skip to: 40669 >+/* 16298 */ MCD_OPC_Decode, 163, 5, 117, // Opcode: FRINTMv2f64 >+/* 16302 */ MCD_OPC_FilterValue, 3, 43, 95, // Skip to: 40669 >+/* 16306 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16309 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16321 >+/* 16313 */ MCD_OPC_CheckPredicate, 0, 32, 95, // Skip to: 40669 >+/* 16317 */ MCD_OPC_Decode, 228, 1, 117, // Opcode: CMLEv8i16rz >+/* 16321 */ MCD_OPC_FilterValue, 33, 24, 95, // Skip to: 40669 >+/* 16325 */ MCD_OPC_CheckPredicate, 0, 20, 95, // Skip to: 40669 >+/* 16329 */ MCD_OPC_Decode, 178, 5, 117, // Opcode: FRINTXv2f64 >+/* 16333 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 16376 >+/* 16337 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16340 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16358 >+/* 16344 */ MCD_OPC_CheckPredicate, 0, 1, 95, // Skip to: 40669 >+/* 16348 */ MCD_OPC_CheckField, 21, 1, 1, 251, 94, // Skip to: 40669 >+/* 16354 */ MCD_OPC_Decode, 232, 8, 89, // Opcode: MULv4i16 >+/* 16358 */ MCD_OPC_FilterValue, 2, 243, 94, // Skip to: 40669 >+/* 16362 */ MCD_OPC_CheckPredicate, 0, 239, 94, // Skip to: 40669 >+/* 16366 */ MCD_OPC_CheckField, 21, 1, 1, 233, 94, // Skip to: 40669 >+/* 16372 */ MCD_OPC_Decode, 236, 8, 112, // Opcode: MULv8i16 >+/* 16376 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 16455 >+/* 16380 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16383 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16401 >+/* 16387 */ MCD_OPC_CheckPredicate, 0, 214, 94, // Skip to: 40669 >+/* 16391 */ MCD_OPC_CheckField, 21, 1, 1, 208, 94, // Skip to: 40669 >+/* 16397 */ MCD_OPC_Decode, 252, 10, 105, // Opcode: SMLSLv4i16_v4i32 >+/* 16401 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16419 >+/* 16405 */ MCD_OPC_CheckPredicate, 0, 196, 94, // Skip to: 40669 >+/* 16409 */ MCD_OPC_CheckField, 21, 1, 1, 190, 94, // Skip to: 40669 >+/* 16415 */ MCD_OPC_Decode, 243, 16, 105, // Opcode: UMLSLv4i16_v4i32 >+/* 16419 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16437 >+/* 16423 */ MCD_OPC_CheckPredicate, 0, 178, 94, // Skip to: 40669 >+/* 16427 */ MCD_OPC_CheckField, 21, 1, 1, 172, 94, // Skip to: 40669 >+/* 16433 */ MCD_OPC_Decode, 128, 11, 120, // Opcode: SMLSLv8i16_v4i32 >+/* 16437 */ MCD_OPC_FilterValue, 3, 164, 94, // Skip to: 40669 >+/* 16441 */ MCD_OPC_CheckPredicate, 0, 160, 94, // Skip to: 40669 >+/* 16445 */ MCD_OPC_CheckField, 21, 1, 1, 154, 94, // Skip to: 40669 >+/* 16451 */ MCD_OPC_Decode, 247, 16, 120, // Opcode: UMLSLv8i16_v4i32 >+/* 16455 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 16534 >+/* 16459 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16462 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16480 >+/* 16466 */ MCD_OPC_CheckPredicate, 0, 135, 94, // Skip to: 40669 >+/* 16470 */ MCD_OPC_CheckField, 21, 1, 1, 129, 94, // Skip to: 40669 >+/* 16476 */ MCD_OPC_Decode, 205, 10, 89, // Opcode: SMAXPv4i16 >+/* 16480 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16498 >+/* 16484 */ MCD_OPC_CheckPredicate, 0, 117, 94, // Skip to: 40669 >+/* 16488 */ MCD_OPC_CheckField, 21, 1, 1, 111, 94, // Skip to: 40669 >+/* 16494 */ MCD_OPC_Decode, 197, 16, 89, // Opcode: UMAXPv4i16 >+/* 16498 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16516 >+/* 16502 */ MCD_OPC_CheckPredicate, 0, 99, 94, // Skip to: 40669 >+/* 16506 */ MCD_OPC_CheckField, 21, 1, 1, 93, 94, // Skip to: 40669 >+/* 16512 */ MCD_OPC_Decode, 207, 10, 112, // Opcode: SMAXPv8i16 >+/* 16516 */ MCD_OPC_FilterValue, 3, 85, 94, // Skip to: 40669 >+/* 16520 */ MCD_OPC_CheckPredicate, 0, 81, 94, // Skip to: 40669 >+/* 16524 */ MCD_OPC_CheckField, 21, 1, 1, 75, 94, // Skip to: 40669 >+/* 16530 */ MCD_OPC_Decode, 199, 16, 112, // Opcode: UMAXPv8i16 >+/* 16534 */ MCD_OPC_FilterValue, 42, 179, 0, // Skip to: 16717 >+/* 16538 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16541 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 16572 >+/* 16545 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16548 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16560 >+/* 16552 */ MCD_OPC_CheckPredicate, 0, 49, 94, // Skip to: 40669 >+/* 16556 */ MCD_OPC_Decode, 234, 1, 90, // Opcode: CMLTv4i16rz >+/* 16560 */ MCD_OPC_FilterValue, 2, 41, 94, // Skip to: 40669 >+/* 16564 */ MCD_OPC_CheckPredicate, 0, 37, 94, // Skip to: 40669 >+/* 16568 */ MCD_OPC_Decode, 236, 1, 117, // Opcode: CMLTv8i16rz >+/* 16572 */ MCD_OPC_FilterValue, 33, 27, 0, // Skip to: 16603 >+/* 16576 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16579 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16591 >+/* 16583 */ MCD_OPC_CheckPredicate, 0, 18, 94, // Skip to: 40669 >+/* 16587 */ MCD_OPC_Decode, 185, 3, 117, // Opcode: FCVTNSv2f64 >+/* 16591 */ MCD_OPC_FilterValue, 3, 10, 94, // Skip to: 40669 >+/* 16595 */ MCD_OPC_CheckPredicate, 0, 6, 94, // Skip to: 40669 >+/* 16599 */ MCD_OPC_Decode, 194, 3, 117, // Opcode: FCVTNUv2f64 >+/* 16603 */ MCD_OPC_FilterValue, 48, 53, 0, // Skip to: 16660 >+/* 16607 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16610 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16622 >+/* 16614 */ MCD_OPC_CheckPredicate, 0, 243, 93, // Skip to: 40669 >+/* 16618 */ MCD_OPC_Decode, 210, 10, 100, // Opcode: SMAXVv4i16v >+/* 16622 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16634 >+/* 16626 */ MCD_OPC_CheckPredicate, 0, 231, 93, // Skip to: 40669 >+/* 16630 */ MCD_OPC_Decode, 202, 16, 100, // Opcode: UMAXVv4i16v >+/* 16634 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16647 >+/* 16638 */ MCD_OPC_CheckPredicate, 0, 219, 93, // Skip to: 40669 >+/* 16642 */ MCD_OPC_Decode, 212, 10, 131, 1, // Opcode: SMAXVv8i16v >+/* 16647 */ MCD_OPC_FilterValue, 3, 210, 93, // Skip to: 40669 >+/* 16651 */ MCD_OPC_CheckPredicate, 0, 206, 93, // Skip to: 40669 >+/* 16655 */ MCD_OPC_Decode, 204, 16, 131, 1, // Opcode: UMAXVv8i16v >+/* 16660 */ MCD_OPC_FilterValue, 49, 197, 93, // Skip to: 40669 >+/* 16664 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16679 >+/* 16671 */ MCD_OPC_CheckPredicate, 0, 186, 93, // Skip to: 40669 >+/* 16675 */ MCD_OPC_Decode, 228, 10, 100, // Opcode: SMINVv4i16v >+/* 16679 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16691 >+/* 16683 */ MCD_OPC_CheckPredicate, 0, 174, 93, // Skip to: 40669 >+/* 16687 */ MCD_OPC_Decode, 219, 16, 100, // Opcode: UMINVv4i16v >+/* 16691 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16704 >+/* 16695 */ MCD_OPC_CheckPredicate, 0, 162, 93, // Skip to: 40669 >+/* 16699 */ MCD_OPC_Decode, 230, 10, 131, 1, // Opcode: SMINVv8i16v >+/* 16704 */ MCD_OPC_FilterValue, 3, 153, 93, // Skip to: 40669 >+/* 16708 */ MCD_OPC_CheckPredicate, 0, 149, 93, // Skip to: 40669 >+/* 16712 */ MCD_OPC_Decode, 221, 16, 131, 1, // Opcode: UMINVv8i16v >+/* 16717 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 16796 >+/* 16721 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16742 >+/* 16728 */ MCD_OPC_CheckPredicate, 0, 129, 93, // Skip to: 40669 >+/* 16732 */ MCD_OPC_CheckField, 21, 1, 1, 123, 93, // Skip to: 40669 >+/* 16738 */ MCD_OPC_Decode, 223, 10, 89, // Opcode: SMINPv4i16 >+/* 16742 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16760 >+/* 16746 */ MCD_OPC_CheckPredicate, 0, 111, 93, // Skip to: 40669 >+/* 16750 */ MCD_OPC_CheckField, 21, 1, 1, 105, 93, // Skip to: 40669 >+/* 16756 */ MCD_OPC_Decode, 214, 16, 89, // Opcode: UMINPv4i16 >+/* 16760 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16778 >+/* 16764 */ MCD_OPC_CheckPredicate, 0, 93, 93, // Skip to: 40669 >+/* 16768 */ MCD_OPC_CheckField, 21, 1, 1, 87, 93, // Skip to: 40669 >+/* 16774 */ MCD_OPC_Decode, 225, 10, 112, // Opcode: SMINPv8i16 >+/* 16778 */ MCD_OPC_FilterValue, 3, 79, 93, // Skip to: 40669 >+/* 16782 */ MCD_OPC_CheckPredicate, 0, 75, 93, // Skip to: 40669 >+/* 16786 */ MCD_OPC_CheckField, 21, 1, 1, 69, 93, // Skip to: 40669 >+/* 16792 */ MCD_OPC_Decode, 216, 16, 112, // Opcode: UMINPv8i16 >+/* 16796 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 16839 >+/* 16800 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16803 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16821 >+/* 16807 */ MCD_OPC_CheckPredicate, 0, 50, 93, // Skip to: 40669 >+/* 16811 */ MCD_OPC_CheckField, 21, 1, 1, 44, 93, // Skip to: 40669 >+/* 16817 */ MCD_OPC_Decode, 188, 11, 105, // Opcode: SQDMLSLv4i16_v4i32 >+/* 16821 */ MCD_OPC_FilterValue, 2, 36, 93, // Skip to: 40669 >+/* 16825 */ MCD_OPC_CheckPredicate, 0, 32, 93, // Skip to: 40669 >+/* 16829 */ MCD_OPC_CheckField, 21, 1, 1, 26, 93, // Skip to: 40669 >+/* 16835 */ MCD_OPC_Decode, 192, 11, 120, // Opcode: SQDMLSLv8i16_v4i32 >+/* 16839 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 16918 >+/* 16843 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16846 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16864 >+/* 16850 */ MCD_OPC_CheckPredicate, 0, 7, 93, // Skip to: 40669 >+/* 16854 */ MCD_OPC_CheckField, 21, 1, 1, 1, 93, // Skip to: 40669 >+/* 16860 */ MCD_OPC_Decode, 199, 11, 89, // Opcode: SQDMULHv4i16 >+/* 16864 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16882 >+/* 16868 */ MCD_OPC_CheckPredicate, 0, 245, 92, // Skip to: 40669 >+/* 16872 */ MCD_OPC_CheckField, 21, 1, 1, 239, 92, // Skip to: 40669 >+/* 16878 */ MCD_OPC_Decode, 234, 11, 89, // Opcode: SQRDMULHv4i16 >+/* 16882 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16900 >+/* 16886 */ MCD_OPC_CheckPredicate, 0, 227, 92, // Skip to: 40669 >+/* 16890 */ MCD_OPC_CheckField, 21, 1, 1, 221, 92, // Skip to: 40669 >+/* 16896 */ MCD_OPC_Decode, 203, 11, 112, // Opcode: SQDMULHv8i16 >+/* 16900 */ MCD_OPC_FilterValue, 3, 213, 92, // Skip to: 40669 >+/* 16904 */ MCD_OPC_CheckPredicate, 0, 209, 92, // Skip to: 40669 >+/* 16908 */ MCD_OPC_CheckField, 21, 1, 1, 203, 92, // Skip to: 40669 >+/* 16914 */ MCD_OPC_Decode, 238, 11, 112, // Opcode: SQRDMULHv8i16 >+/* 16918 */ MCD_OPC_FilterValue, 46, 123, 0, // Skip to: 17045 >+/* 16922 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 16925 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 16954 >+/* 16929 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16932 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16943 >+/* 16936 */ MCD_OPC_CheckPredicate, 0, 177, 92, // Skip to: 40669 >+/* 16940 */ MCD_OPC_Decode, 24, 90, // Opcode: ABSv4i16 >+/* 16943 */ MCD_OPC_FilterValue, 49, 170, 92, // Skip to: 40669 >+/* 16947 */ MCD_OPC_CheckPredicate, 0, 166, 92, // Skip to: 40669 >+/* 16951 */ MCD_OPC_Decode, 56, 100, // Opcode: ADDVv4i16v >+/* 16954 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16972 >+/* 16958 */ MCD_OPC_CheckPredicate, 0, 155, 92, // Skip to: 40669 >+/* 16962 */ MCD_OPC_CheckField, 16, 6, 32, 149, 92, // Skip to: 40669 >+/* 16968 */ MCD_OPC_Decode, 249, 8, 90, // Opcode: NEGv4i16 >+/* 16972 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 17014 >+/* 16976 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 16979 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16990 >+/* 16983 */ MCD_OPC_CheckPredicate, 0, 130, 92, // Skip to: 40669 >+/* 16987 */ MCD_OPC_Decode, 26, 117, // Opcode: ABSv8i16 >+/* 16990 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 17002 >+/* 16994 */ MCD_OPC_CheckPredicate, 0, 119, 92, // Skip to: 40669 >+/* 16998 */ MCD_OPC_Decode, 167, 3, 117, // Opcode: FCVTMSv2f64 >+/* 17002 */ MCD_OPC_FilterValue, 49, 111, 92, // Skip to: 40669 >+/* 17006 */ MCD_OPC_CheckPredicate, 0, 107, 92, // Skip to: 40669 >+/* 17010 */ MCD_OPC_Decode, 58, 131, 1, // Opcode: ADDVv8i16v >+/* 17014 */ MCD_OPC_FilterValue, 3, 99, 92, // Skip to: 40669 >+/* 17018 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 17021 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 17033 >+/* 17025 */ MCD_OPC_CheckPredicate, 0, 88, 92, // Skip to: 40669 >+/* 17029 */ MCD_OPC_Decode, 251, 8, 117, // Opcode: NEGv8i16 >+/* 17033 */ MCD_OPC_FilterValue, 33, 80, 92, // Skip to: 40669 >+/* 17037 */ MCD_OPC_CheckPredicate, 0, 76, 92, // Skip to: 40669 >+/* 17041 */ MCD_OPC_Decode, 176, 3, 117, // Opcode: FCVTMUv2f64 >+/* 17045 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 17086 >+/* 17049 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17052 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 17069 >+/* 17056 */ MCD_OPC_CheckPredicate, 0, 57, 92, // Skip to: 40669 >+/* 17060 */ MCD_OPC_CheckField, 21, 1, 1, 51, 92, // Skip to: 40669 >+/* 17066 */ MCD_OPC_Decode, 42, 89, // Opcode: ADDPv4i16 >+/* 17069 */ MCD_OPC_FilterValue, 2, 44, 92, // Skip to: 40669 >+/* 17073 */ MCD_OPC_CheckPredicate, 0, 40, 92, // Skip to: 40669 >+/* 17077 */ MCD_OPC_CheckField, 21, 1, 1, 34, 92, // Skip to: 40669 >+/* 17083 */ MCD_OPC_Decode, 44, 112, // Opcode: ADDPv8i16 >+/* 17086 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 17165 >+/* 17090 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17093 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17111 >+/* 17097 */ MCD_OPC_CheckPredicate, 0, 16, 92, // Skip to: 40669 >+/* 17101 */ MCD_OPC_CheckField, 21, 1, 1, 10, 92, // Skip to: 40669 >+/* 17107 */ MCD_OPC_Decode, 141, 11, 85, // Opcode: SMULLv4i16_v4i32 >+/* 17111 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17129 >+/* 17115 */ MCD_OPC_CheckPredicate, 0, 254, 91, // Skip to: 40669 >+/* 17119 */ MCD_OPC_CheckField, 21, 1, 1, 248, 91, // Skip to: 40669 >+/* 17125 */ MCD_OPC_Decode, 131, 17, 85, // Opcode: UMULLv4i16_v4i32 >+/* 17129 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17147 >+/* 17133 */ MCD_OPC_CheckPredicate, 0, 236, 91, // Skip to: 40669 >+/* 17137 */ MCD_OPC_CheckField, 21, 1, 1, 230, 91, // Skip to: 40669 >+/* 17143 */ MCD_OPC_Decode, 145, 11, 112, // Opcode: SMULLv8i16_v4i32 >+/* 17147 */ MCD_OPC_FilterValue, 3, 222, 91, // Skip to: 40669 >+/* 17151 */ MCD_OPC_CheckPredicate, 0, 218, 91, // Skip to: 40669 >+/* 17155 */ MCD_OPC_CheckField, 21, 1, 1, 212, 91, // Skip to: 40669 >+/* 17161 */ MCD_OPC_Decode, 135, 17, 112, // Opcode: UMULLv8i16_v4i32 >+/* 17165 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 17208 >+/* 17169 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17172 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17190 >+/* 17176 */ MCD_OPC_CheckPredicate, 0, 193, 91, // Skip to: 40669 >+/* 17180 */ MCD_OPC_CheckField, 21, 1, 1, 187, 91, // Skip to: 40669 >+/* 17186 */ MCD_OPC_Decode, 170, 4, 112, // Opcode: FMAXNMv2f64 >+/* 17190 */ MCD_OPC_FilterValue, 3, 179, 91, // Skip to: 40669 >+/* 17194 */ MCD_OPC_CheckPredicate, 0, 175, 91, // Skip to: 40669 >+/* 17198 */ MCD_OPC_CheckField, 21, 1, 1, 169, 91, // Skip to: 40669 >+/* 17204 */ MCD_OPC_Decode, 163, 4, 112, // Opcode: FMAXNMPv2f64 >+/* 17208 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 17251 >+/* 17212 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17215 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17233 >+/* 17219 */ MCD_OPC_CheckPredicate, 0, 150, 91, // Skip to: 40669 >+/* 17223 */ MCD_OPC_CheckField, 16, 6, 33, 144, 91, // Skip to: 40669 >+/* 17229 */ MCD_OPC_Decode, 141, 3, 117, // Opcode: FCVTASv2f64 >+/* 17233 */ MCD_OPC_FilterValue, 3, 136, 91, // Skip to: 40669 >+/* 17237 */ MCD_OPC_CheckPredicate, 0, 132, 91, // Skip to: 40669 >+/* 17241 */ MCD_OPC_CheckField, 16, 6, 33, 126, 91, // Skip to: 40669 >+/* 17247 */ MCD_OPC_Decode, 150, 3, 117, // Opcode: FCVTAUv2f64 >+/* 17251 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 17275 >+/* 17255 */ MCD_OPC_CheckPredicate, 0, 114, 91, // Skip to: 40669 >+/* 17259 */ MCD_OPC_CheckField, 29, 3, 2, 108, 91, // Skip to: 40669 >+/* 17265 */ MCD_OPC_CheckField, 21, 1, 1, 102, 91, // Skip to: 40669 >+/* 17271 */ MCD_OPC_Decode, 207, 4, 120, // Opcode: FMLAv2f64 >+/* 17275 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 17318 >+/* 17279 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17282 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17300 >+/* 17286 */ MCD_OPC_CheckPredicate, 0, 83, 91, // Skip to: 40669 >+/* 17290 */ MCD_OPC_CheckField, 21, 1, 1, 77, 91, // Skip to: 40669 >+/* 17296 */ MCD_OPC_Decode, 212, 11, 85, // Opcode: SQDMULLv4i16_v4i32 >+/* 17300 */ MCD_OPC_FilterValue, 2, 69, 91, // Skip to: 40669 >+/* 17304 */ MCD_OPC_CheckPredicate, 0, 65, 91, // Skip to: 40669 >+/* 17308 */ MCD_OPC_CheckField, 21, 1, 1, 59, 91, // Skip to: 40669 >+/* 17314 */ MCD_OPC_Decode, 216, 11, 112, // Opcode: SQDMULLv8i16_v4i32 >+/* 17318 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 17361 >+/* 17322 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17325 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17343 >+/* 17329 */ MCD_OPC_CheckPredicate, 0, 40, 91, // Skip to: 40669 >+/* 17333 */ MCD_OPC_CheckField, 21, 1, 1, 34, 91, // Skip to: 40669 >+/* 17339 */ MCD_OPC_Decode, 206, 2, 112, // Opcode: FADDv2f64 >+/* 17343 */ MCD_OPC_FilterValue, 3, 26, 91, // Skip to: 40669 >+/* 17347 */ MCD_OPC_CheckPredicate, 0, 22, 91, // Skip to: 40669 >+/* 17351 */ MCD_OPC_CheckField, 21, 1, 1, 16, 91, // Skip to: 40669 >+/* 17357 */ MCD_OPC_Decode, 200, 2, 112, // Opcode: FADDPv2f64 >+/* 17361 */ MCD_OPC_FilterValue, 54, 39, 0, // Skip to: 17404 >+/* 17365 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17368 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17386 >+/* 17372 */ MCD_OPC_CheckPredicate, 0, 253, 90, // Skip to: 40669 >+/* 17376 */ MCD_OPC_CheckField, 16, 6, 33, 247, 90, // Skip to: 40669 >+/* 17382 */ MCD_OPC_Decode, 143, 10, 117, // Opcode: SCVTFv2f64 >+/* 17386 */ MCD_OPC_FilterValue, 3, 239, 90, // Skip to: 40669 >+/* 17390 */ MCD_OPC_CheckPredicate, 0, 235, 90, // Skip to: 40669 >+/* 17394 */ MCD_OPC_CheckField, 16, 6, 33, 229, 90, // Skip to: 40669 >+/* 17400 */ MCD_OPC_Decode, 173, 16, 117, // Opcode: UCVTFv2f64 >+/* 17404 */ MCD_OPC_FilterValue, 55, 39, 0, // Skip to: 17447 >+/* 17408 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17411 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17429 >+/* 17415 */ MCD_OPC_CheckPredicate, 0, 210, 90, // Skip to: 40669 >+/* 17419 */ MCD_OPC_CheckField, 21, 1, 1, 204, 90, // Skip to: 40669 >+/* 17425 */ MCD_OPC_Decode, 242, 4, 112, // Opcode: FMULXv2f64 >+/* 17429 */ MCD_OPC_FilterValue, 3, 196, 90, // Skip to: 40669 >+/* 17433 */ MCD_OPC_CheckPredicate, 0, 192, 90, // Skip to: 40669 >+/* 17437 */ MCD_OPC_CheckField, 21, 1, 1, 186, 90, // Skip to: 40669 >+/* 17443 */ MCD_OPC_Decode, 250, 4, 112, // Opcode: FMULv2f64 >+/* 17447 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 17490 >+/* 17451 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17454 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17472 >+/* 17458 */ MCD_OPC_CheckPredicate, 0, 167, 90, // Skip to: 40669 >+/* 17462 */ MCD_OPC_CheckField, 21, 1, 1, 161, 90, // Skip to: 40669 >+/* 17468 */ MCD_OPC_Decode, 217, 2, 112, // Opcode: FCMEQv2f64 >+/* 17472 */ MCD_OPC_FilterValue, 3, 153, 90, // Skip to: 40669 >+/* 17476 */ MCD_OPC_CheckPredicate, 0, 149, 90, // Skip to: 40669 >+/* 17480 */ MCD_OPC_CheckField, 21, 1, 1, 143, 90, // Skip to: 40669 >+/* 17486 */ MCD_OPC_Decode, 227, 2, 112, // Opcode: FCMGEv2f64 >+/* 17490 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 17514 >+/* 17494 */ MCD_OPC_CheckPredicate, 0, 131, 90, // Skip to: 40669 >+/* 17498 */ MCD_OPC_CheckField, 29, 3, 3, 125, 90, // Skip to: 40669 >+/* 17504 */ MCD_OPC_CheckField, 21, 1, 1, 119, 90, // Skip to: 40669 >+/* 17510 */ MCD_OPC_Decode, 191, 2, 112, // Opcode: FACGEv2f64 >+/* 17514 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 17557 >+/* 17518 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17521 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17539 >+/* 17525 */ MCD_OPC_CheckPredicate, 0, 100, 90, // Skip to: 40669 >+/* 17529 */ MCD_OPC_CheckField, 21, 1, 1, 94, 90, // Skip to: 40669 >+/* 17535 */ MCD_OPC_Decode, 180, 4, 112, // Opcode: FMAXv2f64 >+/* 17539 */ MCD_OPC_FilterValue, 3, 86, 90, // Skip to: 40669 >+/* 17543 */ MCD_OPC_CheckPredicate, 0, 82, 90, // Skip to: 40669 >+/* 17547 */ MCD_OPC_CheckField, 21, 1, 1, 76, 90, // Skip to: 40669 >+/* 17553 */ MCD_OPC_Decode, 173, 4, 112, // Opcode: FMAXPv2f64 >+/* 17557 */ MCD_OPC_FilterValue, 63, 68, 90, // Skip to: 40669 >+/* 17561 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17564 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17582 >+/* 17568 */ MCD_OPC_CheckPredicate, 0, 57, 90, // Skip to: 40669 >+/* 17572 */ MCD_OPC_CheckField, 21, 1, 1, 51, 90, // Skip to: 40669 >+/* 17578 */ MCD_OPC_Decode, 146, 5, 112, // Opcode: FRECPSv2f64 >+/* 17582 */ MCD_OPC_FilterValue, 3, 43, 90, // Skip to: 40669 >+/* 17586 */ MCD_OPC_CheckPredicate, 0, 39, 90, // Skip to: 40669 >+/* 17590 */ MCD_OPC_CheckField, 21, 1, 1, 33, 90, // Skip to: 40669 >+/* 17596 */ MCD_OPC_Decode, 156, 4, 112, // Opcode: FDIVv2f64 >+/* 17600 */ MCD_OPC_FilterValue, 10, 165, 19, // Skip to: 22633 >+/* 17604 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 17607 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 17686 >+/* 17611 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17614 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17632 >+/* 17618 */ MCD_OPC_CheckPredicate, 0, 7, 90, // Skip to: 40669 >+/* 17622 */ MCD_OPC_CheckField, 21, 1, 1, 1, 90, // Skip to: 40669 >+/* 17628 */ MCD_OPC_Decode, 241, 9, 85, // Opcode: SADDLv2i32_v2i64 >+/* 17632 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17650 >+/* 17636 */ MCD_OPC_CheckPredicate, 0, 245, 89, // Skip to: 40669 >+/* 17640 */ MCD_OPC_CheckField, 21, 1, 1, 239, 89, // Skip to: 40669 >+/* 17646 */ MCD_OPC_Decode, 147, 16, 85, // Opcode: UADDLv2i32_v2i64 >+/* 17650 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17668 >+/* 17654 */ MCD_OPC_CheckPredicate, 0, 227, 89, // Skip to: 40669 >+/* 17658 */ MCD_OPC_CheckField, 21, 1, 1, 221, 89, // Skip to: 40669 >+/* 17664 */ MCD_OPC_Decode, 243, 9, 112, // Opcode: SADDLv4i32_v2i64 >+/* 17668 */ MCD_OPC_FilterValue, 3, 213, 89, // Skip to: 40669 >+/* 17672 */ MCD_OPC_CheckPredicate, 0, 209, 89, // Skip to: 40669 >+/* 17676 */ MCD_OPC_CheckField, 21, 1, 1, 203, 89, // Skip to: 40669 >+/* 17682 */ MCD_OPC_Decode, 149, 16, 112, // Opcode: UADDLv4i32_v2i64 >+/* 17686 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 17765 >+/* 17690 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17693 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17711 >+/* 17697 */ MCD_OPC_CheckPredicate, 0, 184, 89, // Skip to: 40669 >+/* 17701 */ MCD_OPC_CheckField, 21, 1, 1, 178, 89, // Skip to: 40669 >+/* 17707 */ MCD_OPC_Decode, 163, 10, 89, // Opcode: SHADDv2i32 >+/* 17711 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17729 >+/* 17715 */ MCD_OPC_CheckPredicate, 0, 166, 89, // Skip to: 40669 >+/* 17719 */ MCD_OPC_CheckField, 21, 1, 1, 160, 89, // Skip to: 40669 >+/* 17725 */ MCD_OPC_Decode, 183, 16, 89, // Opcode: UHADDv2i32 >+/* 17729 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17747 >+/* 17733 */ MCD_OPC_CheckPredicate, 0, 148, 89, // Skip to: 40669 >+/* 17737 */ MCD_OPC_CheckField, 21, 1, 1, 142, 89, // Skip to: 40669 >+/* 17743 */ MCD_OPC_Decode, 165, 10, 112, // Opcode: SHADDv4i32 >+/* 17747 */ MCD_OPC_FilterValue, 3, 134, 89, // Skip to: 40669 >+/* 17751 */ MCD_OPC_CheckPredicate, 0, 130, 89, // Skip to: 40669 >+/* 17755 */ MCD_OPC_CheckField, 21, 1, 1, 124, 89, // Skip to: 40669 >+/* 17761 */ MCD_OPC_Decode, 185, 16, 112, // Opcode: UHADDv4i32 >+/* 17765 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 17808 >+/* 17769 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17772 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17790 >+/* 17776 */ MCD_OPC_CheckPredicate, 0, 105, 89, // Skip to: 40669 >+/* 17780 */ MCD_OPC_CheckField, 16, 6, 32, 99, 89, // Skip to: 40669 >+/* 17786 */ MCD_OPC_Decode, 178, 9, 90, // Opcode: REV64v2i32 >+/* 17790 */ MCD_OPC_FilterValue, 2, 91, 89, // Skip to: 40669 >+/* 17794 */ MCD_OPC_CheckPredicate, 0, 87, 89, // Skip to: 40669 >+/* 17798 */ MCD_OPC_CheckField, 16, 6, 32, 81, 89, // Skip to: 40669 >+/* 17804 */ MCD_OPC_Decode, 180, 9, 117, // Opcode: REV64v4i32 >+/* 17808 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 17887 >+/* 17812 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17815 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17833 >+/* 17819 */ MCD_OPC_CheckPredicate, 0, 62, 89, // Skip to: 40669 >+/* 17823 */ MCD_OPC_CheckField, 21, 1, 1, 56, 89, // Skip to: 40669 >+/* 17829 */ MCD_OPC_Decode, 163, 11, 89, // Opcode: SQADDv2i32 >+/* 17833 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17851 >+/* 17837 */ MCD_OPC_CheckPredicate, 0, 44, 89, // Skip to: 40669 >+/* 17841 */ MCD_OPC_CheckField, 21, 1, 1, 38, 89, // Skip to: 40669 >+/* 17847 */ MCD_OPC_Decode, 142, 17, 89, // Opcode: UQADDv2i32 >+/* 17851 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17869 >+/* 17855 */ MCD_OPC_CheckPredicate, 0, 26, 89, // Skip to: 40669 >+/* 17859 */ MCD_OPC_CheckField, 21, 1, 1, 20, 89, // Skip to: 40669 >+/* 17865 */ MCD_OPC_Decode, 166, 11, 112, // Opcode: SQADDv4i32 >+/* 17869 */ MCD_OPC_FilterValue, 3, 12, 89, // Skip to: 40669 >+/* 17873 */ MCD_OPC_CheckPredicate, 0, 8, 89, // Skip to: 40669 >+/* 17877 */ MCD_OPC_CheckField, 21, 1, 1, 2, 89, // Skip to: 40669 >+/* 17883 */ MCD_OPC_Decode, 145, 17, 112, // Opcode: UQADDv4i32 >+/* 17887 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 17966 >+/* 17891 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17894 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17912 >+/* 17898 */ MCD_OPC_CheckPredicate, 0, 239, 88, // Skip to: 40669 >+/* 17902 */ MCD_OPC_CheckField, 21, 1, 1, 233, 88, // Skip to: 40669 >+/* 17908 */ MCD_OPC_Decode, 247, 9, 93, // Opcode: SADDWv2i32_v2i64 >+/* 17912 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17930 >+/* 17916 */ MCD_OPC_CheckPredicate, 0, 221, 88, // Skip to: 40669 >+/* 17920 */ MCD_OPC_CheckField, 21, 1, 1, 215, 88, // Skip to: 40669 >+/* 17926 */ MCD_OPC_Decode, 153, 16, 93, // Opcode: UADDWv2i32_v2i64 >+/* 17930 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17948 >+/* 17934 */ MCD_OPC_CheckPredicate, 0, 203, 88, // Skip to: 40669 >+/* 17938 */ MCD_OPC_CheckField, 21, 1, 1, 197, 88, // Skip to: 40669 >+/* 17944 */ MCD_OPC_Decode, 249, 9, 112, // Opcode: SADDWv4i32_v2i64 >+/* 17948 */ MCD_OPC_FilterValue, 3, 189, 88, // Skip to: 40669 >+/* 17952 */ MCD_OPC_CheckPredicate, 0, 185, 88, // Skip to: 40669 >+/* 17956 */ MCD_OPC_CheckField, 21, 1, 1, 179, 88, // Skip to: 40669 >+/* 17962 */ MCD_OPC_Decode, 155, 16, 112, // Opcode: UADDWv4i32_v2i64 >+/* 17966 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 18045 >+/* 17970 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 17973 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17991 >+/* 17977 */ MCD_OPC_CheckPredicate, 0, 160, 88, // Skip to: 40669 >+/* 17981 */ MCD_OPC_CheckField, 21, 1, 1, 154, 88, // Skip to: 40669 >+/* 17987 */ MCD_OPC_Decode, 222, 12, 89, // Opcode: SRHADDv2i32 >+/* 17991 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18009 >+/* 17995 */ MCD_OPC_CheckPredicate, 0, 142, 88, // Skip to: 40669 >+/* 17999 */ MCD_OPC_CheckField, 21, 1, 1, 136, 88, // Skip to: 40669 >+/* 18005 */ MCD_OPC_Decode, 222, 17, 89, // Opcode: URHADDv2i32 >+/* 18009 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18027 >+/* 18013 */ MCD_OPC_CheckPredicate, 0, 124, 88, // Skip to: 40669 >+/* 18017 */ MCD_OPC_CheckField, 21, 1, 1, 118, 88, // Skip to: 40669 >+/* 18023 */ MCD_OPC_Decode, 224, 12, 112, // Opcode: SRHADDv4i32 >+/* 18027 */ MCD_OPC_FilterValue, 3, 110, 88, // Skip to: 40669 >+/* 18031 */ MCD_OPC_CheckPredicate, 0, 106, 88, // Skip to: 40669 >+/* 18035 */ MCD_OPC_CheckField, 21, 1, 1, 100, 88, // Skip to: 40669 >+/* 18041 */ MCD_OPC_Decode, 224, 17, 112, // Opcode: URHADDv4i32 >+/* 18045 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 18088 >+/* 18049 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18052 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18070 >+/* 18056 */ MCD_OPC_CheckPredicate, 0, 81, 88, // Skip to: 40669 >+/* 18060 */ MCD_OPC_CheckField, 21, 1, 0, 75, 88, // Skip to: 40669 >+/* 18066 */ MCD_OPC_Decode, 179, 18, 89, // Opcode: UZP1v2i32 >+/* 18070 */ MCD_OPC_FilterValue, 2, 67, 88, // Skip to: 40669 >+/* 18074 */ MCD_OPC_CheckPredicate, 0, 63, 88, // Skip to: 40669 >+/* 18078 */ MCD_OPC_CheckField, 21, 1, 0, 57, 88, // Skip to: 40669 >+/* 18084 */ MCD_OPC_Decode, 182, 18, 112, // Opcode: UZP1v4i32 >+/* 18088 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 18165 >+/* 18092 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18095 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18113 >+/* 18099 */ MCD_OPC_CheckPredicate, 0, 38, 88, // Skip to: 40669 >+/* 18103 */ MCD_OPC_CheckField, 21, 1, 1, 32, 88, // Skip to: 40669 >+/* 18109 */ MCD_OPC_Decode, 144, 9, 89, // Opcode: ORRv8i8 >+/* 18113 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 18130 >+/* 18117 */ MCD_OPC_CheckPredicate, 0, 20, 88, // Skip to: 40669 >+/* 18121 */ MCD_OPC_CheckField, 21, 1, 1, 14, 88, // Skip to: 40669 >+/* 18127 */ MCD_OPC_Decode, 121, 109, // Opcode: BITv8i8 >+/* 18130 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18148 >+/* 18134 */ MCD_OPC_CheckPredicate, 0, 3, 88, // Skip to: 40669 >+/* 18138 */ MCD_OPC_CheckField, 21, 1, 1, 253, 87, // Skip to: 40669 >+/* 18144 */ MCD_OPC_Decode, 139, 9, 112, // Opcode: ORRv16i8 >+/* 18148 */ MCD_OPC_FilterValue, 3, 245, 87, // Skip to: 40669 >+/* 18152 */ MCD_OPC_CheckPredicate, 0, 241, 87, // Skip to: 40669 >+/* 18156 */ MCD_OPC_CheckField, 21, 1, 1, 235, 87, // Skip to: 40669 >+/* 18162 */ MCD_OPC_Decode, 120, 120, // Opcode: BITv16i8 >+/* 18165 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 18244 >+/* 18169 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18172 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18190 >+/* 18176 */ MCD_OPC_CheckPredicate, 0, 217, 87, // Skip to: 40669 >+/* 18180 */ MCD_OPC_CheckField, 21, 1, 1, 211, 87, // Skip to: 40669 >+/* 18186 */ MCD_OPC_Decode, 162, 13, 85, // Opcode: SSUBLv2i32_v2i64 >+/* 18190 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18208 >+/* 18194 */ MCD_OPC_CheckPredicate, 0, 199, 87, // Skip to: 40669 >+/* 18198 */ MCD_OPC_CheckField, 21, 1, 1, 193, 87, // Skip to: 40669 >+/* 18204 */ MCD_OPC_Decode, 167, 18, 85, // Opcode: USUBLv2i32_v2i64 >+/* 18208 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18226 >+/* 18212 */ MCD_OPC_CheckPredicate, 0, 181, 87, // Skip to: 40669 >+/* 18216 */ MCD_OPC_CheckField, 21, 1, 1, 175, 87, // Skip to: 40669 >+/* 18222 */ MCD_OPC_Decode, 164, 13, 112, // Opcode: SSUBLv4i32_v2i64 >+/* 18226 */ MCD_OPC_FilterValue, 3, 167, 87, // Skip to: 40669 >+/* 18230 */ MCD_OPC_CheckPredicate, 0, 163, 87, // Skip to: 40669 >+/* 18234 */ MCD_OPC_CheckField, 21, 1, 1, 157, 87, // Skip to: 40669 >+/* 18240 */ MCD_OPC_Decode, 169, 18, 112, // Opcode: USUBLv4i32_v2i64 >+/* 18244 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 18323 >+/* 18248 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18251 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18269 >+/* 18255 */ MCD_OPC_CheckPredicate, 0, 138, 87, // Skip to: 40669 >+/* 18259 */ MCD_OPC_CheckField, 21, 1, 1, 132, 87, // Skip to: 40669 >+/* 18265 */ MCD_OPC_Decode, 189, 10, 89, // Opcode: SHSUBv2i32 >+/* 18269 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18287 >+/* 18273 */ MCD_OPC_CheckPredicate, 0, 120, 87, // Skip to: 40669 >+/* 18277 */ MCD_OPC_CheckField, 21, 1, 1, 114, 87, // Skip to: 40669 >+/* 18283 */ MCD_OPC_Decode, 189, 16, 89, // Opcode: UHSUBv2i32 >+/* 18287 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18305 >+/* 18291 */ MCD_OPC_CheckPredicate, 0, 102, 87, // Skip to: 40669 >+/* 18295 */ MCD_OPC_CheckField, 21, 1, 1, 96, 87, // Skip to: 40669 >+/* 18301 */ MCD_OPC_Decode, 191, 10, 112, // Opcode: SHSUBv4i32 >+/* 18305 */ MCD_OPC_FilterValue, 3, 88, 87, // Skip to: 40669 >+/* 18309 */ MCD_OPC_CheckPredicate, 0, 84, 87, // Skip to: 40669 >+/* 18313 */ MCD_OPC_CheckField, 21, 1, 1, 78, 87, // Skip to: 40669 >+/* 18319 */ MCD_OPC_Decode, 191, 16, 112, // Opcode: UHSUBv4i32 >+/* 18323 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 18492 >+/* 18327 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18330 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 18380 >+/* 18334 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 18337 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18349 >+/* 18341 */ MCD_OPC_CheckPredicate, 0, 52, 87, // Skip to: 40669 >+/* 18345 */ MCD_OPC_Decode, 220, 15, 89, // Opcode: TRN1v2i32 >+/* 18349 */ MCD_OPC_FilterValue, 1, 44, 87, // Skip to: 40669 >+/* 18353 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 18356 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18368 >+/* 18360 */ MCD_OPC_CheckPredicate, 0, 33, 87, // Skip to: 40669 >+/* 18364 */ MCD_OPC_Decode, 230, 9, 90, // Opcode: SADDLPv2i32_v1i64 >+/* 18368 */ MCD_OPC_FilterValue, 1, 25, 87, // Skip to: 40669 >+/* 18372 */ MCD_OPC_CheckPredicate, 0, 21, 87, // Skip to: 40669 >+/* 18376 */ MCD_OPC_Decode, 193, 18, 95, // Opcode: XTNv2i32 >+/* 18380 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18411 >+/* 18384 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 18387 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18399 >+/* 18391 */ MCD_OPC_CheckPredicate, 0, 2, 87, // Skip to: 40669 >+/* 18395 */ MCD_OPC_Decode, 136, 16, 90, // Opcode: UADDLPv2i32_v1i64 >+/* 18399 */ MCD_OPC_FilterValue, 33, 250, 86, // Skip to: 40669 >+/* 18403 */ MCD_OPC_CheckPredicate, 0, 246, 86, // Skip to: 40669 >+/* 18407 */ MCD_OPC_Decode, 216, 12, 95, // Opcode: SQXTUNv2i32 >+/* 18411 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18461 >+/* 18415 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 18418 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18430 >+/* 18422 */ MCD_OPC_CheckPredicate, 0, 227, 86, // Skip to: 40669 >+/* 18426 */ MCD_OPC_Decode, 223, 15, 112, // Opcode: TRN1v4i32 >+/* 18430 */ MCD_OPC_FilterValue, 1, 219, 86, // Skip to: 40669 >+/* 18434 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 18437 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18449 >+/* 18441 */ MCD_OPC_CheckPredicate, 0, 208, 86, // Skip to: 40669 >+/* 18445 */ MCD_OPC_Decode, 232, 9, 117, // Opcode: SADDLPv4i32_v2i64 >+/* 18449 */ MCD_OPC_FilterValue, 1, 200, 86, // Skip to: 40669 >+/* 18453 */ MCD_OPC_CheckPredicate, 0, 196, 86, // Skip to: 40669 >+/* 18457 */ MCD_OPC_Decode, 195, 18, 126, // Opcode: XTNv4i32 >+/* 18461 */ MCD_OPC_FilterValue, 3, 188, 86, // Skip to: 40669 >+/* 18465 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 18468 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18480 >+/* 18472 */ MCD_OPC_CheckPredicate, 0, 177, 86, // Skip to: 40669 >+/* 18476 */ MCD_OPC_Decode, 138, 16, 117, // Opcode: UADDLPv4i32_v2i64 >+/* 18480 */ MCD_OPC_FilterValue, 33, 169, 86, // Skip to: 40669 >+/* 18484 */ MCD_OPC_CheckPredicate, 0, 165, 86, // Skip to: 40669 >+/* 18488 */ MCD_OPC_Decode, 218, 12, 126, // Opcode: SQXTUNv4i32 >+/* 18492 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 18571 >+/* 18496 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18499 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18517 >+/* 18503 */ MCD_OPC_CheckPredicate, 0, 146, 86, // Skip to: 40669 >+/* 18507 */ MCD_OPC_CheckField, 21, 1, 1, 140, 86, // Skip to: 40669 >+/* 18513 */ MCD_OPC_Decode, 197, 12, 89, // Opcode: SQSUBv2i32 >+/* 18517 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18535 >+/* 18521 */ MCD_OPC_CheckPredicate, 0, 128, 86, // Skip to: 40669 >+/* 18525 */ MCD_OPC_CheckField, 21, 1, 1, 122, 86, // Skip to: 40669 >+/* 18531 */ MCD_OPC_Decode, 204, 17, 89, // Opcode: UQSUBv2i32 >+/* 18535 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18553 >+/* 18539 */ MCD_OPC_CheckPredicate, 0, 110, 86, // Skip to: 40669 >+/* 18543 */ MCD_OPC_CheckField, 21, 1, 1, 104, 86, // Skip to: 40669 >+/* 18549 */ MCD_OPC_Decode, 200, 12, 112, // Opcode: SQSUBv4i32 >+/* 18553 */ MCD_OPC_FilterValue, 3, 96, 86, // Skip to: 40669 >+/* 18557 */ MCD_OPC_CheckPredicate, 0, 92, 86, // Skip to: 40669 >+/* 18561 */ MCD_OPC_CheckField, 21, 1, 1, 86, 86, // Skip to: 40669 >+/* 18567 */ MCD_OPC_Decode, 207, 17, 112, // Opcode: UQSUBv4i32 >+/* 18571 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 18650 >+/* 18575 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18578 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18596 >+/* 18582 */ MCD_OPC_CheckPredicate, 0, 67, 86, // Skip to: 40669 >+/* 18586 */ MCD_OPC_CheckField, 21, 1, 1, 61, 86, // Skip to: 40669 >+/* 18592 */ MCD_OPC_Decode, 168, 13, 93, // Opcode: SSUBWv2i32_v2i64 >+/* 18596 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18614 >+/* 18600 */ MCD_OPC_CheckPredicate, 0, 49, 86, // Skip to: 40669 >+/* 18604 */ MCD_OPC_CheckField, 21, 1, 1, 43, 86, // Skip to: 40669 >+/* 18610 */ MCD_OPC_Decode, 173, 18, 93, // Opcode: USUBWv2i32_v2i64 >+/* 18614 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18632 >+/* 18618 */ MCD_OPC_CheckPredicate, 0, 31, 86, // Skip to: 40669 >+/* 18622 */ MCD_OPC_CheckField, 21, 1, 1, 25, 86, // Skip to: 40669 >+/* 18628 */ MCD_OPC_Decode, 170, 13, 112, // Opcode: SSUBWv4i32_v2i64 >+/* 18632 */ MCD_OPC_FilterValue, 3, 17, 86, // Skip to: 40669 >+/* 18636 */ MCD_OPC_CheckPredicate, 0, 13, 86, // Skip to: 40669 >+/* 18640 */ MCD_OPC_CheckField, 21, 1, 1, 7, 86, // Skip to: 40669 >+/* 18646 */ MCD_OPC_Decode, 175, 18, 112, // Opcode: USUBWv4i32_v2i64 >+/* 18650 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 18729 >+/* 18654 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18657 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18675 >+/* 18661 */ MCD_OPC_CheckPredicate, 0, 244, 85, // Skip to: 40669 >+/* 18665 */ MCD_OPC_CheckField, 21, 1, 1, 238, 85, // Skip to: 40669 >+/* 18671 */ MCD_OPC_Decode, 194, 1, 89, // Opcode: CMGTv2i32 >+/* 18675 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18693 >+/* 18679 */ MCD_OPC_CheckPredicate, 0, 226, 85, // Skip to: 40669 >+/* 18683 */ MCD_OPC_CheckField, 21, 1, 1, 220, 85, // Skip to: 40669 >+/* 18689 */ MCD_OPC_Decode, 208, 1, 89, // Opcode: CMHIv2i32 >+/* 18693 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18711 >+/* 18697 */ MCD_OPC_CheckPredicate, 0, 208, 85, // Skip to: 40669 >+/* 18701 */ MCD_OPC_CheckField, 21, 1, 1, 202, 85, // Skip to: 40669 >+/* 18707 */ MCD_OPC_Decode, 200, 1, 112, // Opcode: CMGTv4i32 >+/* 18711 */ MCD_OPC_FilterValue, 3, 194, 85, // Skip to: 40669 >+/* 18715 */ MCD_OPC_CheckPredicate, 0, 190, 85, // Skip to: 40669 >+/* 18719 */ MCD_OPC_CheckField, 21, 1, 1, 184, 85, // Skip to: 40669 >+/* 18725 */ MCD_OPC_Decode, 211, 1, 112, // Opcode: CMHIv4i32 >+/* 18729 */ MCD_OPC_FilterValue, 14, 164, 0, // Skip to: 18897 >+/* 18733 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18736 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 18773 >+/* 18740 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 18743 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18755 >+/* 18747 */ MCD_OPC_CheckPredicate, 0, 158, 85, // Skip to: 40669 >+/* 18751 */ MCD_OPC_Decode, 199, 18, 89, // Opcode: ZIP1v2i32 >+/* 18755 */ MCD_OPC_FilterValue, 1, 150, 85, // Skip to: 40669 >+/* 18759 */ MCD_OPC_CheckPredicate, 0, 146, 85, // Skip to: 40669 >+/* 18763 */ MCD_OPC_CheckField, 16, 5, 0, 140, 85, // Skip to: 40669 >+/* 18769 */ MCD_OPC_Decode, 186, 15, 99, // Opcode: SUQADDv2i32 >+/* 18773 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18804 >+/* 18777 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 18780 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18792 >+/* 18784 */ MCD_OPC_CheckPredicate, 0, 121, 85, // Skip to: 40669 >+/* 18788 */ MCD_OPC_Decode, 152, 18, 99, // Opcode: USQADDv2i32 >+/* 18792 */ MCD_OPC_FilterValue, 33, 113, 85, // Skip to: 40669 >+/* 18796 */ MCD_OPC_CheckPredicate, 0, 109, 85, // Skip to: 40669 >+/* 18800 */ MCD_OPC_Decode, 169, 10, 108, // Opcode: SHLLv2i32 >+/* 18804 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18854 >+/* 18808 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 18811 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18823 >+/* 18815 */ MCD_OPC_CheckPredicate, 0, 90, 85, // Skip to: 40669 >+/* 18819 */ MCD_OPC_Decode, 202, 18, 112, // Opcode: ZIP1v4i32 >+/* 18823 */ MCD_OPC_FilterValue, 1, 82, 85, // Skip to: 40669 >+/* 18827 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 18830 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18842 >+/* 18834 */ MCD_OPC_CheckPredicate, 0, 71, 85, // Skip to: 40669 >+/* 18838 */ MCD_OPC_Decode, 189, 15, 126, // Opcode: SUQADDv4i32 >+/* 18842 */ MCD_OPC_FilterValue, 16, 63, 85, // Skip to: 40669 >+/* 18846 */ MCD_OPC_CheckPredicate, 0, 59, 85, // Skip to: 40669 >+/* 18850 */ MCD_OPC_Decode, 237, 9, 95, // Opcode: SADDLVv4i32v >+/* 18854 */ MCD_OPC_FilterValue, 3, 51, 85, // Skip to: 40669 >+/* 18858 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 18861 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18873 >+/* 18865 */ MCD_OPC_CheckPredicate, 0, 40, 85, // Skip to: 40669 >+/* 18869 */ MCD_OPC_Decode, 155, 18, 126, // Opcode: USQADDv4i32 >+/* 18873 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 18885 >+/* 18877 */ MCD_OPC_CheckPredicate, 0, 28, 85, // Skip to: 40669 >+/* 18881 */ MCD_OPC_Decode, 171, 10, 117, // Opcode: SHLLv4i32 >+/* 18885 */ MCD_OPC_FilterValue, 48, 20, 85, // Skip to: 40669 >+/* 18889 */ MCD_OPC_CheckPredicate, 0, 16, 85, // Skip to: 40669 >+/* 18893 */ MCD_OPC_Decode, 143, 16, 95, // Opcode: UADDLVv4i32v >+/* 18897 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 18976 >+/* 18901 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18904 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18922 >+/* 18908 */ MCD_OPC_CheckPredicate, 0, 253, 84, // Skip to: 40669 >+/* 18912 */ MCD_OPC_CheckField, 21, 1, 1, 247, 84, // Skip to: 40669 >+/* 18918 */ MCD_OPC_Decode, 178, 1, 89, // Opcode: CMGEv2i32 >+/* 18922 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18940 >+/* 18926 */ MCD_OPC_CheckPredicate, 0, 235, 84, // Skip to: 40669 >+/* 18930 */ MCD_OPC_CheckField, 21, 1, 1, 229, 84, // Skip to: 40669 >+/* 18936 */ MCD_OPC_Decode, 216, 1, 89, // Opcode: CMHSv2i32 >+/* 18940 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18958 >+/* 18944 */ MCD_OPC_CheckPredicate, 0, 217, 84, // Skip to: 40669 >+/* 18948 */ MCD_OPC_CheckField, 21, 1, 1, 211, 84, // Skip to: 40669 >+/* 18954 */ MCD_OPC_Decode, 184, 1, 112, // Opcode: CMGEv4i32 >+/* 18958 */ MCD_OPC_FilterValue, 3, 203, 84, // Skip to: 40669 >+/* 18962 */ MCD_OPC_CheckPredicate, 0, 199, 84, // Skip to: 40669 >+/* 18966 */ MCD_OPC_CheckField, 21, 1, 1, 193, 84, // Skip to: 40669 >+/* 18972 */ MCD_OPC_Decode, 219, 1, 112, // Opcode: CMHSv4i32 >+/* 18976 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 19053 >+/* 18980 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 18983 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 19000 >+/* 18987 */ MCD_OPC_CheckPredicate, 0, 174, 84, // Skip to: 40669 >+/* 18991 */ MCD_OPC_CheckField, 21, 1, 1, 168, 84, // Skip to: 40669 >+/* 18997 */ MCD_OPC_Decode, 32, 103, // Opcode: ADDHNv2i64_v2i32 >+/* 19000 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19018 >+/* 19004 */ MCD_OPC_CheckPredicate, 0, 157, 84, // Skip to: 40669 >+/* 19008 */ MCD_OPC_CheckField, 21, 1, 1, 151, 84, // Skip to: 40669 >+/* 19014 */ MCD_OPC_Decode, 156, 9, 103, // Opcode: RADDHNv2i64_v2i32 >+/* 19018 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 19035 >+/* 19022 */ MCD_OPC_CheckPredicate, 0, 139, 84, // Skip to: 40669 >+/* 19026 */ MCD_OPC_CheckField, 21, 1, 1, 133, 84, // Skip to: 40669 >+/* 19032 */ MCD_OPC_Decode, 33, 120, // Opcode: ADDHNv2i64_v4i32 >+/* 19035 */ MCD_OPC_FilterValue, 3, 126, 84, // Skip to: 40669 >+/* 19039 */ MCD_OPC_CheckPredicate, 0, 122, 84, // Skip to: 40669 >+/* 19043 */ MCD_OPC_CheckField, 21, 1, 1, 116, 84, // Skip to: 40669 >+/* 19049 */ MCD_OPC_Decode, 157, 9, 120, // Opcode: RADDHNv2i64_v4i32 >+/* 19053 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 19132 >+/* 19057 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19060 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19078 >+/* 19064 */ MCD_OPC_CheckPredicate, 0, 97, 84, // Skip to: 40669 >+/* 19068 */ MCD_OPC_CheckField, 21, 1, 1, 91, 84, // Skip to: 40669 >+/* 19074 */ MCD_OPC_Decode, 139, 13, 89, // Opcode: SSHLv2i32 >+/* 19078 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19096 >+/* 19082 */ MCD_OPC_CheckPredicate, 0, 79, 84, // Skip to: 40669 >+/* 19086 */ MCD_OPC_CheckField, 21, 1, 1, 73, 84, // Skip to: 40669 >+/* 19092 */ MCD_OPC_Decode, 133, 18, 89, // Opcode: USHLv2i32 >+/* 19096 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19114 >+/* 19100 */ MCD_OPC_CheckPredicate, 0, 61, 84, // Skip to: 40669 >+/* 19104 */ MCD_OPC_CheckField, 21, 1, 1, 55, 84, // Skip to: 40669 >+/* 19110 */ MCD_OPC_Decode, 142, 13, 112, // Opcode: SSHLv4i32 >+/* 19114 */ MCD_OPC_FilterValue, 3, 47, 84, // Skip to: 40669 >+/* 19118 */ MCD_OPC_CheckPredicate, 0, 43, 84, // Skip to: 40669 >+/* 19122 */ MCD_OPC_CheckField, 21, 1, 1, 37, 84, // Skip to: 40669 >+/* 19128 */ MCD_OPC_Decode, 136, 18, 112, // Opcode: USHLv4i32 >+/* 19132 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 19263 >+/* 19136 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19139 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 19170 >+/* 19143 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 19146 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19158 >+/* 19150 */ MCD_OPC_CheckPredicate, 0, 11, 84, // Skip to: 40669 >+/* 19154 */ MCD_OPC_Decode, 145, 1, 90, // Opcode: CLSv2i32 >+/* 19158 */ MCD_OPC_FilterValue, 33, 3, 84, // Skip to: 40669 >+/* 19162 */ MCD_OPC_CheckPredicate, 0, 255, 83, // Skip to: 40669 >+/* 19166 */ MCD_OPC_Decode, 207, 12, 95, // Opcode: SQXTNv2i32 >+/* 19170 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 19201 >+/* 19174 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 19177 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19189 >+/* 19181 */ MCD_OPC_CheckPredicate, 0, 236, 83, // Skip to: 40669 >+/* 19185 */ MCD_OPC_Decode, 153, 1, 90, // Opcode: CLZv2i32 >+/* 19189 */ MCD_OPC_FilterValue, 33, 228, 83, // Skip to: 40669 >+/* 19193 */ MCD_OPC_CheckPredicate, 0, 224, 83, // Skip to: 40669 >+/* 19197 */ MCD_OPC_Decode, 214, 17, 95, // Opcode: UQXTNv2i32 >+/* 19201 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 19232 >+/* 19205 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 19208 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19220 >+/* 19212 */ MCD_OPC_CheckPredicate, 0, 205, 83, // Skip to: 40669 >+/* 19216 */ MCD_OPC_Decode, 147, 1, 117, // Opcode: CLSv4i32 >+/* 19220 */ MCD_OPC_FilterValue, 33, 197, 83, // Skip to: 40669 >+/* 19224 */ MCD_OPC_CheckPredicate, 0, 193, 83, // Skip to: 40669 >+/* 19228 */ MCD_OPC_Decode, 209, 12, 126, // Opcode: SQXTNv4i32 >+/* 19232 */ MCD_OPC_FilterValue, 3, 185, 83, // Skip to: 40669 >+/* 19236 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 19239 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19251 >+/* 19243 */ MCD_OPC_CheckPredicate, 0, 174, 83, // Skip to: 40669 >+/* 19247 */ MCD_OPC_Decode, 155, 1, 117, // Opcode: CLZv4i32 >+/* 19251 */ MCD_OPC_FilterValue, 33, 166, 83, // Skip to: 40669 >+/* 19255 */ MCD_OPC_CheckPredicate, 0, 162, 83, // Skip to: 40669 >+/* 19259 */ MCD_OPC_Decode, 216, 17, 126, // Opcode: UQXTNv4i32 >+/* 19263 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 19342 >+/* 19267 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19270 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19288 >+/* 19274 */ MCD_OPC_CheckPredicate, 0, 143, 83, // Skip to: 40669 >+/* 19278 */ MCD_OPC_CheckField, 21, 1, 1, 137, 83, // Skip to: 40669 >+/* 19284 */ MCD_OPC_Decode, 162, 12, 89, // Opcode: SQSHLv2i32 >+/* 19288 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19306 >+/* 19292 */ MCD_OPC_CheckPredicate, 0, 125, 83, // Skip to: 40669 >+/* 19296 */ MCD_OPC_CheckField, 21, 1, 1, 119, 83, // Skip to: 40669 >+/* 19302 */ MCD_OPC_Decode, 178, 17, 89, // Opcode: UQSHLv2i32 >+/* 19306 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19324 >+/* 19310 */ MCD_OPC_CheckPredicate, 0, 107, 83, // Skip to: 40669 >+/* 19314 */ MCD_OPC_CheckField, 21, 1, 1, 101, 83, // Skip to: 40669 >+/* 19320 */ MCD_OPC_Decode, 168, 12, 112, // Opcode: SQSHLv4i32 >+/* 19324 */ MCD_OPC_FilterValue, 3, 93, 83, // Skip to: 40669 >+/* 19328 */ MCD_OPC_CheckPredicate, 0, 89, 83, // Skip to: 40669 >+/* 19332 */ MCD_OPC_CheckField, 21, 1, 1, 83, 83, // Skip to: 40669 >+/* 19338 */ MCD_OPC_Decode, 184, 17, 112, // Opcode: UQSHLv4i32 >+/* 19342 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 19421 >+/* 19346 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19349 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19367 >+/* 19353 */ MCD_OPC_CheckPredicate, 0, 64, 83, // Skip to: 40669 >+/* 19357 */ MCD_OPC_CheckField, 21, 1, 1, 58, 83, // Skip to: 40669 >+/* 19363 */ MCD_OPC_Decode, 200, 9, 105, // Opcode: SABALv2i32_v2i64 >+/* 19367 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19385 >+/* 19371 */ MCD_OPC_CheckPredicate, 0, 46, 83, // Skip to: 40669 >+/* 19375 */ MCD_OPC_CheckField, 21, 1, 1, 40, 83, // Skip to: 40669 >+/* 19381 */ MCD_OPC_Decode, 234, 15, 105, // Opcode: UABALv2i32_v2i64 >+/* 19385 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19403 >+/* 19389 */ MCD_OPC_CheckPredicate, 0, 28, 83, // Skip to: 40669 >+/* 19393 */ MCD_OPC_CheckField, 21, 1, 1, 22, 83, // Skip to: 40669 >+/* 19399 */ MCD_OPC_Decode, 202, 9, 120, // Opcode: SABALv4i32_v2i64 >+/* 19403 */ MCD_OPC_FilterValue, 3, 14, 83, // Skip to: 40669 >+/* 19407 */ MCD_OPC_CheckPredicate, 0, 10, 83, // Skip to: 40669 >+/* 19411 */ MCD_OPC_CheckField, 21, 1, 1, 4, 83, // Skip to: 40669 >+/* 19417 */ MCD_OPC_Decode, 236, 15, 120, // Opcode: UABALv4i32_v2i64 >+/* 19421 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 19500 >+/* 19425 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19428 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19446 >+/* 19432 */ MCD_OPC_CheckPredicate, 0, 241, 82, // Skip to: 40669 >+/* 19436 */ MCD_OPC_CheckField, 21, 1, 1, 235, 82, // Skip to: 40669 >+/* 19442 */ MCD_OPC_Decode, 237, 12, 89, // Opcode: SRSHLv2i32 >+/* 19446 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19464 >+/* 19450 */ MCD_OPC_CheckPredicate, 0, 223, 82, // Skip to: 40669 >+/* 19454 */ MCD_OPC_CheckField, 21, 1, 1, 217, 82, // Skip to: 40669 >+/* 19460 */ MCD_OPC_Decode, 229, 17, 89, // Opcode: URSHLv2i32 >+/* 19464 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19482 >+/* 19468 */ MCD_OPC_CheckPredicate, 0, 205, 82, // Skip to: 40669 >+/* 19472 */ MCD_OPC_CheckField, 21, 1, 1, 199, 82, // Skip to: 40669 >+/* 19478 */ MCD_OPC_Decode, 240, 12, 112, // Opcode: SRSHLv4i32 >+/* 19482 */ MCD_OPC_FilterValue, 3, 191, 82, // Skip to: 40669 >+/* 19486 */ MCD_OPC_CheckPredicate, 0, 187, 82, // Skip to: 40669 >+/* 19490 */ MCD_OPC_CheckField, 21, 1, 1, 181, 82, // Skip to: 40669 >+/* 19496 */ MCD_OPC_Decode, 232, 17, 112, // Opcode: URSHLv4i32 >+/* 19500 */ MCD_OPC_FilterValue, 22, 39, 0, // Skip to: 19543 >+/* 19504 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19507 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19525 >+/* 19511 */ MCD_OPC_CheckPredicate, 0, 162, 82, // Skip to: 40669 >+/* 19515 */ MCD_OPC_CheckField, 21, 1, 0, 156, 82, // Skip to: 40669 >+/* 19521 */ MCD_OPC_Decode, 186, 18, 89, // Opcode: UZP2v2i32 >+/* 19525 */ MCD_OPC_FilterValue, 2, 148, 82, // Skip to: 40669 >+/* 19529 */ MCD_OPC_CheckPredicate, 0, 144, 82, // Skip to: 40669 >+/* 19533 */ MCD_OPC_CheckField, 21, 1, 0, 138, 82, // Skip to: 40669 >+/* 19539 */ MCD_OPC_Decode, 189, 18, 112, // Opcode: UZP2v4i32 >+/* 19543 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 19622 >+/* 19547 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19550 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19568 >+/* 19554 */ MCD_OPC_CheckPredicate, 0, 119, 82, // Skip to: 40669 >+/* 19558 */ MCD_OPC_CheckField, 21, 1, 1, 113, 82, // Skip to: 40669 >+/* 19564 */ MCD_OPC_Decode, 245, 11, 89, // Opcode: SQRSHLv2i32 >+/* 19568 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19586 >+/* 19572 */ MCD_OPC_CheckPredicate, 0, 101, 82, // Skip to: 40669 >+/* 19576 */ MCD_OPC_CheckField, 21, 1, 1, 95, 82, // Skip to: 40669 >+/* 19582 */ MCD_OPC_Decode, 153, 17, 89, // Opcode: UQRSHLv2i32 >+/* 19586 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19604 >+/* 19590 */ MCD_OPC_CheckPredicate, 0, 83, 82, // Skip to: 40669 >+/* 19594 */ MCD_OPC_CheckField, 21, 1, 1, 77, 82, // Skip to: 40669 >+/* 19600 */ MCD_OPC_Decode, 248, 11, 112, // Opcode: SQRSHLv4i32 >+/* 19604 */ MCD_OPC_FilterValue, 3, 69, 82, // Skip to: 40669 >+/* 19608 */ MCD_OPC_CheckPredicate, 0, 65, 82, // Skip to: 40669 >+/* 19612 */ MCD_OPC_CheckField, 21, 1, 1, 59, 82, // Skip to: 40669 >+/* 19618 */ MCD_OPC_Decode, 156, 17, 112, // Opcode: UQRSHLv4i32 >+/* 19622 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 19701 >+/* 19626 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19629 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19647 >+/* 19633 */ MCD_OPC_CheckPredicate, 0, 40, 82, // Skip to: 40669 >+/* 19637 */ MCD_OPC_CheckField, 21, 1, 1, 34, 82, // Skip to: 40669 >+/* 19643 */ MCD_OPC_Decode, 149, 15, 103, // Opcode: SUBHNv2i64_v2i32 >+/* 19647 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19665 >+/* 19651 */ MCD_OPC_CheckPredicate, 0, 22, 82, // Skip to: 40669 >+/* 19655 */ MCD_OPC_CheckField, 21, 1, 1, 16, 82, // Skip to: 40669 >+/* 19661 */ MCD_OPC_Decode, 193, 9, 103, // Opcode: RSUBHNv2i64_v2i32 >+/* 19665 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19683 >+/* 19669 */ MCD_OPC_CheckPredicate, 0, 4, 82, // Skip to: 40669 >+/* 19673 */ MCD_OPC_CheckField, 21, 1, 1, 254, 81, // Skip to: 40669 >+/* 19679 */ MCD_OPC_Decode, 150, 15, 120, // Opcode: SUBHNv2i64_v4i32 >+/* 19683 */ MCD_OPC_FilterValue, 3, 246, 81, // Skip to: 40669 >+/* 19687 */ MCD_OPC_CheckPredicate, 0, 242, 81, // Skip to: 40669 >+/* 19691 */ MCD_OPC_CheckField, 21, 1, 1, 236, 81, // Skip to: 40669 >+/* 19697 */ MCD_OPC_Decode, 194, 9, 120, // Opcode: RSUBHNv2i64_v4i32 >+/* 19701 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 19780 >+/* 19705 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19708 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19726 >+/* 19712 */ MCD_OPC_CheckPredicate, 0, 217, 81, // Skip to: 40669 >+/* 19716 */ MCD_OPC_CheckField, 21, 1, 1, 211, 81, // Skip to: 40669 >+/* 19722 */ MCD_OPC_Decode, 215, 10, 89, // Opcode: SMAXv2i32 >+/* 19726 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19744 >+/* 19730 */ MCD_OPC_CheckPredicate, 0, 199, 81, // Skip to: 40669 >+/* 19734 */ MCD_OPC_CheckField, 21, 1, 1, 193, 81, // Skip to: 40669 >+/* 19740 */ MCD_OPC_Decode, 207, 16, 89, // Opcode: UMAXv2i32 >+/* 19744 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19762 >+/* 19748 */ MCD_OPC_CheckPredicate, 0, 181, 81, // Skip to: 40669 >+/* 19752 */ MCD_OPC_CheckField, 21, 1, 1, 175, 81, // Skip to: 40669 >+/* 19758 */ MCD_OPC_Decode, 217, 10, 112, // Opcode: SMAXv4i32 >+/* 19762 */ MCD_OPC_FilterValue, 3, 167, 81, // Skip to: 40669 >+/* 19766 */ MCD_OPC_CheckPredicate, 0, 163, 81, // Skip to: 40669 >+/* 19770 */ MCD_OPC_CheckField, 21, 1, 1, 157, 81, // Skip to: 40669 >+/* 19776 */ MCD_OPC_Decode, 209, 16, 112, // Opcode: UMAXv4i32 >+/* 19780 */ MCD_OPC_FilterValue, 26, 113, 0, // Skip to: 19897 >+/* 19784 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19787 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 19824 >+/* 19791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 19794 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19806 >+/* 19798 */ MCD_OPC_CheckPredicate, 0, 131, 81, // Skip to: 40669 >+/* 19802 */ MCD_OPC_Decode, 227, 15, 89, // Opcode: TRN2v2i32 >+/* 19806 */ MCD_OPC_FilterValue, 1, 123, 81, // Skip to: 40669 >+/* 19810 */ MCD_OPC_CheckPredicate, 0, 119, 81, // Skip to: 40669 >+/* 19814 */ MCD_OPC_CheckField, 16, 5, 0, 113, 81, // Skip to: 40669 >+/* 19820 */ MCD_OPC_Decode, 224, 9, 99, // Opcode: SADALPv2i32_v1i64 >+/* 19824 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19842 >+/* 19828 */ MCD_OPC_CheckPredicate, 0, 101, 81, // Skip to: 40669 >+/* 19832 */ MCD_OPC_CheckField, 16, 6, 32, 95, 81, // Skip to: 40669 >+/* 19838 */ MCD_OPC_Decode, 130, 16, 99, // Opcode: UADALPv2i32_v1i64 >+/* 19842 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 19879 >+/* 19846 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 19849 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19861 >+/* 19853 */ MCD_OPC_CheckPredicate, 0, 76, 81, // Skip to: 40669 >+/* 19857 */ MCD_OPC_Decode, 230, 15, 112, // Opcode: TRN2v4i32 >+/* 19861 */ MCD_OPC_FilterValue, 1, 68, 81, // Skip to: 40669 >+/* 19865 */ MCD_OPC_CheckPredicate, 0, 64, 81, // Skip to: 40669 >+/* 19869 */ MCD_OPC_CheckField, 16, 5, 0, 58, 81, // Skip to: 40669 >+/* 19875 */ MCD_OPC_Decode, 226, 9, 126, // Opcode: SADALPv4i32_v2i64 >+/* 19879 */ MCD_OPC_FilterValue, 3, 50, 81, // Skip to: 40669 >+/* 19883 */ MCD_OPC_CheckPredicate, 0, 46, 81, // Skip to: 40669 >+/* 19887 */ MCD_OPC_CheckField, 16, 6, 32, 40, 81, // Skip to: 40669 >+/* 19893 */ MCD_OPC_Decode, 132, 16, 126, // Opcode: UADALPv4i32_v2i64 >+/* 19897 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 19976 >+/* 19901 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19904 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19922 >+/* 19908 */ MCD_OPC_CheckPredicate, 0, 21, 81, // Skip to: 40669 >+/* 19912 */ MCD_OPC_CheckField, 21, 1, 1, 15, 81, // Skip to: 40669 >+/* 19918 */ MCD_OPC_Decode, 233, 10, 89, // Opcode: SMINv2i32 >+/* 19922 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19940 >+/* 19926 */ MCD_OPC_CheckPredicate, 0, 3, 81, // Skip to: 40669 >+/* 19930 */ MCD_OPC_CheckField, 21, 1, 1, 253, 80, // Skip to: 40669 >+/* 19936 */ MCD_OPC_Decode, 224, 16, 89, // Opcode: UMINv2i32 >+/* 19940 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19958 >+/* 19944 */ MCD_OPC_CheckPredicate, 0, 241, 80, // Skip to: 40669 >+/* 19948 */ MCD_OPC_CheckField, 21, 1, 1, 235, 80, // Skip to: 40669 >+/* 19954 */ MCD_OPC_Decode, 235, 10, 112, // Opcode: SMINv4i32 >+/* 19958 */ MCD_OPC_FilterValue, 3, 227, 80, // Skip to: 40669 >+/* 19962 */ MCD_OPC_CheckPredicate, 0, 223, 80, // Skip to: 40669 >+/* 19966 */ MCD_OPC_CheckField, 21, 1, 1, 217, 80, // Skip to: 40669 >+/* 19972 */ MCD_OPC_Decode, 226, 16, 112, // Opcode: UMINv4i32 >+/* 19976 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 20055 >+/* 19980 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 19983 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20001 >+/* 19987 */ MCD_OPC_CheckPredicate, 0, 198, 80, // Skip to: 40669 >+/* 19991 */ MCD_OPC_CheckField, 21, 1, 1, 192, 80, // Skip to: 40669 >+/* 19997 */ MCD_OPC_Decode, 212, 9, 85, // Opcode: SABDLv2i32_v2i64 >+/* 20001 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20019 >+/* 20005 */ MCD_OPC_CheckPredicate, 0, 180, 80, // Skip to: 40669 >+/* 20009 */ MCD_OPC_CheckField, 21, 1, 1, 174, 80, // Skip to: 40669 >+/* 20015 */ MCD_OPC_Decode, 246, 15, 85, // Opcode: UABDLv2i32_v2i64 >+/* 20019 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20037 >+/* 20023 */ MCD_OPC_CheckPredicate, 0, 162, 80, // Skip to: 40669 >+/* 20027 */ MCD_OPC_CheckField, 21, 1, 1, 156, 80, // Skip to: 40669 >+/* 20033 */ MCD_OPC_Decode, 214, 9, 112, // Opcode: SABDLv4i32_v2i64 >+/* 20037 */ MCD_OPC_FilterValue, 3, 148, 80, // Skip to: 40669 >+/* 20041 */ MCD_OPC_CheckPredicate, 0, 144, 80, // Skip to: 40669 >+/* 20045 */ MCD_OPC_CheckField, 21, 1, 1, 138, 80, // Skip to: 40669 >+/* 20051 */ MCD_OPC_Decode, 248, 15, 112, // Opcode: UABDLv4i32_v2i64 >+/* 20055 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 20134 >+/* 20059 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20062 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20080 >+/* 20066 */ MCD_OPC_CheckPredicate, 0, 119, 80, // Skip to: 40669 >+/* 20070 */ MCD_OPC_CheckField, 21, 1, 1, 113, 80, // Skip to: 40669 >+/* 20076 */ MCD_OPC_Decode, 218, 9, 89, // Opcode: SABDv2i32 >+/* 20080 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20098 >+/* 20084 */ MCD_OPC_CheckPredicate, 0, 101, 80, // Skip to: 40669 >+/* 20088 */ MCD_OPC_CheckField, 21, 1, 1, 95, 80, // Skip to: 40669 >+/* 20094 */ MCD_OPC_Decode, 252, 15, 89, // Opcode: UABDv2i32 >+/* 20098 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20116 >+/* 20102 */ MCD_OPC_CheckPredicate, 0, 83, 80, // Skip to: 40669 >+/* 20106 */ MCD_OPC_CheckField, 21, 1, 1, 77, 80, // Skip to: 40669 >+/* 20112 */ MCD_OPC_Decode, 220, 9, 112, // Opcode: SABDv4i32 >+/* 20116 */ MCD_OPC_FilterValue, 3, 69, 80, // Skip to: 40669 >+/* 20120 */ MCD_OPC_CheckPredicate, 0, 65, 80, // Skip to: 40669 >+/* 20124 */ MCD_OPC_CheckField, 21, 1, 1, 59, 80, // Skip to: 40669 >+/* 20130 */ MCD_OPC_Decode, 254, 15, 112, // Opcode: UABDv4i32 >+/* 20134 */ MCD_OPC_FilterValue, 30, 113, 0, // Skip to: 20251 >+/* 20138 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20141 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 20178 >+/* 20145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 20148 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20160 >+/* 20152 */ MCD_OPC_CheckPredicate, 0, 33, 80, // Skip to: 40669 >+/* 20156 */ MCD_OPC_Decode, 206, 18, 89, // Opcode: ZIP2v2i32 >+/* 20160 */ MCD_OPC_FilterValue, 1, 25, 80, // Skip to: 40669 >+/* 20164 */ MCD_OPC_CheckPredicate, 0, 21, 80, // Skip to: 40669 >+/* 20168 */ MCD_OPC_CheckField, 16, 5, 0, 15, 80, // Skip to: 40669 >+/* 20174 */ MCD_OPC_Decode, 152, 11, 90, // Opcode: SQABSv2i32 >+/* 20178 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20196 >+/* 20182 */ MCD_OPC_CheckPredicate, 0, 3, 80, // Skip to: 40669 >+/* 20186 */ MCD_OPC_CheckField, 16, 6, 32, 253, 79, // Skip to: 40669 >+/* 20192 */ MCD_OPC_Decode, 222, 11, 90, // Opcode: SQNEGv2i32 >+/* 20196 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 20233 >+/* 20200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 20203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20215 >+/* 20207 */ MCD_OPC_CheckPredicate, 0, 234, 79, // Skip to: 40669 >+/* 20211 */ MCD_OPC_Decode, 209, 18, 112, // Opcode: ZIP2v4i32 >+/* 20215 */ MCD_OPC_FilterValue, 1, 226, 79, // Skip to: 40669 >+/* 20219 */ MCD_OPC_CheckPredicate, 0, 222, 79, // Skip to: 40669 >+/* 20223 */ MCD_OPC_CheckField, 16, 5, 0, 216, 79, // Skip to: 40669 >+/* 20229 */ MCD_OPC_Decode, 155, 11, 117, // Opcode: SQABSv4i32 >+/* 20233 */ MCD_OPC_FilterValue, 3, 208, 79, // Skip to: 40669 >+/* 20237 */ MCD_OPC_CheckPredicate, 0, 204, 79, // Skip to: 40669 >+/* 20241 */ MCD_OPC_CheckField, 16, 6, 32, 198, 79, // Skip to: 40669 >+/* 20247 */ MCD_OPC_Decode, 225, 11, 117, // Opcode: SQNEGv4i32 >+/* 20251 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 20330 >+/* 20255 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20258 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20276 >+/* 20262 */ MCD_OPC_CheckPredicate, 0, 179, 79, // Skip to: 40669 >+/* 20266 */ MCD_OPC_CheckField, 21, 1, 1, 173, 79, // Skip to: 40669 >+/* 20272 */ MCD_OPC_Decode, 206, 9, 109, // Opcode: SABAv2i32 >+/* 20276 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20294 >+/* 20280 */ MCD_OPC_CheckPredicate, 0, 161, 79, // Skip to: 40669 >+/* 20284 */ MCD_OPC_CheckField, 21, 1, 1, 155, 79, // Skip to: 40669 >+/* 20290 */ MCD_OPC_Decode, 240, 15, 109, // Opcode: UABAv2i32 >+/* 20294 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20312 >+/* 20298 */ MCD_OPC_CheckPredicate, 0, 143, 79, // Skip to: 40669 >+/* 20302 */ MCD_OPC_CheckField, 21, 1, 1, 137, 79, // Skip to: 40669 >+/* 20308 */ MCD_OPC_Decode, 208, 9, 120, // Opcode: SABAv4i32 >+/* 20312 */ MCD_OPC_FilterValue, 3, 129, 79, // Skip to: 40669 >+/* 20316 */ MCD_OPC_CheckPredicate, 0, 125, 79, // Skip to: 40669 >+/* 20320 */ MCD_OPC_CheckField, 21, 1, 1, 119, 79, // Skip to: 40669 >+/* 20326 */ MCD_OPC_Decode, 242, 15, 120, // Opcode: UABAv4i32 >+/* 20330 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 20409 >+/* 20334 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20337 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20355 >+/* 20341 */ MCD_OPC_CheckPredicate, 0, 100, 79, // Skip to: 40669 >+/* 20345 */ MCD_OPC_CheckField, 21, 1, 1, 94, 79, // Skip to: 40669 >+/* 20351 */ MCD_OPC_Decode, 240, 10, 105, // Opcode: SMLALv2i32_v2i64 >+/* 20355 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20373 >+/* 20359 */ MCD_OPC_CheckPredicate, 0, 82, 79, // Skip to: 40669 >+/* 20363 */ MCD_OPC_CheckField, 21, 1, 1, 76, 79, // Skip to: 40669 >+/* 20369 */ MCD_OPC_Decode, 231, 16, 105, // Opcode: UMLALv2i32_v2i64 >+/* 20373 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20391 >+/* 20377 */ MCD_OPC_CheckPredicate, 0, 64, 79, // Skip to: 40669 >+/* 20381 */ MCD_OPC_CheckField, 21, 1, 1, 58, 79, // Skip to: 40669 >+/* 20387 */ MCD_OPC_Decode, 244, 10, 120, // Opcode: SMLALv4i32_v2i64 >+/* 20391 */ MCD_OPC_FilterValue, 3, 50, 79, // Skip to: 40669 >+/* 20395 */ MCD_OPC_CheckPredicate, 0, 46, 79, // Skip to: 40669 >+/* 20399 */ MCD_OPC_CheckField, 21, 1, 1, 40, 79, // Skip to: 40669 >+/* 20405 */ MCD_OPC_Decode, 235, 16, 120, // Opcode: UMLALv4i32_v2i64 >+/* 20409 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 20486 >+/* 20413 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20416 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 20433 >+/* 20420 */ MCD_OPC_CheckPredicate, 0, 21, 79, // Skip to: 40669 >+/* 20424 */ MCD_OPC_CheckField, 21, 1, 1, 15, 79, // Skip to: 40669 >+/* 20430 */ MCD_OPC_Decode, 71, 89, // Opcode: ADDv2i32 >+/* 20433 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20451 >+/* 20437 */ MCD_OPC_CheckPredicate, 0, 4, 79, // Skip to: 40669 >+/* 20441 */ MCD_OPC_CheckField, 21, 1, 1, 254, 78, // Skip to: 40669 >+/* 20447 */ MCD_OPC_Decode, 175, 15, 89, // Opcode: SUBv2i32 >+/* 20451 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 20468 >+/* 20455 */ MCD_OPC_CheckPredicate, 0, 242, 78, // Skip to: 40669 >+/* 20459 */ MCD_OPC_CheckField, 21, 1, 1, 236, 78, // Skip to: 40669 >+/* 20465 */ MCD_OPC_Decode, 74, 112, // Opcode: ADDv4i32 >+/* 20468 */ MCD_OPC_FilterValue, 3, 229, 78, // Skip to: 40669 >+/* 20472 */ MCD_OPC_CheckPredicate, 0, 225, 78, // Skip to: 40669 >+/* 20476 */ MCD_OPC_CheckField, 21, 1, 1, 219, 78, // Skip to: 40669 >+/* 20482 */ MCD_OPC_Decode, 178, 15, 112, // Opcode: SUBv4i32 >+/* 20486 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 20591 >+/* 20490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20493 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20524 >+/* 20497 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20500 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20512 >+/* 20504 */ MCD_OPC_CheckPredicate, 0, 193, 78, // Skip to: 40669 >+/* 20508 */ MCD_OPC_Decode, 195, 1, 90, // Opcode: CMGTv2i32rz >+/* 20512 */ MCD_OPC_FilterValue, 33, 185, 78, // Skip to: 40669 >+/* 20516 */ MCD_OPC_CheckPredicate, 0, 181, 78, // Skip to: 40669 >+/* 20520 */ MCD_OPC_Decode, 172, 5, 90, // Opcode: FRINTPv2f32 >+/* 20524 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20542 >+/* 20528 */ MCD_OPC_CheckPredicate, 0, 169, 78, // Skip to: 40669 >+/* 20532 */ MCD_OPC_CheckField, 16, 6, 32, 163, 78, // Skip to: 40669 >+/* 20538 */ MCD_OPC_Decode, 179, 1, 90, // Opcode: CMGEv2i32rz >+/* 20542 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20573 >+/* 20546 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20549 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20561 >+/* 20553 */ MCD_OPC_CheckPredicate, 0, 144, 78, // Skip to: 40669 >+/* 20557 */ MCD_OPC_Decode, 201, 1, 117, // Opcode: CMGTv4i32rz >+/* 20561 */ MCD_OPC_FilterValue, 33, 136, 78, // Skip to: 40669 >+/* 20565 */ MCD_OPC_CheckPredicate, 0, 132, 78, // Skip to: 40669 >+/* 20569 */ MCD_OPC_Decode, 174, 5, 117, // Opcode: FRINTPv4f32 >+/* 20573 */ MCD_OPC_FilterValue, 3, 124, 78, // Skip to: 40669 >+/* 20577 */ MCD_OPC_CheckPredicate, 0, 120, 78, // Skip to: 40669 >+/* 20581 */ MCD_OPC_CheckField, 16, 6, 32, 114, 78, // Skip to: 40669 >+/* 20587 */ MCD_OPC_Decode, 185, 1, 117, // Opcode: CMGEv4i32rz >+/* 20591 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 20670 >+/* 20595 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20598 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20616 >+/* 20602 */ MCD_OPC_CheckPredicate, 0, 95, 78, // Skip to: 40669 >+/* 20606 */ MCD_OPC_CheckField, 21, 1, 1, 89, 78, // Skip to: 40669 >+/* 20612 */ MCD_OPC_Decode, 240, 1, 89, // Opcode: CMTSTv2i32 >+/* 20616 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20634 >+/* 20620 */ MCD_OPC_CheckPredicate, 0, 77, 78, // Skip to: 40669 >+/* 20624 */ MCD_OPC_CheckField, 21, 1, 1, 71, 78, // Skip to: 40669 >+/* 20630 */ MCD_OPC_Decode, 162, 1, 89, // Opcode: CMEQv2i32 >+/* 20634 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20652 >+/* 20638 */ MCD_OPC_CheckPredicate, 0, 59, 78, // Skip to: 40669 >+/* 20642 */ MCD_OPC_CheckField, 21, 1, 1, 53, 78, // Skip to: 40669 >+/* 20648 */ MCD_OPC_Decode, 243, 1, 112, // Opcode: CMTSTv4i32 >+/* 20652 */ MCD_OPC_FilterValue, 3, 45, 78, // Skip to: 40669 >+/* 20656 */ MCD_OPC_CheckPredicate, 0, 41, 78, // Skip to: 40669 >+/* 20660 */ MCD_OPC_CheckField, 21, 1, 1, 35, 78, // Skip to: 40669 >+/* 20666 */ MCD_OPC_Decode, 168, 1, 112, // Opcode: CMEQv4i32 >+/* 20670 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 20713 >+/* 20674 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20677 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20695 >+/* 20681 */ MCD_OPC_CheckPredicate, 0, 16, 78, // Skip to: 40669 >+/* 20685 */ MCD_OPC_CheckField, 21, 1, 1, 10, 78, // Skip to: 40669 >+/* 20691 */ MCD_OPC_Decode, 174, 11, 105, // Opcode: SQDMLALv2i32_v2i64 >+/* 20695 */ MCD_OPC_FilterValue, 2, 2, 78, // Skip to: 40669 >+/* 20699 */ MCD_OPC_CheckPredicate, 0, 254, 77, // Skip to: 40669 >+/* 20703 */ MCD_OPC_CheckField, 21, 1, 1, 248, 77, // Skip to: 40669 >+/* 20709 */ MCD_OPC_Decode, 178, 11, 120, // Opcode: SQDMLALv4i32_v2i64 >+/* 20713 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 20792 >+/* 20717 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20720 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20738 >+/* 20724 */ MCD_OPC_CheckPredicate, 0, 229, 77, // Skip to: 40669 >+/* 20728 */ MCD_OPC_CheckField, 21, 1, 1, 223, 77, // Skip to: 40669 >+/* 20734 */ MCD_OPC_Decode, 181, 8, 109, // Opcode: MLAv2i32 >+/* 20738 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20756 >+/* 20742 */ MCD_OPC_CheckPredicate, 0, 211, 77, // Skip to: 40669 >+/* 20746 */ MCD_OPC_CheckField, 21, 1, 1, 205, 77, // Skip to: 40669 >+/* 20752 */ MCD_OPC_Decode, 191, 8, 109, // Opcode: MLSv2i32 >+/* 20756 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20774 >+/* 20760 */ MCD_OPC_CheckPredicate, 0, 193, 77, // Skip to: 40669 >+/* 20764 */ MCD_OPC_CheckField, 21, 1, 1, 187, 77, // Skip to: 40669 >+/* 20770 */ MCD_OPC_Decode, 185, 8, 120, // Opcode: MLAv4i32 >+/* 20774 */ MCD_OPC_FilterValue, 3, 179, 77, // Skip to: 40669 >+/* 20778 */ MCD_OPC_CheckPredicate, 0, 175, 77, // Skip to: 40669 >+/* 20782 */ MCD_OPC_CheckField, 21, 1, 1, 169, 77, // Skip to: 40669 >+/* 20788 */ MCD_OPC_Decode, 195, 8, 120, // Opcode: MLSv4i32 >+/* 20792 */ MCD_OPC_FilterValue, 38, 127, 0, // Skip to: 20923 >+/* 20796 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20799 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20830 >+/* 20803 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20806 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20818 >+/* 20810 */ MCD_OPC_CheckPredicate, 0, 143, 77, // Skip to: 40669 >+/* 20814 */ MCD_OPC_Decode, 163, 1, 90, // Opcode: CMEQv2i32rz >+/* 20818 */ MCD_OPC_FilterValue, 33, 135, 77, // Skip to: 40669 >+/* 20822 */ MCD_OPC_CheckPredicate, 0, 131, 77, // Skip to: 40669 >+/* 20826 */ MCD_OPC_Decode, 182, 5, 90, // Opcode: FRINTZv2f32 >+/* 20830 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 20861 >+/* 20834 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20837 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20849 >+/* 20841 */ MCD_OPC_CheckPredicate, 0, 112, 77, // Skip to: 40669 >+/* 20845 */ MCD_OPC_Decode, 224, 1, 90, // Opcode: CMLEv2i32rz >+/* 20849 */ MCD_OPC_FilterValue, 33, 104, 77, // Skip to: 40669 >+/* 20853 */ MCD_OPC_CheckPredicate, 0, 100, 77, // Skip to: 40669 >+/* 20857 */ MCD_OPC_Decode, 157, 5, 90, // Opcode: FRINTIv2f32 >+/* 20861 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20892 >+/* 20865 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20868 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20880 >+/* 20872 */ MCD_OPC_CheckPredicate, 0, 81, 77, // Skip to: 40669 >+/* 20876 */ MCD_OPC_Decode, 169, 1, 117, // Opcode: CMEQv4i32rz >+/* 20880 */ MCD_OPC_FilterValue, 33, 73, 77, // Skip to: 40669 >+/* 20884 */ MCD_OPC_CheckPredicate, 0, 69, 77, // Skip to: 40669 >+/* 20888 */ MCD_OPC_Decode, 184, 5, 117, // Opcode: FRINTZv4f32 >+/* 20892 */ MCD_OPC_FilterValue, 3, 61, 77, // Skip to: 40669 >+/* 20896 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 20899 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20911 >+/* 20903 */ MCD_OPC_CheckPredicate, 0, 50, 77, // Skip to: 40669 >+/* 20907 */ MCD_OPC_Decode, 227, 1, 117, // Opcode: CMLEv4i32rz >+/* 20911 */ MCD_OPC_FilterValue, 33, 42, 77, // Skip to: 40669 >+/* 20915 */ MCD_OPC_CheckPredicate, 0, 38, 77, // Skip to: 40669 >+/* 20919 */ MCD_OPC_Decode, 159, 5, 117, // Opcode: FRINTIv4f32 >+/* 20923 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 20966 >+/* 20927 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20930 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20948 >+/* 20934 */ MCD_OPC_CheckPredicate, 0, 19, 77, // Skip to: 40669 >+/* 20938 */ MCD_OPC_CheckField, 21, 1, 1, 13, 77, // Skip to: 40669 >+/* 20944 */ MCD_OPC_Decode, 230, 8, 89, // Opcode: MULv2i32 >+/* 20948 */ MCD_OPC_FilterValue, 2, 5, 77, // Skip to: 40669 >+/* 20952 */ MCD_OPC_CheckPredicate, 0, 1, 77, // Skip to: 40669 >+/* 20956 */ MCD_OPC_CheckField, 21, 1, 1, 251, 76, // Skip to: 40669 >+/* 20962 */ MCD_OPC_Decode, 234, 8, 112, // Opcode: MULv4i32 >+/* 20966 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 21045 >+/* 20970 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 20973 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20991 >+/* 20977 */ MCD_OPC_CheckPredicate, 0, 232, 76, // Skip to: 40669 >+/* 20981 */ MCD_OPC_CheckField, 21, 1, 1, 226, 76, // Skip to: 40669 >+/* 20987 */ MCD_OPC_Decode, 250, 10, 105, // Opcode: SMLSLv2i32_v2i64 >+/* 20991 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21009 >+/* 20995 */ MCD_OPC_CheckPredicate, 0, 214, 76, // Skip to: 40669 >+/* 20999 */ MCD_OPC_CheckField, 21, 1, 1, 208, 76, // Skip to: 40669 >+/* 21005 */ MCD_OPC_Decode, 241, 16, 105, // Opcode: UMLSLv2i32_v2i64 >+/* 21009 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21027 >+/* 21013 */ MCD_OPC_CheckPredicate, 0, 196, 76, // Skip to: 40669 >+/* 21017 */ MCD_OPC_CheckField, 21, 1, 1, 190, 76, // Skip to: 40669 >+/* 21023 */ MCD_OPC_Decode, 254, 10, 120, // Opcode: SMLSLv4i32_v2i64 >+/* 21027 */ MCD_OPC_FilterValue, 3, 182, 76, // Skip to: 40669 >+/* 21031 */ MCD_OPC_CheckPredicate, 0, 178, 76, // Skip to: 40669 >+/* 21035 */ MCD_OPC_CheckField, 21, 1, 1, 172, 76, // Skip to: 40669 >+/* 21041 */ MCD_OPC_Decode, 245, 16, 120, // Opcode: UMLSLv4i32_v2i64 >+/* 21045 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 21124 >+/* 21049 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21052 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21070 >+/* 21056 */ MCD_OPC_CheckPredicate, 0, 153, 76, // Skip to: 40669 >+/* 21060 */ MCD_OPC_CheckField, 21, 1, 1, 147, 76, // Skip to: 40669 >+/* 21066 */ MCD_OPC_Decode, 204, 10, 89, // Opcode: SMAXPv2i32 >+/* 21070 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21088 >+/* 21074 */ MCD_OPC_CheckPredicate, 0, 135, 76, // Skip to: 40669 >+/* 21078 */ MCD_OPC_CheckField, 21, 1, 1, 129, 76, // Skip to: 40669 >+/* 21084 */ MCD_OPC_Decode, 196, 16, 89, // Opcode: UMAXPv2i32 >+/* 21088 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21106 >+/* 21092 */ MCD_OPC_CheckPredicate, 0, 117, 76, // Skip to: 40669 >+/* 21096 */ MCD_OPC_CheckField, 21, 1, 1, 111, 76, // Skip to: 40669 >+/* 21102 */ MCD_OPC_Decode, 206, 10, 112, // Opcode: SMAXPv4i32 >+/* 21106 */ MCD_OPC_FilterValue, 3, 103, 76, // Skip to: 40669 >+/* 21110 */ MCD_OPC_CheckPredicate, 0, 99, 76, // Skip to: 40669 >+/* 21114 */ MCD_OPC_CheckField, 21, 1, 1, 93, 76, // Skip to: 40669 >+/* 21120 */ MCD_OPC_Decode, 198, 16, 112, // Opcode: UMAXPv4i32 >+/* 21124 */ MCD_OPC_FilterValue, 42, 155, 0, // Skip to: 21283 >+/* 21128 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21131 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 21162 >+/* 21135 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21138 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21150 >+/* 21142 */ MCD_OPC_CheckPredicate, 0, 67, 76, // Skip to: 40669 >+/* 21146 */ MCD_OPC_Decode, 232, 1, 90, // Opcode: CMLTv2i32rz >+/* 21150 */ MCD_OPC_FilterValue, 2, 59, 76, // Skip to: 40669 >+/* 21154 */ MCD_OPC_CheckPredicate, 0, 55, 76, // Skip to: 40669 >+/* 21158 */ MCD_OPC_Decode, 235, 1, 117, // Opcode: CMLTv4i32rz >+/* 21162 */ MCD_OPC_FilterValue, 33, 51, 0, // Skip to: 21217 >+/* 21166 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21169 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21181 >+/* 21173 */ MCD_OPC_CheckPredicate, 0, 36, 76, // Skip to: 40669 >+/* 21177 */ MCD_OPC_Decode, 206, 3, 90, // Opcode: FCVTPSv2f32 >+/* 21181 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 21193 >+/* 21185 */ MCD_OPC_CheckPredicate, 0, 24, 76, // Skip to: 40669 >+/* 21189 */ MCD_OPC_Decode, 215, 3, 90, // Opcode: FCVTPUv2f32 >+/* 21193 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 21205 >+/* 21197 */ MCD_OPC_CheckPredicate, 0, 12, 76, // Skip to: 40669 >+/* 21201 */ MCD_OPC_Decode, 208, 3, 117, // Opcode: FCVTPSv4f32 >+/* 21205 */ MCD_OPC_FilterValue, 3, 4, 76, // Skip to: 40669 >+/* 21209 */ MCD_OPC_CheckPredicate, 0, 0, 76, // Skip to: 40669 >+/* 21213 */ MCD_OPC_Decode, 217, 3, 117, // Opcode: FCVTPUv4f32 >+/* 21217 */ MCD_OPC_FilterValue, 48, 29, 0, // Skip to: 21250 >+/* 21221 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21224 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21237 >+/* 21228 */ MCD_OPC_CheckPredicate, 0, 237, 75, // Skip to: 40669 >+/* 21232 */ MCD_OPC_Decode, 211, 10, 139, 1, // Opcode: SMAXVv4i32v >+/* 21237 */ MCD_OPC_FilterValue, 3, 228, 75, // Skip to: 40669 >+/* 21241 */ MCD_OPC_CheckPredicate, 0, 224, 75, // Skip to: 40669 >+/* 21245 */ MCD_OPC_Decode, 203, 16, 139, 1, // Opcode: UMAXVv4i32v >+/* 21250 */ MCD_OPC_FilterValue, 49, 215, 75, // Skip to: 40669 >+/* 21254 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21257 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21270 >+/* 21261 */ MCD_OPC_CheckPredicate, 0, 204, 75, // Skip to: 40669 >+/* 21265 */ MCD_OPC_Decode, 229, 10, 139, 1, // Opcode: SMINVv4i32v >+/* 21270 */ MCD_OPC_FilterValue, 3, 195, 75, // Skip to: 40669 >+/* 21274 */ MCD_OPC_CheckPredicate, 0, 191, 75, // Skip to: 40669 >+/* 21278 */ MCD_OPC_Decode, 220, 16, 139, 1, // Opcode: UMINVv4i32v >+/* 21283 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 21362 >+/* 21287 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21290 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21308 >+/* 21294 */ MCD_OPC_CheckPredicate, 0, 171, 75, // Skip to: 40669 >+/* 21298 */ MCD_OPC_CheckField, 21, 1, 1, 165, 75, // Skip to: 40669 >+/* 21304 */ MCD_OPC_Decode, 222, 10, 89, // Opcode: SMINPv2i32 >+/* 21308 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21326 >+/* 21312 */ MCD_OPC_CheckPredicate, 0, 153, 75, // Skip to: 40669 >+/* 21316 */ MCD_OPC_CheckField, 21, 1, 1, 147, 75, // Skip to: 40669 >+/* 21322 */ MCD_OPC_Decode, 213, 16, 89, // Opcode: UMINPv2i32 >+/* 21326 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21344 >+/* 21330 */ MCD_OPC_CheckPredicate, 0, 135, 75, // Skip to: 40669 >+/* 21334 */ MCD_OPC_CheckField, 21, 1, 1, 129, 75, // Skip to: 40669 >+/* 21340 */ MCD_OPC_Decode, 224, 10, 112, // Opcode: SMINPv4i32 >+/* 21344 */ MCD_OPC_FilterValue, 3, 121, 75, // Skip to: 40669 >+/* 21348 */ MCD_OPC_CheckPredicate, 0, 117, 75, // Skip to: 40669 >+/* 21352 */ MCD_OPC_CheckField, 21, 1, 1, 111, 75, // Skip to: 40669 >+/* 21358 */ MCD_OPC_Decode, 215, 16, 112, // Opcode: UMINPv4i32 >+/* 21362 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 21405 >+/* 21366 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21369 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21387 >+/* 21373 */ MCD_OPC_CheckPredicate, 0, 92, 75, // Skip to: 40669 >+/* 21377 */ MCD_OPC_CheckField, 21, 1, 1, 86, 75, // Skip to: 40669 >+/* 21383 */ MCD_OPC_Decode, 186, 11, 105, // Opcode: SQDMLSLv2i32_v2i64 >+/* 21387 */ MCD_OPC_FilterValue, 2, 78, 75, // Skip to: 40669 >+/* 21391 */ MCD_OPC_CheckPredicate, 0, 74, 75, // Skip to: 40669 >+/* 21395 */ MCD_OPC_CheckField, 21, 1, 1, 68, 75, // Skip to: 40669 >+/* 21401 */ MCD_OPC_Decode, 190, 11, 120, // Opcode: SQDMLSLv4i32_v2i64 >+/* 21405 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 21484 >+/* 21409 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21412 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21430 >+/* 21416 */ MCD_OPC_CheckPredicate, 0, 49, 75, // Skip to: 40669 >+/* 21420 */ MCD_OPC_CheckField, 21, 1, 1, 43, 75, // Skip to: 40669 >+/* 21426 */ MCD_OPC_Decode, 197, 11, 89, // Opcode: SQDMULHv2i32 >+/* 21430 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21448 >+/* 21434 */ MCD_OPC_CheckPredicate, 0, 31, 75, // Skip to: 40669 >+/* 21438 */ MCD_OPC_CheckField, 21, 1, 1, 25, 75, // Skip to: 40669 >+/* 21444 */ MCD_OPC_Decode, 232, 11, 89, // Opcode: SQRDMULHv2i32 >+/* 21448 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21466 >+/* 21452 */ MCD_OPC_CheckPredicate, 0, 13, 75, // Skip to: 40669 >+/* 21456 */ MCD_OPC_CheckField, 21, 1, 1, 7, 75, // Skip to: 40669 >+/* 21462 */ MCD_OPC_Decode, 201, 11, 112, // Opcode: SQDMULHv4i32 >+/* 21466 */ MCD_OPC_FilterValue, 3, 255, 74, // Skip to: 40669 >+/* 21470 */ MCD_OPC_CheckPredicate, 0, 251, 74, // Skip to: 40669 >+/* 21474 */ MCD_OPC_CheckField, 21, 1, 1, 245, 74, // Skip to: 40669 >+/* 21480 */ MCD_OPC_Decode, 236, 11, 112, // Opcode: SQRDMULHv4i32 >+/* 21484 */ MCD_OPC_FilterValue, 46, 137, 0, // Skip to: 21625 >+/* 21488 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21491 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 21521 >+/* 21495 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21498 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21509 >+/* 21502 */ MCD_OPC_CheckPredicate, 0, 219, 74, // Skip to: 40669 >+/* 21506 */ MCD_OPC_Decode, 22, 90, // Opcode: ABSv2i32 >+/* 21509 */ MCD_OPC_FilterValue, 33, 212, 74, // Skip to: 40669 >+/* 21513 */ MCD_OPC_CheckPredicate, 0, 208, 74, // Skip to: 40669 >+/* 21517 */ MCD_OPC_Decode, 246, 3, 90, // Opcode: FCVTZSv2f32 >+/* 21521 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21552 >+/* 21525 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21528 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21540 >+/* 21532 */ MCD_OPC_CheckPredicate, 0, 189, 74, // Skip to: 40669 >+/* 21536 */ MCD_OPC_Decode, 247, 8, 90, // Opcode: NEGv2i32 >+/* 21540 */ MCD_OPC_FilterValue, 33, 181, 74, // Skip to: 40669 >+/* 21544 */ MCD_OPC_CheckPredicate, 0, 177, 74, // Skip to: 40669 >+/* 21548 */ MCD_OPC_Decode, 147, 4, 90, // Opcode: FCVTZUv2f32 >+/* 21552 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 21594 >+/* 21556 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21559 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21570 >+/* 21563 */ MCD_OPC_CheckPredicate, 0, 158, 74, // Skip to: 40669 >+/* 21567 */ MCD_OPC_Decode, 25, 117, // Opcode: ABSv4i32 >+/* 21570 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21582 >+/* 21574 */ MCD_OPC_CheckPredicate, 0, 147, 74, // Skip to: 40669 >+/* 21578 */ MCD_OPC_Decode, 250, 3, 117, // Opcode: FCVTZSv4f32 >+/* 21582 */ MCD_OPC_FilterValue, 49, 139, 74, // Skip to: 40669 >+/* 21586 */ MCD_OPC_CheckPredicate, 0, 135, 74, // Skip to: 40669 >+/* 21590 */ MCD_OPC_Decode, 57, 139, 1, // Opcode: ADDVv4i32v >+/* 21594 */ MCD_OPC_FilterValue, 3, 127, 74, // Skip to: 40669 >+/* 21598 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21601 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21613 >+/* 21605 */ MCD_OPC_CheckPredicate, 0, 116, 74, // Skip to: 40669 >+/* 21609 */ MCD_OPC_Decode, 250, 8, 117, // Opcode: NEGv4i32 >+/* 21613 */ MCD_OPC_FilterValue, 33, 108, 74, // Skip to: 40669 >+/* 21617 */ MCD_OPC_CheckPredicate, 0, 104, 74, // Skip to: 40669 >+/* 21621 */ MCD_OPC_Decode, 151, 4, 117, // Opcode: FCVTZUv4f32 >+/* 21625 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 21666 >+/* 21629 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21632 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 21649 >+/* 21636 */ MCD_OPC_CheckPredicate, 0, 85, 74, // Skip to: 40669 >+/* 21640 */ MCD_OPC_CheckField, 21, 1, 1, 79, 74, // Skip to: 40669 >+/* 21646 */ MCD_OPC_Decode, 39, 89, // Opcode: ADDPv2i32 >+/* 21649 */ MCD_OPC_FilterValue, 2, 72, 74, // Skip to: 40669 >+/* 21653 */ MCD_OPC_CheckPredicate, 0, 68, 74, // Skip to: 40669 >+/* 21657 */ MCD_OPC_CheckField, 21, 1, 1, 62, 74, // Skip to: 40669 >+/* 21663 */ MCD_OPC_Decode, 43, 112, // Opcode: ADDPv4i32 >+/* 21666 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 21745 >+/* 21670 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21673 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21691 >+/* 21677 */ MCD_OPC_CheckPredicate, 0, 44, 74, // Skip to: 40669 >+/* 21681 */ MCD_OPC_CheckField, 21, 1, 1, 38, 74, // Skip to: 40669 >+/* 21687 */ MCD_OPC_Decode, 139, 11, 85, // Opcode: SMULLv2i32_v2i64 >+/* 21691 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21709 >+/* 21695 */ MCD_OPC_CheckPredicate, 0, 26, 74, // Skip to: 40669 >+/* 21699 */ MCD_OPC_CheckField, 21, 1, 1, 20, 74, // Skip to: 40669 >+/* 21705 */ MCD_OPC_Decode, 129, 17, 85, // Opcode: UMULLv2i32_v2i64 >+/* 21709 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21727 >+/* 21713 */ MCD_OPC_CheckPredicate, 0, 8, 74, // Skip to: 40669 >+/* 21717 */ MCD_OPC_CheckField, 21, 1, 1, 2, 74, // Skip to: 40669 >+/* 21723 */ MCD_OPC_Decode, 143, 11, 112, // Opcode: SMULLv4i32_v2i64 >+/* 21727 */ MCD_OPC_FilterValue, 3, 250, 73, // Skip to: 40669 >+/* 21731 */ MCD_OPC_CheckPredicate, 0, 246, 73, // Skip to: 40669 >+/* 21735 */ MCD_OPC_CheckField, 21, 1, 1, 240, 73, // Skip to: 40669 >+/* 21741 */ MCD_OPC_Decode, 133, 17, 112, // Opcode: UMULLv4i32_v2i64 >+/* 21745 */ MCD_OPC_FilterValue, 49, 75, 0, // Skip to: 21824 >+/* 21749 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21752 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21770 >+/* 21756 */ MCD_OPC_CheckPredicate, 0, 221, 73, // Skip to: 40669 >+/* 21760 */ MCD_OPC_CheckField, 21, 1, 1, 215, 73, // Skip to: 40669 >+/* 21766 */ MCD_OPC_Decode, 191, 4, 89, // Opcode: FMINNMv2f32 >+/* 21770 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21788 >+/* 21774 */ MCD_OPC_CheckPredicate, 0, 203, 73, // Skip to: 40669 >+/* 21778 */ MCD_OPC_CheckField, 21, 1, 1, 197, 73, // Skip to: 40669 >+/* 21784 */ MCD_OPC_Decode, 184, 4, 89, // Opcode: FMINNMPv2f32 >+/* 21788 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21806 >+/* 21792 */ MCD_OPC_CheckPredicate, 0, 185, 73, // Skip to: 40669 >+/* 21796 */ MCD_OPC_CheckField, 21, 1, 1, 179, 73, // Skip to: 40669 >+/* 21802 */ MCD_OPC_Decode, 193, 4, 112, // Opcode: FMINNMv4f32 >+/* 21806 */ MCD_OPC_FilterValue, 3, 171, 73, // Skip to: 40669 >+/* 21810 */ MCD_OPC_CheckPredicate, 0, 167, 73, // Skip to: 40669 >+/* 21814 */ MCD_OPC_CheckField, 21, 1, 1, 161, 73, // Skip to: 40669 >+/* 21820 */ MCD_OPC_Decode, 188, 4, 112, // Opcode: FMINNMPv4f32 >+/* 21824 */ MCD_OPC_FilterValue, 50, 140, 0, // Skip to: 21968 >+/* 21828 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21831 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 21862 >+/* 21835 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21838 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21850 >+/* 21842 */ MCD_OPC_CheckPredicate, 0, 135, 73, // Skip to: 40669 >+/* 21846 */ MCD_OPC_Decode, 238, 2, 90, // Opcode: FCMGTv2i32rz >+/* 21850 */ MCD_OPC_FilterValue, 33, 127, 73, // Skip to: 40669 >+/* 21854 */ MCD_OPC_CheckPredicate, 0, 123, 73, // Skip to: 40669 >+/* 21858 */ MCD_OPC_Decode, 219, 17, 90, // Opcode: URECPEv2i32 >+/* 21862 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21893 >+/* 21866 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21869 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21881 >+/* 21873 */ MCD_OPC_CheckPredicate, 0, 104, 73, // Skip to: 40669 >+/* 21877 */ MCD_OPC_Decode, 228, 2, 90, // Opcode: FCMGEv2i32rz >+/* 21881 */ MCD_OPC_FilterValue, 33, 96, 73, // Skip to: 40669 >+/* 21885 */ MCD_OPC_CheckPredicate, 0, 92, 73, // Skip to: 40669 >+/* 21889 */ MCD_OPC_Decode, 243, 17, 90, // Opcode: URSQRTEv2i32 >+/* 21893 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 21924 >+/* 21897 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21900 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21912 >+/* 21904 */ MCD_OPC_CheckPredicate, 0, 73, 73, // Skip to: 40669 >+/* 21908 */ MCD_OPC_Decode, 241, 2, 117, // Opcode: FCMGTv4i32rz >+/* 21912 */ MCD_OPC_FilterValue, 33, 65, 73, // Skip to: 40669 >+/* 21916 */ MCD_OPC_CheckPredicate, 0, 61, 73, // Skip to: 40669 >+/* 21920 */ MCD_OPC_Decode, 220, 17, 117, // Opcode: URECPEv4i32 >+/* 21924 */ MCD_OPC_FilterValue, 3, 53, 73, // Skip to: 40669 >+/* 21928 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 21931 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21943 >+/* 21935 */ MCD_OPC_CheckPredicate, 0, 42, 73, // Skip to: 40669 >+/* 21939 */ MCD_OPC_Decode, 231, 2, 117, // Opcode: FCMGEv4i32rz >+/* 21943 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21955 >+/* 21947 */ MCD_OPC_CheckPredicate, 0, 30, 73, // Skip to: 40669 >+/* 21951 */ MCD_OPC_Decode, 244, 17, 117, // Opcode: URSQRTEv4i32 >+/* 21955 */ MCD_OPC_FilterValue, 48, 22, 73, // Skip to: 40669 >+/* 21959 */ MCD_OPC_CheckPredicate, 0, 18, 73, // Skip to: 40669 >+/* 21963 */ MCD_OPC_Decode, 190, 4, 139, 1, // Opcode: FMINNMVv4i32v >+/* 21968 */ MCD_OPC_FilterValue, 51, 39, 0, // Skip to: 22011 >+/* 21972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 21975 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21993 >+/* 21979 */ MCD_OPC_CheckPredicate, 0, 254, 72, // Skip to: 40669 >+/* 21983 */ MCD_OPC_CheckField, 21, 1, 1, 248, 72, // Skip to: 40669 >+/* 21989 */ MCD_OPC_Decode, 214, 4, 109, // Opcode: FMLSv2f32 >+/* 21993 */ MCD_OPC_FilterValue, 2, 240, 72, // Skip to: 40669 >+/* 21997 */ MCD_OPC_CheckPredicate, 0, 236, 72, // Skip to: 40669 >+/* 22001 */ MCD_OPC_CheckField, 21, 1, 1, 230, 72, // Skip to: 40669 >+/* 22007 */ MCD_OPC_Decode, 218, 4, 120, // Opcode: FMLSv4f32 >+/* 22011 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 22054 >+/* 22015 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22018 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22036 >+/* 22022 */ MCD_OPC_CheckPredicate, 0, 211, 72, // Skip to: 40669 >+/* 22026 */ MCD_OPC_CheckField, 21, 1, 1, 205, 72, // Skip to: 40669 >+/* 22032 */ MCD_OPC_Decode, 210, 11, 85, // Opcode: SQDMULLv2i32_v2i64 >+/* 22036 */ MCD_OPC_FilterValue, 2, 197, 72, // Skip to: 40669 >+/* 22040 */ MCD_OPC_CheckPredicate, 0, 193, 72, // Skip to: 40669 >+/* 22044 */ MCD_OPC_CheckField, 21, 1, 1, 187, 72, // Skip to: 40669 >+/* 22050 */ MCD_OPC_Decode, 214, 11, 112, // Opcode: SQDMULLv4i32_v2i64 >+/* 22054 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 22133 >+/* 22058 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22061 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22079 >+/* 22065 */ MCD_OPC_CheckPredicate, 0, 168, 72, // Skip to: 40669 >+/* 22069 */ MCD_OPC_CheckField, 21, 1, 1, 162, 72, // Skip to: 40669 >+/* 22075 */ MCD_OPC_Decode, 202, 5, 89, // Opcode: FSUBv2f32 >+/* 22079 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22097 >+/* 22083 */ MCD_OPC_CheckPredicate, 0, 150, 72, // Skip to: 40669 >+/* 22087 */ MCD_OPC_CheckField, 21, 1, 1, 144, 72, // Skip to: 40669 >+/* 22093 */ MCD_OPC_Decode, 180, 2, 89, // Opcode: FABDv2f32 >+/* 22097 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22115 >+/* 22101 */ MCD_OPC_CheckPredicate, 0, 132, 72, // Skip to: 40669 >+/* 22105 */ MCD_OPC_CheckField, 21, 1, 1, 126, 72, // Skip to: 40669 >+/* 22111 */ MCD_OPC_Decode, 204, 5, 112, // Opcode: FSUBv4f32 >+/* 22115 */ MCD_OPC_FilterValue, 3, 118, 72, // Skip to: 40669 >+/* 22119 */ MCD_OPC_CheckPredicate, 0, 114, 72, // Skip to: 40669 >+/* 22123 */ MCD_OPC_CheckField, 21, 1, 1, 108, 72, // Skip to: 40669 >+/* 22129 */ MCD_OPC_Decode, 182, 2, 112, // Opcode: FABDv4f32 >+/* 22133 */ MCD_OPC_FilterValue, 54, 127, 0, // Skip to: 22264 >+/* 22137 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22140 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 22171 >+/* 22144 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22147 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22159 >+/* 22151 */ MCD_OPC_CheckPredicate, 0, 82, 72, // Skip to: 40669 >+/* 22155 */ MCD_OPC_Decode, 218, 2, 90, // Opcode: FCMEQv2i32rz >+/* 22159 */ MCD_OPC_FilterValue, 33, 74, 72, // Skip to: 40669 >+/* 22163 */ MCD_OPC_CheckPredicate, 0, 70, 72, // Skip to: 40669 >+/* 22167 */ MCD_OPC_Decode, 140, 5, 90, // Opcode: FRECPEv2f32 >+/* 22171 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22202 >+/* 22175 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22178 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22190 >+/* 22182 */ MCD_OPC_CheckPredicate, 0, 51, 72, // Skip to: 40669 >+/* 22186 */ MCD_OPC_Decode, 244, 2, 90, // Opcode: FCMLEv2i32rz >+/* 22190 */ MCD_OPC_FilterValue, 33, 43, 72, // Skip to: 40669 >+/* 22194 */ MCD_OPC_CheckPredicate, 0, 39, 72, // Skip to: 40669 >+/* 22198 */ MCD_OPC_Decode, 187, 5, 90, // Opcode: FRSQRTEv2f32 >+/* 22202 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 22233 >+/* 22206 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22209 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22221 >+/* 22213 */ MCD_OPC_CheckPredicate, 0, 20, 72, // Skip to: 40669 >+/* 22217 */ MCD_OPC_Decode, 221, 2, 117, // Opcode: FCMEQv4i32rz >+/* 22221 */ MCD_OPC_FilterValue, 33, 12, 72, // Skip to: 40669 >+/* 22225 */ MCD_OPC_CheckPredicate, 0, 8, 72, // Skip to: 40669 >+/* 22229 */ MCD_OPC_Decode, 142, 5, 117, // Opcode: FRECPEv4f32 >+/* 22233 */ MCD_OPC_FilterValue, 3, 0, 72, // Skip to: 40669 >+/* 22237 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22240 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22252 >+/* 22244 */ MCD_OPC_CheckPredicate, 0, 245, 71, // Skip to: 40669 >+/* 22248 */ MCD_OPC_Decode, 246, 2, 117, // Opcode: FCMLEv4i32rz >+/* 22252 */ MCD_OPC_FilterValue, 33, 237, 71, // Skip to: 40669 >+/* 22256 */ MCD_OPC_CheckPredicate, 0, 233, 71, // Skip to: 40669 >+/* 22260 */ MCD_OPC_Decode, 189, 5, 117, // Opcode: FRSQRTEv4f32 >+/* 22264 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 22307 >+/* 22268 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22271 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22289 >+/* 22275 */ MCD_OPC_CheckPredicate, 0, 214, 71, // Skip to: 40669 >+/* 22279 */ MCD_OPC_CheckField, 21, 1, 1, 208, 71, // Skip to: 40669 >+/* 22285 */ MCD_OPC_Decode, 236, 2, 89, // Opcode: FCMGTv2f32 >+/* 22289 */ MCD_OPC_FilterValue, 3, 200, 71, // Skip to: 40669 >+/* 22293 */ MCD_OPC_CheckPredicate, 0, 196, 71, // Skip to: 40669 >+/* 22297 */ MCD_OPC_CheckField, 21, 1, 1, 190, 71, // Skip to: 40669 >+/* 22303 */ MCD_OPC_Decode, 240, 2, 112, // Opcode: FCMGTv4f32 >+/* 22307 */ MCD_OPC_FilterValue, 58, 39, 0, // Skip to: 22350 >+/* 22311 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22314 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22332 >+/* 22318 */ MCD_OPC_CheckPredicate, 0, 171, 71, // Skip to: 40669 >+/* 22322 */ MCD_OPC_CheckField, 16, 6, 32, 165, 71, // Skip to: 40669 >+/* 22328 */ MCD_OPC_Decode, 249, 2, 90, // Opcode: FCMLTv2i32rz >+/* 22332 */ MCD_OPC_FilterValue, 2, 157, 71, // Skip to: 40669 >+/* 22336 */ MCD_OPC_CheckPredicate, 0, 153, 71, // Skip to: 40669 >+/* 22340 */ MCD_OPC_CheckField, 16, 6, 32, 147, 71, // Skip to: 40669 >+/* 22346 */ MCD_OPC_Decode, 251, 2, 117, // Opcode: FCMLTv4i32rz >+/* 22350 */ MCD_OPC_FilterValue, 59, 39, 0, // Skip to: 22393 >+/* 22354 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22357 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22375 >+/* 22361 */ MCD_OPC_CheckPredicate, 0, 128, 71, // Skip to: 40669 >+/* 22365 */ MCD_OPC_CheckField, 21, 1, 1, 122, 71, // Skip to: 40669 >+/* 22371 */ MCD_OPC_Decode, 195, 2, 89, // Opcode: FACGTv2f32 >+/* 22375 */ MCD_OPC_FilterValue, 3, 114, 71, // Skip to: 40669 >+/* 22379 */ MCD_OPC_CheckPredicate, 0, 110, 71, // Skip to: 40669 >+/* 22383 */ MCD_OPC_CheckField, 21, 1, 1, 104, 71, // Skip to: 40669 >+/* 22389 */ MCD_OPC_Decode, 197, 2, 112, // Opcode: FACGTv4f32 >+/* 22393 */ MCD_OPC_FilterValue, 61, 75, 0, // Skip to: 22472 >+/* 22397 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22400 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22418 >+/* 22404 */ MCD_OPC_CheckPredicate, 0, 85, 71, // Skip to: 40669 >+/* 22408 */ MCD_OPC_CheckField, 21, 1, 1, 79, 71, // Skip to: 40669 >+/* 22414 */ MCD_OPC_Decode, 201, 4, 89, // Opcode: FMINv2f32 >+/* 22418 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22436 >+/* 22422 */ MCD_OPC_CheckPredicate, 0, 67, 71, // Skip to: 40669 >+/* 22426 */ MCD_OPC_CheckField, 21, 1, 1, 61, 71, // Skip to: 40669 >+/* 22432 */ MCD_OPC_Decode, 194, 4, 89, // Opcode: FMINPv2f32 >+/* 22436 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22454 >+/* 22440 */ MCD_OPC_CheckPredicate, 0, 49, 71, // Skip to: 40669 >+/* 22444 */ MCD_OPC_CheckField, 21, 1, 1, 43, 71, // Skip to: 40669 >+/* 22450 */ MCD_OPC_Decode, 203, 4, 112, // Opcode: FMINv4f32 >+/* 22454 */ MCD_OPC_FilterValue, 3, 35, 71, // Skip to: 40669 >+/* 22458 */ MCD_OPC_CheckPredicate, 0, 31, 71, // Skip to: 40669 >+/* 22462 */ MCD_OPC_CheckField, 21, 1, 1, 25, 71, // Skip to: 40669 >+/* 22468 */ MCD_OPC_Decode, 198, 4, 112, // Opcode: FMINPv4f32 >+/* 22472 */ MCD_OPC_FilterValue, 62, 114, 0, // Skip to: 22590 >+/* 22476 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22479 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22497 >+/* 22483 */ MCD_OPC_CheckPredicate, 0, 6, 71, // Skip to: 40669 >+/* 22487 */ MCD_OPC_CheckField, 16, 6, 32, 0, 71, // Skip to: 40669 >+/* 22493 */ MCD_OPC_Decode, 185, 2, 90, // Opcode: FABSv2f32 >+/* 22497 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22528 >+/* 22501 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22504 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22516 >+/* 22508 */ MCD_OPC_CheckPredicate, 0, 237, 70, // Skip to: 40669 >+/* 22512 */ MCD_OPC_Decode, 129, 5, 90, // Opcode: FNEGv2f32 >+/* 22516 */ MCD_OPC_FilterValue, 33, 229, 70, // Skip to: 40669 >+/* 22520 */ MCD_OPC_CheckPredicate, 0, 225, 70, // Skip to: 40669 >+/* 22524 */ MCD_OPC_Decode, 197, 5, 90, // Opcode: FSQRTv2f32 >+/* 22528 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22546 >+/* 22532 */ MCD_OPC_CheckPredicate, 0, 213, 70, // Skip to: 40669 >+/* 22536 */ MCD_OPC_CheckField, 16, 6, 32, 207, 70, // Skip to: 40669 >+/* 22542 */ MCD_OPC_Decode, 187, 2, 117, // Opcode: FABSv4f32 >+/* 22546 */ MCD_OPC_FilterValue, 3, 199, 70, // Skip to: 40669 >+/* 22550 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 22553 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22565 >+/* 22557 */ MCD_OPC_CheckPredicate, 0, 188, 70, // Skip to: 40669 >+/* 22561 */ MCD_OPC_Decode, 131, 5, 117, // Opcode: FNEGv4f32 >+/* 22565 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 22577 >+/* 22569 */ MCD_OPC_CheckPredicate, 0, 176, 70, // Skip to: 40669 >+/* 22573 */ MCD_OPC_Decode, 199, 5, 117, // Opcode: FSQRTv4f32 >+/* 22577 */ MCD_OPC_FilterValue, 48, 168, 70, // Skip to: 40669 >+/* 22581 */ MCD_OPC_CheckPredicate, 0, 164, 70, // Skip to: 40669 >+/* 22585 */ MCD_OPC_Decode, 200, 4, 139, 1, // Opcode: FMINVv4i32v >+/* 22590 */ MCD_OPC_FilterValue, 63, 155, 70, // Skip to: 40669 >+/* 22594 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22597 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22615 >+/* 22601 */ MCD_OPC_CheckPredicate, 0, 144, 70, // Skip to: 40669 >+/* 22605 */ MCD_OPC_CheckField, 21, 1, 1, 138, 70, // Skip to: 40669 >+/* 22611 */ MCD_OPC_Decode, 192, 5, 89, // Opcode: FRSQRTSv2f32 >+/* 22615 */ MCD_OPC_FilterValue, 2, 130, 70, // Skip to: 40669 >+/* 22619 */ MCD_OPC_CheckPredicate, 0, 126, 70, // Skip to: 40669 >+/* 22623 */ MCD_OPC_CheckField, 21, 1, 1, 120, 70, // Skip to: 40669 >+/* 22629 */ MCD_OPC_Decode, 194, 5, 112, // Opcode: FRSQRTSv4f32 >+/* 22633 */ MCD_OPC_FilterValue, 11, 193, 5, // Skip to: 24110 >+/* 22637 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 22640 */ MCD_OPC_FilterValue, 3, 39, 0, // Skip to: 22683 >+/* 22644 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22647 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22665 >+/* 22651 */ MCD_OPC_CheckPredicate, 0, 94, 70, // Skip to: 40669 >+/* 22655 */ MCD_OPC_CheckField, 21, 1, 1, 88, 70, // Skip to: 40669 >+/* 22661 */ MCD_OPC_Decode, 164, 11, 112, // Opcode: SQADDv2i64 >+/* 22665 */ MCD_OPC_FilterValue, 3, 80, 70, // Skip to: 40669 >+/* 22669 */ MCD_OPC_CheckPredicate, 0, 76, 70, // Skip to: 40669 >+/* 22673 */ MCD_OPC_CheckField, 21, 1, 1, 70, 70, // Skip to: 40669 >+/* 22679 */ MCD_OPC_Decode, 143, 17, 112, // Opcode: UQADDv2i64 >+/* 22683 */ MCD_OPC_FilterValue, 6, 20, 0, // Skip to: 22707 >+/* 22687 */ MCD_OPC_CheckPredicate, 0, 58, 70, // Skip to: 40669 >+/* 22691 */ MCD_OPC_CheckField, 29, 3, 2, 52, 70, // Skip to: 40669 >+/* 22697 */ MCD_OPC_CheckField, 21, 1, 0, 46, 70, // Skip to: 40669 >+/* 22703 */ MCD_OPC_Decode, 180, 18, 112, // Opcode: UZP1v2i64 >+/* 22707 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 22784 >+/* 22711 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22714 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22732 >+/* 22718 */ MCD_OPC_CheckPredicate, 0, 27, 70, // Skip to: 40669 >+/* 22722 */ MCD_OPC_CheckField, 21, 1, 1, 21, 70, // Skip to: 40669 >+/* 22728 */ MCD_OPC_Decode, 132, 9, 89, // Opcode: ORNv8i8 >+/* 22732 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 22749 >+/* 22736 */ MCD_OPC_CheckPredicate, 0, 9, 70, // Skip to: 40669 >+/* 22740 */ MCD_OPC_CheckField, 21, 1, 1, 3, 70, // Skip to: 40669 >+/* 22746 */ MCD_OPC_Decode, 119, 89, // Opcode: BIFv8i8 >+/* 22749 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22767 >+/* 22753 */ MCD_OPC_CheckPredicate, 0, 248, 69, // Skip to: 40669 >+/* 22757 */ MCD_OPC_CheckField, 21, 1, 1, 242, 69, // Skip to: 40669 >+/* 22763 */ MCD_OPC_Decode, 131, 9, 112, // Opcode: ORNv16i8 >+/* 22767 */ MCD_OPC_FilterValue, 3, 234, 69, // Skip to: 40669 >+/* 22771 */ MCD_OPC_CheckPredicate, 0, 230, 69, // Skip to: 40669 >+/* 22775 */ MCD_OPC_CheckField, 21, 1, 1, 224, 69, // Skip to: 40669 >+/* 22781 */ MCD_OPC_Decode, 118, 112, // Opcode: BIFv16i8 >+/* 22784 */ MCD_OPC_FilterValue, 10, 20, 0, // Skip to: 22808 >+/* 22788 */ MCD_OPC_CheckPredicate, 0, 213, 69, // Skip to: 40669 >+/* 22792 */ MCD_OPC_CheckField, 29, 3, 2, 207, 69, // Skip to: 40669 >+/* 22798 */ MCD_OPC_CheckField, 21, 1, 0, 201, 69, // Skip to: 40669 >+/* 22804 */ MCD_OPC_Decode, 221, 15, 112, // Opcode: TRN1v2i64 >+/* 22808 */ MCD_OPC_FilterValue, 11, 39, 0, // Skip to: 22851 >+/* 22812 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22815 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22833 >+/* 22819 */ MCD_OPC_CheckPredicate, 0, 182, 69, // Skip to: 40669 >+/* 22823 */ MCD_OPC_CheckField, 21, 1, 1, 176, 69, // Skip to: 40669 >+/* 22829 */ MCD_OPC_Decode, 198, 12, 112, // Opcode: SQSUBv2i64 >+/* 22833 */ MCD_OPC_FilterValue, 3, 168, 69, // Skip to: 40669 >+/* 22837 */ MCD_OPC_CheckPredicate, 0, 164, 69, // Skip to: 40669 >+/* 22841 */ MCD_OPC_CheckField, 21, 1, 1, 158, 69, // Skip to: 40669 >+/* 22847 */ MCD_OPC_Decode, 205, 17, 112, // Opcode: UQSUBv2i64 >+/* 22851 */ MCD_OPC_FilterValue, 13, 39, 0, // Skip to: 22894 >+/* 22855 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22858 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22876 >+/* 22862 */ MCD_OPC_CheckPredicate, 0, 139, 69, // Skip to: 40669 >+/* 22866 */ MCD_OPC_CheckField, 21, 1, 1, 133, 69, // Skip to: 40669 >+/* 22872 */ MCD_OPC_Decode, 196, 1, 112, // Opcode: CMGTv2i64 >+/* 22876 */ MCD_OPC_FilterValue, 3, 125, 69, // Skip to: 40669 >+/* 22880 */ MCD_OPC_CheckPredicate, 0, 121, 69, // Skip to: 40669 >+/* 22884 */ MCD_OPC_CheckField, 21, 1, 1, 115, 69, // Skip to: 40669 >+/* 22890 */ MCD_OPC_Decode, 209, 1, 112, // Opcode: CMHIv2i64 >+/* 22894 */ MCD_OPC_FilterValue, 14, 64, 0, // Skip to: 22962 >+/* 22898 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 22901 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22919 >+/* 22905 */ MCD_OPC_CheckPredicate, 0, 96, 69, // Skip to: 40669 >+/* 22909 */ MCD_OPC_CheckField, 29, 3, 2, 90, 69, // Skip to: 40669 >+/* 22915 */ MCD_OPC_Decode, 200, 18, 112, // Opcode: ZIP1v2i64 >+/* 22919 */ MCD_OPC_FilterValue, 1, 82, 69, // Skip to: 40669 >+/* 22923 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22926 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22944 >+/* 22930 */ MCD_OPC_CheckPredicate, 0, 71, 69, // Skip to: 40669 >+/* 22934 */ MCD_OPC_CheckField, 16, 5, 0, 65, 69, // Skip to: 40669 >+/* 22940 */ MCD_OPC_Decode, 187, 15, 126, // Opcode: SUQADDv2i64 >+/* 22944 */ MCD_OPC_FilterValue, 3, 57, 69, // Skip to: 40669 >+/* 22948 */ MCD_OPC_CheckPredicate, 0, 53, 69, // Skip to: 40669 >+/* 22952 */ MCD_OPC_CheckField, 16, 5, 0, 47, 69, // Skip to: 40669 >+/* 22958 */ MCD_OPC_Decode, 153, 18, 126, // Opcode: USQADDv2i64 >+/* 22962 */ MCD_OPC_FilterValue, 15, 39, 0, // Skip to: 23005 >+/* 22966 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 22969 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22987 >+/* 22973 */ MCD_OPC_CheckPredicate, 0, 28, 69, // Skip to: 40669 >+/* 22977 */ MCD_OPC_CheckField, 21, 1, 1, 22, 69, // Skip to: 40669 >+/* 22983 */ MCD_OPC_Decode, 180, 1, 112, // Opcode: CMGEv2i64 >+/* 22987 */ MCD_OPC_FilterValue, 3, 14, 69, // Skip to: 40669 >+/* 22991 */ MCD_OPC_CheckPredicate, 0, 10, 69, // Skip to: 40669 >+/* 22995 */ MCD_OPC_CheckField, 21, 1, 1, 4, 69, // Skip to: 40669 >+/* 23001 */ MCD_OPC_Decode, 217, 1, 112, // Opcode: CMHSv2i64 >+/* 23005 */ MCD_OPC_FilterValue, 17, 39, 0, // Skip to: 23048 >+/* 23009 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23012 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23030 >+/* 23016 */ MCD_OPC_CheckPredicate, 0, 241, 68, // Skip to: 40669 >+/* 23020 */ MCD_OPC_CheckField, 21, 1, 1, 235, 68, // Skip to: 40669 >+/* 23026 */ MCD_OPC_Decode, 140, 13, 112, // Opcode: SSHLv2i64 >+/* 23030 */ MCD_OPC_FilterValue, 3, 227, 68, // Skip to: 40669 >+/* 23034 */ MCD_OPC_CheckPredicate, 0, 223, 68, // Skip to: 40669 >+/* 23038 */ MCD_OPC_CheckField, 21, 1, 1, 217, 68, // Skip to: 40669 >+/* 23044 */ MCD_OPC_Decode, 134, 18, 112, // Opcode: USHLv2i64 >+/* 23048 */ MCD_OPC_FilterValue, 19, 39, 0, // Skip to: 23091 >+/* 23052 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23055 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23073 >+/* 23059 */ MCD_OPC_CheckPredicate, 0, 198, 68, // Skip to: 40669 >+/* 23063 */ MCD_OPC_CheckField, 21, 1, 1, 192, 68, // Skip to: 40669 >+/* 23069 */ MCD_OPC_Decode, 164, 12, 112, // Opcode: SQSHLv2i64 >+/* 23073 */ MCD_OPC_FilterValue, 3, 184, 68, // Skip to: 40669 >+/* 23077 */ MCD_OPC_CheckPredicate, 0, 180, 68, // Skip to: 40669 >+/* 23081 */ MCD_OPC_CheckField, 21, 1, 1, 174, 68, // Skip to: 40669 >+/* 23087 */ MCD_OPC_Decode, 180, 17, 112, // Opcode: UQSHLv2i64 >+/* 23091 */ MCD_OPC_FilterValue, 21, 39, 0, // Skip to: 23134 >+/* 23095 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23098 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23116 >+/* 23102 */ MCD_OPC_CheckPredicate, 0, 155, 68, // Skip to: 40669 >+/* 23106 */ MCD_OPC_CheckField, 21, 1, 1, 149, 68, // Skip to: 40669 >+/* 23112 */ MCD_OPC_Decode, 238, 12, 112, // Opcode: SRSHLv2i64 >+/* 23116 */ MCD_OPC_FilterValue, 3, 141, 68, // Skip to: 40669 >+/* 23120 */ MCD_OPC_CheckPredicate, 0, 137, 68, // Skip to: 40669 >+/* 23124 */ MCD_OPC_CheckField, 21, 1, 1, 131, 68, // Skip to: 40669 >+/* 23130 */ MCD_OPC_Decode, 230, 17, 112, // Opcode: URSHLv2i64 >+/* 23134 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 23158 >+/* 23138 */ MCD_OPC_CheckPredicate, 0, 119, 68, // Skip to: 40669 >+/* 23142 */ MCD_OPC_CheckField, 29, 3, 2, 113, 68, // Skip to: 40669 >+/* 23148 */ MCD_OPC_CheckField, 21, 1, 0, 107, 68, // Skip to: 40669 >+/* 23154 */ MCD_OPC_Decode, 187, 18, 112, // Opcode: UZP2v2i64 >+/* 23158 */ MCD_OPC_FilterValue, 23, 39, 0, // Skip to: 23201 >+/* 23162 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23165 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23183 >+/* 23169 */ MCD_OPC_CheckPredicate, 0, 88, 68, // Skip to: 40669 >+/* 23173 */ MCD_OPC_CheckField, 21, 1, 1, 82, 68, // Skip to: 40669 >+/* 23179 */ MCD_OPC_Decode, 246, 11, 112, // Opcode: SQRSHLv2i64 >+/* 23183 */ MCD_OPC_FilterValue, 3, 74, 68, // Skip to: 40669 >+/* 23187 */ MCD_OPC_CheckPredicate, 0, 70, 68, // Skip to: 40669 >+/* 23191 */ MCD_OPC_CheckField, 21, 1, 1, 64, 68, // Skip to: 40669 >+/* 23197 */ MCD_OPC_Decode, 154, 17, 112, // Opcode: UQRSHLv2i64 >+/* 23201 */ MCD_OPC_FilterValue, 26, 20, 0, // Skip to: 23225 >+/* 23205 */ MCD_OPC_CheckPredicate, 0, 52, 68, // Skip to: 40669 >+/* 23209 */ MCD_OPC_CheckField, 29, 3, 2, 46, 68, // Skip to: 40669 >+/* 23215 */ MCD_OPC_CheckField, 21, 1, 0, 40, 68, // Skip to: 40669 >+/* 23221 */ MCD_OPC_Decode, 228, 15, 112, // Opcode: TRN2v2i64 >+/* 23225 */ MCD_OPC_FilterValue, 30, 64, 0, // Skip to: 23293 >+/* 23229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 23232 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23250 >+/* 23236 */ MCD_OPC_CheckPredicate, 0, 21, 68, // Skip to: 40669 >+/* 23240 */ MCD_OPC_CheckField, 29, 3, 2, 15, 68, // Skip to: 40669 >+/* 23246 */ MCD_OPC_Decode, 207, 18, 112, // Opcode: ZIP2v2i64 >+/* 23250 */ MCD_OPC_FilterValue, 1, 7, 68, // Skip to: 40669 >+/* 23254 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23257 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23275 >+/* 23261 */ MCD_OPC_CheckPredicate, 0, 252, 67, // Skip to: 40669 >+/* 23265 */ MCD_OPC_CheckField, 16, 5, 0, 246, 67, // Skip to: 40669 >+/* 23271 */ MCD_OPC_Decode, 153, 11, 117, // Opcode: SQABSv2i64 >+/* 23275 */ MCD_OPC_FilterValue, 3, 238, 67, // Skip to: 40669 >+/* 23279 */ MCD_OPC_CheckPredicate, 0, 234, 67, // Skip to: 40669 >+/* 23283 */ MCD_OPC_CheckField, 16, 5, 0, 228, 67, // Skip to: 40669 >+/* 23289 */ MCD_OPC_Decode, 223, 11, 117, // Opcode: SQNEGv2i64 >+/* 23293 */ MCD_OPC_FilterValue, 33, 38, 0, // Skip to: 23335 >+/* 23297 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23300 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 23317 >+/* 23304 */ MCD_OPC_CheckPredicate, 0, 209, 67, // Skip to: 40669 >+/* 23308 */ MCD_OPC_CheckField, 21, 1, 1, 203, 67, // Skip to: 40669 >+/* 23314 */ MCD_OPC_Decode, 72, 112, // Opcode: ADDv2i64 >+/* 23317 */ MCD_OPC_FilterValue, 3, 196, 67, // Skip to: 40669 >+/* 23321 */ MCD_OPC_CheckPredicate, 0, 192, 67, // Skip to: 40669 >+/* 23325 */ MCD_OPC_CheckField, 21, 1, 1, 186, 67, // Skip to: 40669 >+/* 23331 */ MCD_OPC_Decode, 176, 15, 112, // Opcode: SUBv2i64 >+/* 23335 */ MCD_OPC_FilterValue, 34, 52, 0, // Skip to: 23391 >+/* 23339 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 23342 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23373 >+/* 23346 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23349 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23361 >+/* 23353 */ MCD_OPC_CheckPredicate, 0, 160, 67, // Skip to: 40669 >+/* 23357 */ MCD_OPC_Decode, 197, 1, 117, // Opcode: CMGTv2i64rz >+/* 23361 */ MCD_OPC_FilterValue, 3, 152, 67, // Skip to: 40669 >+/* 23365 */ MCD_OPC_CheckPredicate, 0, 148, 67, // Skip to: 40669 >+/* 23369 */ MCD_OPC_Decode, 181, 1, 117, // Opcode: CMGEv2i64rz >+/* 23373 */ MCD_OPC_FilterValue, 33, 140, 67, // Skip to: 40669 >+/* 23377 */ MCD_OPC_CheckPredicate, 0, 136, 67, // Skip to: 40669 >+/* 23381 */ MCD_OPC_CheckField, 29, 3, 2, 130, 67, // Skip to: 40669 >+/* 23387 */ MCD_OPC_Decode, 173, 5, 117, // Opcode: FRINTPv2f64 >+/* 23391 */ MCD_OPC_FilterValue, 35, 39, 0, // Skip to: 23434 >+/* 23395 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23398 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23416 >+/* 23402 */ MCD_OPC_CheckPredicate, 0, 111, 67, // Skip to: 40669 >+/* 23406 */ MCD_OPC_CheckField, 21, 1, 1, 105, 67, // Skip to: 40669 >+/* 23412 */ MCD_OPC_Decode, 241, 1, 112, // Opcode: CMTSTv2i64 >+/* 23416 */ MCD_OPC_FilterValue, 3, 97, 67, // Skip to: 40669 >+/* 23420 */ MCD_OPC_CheckPredicate, 0, 93, 67, // Skip to: 40669 >+/* 23424 */ MCD_OPC_CheckField, 21, 1, 1, 87, 67, // Skip to: 40669 >+/* 23430 */ MCD_OPC_Decode, 164, 1, 112, // Opcode: CMEQv2i64 >+/* 23434 */ MCD_OPC_FilterValue, 38, 65, 0, // Skip to: 23503 >+/* 23438 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 23441 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23472 >+/* 23445 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23448 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23460 >+/* 23452 */ MCD_OPC_CheckPredicate, 0, 61, 67, // Skip to: 40669 >+/* 23456 */ MCD_OPC_Decode, 165, 1, 117, // Opcode: CMEQv2i64rz >+/* 23460 */ MCD_OPC_FilterValue, 3, 53, 67, // Skip to: 40669 >+/* 23464 */ MCD_OPC_CheckPredicate, 0, 49, 67, // Skip to: 40669 >+/* 23468 */ MCD_OPC_Decode, 225, 1, 117, // Opcode: CMLEv2i64rz >+/* 23472 */ MCD_OPC_FilterValue, 33, 41, 67, // Skip to: 40669 >+/* 23476 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23479 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23491 >+/* 23483 */ MCD_OPC_CheckPredicate, 0, 30, 67, // Skip to: 40669 >+/* 23487 */ MCD_OPC_Decode, 183, 5, 117, // Opcode: FRINTZv2f64 >+/* 23491 */ MCD_OPC_FilterValue, 3, 22, 67, // Skip to: 40669 >+/* 23495 */ MCD_OPC_CheckPredicate, 0, 18, 67, // Skip to: 40669 >+/* 23499 */ MCD_OPC_Decode, 158, 5, 117, // Opcode: FRINTIv2f64 >+/* 23503 */ MCD_OPC_FilterValue, 42, 52, 0, // Skip to: 23559 >+/* 23507 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 23510 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 23528 >+/* 23514 */ MCD_OPC_CheckPredicate, 0, 255, 66, // Skip to: 40669 >+/* 23518 */ MCD_OPC_CheckField, 29, 3, 2, 249, 66, // Skip to: 40669 >+/* 23524 */ MCD_OPC_Decode, 233, 1, 117, // Opcode: CMLTv2i64rz >+/* 23528 */ MCD_OPC_FilterValue, 33, 241, 66, // Skip to: 40669 >+/* 23532 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23535 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23547 >+/* 23539 */ MCD_OPC_CheckPredicate, 0, 230, 66, // Skip to: 40669 >+/* 23543 */ MCD_OPC_Decode, 207, 3, 117, // Opcode: FCVTPSv2f64 >+/* 23547 */ MCD_OPC_FilterValue, 3, 222, 66, // Skip to: 40669 >+/* 23551 */ MCD_OPC_CheckPredicate, 0, 218, 66, // Skip to: 40669 >+/* 23555 */ MCD_OPC_Decode, 216, 3, 117, // Opcode: FCVTPUv2f64 >+/* 23559 */ MCD_OPC_FilterValue, 46, 64, 0, // Skip to: 23627 >+/* 23563 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 23566 */ MCD_OPC_FilterValue, 32, 26, 0, // Skip to: 23596 >+/* 23570 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23573 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 23584 >+/* 23577 */ MCD_OPC_CheckPredicate, 0, 192, 66, // Skip to: 40669 >+/* 23581 */ MCD_OPC_Decode, 23, 117, // Opcode: ABSv2i64 >+/* 23584 */ MCD_OPC_FilterValue, 3, 185, 66, // Skip to: 40669 >+/* 23588 */ MCD_OPC_CheckPredicate, 0, 181, 66, // Skip to: 40669 >+/* 23592 */ MCD_OPC_Decode, 248, 8, 117, // Opcode: NEGv2i64 >+/* 23596 */ MCD_OPC_FilterValue, 33, 173, 66, // Skip to: 40669 >+/* 23600 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23603 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23615 >+/* 23607 */ MCD_OPC_CheckPredicate, 0, 162, 66, // Skip to: 40669 >+/* 23611 */ MCD_OPC_Decode, 247, 3, 117, // Opcode: FCVTZSv2f64 >+/* 23615 */ MCD_OPC_FilterValue, 3, 154, 66, // Skip to: 40669 >+/* 23619 */ MCD_OPC_CheckPredicate, 0, 150, 66, // Skip to: 40669 >+/* 23623 */ MCD_OPC_Decode, 148, 4, 117, // Opcode: FCVTZUv2f64 >+/* 23627 */ MCD_OPC_FilterValue, 47, 19, 0, // Skip to: 23650 >+/* 23631 */ MCD_OPC_CheckPredicate, 0, 138, 66, // Skip to: 40669 >+/* 23635 */ MCD_OPC_CheckField, 29, 3, 2, 132, 66, // Skip to: 40669 >+/* 23641 */ MCD_OPC_CheckField, 21, 1, 1, 126, 66, // Skip to: 40669 >+/* 23647 */ MCD_OPC_Decode, 40, 112, // Opcode: ADDPv2i64 >+/* 23650 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 23693 >+/* 23654 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23657 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23675 >+/* 23661 */ MCD_OPC_CheckPredicate, 0, 108, 66, // Skip to: 40669 >+/* 23665 */ MCD_OPC_CheckField, 21, 1, 1, 102, 66, // Skip to: 40669 >+/* 23671 */ MCD_OPC_Decode, 192, 4, 112, // Opcode: FMINNMv2f64 >+/* 23675 */ MCD_OPC_FilterValue, 3, 94, 66, // Skip to: 40669 >+/* 23679 */ MCD_OPC_CheckPredicate, 0, 90, 66, // Skip to: 40669 >+/* 23683 */ MCD_OPC_CheckField, 21, 1, 1, 84, 66, // Skip to: 40669 >+/* 23689 */ MCD_OPC_Decode, 185, 4, 112, // Opcode: FMINNMPv2f64 >+/* 23693 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 23736 >+/* 23697 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23700 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23718 >+/* 23704 */ MCD_OPC_CheckPredicate, 0, 65, 66, // Skip to: 40669 >+/* 23708 */ MCD_OPC_CheckField, 16, 6, 32, 59, 66, // Skip to: 40669 >+/* 23714 */ MCD_OPC_Decode, 239, 2, 117, // Opcode: FCMGTv2i64rz >+/* 23718 */ MCD_OPC_FilterValue, 3, 51, 66, // Skip to: 40669 >+/* 23722 */ MCD_OPC_CheckPredicate, 0, 47, 66, // Skip to: 40669 >+/* 23726 */ MCD_OPC_CheckField, 16, 6, 32, 41, 66, // Skip to: 40669 >+/* 23732 */ MCD_OPC_Decode, 229, 2, 117, // Opcode: FCMGEv2i64rz >+/* 23736 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 23760 >+/* 23740 */ MCD_OPC_CheckPredicate, 0, 29, 66, // Skip to: 40669 >+/* 23744 */ MCD_OPC_CheckField, 29, 3, 2, 23, 66, // Skip to: 40669 >+/* 23750 */ MCD_OPC_CheckField, 21, 1, 1, 17, 66, // Skip to: 40669 >+/* 23756 */ MCD_OPC_Decode, 215, 4, 120, // Opcode: FMLSv2f64 >+/* 23760 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 23803 >+/* 23764 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23767 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23785 >+/* 23771 */ MCD_OPC_CheckPredicate, 0, 254, 65, // Skip to: 40669 >+/* 23775 */ MCD_OPC_CheckField, 21, 1, 1, 248, 65, // Skip to: 40669 >+/* 23781 */ MCD_OPC_Decode, 203, 5, 112, // Opcode: FSUBv2f64 >+/* 23785 */ MCD_OPC_FilterValue, 3, 240, 65, // Skip to: 40669 >+/* 23789 */ MCD_OPC_CheckPredicate, 0, 236, 65, // Skip to: 40669 >+/* 23793 */ MCD_OPC_CheckField, 21, 1, 1, 230, 65, // Skip to: 40669 >+/* 23799 */ MCD_OPC_Decode, 181, 2, 112, // Opcode: FABDv2f64 >+/* 23803 */ MCD_OPC_FilterValue, 54, 65, 0, // Skip to: 23872 >+/* 23807 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 23810 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23841 >+/* 23814 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23817 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23829 >+/* 23821 */ MCD_OPC_CheckPredicate, 0, 204, 65, // Skip to: 40669 >+/* 23825 */ MCD_OPC_Decode, 219, 2, 117, // Opcode: FCMEQv2i64rz >+/* 23829 */ MCD_OPC_FilterValue, 3, 196, 65, // Skip to: 40669 >+/* 23833 */ MCD_OPC_CheckPredicate, 0, 192, 65, // Skip to: 40669 >+/* 23837 */ MCD_OPC_Decode, 245, 2, 117, // Opcode: FCMLEv2i64rz >+/* 23841 */ MCD_OPC_FilterValue, 33, 184, 65, // Skip to: 40669 >+/* 23845 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23848 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23860 >+/* 23852 */ MCD_OPC_CheckPredicate, 0, 173, 65, // Skip to: 40669 >+/* 23856 */ MCD_OPC_Decode, 141, 5, 117, // Opcode: FRECPEv2f64 >+/* 23860 */ MCD_OPC_FilterValue, 3, 165, 65, // Skip to: 40669 >+/* 23864 */ MCD_OPC_CheckPredicate, 0, 161, 65, // Skip to: 40669 >+/* 23868 */ MCD_OPC_Decode, 188, 5, 117, // Opcode: FRSQRTEv2f64 >+/* 23872 */ MCD_OPC_FilterValue, 56, 39, 0, // Skip to: 23915 >+/* 23876 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23879 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23897 >+/* 23883 */ MCD_OPC_CheckPredicate, 1, 142, 65, // Skip to: 40669 >+/* 23887 */ MCD_OPC_CheckField, 21, 1, 1, 136, 65, // Skip to: 40669 >+/* 23893 */ MCD_OPC_Decode, 146, 9, 85, // Opcode: PMULLv1i64 >+/* 23897 */ MCD_OPC_FilterValue, 2, 128, 65, // Skip to: 40669 >+/* 23901 */ MCD_OPC_CheckPredicate, 1, 124, 65, // Skip to: 40669 >+/* 23905 */ MCD_OPC_CheckField, 21, 1, 1, 118, 65, // Skip to: 40669 >+/* 23911 */ MCD_OPC_Decode, 147, 9, 112, // Opcode: PMULLv2i64 >+/* 23915 */ MCD_OPC_FilterValue, 57, 20, 0, // Skip to: 23939 >+/* 23919 */ MCD_OPC_CheckPredicate, 0, 106, 65, // Skip to: 40669 >+/* 23923 */ MCD_OPC_CheckField, 29, 3, 3, 100, 65, // Skip to: 40669 >+/* 23929 */ MCD_OPC_CheckField, 21, 1, 1, 94, 65, // Skip to: 40669 >+/* 23935 */ MCD_OPC_Decode, 237, 2, 112, // Opcode: FCMGTv2f64 >+/* 23939 */ MCD_OPC_FilterValue, 58, 20, 0, // Skip to: 23963 >+/* 23943 */ MCD_OPC_CheckPredicate, 0, 82, 65, // Skip to: 40669 >+/* 23947 */ MCD_OPC_CheckField, 29, 3, 2, 76, 65, // Skip to: 40669 >+/* 23953 */ MCD_OPC_CheckField, 16, 6, 32, 70, 65, // Skip to: 40669 >+/* 23959 */ MCD_OPC_Decode, 250, 2, 117, // Opcode: FCMLTv2i64rz >+/* 23963 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 23987 >+/* 23967 */ MCD_OPC_CheckPredicate, 0, 58, 65, // Skip to: 40669 >+/* 23971 */ MCD_OPC_CheckField, 29, 3, 3, 52, 65, // Skip to: 40669 >+/* 23977 */ MCD_OPC_CheckField, 21, 1, 1, 46, 65, // Skip to: 40669 >+/* 23983 */ MCD_OPC_Decode, 196, 2, 112, // Opcode: FACGTv2f64 >+/* 23987 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 24030 >+/* 23991 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 23994 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 24012 >+/* 23998 */ MCD_OPC_CheckPredicate, 0, 27, 65, // Skip to: 40669 >+/* 24002 */ MCD_OPC_CheckField, 21, 1, 1, 21, 65, // Skip to: 40669 >+/* 24008 */ MCD_OPC_Decode, 202, 4, 112, // Opcode: FMINv2f64 >+/* 24012 */ MCD_OPC_FilterValue, 3, 13, 65, // Skip to: 40669 >+/* 24016 */ MCD_OPC_CheckPredicate, 0, 9, 65, // Skip to: 40669 >+/* 24020 */ MCD_OPC_CheckField, 21, 1, 1, 3, 65, // Skip to: 40669 >+/* 24026 */ MCD_OPC_Decode, 195, 4, 112, // Opcode: FMINPv2f64 >+/* 24030 */ MCD_OPC_FilterValue, 62, 52, 0, // Skip to: 24086 >+/* 24034 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 24037 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 24068 >+/* 24041 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 24044 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 24056 >+/* 24048 */ MCD_OPC_CheckPredicate, 0, 233, 64, // Skip to: 40669 >+/* 24052 */ MCD_OPC_Decode, 186, 2, 117, // Opcode: FABSv2f64 >+/* 24056 */ MCD_OPC_FilterValue, 3, 225, 64, // Skip to: 40669 >+/* 24060 */ MCD_OPC_CheckPredicate, 0, 221, 64, // Skip to: 40669 >+/* 24064 */ MCD_OPC_Decode, 130, 5, 117, // Opcode: FNEGv2f64 >+/* 24068 */ MCD_OPC_FilterValue, 33, 213, 64, // Skip to: 40669 >+/* 24072 */ MCD_OPC_CheckPredicate, 0, 209, 64, // Skip to: 40669 >+/* 24076 */ MCD_OPC_CheckField, 29, 3, 3, 203, 64, // Skip to: 40669 >+/* 24082 */ MCD_OPC_Decode, 198, 5, 117, // Opcode: FSQRTv2f64 >+/* 24086 */ MCD_OPC_FilterValue, 63, 195, 64, // Skip to: 40669 >+/* 24090 */ MCD_OPC_CheckPredicate, 0, 191, 64, // Skip to: 40669 >+/* 24094 */ MCD_OPC_CheckField, 29, 3, 2, 185, 64, // Skip to: 40669 >+/* 24100 */ MCD_OPC_CheckField, 21, 1, 1, 179, 64, // Skip to: 40669 >+/* 24106 */ MCD_OPC_Decode, 193, 5, 112, // Opcode: FRSQRTSv2f64 >+/* 24110 */ MCD_OPC_FilterValue, 12, 165, 13, // Skip to: 27607 >+/* 24114 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 24117 */ MCD_OPC_FilterValue, 0, 66, 3, // Skip to: 24955 >+/* 24121 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 24124 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 24811 >+/* 24128 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 24131 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 24482 >+/* 24135 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 24138 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24271 >+/* 24142 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24145 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24238 >+/* 24149 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24152 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24205 >+/* 24156 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 24159 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24172 >+/* 24163 */ MCD_OPC_CheckPredicate, 0, 118, 64, // Skip to: 40669 >+/* 24167 */ MCD_OPC_Decode, 203, 8, 145, 1, // Opcode: MOVIv2i32 >+/* 24172 */ MCD_OPC_FilterValue, 1, 109, 64, // Skip to: 40669 >+/* 24176 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24179 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24192 >+/* 24183 */ MCD_OPC_CheckPredicate, 0, 98, 64, // Skip to: 40669 >+/* 24187 */ MCD_OPC_Decode, 152, 13, 146, 1, // Opcode: SSHRv8i8_shift >+/* 24192 */ MCD_OPC_FilterValue, 1, 89, 64, // Skip to: 40669 >+/* 24196 */ MCD_OPC_CheckPredicate, 0, 85, 64, // Skip to: 40669 >+/* 24200 */ MCD_OPC_Decode, 250, 12, 146, 1, // Opcode: SRSHRv8i8_shift >+/* 24205 */ MCD_OPC_FilterValue, 1, 76, 64, // Skip to: 40669 >+/* 24209 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24212 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24225 >+/* 24216 */ MCD_OPC_CheckPredicate, 0, 65, 64, // Skip to: 40669 >+/* 24220 */ MCD_OPC_Decode, 149, 13, 147, 1, // Opcode: SSHRv4i16_shift >+/* 24225 */ MCD_OPC_FilterValue, 1, 56, 64, // Skip to: 40669 >+/* 24229 */ MCD_OPC_CheckPredicate, 0, 52, 64, // Skip to: 40669 >+/* 24233 */ MCD_OPC_Decode, 247, 12, 147, 1, // Opcode: SRSHRv4i16_shift >+/* 24238 */ MCD_OPC_FilterValue, 1, 43, 64, // Skip to: 40669 >+/* 24242 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24245 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24258 >+/* 24249 */ MCD_OPC_CheckPredicate, 0, 32, 64, // Skip to: 40669 >+/* 24253 */ MCD_OPC_Decode, 147, 13, 148, 1, // Opcode: SSHRv2i32_shift >+/* 24258 */ MCD_OPC_FilterValue, 1, 23, 64, // Skip to: 40669 >+/* 24262 */ MCD_OPC_CheckPredicate, 0, 19, 64, // Skip to: 40669 >+/* 24266 */ MCD_OPC_Decode, 245, 12, 148, 1, // Opcode: SRSHRv2i32_shift >+/* 24271 */ MCD_OPC_FilterValue, 1, 10, 64, // Skip to: 40669 >+/* 24275 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24278 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 24423 >+/* 24282 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24285 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 24364 >+/* 24289 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 24292 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24305 >+/* 24296 */ MCD_OPC_CheckPredicate, 0, 241, 63, // Skip to: 40669 >+/* 24300 */ MCD_OPC_Decode, 140, 9, 149, 1, // Opcode: ORRv2i32 >+/* 24305 */ MCD_OPC_FilterValue, 1, 232, 63, // Skip to: 40669 >+/* 24309 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24312 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24325 >+/* 24316 */ MCD_OPC_CheckPredicate, 0, 221, 63, // Skip to: 40669 >+/* 24320 */ MCD_OPC_Decode, 160, 13, 150, 1, // Opcode: SSRAv8i8_shift >+/* 24325 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24338 >+/* 24329 */ MCD_OPC_CheckPredicate, 0, 208, 63, // Skip to: 40669 >+/* 24333 */ MCD_OPC_Decode, 130, 13, 150, 1, // Opcode: SRSRAv8i8_shift >+/* 24338 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24351 >+/* 24342 */ MCD_OPC_CheckPredicate, 0, 195, 63, // Skip to: 40669 >+/* 24346 */ MCD_OPC_Decode, 181, 10, 151, 1, // Opcode: SHLv8i8_shift >+/* 24351 */ MCD_OPC_FilterValue, 3, 186, 63, // Skip to: 40669 >+/* 24355 */ MCD_OPC_CheckPredicate, 0, 182, 63, // Skip to: 40669 >+/* 24359 */ MCD_OPC_Decode, 173, 12, 151, 1, // Opcode: SQSHLv8i8_shift >+/* 24364 */ MCD_OPC_FilterValue, 1, 173, 63, // Skip to: 40669 >+/* 24368 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24371 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24384 >+/* 24375 */ MCD_OPC_CheckPredicate, 0, 162, 63, // Skip to: 40669 >+/* 24379 */ MCD_OPC_Decode, 157, 13, 152, 1, // Opcode: SSRAv4i16_shift >+/* 24384 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24397 >+/* 24388 */ MCD_OPC_CheckPredicate, 0, 149, 63, // Skip to: 40669 >+/* 24392 */ MCD_OPC_Decode, 255, 12, 152, 1, // Opcode: SRSRAv4i16_shift >+/* 24397 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24410 >+/* 24401 */ MCD_OPC_CheckPredicate, 0, 136, 63, // Skip to: 40669 >+/* 24405 */ MCD_OPC_Decode, 178, 10, 153, 1, // Opcode: SHLv4i16_shift >+/* 24410 */ MCD_OPC_FilterValue, 3, 127, 63, // Skip to: 40669 >+/* 24414 */ MCD_OPC_CheckPredicate, 0, 123, 63, // Skip to: 40669 >+/* 24418 */ MCD_OPC_Decode, 167, 12, 153, 1, // Opcode: SQSHLv4i16_shift >+/* 24423 */ MCD_OPC_FilterValue, 1, 114, 63, // Skip to: 40669 >+/* 24427 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 24430 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24443 >+/* 24434 */ MCD_OPC_CheckPredicate, 0, 103, 63, // Skip to: 40669 >+/* 24438 */ MCD_OPC_Decode, 155, 13, 154, 1, // Opcode: SSRAv2i32_shift >+/* 24443 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24456 >+/* 24447 */ MCD_OPC_CheckPredicate, 0, 90, 63, // Skip to: 40669 >+/* 24451 */ MCD_OPC_Decode, 253, 12, 154, 1, // Opcode: SRSRAv2i32_shift >+/* 24456 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24469 >+/* 24460 */ MCD_OPC_CheckPredicate, 0, 77, 63, // Skip to: 40669 >+/* 24464 */ MCD_OPC_Decode, 176, 10, 155, 1, // Opcode: SHLv2i32_shift >+/* 24469 */ MCD_OPC_FilterValue, 3, 68, 63, // Skip to: 40669 >+/* 24473 */ MCD_OPC_CheckPredicate, 0, 64, 63, // Skip to: 40669 >+/* 24477 */ MCD_OPC_Decode, 163, 12, 155, 1, // Opcode: SQSHLv2i32_shift >+/* 24482 */ MCD_OPC_FilterValue, 1, 55, 63, // Skip to: 40669 >+/* 24486 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 24489 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 24720 >+/* 24493 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 24496 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24629 >+/* 24500 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24503 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24596 >+/* 24507 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24510 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24563 >+/* 24514 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 24517 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24530 >+/* 24521 */ MCD_OPC_CheckPredicate, 0, 16, 63, // Skip to: 40669 >+/* 24525 */ MCD_OPC_Decode, 205, 8, 145, 1, // Opcode: MOVIv4i16 >+/* 24530 */ MCD_OPC_FilterValue, 1, 7, 63, // Skip to: 40669 >+/* 24534 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 24537 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24550 >+/* 24541 */ MCD_OPC_CheckPredicate, 0, 252, 62, // Skip to: 40669 >+/* 24545 */ MCD_OPC_Decode, 187, 10, 156, 1, // Opcode: SHRNv8i8_shift >+/* 24550 */ MCD_OPC_FilterValue, 1, 243, 62, // Skip to: 40669 >+/* 24554 */ MCD_OPC_CheckPredicate, 0, 239, 62, // Skip to: 40669 >+/* 24558 */ MCD_OPC_Decode, 136, 13, 157, 1, // Opcode: SSHLLv8i8_shift >+/* 24563 */ MCD_OPC_FilterValue, 1, 230, 62, // Skip to: 40669 >+/* 24567 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 24570 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24583 >+/* 24574 */ MCD_OPC_CheckPredicate, 0, 219, 62, // Skip to: 40669 >+/* 24578 */ MCD_OPC_Decode, 184, 10, 158, 1, // Opcode: SHRNv4i16_shift >+/* 24583 */ MCD_OPC_FilterValue, 1, 210, 62, // Skip to: 40669 >+/* 24587 */ MCD_OPC_CheckPredicate, 0, 206, 62, // Skip to: 40669 >+/* 24591 */ MCD_OPC_Decode, 133, 13, 159, 1, // Opcode: SSHLLv4i16_shift >+/* 24596 */ MCD_OPC_FilterValue, 1, 197, 62, // Skip to: 40669 >+/* 24600 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 24603 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24616 >+/* 24607 */ MCD_OPC_CheckPredicate, 0, 186, 62, // Skip to: 40669 >+/* 24611 */ MCD_OPC_Decode, 183, 10, 160, 1, // Opcode: SHRNv2i32_shift >+/* 24616 */ MCD_OPC_FilterValue, 1, 177, 62, // Skip to: 40669 >+/* 24620 */ MCD_OPC_CheckPredicate, 0, 173, 62, // Skip to: 40669 >+/* 24624 */ MCD_OPC_Decode, 132, 13, 161, 1, // Opcode: SSHLLv2i32_shift >+/* 24629 */ MCD_OPC_FilterValue, 1, 164, 62, // Skip to: 40669 >+/* 24633 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24636 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 24701 >+/* 24640 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24643 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24682 >+/* 24647 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 24650 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24663 >+/* 24654 */ MCD_OPC_CheckPredicate, 0, 139, 62, // Skip to: 40669 >+/* 24658 */ MCD_OPC_Decode, 141, 9, 149, 1, // Opcode: ORRv4i16 >+/* 24663 */ MCD_OPC_FilterValue, 1, 130, 62, // Skip to: 40669 >+/* 24667 */ MCD_OPC_CheckPredicate, 0, 126, 62, // Skip to: 40669 >+/* 24671 */ MCD_OPC_CheckField, 13, 1, 0, 120, 62, // Skip to: 40669 >+/* 24677 */ MCD_OPC_Decode, 182, 12, 156, 1, // Opcode: SQSHRNv8i8_shift >+/* 24682 */ MCD_OPC_FilterValue, 1, 111, 62, // Skip to: 40669 >+/* 24686 */ MCD_OPC_CheckPredicate, 0, 107, 62, // Skip to: 40669 >+/* 24690 */ MCD_OPC_CheckField, 13, 1, 0, 101, 62, // Skip to: 40669 >+/* 24696 */ MCD_OPC_Decode, 179, 12, 158, 1, // Opcode: SQSHRNv4i16_shift >+/* 24701 */ MCD_OPC_FilterValue, 1, 92, 62, // Skip to: 40669 >+/* 24705 */ MCD_OPC_CheckPredicate, 0, 88, 62, // Skip to: 40669 >+/* 24709 */ MCD_OPC_CheckField, 13, 1, 0, 82, 62, // Skip to: 40669 >+/* 24715 */ MCD_OPC_Decode, 178, 12, 160, 1, // Opcode: SQSHRNv2i32_shift >+/* 24720 */ MCD_OPC_FilterValue, 1, 73, 62, // Skip to: 40669 >+/* 24724 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 24727 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24746 >+/* 24731 */ MCD_OPC_CheckPredicate, 0, 62, 62, // Skip to: 40669 >+/* 24735 */ MCD_OPC_CheckField, 19, 3, 0, 56, 62, // Skip to: 40669 >+/* 24741 */ MCD_OPC_Decode, 204, 8, 145, 1, // Opcode: MOVIv2s_msl >+/* 24746 */ MCD_OPC_FilterValue, 1, 47, 62, // Skip to: 40669 >+/* 24750 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 24753 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24792 >+/* 24757 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24760 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24779 >+/* 24764 */ MCD_OPC_CheckPredicate, 0, 29, 62, // Skip to: 40669 >+/* 24768 */ MCD_OPC_CheckField, 19, 2, 0, 23, 62, // Skip to: 40669 >+/* 24774 */ MCD_OPC_Decode, 208, 8, 145, 1, // Opcode: MOVIv8b_ns >+/* 24779 */ MCD_OPC_FilterValue, 1, 14, 62, // Skip to: 40669 >+/* 24783 */ MCD_OPC_CheckPredicate, 0, 10, 62, // Skip to: 40669 >+/* 24787 */ MCD_OPC_Decode, 144, 10, 148, 1, // Opcode: SCVTFv2i32_shift >+/* 24792 */ MCD_OPC_FilterValue, 1, 1, 62, // Skip to: 40669 >+/* 24796 */ MCD_OPC_CheckPredicate, 0, 253, 61, // Skip to: 40669 >+/* 24800 */ MCD_OPC_CheckField, 19, 3, 0, 247, 61, // Skip to: 40669 >+/* 24806 */ MCD_OPC_Decode, 230, 4, 145, 1, // Opcode: FMOVv2f32_ns >+/* 24811 */ MCD_OPC_FilterValue, 3, 238, 61, // Skip to: 40669 >+/* 24815 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 24818 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 24877 >+/* 24822 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24825 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24864 >+/* 24829 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24832 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24851 >+/* 24836 */ MCD_OPC_CheckPredicate, 0, 213, 61, // Skip to: 40669 >+/* 24840 */ MCD_OPC_CheckField, 19, 1, 1, 207, 61, // Skip to: 40669 >+/* 24846 */ MCD_OPC_Decode, 192, 9, 156, 1, // Opcode: RSHRNv8i8_shift >+/* 24851 */ MCD_OPC_FilterValue, 1, 198, 61, // Skip to: 40669 >+/* 24855 */ MCD_OPC_CheckPredicate, 0, 194, 61, // Skip to: 40669 >+/* 24859 */ MCD_OPC_Decode, 189, 9, 158, 1, // Opcode: RSHRNv4i16_shift >+/* 24864 */ MCD_OPC_FilterValue, 1, 185, 61, // Skip to: 40669 >+/* 24868 */ MCD_OPC_CheckPredicate, 0, 181, 61, // Skip to: 40669 >+/* 24872 */ MCD_OPC_Decode, 188, 9, 160, 1, // Opcode: RSHRNv2i32_shift >+/* 24877 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 24936 >+/* 24881 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24884 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24923 >+/* 24888 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24891 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24910 >+/* 24895 */ MCD_OPC_CheckPredicate, 0, 154, 61, // Skip to: 40669 >+/* 24899 */ MCD_OPC_CheckField, 19, 1, 1, 148, 61, // Skip to: 40669 >+/* 24905 */ MCD_OPC_Decode, 131, 12, 156, 1, // Opcode: SQRSHRNv8i8_shift >+/* 24910 */ MCD_OPC_FilterValue, 1, 139, 61, // Skip to: 40669 >+/* 24914 */ MCD_OPC_CheckPredicate, 0, 135, 61, // Skip to: 40669 >+/* 24918 */ MCD_OPC_Decode, 128, 12, 158, 1, // Opcode: SQRSHRNv4i16_shift >+/* 24923 */ MCD_OPC_FilterValue, 1, 126, 61, // Skip to: 40669 >+/* 24927 */ MCD_OPC_CheckPredicate, 0, 122, 61, // Skip to: 40669 >+/* 24931 */ MCD_OPC_Decode, 255, 11, 160, 1, // Opcode: SQRSHRNv2i32_shift >+/* 24936 */ MCD_OPC_FilterValue, 15, 113, 61, // Skip to: 40669 >+/* 24940 */ MCD_OPC_CheckPredicate, 0, 109, 61, // Skip to: 40669 >+/* 24944 */ MCD_OPC_CheckField, 21, 1, 1, 103, 61, // Skip to: 40669 >+/* 24950 */ MCD_OPC_Decode, 248, 3, 148, 1, // Opcode: FCVTZSv2i32_shift >+/* 24955 */ MCD_OPC_FilterValue, 1, 128, 3, // Skip to: 25855 >+/* 24959 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 24962 */ MCD_OPC_FilterValue, 1, 233, 2, // Skip to: 25711 >+/* 24966 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 24969 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 25397 >+/* 24973 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 24976 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 25187 >+/* 24980 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 24983 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 25128 >+/* 24987 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 24990 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 25069 >+/* 24994 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 24997 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25010 >+/* 25001 */ MCD_OPC_CheckPredicate, 0, 48, 61, // Skip to: 40669 >+/* 25005 */ MCD_OPC_Decode, 239, 8, 145, 1, // Opcode: MVNIv2i32 >+/* 25010 */ MCD_OPC_FilterValue, 1, 39, 61, // Skip to: 40669 >+/* 25014 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25017 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25030 >+/* 25021 */ MCD_OPC_CheckPredicate, 0, 28, 61, // Skip to: 40669 >+/* 25025 */ MCD_OPC_Decode, 146, 18, 146, 1, // Opcode: USHRv8i8_shift >+/* 25030 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25043 >+/* 25034 */ MCD_OPC_CheckPredicate, 0, 15, 61, // Skip to: 40669 >+/* 25038 */ MCD_OPC_Decode, 242, 17, 146, 1, // Opcode: URSHRv8i8_shift >+/* 25043 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25056 >+/* 25047 */ MCD_OPC_CheckPredicate, 0, 2, 61, // Skip to: 40669 >+/* 25051 */ MCD_OPC_Decode, 234, 12, 150, 1, // Opcode: SRIv8i8_shift >+/* 25056 */ MCD_OPC_FilterValue, 3, 249, 60, // Skip to: 40669 >+/* 25060 */ MCD_OPC_CheckPredicate, 0, 245, 60, // Skip to: 40669 >+/* 25064 */ MCD_OPC_Decode, 151, 12, 151, 1, // Opcode: SQSHLUv8i8_shift >+/* 25069 */ MCD_OPC_FilterValue, 1, 236, 60, // Skip to: 40669 >+/* 25073 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25076 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25089 >+/* 25080 */ MCD_OPC_CheckPredicate, 0, 225, 60, // Skip to: 40669 >+/* 25084 */ MCD_OPC_Decode, 143, 18, 147, 1, // Opcode: USHRv4i16_shift >+/* 25089 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25102 >+/* 25093 */ MCD_OPC_CheckPredicate, 0, 212, 60, // Skip to: 40669 >+/* 25097 */ MCD_OPC_Decode, 239, 17, 147, 1, // Opcode: URSHRv4i16_shift >+/* 25102 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25115 >+/* 25106 */ MCD_OPC_CheckPredicate, 0, 199, 60, // Skip to: 40669 >+/* 25110 */ MCD_OPC_Decode, 231, 12, 152, 1, // Opcode: SRIv4i16_shift >+/* 25115 */ MCD_OPC_FilterValue, 3, 190, 60, // Skip to: 40669 >+/* 25119 */ MCD_OPC_CheckPredicate, 0, 186, 60, // Skip to: 40669 >+/* 25123 */ MCD_OPC_Decode, 148, 12, 153, 1, // Opcode: SQSHLUv4i16_shift >+/* 25128 */ MCD_OPC_FilterValue, 1, 177, 60, // Skip to: 40669 >+/* 25132 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25135 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25148 >+/* 25139 */ MCD_OPC_CheckPredicate, 0, 166, 60, // Skip to: 40669 >+/* 25143 */ MCD_OPC_Decode, 141, 18, 148, 1, // Opcode: USHRv2i32_shift >+/* 25148 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25161 >+/* 25152 */ MCD_OPC_CheckPredicate, 0, 153, 60, // Skip to: 40669 >+/* 25156 */ MCD_OPC_Decode, 237, 17, 148, 1, // Opcode: URSHRv2i32_shift >+/* 25161 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25174 >+/* 25165 */ MCD_OPC_CheckPredicate, 0, 140, 60, // Skip to: 40669 >+/* 25169 */ MCD_OPC_Decode, 229, 12, 154, 1, // Opcode: SRIv2i32_shift >+/* 25174 */ MCD_OPC_FilterValue, 3, 131, 60, // Skip to: 40669 >+/* 25178 */ MCD_OPC_CheckPredicate, 0, 127, 60, // Skip to: 40669 >+/* 25182 */ MCD_OPC_Decode, 146, 12, 155, 1, // Opcode: SQSHLUv2i32_shift >+/* 25187 */ MCD_OPC_FilterValue, 1, 118, 60, // Skip to: 40669 >+/* 25191 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25194 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 25338 >+/* 25198 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25201 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 25279 >+/* 25205 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 25208 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25220 >+/* 25212 */ MCD_OPC_CheckPredicate, 0, 93, 60, // Skip to: 40669 >+/* 25216 */ MCD_OPC_Decode, 113, 149, 1, // Opcode: BICv2i32 >+/* 25220 */ MCD_OPC_FilterValue, 1, 85, 60, // Skip to: 40669 >+/* 25224 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25227 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25240 >+/* 25231 */ MCD_OPC_CheckPredicate, 0, 74, 60, // Skip to: 40669 >+/* 25235 */ MCD_OPC_Decode, 165, 18, 150, 1, // Opcode: USRAv8i8_shift >+/* 25240 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25253 >+/* 25244 */ MCD_OPC_CheckPredicate, 0, 61, 60, // Skip to: 40669 >+/* 25248 */ MCD_OPC_Decode, 252, 17, 150, 1, // Opcode: URSRAv8i8_shift >+/* 25253 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25266 >+/* 25257 */ MCD_OPC_CheckPredicate, 0, 48, 60, // Skip to: 40669 >+/* 25261 */ MCD_OPC_Decode, 201, 10, 162, 1, // Opcode: SLIv8i8_shift >+/* 25266 */ MCD_OPC_FilterValue, 3, 39, 60, // Skip to: 40669 >+/* 25270 */ MCD_OPC_CheckPredicate, 0, 35, 60, // Skip to: 40669 >+/* 25274 */ MCD_OPC_Decode, 189, 17, 151, 1, // Opcode: UQSHLv8i8_shift >+/* 25279 */ MCD_OPC_FilterValue, 1, 26, 60, // Skip to: 40669 >+/* 25283 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25286 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25299 >+/* 25290 */ MCD_OPC_CheckPredicate, 0, 15, 60, // Skip to: 40669 >+/* 25294 */ MCD_OPC_Decode, 162, 18, 152, 1, // Opcode: USRAv4i16_shift >+/* 25299 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25312 >+/* 25303 */ MCD_OPC_CheckPredicate, 0, 2, 60, // Skip to: 40669 >+/* 25307 */ MCD_OPC_Decode, 249, 17, 152, 1, // Opcode: URSRAv4i16_shift >+/* 25312 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25325 >+/* 25316 */ MCD_OPC_CheckPredicate, 0, 245, 59, // Skip to: 40669 >+/* 25320 */ MCD_OPC_Decode, 198, 10, 163, 1, // Opcode: SLIv4i16_shift >+/* 25325 */ MCD_OPC_FilterValue, 3, 236, 59, // Skip to: 40669 >+/* 25329 */ MCD_OPC_CheckPredicate, 0, 232, 59, // Skip to: 40669 >+/* 25333 */ MCD_OPC_Decode, 183, 17, 153, 1, // Opcode: UQSHLv4i16_shift >+/* 25338 */ MCD_OPC_FilterValue, 1, 223, 59, // Skip to: 40669 >+/* 25342 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25345 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25358 >+/* 25349 */ MCD_OPC_CheckPredicate, 0, 212, 59, // Skip to: 40669 >+/* 25353 */ MCD_OPC_Decode, 160, 18, 154, 1, // Opcode: USRAv2i32_shift >+/* 25358 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25371 >+/* 25362 */ MCD_OPC_CheckPredicate, 0, 199, 59, // Skip to: 40669 >+/* 25366 */ MCD_OPC_Decode, 247, 17, 154, 1, // Opcode: URSRAv2i32_shift >+/* 25371 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25384 >+/* 25375 */ MCD_OPC_CheckPredicate, 0, 186, 59, // Skip to: 40669 >+/* 25379 */ MCD_OPC_Decode, 196, 10, 164, 1, // Opcode: SLIv2i32_shift >+/* 25384 */ MCD_OPC_FilterValue, 3, 177, 59, // Skip to: 40669 >+/* 25388 */ MCD_OPC_CheckPredicate, 0, 173, 59, // Skip to: 40669 >+/* 25392 */ MCD_OPC_Decode, 179, 17, 155, 1, // Opcode: UQSHLv2i32_shift >+/* 25397 */ MCD_OPC_FilterValue, 1, 164, 59, // Skip to: 40669 >+/* 25401 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 25404 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 25634 >+/* 25408 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 25411 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 25544 >+/* 25415 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25418 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25511 >+/* 25422 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25425 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25478 >+/* 25429 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 25432 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25445 >+/* 25436 */ MCD_OPC_CheckPredicate, 0, 125, 59, // Skip to: 40669 >+/* 25440 */ MCD_OPC_Decode, 241, 8, 145, 1, // Opcode: MVNIv4i16 >+/* 25445 */ MCD_OPC_FilterValue, 1, 116, 59, // Skip to: 40669 >+/* 25449 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 25452 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25465 >+/* 25456 */ MCD_OPC_CheckPredicate, 0, 105, 59, // Skip to: 40669 >+/* 25460 */ MCD_OPC_Decode, 191, 12, 156, 1, // Opcode: SQSHRUNv8i8_shift >+/* 25465 */ MCD_OPC_FilterValue, 1, 96, 59, // Skip to: 40669 >+/* 25469 */ MCD_OPC_CheckPredicate, 0, 92, 59, // Skip to: 40669 >+/* 25473 */ MCD_OPC_Decode, 130, 18, 157, 1, // Opcode: USHLLv8i8_shift >+/* 25478 */ MCD_OPC_FilterValue, 1, 83, 59, // Skip to: 40669 >+/* 25482 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 25485 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25498 >+/* 25489 */ MCD_OPC_CheckPredicate, 0, 72, 59, // Skip to: 40669 >+/* 25493 */ MCD_OPC_Decode, 188, 12, 158, 1, // Opcode: SQSHRUNv4i16_shift >+/* 25498 */ MCD_OPC_FilterValue, 1, 63, 59, // Skip to: 40669 >+/* 25502 */ MCD_OPC_CheckPredicate, 0, 59, 59, // Skip to: 40669 >+/* 25506 */ MCD_OPC_Decode, 255, 17, 159, 1, // Opcode: USHLLv4i16_shift >+/* 25511 */ MCD_OPC_FilterValue, 1, 50, 59, // Skip to: 40669 >+/* 25515 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 25518 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25531 >+/* 25522 */ MCD_OPC_CheckPredicate, 0, 39, 59, // Skip to: 40669 >+/* 25526 */ MCD_OPC_Decode, 187, 12, 160, 1, // Opcode: SQSHRUNv2i32_shift >+/* 25531 */ MCD_OPC_FilterValue, 1, 30, 59, // Skip to: 40669 >+/* 25535 */ MCD_OPC_CheckPredicate, 0, 26, 59, // Skip to: 40669 >+/* 25539 */ MCD_OPC_Decode, 254, 17, 161, 1, // Opcode: USHLLv2i32_shift >+/* 25544 */ MCD_OPC_FilterValue, 1, 17, 59, // Skip to: 40669 >+/* 25548 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25551 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 25615 >+/* 25555 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25558 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 25596 >+/* 25562 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 25565 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25577 >+/* 25569 */ MCD_OPC_CheckPredicate, 0, 248, 58, // Skip to: 40669 >+/* 25573 */ MCD_OPC_Decode, 114, 149, 1, // Opcode: BICv4i16 >+/* 25577 */ MCD_OPC_FilterValue, 1, 240, 58, // Skip to: 40669 >+/* 25581 */ MCD_OPC_CheckPredicate, 0, 236, 58, // Skip to: 40669 >+/* 25585 */ MCD_OPC_CheckField, 13, 1, 0, 230, 58, // Skip to: 40669 >+/* 25591 */ MCD_OPC_Decode, 198, 17, 156, 1, // Opcode: UQSHRNv8i8_shift >+/* 25596 */ MCD_OPC_FilterValue, 1, 221, 58, // Skip to: 40669 >+/* 25600 */ MCD_OPC_CheckPredicate, 0, 217, 58, // Skip to: 40669 >+/* 25604 */ MCD_OPC_CheckField, 13, 1, 0, 211, 58, // Skip to: 40669 >+/* 25610 */ MCD_OPC_Decode, 195, 17, 158, 1, // Opcode: UQSHRNv4i16_shift >+/* 25615 */ MCD_OPC_FilterValue, 1, 202, 58, // Skip to: 40669 >+/* 25619 */ MCD_OPC_CheckPredicate, 0, 198, 58, // Skip to: 40669 >+/* 25623 */ MCD_OPC_CheckField, 13, 1, 0, 192, 58, // Skip to: 40669 >+/* 25629 */ MCD_OPC_Decode, 194, 17, 160, 1, // Opcode: UQSHRNv2i32_shift >+/* 25634 */ MCD_OPC_FilterValue, 1, 183, 58, // Skip to: 40669 >+/* 25638 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 25641 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25660 >+/* 25645 */ MCD_OPC_CheckPredicate, 0, 172, 58, // Skip to: 40669 >+/* 25649 */ MCD_OPC_CheckField, 19, 3, 0, 166, 58, // Skip to: 40669 >+/* 25655 */ MCD_OPC_Decode, 240, 8, 145, 1, // Opcode: MVNIv2s_msl >+/* 25660 */ MCD_OPC_FilterValue, 1, 157, 58, // Skip to: 40669 >+/* 25664 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25667 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 25692 >+/* 25671 */ MCD_OPC_CheckPredicate, 0, 146, 58, // Skip to: 40669 >+/* 25675 */ MCD_OPC_CheckField, 19, 2, 0, 140, 58, // Skip to: 40669 >+/* 25681 */ MCD_OPC_CheckField, 12, 1, 0, 134, 58, // Skip to: 40669 >+/* 25687 */ MCD_OPC_Decode, 200, 8, 145, 1, // Opcode: MOVID >+/* 25692 */ MCD_OPC_FilterValue, 1, 125, 58, // Skip to: 40669 >+/* 25696 */ MCD_OPC_CheckPredicate, 0, 121, 58, // Skip to: 40669 >+/* 25700 */ MCD_OPC_CheckField, 12, 1, 0, 115, 58, // Skip to: 40669 >+/* 25706 */ MCD_OPC_Decode, 174, 16, 148, 1, // Opcode: UCVTFv2i32_shift >+/* 25711 */ MCD_OPC_FilterValue, 3, 106, 58, // Skip to: 40669 >+/* 25715 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 25718 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 25777 >+/* 25722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25725 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25764 >+/* 25729 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25732 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25751 >+/* 25736 */ MCD_OPC_CheckPredicate, 0, 81, 58, // Skip to: 40669 >+/* 25740 */ MCD_OPC_CheckField, 19, 1, 1, 75, 58, // Skip to: 40669 >+/* 25746 */ MCD_OPC_Decode, 140, 12, 156, 1, // Opcode: SQRSHRUNv8i8_shift >+/* 25751 */ MCD_OPC_FilterValue, 1, 66, 58, // Skip to: 40669 >+/* 25755 */ MCD_OPC_CheckPredicate, 0, 62, 58, // Skip to: 40669 >+/* 25759 */ MCD_OPC_Decode, 137, 12, 158, 1, // Opcode: SQRSHRUNv4i16_shift >+/* 25764 */ MCD_OPC_FilterValue, 1, 53, 58, // Skip to: 40669 >+/* 25768 */ MCD_OPC_CheckPredicate, 0, 49, 58, // Skip to: 40669 >+/* 25772 */ MCD_OPC_Decode, 136, 12, 160, 1, // Opcode: SQRSHRUNv2i32_shift >+/* 25777 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 25836 >+/* 25781 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25784 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25823 >+/* 25788 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25791 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25810 >+/* 25795 */ MCD_OPC_CheckPredicate, 0, 22, 58, // Skip to: 40669 >+/* 25799 */ MCD_OPC_CheckField, 19, 1, 1, 16, 58, // Skip to: 40669 >+/* 25805 */ MCD_OPC_Decode, 167, 17, 156, 1, // Opcode: UQRSHRNv8i8_shift >+/* 25810 */ MCD_OPC_FilterValue, 1, 7, 58, // Skip to: 40669 >+/* 25814 */ MCD_OPC_CheckPredicate, 0, 3, 58, // Skip to: 40669 >+/* 25818 */ MCD_OPC_Decode, 164, 17, 158, 1, // Opcode: UQRSHRNv4i16_shift >+/* 25823 */ MCD_OPC_FilterValue, 1, 250, 57, // Skip to: 40669 >+/* 25827 */ MCD_OPC_CheckPredicate, 0, 246, 57, // Skip to: 40669 >+/* 25831 */ MCD_OPC_Decode, 163, 17, 160, 1, // Opcode: UQRSHRNv2i32_shift >+/* 25836 */ MCD_OPC_FilterValue, 15, 237, 57, // Skip to: 40669 >+/* 25840 */ MCD_OPC_CheckPredicate, 0, 233, 57, // Skip to: 40669 >+/* 25844 */ MCD_OPC_CheckField, 21, 1, 1, 227, 57, // Skip to: 40669 >+/* 25850 */ MCD_OPC_Decode, 149, 4, 148, 1, // Opcode: FCVTZUv2i32_shift >+/* 25855 */ MCD_OPC_FilterValue, 2, 66, 3, // Skip to: 26693 >+/* 25859 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 25862 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 26549 >+/* 25866 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 25869 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 26220 >+/* 25873 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 25876 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26009 >+/* 25880 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 25883 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25976 >+/* 25887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 25890 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25943 >+/* 25894 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 25897 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25910 >+/* 25901 */ MCD_OPC_CheckPredicate, 0, 172, 57, // Skip to: 40669 >+/* 25905 */ MCD_OPC_Decode, 206, 8, 145, 1, // Opcode: MOVIv4i32 >+/* 25910 */ MCD_OPC_FilterValue, 1, 163, 57, // Skip to: 40669 >+/* 25914 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25917 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25930 >+/* 25921 */ MCD_OPC_CheckPredicate, 0, 152, 57, // Skip to: 40669 >+/* 25925 */ MCD_OPC_Decode, 146, 13, 165, 1, // Opcode: SSHRv16i8_shift >+/* 25930 */ MCD_OPC_FilterValue, 1, 143, 57, // Skip to: 40669 >+/* 25934 */ MCD_OPC_CheckPredicate, 0, 139, 57, // Skip to: 40669 >+/* 25938 */ MCD_OPC_Decode, 244, 12, 165, 1, // Opcode: SRSHRv16i8_shift >+/* 25943 */ MCD_OPC_FilterValue, 1, 130, 57, // Skip to: 40669 >+/* 25947 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25950 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25963 >+/* 25954 */ MCD_OPC_CheckPredicate, 0, 119, 57, // Skip to: 40669 >+/* 25958 */ MCD_OPC_Decode, 151, 13, 166, 1, // Opcode: SSHRv8i16_shift >+/* 25963 */ MCD_OPC_FilterValue, 1, 110, 57, // Skip to: 40669 >+/* 25967 */ MCD_OPC_CheckPredicate, 0, 106, 57, // Skip to: 40669 >+/* 25971 */ MCD_OPC_Decode, 249, 12, 166, 1, // Opcode: SRSHRv8i16_shift >+/* 25976 */ MCD_OPC_FilterValue, 1, 97, 57, // Skip to: 40669 >+/* 25980 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 25983 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25996 >+/* 25987 */ MCD_OPC_CheckPredicate, 0, 86, 57, // Skip to: 40669 >+/* 25991 */ MCD_OPC_Decode, 150, 13, 167, 1, // Opcode: SSHRv4i32_shift >+/* 25996 */ MCD_OPC_FilterValue, 1, 77, 57, // Skip to: 40669 >+/* 26000 */ MCD_OPC_CheckPredicate, 0, 73, 57, // Skip to: 40669 >+/* 26004 */ MCD_OPC_Decode, 248, 12, 167, 1, // Opcode: SRSHRv4i32_shift >+/* 26009 */ MCD_OPC_FilterValue, 1, 64, 57, // Skip to: 40669 >+/* 26013 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26016 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26161 >+/* 26020 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26023 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26102 >+/* 26027 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 26030 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26043 >+/* 26034 */ MCD_OPC_CheckPredicate, 0, 39, 57, // Skip to: 40669 >+/* 26038 */ MCD_OPC_Decode, 142, 9, 149, 1, // Opcode: ORRv4i32 >+/* 26043 */ MCD_OPC_FilterValue, 1, 30, 57, // Skip to: 40669 >+/* 26047 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26050 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26063 >+/* 26054 */ MCD_OPC_CheckPredicate, 0, 19, 57, // Skip to: 40669 >+/* 26058 */ MCD_OPC_Decode, 154, 13, 168, 1, // Opcode: SSRAv16i8_shift >+/* 26063 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26076 >+/* 26067 */ MCD_OPC_CheckPredicate, 0, 6, 57, // Skip to: 40669 >+/* 26071 */ MCD_OPC_Decode, 252, 12, 168, 1, // Opcode: SRSRAv16i8_shift >+/* 26076 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26089 >+/* 26080 */ MCD_OPC_CheckPredicate, 0, 249, 56, // Skip to: 40669 >+/* 26084 */ MCD_OPC_Decode, 175, 10, 169, 1, // Opcode: SHLv16i8_shift >+/* 26089 */ MCD_OPC_FilterValue, 3, 240, 56, // Skip to: 40669 >+/* 26093 */ MCD_OPC_CheckPredicate, 0, 236, 56, // Skip to: 40669 >+/* 26097 */ MCD_OPC_Decode, 157, 12, 169, 1, // Opcode: SQSHLv16i8_shift >+/* 26102 */ MCD_OPC_FilterValue, 1, 227, 56, // Skip to: 40669 >+/* 26106 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26109 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26122 >+/* 26113 */ MCD_OPC_CheckPredicate, 0, 216, 56, // Skip to: 40669 >+/* 26117 */ MCD_OPC_Decode, 159, 13, 170, 1, // Opcode: SSRAv8i16_shift >+/* 26122 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26135 >+/* 26126 */ MCD_OPC_CheckPredicate, 0, 203, 56, // Skip to: 40669 >+/* 26130 */ MCD_OPC_Decode, 129, 13, 170, 1, // Opcode: SRSRAv8i16_shift >+/* 26135 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26148 >+/* 26139 */ MCD_OPC_CheckPredicate, 0, 190, 56, // Skip to: 40669 >+/* 26143 */ MCD_OPC_Decode, 180, 10, 171, 1, // Opcode: SHLv8i16_shift >+/* 26148 */ MCD_OPC_FilterValue, 3, 181, 56, // Skip to: 40669 >+/* 26152 */ MCD_OPC_CheckPredicate, 0, 177, 56, // Skip to: 40669 >+/* 26156 */ MCD_OPC_Decode, 171, 12, 171, 1, // Opcode: SQSHLv8i16_shift >+/* 26161 */ MCD_OPC_FilterValue, 1, 168, 56, // Skip to: 40669 >+/* 26165 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26168 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26181 >+/* 26172 */ MCD_OPC_CheckPredicate, 0, 157, 56, // Skip to: 40669 >+/* 26176 */ MCD_OPC_Decode, 158, 13, 172, 1, // Opcode: SSRAv4i32_shift >+/* 26181 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26194 >+/* 26185 */ MCD_OPC_CheckPredicate, 0, 144, 56, // Skip to: 40669 >+/* 26189 */ MCD_OPC_Decode, 128, 13, 172, 1, // Opcode: SRSRAv4i32_shift >+/* 26194 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26207 >+/* 26198 */ MCD_OPC_CheckPredicate, 0, 131, 56, // Skip to: 40669 >+/* 26202 */ MCD_OPC_Decode, 179, 10, 173, 1, // Opcode: SHLv4i32_shift >+/* 26207 */ MCD_OPC_FilterValue, 3, 122, 56, // Skip to: 40669 >+/* 26211 */ MCD_OPC_CheckPredicate, 0, 118, 56, // Skip to: 40669 >+/* 26215 */ MCD_OPC_Decode, 169, 12, 173, 1, // Opcode: SQSHLv4i32_shift >+/* 26220 */ MCD_OPC_FilterValue, 1, 109, 56, // Skip to: 40669 >+/* 26224 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 26227 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 26458 >+/* 26231 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 26234 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26367 >+/* 26238 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26241 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 26334 >+/* 26245 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26248 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 26301 >+/* 26252 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 26255 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26268 >+/* 26259 */ MCD_OPC_CheckPredicate, 0, 70, 56, // Skip to: 40669 >+/* 26263 */ MCD_OPC_Decode, 209, 8, 145, 1, // Opcode: MOVIv8i16 >+/* 26268 */ MCD_OPC_FilterValue, 1, 61, 56, // Skip to: 40669 >+/* 26272 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 26275 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26288 >+/* 26279 */ MCD_OPC_CheckPredicate, 0, 50, 56, // Skip to: 40669 >+/* 26283 */ MCD_OPC_Decode, 182, 10, 174, 1, // Opcode: SHRNv16i8_shift >+/* 26288 */ MCD_OPC_FilterValue, 1, 41, 56, // Skip to: 40669 >+/* 26292 */ MCD_OPC_CheckPredicate, 0, 37, 56, // Skip to: 40669 >+/* 26296 */ MCD_OPC_Decode, 131, 13, 169, 1, // Opcode: SSHLLv16i8_shift >+/* 26301 */ MCD_OPC_FilterValue, 1, 28, 56, // Skip to: 40669 >+/* 26305 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 26308 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26321 >+/* 26312 */ MCD_OPC_CheckPredicate, 0, 17, 56, // Skip to: 40669 >+/* 26316 */ MCD_OPC_Decode, 186, 10, 175, 1, // Opcode: SHRNv8i16_shift >+/* 26321 */ MCD_OPC_FilterValue, 1, 8, 56, // Skip to: 40669 >+/* 26325 */ MCD_OPC_CheckPredicate, 0, 4, 56, // Skip to: 40669 >+/* 26329 */ MCD_OPC_Decode, 135, 13, 171, 1, // Opcode: SSHLLv8i16_shift >+/* 26334 */ MCD_OPC_FilterValue, 1, 251, 55, // Skip to: 40669 >+/* 26338 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 26341 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26354 >+/* 26345 */ MCD_OPC_CheckPredicate, 0, 240, 55, // Skip to: 40669 >+/* 26349 */ MCD_OPC_Decode, 185, 10, 176, 1, // Opcode: SHRNv4i32_shift >+/* 26354 */ MCD_OPC_FilterValue, 1, 231, 55, // Skip to: 40669 >+/* 26358 */ MCD_OPC_CheckPredicate, 0, 227, 55, // Skip to: 40669 >+/* 26362 */ MCD_OPC_Decode, 134, 13, 173, 1, // Opcode: SSHLLv4i32_shift >+/* 26367 */ MCD_OPC_FilterValue, 1, 218, 55, // Skip to: 40669 >+/* 26371 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26374 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 26439 >+/* 26378 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26381 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26420 >+/* 26385 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 26388 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26401 >+/* 26392 */ MCD_OPC_CheckPredicate, 0, 193, 55, // Skip to: 40669 >+/* 26396 */ MCD_OPC_Decode, 143, 9, 149, 1, // Opcode: ORRv8i16 >+/* 26401 */ MCD_OPC_FilterValue, 1, 184, 55, // Skip to: 40669 >+/* 26405 */ MCD_OPC_CheckPredicate, 0, 180, 55, // Skip to: 40669 >+/* 26409 */ MCD_OPC_CheckField, 13, 1, 0, 174, 55, // Skip to: 40669 >+/* 26415 */ MCD_OPC_Decode, 177, 12, 174, 1, // Opcode: SQSHRNv16i8_shift >+/* 26420 */ MCD_OPC_FilterValue, 1, 165, 55, // Skip to: 40669 >+/* 26424 */ MCD_OPC_CheckPredicate, 0, 161, 55, // Skip to: 40669 >+/* 26428 */ MCD_OPC_CheckField, 13, 1, 0, 155, 55, // Skip to: 40669 >+/* 26434 */ MCD_OPC_Decode, 181, 12, 175, 1, // Opcode: SQSHRNv8i16_shift >+/* 26439 */ MCD_OPC_FilterValue, 1, 146, 55, // Skip to: 40669 >+/* 26443 */ MCD_OPC_CheckPredicate, 0, 142, 55, // Skip to: 40669 >+/* 26447 */ MCD_OPC_CheckField, 13, 1, 0, 136, 55, // Skip to: 40669 >+/* 26453 */ MCD_OPC_Decode, 180, 12, 176, 1, // Opcode: SQSHRNv4i32_shift >+/* 26458 */ MCD_OPC_FilterValue, 1, 127, 55, // Skip to: 40669 >+/* 26462 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 26465 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26484 >+/* 26469 */ MCD_OPC_CheckPredicate, 0, 116, 55, // Skip to: 40669 >+/* 26473 */ MCD_OPC_CheckField, 19, 3, 0, 110, 55, // Skip to: 40669 >+/* 26479 */ MCD_OPC_Decode, 207, 8, 145, 1, // Opcode: MOVIv4s_msl >+/* 26484 */ MCD_OPC_FilterValue, 1, 101, 55, // Skip to: 40669 >+/* 26488 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 26491 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26530 >+/* 26495 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26498 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26517 >+/* 26502 */ MCD_OPC_CheckPredicate, 0, 83, 55, // Skip to: 40669 >+/* 26506 */ MCD_OPC_CheckField, 19, 2, 0, 77, 55, // Skip to: 40669 >+/* 26512 */ MCD_OPC_Decode, 201, 8, 145, 1, // Opcode: MOVIv16b_ns >+/* 26517 */ MCD_OPC_FilterValue, 1, 68, 55, // Skip to: 40669 >+/* 26521 */ MCD_OPC_CheckPredicate, 0, 64, 55, // Skip to: 40669 >+/* 26525 */ MCD_OPC_Decode, 147, 10, 167, 1, // Opcode: SCVTFv4i32_shift >+/* 26530 */ MCD_OPC_FilterValue, 1, 55, 55, // Skip to: 40669 >+/* 26534 */ MCD_OPC_CheckPredicate, 0, 51, 55, // Skip to: 40669 >+/* 26538 */ MCD_OPC_CheckField, 19, 3, 0, 45, 55, // Skip to: 40669 >+/* 26544 */ MCD_OPC_Decode, 232, 4, 145, 1, // Opcode: FMOVv4f32_ns >+/* 26549 */ MCD_OPC_FilterValue, 3, 36, 55, // Skip to: 40669 >+/* 26553 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 26556 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 26615 >+/* 26560 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26563 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26602 >+/* 26567 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26570 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26589 >+/* 26574 */ MCD_OPC_CheckPredicate, 0, 11, 55, // Skip to: 40669 >+/* 26578 */ MCD_OPC_CheckField, 19, 1, 1, 5, 55, // Skip to: 40669 >+/* 26584 */ MCD_OPC_Decode, 187, 9, 174, 1, // Opcode: RSHRNv16i8_shift >+/* 26589 */ MCD_OPC_FilterValue, 1, 252, 54, // Skip to: 40669 >+/* 26593 */ MCD_OPC_CheckPredicate, 0, 248, 54, // Skip to: 40669 >+/* 26597 */ MCD_OPC_Decode, 191, 9, 175, 1, // Opcode: RSHRNv8i16_shift >+/* 26602 */ MCD_OPC_FilterValue, 1, 239, 54, // Skip to: 40669 >+/* 26606 */ MCD_OPC_CheckPredicate, 0, 235, 54, // Skip to: 40669 >+/* 26610 */ MCD_OPC_Decode, 190, 9, 176, 1, // Opcode: RSHRNv4i32_shift >+/* 26615 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 26674 >+/* 26619 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26622 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26661 >+/* 26626 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26629 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26648 >+/* 26633 */ MCD_OPC_CheckPredicate, 0, 208, 54, // Skip to: 40669 >+/* 26637 */ MCD_OPC_CheckField, 19, 1, 1, 202, 54, // Skip to: 40669 >+/* 26643 */ MCD_OPC_Decode, 254, 11, 174, 1, // Opcode: SQRSHRNv16i8_shift >+/* 26648 */ MCD_OPC_FilterValue, 1, 193, 54, // Skip to: 40669 >+/* 26652 */ MCD_OPC_CheckPredicate, 0, 189, 54, // Skip to: 40669 >+/* 26656 */ MCD_OPC_Decode, 130, 12, 175, 1, // Opcode: SQRSHRNv8i16_shift >+/* 26661 */ MCD_OPC_FilterValue, 1, 180, 54, // Skip to: 40669 >+/* 26665 */ MCD_OPC_CheckPredicate, 0, 176, 54, // Skip to: 40669 >+/* 26669 */ MCD_OPC_Decode, 129, 12, 176, 1, // Opcode: SQRSHRNv4i32_shift >+/* 26674 */ MCD_OPC_FilterValue, 15, 167, 54, // Skip to: 40669 >+/* 26678 */ MCD_OPC_CheckPredicate, 0, 163, 54, // Skip to: 40669 >+/* 26682 */ MCD_OPC_CheckField, 21, 1, 1, 157, 54, // Skip to: 40669 >+/* 26688 */ MCD_OPC_Decode, 251, 3, 167, 1, // Opcode: FCVTZSv4i32_shift >+/* 26693 */ MCD_OPC_FilterValue, 3, 148, 54, // Skip to: 40669 >+/* 26697 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 26700 */ MCD_OPC_FilterValue, 1, 247, 2, // Skip to: 27463 >+/* 26704 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 26707 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 27135 >+/* 26711 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 26714 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 26925 >+/* 26718 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26721 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26866 >+/* 26725 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26728 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26807 >+/* 26732 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 26735 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26748 >+/* 26739 */ MCD_OPC_CheckPredicate, 0, 102, 54, // Skip to: 40669 >+/* 26743 */ MCD_OPC_Decode, 242, 8, 145, 1, // Opcode: MVNIv4i32 >+/* 26748 */ MCD_OPC_FilterValue, 1, 93, 54, // Skip to: 40669 >+/* 26752 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26755 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26768 >+/* 26759 */ MCD_OPC_CheckPredicate, 0, 82, 54, // Skip to: 40669 >+/* 26763 */ MCD_OPC_Decode, 140, 18, 165, 1, // Opcode: USHRv16i8_shift >+/* 26768 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26781 >+/* 26772 */ MCD_OPC_CheckPredicate, 0, 69, 54, // Skip to: 40669 >+/* 26776 */ MCD_OPC_Decode, 236, 17, 165, 1, // Opcode: URSHRv16i8_shift >+/* 26781 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26794 >+/* 26785 */ MCD_OPC_CheckPredicate, 0, 56, 54, // Skip to: 40669 >+/* 26789 */ MCD_OPC_Decode, 228, 12, 168, 1, // Opcode: SRIv16i8_shift >+/* 26794 */ MCD_OPC_FilterValue, 3, 47, 54, // Skip to: 40669 >+/* 26798 */ MCD_OPC_CheckPredicate, 0, 43, 54, // Skip to: 40669 >+/* 26802 */ MCD_OPC_Decode, 145, 12, 169, 1, // Opcode: SQSHLUv16i8_shift >+/* 26807 */ MCD_OPC_FilterValue, 1, 34, 54, // Skip to: 40669 >+/* 26811 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26814 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26827 >+/* 26818 */ MCD_OPC_CheckPredicate, 0, 23, 54, // Skip to: 40669 >+/* 26822 */ MCD_OPC_Decode, 145, 18, 166, 1, // Opcode: USHRv8i16_shift >+/* 26827 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26840 >+/* 26831 */ MCD_OPC_CheckPredicate, 0, 10, 54, // Skip to: 40669 >+/* 26835 */ MCD_OPC_Decode, 241, 17, 166, 1, // Opcode: URSHRv8i16_shift >+/* 26840 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26853 >+/* 26844 */ MCD_OPC_CheckPredicate, 0, 253, 53, // Skip to: 40669 >+/* 26848 */ MCD_OPC_Decode, 233, 12, 170, 1, // Opcode: SRIv8i16_shift >+/* 26853 */ MCD_OPC_FilterValue, 3, 244, 53, // Skip to: 40669 >+/* 26857 */ MCD_OPC_CheckPredicate, 0, 240, 53, // Skip to: 40669 >+/* 26861 */ MCD_OPC_Decode, 150, 12, 171, 1, // Opcode: SQSHLUv8i16_shift >+/* 26866 */ MCD_OPC_FilterValue, 1, 231, 53, // Skip to: 40669 >+/* 26870 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26873 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26886 >+/* 26877 */ MCD_OPC_CheckPredicate, 0, 220, 53, // Skip to: 40669 >+/* 26881 */ MCD_OPC_Decode, 144, 18, 167, 1, // Opcode: USHRv4i32_shift >+/* 26886 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26899 >+/* 26890 */ MCD_OPC_CheckPredicate, 0, 207, 53, // Skip to: 40669 >+/* 26894 */ MCD_OPC_Decode, 240, 17, 167, 1, // Opcode: URSHRv4i32_shift >+/* 26899 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26912 >+/* 26903 */ MCD_OPC_CheckPredicate, 0, 194, 53, // Skip to: 40669 >+/* 26907 */ MCD_OPC_Decode, 232, 12, 172, 1, // Opcode: SRIv4i32_shift >+/* 26912 */ MCD_OPC_FilterValue, 3, 185, 53, // Skip to: 40669 >+/* 26916 */ MCD_OPC_CheckPredicate, 0, 181, 53, // Skip to: 40669 >+/* 26920 */ MCD_OPC_Decode, 149, 12, 173, 1, // Opcode: SQSHLUv4i32_shift >+/* 26925 */ MCD_OPC_FilterValue, 1, 172, 53, // Skip to: 40669 >+/* 26929 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 26932 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 27076 >+/* 26936 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 26939 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 27017 >+/* 26943 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 26946 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 26958 >+/* 26950 */ MCD_OPC_CheckPredicate, 0, 147, 53, // Skip to: 40669 >+/* 26954 */ MCD_OPC_Decode, 115, 149, 1, // Opcode: BICv4i32 >+/* 26958 */ MCD_OPC_FilterValue, 1, 139, 53, // Skip to: 40669 >+/* 26962 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 26965 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26978 >+/* 26969 */ MCD_OPC_CheckPredicate, 0, 128, 53, // Skip to: 40669 >+/* 26973 */ MCD_OPC_Decode, 159, 18, 168, 1, // Opcode: USRAv16i8_shift >+/* 26978 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26991 >+/* 26982 */ MCD_OPC_CheckPredicate, 0, 115, 53, // Skip to: 40669 >+/* 26986 */ MCD_OPC_Decode, 246, 17, 168, 1, // Opcode: URSRAv16i8_shift >+/* 26991 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27004 >+/* 26995 */ MCD_OPC_CheckPredicate, 0, 102, 53, // Skip to: 40669 >+/* 26999 */ MCD_OPC_Decode, 195, 10, 177, 1, // Opcode: SLIv16i8_shift >+/* 27004 */ MCD_OPC_FilterValue, 3, 93, 53, // Skip to: 40669 >+/* 27008 */ MCD_OPC_CheckPredicate, 0, 89, 53, // Skip to: 40669 >+/* 27012 */ MCD_OPC_Decode, 173, 17, 169, 1, // Opcode: UQSHLv16i8_shift >+/* 27017 */ MCD_OPC_FilterValue, 1, 80, 53, // Skip to: 40669 >+/* 27021 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 27024 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27037 >+/* 27028 */ MCD_OPC_CheckPredicate, 0, 69, 53, // Skip to: 40669 >+/* 27032 */ MCD_OPC_Decode, 164, 18, 170, 1, // Opcode: USRAv8i16_shift >+/* 27037 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27050 >+/* 27041 */ MCD_OPC_CheckPredicate, 0, 56, 53, // Skip to: 40669 >+/* 27045 */ MCD_OPC_Decode, 251, 17, 170, 1, // Opcode: URSRAv8i16_shift >+/* 27050 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27063 >+/* 27054 */ MCD_OPC_CheckPredicate, 0, 43, 53, // Skip to: 40669 >+/* 27058 */ MCD_OPC_Decode, 200, 10, 178, 1, // Opcode: SLIv8i16_shift >+/* 27063 */ MCD_OPC_FilterValue, 3, 34, 53, // Skip to: 40669 >+/* 27067 */ MCD_OPC_CheckPredicate, 0, 30, 53, // Skip to: 40669 >+/* 27071 */ MCD_OPC_Decode, 187, 17, 171, 1, // Opcode: UQSHLv8i16_shift >+/* 27076 */ MCD_OPC_FilterValue, 1, 21, 53, // Skip to: 40669 >+/* 27080 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 27083 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27096 >+/* 27087 */ MCD_OPC_CheckPredicate, 0, 10, 53, // Skip to: 40669 >+/* 27091 */ MCD_OPC_Decode, 163, 18, 172, 1, // Opcode: USRAv4i32_shift >+/* 27096 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27109 >+/* 27100 */ MCD_OPC_CheckPredicate, 0, 253, 52, // Skip to: 40669 >+/* 27104 */ MCD_OPC_Decode, 250, 17, 172, 1, // Opcode: URSRAv4i32_shift >+/* 27109 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27122 >+/* 27113 */ MCD_OPC_CheckPredicate, 0, 240, 52, // Skip to: 40669 >+/* 27117 */ MCD_OPC_Decode, 199, 10, 179, 1, // Opcode: SLIv4i32_shift >+/* 27122 */ MCD_OPC_FilterValue, 3, 231, 52, // Skip to: 40669 >+/* 27126 */ MCD_OPC_CheckPredicate, 0, 227, 52, // Skip to: 40669 >+/* 27130 */ MCD_OPC_Decode, 185, 17, 173, 1, // Opcode: UQSHLv4i32_shift >+/* 27135 */ MCD_OPC_FilterValue, 1, 218, 52, // Skip to: 40669 >+/* 27139 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 27142 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 27372 >+/* 27146 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 27149 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 27282 >+/* 27153 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 27156 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 27249 >+/* 27160 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 27163 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 27216 >+/* 27167 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 27170 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27183 >+/* 27174 */ MCD_OPC_CheckPredicate, 0, 179, 52, // Skip to: 40669 >+/* 27178 */ MCD_OPC_Decode, 244, 8, 145, 1, // Opcode: MVNIv8i16 >+/* 27183 */ MCD_OPC_FilterValue, 1, 170, 52, // Skip to: 40669 >+/* 27187 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 27190 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27203 >+/* 27194 */ MCD_OPC_CheckPredicate, 0, 159, 52, // Skip to: 40669 >+/* 27198 */ MCD_OPC_Decode, 186, 12, 174, 1, // Opcode: SQSHRUNv16i8_shift >+/* 27203 */ MCD_OPC_FilterValue, 1, 150, 52, // Skip to: 40669 >+/* 27207 */ MCD_OPC_CheckPredicate, 0, 146, 52, // Skip to: 40669 >+/* 27211 */ MCD_OPC_Decode, 253, 17, 169, 1, // Opcode: USHLLv16i8_shift >+/* 27216 */ MCD_OPC_FilterValue, 1, 137, 52, // Skip to: 40669 >+/* 27220 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 27223 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27236 >+/* 27227 */ MCD_OPC_CheckPredicate, 0, 126, 52, // Skip to: 40669 >+/* 27231 */ MCD_OPC_Decode, 190, 12, 175, 1, // Opcode: SQSHRUNv8i16_shift >+/* 27236 */ MCD_OPC_FilterValue, 1, 117, 52, // Skip to: 40669 >+/* 27240 */ MCD_OPC_CheckPredicate, 0, 113, 52, // Skip to: 40669 >+/* 27244 */ MCD_OPC_Decode, 129, 18, 171, 1, // Opcode: USHLLv8i16_shift >+/* 27249 */ MCD_OPC_FilterValue, 1, 104, 52, // Skip to: 40669 >+/* 27253 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 27256 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27269 >+/* 27260 */ MCD_OPC_CheckPredicate, 0, 93, 52, // Skip to: 40669 >+/* 27264 */ MCD_OPC_Decode, 189, 12, 176, 1, // Opcode: SQSHRUNv4i32_shift >+/* 27269 */ MCD_OPC_FilterValue, 1, 84, 52, // Skip to: 40669 >+/* 27273 */ MCD_OPC_CheckPredicate, 0, 80, 52, // Skip to: 40669 >+/* 27277 */ MCD_OPC_Decode, 128, 18, 173, 1, // Opcode: USHLLv4i32_shift >+/* 27282 */ MCD_OPC_FilterValue, 1, 71, 52, // Skip to: 40669 >+/* 27286 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 27289 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 27353 >+/* 27293 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 27296 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 27334 >+/* 27300 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 27303 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 27315 >+/* 27307 */ MCD_OPC_CheckPredicate, 0, 46, 52, // Skip to: 40669 >+/* 27311 */ MCD_OPC_Decode, 116, 149, 1, // Opcode: BICv8i16 >+/* 27315 */ MCD_OPC_FilterValue, 1, 38, 52, // Skip to: 40669 >+/* 27319 */ MCD_OPC_CheckPredicate, 0, 34, 52, // Skip to: 40669 >+/* 27323 */ MCD_OPC_CheckField, 13, 1, 0, 28, 52, // Skip to: 40669 >+/* 27329 */ MCD_OPC_Decode, 193, 17, 174, 1, // Opcode: UQSHRNv16i8_shift >+/* 27334 */ MCD_OPC_FilterValue, 1, 19, 52, // Skip to: 40669 >+/* 27338 */ MCD_OPC_CheckPredicate, 0, 15, 52, // Skip to: 40669 >+/* 27342 */ MCD_OPC_CheckField, 13, 1, 0, 9, 52, // Skip to: 40669 >+/* 27348 */ MCD_OPC_Decode, 197, 17, 175, 1, // Opcode: UQSHRNv8i16_shift >+/* 27353 */ MCD_OPC_FilterValue, 1, 0, 52, // Skip to: 40669 >+/* 27357 */ MCD_OPC_CheckPredicate, 0, 252, 51, // Skip to: 40669 >+/* 27361 */ MCD_OPC_CheckField, 13, 1, 0, 246, 51, // Skip to: 40669 >+/* 27367 */ MCD_OPC_Decode, 196, 17, 176, 1, // Opcode: UQSHRNv4i32_shift >+/* 27372 */ MCD_OPC_FilterValue, 1, 237, 51, // Skip to: 40669 >+/* 27376 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 27379 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27398 >+/* 27383 */ MCD_OPC_CheckPredicate, 0, 226, 51, // Skip to: 40669 >+/* 27387 */ MCD_OPC_CheckField, 19, 3, 0, 220, 51, // Skip to: 40669 >+/* 27393 */ MCD_OPC_Decode, 243, 8, 145, 1, // Opcode: MVNIv4s_msl >+/* 27398 */ MCD_OPC_FilterValue, 1, 211, 51, // Skip to: 40669 >+/* 27402 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 27405 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27444 >+/* 27409 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 27412 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27431 >+/* 27416 */ MCD_OPC_CheckPredicate, 0, 193, 51, // Skip to: 40669 >+/* 27420 */ MCD_OPC_CheckField, 19, 2, 0, 187, 51, // Skip to: 40669 >+/* 27426 */ MCD_OPC_Decode, 202, 8, 145, 1, // Opcode: MOVIv2d_ns >+/* 27431 */ MCD_OPC_FilterValue, 1, 178, 51, // Skip to: 40669 >+/* 27435 */ MCD_OPC_CheckPredicate, 0, 174, 51, // Skip to: 40669 >+/* 27439 */ MCD_OPC_Decode, 177, 16, 167, 1, // Opcode: UCVTFv4i32_shift >+/* 27444 */ MCD_OPC_FilterValue, 1, 165, 51, // Skip to: 40669 >+/* 27448 */ MCD_OPC_CheckPredicate, 0, 161, 51, // Skip to: 40669 >+/* 27452 */ MCD_OPC_CheckField, 19, 3, 0, 155, 51, // Skip to: 40669 >+/* 27458 */ MCD_OPC_Decode, 231, 4, 145, 1, // Opcode: FMOVv2f64_ns >+/* 27463 */ MCD_OPC_FilterValue, 3, 146, 51, // Skip to: 40669 >+/* 27467 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 27470 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 27529 >+/* 27474 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 27477 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27516 >+/* 27481 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 27484 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27503 >+/* 27488 */ MCD_OPC_CheckPredicate, 0, 121, 51, // Skip to: 40669 >+/* 27492 */ MCD_OPC_CheckField, 19, 1, 1, 115, 51, // Skip to: 40669 >+/* 27498 */ MCD_OPC_Decode, 135, 12, 174, 1, // Opcode: SQRSHRUNv16i8_shift >+/* 27503 */ MCD_OPC_FilterValue, 1, 106, 51, // Skip to: 40669 >+/* 27507 */ MCD_OPC_CheckPredicate, 0, 102, 51, // Skip to: 40669 >+/* 27511 */ MCD_OPC_Decode, 139, 12, 175, 1, // Opcode: SQRSHRUNv8i16_shift >+/* 27516 */ MCD_OPC_FilterValue, 1, 93, 51, // Skip to: 40669 >+/* 27520 */ MCD_OPC_CheckPredicate, 0, 89, 51, // Skip to: 40669 >+/* 27524 */ MCD_OPC_Decode, 138, 12, 176, 1, // Opcode: SQRSHRUNv4i32_shift >+/* 27529 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 27588 >+/* 27533 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 27536 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27575 >+/* 27540 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 27543 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27562 >+/* 27547 */ MCD_OPC_CheckPredicate, 0, 62, 51, // Skip to: 40669 >+/* 27551 */ MCD_OPC_CheckField, 19, 1, 1, 56, 51, // Skip to: 40669 >+/* 27557 */ MCD_OPC_Decode, 162, 17, 174, 1, // Opcode: UQRSHRNv16i8_shift >+/* 27562 */ MCD_OPC_FilterValue, 1, 47, 51, // Skip to: 40669 >+/* 27566 */ MCD_OPC_CheckPredicate, 0, 43, 51, // Skip to: 40669 >+/* 27570 */ MCD_OPC_Decode, 166, 17, 175, 1, // Opcode: UQRSHRNv8i16_shift >+/* 27575 */ MCD_OPC_FilterValue, 1, 34, 51, // Skip to: 40669 >+/* 27579 */ MCD_OPC_CheckPredicate, 0, 30, 51, // Skip to: 40669 >+/* 27583 */ MCD_OPC_Decode, 165, 17, 176, 1, // Opcode: UQRSHRNv4i32_shift >+/* 27588 */ MCD_OPC_FilterValue, 15, 21, 51, // Skip to: 40669 >+/* 27592 */ MCD_OPC_CheckPredicate, 0, 17, 51, // Skip to: 40669 >+/* 27596 */ MCD_OPC_CheckField, 21, 1, 1, 11, 51, // Skip to: 40669 >+/* 27602 */ MCD_OPC_Decode, 152, 4, 167, 1, // Opcode: FCVTZUv4i32_shift >+/* 27607 */ MCD_OPC_FilterValue, 13, 221, 3, // Skip to: 28600 >+/* 27611 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 27614 */ MCD_OPC_FilterValue, 0, 80, 0, // Skip to: 27698 >+/* 27618 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 27621 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27640 >+/* 27625 */ MCD_OPC_CheckPredicate, 0, 240, 50, // Skip to: 40669 >+/* 27629 */ MCD_OPC_CheckField, 10, 1, 0, 234, 50, // Skip to: 40669 >+/* 27635 */ MCD_OPC_Decode, 184, 8, 180, 1, // Opcode: MLAv4i16_indexed >+/* 27640 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27659 >+/* 27644 */ MCD_OPC_CheckPredicate, 0, 221, 50, // Skip to: 40669 >+/* 27648 */ MCD_OPC_CheckField, 10, 2, 1, 215, 50, // Skip to: 40669 >+/* 27654 */ MCD_OPC_Decode, 148, 13, 181, 1, // Opcode: SSHRv2i64_shift >+/* 27659 */ MCD_OPC_FilterValue, 3, 206, 50, // Skip to: 40669 >+/* 27663 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 27666 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27679 >+/* 27670 */ MCD_OPC_CheckPredicate, 0, 195, 50, // Skip to: 40669 >+/* 27674 */ MCD_OPC_Decode, 188, 8, 182, 1, // Opcode: MLAv8i16_indexed >+/* 27679 */ MCD_OPC_FilterValue, 1, 186, 50, // Skip to: 40669 >+/* 27683 */ MCD_OPC_CheckPredicate, 0, 182, 50, // Skip to: 40669 >+/* 27687 */ MCD_OPC_CheckField, 11, 1, 0, 176, 50, // Skip to: 40669 >+/* 27693 */ MCD_OPC_Decode, 142, 18, 181, 1, // Opcode: USHRv2i64_shift >+/* 27698 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 27743 >+/* 27702 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 27705 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27724 >+/* 27709 */ MCD_OPC_CheckPredicate, 0, 156, 50, // Skip to: 40669 >+/* 27713 */ MCD_OPC_CheckField, 10, 2, 1, 150, 50, // Skip to: 40669 >+/* 27719 */ MCD_OPC_Decode, 156, 13, 183, 1, // Opcode: SSRAv2i64_shift >+/* 27724 */ MCD_OPC_FilterValue, 3, 141, 50, // Skip to: 40669 >+/* 27728 */ MCD_OPC_CheckPredicate, 0, 137, 50, // Skip to: 40669 >+/* 27732 */ MCD_OPC_CheckField, 10, 2, 1, 131, 50, // Skip to: 40669 >+/* 27738 */ MCD_OPC_Decode, 161, 18, 183, 1, // Opcode: USRAv2i64_shift >+/* 27743 */ MCD_OPC_FilterValue, 2, 119, 0, // Skip to: 27866 >+/* 27747 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 27750 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27769 >+/* 27754 */ MCD_OPC_CheckPredicate, 0, 111, 50, // Skip to: 40669 >+/* 27758 */ MCD_OPC_CheckField, 10, 1, 0, 105, 50, // Skip to: 40669 >+/* 27764 */ MCD_OPC_Decode, 241, 10, 184, 1, // Opcode: SMLALv4i16_indexed >+/* 27769 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27788 >+/* 27773 */ MCD_OPC_CheckPredicate, 0, 92, 50, // Skip to: 40669 >+/* 27777 */ MCD_OPC_CheckField, 10, 1, 0, 86, 50, // Skip to: 40669 >+/* 27783 */ MCD_OPC_Decode, 232, 16, 184, 1, // Opcode: UMLALv4i16_indexed >+/* 27788 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27827 >+/* 27792 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 27795 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27808 >+/* 27799 */ MCD_OPC_CheckPredicate, 0, 66, 50, // Skip to: 40669 >+/* 27803 */ MCD_OPC_Decode, 245, 10, 182, 1, // Opcode: SMLALv8i16_indexed >+/* 27808 */ MCD_OPC_FilterValue, 1, 57, 50, // Skip to: 40669 >+/* 27812 */ MCD_OPC_CheckPredicate, 0, 53, 50, // Skip to: 40669 >+/* 27816 */ MCD_OPC_CheckField, 11, 1, 0, 47, 50, // Skip to: 40669 >+/* 27822 */ MCD_OPC_Decode, 246, 12, 181, 1, // Opcode: SRSHRv2i64_shift >+/* 27827 */ MCD_OPC_FilterValue, 3, 38, 50, // Skip to: 40669 >+/* 27831 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 27834 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27847 >+/* 27838 */ MCD_OPC_CheckPredicate, 0, 27, 50, // Skip to: 40669 >+/* 27842 */ MCD_OPC_Decode, 236, 16, 182, 1, // Opcode: UMLALv8i16_indexed >+/* 27847 */ MCD_OPC_FilterValue, 1, 18, 50, // Skip to: 40669 >+/* 27851 */ MCD_OPC_CheckPredicate, 0, 14, 50, // Skip to: 40669 >+/* 27855 */ MCD_OPC_CheckField, 11, 1, 0, 8, 50, // Skip to: 40669 >+/* 27861 */ MCD_OPC_Decode, 238, 17, 181, 1, // Opcode: URSHRv2i64_shift >+/* 27866 */ MCD_OPC_FilterValue, 3, 80, 0, // Skip to: 27950 >+/* 27870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 27873 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27892 >+/* 27877 */ MCD_OPC_CheckPredicate, 0, 244, 49, // Skip to: 40669 >+/* 27881 */ MCD_OPC_CheckField, 10, 1, 0, 238, 49, // Skip to: 40669 >+/* 27887 */ MCD_OPC_Decode, 175, 11, 184, 1, // Opcode: SQDMLALv4i16_indexed >+/* 27892 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27931 >+/* 27896 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 27899 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27912 >+/* 27903 */ MCD_OPC_CheckPredicate, 0, 218, 49, // Skip to: 40669 >+/* 27907 */ MCD_OPC_Decode, 179, 11, 182, 1, // Opcode: SQDMLALv8i16_indexed >+/* 27912 */ MCD_OPC_FilterValue, 1, 209, 49, // Skip to: 40669 >+/* 27916 */ MCD_OPC_CheckPredicate, 0, 205, 49, // Skip to: 40669 >+/* 27920 */ MCD_OPC_CheckField, 11, 1, 0, 199, 49, // Skip to: 40669 >+/* 27926 */ MCD_OPC_Decode, 254, 12, 183, 1, // Opcode: SRSRAv2i64_shift >+/* 27931 */ MCD_OPC_FilterValue, 3, 190, 49, // Skip to: 40669 >+/* 27935 */ MCD_OPC_CheckPredicate, 0, 186, 49, // Skip to: 40669 >+/* 27939 */ MCD_OPC_CheckField, 10, 2, 1, 180, 49, // Skip to: 40669 >+/* 27945 */ MCD_OPC_Decode, 248, 17, 183, 1, // Opcode: URSRAv2i64_shift >+/* 27950 */ MCD_OPC_FilterValue, 4, 61, 0, // Skip to: 28015 >+/* 27954 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 27957 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 27990 >+/* 27961 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 27964 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27977 >+/* 27968 */ MCD_OPC_CheckPredicate, 0, 153, 49, // Skip to: 40669 >+/* 27972 */ MCD_OPC_Decode, 194, 8, 180, 1, // Opcode: MLSv4i16_indexed >+/* 27977 */ MCD_OPC_FilterValue, 3, 144, 49, // Skip to: 40669 >+/* 27981 */ MCD_OPC_CheckPredicate, 0, 140, 49, // Skip to: 40669 >+/* 27985 */ MCD_OPC_Decode, 198, 8, 182, 1, // Opcode: MLSv8i16_indexed >+/* 27990 */ MCD_OPC_FilterValue, 1, 131, 49, // Skip to: 40669 >+/* 27994 */ MCD_OPC_CheckPredicate, 0, 127, 49, // Skip to: 40669 >+/* 27998 */ MCD_OPC_CheckField, 29, 3, 3, 121, 49, // Skip to: 40669 >+/* 28004 */ MCD_OPC_CheckField, 11, 1, 0, 115, 49, // Skip to: 40669 >+/* 28010 */ MCD_OPC_Decode, 230, 12, 183, 1, // Opcode: SRIv2i64_shift >+/* 28015 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28060 >+/* 28019 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28022 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28041 >+/* 28026 */ MCD_OPC_CheckPredicate, 0, 95, 49, // Skip to: 40669 >+/* 28030 */ MCD_OPC_CheckField, 10, 2, 1, 89, 49, // Skip to: 40669 >+/* 28036 */ MCD_OPC_Decode, 177, 10, 185, 1, // Opcode: SHLv2i64_shift >+/* 28041 */ MCD_OPC_FilterValue, 3, 80, 49, // Skip to: 40669 >+/* 28045 */ MCD_OPC_CheckPredicate, 0, 76, 49, // Skip to: 40669 >+/* 28049 */ MCD_OPC_CheckField, 10, 2, 1, 70, 49, // Skip to: 40669 >+/* 28055 */ MCD_OPC_Decode, 197, 10, 186, 1, // Opcode: SLIv2i64_shift >+/* 28060 */ MCD_OPC_FilterValue, 6, 99, 0, // Skip to: 28163 >+/* 28064 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28067 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28086 >+/* 28071 */ MCD_OPC_CheckPredicate, 0, 50, 49, // Skip to: 40669 >+/* 28075 */ MCD_OPC_CheckField, 10, 1, 0, 44, 49, // Skip to: 40669 >+/* 28081 */ MCD_OPC_Decode, 251, 10, 184, 1, // Opcode: SMLSLv4i16_indexed >+/* 28086 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28105 >+/* 28090 */ MCD_OPC_CheckPredicate, 0, 31, 49, // Skip to: 40669 >+/* 28094 */ MCD_OPC_CheckField, 10, 1, 0, 25, 49, // Skip to: 40669 >+/* 28100 */ MCD_OPC_Decode, 242, 16, 184, 1, // Opcode: UMLSLv4i16_indexed >+/* 28105 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28124 >+/* 28109 */ MCD_OPC_CheckPredicate, 0, 12, 49, // Skip to: 40669 >+/* 28113 */ MCD_OPC_CheckField, 10, 1, 0, 6, 49, // Skip to: 40669 >+/* 28119 */ MCD_OPC_Decode, 255, 10, 182, 1, // Opcode: SMLSLv8i16_indexed >+/* 28124 */ MCD_OPC_FilterValue, 3, 253, 48, // Skip to: 40669 >+/* 28128 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 28131 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28144 >+/* 28135 */ MCD_OPC_CheckPredicate, 0, 242, 48, // Skip to: 40669 >+/* 28139 */ MCD_OPC_Decode, 246, 16, 182, 1, // Opcode: UMLSLv8i16_indexed >+/* 28144 */ MCD_OPC_FilterValue, 1, 233, 48, // Skip to: 40669 >+/* 28148 */ MCD_OPC_CheckPredicate, 0, 229, 48, // Skip to: 40669 >+/* 28152 */ MCD_OPC_CheckField, 11, 1, 0, 223, 48, // Skip to: 40669 >+/* 28158 */ MCD_OPC_Decode, 147, 12, 185, 1, // Opcode: SQSHLUv2i64_shift >+/* 28163 */ MCD_OPC_FilterValue, 7, 80, 0, // Skip to: 28247 >+/* 28167 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28170 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28189 >+/* 28174 */ MCD_OPC_CheckPredicate, 0, 203, 48, // Skip to: 40669 >+/* 28178 */ MCD_OPC_CheckField, 10, 1, 0, 197, 48, // Skip to: 40669 >+/* 28184 */ MCD_OPC_Decode, 187, 11, 184, 1, // Opcode: SQDMLSLv4i16_indexed >+/* 28189 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 28228 >+/* 28193 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 28196 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28209 >+/* 28200 */ MCD_OPC_CheckPredicate, 0, 177, 48, // Skip to: 40669 >+/* 28204 */ MCD_OPC_Decode, 191, 11, 182, 1, // Opcode: SQDMLSLv8i16_indexed >+/* 28209 */ MCD_OPC_FilterValue, 1, 168, 48, // Skip to: 40669 >+/* 28213 */ MCD_OPC_CheckPredicate, 0, 164, 48, // Skip to: 40669 >+/* 28217 */ MCD_OPC_CheckField, 11, 1, 0, 158, 48, // Skip to: 40669 >+/* 28223 */ MCD_OPC_Decode, 165, 12, 185, 1, // Opcode: SQSHLv2i64_shift >+/* 28228 */ MCD_OPC_FilterValue, 3, 149, 48, // Skip to: 40669 >+/* 28232 */ MCD_OPC_CheckPredicate, 0, 145, 48, // Skip to: 40669 >+/* 28236 */ MCD_OPC_CheckField, 10, 2, 1, 139, 48, // Skip to: 40669 >+/* 28242 */ MCD_OPC_Decode, 181, 17, 185, 1, // Opcode: UQSHLv2i64_shift >+/* 28247 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 28292 >+/* 28251 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28254 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28273 >+/* 28258 */ MCD_OPC_CheckPredicate, 0, 119, 48, // Skip to: 40669 >+/* 28262 */ MCD_OPC_CheckField, 10, 1, 0, 113, 48, // Skip to: 40669 >+/* 28268 */ MCD_OPC_Decode, 233, 8, 187, 1, // Opcode: MULv4i16_indexed >+/* 28273 */ MCD_OPC_FilterValue, 2, 104, 48, // Skip to: 40669 >+/* 28277 */ MCD_OPC_CheckPredicate, 0, 100, 48, // Skip to: 40669 >+/* 28281 */ MCD_OPC_CheckField, 10, 1, 0, 94, 48, // Skip to: 40669 >+/* 28287 */ MCD_OPC_Decode, 237, 8, 188, 1, // Opcode: MULv8i16_indexed >+/* 28292 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 28375 >+/* 28296 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28299 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28318 >+/* 28303 */ MCD_OPC_CheckPredicate, 0, 74, 48, // Skip to: 40669 >+/* 28307 */ MCD_OPC_CheckField, 10, 1, 0, 68, 48, // Skip to: 40669 >+/* 28313 */ MCD_OPC_Decode, 140, 11, 189, 1, // Opcode: SMULLv4i16_indexed >+/* 28318 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28337 >+/* 28322 */ MCD_OPC_CheckPredicate, 0, 55, 48, // Skip to: 40669 >+/* 28326 */ MCD_OPC_CheckField, 10, 1, 0, 49, 48, // Skip to: 40669 >+/* 28332 */ MCD_OPC_Decode, 130, 17, 189, 1, // Opcode: UMULLv4i16_indexed >+/* 28337 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28356 >+/* 28341 */ MCD_OPC_CheckPredicate, 0, 36, 48, // Skip to: 40669 >+/* 28345 */ MCD_OPC_CheckField, 10, 1, 0, 30, 48, // Skip to: 40669 >+/* 28351 */ MCD_OPC_Decode, 144, 11, 188, 1, // Opcode: SMULLv8i16_indexed >+/* 28356 */ MCD_OPC_FilterValue, 3, 21, 48, // Skip to: 40669 >+/* 28360 */ MCD_OPC_CheckPredicate, 0, 17, 48, // Skip to: 40669 >+/* 28364 */ MCD_OPC_CheckField, 10, 1, 0, 11, 48, // Skip to: 40669 >+/* 28370 */ MCD_OPC_Decode, 134, 17, 188, 1, // Opcode: UMULLv8i16_indexed >+/* 28375 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 28420 >+/* 28379 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28382 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28401 >+/* 28386 */ MCD_OPC_CheckPredicate, 0, 247, 47, // Skip to: 40669 >+/* 28390 */ MCD_OPC_CheckField, 10, 1, 0, 241, 47, // Skip to: 40669 >+/* 28396 */ MCD_OPC_Decode, 211, 11, 189, 1, // Opcode: SQDMULLv4i16_indexed >+/* 28401 */ MCD_OPC_FilterValue, 2, 232, 47, // Skip to: 40669 >+/* 28405 */ MCD_OPC_CheckPredicate, 0, 228, 47, // Skip to: 40669 >+/* 28409 */ MCD_OPC_CheckField, 10, 1, 0, 222, 47, // Skip to: 40669 >+/* 28415 */ MCD_OPC_Decode, 215, 11, 188, 1, // Opcode: SQDMULLv8i16_indexed >+/* 28420 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 28465 >+/* 28424 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28427 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28446 >+/* 28431 */ MCD_OPC_CheckPredicate, 0, 202, 47, // Skip to: 40669 >+/* 28435 */ MCD_OPC_CheckField, 10, 1, 0, 196, 47, // Skip to: 40669 >+/* 28441 */ MCD_OPC_Decode, 200, 11, 187, 1, // Opcode: SQDMULHv4i16_indexed >+/* 28446 */ MCD_OPC_FilterValue, 2, 187, 47, // Skip to: 40669 >+/* 28450 */ MCD_OPC_CheckPredicate, 0, 183, 47, // Skip to: 40669 >+/* 28454 */ MCD_OPC_CheckField, 10, 1, 0, 177, 47, // Skip to: 40669 >+/* 28460 */ MCD_OPC_Decode, 204, 11, 188, 1, // Opcode: SQDMULHv8i16_indexed >+/* 28465 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 28510 >+/* 28469 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28472 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28491 >+/* 28476 */ MCD_OPC_CheckPredicate, 0, 157, 47, // Skip to: 40669 >+/* 28480 */ MCD_OPC_CheckField, 10, 1, 0, 151, 47, // Skip to: 40669 >+/* 28486 */ MCD_OPC_Decode, 235, 11, 187, 1, // Opcode: SQRDMULHv4i16_indexed >+/* 28491 */ MCD_OPC_FilterValue, 2, 142, 47, // Skip to: 40669 >+/* 28495 */ MCD_OPC_CheckPredicate, 0, 138, 47, // Skip to: 40669 >+/* 28499 */ MCD_OPC_CheckField, 10, 1, 0, 132, 47, // Skip to: 40669 >+/* 28505 */ MCD_OPC_Decode, 239, 11, 188, 1, // Opcode: SQRDMULHv8i16_indexed >+/* 28510 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 28555 >+/* 28514 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28517 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28536 >+/* 28521 */ MCD_OPC_CheckPredicate, 0, 112, 47, // Skip to: 40669 >+/* 28525 */ MCD_OPC_CheckField, 10, 2, 1, 106, 47, // Skip to: 40669 >+/* 28531 */ MCD_OPC_Decode, 145, 10, 181, 1, // Opcode: SCVTFv2i64_shift >+/* 28536 */ MCD_OPC_FilterValue, 3, 97, 47, // Skip to: 40669 >+/* 28540 */ MCD_OPC_CheckPredicate, 0, 93, 47, // Skip to: 40669 >+/* 28544 */ MCD_OPC_CheckField, 10, 2, 1, 87, 47, // Skip to: 40669 >+/* 28550 */ MCD_OPC_Decode, 175, 16, 181, 1, // Opcode: UCVTFv2i64_shift >+/* 28555 */ MCD_OPC_FilterValue, 15, 78, 47, // Skip to: 40669 >+/* 28559 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28562 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28581 >+/* 28566 */ MCD_OPC_CheckPredicate, 0, 67, 47, // Skip to: 40669 >+/* 28570 */ MCD_OPC_CheckField, 10, 2, 3, 61, 47, // Skip to: 40669 >+/* 28576 */ MCD_OPC_Decode, 249, 3, 181, 1, // Opcode: FCVTZSv2i64_shift >+/* 28581 */ MCD_OPC_FilterValue, 3, 52, 47, // Skip to: 40669 >+/* 28585 */ MCD_OPC_CheckPredicate, 0, 48, 47, // Skip to: 40669 >+/* 28589 */ MCD_OPC_CheckField, 10, 2, 3, 42, 47, // Skip to: 40669 >+/* 28595 */ MCD_OPC_Decode, 150, 4, 181, 1, // Opcode: FCVTZUv2i64_shift >+/* 28600 */ MCD_OPC_FilterValue, 14, 17, 3, // Skip to: 29389 >+/* 28604 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 28607 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 28652 >+/* 28611 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28614 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28633 >+/* 28618 */ MCD_OPC_CheckPredicate, 0, 15, 47, // Skip to: 40669 >+/* 28622 */ MCD_OPC_CheckField, 10, 1, 0, 9, 47, // Skip to: 40669 >+/* 28628 */ MCD_OPC_Decode, 182, 8, 190, 1, // Opcode: MLAv2i32_indexed >+/* 28633 */ MCD_OPC_FilterValue, 3, 0, 47, // Skip to: 40669 >+/* 28637 */ MCD_OPC_CheckPredicate, 0, 252, 46, // Skip to: 40669 >+/* 28641 */ MCD_OPC_CheckField, 10, 1, 0, 246, 46, // Skip to: 40669 >+/* 28647 */ MCD_OPC_Decode, 186, 8, 191, 1, // Opcode: MLAv4i32_indexed >+/* 28652 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 28697 >+/* 28656 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28659 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28678 >+/* 28663 */ MCD_OPC_CheckPredicate, 0, 226, 46, // Skip to: 40669 >+/* 28667 */ MCD_OPC_CheckField, 10, 1, 0, 220, 46, // Skip to: 40669 >+/* 28673 */ MCD_OPC_Decode, 208, 4, 190, 1, // Opcode: FMLAv2i32_indexed >+/* 28678 */ MCD_OPC_FilterValue, 2, 211, 46, // Skip to: 40669 >+/* 28682 */ MCD_OPC_CheckPredicate, 0, 207, 46, // Skip to: 40669 >+/* 28686 */ MCD_OPC_CheckField, 10, 1, 0, 201, 46, // Skip to: 40669 >+/* 28692 */ MCD_OPC_Decode, 211, 4, 191, 1, // Opcode: FMLAv4i32_indexed >+/* 28697 */ MCD_OPC_FilterValue, 2, 79, 0, // Skip to: 28780 >+/* 28701 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28704 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28723 >+/* 28708 */ MCD_OPC_CheckPredicate, 0, 181, 46, // Skip to: 40669 >+/* 28712 */ MCD_OPC_CheckField, 10, 1, 0, 175, 46, // Skip to: 40669 >+/* 28718 */ MCD_OPC_Decode, 239, 10, 192, 1, // Opcode: SMLALv2i32_indexed >+/* 28723 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28742 >+/* 28727 */ MCD_OPC_CheckPredicate, 0, 162, 46, // Skip to: 40669 >+/* 28731 */ MCD_OPC_CheckField, 10, 1, 0, 156, 46, // Skip to: 40669 >+/* 28737 */ MCD_OPC_Decode, 230, 16, 192, 1, // Opcode: UMLALv2i32_indexed >+/* 28742 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28761 >+/* 28746 */ MCD_OPC_CheckPredicate, 0, 143, 46, // Skip to: 40669 >+/* 28750 */ MCD_OPC_CheckField, 10, 1, 0, 137, 46, // Skip to: 40669 >+/* 28756 */ MCD_OPC_Decode, 243, 10, 191, 1, // Opcode: SMLALv4i32_indexed >+/* 28761 */ MCD_OPC_FilterValue, 3, 128, 46, // Skip to: 40669 >+/* 28765 */ MCD_OPC_CheckPredicate, 0, 124, 46, // Skip to: 40669 >+/* 28769 */ MCD_OPC_CheckField, 10, 1, 0, 118, 46, // Skip to: 40669 >+/* 28775 */ MCD_OPC_Decode, 234, 16, 191, 1, // Opcode: UMLALv4i32_indexed >+/* 28780 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 28825 >+/* 28784 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28787 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28806 >+/* 28791 */ MCD_OPC_CheckPredicate, 0, 98, 46, // Skip to: 40669 >+/* 28795 */ MCD_OPC_CheckField, 10, 1, 0, 92, 46, // Skip to: 40669 >+/* 28801 */ MCD_OPC_Decode, 173, 11, 192, 1, // Opcode: SQDMLALv2i32_indexed >+/* 28806 */ MCD_OPC_FilterValue, 2, 83, 46, // Skip to: 40669 >+/* 28810 */ MCD_OPC_CheckPredicate, 0, 79, 46, // Skip to: 40669 >+/* 28814 */ MCD_OPC_CheckField, 10, 1, 0, 73, 46, // Skip to: 40669 >+/* 28820 */ MCD_OPC_Decode, 177, 11, 191, 1, // Opcode: SQDMLALv4i32_indexed >+/* 28825 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 28870 >+/* 28829 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28832 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28851 >+/* 28836 */ MCD_OPC_CheckPredicate, 0, 53, 46, // Skip to: 40669 >+/* 28840 */ MCD_OPC_CheckField, 10, 1, 0, 47, 46, // Skip to: 40669 >+/* 28846 */ MCD_OPC_Decode, 192, 8, 190, 1, // Opcode: MLSv2i32_indexed >+/* 28851 */ MCD_OPC_FilterValue, 3, 38, 46, // Skip to: 40669 >+/* 28855 */ MCD_OPC_CheckPredicate, 0, 34, 46, // Skip to: 40669 >+/* 28859 */ MCD_OPC_CheckField, 10, 1, 0, 28, 46, // Skip to: 40669 >+/* 28865 */ MCD_OPC_Decode, 196, 8, 191, 1, // Opcode: MLSv4i32_indexed >+/* 28870 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28915 >+/* 28874 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28877 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28896 >+/* 28881 */ MCD_OPC_CheckPredicate, 0, 8, 46, // Skip to: 40669 >+/* 28885 */ MCD_OPC_CheckField, 10, 1, 0, 2, 46, // Skip to: 40669 >+/* 28891 */ MCD_OPC_Decode, 216, 4, 190, 1, // Opcode: FMLSv2i32_indexed >+/* 28896 */ MCD_OPC_FilterValue, 2, 249, 45, // Skip to: 40669 >+/* 28900 */ MCD_OPC_CheckPredicate, 0, 245, 45, // Skip to: 40669 >+/* 28904 */ MCD_OPC_CheckField, 10, 1, 0, 239, 45, // Skip to: 40669 >+/* 28910 */ MCD_OPC_Decode, 219, 4, 191, 1, // Opcode: FMLSv4i32_indexed >+/* 28915 */ MCD_OPC_FilterValue, 6, 79, 0, // Skip to: 28998 >+/* 28919 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 28922 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28941 >+/* 28926 */ MCD_OPC_CheckPredicate, 0, 219, 45, // Skip to: 40669 >+/* 28930 */ MCD_OPC_CheckField, 10, 1, 0, 213, 45, // Skip to: 40669 >+/* 28936 */ MCD_OPC_Decode, 249, 10, 192, 1, // Opcode: SMLSLv2i32_indexed >+/* 28941 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28960 >+/* 28945 */ MCD_OPC_CheckPredicate, 0, 200, 45, // Skip to: 40669 >+/* 28949 */ MCD_OPC_CheckField, 10, 1, 0, 194, 45, // Skip to: 40669 >+/* 28955 */ MCD_OPC_Decode, 240, 16, 192, 1, // Opcode: UMLSLv2i32_indexed >+/* 28960 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28979 >+/* 28964 */ MCD_OPC_CheckPredicate, 0, 181, 45, // Skip to: 40669 >+/* 28968 */ MCD_OPC_CheckField, 10, 1, 0, 175, 45, // Skip to: 40669 >+/* 28974 */ MCD_OPC_Decode, 253, 10, 191, 1, // Opcode: SMLSLv4i32_indexed >+/* 28979 */ MCD_OPC_FilterValue, 3, 166, 45, // Skip to: 40669 >+/* 28983 */ MCD_OPC_CheckPredicate, 0, 162, 45, // Skip to: 40669 >+/* 28987 */ MCD_OPC_CheckField, 10, 1, 0, 156, 45, // Skip to: 40669 >+/* 28993 */ MCD_OPC_Decode, 244, 16, 191, 1, // Opcode: UMLSLv4i32_indexed >+/* 28998 */ MCD_OPC_FilterValue, 7, 41, 0, // Skip to: 29043 >+/* 29002 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29005 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29024 >+/* 29009 */ MCD_OPC_CheckPredicate, 0, 136, 45, // Skip to: 40669 >+/* 29013 */ MCD_OPC_CheckField, 10, 1, 0, 130, 45, // Skip to: 40669 >+/* 29019 */ MCD_OPC_Decode, 185, 11, 192, 1, // Opcode: SQDMLSLv2i32_indexed >+/* 29024 */ MCD_OPC_FilterValue, 2, 121, 45, // Skip to: 40669 >+/* 29028 */ MCD_OPC_CheckPredicate, 0, 117, 45, // Skip to: 40669 >+/* 29032 */ MCD_OPC_CheckField, 10, 1, 0, 111, 45, // Skip to: 40669 >+/* 29038 */ MCD_OPC_Decode, 189, 11, 191, 1, // Opcode: SQDMLSLv4i32_indexed >+/* 29043 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 29088 >+/* 29047 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29050 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29069 >+/* 29054 */ MCD_OPC_CheckPredicate, 0, 91, 45, // Skip to: 40669 >+/* 29058 */ MCD_OPC_CheckField, 10, 1, 0, 85, 45, // Skip to: 40669 >+/* 29064 */ MCD_OPC_Decode, 231, 8, 193, 1, // Opcode: MULv2i32_indexed >+/* 29069 */ MCD_OPC_FilterValue, 2, 76, 45, // Skip to: 40669 >+/* 29073 */ MCD_OPC_CheckPredicate, 0, 72, 45, // Skip to: 40669 >+/* 29077 */ MCD_OPC_CheckField, 10, 1, 0, 66, 45, // Skip to: 40669 >+/* 29083 */ MCD_OPC_Decode, 235, 8, 194, 1, // Opcode: MULv4i32_indexed >+/* 29088 */ MCD_OPC_FilterValue, 9, 79, 0, // Skip to: 29171 >+/* 29092 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29095 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29114 >+/* 29099 */ MCD_OPC_CheckPredicate, 0, 46, 45, // Skip to: 40669 >+/* 29103 */ MCD_OPC_CheckField, 10, 1, 0, 40, 45, // Skip to: 40669 >+/* 29109 */ MCD_OPC_Decode, 251, 4, 193, 1, // Opcode: FMULv2i32_indexed >+/* 29114 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29133 >+/* 29118 */ MCD_OPC_CheckPredicate, 0, 27, 45, // Skip to: 40669 >+/* 29122 */ MCD_OPC_CheckField, 10, 1, 0, 21, 45, // Skip to: 40669 >+/* 29128 */ MCD_OPC_Decode, 243, 4, 193, 1, // Opcode: FMULXv2i32_indexed >+/* 29133 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29152 >+/* 29137 */ MCD_OPC_CheckPredicate, 0, 8, 45, // Skip to: 40669 >+/* 29141 */ MCD_OPC_CheckField, 10, 1, 0, 2, 45, // Skip to: 40669 >+/* 29147 */ MCD_OPC_Decode, 254, 4, 194, 1, // Opcode: FMULv4i32_indexed >+/* 29152 */ MCD_OPC_FilterValue, 3, 249, 44, // Skip to: 40669 >+/* 29156 */ MCD_OPC_CheckPredicate, 0, 245, 44, // Skip to: 40669 >+/* 29160 */ MCD_OPC_CheckField, 10, 1, 0, 239, 44, // Skip to: 40669 >+/* 29166 */ MCD_OPC_Decode, 246, 4, 194, 1, // Opcode: FMULXv4i32_indexed >+/* 29171 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 29254 >+/* 29175 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29178 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29197 >+/* 29182 */ MCD_OPC_CheckPredicate, 0, 219, 44, // Skip to: 40669 >+/* 29186 */ MCD_OPC_CheckField, 10, 1, 0, 213, 44, // Skip to: 40669 >+/* 29192 */ MCD_OPC_Decode, 138, 11, 195, 1, // Opcode: SMULLv2i32_indexed >+/* 29197 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29216 >+/* 29201 */ MCD_OPC_CheckPredicate, 0, 200, 44, // Skip to: 40669 >+/* 29205 */ MCD_OPC_CheckField, 10, 1, 0, 194, 44, // Skip to: 40669 >+/* 29211 */ MCD_OPC_Decode, 128, 17, 195, 1, // Opcode: UMULLv2i32_indexed >+/* 29216 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29235 >+/* 29220 */ MCD_OPC_CheckPredicate, 0, 181, 44, // Skip to: 40669 >+/* 29224 */ MCD_OPC_CheckField, 10, 1, 0, 175, 44, // Skip to: 40669 >+/* 29230 */ MCD_OPC_Decode, 142, 11, 194, 1, // Opcode: SMULLv4i32_indexed >+/* 29235 */ MCD_OPC_FilterValue, 3, 166, 44, // Skip to: 40669 >+/* 29239 */ MCD_OPC_CheckPredicate, 0, 162, 44, // Skip to: 40669 >+/* 29243 */ MCD_OPC_CheckField, 10, 1, 0, 156, 44, // Skip to: 40669 >+/* 29249 */ MCD_OPC_Decode, 132, 17, 194, 1, // Opcode: UMULLv4i32_indexed >+/* 29254 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 29299 >+/* 29258 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29261 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29280 >+/* 29265 */ MCD_OPC_CheckPredicate, 0, 136, 44, // Skip to: 40669 >+/* 29269 */ MCD_OPC_CheckField, 10, 1, 0, 130, 44, // Skip to: 40669 >+/* 29275 */ MCD_OPC_Decode, 209, 11, 195, 1, // Opcode: SQDMULLv2i32_indexed >+/* 29280 */ MCD_OPC_FilterValue, 2, 121, 44, // Skip to: 40669 >+/* 29284 */ MCD_OPC_CheckPredicate, 0, 117, 44, // Skip to: 40669 >+/* 29288 */ MCD_OPC_CheckField, 10, 1, 0, 111, 44, // Skip to: 40669 >+/* 29294 */ MCD_OPC_Decode, 213, 11, 194, 1, // Opcode: SQDMULLv4i32_indexed >+/* 29299 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 29344 >+/* 29303 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29306 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29325 >+/* 29310 */ MCD_OPC_CheckPredicate, 0, 91, 44, // Skip to: 40669 >+/* 29314 */ MCD_OPC_CheckField, 10, 1, 0, 85, 44, // Skip to: 40669 >+/* 29320 */ MCD_OPC_Decode, 198, 11, 193, 1, // Opcode: SQDMULHv2i32_indexed >+/* 29325 */ MCD_OPC_FilterValue, 2, 76, 44, // Skip to: 40669 >+/* 29329 */ MCD_OPC_CheckPredicate, 0, 72, 44, // Skip to: 40669 >+/* 29333 */ MCD_OPC_CheckField, 10, 1, 0, 66, 44, // Skip to: 40669 >+/* 29339 */ MCD_OPC_Decode, 202, 11, 194, 1, // Opcode: SQDMULHv4i32_indexed >+/* 29344 */ MCD_OPC_FilterValue, 13, 57, 44, // Skip to: 40669 >+/* 29348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29351 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29370 >+/* 29355 */ MCD_OPC_CheckPredicate, 0, 46, 44, // Skip to: 40669 >+/* 29359 */ MCD_OPC_CheckField, 10, 1, 0, 40, 44, // Skip to: 40669 >+/* 29365 */ MCD_OPC_Decode, 233, 11, 193, 1, // Opcode: SQRDMULHv2i32_indexed >+/* 29370 */ MCD_OPC_FilterValue, 2, 31, 44, // Skip to: 40669 >+/* 29374 */ MCD_OPC_CheckPredicate, 0, 27, 44, // Skip to: 40669 >+/* 29378 */ MCD_OPC_CheckField, 10, 1, 0, 21, 44, // Skip to: 40669 >+/* 29384 */ MCD_OPC_Decode, 237, 11, 194, 1, // Opcode: SQRDMULHv4i32_indexed >+/* 29389 */ MCD_OPC_FilterValue, 15, 12, 44, // Skip to: 40669 >+/* 29393 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 29396 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 29427 >+/* 29400 */ MCD_OPC_CheckPredicate, 0, 1, 44, // Skip to: 40669 >+/* 29404 */ MCD_OPC_CheckField, 29, 3, 2, 251, 43, // Skip to: 40669 >+/* 29410 */ MCD_OPC_CheckField, 21, 1, 0, 245, 43, // Skip to: 40669 >+/* 29416 */ MCD_OPC_CheckField, 10, 1, 0, 239, 43, // Skip to: 40669 >+/* 29422 */ MCD_OPC_Decode, 209, 4, 196, 1, // Opcode: FMLAv2i64_indexed >+/* 29427 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 29458 >+/* 29431 */ MCD_OPC_CheckPredicate, 0, 226, 43, // Skip to: 40669 >+/* 29435 */ MCD_OPC_CheckField, 29, 3, 2, 220, 43, // Skip to: 40669 >+/* 29441 */ MCD_OPC_CheckField, 21, 1, 0, 214, 43, // Skip to: 40669 >+/* 29447 */ MCD_OPC_CheckField, 10, 1, 0, 208, 43, // Skip to: 40669 >+/* 29453 */ MCD_OPC_Decode, 217, 4, 196, 1, // Opcode: FMLSv2i64_indexed >+/* 29458 */ MCD_OPC_FilterValue, 9, 199, 43, // Skip to: 40669 >+/* 29462 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29465 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 29490 >+/* 29469 */ MCD_OPC_CheckPredicate, 0, 188, 43, // Skip to: 40669 >+/* 29473 */ MCD_OPC_CheckField, 21, 1, 0, 182, 43, // Skip to: 40669 >+/* 29479 */ MCD_OPC_CheckField, 10, 1, 0, 176, 43, // Skip to: 40669 >+/* 29485 */ MCD_OPC_Decode, 252, 4, 197, 1, // Opcode: FMULv2i64_indexed >+/* 29490 */ MCD_OPC_FilterValue, 3, 167, 43, // Skip to: 40669 >+/* 29494 */ MCD_OPC_CheckPredicate, 0, 163, 43, // Skip to: 40669 >+/* 29498 */ MCD_OPC_CheckField, 21, 1, 0, 157, 43, // Skip to: 40669 >+/* 29504 */ MCD_OPC_CheckField, 10, 1, 0, 151, 43, // Skip to: 40669 >+/* 29510 */ MCD_OPC_Decode, 244, 4, 197, 1, // Opcode: FMULXv2i64_indexed >+/* 29515 */ MCD_OPC_FilterValue, 4, 191, 1, // Skip to: 29966 >+/* 29519 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 29522 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 29545 >+/* 29526 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... >+/* 29529 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29537 >+/* 29533 */ MCD_OPC_Decode, 79, 198, 1, // Opcode: ADR >+/* 29537 */ MCD_OPC_FilterValue, 1, 120, 43, // Skip to: 40669 >+/* 29541 */ MCD_OPC_Decode, 80, 198, 1, // Opcode: ADRP >+/* 29545 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 29620 >+/* 29549 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29552 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29560 >+/* 29556 */ MCD_OPC_Decode, 60, 199, 1, // Opcode: ADDWri >+/* 29560 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 29568 >+/* 29564 */ MCD_OPC_Decode, 46, 199, 1, // Opcode: ADDSWri >+/* 29568 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 29577 >+/* 29572 */ MCD_OPC_Decode, 164, 15, 199, 1, // Opcode: SUBWri >+/* 29577 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 29586 >+/* 29581 */ MCD_OPC_Decode, 155, 15, 199, 1, // Opcode: SUBSWri >+/* 29586 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 29594 >+/* 29590 */ MCD_OPC_Decode, 64, 199, 1, // Opcode: ADDXri >+/* 29594 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 29602 >+/* 29598 */ MCD_OPC_Decode, 50, 199, 1, // Opcode: ADDSXri >+/* 29602 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 29611 >+/* 29606 */ MCD_OPC_Decode, 168, 15, 199, 1, // Opcode: SUBXri >+/* 29611 */ MCD_OPC_FilterValue, 7, 46, 43, // Skip to: 40669 >+/* 29615 */ MCD_OPC_Decode, 159, 15, 199, 1, // Opcode: SUBSXri >+/* 29620 */ MCD_OPC_FilterValue, 2, 197, 0, // Skip to: 29821 >+/* 29624 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29627 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 29657 >+/* 29631 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29634 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29648 >+/* 29638 */ MCD_OPC_CheckField, 22, 1, 0, 17, 43, // Skip to: 40669 >+/* 29644 */ MCD_OPC_Decode, 91, 200, 1, // Opcode: ANDWri >+/* 29648 */ MCD_OPC_FilterValue, 1, 9, 43, // Skip to: 40669 >+/* 29652 */ MCD_OPC_Decode, 212, 8, 201, 1, // Opcode: MOVNWi >+/* 29657 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 29672 >+/* 29661 */ MCD_OPC_CheckField, 22, 2, 0, 250, 42, // Skip to: 40669 >+/* 29667 */ MCD_OPC_Decode, 133, 9, 200, 1, // Opcode: ORRWri >+/* 29672 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 29703 >+/* 29676 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29679 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29694 >+/* 29683 */ MCD_OPC_CheckField, 22, 1, 0, 228, 42, // Skip to: 40669 >+/* 29689 */ MCD_OPC_Decode, 164, 2, 200, 1, // Opcode: EORWri >+/* 29694 */ MCD_OPC_FilterValue, 1, 219, 42, // Skip to: 40669 >+/* 29698 */ MCD_OPC_Decode, 214, 8, 201, 1, // Opcode: MOVZWi >+/* 29703 */ MCD_OPC_FilterValue, 3, 26, 0, // Skip to: 29733 >+/* 29707 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29710 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29724 >+/* 29714 */ MCD_OPC_CheckField, 22, 1, 0, 197, 42, // Skip to: 40669 >+/* 29720 */ MCD_OPC_Decode, 85, 200, 1, // Opcode: ANDSWri >+/* 29724 */ MCD_OPC_FilterValue, 1, 189, 42, // Skip to: 40669 >+/* 29728 */ MCD_OPC_Decode, 210, 8, 201, 1, // Opcode: MOVKWi >+/* 29733 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 29757 >+/* 29737 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29740 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29748 >+/* 29744 */ MCD_OPC_Decode, 94, 200, 1, // Opcode: ANDXri >+/* 29748 */ MCD_OPC_FilterValue, 1, 165, 42, // Skip to: 40669 >+/* 29752 */ MCD_OPC_Decode, 213, 8, 201, 1, // Opcode: MOVNXi >+/* 29757 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 29772 >+/* 29761 */ MCD_OPC_CheckField, 23, 1, 0, 150, 42, // Skip to: 40669 >+/* 29767 */ MCD_OPC_Decode, 136, 9, 200, 1, // Opcode: ORRXri >+/* 29772 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 29797 >+/* 29776 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29779 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29788 >+/* 29783 */ MCD_OPC_Decode, 167, 2, 200, 1, // Opcode: EORXri >+/* 29788 */ MCD_OPC_FilterValue, 1, 125, 42, // Skip to: 40669 >+/* 29792 */ MCD_OPC_Decode, 215, 8, 201, 1, // Opcode: MOVZXi >+/* 29797 */ MCD_OPC_FilterValue, 7, 116, 42, // Skip to: 40669 >+/* 29801 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 29804 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29812 >+/* 29808 */ MCD_OPC_Decode, 88, 200, 1, // Opcode: ANDSXri >+/* 29812 */ MCD_OPC_FilterValue, 1, 101, 42, // Skip to: 40669 >+/* 29816 */ MCD_OPC_Decode, 211, 8, 201, 1, // Opcode: MOVKXi >+/* 29821 */ MCD_OPC_FilterValue, 3, 92, 42, // Skip to: 40669 >+/* 29825 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29828 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 29865 >+/* 29832 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 29835 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29850 >+/* 29839 */ MCD_OPC_CheckField, 15, 1, 0, 72, 42, // Skip to: 40669 >+/* 29845 */ MCD_OPC_Decode, 128, 10, 202, 1, // Opcode: SBFMWri >+/* 29850 */ MCD_OPC_FilterValue, 4, 63, 42, // Skip to: 40669 >+/* 29854 */ MCD_OPC_CheckField, 15, 1, 0, 57, 42, // Skip to: 40669 >+/* 29860 */ MCD_OPC_Decode, 173, 2, 203, 1, // Opcode: EXTRWrri >+/* 29865 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 29885 >+/* 29869 */ MCD_OPC_CheckField, 21, 3, 0, 42, 42, // Skip to: 40669 >+/* 29875 */ MCD_OPC_CheckField, 15, 1, 0, 36, 42, // Skip to: 40669 >+/* 29881 */ MCD_OPC_Decode, 102, 204, 1, // Opcode: BFMWri >+/* 29885 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 29906 >+/* 29889 */ MCD_OPC_CheckField, 21, 3, 0, 22, 42, // Skip to: 40669 >+/* 29895 */ MCD_OPC_CheckField, 15, 1, 0, 16, 42, // Skip to: 40669 >+/* 29901 */ MCD_OPC_Decode, 158, 16, 202, 1, // Opcode: UBFMWri >+/* 29906 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 29937 >+/* 29910 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 29913 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29922 >+/* 29917 */ MCD_OPC_Decode, 129, 10, 205, 1, // Opcode: SBFMXri >+/* 29922 */ MCD_OPC_FilterValue, 3, 247, 41, // Skip to: 40669 >+/* 29926 */ MCD_OPC_CheckField, 21, 1, 0, 241, 41, // Skip to: 40669 >+/* 29932 */ MCD_OPC_Decode, 174, 2, 206, 1, // Opcode: EXTRXrri >+/* 29937 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 29951 >+/* 29941 */ MCD_OPC_CheckField, 22, 2, 1, 226, 41, // Skip to: 40669 >+/* 29947 */ MCD_OPC_Decode, 103, 207, 1, // Opcode: BFMXri >+/* 29951 */ MCD_OPC_FilterValue, 6, 218, 41, // Skip to: 40669 >+/* 29955 */ MCD_OPC_CheckField, 22, 2, 1, 212, 41, // Skip to: 40669 >+/* 29961 */ MCD_OPC_Decode, 159, 16, 205, 1, // Opcode: UBFMXri >+/* 29966 */ MCD_OPC_FilterValue, 5, 248, 1, // Skip to: 30474 >+/* 29970 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 29973 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29981 >+/* 29977 */ MCD_OPC_Decode, 101, 208, 1, // Opcode: B >+/* 29981 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 30024 >+/* 29985 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 29988 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29997 >+/* 29992 */ MCD_OPC_Decode, 131, 1, 209, 1, // Opcode: CBZW >+/* 29997 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30006 >+/* 30001 */ MCD_OPC_Decode, 129, 1, 209, 1, // Opcode: CBNZW >+/* 30006 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30015 >+/* 30010 */ MCD_OPC_Decode, 213, 15, 210, 1, // Opcode: TBZW >+/* 30015 */ MCD_OPC_FilterValue, 3, 154, 41, // Skip to: 40669 >+/* 30019 */ MCD_OPC_Decode, 203, 15, 210, 1, // Opcode: TBNZW >+/* 30024 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 30045 >+/* 30028 */ MCD_OPC_CheckField, 24, 2, 0, 139, 41, // Skip to: 40669 >+/* 30034 */ MCD_OPC_CheckField, 4, 1, 0, 133, 41, // Skip to: 40669 >+/* 30040 */ MCD_OPC_Decode, 128, 1, 211, 1, // Opcode: Bcc >+/* 30045 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 30053 >+/* 30049 */ MCD_OPC_Decode, 122, 208, 1, // Opcode: BL >+/* 30053 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 30096 >+/* 30057 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 30060 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30069 >+/* 30064 */ MCD_OPC_Decode, 132, 1, 212, 1, // Opcode: CBZX >+/* 30069 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30078 >+/* 30073 */ MCD_OPC_Decode, 130, 1, 212, 1, // Opcode: CBNZX >+/* 30078 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30087 >+/* 30082 */ MCD_OPC_Decode, 214, 15, 210, 1, // Opcode: TBZX >+/* 30087 */ MCD_OPC_FilterValue, 3, 82, 41, // Skip to: 40669 >+/* 30091 */ MCD_OPC_Decode, 204, 15, 210, 1, // Opcode: TBNZX >+/* 30096 */ MCD_OPC_FilterValue, 6, 73, 41, // Skip to: 40669 >+/* 30100 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 30103 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 30137 >+/* 30107 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... >+/* 30110 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30119 >+/* 30114 */ MCD_OPC_Decode, 192, 15, 213, 1, // Opcode: SVC >+/* 30119 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30128 >+/* 30123 */ MCD_OPC_Decode, 207, 5, 213, 1, // Opcode: HVC >+/* 30128 */ MCD_OPC_FilterValue, 3, 41, 41, // Skip to: 40669 >+/* 30132 */ MCD_OPC_Decode, 220, 10, 213, 1, // Opcode: SMC >+/* 30137 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 30151 >+/* 30141 */ MCD_OPC_CheckField, 0, 5, 0, 26, 41, // Skip to: 40669 >+/* 30147 */ MCD_OPC_Decode, 125, 213, 1, // Opcode: BRK >+/* 30151 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 30166 >+/* 30155 */ MCD_OPC_CheckField, 0, 5, 0, 12, 41, // Skip to: 40669 >+/* 30161 */ MCD_OPC_Decode, 206, 5, 213, 1, // Opcode: HLT >+/* 30166 */ MCD_OPC_FilterValue, 5, 30, 0, // Skip to: 30200 >+/* 30170 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... >+/* 30173 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30182 >+/* 30177 */ MCD_OPC_Decode, 140, 2, 213, 1, // Opcode: DCPS1 >+/* 30182 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30191 >+/* 30186 */ MCD_OPC_Decode, 141, 2, 213, 1, // Opcode: DCPS2 >+/* 30191 */ MCD_OPC_FilterValue, 3, 234, 40, // Skip to: 40669 >+/* 30195 */ MCD_OPC_Decode, 142, 2, 213, 1, // Opcode: DCPS3 >+/* 30200 */ MCD_OPC_FilterValue, 8, 141, 0, // Skip to: 30345 >+/* 30204 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 30207 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 30336 >+/* 30211 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 30214 */ MCD_OPC_FilterValue, 0, 109, 0, // Skip to: 30327 >+/* 30218 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 30221 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 30242 >+/* 30225 */ MCD_OPC_CheckField, 16, 3, 3, 198, 40, // Skip to: 40669 >+/* 30231 */ MCD_OPC_CheckField, 0, 5, 31, 192, 40, // Skip to: 40669 >+/* 30237 */ MCD_OPC_Decode, 205, 5, 214, 1, // Opcode: HINT >+/* 30242 */ MCD_OPC_FilterValue, 3, 66, 0, // Skip to: 30312 >+/* 30246 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... >+/* 30249 */ MCD_OPC_FilterValue, 95, 11, 0, // Skip to: 30264 >+/* 30253 */ MCD_OPC_CheckField, 16, 3, 3, 170, 40, // Skip to: 40669 >+/* 30259 */ MCD_OPC_Decode, 141, 1, 215, 1, // Opcode: CLREX >+/* 30264 */ MCD_OPC_FilterValue, 159, 1, 11, 0, // Skip to: 30280 >+/* 30269 */ MCD_OPC_CheckField, 16, 3, 3, 154, 40, // Skip to: 40669 >+/* 30275 */ MCD_OPC_Decode, 145, 2, 215, 1, // Opcode: DSB >+/* 30280 */ MCD_OPC_FilterValue, 191, 1, 11, 0, // Skip to: 30296 >+/* 30285 */ MCD_OPC_CheckField, 16, 3, 3, 138, 40, // Skip to: 40669 >+/* 30291 */ MCD_OPC_Decode, 143, 2, 215, 1, // Opcode: DMB >+/* 30296 */ MCD_OPC_FilterValue, 223, 1, 128, 40, // Skip to: 40669 >+/* 30301 */ MCD_OPC_CheckField, 16, 3, 3, 122, 40, // Skip to: 40669 >+/* 30307 */ MCD_OPC_Decode, 216, 5, 215, 1, // Opcode: ISB >+/* 30312 */ MCD_OPC_FilterValue, 4, 113, 40, // Skip to: 40669 >+/* 30316 */ MCD_OPC_CheckField, 0, 5, 31, 107, 40, // Skip to: 40669 >+/* 30322 */ MCD_OPC_Decode, 226, 8, 216, 1, // Opcode: MSRpstate >+/* 30327 */ MCD_OPC_FilterValue, 1, 98, 40, // Skip to: 40669 >+/* 30331 */ MCD_OPC_Decode, 194, 15, 217, 1, // Opcode: SYSxt >+/* 30336 */ MCD_OPC_FilterValue, 1, 89, 40, // Skip to: 40669 >+/* 30340 */ MCD_OPC_Decode, 225, 8, 218, 1, // Opcode: MSR >+/* 30345 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 30376 >+/* 30349 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 30352 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30367 >+/* 30356 */ MCD_OPC_CheckField, 19, 1, 1, 67, 40, // Skip to: 40669 >+/* 30362 */ MCD_OPC_Decode, 193, 15, 219, 1, // Opcode: SYSLxt >+/* 30367 */ MCD_OPC_FilterValue, 1, 58, 40, // Skip to: 40669 >+/* 30371 */ MCD_OPC_Decode, 224, 8, 220, 1, // Opcode: MRS >+/* 30376 */ MCD_OPC_FilterValue, 16, 17, 0, // Skip to: 30397 >+/* 30380 */ MCD_OPC_CheckField, 10, 11, 192, 15, 42, 40, // Skip to: 40669 >+/* 30387 */ MCD_OPC_CheckField, 0, 5, 0, 36, 40, // Skip to: 40669 >+/* 30393 */ MCD_OPC_Decode, 124, 221, 1, // Opcode: BR >+/* 30397 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 30418 >+/* 30401 */ MCD_OPC_CheckField, 10, 11, 192, 15, 21, 40, // Skip to: 40669 >+/* 30408 */ MCD_OPC_CheckField, 0, 5, 0, 15, 40, // Skip to: 40669 >+/* 30414 */ MCD_OPC_Decode, 123, 221, 1, // Opcode: BLR >+/* 30418 */ MCD_OPC_FilterValue, 18, 18, 0, // Skip to: 30440 >+/* 30422 */ MCD_OPC_CheckField, 10, 11, 192, 15, 0, 40, // Skip to: 40669 >+/* 30429 */ MCD_OPC_CheckField, 0, 5, 0, 250, 39, // Skip to: 40669 >+/* 30435 */ MCD_OPC_Decode, 166, 9, 221, 1, // Opcode: RET >+/* 30440 */ MCD_OPC_FilterValue, 20, 13, 0, // Skip to: 30457 >+/* 30444 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 233, 39, // Skip to: 40669 >+/* 30452 */ MCD_OPC_Decode, 172, 2, 222, 1, // Opcode: ERET >+/* 30457 */ MCD_OPC_FilterValue, 21, 224, 39, // Skip to: 40669 >+/* 30461 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 216, 39, // Skip to: 40669 >+/* 30469 */ MCD_OPC_Decode, 144, 2, 222, 1, // Opcode: DRPS >+/* 30474 */ MCD_OPC_FilterValue, 6, 54, 10, // Skip to: 33092 >+/* 30478 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 30481 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 30782 >+/* 30485 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 30488 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30497 >+/* 30492 */ MCD_OPC_Decode, 132, 8, 209, 1, // Opcode: LDRWl >+/* 30497 */ MCD_OPC_FilterValue, 2, 244, 0, // Skip to: 30745 >+/* 30501 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 30504 */ MCD_OPC_FilterValue, 0, 68, 0, // Skip to: 30576 >+/* 30508 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 30511 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 30525 >+/* 30515 */ MCD_OPC_CheckField, 12, 4, 0, 164, 39, // Skip to: 40669 >+/* 30521 */ MCD_OPC_Decode, 30, 223, 1, // Opcode: ADCWr >+/* 30525 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30534 >+/* 30529 */ MCD_OPC_Decode, 132, 2, 224, 1, // Opcode: CSELWr >+/* 30534 */ MCD_OPC_FilterValue, 6, 147, 39, // Skip to: 40669 >+/* 30538 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 30541 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30550 >+/* 30545 */ MCD_OPC_Decode, 174, 8, 223, 1, // Opcode: LSLVWr >+/* 30550 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30563 >+/* 30554 */ MCD_OPC_CheckPredicate, 2, 127, 39, // Skip to: 40669 >+/* 30558 */ MCD_OPC_Decode, 252, 1, 223, 1, // Opcode: CRC32Brr >+/* 30563 */ MCD_OPC_FilterValue, 5, 118, 39, // Skip to: 40669 >+/* 30567 */ MCD_OPC_CheckPredicate, 2, 114, 39, // Skip to: 40669 >+/* 30571 */ MCD_OPC_Decode, 253, 1, 223, 1, // Opcode: CRC32CBrr >+/* 30576 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 30634 >+/* 30580 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 30583 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30592 >+/* 30587 */ MCD_OPC_Decode, 134, 2, 224, 1, // Opcode: CSINCWr >+/* 30592 */ MCD_OPC_FilterValue, 6, 89, 39, // Skip to: 40669 >+/* 30596 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 30599 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30608 >+/* 30603 */ MCD_OPC_Decode, 176, 8, 223, 1, // Opcode: LSRVWr >+/* 30608 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30621 >+/* 30612 */ MCD_OPC_CheckPredicate, 2, 69, 39, // Skip to: 40669 >+/* 30616 */ MCD_OPC_Decode, 129, 2, 223, 1, // Opcode: CRC32Hrr >+/* 30621 */ MCD_OPC_FilterValue, 5, 60, 39, // Skip to: 40669 >+/* 30625 */ MCD_OPC_CheckPredicate, 2, 56, 39, // Skip to: 40669 >+/* 30629 */ MCD_OPC_Decode, 254, 1, 223, 1, // Opcode: CRC32CHrr >+/* 30634 */ MCD_OPC_FilterValue, 2, 70, 0, // Skip to: 30708 >+/* 30638 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 30641 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30656 >+/* 30645 */ MCD_OPC_CheckField, 21, 3, 6, 34, 39, // Skip to: 40669 >+/* 30651 */ MCD_OPC_Decode, 178, 16, 223, 1, // Opcode: UDIVWr >+/* 30656 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 30670 >+/* 30660 */ MCD_OPC_CheckField, 21, 3, 6, 19, 39, // Skip to: 40669 >+/* 30666 */ MCD_OPC_Decode, 99, 223, 1, // Opcode: ASRVWr >+/* 30670 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 30689 >+/* 30674 */ MCD_OPC_CheckPredicate, 2, 7, 39, // Skip to: 40669 >+/* 30678 */ MCD_OPC_CheckField, 21, 3, 6, 1, 39, // Skip to: 40669 >+/* 30684 */ MCD_OPC_Decode, 130, 2, 223, 1, // Opcode: CRC32Wrr >+/* 30689 */ MCD_OPC_FilterValue, 5, 248, 38, // Skip to: 40669 >+/* 30693 */ MCD_OPC_CheckPredicate, 2, 244, 38, // Skip to: 40669 >+/* 30697 */ MCD_OPC_CheckField, 21, 3, 6, 238, 38, // Skip to: 40669 >+/* 30703 */ MCD_OPC_Decode, 255, 1, 223, 1, // Opcode: CRC32CWrr >+/* 30708 */ MCD_OPC_FilterValue, 3, 229, 38, // Skip to: 40669 >+/* 30712 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 30715 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30730 >+/* 30719 */ MCD_OPC_CheckField, 21, 3, 6, 216, 38, // Skip to: 40669 >+/* 30725 */ MCD_OPC_Decode, 148, 10, 223, 1, // Opcode: SDIVWr >+/* 30730 */ MCD_OPC_FilterValue, 2, 207, 38, // Skip to: 40669 >+/* 30734 */ MCD_OPC_CheckField, 21, 3, 6, 201, 38, // Skip to: 40669 >+/* 30740 */ MCD_OPC_Decode, 185, 9, 223, 1, // Opcode: RORVWr >+/* 30745 */ MCD_OPC_FilterValue, 3, 192, 38, // Skip to: 40669 >+/* 30749 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 30752 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30767 >+/* 30756 */ MCD_OPC_CheckField, 21, 3, 0, 179, 38, // Skip to: 40669 >+/* 30762 */ MCD_OPC_Decode, 178, 8, 225, 1, // Opcode: MADDWrrr >+/* 30767 */ MCD_OPC_FilterValue, 1, 170, 38, // Skip to: 40669 >+/* 30771 */ MCD_OPC_CheckField, 21, 3, 0, 164, 38, // Skip to: 40669 >+/* 30777 */ MCD_OPC_Decode, 227, 8, 225, 1, // Opcode: MSUBWrrr >+/* 30782 */ MCD_OPC_FilterValue, 1, 224, 1, // Skip to: 31266 >+/* 30786 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 30789 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 30882 >+/* 30793 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 30796 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30811 >+/* 30800 */ MCD_OPC_CheckField, 21, 1, 0, 135, 38, // Skip to: 40669 >+/* 30806 */ MCD_OPC_Decode, 134, 15, 226, 1, // Opcode: STURBBi >+/* 30811 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30826 >+/* 30815 */ MCD_OPC_CheckField, 21, 1, 0, 120, 38, // Skip to: 40669 >+/* 30821 */ MCD_OPC_Decode, 213, 14, 226, 1, // Opcode: STRBBpost >+/* 30826 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30867 >+/* 30830 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 30833 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30842 >+/* 30837 */ MCD_OPC_Decode, 130, 15, 226, 1, // Opcode: STTRBi >+/* 30842 */ MCD_OPC_FilterValue, 1, 95, 38, // Skip to: 40669 >+/* 30846 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 30849 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30858 >+/* 30853 */ MCD_OPC_Decode, 215, 14, 227, 1, // Opcode: STRBBroW >+/* 30858 */ MCD_OPC_FilterValue, 3, 79, 38, // Skip to: 40669 >+/* 30862 */ MCD_OPC_Decode, 216, 14, 228, 1, // Opcode: STRBBroX >+/* 30867 */ MCD_OPC_FilterValue, 3, 70, 38, // Skip to: 40669 >+/* 30871 */ MCD_OPC_CheckField, 21, 1, 0, 64, 38, // Skip to: 40669 >+/* 30877 */ MCD_OPC_Decode, 214, 14, 226, 1, // Opcode: STRBBpre >+/* 30882 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 30975 >+/* 30886 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 30889 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30904 >+/* 30893 */ MCD_OPC_CheckField, 21, 1, 0, 42, 38, // Skip to: 40669 >+/* 30899 */ MCD_OPC_Decode, 153, 8, 226, 1, // Opcode: LDURBBi >+/* 30904 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30919 >+/* 30908 */ MCD_OPC_CheckField, 21, 1, 0, 27, 38, // Skip to: 40669 >+/* 30914 */ MCD_OPC_Decode, 196, 7, 226, 1, // Opcode: LDRBBpost >+/* 30919 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30960 >+/* 30923 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 30926 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30935 >+/* 30930 */ MCD_OPC_Decode, 144, 8, 226, 1, // Opcode: LDTRBi >+/* 30935 */ MCD_OPC_FilterValue, 1, 2, 38, // Skip to: 40669 >+/* 30939 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 30942 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30951 >+/* 30946 */ MCD_OPC_Decode, 198, 7, 227, 1, // Opcode: LDRBBroW >+/* 30951 */ MCD_OPC_FilterValue, 3, 242, 37, // Skip to: 40669 >+/* 30955 */ MCD_OPC_Decode, 199, 7, 228, 1, // Opcode: LDRBBroX >+/* 30960 */ MCD_OPC_FilterValue, 3, 233, 37, // Skip to: 40669 >+/* 30964 */ MCD_OPC_CheckField, 21, 1, 0, 227, 37, // Skip to: 40669 >+/* 30970 */ MCD_OPC_Decode, 197, 7, 226, 1, // Opcode: LDRBBpre >+/* 30975 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31068 >+/* 30979 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 30982 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30997 >+/* 30986 */ MCD_OPC_CheckField, 21, 1, 0, 205, 37, // Skip to: 40669 >+/* 30992 */ MCD_OPC_Decode, 160, 8, 226, 1, // Opcode: LDURSBXi >+/* 30997 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31012 >+/* 31001 */ MCD_OPC_CheckField, 21, 1, 0, 190, 37, // Skip to: 40669 >+/* 31007 */ MCD_OPC_Decode, 233, 7, 226, 1, // Opcode: LDRSBXpost >+/* 31012 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31053 >+/* 31016 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31019 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31028 >+/* 31023 */ MCD_OPC_Decode, 147, 8, 226, 1, // Opcode: LDTRSBXi >+/* 31028 */ MCD_OPC_FilterValue, 1, 165, 37, // Skip to: 40669 >+/* 31032 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31035 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31044 >+/* 31039 */ MCD_OPC_Decode, 235, 7, 229, 1, // Opcode: LDRSBXroW >+/* 31044 */ MCD_OPC_FilterValue, 3, 149, 37, // Skip to: 40669 >+/* 31048 */ MCD_OPC_Decode, 236, 7, 230, 1, // Opcode: LDRSBXroX >+/* 31053 */ MCD_OPC_FilterValue, 3, 140, 37, // Skip to: 40669 >+/* 31057 */ MCD_OPC_CheckField, 21, 1, 0, 134, 37, // Skip to: 40669 >+/* 31063 */ MCD_OPC_Decode, 234, 7, 226, 1, // Opcode: LDRSBXpre >+/* 31068 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31161 >+/* 31072 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31075 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31090 >+/* 31079 */ MCD_OPC_CheckField, 21, 1, 0, 112, 37, // Skip to: 40669 >+/* 31085 */ MCD_OPC_Decode, 159, 8, 226, 1, // Opcode: LDURSBWi >+/* 31090 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31105 >+/* 31094 */ MCD_OPC_CheckField, 21, 1, 0, 97, 37, // Skip to: 40669 >+/* 31100 */ MCD_OPC_Decode, 228, 7, 226, 1, // Opcode: LDRSBWpost >+/* 31105 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31146 >+/* 31109 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31112 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31121 >+/* 31116 */ MCD_OPC_Decode, 146, 8, 226, 1, // Opcode: LDTRSBWi >+/* 31121 */ MCD_OPC_FilterValue, 1, 72, 37, // Skip to: 40669 >+/* 31125 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31128 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31137 >+/* 31132 */ MCD_OPC_Decode, 230, 7, 227, 1, // Opcode: LDRSBWroW >+/* 31137 */ MCD_OPC_FilterValue, 3, 56, 37, // Skip to: 40669 >+/* 31141 */ MCD_OPC_Decode, 231, 7, 228, 1, // Opcode: LDRSBWroX >+/* 31146 */ MCD_OPC_FilterValue, 3, 47, 37, // Skip to: 40669 >+/* 31150 */ MCD_OPC_CheckField, 21, 1, 0, 41, 37, // Skip to: 40669 >+/* 31156 */ MCD_OPC_Decode, 229, 7, 226, 1, // Opcode: LDRSBWpre >+/* 31161 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31170 >+/* 31165 */ MCD_OPC_Decode, 217, 14, 231, 1, // Opcode: STRBBui >+/* 31170 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31179 >+/* 31174 */ MCD_OPC_Decode, 200, 7, 231, 1, // Opcode: LDRBBui >+/* 31179 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31188 >+/* 31183 */ MCD_OPC_Decode, 237, 7, 231, 1, // Opcode: LDRSBXui >+/* 31188 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31197 >+/* 31192 */ MCD_OPC_Decode, 232, 7, 231, 1, // Opcode: LDRSBWui >+/* 31197 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 31217 >+/* 31201 */ MCD_OPC_CheckField, 21, 1, 0, 246, 36, // Skip to: 40669 >+/* 31207 */ MCD_OPC_CheckField, 10, 6, 0, 240, 36, // Skip to: 40669 >+/* 31213 */ MCD_OPC_Decode, 28, 223, 1, // Opcode: ADCSWr >+/* 31217 */ MCD_OPC_FilterValue, 9, 232, 36, // Skip to: 40669 >+/* 31221 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31224 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31245 >+/* 31228 */ MCD_OPC_CheckField, 21, 1, 0, 219, 36, // Skip to: 40669 >+/* 31234 */ MCD_OPC_CheckField, 4, 1, 0, 213, 36, // Skip to: 40669 >+/* 31240 */ MCD_OPC_Decode, 134, 1, 232, 1, // Opcode: CCMNWr >+/* 31245 */ MCD_OPC_FilterValue, 2, 204, 36, // Skip to: 40669 >+/* 31249 */ MCD_OPC_CheckField, 21, 1, 0, 198, 36, // Skip to: 40669 >+/* 31255 */ MCD_OPC_CheckField, 4, 1, 0, 192, 36, // Skip to: 40669 >+/* 31261 */ MCD_OPC_Decode, 133, 1, 233, 1, // Opcode: CCMNWi >+/* 31266 */ MCD_OPC_FilterValue, 2, 132, 0, // Skip to: 31402 >+/* 31270 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 31273 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31282 >+/* 31277 */ MCD_OPC_Decode, 138, 8, 212, 1, // Opcode: LDRXl >+/* 31282 */ MCD_OPC_FilterValue, 2, 167, 36, // Skip to: 40669 >+/* 31286 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31289 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 31345 >+/* 31293 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 31296 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31311 >+/* 31300 */ MCD_OPC_CheckField, 12, 4, 0, 147, 36, // Skip to: 40669 >+/* 31306 */ MCD_OPC_Decode, 254, 9, 223, 1, // Opcode: SBCWr >+/* 31311 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31320 >+/* 31315 */ MCD_OPC_Decode, 136, 2, 224, 1, // Opcode: CSINVWr >+/* 31320 */ MCD_OPC_FilterValue, 6, 129, 36, // Skip to: 40669 >+/* 31324 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... >+/* 31327 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31336 >+/* 31331 */ MCD_OPC_Decode, 162, 9, 234, 1, // Opcode: RBITWr >+/* 31336 */ MCD_OPC_FilterValue, 1, 113, 36, // Skip to: 40669 >+/* 31340 */ MCD_OPC_Decode, 150, 1, 234, 1, // Opcode: CLZWr >+/* 31345 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 31386 >+/* 31349 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 31352 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31361 >+/* 31356 */ MCD_OPC_Decode, 138, 2, 224, 1, // Opcode: CSNEGWr >+/* 31361 */ MCD_OPC_FilterValue, 6, 88, 36, // Skip to: 40669 >+/* 31365 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... >+/* 31368 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31377 >+/* 31372 */ MCD_OPC_Decode, 168, 9, 234, 1, // Opcode: REV16Wr >+/* 31377 */ MCD_OPC_FilterValue, 1, 72, 36, // Skip to: 40669 >+/* 31381 */ MCD_OPC_Decode, 142, 1, 234, 1, // Opcode: CLSWr >+/* 31386 */ MCD_OPC_FilterValue, 2, 63, 36, // Skip to: 40669 >+/* 31390 */ MCD_OPC_CheckField, 12, 12, 128, 24, 56, 36, // Skip to: 40669 >+/* 31397 */ MCD_OPC_Decode, 183, 9, 234, 1, // Opcode: REVWr >+/* 31402 */ MCD_OPC_FilterValue, 3, 225, 1, // Skip to: 31887 >+/* 31406 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 31409 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 31502 >+/* 31413 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31416 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31431 >+/* 31420 */ MCD_OPC_CheckField, 21, 1, 0, 27, 36, // Skip to: 40669 >+/* 31426 */ MCD_OPC_Decode, 137, 15, 226, 1, // Opcode: STURHHi >+/* 31431 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31446 >+/* 31435 */ MCD_OPC_CheckField, 21, 1, 0, 12, 36, // Skip to: 40669 >+/* 31441 */ MCD_OPC_Decode, 228, 14, 226, 1, // Opcode: STRHHpost >+/* 31446 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31487 >+/* 31450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31453 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31462 >+/* 31457 */ MCD_OPC_Decode, 131, 15, 226, 1, // Opcode: STTRHi >+/* 31462 */ MCD_OPC_FilterValue, 1, 243, 35, // Skip to: 40669 >+/* 31466 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31469 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31478 >+/* 31473 */ MCD_OPC_Decode, 230, 14, 227, 1, // Opcode: STRHHroW >+/* 31478 */ MCD_OPC_FilterValue, 3, 227, 35, // Skip to: 40669 >+/* 31482 */ MCD_OPC_Decode, 231, 14, 228, 1, // Opcode: STRHHroX >+/* 31487 */ MCD_OPC_FilterValue, 3, 218, 35, // Skip to: 40669 >+/* 31491 */ MCD_OPC_CheckField, 21, 1, 0, 212, 35, // Skip to: 40669 >+/* 31497 */ MCD_OPC_Decode, 229, 14, 226, 1, // Opcode: STRHHpre >+/* 31502 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 31595 >+/* 31506 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31509 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31524 >+/* 31513 */ MCD_OPC_CheckField, 21, 1, 0, 190, 35, // Skip to: 40669 >+/* 31519 */ MCD_OPC_Decode, 156, 8, 226, 1, // Opcode: LDURHHi >+/* 31524 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31539 >+/* 31528 */ MCD_OPC_CheckField, 21, 1, 0, 175, 35, // Skip to: 40669 >+/* 31534 */ MCD_OPC_Decode, 212, 7, 226, 1, // Opcode: LDRHHpost >+/* 31539 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31580 >+/* 31543 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31546 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31555 >+/* 31550 */ MCD_OPC_Decode, 145, 8, 226, 1, // Opcode: LDTRHi >+/* 31555 */ MCD_OPC_FilterValue, 1, 150, 35, // Skip to: 40669 >+/* 31559 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31562 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31571 >+/* 31566 */ MCD_OPC_Decode, 214, 7, 227, 1, // Opcode: LDRHHroW >+/* 31571 */ MCD_OPC_FilterValue, 3, 134, 35, // Skip to: 40669 >+/* 31575 */ MCD_OPC_Decode, 215, 7, 228, 1, // Opcode: LDRHHroX >+/* 31580 */ MCD_OPC_FilterValue, 3, 125, 35, // Skip to: 40669 >+/* 31584 */ MCD_OPC_CheckField, 21, 1, 0, 119, 35, // Skip to: 40669 >+/* 31590 */ MCD_OPC_Decode, 213, 7, 226, 1, // Opcode: LDRHHpre >+/* 31595 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31688 >+/* 31599 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31602 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31617 >+/* 31606 */ MCD_OPC_CheckField, 21, 1, 0, 97, 35, // Skip to: 40669 >+/* 31612 */ MCD_OPC_Decode, 162, 8, 226, 1, // Opcode: LDURSHXi >+/* 31617 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31632 >+/* 31621 */ MCD_OPC_CheckField, 21, 1, 0, 82, 35, // Skip to: 40669 >+/* 31627 */ MCD_OPC_Decode, 243, 7, 226, 1, // Opcode: LDRSHXpost >+/* 31632 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31673 >+/* 31636 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31639 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31648 >+/* 31643 */ MCD_OPC_Decode, 149, 8, 226, 1, // Opcode: LDTRSHXi >+/* 31648 */ MCD_OPC_FilterValue, 1, 57, 35, // Skip to: 40669 >+/* 31652 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31655 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31664 >+/* 31659 */ MCD_OPC_Decode, 245, 7, 229, 1, // Opcode: LDRSHXroW >+/* 31664 */ MCD_OPC_FilterValue, 3, 41, 35, // Skip to: 40669 >+/* 31668 */ MCD_OPC_Decode, 246, 7, 230, 1, // Opcode: LDRSHXroX >+/* 31673 */ MCD_OPC_FilterValue, 3, 32, 35, // Skip to: 40669 >+/* 31677 */ MCD_OPC_CheckField, 21, 1, 0, 26, 35, // Skip to: 40669 >+/* 31683 */ MCD_OPC_Decode, 244, 7, 226, 1, // Opcode: LDRSHXpre >+/* 31688 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31781 >+/* 31692 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31695 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31710 >+/* 31699 */ MCD_OPC_CheckField, 21, 1, 0, 4, 35, // Skip to: 40669 >+/* 31705 */ MCD_OPC_Decode, 161, 8, 226, 1, // Opcode: LDURSHWi >+/* 31710 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31725 >+/* 31714 */ MCD_OPC_CheckField, 21, 1, 0, 245, 34, // Skip to: 40669 >+/* 31720 */ MCD_OPC_Decode, 238, 7, 226, 1, // Opcode: LDRSHWpost >+/* 31725 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31766 >+/* 31729 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 31732 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31741 >+/* 31736 */ MCD_OPC_Decode, 148, 8, 226, 1, // Opcode: LDTRSHWi >+/* 31741 */ MCD_OPC_FilterValue, 1, 220, 34, // Skip to: 40669 >+/* 31745 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 31748 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31757 >+/* 31752 */ MCD_OPC_Decode, 240, 7, 227, 1, // Opcode: LDRSHWroW >+/* 31757 */ MCD_OPC_FilterValue, 3, 204, 34, // Skip to: 40669 >+/* 31761 */ MCD_OPC_Decode, 241, 7, 228, 1, // Opcode: LDRSHWroX >+/* 31766 */ MCD_OPC_FilterValue, 3, 195, 34, // Skip to: 40669 >+/* 31770 */ MCD_OPC_CheckField, 21, 1, 0, 189, 34, // Skip to: 40669 >+/* 31776 */ MCD_OPC_Decode, 239, 7, 226, 1, // Opcode: LDRSHWpre >+/* 31781 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31790 >+/* 31785 */ MCD_OPC_Decode, 232, 14, 231, 1, // Opcode: STRHHui >+/* 31790 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31799 >+/* 31794 */ MCD_OPC_Decode, 216, 7, 231, 1, // Opcode: LDRHHui >+/* 31799 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31808 >+/* 31803 */ MCD_OPC_Decode, 247, 7, 231, 1, // Opcode: LDRSHXui >+/* 31808 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31817 >+/* 31812 */ MCD_OPC_Decode, 242, 7, 231, 1, // Opcode: LDRSHWui >+/* 31817 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 31838 >+/* 31821 */ MCD_OPC_CheckField, 21, 1, 0, 138, 34, // Skip to: 40669 >+/* 31827 */ MCD_OPC_CheckField, 10, 6, 0, 132, 34, // Skip to: 40669 >+/* 31833 */ MCD_OPC_Decode, 252, 9, 223, 1, // Opcode: SBCSWr >+/* 31838 */ MCD_OPC_FilterValue, 9, 123, 34, // Skip to: 40669 >+/* 31842 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31845 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31866 >+/* 31849 */ MCD_OPC_CheckField, 21, 1, 0, 110, 34, // Skip to: 40669 >+/* 31855 */ MCD_OPC_CheckField, 4, 1, 0, 104, 34, // Skip to: 40669 >+/* 31861 */ MCD_OPC_Decode, 138, 1, 232, 1, // Opcode: CCMPWr >+/* 31866 */ MCD_OPC_FilterValue, 2, 95, 34, // Skip to: 40669 >+/* 31870 */ MCD_OPC_CheckField, 21, 1, 0, 89, 34, // Skip to: 40669 >+/* 31876 */ MCD_OPC_CheckField, 4, 1, 0, 83, 34, // Skip to: 40669 >+/* 31882 */ MCD_OPC_Decode, 137, 1, 233, 1, // Opcode: CCMPWi >+/* 31887 */ MCD_OPC_FilterValue, 4, 62, 1, // Skip to: 32209 >+/* 31891 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 31894 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31903 >+/* 31898 */ MCD_OPC_Decode, 248, 7, 212, 1, // Opcode: LDRSWl >+/* 31903 */ MCD_OPC_FilterValue, 2, 190, 0, // Skip to: 32097 >+/* 31907 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 31910 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 31955 >+/* 31914 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 31917 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31931 >+/* 31921 */ MCD_OPC_CheckField, 12, 4, 0, 38, 34, // Skip to: 40669 >+/* 31927 */ MCD_OPC_Decode, 31, 235, 1, // Opcode: ADCXr >+/* 31931 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31940 >+/* 31935 */ MCD_OPC_Decode, 133, 2, 236, 1, // Opcode: CSELXr >+/* 31940 */ MCD_OPC_FilterValue, 6, 21, 34, // Skip to: 40669 >+/* 31944 */ MCD_OPC_CheckField, 12, 4, 2, 15, 34, // Skip to: 40669 >+/* 31950 */ MCD_OPC_Decode, 175, 8, 235, 1, // Opcode: LSLVXr >+/* 31955 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 31986 >+/* 31959 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 31962 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31971 >+/* 31966 */ MCD_OPC_Decode, 135, 2, 236, 1, // Opcode: CSINCXr >+/* 31971 */ MCD_OPC_FilterValue, 6, 246, 33, // Skip to: 40669 >+/* 31975 */ MCD_OPC_CheckField, 12, 4, 2, 240, 33, // Skip to: 40669 >+/* 31981 */ MCD_OPC_Decode, 177, 8, 235, 1, // Opcode: LSRVXr >+/* 31986 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 32022 >+/* 31990 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 31993 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32008 >+/* 31997 */ MCD_OPC_CheckField, 21, 3, 6, 218, 33, // Skip to: 40669 >+/* 32003 */ MCD_OPC_Decode, 179, 16, 235, 1, // Opcode: UDIVXr >+/* 32008 */ MCD_OPC_FilterValue, 2, 209, 33, // Skip to: 40669 >+/* 32012 */ MCD_OPC_CheckField, 21, 3, 6, 203, 33, // Skip to: 40669 >+/* 32018 */ MCD_OPC_Decode, 100, 235, 1, // Opcode: ASRVXr >+/* 32022 */ MCD_OPC_FilterValue, 3, 195, 33, // Skip to: 40669 >+/* 32026 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 32029 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32044 >+/* 32033 */ MCD_OPC_CheckField, 21, 3, 6, 182, 33, // Skip to: 40669 >+/* 32039 */ MCD_OPC_Decode, 149, 10, 235, 1, // Opcode: SDIVXr >+/* 32044 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32059 >+/* 32048 */ MCD_OPC_CheckField, 21, 3, 6, 167, 33, // Skip to: 40669 >+/* 32054 */ MCD_OPC_Decode, 186, 9, 235, 1, // Opcode: RORVXr >+/* 32059 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 32078 >+/* 32063 */ MCD_OPC_CheckPredicate, 2, 154, 33, // Skip to: 40669 >+/* 32067 */ MCD_OPC_CheckField, 21, 3, 6, 148, 33, // Skip to: 40669 >+/* 32073 */ MCD_OPC_Decode, 131, 2, 237, 1, // Opcode: CRC32Xrr >+/* 32078 */ MCD_OPC_FilterValue, 5, 139, 33, // Skip to: 40669 >+/* 32082 */ MCD_OPC_CheckPredicate, 2, 135, 33, // Skip to: 40669 >+/* 32086 */ MCD_OPC_CheckField, 21, 3, 6, 129, 33, // Skip to: 40669 >+/* 32092 */ MCD_OPC_Decode, 128, 2, 237, 1, // Opcode: CRC32CXrr >+/* 32097 */ MCD_OPC_FilterValue, 3, 120, 33, // Skip to: 40669 >+/* 32101 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 32104 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 32129 >+/* 32108 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 32111 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32120 >+/* 32115 */ MCD_OPC_Decode, 179, 8, 238, 1, // Opcode: MADDXrrr >+/* 32120 */ MCD_OPC_FilterValue, 1, 97, 33, // Skip to: 40669 >+/* 32124 */ MCD_OPC_Decode, 228, 8, 238, 1, // Opcode: MSUBXrrr >+/* 32129 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 32154 >+/* 32133 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 32136 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32145 >+/* 32140 */ MCD_OPC_Decode, 202, 10, 239, 1, // Opcode: SMADDLrrr >+/* 32145 */ MCD_OPC_FilterValue, 1, 72, 33, // Skip to: 40669 >+/* 32149 */ MCD_OPC_Decode, 135, 11, 239, 1, // Opcode: SMSUBLrrr >+/* 32154 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32169 >+/* 32158 */ MCD_OPC_CheckField, 15, 1, 0, 57, 33, // Skip to: 40669 >+/* 32164 */ MCD_OPC_Decode, 136, 11, 235, 1, // Opcode: SMULHrr >+/* 32169 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 32194 >+/* 32173 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 32176 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32185 >+/* 32180 */ MCD_OPC_Decode, 194, 16, 239, 1, // Opcode: UMADDLrrr >+/* 32185 */ MCD_OPC_FilterValue, 1, 32, 33, // Skip to: 40669 >+/* 32189 */ MCD_OPC_Decode, 253, 16, 239, 1, // Opcode: UMSUBLrrr >+/* 32194 */ MCD_OPC_FilterValue, 6, 23, 33, // Skip to: 40669 >+/* 32198 */ MCD_OPC_CheckField, 15, 1, 0, 17, 33, // Skip to: 40669 >+/* 32204 */ MCD_OPC_Decode, 254, 16, 235, 1, // Opcode: UMULHrr >+/* 32209 */ MCD_OPC_FilterValue, 5, 122, 1, // Skip to: 32591 >+/* 32213 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 32216 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32309 >+/* 32220 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32223 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32238 >+/* 32227 */ MCD_OPC_CheckField, 21, 1, 0, 244, 32, // Skip to: 40669 >+/* 32233 */ MCD_OPC_Decode, 141, 15, 226, 1, // Opcode: STURWi >+/* 32238 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32253 >+/* 32242 */ MCD_OPC_CheckField, 21, 1, 0, 229, 32, // Skip to: 40669 >+/* 32248 */ MCD_OPC_Decode, 248, 14, 226, 1, // Opcode: STRWpost >+/* 32253 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32294 >+/* 32257 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 32260 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32269 >+/* 32264 */ MCD_OPC_Decode, 132, 15, 226, 1, // Opcode: STTRWi >+/* 32269 */ MCD_OPC_FilterValue, 1, 204, 32, // Skip to: 40669 >+/* 32273 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32276 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32285 >+/* 32280 */ MCD_OPC_Decode, 250, 14, 227, 1, // Opcode: STRWroW >+/* 32285 */ MCD_OPC_FilterValue, 3, 188, 32, // Skip to: 40669 >+/* 32289 */ MCD_OPC_Decode, 251, 14, 228, 1, // Opcode: STRWroX >+/* 32294 */ MCD_OPC_FilterValue, 3, 179, 32, // Skip to: 40669 >+/* 32298 */ MCD_OPC_CheckField, 21, 1, 0, 173, 32, // Skip to: 40669 >+/* 32304 */ MCD_OPC_Decode, 249, 14, 226, 1, // Opcode: STRWpre >+/* 32309 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32402 >+/* 32313 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32316 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32331 >+/* 32320 */ MCD_OPC_CheckField, 21, 1, 0, 151, 32, // Skip to: 40669 >+/* 32326 */ MCD_OPC_Decode, 165, 8, 226, 1, // Opcode: LDURWi >+/* 32331 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32346 >+/* 32335 */ MCD_OPC_CheckField, 21, 1, 0, 136, 32, // Skip to: 40669 >+/* 32341 */ MCD_OPC_Decode, 133, 8, 226, 1, // Opcode: LDRWpost >+/* 32346 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32387 >+/* 32350 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 32353 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32362 >+/* 32357 */ MCD_OPC_Decode, 151, 8, 226, 1, // Opcode: LDTRWi >+/* 32362 */ MCD_OPC_FilterValue, 1, 111, 32, // Skip to: 40669 >+/* 32366 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32369 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32378 >+/* 32373 */ MCD_OPC_Decode, 135, 8, 227, 1, // Opcode: LDRWroW >+/* 32378 */ MCD_OPC_FilterValue, 3, 95, 32, // Skip to: 40669 >+/* 32382 */ MCD_OPC_Decode, 136, 8, 228, 1, // Opcode: LDRWroX >+/* 32387 */ MCD_OPC_FilterValue, 3, 86, 32, // Skip to: 40669 >+/* 32391 */ MCD_OPC_CheckField, 21, 1, 0, 80, 32, // Skip to: 40669 >+/* 32397 */ MCD_OPC_Decode, 134, 8, 226, 1, // Opcode: LDRWpre >+/* 32402 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 32495 >+/* 32406 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32409 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32424 >+/* 32413 */ MCD_OPC_CheckField, 21, 1, 0, 58, 32, // Skip to: 40669 >+/* 32419 */ MCD_OPC_Decode, 163, 8, 226, 1, // Opcode: LDURSWi >+/* 32424 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32439 >+/* 32428 */ MCD_OPC_CheckField, 21, 1, 0, 43, 32, // Skip to: 40669 >+/* 32434 */ MCD_OPC_Decode, 249, 7, 226, 1, // Opcode: LDRSWpost >+/* 32439 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32480 >+/* 32443 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 32446 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32455 >+/* 32450 */ MCD_OPC_Decode, 150, 8, 226, 1, // Opcode: LDTRSWi >+/* 32455 */ MCD_OPC_FilterValue, 1, 18, 32, // Skip to: 40669 >+/* 32459 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32462 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32471 >+/* 32466 */ MCD_OPC_Decode, 251, 7, 229, 1, // Opcode: LDRSWroW >+/* 32471 */ MCD_OPC_FilterValue, 3, 2, 32, // Skip to: 40669 >+/* 32475 */ MCD_OPC_Decode, 252, 7, 230, 1, // Opcode: LDRSWroX >+/* 32480 */ MCD_OPC_FilterValue, 3, 249, 31, // Skip to: 40669 >+/* 32484 */ MCD_OPC_CheckField, 21, 1, 0, 243, 31, // Skip to: 40669 >+/* 32490 */ MCD_OPC_Decode, 250, 7, 226, 1, // Opcode: LDRSWpre >+/* 32495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32504 >+/* 32499 */ MCD_OPC_Decode, 252, 14, 231, 1, // Opcode: STRWui >+/* 32504 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 32513 >+/* 32508 */ MCD_OPC_Decode, 137, 8, 231, 1, // Opcode: LDRWui >+/* 32513 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 32522 >+/* 32517 */ MCD_OPC_Decode, 253, 7, 231, 1, // Opcode: LDRSWui >+/* 32522 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 32542 >+/* 32526 */ MCD_OPC_CheckField, 21, 1, 0, 201, 31, // Skip to: 40669 >+/* 32532 */ MCD_OPC_CheckField, 10, 6, 0, 195, 31, // Skip to: 40669 >+/* 32538 */ MCD_OPC_Decode, 29, 235, 1, // Opcode: ADCSXr >+/* 32542 */ MCD_OPC_FilterValue, 9, 187, 31, // Skip to: 40669 >+/* 32546 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32549 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 32570 >+/* 32553 */ MCD_OPC_CheckField, 21, 1, 0, 174, 31, // Skip to: 40669 >+/* 32559 */ MCD_OPC_CheckField, 4, 1, 0, 168, 31, // Skip to: 40669 >+/* 32565 */ MCD_OPC_Decode, 136, 1, 240, 1, // Opcode: CCMNXr >+/* 32570 */ MCD_OPC_FilterValue, 2, 159, 31, // Skip to: 40669 >+/* 32574 */ MCD_OPC_CheckField, 21, 1, 0, 153, 31, // Skip to: 40669 >+/* 32580 */ MCD_OPC_CheckField, 4, 1, 0, 147, 31, // Skip to: 40669 >+/* 32586 */ MCD_OPC_Decode, 135, 1, 241, 1, // Opcode: CCMNXi >+/* 32591 */ MCD_OPC_FilterValue, 6, 148, 0, // Skip to: 32743 >+/* 32595 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 32598 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32607 >+/* 32602 */ MCD_OPC_Decode, 151, 9, 242, 1, // Opcode: PRFMl >+/* 32607 */ MCD_OPC_FilterValue, 2, 122, 31, // Skip to: 40669 >+/* 32611 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32614 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 32670 >+/* 32618 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 32621 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32636 >+/* 32625 */ MCD_OPC_CheckField, 12, 4, 0, 102, 31, // Skip to: 40669 >+/* 32631 */ MCD_OPC_Decode, 255, 9, 235, 1, // Opcode: SBCXr >+/* 32636 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32645 >+/* 32640 */ MCD_OPC_Decode, 137, 2, 236, 1, // Opcode: CSINVXr >+/* 32645 */ MCD_OPC_FilterValue, 6, 84, 31, // Skip to: 40669 >+/* 32649 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... >+/* 32652 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32661 >+/* 32656 */ MCD_OPC_Decode, 163, 9, 243, 1, // Opcode: RBITXr >+/* 32661 */ MCD_OPC_FilterValue, 1, 68, 31, // Skip to: 40669 >+/* 32665 */ MCD_OPC_Decode, 151, 1, 243, 1, // Opcode: CLZXr >+/* 32670 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 32711 >+/* 32674 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 32677 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32686 >+/* 32681 */ MCD_OPC_Decode, 139, 2, 236, 1, // Opcode: CSNEGXr >+/* 32686 */ MCD_OPC_FilterValue, 6, 43, 31, // Skip to: 40669 >+/* 32690 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... >+/* 32693 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32702 >+/* 32697 */ MCD_OPC_Decode, 169, 9, 243, 1, // Opcode: REV16Xr >+/* 32702 */ MCD_OPC_FilterValue, 1, 27, 31, // Skip to: 40669 >+/* 32706 */ MCD_OPC_Decode, 143, 1, 243, 1, // Opcode: CLSXr >+/* 32711 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 32727 >+/* 32715 */ MCD_OPC_CheckField, 12, 12, 128, 24, 11, 31, // Skip to: 40669 >+/* 32722 */ MCD_OPC_Decode, 172, 9, 243, 1, // Opcode: REV32Xr >+/* 32727 */ MCD_OPC_FilterValue, 3, 2, 31, // Skip to: 40669 >+/* 32731 */ MCD_OPC_CheckField, 12, 12, 128, 24, 251, 30, // Skip to: 40669 >+/* 32738 */ MCD_OPC_Decode, 184, 9, 243, 1, // Opcode: REVXr >+/* 32743 */ MCD_OPC_FilterValue, 7, 242, 30, // Skip to: 40669 >+/* 32747 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 32750 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32843 >+/* 32754 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32757 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32772 >+/* 32761 */ MCD_OPC_CheckField, 21, 1, 0, 222, 30, // Skip to: 40669 >+/* 32767 */ MCD_OPC_Decode, 142, 15, 226, 1, // Opcode: STURXi >+/* 32772 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32787 >+/* 32776 */ MCD_OPC_CheckField, 21, 1, 0, 207, 30, // Skip to: 40669 >+/* 32782 */ MCD_OPC_Decode, 253, 14, 226, 1, // Opcode: STRXpost >+/* 32787 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32828 >+/* 32791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 32794 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32803 >+/* 32798 */ MCD_OPC_Decode, 133, 15, 226, 1, // Opcode: STTRXi >+/* 32803 */ MCD_OPC_FilterValue, 1, 182, 30, // Skip to: 40669 >+/* 32807 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32810 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32819 >+/* 32814 */ MCD_OPC_Decode, 255, 14, 229, 1, // Opcode: STRXroW >+/* 32819 */ MCD_OPC_FilterValue, 3, 166, 30, // Skip to: 40669 >+/* 32823 */ MCD_OPC_Decode, 128, 15, 230, 1, // Opcode: STRXroX >+/* 32828 */ MCD_OPC_FilterValue, 3, 157, 30, // Skip to: 40669 >+/* 32832 */ MCD_OPC_CheckField, 21, 1, 0, 151, 30, // Skip to: 40669 >+/* 32838 */ MCD_OPC_Decode, 254, 14, 226, 1, // Opcode: STRXpre >+/* 32843 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32936 >+/* 32847 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32850 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32865 >+/* 32854 */ MCD_OPC_CheckField, 21, 1, 0, 129, 30, // Skip to: 40669 >+/* 32860 */ MCD_OPC_Decode, 166, 8, 226, 1, // Opcode: LDURXi >+/* 32865 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32880 >+/* 32869 */ MCD_OPC_CheckField, 21, 1, 0, 114, 30, // Skip to: 40669 >+/* 32875 */ MCD_OPC_Decode, 139, 8, 226, 1, // Opcode: LDRXpost >+/* 32880 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32921 >+/* 32884 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 32887 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32896 >+/* 32891 */ MCD_OPC_Decode, 152, 8, 226, 1, // Opcode: LDTRXi >+/* 32896 */ MCD_OPC_FilterValue, 1, 89, 30, // Skip to: 40669 >+/* 32900 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32903 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32912 >+/* 32907 */ MCD_OPC_Decode, 141, 8, 229, 1, // Opcode: LDRXroW >+/* 32912 */ MCD_OPC_FilterValue, 3, 73, 30, // Skip to: 40669 >+/* 32916 */ MCD_OPC_Decode, 142, 8, 230, 1, // Opcode: LDRXroX >+/* 32921 */ MCD_OPC_FilterValue, 3, 64, 30, // Skip to: 40669 >+/* 32925 */ MCD_OPC_CheckField, 21, 1, 0, 58, 30, // Skip to: 40669 >+/* 32931 */ MCD_OPC_Decode, 140, 8, 226, 1, // Opcode: LDRXpre >+/* 32936 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 32995 >+/* 32940 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 32943 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32958 >+/* 32947 */ MCD_OPC_CheckField, 21, 1, 0, 36, 30, // Skip to: 40669 >+/* 32953 */ MCD_OPC_Decode, 155, 9, 226, 1, // Opcode: PRFUMi >+/* 32958 */ MCD_OPC_FilterValue, 2, 27, 30, // Skip to: 40669 >+/* 32962 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 32965 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32980 >+/* 32969 */ MCD_OPC_CheckField, 21, 1, 1, 14, 30, // Skip to: 40669 >+/* 32975 */ MCD_OPC_Decode, 152, 9, 244, 1, // Opcode: PRFMroW >+/* 32980 */ MCD_OPC_FilterValue, 3, 5, 30, // Skip to: 40669 >+/* 32984 */ MCD_OPC_CheckField, 21, 1, 1, 255, 29, // Skip to: 40669 >+/* 32990 */ MCD_OPC_Decode, 153, 9, 245, 1, // Opcode: PRFMroX >+/* 32995 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 33004 >+/* 32999 */ MCD_OPC_Decode, 129, 15, 231, 1, // Opcode: STRXui >+/* 33004 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 33013 >+/* 33008 */ MCD_OPC_Decode, 143, 8, 231, 1, // Opcode: LDRXui >+/* 33013 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 33022 >+/* 33017 */ MCD_OPC_Decode, 154, 9, 231, 1, // Opcode: PRFMui >+/* 33022 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 33043 >+/* 33026 */ MCD_OPC_CheckField, 21, 1, 0, 213, 29, // Skip to: 40669 >+/* 33032 */ MCD_OPC_CheckField, 10, 6, 0, 207, 29, // Skip to: 40669 >+/* 33038 */ MCD_OPC_Decode, 253, 9, 235, 1, // Opcode: SBCSXr >+/* 33043 */ MCD_OPC_FilterValue, 9, 198, 29, // Skip to: 40669 >+/* 33047 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 33050 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 33071 >+/* 33054 */ MCD_OPC_CheckField, 21, 1, 0, 185, 29, // Skip to: 40669 >+/* 33060 */ MCD_OPC_CheckField, 4, 1, 0, 179, 29, // Skip to: 40669 >+/* 33066 */ MCD_OPC_Decode, 140, 1, 240, 1, // Opcode: CCMPXr >+/* 33071 */ MCD_OPC_FilterValue, 2, 170, 29, // Skip to: 40669 >+/* 33075 */ MCD_OPC_CheckField, 21, 1, 0, 164, 29, // Skip to: 40669 >+/* 33081 */ MCD_OPC_CheckField, 4, 1, 0, 158, 29, // Skip to: 40669 >+/* 33087 */ MCD_OPC_Decode, 139, 1, 241, 1, // Opcode: CCMPXi >+/* 33092 */ MCD_OPC_FilterValue, 7, 149, 29, // Skip to: 40669 >+/* 33096 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... >+/* 33099 */ MCD_OPC_FilterValue, 0, 8, 6, // Skip to: 34647 >+/* 33103 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 33106 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 33115 >+/* 33110 */ MCD_OPC_Decode, 254, 7, 246, 1, // Opcode: LDRSl >+/* 33115 */ MCD_OPC_FilterValue, 2, 109, 5, // Skip to: 34508 >+/* 33119 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 33122 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 33181 >+/* 33126 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... >+/* 33129 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33142 >+/* 33133 */ MCD_OPC_CheckPredicate, 3, 108, 29, // Skip to: 40669 >+/* 33137 */ MCD_OPC_Decode, 131, 10, 247, 1, // Opcode: SCVTFSWSri >+/* 33142 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33155 >+/* 33146 */ MCD_OPC_CheckPredicate, 3, 95, 29, // Skip to: 40669 >+/* 33150 */ MCD_OPC_Decode, 161, 16, 247, 1, // Opcode: UCVTFSWSri >+/* 33155 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33168 >+/* 33159 */ MCD_OPC_CheckPredicate, 3, 82, 29, // Skip to: 40669 >+/* 33163 */ MCD_OPC_Decode, 224, 3, 248, 1, // Opcode: FCVTZSSWSri >+/* 33168 */ MCD_OPC_FilterValue, 51, 73, 29, // Skip to: 40669 >+/* 33172 */ MCD_OPC_CheckPredicate, 3, 69, 29, // Skip to: 40669 >+/* 33176 */ MCD_OPC_Decode, 253, 3, 248, 1, // Opcode: FCVTZUSWSri >+/* 33181 */ MCD_OPC_FilterValue, 1, 125, 2, // Skip to: 33822 >+/* 33185 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 33188 */ MCD_OPC_FilterValue, 0, 204, 1, // Skip to: 33652 >+/* 33192 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 33195 */ MCD_OPC_FilterValue, 0, 178, 1, // Skip to: 33633 >+/* 33199 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 33202 */ MCD_OPC_FilterValue, 0, 185, 0, // Skip to: 33391 >+/* 33206 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 33209 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33222 >+/* 33213 */ MCD_OPC_CheckPredicate, 3, 28, 29, // Skip to: 40669 >+/* 33217 */ MCD_OPC_Decode, 179, 3, 249, 1, // Opcode: FCVTNSUWSr >+/* 33222 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33235 >+/* 33226 */ MCD_OPC_CheckPredicate, 3, 15, 29, // Skip to: 40669 >+/* 33230 */ MCD_OPC_Decode, 188, 3, 249, 1, // Opcode: FCVTNUUWSr >+/* 33235 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33248 >+/* 33239 */ MCD_OPC_CheckPredicate, 3, 2, 29, // Skip to: 40669 >+/* 33243 */ MCD_OPC_Decode, 135, 10, 250, 1, // Opcode: SCVTFUWSri >+/* 33248 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33261 >+/* 33252 */ MCD_OPC_CheckPredicate, 3, 245, 28, // Skip to: 40669 >+/* 33256 */ MCD_OPC_Decode, 165, 16, 250, 1, // Opcode: UCVTFUWSri >+/* 33261 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33274 >+/* 33265 */ MCD_OPC_CheckPredicate, 3, 232, 28, // Skip to: 40669 >+/* 33269 */ MCD_OPC_Decode, 135, 3, 249, 1, // Opcode: FCVTASUWSr >+/* 33274 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33287 >+/* 33278 */ MCD_OPC_CheckPredicate, 3, 219, 28, // Skip to: 40669 >+/* 33282 */ MCD_OPC_Decode, 144, 3, 249, 1, // Opcode: FCVTAUUWSr >+/* 33287 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33300 >+/* 33291 */ MCD_OPC_CheckPredicate, 3, 206, 28, // Skip to: 40669 >+/* 33295 */ MCD_OPC_Decode, 224, 4, 249, 1, // Opcode: FMOVSWr >+/* 33300 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33313 >+/* 33304 */ MCD_OPC_CheckPredicate, 3, 193, 28, // Skip to: 40669 >+/* 33308 */ MCD_OPC_Decode, 227, 4, 250, 1, // Opcode: FMOVWSr >+/* 33313 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33326 >+/* 33317 */ MCD_OPC_CheckPredicate, 3, 180, 28, // Skip to: 40669 >+/* 33321 */ MCD_OPC_Decode, 201, 3, 249, 1, // Opcode: FCVTPSUWSr >+/* 33326 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 33339 >+/* 33330 */ MCD_OPC_CheckPredicate, 3, 167, 28, // Skip to: 40669 >+/* 33334 */ MCD_OPC_Decode, 210, 3, 249, 1, // Opcode: FCVTPUUWSr >+/* 33339 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33352 >+/* 33343 */ MCD_OPC_CheckPredicate, 3, 154, 28, // Skip to: 40669 >+/* 33347 */ MCD_OPC_Decode, 161, 3, 249, 1, // Opcode: FCVTMSUWSr >+/* 33352 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 33365 >+/* 33356 */ MCD_OPC_CheckPredicate, 3, 141, 28, // Skip to: 40669 >+/* 33360 */ MCD_OPC_Decode, 170, 3, 249, 1, // Opcode: FCVTMUUWSr >+/* 33365 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 33378 >+/* 33369 */ MCD_OPC_CheckPredicate, 3, 128, 28, // Skip to: 40669 >+/* 33373 */ MCD_OPC_Decode, 228, 3, 249, 1, // Opcode: FCVTZSUWSr >+/* 33378 */ MCD_OPC_FilterValue, 25, 119, 28, // Skip to: 40669 >+/* 33382 */ MCD_OPC_CheckPredicate, 3, 115, 28, // Skip to: 40669 >+/* 33386 */ MCD_OPC_Decode, 129, 4, 249, 1, // Opcode: FCVTZUUWSr >+/* 33391 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 33450 >+/* 33395 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... >+/* 33398 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33411 >+/* 33402 */ MCD_OPC_CheckPredicate, 3, 95, 28, // Skip to: 40669 >+/* 33406 */ MCD_OPC_Decode, 131, 3, 251, 1, // Opcode: FCMPSrr >+/* 33411 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33424 >+/* 33415 */ MCD_OPC_CheckPredicate, 3, 82, 28, // Skip to: 40669 >+/* 33419 */ MCD_OPC_Decode, 130, 3, 252, 1, // Opcode: FCMPSri >+/* 33424 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33437 >+/* 33428 */ MCD_OPC_CheckPredicate, 3, 69, 28, // Skip to: 40669 >+/* 33432 */ MCD_OPC_Decode, 129, 3, 251, 1, // Opcode: FCMPESrr >+/* 33437 */ MCD_OPC_FilterValue, 24, 60, 28, // Skip to: 40669 >+/* 33441 */ MCD_OPC_CheckPredicate, 3, 56, 28, // Skip to: 40669 >+/* 33445 */ MCD_OPC_Decode, 128, 3, 252, 1, // Opcode: FCMPESri >+/* 33450 */ MCD_OPC_FilterValue, 2, 81, 0, // Skip to: 33535 >+/* 33454 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 33457 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33470 >+/* 33461 */ MCD_OPC_CheckPredicate, 3, 36, 28, // Skip to: 40669 >+/* 33465 */ MCD_OPC_Decode, 226, 4, 253, 1, // Opcode: FMOVSr >+/* 33470 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33483 >+/* 33474 */ MCD_OPC_CheckPredicate, 3, 23, 28, // Skip to: 40669 >+/* 33478 */ MCD_OPC_Decode, 128, 5, 253, 1, // Opcode: FNEGSr >+/* 33483 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33496 >+/* 33487 */ MCD_OPC_CheckPredicate, 3, 10, 28, // Skip to: 40669 >+/* 33491 */ MCD_OPC_Decode, 166, 5, 253, 1, // Opcode: FRINTNSr >+/* 33496 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33509 >+/* 33500 */ MCD_OPC_CheckPredicate, 3, 253, 27, // Skip to: 40669 >+/* 33504 */ MCD_OPC_Decode, 161, 5, 253, 1, // Opcode: FRINTMSr >+/* 33509 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33522 >+/* 33513 */ MCD_OPC_CheckPredicate, 3, 240, 27, // Skip to: 40669 >+/* 33517 */ MCD_OPC_Decode, 151, 5, 253, 1, // Opcode: FRINTASr >+/* 33522 */ MCD_OPC_FilterValue, 7, 231, 27, // Skip to: 40669 >+/* 33526 */ MCD_OPC_CheckPredicate, 3, 227, 27, // Skip to: 40669 >+/* 33530 */ MCD_OPC_Decode, 176, 5, 253, 1, // Opcode: FRINTXSr >+/* 33535 */ MCD_OPC_FilterValue, 6, 218, 27, // Skip to: 40669 >+/* 33539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 33542 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33555 >+/* 33546 */ MCD_OPC_CheckPredicate, 3, 207, 27, // Skip to: 40669 >+/* 33550 */ MCD_OPC_Decode, 184, 2, 253, 1, // Opcode: FABSSr >+/* 33555 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33568 >+/* 33559 */ MCD_OPC_CheckPredicate, 3, 194, 27, // Skip to: 40669 >+/* 33563 */ MCD_OPC_Decode, 196, 5, 253, 1, // Opcode: FSQRTSr >+/* 33568 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33581 >+/* 33572 */ MCD_OPC_CheckPredicate, 3, 181, 27, // Skip to: 40669 >+/* 33576 */ MCD_OPC_Decode, 153, 3, 254, 1, // Opcode: FCVTDSr >+/* 33581 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33594 >+/* 33585 */ MCD_OPC_CheckPredicate, 3, 168, 27, // Skip to: 40669 >+/* 33589 */ MCD_OPC_Decode, 155, 3, 255, 1, // Opcode: FCVTHSr >+/* 33594 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33607 >+/* 33598 */ MCD_OPC_CheckPredicate, 3, 155, 27, // Skip to: 40669 >+/* 33602 */ MCD_OPC_Decode, 171, 5, 253, 1, // Opcode: FRINTPSr >+/* 33607 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33620 >+/* 33611 */ MCD_OPC_CheckPredicate, 3, 142, 27, // Skip to: 40669 >+/* 33615 */ MCD_OPC_Decode, 181, 5, 253, 1, // Opcode: FRINTZSr >+/* 33620 */ MCD_OPC_FilterValue, 7, 133, 27, // Skip to: 40669 >+/* 33624 */ MCD_OPC_CheckPredicate, 3, 129, 27, // Skip to: 40669 >+/* 33628 */ MCD_OPC_Decode, 156, 5, 253, 1, // Opcode: FRINTISr >+/* 33633 */ MCD_OPC_FilterValue, 1, 120, 27, // Skip to: 40669 >+/* 33637 */ MCD_OPC_CheckPredicate, 3, 116, 27, // Skip to: 40669 >+/* 33641 */ MCD_OPC_CheckField, 5, 5, 0, 110, 27, // Skip to: 40669 >+/* 33647 */ MCD_OPC_Decode, 225, 4, 128, 2, // Opcode: FMOVSi >+/* 33652 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 33685 >+/* 33656 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 33659 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33672 >+/* 33663 */ MCD_OPC_CheckPredicate, 3, 90, 27, // Skip to: 40669 >+/* 33667 */ MCD_OPC_Decode, 211, 2, 129, 2, // Opcode: FCCMPSrr >+/* 33672 */ MCD_OPC_FilterValue, 1, 81, 27, // Skip to: 40669 >+/* 33676 */ MCD_OPC_CheckPredicate, 3, 77, 27, // Skip to: 40669 >+/* 33680 */ MCD_OPC_Decode, 210, 2, 129, 2, // Opcode: FCCMPESrr >+/* 33685 */ MCD_OPC_FilterValue, 2, 120, 0, // Skip to: 33809 >+/* 33689 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 33692 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33705 >+/* 33696 */ MCD_OPC_CheckPredicate, 3, 57, 27, // Skip to: 40669 >+/* 33700 */ MCD_OPC_Decode, 236, 4, 130, 2, // Opcode: FMULSrr >+/* 33705 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33718 >+/* 33709 */ MCD_OPC_CheckPredicate, 3, 44, 27, // Skip to: 40669 >+/* 33713 */ MCD_OPC_Decode, 154, 4, 130, 2, // Opcode: FDIVSrr >+/* 33718 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33731 >+/* 33722 */ MCD_OPC_CheckPredicate, 3, 31, 27, // Skip to: 40669 >+/* 33726 */ MCD_OPC_Decode, 204, 2, 130, 2, // Opcode: FADDSrr >+/* 33731 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33744 >+/* 33735 */ MCD_OPC_CheckPredicate, 3, 18, 27, // Skip to: 40669 >+/* 33739 */ MCD_OPC_Decode, 201, 5, 130, 2, // Opcode: FSUBSrr >+/* 33744 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33757 >+/* 33748 */ MCD_OPC_CheckPredicate, 3, 5, 27, // Skip to: 40669 >+/* 33752 */ MCD_OPC_Decode, 177, 4, 130, 2, // Opcode: FMAXSrr >+/* 33757 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33770 >+/* 33761 */ MCD_OPC_CheckPredicate, 3, 248, 26, // Skip to: 40669 >+/* 33765 */ MCD_OPC_Decode, 199, 4, 130, 2, // Opcode: FMINSrr >+/* 33770 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33783 >+/* 33774 */ MCD_OPC_CheckPredicate, 3, 235, 26, // Skip to: 40669 >+/* 33778 */ MCD_OPC_Decode, 167, 4, 130, 2, // Opcode: FMAXNMSrr >+/* 33783 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33796 >+/* 33787 */ MCD_OPC_CheckPredicate, 3, 222, 26, // Skip to: 40669 >+/* 33791 */ MCD_OPC_Decode, 189, 4, 130, 2, // Opcode: FMINNMSrr >+/* 33796 */ MCD_OPC_FilterValue, 8, 213, 26, // Skip to: 40669 >+/* 33800 */ MCD_OPC_CheckPredicate, 3, 209, 26, // Skip to: 40669 >+/* 33804 */ MCD_OPC_Decode, 137, 5, 130, 2, // Opcode: FNMULSrr >+/* 33809 */ MCD_OPC_FilterValue, 3, 200, 26, // Skip to: 40669 >+/* 33813 */ MCD_OPC_CheckPredicate, 3, 196, 26, // Skip to: 40669 >+/* 33817 */ MCD_OPC_Decode, 133, 3, 131, 2, // Opcode: FCSELSrrr >+/* 33822 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 33881 >+/* 33826 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... >+/* 33829 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33842 >+/* 33833 */ MCD_OPC_CheckPredicate, 3, 176, 26, // Skip to: 40669 >+/* 33837 */ MCD_OPC_Decode, 130, 10, 132, 2, // Opcode: SCVTFSWDri >+/* 33842 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33855 >+/* 33846 */ MCD_OPC_CheckPredicate, 3, 163, 26, // Skip to: 40669 >+/* 33850 */ MCD_OPC_Decode, 160, 16, 132, 2, // Opcode: UCVTFSWDri >+/* 33855 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33868 >+/* 33859 */ MCD_OPC_CheckPredicate, 3, 150, 26, // Skip to: 40669 >+/* 33863 */ MCD_OPC_Decode, 223, 3, 133, 2, // Opcode: FCVTZSSWDri >+/* 33868 */ MCD_OPC_FilterValue, 51, 141, 26, // Skip to: 40669 >+/* 33872 */ MCD_OPC_CheckPredicate, 3, 137, 26, // Skip to: 40669 >+/* 33876 */ MCD_OPC_Decode, 252, 3, 133, 2, // Opcode: FCVTZUSWDri >+/* 33881 */ MCD_OPC_FilterValue, 3, 76, 2, // Skip to: 34473 >+/* 33885 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 33888 */ MCD_OPC_FilterValue, 0, 164, 1, // Skip to: 34312 >+/* 33892 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 33895 */ MCD_OPC_FilterValue, 0, 138, 1, // Skip to: 34293 >+/* 33899 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 33902 */ MCD_OPC_FilterValue, 0, 157, 0, // Skip to: 34063 >+/* 33906 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 33909 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33922 >+/* 33913 */ MCD_OPC_CheckPredicate, 3, 96, 26, // Skip to: 40669 >+/* 33917 */ MCD_OPC_Decode, 178, 3, 134, 2, // Opcode: FCVTNSUWDr >+/* 33922 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33935 >+/* 33926 */ MCD_OPC_CheckPredicate, 3, 83, 26, // Skip to: 40669 >+/* 33930 */ MCD_OPC_Decode, 187, 3, 134, 2, // Opcode: FCVTNUUWDr >+/* 33935 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 33947 >+/* 33939 */ MCD_OPC_CheckPredicate, 3, 70, 26, // Skip to: 40669 >+/* 33943 */ MCD_OPC_Decode, 134, 10, 91, // Opcode: SCVTFUWDri >+/* 33947 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 33959 >+/* 33951 */ MCD_OPC_CheckPredicate, 3, 58, 26, // Skip to: 40669 >+/* 33955 */ MCD_OPC_Decode, 164, 16, 91, // Opcode: UCVTFUWDri >+/* 33959 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33972 >+/* 33963 */ MCD_OPC_CheckPredicate, 3, 46, 26, // Skip to: 40669 >+/* 33967 */ MCD_OPC_Decode, 134, 3, 134, 2, // Opcode: FCVTASUWDr >+/* 33972 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33985 >+/* 33976 */ MCD_OPC_CheckPredicate, 3, 33, 26, // Skip to: 40669 >+/* 33980 */ MCD_OPC_Decode, 143, 3, 134, 2, // Opcode: FCVTAUUWDr >+/* 33985 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33998 >+/* 33989 */ MCD_OPC_CheckPredicate, 3, 20, 26, // Skip to: 40669 >+/* 33993 */ MCD_OPC_Decode, 200, 3, 134, 2, // Opcode: FCVTPSUWDr >+/* 33998 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 34011 >+/* 34002 */ MCD_OPC_CheckPredicate, 3, 7, 26, // Skip to: 40669 >+/* 34006 */ MCD_OPC_Decode, 209, 3, 134, 2, // Opcode: FCVTPUUWDr >+/* 34011 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 34024 >+/* 34015 */ MCD_OPC_CheckPredicate, 3, 250, 25, // Skip to: 40669 >+/* 34019 */ MCD_OPC_Decode, 160, 3, 134, 2, // Opcode: FCVTMSUWDr >+/* 34024 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 34037 >+/* 34028 */ MCD_OPC_CheckPredicate, 3, 237, 25, // Skip to: 40669 >+/* 34032 */ MCD_OPC_Decode, 169, 3, 134, 2, // Opcode: FCVTMUUWDr >+/* 34037 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 34050 >+/* 34041 */ MCD_OPC_CheckPredicate, 3, 224, 25, // Skip to: 40669 >+/* 34045 */ MCD_OPC_Decode, 227, 3, 134, 2, // Opcode: FCVTZSUWDr >+/* 34050 */ MCD_OPC_FilterValue, 25, 215, 25, // Skip to: 40669 >+/* 34054 */ MCD_OPC_CheckPredicate, 3, 211, 25, // Skip to: 40669 >+/* 34058 */ MCD_OPC_Decode, 128, 4, 134, 2, // Opcode: FCVTZUUWDr >+/* 34063 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 34122 >+/* 34067 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... >+/* 34070 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34083 >+/* 34074 */ MCD_OPC_CheckPredicate, 3, 191, 25, // Skip to: 40669 >+/* 34078 */ MCD_OPC_Decode, 253, 2, 135, 2, // Opcode: FCMPDrr >+/* 34083 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 34096 >+/* 34087 */ MCD_OPC_CheckPredicate, 3, 178, 25, // Skip to: 40669 >+/* 34091 */ MCD_OPC_Decode, 252, 2, 136, 2, // Opcode: FCMPDri >+/* 34096 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 34109 >+/* 34100 */ MCD_OPC_CheckPredicate, 3, 165, 25, // Skip to: 40669 >+/* 34104 */ MCD_OPC_Decode, 255, 2, 135, 2, // Opcode: FCMPEDrr >+/* 34109 */ MCD_OPC_FilterValue, 24, 156, 25, // Skip to: 40669 >+/* 34113 */ MCD_OPC_CheckPredicate, 3, 152, 25, // Skip to: 40669 >+/* 34117 */ MCD_OPC_Decode, 254, 2, 136, 2, // Opcode: FCMPEDri >+/* 34122 */ MCD_OPC_FilterValue, 2, 88, 0, // Skip to: 34214 >+/* 34126 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 34129 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34141 >+/* 34133 */ MCD_OPC_CheckPredicate, 3, 132, 25, // Skip to: 40669 >+/* 34137 */ MCD_OPC_Decode, 223, 4, 90, // Opcode: FMOVDr >+/* 34141 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34153 >+/* 34145 */ MCD_OPC_CheckPredicate, 3, 120, 25, // Skip to: 40669 >+/* 34149 */ MCD_OPC_Decode, 255, 4, 90, // Opcode: FNEGDr >+/* 34153 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 34166 >+/* 34157 */ MCD_OPC_CheckPredicate, 3, 108, 25, // Skip to: 40669 >+/* 34161 */ MCD_OPC_Decode, 218, 3, 144, 1, // Opcode: FCVTSDr >+/* 34166 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34178 >+/* 34170 */ MCD_OPC_CheckPredicate, 3, 95, 25, // Skip to: 40669 >+/* 34174 */ MCD_OPC_Decode, 165, 5, 90, // Opcode: FRINTNDr >+/* 34178 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34190 >+/* 34182 */ MCD_OPC_CheckPredicate, 3, 83, 25, // Skip to: 40669 >+/* 34186 */ MCD_OPC_Decode, 160, 5, 90, // Opcode: FRINTMDr >+/* 34190 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34202 >+/* 34194 */ MCD_OPC_CheckPredicate, 3, 71, 25, // Skip to: 40669 >+/* 34198 */ MCD_OPC_Decode, 150, 5, 90, // Opcode: FRINTADr >+/* 34202 */ MCD_OPC_FilterValue, 7, 63, 25, // Skip to: 40669 >+/* 34206 */ MCD_OPC_CheckPredicate, 3, 59, 25, // Skip to: 40669 >+/* 34210 */ MCD_OPC_Decode, 175, 5, 90, // Opcode: FRINTXDr >+/* 34214 */ MCD_OPC_FilterValue, 6, 51, 25, // Skip to: 40669 >+/* 34218 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 34221 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34233 >+/* 34225 */ MCD_OPC_CheckPredicate, 3, 40, 25, // Skip to: 40669 >+/* 34229 */ MCD_OPC_Decode, 183, 2, 90, // Opcode: FABSDr >+/* 34233 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34245 >+/* 34237 */ MCD_OPC_CheckPredicate, 3, 28, 25, // Skip to: 40669 >+/* 34241 */ MCD_OPC_Decode, 195, 5, 90, // Opcode: FSQRTDr >+/* 34245 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34257 >+/* 34249 */ MCD_OPC_CheckPredicate, 3, 16, 25, // Skip to: 40669 >+/* 34253 */ MCD_OPC_Decode, 154, 3, 100, // Opcode: FCVTHDr >+/* 34257 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34269 >+/* 34261 */ MCD_OPC_CheckPredicate, 3, 4, 25, // Skip to: 40669 >+/* 34265 */ MCD_OPC_Decode, 170, 5, 90, // Opcode: FRINTPDr >+/* 34269 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34281 >+/* 34273 */ MCD_OPC_CheckPredicate, 3, 248, 24, // Skip to: 40669 >+/* 34277 */ MCD_OPC_Decode, 180, 5, 90, // Opcode: FRINTZDr >+/* 34281 */ MCD_OPC_FilterValue, 7, 240, 24, // Skip to: 40669 >+/* 34285 */ MCD_OPC_CheckPredicate, 3, 236, 24, // Skip to: 40669 >+/* 34289 */ MCD_OPC_Decode, 155, 5, 90, // Opcode: FRINTIDr >+/* 34293 */ MCD_OPC_FilterValue, 1, 228, 24, // Skip to: 40669 >+/* 34297 */ MCD_OPC_CheckPredicate, 3, 224, 24, // Skip to: 40669 >+/* 34301 */ MCD_OPC_CheckField, 5, 5, 0, 218, 24, // Skip to: 40669 >+/* 34307 */ MCD_OPC_Decode, 222, 4, 137, 2, // Opcode: FMOVDi >+/* 34312 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34345 >+/* 34316 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 34319 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34332 >+/* 34323 */ MCD_OPC_CheckPredicate, 3, 198, 24, // Skip to: 40669 >+/* 34327 */ MCD_OPC_Decode, 208, 2, 138, 2, // Opcode: FCCMPDrr >+/* 34332 */ MCD_OPC_FilterValue, 1, 189, 24, // Skip to: 40669 >+/* 34336 */ MCD_OPC_CheckPredicate, 3, 185, 24, // Skip to: 40669 >+/* 34340 */ MCD_OPC_Decode, 209, 2, 138, 2, // Opcode: FCCMPEDrr >+/* 34345 */ MCD_OPC_FilterValue, 2, 111, 0, // Skip to: 34460 >+/* 34349 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 34352 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34364 >+/* 34356 */ MCD_OPC_CheckPredicate, 3, 165, 24, // Skip to: 40669 >+/* 34360 */ MCD_OPC_Decode, 235, 4, 89, // Opcode: FMULDrr >+/* 34364 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34376 >+/* 34368 */ MCD_OPC_CheckPredicate, 3, 153, 24, // Skip to: 40669 >+/* 34372 */ MCD_OPC_Decode, 153, 4, 89, // Opcode: FDIVDrr >+/* 34376 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 34388 >+/* 34380 */ MCD_OPC_CheckPredicate, 3, 141, 24, // Skip to: 40669 >+/* 34384 */ MCD_OPC_Decode, 198, 2, 89, // Opcode: FADDDrr >+/* 34388 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34400 >+/* 34392 */ MCD_OPC_CheckPredicate, 3, 129, 24, // Skip to: 40669 >+/* 34396 */ MCD_OPC_Decode, 200, 5, 89, // Opcode: FSUBDrr >+/* 34400 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34412 >+/* 34404 */ MCD_OPC_CheckPredicate, 3, 117, 24, // Skip to: 40669 >+/* 34408 */ MCD_OPC_Decode, 160, 4, 89, // Opcode: FMAXDrr >+/* 34412 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34424 >+/* 34416 */ MCD_OPC_CheckPredicate, 3, 105, 24, // Skip to: 40669 >+/* 34420 */ MCD_OPC_Decode, 182, 4, 89, // Opcode: FMINDrr >+/* 34424 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34436 >+/* 34428 */ MCD_OPC_CheckPredicate, 3, 93, 24, // Skip to: 40669 >+/* 34432 */ MCD_OPC_Decode, 161, 4, 89, // Opcode: FMAXNMDrr >+/* 34436 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 34448 >+/* 34440 */ MCD_OPC_CheckPredicate, 3, 81, 24, // Skip to: 40669 >+/* 34444 */ MCD_OPC_Decode, 183, 4, 89, // Opcode: FMINNMDrr >+/* 34448 */ MCD_OPC_FilterValue, 8, 73, 24, // Skip to: 40669 >+/* 34452 */ MCD_OPC_CheckPredicate, 3, 69, 24, // Skip to: 40669 >+/* 34456 */ MCD_OPC_Decode, 136, 5, 89, // Opcode: FNMULDrr >+/* 34460 */ MCD_OPC_FilterValue, 3, 61, 24, // Skip to: 40669 >+/* 34464 */ MCD_OPC_CheckPredicate, 3, 57, 24, // Skip to: 40669 >+/* 34468 */ MCD_OPC_Decode, 132, 3, 139, 2, // Opcode: FCSELDrrr >+/* 34473 */ MCD_OPC_FilterValue, 7, 48, 24, // Skip to: 40669 >+/* 34477 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... >+/* 34480 */ MCD_OPC_FilterValue, 144, 1, 9, 0, // Skip to: 34494 >+/* 34485 */ MCD_OPC_CheckPredicate, 3, 36, 24, // Skip to: 40669 >+/* 34489 */ MCD_OPC_Decode, 219, 3, 140, 2, // Opcode: FCVTSHr >+/* 34494 */ MCD_OPC_FilterValue, 176, 1, 26, 24, // Skip to: 40669 >+/* 34499 */ MCD_OPC_CheckPredicate, 3, 22, 24, // Skip to: 40669 >+/* 34503 */ MCD_OPC_Decode, 152, 3, 141, 2, // Opcode: FCVTDHr >+/* 34508 */ MCD_OPC_FilterValue, 3, 13, 24, // Skip to: 40669 >+/* 34512 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 34515 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 34548 >+/* 34519 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 34522 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34535 >+/* 34526 */ MCD_OPC_CheckPredicate, 3, 251, 23, // Skip to: 40669 >+/* 34530 */ MCD_OPC_Decode, 159, 4, 142, 2, // Opcode: FMADDSrrr >+/* 34535 */ MCD_OPC_FilterValue, 1, 242, 23, // Skip to: 40669 >+/* 34539 */ MCD_OPC_CheckPredicate, 3, 238, 23, // Skip to: 40669 >+/* 34543 */ MCD_OPC_Decode, 234, 4, 142, 2, // Opcode: FMSUBSrrr >+/* 34548 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34581 >+/* 34552 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 34555 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34568 >+/* 34559 */ MCD_OPC_CheckPredicate, 3, 218, 23, // Skip to: 40669 >+/* 34563 */ MCD_OPC_Decode, 133, 5, 142, 2, // Opcode: FNMADDSrrr >+/* 34568 */ MCD_OPC_FilterValue, 1, 209, 23, // Skip to: 40669 >+/* 34572 */ MCD_OPC_CheckPredicate, 3, 205, 23, // Skip to: 40669 >+/* 34576 */ MCD_OPC_Decode, 135, 5, 142, 2, // Opcode: FNMSUBSrrr >+/* 34581 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 34614 >+/* 34585 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 34588 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34601 >+/* 34592 */ MCD_OPC_CheckPredicate, 3, 185, 23, // Skip to: 40669 >+/* 34596 */ MCD_OPC_Decode, 158, 4, 143, 2, // Opcode: FMADDDrrr >+/* 34601 */ MCD_OPC_FilterValue, 1, 176, 23, // Skip to: 40669 >+/* 34605 */ MCD_OPC_CheckPredicate, 3, 172, 23, // Skip to: 40669 >+/* 34609 */ MCD_OPC_Decode, 233, 4, 143, 2, // Opcode: FMSUBDrrr >+/* 34614 */ MCD_OPC_FilterValue, 3, 163, 23, // Skip to: 40669 >+/* 34618 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 34621 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34634 >+/* 34625 */ MCD_OPC_CheckPredicate, 3, 152, 23, // Skip to: 40669 >+/* 34629 */ MCD_OPC_Decode, 132, 5, 143, 2, // Opcode: FNMADDDrrr >+/* 34634 */ MCD_OPC_FilterValue, 1, 143, 23, // Skip to: 40669 >+/* 34638 */ MCD_OPC_CheckPredicate, 3, 139, 23, // Skip to: 40669 >+/* 34642 */ MCD_OPC_Decode, 134, 5, 143, 2, // Opcode: FNMSUBDrrr >+/* 34647 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 35046 >+/* 34651 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 34654 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 34743 >+/* 34658 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 34661 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34676 >+/* 34665 */ MCD_OPC_CheckField, 21, 1, 0, 110, 23, // Skip to: 40669 >+/* 34671 */ MCD_OPC_Decode, 135, 15, 226, 1, // Opcode: STURBi >+/* 34676 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34691 >+/* 34680 */ MCD_OPC_CheckField, 21, 1, 0, 95, 23, // Skip to: 40669 >+/* 34686 */ MCD_OPC_Decode, 218, 14, 226, 1, // Opcode: STRBpost >+/* 34691 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34728 >+/* 34695 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 34698 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34713 >+/* 34702 */ MCD_OPC_CheckField, 21, 1, 1, 73, 23, // Skip to: 40669 >+/* 34708 */ MCD_OPC_Decode, 220, 14, 144, 2, // Opcode: STRBroW >+/* 34713 */ MCD_OPC_FilterValue, 3, 64, 23, // Skip to: 40669 >+/* 34717 */ MCD_OPC_CheckField, 21, 1, 1, 58, 23, // Skip to: 40669 >+/* 34723 */ MCD_OPC_Decode, 221, 14, 145, 2, // Opcode: STRBroX >+/* 34728 */ MCD_OPC_FilterValue, 3, 49, 23, // Skip to: 40669 >+/* 34732 */ MCD_OPC_CheckField, 21, 1, 0, 43, 23, // Skip to: 40669 >+/* 34738 */ MCD_OPC_Decode, 219, 14, 226, 1, // Opcode: STRBpre >+/* 34743 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 34832 >+/* 34747 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 34750 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34765 >+/* 34754 */ MCD_OPC_CheckField, 21, 1, 0, 21, 23, // Skip to: 40669 >+/* 34760 */ MCD_OPC_Decode, 154, 8, 226, 1, // Opcode: LDURBi >+/* 34765 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34780 >+/* 34769 */ MCD_OPC_CheckField, 21, 1, 0, 6, 23, // Skip to: 40669 >+/* 34775 */ MCD_OPC_Decode, 201, 7, 226, 1, // Opcode: LDRBpost >+/* 34780 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34817 >+/* 34784 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 34787 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34802 >+/* 34791 */ MCD_OPC_CheckField, 21, 1, 1, 240, 22, // Skip to: 40669 >+/* 34797 */ MCD_OPC_Decode, 203, 7, 144, 2, // Opcode: LDRBroW >+/* 34802 */ MCD_OPC_FilterValue, 3, 231, 22, // Skip to: 40669 >+/* 34806 */ MCD_OPC_CheckField, 21, 1, 1, 225, 22, // Skip to: 40669 >+/* 34812 */ MCD_OPC_Decode, 204, 7, 145, 2, // Opcode: LDRBroX >+/* 34817 */ MCD_OPC_FilterValue, 3, 216, 22, // Skip to: 40669 >+/* 34821 */ MCD_OPC_CheckField, 21, 1, 0, 210, 22, // Skip to: 40669 >+/* 34827 */ MCD_OPC_Decode, 202, 7, 226, 1, // Opcode: LDRBpre >+/* 34832 */ MCD_OPC_FilterValue, 2, 85, 0, // Skip to: 34921 >+/* 34836 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 34839 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34854 >+/* 34843 */ MCD_OPC_CheckField, 21, 1, 0, 188, 22, // Skip to: 40669 >+/* 34849 */ MCD_OPC_Decode, 139, 15, 226, 1, // Opcode: STURQi >+/* 34854 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34869 >+/* 34858 */ MCD_OPC_CheckField, 21, 1, 0, 173, 22, // Skip to: 40669 >+/* 34864 */ MCD_OPC_Decode, 238, 14, 226, 1, // Opcode: STRQpost >+/* 34869 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34906 >+/* 34873 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 34876 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34891 >+/* 34880 */ MCD_OPC_CheckField, 21, 1, 1, 151, 22, // Skip to: 40669 >+/* 34886 */ MCD_OPC_Decode, 240, 14, 146, 2, // Opcode: STRQroW >+/* 34891 */ MCD_OPC_FilterValue, 3, 142, 22, // Skip to: 40669 >+/* 34895 */ MCD_OPC_CheckField, 21, 1, 1, 136, 22, // Skip to: 40669 >+/* 34901 */ MCD_OPC_Decode, 241, 14, 147, 2, // Opcode: STRQroX >+/* 34906 */ MCD_OPC_FilterValue, 3, 127, 22, // Skip to: 40669 >+/* 34910 */ MCD_OPC_CheckField, 21, 1, 0, 121, 22, // Skip to: 40669 >+/* 34916 */ MCD_OPC_Decode, 239, 14, 226, 1, // Opcode: STRQpre >+/* 34921 */ MCD_OPC_FilterValue, 3, 85, 0, // Skip to: 35010 >+/* 34925 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 34928 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34943 >+/* 34932 */ MCD_OPC_CheckField, 21, 1, 0, 99, 22, // Skip to: 40669 >+/* 34938 */ MCD_OPC_Decode, 158, 8, 226, 1, // Opcode: LDURQi >+/* 34943 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34958 >+/* 34947 */ MCD_OPC_CheckField, 21, 1, 0, 84, 22, // Skip to: 40669 >+/* 34953 */ MCD_OPC_Decode, 223, 7, 226, 1, // Opcode: LDRQpost >+/* 34958 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34995 >+/* 34962 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 34965 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34980 >+/* 34969 */ MCD_OPC_CheckField, 21, 1, 1, 62, 22, // Skip to: 40669 >+/* 34975 */ MCD_OPC_Decode, 225, 7, 146, 2, // Opcode: LDRQroW >+/* 34980 */ MCD_OPC_FilterValue, 3, 53, 22, // Skip to: 40669 >+/* 34984 */ MCD_OPC_CheckField, 21, 1, 1, 47, 22, // Skip to: 40669 >+/* 34990 */ MCD_OPC_Decode, 226, 7, 147, 2, // Opcode: LDRQroX >+/* 34995 */ MCD_OPC_FilterValue, 3, 38, 22, // Skip to: 40669 >+/* 34999 */ MCD_OPC_CheckField, 21, 1, 0, 32, 22, // Skip to: 40669 >+/* 35005 */ MCD_OPC_Decode, 224, 7, 226, 1, // Opcode: LDRQpre >+/* 35010 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 35019 >+/* 35014 */ MCD_OPC_Decode, 222, 14, 231, 1, // Opcode: STRBui >+/* 35019 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 35028 >+/* 35023 */ MCD_OPC_Decode, 205, 7, 231, 1, // Opcode: LDRBui >+/* 35028 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 35037 >+/* 35032 */ MCD_OPC_Decode, 242, 14, 231, 1, // Opcode: STRQui >+/* 35037 */ MCD_OPC_FilterValue, 7, 252, 21, // Skip to: 40669 >+/* 35041 */ MCD_OPC_Decode, 227, 7, 231, 1, // Opcode: LDRQui >+/* 35046 */ MCD_OPC_FilterValue, 2, 240, 8, // Skip to: 37338 >+/* 35050 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 35053 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 35062 >+/* 35057 */ MCD_OPC_Decode, 206, 7, 148, 2, // Opcode: LDRDl >+/* 35062 */ MCD_OPC_FilterValue, 2, 175, 5, // Skip to: 36521 >+/* 35066 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 35069 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 35088 >+/* 35073 */ MCD_OPC_CheckPredicate, 1, 216, 21, // Skip to: 40669 >+/* 35077 */ MCD_OPC_CheckField, 21, 3, 0, 210, 21, // Skip to: 40669 >+/* 35083 */ MCD_OPC_Decode, 152, 10, 149, 2, // Opcode: SHA1Crrr >+/* 35088 */ MCD_OPC_FilterValue, 1, 99, 0, // Skip to: 35191 >+/* 35092 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 35095 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 35172 >+/* 35099 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 35102 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 35153 >+/* 35106 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 35109 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 35134 >+/* 35113 */ MCD_OPC_CheckPredicate, 0, 176, 21, // Skip to: 40669 >+/* 35117 */ MCD_OPC_CheckField, 21, 3, 0, 170, 21, // Skip to: 40669 >+/* 35123 */ MCD_OPC_CheckField, 19, 1, 1, 164, 21, // Skip to: 40669 >+/* 35129 */ MCD_OPC_Decode, 250, 1, 150, 2, // Opcode: CPYi64 >+/* 35134 */ MCD_OPC_FilterValue, 1, 155, 21, // Skip to: 40669 >+/* 35138 */ MCD_OPC_CheckPredicate, 0, 151, 21, // Skip to: 40669 >+/* 35142 */ MCD_OPC_CheckField, 21, 3, 0, 145, 21, // Skip to: 40669 >+/* 35148 */ MCD_OPC_Decode, 249, 1, 151, 2, // Opcode: CPYi32 >+/* 35153 */ MCD_OPC_FilterValue, 1, 136, 21, // Skip to: 40669 >+/* 35157 */ MCD_OPC_CheckPredicate, 0, 132, 21, // Skip to: 40669 >+/* 35161 */ MCD_OPC_CheckField, 21, 3, 0, 126, 21, // Skip to: 40669 >+/* 35167 */ MCD_OPC_Decode, 248, 1, 152, 2, // Opcode: CPYi16 >+/* 35172 */ MCD_OPC_FilterValue, 1, 117, 21, // Skip to: 40669 >+/* 35176 */ MCD_OPC_CheckPredicate, 0, 113, 21, // Skip to: 40669 >+/* 35180 */ MCD_OPC_CheckField, 21, 3, 0, 107, 21, // Skip to: 40669 >+/* 35186 */ MCD_OPC_Decode, 251, 1, 153, 2, // Opcode: CPYi8 >+/* 35191 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 35210 >+/* 35195 */ MCD_OPC_CheckPredicate, 1, 94, 21, // Skip to: 40669 >+/* 35199 */ MCD_OPC_CheckField, 16, 8, 40, 88, 21, // Skip to: 40669 >+/* 35205 */ MCD_OPC_Decode, 153, 10, 253, 1, // Opcode: SHA1Hrr >+/* 35210 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 35268 >+/* 35214 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 35217 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35230 >+/* 35221 */ MCD_OPC_CheckPredicate, 0, 68, 21, // Skip to: 40669 >+/* 35225 */ MCD_OPC_Decode, 162, 11, 154, 2, // Opcode: SQADDv1i8 >+/* 35230 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35243 >+/* 35234 */ MCD_OPC_CheckPredicate, 0, 55, 21, // Skip to: 40669 >+/* 35238 */ MCD_OPC_Decode, 159, 11, 155, 2, // Opcode: SQADDv1i16 >+/* 35243 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35256 >+/* 35247 */ MCD_OPC_CheckPredicate, 0, 42, 21, // Skip to: 40669 >+/* 35251 */ MCD_OPC_Decode, 160, 11, 130, 2, // Opcode: SQADDv1i32 >+/* 35256 */ MCD_OPC_FilterValue, 7, 33, 21, // Skip to: 40669 >+/* 35260 */ MCD_OPC_CheckPredicate, 0, 29, 21, // Skip to: 40669 >+/* 35264 */ MCD_OPC_Decode, 161, 11, 89, // Opcode: SQADDv1i64 >+/* 35268 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 35287 >+/* 35272 */ MCD_OPC_CheckPredicate, 1, 17, 21, // Skip to: 40669 >+/* 35276 */ MCD_OPC_CheckField, 21, 3, 0, 11, 21, // Skip to: 40669 >+/* 35282 */ MCD_OPC_Decode, 155, 10, 149, 2, // Opcode: SHA1Prrr >+/* 35287 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 35305 >+/* 35291 */ MCD_OPC_CheckPredicate, 1, 254, 20, // Skip to: 40669 >+/* 35295 */ MCD_OPC_CheckField, 16, 8, 40, 248, 20, // Skip to: 40669 >+/* 35301 */ MCD_OPC_Decode, 157, 10, 126, // Opcode: SHA1SU1rr >+/* 35305 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 35324 >+/* 35309 */ MCD_OPC_CheckPredicate, 1, 236, 20, // Skip to: 40669 >+/* 35313 */ MCD_OPC_CheckField, 21, 3, 0, 230, 20, // Skip to: 40669 >+/* 35319 */ MCD_OPC_Decode, 154, 10, 149, 2, // Opcode: SHA1Mrrr >+/* 35324 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 35342 >+/* 35328 */ MCD_OPC_CheckPredicate, 1, 217, 20, // Skip to: 40669 >+/* 35332 */ MCD_OPC_CheckField, 16, 8, 40, 211, 20, // Skip to: 40669 >+/* 35338 */ MCD_OPC_Decode, 160, 10, 126, // Opcode: SHA256SU0rr >+/* 35342 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 35400 >+/* 35346 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 35349 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35362 >+/* 35353 */ MCD_OPC_CheckPredicate, 0, 192, 20, // Skip to: 40669 >+/* 35357 */ MCD_OPC_Decode, 196, 12, 154, 2, // Opcode: SQSUBv1i8 >+/* 35362 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35375 >+/* 35366 */ MCD_OPC_CheckPredicate, 0, 179, 20, // Skip to: 40669 >+/* 35370 */ MCD_OPC_Decode, 193, 12, 155, 2, // Opcode: SQSUBv1i16 >+/* 35375 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35388 >+/* 35379 */ MCD_OPC_CheckPredicate, 0, 166, 20, // Skip to: 40669 >+/* 35383 */ MCD_OPC_Decode, 194, 12, 130, 2, // Opcode: SQSUBv1i32 >+/* 35388 */ MCD_OPC_FilterValue, 7, 157, 20, // Skip to: 40669 >+/* 35392 */ MCD_OPC_CheckPredicate, 0, 153, 20, // Skip to: 40669 >+/* 35396 */ MCD_OPC_Decode, 195, 12, 89, // Opcode: SQSUBv1i64 >+/* 35400 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 35418 >+/* 35404 */ MCD_OPC_CheckPredicate, 1, 141, 20, // Skip to: 40669 >+/* 35408 */ MCD_OPC_CheckField, 21, 3, 0, 135, 20, // Skip to: 40669 >+/* 35414 */ MCD_OPC_Decode, 156, 10, 120, // Opcode: SHA1SU0rrr >+/* 35418 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 35436 >+/* 35422 */ MCD_OPC_CheckPredicate, 0, 123, 20, // Skip to: 40669 >+/* 35426 */ MCD_OPC_CheckField, 21, 3, 7, 117, 20, // Skip to: 40669 >+/* 35432 */ MCD_OPC_Decode, 192, 1, 89, // Opcode: CMGTv1i64 >+/* 35436 */ MCD_OPC_FilterValue, 14, 56, 0, // Skip to: 35496 >+/* 35440 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 35443 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35456 >+/* 35447 */ MCD_OPC_CheckPredicate, 0, 98, 20, // Skip to: 40669 >+/* 35451 */ MCD_OPC_Decode, 185, 15, 156, 2, // Opcode: SUQADDv1i8 >+/* 35456 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35469 >+/* 35460 */ MCD_OPC_CheckPredicate, 0, 85, 20, // Skip to: 40669 >+/* 35464 */ MCD_OPC_Decode, 182, 15, 157, 2, // Opcode: SUQADDv1i16 >+/* 35469 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35483 >+/* 35474 */ MCD_OPC_CheckPredicate, 0, 71, 20, // Skip to: 40669 >+/* 35478 */ MCD_OPC_Decode, 183, 15, 158, 2, // Opcode: SUQADDv1i32 >+/* 35483 */ MCD_OPC_FilterValue, 224, 1, 61, 20, // Skip to: 40669 >+/* 35488 */ MCD_OPC_CheckPredicate, 0, 57, 20, // Skip to: 40669 >+/* 35492 */ MCD_OPC_Decode, 184, 15, 99, // Opcode: SUQADDv1i64 >+/* 35496 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 35514 >+/* 35500 */ MCD_OPC_CheckPredicate, 0, 45, 20, // Skip to: 40669 >+/* 35504 */ MCD_OPC_CheckField, 21, 3, 7, 39, 20, // Skip to: 40669 >+/* 35510 */ MCD_OPC_Decode, 176, 1, 89, // Opcode: CMGEv1i64 >+/* 35514 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 35532 >+/* 35518 */ MCD_OPC_CheckPredicate, 1, 27, 20, // Skip to: 40669 >+/* 35522 */ MCD_OPC_CheckField, 21, 3, 0, 21, 20, // Skip to: 40669 >+/* 35528 */ MCD_OPC_Decode, 159, 10, 120, // Opcode: SHA256Hrrr >+/* 35532 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 35550 >+/* 35536 */ MCD_OPC_CheckPredicate, 0, 9, 20, // Skip to: 40669 >+/* 35540 */ MCD_OPC_CheckField, 21, 3, 7, 3, 20, // Skip to: 40669 >+/* 35546 */ MCD_OPC_Decode, 138, 13, 89, // Opcode: SSHLv1i64 >+/* 35550 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 35597 >+/* 35554 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 35557 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35570 >+/* 35561 */ MCD_OPC_CheckPredicate, 0, 240, 19, // Skip to: 40669 >+/* 35565 */ MCD_OPC_Decode, 206, 12, 159, 2, // Opcode: SQXTNv1i8 >+/* 35570 */ MCD_OPC_FilterValue, 97, 9, 0, // Skip to: 35583 >+/* 35574 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 40669 >+/* 35578 */ MCD_OPC_Decode, 204, 12, 255, 1, // Opcode: SQXTNv1i16 >+/* 35583 */ MCD_OPC_FilterValue, 161, 1, 217, 19, // Skip to: 40669 >+/* 35588 */ MCD_OPC_CheckPredicate, 0, 213, 19, // Skip to: 40669 >+/* 35592 */ MCD_OPC_Decode, 205, 12, 144, 1, // Opcode: SQXTNv1i32 >+/* 35597 */ MCD_OPC_FilterValue, 19, 54, 0, // Skip to: 35655 >+/* 35601 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 35604 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35617 >+/* 35608 */ MCD_OPC_CheckPredicate, 0, 193, 19, // Skip to: 40669 >+/* 35612 */ MCD_OPC_Decode, 161, 12, 154, 2, // Opcode: SQSHLv1i8 >+/* 35617 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35630 >+/* 35621 */ MCD_OPC_CheckPredicate, 0, 180, 19, // Skip to: 40669 >+/* 35625 */ MCD_OPC_Decode, 158, 12, 155, 2, // Opcode: SQSHLv1i16 >+/* 35630 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35643 >+/* 35634 */ MCD_OPC_CheckPredicate, 0, 167, 19, // Skip to: 40669 >+/* 35638 */ MCD_OPC_Decode, 159, 12, 130, 2, // Opcode: SQSHLv1i32 >+/* 35643 */ MCD_OPC_FilterValue, 7, 158, 19, // Skip to: 40669 >+/* 35647 */ MCD_OPC_CheckPredicate, 0, 154, 19, // Skip to: 40669 >+/* 35651 */ MCD_OPC_Decode, 160, 12, 89, // Opcode: SQSHLv1i64 >+/* 35655 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 35673 >+/* 35659 */ MCD_OPC_CheckPredicate, 1, 142, 19, // Skip to: 40669 >+/* 35663 */ MCD_OPC_CheckField, 21, 3, 0, 136, 19, // Skip to: 40669 >+/* 35669 */ MCD_OPC_Decode, 158, 10, 120, // Opcode: SHA256H2rrr >+/* 35673 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 35691 >+/* 35677 */ MCD_OPC_CheckPredicate, 0, 124, 19, // Skip to: 40669 >+/* 35681 */ MCD_OPC_CheckField, 21, 3, 7, 118, 19, // Skip to: 40669 >+/* 35687 */ MCD_OPC_Decode, 236, 12, 89, // Opcode: SRSHLv1i64 >+/* 35691 */ MCD_OPC_FilterValue, 23, 54, 0, // Skip to: 35749 >+/* 35695 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 35698 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35711 >+/* 35702 */ MCD_OPC_CheckPredicate, 0, 99, 19, // Skip to: 40669 >+/* 35706 */ MCD_OPC_Decode, 244, 11, 154, 2, // Opcode: SQRSHLv1i8 >+/* 35711 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35724 >+/* 35715 */ MCD_OPC_CheckPredicate, 0, 86, 19, // Skip to: 40669 >+/* 35719 */ MCD_OPC_Decode, 241, 11, 155, 2, // Opcode: SQRSHLv1i16 >+/* 35724 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35737 >+/* 35728 */ MCD_OPC_CheckPredicate, 0, 73, 19, // Skip to: 40669 >+/* 35732 */ MCD_OPC_Decode, 242, 11, 130, 2, // Opcode: SQRSHLv1i32 >+/* 35737 */ MCD_OPC_FilterValue, 7, 64, 19, // Skip to: 40669 >+/* 35741 */ MCD_OPC_CheckPredicate, 0, 60, 19, // Skip to: 40669 >+/* 35745 */ MCD_OPC_Decode, 243, 11, 89, // Opcode: SQRSHLv1i64 >+/* 35749 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 35767 >+/* 35753 */ MCD_OPC_CheckPredicate, 1, 48, 19, // Skip to: 40669 >+/* 35757 */ MCD_OPC_CheckField, 21, 3, 0, 42, 19, // Skip to: 40669 >+/* 35763 */ MCD_OPC_Decode, 161, 10, 120, // Opcode: SHA256SU1rrr >+/* 35767 */ MCD_OPC_FilterValue, 30, 56, 0, // Skip to: 35827 >+/* 35771 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 35774 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35787 >+/* 35778 */ MCD_OPC_CheckPredicate, 0, 23, 19, // Skip to: 40669 >+/* 35782 */ MCD_OPC_Decode, 151, 11, 160, 2, // Opcode: SQABSv1i8 >+/* 35787 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35800 >+/* 35791 */ MCD_OPC_CheckPredicate, 0, 10, 19, // Skip to: 40669 >+/* 35795 */ MCD_OPC_Decode, 148, 11, 161, 2, // Opcode: SQABSv1i16 >+/* 35800 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35814 >+/* 35805 */ MCD_OPC_CheckPredicate, 0, 252, 18, // Skip to: 40669 >+/* 35809 */ MCD_OPC_Decode, 149, 11, 253, 1, // Opcode: SQABSv1i32 >+/* 35814 */ MCD_OPC_FilterValue, 224, 1, 242, 18, // Skip to: 40669 >+/* 35819 */ MCD_OPC_CheckPredicate, 0, 238, 18, // Skip to: 40669 >+/* 35823 */ MCD_OPC_Decode, 150, 11, 90, // Opcode: SQABSv1i64 >+/* 35827 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 35844 >+/* 35831 */ MCD_OPC_CheckPredicate, 0, 226, 18, // Skip to: 40669 >+/* 35835 */ MCD_OPC_CheckField, 21, 3, 7, 220, 18, // Skip to: 40669 >+/* 35841 */ MCD_OPC_Decode, 70, 89, // Opcode: ADDv1i64 >+/* 35844 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 35863 >+/* 35848 */ MCD_OPC_CheckPredicate, 0, 209, 18, // Skip to: 40669 >+/* 35852 */ MCD_OPC_CheckField, 16, 8, 224, 1, 202, 18, // Skip to: 40669 >+/* 35859 */ MCD_OPC_Decode, 193, 1, 90, // Opcode: CMGTv1i64rz >+/* 35863 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 35881 >+/* 35867 */ MCD_OPC_CheckPredicate, 0, 190, 18, // Skip to: 40669 >+/* 35871 */ MCD_OPC_CheckField, 21, 3, 7, 184, 18, // Skip to: 40669 >+/* 35877 */ MCD_OPC_Decode, 239, 1, 89, // Opcode: CMTSTv1i64 >+/* 35881 */ MCD_OPC_FilterValue, 36, 29, 0, // Skip to: 35914 >+/* 35885 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 35888 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35901 >+/* 35892 */ MCD_OPC_CheckPredicate, 0, 165, 18, // Skip to: 40669 >+/* 35896 */ MCD_OPC_Decode, 169, 11, 162, 2, // Opcode: SQDMLALi16 >+/* 35901 */ MCD_OPC_FilterValue, 5, 156, 18, // Skip to: 40669 >+/* 35905 */ MCD_OPC_CheckPredicate, 0, 152, 18, // Skip to: 40669 >+/* 35909 */ MCD_OPC_Decode, 170, 11, 163, 2, // Opcode: SQDMLALi32 >+/* 35914 */ MCD_OPC_FilterValue, 38, 15, 0, // Skip to: 35933 >+/* 35918 */ MCD_OPC_CheckPredicate, 0, 139, 18, // Skip to: 40669 >+/* 35922 */ MCD_OPC_CheckField, 16, 8, 224, 1, 132, 18, // Skip to: 40669 >+/* 35929 */ MCD_OPC_Decode, 161, 1, 90, // Opcode: CMEQv1i64rz >+/* 35933 */ MCD_OPC_FilterValue, 42, 68, 0, // Skip to: 36005 >+/* 35937 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 35940 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35953 >+/* 35944 */ MCD_OPC_CheckPredicate, 0, 113, 18, // Skip to: 40669 >+/* 35948 */ MCD_OPC_Decode, 182, 3, 253, 1, // Opcode: FCVTNSv1i32 >+/* 35953 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 35965 >+/* 35957 */ MCD_OPC_CheckPredicate, 0, 100, 18, // Skip to: 40669 >+/* 35961 */ MCD_OPC_Decode, 183, 3, 90, // Opcode: FCVTNSv1i64 >+/* 35965 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 35979 >+/* 35970 */ MCD_OPC_CheckPredicate, 0, 87, 18, // Skip to: 40669 >+/* 35974 */ MCD_OPC_Decode, 204, 3, 253, 1, // Opcode: FCVTPSv1i32 >+/* 35979 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 35992 >+/* 35984 */ MCD_OPC_CheckPredicate, 0, 73, 18, // Skip to: 40669 >+/* 35988 */ MCD_OPC_Decode, 231, 1, 90, // Opcode: CMLTv1i64rz >+/* 35992 */ MCD_OPC_FilterValue, 225, 1, 64, 18, // Skip to: 40669 >+/* 35997 */ MCD_OPC_CheckPredicate, 0, 60, 18, // Skip to: 40669 >+/* 36001 */ MCD_OPC_Decode, 205, 3, 90, // Opcode: FCVTPSv1i64 >+/* 36005 */ MCD_OPC_FilterValue, 44, 29, 0, // Skip to: 36038 >+/* 36009 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36012 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36025 >+/* 36016 */ MCD_OPC_CheckPredicate, 0, 41, 18, // Skip to: 40669 >+/* 36020 */ MCD_OPC_Decode, 181, 11, 162, 2, // Opcode: SQDMLSLi16 >+/* 36025 */ MCD_OPC_FilterValue, 5, 32, 18, // Skip to: 40669 >+/* 36029 */ MCD_OPC_CheckPredicate, 0, 28, 18, // Skip to: 40669 >+/* 36033 */ MCD_OPC_Decode, 182, 11, 163, 2, // Opcode: SQDMLSLi32 >+/* 36038 */ MCD_OPC_FilterValue, 45, 29, 0, // Skip to: 36071 >+/* 36042 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36045 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36058 >+/* 36049 */ MCD_OPC_CheckPredicate, 0, 8, 18, // Skip to: 40669 >+/* 36053 */ MCD_OPC_Decode, 193, 11, 155, 2, // Opcode: SQDMULHv1i16 >+/* 36058 */ MCD_OPC_FilterValue, 5, 255, 17, // Skip to: 40669 >+/* 36062 */ MCD_OPC_CheckPredicate, 0, 251, 17, // Skip to: 40669 >+/* 36066 */ MCD_OPC_Decode, 195, 11, 130, 2, // Opcode: SQDMULHv1i32 >+/* 36071 */ MCD_OPC_FilterValue, 46, 79, 0, // Skip to: 36154 >+/* 36075 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 36078 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36091 >+/* 36082 */ MCD_OPC_CheckPredicate, 0, 231, 17, // Skip to: 40669 >+/* 36086 */ MCD_OPC_Decode, 164, 3, 253, 1, // Opcode: FCVTMSv1i32 >+/* 36091 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36103 >+/* 36095 */ MCD_OPC_CheckPredicate, 0, 218, 17, // Skip to: 40669 >+/* 36099 */ MCD_OPC_Decode, 165, 3, 90, // Opcode: FCVTMSv1i64 >+/* 36103 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36117 >+/* 36108 */ MCD_OPC_CheckPredicate, 0, 205, 17, // Skip to: 40669 >+/* 36112 */ MCD_OPC_Decode, 244, 3, 253, 1, // Opcode: FCVTZSv1i32 >+/* 36117 */ MCD_OPC_FilterValue, 224, 1, 7, 0, // Skip to: 36129 >+/* 36122 */ MCD_OPC_CheckPredicate, 0, 191, 17, // Skip to: 40669 >+/* 36126 */ MCD_OPC_Decode, 21, 90, // Opcode: ABSv1i64 >+/* 36129 */ MCD_OPC_FilterValue, 225, 1, 8, 0, // Skip to: 36142 >+/* 36134 */ MCD_OPC_CheckPredicate, 0, 179, 17, // Skip to: 40669 >+/* 36138 */ MCD_OPC_Decode, 245, 3, 90, // Opcode: FCVTZSv1i64 >+/* 36142 */ MCD_OPC_FilterValue, 241, 1, 170, 17, // Skip to: 40669 >+/* 36147 */ MCD_OPC_CheckPredicate, 0, 166, 17, // Skip to: 40669 >+/* 36151 */ MCD_OPC_Decode, 41, 95, // Opcode: ADDPv2i64p >+/* 36154 */ MCD_OPC_FilterValue, 50, 55, 0, // Skip to: 36213 >+/* 36158 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 36161 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36174 >+/* 36165 */ MCD_OPC_CheckPredicate, 0, 148, 17, // Skip to: 40669 >+/* 36169 */ MCD_OPC_Decode, 138, 3, 253, 1, // Opcode: FCVTASv1i32 >+/* 36174 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36186 >+/* 36178 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 40669 >+/* 36182 */ MCD_OPC_Decode, 139, 3, 90, // Opcode: FCVTASv1i64 >+/* 36186 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36200 >+/* 36191 */ MCD_OPC_CheckPredicate, 0, 122, 17, // Skip to: 40669 >+/* 36195 */ MCD_OPC_Decode, 234, 2, 253, 1, // Opcode: FCMGTv1i32rz >+/* 36200 */ MCD_OPC_FilterValue, 224, 1, 112, 17, // Skip to: 40669 >+/* 36205 */ MCD_OPC_CheckPredicate, 0, 108, 17, // Skip to: 40669 >+/* 36209 */ MCD_OPC_Decode, 235, 2, 90, // Opcode: FCMGTv1i64rz >+/* 36213 */ MCD_OPC_FilterValue, 52, 29, 0, // Skip to: 36246 >+/* 36217 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36220 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36233 >+/* 36224 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 40669 >+/* 36228 */ MCD_OPC_Decode, 205, 11, 164, 2, // Opcode: SQDMULLi16 >+/* 36233 */ MCD_OPC_FilterValue, 5, 80, 17, // Skip to: 40669 >+/* 36237 */ MCD_OPC_CheckPredicate, 0, 76, 17, // Skip to: 40669 >+/* 36241 */ MCD_OPC_Decode, 206, 11, 165, 2, // Opcode: SQDMULLi32 >+/* 36246 */ MCD_OPC_FilterValue, 54, 82, 0, // Skip to: 36332 >+/* 36250 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 36253 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36266 >+/* 36257 */ MCD_OPC_CheckPredicate, 0, 56, 17, // Skip to: 40669 >+/* 36261 */ MCD_OPC_Decode, 140, 10, 253, 1, // Opcode: SCVTFv1i32 >+/* 36266 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36278 >+/* 36270 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 40669 >+/* 36274 */ MCD_OPC_Decode, 141, 10, 90, // Opcode: SCVTFv1i64 >+/* 36278 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36292 >+/* 36283 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 40669 >+/* 36287 */ MCD_OPC_Decode, 214, 2, 253, 1, // Opcode: FCMEQv1i32rz >+/* 36292 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36306 >+/* 36297 */ MCD_OPC_CheckPredicate, 0, 16, 17, // Skip to: 40669 >+/* 36301 */ MCD_OPC_Decode, 138, 5, 253, 1, // Opcode: FRECPEv1i32 >+/* 36306 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 36319 >+/* 36311 */ MCD_OPC_CheckPredicate, 0, 2, 17, // Skip to: 40669 >+/* 36315 */ MCD_OPC_Decode, 215, 2, 90, // Opcode: FCMEQv1i64rz >+/* 36319 */ MCD_OPC_FilterValue, 225, 1, 249, 16, // Skip to: 40669 >+/* 36324 */ MCD_OPC_CheckPredicate, 0, 245, 16, // Skip to: 40669 >+/* 36328 */ MCD_OPC_Decode, 139, 5, 90, // Opcode: FRECPEv1i64 >+/* 36332 */ MCD_OPC_FilterValue, 55, 28, 0, // Skip to: 36364 >+/* 36336 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36339 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36352 >+/* 36343 */ MCD_OPC_CheckPredicate, 0, 226, 16, // Skip to: 40669 >+/* 36347 */ MCD_OPC_Decode, 237, 4, 130, 2, // Opcode: FMULX32 >+/* 36352 */ MCD_OPC_FilterValue, 3, 217, 16, // Skip to: 40669 >+/* 36356 */ MCD_OPC_CheckPredicate, 0, 213, 16, // Skip to: 40669 >+/* 36360 */ MCD_OPC_Decode, 238, 4, 89, // Opcode: FMULX64 >+/* 36364 */ MCD_OPC_FilterValue, 57, 28, 0, // Skip to: 36396 >+/* 36368 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36371 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36384 >+/* 36375 */ MCD_OPC_CheckPredicate, 0, 194, 16, // Skip to: 40669 >+/* 36379 */ MCD_OPC_Decode, 212, 2, 130, 2, // Opcode: FCMEQ32 >+/* 36384 */ MCD_OPC_FilterValue, 3, 185, 16, // Skip to: 40669 >+/* 36388 */ MCD_OPC_CheckPredicate, 0, 181, 16, // Skip to: 40669 >+/* 36392 */ MCD_OPC_Decode, 213, 2, 89, // Opcode: FCMEQ64 >+/* 36396 */ MCD_OPC_FilterValue, 58, 30, 0, // Skip to: 36430 >+/* 36400 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 36403 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36417 >+/* 36408 */ MCD_OPC_CheckPredicate, 0, 161, 16, // Skip to: 40669 >+/* 36412 */ MCD_OPC_Decode, 247, 2, 253, 1, // Opcode: FCMLTv1i32rz >+/* 36417 */ MCD_OPC_FilterValue, 224, 1, 151, 16, // Skip to: 40669 >+/* 36422 */ MCD_OPC_CheckPredicate, 0, 147, 16, // Skip to: 40669 >+/* 36426 */ MCD_OPC_Decode, 248, 2, 90, // Opcode: FCMLTv1i64rz >+/* 36430 */ MCD_OPC_FilterValue, 62, 30, 0, // Skip to: 36464 >+/* 36434 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 36437 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36451 >+/* 36442 */ MCD_OPC_CheckPredicate, 0, 127, 16, // Skip to: 40669 >+/* 36446 */ MCD_OPC_Decode, 148, 5, 253, 1, // Opcode: FRECPXv1i32 >+/* 36451 */ MCD_OPC_FilterValue, 225, 1, 117, 16, // Skip to: 40669 >+/* 36456 */ MCD_OPC_CheckPredicate, 0, 113, 16, // Skip to: 40669 >+/* 36460 */ MCD_OPC_Decode, 149, 5, 90, // Opcode: FRECPXv1i64 >+/* 36464 */ MCD_OPC_FilterValue, 63, 105, 16, // Skip to: 40669 >+/* 36468 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 36471 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36484 >+/* 36475 */ MCD_OPC_CheckPredicate, 0, 94, 16, // Skip to: 40669 >+/* 36479 */ MCD_OPC_Decode, 143, 5, 130, 2, // Opcode: FRECPS32 >+/* 36484 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 36496 >+/* 36488 */ MCD_OPC_CheckPredicate, 0, 81, 16, // Skip to: 40669 >+/* 36492 */ MCD_OPC_Decode, 144, 5, 89, // Opcode: FRECPS64 >+/* 36496 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 36509 >+/* 36500 */ MCD_OPC_CheckPredicate, 0, 69, 16, // Skip to: 40669 >+/* 36504 */ MCD_OPC_Decode, 190, 5, 130, 2, // Opcode: FRSQRTS32 >+/* 36509 */ MCD_OPC_FilterValue, 7, 60, 16, // Skip to: 40669 >+/* 36513 */ MCD_OPC_CheckPredicate, 0, 56, 16, // Skip to: 40669 >+/* 36517 */ MCD_OPC_Decode, 191, 5, 89, // Opcode: FRSQRTS64 >+/* 36521 */ MCD_OPC_FilterValue, 3, 48, 16, // Skip to: 40669 >+/* 36525 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 36528 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36553 >+/* 36532 */ MCD_OPC_CheckPredicate, 0, 37, 16, // Skip to: 40669 >+/* 36536 */ MCD_OPC_CheckField, 22, 2, 1, 31, 16, // Skip to: 40669 >+/* 36542 */ MCD_OPC_CheckField, 10, 2, 1, 25, 16, // Skip to: 40669 >+/* 36548 */ MCD_OPC_Decode, 145, 13, 166, 2, // Opcode: SSHRd >+/* 36553 */ MCD_OPC_FilterValue, 1, 66, 0, // Skip to: 36623 >+/* 36557 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 36560 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36579 >+/* 36564 */ MCD_OPC_CheckPredicate, 0, 5, 16, // Skip to: 40669 >+/* 36568 */ MCD_OPC_CheckField, 10, 2, 1, 255, 15, // Skip to: 40669 >+/* 36574 */ MCD_OPC_Decode, 153, 13, 167, 2, // Opcode: SSRAd >+/* 36579 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36598 >+/* 36583 */ MCD_OPC_CheckPredicate, 0, 242, 15, // Skip to: 40669 >+/* 36587 */ MCD_OPC_CheckField, 10, 1, 0, 236, 15, // Skip to: 40669 >+/* 36593 */ MCD_OPC_Decode, 204, 4, 168, 2, // Opcode: FMLAv1i32_indexed >+/* 36598 */ MCD_OPC_FilterValue, 3, 227, 15, // Skip to: 40669 >+/* 36602 */ MCD_OPC_CheckPredicate, 0, 223, 15, // Skip to: 40669 >+/* 36606 */ MCD_OPC_CheckField, 21, 1, 0, 217, 15, // Skip to: 40669 >+/* 36612 */ MCD_OPC_CheckField, 10, 1, 0, 211, 15, // Skip to: 40669 >+/* 36618 */ MCD_OPC_Decode, 205, 4, 169, 2, // Opcode: FMLAv1i64_indexed >+/* 36623 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 36648 >+/* 36627 */ MCD_OPC_CheckPredicate, 0, 198, 15, // Skip to: 40669 >+/* 36631 */ MCD_OPC_CheckField, 22, 2, 1, 192, 15, // Skip to: 40669 >+/* 36637 */ MCD_OPC_CheckField, 10, 2, 1, 186, 15, // Skip to: 40669 >+/* 36643 */ MCD_OPC_Decode, 243, 12, 166, 2, // Opcode: SRSHRd >+/* 36648 */ MCD_OPC_FilterValue, 3, 61, 0, // Skip to: 36713 >+/* 36652 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 36655 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 36688 >+/* 36659 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 36662 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36675 >+/* 36666 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 40669 >+/* 36670 */ MCD_OPC_Decode, 171, 11, 170, 2, // Opcode: SQDMLALv1i32_indexed >+/* 36675 */ MCD_OPC_FilterValue, 2, 150, 15, // Skip to: 40669 >+/* 36679 */ MCD_OPC_CheckPredicate, 0, 146, 15, // Skip to: 40669 >+/* 36683 */ MCD_OPC_Decode, 172, 11, 171, 2, // Opcode: SQDMLALv1i64_indexed >+/* 36688 */ MCD_OPC_FilterValue, 1, 137, 15, // Skip to: 40669 >+/* 36692 */ MCD_OPC_CheckPredicate, 0, 133, 15, // Skip to: 40669 >+/* 36696 */ MCD_OPC_CheckField, 22, 2, 1, 127, 15, // Skip to: 40669 >+/* 36702 */ MCD_OPC_CheckField, 11, 1, 0, 121, 15, // Skip to: 40669 >+/* 36708 */ MCD_OPC_Decode, 251, 12, 167, 2, // Opcode: SRSRAd >+/* 36713 */ MCD_OPC_FilterValue, 5, 66, 0, // Skip to: 36783 >+/* 36717 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 36720 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36739 >+/* 36724 */ MCD_OPC_CheckPredicate, 0, 101, 15, // Skip to: 40669 >+/* 36728 */ MCD_OPC_CheckField, 10, 2, 1, 95, 15, // Skip to: 40669 >+/* 36734 */ MCD_OPC_Decode, 174, 10, 172, 2, // Opcode: SHLd >+/* 36739 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36758 >+/* 36743 */ MCD_OPC_CheckPredicate, 0, 82, 15, // Skip to: 40669 >+/* 36747 */ MCD_OPC_CheckField, 10, 1, 0, 76, 15, // Skip to: 40669 >+/* 36753 */ MCD_OPC_Decode, 212, 4, 168, 2, // Opcode: FMLSv1i32_indexed >+/* 36758 */ MCD_OPC_FilterValue, 3, 67, 15, // Skip to: 40669 >+/* 36762 */ MCD_OPC_CheckPredicate, 0, 63, 15, // Skip to: 40669 >+/* 36766 */ MCD_OPC_CheckField, 21, 1, 0, 57, 15, // Skip to: 40669 >+/* 36772 */ MCD_OPC_CheckField, 10, 1, 0, 51, 15, // Skip to: 40669 >+/* 36778 */ MCD_OPC_Decode, 213, 4, 169, 2, // Opcode: FMLSv1i64_indexed >+/* 36783 */ MCD_OPC_FilterValue, 7, 138, 0, // Skip to: 36925 >+/* 36787 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 36790 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 36867 >+/* 36794 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 36797 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 36848 >+/* 36801 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 36804 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36829 >+/* 36808 */ MCD_OPC_CheckPredicate, 0, 17, 15, // Skip to: 40669 >+/* 36812 */ MCD_OPC_CheckField, 19, 1, 1, 11, 15, // Skip to: 40669 >+/* 36818 */ MCD_OPC_CheckField, 10, 2, 1, 5, 15, // Skip to: 40669 >+/* 36824 */ MCD_OPC_Decode, 152, 12, 173, 2, // Opcode: SQSHLb >+/* 36829 */ MCD_OPC_FilterValue, 1, 252, 14, // Skip to: 40669 >+/* 36833 */ MCD_OPC_CheckPredicate, 0, 248, 14, // Skip to: 40669 >+/* 36837 */ MCD_OPC_CheckField, 10, 2, 1, 242, 14, // Skip to: 40669 >+/* 36843 */ MCD_OPC_Decode, 154, 12, 174, 2, // Opcode: SQSHLh >+/* 36848 */ MCD_OPC_FilterValue, 1, 233, 14, // Skip to: 40669 >+/* 36852 */ MCD_OPC_CheckPredicate, 0, 229, 14, // Skip to: 40669 >+/* 36856 */ MCD_OPC_CheckField, 10, 2, 1, 223, 14, // Skip to: 40669 >+/* 36862 */ MCD_OPC_Decode, 155, 12, 175, 2, // Opcode: SQSHLs >+/* 36867 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 36906 >+/* 36871 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... >+/* 36874 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 36887 >+/* 36878 */ MCD_OPC_CheckPredicate, 0, 203, 14, // Skip to: 40669 >+/* 36882 */ MCD_OPC_Decode, 183, 11, 170, 2, // Opcode: SQDMLSLv1i32_indexed >+/* 36887 */ MCD_OPC_FilterValue, 1, 194, 14, // Skip to: 40669 >+/* 36891 */ MCD_OPC_CheckPredicate, 0, 190, 14, // Skip to: 40669 >+/* 36895 */ MCD_OPC_CheckField, 11, 1, 0, 184, 14, // Skip to: 40669 >+/* 36901 */ MCD_OPC_Decode, 153, 12, 172, 2, // Opcode: SQSHLd >+/* 36906 */ MCD_OPC_FilterValue, 2, 175, 14, // Skip to: 40669 >+/* 36910 */ MCD_OPC_CheckPredicate, 0, 171, 14, // Skip to: 40669 >+/* 36914 */ MCD_OPC_CheckField, 10, 1, 0, 165, 14, // Skip to: 40669 >+/* 36920 */ MCD_OPC_Decode, 184, 11, 171, 2, // Opcode: SQDMLSLv1i64_indexed >+/* 36925 */ MCD_OPC_FilterValue, 9, 172, 0, // Skip to: 37101 >+/* 36929 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 36932 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 37057 >+/* 36936 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 36939 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 36998 >+/* 36943 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 36946 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 36985 >+/* 36950 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 36953 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 36972 >+/* 36957 */ MCD_OPC_CheckPredicate, 0, 124, 14, // Skip to: 40669 >+/* 36961 */ MCD_OPC_CheckField, 19, 1, 1, 118, 14, // Skip to: 40669 >+/* 36967 */ MCD_OPC_Decode, 174, 12, 176, 2, // Opcode: SQSHRNb >+/* 36972 */ MCD_OPC_FilterValue, 1, 109, 14, // Skip to: 40669 >+/* 36976 */ MCD_OPC_CheckPredicate, 0, 105, 14, // Skip to: 40669 >+/* 36980 */ MCD_OPC_Decode, 175, 12, 177, 2, // Opcode: SQSHRNh >+/* 36985 */ MCD_OPC_FilterValue, 1, 96, 14, // Skip to: 40669 >+/* 36989 */ MCD_OPC_CheckPredicate, 0, 92, 14, // Skip to: 40669 >+/* 36993 */ MCD_OPC_Decode, 176, 12, 178, 2, // Opcode: SQSHRNs >+/* 36998 */ MCD_OPC_FilterValue, 3, 83, 14, // Skip to: 40669 >+/* 37002 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 37005 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 37044 >+/* 37009 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 37012 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 37031 >+/* 37016 */ MCD_OPC_CheckPredicate, 0, 65, 14, // Skip to: 40669 >+/* 37020 */ MCD_OPC_CheckField, 19, 1, 1, 59, 14, // Skip to: 40669 >+/* 37026 */ MCD_OPC_Decode, 251, 11, 176, 2, // Opcode: SQRSHRNb >+/* 37031 */ MCD_OPC_FilterValue, 1, 50, 14, // Skip to: 40669 >+/* 37035 */ MCD_OPC_CheckPredicate, 0, 46, 14, // Skip to: 40669 >+/* 37039 */ MCD_OPC_Decode, 252, 11, 177, 2, // Opcode: SQRSHRNh >+/* 37044 */ MCD_OPC_FilterValue, 1, 37, 14, // Skip to: 40669 >+/* 37048 */ MCD_OPC_CheckPredicate, 0, 33, 14, // Skip to: 40669 >+/* 37052 */ MCD_OPC_Decode, 253, 11, 178, 2, // Opcode: SQRSHRNs >+/* 37057 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 37076 >+/* 37061 */ MCD_OPC_CheckPredicate, 0, 20, 14, // Skip to: 40669 >+/* 37065 */ MCD_OPC_CheckField, 10, 1, 0, 14, 14, // Skip to: 40669 >+/* 37071 */ MCD_OPC_Decode, 247, 4, 179, 2, // Opcode: FMULv1i32_indexed >+/* 37076 */ MCD_OPC_FilterValue, 3, 5, 14, // Skip to: 40669 >+/* 37080 */ MCD_OPC_CheckPredicate, 0, 1, 14, // Skip to: 40669 >+/* 37084 */ MCD_OPC_CheckField, 21, 1, 0, 251, 13, // Skip to: 40669 >+/* 37090 */ MCD_OPC_CheckField, 10, 1, 0, 245, 13, // Skip to: 40669 >+/* 37096 */ MCD_OPC_Decode, 248, 4, 180, 2, // Opcode: FMULv1i64_indexed >+/* 37101 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 37146 >+/* 37105 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 37108 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37127 >+/* 37112 */ MCD_OPC_CheckPredicate, 0, 225, 13, // Skip to: 40669 >+/* 37116 */ MCD_OPC_CheckField, 10, 1, 0, 219, 13, // Skip to: 40669 >+/* 37122 */ MCD_OPC_Decode, 207, 11, 181, 2, // Opcode: SQDMULLv1i32_indexed >+/* 37127 */ MCD_OPC_FilterValue, 2, 210, 13, // Skip to: 40669 >+/* 37131 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 40669 >+/* 37135 */ MCD_OPC_CheckField, 10, 1, 0, 200, 13, // Skip to: 40669 >+/* 37141 */ MCD_OPC_Decode, 208, 11, 182, 2, // Opcode: SQDMULLv1i64_indexed >+/* 37146 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 37191 >+/* 37150 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 37153 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37172 >+/* 37157 */ MCD_OPC_CheckPredicate, 0, 180, 13, // Skip to: 40669 >+/* 37161 */ MCD_OPC_CheckField, 10, 1, 0, 174, 13, // Skip to: 40669 >+/* 37167 */ MCD_OPC_Decode, 194, 11, 183, 2, // Opcode: SQDMULHv1i16_indexed >+/* 37172 */ MCD_OPC_FilterValue, 2, 165, 13, // Skip to: 40669 >+/* 37176 */ MCD_OPC_CheckPredicate, 0, 161, 13, // Skip to: 40669 >+/* 37180 */ MCD_OPC_CheckField, 10, 1, 0, 155, 13, // Skip to: 40669 >+/* 37186 */ MCD_OPC_Decode, 196, 11, 179, 2, // Opcode: SQDMULHv1i32_indexed >+/* 37191 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 37236 >+/* 37195 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 37198 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37217 >+/* 37202 */ MCD_OPC_CheckPredicate, 0, 135, 13, // Skip to: 40669 >+/* 37206 */ MCD_OPC_CheckField, 10, 1, 0, 129, 13, // Skip to: 40669 >+/* 37212 */ MCD_OPC_Decode, 229, 11, 183, 2, // Opcode: SQRDMULHv1i16_indexed >+/* 37217 */ MCD_OPC_FilterValue, 2, 120, 13, // Skip to: 40669 >+/* 37221 */ MCD_OPC_CheckPredicate, 0, 116, 13, // Skip to: 40669 >+/* 37225 */ MCD_OPC_CheckField, 10, 1, 0, 110, 13, // Skip to: 40669 >+/* 37231 */ MCD_OPC_Decode, 231, 11, 179, 2, // Opcode: SQRDMULHv1i32_indexed >+/* 37236 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 37287 >+/* 37240 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 37243 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37268 >+/* 37247 */ MCD_OPC_CheckPredicate, 0, 90, 13, // Skip to: 40669 >+/* 37251 */ MCD_OPC_CheckField, 21, 1, 1, 84, 13, // Skip to: 40669 >+/* 37257 */ MCD_OPC_CheckField, 10, 2, 1, 78, 13, // Skip to: 40669 >+/* 37263 */ MCD_OPC_Decode, 139, 10, 184, 2, // Opcode: SCVTFs >+/* 37268 */ MCD_OPC_FilterValue, 1, 69, 13, // Skip to: 40669 >+/* 37272 */ MCD_OPC_CheckPredicate, 0, 65, 13, // Skip to: 40669 >+/* 37276 */ MCD_OPC_CheckField, 10, 2, 1, 59, 13, // Skip to: 40669 >+/* 37282 */ MCD_OPC_Decode, 138, 10, 166, 2, // Opcode: SCVTFd >+/* 37287 */ MCD_OPC_FilterValue, 15, 50, 13, // Skip to: 40669 >+/* 37291 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 37294 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37319 >+/* 37298 */ MCD_OPC_CheckPredicate, 0, 39, 13, // Skip to: 40669 >+/* 37302 */ MCD_OPC_CheckField, 21, 1, 1, 33, 13, // Skip to: 40669 >+/* 37308 */ MCD_OPC_CheckField, 10, 2, 3, 27, 13, // Skip to: 40669 >+/* 37314 */ MCD_OPC_Decode, 243, 3, 184, 2, // Opcode: FCVTZSs >+/* 37319 */ MCD_OPC_FilterValue, 1, 18, 13, // Skip to: 40669 >+/* 37323 */ MCD_OPC_CheckPredicate, 0, 14, 13, // Skip to: 40669 >+/* 37327 */ MCD_OPC_CheckField, 10, 2, 3, 8, 13, // Skip to: 40669 >+/* 37333 */ MCD_OPC_Decode, 242, 3, 166, 2, // Opcode: FCVTZSd >+/* 37338 */ MCD_OPC_FilterValue, 3, 212, 8, // Skip to: 39602 >+/* 37342 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 37345 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 37434 >+/* 37349 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 37352 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37367 >+/* 37356 */ MCD_OPC_CheckField, 21, 1, 0, 235, 12, // Skip to: 40669 >+/* 37362 */ MCD_OPC_Decode, 138, 15, 226, 1, // Opcode: STURHi >+/* 37367 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37382 >+/* 37371 */ MCD_OPC_CheckField, 21, 1, 0, 220, 12, // Skip to: 40669 >+/* 37377 */ MCD_OPC_Decode, 233, 14, 226, 1, // Opcode: STRHpost >+/* 37382 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37419 >+/* 37386 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 37389 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37404 >+/* 37393 */ MCD_OPC_CheckField, 21, 1, 1, 198, 12, // Skip to: 40669 >+/* 37399 */ MCD_OPC_Decode, 235, 14, 185, 2, // Opcode: STRHroW >+/* 37404 */ MCD_OPC_FilterValue, 3, 189, 12, // Skip to: 40669 >+/* 37408 */ MCD_OPC_CheckField, 21, 1, 1, 183, 12, // Skip to: 40669 >+/* 37414 */ MCD_OPC_Decode, 236, 14, 186, 2, // Opcode: STRHroX >+/* 37419 */ MCD_OPC_FilterValue, 3, 174, 12, // Skip to: 40669 >+/* 37423 */ MCD_OPC_CheckField, 21, 1, 0, 168, 12, // Skip to: 40669 >+/* 37429 */ MCD_OPC_Decode, 234, 14, 226, 1, // Opcode: STRHpre >+/* 37434 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 37523 >+/* 37438 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 37441 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37456 >+/* 37445 */ MCD_OPC_CheckField, 21, 1, 0, 146, 12, // Skip to: 40669 >+/* 37451 */ MCD_OPC_Decode, 157, 8, 226, 1, // Opcode: LDURHi >+/* 37456 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37471 >+/* 37460 */ MCD_OPC_CheckField, 21, 1, 0, 131, 12, // Skip to: 40669 >+/* 37466 */ MCD_OPC_Decode, 217, 7, 226, 1, // Opcode: LDRHpost >+/* 37471 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37508 >+/* 37475 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 37478 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37493 >+/* 37482 */ MCD_OPC_CheckField, 21, 1, 1, 109, 12, // Skip to: 40669 >+/* 37488 */ MCD_OPC_Decode, 219, 7, 185, 2, // Opcode: LDRHroW >+/* 37493 */ MCD_OPC_FilterValue, 3, 100, 12, // Skip to: 40669 >+/* 37497 */ MCD_OPC_CheckField, 21, 1, 1, 94, 12, // Skip to: 40669 >+/* 37503 */ MCD_OPC_Decode, 220, 7, 186, 2, // Opcode: LDRHroX >+/* 37508 */ MCD_OPC_FilterValue, 3, 85, 12, // Skip to: 40669 >+/* 37512 */ MCD_OPC_CheckField, 21, 1, 0, 79, 12, // Skip to: 40669 >+/* 37518 */ MCD_OPC_Decode, 218, 7, 226, 1, // Opcode: LDRHpre >+/* 37523 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 37532 >+/* 37527 */ MCD_OPC_Decode, 237, 14, 231, 1, // Opcode: STRHui >+/* 37532 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 37541 >+/* 37536 */ MCD_OPC_Decode, 221, 7, 231, 1, // Opcode: LDRHui >+/* 37541 */ MCD_OPC_FilterValue, 8, 60, 1, // Skip to: 37861 >+/* 37545 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 37548 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37567 >+/* 37552 */ MCD_OPC_CheckPredicate, 0, 41, 12, // Skip to: 40669 >+/* 37556 */ MCD_OPC_CheckField, 21, 1, 1, 35, 12, // Skip to: 40669 >+/* 37562 */ MCD_OPC_Decode, 141, 17, 154, 2, // Opcode: UQADDv1i8 >+/* 37567 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37586 >+/* 37571 */ MCD_OPC_CheckPredicate, 0, 22, 12, // Skip to: 40669 >+/* 37575 */ MCD_OPC_CheckField, 16, 6, 33, 16, 12, // Skip to: 40669 >+/* 37581 */ MCD_OPC_Decode, 215, 12, 159, 2, // Opcode: SQXTUNv1i8 >+/* 37586 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37605 >+/* 37590 */ MCD_OPC_CheckPredicate, 0, 3, 12, // Skip to: 40669 >+/* 37594 */ MCD_OPC_CheckField, 21, 1, 1, 253, 11, // Skip to: 40669 >+/* 37600 */ MCD_OPC_Decode, 203, 17, 154, 2, // Opcode: UQSUBv1i8 >+/* 37605 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37624 >+/* 37609 */ MCD_OPC_CheckPredicate, 0, 240, 11, // Skip to: 40669 >+/* 37613 */ MCD_OPC_CheckField, 16, 6, 32, 234, 11, // Skip to: 40669 >+/* 37619 */ MCD_OPC_Decode, 151, 18, 156, 2, // Opcode: USQADDv1i8 >+/* 37624 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37643 >+/* 37628 */ MCD_OPC_CheckPredicate, 0, 221, 11, // Skip to: 40669 >+/* 37632 */ MCD_OPC_CheckField, 16, 6, 33, 215, 11, // Skip to: 40669 >+/* 37638 */ MCD_OPC_Decode, 213, 17, 159, 2, // Opcode: UQXTNv1i8 >+/* 37643 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37662 >+/* 37647 */ MCD_OPC_CheckPredicate, 0, 202, 11, // Skip to: 40669 >+/* 37651 */ MCD_OPC_CheckField, 21, 1, 1, 196, 11, // Skip to: 40669 >+/* 37657 */ MCD_OPC_Decode, 177, 17, 154, 2, // Opcode: UQSHLv1i8 >+/* 37662 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 37681 >+/* 37666 */ MCD_OPC_CheckPredicate, 0, 183, 11, // Skip to: 40669 >+/* 37670 */ MCD_OPC_CheckField, 21, 1, 1, 177, 11, // Skip to: 40669 >+/* 37676 */ MCD_OPC_Decode, 152, 17, 154, 2, // Opcode: UQRSHLv1i8 >+/* 37681 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 37700 >+/* 37685 */ MCD_OPC_CheckPredicate, 0, 164, 11, // Skip to: 40669 >+/* 37689 */ MCD_OPC_CheckField, 16, 6, 32, 158, 11, // Skip to: 40669 >+/* 37695 */ MCD_OPC_Decode, 221, 11, 160, 2, // Opcode: SQNEGv1i8 >+/* 37700 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 37719 >+/* 37704 */ MCD_OPC_CheckPredicate, 0, 145, 11, // Skip to: 40669 >+/* 37708 */ MCD_OPC_CheckField, 16, 6, 33, 139, 11, // Skip to: 40669 >+/* 37714 */ MCD_OPC_Decode, 191, 3, 253, 1, // Opcode: FCVTNUv1i32 >+/* 37719 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 37738 >+/* 37723 */ MCD_OPC_CheckPredicate, 0, 126, 11, // Skip to: 40669 >+/* 37727 */ MCD_OPC_CheckField, 16, 6, 33, 120, 11, // Skip to: 40669 >+/* 37733 */ MCD_OPC_Decode, 173, 3, 253, 1, // Opcode: FCVTMUv1i32 >+/* 37738 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 37771 >+/* 37742 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 37745 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37758 >+/* 37749 */ MCD_OPC_CheckPredicate, 0, 100, 11, // Skip to: 40669 >+/* 37753 */ MCD_OPC_Decode, 147, 3, 253, 1, // Opcode: FCVTAUv1i32 >+/* 37758 */ MCD_OPC_FilterValue, 48, 91, 11, // Skip to: 40669 >+/* 37762 */ MCD_OPC_CheckPredicate, 0, 87, 11, // Skip to: 40669 >+/* 37766 */ MCD_OPC_Decode, 164, 4, 144, 1, // Opcode: FMAXNMPv2i32p >+/* 37771 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 37804 >+/* 37775 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 37778 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37791 >+/* 37782 */ MCD_OPC_CheckPredicate, 0, 67, 11, // Skip to: 40669 >+/* 37786 */ MCD_OPC_Decode, 170, 16, 253, 1, // Opcode: UCVTFv1i32 >+/* 37791 */ MCD_OPC_FilterValue, 48, 58, 11, // Skip to: 40669 >+/* 37795 */ MCD_OPC_CheckPredicate, 0, 54, 11, // Skip to: 40669 >+/* 37799 */ MCD_OPC_Decode, 201, 2, 144, 1, // Opcode: FADDPv2i32p >+/* 37804 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 37823 >+/* 37808 */ MCD_OPC_CheckPredicate, 0, 41, 11, // Skip to: 40669 >+/* 37812 */ MCD_OPC_CheckField, 21, 1, 1, 35, 11, // Skip to: 40669 >+/* 37818 */ MCD_OPC_Decode, 222, 2, 130, 2, // Opcode: FCMGE32 >+/* 37823 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 37842 >+/* 37827 */ MCD_OPC_CheckPredicate, 0, 22, 11, // Skip to: 40669 >+/* 37831 */ MCD_OPC_CheckField, 21, 1, 1, 16, 11, // Skip to: 40669 >+/* 37837 */ MCD_OPC_Decode, 188, 2, 130, 2, // Opcode: FACGE32 >+/* 37842 */ MCD_OPC_FilterValue, 62, 7, 11, // Skip to: 40669 >+/* 37846 */ MCD_OPC_CheckPredicate, 0, 3, 11, // Skip to: 40669 >+/* 37850 */ MCD_OPC_CheckField, 16, 6, 48, 253, 10, // Skip to: 40669 >+/* 37856 */ MCD_OPC_Decode, 174, 4, 144, 1, // Opcode: FMAXPv2i32p >+/* 37861 */ MCD_OPC_FilterValue, 9, 89, 1, // Skip to: 38210 >+/* 37865 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 37868 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37887 >+/* 37872 */ MCD_OPC_CheckPredicate, 0, 233, 10, // Skip to: 40669 >+/* 37876 */ MCD_OPC_CheckField, 21, 1, 1, 227, 10, // Skip to: 40669 >+/* 37882 */ MCD_OPC_Decode, 138, 17, 155, 2, // Opcode: UQADDv1i16 >+/* 37887 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37906 >+/* 37891 */ MCD_OPC_CheckPredicate, 0, 214, 10, // Skip to: 40669 >+/* 37895 */ MCD_OPC_CheckField, 16, 6, 33, 208, 10, // Skip to: 40669 >+/* 37901 */ MCD_OPC_Decode, 213, 12, 255, 1, // Opcode: SQXTUNv1i16 >+/* 37906 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37925 >+/* 37910 */ MCD_OPC_CheckPredicate, 0, 195, 10, // Skip to: 40669 >+/* 37914 */ MCD_OPC_CheckField, 21, 1, 1, 189, 10, // Skip to: 40669 >+/* 37920 */ MCD_OPC_Decode, 200, 17, 155, 2, // Opcode: UQSUBv1i16 >+/* 37925 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37944 >+/* 37929 */ MCD_OPC_CheckPredicate, 0, 176, 10, // Skip to: 40669 >+/* 37933 */ MCD_OPC_CheckField, 16, 6, 32, 170, 10, // Skip to: 40669 >+/* 37939 */ MCD_OPC_Decode, 148, 18, 157, 2, // Opcode: USQADDv1i16 >+/* 37944 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37963 >+/* 37948 */ MCD_OPC_CheckPredicate, 0, 157, 10, // Skip to: 40669 >+/* 37952 */ MCD_OPC_CheckField, 16, 6, 33, 151, 10, // Skip to: 40669 >+/* 37958 */ MCD_OPC_Decode, 211, 17, 255, 1, // Opcode: UQXTNv1i16 >+/* 37963 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37982 >+/* 37967 */ MCD_OPC_CheckPredicate, 0, 138, 10, // Skip to: 40669 >+/* 37971 */ MCD_OPC_CheckField, 21, 1, 1, 132, 10, // Skip to: 40669 >+/* 37977 */ MCD_OPC_Decode, 174, 17, 155, 2, // Opcode: UQSHLv1i16 >+/* 37982 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 38001 >+/* 37986 */ MCD_OPC_CheckPredicate, 0, 119, 10, // Skip to: 40669 >+/* 37990 */ MCD_OPC_CheckField, 21, 1, 1, 113, 10, // Skip to: 40669 >+/* 37996 */ MCD_OPC_Decode, 149, 17, 155, 2, // Opcode: UQRSHLv1i16 >+/* 38001 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 38020 >+/* 38005 */ MCD_OPC_CheckPredicate, 0, 100, 10, // Skip to: 40669 >+/* 38009 */ MCD_OPC_CheckField, 16, 6, 33, 94, 10, // Skip to: 40669 >+/* 38015 */ MCD_OPC_Decode, 220, 3, 144, 1, // Opcode: FCVTXNv1i64 >+/* 38020 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38039 >+/* 38024 */ MCD_OPC_CheckPredicate, 0, 81, 10, // Skip to: 40669 >+/* 38028 */ MCD_OPC_CheckField, 16, 6, 32, 75, 10, // Skip to: 40669 >+/* 38034 */ MCD_OPC_Decode, 218, 11, 161, 2, // Opcode: SQNEGv1i16 >+/* 38039 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38057 >+/* 38043 */ MCD_OPC_CheckPredicate, 0, 62, 10, // Skip to: 40669 >+/* 38047 */ MCD_OPC_CheckField, 16, 6, 33, 56, 10, // Skip to: 40669 >+/* 38053 */ MCD_OPC_Decode, 192, 3, 90, // Opcode: FCVTNUv1i64 >+/* 38057 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38076 >+/* 38061 */ MCD_OPC_CheckPredicate, 0, 44, 10, // Skip to: 40669 >+/* 38065 */ MCD_OPC_CheckField, 21, 1, 1, 38, 10, // Skip to: 40669 >+/* 38071 */ MCD_OPC_Decode, 228, 11, 155, 2, // Opcode: SQRDMULHv1i16 >+/* 38076 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 38094 >+/* 38080 */ MCD_OPC_CheckPredicate, 0, 25, 10, // Skip to: 40669 >+/* 38084 */ MCD_OPC_CheckField, 16, 6, 33, 19, 10, // Skip to: 40669 >+/* 38090 */ MCD_OPC_Decode, 174, 3, 90, // Opcode: FCVTMUv1i64 >+/* 38094 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38125 >+/* 38098 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38101 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38113 >+/* 38105 */ MCD_OPC_CheckPredicate, 0, 0, 10, // Skip to: 40669 >+/* 38109 */ MCD_OPC_Decode, 148, 3, 90, // Opcode: FCVTAUv1i64 >+/* 38113 */ MCD_OPC_FilterValue, 48, 248, 9, // Skip to: 40669 >+/* 38117 */ MCD_OPC_CheckPredicate, 0, 244, 9, // Skip to: 40669 >+/* 38121 */ MCD_OPC_Decode, 165, 4, 95, // Opcode: FMAXNMPv2i64p >+/* 38125 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38156 >+/* 38129 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38132 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38144 >+/* 38136 */ MCD_OPC_CheckPredicate, 0, 225, 9, // Skip to: 40669 >+/* 38140 */ MCD_OPC_Decode, 171, 16, 90, // Opcode: UCVTFv1i64 >+/* 38144 */ MCD_OPC_FilterValue, 48, 217, 9, // Skip to: 40669 >+/* 38148 */ MCD_OPC_CheckPredicate, 0, 213, 9, // Skip to: 40669 >+/* 38152 */ MCD_OPC_Decode, 202, 2, 95, // Opcode: FADDPv2i64p >+/* 38156 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38174 >+/* 38160 */ MCD_OPC_CheckPredicate, 0, 201, 9, // Skip to: 40669 >+/* 38164 */ MCD_OPC_CheckField, 21, 1, 1, 195, 9, // Skip to: 40669 >+/* 38170 */ MCD_OPC_Decode, 223, 2, 89, // Opcode: FCMGE64 >+/* 38174 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38192 >+/* 38178 */ MCD_OPC_CheckPredicate, 0, 183, 9, // Skip to: 40669 >+/* 38182 */ MCD_OPC_CheckField, 21, 1, 1, 177, 9, // Skip to: 40669 >+/* 38188 */ MCD_OPC_Decode, 189, 2, 89, // Opcode: FACGE64 >+/* 38192 */ MCD_OPC_FilterValue, 62, 169, 9, // Skip to: 40669 >+/* 38196 */ MCD_OPC_CheckPredicate, 0, 165, 9, // Skip to: 40669 >+/* 38200 */ MCD_OPC_CheckField, 16, 6, 48, 159, 9, // Skip to: 40669 >+/* 38206 */ MCD_OPC_Decode, 175, 4, 95, // Opcode: FMAXPv2i64p >+/* 38210 */ MCD_OPC_FilterValue, 10, 98, 1, // Skip to: 38568 >+/* 38214 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 38217 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 38236 >+/* 38221 */ MCD_OPC_CheckPredicate, 0, 140, 9, // Skip to: 40669 >+/* 38225 */ MCD_OPC_CheckField, 21, 1, 1, 134, 9, // Skip to: 40669 >+/* 38231 */ MCD_OPC_Decode, 139, 17, 130, 2, // Opcode: UQADDv1i32 >+/* 38236 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 38255 >+/* 38240 */ MCD_OPC_CheckPredicate, 0, 121, 9, // Skip to: 40669 >+/* 38244 */ MCD_OPC_CheckField, 16, 6, 33, 115, 9, // Skip to: 40669 >+/* 38250 */ MCD_OPC_Decode, 214, 12, 144, 1, // Opcode: SQXTUNv1i32 >+/* 38255 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 38274 >+/* 38259 */ MCD_OPC_CheckPredicate, 0, 102, 9, // Skip to: 40669 >+/* 38263 */ MCD_OPC_CheckField, 21, 1, 1, 96, 9, // Skip to: 40669 >+/* 38269 */ MCD_OPC_Decode, 201, 17, 130, 2, // Opcode: UQSUBv1i32 >+/* 38274 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 38293 >+/* 38278 */ MCD_OPC_CheckPredicate, 0, 83, 9, // Skip to: 40669 >+/* 38282 */ MCD_OPC_CheckField, 16, 6, 32, 77, 9, // Skip to: 40669 >+/* 38288 */ MCD_OPC_Decode, 149, 18, 158, 2, // Opcode: USQADDv1i32 >+/* 38293 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 38312 >+/* 38297 */ MCD_OPC_CheckPredicate, 0, 64, 9, // Skip to: 40669 >+/* 38301 */ MCD_OPC_CheckField, 16, 6, 33, 58, 9, // Skip to: 40669 >+/* 38307 */ MCD_OPC_Decode, 212, 17, 144, 1, // Opcode: UQXTNv1i32 >+/* 38312 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 38331 >+/* 38316 */ MCD_OPC_CheckPredicate, 0, 45, 9, // Skip to: 40669 >+/* 38320 */ MCD_OPC_CheckField, 21, 1, 1, 39, 9, // Skip to: 40669 >+/* 38326 */ MCD_OPC_Decode, 175, 17, 130, 2, // Opcode: UQSHLv1i32 >+/* 38331 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 38350 >+/* 38335 */ MCD_OPC_CheckPredicate, 0, 26, 9, // Skip to: 40669 >+/* 38339 */ MCD_OPC_CheckField, 21, 1, 1, 20, 9, // Skip to: 40669 >+/* 38345 */ MCD_OPC_Decode, 150, 17, 130, 2, // Opcode: UQRSHLv1i32 >+/* 38350 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38369 >+/* 38354 */ MCD_OPC_CheckPredicate, 0, 7, 9, // Skip to: 40669 >+/* 38358 */ MCD_OPC_CheckField, 16, 6, 32, 1, 9, // Skip to: 40669 >+/* 38364 */ MCD_OPC_Decode, 219, 11, 253, 1, // Opcode: SQNEGv1i32 >+/* 38369 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 38388 >+/* 38373 */ MCD_OPC_CheckPredicate, 0, 244, 8, // Skip to: 40669 >+/* 38377 */ MCD_OPC_CheckField, 16, 6, 33, 238, 8, // Skip to: 40669 >+/* 38383 */ MCD_OPC_Decode, 213, 3, 253, 1, // Opcode: FCVTPUv1i32 >+/* 38388 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38407 >+/* 38392 */ MCD_OPC_CheckPredicate, 0, 225, 8, // Skip to: 40669 >+/* 38396 */ MCD_OPC_CheckField, 21, 1, 1, 219, 8, // Skip to: 40669 >+/* 38402 */ MCD_OPC_Decode, 230, 11, 130, 2, // Opcode: SQRDMULHv1i32 >+/* 38407 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 38426 >+/* 38411 */ MCD_OPC_CheckPredicate, 0, 206, 8, // Skip to: 40669 >+/* 38415 */ MCD_OPC_CheckField, 16, 6, 33, 200, 8, // Skip to: 40669 >+/* 38421 */ MCD_OPC_Decode, 145, 4, 253, 1, // Opcode: FCVTZUv1i32 >+/* 38426 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 38459 >+/* 38430 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38433 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38446 >+/* 38437 */ MCD_OPC_CheckPredicate, 0, 180, 8, // Skip to: 40669 >+/* 38441 */ MCD_OPC_Decode, 224, 2, 253, 1, // Opcode: FCMGEv1i32rz >+/* 38446 */ MCD_OPC_FilterValue, 48, 171, 8, // Skip to: 40669 >+/* 38450 */ MCD_OPC_CheckPredicate, 0, 167, 8, // Skip to: 40669 >+/* 38454 */ MCD_OPC_Decode, 186, 4, 144, 1, // Opcode: FMINNMPv2i32p >+/* 38459 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 38478 >+/* 38463 */ MCD_OPC_CheckPredicate, 0, 154, 8, // Skip to: 40669 >+/* 38467 */ MCD_OPC_CheckField, 21, 1, 1, 148, 8, // Skip to: 40669 >+/* 38473 */ MCD_OPC_Decode, 178, 2, 130, 2, // Opcode: FABD32 >+/* 38478 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 38511 >+/* 38482 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38485 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38498 >+/* 38489 */ MCD_OPC_CheckPredicate, 0, 128, 8, // Skip to: 40669 >+/* 38493 */ MCD_OPC_Decode, 242, 2, 253, 1, // Opcode: FCMLEv1i32rz >+/* 38498 */ MCD_OPC_FilterValue, 33, 119, 8, // Skip to: 40669 >+/* 38502 */ MCD_OPC_CheckPredicate, 0, 115, 8, // Skip to: 40669 >+/* 38506 */ MCD_OPC_Decode, 185, 5, 253, 1, // Opcode: FRSQRTEv1i32 >+/* 38511 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 38530 >+/* 38515 */ MCD_OPC_CheckPredicate, 0, 102, 8, // Skip to: 40669 >+/* 38519 */ MCD_OPC_CheckField, 21, 1, 1, 96, 8, // Skip to: 40669 >+/* 38525 */ MCD_OPC_Decode, 232, 2, 130, 2, // Opcode: FCMGT32 >+/* 38530 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 38549 >+/* 38534 */ MCD_OPC_CheckPredicate, 0, 83, 8, // Skip to: 40669 >+/* 38538 */ MCD_OPC_CheckField, 21, 1, 1, 77, 8, // Skip to: 40669 >+/* 38544 */ MCD_OPC_Decode, 193, 2, 130, 2, // Opcode: FACGT32 >+/* 38549 */ MCD_OPC_FilterValue, 62, 68, 8, // Skip to: 40669 >+/* 38553 */ MCD_OPC_CheckPredicate, 0, 64, 8, // Skip to: 40669 >+/* 38557 */ MCD_OPC_CheckField, 16, 6, 48, 58, 8, // Skip to: 40669 >+/* 38563 */ MCD_OPC_Decode, 196, 4, 144, 1, // Opcode: FMINPv2i32p >+/* 38568 */ MCD_OPC_FilterValue, 11, 182, 1, // Skip to: 39010 >+/* 38572 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 38575 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 38593 >+/* 38579 */ MCD_OPC_CheckPredicate, 0, 38, 8, // Skip to: 40669 >+/* 38583 */ MCD_OPC_CheckField, 21, 1, 1, 32, 8, // Skip to: 40669 >+/* 38589 */ MCD_OPC_Decode, 140, 17, 89, // Opcode: UQADDv1i64 >+/* 38593 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 38611 >+/* 38597 */ MCD_OPC_CheckPredicate, 0, 20, 8, // Skip to: 40669 >+/* 38601 */ MCD_OPC_CheckField, 21, 1, 1, 14, 8, // Skip to: 40669 >+/* 38607 */ MCD_OPC_Decode, 202, 17, 89, // Opcode: UQSUBv1i64 >+/* 38611 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 38629 >+/* 38615 */ MCD_OPC_CheckPredicate, 0, 2, 8, // Skip to: 40669 >+/* 38619 */ MCD_OPC_CheckField, 21, 1, 1, 252, 7, // Skip to: 40669 >+/* 38625 */ MCD_OPC_Decode, 207, 1, 89, // Opcode: CMHIv1i64 >+/* 38629 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 38647 >+/* 38633 */ MCD_OPC_CheckPredicate, 0, 240, 7, // Skip to: 40669 >+/* 38637 */ MCD_OPC_CheckField, 16, 6, 32, 234, 7, // Skip to: 40669 >+/* 38643 */ MCD_OPC_Decode, 150, 18, 99, // Opcode: USQADDv1i64 >+/* 38647 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 38665 >+/* 38651 */ MCD_OPC_CheckPredicate, 0, 222, 7, // Skip to: 40669 >+/* 38655 */ MCD_OPC_CheckField, 21, 1, 1, 216, 7, // Skip to: 40669 >+/* 38661 */ MCD_OPC_Decode, 215, 1, 89, // Opcode: CMHSv1i64 >+/* 38665 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 38683 >+/* 38669 */ MCD_OPC_CheckPredicate, 0, 204, 7, // Skip to: 40669 >+/* 38673 */ MCD_OPC_CheckField, 21, 1, 1, 198, 7, // Skip to: 40669 >+/* 38679 */ MCD_OPC_Decode, 132, 18, 89, // Opcode: USHLv1i64 >+/* 38683 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 38701 >+/* 38687 */ MCD_OPC_CheckPredicate, 0, 186, 7, // Skip to: 40669 >+/* 38691 */ MCD_OPC_CheckField, 21, 1, 1, 180, 7, // Skip to: 40669 >+/* 38697 */ MCD_OPC_Decode, 176, 17, 89, // Opcode: UQSHLv1i64 >+/* 38701 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 38719 >+/* 38705 */ MCD_OPC_CheckPredicate, 0, 168, 7, // Skip to: 40669 >+/* 38709 */ MCD_OPC_CheckField, 21, 1, 1, 162, 7, // Skip to: 40669 >+/* 38715 */ MCD_OPC_Decode, 228, 17, 89, // Opcode: URSHLv1i64 >+/* 38719 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 38737 >+/* 38723 */ MCD_OPC_CheckPredicate, 0, 150, 7, // Skip to: 40669 >+/* 38727 */ MCD_OPC_CheckField, 21, 1, 1, 144, 7, // Skip to: 40669 >+/* 38733 */ MCD_OPC_Decode, 151, 17, 89, // Opcode: UQRSHLv1i64 >+/* 38737 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 38755 >+/* 38741 */ MCD_OPC_CheckPredicate, 0, 132, 7, // Skip to: 40669 >+/* 38745 */ MCD_OPC_CheckField, 16, 6, 32, 126, 7, // Skip to: 40669 >+/* 38751 */ MCD_OPC_Decode, 220, 11, 90, // Opcode: SQNEGv1i64 >+/* 38755 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 38773 >+/* 38759 */ MCD_OPC_CheckPredicate, 0, 114, 7, // Skip to: 40669 >+/* 38763 */ MCD_OPC_CheckField, 21, 1, 1, 108, 7, // Skip to: 40669 >+/* 38769 */ MCD_OPC_Decode, 174, 15, 89, // Opcode: SUBv1i64 >+/* 38773 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 38791 >+/* 38777 */ MCD_OPC_CheckPredicate, 0, 96, 7, // Skip to: 40669 >+/* 38781 */ MCD_OPC_CheckField, 16, 6, 32, 90, 7, // Skip to: 40669 >+/* 38787 */ MCD_OPC_Decode, 177, 1, 90, // Opcode: CMGEv1i64rz >+/* 38791 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 38809 >+/* 38795 */ MCD_OPC_CheckPredicate, 0, 78, 7, // Skip to: 40669 >+/* 38799 */ MCD_OPC_CheckField, 21, 1, 1, 72, 7, // Skip to: 40669 >+/* 38805 */ MCD_OPC_Decode, 160, 1, 89, // Opcode: CMEQv1i64 >+/* 38809 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 38827 >+/* 38813 */ MCD_OPC_CheckPredicate, 0, 60, 7, // Skip to: 40669 >+/* 38817 */ MCD_OPC_CheckField, 16, 6, 32, 54, 7, // Skip to: 40669 >+/* 38823 */ MCD_OPC_Decode, 223, 1, 90, // Opcode: CMLEv1i64rz >+/* 38827 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38845 >+/* 38831 */ MCD_OPC_CheckPredicate, 0, 42, 7, // Skip to: 40669 >+/* 38835 */ MCD_OPC_CheckField, 16, 6, 33, 36, 7, // Skip to: 40669 >+/* 38841 */ MCD_OPC_Decode, 214, 3, 90, // Opcode: FCVTPUv1i64 >+/* 38845 */ MCD_OPC_FilterValue, 46, 27, 0, // Skip to: 38876 >+/* 38849 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38852 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38864 >+/* 38856 */ MCD_OPC_CheckPredicate, 0, 17, 7, // Skip to: 40669 >+/* 38860 */ MCD_OPC_Decode, 246, 8, 90, // Opcode: NEGv1i64 >+/* 38864 */ MCD_OPC_FilterValue, 33, 9, 7, // Skip to: 40669 >+/* 38868 */ MCD_OPC_CheckPredicate, 0, 5, 7, // Skip to: 40669 >+/* 38872 */ MCD_OPC_Decode, 146, 4, 90, // Opcode: FCVTZUv1i64 >+/* 38876 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38907 >+/* 38880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38883 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38895 >+/* 38887 */ MCD_OPC_CheckPredicate, 0, 242, 6, // Skip to: 40669 >+/* 38891 */ MCD_OPC_Decode, 225, 2, 90, // Opcode: FCMGEv1i64rz >+/* 38895 */ MCD_OPC_FilterValue, 48, 234, 6, // Skip to: 40669 >+/* 38899 */ MCD_OPC_CheckPredicate, 0, 230, 6, // Skip to: 40669 >+/* 38903 */ MCD_OPC_Decode, 187, 4, 95, // Opcode: FMINNMPv2i64p >+/* 38907 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 38925 >+/* 38911 */ MCD_OPC_CheckPredicate, 0, 218, 6, // Skip to: 40669 >+/* 38915 */ MCD_OPC_CheckField, 21, 1, 1, 212, 6, // Skip to: 40669 >+/* 38921 */ MCD_OPC_Decode, 179, 2, 89, // Opcode: FABD64 >+/* 38925 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38956 >+/* 38929 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... >+/* 38932 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38944 >+/* 38936 */ MCD_OPC_CheckPredicate, 0, 193, 6, // Skip to: 40669 >+/* 38940 */ MCD_OPC_Decode, 243, 2, 90, // Opcode: FCMLEv1i64rz >+/* 38944 */ MCD_OPC_FilterValue, 33, 185, 6, // Skip to: 40669 >+/* 38948 */ MCD_OPC_CheckPredicate, 0, 181, 6, // Skip to: 40669 >+/* 38952 */ MCD_OPC_Decode, 186, 5, 90, // Opcode: FRSQRTEv1i64 >+/* 38956 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38974 >+/* 38960 */ MCD_OPC_CheckPredicate, 0, 169, 6, // Skip to: 40669 >+/* 38964 */ MCD_OPC_CheckField, 21, 1, 1, 163, 6, // Skip to: 40669 >+/* 38970 */ MCD_OPC_Decode, 233, 2, 89, // Opcode: FCMGT64 >+/* 38974 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38992 >+/* 38978 */ MCD_OPC_CheckPredicate, 0, 151, 6, // Skip to: 40669 >+/* 38982 */ MCD_OPC_CheckField, 21, 1, 1, 145, 6, // Skip to: 40669 >+/* 38988 */ MCD_OPC_Decode, 194, 2, 89, // Opcode: FACGT64 >+/* 38992 */ MCD_OPC_FilterValue, 62, 137, 6, // Skip to: 40669 >+/* 38996 */ MCD_OPC_CheckPredicate, 0, 133, 6, // Skip to: 40669 >+/* 39000 */ MCD_OPC_CheckField, 16, 6, 48, 127, 6, // Skip to: 40669 >+/* 39006 */ MCD_OPC_Decode, 197, 4, 95, // Opcode: FMINPv2i64p >+/* 39010 */ MCD_OPC_FilterValue, 12, 139, 1, // Skip to: 39409 >+/* 39014 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 39017 */ MCD_OPC_FilterValue, 25, 55, 0, // Skip to: 39076 >+/* 39021 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39024 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39063 >+/* 39028 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39031 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39050 >+/* 39035 */ MCD_OPC_CheckPredicate, 0, 94, 6, // Skip to: 40669 >+/* 39039 */ MCD_OPC_CheckField, 19, 1, 1, 88, 6, // Skip to: 40669 >+/* 39045 */ MCD_OPC_Decode, 141, 12, 173, 2, // Opcode: SQSHLUb >+/* 39050 */ MCD_OPC_FilterValue, 1, 79, 6, // Skip to: 40669 >+/* 39054 */ MCD_OPC_CheckPredicate, 0, 75, 6, // Skip to: 40669 >+/* 39058 */ MCD_OPC_Decode, 143, 12, 174, 2, // Opcode: SQSHLUh >+/* 39063 */ MCD_OPC_FilterValue, 1, 66, 6, // Skip to: 40669 >+/* 39067 */ MCD_OPC_CheckPredicate, 0, 62, 6, // Skip to: 40669 >+/* 39071 */ MCD_OPC_Decode, 144, 12, 175, 2, // Opcode: SQSHLUs >+/* 39076 */ MCD_OPC_FilterValue, 29, 55, 0, // Skip to: 39135 >+/* 39080 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39083 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39122 >+/* 39087 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39090 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39109 >+/* 39094 */ MCD_OPC_CheckPredicate, 0, 35, 6, // Skip to: 40669 >+/* 39098 */ MCD_OPC_CheckField, 19, 1, 1, 29, 6, // Skip to: 40669 >+/* 39104 */ MCD_OPC_Decode, 168, 17, 173, 2, // Opcode: UQSHLb >+/* 39109 */ MCD_OPC_FilterValue, 1, 20, 6, // Skip to: 40669 >+/* 39113 */ MCD_OPC_CheckPredicate, 0, 16, 6, // Skip to: 40669 >+/* 39117 */ MCD_OPC_Decode, 170, 17, 174, 2, // Opcode: UQSHLh >+/* 39122 */ MCD_OPC_FilterValue, 1, 7, 6, // Skip to: 40669 >+/* 39126 */ MCD_OPC_CheckPredicate, 0, 3, 6, // Skip to: 40669 >+/* 39130 */ MCD_OPC_Decode, 171, 17, 175, 2, // Opcode: UQSHLs >+/* 39135 */ MCD_OPC_FilterValue, 33, 55, 0, // Skip to: 39194 >+/* 39139 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39142 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39181 >+/* 39146 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39149 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39168 >+/* 39153 */ MCD_OPC_CheckPredicate, 0, 232, 5, // Skip to: 40669 >+/* 39157 */ MCD_OPC_CheckField, 19, 1, 1, 226, 5, // Skip to: 40669 >+/* 39163 */ MCD_OPC_Decode, 183, 12, 176, 2, // Opcode: SQSHRUNb >+/* 39168 */ MCD_OPC_FilterValue, 1, 217, 5, // Skip to: 40669 >+/* 39172 */ MCD_OPC_CheckPredicate, 0, 213, 5, // Skip to: 40669 >+/* 39176 */ MCD_OPC_Decode, 184, 12, 177, 2, // Opcode: SQSHRUNh >+/* 39181 */ MCD_OPC_FilterValue, 1, 204, 5, // Skip to: 40669 >+/* 39185 */ MCD_OPC_CheckPredicate, 0, 200, 5, // Skip to: 40669 >+/* 39189 */ MCD_OPC_Decode, 185, 12, 178, 2, // Opcode: SQSHRUNs >+/* 39194 */ MCD_OPC_FilterValue, 35, 55, 0, // Skip to: 39253 >+/* 39198 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39201 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39240 >+/* 39205 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39208 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39227 >+/* 39212 */ MCD_OPC_CheckPredicate, 0, 173, 5, // Skip to: 40669 >+/* 39216 */ MCD_OPC_CheckField, 19, 1, 1, 167, 5, // Skip to: 40669 >+/* 39222 */ MCD_OPC_Decode, 132, 12, 176, 2, // Opcode: SQRSHRUNb >+/* 39227 */ MCD_OPC_FilterValue, 1, 158, 5, // Skip to: 40669 >+/* 39231 */ MCD_OPC_CheckPredicate, 0, 154, 5, // Skip to: 40669 >+/* 39235 */ MCD_OPC_Decode, 133, 12, 177, 2, // Opcode: SQRSHRUNh >+/* 39240 */ MCD_OPC_FilterValue, 1, 145, 5, // Skip to: 40669 >+/* 39244 */ MCD_OPC_CheckPredicate, 0, 141, 5, // Skip to: 40669 >+/* 39248 */ MCD_OPC_Decode, 134, 12, 178, 2, // Opcode: SQRSHRUNs >+/* 39253 */ MCD_OPC_FilterValue, 37, 55, 0, // Skip to: 39312 >+/* 39257 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39260 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39299 >+/* 39264 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39267 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39286 >+/* 39271 */ MCD_OPC_CheckPredicate, 0, 114, 5, // Skip to: 40669 >+/* 39275 */ MCD_OPC_CheckField, 19, 1, 1, 108, 5, // Skip to: 40669 >+/* 39281 */ MCD_OPC_Decode, 190, 17, 176, 2, // Opcode: UQSHRNb >+/* 39286 */ MCD_OPC_FilterValue, 1, 99, 5, // Skip to: 40669 >+/* 39290 */ MCD_OPC_CheckPredicate, 0, 95, 5, // Skip to: 40669 >+/* 39294 */ MCD_OPC_Decode, 191, 17, 177, 2, // Opcode: UQSHRNh >+/* 39299 */ MCD_OPC_FilterValue, 1, 86, 5, // Skip to: 40669 >+/* 39303 */ MCD_OPC_CheckPredicate, 0, 82, 5, // Skip to: 40669 >+/* 39307 */ MCD_OPC_Decode, 192, 17, 178, 2, // Opcode: UQSHRNs >+/* 39312 */ MCD_OPC_FilterValue, 39, 55, 0, // Skip to: 39371 >+/* 39316 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 39319 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39358 >+/* 39323 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 39326 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39345 >+/* 39330 */ MCD_OPC_CheckPredicate, 0, 55, 5, // Skip to: 40669 >+/* 39334 */ MCD_OPC_CheckField, 19, 1, 1, 49, 5, // Skip to: 40669 >+/* 39340 */ MCD_OPC_Decode, 159, 17, 176, 2, // Opcode: UQRSHRNb >+/* 39345 */ MCD_OPC_FilterValue, 1, 40, 5, // Skip to: 40669 >+/* 39349 */ MCD_OPC_CheckPredicate, 0, 36, 5, // Skip to: 40669 >+/* 39353 */ MCD_OPC_Decode, 160, 17, 177, 2, // Opcode: UQRSHRNh >+/* 39358 */ MCD_OPC_FilterValue, 1, 27, 5, // Skip to: 40669 >+/* 39362 */ MCD_OPC_CheckPredicate, 0, 23, 5, // Skip to: 40669 >+/* 39366 */ MCD_OPC_Decode, 161, 17, 178, 2, // Opcode: UQRSHRNs >+/* 39371 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39390 >+/* 39375 */ MCD_OPC_CheckPredicate, 0, 10, 5, // Skip to: 40669 >+/* 39379 */ MCD_OPC_CheckField, 21, 1, 1, 4, 5, // Skip to: 40669 >+/* 39385 */ MCD_OPC_Decode, 169, 16, 184, 2, // Opcode: UCVTFs >+/* 39390 */ MCD_OPC_FilterValue, 63, 251, 4, // Skip to: 40669 >+/* 39394 */ MCD_OPC_CheckPredicate, 0, 247, 4, // Skip to: 40669 >+/* 39398 */ MCD_OPC_CheckField, 21, 1, 1, 241, 4, // Skip to: 40669 >+/* 39404 */ MCD_OPC_Decode, 144, 4, 184, 2, // Opcode: FCVTZUs >+/* 39409 */ MCD_OPC_FilterValue, 13, 133, 0, // Skip to: 39546 >+/* 39413 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... >+/* 39416 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 39429 >+/* 39420 */ MCD_OPC_CheckPredicate, 0, 221, 4, // Skip to: 40669 >+/* 39424 */ MCD_OPC_Decode, 139, 18, 166, 2, // Opcode: USHRd >+/* 39429 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 39442 >+/* 39433 */ MCD_OPC_CheckPredicate, 0, 208, 4, // Skip to: 40669 >+/* 39437 */ MCD_OPC_Decode, 158, 18, 167, 2, // Opcode: USRAd >+/* 39442 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 39455 >+/* 39446 */ MCD_OPC_CheckPredicate, 0, 195, 4, // Skip to: 40669 >+/* 39450 */ MCD_OPC_Decode, 235, 17, 166, 2, // Opcode: URSHRd >+/* 39455 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 39468 >+/* 39459 */ MCD_OPC_CheckPredicate, 0, 182, 4, // Skip to: 40669 >+/* 39463 */ MCD_OPC_Decode, 245, 17, 167, 2, // Opcode: URSRAd >+/* 39468 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 39481 >+/* 39472 */ MCD_OPC_CheckPredicate, 0, 169, 4, // Skip to: 40669 >+/* 39476 */ MCD_OPC_Decode, 227, 12, 167, 2, // Opcode: SRId >+/* 39481 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 39494 >+/* 39485 */ MCD_OPC_CheckPredicate, 0, 156, 4, // Skip to: 40669 >+/* 39489 */ MCD_OPC_Decode, 194, 10, 187, 2, // Opcode: SLId >+/* 39494 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39507 >+/* 39498 */ MCD_OPC_CheckPredicate, 0, 143, 4, // Skip to: 40669 >+/* 39502 */ MCD_OPC_Decode, 142, 12, 172, 2, // Opcode: SQSHLUd >+/* 39507 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 39520 >+/* 39511 */ MCD_OPC_CheckPredicate, 0, 130, 4, // Skip to: 40669 >+/* 39515 */ MCD_OPC_Decode, 169, 17, 172, 2, // Opcode: UQSHLd >+/* 39520 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 39533 >+/* 39524 */ MCD_OPC_CheckPredicate, 0, 117, 4, // Skip to: 40669 >+/* 39528 */ MCD_OPC_Decode, 168, 16, 166, 2, // Opcode: UCVTFd >+/* 39533 */ MCD_OPC_FilterValue, 63, 108, 4, // Skip to: 40669 >+/* 39537 */ MCD_OPC_CheckPredicate, 0, 104, 4, // Skip to: 40669 >+/* 39541 */ MCD_OPC_Decode, 143, 4, 166, 2, // Opcode: FCVTZUd >+/* 39546 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 39571 >+/* 39550 */ MCD_OPC_CheckPredicate, 0, 91, 4, // Skip to: 40669 >+/* 39554 */ MCD_OPC_CheckField, 12, 4, 9, 85, 4, // Skip to: 40669 >+/* 39560 */ MCD_OPC_CheckField, 10, 1, 0, 79, 4, // Skip to: 40669 >+/* 39566 */ MCD_OPC_Decode, 239, 4, 179, 2, // Opcode: FMULXv1i32_indexed >+/* 39571 */ MCD_OPC_FilterValue, 15, 70, 4, // Skip to: 40669 >+/* 39575 */ MCD_OPC_CheckPredicate, 0, 66, 4, // Skip to: 40669 >+/* 39579 */ MCD_OPC_CheckField, 21, 1, 0, 60, 4, // Skip to: 40669 >+/* 39585 */ MCD_OPC_CheckField, 12, 4, 9, 54, 4, // Skip to: 40669 >+/* 39591 */ MCD_OPC_CheckField, 10, 1, 0, 48, 4, // Skip to: 40669 >+/* 39597 */ MCD_OPC_Decode, 240, 4, 180, 2, // Opcode: FMULXv1i64_indexed >+/* 39602 */ MCD_OPC_FilterValue, 4, 145, 2, // Skip to: 40263 >+/* 39606 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 39609 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 39618 >+/* 39613 */ MCD_OPC_Decode, 222, 7, 188, 2, // Opcode: LDRQl >+/* 39618 */ MCD_OPC_FilterValue, 2, 23, 4, // Skip to: 40669 >+/* 39622 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... >+/* 39625 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 39638 >+/* 39629 */ MCD_OPC_CheckPredicate, 3, 12, 4, // Skip to: 40669 >+/* 39633 */ MCD_OPC_Decode, 133, 10, 189, 2, // Opcode: SCVTFSXSri >+/* 39638 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 39651 >+/* 39642 */ MCD_OPC_CheckPredicate, 3, 255, 3, // Skip to: 40669 >+/* 39646 */ MCD_OPC_Decode, 163, 16, 189, 2, // Opcode: UCVTFSXSri >+/* 39651 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 39664 >+/* 39655 */ MCD_OPC_CheckPredicate, 3, 242, 3, // Skip to: 40669 >+/* 39659 */ MCD_OPC_Decode, 226, 3, 190, 2, // Opcode: FCVTZSSXSri >+/* 39664 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39677 >+/* 39668 */ MCD_OPC_CheckPredicate, 3, 229, 3, // Skip to: 40669 >+/* 39672 */ MCD_OPC_Decode, 255, 3, 190, 2, // Opcode: FCVTZUSXSri >+/* 39677 */ MCD_OPC_FilterValue, 32, 15, 0, // Skip to: 39696 >+/* 39681 */ MCD_OPC_CheckPredicate, 3, 216, 3, // Skip to: 40669 >+/* 39685 */ MCD_OPC_CheckField, 10, 6, 0, 210, 3, // Skip to: 40669 >+/* 39691 */ MCD_OPC_Decode, 181, 3, 191, 2, // Opcode: FCVTNSUXSr >+/* 39696 */ MCD_OPC_FilterValue, 33, 15, 0, // Skip to: 39715 >+/* 39700 */ MCD_OPC_CheckPredicate, 3, 197, 3, // Skip to: 40669 >+/* 39704 */ MCD_OPC_CheckField, 10, 6, 0, 191, 3, // Skip to: 40669 >+/* 39710 */ MCD_OPC_Decode, 190, 3, 191, 2, // Opcode: FCVTNUUXSr >+/* 39715 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 39734 >+/* 39719 */ MCD_OPC_CheckPredicate, 3, 178, 3, // Skip to: 40669 >+/* 39723 */ MCD_OPC_CheckField, 10, 6, 0, 172, 3, // Skip to: 40669 >+/* 39729 */ MCD_OPC_Decode, 137, 10, 192, 2, // Opcode: SCVTFUXSri >+/* 39734 */ MCD_OPC_FilterValue, 35, 15, 0, // Skip to: 39753 >+/* 39738 */ MCD_OPC_CheckPredicate, 3, 159, 3, // Skip to: 40669 >+/* 39742 */ MCD_OPC_CheckField, 10, 6, 0, 153, 3, // Skip to: 40669 >+/* 39748 */ MCD_OPC_Decode, 167, 16, 192, 2, // Opcode: UCVTFUXSri >+/* 39753 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 39772 >+/* 39757 */ MCD_OPC_CheckPredicate, 3, 140, 3, // Skip to: 40669 >+/* 39761 */ MCD_OPC_CheckField, 10, 6, 0, 134, 3, // Skip to: 40669 >+/* 39767 */ MCD_OPC_Decode, 137, 3, 191, 2, // Opcode: FCVTASUXSr >+/* 39772 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 39791 >+/* 39776 */ MCD_OPC_CheckPredicate, 3, 121, 3, // Skip to: 40669 >+/* 39780 */ MCD_OPC_CheckField, 10, 6, 0, 115, 3, // Skip to: 40669 >+/* 39786 */ MCD_OPC_Decode, 146, 3, 191, 2, // Opcode: FCVTAUUXSr >+/* 39791 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 39810 >+/* 39795 */ MCD_OPC_CheckPredicate, 3, 102, 3, // Skip to: 40669 >+/* 39799 */ MCD_OPC_CheckField, 10, 6, 0, 96, 3, // Skip to: 40669 >+/* 39805 */ MCD_OPC_Decode, 203, 3, 191, 2, // Opcode: FCVTPSUXSr >+/* 39810 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 39829 >+/* 39814 */ MCD_OPC_CheckPredicate, 3, 83, 3, // Skip to: 40669 >+/* 39818 */ MCD_OPC_CheckField, 10, 6, 0, 77, 3, // Skip to: 40669 >+/* 39824 */ MCD_OPC_Decode, 212, 3, 191, 2, // Opcode: FCVTPUUXSr >+/* 39829 */ MCD_OPC_FilterValue, 48, 15, 0, // Skip to: 39848 >+/* 39833 */ MCD_OPC_CheckPredicate, 3, 64, 3, // Skip to: 40669 >+/* 39837 */ MCD_OPC_CheckField, 10, 6, 0, 58, 3, // Skip to: 40669 >+/* 39843 */ MCD_OPC_Decode, 163, 3, 191, 2, // Opcode: FCVTMSUXSr >+/* 39848 */ MCD_OPC_FilterValue, 49, 15, 0, // Skip to: 39867 >+/* 39852 */ MCD_OPC_CheckPredicate, 3, 45, 3, // Skip to: 40669 >+/* 39856 */ MCD_OPC_CheckField, 10, 6, 0, 39, 3, // Skip to: 40669 >+/* 39862 */ MCD_OPC_Decode, 172, 3, 191, 2, // Opcode: FCVTMUUXSr >+/* 39867 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 39886 >+/* 39871 */ MCD_OPC_CheckPredicate, 3, 26, 3, // Skip to: 40669 >+/* 39875 */ MCD_OPC_CheckField, 10, 6, 0, 20, 3, // Skip to: 40669 >+/* 39881 */ MCD_OPC_Decode, 230, 3, 191, 2, // Opcode: FCVTZSUXSr >+/* 39886 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39905 >+/* 39890 */ MCD_OPC_CheckPredicate, 3, 7, 3, // Skip to: 40669 >+/* 39894 */ MCD_OPC_CheckField, 10, 6, 0, 1, 3, // Skip to: 40669 >+/* 39900 */ MCD_OPC_Decode, 131, 4, 191, 2, // Opcode: FCVTZUUXSr >+/* 39905 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 39918 >+/* 39909 */ MCD_OPC_CheckPredicate, 3, 244, 2, // Skip to: 40669 >+/* 39913 */ MCD_OPC_Decode, 132, 10, 193, 2, // Opcode: SCVTFSXDri >+/* 39918 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 39931 >+/* 39922 */ MCD_OPC_CheckPredicate, 3, 231, 2, // Skip to: 40669 >+/* 39926 */ MCD_OPC_Decode, 162, 16, 193, 2, // Opcode: UCVTFSXDri >+/* 39931 */ MCD_OPC_FilterValue, 88, 9, 0, // Skip to: 39944 >+/* 39935 */ MCD_OPC_CheckPredicate, 3, 218, 2, // Skip to: 40669 >+/* 39939 */ MCD_OPC_Decode, 225, 3, 194, 2, // Opcode: FCVTZSSXDri >+/* 39944 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 39957 >+/* 39948 */ MCD_OPC_CheckPredicate, 3, 205, 2, // Skip to: 40669 >+/* 39952 */ MCD_OPC_Decode, 254, 3, 194, 2, // Opcode: FCVTZUSXDri >+/* 39957 */ MCD_OPC_FilterValue, 96, 15, 0, // Skip to: 39976 >+/* 39961 */ MCD_OPC_CheckPredicate, 3, 192, 2, // Skip to: 40669 >+/* 39965 */ MCD_OPC_CheckField, 10, 6, 0, 186, 2, // Skip to: 40669 >+/* 39971 */ MCD_OPC_Decode, 180, 3, 195, 2, // Opcode: FCVTNSUXDr >+/* 39976 */ MCD_OPC_FilterValue, 97, 15, 0, // Skip to: 39995 >+/* 39980 */ MCD_OPC_CheckPredicate, 3, 173, 2, // Skip to: 40669 >+/* 39984 */ MCD_OPC_CheckField, 10, 6, 0, 167, 2, // Skip to: 40669 >+/* 39990 */ MCD_OPC_Decode, 189, 3, 195, 2, // Opcode: FCVTNUUXDr >+/* 39995 */ MCD_OPC_FilterValue, 98, 15, 0, // Skip to: 40014 >+/* 39999 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 40669 >+/* 40003 */ MCD_OPC_CheckField, 10, 6, 0, 148, 2, // Skip to: 40669 >+/* 40009 */ MCD_OPC_Decode, 136, 10, 196, 2, // Opcode: SCVTFUXDri >+/* 40014 */ MCD_OPC_FilterValue, 99, 15, 0, // Skip to: 40033 >+/* 40018 */ MCD_OPC_CheckPredicate, 3, 135, 2, // Skip to: 40669 >+/* 40022 */ MCD_OPC_CheckField, 10, 6, 0, 129, 2, // Skip to: 40669 >+/* 40028 */ MCD_OPC_Decode, 166, 16, 196, 2, // Opcode: UCVTFUXDri >+/* 40033 */ MCD_OPC_FilterValue, 100, 15, 0, // Skip to: 40052 >+/* 40037 */ MCD_OPC_CheckPredicate, 3, 116, 2, // Skip to: 40669 >+/* 40041 */ MCD_OPC_CheckField, 10, 6, 0, 110, 2, // Skip to: 40669 >+/* 40047 */ MCD_OPC_Decode, 136, 3, 195, 2, // Opcode: FCVTASUXDr >+/* 40052 */ MCD_OPC_FilterValue, 101, 15, 0, // Skip to: 40071 >+/* 40056 */ MCD_OPC_CheckPredicate, 3, 97, 2, // Skip to: 40669 >+/* 40060 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, // Skip to: 40669 >+/* 40066 */ MCD_OPC_Decode, 145, 3, 195, 2, // Opcode: FCVTAUUXDr >+/* 40071 */ MCD_OPC_FilterValue, 102, 15, 0, // Skip to: 40090 >+/* 40075 */ MCD_OPC_CheckPredicate, 3, 78, 2, // Skip to: 40669 >+/* 40079 */ MCD_OPC_CheckField, 10, 6, 0, 72, 2, // Skip to: 40669 >+/* 40085 */ MCD_OPC_Decode, 221, 4, 195, 2, // Opcode: FMOVDXr >+/* 40090 */ MCD_OPC_FilterValue, 103, 15, 0, // Skip to: 40109 >+/* 40094 */ MCD_OPC_CheckPredicate, 3, 59, 2, // Skip to: 40669 >+/* 40098 */ MCD_OPC_CheckField, 10, 6, 0, 53, 2, // Skip to: 40669 >+/* 40104 */ MCD_OPC_Decode, 229, 4, 196, 2, // Opcode: FMOVXDr >+/* 40109 */ MCD_OPC_FilterValue, 104, 15, 0, // Skip to: 40128 >+/* 40113 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 40669 >+/* 40117 */ MCD_OPC_CheckField, 10, 6, 0, 34, 2, // Skip to: 40669 >+/* 40123 */ MCD_OPC_Decode, 202, 3, 195, 2, // Opcode: FCVTPSUXDr >+/* 40128 */ MCD_OPC_FilterValue, 105, 15, 0, // Skip to: 40147 >+/* 40132 */ MCD_OPC_CheckPredicate, 3, 21, 2, // Skip to: 40669 >+/* 40136 */ MCD_OPC_CheckField, 10, 6, 0, 15, 2, // Skip to: 40669 >+/* 40142 */ MCD_OPC_Decode, 211, 3, 195, 2, // Opcode: FCVTPUUXDr >+/* 40147 */ MCD_OPC_FilterValue, 112, 15, 0, // Skip to: 40166 >+/* 40151 */ MCD_OPC_CheckPredicate, 3, 2, 2, // Skip to: 40669 >+/* 40155 */ MCD_OPC_CheckField, 10, 6, 0, 252, 1, // Skip to: 40669 >+/* 40161 */ MCD_OPC_Decode, 162, 3, 195, 2, // Opcode: FCVTMSUXDr >+/* 40166 */ MCD_OPC_FilterValue, 113, 15, 0, // Skip to: 40185 >+/* 40170 */ MCD_OPC_CheckPredicate, 3, 239, 1, // Skip to: 40669 >+/* 40174 */ MCD_OPC_CheckField, 10, 6, 0, 233, 1, // Skip to: 40669 >+/* 40180 */ MCD_OPC_Decode, 171, 3, 195, 2, // Opcode: FCVTMUUXDr >+/* 40185 */ MCD_OPC_FilterValue, 120, 15, 0, // Skip to: 40204 >+/* 40189 */ MCD_OPC_CheckPredicate, 3, 220, 1, // Skip to: 40669 >+/* 40193 */ MCD_OPC_CheckField, 10, 6, 0, 214, 1, // Skip to: 40669 >+/* 40199 */ MCD_OPC_Decode, 229, 3, 195, 2, // Opcode: FCVTZSUXDr >+/* 40204 */ MCD_OPC_FilterValue, 121, 15, 0, // Skip to: 40223 >+/* 40208 */ MCD_OPC_CheckPredicate, 3, 201, 1, // Skip to: 40669 >+/* 40212 */ MCD_OPC_CheckField, 10, 6, 0, 195, 1, // Skip to: 40669 >+/* 40218 */ MCD_OPC_Decode, 130, 4, 195, 2, // Opcode: FCVTZUUXDr >+/* 40223 */ MCD_OPC_FilterValue, 174, 1, 15, 0, // Skip to: 40243 >+/* 40228 */ MCD_OPC_CheckPredicate, 3, 181, 1, // Skip to: 40669 >+/* 40232 */ MCD_OPC_CheckField, 10, 6, 0, 175, 1, // Skip to: 40669 >+/* 40238 */ MCD_OPC_Decode, 220, 4, 197, 2, // Opcode: FMOVDXHighr >+/* 40243 */ MCD_OPC_FilterValue, 175, 1, 165, 1, // Skip to: 40669 >+/* 40248 */ MCD_OPC_CheckPredicate, 3, 161, 1, // Skip to: 40669 >+/* 40252 */ MCD_OPC_CheckField, 10, 6, 0, 155, 1, // Skip to: 40669 >+/* 40258 */ MCD_OPC_Decode, 228, 4, 197, 2, // Opcode: FMOVXDHighr >+/* 40263 */ MCD_OPC_FilterValue, 5, 199, 0, // Skip to: 40466 >+/* 40267 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 40270 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40359 >+/* 40274 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 40277 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40292 >+/* 40281 */ MCD_OPC_CheckField, 21, 1, 0, 126, 1, // Skip to: 40669 >+/* 40287 */ MCD_OPC_Decode, 140, 15, 226, 1, // Opcode: STURSi >+/* 40292 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40307 >+/* 40296 */ MCD_OPC_CheckField, 21, 1, 0, 111, 1, // Skip to: 40669 >+/* 40302 */ MCD_OPC_Decode, 243, 14, 226, 1, // Opcode: STRSpost >+/* 40307 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40344 >+/* 40311 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 40314 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40329 >+/* 40318 */ MCD_OPC_CheckField, 21, 1, 1, 89, 1, // Skip to: 40669 >+/* 40324 */ MCD_OPC_Decode, 245, 14, 198, 2, // Opcode: STRSroW >+/* 40329 */ MCD_OPC_FilterValue, 3, 80, 1, // Skip to: 40669 >+/* 40333 */ MCD_OPC_CheckField, 21, 1, 1, 74, 1, // Skip to: 40669 >+/* 40339 */ MCD_OPC_Decode, 246, 14, 199, 2, // Opcode: STRSroX >+/* 40344 */ MCD_OPC_FilterValue, 3, 65, 1, // Skip to: 40669 >+/* 40348 */ MCD_OPC_CheckField, 21, 1, 0, 59, 1, // Skip to: 40669 >+/* 40354 */ MCD_OPC_Decode, 244, 14, 226, 1, // Opcode: STRSpre >+/* 40359 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40448 >+/* 40363 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 40366 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40381 >+/* 40370 */ MCD_OPC_CheckField, 21, 1, 0, 37, 1, // Skip to: 40669 >+/* 40376 */ MCD_OPC_Decode, 164, 8, 226, 1, // Opcode: LDURSi >+/* 40381 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40396 >+/* 40385 */ MCD_OPC_CheckField, 21, 1, 0, 22, 1, // Skip to: 40669 >+/* 40391 */ MCD_OPC_Decode, 255, 7, 226, 1, // Opcode: LDRSpost >+/* 40396 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40433 >+/* 40400 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 40403 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40418 >+/* 40407 */ MCD_OPC_CheckField, 21, 1, 1, 0, 1, // Skip to: 40669 >+/* 40413 */ MCD_OPC_Decode, 129, 8, 198, 2, // Opcode: LDRSroW >+/* 40418 */ MCD_OPC_FilterValue, 3, 247, 0, // Skip to: 40669 >+/* 40422 */ MCD_OPC_CheckField, 21, 1, 1, 241, 0, // Skip to: 40669 >+/* 40428 */ MCD_OPC_Decode, 130, 8, 199, 2, // Opcode: LDRSroX >+/* 40433 */ MCD_OPC_FilterValue, 3, 232, 0, // Skip to: 40669 >+/* 40437 */ MCD_OPC_CheckField, 21, 1, 0, 226, 0, // Skip to: 40669 >+/* 40443 */ MCD_OPC_Decode, 128, 8, 226, 1, // Opcode: LDRSpre >+/* 40448 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40457 >+/* 40452 */ MCD_OPC_Decode, 247, 14, 231, 1, // Opcode: STRSui >+/* 40457 */ MCD_OPC_FilterValue, 5, 208, 0, // Skip to: 40669 >+/* 40461 */ MCD_OPC_Decode, 131, 8, 231, 1, // Opcode: LDRSui >+/* 40466 */ MCD_OPC_FilterValue, 7, 199, 0, // Skip to: 40669 >+/* 40470 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 40473 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40562 >+/* 40477 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 40480 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40495 >+/* 40484 */ MCD_OPC_CheckField, 21, 1, 0, 179, 0, // Skip to: 40669 >+/* 40490 */ MCD_OPC_Decode, 136, 15, 226, 1, // Opcode: STURDi >+/* 40495 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40510 >+/* 40499 */ MCD_OPC_CheckField, 21, 1, 0, 164, 0, // Skip to: 40669 >+/* 40505 */ MCD_OPC_Decode, 223, 14, 226, 1, // Opcode: STRDpost >+/* 40510 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40547 >+/* 40514 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 40517 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40532 >+/* 40521 */ MCD_OPC_CheckField, 21, 1, 1, 142, 0, // Skip to: 40669 >+/* 40527 */ MCD_OPC_Decode, 225, 14, 200, 2, // Opcode: STRDroW >+/* 40532 */ MCD_OPC_FilterValue, 3, 133, 0, // Skip to: 40669 >+/* 40536 */ MCD_OPC_CheckField, 21, 1, 1, 127, 0, // Skip to: 40669 >+/* 40542 */ MCD_OPC_Decode, 226, 14, 201, 2, // Opcode: STRDroX >+/* 40547 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 40669 >+/* 40551 */ MCD_OPC_CheckField, 21, 1, 0, 112, 0, // Skip to: 40669 >+/* 40557 */ MCD_OPC_Decode, 224, 14, 226, 1, // Opcode: STRDpre >+/* 40562 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40651 >+/* 40566 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 40569 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40584 >+/* 40573 */ MCD_OPC_CheckField, 21, 1, 0, 90, 0, // Skip to: 40669 >+/* 40579 */ MCD_OPC_Decode, 155, 8, 226, 1, // Opcode: LDURDi >+/* 40584 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40599 >+/* 40588 */ MCD_OPC_CheckField, 21, 1, 0, 75, 0, // Skip to: 40669 >+/* 40594 */ MCD_OPC_Decode, 207, 7, 226, 1, // Opcode: LDRDpost >+/* 40599 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40636 >+/* 40603 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... >+/* 40606 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40621 >+/* 40610 */ MCD_OPC_CheckField, 21, 1, 1, 53, 0, // Skip to: 40669 >+/* 40616 */ MCD_OPC_Decode, 209, 7, 200, 2, // Opcode: LDRDroW >+/* 40621 */ MCD_OPC_FilterValue, 3, 44, 0, // Skip to: 40669 >+/* 40625 */ MCD_OPC_CheckField, 21, 1, 1, 38, 0, // Skip to: 40669 >+/* 40631 */ MCD_OPC_Decode, 210, 7, 201, 2, // Opcode: LDRDroX >+/* 40636 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 40669 >+/* 40640 */ MCD_OPC_CheckField, 21, 1, 0, 23, 0, // Skip to: 40669 >+/* 40646 */ MCD_OPC_Decode, 208, 7, 226, 1, // Opcode: LDRDpre >+/* 40651 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40660 >+/* 40655 */ MCD_OPC_Decode, 227, 14, 231, 1, // Opcode: STRDui >+/* 40660 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 40669 >+/* 40664 */ MCD_OPC_Decode, 211, 7, 231, 1, // Opcode: LDRDui >+/* 40669 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static bool getbool(uint64_t b) >+{ >+ return b != 0; >+} >+ >+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) >+{ >+ switch (Idx) { >+ default: // llvm_unreachable("Invalid index!"); >+ case 0: >+ return getbool((Bits & AArch64_FeatureNEON)); >+ case 1: >+ return getbool((Bits & AArch64_FeatureCrypto)); >+ case 2: >+ return getbool((Bits & AArch64_FeatureCRC)); >+ case 3: >+ return getbool((Bits & AArch64_FeatureFPARMv8)); >+ } >+} >+ >+#define DecodeToMCInst(fname,fieldname, InsnType) \ >+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ >+ uint64_t Address, const void *Decoder) \ >+{ \ >+ InsnType tmp; \ >+ switch (Idx) { \ >+ default: \ >+ case 0: \ >+ if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 1: \ >+ if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 2: \ >+ if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 3: \ >+ if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 4: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 5: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 6: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 7: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 8: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 9: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 10: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 11: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 12: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 13: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 14: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 15: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 16: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 17: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 18: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 19: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 20: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 21: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 22: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 23: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 24: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 25: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 26: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 27: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 28: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 29: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 30: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 31: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 32: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 33: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 34: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 35: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 36: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 37: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 38: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 39: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 40: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 41: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 42: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 43: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 44: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 45: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 46: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 47: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 48: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 49: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 50: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 51: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 52: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 53: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 54: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 55: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 56: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 57: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 58: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 59: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 60: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 61: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 62: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 63: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 64: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 65: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 66: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 67: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 68: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 69: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 70: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 71: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 10, 3) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 72: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 73: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 74: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 75: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 2) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 76: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 77: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 78: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 79: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 80: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 81: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 30, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 82: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 83: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 30, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 84: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 85: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 86: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 87: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 88: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 89: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 90: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 91: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 92: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 93: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 94: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 95: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 96: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 97: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 98: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 99: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 100: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 101: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 102: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 103: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 104: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 105: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 106: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 107: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 108: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 109: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 110: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 111: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 112: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 113: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 114: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 115: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 116: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 117: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 118: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 119: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 120: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 121: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 122: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 123: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 124: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 125: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 126: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 127: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 128: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 129: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 130: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 131: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 132: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 133: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 134: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 135: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 136: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 137: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 138: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 139: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 140: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 14, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 141: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 13, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 142: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 143: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 144: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 145: \ >+ if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 146: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 147: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 148: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 149: \ >+ if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 150: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 151: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 152: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 153: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 154: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 155: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 156: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 157: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 158: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 159: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 160: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 161: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 162: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 163: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 164: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 165: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 166: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 167: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 168: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 169: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 170: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 171: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 172: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 173: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 174: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 175: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 176: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 177: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 178: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 179: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 180: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 181: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 182: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 183: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 184: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 185: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 186: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 187: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 188: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 189: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 190: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 191: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 192: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 193: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 194: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 195: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 196: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 197: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 198: \ >+ if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 199: \ >+ if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 200: \ >+ if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 201: \ >+ if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 202: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 10, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 203: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 204: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 10, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 205: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 10, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 206: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 207: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 10, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 208: \ >+ if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 209: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 210: \ >+ if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 211: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 212: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 213: \ >+ tmp = fieldname(insn, 5, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 214: \ >+ tmp = fieldname(insn, 5, 7); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 215: \ >+ tmp = fieldname(insn, 8, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 216: \ >+ if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 217: \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 8, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 218: \ >+ tmp = fieldname(insn, 5, 15); \ >+ if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 219: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 8, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 220: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 15); \ >+ if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 221: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 222: \ >+ return S; \ >+ case 223: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 224: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 225: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 226: \ >+ if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 227: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 228: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 229: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 230: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 231: \ >+ if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 232: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 233: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 234: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 235: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 236: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 237: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 238: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 239: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 240: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 241: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 242: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 243: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 244: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 245: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 246: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 247: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 248: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 249: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 250: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 251: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 252: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 253: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 254: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 255: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 256: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 13, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 257: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 258: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 259: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 260: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 261: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 262: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 263: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 264: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 265: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 13, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 266: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 267: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 268: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 269: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 270: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 271: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 272: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 273: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 274: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 275: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 276: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 277: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 278: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 279: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 280: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 281: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 282: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 283: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 284: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 285: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 286: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 287: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 288: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 289: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 290: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 291: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 292: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 293: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 294: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 295: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 296: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 297: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 298: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 299: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 300: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 301: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 302: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 303: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 304: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 305: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 306: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 307: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 308: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 309: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 310: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 1); \ >+ tmp |= (fieldname(insn, 21, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 311: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 1) << 2); \ >+ tmp |= (fieldname(insn, 20, 2) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 312: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 313: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 314: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 315: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 316: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 19); \ >+ if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 317: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 6); \ >+ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 318: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 6); \ >+ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 319: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 320: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 321: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 6); \ >+ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 322: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 6); \ >+ if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 323: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 324: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 325: \ >+ if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 326: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 327: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 328: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 329: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 1) << 0); \ >+ tmp |= (fieldname(insn, 15, 1) << 1); \ >+ if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ } \ >+} >+ >+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ >+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ >+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ >+{ \ >+ uint64_t Bits = getFeatureBits(feature); \ >+ const uint8_t *Ptr = DecodeTable; \ >+ uint32_t CurFieldValue = 0, ExpectedValue; \ >+ DecodeStatus S = MCDisassembler_Success; \ >+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ >+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ >+ bool Pred, Fail; \ >+ for (;;) { \ >+ switch (*Ptr) { \ >+ default: \ >+ return MCDisassembler_Fail; \ >+ case MCD_OPC_ExtractField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ ++Ptr; \ >+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ >+ break; \ >+ } \ >+ case MCD_OPC_FilterValue: { \ >+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (Val != CurFieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ FieldValue = fieldname(insn, Start, Len); \ >+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (ExpectedValue != FieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckPredicate: { \ >+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ Pred = checkDecoderPredicate(PIdx, Bits); \ >+ if (!Pred) \ >+ Ptr += NumToSkip; \ >+ (void)Pred; \ >+ break; \ >+ } \ >+ case MCD_OPC_Decode: { \ >+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ MCInst_setOpcode(MI, Opc); \ >+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ >+ } \ >+ case MCD_OPC_SoftFail: { \ >+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ >+ if (Fail) \ >+ S = MCDisassembler_SoftFail; \ >+ break; \ >+ } \ >+ case MCD_OPC_Fail: { \ >+ return MCDisassembler_Fail; \ >+ } \ >+ } \ >+ } \ >+} >+ >+FieldFromInstruction(fieldFromInstruction, uint32_t) >+DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) >+DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenInstrInfo.inc b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenInstrInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..bb024a7123813356c6159d24320c3d0c7cc5978a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenInstrInfo.inc >@@ -0,0 +1,2409 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Instruction Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_INSTRINFO_ENUM >+#undef GET_INSTRINFO_ENUM >+ >+enum { >+ AArch64_PHI = 0, >+ AArch64_INLINEASM = 1, >+ AArch64_CFI_INSTRUCTION = 2, >+ AArch64_EH_LABEL = 3, >+ AArch64_GC_LABEL = 4, >+ AArch64_KILL = 5, >+ AArch64_EXTRACT_SUBREG = 6, >+ AArch64_INSERT_SUBREG = 7, >+ AArch64_IMPLICIT_DEF = 8, >+ AArch64_SUBREG_TO_REG = 9, >+ AArch64_COPY_TO_REGCLASS = 10, >+ AArch64_DBG_VALUE = 11, >+ AArch64_REG_SEQUENCE = 12, >+ AArch64_COPY = 13, >+ AArch64_BUNDLE = 14, >+ AArch64_LIFETIME_START = 15, >+ AArch64_LIFETIME_END = 16, >+ AArch64_STACKMAP = 17, >+ AArch64_PATCHPOINT = 18, >+ AArch64_LOAD_STACK_GUARD = 19, >+ AArch64_ABSv16i8 = 20, >+ AArch64_ABSv1i64 = 21, >+ AArch64_ABSv2i32 = 22, >+ AArch64_ABSv2i64 = 23, >+ AArch64_ABSv4i16 = 24, >+ AArch64_ABSv4i32 = 25, >+ AArch64_ABSv8i16 = 26, >+ AArch64_ABSv8i8 = 27, >+ AArch64_ADCSWr = 28, >+ AArch64_ADCSXr = 29, >+ AArch64_ADCWr = 30, >+ AArch64_ADCXr = 31, >+ AArch64_ADDHNv2i64_v2i32 = 32, >+ AArch64_ADDHNv2i64_v4i32 = 33, >+ AArch64_ADDHNv4i32_v4i16 = 34, >+ AArch64_ADDHNv4i32_v8i16 = 35, >+ AArch64_ADDHNv8i16_v16i8 = 36, >+ AArch64_ADDHNv8i16_v8i8 = 37, >+ AArch64_ADDPv16i8 = 38, >+ AArch64_ADDPv2i32 = 39, >+ AArch64_ADDPv2i64 = 40, >+ AArch64_ADDPv2i64p = 41, >+ AArch64_ADDPv4i16 = 42, >+ AArch64_ADDPv4i32 = 43, >+ AArch64_ADDPv8i16 = 44, >+ AArch64_ADDPv8i8 = 45, >+ AArch64_ADDSWri = 46, >+ AArch64_ADDSWrr = 47, >+ AArch64_ADDSWrs = 48, >+ AArch64_ADDSWrx = 49, >+ AArch64_ADDSXri = 50, >+ AArch64_ADDSXrr = 51, >+ AArch64_ADDSXrs = 52, >+ AArch64_ADDSXrx = 53, >+ AArch64_ADDSXrx64 = 54, >+ AArch64_ADDVv16i8v = 55, >+ AArch64_ADDVv4i16v = 56, >+ AArch64_ADDVv4i32v = 57, >+ AArch64_ADDVv8i16v = 58, >+ AArch64_ADDVv8i8v = 59, >+ AArch64_ADDWri = 60, >+ AArch64_ADDWrr = 61, >+ AArch64_ADDWrs = 62, >+ AArch64_ADDWrx = 63, >+ AArch64_ADDXri = 64, >+ AArch64_ADDXrr = 65, >+ AArch64_ADDXrs = 66, >+ AArch64_ADDXrx = 67, >+ AArch64_ADDXrx64 = 68, >+ AArch64_ADDv16i8 = 69, >+ AArch64_ADDv1i64 = 70, >+ AArch64_ADDv2i32 = 71, >+ AArch64_ADDv2i64 = 72, >+ AArch64_ADDv4i16 = 73, >+ AArch64_ADDv4i32 = 74, >+ AArch64_ADDv8i16 = 75, >+ AArch64_ADDv8i8 = 76, >+ AArch64_ADJCALLSTACKDOWN = 77, >+ AArch64_ADJCALLSTACKUP = 78, >+ AArch64_ADR = 79, >+ AArch64_ADRP = 80, >+ AArch64_AESDrr = 81, >+ AArch64_AESErr = 82, >+ AArch64_AESIMCrr = 83, >+ AArch64_AESMCrr = 84, >+ AArch64_ANDSWri = 85, >+ AArch64_ANDSWrr = 86, >+ AArch64_ANDSWrs = 87, >+ AArch64_ANDSXri = 88, >+ AArch64_ANDSXrr = 89, >+ AArch64_ANDSXrs = 90, >+ AArch64_ANDWri = 91, >+ AArch64_ANDWrr = 92, >+ AArch64_ANDWrs = 93, >+ AArch64_ANDXri = 94, >+ AArch64_ANDXrr = 95, >+ AArch64_ANDXrs = 96, >+ AArch64_ANDv16i8 = 97, >+ AArch64_ANDv8i8 = 98, >+ AArch64_ASRVWr = 99, >+ AArch64_ASRVXr = 100, >+ AArch64_B = 101, >+ AArch64_BFMWri = 102, >+ AArch64_BFMXri = 103, >+ AArch64_BICSWrr = 104, >+ AArch64_BICSWrs = 105, >+ AArch64_BICSXrr = 106, >+ AArch64_BICSXrs = 107, >+ AArch64_BICWrr = 108, >+ AArch64_BICWrs = 109, >+ AArch64_BICXrr = 110, >+ AArch64_BICXrs = 111, >+ AArch64_BICv16i8 = 112, >+ AArch64_BICv2i32 = 113, >+ AArch64_BICv4i16 = 114, >+ AArch64_BICv4i32 = 115, >+ AArch64_BICv8i16 = 116, >+ AArch64_BICv8i8 = 117, >+ AArch64_BIFv16i8 = 118, >+ AArch64_BIFv8i8 = 119, >+ AArch64_BITv16i8 = 120, >+ AArch64_BITv8i8 = 121, >+ AArch64_BL = 122, >+ AArch64_BLR = 123, >+ AArch64_BR = 124, >+ AArch64_BRK = 125, >+ AArch64_BSLv16i8 = 126, >+ AArch64_BSLv8i8 = 127, >+ AArch64_Bcc = 128, >+ AArch64_CBNZW = 129, >+ AArch64_CBNZX = 130, >+ AArch64_CBZW = 131, >+ AArch64_CBZX = 132, >+ AArch64_CCMNWi = 133, >+ AArch64_CCMNWr = 134, >+ AArch64_CCMNXi = 135, >+ AArch64_CCMNXr = 136, >+ AArch64_CCMPWi = 137, >+ AArch64_CCMPWr = 138, >+ AArch64_CCMPXi = 139, >+ AArch64_CCMPXr = 140, >+ AArch64_CLREX = 141, >+ AArch64_CLSWr = 142, >+ AArch64_CLSXr = 143, >+ AArch64_CLSv16i8 = 144, >+ AArch64_CLSv2i32 = 145, >+ AArch64_CLSv4i16 = 146, >+ AArch64_CLSv4i32 = 147, >+ AArch64_CLSv8i16 = 148, >+ AArch64_CLSv8i8 = 149, >+ AArch64_CLZWr = 150, >+ AArch64_CLZXr = 151, >+ AArch64_CLZv16i8 = 152, >+ AArch64_CLZv2i32 = 153, >+ AArch64_CLZv4i16 = 154, >+ AArch64_CLZv4i32 = 155, >+ AArch64_CLZv8i16 = 156, >+ AArch64_CLZv8i8 = 157, >+ AArch64_CMEQv16i8 = 158, >+ AArch64_CMEQv16i8rz = 159, >+ AArch64_CMEQv1i64 = 160, >+ AArch64_CMEQv1i64rz = 161, >+ AArch64_CMEQv2i32 = 162, >+ AArch64_CMEQv2i32rz = 163, >+ AArch64_CMEQv2i64 = 164, >+ AArch64_CMEQv2i64rz = 165, >+ AArch64_CMEQv4i16 = 166, >+ AArch64_CMEQv4i16rz = 167, >+ AArch64_CMEQv4i32 = 168, >+ AArch64_CMEQv4i32rz = 169, >+ AArch64_CMEQv8i16 = 170, >+ AArch64_CMEQv8i16rz = 171, >+ AArch64_CMEQv8i8 = 172, >+ AArch64_CMEQv8i8rz = 173, >+ AArch64_CMGEv16i8 = 174, >+ AArch64_CMGEv16i8rz = 175, >+ AArch64_CMGEv1i64 = 176, >+ AArch64_CMGEv1i64rz = 177, >+ AArch64_CMGEv2i32 = 178, >+ AArch64_CMGEv2i32rz = 179, >+ AArch64_CMGEv2i64 = 180, >+ AArch64_CMGEv2i64rz = 181, >+ AArch64_CMGEv4i16 = 182, >+ AArch64_CMGEv4i16rz = 183, >+ AArch64_CMGEv4i32 = 184, >+ AArch64_CMGEv4i32rz = 185, >+ AArch64_CMGEv8i16 = 186, >+ AArch64_CMGEv8i16rz = 187, >+ AArch64_CMGEv8i8 = 188, >+ AArch64_CMGEv8i8rz = 189, >+ AArch64_CMGTv16i8 = 190, >+ AArch64_CMGTv16i8rz = 191, >+ AArch64_CMGTv1i64 = 192, >+ AArch64_CMGTv1i64rz = 193, >+ AArch64_CMGTv2i32 = 194, >+ AArch64_CMGTv2i32rz = 195, >+ AArch64_CMGTv2i64 = 196, >+ AArch64_CMGTv2i64rz = 197, >+ AArch64_CMGTv4i16 = 198, >+ AArch64_CMGTv4i16rz = 199, >+ AArch64_CMGTv4i32 = 200, >+ AArch64_CMGTv4i32rz = 201, >+ AArch64_CMGTv8i16 = 202, >+ AArch64_CMGTv8i16rz = 203, >+ AArch64_CMGTv8i8 = 204, >+ AArch64_CMGTv8i8rz = 205, >+ AArch64_CMHIv16i8 = 206, >+ AArch64_CMHIv1i64 = 207, >+ AArch64_CMHIv2i32 = 208, >+ AArch64_CMHIv2i64 = 209, >+ AArch64_CMHIv4i16 = 210, >+ AArch64_CMHIv4i32 = 211, >+ AArch64_CMHIv8i16 = 212, >+ AArch64_CMHIv8i8 = 213, >+ AArch64_CMHSv16i8 = 214, >+ AArch64_CMHSv1i64 = 215, >+ AArch64_CMHSv2i32 = 216, >+ AArch64_CMHSv2i64 = 217, >+ AArch64_CMHSv4i16 = 218, >+ AArch64_CMHSv4i32 = 219, >+ AArch64_CMHSv8i16 = 220, >+ AArch64_CMHSv8i8 = 221, >+ AArch64_CMLEv16i8rz = 222, >+ AArch64_CMLEv1i64rz = 223, >+ AArch64_CMLEv2i32rz = 224, >+ AArch64_CMLEv2i64rz = 225, >+ AArch64_CMLEv4i16rz = 226, >+ AArch64_CMLEv4i32rz = 227, >+ AArch64_CMLEv8i16rz = 228, >+ AArch64_CMLEv8i8rz = 229, >+ AArch64_CMLTv16i8rz = 230, >+ AArch64_CMLTv1i64rz = 231, >+ AArch64_CMLTv2i32rz = 232, >+ AArch64_CMLTv2i64rz = 233, >+ AArch64_CMLTv4i16rz = 234, >+ AArch64_CMLTv4i32rz = 235, >+ AArch64_CMLTv8i16rz = 236, >+ AArch64_CMLTv8i8rz = 237, >+ AArch64_CMTSTv16i8 = 238, >+ AArch64_CMTSTv1i64 = 239, >+ AArch64_CMTSTv2i32 = 240, >+ AArch64_CMTSTv2i64 = 241, >+ AArch64_CMTSTv4i16 = 242, >+ AArch64_CMTSTv4i32 = 243, >+ AArch64_CMTSTv8i16 = 244, >+ AArch64_CMTSTv8i8 = 245, >+ AArch64_CNTv16i8 = 246, >+ AArch64_CNTv8i8 = 247, >+ AArch64_CPYi16 = 248, >+ AArch64_CPYi32 = 249, >+ AArch64_CPYi64 = 250, >+ AArch64_CPYi8 = 251, >+ AArch64_CRC32Brr = 252, >+ AArch64_CRC32CBrr = 253, >+ AArch64_CRC32CHrr = 254, >+ AArch64_CRC32CWrr = 255, >+ AArch64_CRC32CXrr = 256, >+ AArch64_CRC32Hrr = 257, >+ AArch64_CRC32Wrr = 258, >+ AArch64_CRC32Xrr = 259, >+ AArch64_CSELWr = 260, >+ AArch64_CSELXr = 261, >+ AArch64_CSINCWr = 262, >+ AArch64_CSINCXr = 263, >+ AArch64_CSINVWr = 264, >+ AArch64_CSINVXr = 265, >+ AArch64_CSNEGWr = 266, >+ AArch64_CSNEGXr = 267, >+ AArch64_DCPS1 = 268, >+ AArch64_DCPS2 = 269, >+ AArch64_DCPS3 = 270, >+ AArch64_DMB = 271, >+ AArch64_DRPS = 272, >+ AArch64_DSB = 273, >+ AArch64_DUPv16i8gpr = 274, >+ AArch64_DUPv16i8lane = 275, >+ AArch64_DUPv2i32gpr = 276, >+ AArch64_DUPv2i32lane = 277, >+ AArch64_DUPv2i64gpr = 278, >+ AArch64_DUPv2i64lane = 279, >+ AArch64_DUPv4i16gpr = 280, >+ AArch64_DUPv4i16lane = 281, >+ AArch64_DUPv4i32gpr = 282, >+ AArch64_DUPv4i32lane = 283, >+ AArch64_DUPv8i16gpr = 284, >+ AArch64_DUPv8i16lane = 285, >+ AArch64_DUPv8i8gpr = 286, >+ AArch64_DUPv8i8lane = 287, >+ AArch64_EONWrr = 288, >+ AArch64_EONWrs = 289, >+ AArch64_EONXrr = 290, >+ AArch64_EONXrs = 291, >+ AArch64_EORWri = 292, >+ AArch64_EORWrr = 293, >+ AArch64_EORWrs = 294, >+ AArch64_EORXri = 295, >+ AArch64_EORXrr = 296, >+ AArch64_EORXrs = 297, >+ AArch64_EORv16i8 = 298, >+ AArch64_EORv8i8 = 299, >+ AArch64_ERET = 300, >+ AArch64_EXTRWrri = 301, >+ AArch64_EXTRXrri = 302, >+ AArch64_EXTv16i8 = 303, >+ AArch64_EXTv8i8 = 304, >+ AArch64_F128CSEL = 305, >+ AArch64_FABD32 = 306, >+ AArch64_FABD64 = 307, >+ AArch64_FABDv2f32 = 308, >+ AArch64_FABDv2f64 = 309, >+ AArch64_FABDv4f32 = 310, >+ AArch64_FABSDr = 311, >+ AArch64_FABSSr = 312, >+ AArch64_FABSv2f32 = 313, >+ AArch64_FABSv2f64 = 314, >+ AArch64_FABSv4f32 = 315, >+ AArch64_FACGE32 = 316, >+ AArch64_FACGE64 = 317, >+ AArch64_FACGEv2f32 = 318, >+ AArch64_FACGEv2f64 = 319, >+ AArch64_FACGEv4f32 = 320, >+ AArch64_FACGT32 = 321, >+ AArch64_FACGT64 = 322, >+ AArch64_FACGTv2f32 = 323, >+ AArch64_FACGTv2f64 = 324, >+ AArch64_FACGTv4f32 = 325, >+ AArch64_FADDDrr = 326, >+ AArch64_FADDPv2f32 = 327, >+ AArch64_FADDPv2f64 = 328, >+ AArch64_FADDPv2i32p = 329, >+ AArch64_FADDPv2i64p = 330, >+ AArch64_FADDPv4f32 = 331, >+ AArch64_FADDSrr = 332, >+ AArch64_FADDv2f32 = 333, >+ AArch64_FADDv2f64 = 334, >+ AArch64_FADDv4f32 = 335, >+ AArch64_FCCMPDrr = 336, >+ AArch64_FCCMPEDrr = 337, >+ AArch64_FCCMPESrr = 338, >+ AArch64_FCCMPSrr = 339, >+ AArch64_FCMEQ32 = 340, >+ AArch64_FCMEQ64 = 341, >+ AArch64_FCMEQv1i32rz = 342, >+ AArch64_FCMEQv1i64rz = 343, >+ AArch64_FCMEQv2f32 = 344, >+ AArch64_FCMEQv2f64 = 345, >+ AArch64_FCMEQv2i32rz = 346, >+ AArch64_FCMEQv2i64rz = 347, >+ AArch64_FCMEQv4f32 = 348, >+ AArch64_FCMEQv4i32rz = 349, >+ AArch64_FCMGE32 = 350, >+ AArch64_FCMGE64 = 351, >+ AArch64_FCMGEv1i32rz = 352, >+ AArch64_FCMGEv1i64rz = 353, >+ AArch64_FCMGEv2f32 = 354, >+ AArch64_FCMGEv2f64 = 355, >+ AArch64_FCMGEv2i32rz = 356, >+ AArch64_FCMGEv2i64rz = 357, >+ AArch64_FCMGEv4f32 = 358, >+ AArch64_FCMGEv4i32rz = 359, >+ AArch64_FCMGT32 = 360, >+ AArch64_FCMGT64 = 361, >+ AArch64_FCMGTv1i32rz = 362, >+ AArch64_FCMGTv1i64rz = 363, >+ AArch64_FCMGTv2f32 = 364, >+ AArch64_FCMGTv2f64 = 365, >+ AArch64_FCMGTv2i32rz = 366, >+ AArch64_FCMGTv2i64rz = 367, >+ AArch64_FCMGTv4f32 = 368, >+ AArch64_FCMGTv4i32rz = 369, >+ AArch64_FCMLEv1i32rz = 370, >+ AArch64_FCMLEv1i64rz = 371, >+ AArch64_FCMLEv2i32rz = 372, >+ AArch64_FCMLEv2i64rz = 373, >+ AArch64_FCMLEv4i32rz = 374, >+ AArch64_FCMLTv1i32rz = 375, >+ AArch64_FCMLTv1i64rz = 376, >+ AArch64_FCMLTv2i32rz = 377, >+ AArch64_FCMLTv2i64rz = 378, >+ AArch64_FCMLTv4i32rz = 379, >+ AArch64_FCMPDri = 380, >+ AArch64_FCMPDrr = 381, >+ AArch64_FCMPEDri = 382, >+ AArch64_FCMPEDrr = 383, >+ AArch64_FCMPESri = 384, >+ AArch64_FCMPESrr = 385, >+ AArch64_FCMPSri = 386, >+ AArch64_FCMPSrr = 387, >+ AArch64_FCSELDrrr = 388, >+ AArch64_FCSELSrrr = 389, >+ AArch64_FCVTASUWDr = 390, >+ AArch64_FCVTASUWSr = 391, >+ AArch64_FCVTASUXDr = 392, >+ AArch64_FCVTASUXSr = 393, >+ AArch64_FCVTASv1i32 = 394, >+ AArch64_FCVTASv1i64 = 395, >+ AArch64_FCVTASv2f32 = 396, >+ AArch64_FCVTASv2f64 = 397, >+ AArch64_FCVTASv4f32 = 398, >+ AArch64_FCVTAUUWDr = 399, >+ AArch64_FCVTAUUWSr = 400, >+ AArch64_FCVTAUUXDr = 401, >+ AArch64_FCVTAUUXSr = 402, >+ AArch64_FCVTAUv1i32 = 403, >+ AArch64_FCVTAUv1i64 = 404, >+ AArch64_FCVTAUv2f32 = 405, >+ AArch64_FCVTAUv2f64 = 406, >+ AArch64_FCVTAUv4f32 = 407, >+ AArch64_FCVTDHr = 408, >+ AArch64_FCVTDSr = 409, >+ AArch64_FCVTHDr = 410, >+ AArch64_FCVTHSr = 411, >+ AArch64_FCVTLv2i32 = 412, >+ AArch64_FCVTLv4i16 = 413, >+ AArch64_FCVTLv4i32 = 414, >+ AArch64_FCVTLv8i16 = 415, >+ AArch64_FCVTMSUWDr = 416, >+ AArch64_FCVTMSUWSr = 417, >+ AArch64_FCVTMSUXDr = 418, >+ AArch64_FCVTMSUXSr = 419, >+ AArch64_FCVTMSv1i32 = 420, >+ AArch64_FCVTMSv1i64 = 421, >+ AArch64_FCVTMSv2f32 = 422, >+ AArch64_FCVTMSv2f64 = 423, >+ AArch64_FCVTMSv4f32 = 424, >+ AArch64_FCVTMUUWDr = 425, >+ AArch64_FCVTMUUWSr = 426, >+ AArch64_FCVTMUUXDr = 427, >+ AArch64_FCVTMUUXSr = 428, >+ AArch64_FCVTMUv1i32 = 429, >+ AArch64_FCVTMUv1i64 = 430, >+ AArch64_FCVTMUv2f32 = 431, >+ AArch64_FCVTMUv2f64 = 432, >+ AArch64_FCVTMUv4f32 = 433, >+ AArch64_FCVTNSUWDr = 434, >+ AArch64_FCVTNSUWSr = 435, >+ AArch64_FCVTNSUXDr = 436, >+ AArch64_FCVTNSUXSr = 437, >+ AArch64_FCVTNSv1i32 = 438, >+ AArch64_FCVTNSv1i64 = 439, >+ AArch64_FCVTNSv2f32 = 440, >+ AArch64_FCVTNSv2f64 = 441, >+ AArch64_FCVTNSv4f32 = 442, >+ AArch64_FCVTNUUWDr = 443, >+ AArch64_FCVTNUUWSr = 444, >+ AArch64_FCVTNUUXDr = 445, >+ AArch64_FCVTNUUXSr = 446, >+ AArch64_FCVTNUv1i32 = 447, >+ AArch64_FCVTNUv1i64 = 448, >+ AArch64_FCVTNUv2f32 = 449, >+ AArch64_FCVTNUv2f64 = 450, >+ AArch64_FCVTNUv4f32 = 451, >+ AArch64_FCVTNv2i32 = 452, >+ AArch64_FCVTNv4i16 = 453, >+ AArch64_FCVTNv4i32 = 454, >+ AArch64_FCVTNv8i16 = 455, >+ AArch64_FCVTPSUWDr = 456, >+ AArch64_FCVTPSUWSr = 457, >+ AArch64_FCVTPSUXDr = 458, >+ AArch64_FCVTPSUXSr = 459, >+ AArch64_FCVTPSv1i32 = 460, >+ AArch64_FCVTPSv1i64 = 461, >+ AArch64_FCVTPSv2f32 = 462, >+ AArch64_FCVTPSv2f64 = 463, >+ AArch64_FCVTPSv4f32 = 464, >+ AArch64_FCVTPUUWDr = 465, >+ AArch64_FCVTPUUWSr = 466, >+ AArch64_FCVTPUUXDr = 467, >+ AArch64_FCVTPUUXSr = 468, >+ AArch64_FCVTPUv1i32 = 469, >+ AArch64_FCVTPUv1i64 = 470, >+ AArch64_FCVTPUv2f32 = 471, >+ AArch64_FCVTPUv2f64 = 472, >+ AArch64_FCVTPUv4f32 = 473, >+ AArch64_FCVTSDr = 474, >+ AArch64_FCVTSHr = 475, >+ AArch64_FCVTXNv1i64 = 476, >+ AArch64_FCVTXNv2f32 = 477, >+ AArch64_FCVTXNv4f32 = 478, >+ AArch64_FCVTZSSWDri = 479, >+ AArch64_FCVTZSSWSri = 480, >+ AArch64_FCVTZSSXDri = 481, >+ AArch64_FCVTZSSXSri = 482, >+ AArch64_FCVTZSUWDr = 483, >+ AArch64_FCVTZSUWSr = 484, >+ AArch64_FCVTZSUXDr = 485, >+ AArch64_FCVTZSUXSr = 486, >+ AArch64_FCVTZS_IntSWDri = 487, >+ AArch64_FCVTZS_IntSWSri = 488, >+ AArch64_FCVTZS_IntSXDri = 489, >+ AArch64_FCVTZS_IntSXSri = 490, >+ AArch64_FCVTZS_IntUWDr = 491, >+ AArch64_FCVTZS_IntUWSr = 492, >+ AArch64_FCVTZS_IntUXDr = 493, >+ AArch64_FCVTZS_IntUXSr = 494, >+ AArch64_FCVTZS_Intv2f32 = 495, >+ AArch64_FCVTZS_Intv2f64 = 496, >+ AArch64_FCVTZS_Intv4f32 = 497, >+ AArch64_FCVTZSd = 498, >+ AArch64_FCVTZSs = 499, >+ AArch64_FCVTZSv1i32 = 500, >+ AArch64_FCVTZSv1i64 = 501, >+ AArch64_FCVTZSv2f32 = 502, >+ AArch64_FCVTZSv2f64 = 503, >+ AArch64_FCVTZSv2i32_shift = 504, >+ AArch64_FCVTZSv2i64_shift = 505, >+ AArch64_FCVTZSv4f32 = 506, >+ AArch64_FCVTZSv4i32_shift = 507, >+ AArch64_FCVTZUSWDri = 508, >+ AArch64_FCVTZUSWSri = 509, >+ AArch64_FCVTZUSXDri = 510, >+ AArch64_FCVTZUSXSri = 511, >+ AArch64_FCVTZUUWDr = 512, >+ AArch64_FCVTZUUWSr = 513, >+ AArch64_FCVTZUUXDr = 514, >+ AArch64_FCVTZUUXSr = 515, >+ AArch64_FCVTZU_IntSWDri = 516, >+ AArch64_FCVTZU_IntSWSri = 517, >+ AArch64_FCVTZU_IntSXDri = 518, >+ AArch64_FCVTZU_IntSXSri = 519, >+ AArch64_FCVTZU_IntUWDr = 520, >+ AArch64_FCVTZU_IntUWSr = 521, >+ AArch64_FCVTZU_IntUXDr = 522, >+ AArch64_FCVTZU_IntUXSr = 523, >+ AArch64_FCVTZU_Intv2f32 = 524, >+ AArch64_FCVTZU_Intv2f64 = 525, >+ AArch64_FCVTZU_Intv4f32 = 526, >+ AArch64_FCVTZUd = 527, >+ AArch64_FCVTZUs = 528, >+ AArch64_FCVTZUv1i32 = 529, >+ AArch64_FCVTZUv1i64 = 530, >+ AArch64_FCVTZUv2f32 = 531, >+ AArch64_FCVTZUv2f64 = 532, >+ AArch64_FCVTZUv2i32_shift = 533, >+ AArch64_FCVTZUv2i64_shift = 534, >+ AArch64_FCVTZUv4f32 = 535, >+ AArch64_FCVTZUv4i32_shift = 536, >+ AArch64_FDIVDrr = 537, >+ AArch64_FDIVSrr = 538, >+ AArch64_FDIVv2f32 = 539, >+ AArch64_FDIVv2f64 = 540, >+ AArch64_FDIVv4f32 = 541, >+ AArch64_FMADDDrrr = 542, >+ AArch64_FMADDSrrr = 543, >+ AArch64_FMAXDrr = 544, >+ AArch64_FMAXNMDrr = 545, >+ AArch64_FMAXNMPv2f32 = 546, >+ AArch64_FMAXNMPv2f64 = 547, >+ AArch64_FMAXNMPv2i32p = 548, >+ AArch64_FMAXNMPv2i64p = 549, >+ AArch64_FMAXNMPv4f32 = 550, >+ AArch64_FMAXNMSrr = 551, >+ AArch64_FMAXNMVv4i32v = 552, >+ AArch64_FMAXNMv2f32 = 553, >+ AArch64_FMAXNMv2f64 = 554, >+ AArch64_FMAXNMv4f32 = 555, >+ AArch64_FMAXPv2f32 = 556, >+ AArch64_FMAXPv2f64 = 557, >+ AArch64_FMAXPv2i32p = 558, >+ AArch64_FMAXPv2i64p = 559, >+ AArch64_FMAXPv4f32 = 560, >+ AArch64_FMAXSrr = 561, >+ AArch64_FMAXVv4i32v = 562, >+ AArch64_FMAXv2f32 = 563, >+ AArch64_FMAXv2f64 = 564, >+ AArch64_FMAXv4f32 = 565, >+ AArch64_FMINDrr = 566, >+ AArch64_FMINNMDrr = 567, >+ AArch64_FMINNMPv2f32 = 568, >+ AArch64_FMINNMPv2f64 = 569, >+ AArch64_FMINNMPv2i32p = 570, >+ AArch64_FMINNMPv2i64p = 571, >+ AArch64_FMINNMPv4f32 = 572, >+ AArch64_FMINNMSrr = 573, >+ AArch64_FMINNMVv4i32v = 574, >+ AArch64_FMINNMv2f32 = 575, >+ AArch64_FMINNMv2f64 = 576, >+ AArch64_FMINNMv4f32 = 577, >+ AArch64_FMINPv2f32 = 578, >+ AArch64_FMINPv2f64 = 579, >+ AArch64_FMINPv2i32p = 580, >+ AArch64_FMINPv2i64p = 581, >+ AArch64_FMINPv4f32 = 582, >+ AArch64_FMINSrr = 583, >+ AArch64_FMINVv4i32v = 584, >+ AArch64_FMINv2f32 = 585, >+ AArch64_FMINv2f64 = 586, >+ AArch64_FMINv4f32 = 587, >+ AArch64_FMLAv1i32_indexed = 588, >+ AArch64_FMLAv1i64_indexed = 589, >+ AArch64_FMLAv2f32 = 590, >+ AArch64_FMLAv2f64 = 591, >+ AArch64_FMLAv2i32_indexed = 592, >+ AArch64_FMLAv2i64_indexed = 593, >+ AArch64_FMLAv4f32 = 594, >+ AArch64_FMLAv4i32_indexed = 595, >+ AArch64_FMLSv1i32_indexed = 596, >+ AArch64_FMLSv1i64_indexed = 597, >+ AArch64_FMLSv2f32 = 598, >+ AArch64_FMLSv2f64 = 599, >+ AArch64_FMLSv2i32_indexed = 600, >+ AArch64_FMLSv2i64_indexed = 601, >+ AArch64_FMLSv4f32 = 602, >+ AArch64_FMLSv4i32_indexed = 603, >+ AArch64_FMOVDXHighr = 604, >+ AArch64_FMOVDXr = 605, >+ AArch64_FMOVDi = 606, >+ AArch64_FMOVDr = 607, >+ AArch64_FMOVSWr = 608, >+ AArch64_FMOVSi = 609, >+ AArch64_FMOVSr = 610, >+ AArch64_FMOVWSr = 611, >+ AArch64_FMOVXDHighr = 612, >+ AArch64_FMOVXDr = 613, >+ AArch64_FMOVv2f32_ns = 614, >+ AArch64_FMOVv2f64_ns = 615, >+ AArch64_FMOVv4f32_ns = 616, >+ AArch64_FMSUBDrrr = 617, >+ AArch64_FMSUBSrrr = 618, >+ AArch64_FMULDrr = 619, >+ AArch64_FMULSrr = 620, >+ AArch64_FMULX32 = 621, >+ AArch64_FMULX64 = 622, >+ AArch64_FMULXv1i32_indexed = 623, >+ AArch64_FMULXv1i64_indexed = 624, >+ AArch64_FMULXv2f32 = 625, >+ AArch64_FMULXv2f64 = 626, >+ AArch64_FMULXv2i32_indexed = 627, >+ AArch64_FMULXv2i64_indexed = 628, >+ AArch64_FMULXv4f32 = 629, >+ AArch64_FMULXv4i32_indexed = 630, >+ AArch64_FMULv1i32_indexed = 631, >+ AArch64_FMULv1i64_indexed = 632, >+ AArch64_FMULv2f32 = 633, >+ AArch64_FMULv2f64 = 634, >+ AArch64_FMULv2i32_indexed = 635, >+ AArch64_FMULv2i64_indexed = 636, >+ AArch64_FMULv4f32 = 637, >+ AArch64_FMULv4i32_indexed = 638, >+ AArch64_FNEGDr = 639, >+ AArch64_FNEGSr = 640, >+ AArch64_FNEGv2f32 = 641, >+ AArch64_FNEGv2f64 = 642, >+ AArch64_FNEGv4f32 = 643, >+ AArch64_FNMADDDrrr = 644, >+ AArch64_FNMADDSrrr = 645, >+ AArch64_FNMSUBDrrr = 646, >+ AArch64_FNMSUBSrrr = 647, >+ AArch64_FNMULDrr = 648, >+ AArch64_FNMULSrr = 649, >+ AArch64_FRECPEv1i32 = 650, >+ AArch64_FRECPEv1i64 = 651, >+ AArch64_FRECPEv2f32 = 652, >+ AArch64_FRECPEv2f64 = 653, >+ AArch64_FRECPEv4f32 = 654, >+ AArch64_FRECPS32 = 655, >+ AArch64_FRECPS64 = 656, >+ AArch64_FRECPSv2f32 = 657, >+ AArch64_FRECPSv2f64 = 658, >+ AArch64_FRECPSv4f32 = 659, >+ AArch64_FRECPXv1i32 = 660, >+ AArch64_FRECPXv1i64 = 661, >+ AArch64_FRINTADr = 662, >+ AArch64_FRINTASr = 663, >+ AArch64_FRINTAv2f32 = 664, >+ AArch64_FRINTAv2f64 = 665, >+ AArch64_FRINTAv4f32 = 666, >+ AArch64_FRINTIDr = 667, >+ AArch64_FRINTISr = 668, >+ AArch64_FRINTIv2f32 = 669, >+ AArch64_FRINTIv2f64 = 670, >+ AArch64_FRINTIv4f32 = 671, >+ AArch64_FRINTMDr = 672, >+ AArch64_FRINTMSr = 673, >+ AArch64_FRINTMv2f32 = 674, >+ AArch64_FRINTMv2f64 = 675, >+ AArch64_FRINTMv4f32 = 676, >+ AArch64_FRINTNDr = 677, >+ AArch64_FRINTNSr = 678, >+ AArch64_FRINTNv2f32 = 679, >+ AArch64_FRINTNv2f64 = 680, >+ AArch64_FRINTNv4f32 = 681, >+ AArch64_FRINTPDr = 682, >+ AArch64_FRINTPSr = 683, >+ AArch64_FRINTPv2f32 = 684, >+ AArch64_FRINTPv2f64 = 685, >+ AArch64_FRINTPv4f32 = 686, >+ AArch64_FRINTXDr = 687, >+ AArch64_FRINTXSr = 688, >+ AArch64_FRINTXv2f32 = 689, >+ AArch64_FRINTXv2f64 = 690, >+ AArch64_FRINTXv4f32 = 691, >+ AArch64_FRINTZDr = 692, >+ AArch64_FRINTZSr = 693, >+ AArch64_FRINTZv2f32 = 694, >+ AArch64_FRINTZv2f64 = 695, >+ AArch64_FRINTZv4f32 = 696, >+ AArch64_FRSQRTEv1i32 = 697, >+ AArch64_FRSQRTEv1i64 = 698, >+ AArch64_FRSQRTEv2f32 = 699, >+ AArch64_FRSQRTEv2f64 = 700, >+ AArch64_FRSQRTEv4f32 = 701, >+ AArch64_FRSQRTS32 = 702, >+ AArch64_FRSQRTS64 = 703, >+ AArch64_FRSQRTSv2f32 = 704, >+ AArch64_FRSQRTSv2f64 = 705, >+ AArch64_FRSQRTSv4f32 = 706, >+ AArch64_FSQRTDr = 707, >+ AArch64_FSQRTSr = 708, >+ AArch64_FSQRTv2f32 = 709, >+ AArch64_FSQRTv2f64 = 710, >+ AArch64_FSQRTv4f32 = 711, >+ AArch64_FSUBDrr = 712, >+ AArch64_FSUBSrr = 713, >+ AArch64_FSUBv2f32 = 714, >+ AArch64_FSUBv2f64 = 715, >+ AArch64_FSUBv4f32 = 716, >+ AArch64_HINT = 717, >+ AArch64_HLT = 718, >+ AArch64_HVC = 719, >+ AArch64_INSvi16gpr = 720, >+ AArch64_INSvi16lane = 721, >+ AArch64_INSvi32gpr = 722, >+ AArch64_INSvi32lane = 723, >+ AArch64_INSvi64gpr = 724, >+ AArch64_INSvi64lane = 725, >+ AArch64_INSvi8gpr = 726, >+ AArch64_INSvi8lane = 727, >+ AArch64_ISB = 728, >+ AArch64_LD1Fourv16b = 729, >+ AArch64_LD1Fourv16b_POST = 730, >+ AArch64_LD1Fourv1d = 731, >+ AArch64_LD1Fourv1d_POST = 732, >+ AArch64_LD1Fourv2d = 733, >+ AArch64_LD1Fourv2d_POST = 734, >+ AArch64_LD1Fourv2s = 735, >+ AArch64_LD1Fourv2s_POST = 736, >+ AArch64_LD1Fourv4h = 737, >+ AArch64_LD1Fourv4h_POST = 738, >+ AArch64_LD1Fourv4s = 739, >+ AArch64_LD1Fourv4s_POST = 740, >+ AArch64_LD1Fourv8b = 741, >+ AArch64_LD1Fourv8b_POST = 742, >+ AArch64_LD1Fourv8h = 743, >+ AArch64_LD1Fourv8h_POST = 744, >+ AArch64_LD1Onev16b = 745, >+ AArch64_LD1Onev16b_POST = 746, >+ AArch64_LD1Onev1d = 747, >+ AArch64_LD1Onev1d_POST = 748, >+ AArch64_LD1Onev2d = 749, >+ AArch64_LD1Onev2d_POST = 750, >+ AArch64_LD1Onev2s = 751, >+ AArch64_LD1Onev2s_POST = 752, >+ AArch64_LD1Onev4h = 753, >+ AArch64_LD1Onev4h_POST = 754, >+ AArch64_LD1Onev4s = 755, >+ AArch64_LD1Onev4s_POST = 756, >+ AArch64_LD1Onev8b = 757, >+ AArch64_LD1Onev8b_POST = 758, >+ AArch64_LD1Onev8h = 759, >+ AArch64_LD1Onev8h_POST = 760, >+ AArch64_LD1Rv16b = 761, >+ AArch64_LD1Rv16b_POST = 762, >+ AArch64_LD1Rv1d = 763, >+ AArch64_LD1Rv1d_POST = 764, >+ AArch64_LD1Rv2d = 765, >+ AArch64_LD1Rv2d_POST = 766, >+ AArch64_LD1Rv2s = 767, >+ AArch64_LD1Rv2s_POST = 768, >+ AArch64_LD1Rv4h = 769, >+ AArch64_LD1Rv4h_POST = 770, >+ AArch64_LD1Rv4s = 771, >+ AArch64_LD1Rv4s_POST = 772, >+ AArch64_LD1Rv8b = 773, >+ AArch64_LD1Rv8b_POST = 774, >+ AArch64_LD1Rv8h = 775, >+ AArch64_LD1Rv8h_POST = 776, >+ AArch64_LD1Threev16b = 777, >+ AArch64_LD1Threev16b_POST = 778, >+ AArch64_LD1Threev1d = 779, >+ AArch64_LD1Threev1d_POST = 780, >+ AArch64_LD1Threev2d = 781, >+ AArch64_LD1Threev2d_POST = 782, >+ AArch64_LD1Threev2s = 783, >+ AArch64_LD1Threev2s_POST = 784, >+ AArch64_LD1Threev4h = 785, >+ AArch64_LD1Threev4h_POST = 786, >+ AArch64_LD1Threev4s = 787, >+ AArch64_LD1Threev4s_POST = 788, >+ AArch64_LD1Threev8b = 789, >+ AArch64_LD1Threev8b_POST = 790, >+ AArch64_LD1Threev8h = 791, >+ AArch64_LD1Threev8h_POST = 792, >+ AArch64_LD1Twov16b = 793, >+ AArch64_LD1Twov16b_POST = 794, >+ AArch64_LD1Twov1d = 795, >+ AArch64_LD1Twov1d_POST = 796, >+ AArch64_LD1Twov2d = 797, >+ AArch64_LD1Twov2d_POST = 798, >+ AArch64_LD1Twov2s = 799, >+ AArch64_LD1Twov2s_POST = 800, >+ AArch64_LD1Twov4h = 801, >+ AArch64_LD1Twov4h_POST = 802, >+ AArch64_LD1Twov4s = 803, >+ AArch64_LD1Twov4s_POST = 804, >+ AArch64_LD1Twov8b = 805, >+ AArch64_LD1Twov8b_POST = 806, >+ AArch64_LD1Twov8h = 807, >+ AArch64_LD1Twov8h_POST = 808, >+ AArch64_LD1i16 = 809, >+ AArch64_LD1i16_POST = 810, >+ AArch64_LD1i32 = 811, >+ AArch64_LD1i32_POST = 812, >+ AArch64_LD1i64 = 813, >+ AArch64_LD1i64_POST = 814, >+ AArch64_LD1i8 = 815, >+ AArch64_LD1i8_POST = 816, >+ AArch64_LD2Rv16b = 817, >+ AArch64_LD2Rv16b_POST = 818, >+ AArch64_LD2Rv1d = 819, >+ AArch64_LD2Rv1d_POST = 820, >+ AArch64_LD2Rv2d = 821, >+ AArch64_LD2Rv2d_POST = 822, >+ AArch64_LD2Rv2s = 823, >+ AArch64_LD2Rv2s_POST = 824, >+ AArch64_LD2Rv4h = 825, >+ AArch64_LD2Rv4h_POST = 826, >+ AArch64_LD2Rv4s = 827, >+ AArch64_LD2Rv4s_POST = 828, >+ AArch64_LD2Rv8b = 829, >+ AArch64_LD2Rv8b_POST = 830, >+ AArch64_LD2Rv8h = 831, >+ AArch64_LD2Rv8h_POST = 832, >+ AArch64_LD2Twov16b = 833, >+ AArch64_LD2Twov16b_POST = 834, >+ AArch64_LD2Twov2d = 835, >+ AArch64_LD2Twov2d_POST = 836, >+ AArch64_LD2Twov2s = 837, >+ AArch64_LD2Twov2s_POST = 838, >+ AArch64_LD2Twov4h = 839, >+ AArch64_LD2Twov4h_POST = 840, >+ AArch64_LD2Twov4s = 841, >+ AArch64_LD2Twov4s_POST = 842, >+ AArch64_LD2Twov8b = 843, >+ AArch64_LD2Twov8b_POST = 844, >+ AArch64_LD2Twov8h = 845, >+ AArch64_LD2Twov8h_POST = 846, >+ AArch64_LD2i16 = 847, >+ AArch64_LD2i16_POST = 848, >+ AArch64_LD2i32 = 849, >+ AArch64_LD2i32_POST = 850, >+ AArch64_LD2i64 = 851, >+ AArch64_LD2i64_POST = 852, >+ AArch64_LD2i8 = 853, >+ AArch64_LD2i8_POST = 854, >+ AArch64_LD3Rv16b = 855, >+ AArch64_LD3Rv16b_POST = 856, >+ AArch64_LD3Rv1d = 857, >+ AArch64_LD3Rv1d_POST = 858, >+ AArch64_LD3Rv2d = 859, >+ AArch64_LD3Rv2d_POST = 860, >+ AArch64_LD3Rv2s = 861, >+ AArch64_LD3Rv2s_POST = 862, >+ AArch64_LD3Rv4h = 863, >+ AArch64_LD3Rv4h_POST = 864, >+ AArch64_LD3Rv4s = 865, >+ AArch64_LD3Rv4s_POST = 866, >+ AArch64_LD3Rv8b = 867, >+ AArch64_LD3Rv8b_POST = 868, >+ AArch64_LD3Rv8h = 869, >+ AArch64_LD3Rv8h_POST = 870, >+ AArch64_LD3Threev16b = 871, >+ AArch64_LD3Threev16b_POST = 872, >+ AArch64_LD3Threev2d = 873, >+ AArch64_LD3Threev2d_POST = 874, >+ AArch64_LD3Threev2s = 875, >+ AArch64_LD3Threev2s_POST = 876, >+ AArch64_LD3Threev4h = 877, >+ AArch64_LD3Threev4h_POST = 878, >+ AArch64_LD3Threev4s = 879, >+ AArch64_LD3Threev4s_POST = 880, >+ AArch64_LD3Threev8b = 881, >+ AArch64_LD3Threev8b_POST = 882, >+ AArch64_LD3Threev8h = 883, >+ AArch64_LD3Threev8h_POST = 884, >+ AArch64_LD3i16 = 885, >+ AArch64_LD3i16_POST = 886, >+ AArch64_LD3i32 = 887, >+ AArch64_LD3i32_POST = 888, >+ AArch64_LD3i64 = 889, >+ AArch64_LD3i64_POST = 890, >+ AArch64_LD3i8 = 891, >+ AArch64_LD3i8_POST = 892, >+ AArch64_LD4Fourv16b = 893, >+ AArch64_LD4Fourv16b_POST = 894, >+ AArch64_LD4Fourv2d = 895, >+ AArch64_LD4Fourv2d_POST = 896, >+ AArch64_LD4Fourv2s = 897, >+ AArch64_LD4Fourv2s_POST = 898, >+ AArch64_LD4Fourv4h = 899, >+ AArch64_LD4Fourv4h_POST = 900, >+ AArch64_LD4Fourv4s = 901, >+ AArch64_LD4Fourv4s_POST = 902, >+ AArch64_LD4Fourv8b = 903, >+ AArch64_LD4Fourv8b_POST = 904, >+ AArch64_LD4Fourv8h = 905, >+ AArch64_LD4Fourv8h_POST = 906, >+ AArch64_LD4Rv16b = 907, >+ AArch64_LD4Rv16b_POST = 908, >+ AArch64_LD4Rv1d = 909, >+ AArch64_LD4Rv1d_POST = 910, >+ AArch64_LD4Rv2d = 911, >+ AArch64_LD4Rv2d_POST = 912, >+ AArch64_LD4Rv2s = 913, >+ AArch64_LD4Rv2s_POST = 914, >+ AArch64_LD4Rv4h = 915, >+ AArch64_LD4Rv4h_POST = 916, >+ AArch64_LD4Rv4s = 917, >+ AArch64_LD4Rv4s_POST = 918, >+ AArch64_LD4Rv8b = 919, >+ AArch64_LD4Rv8b_POST = 920, >+ AArch64_LD4Rv8h = 921, >+ AArch64_LD4Rv8h_POST = 922, >+ AArch64_LD4i16 = 923, >+ AArch64_LD4i16_POST = 924, >+ AArch64_LD4i32 = 925, >+ AArch64_LD4i32_POST = 926, >+ AArch64_LD4i64 = 927, >+ AArch64_LD4i64_POST = 928, >+ AArch64_LD4i8 = 929, >+ AArch64_LD4i8_POST = 930, >+ AArch64_LDARB = 931, >+ AArch64_LDARH = 932, >+ AArch64_LDARW = 933, >+ AArch64_LDARX = 934, >+ AArch64_LDAXPW = 935, >+ AArch64_LDAXPX = 936, >+ AArch64_LDAXRB = 937, >+ AArch64_LDAXRH = 938, >+ AArch64_LDAXRW = 939, >+ AArch64_LDAXRX = 940, >+ AArch64_LDNPDi = 941, >+ AArch64_LDNPQi = 942, >+ AArch64_LDNPSi = 943, >+ AArch64_LDNPWi = 944, >+ AArch64_LDNPXi = 945, >+ AArch64_LDPDi = 946, >+ AArch64_LDPDpost = 947, >+ AArch64_LDPDpre = 948, >+ AArch64_LDPQi = 949, >+ AArch64_LDPQpost = 950, >+ AArch64_LDPQpre = 951, >+ AArch64_LDPSWi = 952, >+ AArch64_LDPSWpost = 953, >+ AArch64_LDPSWpre = 954, >+ AArch64_LDPSi = 955, >+ AArch64_LDPSpost = 956, >+ AArch64_LDPSpre = 957, >+ AArch64_LDPWi = 958, >+ AArch64_LDPWpost = 959, >+ AArch64_LDPWpre = 960, >+ AArch64_LDPXi = 961, >+ AArch64_LDPXpost = 962, >+ AArch64_LDPXpre = 963, >+ AArch64_LDRBBpost = 964, >+ AArch64_LDRBBpre = 965, >+ AArch64_LDRBBroW = 966, >+ AArch64_LDRBBroX = 967, >+ AArch64_LDRBBui = 968, >+ AArch64_LDRBpost = 969, >+ AArch64_LDRBpre = 970, >+ AArch64_LDRBroW = 971, >+ AArch64_LDRBroX = 972, >+ AArch64_LDRBui = 973, >+ AArch64_LDRDl = 974, >+ AArch64_LDRDpost = 975, >+ AArch64_LDRDpre = 976, >+ AArch64_LDRDroW = 977, >+ AArch64_LDRDroX = 978, >+ AArch64_LDRDui = 979, >+ AArch64_LDRHHpost = 980, >+ AArch64_LDRHHpre = 981, >+ AArch64_LDRHHroW = 982, >+ AArch64_LDRHHroX = 983, >+ AArch64_LDRHHui = 984, >+ AArch64_LDRHpost = 985, >+ AArch64_LDRHpre = 986, >+ AArch64_LDRHroW = 987, >+ AArch64_LDRHroX = 988, >+ AArch64_LDRHui = 989, >+ AArch64_LDRQl = 990, >+ AArch64_LDRQpost = 991, >+ AArch64_LDRQpre = 992, >+ AArch64_LDRQroW = 993, >+ AArch64_LDRQroX = 994, >+ AArch64_LDRQui = 995, >+ AArch64_LDRSBWpost = 996, >+ AArch64_LDRSBWpre = 997, >+ AArch64_LDRSBWroW = 998, >+ AArch64_LDRSBWroX = 999, >+ AArch64_LDRSBWui = 1000, >+ AArch64_LDRSBXpost = 1001, >+ AArch64_LDRSBXpre = 1002, >+ AArch64_LDRSBXroW = 1003, >+ AArch64_LDRSBXroX = 1004, >+ AArch64_LDRSBXui = 1005, >+ AArch64_LDRSHWpost = 1006, >+ AArch64_LDRSHWpre = 1007, >+ AArch64_LDRSHWroW = 1008, >+ AArch64_LDRSHWroX = 1009, >+ AArch64_LDRSHWui = 1010, >+ AArch64_LDRSHXpost = 1011, >+ AArch64_LDRSHXpre = 1012, >+ AArch64_LDRSHXroW = 1013, >+ AArch64_LDRSHXroX = 1014, >+ AArch64_LDRSHXui = 1015, >+ AArch64_LDRSWl = 1016, >+ AArch64_LDRSWpost = 1017, >+ AArch64_LDRSWpre = 1018, >+ AArch64_LDRSWroW = 1019, >+ AArch64_LDRSWroX = 1020, >+ AArch64_LDRSWui = 1021, >+ AArch64_LDRSl = 1022, >+ AArch64_LDRSpost = 1023, >+ AArch64_LDRSpre = 1024, >+ AArch64_LDRSroW = 1025, >+ AArch64_LDRSroX = 1026, >+ AArch64_LDRSui = 1027, >+ AArch64_LDRWl = 1028, >+ AArch64_LDRWpost = 1029, >+ AArch64_LDRWpre = 1030, >+ AArch64_LDRWroW = 1031, >+ AArch64_LDRWroX = 1032, >+ AArch64_LDRWui = 1033, >+ AArch64_LDRXl = 1034, >+ AArch64_LDRXpost = 1035, >+ AArch64_LDRXpre = 1036, >+ AArch64_LDRXroW = 1037, >+ AArch64_LDRXroX = 1038, >+ AArch64_LDRXui = 1039, >+ AArch64_LDTRBi = 1040, >+ AArch64_LDTRHi = 1041, >+ AArch64_LDTRSBWi = 1042, >+ AArch64_LDTRSBXi = 1043, >+ AArch64_LDTRSHWi = 1044, >+ AArch64_LDTRSHXi = 1045, >+ AArch64_LDTRSWi = 1046, >+ AArch64_LDTRWi = 1047, >+ AArch64_LDTRXi = 1048, >+ AArch64_LDURBBi = 1049, >+ AArch64_LDURBi = 1050, >+ AArch64_LDURDi = 1051, >+ AArch64_LDURHHi = 1052, >+ AArch64_LDURHi = 1053, >+ AArch64_LDURQi = 1054, >+ AArch64_LDURSBWi = 1055, >+ AArch64_LDURSBXi = 1056, >+ AArch64_LDURSHWi = 1057, >+ AArch64_LDURSHXi = 1058, >+ AArch64_LDURSWi = 1059, >+ AArch64_LDURSi = 1060, >+ AArch64_LDURWi = 1061, >+ AArch64_LDURXi = 1062, >+ AArch64_LDXPW = 1063, >+ AArch64_LDXPX = 1064, >+ AArch64_LDXRB = 1065, >+ AArch64_LDXRH = 1066, >+ AArch64_LDXRW = 1067, >+ AArch64_LDXRX = 1068, >+ AArch64_LOADgot = 1069, >+ AArch64_LSLVWr = 1070, >+ AArch64_LSLVXr = 1071, >+ AArch64_LSRVWr = 1072, >+ AArch64_LSRVXr = 1073, >+ AArch64_MADDWrrr = 1074, >+ AArch64_MADDXrrr = 1075, >+ AArch64_MLAv16i8 = 1076, >+ AArch64_MLAv2i32 = 1077, >+ AArch64_MLAv2i32_indexed = 1078, >+ AArch64_MLAv4i16 = 1079, >+ AArch64_MLAv4i16_indexed = 1080, >+ AArch64_MLAv4i32 = 1081, >+ AArch64_MLAv4i32_indexed = 1082, >+ AArch64_MLAv8i16 = 1083, >+ AArch64_MLAv8i16_indexed = 1084, >+ AArch64_MLAv8i8 = 1085, >+ AArch64_MLSv16i8 = 1086, >+ AArch64_MLSv2i32 = 1087, >+ AArch64_MLSv2i32_indexed = 1088, >+ AArch64_MLSv4i16 = 1089, >+ AArch64_MLSv4i16_indexed = 1090, >+ AArch64_MLSv4i32 = 1091, >+ AArch64_MLSv4i32_indexed = 1092, >+ AArch64_MLSv8i16 = 1093, >+ AArch64_MLSv8i16_indexed = 1094, >+ AArch64_MLSv8i8 = 1095, >+ AArch64_MOVID = 1096, >+ AArch64_MOVIv16b_ns = 1097, >+ AArch64_MOVIv2d_ns = 1098, >+ AArch64_MOVIv2i32 = 1099, >+ AArch64_MOVIv2s_msl = 1100, >+ AArch64_MOVIv4i16 = 1101, >+ AArch64_MOVIv4i32 = 1102, >+ AArch64_MOVIv4s_msl = 1103, >+ AArch64_MOVIv8b_ns = 1104, >+ AArch64_MOVIv8i16 = 1105, >+ AArch64_MOVKWi = 1106, >+ AArch64_MOVKXi = 1107, >+ AArch64_MOVNWi = 1108, >+ AArch64_MOVNXi = 1109, >+ AArch64_MOVZWi = 1110, >+ AArch64_MOVZXi = 1111, >+ AArch64_MOVaddr = 1112, >+ AArch64_MOVaddrBA = 1113, >+ AArch64_MOVaddrCP = 1114, >+ AArch64_MOVaddrEXT = 1115, >+ AArch64_MOVaddrJT = 1116, >+ AArch64_MOVaddrTLS = 1117, >+ AArch64_MOVi32imm = 1118, >+ AArch64_MOVi64imm = 1119, >+ AArch64_MRS = 1120, >+ AArch64_MSR = 1121, >+ AArch64_MSRpstate = 1122, >+ AArch64_MSUBWrrr = 1123, >+ AArch64_MSUBXrrr = 1124, >+ AArch64_MULv16i8 = 1125, >+ AArch64_MULv2i32 = 1126, >+ AArch64_MULv2i32_indexed = 1127, >+ AArch64_MULv4i16 = 1128, >+ AArch64_MULv4i16_indexed = 1129, >+ AArch64_MULv4i32 = 1130, >+ AArch64_MULv4i32_indexed = 1131, >+ AArch64_MULv8i16 = 1132, >+ AArch64_MULv8i16_indexed = 1133, >+ AArch64_MULv8i8 = 1134, >+ AArch64_MVNIv2i32 = 1135, >+ AArch64_MVNIv2s_msl = 1136, >+ AArch64_MVNIv4i16 = 1137, >+ AArch64_MVNIv4i32 = 1138, >+ AArch64_MVNIv4s_msl = 1139, >+ AArch64_MVNIv8i16 = 1140, >+ AArch64_NEGv16i8 = 1141, >+ AArch64_NEGv1i64 = 1142, >+ AArch64_NEGv2i32 = 1143, >+ AArch64_NEGv2i64 = 1144, >+ AArch64_NEGv4i16 = 1145, >+ AArch64_NEGv4i32 = 1146, >+ AArch64_NEGv8i16 = 1147, >+ AArch64_NEGv8i8 = 1148, >+ AArch64_NOTv16i8 = 1149, >+ AArch64_NOTv8i8 = 1150, >+ AArch64_ORNWrr = 1151, >+ AArch64_ORNWrs = 1152, >+ AArch64_ORNXrr = 1153, >+ AArch64_ORNXrs = 1154, >+ AArch64_ORNv16i8 = 1155, >+ AArch64_ORNv8i8 = 1156, >+ AArch64_ORRWri = 1157, >+ AArch64_ORRWrr = 1158, >+ AArch64_ORRWrs = 1159, >+ AArch64_ORRXri = 1160, >+ AArch64_ORRXrr = 1161, >+ AArch64_ORRXrs = 1162, >+ AArch64_ORRv16i8 = 1163, >+ AArch64_ORRv2i32 = 1164, >+ AArch64_ORRv4i16 = 1165, >+ AArch64_ORRv4i32 = 1166, >+ AArch64_ORRv8i16 = 1167, >+ AArch64_ORRv8i8 = 1168, >+ AArch64_PMULLv16i8 = 1169, >+ AArch64_PMULLv1i64 = 1170, >+ AArch64_PMULLv2i64 = 1171, >+ AArch64_PMULLv8i8 = 1172, >+ AArch64_PMULv16i8 = 1173, >+ AArch64_PMULv8i8 = 1174, >+ AArch64_PRFMl = 1175, >+ AArch64_PRFMroW = 1176, >+ AArch64_PRFMroX = 1177, >+ AArch64_PRFMui = 1178, >+ AArch64_PRFUMi = 1179, >+ AArch64_RADDHNv2i64_v2i32 = 1180, >+ AArch64_RADDHNv2i64_v4i32 = 1181, >+ AArch64_RADDHNv4i32_v4i16 = 1182, >+ AArch64_RADDHNv4i32_v8i16 = 1183, >+ AArch64_RADDHNv8i16_v16i8 = 1184, >+ AArch64_RADDHNv8i16_v8i8 = 1185, >+ AArch64_RBITWr = 1186, >+ AArch64_RBITXr = 1187, >+ AArch64_RBITv16i8 = 1188, >+ AArch64_RBITv8i8 = 1189, >+ AArch64_RET = 1190, >+ AArch64_RET_ReallyLR = 1191, >+ AArch64_REV16Wr = 1192, >+ AArch64_REV16Xr = 1193, >+ AArch64_REV16v16i8 = 1194, >+ AArch64_REV16v8i8 = 1195, >+ AArch64_REV32Xr = 1196, >+ AArch64_REV32v16i8 = 1197, >+ AArch64_REV32v4i16 = 1198, >+ AArch64_REV32v8i16 = 1199, >+ AArch64_REV32v8i8 = 1200, >+ AArch64_REV64v16i8 = 1201, >+ AArch64_REV64v2i32 = 1202, >+ AArch64_REV64v4i16 = 1203, >+ AArch64_REV64v4i32 = 1204, >+ AArch64_REV64v8i16 = 1205, >+ AArch64_REV64v8i8 = 1206, >+ AArch64_REVWr = 1207, >+ AArch64_REVXr = 1208, >+ AArch64_RORVWr = 1209, >+ AArch64_RORVXr = 1210, >+ AArch64_RSHRNv16i8_shift = 1211, >+ AArch64_RSHRNv2i32_shift = 1212, >+ AArch64_RSHRNv4i16_shift = 1213, >+ AArch64_RSHRNv4i32_shift = 1214, >+ AArch64_RSHRNv8i16_shift = 1215, >+ AArch64_RSHRNv8i8_shift = 1216, >+ AArch64_RSUBHNv2i64_v2i32 = 1217, >+ AArch64_RSUBHNv2i64_v4i32 = 1218, >+ AArch64_RSUBHNv4i32_v4i16 = 1219, >+ AArch64_RSUBHNv4i32_v8i16 = 1220, >+ AArch64_RSUBHNv8i16_v16i8 = 1221, >+ AArch64_RSUBHNv8i16_v8i8 = 1222, >+ AArch64_SABALv16i8_v8i16 = 1223, >+ AArch64_SABALv2i32_v2i64 = 1224, >+ AArch64_SABALv4i16_v4i32 = 1225, >+ AArch64_SABALv4i32_v2i64 = 1226, >+ AArch64_SABALv8i16_v4i32 = 1227, >+ AArch64_SABALv8i8_v8i16 = 1228, >+ AArch64_SABAv16i8 = 1229, >+ AArch64_SABAv2i32 = 1230, >+ AArch64_SABAv4i16 = 1231, >+ AArch64_SABAv4i32 = 1232, >+ AArch64_SABAv8i16 = 1233, >+ AArch64_SABAv8i8 = 1234, >+ AArch64_SABDLv16i8_v8i16 = 1235, >+ AArch64_SABDLv2i32_v2i64 = 1236, >+ AArch64_SABDLv4i16_v4i32 = 1237, >+ AArch64_SABDLv4i32_v2i64 = 1238, >+ AArch64_SABDLv8i16_v4i32 = 1239, >+ AArch64_SABDLv8i8_v8i16 = 1240, >+ AArch64_SABDv16i8 = 1241, >+ AArch64_SABDv2i32 = 1242, >+ AArch64_SABDv4i16 = 1243, >+ AArch64_SABDv4i32 = 1244, >+ AArch64_SABDv8i16 = 1245, >+ AArch64_SABDv8i8 = 1246, >+ AArch64_SADALPv16i8_v8i16 = 1247, >+ AArch64_SADALPv2i32_v1i64 = 1248, >+ AArch64_SADALPv4i16_v2i32 = 1249, >+ AArch64_SADALPv4i32_v2i64 = 1250, >+ AArch64_SADALPv8i16_v4i32 = 1251, >+ AArch64_SADALPv8i8_v4i16 = 1252, >+ AArch64_SADDLPv16i8_v8i16 = 1253, >+ AArch64_SADDLPv2i32_v1i64 = 1254, >+ AArch64_SADDLPv4i16_v2i32 = 1255, >+ AArch64_SADDLPv4i32_v2i64 = 1256, >+ AArch64_SADDLPv8i16_v4i32 = 1257, >+ AArch64_SADDLPv8i8_v4i16 = 1258, >+ AArch64_SADDLVv16i8v = 1259, >+ AArch64_SADDLVv4i16v = 1260, >+ AArch64_SADDLVv4i32v = 1261, >+ AArch64_SADDLVv8i16v = 1262, >+ AArch64_SADDLVv8i8v = 1263, >+ AArch64_SADDLv16i8_v8i16 = 1264, >+ AArch64_SADDLv2i32_v2i64 = 1265, >+ AArch64_SADDLv4i16_v4i32 = 1266, >+ AArch64_SADDLv4i32_v2i64 = 1267, >+ AArch64_SADDLv8i16_v4i32 = 1268, >+ AArch64_SADDLv8i8_v8i16 = 1269, >+ AArch64_SADDWv16i8_v8i16 = 1270, >+ AArch64_SADDWv2i32_v2i64 = 1271, >+ AArch64_SADDWv4i16_v4i32 = 1272, >+ AArch64_SADDWv4i32_v2i64 = 1273, >+ AArch64_SADDWv8i16_v4i32 = 1274, >+ AArch64_SADDWv8i8_v8i16 = 1275, >+ AArch64_SBCSWr = 1276, >+ AArch64_SBCSXr = 1277, >+ AArch64_SBCWr = 1278, >+ AArch64_SBCXr = 1279, >+ AArch64_SBFMWri = 1280, >+ AArch64_SBFMXri = 1281, >+ AArch64_SCVTFSWDri = 1282, >+ AArch64_SCVTFSWSri = 1283, >+ AArch64_SCVTFSXDri = 1284, >+ AArch64_SCVTFSXSri = 1285, >+ AArch64_SCVTFUWDri = 1286, >+ AArch64_SCVTFUWSri = 1287, >+ AArch64_SCVTFUXDri = 1288, >+ AArch64_SCVTFUXSri = 1289, >+ AArch64_SCVTFd = 1290, >+ AArch64_SCVTFs = 1291, >+ AArch64_SCVTFv1i32 = 1292, >+ AArch64_SCVTFv1i64 = 1293, >+ AArch64_SCVTFv2f32 = 1294, >+ AArch64_SCVTFv2f64 = 1295, >+ AArch64_SCVTFv2i32_shift = 1296, >+ AArch64_SCVTFv2i64_shift = 1297, >+ AArch64_SCVTFv4f32 = 1298, >+ AArch64_SCVTFv4i32_shift = 1299, >+ AArch64_SDIVWr = 1300, >+ AArch64_SDIVXr = 1301, >+ AArch64_SDIV_IntWr = 1302, >+ AArch64_SDIV_IntXr = 1303, >+ AArch64_SHA1Crrr = 1304, >+ AArch64_SHA1Hrr = 1305, >+ AArch64_SHA1Mrrr = 1306, >+ AArch64_SHA1Prrr = 1307, >+ AArch64_SHA1SU0rrr = 1308, >+ AArch64_SHA1SU1rr = 1309, >+ AArch64_SHA256H2rrr = 1310, >+ AArch64_SHA256Hrrr = 1311, >+ AArch64_SHA256SU0rr = 1312, >+ AArch64_SHA256SU1rrr = 1313, >+ AArch64_SHADDv16i8 = 1314, >+ AArch64_SHADDv2i32 = 1315, >+ AArch64_SHADDv4i16 = 1316, >+ AArch64_SHADDv4i32 = 1317, >+ AArch64_SHADDv8i16 = 1318, >+ AArch64_SHADDv8i8 = 1319, >+ AArch64_SHLLv16i8 = 1320, >+ AArch64_SHLLv2i32 = 1321, >+ AArch64_SHLLv4i16 = 1322, >+ AArch64_SHLLv4i32 = 1323, >+ AArch64_SHLLv8i16 = 1324, >+ AArch64_SHLLv8i8 = 1325, >+ AArch64_SHLd = 1326, >+ AArch64_SHLv16i8_shift = 1327, >+ AArch64_SHLv2i32_shift = 1328, >+ AArch64_SHLv2i64_shift = 1329, >+ AArch64_SHLv4i16_shift = 1330, >+ AArch64_SHLv4i32_shift = 1331, >+ AArch64_SHLv8i16_shift = 1332, >+ AArch64_SHLv8i8_shift = 1333, >+ AArch64_SHRNv16i8_shift = 1334, >+ AArch64_SHRNv2i32_shift = 1335, >+ AArch64_SHRNv4i16_shift = 1336, >+ AArch64_SHRNv4i32_shift = 1337, >+ AArch64_SHRNv8i16_shift = 1338, >+ AArch64_SHRNv8i8_shift = 1339, >+ AArch64_SHSUBv16i8 = 1340, >+ AArch64_SHSUBv2i32 = 1341, >+ AArch64_SHSUBv4i16 = 1342, >+ AArch64_SHSUBv4i32 = 1343, >+ AArch64_SHSUBv8i16 = 1344, >+ AArch64_SHSUBv8i8 = 1345, >+ AArch64_SLId = 1346, >+ AArch64_SLIv16i8_shift = 1347, >+ AArch64_SLIv2i32_shift = 1348, >+ AArch64_SLIv2i64_shift = 1349, >+ AArch64_SLIv4i16_shift = 1350, >+ AArch64_SLIv4i32_shift = 1351, >+ AArch64_SLIv8i16_shift = 1352, >+ AArch64_SLIv8i8_shift = 1353, >+ AArch64_SMADDLrrr = 1354, >+ AArch64_SMAXPv16i8 = 1355, >+ AArch64_SMAXPv2i32 = 1356, >+ AArch64_SMAXPv4i16 = 1357, >+ AArch64_SMAXPv4i32 = 1358, >+ AArch64_SMAXPv8i16 = 1359, >+ AArch64_SMAXPv8i8 = 1360, >+ AArch64_SMAXVv16i8v = 1361, >+ AArch64_SMAXVv4i16v = 1362, >+ AArch64_SMAXVv4i32v = 1363, >+ AArch64_SMAXVv8i16v = 1364, >+ AArch64_SMAXVv8i8v = 1365, >+ AArch64_SMAXv16i8 = 1366, >+ AArch64_SMAXv2i32 = 1367, >+ AArch64_SMAXv4i16 = 1368, >+ AArch64_SMAXv4i32 = 1369, >+ AArch64_SMAXv8i16 = 1370, >+ AArch64_SMAXv8i8 = 1371, >+ AArch64_SMC = 1372, >+ AArch64_SMINPv16i8 = 1373, >+ AArch64_SMINPv2i32 = 1374, >+ AArch64_SMINPv4i16 = 1375, >+ AArch64_SMINPv4i32 = 1376, >+ AArch64_SMINPv8i16 = 1377, >+ AArch64_SMINPv8i8 = 1378, >+ AArch64_SMINVv16i8v = 1379, >+ AArch64_SMINVv4i16v = 1380, >+ AArch64_SMINVv4i32v = 1381, >+ AArch64_SMINVv8i16v = 1382, >+ AArch64_SMINVv8i8v = 1383, >+ AArch64_SMINv16i8 = 1384, >+ AArch64_SMINv2i32 = 1385, >+ AArch64_SMINv4i16 = 1386, >+ AArch64_SMINv4i32 = 1387, >+ AArch64_SMINv8i16 = 1388, >+ AArch64_SMINv8i8 = 1389, >+ AArch64_SMLALv16i8_v8i16 = 1390, >+ AArch64_SMLALv2i32_indexed = 1391, >+ AArch64_SMLALv2i32_v2i64 = 1392, >+ AArch64_SMLALv4i16_indexed = 1393, >+ AArch64_SMLALv4i16_v4i32 = 1394, >+ AArch64_SMLALv4i32_indexed = 1395, >+ AArch64_SMLALv4i32_v2i64 = 1396, >+ AArch64_SMLALv8i16_indexed = 1397, >+ AArch64_SMLALv8i16_v4i32 = 1398, >+ AArch64_SMLALv8i8_v8i16 = 1399, >+ AArch64_SMLSLv16i8_v8i16 = 1400, >+ AArch64_SMLSLv2i32_indexed = 1401, >+ AArch64_SMLSLv2i32_v2i64 = 1402, >+ AArch64_SMLSLv4i16_indexed = 1403, >+ AArch64_SMLSLv4i16_v4i32 = 1404, >+ AArch64_SMLSLv4i32_indexed = 1405, >+ AArch64_SMLSLv4i32_v2i64 = 1406, >+ AArch64_SMLSLv8i16_indexed = 1407, >+ AArch64_SMLSLv8i16_v4i32 = 1408, >+ AArch64_SMLSLv8i8_v8i16 = 1409, >+ AArch64_SMOVvi16to32 = 1410, >+ AArch64_SMOVvi16to64 = 1411, >+ AArch64_SMOVvi32to64 = 1412, >+ AArch64_SMOVvi8to32 = 1413, >+ AArch64_SMOVvi8to64 = 1414, >+ AArch64_SMSUBLrrr = 1415, >+ AArch64_SMULHrr = 1416, >+ AArch64_SMULLv16i8_v8i16 = 1417, >+ AArch64_SMULLv2i32_indexed = 1418, >+ AArch64_SMULLv2i32_v2i64 = 1419, >+ AArch64_SMULLv4i16_indexed = 1420, >+ AArch64_SMULLv4i16_v4i32 = 1421, >+ AArch64_SMULLv4i32_indexed = 1422, >+ AArch64_SMULLv4i32_v2i64 = 1423, >+ AArch64_SMULLv8i16_indexed = 1424, >+ AArch64_SMULLv8i16_v4i32 = 1425, >+ AArch64_SMULLv8i8_v8i16 = 1426, >+ AArch64_SQABSv16i8 = 1427, >+ AArch64_SQABSv1i16 = 1428, >+ AArch64_SQABSv1i32 = 1429, >+ AArch64_SQABSv1i64 = 1430, >+ AArch64_SQABSv1i8 = 1431, >+ AArch64_SQABSv2i32 = 1432, >+ AArch64_SQABSv2i64 = 1433, >+ AArch64_SQABSv4i16 = 1434, >+ AArch64_SQABSv4i32 = 1435, >+ AArch64_SQABSv8i16 = 1436, >+ AArch64_SQABSv8i8 = 1437, >+ AArch64_SQADDv16i8 = 1438, >+ AArch64_SQADDv1i16 = 1439, >+ AArch64_SQADDv1i32 = 1440, >+ AArch64_SQADDv1i64 = 1441, >+ AArch64_SQADDv1i8 = 1442, >+ AArch64_SQADDv2i32 = 1443, >+ AArch64_SQADDv2i64 = 1444, >+ AArch64_SQADDv4i16 = 1445, >+ AArch64_SQADDv4i32 = 1446, >+ AArch64_SQADDv8i16 = 1447, >+ AArch64_SQADDv8i8 = 1448, >+ AArch64_SQDMLALi16 = 1449, >+ AArch64_SQDMLALi32 = 1450, >+ AArch64_SQDMLALv1i32_indexed = 1451, >+ AArch64_SQDMLALv1i64_indexed = 1452, >+ AArch64_SQDMLALv2i32_indexed = 1453, >+ AArch64_SQDMLALv2i32_v2i64 = 1454, >+ AArch64_SQDMLALv4i16_indexed = 1455, >+ AArch64_SQDMLALv4i16_v4i32 = 1456, >+ AArch64_SQDMLALv4i32_indexed = 1457, >+ AArch64_SQDMLALv4i32_v2i64 = 1458, >+ AArch64_SQDMLALv8i16_indexed = 1459, >+ AArch64_SQDMLALv8i16_v4i32 = 1460, >+ AArch64_SQDMLSLi16 = 1461, >+ AArch64_SQDMLSLi32 = 1462, >+ AArch64_SQDMLSLv1i32_indexed = 1463, >+ AArch64_SQDMLSLv1i64_indexed = 1464, >+ AArch64_SQDMLSLv2i32_indexed = 1465, >+ AArch64_SQDMLSLv2i32_v2i64 = 1466, >+ AArch64_SQDMLSLv4i16_indexed = 1467, >+ AArch64_SQDMLSLv4i16_v4i32 = 1468, >+ AArch64_SQDMLSLv4i32_indexed = 1469, >+ AArch64_SQDMLSLv4i32_v2i64 = 1470, >+ AArch64_SQDMLSLv8i16_indexed = 1471, >+ AArch64_SQDMLSLv8i16_v4i32 = 1472, >+ AArch64_SQDMULHv1i16 = 1473, >+ AArch64_SQDMULHv1i16_indexed = 1474, >+ AArch64_SQDMULHv1i32 = 1475, >+ AArch64_SQDMULHv1i32_indexed = 1476, >+ AArch64_SQDMULHv2i32 = 1477, >+ AArch64_SQDMULHv2i32_indexed = 1478, >+ AArch64_SQDMULHv4i16 = 1479, >+ AArch64_SQDMULHv4i16_indexed = 1480, >+ AArch64_SQDMULHv4i32 = 1481, >+ AArch64_SQDMULHv4i32_indexed = 1482, >+ AArch64_SQDMULHv8i16 = 1483, >+ AArch64_SQDMULHv8i16_indexed = 1484, >+ AArch64_SQDMULLi16 = 1485, >+ AArch64_SQDMULLi32 = 1486, >+ AArch64_SQDMULLv1i32_indexed = 1487, >+ AArch64_SQDMULLv1i64_indexed = 1488, >+ AArch64_SQDMULLv2i32_indexed = 1489, >+ AArch64_SQDMULLv2i32_v2i64 = 1490, >+ AArch64_SQDMULLv4i16_indexed = 1491, >+ AArch64_SQDMULLv4i16_v4i32 = 1492, >+ AArch64_SQDMULLv4i32_indexed = 1493, >+ AArch64_SQDMULLv4i32_v2i64 = 1494, >+ AArch64_SQDMULLv8i16_indexed = 1495, >+ AArch64_SQDMULLv8i16_v4i32 = 1496, >+ AArch64_SQNEGv16i8 = 1497, >+ AArch64_SQNEGv1i16 = 1498, >+ AArch64_SQNEGv1i32 = 1499, >+ AArch64_SQNEGv1i64 = 1500, >+ AArch64_SQNEGv1i8 = 1501, >+ AArch64_SQNEGv2i32 = 1502, >+ AArch64_SQNEGv2i64 = 1503, >+ AArch64_SQNEGv4i16 = 1504, >+ AArch64_SQNEGv4i32 = 1505, >+ AArch64_SQNEGv8i16 = 1506, >+ AArch64_SQNEGv8i8 = 1507, >+ AArch64_SQRDMULHv1i16 = 1508, >+ AArch64_SQRDMULHv1i16_indexed = 1509, >+ AArch64_SQRDMULHv1i32 = 1510, >+ AArch64_SQRDMULHv1i32_indexed = 1511, >+ AArch64_SQRDMULHv2i32 = 1512, >+ AArch64_SQRDMULHv2i32_indexed = 1513, >+ AArch64_SQRDMULHv4i16 = 1514, >+ AArch64_SQRDMULHv4i16_indexed = 1515, >+ AArch64_SQRDMULHv4i32 = 1516, >+ AArch64_SQRDMULHv4i32_indexed = 1517, >+ AArch64_SQRDMULHv8i16 = 1518, >+ AArch64_SQRDMULHv8i16_indexed = 1519, >+ AArch64_SQRSHLv16i8 = 1520, >+ AArch64_SQRSHLv1i16 = 1521, >+ AArch64_SQRSHLv1i32 = 1522, >+ AArch64_SQRSHLv1i64 = 1523, >+ AArch64_SQRSHLv1i8 = 1524, >+ AArch64_SQRSHLv2i32 = 1525, >+ AArch64_SQRSHLv2i64 = 1526, >+ AArch64_SQRSHLv4i16 = 1527, >+ AArch64_SQRSHLv4i32 = 1528, >+ AArch64_SQRSHLv8i16 = 1529, >+ AArch64_SQRSHLv8i8 = 1530, >+ AArch64_SQRSHRNb = 1531, >+ AArch64_SQRSHRNh = 1532, >+ AArch64_SQRSHRNs = 1533, >+ AArch64_SQRSHRNv16i8_shift = 1534, >+ AArch64_SQRSHRNv2i32_shift = 1535, >+ AArch64_SQRSHRNv4i16_shift = 1536, >+ AArch64_SQRSHRNv4i32_shift = 1537, >+ AArch64_SQRSHRNv8i16_shift = 1538, >+ AArch64_SQRSHRNv8i8_shift = 1539, >+ AArch64_SQRSHRUNb = 1540, >+ AArch64_SQRSHRUNh = 1541, >+ AArch64_SQRSHRUNs = 1542, >+ AArch64_SQRSHRUNv16i8_shift = 1543, >+ AArch64_SQRSHRUNv2i32_shift = 1544, >+ AArch64_SQRSHRUNv4i16_shift = 1545, >+ AArch64_SQRSHRUNv4i32_shift = 1546, >+ AArch64_SQRSHRUNv8i16_shift = 1547, >+ AArch64_SQRSHRUNv8i8_shift = 1548, >+ AArch64_SQSHLUb = 1549, >+ AArch64_SQSHLUd = 1550, >+ AArch64_SQSHLUh = 1551, >+ AArch64_SQSHLUs = 1552, >+ AArch64_SQSHLUv16i8_shift = 1553, >+ AArch64_SQSHLUv2i32_shift = 1554, >+ AArch64_SQSHLUv2i64_shift = 1555, >+ AArch64_SQSHLUv4i16_shift = 1556, >+ AArch64_SQSHLUv4i32_shift = 1557, >+ AArch64_SQSHLUv8i16_shift = 1558, >+ AArch64_SQSHLUv8i8_shift = 1559, >+ AArch64_SQSHLb = 1560, >+ AArch64_SQSHLd = 1561, >+ AArch64_SQSHLh = 1562, >+ AArch64_SQSHLs = 1563, >+ AArch64_SQSHLv16i8 = 1564, >+ AArch64_SQSHLv16i8_shift = 1565, >+ AArch64_SQSHLv1i16 = 1566, >+ AArch64_SQSHLv1i32 = 1567, >+ AArch64_SQSHLv1i64 = 1568, >+ AArch64_SQSHLv1i8 = 1569, >+ AArch64_SQSHLv2i32 = 1570, >+ AArch64_SQSHLv2i32_shift = 1571, >+ AArch64_SQSHLv2i64 = 1572, >+ AArch64_SQSHLv2i64_shift = 1573, >+ AArch64_SQSHLv4i16 = 1574, >+ AArch64_SQSHLv4i16_shift = 1575, >+ AArch64_SQSHLv4i32 = 1576, >+ AArch64_SQSHLv4i32_shift = 1577, >+ AArch64_SQSHLv8i16 = 1578, >+ AArch64_SQSHLv8i16_shift = 1579, >+ AArch64_SQSHLv8i8 = 1580, >+ AArch64_SQSHLv8i8_shift = 1581, >+ AArch64_SQSHRNb = 1582, >+ AArch64_SQSHRNh = 1583, >+ AArch64_SQSHRNs = 1584, >+ AArch64_SQSHRNv16i8_shift = 1585, >+ AArch64_SQSHRNv2i32_shift = 1586, >+ AArch64_SQSHRNv4i16_shift = 1587, >+ AArch64_SQSHRNv4i32_shift = 1588, >+ AArch64_SQSHRNv8i16_shift = 1589, >+ AArch64_SQSHRNv8i8_shift = 1590, >+ AArch64_SQSHRUNb = 1591, >+ AArch64_SQSHRUNh = 1592, >+ AArch64_SQSHRUNs = 1593, >+ AArch64_SQSHRUNv16i8_shift = 1594, >+ AArch64_SQSHRUNv2i32_shift = 1595, >+ AArch64_SQSHRUNv4i16_shift = 1596, >+ AArch64_SQSHRUNv4i32_shift = 1597, >+ AArch64_SQSHRUNv8i16_shift = 1598, >+ AArch64_SQSHRUNv8i8_shift = 1599, >+ AArch64_SQSUBv16i8 = 1600, >+ AArch64_SQSUBv1i16 = 1601, >+ AArch64_SQSUBv1i32 = 1602, >+ AArch64_SQSUBv1i64 = 1603, >+ AArch64_SQSUBv1i8 = 1604, >+ AArch64_SQSUBv2i32 = 1605, >+ AArch64_SQSUBv2i64 = 1606, >+ AArch64_SQSUBv4i16 = 1607, >+ AArch64_SQSUBv4i32 = 1608, >+ AArch64_SQSUBv8i16 = 1609, >+ AArch64_SQSUBv8i8 = 1610, >+ AArch64_SQXTNv16i8 = 1611, >+ AArch64_SQXTNv1i16 = 1612, >+ AArch64_SQXTNv1i32 = 1613, >+ AArch64_SQXTNv1i8 = 1614, >+ AArch64_SQXTNv2i32 = 1615, >+ AArch64_SQXTNv4i16 = 1616, >+ AArch64_SQXTNv4i32 = 1617, >+ AArch64_SQXTNv8i16 = 1618, >+ AArch64_SQXTNv8i8 = 1619, >+ AArch64_SQXTUNv16i8 = 1620, >+ AArch64_SQXTUNv1i16 = 1621, >+ AArch64_SQXTUNv1i32 = 1622, >+ AArch64_SQXTUNv1i8 = 1623, >+ AArch64_SQXTUNv2i32 = 1624, >+ AArch64_SQXTUNv4i16 = 1625, >+ AArch64_SQXTUNv4i32 = 1626, >+ AArch64_SQXTUNv8i16 = 1627, >+ AArch64_SQXTUNv8i8 = 1628, >+ AArch64_SRHADDv16i8 = 1629, >+ AArch64_SRHADDv2i32 = 1630, >+ AArch64_SRHADDv4i16 = 1631, >+ AArch64_SRHADDv4i32 = 1632, >+ AArch64_SRHADDv8i16 = 1633, >+ AArch64_SRHADDv8i8 = 1634, >+ AArch64_SRId = 1635, >+ AArch64_SRIv16i8_shift = 1636, >+ AArch64_SRIv2i32_shift = 1637, >+ AArch64_SRIv2i64_shift = 1638, >+ AArch64_SRIv4i16_shift = 1639, >+ AArch64_SRIv4i32_shift = 1640, >+ AArch64_SRIv8i16_shift = 1641, >+ AArch64_SRIv8i8_shift = 1642, >+ AArch64_SRSHLv16i8 = 1643, >+ AArch64_SRSHLv1i64 = 1644, >+ AArch64_SRSHLv2i32 = 1645, >+ AArch64_SRSHLv2i64 = 1646, >+ AArch64_SRSHLv4i16 = 1647, >+ AArch64_SRSHLv4i32 = 1648, >+ AArch64_SRSHLv8i16 = 1649, >+ AArch64_SRSHLv8i8 = 1650, >+ AArch64_SRSHRd = 1651, >+ AArch64_SRSHRv16i8_shift = 1652, >+ AArch64_SRSHRv2i32_shift = 1653, >+ AArch64_SRSHRv2i64_shift = 1654, >+ AArch64_SRSHRv4i16_shift = 1655, >+ AArch64_SRSHRv4i32_shift = 1656, >+ AArch64_SRSHRv8i16_shift = 1657, >+ AArch64_SRSHRv8i8_shift = 1658, >+ AArch64_SRSRAd = 1659, >+ AArch64_SRSRAv16i8_shift = 1660, >+ AArch64_SRSRAv2i32_shift = 1661, >+ AArch64_SRSRAv2i64_shift = 1662, >+ AArch64_SRSRAv4i16_shift = 1663, >+ AArch64_SRSRAv4i32_shift = 1664, >+ AArch64_SRSRAv8i16_shift = 1665, >+ AArch64_SRSRAv8i8_shift = 1666, >+ AArch64_SSHLLv16i8_shift = 1667, >+ AArch64_SSHLLv2i32_shift = 1668, >+ AArch64_SSHLLv4i16_shift = 1669, >+ AArch64_SSHLLv4i32_shift = 1670, >+ AArch64_SSHLLv8i16_shift = 1671, >+ AArch64_SSHLLv8i8_shift = 1672, >+ AArch64_SSHLv16i8 = 1673, >+ AArch64_SSHLv1i64 = 1674, >+ AArch64_SSHLv2i32 = 1675, >+ AArch64_SSHLv2i64 = 1676, >+ AArch64_SSHLv4i16 = 1677, >+ AArch64_SSHLv4i32 = 1678, >+ AArch64_SSHLv8i16 = 1679, >+ AArch64_SSHLv8i8 = 1680, >+ AArch64_SSHRd = 1681, >+ AArch64_SSHRv16i8_shift = 1682, >+ AArch64_SSHRv2i32_shift = 1683, >+ AArch64_SSHRv2i64_shift = 1684, >+ AArch64_SSHRv4i16_shift = 1685, >+ AArch64_SSHRv4i32_shift = 1686, >+ AArch64_SSHRv8i16_shift = 1687, >+ AArch64_SSHRv8i8_shift = 1688, >+ AArch64_SSRAd = 1689, >+ AArch64_SSRAv16i8_shift = 1690, >+ AArch64_SSRAv2i32_shift = 1691, >+ AArch64_SSRAv2i64_shift = 1692, >+ AArch64_SSRAv4i16_shift = 1693, >+ AArch64_SSRAv4i32_shift = 1694, >+ AArch64_SSRAv8i16_shift = 1695, >+ AArch64_SSRAv8i8_shift = 1696, >+ AArch64_SSUBLv16i8_v8i16 = 1697, >+ AArch64_SSUBLv2i32_v2i64 = 1698, >+ AArch64_SSUBLv4i16_v4i32 = 1699, >+ AArch64_SSUBLv4i32_v2i64 = 1700, >+ AArch64_SSUBLv8i16_v4i32 = 1701, >+ AArch64_SSUBLv8i8_v8i16 = 1702, >+ AArch64_SSUBWv16i8_v8i16 = 1703, >+ AArch64_SSUBWv2i32_v2i64 = 1704, >+ AArch64_SSUBWv4i16_v4i32 = 1705, >+ AArch64_SSUBWv4i32_v2i64 = 1706, >+ AArch64_SSUBWv8i16_v4i32 = 1707, >+ AArch64_SSUBWv8i8_v8i16 = 1708, >+ AArch64_ST1Fourv16b = 1709, >+ AArch64_ST1Fourv16b_POST = 1710, >+ AArch64_ST1Fourv1d = 1711, >+ AArch64_ST1Fourv1d_POST = 1712, >+ AArch64_ST1Fourv2d = 1713, >+ AArch64_ST1Fourv2d_POST = 1714, >+ AArch64_ST1Fourv2s = 1715, >+ AArch64_ST1Fourv2s_POST = 1716, >+ AArch64_ST1Fourv4h = 1717, >+ AArch64_ST1Fourv4h_POST = 1718, >+ AArch64_ST1Fourv4s = 1719, >+ AArch64_ST1Fourv4s_POST = 1720, >+ AArch64_ST1Fourv8b = 1721, >+ AArch64_ST1Fourv8b_POST = 1722, >+ AArch64_ST1Fourv8h = 1723, >+ AArch64_ST1Fourv8h_POST = 1724, >+ AArch64_ST1Onev16b = 1725, >+ AArch64_ST1Onev16b_POST = 1726, >+ AArch64_ST1Onev1d = 1727, >+ AArch64_ST1Onev1d_POST = 1728, >+ AArch64_ST1Onev2d = 1729, >+ AArch64_ST1Onev2d_POST = 1730, >+ AArch64_ST1Onev2s = 1731, >+ AArch64_ST1Onev2s_POST = 1732, >+ AArch64_ST1Onev4h = 1733, >+ AArch64_ST1Onev4h_POST = 1734, >+ AArch64_ST1Onev4s = 1735, >+ AArch64_ST1Onev4s_POST = 1736, >+ AArch64_ST1Onev8b = 1737, >+ AArch64_ST1Onev8b_POST = 1738, >+ AArch64_ST1Onev8h = 1739, >+ AArch64_ST1Onev8h_POST = 1740, >+ AArch64_ST1Threev16b = 1741, >+ AArch64_ST1Threev16b_POST = 1742, >+ AArch64_ST1Threev1d = 1743, >+ AArch64_ST1Threev1d_POST = 1744, >+ AArch64_ST1Threev2d = 1745, >+ AArch64_ST1Threev2d_POST = 1746, >+ AArch64_ST1Threev2s = 1747, >+ AArch64_ST1Threev2s_POST = 1748, >+ AArch64_ST1Threev4h = 1749, >+ AArch64_ST1Threev4h_POST = 1750, >+ AArch64_ST1Threev4s = 1751, >+ AArch64_ST1Threev4s_POST = 1752, >+ AArch64_ST1Threev8b = 1753, >+ AArch64_ST1Threev8b_POST = 1754, >+ AArch64_ST1Threev8h = 1755, >+ AArch64_ST1Threev8h_POST = 1756, >+ AArch64_ST1Twov16b = 1757, >+ AArch64_ST1Twov16b_POST = 1758, >+ AArch64_ST1Twov1d = 1759, >+ AArch64_ST1Twov1d_POST = 1760, >+ AArch64_ST1Twov2d = 1761, >+ AArch64_ST1Twov2d_POST = 1762, >+ AArch64_ST1Twov2s = 1763, >+ AArch64_ST1Twov2s_POST = 1764, >+ AArch64_ST1Twov4h = 1765, >+ AArch64_ST1Twov4h_POST = 1766, >+ AArch64_ST1Twov4s = 1767, >+ AArch64_ST1Twov4s_POST = 1768, >+ AArch64_ST1Twov8b = 1769, >+ AArch64_ST1Twov8b_POST = 1770, >+ AArch64_ST1Twov8h = 1771, >+ AArch64_ST1Twov8h_POST = 1772, >+ AArch64_ST1i16 = 1773, >+ AArch64_ST1i16_POST = 1774, >+ AArch64_ST1i32 = 1775, >+ AArch64_ST1i32_POST = 1776, >+ AArch64_ST1i64 = 1777, >+ AArch64_ST1i64_POST = 1778, >+ AArch64_ST1i8 = 1779, >+ AArch64_ST1i8_POST = 1780, >+ AArch64_ST2Twov16b = 1781, >+ AArch64_ST2Twov16b_POST = 1782, >+ AArch64_ST2Twov2d = 1783, >+ AArch64_ST2Twov2d_POST = 1784, >+ AArch64_ST2Twov2s = 1785, >+ AArch64_ST2Twov2s_POST = 1786, >+ AArch64_ST2Twov4h = 1787, >+ AArch64_ST2Twov4h_POST = 1788, >+ AArch64_ST2Twov4s = 1789, >+ AArch64_ST2Twov4s_POST = 1790, >+ AArch64_ST2Twov8b = 1791, >+ AArch64_ST2Twov8b_POST = 1792, >+ AArch64_ST2Twov8h = 1793, >+ AArch64_ST2Twov8h_POST = 1794, >+ AArch64_ST2i16 = 1795, >+ AArch64_ST2i16_POST = 1796, >+ AArch64_ST2i32 = 1797, >+ AArch64_ST2i32_POST = 1798, >+ AArch64_ST2i64 = 1799, >+ AArch64_ST2i64_POST = 1800, >+ AArch64_ST2i8 = 1801, >+ AArch64_ST2i8_POST = 1802, >+ AArch64_ST3Threev16b = 1803, >+ AArch64_ST3Threev16b_POST = 1804, >+ AArch64_ST3Threev2d = 1805, >+ AArch64_ST3Threev2d_POST = 1806, >+ AArch64_ST3Threev2s = 1807, >+ AArch64_ST3Threev2s_POST = 1808, >+ AArch64_ST3Threev4h = 1809, >+ AArch64_ST3Threev4h_POST = 1810, >+ AArch64_ST3Threev4s = 1811, >+ AArch64_ST3Threev4s_POST = 1812, >+ AArch64_ST3Threev8b = 1813, >+ AArch64_ST3Threev8b_POST = 1814, >+ AArch64_ST3Threev8h = 1815, >+ AArch64_ST3Threev8h_POST = 1816, >+ AArch64_ST3i16 = 1817, >+ AArch64_ST3i16_POST = 1818, >+ AArch64_ST3i32 = 1819, >+ AArch64_ST3i32_POST = 1820, >+ AArch64_ST3i64 = 1821, >+ AArch64_ST3i64_POST = 1822, >+ AArch64_ST3i8 = 1823, >+ AArch64_ST3i8_POST = 1824, >+ AArch64_ST4Fourv16b = 1825, >+ AArch64_ST4Fourv16b_POST = 1826, >+ AArch64_ST4Fourv2d = 1827, >+ AArch64_ST4Fourv2d_POST = 1828, >+ AArch64_ST4Fourv2s = 1829, >+ AArch64_ST4Fourv2s_POST = 1830, >+ AArch64_ST4Fourv4h = 1831, >+ AArch64_ST4Fourv4h_POST = 1832, >+ AArch64_ST4Fourv4s = 1833, >+ AArch64_ST4Fourv4s_POST = 1834, >+ AArch64_ST4Fourv8b = 1835, >+ AArch64_ST4Fourv8b_POST = 1836, >+ AArch64_ST4Fourv8h = 1837, >+ AArch64_ST4Fourv8h_POST = 1838, >+ AArch64_ST4i16 = 1839, >+ AArch64_ST4i16_POST = 1840, >+ AArch64_ST4i32 = 1841, >+ AArch64_ST4i32_POST = 1842, >+ AArch64_ST4i64 = 1843, >+ AArch64_ST4i64_POST = 1844, >+ AArch64_ST4i8 = 1845, >+ AArch64_ST4i8_POST = 1846, >+ AArch64_STLRB = 1847, >+ AArch64_STLRH = 1848, >+ AArch64_STLRW = 1849, >+ AArch64_STLRX = 1850, >+ AArch64_STLXPW = 1851, >+ AArch64_STLXPX = 1852, >+ AArch64_STLXRB = 1853, >+ AArch64_STLXRH = 1854, >+ AArch64_STLXRW = 1855, >+ AArch64_STLXRX = 1856, >+ AArch64_STNPDi = 1857, >+ AArch64_STNPQi = 1858, >+ AArch64_STNPSi = 1859, >+ AArch64_STNPWi = 1860, >+ AArch64_STNPXi = 1861, >+ AArch64_STPDi = 1862, >+ AArch64_STPDpost = 1863, >+ AArch64_STPDpre = 1864, >+ AArch64_STPQi = 1865, >+ AArch64_STPQpost = 1866, >+ AArch64_STPQpre = 1867, >+ AArch64_STPSi = 1868, >+ AArch64_STPSpost = 1869, >+ AArch64_STPSpre = 1870, >+ AArch64_STPWi = 1871, >+ AArch64_STPWpost = 1872, >+ AArch64_STPWpre = 1873, >+ AArch64_STPXi = 1874, >+ AArch64_STPXpost = 1875, >+ AArch64_STPXpre = 1876, >+ AArch64_STRBBpost = 1877, >+ AArch64_STRBBpre = 1878, >+ AArch64_STRBBroW = 1879, >+ AArch64_STRBBroX = 1880, >+ AArch64_STRBBui = 1881, >+ AArch64_STRBpost = 1882, >+ AArch64_STRBpre = 1883, >+ AArch64_STRBroW = 1884, >+ AArch64_STRBroX = 1885, >+ AArch64_STRBui = 1886, >+ AArch64_STRDpost = 1887, >+ AArch64_STRDpre = 1888, >+ AArch64_STRDroW = 1889, >+ AArch64_STRDroX = 1890, >+ AArch64_STRDui = 1891, >+ AArch64_STRHHpost = 1892, >+ AArch64_STRHHpre = 1893, >+ AArch64_STRHHroW = 1894, >+ AArch64_STRHHroX = 1895, >+ AArch64_STRHHui = 1896, >+ AArch64_STRHpost = 1897, >+ AArch64_STRHpre = 1898, >+ AArch64_STRHroW = 1899, >+ AArch64_STRHroX = 1900, >+ AArch64_STRHui = 1901, >+ AArch64_STRQpost = 1902, >+ AArch64_STRQpre = 1903, >+ AArch64_STRQroW = 1904, >+ AArch64_STRQroX = 1905, >+ AArch64_STRQui = 1906, >+ AArch64_STRSpost = 1907, >+ AArch64_STRSpre = 1908, >+ AArch64_STRSroW = 1909, >+ AArch64_STRSroX = 1910, >+ AArch64_STRSui = 1911, >+ AArch64_STRWpost = 1912, >+ AArch64_STRWpre = 1913, >+ AArch64_STRWroW = 1914, >+ AArch64_STRWroX = 1915, >+ AArch64_STRWui = 1916, >+ AArch64_STRXpost = 1917, >+ AArch64_STRXpre = 1918, >+ AArch64_STRXroW = 1919, >+ AArch64_STRXroX = 1920, >+ AArch64_STRXui = 1921, >+ AArch64_STTRBi = 1922, >+ AArch64_STTRHi = 1923, >+ AArch64_STTRWi = 1924, >+ AArch64_STTRXi = 1925, >+ AArch64_STURBBi = 1926, >+ AArch64_STURBi = 1927, >+ AArch64_STURDi = 1928, >+ AArch64_STURHHi = 1929, >+ AArch64_STURHi = 1930, >+ AArch64_STURQi = 1931, >+ AArch64_STURSi = 1932, >+ AArch64_STURWi = 1933, >+ AArch64_STURXi = 1934, >+ AArch64_STXPW = 1935, >+ AArch64_STXPX = 1936, >+ AArch64_STXRB = 1937, >+ AArch64_STXRH = 1938, >+ AArch64_STXRW = 1939, >+ AArch64_STXRX = 1940, >+ AArch64_SUBHNv2i64_v2i32 = 1941, >+ AArch64_SUBHNv2i64_v4i32 = 1942, >+ AArch64_SUBHNv4i32_v4i16 = 1943, >+ AArch64_SUBHNv4i32_v8i16 = 1944, >+ AArch64_SUBHNv8i16_v16i8 = 1945, >+ AArch64_SUBHNv8i16_v8i8 = 1946, >+ AArch64_SUBSWri = 1947, >+ AArch64_SUBSWrr = 1948, >+ AArch64_SUBSWrs = 1949, >+ AArch64_SUBSWrx = 1950, >+ AArch64_SUBSXri = 1951, >+ AArch64_SUBSXrr = 1952, >+ AArch64_SUBSXrs = 1953, >+ AArch64_SUBSXrx = 1954, >+ AArch64_SUBSXrx64 = 1955, >+ AArch64_SUBWri = 1956, >+ AArch64_SUBWrr = 1957, >+ AArch64_SUBWrs = 1958, >+ AArch64_SUBWrx = 1959, >+ AArch64_SUBXri = 1960, >+ AArch64_SUBXrr = 1961, >+ AArch64_SUBXrs = 1962, >+ AArch64_SUBXrx = 1963, >+ AArch64_SUBXrx64 = 1964, >+ AArch64_SUBv16i8 = 1965, >+ AArch64_SUBv1i64 = 1966, >+ AArch64_SUBv2i32 = 1967, >+ AArch64_SUBv2i64 = 1968, >+ AArch64_SUBv4i16 = 1969, >+ AArch64_SUBv4i32 = 1970, >+ AArch64_SUBv8i16 = 1971, >+ AArch64_SUBv8i8 = 1972, >+ AArch64_SUQADDv16i8 = 1973, >+ AArch64_SUQADDv1i16 = 1974, >+ AArch64_SUQADDv1i32 = 1975, >+ AArch64_SUQADDv1i64 = 1976, >+ AArch64_SUQADDv1i8 = 1977, >+ AArch64_SUQADDv2i32 = 1978, >+ AArch64_SUQADDv2i64 = 1979, >+ AArch64_SUQADDv4i16 = 1980, >+ AArch64_SUQADDv4i32 = 1981, >+ AArch64_SUQADDv8i16 = 1982, >+ AArch64_SUQADDv8i8 = 1983, >+ AArch64_SVC = 1984, >+ AArch64_SYSLxt = 1985, >+ AArch64_SYSxt = 1986, >+ AArch64_TBLv16i8Four = 1987, >+ AArch64_TBLv16i8One = 1988, >+ AArch64_TBLv16i8Three = 1989, >+ AArch64_TBLv16i8Two = 1990, >+ AArch64_TBLv8i8Four = 1991, >+ AArch64_TBLv8i8One = 1992, >+ AArch64_TBLv8i8Three = 1993, >+ AArch64_TBLv8i8Two = 1994, >+ AArch64_TBNZW = 1995, >+ AArch64_TBNZX = 1996, >+ AArch64_TBXv16i8Four = 1997, >+ AArch64_TBXv16i8One = 1998, >+ AArch64_TBXv16i8Three = 1999, >+ AArch64_TBXv16i8Two = 2000, >+ AArch64_TBXv8i8Four = 2001, >+ AArch64_TBXv8i8One = 2002, >+ AArch64_TBXv8i8Three = 2003, >+ AArch64_TBXv8i8Two = 2004, >+ AArch64_TBZW = 2005, >+ AArch64_TBZX = 2006, >+ AArch64_TCRETURNdi = 2007, >+ AArch64_TCRETURNri = 2008, >+ AArch64_TLSDESCCALL = 2009, >+ AArch64_TLSDESC_BLR = 2010, >+ AArch64_TRN1v16i8 = 2011, >+ AArch64_TRN1v2i32 = 2012, >+ AArch64_TRN1v2i64 = 2013, >+ AArch64_TRN1v4i16 = 2014, >+ AArch64_TRN1v4i32 = 2015, >+ AArch64_TRN1v8i16 = 2016, >+ AArch64_TRN1v8i8 = 2017, >+ AArch64_TRN2v16i8 = 2018, >+ AArch64_TRN2v2i32 = 2019, >+ AArch64_TRN2v2i64 = 2020, >+ AArch64_TRN2v4i16 = 2021, >+ AArch64_TRN2v4i32 = 2022, >+ AArch64_TRN2v8i16 = 2023, >+ AArch64_TRN2v8i8 = 2024, >+ AArch64_UABALv16i8_v8i16 = 2025, >+ AArch64_UABALv2i32_v2i64 = 2026, >+ AArch64_UABALv4i16_v4i32 = 2027, >+ AArch64_UABALv4i32_v2i64 = 2028, >+ AArch64_UABALv8i16_v4i32 = 2029, >+ AArch64_UABALv8i8_v8i16 = 2030, >+ AArch64_UABAv16i8 = 2031, >+ AArch64_UABAv2i32 = 2032, >+ AArch64_UABAv4i16 = 2033, >+ AArch64_UABAv4i32 = 2034, >+ AArch64_UABAv8i16 = 2035, >+ AArch64_UABAv8i8 = 2036, >+ AArch64_UABDLv16i8_v8i16 = 2037, >+ AArch64_UABDLv2i32_v2i64 = 2038, >+ AArch64_UABDLv4i16_v4i32 = 2039, >+ AArch64_UABDLv4i32_v2i64 = 2040, >+ AArch64_UABDLv8i16_v4i32 = 2041, >+ AArch64_UABDLv8i8_v8i16 = 2042, >+ AArch64_UABDv16i8 = 2043, >+ AArch64_UABDv2i32 = 2044, >+ AArch64_UABDv4i16 = 2045, >+ AArch64_UABDv4i32 = 2046, >+ AArch64_UABDv8i16 = 2047, >+ AArch64_UABDv8i8 = 2048, >+ AArch64_UADALPv16i8_v8i16 = 2049, >+ AArch64_UADALPv2i32_v1i64 = 2050, >+ AArch64_UADALPv4i16_v2i32 = 2051, >+ AArch64_UADALPv4i32_v2i64 = 2052, >+ AArch64_UADALPv8i16_v4i32 = 2053, >+ AArch64_UADALPv8i8_v4i16 = 2054, >+ AArch64_UADDLPv16i8_v8i16 = 2055, >+ AArch64_UADDLPv2i32_v1i64 = 2056, >+ AArch64_UADDLPv4i16_v2i32 = 2057, >+ AArch64_UADDLPv4i32_v2i64 = 2058, >+ AArch64_UADDLPv8i16_v4i32 = 2059, >+ AArch64_UADDLPv8i8_v4i16 = 2060, >+ AArch64_UADDLVv16i8v = 2061, >+ AArch64_UADDLVv4i16v = 2062, >+ AArch64_UADDLVv4i32v = 2063, >+ AArch64_UADDLVv8i16v = 2064, >+ AArch64_UADDLVv8i8v = 2065, >+ AArch64_UADDLv16i8_v8i16 = 2066, >+ AArch64_UADDLv2i32_v2i64 = 2067, >+ AArch64_UADDLv4i16_v4i32 = 2068, >+ AArch64_UADDLv4i32_v2i64 = 2069, >+ AArch64_UADDLv8i16_v4i32 = 2070, >+ AArch64_UADDLv8i8_v8i16 = 2071, >+ AArch64_UADDWv16i8_v8i16 = 2072, >+ AArch64_UADDWv2i32_v2i64 = 2073, >+ AArch64_UADDWv4i16_v4i32 = 2074, >+ AArch64_UADDWv4i32_v2i64 = 2075, >+ AArch64_UADDWv8i16_v4i32 = 2076, >+ AArch64_UADDWv8i8_v8i16 = 2077, >+ AArch64_UBFMWri = 2078, >+ AArch64_UBFMXri = 2079, >+ AArch64_UCVTFSWDri = 2080, >+ AArch64_UCVTFSWSri = 2081, >+ AArch64_UCVTFSXDri = 2082, >+ AArch64_UCVTFSXSri = 2083, >+ AArch64_UCVTFUWDri = 2084, >+ AArch64_UCVTFUWSri = 2085, >+ AArch64_UCVTFUXDri = 2086, >+ AArch64_UCVTFUXSri = 2087, >+ AArch64_UCVTFd = 2088, >+ AArch64_UCVTFs = 2089, >+ AArch64_UCVTFv1i32 = 2090, >+ AArch64_UCVTFv1i64 = 2091, >+ AArch64_UCVTFv2f32 = 2092, >+ AArch64_UCVTFv2f64 = 2093, >+ AArch64_UCVTFv2i32_shift = 2094, >+ AArch64_UCVTFv2i64_shift = 2095, >+ AArch64_UCVTFv4f32 = 2096, >+ AArch64_UCVTFv4i32_shift = 2097, >+ AArch64_UDIVWr = 2098, >+ AArch64_UDIVXr = 2099, >+ AArch64_UDIV_IntWr = 2100, >+ AArch64_UDIV_IntXr = 2101, >+ AArch64_UHADDv16i8 = 2102, >+ AArch64_UHADDv2i32 = 2103, >+ AArch64_UHADDv4i16 = 2104, >+ AArch64_UHADDv4i32 = 2105, >+ AArch64_UHADDv8i16 = 2106, >+ AArch64_UHADDv8i8 = 2107, >+ AArch64_UHSUBv16i8 = 2108, >+ AArch64_UHSUBv2i32 = 2109, >+ AArch64_UHSUBv4i16 = 2110, >+ AArch64_UHSUBv4i32 = 2111, >+ AArch64_UHSUBv8i16 = 2112, >+ AArch64_UHSUBv8i8 = 2113, >+ AArch64_UMADDLrrr = 2114, >+ AArch64_UMAXPv16i8 = 2115, >+ AArch64_UMAXPv2i32 = 2116, >+ AArch64_UMAXPv4i16 = 2117, >+ AArch64_UMAXPv4i32 = 2118, >+ AArch64_UMAXPv8i16 = 2119, >+ AArch64_UMAXPv8i8 = 2120, >+ AArch64_UMAXVv16i8v = 2121, >+ AArch64_UMAXVv4i16v = 2122, >+ AArch64_UMAXVv4i32v = 2123, >+ AArch64_UMAXVv8i16v = 2124, >+ AArch64_UMAXVv8i8v = 2125, >+ AArch64_UMAXv16i8 = 2126, >+ AArch64_UMAXv2i32 = 2127, >+ AArch64_UMAXv4i16 = 2128, >+ AArch64_UMAXv4i32 = 2129, >+ AArch64_UMAXv8i16 = 2130, >+ AArch64_UMAXv8i8 = 2131, >+ AArch64_UMINPv16i8 = 2132, >+ AArch64_UMINPv2i32 = 2133, >+ AArch64_UMINPv4i16 = 2134, >+ AArch64_UMINPv4i32 = 2135, >+ AArch64_UMINPv8i16 = 2136, >+ AArch64_UMINPv8i8 = 2137, >+ AArch64_UMINVv16i8v = 2138, >+ AArch64_UMINVv4i16v = 2139, >+ AArch64_UMINVv4i32v = 2140, >+ AArch64_UMINVv8i16v = 2141, >+ AArch64_UMINVv8i8v = 2142, >+ AArch64_UMINv16i8 = 2143, >+ AArch64_UMINv2i32 = 2144, >+ AArch64_UMINv4i16 = 2145, >+ AArch64_UMINv4i32 = 2146, >+ AArch64_UMINv8i16 = 2147, >+ AArch64_UMINv8i8 = 2148, >+ AArch64_UMLALv16i8_v8i16 = 2149, >+ AArch64_UMLALv2i32_indexed = 2150, >+ AArch64_UMLALv2i32_v2i64 = 2151, >+ AArch64_UMLALv4i16_indexed = 2152, >+ AArch64_UMLALv4i16_v4i32 = 2153, >+ AArch64_UMLALv4i32_indexed = 2154, >+ AArch64_UMLALv4i32_v2i64 = 2155, >+ AArch64_UMLALv8i16_indexed = 2156, >+ AArch64_UMLALv8i16_v4i32 = 2157, >+ AArch64_UMLALv8i8_v8i16 = 2158, >+ AArch64_UMLSLv16i8_v8i16 = 2159, >+ AArch64_UMLSLv2i32_indexed = 2160, >+ AArch64_UMLSLv2i32_v2i64 = 2161, >+ AArch64_UMLSLv4i16_indexed = 2162, >+ AArch64_UMLSLv4i16_v4i32 = 2163, >+ AArch64_UMLSLv4i32_indexed = 2164, >+ AArch64_UMLSLv4i32_v2i64 = 2165, >+ AArch64_UMLSLv8i16_indexed = 2166, >+ AArch64_UMLSLv8i16_v4i32 = 2167, >+ AArch64_UMLSLv8i8_v8i16 = 2168, >+ AArch64_UMOVvi16 = 2169, >+ AArch64_UMOVvi32 = 2170, >+ AArch64_UMOVvi64 = 2171, >+ AArch64_UMOVvi8 = 2172, >+ AArch64_UMSUBLrrr = 2173, >+ AArch64_UMULHrr = 2174, >+ AArch64_UMULLv16i8_v8i16 = 2175, >+ AArch64_UMULLv2i32_indexed = 2176, >+ AArch64_UMULLv2i32_v2i64 = 2177, >+ AArch64_UMULLv4i16_indexed = 2178, >+ AArch64_UMULLv4i16_v4i32 = 2179, >+ AArch64_UMULLv4i32_indexed = 2180, >+ AArch64_UMULLv4i32_v2i64 = 2181, >+ AArch64_UMULLv8i16_indexed = 2182, >+ AArch64_UMULLv8i16_v4i32 = 2183, >+ AArch64_UMULLv8i8_v8i16 = 2184, >+ AArch64_UQADDv16i8 = 2185, >+ AArch64_UQADDv1i16 = 2186, >+ AArch64_UQADDv1i32 = 2187, >+ AArch64_UQADDv1i64 = 2188, >+ AArch64_UQADDv1i8 = 2189, >+ AArch64_UQADDv2i32 = 2190, >+ AArch64_UQADDv2i64 = 2191, >+ AArch64_UQADDv4i16 = 2192, >+ AArch64_UQADDv4i32 = 2193, >+ AArch64_UQADDv8i16 = 2194, >+ AArch64_UQADDv8i8 = 2195, >+ AArch64_UQRSHLv16i8 = 2196, >+ AArch64_UQRSHLv1i16 = 2197, >+ AArch64_UQRSHLv1i32 = 2198, >+ AArch64_UQRSHLv1i64 = 2199, >+ AArch64_UQRSHLv1i8 = 2200, >+ AArch64_UQRSHLv2i32 = 2201, >+ AArch64_UQRSHLv2i64 = 2202, >+ AArch64_UQRSHLv4i16 = 2203, >+ AArch64_UQRSHLv4i32 = 2204, >+ AArch64_UQRSHLv8i16 = 2205, >+ AArch64_UQRSHLv8i8 = 2206, >+ AArch64_UQRSHRNb = 2207, >+ AArch64_UQRSHRNh = 2208, >+ AArch64_UQRSHRNs = 2209, >+ AArch64_UQRSHRNv16i8_shift = 2210, >+ AArch64_UQRSHRNv2i32_shift = 2211, >+ AArch64_UQRSHRNv4i16_shift = 2212, >+ AArch64_UQRSHRNv4i32_shift = 2213, >+ AArch64_UQRSHRNv8i16_shift = 2214, >+ AArch64_UQRSHRNv8i8_shift = 2215, >+ AArch64_UQSHLb = 2216, >+ AArch64_UQSHLd = 2217, >+ AArch64_UQSHLh = 2218, >+ AArch64_UQSHLs = 2219, >+ AArch64_UQSHLv16i8 = 2220, >+ AArch64_UQSHLv16i8_shift = 2221, >+ AArch64_UQSHLv1i16 = 2222, >+ AArch64_UQSHLv1i32 = 2223, >+ AArch64_UQSHLv1i64 = 2224, >+ AArch64_UQSHLv1i8 = 2225, >+ AArch64_UQSHLv2i32 = 2226, >+ AArch64_UQSHLv2i32_shift = 2227, >+ AArch64_UQSHLv2i64 = 2228, >+ AArch64_UQSHLv2i64_shift = 2229, >+ AArch64_UQSHLv4i16 = 2230, >+ AArch64_UQSHLv4i16_shift = 2231, >+ AArch64_UQSHLv4i32 = 2232, >+ AArch64_UQSHLv4i32_shift = 2233, >+ AArch64_UQSHLv8i16 = 2234, >+ AArch64_UQSHLv8i16_shift = 2235, >+ AArch64_UQSHLv8i8 = 2236, >+ AArch64_UQSHLv8i8_shift = 2237, >+ AArch64_UQSHRNb = 2238, >+ AArch64_UQSHRNh = 2239, >+ AArch64_UQSHRNs = 2240, >+ AArch64_UQSHRNv16i8_shift = 2241, >+ AArch64_UQSHRNv2i32_shift = 2242, >+ AArch64_UQSHRNv4i16_shift = 2243, >+ AArch64_UQSHRNv4i32_shift = 2244, >+ AArch64_UQSHRNv8i16_shift = 2245, >+ AArch64_UQSHRNv8i8_shift = 2246, >+ AArch64_UQSUBv16i8 = 2247, >+ AArch64_UQSUBv1i16 = 2248, >+ AArch64_UQSUBv1i32 = 2249, >+ AArch64_UQSUBv1i64 = 2250, >+ AArch64_UQSUBv1i8 = 2251, >+ AArch64_UQSUBv2i32 = 2252, >+ AArch64_UQSUBv2i64 = 2253, >+ AArch64_UQSUBv4i16 = 2254, >+ AArch64_UQSUBv4i32 = 2255, >+ AArch64_UQSUBv8i16 = 2256, >+ AArch64_UQSUBv8i8 = 2257, >+ AArch64_UQXTNv16i8 = 2258, >+ AArch64_UQXTNv1i16 = 2259, >+ AArch64_UQXTNv1i32 = 2260, >+ AArch64_UQXTNv1i8 = 2261, >+ AArch64_UQXTNv2i32 = 2262, >+ AArch64_UQXTNv4i16 = 2263, >+ AArch64_UQXTNv4i32 = 2264, >+ AArch64_UQXTNv8i16 = 2265, >+ AArch64_UQXTNv8i8 = 2266, >+ AArch64_URECPEv2i32 = 2267, >+ AArch64_URECPEv4i32 = 2268, >+ AArch64_URHADDv16i8 = 2269, >+ AArch64_URHADDv2i32 = 2270, >+ AArch64_URHADDv4i16 = 2271, >+ AArch64_URHADDv4i32 = 2272, >+ AArch64_URHADDv8i16 = 2273, >+ AArch64_URHADDv8i8 = 2274, >+ AArch64_URSHLv16i8 = 2275, >+ AArch64_URSHLv1i64 = 2276, >+ AArch64_URSHLv2i32 = 2277, >+ AArch64_URSHLv2i64 = 2278, >+ AArch64_URSHLv4i16 = 2279, >+ AArch64_URSHLv4i32 = 2280, >+ AArch64_URSHLv8i16 = 2281, >+ AArch64_URSHLv8i8 = 2282, >+ AArch64_URSHRd = 2283, >+ AArch64_URSHRv16i8_shift = 2284, >+ AArch64_URSHRv2i32_shift = 2285, >+ AArch64_URSHRv2i64_shift = 2286, >+ AArch64_URSHRv4i16_shift = 2287, >+ AArch64_URSHRv4i32_shift = 2288, >+ AArch64_URSHRv8i16_shift = 2289, >+ AArch64_URSHRv8i8_shift = 2290, >+ AArch64_URSQRTEv2i32 = 2291, >+ AArch64_URSQRTEv4i32 = 2292, >+ AArch64_URSRAd = 2293, >+ AArch64_URSRAv16i8_shift = 2294, >+ AArch64_URSRAv2i32_shift = 2295, >+ AArch64_URSRAv2i64_shift = 2296, >+ AArch64_URSRAv4i16_shift = 2297, >+ AArch64_URSRAv4i32_shift = 2298, >+ AArch64_URSRAv8i16_shift = 2299, >+ AArch64_URSRAv8i8_shift = 2300, >+ AArch64_USHLLv16i8_shift = 2301, >+ AArch64_USHLLv2i32_shift = 2302, >+ AArch64_USHLLv4i16_shift = 2303, >+ AArch64_USHLLv4i32_shift = 2304, >+ AArch64_USHLLv8i16_shift = 2305, >+ AArch64_USHLLv8i8_shift = 2306, >+ AArch64_USHLv16i8 = 2307, >+ AArch64_USHLv1i64 = 2308, >+ AArch64_USHLv2i32 = 2309, >+ AArch64_USHLv2i64 = 2310, >+ AArch64_USHLv4i16 = 2311, >+ AArch64_USHLv4i32 = 2312, >+ AArch64_USHLv8i16 = 2313, >+ AArch64_USHLv8i8 = 2314, >+ AArch64_USHRd = 2315, >+ AArch64_USHRv16i8_shift = 2316, >+ AArch64_USHRv2i32_shift = 2317, >+ AArch64_USHRv2i64_shift = 2318, >+ AArch64_USHRv4i16_shift = 2319, >+ AArch64_USHRv4i32_shift = 2320, >+ AArch64_USHRv8i16_shift = 2321, >+ AArch64_USHRv8i8_shift = 2322, >+ AArch64_USQADDv16i8 = 2323, >+ AArch64_USQADDv1i16 = 2324, >+ AArch64_USQADDv1i32 = 2325, >+ AArch64_USQADDv1i64 = 2326, >+ AArch64_USQADDv1i8 = 2327, >+ AArch64_USQADDv2i32 = 2328, >+ AArch64_USQADDv2i64 = 2329, >+ AArch64_USQADDv4i16 = 2330, >+ AArch64_USQADDv4i32 = 2331, >+ AArch64_USQADDv8i16 = 2332, >+ AArch64_USQADDv8i8 = 2333, >+ AArch64_USRAd = 2334, >+ AArch64_USRAv16i8_shift = 2335, >+ AArch64_USRAv2i32_shift = 2336, >+ AArch64_USRAv2i64_shift = 2337, >+ AArch64_USRAv4i16_shift = 2338, >+ AArch64_USRAv4i32_shift = 2339, >+ AArch64_USRAv8i16_shift = 2340, >+ AArch64_USRAv8i8_shift = 2341, >+ AArch64_USUBLv16i8_v8i16 = 2342, >+ AArch64_USUBLv2i32_v2i64 = 2343, >+ AArch64_USUBLv4i16_v4i32 = 2344, >+ AArch64_USUBLv4i32_v2i64 = 2345, >+ AArch64_USUBLv8i16_v4i32 = 2346, >+ AArch64_USUBLv8i8_v8i16 = 2347, >+ AArch64_USUBWv16i8_v8i16 = 2348, >+ AArch64_USUBWv2i32_v2i64 = 2349, >+ AArch64_USUBWv4i16_v4i32 = 2350, >+ AArch64_USUBWv4i32_v2i64 = 2351, >+ AArch64_USUBWv8i16_v4i32 = 2352, >+ AArch64_USUBWv8i8_v8i16 = 2353, >+ AArch64_UZP1v16i8 = 2354, >+ AArch64_UZP1v2i32 = 2355, >+ AArch64_UZP1v2i64 = 2356, >+ AArch64_UZP1v4i16 = 2357, >+ AArch64_UZP1v4i32 = 2358, >+ AArch64_UZP1v8i16 = 2359, >+ AArch64_UZP1v8i8 = 2360, >+ AArch64_UZP2v16i8 = 2361, >+ AArch64_UZP2v2i32 = 2362, >+ AArch64_UZP2v2i64 = 2363, >+ AArch64_UZP2v4i16 = 2364, >+ AArch64_UZP2v4i32 = 2365, >+ AArch64_UZP2v8i16 = 2366, >+ AArch64_UZP2v8i8 = 2367, >+ AArch64_XTNv16i8 = 2368, >+ AArch64_XTNv2i32 = 2369, >+ AArch64_XTNv4i16 = 2370, >+ AArch64_XTNv4i32 = 2371, >+ AArch64_XTNv8i16 = 2372, >+ AArch64_XTNv8i8 = 2373, >+ AArch64_ZIP1v16i8 = 2374, >+ AArch64_ZIP1v2i32 = 2375, >+ AArch64_ZIP1v2i64 = 2376, >+ AArch64_ZIP1v4i16 = 2377, >+ AArch64_ZIP1v4i32 = 2378, >+ AArch64_ZIP1v8i16 = 2379, >+ AArch64_ZIP1v8i8 = 2380, >+ AArch64_ZIP2v16i8 = 2381, >+ AArch64_ZIP2v2i32 = 2382, >+ AArch64_ZIP2v2i64 = 2383, >+ AArch64_ZIP2v4i16 = 2384, >+ AArch64_ZIP2v4i32 = 2385, >+ AArch64_ZIP2v8i16 = 2386, >+ AArch64_ZIP2v8i8 = 2387, >+ AArch64_INSTRUCTION_LIST_END = 2388 >+}; >+ >+#endif // GET_INSTRINFO_ENUM >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenRegisterInfo.inc b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenRegisterInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..8e310f5656fab96b13dca800261d75d2daaf843e >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenRegisterInfo.inc >@@ -0,0 +1,1540 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Register Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_ENUM >+#undef GET_REGINFO_ENUM >+ >+enum { >+ AArch64_NoRegister, >+ AArch64_FP = 1, >+ AArch64_LR = 2, >+ AArch64_NZCV = 3, >+ AArch64_SP = 4, >+ AArch64_WSP = 5, >+ AArch64_WZR = 6, >+ AArch64_XZR = 7, >+ AArch64_B0 = 8, >+ AArch64_B1 = 9, >+ AArch64_B2 = 10, >+ AArch64_B3 = 11, >+ AArch64_B4 = 12, >+ AArch64_B5 = 13, >+ AArch64_B6 = 14, >+ AArch64_B7 = 15, >+ AArch64_B8 = 16, >+ AArch64_B9 = 17, >+ AArch64_B10 = 18, >+ AArch64_B11 = 19, >+ AArch64_B12 = 20, >+ AArch64_B13 = 21, >+ AArch64_B14 = 22, >+ AArch64_B15 = 23, >+ AArch64_B16 = 24, >+ AArch64_B17 = 25, >+ AArch64_B18 = 26, >+ AArch64_B19 = 27, >+ AArch64_B20 = 28, >+ AArch64_B21 = 29, >+ AArch64_B22 = 30, >+ AArch64_B23 = 31, >+ AArch64_B24 = 32, >+ AArch64_B25 = 33, >+ AArch64_B26 = 34, >+ AArch64_B27 = 35, >+ AArch64_B28 = 36, >+ AArch64_B29 = 37, >+ AArch64_B30 = 38, >+ AArch64_B31 = 39, >+ AArch64_D0 = 40, >+ AArch64_D1 = 41, >+ AArch64_D2 = 42, >+ AArch64_D3 = 43, >+ AArch64_D4 = 44, >+ AArch64_D5 = 45, >+ AArch64_D6 = 46, >+ AArch64_D7 = 47, >+ AArch64_D8 = 48, >+ AArch64_D9 = 49, >+ AArch64_D10 = 50, >+ AArch64_D11 = 51, >+ AArch64_D12 = 52, >+ AArch64_D13 = 53, >+ AArch64_D14 = 54, >+ AArch64_D15 = 55, >+ AArch64_D16 = 56, >+ AArch64_D17 = 57, >+ AArch64_D18 = 58, >+ AArch64_D19 = 59, >+ AArch64_D20 = 60, >+ AArch64_D21 = 61, >+ AArch64_D22 = 62, >+ AArch64_D23 = 63, >+ AArch64_D24 = 64, >+ AArch64_D25 = 65, >+ AArch64_D26 = 66, >+ AArch64_D27 = 67, >+ AArch64_D28 = 68, >+ AArch64_D29 = 69, >+ AArch64_D30 = 70, >+ AArch64_D31 = 71, >+ AArch64_H0 = 72, >+ AArch64_H1 = 73, >+ AArch64_H2 = 74, >+ AArch64_H3 = 75, >+ AArch64_H4 = 76, >+ AArch64_H5 = 77, >+ AArch64_H6 = 78, >+ AArch64_H7 = 79, >+ AArch64_H8 = 80, >+ AArch64_H9 = 81, >+ AArch64_H10 = 82, >+ AArch64_H11 = 83, >+ AArch64_H12 = 84, >+ AArch64_H13 = 85, >+ AArch64_H14 = 86, >+ AArch64_H15 = 87, >+ AArch64_H16 = 88, >+ AArch64_H17 = 89, >+ AArch64_H18 = 90, >+ AArch64_H19 = 91, >+ AArch64_H20 = 92, >+ AArch64_H21 = 93, >+ AArch64_H22 = 94, >+ AArch64_H23 = 95, >+ AArch64_H24 = 96, >+ AArch64_H25 = 97, >+ AArch64_H26 = 98, >+ AArch64_H27 = 99, >+ AArch64_H28 = 100, >+ AArch64_H29 = 101, >+ AArch64_H30 = 102, >+ AArch64_H31 = 103, >+ AArch64_Q0 = 104, >+ AArch64_Q1 = 105, >+ AArch64_Q2 = 106, >+ AArch64_Q3 = 107, >+ AArch64_Q4 = 108, >+ AArch64_Q5 = 109, >+ AArch64_Q6 = 110, >+ AArch64_Q7 = 111, >+ AArch64_Q8 = 112, >+ AArch64_Q9 = 113, >+ AArch64_Q10 = 114, >+ AArch64_Q11 = 115, >+ AArch64_Q12 = 116, >+ AArch64_Q13 = 117, >+ AArch64_Q14 = 118, >+ AArch64_Q15 = 119, >+ AArch64_Q16 = 120, >+ AArch64_Q17 = 121, >+ AArch64_Q18 = 122, >+ AArch64_Q19 = 123, >+ AArch64_Q20 = 124, >+ AArch64_Q21 = 125, >+ AArch64_Q22 = 126, >+ AArch64_Q23 = 127, >+ AArch64_Q24 = 128, >+ AArch64_Q25 = 129, >+ AArch64_Q26 = 130, >+ AArch64_Q27 = 131, >+ AArch64_Q28 = 132, >+ AArch64_Q29 = 133, >+ AArch64_Q30 = 134, >+ AArch64_Q31 = 135, >+ AArch64_S0 = 136, >+ AArch64_S1 = 137, >+ AArch64_S2 = 138, >+ AArch64_S3 = 139, >+ AArch64_S4 = 140, >+ AArch64_S5 = 141, >+ AArch64_S6 = 142, >+ AArch64_S7 = 143, >+ AArch64_S8 = 144, >+ AArch64_S9 = 145, >+ AArch64_S10 = 146, >+ AArch64_S11 = 147, >+ AArch64_S12 = 148, >+ AArch64_S13 = 149, >+ AArch64_S14 = 150, >+ AArch64_S15 = 151, >+ AArch64_S16 = 152, >+ AArch64_S17 = 153, >+ AArch64_S18 = 154, >+ AArch64_S19 = 155, >+ AArch64_S20 = 156, >+ AArch64_S21 = 157, >+ AArch64_S22 = 158, >+ AArch64_S23 = 159, >+ AArch64_S24 = 160, >+ AArch64_S25 = 161, >+ AArch64_S26 = 162, >+ AArch64_S27 = 163, >+ AArch64_S28 = 164, >+ AArch64_S29 = 165, >+ AArch64_S30 = 166, >+ AArch64_S31 = 167, >+ AArch64_W0 = 168, >+ AArch64_W1 = 169, >+ AArch64_W2 = 170, >+ AArch64_W3 = 171, >+ AArch64_W4 = 172, >+ AArch64_W5 = 173, >+ AArch64_W6 = 174, >+ AArch64_W7 = 175, >+ AArch64_W8 = 176, >+ AArch64_W9 = 177, >+ AArch64_W10 = 178, >+ AArch64_W11 = 179, >+ AArch64_W12 = 180, >+ AArch64_W13 = 181, >+ AArch64_W14 = 182, >+ AArch64_W15 = 183, >+ AArch64_W16 = 184, >+ AArch64_W17 = 185, >+ AArch64_W18 = 186, >+ AArch64_W19 = 187, >+ AArch64_W20 = 188, >+ AArch64_W21 = 189, >+ AArch64_W22 = 190, >+ AArch64_W23 = 191, >+ AArch64_W24 = 192, >+ AArch64_W25 = 193, >+ AArch64_W26 = 194, >+ AArch64_W27 = 195, >+ AArch64_W28 = 196, >+ AArch64_W29 = 197, >+ AArch64_W30 = 198, >+ AArch64_X0 = 199, >+ AArch64_X1 = 200, >+ AArch64_X2 = 201, >+ AArch64_X3 = 202, >+ AArch64_X4 = 203, >+ AArch64_X5 = 204, >+ AArch64_X6 = 205, >+ AArch64_X7 = 206, >+ AArch64_X8 = 207, >+ AArch64_X9 = 208, >+ AArch64_X10 = 209, >+ AArch64_X11 = 210, >+ AArch64_X12 = 211, >+ AArch64_X13 = 212, >+ AArch64_X14 = 213, >+ AArch64_X15 = 214, >+ AArch64_X16 = 215, >+ AArch64_X17 = 216, >+ AArch64_X18 = 217, >+ AArch64_X19 = 218, >+ AArch64_X20 = 219, >+ AArch64_X21 = 220, >+ AArch64_X22 = 221, >+ AArch64_X23 = 222, >+ AArch64_X24 = 223, >+ AArch64_X25 = 224, >+ AArch64_X26 = 225, >+ AArch64_X27 = 226, >+ AArch64_X28 = 227, >+ AArch64_D0_D1 = 228, >+ AArch64_D1_D2 = 229, >+ AArch64_D2_D3 = 230, >+ AArch64_D3_D4 = 231, >+ AArch64_D4_D5 = 232, >+ AArch64_D5_D6 = 233, >+ AArch64_D6_D7 = 234, >+ AArch64_D7_D8 = 235, >+ AArch64_D8_D9 = 236, >+ AArch64_D9_D10 = 237, >+ AArch64_D10_D11 = 238, >+ AArch64_D11_D12 = 239, >+ AArch64_D12_D13 = 240, >+ AArch64_D13_D14 = 241, >+ AArch64_D14_D15 = 242, >+ AArch64_D15_D16 = 243, >+ AArch64_D16_D17 = 244, >+ AArch64_D17_D18 = 245, >+ AArch64_D18_D19 = 246, >+ AArch64_D19_D20 = 247, >+ AArch64_D20_D21 = 248, >+ AArch64_D21_D22 = 249, >+ AArch64_D22_D23 = 250, >+ AArch64_D23_D24 = 251, >+ AArch64_D24_D25 = 252, >+ AArch64_D25_D26 = 253, >+ AArch64_D26_D27 = 254, >+ AArch64_D27_D28 = 255, >+ AArch64_D28_D29 = 256, >+ AArch64_D29_D30 = 257, >+ AArch64_D30_D31 = 258, >+ AArch64_D31_D0 = 259, >+ AArch64_D0_D1_D2_D3 = 260, >+ AArch64_D1_D2_D3_D4 = 261, >+ AArch64_D2_D3_D4_D5 = 262, >+ AArch64_D3_D4_D5_D6 = 263, >+ AArch64_D4_D5_D6_D7 = 264, >+ AArch64_D5_D6_D7_D8 = 265, >+ AArch64_D6_D7_D8_D9 = 266, >+ AArch64_D7_D8_D9_D10 = 267, >+ AArch64_D8_D9_D10_D11 = 268, >+ AArch64_D9_D10_D11_D12 = 269, >+ AArch64_D10_D11_D12_D13 = 270, >+ AArch64_D11_D12_D13_D14 = 271, >+ AArch64_D12_D13_D14_D15 = 272, >+ AArch64_D13_D14_D15_D16 = 273, >+ AArch64_D14_D15_D16_D17 = 274, >+ AArch64_D15_D16_D17_D18 = 275, >+ AArch64_D16_D17_D18_D19 = 276, >+ AArch64_D17_D18_D19_D20 = 277, >+ AArch64_D18_D19_D20_D21 = 278, >+ AArch64_D19_D20_D21_D22 = 279, >+ AArch64_D20_D21_D22_D23 = 280, >+ AArch64_D21_D22_D23_D24 = 281, >+ AArch64_D22_D23_D24_D25 = 282, >+ AArch64_D23_D24_D25_D26 = 283, >+ AArch64_D24_D25_D26_D27 = 284, >+ AArch64_D25_D26_D27_D28 = 285, >+ AArch64_D26_D27_D28_D29 = 286, >+ AArch64_D27_D28_D29_D30 = 287, >+ AArch64_D28_D29_D30_D31 = 288, >+ AArch64_D29_D30_D31_D0 = 289, >+ AArch64_D30_D31_D0_D1 = 290, >+ AArch64_D31_D0_D1_D2 = 291, >+ AArch64_D0_D1_D2 = 292, >+ AArch64_D1_D2_D3 = 293, >+ AArch64_D2_D3_D4 = 294, >+ AArch64_D3_D4_D5 = 295, >+ AArch64_D4_D5_D6 = 296, >+ AArch64_D5_D6_D7 = 297, >+ AArch64_D6_D7_D8 = 298, >+ AArch64_D7_D8_D9 = 299, >+ AArch64_D8_D9_D10 = 300, >+ AArch64_D9_D10_D11 = 301, >+ AArch64_D10_D11_D12 = 302, >+ AArch64_D11_D12_D13 = 303, >+ AArch64_D12_D13_D14 = 304, >+ AArch64_D13_D14_D15 = 305, >+ AArch64_D14_D15_D16 = 306, >+ AArch64_D15_D16_D17 = 307, >+ AArch64_D16_D17_D18 = 308, >+ AArch64_D17_D18_D19 = 309, >+ AArch64_D18_D19_D20 = 310, >+ AArch64_D19_D20_D21 = 311, >+ AArch64_D20_D21_D22 = 312, >+ AArch64_D21_D22_D23 = 313, >+ AArch64_D22_D23_D24 = 314, >+ AArch64_D23_D24_D25 = 315, >+ AArch64_D24_D25_D26 = 316, >+ AArch64_D25_D26_D27 = 317, >+ AArch64_D26_D27_D28 = 318, >+ AArch64_D27_D28_D29 = 319, >+ AArch64_D28_D29_D30 = 320, >+ AArch64_D29_D30_D31 = 321, >+ AArch64_D30_D31_D0 = 322, >+ AArch64_D31_D0_D1 = 323, >+ AArch64_Q0_Q1 = 324, >+ AArch64_Q1_Q2 = 325, >+ AArch64_Q2_Q3 = 326, >+ AArch64_Q3_Q4 = 327, >+ AArch64_Q4_Q5 = 328, >+ AArch64_Q5_Q6 = 329, >+ AArch64_Q6_Q7 = 330, >+ AArch64_Q7_Q8 = 331, >+ AArch64_Q8_Q9 = 332, >+ AArch64_Q9_Q10 = 333, >+ AArch64_Q10_Q11 = 334, >+ AArch64_Q11_Q12 = 335, >+ AArch64_Q12_Q13 = 336, >+ AArch64_Q13_Q14 = 337, >+ AArch64_Q14_Q15 = 338, >+ AArch64_Q15_Q16 = 339, >+ AArch64_Q16_Q17 = 340, >+ AArch64_Q17_Q18 = 341, >+ AArch64_Q18_Q19 = 342, >+ AArch64_Q19_Q20 = 343, >+ AArch64_Q20_Q21 = 344, >+ AArch64_Q21_Q22 = 345, >+ AArch64_Q22_Q23 = 346, >+ AArch64_Q23_Q24 = 347, >+ AArch64_Q24_Q25 = 348, >+ AArch64_Q25_Q26 = 349, >+ AArch64_Q26_Q27 = 350, >+ AArch64_Q27_Q28 = 351, >+ AArch64_Q28_Q29 = 352, >+ AArch64_Q29_Q30 = 353, >+ AArch64_Q30_Q31 = 354, >+ AArch64_Q31_Q0 = 355, >+ AArch64_Q0_Q1_Q2_Q3 = 356, >+ AArch64_Q1_Q2_Q3_Q4 = 357, >+ AArch64_Q2_Q3_Q4_Q5 = 358, >+ AArch64_Q3_Q4_Q5_Q6 = 359, >+ AArch64_Q4_Q5_Q6_Q7 = 360, >+ AArch64_Q5_Q6_Q7_Q8 = 361, >+ AArch64_Q6_Q7_Q8_Q9 = 362, >+ AArch64_Q7_Q8_Q9_Q10 = 363, >+ AArch64_Q8_Q9_Q10_Q11 = 364, >+ AArch64_Q9_Q10_Q11_Q12 = 365, >+ AArch64_Q10_Q11_Q12_Q13 = 366, >+ AArch64_Q11_Q12_Q13_Q14 = 367, >+ AArch64_Q12_Q13_Q14_Q15 = 368, >+ AArch64_Q13_Q14_Q15_Q16 = 369, >+ AArch64_Q14_Q15_Q16_Q17 = 370, >+ AArch64_Q15_Q16_Q17_Q18 = 371, >+ AArch64_Q16_Q17_Q18_Q19 = 372, >+ AArch64_Q17_Q18_Q19_Q20 = 373, >+ AArch64_Q18_Q19_Q20_Q21 = 374, >+ AArch64_Q19_Q20_Q21_Q22 = 375, >+ AArch64_Q20_Q21_Q22_Q23 = 376, >+ AArch64_Q21_Q22_Q23_Q24 = 377, >+ AArch64_Q22_Q23_Q24_Q25 = 378, >+ AArch64_Q23_Q24_Q25_Q26 = 379, >+ AArch64_Q24_Q25_Q26_Q27 = 380, >+ AArch64_Q25_Q26_Q27_Q28 = 381, >+ AArch64_Q26_Q27_Q28_Q29 = 382, >+ AArch64_Q27_Q28_Q29_Q30 = 383, >+ AArch64_Q28_Q29_Q30_Q31 = 384, >+ AArch64_Q29_Q30_Q31_Q0 = 385, >+ AArch64_Q30_Q31_Q0_Q1 = 386, >+ AArch64_Q31_Q0_Q1_Q2 = 387, >+ AArch64_Q0_Q1_Q2 = 388, >+ AArch64_Q1_Q2_Q3 = 389, >+ AArch64_Q2_Q3_Q4 = 390, >+ AArch64_Q3_Q4_Q5 = 391, >+ AArch64_Q4_Q5_Q6 = 392, >+ AArch64_Q5_Q6_Q7 = 393, >+ AArch64_Q6_Q7_Q8 = 394, >+ AArch64_Q7_Q8_Q9 = 395, >+ AArch64_Q8_Q9_Q10 = 396, >+ AArch64_Q9_Q10_Q11 = 397, >+ AArch64_Q10_Q11_Q12 = 398, >+ AArch64_Q11_Q12_Q13 = 399, >+ AArch64_Q12_Q13_Q14 = 400, >+ AArch64_Q13_Q14_Q15 = 401, >+ AArch64_Q14_Q15_Q16 = 402, >+ AArch64_Q15_Q16_Q17 = 403, >+ AArch64_Q16_Q17_Q18 = 404, >+ AArch64_Q17_Q18_Q19 = 405, >+ AArch64_Q18_Q19_Q20 = 406, >+ AArch64_Q19_Q20_Q21 = 407, >+ AArch64_Q20_Q21_Q22 = 408, >+ AArch64_Q21_Q22_Q23 = 409, >+ AArch64_Q22_Q23_Q24 = 410, >+ AArch64_Q23_Q24_Q25 = 411, >+ AArch64_Q24_Q25_Q26 = 412, >+ AArch64_Q25_Q26_Q27 = 413, >+ AArch64_Q26_Q27_Q28 = 414, >+ AArch64_Q27_Q28_Q29 = 415, >+ AArch64_Q28_Q29_Q30 = 416, >+ AArch64_Q29_Q30_Q31 = 417, >+ AArch64_Q30_Q31_Q0 = 418, >+ AArch64_Q31_Q0_Q1 = 419, >+ AArch64_NUM_TARGET_REGS // 420 >+}; >+ >+// Register classes >+enum { >+ AArch64_FPR8RegClassID = 0, >+ AArch64_FPR16RegClassID = 1, >+ AArch64_GPR32allRegClassID = 2, >+ AArch64_FPR32RegClassID = 3, >+ AArch64_GPR32RegClassID = 4, >+ AArch64_GPR32spRegClassID = 5, >+ AArch64_GPR32commonRegClassID = 6, >+ AArch64_CCRRegClassID = 7, >+ AArch64_GPR32sponlyRegClassID = 8, >+ AArch64_GPR64allRegClassID = 9, >+ AArch64_FPR64RegClassID = 10, >+ AArch64_GPR64RegClassID = 11, >+ AArch64_GPR64spRegClassID = 12, >+ AArch64_GPR64commonRegClassID = 13, >+ AArch64_tcGPR64RegClassID = 14, >+ AArch64_GPR64sponlyRegClassID = 15, >+ AArch64_DDRegClassID = 16, >+ AArch64_FPR128RegClassID = 17, >+ AArch64_FPR128_loRegClassID = 18, >+ AArch64_DDDRegClassID = 19, >+ AArch64_DDDDRegClassID = 20, >+ AArch64_QQRegClassID = 21, >+ AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 22, >+ AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 23, >+ AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 24, >+ AArch64_QQQRegClassID = 25, >+ AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 26, >+ AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 27, >+ AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 28, >+ AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 29, >+ AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 30, >+ AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 31, >+ AArch64_QQQQRegClassID = 32, >+ AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 33, >+ AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 34, >+ AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 35, >+ AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 36, >+ AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 37, >+ AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 38, >+ AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 39, >+ AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 40, >+ AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 41, >+ AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42 >+}; >+ >+// Register alternate name indices >+enum { >+ AArch64_NoRegAltName, // 0 >+ AArch64_vlist1, // 1 >+ AArch64_vreg, // 2 >+ AArch64_NUM_TARGET_REG_ALT_NAMES = 3 >+}; >+ >+// Subregister indices >+enum { >+ AArch64_NoSubRegister, >+ AArch64_bsub, // 1 >+ AArch64_dsub, // 2 >+ AArch64_dsub0, // 3 >+ AArch64_dsub1, // 4 >+ AArch64_dsub2, // 5 >+ AArch64_dsub3, // 6 >+ AArch64_hsub, // 7 >+ AArch64_qhisub, // 8 >+ AArch64_qsub, // 9 >+ AArch64_qsub0, // 10 >+ AArch64_qsub1, // 11 >+ AArch64_qsub2, // 12 >+ AArch64_qsub3, // 13 >+ AArch64_ssub, // 14 >+ AArch64_sub_32, // 15 >+ AArch64_dsub1_then_bsub, // 16 >+ AArch64_dsub1_then_hsub, // 17 >+ AArch64_dsub1_then_ssub, // 18 >+ AArch64_dsub3_then_bsub, // 19 >+ AArch64_dsub3_then_hsub, // 20 >+ AArch64_dsub3_then_ssub, // 21 >+ AArch64_dsub2_then_bsub, // 22 >+ AArch64_dsub2_then_hsub, // 23 >+ AArch64_dsub2_then_ssub, // 24 >+ AArch64_qsub1_then_bsub, // 25 >+ AArch64_qsub1_then_dsub, // 26 >+ AArch64_qsub1_then_hsub, // 27 >+ AArch64_qsub1_then_ssub, // 28 >+ AArch64_qsub3_then_bsub, // 29 >+ AArch64_qsub3_then_dsub, // 30 >+ AArch64_qsub3_then_hsub, // 31 >+ AArch64_qsub3_then_ssub, // 32 >+ AArch64_qsub2_then_bsub, // 33 >+ AArch64_qsub2_then_dsub, // 34 >+ AArch64_qsub2_then_hsub, // 35 >+ AArch64_qsub2_then_ssub, // 36 >+ AArch64_dsub0_dsub1, // 37 >+ AArch64_dsub0_dsub1_dsub2, // 38 >+ AArch64_dsub1_dsub2, // 39 >+ AArch64_dsub1_dsub2_dsub3, // 40 >+ AArch64_dsub2_dsub3, // 41 >+ AArch64_dsub_qsub1_then_dsub, // 42 >+ AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 43 >+ AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 44 >+ AArch64_qsub0_qsub1, // 45 >+ AArch64_qsub0_qsub1_qsub2, // 46 >+ AArch64_qsub1_qsub2, // 47 >+ AArch64_qsub1_qsub2_qsub3, // 48 >+ AArch64_qsub2_qsub3, // 49 >+ AArch64_qsub1_then_dsub_qsub2_then_dsub, // 50 >+ AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 51 >+ AArch64_qsub2_then_dsub_qsub3_then_dsub, // 52 >+ AArch64_NUM_TARGET_SUBREGS >+}; >+ >+#endif // GET_REGINFO_ENUM >+ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*MC Register Information *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_MC_DESC >+#undef GET_REGINFO_MC_DESC >+ >+static const MCPhysReg AArch64RegDiffLists[] = { >+ /* 0 */ 65185, 1, 1, 1, 0, >+ /* 5 */ 65281, 1, 1, 1, 0, >+ /* 10 */ 5, 29, 1, 1, 0, >+ /* 15 */ 65153, 1, 1, 0, >+ /* 19 */ 65249, 1, 1, 0, >+ /* 23 */ 5, 1, 29, 1, 0, >+ /* 28 */ 5, 30, 1, 0, >+ /* 32 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0, >+ /* 47 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0, >+ /* 62 */ 65217, 1, 0, >+ /* 65 */ 65313, 1, 0, >+ /* 68 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, >+ /* 91 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, >+ /* 101 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, >+ /* 124 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, >+ /* 134 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0, >+ /* 146 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, >+ /* 169 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, >+ /* 179 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0, >+ /* 191 */ 65503, 1, 128, 65503, 1, 0, >+ /* 197 */ 3, 0, >+ /* 199 */ 4, 0, >+ /* 201 */ 5, 1, 1, 29, 0, >+ /* 206 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, >+ /* 229 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, >+ /* 239 */ 5, 1, 30, 0, >+ /* 243 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0, >+ /* 255 */ 5, 31, 0, >+ /* 258 */ 65504, 31, 97, 65504, 31, 0, >+ /* 264 */ 96, 0, >+ /* 266 */ 196, 0, >+ /* 268 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0, >+ /* 280 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0, >+ /* 292 */ 65339, 0, >+ /* 294 */ 65340, 0, >+ /* 296 */ 65374, 0, >+ /* 298 */ 65405, 0, >+ /* 300 */ 65437, 0, >+ /* 302 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0, >+ /* 323 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0, >+ /* 344 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0, >+ /* 365 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, >+ /* 397 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0, >+ /* 419 */ 65469, 0, >+ /* 421 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0, >+ /* 430 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0, >+ /* 439 */ 65472, 96, 65472, 65472, 0, >+ /* 444 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, >+ /* 476 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, >+ /* 508 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, >+ /* 540 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0, >+ /* 562 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0, >+ /* 584 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0, >+ /* 606 */ 65501, 0, >+ /* 608 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0, >+ /* 623 */ 65533, 0, >+ /* 625 */ 65535, 0, >+}; >+ >+static const uint16_t AArch64SubRegIdxLists[] = { >+ /* 0 */ 2, 14, 7, 1, 0, >+ /* 5 */ 15, 0, >+ /* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0, >+ /* 16 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 37, 39, 0, >+ /* 31 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 6, 21, 20, 19, 37, 38, 39, 40, 41, 0, >+ /* 53 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 42, 0, >+ /* 65 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 42, 44, 45, 47, 50, 0, >+ /* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0, >+}; >+ >+static const MCRegisterDesc AArch64RegDesc[] = { // Descriptors >+ { 3, 0, 0, 0, 0 }, >+ { 1518, 266, 4, 5, 10001 }, >+ { 1525, 266, 4, 5, 10001 }, >+ { 1536, 4, 4, 4, 10001 }, >+ { 1522, 3, 4, 5, 3152 }, >+ { 1521, 4, 625, 4, 3152 }, >+ { 1528, 4, 3, 4, 3184 }, >+ { 1532, 625, 4, 5, 3184 }, >+ { 146, 4, 101, 4, 9969 }, >+ { 335, 4, 146, 4, 9969 }, >+ { 480, 4, 206, 4, 9969 }, >+ { 625, 4, 68, 4, 9969 }, >+ { 768, 4, 68, 4, 9969 }, >+ { 911, 4, 68, 4, 9969 }, >+ { 1054, 4, 68, 4, 9969 }, >+ { 1197, 4, 68, 4, 9969 }, >+ { 1340, 4, 68, 4, 9969 }, >+ { 1479, 4, 68, 4, 9969 }, >+ { 0, 4, 68, 4, 9969 }, >+ { 191, 4, 68, 4, 9969 }, >+ { 378, 4, 68, 4, 9969 }, >+ { 521, 4, 68, 4, 9969 }, >+ { 664, 4, 68, 4, 9969 }, >+ { 807, 4, 68, 4, 9969 }, >+ { 950, 4, 68, 4, 9969 }, >+ { 1093, 4, 68, 4, 9969 }, >+ { 1236, 4, 68, 4, 9969 }, >+ { 1379, 4, 68, 4, 9969 }, >+ { 46, 4, 68, 4, 9969 }, >+ { 239, 4, 68, 4, 9969 }, >+ { 428, 4, 68, 4, 9969 }, >+ { 573, 4, 68, 4, 9969 }, >+ { 716, 4, 68, 4, 9969 }, >+ { 859, 4, 68, 4, 9969 }, >+ { 1002, 4, 68, 4, 9969 }, >+ { 1145, 4, 68, 4, 9969 }, >+ { 1288, 4, 68, 4, 9969 }, >+ { 1431, 4, 68, 4, 9969 }, >+ { 98, 4, 68, 4, 9969 }, >+ { 291, 4, 68, 4, 9969 }, >+ { 161, 426, 104, 1, 9697 }, >+ { 349, 426, 149, 1, 9697 }, >+ { 493, 426, 209, 1, 9697 }, >+ { 637, 426, 71, 1, 9697 }, >+ { 780, 426, 71, 1, 9697 }, >+ { 923, 426, 71, 1, 9697 }, >+ { 1066, 426, 71, 1, 9697 }, >+ { 1209, 426, 71, 1, 9697 }, >+ { 1352, 426, 71, 1, 9697 }, >+ { 1491, 426, 71, 1, 9697 }, >+ { 13, 426, 71, 1, 9697 }, >+ { 205, 426, 71, 1, 9697 }, >+ { 393, 426, 71, 1, 9697 }, >+ { 537, 426, 71, 1, 9697 }, >+ { 680, 426, 71, 1, 9697 }, >+ { 823, 426, 71, 1, 9697 }, >+ { 966, 426, 71, 1, 9697 }, >+ { 1109, 426, 71, 1, 9697 }, >+ { 1252, 426, 71, 1, 9697 }, >+ { 1395, 426, 71, 1, 9697 }, >+ { 62, 426, 71, 1, 9697 }, >+ { 255, 426, 71, 1, 9697 }, >+ { 444, 426, 71, 1, 9697 }, >+ { 589, 426, 71, 1, 9697 }, >+ { 732, 426, 71, 1, 9697 }, >+ { 875, 426, 71, 1, 9697 }, >+ { 1018, 426, 71, 1, 9697 }, >+ { 1161, 426, 71, 1, 9697 }, >+ { 1304, 426, 71, 1, 9697 }, >+ { 1447, 426, 71, 1, 9697 }, >+ { 114, 426, 71, 1, 9697 }, >+ { 307, 426, 71, 1, 9697 }, >+ { 164, 428, 102, 3, 6705 }, >+ { 352, 428, 147, 3, 6705 }, >+ { 496, 428, 207, 3, 6705 }, >+ { 640, 428, 69, 3, 6705 }, >+ { 783, 428, 69, 3, 6705 }, >+ { 926, 428, 69, 3, 6705 }, >+ { 1069, 428, 69, 3, 6705 }, >+ { 1212, 428, 69, 3, 6705 }, >+ { 1355, 428, 69, 3, 6705 }, >+ { 1494, 428, 69, 3, 6705 }, >+ { 17, 428, 69, 3, 6705 }, >+ { 209, 428, 69, 3, 6705 }, >+ { 397, 428, 69, 3, 6705 }, >+ { 541, 428, 69, 3, 6705 }, >+ { 684, 428, 69, 3, 6705 }, >+ { 827, 428, 69, 3, 6705 }, >+ { 970, 428, 69, 3, 6705 }, >+ { 1113, 428, 69, 3, 6705 }, >+ { 1256, 428, 69, 3, 6705 }, >+ { 1399, 428, 69, 3, 6705 }, >+ { 66, 428, 69, 3, 6705 }, >+ { 259, 428, 69, 3, 6705 }, >+ { 448, 428, 69, 3, 6705 }, >+ { 593, 428, 69, 3, 6705 }, >+ { 736, 428, 69, 3, 6705 }, >+ { 879, 428, 69, 3, 6705 }, >+ { 1022, 428, 69, 3, 6705 }, >+ { 1165, 428, 69, 3, 6705 }, >+ { 1308, 428, 69, 3, 6705 }, >+ { 1451, 428, 69, 3, 6705 }, >+ { 118, 428, 69, 3, 6705 }, >+ { 311, 428, 69, 3, 6705 }, >+ { 179, 439, 124, 0, 4801 }, >+ { 366, 439, 169, 0, 4801 }, >+ { 509, 439, 229, 0, 4801 }, >+ { 652, 439, 91, 0, 4801 }, >+ { 795, 439, 91, 0, 4801 }, >+ { 938, 439, 91, 0, 4801 }, >+ { 1081, 439, 91, 0, 4801 }, >+ { 1224, 439, 91, 0, 4801 }, >+ { 1367, 439, 91, 0, 4801 }, >+ { 1506, 439, 91, 0, 4801 }, >+ { 30, 439, 91, 0, 4801 }, >+ { 223, 439, 91, 0, 4801 }, >+ { 412, 439, 91, 0, 4801 }, >+ { 557, 439, 91, 0, 4801 }, >+ { 700, 439, 91, 0, 4801 }, >+ { 843, 439, 91, 0, 4801 }, >+ { 986, 439, 91, 0, 4801 }, >+ { 1129, 439, 91, 0, 4801 }, >+ { 1272, 439, 91, 0, 4801 }, >+ { 1415, 439, 91, 0, 4801 }, >+ { 82, 439, 91, 0, 4801 }, >+ { 275, 439, 91, 0, 4801 }, >+ { 464, 439, 91, 0, 4801 }, >+ { 609, 439, 91, 0, 4801 }, >+ { 752, 439, 91, 0, 4801 }, >+ { 895, 439, 91, 0, 4801 }, >+ { 1038, 439, 91, 0, 4801 }, >+ { 1181, 439, 91, 0, 4801 }, >+ { 1324, 439, 91, 0, 4801 }, >+ { 1467, 439, 91, 0, 4801 }, >+ { 134, 439, 91, 0, 4801 }, >+ { 327, 439, 91, 0, 4801 }, >+ { 182, 427, 103, 2, 4769 }, >+ { 369, 427, 148, 2, 4769 }, >+ { 512, 427, 208, 2, 4769 }, >+ { 655, 427, 70, 2, 4769 }, >+ { 798, 427, 70, 2, 4769 }, >+ { 941, 427, 70, 2, 4769 }, >+ { 1084, 427, 70, 2, 4769 }, >+ { 1227, 427, 70, 2, 4769 }, >+ { 1370, 427, 70, 2, 4769 }, >+ { 1509, 427, 70, 2, 4769 }, >+ { 34, 427, 70, 2, 4769 }, >+ { 227, 427, 70, 2, 4769 }, >+ { 416, 427, 70, 2, 4769 }, >+ { 561, 427, 70, 2, 4769 }, >+ { 704, 427, 70, 2, 4769 }, >+ { 847, 427, 70, 2, 4769 }, >+ { 990, 427, 70, 2, 4769 }, >+ { 1133, 427, 70, 2, 4769 }, >+ { 1276, 427, 70, 2, 4769 }, >+ { 1419, 427, 70, 2, 4769 }, >+ { 86, 427, 70, 2, 4769 }, >+ { 279, 427, 70, 2, 4769 }, >+ { 468, 427, 70, 2, 4769 }, >+ { 613, 427, 70, 2, 4769 }, >+ { 756, 427, 70, 2, 4769 }, >+ { 899, 427, 70, 2, 4769 }, >+ { 1042, 427, 70, 2, 4769 }, >+ { 1185, 427, 70, 2, 4769 }, >+ { 1328, 427, 70, 2, 4769 }, >+ { 1471, 427, 70, 2, 4769 }, >+ { 138, 427, 70, 2, 4769 }, >+ { 331, 427, 70, 2, 4769 }, >+ { 185, 4, 256, 4, 4769 }, >+ { 372, 4, 256, 4, 4769 }, >+ { 515, 4, 256, 4, 4769 }, >+ { 658, 4, 256, 4, 4769 }, >+ { 801, 4, 256, 4, 4769 }, >+ { 944, 4, 256, 4, 4769 }, >+ { 1087, 4, 256, 4, 4769 }, >+ { 1230, 4, 256, 4, 4769 }, >+ { 1373, 4, 256, 4, 4769 }, >+ { 1512, 4, 256, 4, 4769 }, >+ { 38, 4, 256, 4, 4769 }, >+ { 231, 4, 256, 4, 4769 }, >+ { 420, 4, 256, 4, 4769 }, >+ { 565, 4, 256, 4, 4769 }, >+ { 708, 4, 256, 4, 4769 }, >+ { 851, 4, 256, 4, 4769 }, >+ { 994, 4, 256, 4, 4769 }, >+ { 1137, 4, 256, 4, 4769 }, >+ { 1280, 4, 256, 4, 4769 }, >+ { 1423, 4, 256, 4, 4769 }, >+ { 90, 4, 256, 4, 4769 }, >+ { 283, 4, 256, 4, 4769 }, >+ { 472, 4, 256, 4, 4769 }, >+ { 617, 4, 256, 4, 4769 }, >+ { 760, 4, 256, 4, 4769 }, >+ { 903, 4, 256, 4, 4769 }, >+ { 1046, 4, 256, 4, 4769 }, >+ { 1189, 4, 256, 4, 4769 }, >+ { 1332, 4, 256, 4, 4769 }, >+ { 1475, 4, 294, 4, 4673 }, >+ { 142, 4, 294, 4, 4673 }, >+ { 188, 621, 4, 5, 4737 }, >+ { 375, 621, 4, 5, 4737 }, >+ { 518, 621, 4, 5, 4737 }, >+ { 661, 621, 4, 5, 4737 }, >+ { 804, 621, 4, 5, 4737 }, >+ { 947, 621, 4, 5, 4737 }, >+ { 1090, 621, 4, 5, 4737 }, >+ { 1233, 621, 4, 5, 4737 }, >+ { 1376, 621, 4, 5, 4737 }, >+ { 1515, 621, 4, 5, 4737 }, >+ { 42, 621, 4, 5, 4737 }, >+ { 235, 621, 4, 5, 4737 }, >+ { 424, 621, 4, 5, 4737 }, >+ { 569, 621, 4, 5, 4737 }, >+ { 712, 621, 4, 5, 4737 }, >+ { 855, 621, 4, 5, 4737 }, >+ { 998, 621, 4, 5, 4737 }, >+ { 1141, 621, 4, 5, 4737 }, >+ { 1284, 621, 4, 5, 4737 }, >+ { 1427, 621, 4, 5, 4737 }, >+ { 94, 621, 4, 5, 4737 }, >+ { 287, 621, 4, 5, 4737 }, >+ { 476, 621, 4, 5, 4737 }, >+ { 621, 621, 4, 5, 4737 }, >+ { 764, 621, 4, 5, 4737 }, >+ { 907, 621, 4, 5, 4737 }, >+ { 1050, 621, 4, 5, 4737 }, >+ { 1193, 621, 4, 5, 4737 }, >+ { 1336, 621, 4, 5, 4737 }, >+ { 346, 430, 179, 7, 1041 }, >+ { 490, 430, 243, 7, 1041 }, >+ { 634, 430, 134, 7, 1041 }, >+ { 777, 430, 134, 7, 1041 }, >+ { 920, 430, 134, 7, 1041 }, >+ { 1063, 430, 134, 7, 1041 }, >+ { 1206, 430, 134, 7, 1041 }, >+ { 1349, 430, 134, 7, 1041 }, >+ { 1488, 430, 134, 7, 1041 }, >+ { 10, 430, 134, 7, 1041 }, >+ { 201, 430, 134, 7, 1041 }, >+ { 389, 430, 134, 7, 1041 }, >+ { 533, 430, 134, 7, 1041 }, >+ { 676, 430, 134, 7, 1041 }, >+ { 819, 430, 134, 7, 1041 }, >+ { 962, 430, 134, 7, 1041 }, >+ { 1105, 430, 134, 7, 1041 }, >+ { 1248, 430, 134, 7, 1041 }, >+ { 1391, 430, 134, 7, 1041 }, >+ { 58, 430, 134, 7, 1041 }, >+ { 251, 430, 134, 7, 1041 }, >+ { 440, 430, 134, 7, 1041 }, >+ { 585, 430, 134, 7, 1041 }, >+ { 728, 430, 134, 7, 1041 }, >+ { 871, 430, 134, 7, 1041 }, >+ { 1014, 430, 134, 7, 1041 }, >+ { 1157, 430, 134, 7, 1041 }, >+ { 1300, 430, 134, 7, 1041 }, >+ { 1443, 430, 134, 7, 1041 }, >+ { 110, 430, 134, 7, 1041 }, >+ { 303, 430, 134, 7, 1041 }, >+ { 157, 421, 134, 7, 4080 }, >+ { 628, 562, 264, 31, 81 }, >+ { 771, 562, 264, 31, 81 }, >+ { 914, 562, 264, 31, 81 }, >+ { 1057, 562, 264, 31, 81 }, >+ { 1200, 562, 264, 31, 81 }, >+ { 1343, 562, 264, 31, 81 }, >+ { 1482, 562, 264, 31, 81 }, >+ { 4, 562, 264, 31, 81 }, >+ { 195, 562, 264, 31, 81 }, >+ { 382, 562, 264, 31, 81 }, >+ { 525, 562, 264, 31, 81 }, >+ { 668, 562, 264, 31, 81 }, >+ { 811, 562, 264, 31, 81 }, >+ { 954, 562, 264, 31, 81 }, >+ { 1097, 562, 264, 31, 81 }, >+ { 1240, 562, 264, 31, 81 }, >+ { 1383, 562, 264, 31, 81 }, >+ { 50, 562, 264, 31, 81 }, >+ { 243, 562, 264, 31, 81 }, >+ { 432, 562, 264, 31, 81 }, >+ { 577, 562, 264, 31, 81 }, >+ { 720, 562, 264, 31, 81 }, >+ { 863, 562, 264, 31, 81 }, >+ { 1006, 562, 264, 31, 81 }, >+ { 1149, 562, 264, 31, 81 }, >+ { 1292, 562, 264, 31, 81 }, >+ { 1435, 562, 264, 31, 81 }, >+ { 102, 562, 264, 31, 81 }, >+ { 295, 562, 264, 31, 81 }, >+ { 149, 584, 264, 31, 160 }, >+ { 338, 397, 264, 31, 368 }, >+ { 483, 540, 264, 31, 3216 }, >+ { 487, 32, 258, 16, 305 }, >+ { 631, 32, 191, 16, 305 }, >+ { 774, 32, 191, 16, 305 }, >+ { 917, 32, 191, 16, 305 }, >+ { 1060, 32, 191, 16, 305 }, >+ { 1203, 32, 191, 16, 305 }, >+ { 1346, 32, 191, 16, 305 }, >+ { 1485, 32, 191, 16, 305 }, >+ { 7, 32, 191, 16, 305 }, >+ { 198, 32, 191, 16, 305 }, >+ { 385, 32, 191, 16, 305 }, >+ { 529, 32, 191, 16, 305 }, >+ { 672, 32, 191, 16, 305 }, >+ { 815, 32, 191, 16, 305 }, >+ { 958, 32, 191, 16, 305 }, >+ { 1101, 32, 191, 16, 305 }, >+ { 1244, 32, 191, 16, 305 }, >+ { 1387, 32, 191, 16, 305 }, >+ { 54, 32, 191, 16, 305 }, >+ { 247, 32, 191, 16, 305 }, >+ { 436, 32, 191, 16, 305 }, >+ { 581, 32, 191, 16, 305 }, >+ { 724, 32, 191, 16, 305 }, >+ { 867, 32, 191, 16, 305 }, >+ { 1010, 32, 191, 16, 305 }, >+ { 1153, 32, 191, 16, 305 }, >+ { 1296, 32, 191, 16, 305 }, >+ { 1439, 32, 191, 16, 305 }, >+ { 106, 32, 191, 16, 305 }, >+ { 299, 32, 191, 16, 305 }, >+ { 153, 47, 191, 16, 448 }, >+ { 342, 608, 191, 16, 3824 }, >+ { 363, 268, 185, 53, 993 }, >+ { 506, 268, 249, 53, 993 }, >+ { 649, 268, 140, 53, 993 }, >+ { 792, 268, 140, 53, 993 }, >+ { 935, 268, 140, 53, 993 }, >+ { 1078, 268, 140, 53, 993 }, >+ { 1221, 268, 140, 53, 993 }, >+ { 1364, 268, 140, 53, 993 }, >+ { 1503, 268, 140, 53, 993 }, >+ { 27, 268, 140, 53, 993 }, >+ { 219, 268, 140, 53, 993 }, >+ { 408, 268, 140, 53, 993 }, >+ { 553, 268, 140, 53, 993 }, >+ { 696, 268, 140, 53, 993 }, >+ { 839, 268, 140, 53, 993 }, >+ { 982, 268, 140, 53, 993 }, >+ { 1125, 268, 140, 53, 993 }, >+ { 1268, 268, 140, 53, 993 }, >+ { 1411, 268, 140, 53, 993 }, >+ { 78, 268, 140, 53, 993 }, >+ { 271, 268, 140, 53, 993 }, >+ { 460, 268, 140, 53, 993 }, >+ { 605, 268, 140, 53, 993 }, >+ { 748, 268, 140, 53, 993 }, >+ { 891, 268, 140, 53, 993 }, >+ { 1034, 268, 140, 53, 993 }, >+ { 1177, 268, 140, 53, 993 }, >+ { 1320, 268, 140, 53, 993 }, >+ { 1463, 268, 140, 53, 993 }, >+ { 130, 268, 140, 53, 993 }, >+ { 323, 268, 140, 53, 993 }, >+ { 175, 280, 140, 53, 4080 }, >+ { 643, 476, 4, 86, 1 }, >+ { 786, 476, 4, 86, 1 }, >+ { 929, 476, 4, 86, 1 }, >+ { 1072, 476, 4, 86, 1 }, >+ { 1215, 476, 4, 86, 1 }, >+ { 1358, 476, 4, 86, 1 }, >+ { 1497, 476, 4, 86, 1 }, >+ { 21, 476, 4, 86, 1 }, >+ { 213, 476, 4, 86, 1 }, >+ { 401, 476, 4, 86, 1 }, >+ { 545, 476, 4, 86, 1 }, >+ { 688, 476, 4, 86, 1 }, >+ { 831, 476, 4, 86, 1 }, >+ { 974, 476, 4, 86, 1 }, >+ { 1117, 476, 4, 86, 1 }, >+ { 1260, 476, 4, 86, 1 }, >+ { 1403, 476, 4, 86, 1 }, >+ { 70, 476, 4, 86, 1 }, >+ { 263, 476, 4, 86, 1 }, >+ { 452, 476, 4, 86, 1 }, >+ { 597, 476, 4, 86, 1 }, >+ { 740, 476, 4, 86, 1 }, >+ { 883, 476, 4, 86, 1 }, >+ { 1026, 476, 4, 86, 1 }, >+ { 1169, 476, 4, 86, 1 }, >+ { 1312, 476, 4, 86, 1 }, >+ { 1455, 476, 4, 86, 1 }, >+ { 122, 476, 4, 86, 1 }, >+ { 315, 476, 4, 86, 1 }, >+ { 167, 508, 4, 86, 160 }, >+ { 355, 365, 4, 86, 368 }, >+ { 499, 444, 4, 86, 3216 }, >+ { 503, 302, 261, 65, 241 }, >+ { 646, 302, 88, 65, 241 }, >+ { 789, 302, 88, 65, 241 }, >+ { 932, 302, 88, 65, 241 }, >+ { 1075, 302, 88, 65, 241 }, >+ { 1218, 302, 88, 65, 241 }, >+ { 1361, 302, 88, 65, 241 }, >+ { 1500, 302, 88, 65, 241 }, >+ { 24, 302, 88, 65, 241 }, >+ { 216, 302, 88, 65, 241 }, >+ { 404, 302, 88, 65, 241 }, >+ { 549, 302, 88, 65, 241 }, >+ { 692, 302, 88, 65, 241 }, >+ { 835, 302, 88, 65, 241 }, >+ { 978, 302, 88, 65, 241 }, >+ { 1121, 302, 88, 65, 241 }, >+ { 1264, 302, 88, 65, 241 }, >+ { 1407, 302, 88, 65, 241 }, >+ { 74, 302, 88, 65, 241 }, >+ { 267, 302, 88, 65, 241 }, >+ { 456, 302, 88, 65, 241 }, >+ { 601, 302, 88, 65, 241 }, >+ { 744, 302, 88, 65, 241 }, >+ { 887, 302, 88, 65, 241 }, >+ { 1030, 302, 88, 65, 241 }, >+ { 1173, 302, 88, 65, 241 }, >+ { 1316, 302, 88, 65, 241 }, >+ { 1459, 302, 88, 65, 241 }, >+ { 126, 302, 88, 65, 241 }, >+ { 319, 302, 88, 65, 241 }, >+ { 171, 323, 88, 65, 448 }, >+ { 359, 344, 88, 65, 3824 }, >+}; >+ >+ // FPR8 Register Class... >+ static const MCPhysReg FPR8[] = { >+ AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31, >+ }; >+ >+ // FPR8 Bit set. >+ static const uint8_t FPR8Bits[] = { >+ 0x00, 0xff, 0xff, 0xff, 0xff, >+ }; >+ >+ // FPR16 Register Class... >+ static const MCPhysReg FPR16[] = { >+ AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31, >+ }; >+ >+ // FPR16 Bit set. >+ static const uint8_t FPR16Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, >+ }; >+ >+ // GPR32all Register Class... >+ static const MCPhysReg GPR32all[] = { >+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP, >+ }; >+ >+ // GPR32all Bit set. >+ static const uint8_t GPR32allBits[] = { >+ 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // FPR32 Register Class... >+ static const MCPhysReg FPR32[] = { >+ AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31, >+ }; >+ >+ // FPR32 Bit set. >+ static const uint8_t FPR32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, >+ }; >+ >+ // GPR32 Register Class... >+ static const MCPhysReg GPR32[] = { >+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, >+ }; >+ >+ // GPR32 Bit set. >+ static const uint8_t GPR32Bits[] = { >+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // GPR32sp Register Class... >+ static const MCPhysReg GPR32sp[] = { >+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP, >+ }; >+ >+ // GPR32sp Bit set. >+ static const uint8_t GPR32spBits[] = { >+ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // GPR32common Register Class... >+ static const MCPhysReg GPR32common[] = { >+ AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, >+ }; >+ >+ // GPR32common Bit set. >+ static const uint8_t GPR32commonBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // CCR Register Class... >+ static const MCPhysReg CCR[] = { >+ AArch64_NZCV, >+ }; >+ >+ // CCR Bit set. >+ static const uint8_t CCRBits[] = { >+ 0x08, >+ }; >+ >+ // GPR32sponly Register Class... >+ static const MCPhysReg GPR32sponly[] = { >+ AArch64_WSP, >+ }; >+ >+ // GPR32sponly Bit set. >+ static const uint8_t GPR32sponlyBits[] = { >+ 0x20, >+ }; >+ >+ // GPR64all Register Class... >+ static const MCPhysReg GPR64all[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP, >+ }; >+ >+ // GPR64all Bit set. >+ static const uint8_t GPR64allBits[] = { >+ 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // FPR64 Register Class... >+ static const MCPhysReg FPR64[] = { >+ AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31, >+ }; >+ >+ // FPR64 Bit set. >+ static const uint8_t FPR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, >+ }; >+ >+ // GPR64 Register Class... >+ static const MCPhysReg GPR64[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, >+ }; >+ >+ // GPR64 Bit set. >+ static const uint8_t GPR64Bits[] = { >+ 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // GPR64sp Register Class... >+ static const MCPhysReg GPR64sp[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP, >+ }; >+ >+ // GPR64sp Bit set. >+ static const uint8_t GPR64spBits[] = { >+ 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // GPR64common Register Class... >+ static const MCPhysReg GPR64common[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, >+ }; >+ >+ // GPR64common Bit set. >+ static const uint8_t GPR64commonBits[] = { >+ 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // tcGPR64 Register Class... >+ static const MCPhysReg tcGPR64[] = { >+ AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, >+ }; >+ >+ // tcGPR64 Bit set. >+ static const uint8_t tcGPR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, >+ }; >+ >+ // GPR64sponly Register Class... >+ static const MCPhysReg GPR64sponly[] = { >+ AArch64_SP, >+ }; >+ >+ // GPR64sponly Bit set. >+ static const uint8_t GPR64sponlyBits[] = { >+ 0x10, >+ }; >+ >+ // DD Register Class... >+ static const MCPhysReg DD[] = { >+ AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0, >+ }; >+ >+ // DD Bit set. >+ static const uint8_t DDBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // FPR128 Register Class... >+ static const MCPhysReg FPR128[] = { >+ AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31, >+ }; >+ >+ // FPR128 Bit set. >+ static const uint8_t FPR128Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, >+ }; >+ >+ // FPR128_lo Register Class... >+ static const MCPhysReg FPR128_lo[] = { >+ AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, >+ }; >+ >+ // FPR128_lo Bit set. >+ static const uint8_t FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, >+ }; >+ >+ // DDD Register Class... >+ static const MCPhysReg DDD[] = { >+ AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1, >+ }; >+ >+ // DDD Bit set. >+ static const uint8_t DDDBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // DDDD Register Class... >+ static const MCPhysReg DDDD[] = { >+ AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2, >+ }; >+ >+ // DDDD Bit set. >+ static const uint8_t DDDDBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // QQ Register Class... >+ static const MCPhysReg QQ[] = { >+ AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0, >+ }; >+ >+ // QQ Bit set. >+ static const uint8_t QQBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // QQ_with_qsub0_in_FPR128_lo Register Class... >+ static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = { >+ AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, >+ }; >+ >+ // QQ_with_qsub0_in_FPR128_lo Bit set. >+ static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, >+ }; >+ >+ // QQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0, >+ }; >+ >+ // QQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, >+ }; >+ >+ // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, >+ }; >+ >+ // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, >+ }; >+ >+ // QQQ Register Class... >+ static const MCPhysReg QQQ[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, >+ }; >+ >+ // QQQ Bit set. >+ static const uint8_t QQQBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, >+ }; >+ >+ // QQQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1, >+ }; >+ >+ // QQQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, >+ }; >+ >+ // QQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, >+ }; >+ >+ // QQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, >+ }; >+ >+ // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1, >+ }; >+ >+ // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, >+ }; >+ >+ // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, >+ }; >+ >+ // QQQQ Register Class... >+ static const MCPhysReg QQQQ[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ Bit set. >+ static const uint8_t QQQQBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, >+ }; >+ >+ // QQQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, >+ }; >+ >+ // QQQQ_with_qsub3_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub3_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, >+ }; >+ >+ // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2, >+ }; >+ >+ // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... >+ static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { >+ AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, >+ }; >+ >+ // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. >+ static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, >+ }; >+ >+static const MCRegisterClass AArch64MCRegisterClasses[] = { >+ { "FPR8", FPR8, FPR8Bits, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 }, >+ { "FPR16", FPR16, FPR16Bits, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 }, >+ { "GPR32all", GPR32all, GPR32allBits, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 }, >+ { "FPR32", FPR32, FPR32Bits, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 }, >+ { "GPR32", GPR32, GPR32Bits, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 }, >+ { "GPR32sp", GPR32sp, GPR32spBits, 32, sizeof(GPR32spBits), AArch64_GPR32spRegClassID, 4, 4, 1, 1 }, >+ { "GPR32common", GPR32common, GPR32commonBits, 31, sizeof(GPR32commonBits), AArch64_GPR32commonRegClassID, 4, 4, 1, 1 }, >+ { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 }, >+ { "GPR32sponly", GPR32sponly, GPR32sponlyBits, 1, sizeof(GPR32sponlyBits), AArch64_GPR32sponlyRegClassID, 4, 4, 1, 1 }, >+ { "GPR64all", GPR64all, GPR64allBits, 33, sizeof(GPR64allBits), AArch64_GPR64allRegClassID, 8, 8, 1, 1 }, >+ { "FPR64", FPR64, FPR64Bits, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 }, >+ { "GPR64", GPR64, GPR64Bits, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 }, >+ { "GPR64sp", GPR64sp, GPR64spBits, 32, sizeof(GPR64spBits), AArch64_GPR64spRegClassID, 8, 8, 1, 1 }, >+ { "GPR64common", GPR64common, GPR64commonBits, 31, sizeof(GPR64commonBits), AArch64_GPR64commonRegClassID, 8, 8, 1, 1 }, >+ { "tcGPR64", tcGPR64, tcGPR64Bits, 19, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 }, >+ { "GPR64sponly", GPR64sponly, GPR64sponlyBits, 1, sizeof(GPR64sponlyBits), AArch64_GPR64sponlyRegClassID, 8, 8, 1, 1 }, >+ { "DD", DD, DDBits, 32, sizeof(DDBits), AArch64_DDRegClassID, 16, 8, 1, 1 }, >+ { "FPR128", FPR128, FPR128Bits, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 }, >+ { "FPR128_lo", FPR128_lo, FPR128_loBits, 16, sizeof(FPR128_loBits), AArch64_FPR128_loRegClassID, 16, 16, 1, 1 }, >+ { "DDD", DDD, DDDBits, 32, sizeof(DDDBits), AArch64_DDDRegClassID, 24, 8, 1, 1 }, >+ { "DDDD", DDDD, DDDDBits, 32, sizeof(DDDDBits), AArch64_DDDDRegClassID, 32, 8, 1, 1 }, >+ { "QQ", QQ, QQBits, 32, sizeof(QQBits), AArch64_QQRegClassID, 32, 16, 1, 1 }, >+ { "QQ_with_qsub0_in_FPR128_lo", QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 }, >+ { "QQ_with_qsub1_in_FPR128_lo", QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 }, >+ { "QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo", QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 }, >+ { "QQQ", QQQ, QQQBits, 32, sizeof(QQQBits), AArch64_QQQRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub0_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub1_in_FPR128_lo", QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 }, >+ { "QQQQ", QQQQ, QQQQBits, 32, sizeof(QQQQBits), AArch64_QQQQRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub0_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub1_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+ { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 }, >+}; >+ >+#endif // GET_REGINFO_MC_DESC >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenSubtargetInfo.inc b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenSubtargetInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..b27093eacc17ae9e26d285cf485299330937f1e6 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64GenSubtargetInfo.inc >@@ -0,0 +1,29 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Subtarget Enumeration Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_SUBTARGETINFO_ENUM >+#undef GET_SUBTARGETINFO_ENUM >+ >+enum { >+ AArch64_FeatureCRC = 1ULL << 0, >+ AArch64_FeatureCrypto = 1ULL << 1, >+ AArch64_FeatureFPARMv8 = 1ULL << 2, >+ AArch64_FeatureNEON = 1ULL << 3, >+ AArch64_FeatureZCRegMove = 1ULL << 4, >+ AArch64_FeatureZCZeroing = 1ULL << 5, >+ AArch64_ProcA53 = 1ULL << 6, >+ AArch64_ProcA57 = 1ULL << 7, >+ AArch64_ProcCyclone = 1ULL << 8 >+}; >+ >+#endif // GET_SUBTARGETINFO_ENUM >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.c b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.c >new file mode 100644 >index 0000000000000000000000000000000000000000..0314e56d6dbde797ffdedb23db2214b59947aba5 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.c >@@ -0,0 +1,1397 @@ >+//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an AArch64 MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM64 >+ >+#include <platform.h> >+#include <stdio.h> >+#include <stdlib.h> >+ >+#include "AArch64InstPrinter.h" >+#include "AArch64BaseInfo.h" >+#include "../../utils.h" >+#include "../../MCInst.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "../../MathExtras.h" >+ >+#include "AArch64Mapping.h" >+#include "AArch64AddressingModes.h" >+ >+#define GET_REGINFO_ENUM >+#include "AArch64GenRegisterInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "AArch64GenInstrInfo.inc" >+ >+ >+static const char *getRegisterName(unsigned RegNo, int AltIdx); >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); >+static bool printSysAlias(MCInst *MI, SStream *O); >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info); >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); >+static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ MI->csh->doing_mem = status; >+ >+ if (status) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = 0; >+ } else { >+ // done, create the next operand slot >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+void AArch64_printInst(MCInst *MI, SStream *O, void *Info) >+{ >+ // Check for special encodings and print the canonical alias instead. >+ unsigned Opcode = MCInst_getOpcode(MI); >+ int LSB; >+ int Width; >+ char *mnem; >+ >+ if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) >+ return; >+ >+ // SBFM/UBFM should print to a nicer aliased form if possible. >+ if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || >+ Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { >+ MCOperand *Op0 = MCInst_getOperand(MI, 0); >+ MCOperand *Op1 = MCInst_getOperand(MI, 1); >+ MCOperand *Op2 = MCInst_getOperand(MI, 2); >+ MCOperand *Op3 = MCInst_getOperand(MI, 3); >+ >+ bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); >+ bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); >+ >+ if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { >+ const char *AsmMnemonic = NULL; >+ >+ switch (MCOperand_getImm(Op3)) { >+ default: >+ break; >+ case 7: >+ if (IsSigned) >+ AsmMnemonic = "sxtb"; >+ else if (!Is64Bit) >+ AsmMnemonic = "uxtb"; >+ break; >+ case 15: >+ if (IsSigned) >+ AsmMnemonic = "sxth"; >+ else if (!Is64Bit) >+ AsmMnemonic = "uxth"; >+ break; >+ case 31: >+ // *xtw is only valid for signed 64-bit operations. >+ if (Is64Bit && IsSigned) >+ AsmMnemonic = "sxtw"; >+ break; >+ } >+ >+ if (AsmMnemonic) { >+ SStream_concat(O, "%s\t%s, %s", AsmMnemonic, >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1)); >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); >+ >+ return; >+ } >+ } >+ >+ // All immediate shifts are aliases, implemented using the Bitfield >+ // instruction. In all cases the immediate shift amount shift must be in >+ // the range 0 to (reg.size -1). >+ if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) { >+ const char *AsmMnemonic = NULL; >+ int shift = 0; >+ int immr = (int)MCOperand_getImm(Op2); >+ int imms = (int)MCOperand_getImm(Op3); >+ >+ if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { >+ AsmMnemonic = "lsl"; >+ shift = 31 - imms; >+ } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && >+ ((imms + 1 == immr))) { >+ AsmMnemonic = "lsl"; >+ shift = 63 - imms; >+ } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { >+ AsmMnemonic = "lsr"; >+ shift = immr; >+ } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { >+ AsmMnemonic = "lsr"; >+ shift = immr; >+ } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { >+ AsmMnemonic = "asr"; >+ shift = immr; >+ } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { >+ AsmMnemonic = "asr"; >+ shift = immr; >+ } >+ >+ if (AsmMnemonic) { >+ SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic, >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); >+ >+ printInt32Bang(O, shift); >+ >+ MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ return; >+ } >+ } >+ >+ // SBFIZ/UBFIZ aliases >+ if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) { >+ SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); >+ printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); >+ SStream_concat0(O, ", "); >+ printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); >+ >+ MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ return; >+ } >+ >+ // Otherwise SBFX/UBFX is the preferred form >+ SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); >+ printInt32Bang(O, (int)MCOperand_getImm(Op2)); >+ SStream_concat0(O, ", "); >+ printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); >+ >+ MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx")); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ return; >+ } >+ >+ if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) { >+ MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0 >+ MCOperand *Op2 = MCInst_getOperand(MI, 2); >+ int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); >+ int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); >+ >+ // BFI alias >+ if (ImmS < ImmR) { >+ int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; >+ LSB = (BitWidth - ImmR) % BitWidth; >+ Width = ImmS + 1; >+ >+ SStream_concat(O, "bfi\t%s, %s, ", >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); >+ printInt32Bang(O, LSB); >+ SStream_concat0(O, ", "); >+ printInt32Bang(O, Width); >+ MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ return; >+ } >+ >+ LSB = ImmR; >+ Width = ImmS - ImmR + 1; >+ // Otherwise BFXIL the preferred form >+ SStream_concat(O, "bfxil\t%s, %s, ", >+ getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), >+ getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); >+ printInt32Bang(O, LSB); >+ SStream_concat0(O, ", "); >+ printInt32Bang(O, Width); >+ MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2); >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; >+ MI->flat_insn->detail->arm64.op_count++; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ return; >+ } >+ >+ mnem = printAliasInstr(MI, O, Info); >+ if (mnem) { >+ MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); >+ cs_mem_free(mnem); >+ } else { >+ printInstruction(MI, O, Info); >+ } >+} >+ >+static bool printSysAlias(MCInst *MI, SStream *O) >+{ >+ // unsigned Opcode = MCInst_getOpcode(MI); >+ //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); >+ >+ const char *Asm = NULL; >+ MCOperand *Op1 = MCInst_getOperand(MI, 0); >+ MCOperand *Cn = MCInst_getOperand(MI, 1); >+ MCOperand *Cm = MCInst_getOperand(MI, 2); >+ MCOperand *Op2 = MCInst_getOperand(MI, 3); >+ >+ unsigned Op1Val = (unsigned)MCOperand_getImm(Op1); >+ unsigned CnVal = (unsigned)MCOperand_getImm(Cn); >+ unsigned CmVal = (unsigned)MCOperand_getImm(Cm); >+ unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); >+ unsigned insn_id = ARM64_INS_INVALID; >+ unsigned op_ic = 0, op_dc = 0, op_at = 0, op_tlbi = 0; >+ >+ if (CnVal == 7) { >+ switch (CmVal) { >+ default: >+ break; >+ >+ // IC aliases >+ case 1: >+ if (Op1Val == 0 && Op2Val == 0) { >+ Asm = "ic\tialluis"; >+ insn_id = ARM64_INS_IC; >+ op_ic = ARM64_IC_IALLUIS; >+ } >+ break; >+ case 5: >+ if (Op1Val == 0 && Op2Val == 0) { >+ Asm = "ic\tiallu"; >+ insn_id = ARM64_INS_IC; >+ op_ic = ARM64_IC_IALLU; >+ } else if (Op1Val == 3 && Op2Val == 1) { >+ Asm = "ic\tivau"; >+ insn_id = ARM64_INS_IC; >+ op_ic = ARM64_IC_IVAU; >+ } >+ break; >+ >+ // DC aliases >+ case 4: >+ if (Op1Val == 3 && Op2Val == 1) { >+ Asm = "dc\tzva"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_ZVA; >+ } >+ break; >+ case 6: >+ if (Op1Val == 0 && Op2Val == 1) { >+ Asm = "dc\tivac"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_IVAC; >+ } >+ if (Op1Val == 0 && Op2Val == 2) { >+ Asm = "dc\tisw"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_ISW; >+ } >+ break; >+ case 10: >+ if (Op1Val == 3 && Op2Val == 1) { >+ Asm = "dc\tcvac"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_CVAC; >+ } else if (Op1Val == 0 && Op2Val == 2) { >+ Asm = "dc\tcsw"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_CSW; >+ } >+ break; >+ case 11: >+ if (Op1Val == 3 && Op2Val == 1) { >+ Asm = "dc\tcvau"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_CVAU; >+ } >+ break; >+ case 14: >+ if (Op1Val == 3 && Op2Val == 1) { >+ Asm = "dc\tcivac"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_CIVAC; >+ } else if (Op1Val == 0 && Op2Val == 2) { >+ Asm = "dc\tcisw"; >+ insn_id = ARM64_INS_DC; >+ op_dc = ARM64_DC_CISW; >+ } >+ break; >+ >+ // AT aliases >+ case 8: >+ switch (Op1Val) { >+ default: >+ break; >+ case 0: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "at\ts1e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; >+ case 1: Asm = "at\ts1e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; >+ case 2: Asm = "at\ts1e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; >+ case 3: Asm = "at\ts1e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; >+ } >+ break; >+ case 4: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "at\ts1e2r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2R; break; >+ case 1: Asm = "at\ts1e2w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2W; break; >+ case 4: Asm = "at\ts12e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; >+ case 5: Asm = "at\ts12e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; >+ case 6: Asm = "at\ts12e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; >+ case 7: Asm = "at\ts12e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; >+ } >+ break; >+ case 6: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "at\ts1e3r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3R; break; >+ case 1: Asm = "at\ts1e3w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3W; break; >+ } >+ break; >+ } >+ break; >+ } >+ } else if (CnVal == 8) { >+ // TLBI aliases >+ switch (CmVal) { >+ default: >+ break; >+ case 3: >+ switch (Op1Val) { >+ default: >+ break; >+ case 0: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\tvmalle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1IS; break; >+ case 1: Asm = "tlbi\tvae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1IS; break; >+ case 2: Asm = "tlbi\taside1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1IS; break; >+ case 3: Asm = "tlbi\tvaae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1IS; break; >+ case 5: Asm = "tlbi\tvale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1IS; break; >+ case 7: Asm = "tlbi\tvaale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1IS; break; >+ } >+ break; >+ case 4: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\talle2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2IS; break; >+ case 1: Asm = "tlbi\tvae2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2IS; break; >+ case 4: Asm = "tlbi\talle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1IS; break; >+ case 5: Asm = "tlbi\tvale2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2IS; break; >+ case 6: Asm = "tlbi\tvmalls12e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1IS; break; >+ } >+ break; >+ case 6: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\talle3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3IS; break; >+ case 1: Asm = "tlbi\tvae3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3IS; break; >+ case 5: Asm = "tlbi\tvale3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3IS; break; >+ } >+ break; >+ } >+ break; >+ case 0: >+ switch (Op1Val) { >+ default: >+ break; >+ case 4: >+ switch (Op2Val) { >+ default: >+ break; >+ case 1: Asm = "tlbi\tipas2e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1IS; break; >+ case 5: Asm = "tlbi\tipas2le1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1IS; break; >+ } >+ break; >+ } >+ break; >+ case 4: >+ switch (Op1Val) { >+ default: >+ break; >+ case 4: >+ switch (Op2Val) { >+ default: >+ break; >+ case 1: Asm = "tlbi\tipas2e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1; break; >+ case 5: Asm = "tlbi\tipas2le1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1; break; >+ } >+ break; >+ } >+ break; >+ case 7: >+ switch (Op1Val) { >+ default: >+ break; >+ case 0: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\tvmalle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1; break; >+ case 1: Asm = "tlbi\tvae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1; break; >+ case 2: Asm = "tlbi\taside1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1; break; >+ case 3: Asm = "tlbi\tvaae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1; break; >+ case 5: Asm = "tlbi\tvale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1; break; >+ case 7: Asm = "tlbi\tvaale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1; break; >+ } >+ break; >+ case 4: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\talle2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2; break; >+ case 1: Asm = "tlbi\tvae2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2; break; >+ case 4: Asm = "tlbi\talle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1; break; >+ case 5: Asm = "tlbi\tvale2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2; break; >+ case 6: Asm = "tlbi\tvmalls12e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1; break; >+ } >+ break; >+ case 6: >+ switch (Op2Val) { >+ default: >+ break; >+ case 0: Asm = "tlbi\talle3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3; break; >+ case 1: Asm = "tlbi\tvae3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3; break; >+ case 5: Asm = "tlbi\tvale3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3; break; >+ } >+ break; >+ } >+ break; >+ } >+ } >+ >+ if (Asm) { >+ MCInst_setOpcodePub(MI, insn_id); >+ SStream_concat0(O, Asm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = op_ic + op_dc + op_at + op_tlbi; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ if (!strstr(Asm, "all")) { >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); >+ SStream_concat(O, ", %s", getRegisterName(Reg, AArch64_NoRegAltName)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ } >+ >+ return Asm != NULL; >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ >+ if (MCOperand_isReg(Op)) { >+ unsigned Reg = MCOperand_getReg(Op); >+ SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg; >+ } >+ else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg; >+ } >+ } else { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ int64_t imm = MCOperand_getImm(Op); >+ >+ if (MI->Opcode == AArch64_ADR) { >+ imm += MI->address; >+ printUInt64Bang(O, imm); >+ } else >+ printUInt64Bang(O, imm); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm; >+ } else { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ } >+} >+ >+static void printHexImm(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ SStream_concat(O, "#%#llx", MCOperand_getImm(Op)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printPostIncOperand(MCInst *MI, unsigned OpNo, >+ unsigned Imm, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ >+ if (MCOperand_isReg(Op)) { >+ unsigned Reg = MCOperand_getReg(Op); >+ if (Reg == AArch64_XZR) { >+ printInt32Bang(O, Imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } else { >+ SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ } >+ //llvm_unreachable("unknown operand kind in printPostIncOperand64"); >+} >+ >+static void printPostIncOperand2(MCInst *MI, unsigned OpNo, SStream *O, int Amount) >+{ >+ printPostIncOperand(MI, OpNo, Amount, O); >+} >+ >+static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ //assert(Op.isReg() && "Non-register vreg operand!"); >+ unsigned Reg = MCOperand_getReg(Op); >+ SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); >+ SStream_concat(O, "c%u", MCOperand_getImm(Op)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op); >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ if (MCOperand_isImm(MO)) { >+ unsigned Val = (MCOperand_getImm(MO) & 0xfff); >+ //assert(Val == MO.getImm() && "Add/sub immediate out of range!"); >+ unsigned Shift = AArch64_AM_getShiftValue((int)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1))); >+ >+ printInt32Bang(O, Val); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ if (Shift != 0) >+ printShifter(MI, OpNum + 1, O); >+ } >+} >+ >+static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ Val = AArch64_AM_decodeLogicalImmediate(Val, 32); >+ printUInt32Bang(O, (int)Val); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ Val = AArch64_AM_decodeLogicalImmediate(Val, 64); >+ >+ switch(MI->flat_insn->id) { >+ default: >+ printInt64Bang(O, Val); >+ break; >+ case ARM64_INS_ORR: >+ case ARM64_INS_AND: >+ case ARM64_INS_EOR: >+ case ARM64_INS_TST: >+ // do not print number in negative form >+ if (Val >= 0 && Val <= HEX_THRESHOLD) >+ SStream_concat(O, "#%u", (int)Val); >+ else >+ SStream_concat(O, "#0x%"PRIx64, Val); >+ break; >+ } >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ // LSL #0 should not be printed. >+ if (AArch64_AM_getShiftType(Val) == AArch64_AM_LSL && >+ AArch64_AM_getShiftValue(Val) == 0) >+ return; >+ >+ SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); >+ printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); >+ if (MI->csh->detail) { >+ arm64_shifter shifter = ARM64_SFT_INVALID; >+ switch(AArch64_AM_getShiftType(Val)) { >+ default: // never reach >+ case AArch64_AM_LSL: >+ shifter = ARM64_SFT_LSL; >+ break; >+ case AArch64_AM_LSR: >+ shifter = ARM64_SFT_LSR; >+ break; >+ case AArch64_AM_ASR: >+ shifter = ARM64_SFT_ASR; >+ break; >+ case AArch64_AM_ROR: >+ shifter = ARM64_SFT_ROR; >+ break; >+ case AArch64_AM_MSL: >+ shifter = ARM64_SFT_MSL; >+ break; >+ } >+ >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = shifter; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = AArch64_AM_getShiftValue(Val); >+ } >+} >+ >+static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ printShifter(MI, OpNum + 1, O); >+} >+ >+static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); >+ unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val); >+ >+ // If the destination or first source register operand is [W]SP, print >+ // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at >+ // all. >+ if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { >+ unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); >+ unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); >+ if ( ((Dest == AArch64_SP || Src1 == AArch64_SP) && >+ ExtType == AArch64_AM_UXTX) || >+ ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && >+ ExtType == AArch64_AM_UXTW) ) { >+ if (ShiftVal != 0) { >+ SStream_concat0(O, ", lsl "); >+ printInt32Bang(O, ShiftVal); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; >+ } >+ } >+ >+ return; >+ } >+ } >+ >+ SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); >+ if (MI->csh->detail) { >+ arm64_extender ext = ARM64_EXT_INVALID; >+ switch(ExtType) { >+ default: // never reach >+ case AArch64_AM_UXTB: >+ ext = ARM64_EXT_UXTB; >+ break; >+ case AArch64_AM_UXTH: >+ ext = ARM64_EXT_UXTH; >+ break; >+ case AArch64_AM_UXTW: >+ ext = ARM64_EXT_UXTW; >+ break; >+ case AArch64_AM_UXTX: >+ ext = ARM64_EXT_UXTX; >+ break; >+ case AArch64_AM_SXTB: >+ ext = ARM64_EXT_SXTB; >+ break; >+ case AArch64_AM_SXTH: >+ ext = ARM64_EXT_SXTH; >+ break; >+ case AArch64_AM_SXTW: >+ ext = ARM64_EXT_SXTW; >+ break; >+ case AArch64_AM_SXTX: >+ ext = ARM64_EXT_SXTX; >+ break; >+ } >+ >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext; >+ } >+ >+ if (ShiftVal != 0) { >+ SStream_concat0(O, " "); >+ printInt32Bang(O, ShiftVal); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; >+ } >+ } >+} >+ >+static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ >+ SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ >+ printArithExtend(MI, OpNum + 1, O); >+} >+ >+static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind, unsigned Width) >+{ >+ unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); >+ >+ // sxtw, sxtx, uxtw or lsl (== uxtx) >+ bool IsLSL = !SignExtend && SrcRegKind == 'x'; >+ if (IsLSL) { >+ SStream_concat0(O, "lsl"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; >+ } >+ } else { >+ SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); >+ if (MI->csh->detail) { >+ if (!SignExtend) { >+ switch(SrcRegKind) { >+ default: break; >+ case 'b': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTB; >+ break; >+ case 'h': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTH; >+ break; >+ case 'w': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_UXTW; >+ break; >+ } >+ } else { >+ switch(SrcRegKind) { >+ default: break; >+ case 'b': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTB; >+ break; >+ case 'h': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTH; >+ break; >+ case 'w': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTW; >+ break; >+ case 'x': >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].ext = ARM64_EXT_SXTX; >+ break; >+ } >+ } >+ } >+ } >+ >+ if (DoShift || IsLSL) { >+ SStream_concat(O, " #%u", Log2_32(Width / 8)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); >+ } >+ } >+} >+ >+static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, getCondCodeName(CC)); >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm64.cc = (arm64_cc)(CC + 1); >+} >+ >+static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.cc = (arm64_cc)(getInvertedCondCode(CC) + 1); >+ } >+} >+ >+static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) >+{ >+ int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ printInt64Bang(O, val); >+ >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; >+ } else { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+} >+ >+static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ >+ if (MCOperand_isImm(MO)) { >+ int64_t val = Scale * MCOperand_getImm(MO); >+ printInt64Bang(O, val); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; >+ } else { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ } >+} >+ >+static void printUImm12Offset2(MCInst *MI, unsigned OpNum, SStream *O, int Scale) >+{ >+ printUImm12Offset(MI, OpNum, Scale, O); >+} >+ >+static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ bool Valid; >+ const char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid); >+ >+ if (Valid) { >+ SStream_concat0(O, Name); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PREFETCH; >+ // we have to plus 1 to prfop because 0 is a valid value of prfop >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].prefetch = prfop + 1; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } else { >+ printInt32Bang(O, prfop); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+} >+ >+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ double FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); >+ >+ // 8 decimal places are enough to perfectly represent permitted floats. >+#if defined(_KERNEL_MODE) >+ // Issue #681: Windows kernel does not support formatting float point >+ SStream_concat(O, "#<float_point_unsupported>"); >+#else >+ SStream_concat(O, "#%.8f", FPImm); >+#endif >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+//static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) >+static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) >+{ >+ while (Stride--) { >+ switch (Reg) { >+ default: >+ // llvm_unreachable("Vector register expected!"); >+ case AArch64_Q0: Reg = AArch64_Q1; break; >+ case AArch64_Q1: Reg = AArch64_Q2; break; >+ case AArch64_Q2: Reg = AArch64_Q3; break; >+ case AArch64_Q3: Reg = AArch64_Q4; break; >+ case AArch64_Q4: Reg = AArch64_Q5; break; >+ case AArch64_Q5: Reg = AArch64_Q6; break; >+ case AArch64_Q6: Reg = AArch64_Q7; break; >+ case AArch64_Q7: Reg = AArch64_Q8; break; >+ case AArch64_Q8: Reg = AArch64_Q9; break; >+ case AArch64_Q9: Reg = AArch64_Q10; break; >+ case AArch64_Q10: Reg = AArch64_Q11; break; >+ case AArch64_Q11: Reg = AArch64_Q12; break; >+ case AArch64_Q12: Reg = AArch64_Q13; break; >+ case AArch64_Q13: Reg = AArch64_Q14; break; >+ case AArch64_Q14: Reg = AArch64_Q15; break; >+ case AArch64_Q15: Reg = AArch64_Q16; break; >+ case AArch64_Q16: Reg = AArch64_Q17; break; >+ case AArch64_Q17: Reg = AArch64_Q18; break; >+ case AArch64_Q18: Reg = AArch64_Q19; break; >+ case AArch64_Q19: Reg = AArch64_Q20; break; >+ case AArch64_Q20: Reg = AArch64_Q21; break; >+ case AArch64_Q21: Reg = AArch64_Q22; break; >+ case AArch64_Q22: Reg = AArch64_Q23; break; >+ case AArch64_Q23: Reg = AArch64_Q24; break; >+ case AArch64_Q24: Reg = AArch64_Q25; break; >+ case AArch64_Q25: Reg = AArch64_Q26; break; >+ case AArch64_Q26: Reg = AArch64_Q27; break; >+ case AArch64_Q27: Reg = AArch64_Q28; break; >+ case AArch64_Q28: Reg = AArch64_Q29; break; >+ case AArch64_Q29: Reg = AArch64_Q30; break; >+ case AArch64_Q30: Reg = AArch64_Q31; break; >+ // Vector lists can wrap around. >+ case AArch64_Q31: Reg = AArch64_Q0; break; >+ } >+ } >+ >+ return Reg; >+} >+ >+static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess) >+{ >+#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) >+ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned NumRegs = 1, FirstReg, i; >+ >+ SStream_concat0(O, "{"); >+ >+ // Work out how many registers there are in the list (if there is an actual >+ // list). >+ if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || >+ GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) >+ NumRegs = 2; >+ else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || >+ GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) >+ NumRegs = 3; >+ else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || >+ GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) >+ NumRegs = 4; >+ >+ // Now forget about the list and find out what the first register is. >+ if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0))) >+ Reg = FirstReg; >+ else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) >+ Reg = FirstReg; >+ >+ // If it's a D-reg, we need to promote it to the equivalent Q-reg before >+ // printing (otherwise getRegisterName fails). >+ if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) { >+ const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID); >+ Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC); >+ } >+ >+ for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { >+ SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); >+ if (i + 1 != NumRegs) >+ SStream_concat0(O, ", "); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+ >+ SStream_concat0(O, "}"); >+} >+ >+static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI) >+{ >+ char Suffix[32]; >+ arm64_vas vas = 0; >+ arm64_vess vess = 0; >+ >+ if (NumLanes) { >+ cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); >+ switch(LaneKind) { >+ default: break; >+ case 'b': >+ switch(NumLanes) { >+ default: break; >+ case 8: >+ vas = ARM64_VAS_8B; >+ break; >+ case 16: >+ vas = ARM64_VAS_16B; >+ break; >+ } >+ break; >+ case 'h': >+ switch(NumLanes) { >+ default: break; >+ case 4: >+ vas = ARM64_VAS_4H; >+ break; >+ case 8: >+ vas = ARM64_VAS_8H; >+ break; >+ } >+ break; >+ case 's': >+ switch(NumLanes) { >+ default: break; >+ case 2: >+ vas = ARM64_VAS_2S; >+ break; >+ case 4: >+ vas = ARM64_VAS_4S; >+ break; >+ } >+ break; >+ case 'd': >+ switch(NumLanes) { >+ default: break; >+ case 1: >+ vas = ARM64_VAS_1D; >+ break; >+ case 2: >+ vas = ARM64_VAS_2D; >+ break; >+ } >+ break; >+ case 'q': >+ switch(NumLanes) { >+ default: break; >+ case 1: >+ vas = ARM64_VAS_1Q; >+ break; >+ } >+ break; >+ } >+ } else { >+ cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); >+ switch(LaneKind) { >+ default: break; >+ case 'b': >+ vess = ARM64_VESS_B; >+ break; >+ case 'h': >+ vess = ARM64_VESS_H; >+ break; >+ case 's': >+ vess = ARM64_VESS_S; >+ break; >+ case 'd': >+ vess = ARM64_VESS_D; >+ break; >+ } >+ } >+ >+ printVectorList(MI, OpNum, O, Suffix, MRI, vas, vess); >+} >+ >+static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ SStream_concat0(O, "["); >+ printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); >+ SStream_concat0(O, "]"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ } >+} >+ >+static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ >+ // If the label has already been resolved to an immediate offset (say, when >+ // we're running the disassembler), just print the immediate. >+ if (MCOperand_isImm(Op)) { >+ uint64_t imm = (MCOperand_getImm(Op) << 2) + MI->address; >+ printUInt64Bang(O, imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ return; >+ } >+} >+ >+static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ >+ if (MCOperand_isImm(Op)) { >+ // ADRP sign extends a 21-bit offset, shifts it left by 12 >+ // and adds it to the value of the PC with its bottom 12 bits cleared >+ uint64_t imm = (MCOperand_getImm(Op) << 12) + (MI->address & ~0xfff); >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "#%"PRIu64, imm); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ return; >+ } >+} >+ >+static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); >+ unsigned Opcode = MCInst_getOpcode(MI); >+ bool Valid; >+ const char *Name; >+ >+ if (Opcode == AArch64_ISB) >+ Name = A64NamedImmMapper_toString(&A64ISB_ISBMapper, Val, &Valid); >+ else >+ Name = A64NamedImmMapper_toString(&A64DB_DBarrierMapper, Val, &Valid); >+ >+ if (Valid) { >+ SStream_concat0(O, Name); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } else { >+ printUInt32Bang(O, Val); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+} >+ >+static void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); >+ bool Valid; >+ char Name[128]; >+ >+ A64SysRegMapper_toString(&AArch64_MRSMapper, Val, &Valid, Name); >+ >+ if (Valid) { >+ SStream_concat0(O, Name); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+} >+ >+static void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); >+ bool Valid; >+ char Name[128]; >+ >+ A64SysRegMapper_toString(&AArch64_MSRMapper, Val, &Valid, Name); >+ >+ if (Valid) { >+ SStream_concat0(O, Name); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MSR; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } >+} >+ >+static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); >+ bool Valid; >+ const char *Name; >+ >+ Name = A64NamedImmMapper_toString(&A64PState_PStateMapper, Val, &Valid); >+ if (Valid) { >+ SStream_concat0(O, Name); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+ } else { >+ printInt32Bang(O, Val); >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); >+ uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); >+ SStream_concat(O, "#%#016llx", Val); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+ >+#define PRINT_ALIAS_INSTR >+#include "AArch64GenAsmWriter.inc" >+ >+void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) >+{ >+ if (((cs_struct *)handle)->detail != CS_OPT_ON) >+ return; >+ >+ // check if this insn requests write-back >+ if (strrchr(insn_asm, '!') != NULL) >+ flat_insn->detail->arm64.writeback = true; >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.h b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.h >new file mode 100644 >index 0000000000000000000000000000000000000000..46bbe7f1995ef2a36fcb80a14d21b225cde7688e >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64InstPrinter.h >@@ -0,0 +1,28 @@ >+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an AArch64 MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_AARCH64INSTPRINTER_H >+#define CS_LLVM_AARCH64INSTPRINTER_H >+ >+#include "../../MCInst.h" >+#include "../../MCRegisterInfo.h" >+#include "../../SStream.h" >+ >+void AArch64_printInst(MCInst *MI, SStream *O, void *); >+ >+void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.c b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.c >new file mode 100644 >index 0000000000000000000000000000000000000000..fac372353f44ac461d4eed0f90b6a4e5611a6607 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.c >@@ -0,0 +1,14975 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM64 >+ >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "../../utils.h" >+ >+#include "AArch64Mapping.h" >+ >+#define GET_INSTRINFO_ENUM >+#include "AArch64GenInstrInfo.inc" >+ >+#ifndef CAPSTONE_DIET >+static const name_map reg_name_maps[] = { >+ { ARM64_REG_INVALID, NULL }, >+ >+ { ARM64_REG_X29, "x29"}, >+ { ARM64_REG_X30, "x30"}, >+ { ARM64_REG_NZCV, "nzcv"}, >+ { ARM64_REG_SP, "sp"}, >+ { ARM64_REG_WSP, "wsp"}, >+ { ARM64_REG_WZR, "wzr"}, >+ { ARM64_REG_XZR, "xzr"}, >+ { ARM64_REG_B0, "b0"}, >+ { ARM64_REG_B1, "b1"}, >+ { ARM64_REG_B2, "b2"}, >+ { ARM64_REG_B3, "b3"}, >+ { ARM64_REG_B4, "b4"}, >+ { ARM64_REG_B5, "b5"}, >+ { ARM64_REG_B6, "b6"}, >+ { ARM64_REG_B7, "b7"}, >+ { ARM64_REG_B8, "b8"}, >+ { ARM64_REG_B9, "b9"}, >+ { ARM64_REG_B10, "b10"}, >+ { ARM64_REG_B11, "b11"}, >+ { ARM64_REG_B12, "b12"}, >+ { ARM64_REG_B13, "b13"}, >+ { ARM64_REG_B14, "b14"}, >+ { ARM64_REG_B15, "b15"}, >+ { ARM64_REG_B16, "b16"}, >+ { ARM64_REG_B17, "b17"}, >+ { ARM64_REG_B18, "b18"}, >+ { ARM64_REG_B19, "b19"}, >+ { ARM64_REG_B20, "b20"}, >+ { ARM64_REG_B21, "b21"}, >+ { ARM64_REG_B22, "b22"}, >+ { ARM64_REG_B23, "b23"}, >+ { ARM64_REG_B24, "b24"}, >+ { ARM64_REG_B25, "b25"}, >+ { ARM64_REG_B26, "b26"}, >+ { ARM64_REG_B27, "b27"}, >+ { ARM64_REG_B28, "b28"}, >+ { ARM64_REG_B29, "b29"}, >+ { ARM64_REG_B30, "b30"}, >+ { ARM64_REG_B31, "b31"}, >+ { ARM64_REG_D0, "d0"}, >+ { ARM64_REG_D1, "d1"}, >+ { ARM64_REG_D2, "d2"}, >+ { ARM64_REG_D3, "d3"}, >+ { ARM64_REG_D4, "d4"}, >+ { ARM64_REG_D5, "d5"}, >+ { ARM64_REG_D6, "d6"}, >+ { ARM64_REG_D7, "d7"}, >+ { ARM64_REG_D8, "d8"}, >+ { ARM64_REG_D9, "d9"}, >+ { ARM64_REG_D10, "d10"}, >+ { ARM64_REG_D11, "d11"}, >+ { ARM64_REG_D12, "d12"}, >+ { ARM64_REG_D13, "d13"}, >+ { ARM64_REG_D14, "d14"}, >+ { ARM64_REG_D15, "d15"}, >+ { ARM64_REG_D16, "d16"}, >+ { ARM64_REG_D17, "d17"}, >+ { ARM64_REG_D18, "d18"}, >+ { ARM64_REG_D19, "d19"}, >+ { ARM64_REG_D20, "d20"}, >+ { ARM64_REG_D21, "d21"}, >+ { ARM64_REG_D22, "d22"}, >+ { ARM64_REG_D23, "d23"}, >+ { ARM64_REG_D24, "d24"}, >+ { ARM64_REG_D25, "d25"}, >+ { ARM64_REG_D26, "d26"}, >+ { ARM64_REG_D27, "d27"}, >+ { ARM64_REG_D28, "d28"}, >+ { ARM64_REG_D29, "d29"}, >+ { ARM64_REG_D30, "d30"}, >+ { ARM64_REG_D31, "d31"}, >+ { ARM64_REG_H0, "h0"}, >+ { ARM64_REG_H1, "h1"}, >+ { ARM64_REG_H2, "h2"}, >+ { ARM64_REG_H3, "h3"}, >+ { ARM64_REG_H4, "h4"}, >+ { ARM64_REG_H5, "h5"}, >+ { ARM64_REG_H6, "h6"}, >+ { ARM64_REG_H7, "h7"}, >+ { ARM64_REG_H8, "h8"}, >+ { ARM64_REG_H9, "h9"}, >+ { ARM64_REG_H10, "h10"}, >+ { ARM64_REG_H11, "h11"}, >+ { ARM64_REG_H12, "h12"}, >+ { ARM64_REG_H13, "h13"}, >+ { ARM64_REG_H14, "h14"}, >+ { ARM64_REG_H15, "h15"}, >+ { ARM64_REG_H16, "h16"}, >+ { ARM64_REG_H17, "h17"}, >+ { ARM64_REG_H18, "h18"}, >+ { ARM64_REG_H19, "h19"}, >+ { ARM64_REG_H20, "h20"}, >+ { ARM64_REG_H21, "h21"}, >+ { ARM64_REG_H22, "h22"}, >+ { ARM64_REG_H23, "h23"}, >+ { ARM64_REG_H24, "h24"}, >+ { ARM64_REG_H25, "h25"}, >+ { ARM64_REG_H26, "h26"}, >+ { ARM64_REG_H27, "h27"}, >+ { ARM64_REG_H28, "h28"}, >+ { ARM64_REG_H29, "h29"}, >+ { ARM64_REG_H30, "h30"}, >+ { ARM64_REG_H31, "h31"}, >+ { ARM64_REG_Q0, "q0"}, >+ { ARM64_REG_Q1, "q1"}, >+ { ARM64_REG_Q2, "q2"}, >+ { ARM64_REG_Q3, "q3"}, >+ { ARM64_REG_Q4, "q4"}, >+ { ARM64_REG_Q5, "q5"}, >+ { ARM64_REG_Q6, "q6"}, >+ { ARM64_REG_Q7, "q7"}, >+ { ARM64_REG_Q8, "q8"}, >+ { ARM64_REG_Q9, "q9"}, >+ { ARM64_REG_Q10, "q10"}, >+ { ARM64_REG_Q11, "q11"}, >+ { ARM64_REG_Q12, "q12"}, >+ { ARM64_REG_Q13, "q13"}, >+ { ARM64_REG_Q14, "q14"}, >+ { ARM64_REG_Q15, "q15"}, >+ { ARM64_REG_Q16, "q16"}, >+ { ARM64_REG_Q17, "q17"}, >+ { ARM64_REG_Q18, "q18"}, >+ { ARM64_REG_Q19, "q19"}, >+ { ARM64_REG_Q20, "q20"}, >+ { ARM64_REG_Q21, "q21"}, >+ { ARM64_REG_Q22, "q22"}, >+ { ARM64_REG_Q23, "q23"}, >+ { ARM64_REG_Q24, "q24"}, >+ { ARM64_REG_Q25, "q25"}, >+ { ARM64_REG_Q26, "q26"}, >+ { ARM64_REG_Q27, "q27"}, >+ { ARM64_REG_Q28, "q28"}, >+ { ARM64_REG_Q29, "q29"}, >+ { ARM64_REG_Q30, "q30"}, >+ { ARM64_REG_Q31, "q31"}, >+ { ARM64_REG_S0, "s0"}, >+ { ARM64_REG_S1, "s1"}, >+ { ARM64_REG_S2, "s2"}, >+ { ARM64_REG_S3, "s3"}, >+ { ARM64_REG_S4, "s4"}, >+ { ARM64_REG_S5, "s5"}, >+ { ARM64_REG_S6, "s6"}, >+ { ARM64_REG_S7, "s7"}, >+ { ARM64_REG_S8, "s8"}, >+ { ARM64_REG_S9, "s9"}, >+ { ARM64_REG_S10, "s10"}, >+ { ARM64_REG_S11, "s11"}, >+ { ARM64_REG_S12, "s12"}, >+ { ARM64_REG_S13, "s13"}, >+ { ARM64_REG_S14, "s14"}, >+ { ARM64_REG_S15, "s15"}, >+ { ARM64_REG_S16, "s16"}, >+ { ARM64_REG_S17, "s17"}, >+ { ARM64_REG_S18, "s18"}, >+ { ARM64_REG_S19, "s19"}, >+ { ARM64_REG_S20, "s20"}, >+ { ARM64_REG_S21, "s21"}, >+ { ARM64_REG_S22, "s22"}, >+ { ARM64_REG_S23, "s23"}, >+ { ARM64_REG_S24, "s24"}, >+ { ARM64_REG_S25, "s25"}, >+ { ARM64_REG_S26, "s26"}, >+ { ARM64_REG_S27, "s27"}, >+ { ARM64_REG_S28, "s28"}, >+ { ARM64_REG_S29, "s29"}, >+ { ARM64_REG_S30, "s30"}, >+ { ARM64_REG_S31, "s31"}, >+ { ARM64_REG_W0, "w0"}, >+ { ARM64_REG_W1, "w1"}, >+ { ARM64_REG_W2, "w2"}, >+ { ARM64_REG_W3, "w3"}, >+ { ARM64_REG_W4, "w4"}, >+ { ARM64_REG_W5, "w5"}, >+ { ARM64_REG_W6, "w6"}, >+ { ARM64_REG_W7, "w7"}, >+ { ARM64_REG_W8, "w8"}, >+ { ARM64_REG_W9, "w9"}, >+ { ARM64_REG_W10, "w10"}, >+ { ARM64_REG_W11, "w11"}, >+ { ARM64_REG_W12, "w12"}, >+ { ARM64_REG_W13, "w13"}, >+ { ARM64_REG_W14, "w14"}, >+ { ARM64_REG_W15, "w15"}, >+ { ARM64_REG_W16, "w16"}, >+ { ARM64_REG_W17, "w17"}, >+ { ARM64_REG_W18, "w18"}, >+ { ARM64_REG_W19, "w19"}, >+ { ARM64_REG_W20, "w20"}, >+ { ARM64_REG_W21, "w21"}, >+ { ARM64_REG_W22, "w22"}, >+ { ARM64_REG_W23, "w23"}, >+ { ARM64_REG_W24, "w24"}, >+ { ARM64_REG_W25, "w25"}, >+ { ARM64_REG_W26, "w26"}, >+ { ARM64_REG_W27, "w27"}, >+ { ARM64_REG_W28, "w28"}, >+ { ARM64_REG_W29, "w29"}, >+ { ARM64_REG_W30, "w30"}, >+ { ARM64_REG_X0, "x0"}, >+ { ARM64_REG_X1, "x1"}, >+ { ARM64_REG_X2, "x2"}, >+ { ARM64_REG_X3, "x3"}, >+ { ARM64_REG_X4, "x4"}, >+ { ARM64_REG_X5, "x5"}, >+ { ARM64_REG_X6, "x6"}, >+ { ARM64_REG_X7, "x7"}, >+ { ARM64_REG_X8, "x8"}, >+ { ARM64_REG_X9, "x9"}, >+ { ARM64_REG_X10, "x10"}, >+ { ARM64_REG_X11, "x11"}, >+ { ARM64_REG_X12, "x12"}, >+ { ARM64_REG_X13, "x13"}, >+ { ARM64_REG_X14, "x14"}, >+ { ARM64_REG_X15, "x15"}, >+ { ARM64_REG_X16, "x16"}, >+ { ARM64_REG_X17, "x17"}, >+ { ARM64_REG_X18, "x18"}, >+ { ARM64_REG_X19, "x19"}, >+ { ARM64_REG_X20, "x20"}, >+ { ARM64_REG_X21, "x21"}, >+ { ARM64_REG_X22, "x22"}, >+ { ARM64_REG_X23, "x23"}, >+ { ARM64_REG_X24, "x24"}, >+ { ARM64_REG_X25, "x25"}, >+ { ARM64_REG_X26, "x26"}, >+ { ARM64_REG_X27, "x27"}, >+ { ARM64_REG_X28, "x28"}, >+ >+ { ARM64_REG_V0, "v0"}, >+ { ARM64_REG_V1, "v1"}, >+ { ARM64_REG_V2, "v2"}, >+ { ARM64_REG_V3, "v3"}, >+ { ARM64_REG_V4, "v4"}, >+ { ARM64_REG_V5, "v5"}, >+ { ARM64_REG_V6, "v6"}, >+ { ARM64_REG_V7, "v7"}, >+ { ARM64_REG_V8, "v8"}, >+ { ARM64_REG_V9, "v9"}, >+ { ARM64_REG_V10, "v10"}, >+ { ARM64_REG_V11, "v11"}, >+ { ARM64_REG_V12, "v12"}, >+ { ARM64_REG_V13, "v13"}, >+ { ARM64_REG_V14, "v14"}, >+ { ARM64_REG_V15, "v15"}, >+ { ARM64_REG_V16, "v16"}, >+ { ARM64_REG_V17, "v17"}, >+ { ARM64_REG_V18, "v18"}, >+ { ARM64_REG_V19, "v19"}, >+ { ARM64_REG_V20, "v20"}, >+ { ARM64_REG_V21, "v21"}, >+ { ARM64_REG_V22, "v22"}, >+ { ARM64_REG_V23, "v23"}, >+ { ARM64_REG_V24, "v24"}, >+ { ARM64_REG_V25, "v25"}, >+ { ARM64_REG_V26, "v26"}, >+ { ARM64_REG_V27, "v27"}, >+ { ARM64_REG_V28, "v28"}, >+ { ARM64_REG_V29, "v29"}, >+ { ARM64_REG_V30, "v30"}, >+ { ARM64_REG_V31, "v31"}, >+}; >+#endif >+ >+const char *AArch64_reg_name(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= ARM64_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+static const insn_map insns[] = { >+ // dummy item >+ { >+ 0, 0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ >+ { >+ AArch64_ABSv16i8, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv1i64, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv2i32, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv2i64, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv4i16, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv4i32, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv8i16, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ABSv8i8, ARM64_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADCSWr, ARM64_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADCSXr, ARM64_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADCWr, ARM64_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADCXr, ARM64_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv16i8, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv2i32, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv2i64, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv2i64p, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv4i16, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv4i32, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv8i16, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDPv8i8, ARM64_INS_ADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSWri, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSWrs, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSWrx, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSXri, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSXrs, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSXrx, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDSXrx64, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDVv16i8v, ARM64_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDVv4i16v, ARM64_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDVv4i32v, ARM64_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDVv8i16v, ARM64_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDVv8i8v, ARM64_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDWri, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDWrs, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDWrx, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDXri, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDXrs, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDXrx, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDXrx64, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv16i8, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv1i64, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv2i32, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv2i64, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv4i16, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv4i32, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv8i16, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADDv8i8, ARM64_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADR, ARM64_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ADRP, ARM64_INS_ADRP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_AESDrr, ARM64_INS_AESD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_AESErr, ARM64_INS_AESE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_AESIMCrr, ARM64_INS_AESIMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_AESMCrr, ARM64_INS_AESMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDSWri, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDSWrs, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDSXri, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDSXrs, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDWri, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDWrs, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDXri, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDXrs, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDv16i8, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ANDv8i8, ARM64_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ASRVWr, ARM64_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ASRVXr, ARM64_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_B, ARM64_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_BFMWri, ARM64_INS_BFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BFMXri, ARM64_INS_BFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICSWrs, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICSXrs, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICWrs, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICXrs, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv16i8, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv2i32, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv4i16, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv4i32, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv8i16, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BICv8i8, ARM64_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BIFv16i8, ARM64_INS_BIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BIFv8i8, ARM64_INS_BIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BITv16i8, ARM64_INS_BIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BITv8i8, ARM64_INS_BIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BL, ARM64_INS_BL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BLR, ARM64_INS_BLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BR, ARM64_INS_BR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 1 >+#endif >+ }, >+ { >+ AArch64_BRK, ARM64_INS_BRK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BSLv16i8, ARM64_INS_BSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_BSLv8i8, ARM64_INS_BSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_Bcc, ARM64_INS_B, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_CBNZW, ARM64_INS_CBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_CBNZX, ARM64_INS_CBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_CBZW, ARM64_INS_CBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_CBZX, ARM64_INS_CBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_CCMNWi, ARM64_INS_CCMN, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMNWr, ARM64_INS_CCMN, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMNXi, ARM64_INS_CCMN, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMNXr, ARM64_INS_CCMN, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMPWi, ARM64_INS_CCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMPWr, ARM64_INS_CCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMPXi, ARM64_INS_CCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CCMPXr, ARM64_INS_CCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLREX, ARM64_INS_CLREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSWr, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSXr, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv16i8, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv2i32, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv4i16, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv4i32, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv8i16, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLSv8i8, ARM64_INS_CLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZWr, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZXr, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv16i8, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv2i32, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv4i16, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv4i32, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv8i16, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CLZv8i8, ARM64_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv16i8, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv1i64, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv2i32, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv2i64, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv4i16, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv4i32, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv8i16, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv8i8, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv16i8, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv16i8rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv1i64, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv1i64rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv2i32, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv2i32rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv2i64, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv2i64rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv4i16, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv4i16rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv4i32, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv4i32rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv8i16, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv8i16rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv8i8, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGEv8i8rz, ARM64_INS_CMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv16i8, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv16i8rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv1i64, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv1i64rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv2i32, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv2i32rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv2i64, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv2i64rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv4i16, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv4i16rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv4i32, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv4i32rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv8i16, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv8i16rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv8i8, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMGTv8i8rz, ARM64_INS_CMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv16i8, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv1i64, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv2i32, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv2i64, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv4i16, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv4i32, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv8i16, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHIv8i8, ARM64_INS_CMHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv16i8, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv1i64, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv2i32, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv2i64, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv4i16, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv4i32, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv8i16, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMHSv8i8, ARM64_INS_CMHS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv16i8rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv1i64rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv2i32rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv2i64rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv4i16rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv4i32rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv8i16rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLEv8i8rz, ARM64_INS_CMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv16i8rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv1i64rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv2i32rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv2i64rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv4i16rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv4i32rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv8i16rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMLTv8i8rz, ARM64_INS_CMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv16i8, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv1i64, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv2i32, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv2i64, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv4i16, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv4i32, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv8i16, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CMTSTv8i8, ARM64_INS_CMTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CNTv16i8, ARM64_INS_CNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CNTv8i8, ARM64_INS_CNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CPYi16, ARM64_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CPYi32, ARM64_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CPYi64, ARM64_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CPYi8, ARM64_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32Brr, ARM64_INS_CRC32B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32CBrr, ARM64_INS_CRC32CB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32CHrr, ARM64_INS_CRC32CH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32CWrr, ARM64_INS_CRC32CW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32CXrr, ARM64_INS_CRC32CX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32Hrr, ARM64_INS_CRC32H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32Wrr, ARM64_INS_CRC32W, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CRC32Xrr, ARM64_INS_CRC32X, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSELWr, ARM64_INS_CSEL, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSELXr, ARM64_INS_CSEL, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSINCWr, ARM64_INS_CSINC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSINCXr, ARM64_INS_CSINC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSINVWr, ARM64_INS_CSINV, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSINVXr, ARM64_INS_CSINV, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSNEGWr, ARM64_INS_CSNEG, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_CSNEGXr, ARM64_INS_CSNEG, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DCPS1, ARM64_INS_DCPS1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DCPS2, ARM64_INS_DCPS2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DCPS3, ARM64_INS_DCPS3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DMB, ARM64_INS_DMB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DRPS, ARM64_INS_DRPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DSB, ARM64_INS_DSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv16i8gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv16i8lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv2i32gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv2i32lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv2i64gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv2i64lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv4i16gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv4i16lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv4i32gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv4i32lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv8i16gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv8i16lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv8i8gpr, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_DUPv8i8lane, ARM64_INS_DUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EONWrs, ARM64_INS_EON, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EONXrs, ARM64_INS_EON, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORWri, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORWrs, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORXri, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORXrs, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORv16i8, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EORv8i8, ARM64_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ERET, ARM64_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EXTRWrri, ARM64_INS_EXTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EXTRXrri, ARM64_INS_EXTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EXTv16i8, ARM64_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_EXTv8i8, ARM64_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABD32, ARM64_INS_FABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABD64, ARM64_INS_FABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABDv2f32, ARM64_INS_FABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABDv2f64, ARM64_INS_FABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABDv4f32, ARM64_INS_FABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABSDr, ARM64_INS_FABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABSSr, ARM64_INS_FABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABSv2f32, ARM64_INS_FABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABSv2f64, ARM64_INS_FABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FABSv4f32, ARM64_INS_FABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGE32, ARM64_INS_FACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGE64, ARM64_INS_FACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGEv2f32, ARM64_INS_FACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGEv2f64, ARM64_INS_FACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGEv4f32, ARM64_INS_FACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGT32, ARM64_INS_FACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGT64, ARM64_INS_FACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGTv2f32, ARM64_INS_FACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGTv2f64, ARM64_INS_FACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FACGTv4f32, ARM64_INS_FACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDDrr, ARM64_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDPv2f32, ARM64_INS_FADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDPv2f64, ARM64_INS_FADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDPv2i32p, ARM64_INS_FADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDPv2i64p, ARM64_INS_FADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDPv4f32, ARM64_INS_FADDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDSrr, ARM64_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDv2f32, ARM64_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDv2f64, ARM64_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FADDv4f32, ARM64_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCCMPDrr, ARM64_INS_FCCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCCMPESrr, ARM64_INS_FCCMPE, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCCMPSrr, ARM64_INS_FCCMP, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQ32, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQ64, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGE32, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGE64, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv2f32, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv2f64, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv4f32, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGT32, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGT64, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv2f32, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv2f64, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv4f32, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPDri, ARM64_INS_FCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPDrr, ARM64_INS_FCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPEDri, ARM64_INS_FCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPEDrr, ARM64_INS_FCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPESri, ARM64_INS_FCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPESrr, ARM64_INS_FCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPSri, ARM64_INS_FCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCMPSrr, ARM64_INS_FCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCSELDrrr, ARM64_INS_FCSEL, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCSELSrrr, ARM64_INS_FCSEL, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTDHr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTDSr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTHDr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTHSr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTLv2i32, ARM64_INS_FCVTL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTLv4i16, ARM64_INS_FCVTL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNv2i32, ARM64_INS_FCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNv4i16, ARM64_INS_FCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTSDr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTSHr, ARM64_INS_FCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSd, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSs, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUd, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUs, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FDIVDrr, ARM64_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FDIVSrr, ARM64_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FDIVv2f32, ARM64_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FDIVv2f64, ARM64_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FDIVv4f32, ARM64_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMADDDrrr, ARM64_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMADDSrrr, ARM64_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXDrr, ARM64_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMDrr, ARM64_INS_FMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMSrr, ARM64_INS_FMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXPv2f32, ARM64_INS_FMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXPv2f64, ARM64_INS_FMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXPv2i32p, ARM64_INS_FMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXPv2i64p, ARM64_INS_FMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXPv4f32, ARM64_INS_FMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXSrr, ARM64_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXVv4i32v, ARM64_INS_FMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXv2f32, ARM64_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXv2f64, ARM64_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMAXv4f32, ARM64_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINDrr, ARM64_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMDrr, ARM64_INS_FMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMSrr, ARM64_INS_FMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMv2f32, ARM64_INS_FMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMv2f64, ARM64_INS_FMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINNMv4f32, ARM64_INS_FMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINPv2f32, ARM64_INS_FMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINPv2f64, ARM64_INS_FMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINPv2i32p, ARM64_INS_FMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINPv2i64p, ARM64_INS_FMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINPv4f32, ARM64_INS_FMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINSrr, ARM64_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINVv4i32v, ARM64_INS_FMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINv2f32, ARM64_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINv2f64, ARM64_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMINv4f32, ARM64_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv2f32, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv2f64, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv4f32, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv2f32, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv2f64, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv4f32, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVDXHighr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVDXr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVDi, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVDr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVSWr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVSi, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVSr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVWSr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVXDHighr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVXDr, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVv2f32_ns, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVv2f64_ns, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMOVv4f32_ns, ARM64_INS_FMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMSUBDrrr, ARM64_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMSUBSrrr, ARM64_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULDrr, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULSrr, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULX32, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULX64, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv2f32, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv2f64, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv4f32, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv1i32_indexed, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv1i64_indexed, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv2f32, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv2f64, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv2i32_indexed, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv2i64_indexed, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv4f32, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FMULv4i32_indexed, ARM64_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNEGDr, ARM64_INS_FNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNEGSr, ARM64_INS_FNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNEGv2f32, ARM64_INS_FNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNEGv2f64, ARM64_INS_FNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNEGv4f32, ARM64_INS_FNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMADDDrrr, ARM64_INS_FNMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMADDSrrr, ARM64_INS_FNMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMULDrr, ARM64_INS_FNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FNMULSrr, ARM64_INS_FNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPEv1i32, ARM64_INS_FRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPEv1i64, ARM64_INS_FRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPEv2f32, ARM64_INS_FRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPEv2f64, ARM64_INS_FRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPEv4f32, ARM64_INS_FRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPS32, ARM64_INS_FRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPS64, ARM64_INS_FRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPSv2f32, ARM64_INS_FRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPSv2f64, ARM64_INS_FRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPSv4f32, ARM64_INS_FRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPXv1i32, ARM64_INS_FRECPX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRECPXv1i64, ARM64_INS_FRECPX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTADr, ARM64_INS_FRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTASr, ARM64_INS_FRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTAv2f32, ARM64_INS_FRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTAv2f64, ARM64_INS_FRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTAv4f32, ARM64_INS_FRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTIDr, ARM64_INS_FRINTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTISr, ARM64_INS_FRINTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTIv2f32, ARM64_INS_FRINTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTIv2f64, ARM64_INS_FRINTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTIv4f32, ARM64_INS_FRINTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTMDr, ARM64_INS_FRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTMSr, ARM64_INS_FRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTMv2f32, ARM64_INS_FRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTMv2f64, ARM64_INS_FRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTMv4f32, ARM64_INS_FRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTNDr, ARM64_INS_FRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTNSr, ARM64_INS_FRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTNv2f32, ARM64_INS_FRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTNv2f64, ARM64_INS_FRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTNv4f32, ARM64_INS_FRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTPDr, ARM64_INS_FRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTPSr, ARM64_INS_FRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTPv2f32, ARM64_INS_FRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTPv2f64, ARM64_INS_FRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTPv4f32, ARM64_INS_FRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTXDr, ARM64_INS_FRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTXSr, ARM64_INS_FRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTXv2f32, ARM64_INS_FRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTXv2f64, ARM64_INS_FRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTXv4f32, ARM64_INS_FRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTZDr, ARM64_INS_FRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTZSr, ARM64_INS_FRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTZv2f32, ARM64_INS_FRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTZv2f64, ARM64_INS_FRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRINTZv4f32, ARM64_INS_FRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTS32, ARM64_INS_FRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTS64, ARM64_INS_FRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSQRTDr, ARM64_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSQRTSr, ARM64_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSQRTv2f32, ARM64_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSQRTv2f64, ARM64_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSQRTv4f32, ARM64_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSUBDrr, ARM64_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSUBSrr, ARM64_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSUBv2f32, ARM64_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSUBv2f64, ARM64_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_FSUBv4f32, ARM64_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_HINT, ARM64_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_HLT, ARM64_INS_HLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_HVC, ARM64_INS_HVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi16gpr, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi16lane, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi32gpr, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi32lane, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi64gpr, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi64lane, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi8gpr, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_INSvi8lane, ARM64_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ISB, ARM64_INS_ISB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv16b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv16b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv1d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv1d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv2d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv2d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv2s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv2s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv4h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv4h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv4s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv4s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv8b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv8b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv8h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Fourv8h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev16b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev16b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev1d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev1d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev2d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev2d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev2s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev2s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev4h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev4h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev4s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev4s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev8b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev8b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev8h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Onev8h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv16b, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv16b_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv1d, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv1d_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv2d, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv2d_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv2s, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv2s_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv4h, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv4h_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv4s, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv4s_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv8b, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv8b_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv8h, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Rv8h_POST, ARM64_INS_LD1R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev16b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev16b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev1d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev1d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev2d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev2d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev2s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev2s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev4h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev4h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev4s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev4s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev8b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev8b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev8h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Threev8h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov16b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov16b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov1d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov1d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov2d, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov2d_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov2s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov2s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov4h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov4h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov4s, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov4s_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov8b, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov8b_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov8h, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1Twov8h_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i16, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i16_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i32, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i32_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i64, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i64_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i8, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD1i8_POST, ARM64_INS_LD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv16b, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv16b_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv1d, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv1d_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv2d, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv2d_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv2s, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv2s_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv4h, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv4h_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv4s, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv4s_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv8b, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv8b_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv8h, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Rv8h_POST, ARM64_INS_LD2R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov16b, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov16b_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov2d, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov2d_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov2s, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov2s_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov4h, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov4h_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov4s, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov4s_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov8b, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov8b_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov8h, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2Twov8h_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i16, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i16_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i32, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i32_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i64, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i64_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i8, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD2i8_POST, ARM64_INS_LD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv16b, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv16b_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv1d, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv1d_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv2d, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv2d_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv2s, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv2s_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv4h, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv4h_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv4s, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv4s_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv8b, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv8b_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv8h, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Rv8h_POST, ARM64_INS_LD3R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev16b, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev16b_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev2d, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev2d_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev2s, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev2s_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev4h, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev4h_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev4s, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev4s_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev8b, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev8b_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev8h, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3Threev8h_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i16, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i16_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i32, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i32_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i64, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i64_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i8, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD3i8_POST, ARM64_INS_LD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv16b, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv16b_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv2d, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv2d_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv2s, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv2s_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv4h, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv4h_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv4s, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv4s_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv8b, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv8b_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv8h, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Fourv8h_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv16b, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv16b_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv1d, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv1d_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv2d, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv2d_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv2s, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv2s_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv4h, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv4h_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv4s, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv4s_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv8b, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv8b_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv8h, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4Rv8h_POST, ARM64_INS_LD4R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i16, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i16_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i32, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i32_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i64, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i64_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i8, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LD4i8_POST, ARM64_INS_LD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDARB, ARM64_INS_LDARB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDARH, ARM64_INS_LDARH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDARW, ARM64_INS_LDAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDARX, ARM64_INS_LDAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXPW, ARM64_INS_LDAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXPX, ARM64_INS_LDAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXRB, ARM64_INS_LDAXRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXRH, ARM64_INS_LDAXRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXRW, ARM64_INS_LDAXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDAXRX, ARM64_INS_LDAXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDNPDi, ARM64_INS_LDNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDNPQi, ARM64_INS_LDNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDNPSi, ARM64_INS_LDNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDNPWi, ARM64_INS_LDNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDNPXi, ARM64_INS_LDNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPDi, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPDpost, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPDpre, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPQi, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPQpost, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPQpre, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSWi, ARM64_INS_LDPSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSWpost, ARM64_INS_LDPSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSWpre, ARM64_INS_LDPSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSi, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSpost, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPSpre, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPWi, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPWpost, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPWpre, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPXi, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPXpost, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDPXpre, ARM64_INS_LDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBBpost, ARM64_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBBpre, ARM64_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBBroW, ARM64_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBBroX, ARM64_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBBui, ARM64_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRBui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDl, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRDui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHHpost, ARM64_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHHpre, ARM64_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHHroW, ARM64_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHHroX, ARM64_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHHui, ARM64_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRHui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQl, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRQui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBWpost, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBWpre, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBWroW, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBWroX, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBWui, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBXpost, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBXpre, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBXroW, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBXroX, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSBXui, ARM64_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHWpost, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHWpre, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHWroW, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHWroX, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHWui, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHXpost, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHXpre, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHXroW, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHXroX, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSHXui, ARM64_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWl, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWpost, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWpre, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWroW, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWroX, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSWui, ARM64_INS_LDRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSl, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRSui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWl, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRWui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXl, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXpost, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXpre, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXroW, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXroX, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDRXui, ARM64_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRBi, ARM64_INS_LDTRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRHi, ARM64_INS_LDTRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRSBWi, ARM64_INS_LDTRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRSBXi, ARM64_INS_LDTRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRSHWi, ARM64_INS_LDTRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRSHXi, ARM64_INS_LDTRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRSWi, ARM64_INS_LDTRSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRWi, ARM64_INS_LDTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDTRXi, ARM64_INS_LDTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURBBi, ARM64_INS_LDURB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURBi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURDi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURHHi, ARM64_INS_LDURH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURHi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURQi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSBWi, ARM64_INS_LDURSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSBXi, ARM64_INS_LDURSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSHWi, ARM64_INS_LDURSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSHXi, ARM64_INS_LDURSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSWi, ARM64_INS_LDURSW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURSi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURWi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDURXi, ARM64_INS_LDUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXPW, ARM64_INS_LDXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXPX, ARM64_INS_LDXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXRB, ARM64_INS_LDXRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXRH, ARM64_INS_LDXRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXRW, ARM64_INS_LDXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LDXRX, ARM64_INS_LDXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LSLVWr, ARM64_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LSLVXr, ARM64_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LSRVWr, ARM64_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_LSRVXr, ARM64_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MADDWrrr, ARM64_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MADDXrrr, ARM64_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv16i8, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv2i32, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv2i32_indexed, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv4i16, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv4i16_indexed, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv4i32, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv4i32_indexed, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv8i16, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv8i16_indexed, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLAv8i8, ARM64_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv16i8, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv2i32, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv2i32_indexed, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv4i16, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv4i16_indexed, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv4i32, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv4i32_indexed, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv8i16, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv8i16_indexed, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MLSv8i8, ARM64_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVID, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv16b_ns, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv2d_ns, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv2i32, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv2s_msl, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv4i16, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv4i32, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv4s_msl, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv8b_ns, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVIv8i16, ARM64_INS_MOVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVKWi, ARM64_INS_MOVK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVKXi, ARM64_INS_MOVK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVNWi, ARM64_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVNXi, ARM64_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVZWi, ARM64_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MOVZXi, ARM64_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MRS, ARM64_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MSR, ARM64_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MSRpstate, ARM64_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MSUBWrrr, ARM64_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MSUBXrrr, ARM64_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv16i8, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv2i32, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv2i32_indexed, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv4i16, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv4i16_indexed, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv4i32, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv4i32_indexed, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv8i16, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv8i16_indexed, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MULv8i8, ARM64_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv2i32, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv2s_msl, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv4i16, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv4i32, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv4s_msl, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_MVNIv8i16, ARM64_INS_MVNI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv16i8, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv1i64, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv2i32, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv2i64, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv4i16, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv4i32, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv8i16, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NEGv8i8, ARM64_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NOTv16i8, ARM64_INS_NOT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_NOTv8i8, ARM64_INS_NOT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORNWrs, ARM64_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORNXrs, ARM64_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORNv16i8, ARM64_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORNv8i8, ARM64_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRWri, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRWrs, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRXri, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRXrs, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv16i8, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv2i32, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv4i16, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv4i32, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv8i16, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ORRv8i8, ARM64_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULLv16i8, ARM64_INS_PMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULLv1i64, ARM64_INS_PMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULLv2i64, ARM64_INS_PMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULLv8i8, ARM64_INS_PMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULv16i8, ARM64_INS_PMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PMULv8i8, ARM64_INS_PMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PRFMl, ARM64_INS_PRFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PRFMroW, ARM64_INS_PRFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PRFMroX, ARM64_INS_PRFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PRFMui, ARM64_INS_PRFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_PRFUMi, ARM64_INS_PRFUM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RBITWr, ARM64_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RBITXr, ARM64_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RBITv16i8, ARM64_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RBITv8i8, ARM64_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RET, ARM64_INS_RET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV16Wr, ARM64_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV16Xr, ARM64_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV16v16i8, ARM64_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV16v8i8, ARM64_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV32Xr, ARM64_INS_REV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV32v16i8, ARM64_INS_REV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV32v4i16, ARM64_INS_REV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV32v8i16, ARM64_INS_REV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV32v8i8, ARM64_INS_REV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v16i8, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v2i32, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v4i16, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v4i32, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v8i16, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REV64v8i8, ARM64_INS_REV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REVWr, ARM64_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_REVXr, ARM64_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RORVWr, ARM64_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RORVXr, ARM64_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv16i8, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv2i32, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv4i16, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv4i32, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv8i16, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABAv8i8, ARM64_INS_SABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv16i8, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv2i32, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv4i16, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv4i32, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv8i16, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SABDv8i8, ARM64_INS_SABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLVv16i8v, ARM64_INS_SADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLVv4i16v, ARM64_INS_SADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLVv4i32v, ARM64_INS_SADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLVv8i16v, ARM64_INS_SADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLVv8i8v, ARM64_INS_SADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBCSWr, ARM64_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBCSXr, ARM64_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBCWr, ARM64_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBCXr, ARM64_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBFMWri, ARM64_INS_SBFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SBFMXri, ARM64_INS_SBFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFSWDri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFSWSri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFSXDri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFSXSri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFUWDri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFUWSri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFUXDri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFUXSri, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFd, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFs, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv1i32, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv1i64, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv2f32, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv2f64, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv4f32, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SDIVWr, ARM64_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SDIVXr, ARM64_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SDIV_IntWr, ARM64_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SDIV_IntXr, ARM64_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1Crrr, ARM64_INS_SHA1C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1Hrr, ARM64_INS_SHA1H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1Mrrr, ARM64_INS_SHA1M, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1Prrr, ARM64_INS_SHA1P, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA256H2rrr, ARM64_INS_SHA256H2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA256Hrrr, ARM64_INS_SHA256H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv16i8, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv2i32, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv4i16, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv4i32, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv8i16, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHADDv8i8, ARM64_INS_SHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv16i8, ARM64_INS_SHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv2i32, ARM64_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv4i16, ARM64_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv4i32, ARM64_INS_SHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv8i16, ARM64_INS_SHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLLv8i8, ARM64_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLd, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv16i8_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv2i32_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv2i64_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv4i16_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv4i32_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv8i16_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHLv8i8_shift, ARM64_INS_SHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv2i32_shift, ARM64_INS_SHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv4i16_shift, ARM64_INS_SHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHRNv8i8_shift, ARM64_INS_SHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv16i8, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv2i32, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv4i16, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv4i32, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv8i16, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SHSUBv8i8, ARM64_INS_SHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLId, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv16i8_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv2i32_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv2i64_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv4i16_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv4i32_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv8i16_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SLIv8i8_shift, ARM64_INS_SLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMADDLrrr, ARM64_INS_SMADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv16i8, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv2i32, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv4i16, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv4i32, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv8i16, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXPv8i8, ARM64_INS_SMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXVv16i8v, ARM64_INS_SMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXVv4i16v, ARM64_INS_SMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXVv4i32v, ARM64_INS_SMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXVv8i16v, ARM64_INS_SMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXVv8i8v, ARM64_INS_SMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv16i8, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv2i32, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv4i16, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv4i32, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv8i16, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMAXv8i8, ARM64_INS_SMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMC, ARM64_INS_SMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv16i8, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv2i32, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv4i16, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv4i32, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv8i16, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINPv8i8, ARM64_INS_SMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINVv16i8v, ARM64_INS_SMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINVv4i16v, ARM64_INS_SMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINVv4i32v, ARM64_INS_SMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINVv8i16v, ARM64_INS_SMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINVv8i8v, ARM64_INS_SMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv16i8, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv2i32, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv4i16, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv4i32, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv8i16, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMINv8i8, ARM64_INS_SMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMOVvi16to32, ARM64_INS_SMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMOVvi16to64, ARM64_INS_SMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMOVvi32to64, ARM64_INS_SMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMOVvi8to32, ARM64_INS_SMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMOVvi8to64, ARM64_INS_SMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMSUBLrrr, ARM64_INS_SMSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULHrr, ARM64_INS_SMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv16i8, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv1i16, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv1i32, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv1i64, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv1i8, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv2i32, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv2i64, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv4i16, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv4i32, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv8i16, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQABSv8i8, ARM64_INS_SQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv16i8, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv1i16, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv1i32, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv1i64, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv1i8, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv2i32, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv2i64, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv4i16, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv4i32, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv8i16, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQADDv8i8, ARM64_INS_SQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALi16, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALi32, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLi16, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLi32, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv16i8, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv1i16, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv1i32, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv1i64, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv1i8, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv2i32, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv2i64, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv4i16, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv4i32, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv8i16, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQNEGv8i8, ARM64_INS_SQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNb, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNh, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNs, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUb, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUd, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUh, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUs, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLb, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLd, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLh, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLs, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv16i8, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv1i16, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv1i32, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv1i64, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv1i8, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv2i32, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv2i64, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv4i16, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv4i32, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv8i16, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv8i8, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNb, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNh, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNs, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNb, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNh, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNs, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv16i8, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv1i16, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv1i32, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv1i64, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv1i8, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv2i32, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv2i64, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv4i16, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv4i32, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv8i16, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQSUBv8i8, ARM64_INS_SQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv16i8, ARM64_INS_SQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv1i16, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv1i32, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv1i8, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv2i32, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv4i16, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv4i32, ARM64_INS_SQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv8i16, ARM64_INS_SQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTNv8i8, ARM64_INS_SQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv16i8, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv2i32, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv4i16, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv4i32, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv8i16, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRHADDv8i8, ARM64_INS_SRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRId, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv16i8_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv2i32_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv2i64_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv4i16_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv4i32_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv8i16_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRIv8i8_shift, ARM64_INS_SRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv16i8, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv1i64, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv2i32, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv2i64, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv4i16, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv4i32, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv8i16, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHLv8i8, ARM64_INS_SRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRd, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAd, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv16i8, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv1i64, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv2i32, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv2i64, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv4i16, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv4i32, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv8i16, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHLv8i8, ARM64_INS_SSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRd, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv16i8_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv2i32_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv2i64_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv4i16_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv4i32_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv8i16_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSHRv8i8_shift, ARM64_INS_SSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAd, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv16i8_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv2i32_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv2i64_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv4i16_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv4i32_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv8i16_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSRAv8i8_shift, ARM64_INS_SSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv16b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv16b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv1d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv1d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv2d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv2d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv2s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv2s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv4h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv4h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv4s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv4s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv8b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv8b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv8h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Fourv8h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev16b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev16b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev1d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev1d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev2d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev2d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev2s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev2s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev4h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev4h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev4s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev4s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev8b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev8b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev8h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Onev8h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev16b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev16b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev1d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev1d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev2d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev2d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev2s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev2s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev4h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev4h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev4s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev4s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev8b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev8b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev8h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Threev8h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov16b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov16b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov1d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov1d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov2d, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov2d_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov2s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov2s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov4h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov4h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov4s, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov4s_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov8b, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov8b_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov8h, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1Twov8h_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i16, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i16_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i32, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i32_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i64, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i64_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i8, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST1i8_POST, ARM64_INS_ST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov16b, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov16b_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov2d, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov2d_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov2s, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov2s_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov4h, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov4h_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov4s, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov4s_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov8b, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov8b_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov8h, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2Twov8h_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i16, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i16_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i32, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i32_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i64, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i64_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i8, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST2i8_POST, ARM64_INS_ST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev16b, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev16b_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev2d, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev2d_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev2s, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev2s_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev4h, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev4h_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev4s, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev4s_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev8b, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev8b_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev8h, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3Threev8h_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i16, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i16_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i32, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i32_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i64, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i64_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i8, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST3i8_POST, ARM64_INS_ST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv16b, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv16b_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv2d, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv2d_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv2s, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv2s_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv4h, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv4h_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv4s, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv4s_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv8b, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv8b_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv8h, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4Fourv8h_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i16, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i16_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i32, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i32_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i64, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i64_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i8, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ST4i8_POST, ARM64_INS_ST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLRB, ARM64_INS_STLRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLRH, ARM64_INS_STLRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLRW, ARM64_INS_STLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLRX, ARM64_INS_STLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXPW, ARM64_INS_STLXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXPX, ARM64_INS_STLXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXRB, ARM64_INS_STLXRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXRH, ARM64_INS_STLXRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXRW, ARM64_INS_STLXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STLXRX, ARM64_INS_STLXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STNPDi, ARM64_INS_STNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STNPQi, ARM64_INS_STNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STNPSi, ARM64_INS_STNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STNPWi, ARM64_INS_STNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STNPXi, ARM64_INS_STNP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPDi, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPDpost, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPDpre, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPQi, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPQpost, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPQpre, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPSi, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPSpost, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPSpre, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPWi, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPWpost, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPWpre, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPXi, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPXpost, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STPXpre, ARM64_INS_STP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBBpost, ARM64_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBBpre, ARM64_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBBroW, ARM64_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBBroX, ARM64_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBBui, ARM64_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRBui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRDpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRDpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRDroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRDroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRDui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHHpost, ARM64_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHHpre, ARM64_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHHroW, ARM64_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHHroX, ARM64_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHHui, ARM64_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRHui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRQpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRQpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRQroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRQroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRQui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRSpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRSpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRSroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRSroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRSui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRWpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRWpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRWroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRWroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRWui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRXpost, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRXpre, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRXroW, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRXroX, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STRXui, ARM64_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STTRBi, ARM64_INS_STTRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STTRHi, ARM64_INS_STTRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STTRWi, ARM64_INS_STTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STTRXi, ARM64_INS_STTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURBBi, ARM64_INS_STURB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURBi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURDi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURHHi, ARM64_INS_STURH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURHi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURQi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURSi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURWi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STURXi, ARM64_INS_STUR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXPW, ARM64_INS_STXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXPX, ARM64_INS_STXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXRB, ARM64_INS_STXRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXRH, ARM64_INS_STXRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXRW, ARM64_INS_STXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_STXRX, ARM64_INS_STXR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSWri, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSWrs, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSWrx, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSXri, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSXrs, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSXrx, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBSXrx64, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBWri, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBWrs, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBWrx, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBXri, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBXrs, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBXrx, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBXrx64, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv16i8, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv1i64, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv2i32, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv2i64, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv4i16, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv4i32, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv8i16, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUBv8i8, ARM64_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv16i8, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv1i16, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv1i32, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv1i64, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv1i8, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv2i32, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv2i64, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv4i16, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv4i32, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv8i16, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SUQADDv8i8, ARM64_INS_SUQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SVC, ARM64_INS_SVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SYSLxt, ARM64_INS_SYSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_SYSxt, ARM64_INS_SYS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv16i8Four, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv16i8One, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv16i8Three, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv16i8Two, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv8i8Four, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv8i8One, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv8i8Three, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBLv8i8Two, ARM64_INS_TBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBNZW, ARM64_INS_TBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_TBNZX, ARM64_INS_TBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv16i8Four, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv16i8One, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv16i8Three, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv16i8Two, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv8i8Four, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv8i8One, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv8i8Three, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBXv8i8Two, ARM64_INS_TBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TBZW, ARM64_INS_TBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_TBZX, ARM64_INS_TBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 1, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v16i8, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v2i32, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v2i64, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v4i16, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v4i32, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v8i16, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN1v8i8, ARM64_INS_TRN1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v16i8, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v2i32, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v2i64, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v4i16, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v4i32, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v8i16, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_TRN2v8i8, ARM64_INS_TRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv16i8, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv2i32, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv4i16, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv4i32, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv8i16, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABAv8i8, ARM64_INS_UABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv16i8, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv2i32, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv4i16, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv4i32, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv8i16, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UABDv8i8, ARM64_INS_UABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLVv16i8v, ARM64_INS_UADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLVv4i16v, ARM64_INS_UADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLVv4i32v, ARM64_INS_UADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLVv8i16v, ARM64_INS_UADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLVv8i8v, ARM64_INS_UADDLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UBFMWri, ARM64_INS_UBFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UBFMXri, ARM64_INS_UBFM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFSWDri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFSWSri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFSXDri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFSXSri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFUWDri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFUWSri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFUXDri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFUXSri, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFd, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFs, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv1i32, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv1i64, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv2f32, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv2f64, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv4f32, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UDIVWr, ARM64_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UDIVXr, ARM64_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UDIV_IntWr, ARM64_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UDIV_IntXr, ARM64_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv16i8, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv2i32, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv4i16, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv4i32, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv8i16, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHADDv8i8, ARM64_INS_UHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv16i8, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv2i32, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv4i16, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv4i32, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv8i16, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UHSUBv8i8, ARM64_INS_UHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMADDLrrr, ARM64_INS_UMADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv16i8, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv2i32, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv4i16, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv4i32, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv8i16, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXPv8i8, ARM64_INS_UMAXP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXVv16i8v, ARM64_INS_UMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXVv4i16v, ARM64_INS_UMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXVv4i32v, ARM64_INS_UMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXVv8i16v, ARM64_INS_UMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXVv8i8v, ARM64_INS_UMAXV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv16i8, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv2i32, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv4i16, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv4i32, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv8i16, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMAXv8i8, ARM64_INS_UMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv16i8, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv2i32, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv4i16, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv4i32, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv8i16, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINPv8i8, ARM64_INS_UMINP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINVv16i8v, ARM64_INS_UMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINVv4i16v, ARM64_INS_UMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINVv4i32v, ARM64_INS_UMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINVv8i16v, ARM64_INS_UMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINVv8i8v, ARM64_INS_UMINV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv16i8, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv2i32, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv4i16, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv4i32, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv8i16, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMINv8i8, ARM64_INS_UMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMOVvi16, ARM64_INS_UMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMOVvi32, ARM64_INS_UMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMOVvi64, ARM64_INS_UMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMOVvi8, ARM64_INS_UMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMSUBLrrr, ARM64_INS_UMSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULHrr, ARM64_INS_UMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv16i8, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv1i16, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv1i32, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv1i64, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv1i8, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv2i32, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv2i64, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv4i16, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv4i32, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv8i16, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQADDv8i8, ARM64_INS_UQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNb, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNh, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNs, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLb, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLd, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLh, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLs, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv16i8, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv1i16, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv1i32, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv1i64, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv1i8, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv2i32, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv2i64, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv4i16, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv4i32, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv8i16, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv8i8, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNb, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNh, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNs, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv16i8, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv1i16, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv1i32, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv1i64, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv1i8, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv2i32, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv2i64, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv4i16, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv4i32, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv8i16, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQSUBv8i8, ARM64_INS_UQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv16i8, ARM64_INS_UQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv1i16, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv1i32, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv1i8, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv2i32, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv4i16, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv4i32, ARM64_INS_UQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv8i16, ARM64_INS_UQXTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UQXTNv8i8, ARM64_INS_UQXTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URECPEv2i32, ARM64_INS_URECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URECPEv4i32, ARM64_INS_URECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv16i8, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv2i32, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv4i16, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv4i32, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv8i16, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URHADDv8i8, ARM64_INS_URHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv16i8, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv1i64, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv2i32, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv2i64, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv4i16, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv4i32, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv8i16, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHLv8i8, ARM64_INS_URSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRd, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv16i8_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv2i32_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv2i64_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv4i16_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv4i32_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv8i16_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSHRv8i8_shift, ARM64_INS_URSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAd, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv16i8_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv2i32_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv2i64_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv4i16_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv4i32_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv8i16_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_URSRAv8i8_shift, ARM64_INS_URSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv2i32_shift, ARM64_INS_USHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv4i16_shift, ARM64_INS_USHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLLv8i8_shift, ARM64_INS_USHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv16i8, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv1i64, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv2i32, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv2i64, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv4i16, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv4i32, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv8i16, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHLv8i8, ARM64_INS_USHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRd, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv16i8_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv2i32_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv2i64_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv4i16_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv4i32_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv8i16_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USHRv8i8_shift, ARM64_INS_USHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv16i8, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv1i16, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv1i32, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv1i64, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv1i8, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv2i32, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv2i64, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv4i16, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv4i32, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv8i16, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USQADDv8i8, ARM64_INS_USQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAd, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv16i8_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv2i32_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv2i64_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv4i16_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv4i32_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv8i16_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USRAv8i8_shift, ARM64_INS_USRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v16i8, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v2i32, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v2i64, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v4i16, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v4i32, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v8i16, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP1v8i8, ARM64_INS_UZP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v16i8, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v2i32, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v2i64, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v4i16, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v4i32, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v8i16, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_UZP2v8i8, ARM64_INS_UZP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv16i8, ARM64_INS_XTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv2i32, ARM64_INS_XTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv4i16, ARM64_INS_XTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv4i32, ARM64_INS_XTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv8i16, ARM64_INS_XTN2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_XTNv8i8, ARM64_INS_XTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v16i8, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v2i32, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v2i64, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v4i16, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v4i32, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v8i16, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP1v8i8, ARM64_INS_ZIP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v16i8, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v2i32, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v2i64, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v4i16, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v4i32, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v8i16, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ AArch64_ZIP2v8i8, ARM64_INS_ZIP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+}; >+ >+// some alias instruction only need to be defined locally to satisfy >+// some lookup functions >+// just make sure these IDs never reuse any other IDs ARM_INS_* >+#define ARM64_INS_NEGS (unsigned short)-1 >+#define ARM64_INS_NGCS (unsigned short)-2 >+ >+// given internal insn id, return public instruction info >+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) >+{ >+ int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ if (i != 0) { >+ insn->id = insns[i].mapid; >+ >+ if (h->detail) { >+#ifndef CAPSTONE_DIET >+ cs_struct handle; >+ handle.detail = h->detail; >+ >+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); >+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); >+ >+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); >+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); >+ >+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); >+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups); >+ >+ insn->detail->arm64.update_flags = cs_reg_write((csh)&handle, insn, ARM64_REG_NZCV); >+ >+ if (insns[i].branch || insns[i].indirect_branch) { >+ // this insn also belongs to JUMP group. add JUMP group >+ insn->detail->groups[insn->detail->groups_count] = ARM64_GRP_JUMP; >+ insn->detail->groups_count++; >+ } >+#endif >+ } >+ } >+} >+ >+static const name_map insn_name_maps[] = { >+ { ARM64_INS_INVALID, NULL }, >+ >+ { ARM64_INS_ABS, "abs" }, >+ { ARM64_INS_ADC, "adc" }, >+ { ARM64_INS_ADDHN, "addhn" }, >+ { ARM64_INS_ADDHN2, "addhn2" }, >+ { ARM64_INS_ADDP, "addp" }, >+ { ARM64_INS_ADD, "add" }, >+ { ARM64_INS_ADDV, "addv" }, >+ { ARM64_INS_ADR, "adr" }, >+ { ARM64_INS_ADRP, "adrp" }, >+ { ARM64_INS_AESD, "aesd" }, >+ { ARM64_INS_AESE, "aese" }, >+ { ARM64_INS_AESIMC, "aesimc" }, >+ { ARM64_INS_AESMC, "aesmc" }, >+ { ARM64_INS_AND, "and" }, >+ { ARM64_INS_ASR, "asr" }, >+ { ARM64_INS_B, "b" }, >+ { ARM64_INS_BFM, "bfm" }, >+ { ARM64_INS_BIC, "bic" }, >+ { ARM64_INS_BIF, "bif" }, >+ { ARM64_INS_BIT, "bit" }, >+ { ARM64_INS_BL, "bl" }, >+ { ARM64_INS_BLR, "blr" }, >+ { ARM64_INS_BR, "br" }, >+ { ARM64_INS_BRK, "brk" }, >+ { ARM64_INS_BSL, "bsl" }, >+ { ARM64_INS_CBNZ, "cbnz" }, >+ { ARM64_INS_CBZ, "cbz" }, >+ { ARM64_INS_CCMN, "ccmn" }, >+ { ARM64_INS_CCMP, "ccmp" }, >+ { ARM64_INS_CLREX, "clrex" }, >+ { ARM64_INS_CLS, "cls" }, >+ { ARM64_INS_CLZ, "clz" }, >+ { ARM64_INS_CMEQ, "cmeq" }, >+ { ARM64_INS_CMGE, "cmge" }, >+ { ARM64_INS_CMGT, "cmgt" }, >+ { ARM64_INS_CMHI, "cmhi" }, >+ { ARM64_INS_CMHS, "cmhs" }, >+ { ARM64_INS_CMLE, "cmle" }, >+ { ARM64_INS_CMLT, "cmlt" }, >+ { ARM64_INS_CMTST, "cmtst" }, >+ { ARM64_INS_CNT, "cnt" }, >+ { ARM64_INS_MOV, "mov" }, >+ { ARM64_INS_CRC32B, "crc32b" }, >+ { ARM64_INS_CRC32CB, "crc32cb" }, >+ { ARM64_INS_CRC32CH, "crc32ch" }, >+ { ARM64_INS_CRC32CW, "crc32cw" }, >+ { ARM64_INS_CRC32CX, "crc32cx" }, >+ { ARM64_INS_CRC32H, "crc32h" }, >+ { ARM64_INS_CRC32W, "crc32w" }, >+ { ARM64_INS_CRC32X, "crc32x" }, >+ { ARM64_INS_CSEL, "csel" }, >+ { ARM64_INS_CSINC, "csinc" }, >+ { ARM64_INS_CSINV, "csinv" }, >+ { ARM64_INS_CSNEG, "csneg" }, >+ { ARM64_INS_DCPS1, "dcps1" }, >+ { ARM64_INS_DCPS2, "dcps2" }, >+ { ARM64_INS_DCPS3, "dcps3" }, >+ { ARM64_INS_DMB, "dmb" }, >+ { ARM64_INS_DRPS, "drps" }, >+ { ARM64_INS_DSB, "dsb" }, >+ { ARM64_INS_DUP, "dup" }, >+ { ARM64_INS_EON, "eon" }, >+ { ARM64_INS_EOR, "eor" }, >+ { ARM64_INS_ERET, "eret" }, >+ { ARM64_INS_EXTR, "extr" }, >+ { ARM64_INS_EXT, "ext" }, >+ { ARM64_INS_FABD, "fabd" }, >+ { ARM64_INS_FABS, "fabs" }, >+ { ARM64_INS_FACGE, "facge" }, >+ { ARM64_INS_FACGT, "facgt" }, >+ { ARM64_INS_FADD, "fadd" }, >+ { ARM64_INS_FADDP, "faddp" }, >+ { ARM64_INS_FCCMP, "fccmp" }, >+ { ARM64_INS_FCCMPE, "fccmpe" }, >+ { ARM64_INS_FCMEQ, "fcmeq" }, >+ { ARM64_INS_FCMGE, "fcmge" }, >+ { ARM64_INS_FCMGT, "fcmgt" }, >+ { ARM64_INS_FCMLE, "fcmle" }, >+ { ARM64_INS_FCMLT, "fcmlt" }, >+ { ARM64_INS_FCMP, "fcmp" }, >+ { ARM64_INS_FCMPE, "fcmpe" }, >+ { ARM64_INS_FCSEL, "fcsel" }, >+ { ARM64_INS_FCVTAS, "fcvtas" }, >+ { ARM64_INS_FCVTAU, "fcvtau" }, >+ { ARM64_INS_FCVT, "fcvt" }, >+ { ARM64_INS_FCVTL, "fcvtl" }, >+ { ARM64_INS_FCVTL2, "fcvtl2" }, >+ { ARM64_INS_FCVTMS, "fcvtms" }, >+ { ARM64_INS_FCVTMU, "fcvtmu" }, >+ { ARM64_INS_FCVTNS, "fcvtns" }, >+ { ARM64_INS_FCVTNU, "fcvtnu" }, >+ { ARM64_INS_FCVTN, "fcvtn" }, >+ { ARM64_INS_FCVTN2, "fcvtn2" }, >+ { ARM64_INS_FCVTPS, "fcvtps" }, >+ { ARM64_INS_FCVTPU, "fcvtpu" }, >+ { ARM64_INS_FCVTXN, "fcvtxn" }, >+ { ARM64_INS_FCVTXN2, "fcvtxn2" }, >+ { ARM64_INS_FCVTZS, "fcvtzs" }, >+ { ARM64_INS_FCVTZU, "fcvtzu" }, >+ { ARM64_INS_FDIV, "fdiv" }, >+ { ARM64_INS_FMADD, "fmadd" }, >+ { ARM64_INS_FMAX, "fmax" }, >+ { ARM64_INS_FMAXNM, "fmaxnm" }, >+ { ARM64_INS_FMAXNMP, "fmaxnmp" }, >+ { ARM64_INS_FMAXNMV, "fmaxnmv" }, >+ { ARM64_INS_FMAXP, "fmaxp" }, >+ { ARM64_INS_FMAXV, "fmaxv" }, >+ { ARM64_INS_FMIN, "fmin" }, >+ { ARM64_INS_FMINNM, "fminnm" }, >+ { ARM64_INS_FMINNMP, "fminnmp" }, >+ { ARM64_INS_FMINNMV, "fminnmv" }, >+ { ARM64_INS_FMINP, "fminp" }, >+ { ARM64_INS_FMINV, "fminv" }, >+ { ARM64_INS_FMLA, "fmla" }, >+ { ARM64_INS_FMLS, "fmls" }, >+ { ARM64_INS_FMOV, "fmov" }, >+ { ARM64_INS_FMSUB, "fmsub" }, >+ { ARM64_INS_FMUL, "fmul" }, >+ { ARM64_INS_FMULX, "fmulx" }, >+ { ARM64_INS_FNEG, "fneg" }, >+ { ARM64_INS_FNMADD, "fnmadd" }, >+ { ARM64_INS_FNMSUB, "fnmsub" }, >+ { ARM64_INS_FNMUL, "fnmul" }, >+ { ARM64_INS_FRECPE, "frecpe" }, >+ { ARM64_INS_FRECPS, "frecps" }, >+ { ARM64_INS_FRECPX, "frecpx" }, >+ { ARM64_INS_FRINTA, "frinta" }, >+ { ARM64_INS_FRINTI, "frinti" }, >+ { ARM64_INS_FRINTM, "frintm" }, >+ { ARM64_INS_FRINTN, "frintn" }, >+ { ARM64_INS_FRINTP, "frintp" }, >+ { ARM64_INS_FRINTX, "frintx" }, >+ { ARM64_INS_FRINTZ, "frintz" }, >+ { ARM64_INS_FRSQRTE, "frsqrte" }, >+ { ARM64_INS_FRSQRTS, "frsqrts" }, >+ { ARM64_INS_FSQRT, "fsqrt" }, >+ { ARM64_INS_FSUB, "fsub" }, >+ { ARM64_INS_HINT, "hint" }, >+ { ARM64_INS_HLT, "hlt" }, >+ { ARM64_INS_HVC, "hvc" }, >+ { ARM64_INS_INS, "ins" }, >+ { ARM64_INS_ISB, "isb" }, >+ { ARM64_INS_LD1, "ld1" }, >+ { ARM64_INS_LD1R, "ld1r" }, >+ { ARM64_INS_LD2R, "ld2r" }, >+ { ARM64_INS_LD2, "ld2" }, >+ { ARM64_INS_LD3R, "ld3r" }, >+ { ARM64_INS_LD3, "ld3" }, >+ { ARM64_INS_LD4, "ld4" }, >+ { ARM64_INS_LD4R, "ld4r" }, >+ { ARM64_INS_LDARB, "ldarb" }, >+ { ARM64_INS_LDARH, "ldarh" }, >+ { ARM64_INS_LDAR, "ldar" }, >+ { ARM64_INS_LDAXP, "ldaxp" }, >+ { ARM64_INS_LDAXRB, "ldaxrb" }, >+ { ARM64_INS_LDAXRH, "ldaxrh" }, >+ { ARM64_INS_LDAXR, "ldaxr" }, >+ { ARM64_INS_LDNP, "ldnp" }, >+ { ARM64_INS_LDP, "ldp" }, >+ { ARM64_INS_LDPSW, "ldpsw" }, >+ { ARM64_INS_LDRB, "ldrb" }, >+ { ARM64_INS_LDR, "ldr" }, >+ { ARM64_INS_LDRH, "ldrh" }, >+ { ARM64_INS_LDRSB, "ldrsb" }, >+ { ARM64_INS_LDRSH, "ldrsh" }, >+ { ARM64_INS_LDRSW, "ldrsw" }, >+ { ARM64_INS_LDTRB, "ldtrb" }, >+ { ARM64_INS_LDTRH, "ldtrh" }, >+ { ARM64_INS_LDTRSB, "ldtrsb" }, >+ { ARM64_INS_LDTRSH, "ldtrsh" }, >+ { ARM64_INS_LDTRSW, "ldtrsw" }, >+ { ARM64_INS_LDTR, "ldtr" }, >+ { ARM64_INS_LDURB, "ldurb" }, >+ { ARM64_INS_LDUR, "ldur" }, >+ { ARM64_INS_LDURH, "ldurh" }, >+ { ARM64_INS_LDURSB, "ldursb" }, >+ { ARM64_INS_LDURSH, "ldursh" }, >+ { ARM64_INS_LDURSW, "ldursw" }, >+ { ARM64_INS_LDXP, "ldxp" }, >+ { ARM64_INS_LDXRB, "ldxrb" }, >+ { ARM64_INS_LDXRH, "ldxrh" }, >+ { ARM64_INS_LDXR, "ldxr" }, >+ { ARM64_INS_LSL, "lsl" }, >+ { ARM64_INS_LSR, "lsr" }, >+ { ARM64_INS_MADD, "madd" }, >+ { ARM64_INS_MLA, "mla" }, >+ { ARM64_INS_MLS, "mls" }, >+ { ARM64_INS_MOVI, "movi" }, >+ { ARM64_INS_MOVK, "movk" }, >+ { ARM64_INS_MOVN, "movn" }, >+ { ARM64_INS_MOVZ, "movz" }, >+ { ARM64_INS_MRS, "mrs" }, >+ { ARM64_INS_MSR, "msr" }, >+ { ARM64_INS_MSUB, "msub" }, >+ { ARM64_INS_MUL, "mul" }, >+ { ARM64_INS_MVNI, "mvni" }, >+ { ARM64_INS_NEG, "neg" }, >+ { ARM64_INS_NOT, "not" }, >+ { ARM64_INS_ORN, "orn" }, >+ { ARM64_INS_ORR, "orr" }, >+ { ARM64_INS_PMULL2, "pmull2" }, >+ { ARM64_INS_PMULL, "pmull" }, >+ { ARM64_INS_PMUL, "pmul" }, >+ { ARM64_INS_PRFM, "prfm" }, >+ { ARM64_INS_PRFUM, "prfum" }, >+ { ARM64_INS_RADDHN, "raddhn" }, >+ { ARM64_INS_RADDHN2, "raddhn2" }, >+ { ARM64_INS_RBIT, "rbit" }, >+ { ARM64_INS_RET, "ret" }, >+ { ARM64_INS_REV16, "rev16" }, >+ { ARM64_INS_REV32, "rev32" }, >+ { ARM64_INS_REV64, "rev64" }, >+ { ARM64_INS_REV, "rev" }, >+ { ARM64_INS_ROR, "ror" }, >+ { ARM64_INS_RSHRN2, "rshrn2" }, >+ { ARM64_INS_RSHRN, "rshrn" }, >+ { ARM64_INS_RSUBHN, "rsubhn" }, >+ { ARM64_INS_RSUBHN2, "rsubhn2" }, >+ { ARM64_INS_SABAL2, "sabal2" }, >+ { ARM64_INS_SABAL, "sabal" }, >+ { ARM64_INS_SABA, "saba" }, >+ { ARM64_INS_SABDL2, "sabdl2" }, >+ { ARM64_INS_SABDL, "sabdl" }, >+ { ARM64_INS_SABD, "sabd" }, >+ { ARM64_INS_SADALP, "sadalp" }, >+ { ARM64_INS_SADDLP, "saddlp" }, >+ { ARM64_INS_SADDLV, "saddlv" }, >+ { ARM64_INS_SADDL2, "saddl2" }, >+ { ARM64_INS_SADDL, "saddl" }, >+ { ARM64_INS_SADDW2, "saddw2" }, >+ { ARM64_INS_SADDW, "saddw" }, >+ { ARM64_INS_SBC, "sbc" }, >+ { ARM64_INS_SBFM, "sbfm" }, >+ { ARM64_INS_SCVTF, "scvtf" }, >+ { ARM64_INS_SDIV, "sdiv" }, >+ { ARM64_INS_SHA1C, "sha1c" }, >+ { ARM64_INS_SHA1H, "sha1h" }, >+ { ARM64_INS_SHA1M, "sha1m" }, >+ { ARM64_INS_SHA1P, "sha1p" }, >+ { ARM64_INS_SHA1SU0, "sha1su0" }, >+ { ARM64_INS_SHA1SU1, "sha1su1" }, >+ { ARM64_INS_SHA256H2, "sha256h2" }, >+ { ARM64_INS_SHA256H, "sha256h" }, >+ { ARM64_INS_SHA256SU0, "sha256su0" }, >+ { ARM64_INS_SHA256SU1, "sha256su1" }, >+ { ARM64_INS_SHADD, "shadd" }, >+ { ARM64_INS_SHLL2, "shll2" }, >+ { ARM64_INS_SHLL, "shll" }, >+ { ARM64_INS_SHL, "shl" }, >+ { ARM64_INS_SHRN2, "shrn2" }, >+ { ARM64_INS_SHRN, "shrn" }, >+ { ARM64_INS_SHSUB, "shsub" }, >+ { ARM64_INS_SLI, "sli" }, >+ { ARM64_INS_SMADDL, "smaddl" }, >+ { ARM64_INS_SMAXP, "smaxp" }, >+ { ARM64_INS_SMAXV, "smaxv" }, >+ { ARM64_INS_SMAX, "smax" }, >+ { ARM64_INS_SMC, "smc" }, >+ { ARM64_INS_SMINP, "sminp" }, >+ { ARM64_INS_SMINV, "sminv" }, >+ { ARM64_INS_SMIN, "smin" }, >+ { ARM64_INS_SMLAL2, "smlal2" }, >+ { ARM64_INS_SMLAL, "smlal" }, >+ { ARM64_INS_SMLSL2, "smlsl2" }, >+ { ARM64_INS_SMLSL, "smlsl" }, >+ { ARM64_INS_SMOV, "smov" }, >+ { ARM64_INS_SMSUBL, "smsubl" }, >+ { ARM64_INS_SMULH, "smulh" }, >+ { ARM64_INS_SMULL2, "smull2" }, >+ { ARM64_INS_SMULL, "smull" }, >+ { ARM64_INS_SQABS, "sqabs" }, >+ { ARM64_INS_SQADD, "sqadd" }, >+ { ARM64_INS_SQDMLAL, "sqdmlal" }, >+ { ARM64_INS_SQDMLAL2, "sqdmlal2" }, >+ { ARM64_INS_SQDMLSL, "sqdmlsl" }, >+ { ARM64_INS_SQDMLSL2, "sqdmlsl2" }, >+ { ARM64_INS_SQDMULH, "sqdmulh" }, >+ { ARM64_INS_SQDMULL, "sqdmull" }, >+ { ARM64_INS_SQDMULL2, "sqdmull2" }, >+ { ARM64_INS_SQNEG, "sqneg" }, >+ { ARM64_INS_SQRDMULH, "sqrdmulh" }, >+ { ARM64_INS_SQRSHL, "sqrshl" }, >+ { ARM64_INS_SQRSHRN, "sqrshrn" }, >+ { ARM64_INS_SQRSHRN2, "sqrshrn2" }, >+ { ARM64_INS_SQRSHRUN, "sqrshrun" }, >+ { ARM64_INS_SQRSHRUN2, "sqrshrun2" }, >+ { ARM64_INS_SQSHLU, "sqshlu" }, >+ { ARM64_INS_SQSHL, "sqshl" }, >+ { ARM64_INS_SQSHRN, "sqshrn" }, >+ { ARM64_INS_SQSHRN2, "sqshrn2" }, >+ { ARM64_INS_SQSHRUN, "sqshrun" }, >+ { ARM64_INS_SQSHRUN2, "sqshrun2" }, >+ { ARM64_INS_SQSUB, "sqsub" }, >+ { ARM64_INS_SQXTN2, "sqxtn2" }, >+ { ARM64_INS_SQXTN, "sqxtn" }, >+ { ARM64_INS_SQXTUN2, "sqxtun2" }, >+ { ARM64_INS_SQXTUN, "sqxtun" }, >+ { ARM64_INS_SRHADD, "srhadd" }, >+ { ARM64_INS_SRI, "sri" }, >+ { ARM64_INS_SRSHL, "srshl" }, >+ { ARM64_INS_SRSHR, "srshr" }, >+ { ARM64_INS_SRSRA, "srsra" }, >+ { ARM64_INS_SSHLL2, "sshll2" }, >+ { ARM64_INS_SSHLL, "sshll" }, >+ { ARM64_INS_SSHL, "sshl" }, >+ { ARM64_INS_SSHR, "sshr" }, >+ { ARM64_INS_SSRA, "ssra" }, >+ { ARM64_INS_SSUBL2, "ssubl2" }, >+ { ARM64_INS_SSUBL, "ssubl" }, >+ { ARM64_INS_SSUBW2, "ssubw2" }, >+ { ARM64_INS_SSUBW, "ssubw" }, >+ { ARM64_INS_ST1, "st1" }, >+ { ARM64_INS_ST2, "st2" }, >+ { ARM64_INS_ST3, "st3" }, >+ { ARM64_INS_ST4, "st4" }, >+ { ARM64_INS_STLRB, "stlrb" }, >+ { ARM64_INS_STLRH, "stlrh" }, >+ { ARM64_INS_STLR, "stlr" }, >+ { ARM64_INS_STLXP, "stlxp" }, >+ { ARM64_INS_STLXRB, "stlxrb" }, >+ { ARM64_INS_STLXRH, "stlxrh" }, >+ { ARM64_INS_STLXR, "stlxr" }, >+ { ARM64_INS_STNP, "stnp" }, >+ { ARM64_INS_STP, "stp" }, >+ { ARM64_INS_STRB, "strb" }, >+ { ARM64_INS_STR, "str" }, >+ { ARM64_INS_STRH, "strh" }, >+ { ARM64_INS_STTRB, "sttrb" }, >+ { ARM64_INS_STTRH, "sttrh" }, >+ { ARM64_INS_STTR, "sttr" }, >+ { ARM64_INS_STURB, "sturb" }, >+ { ARM64_INS_STUR, "stur" }, >+ { ARM64_INS_STURH, "sturh" }, >+ { ARM64_INS_STXP, "stxp" }, >+ { ARM64_INS_STXRB, "stxrb" }, >+ { ARM64_INS_STXRH, "stxrh" }, >+ { ARM64_INS_STXR, "stxr" }, >+ { ARM64_INS_SUBHN, "subhn" }, >+ { ARM64_INS_SUBHN2, "subhn2" }, >+ { ARM64_INS_SUB, "sub" }, >+ { ARM64_INS_SUQADD, "suqadd" }, >+ { ARM64_INS_SVC, "svc" }, >+ { ARM64_INS_SYSL, "sysl" }, >+ { ARM64_INS_SYS, "sys" }, >+ { ARM64_INS_TBL, "tbl" }, >+ { ARM64_INS_TBNZ, "tbnz" }, >+ { ARM64_INS_TBX, "tbx" }, >+ { ARM64_INS_TBZ, "tbz" }, >+ { ARM64_INS_TRN1, "trn1" }, >+ { ARM64_INS_TRN2, "trn2" }, >+ { ARM64_INS_UABAL2, "uabal2" }, >+ { ARM64_INS_UABAL, "uabal" }, >+ { ARM64_INS_UABA, "uaba" }, >+ { ARM64_INS_UABDL2, "uabdl2" }, >+ { ARM64_INS_UABDL, "uabdl" }, >+ { ARM64_INS_UABD, "uabd" }, >+ { ARM64_INS_UADALP, "uadalp" }, >+ { ARM64_INS_UADDLP, "uaddlp" }, >+ { ARM64_INS_UADDLV, "uaddlv" }, >+ { ARM64_INS_UADDL2, "uaddl2" }, >+ { ARM64_INS_UADDL, "uaddl" }, >+ { ARM64_INS_UADDW2, "uaddw2" }, >+ { ARM64_INS_UADDW, "uaddw" }, >+ { ARM64_INS_UBFM, "ubfm" }, >+ { ARM64_INS_UCVTF, "ucvtf" }, >+ { ARM64_INS_UDIV, "udiv" }, >+ { ARM64_INS_UHADD, "uhadd" }, >+ { ARM64_INS_UHSUB, "uhsub" }, >+ { ARM64_INS_UMADDL, "umaddl" }, >+ { ARM64_INS_UMAXP, "umaxp" }, >+ { ARM64_INS_UMAXV, "umaxv" }, >+ { ARM64_INS_UMAX, "umax" }, >+ { ARM64_INS_UMINP, "uminp" }, >+ { ARM64_INS_UMINV, "uminv" }, >+ { ARM64_INS_UMIN, "umin" }, >+ { ARM64_INS_UMLAL2, "umlal2" }, >+ { ARM64_INS_UMLAL, "umlal" }, >+ { ARM64_INS_UMLSL2, "umlsl2" }, >+ { ARM64_INS_UMLSL, "umlsl" }, >+ { ARM64_INS_UMOV, "umov" }, >+ { ARM64_INS_UMSUBL, "umsubl" }, >+ { ARM64_INS_UMULH, "umulh" }, >+ { ARM64_INS_UMULL2, "umull2" }, >+ { ARM64_INS_UMULL, "umull" }, >+ { ARM64_INS_UQADD, "uqadd" }, >+ { ARM64_INS_UQRSHL, "uqrshl" }, >+ { ARM64_INS_UQRSHRN, "uqrshrn" }, >+ { ARM64_INS_UQRSHRN2, "uqrshrn2" }, >+ { ARM64_INS_UQSHL, "uqshl" }, >+ { ARM64_INS_UQSHRN, "uqshrn" }, >+ { ARM64_INS_UQSHRN2, "uqshrn2" }, >+ { ARM64_INS_UQSUB, "uqsub" }, >+ { ARM64_INS_UQXTN2, "uqxtn2" }, >+ { ARM64_INS_UQXTN, "uqxtn" }, >+ { ARM64_INS_URECPE, "urecpe" }, >+ { ARM64_INS_URHADD, "urhadd" }, >+ { ARM64_INS_URSHL, "urshl" }, >+ { ARM64_INS_URSHR, "urshr" }, >+ { ARM64_INS_URSQRTE, "ursqrte" }, >+ { ARM64_INS_URSRA, "ursra" }, >+ { ARM64_INS_USHLL2, "ushll2" }, >+ { ARM64_INS_USHLL, "ushll" }, >+ { ARM64_INS_USHL, "ushl" }, >+ { ARM64_INS_USHR, "ushr" }, >+ { ARM64_INS_USQADD, "usqadd" }, >+ { ARM64_INS_USRA, "usra" }, >+ { ARM64_INS_USUBL2, "usubl2" }, >+ { ARM64_INS_USUBL, "usubl" }, >+ { ARM64_INS_USUBW2, "usubw2" }, >+ { ARM64_INS_USUBW, "usubw" }, >+ { ARM64_INS_UZP1, "uzp1" }, >+ { ARM64_INS_UZP2, "uzp2" }, >+ { ARM64_INS_XTN2, "xtn2" }, >+ { ARM64_INS_XTN, "xtn" }, >+ { ARM64_INS_ZIP1, "zip1" }, >+ { ARM64_INS_ZIP2, "zip2" }, >+}; >+ >+// map *S & alias instructions back to original id >+static const name_map alias_insn_name_maps[] = { >+ { ARM64_INS_ADC, "adcs" }, >+ { ARM64_INS_AND, "ands" }, >+ { ARM64_INS_ADD, "adds" }, >+ { ARM64_INS_BIC, "bics" }, >+ { ARM64_INS_SBC, "sbcs" }, >+ { ARM64_INS_SUB, "subs" }, >+ >+ // alias insn >+ { ARM64_INS_MNEG, "mneg" }, >+ { ARM64_INS_UMNEGL, "umnegl" }, >+ { ARM64_INS_SMNEGL, "smnegl" }, >+ { ARM64_INS_NOP, "nop" }, >+ { ARM64_INS_YIELD, "yield" }, >+ { ARM64_INS_WFE, "wfe" }, >+ { ARM64_INS_WFI, "wfi" }, >+ { ARM64_INS_SEV, "sev" }, >+ { ARM64_INS_SEVL, "sevl" }, >+ { ARM64_INS_NGC, "ngc" }, >+ { ARM64_INS_NGCS, "ngcs" }, >+ { ARM64_INS_NEGS, "negs" }, >+ >+ { ARM64_INS_SBFIZ, "sbfiz" }, >+ { ARM64_INS_UBFIZ, "ubfiz" }, >+ { ARM64_INS_SBFX, "sbfx" }, >+ { ARM64_INS_UBFX, "ubfx" }, >+ { ARM64_INS_BFI, "bfi" }, >+ { ARM64_INS_BFXIL, "bfxil" }, >+ { ARM64_INS_CMN, "cmn" }, >+ { ARM64_INS_MVN, "mvn" }, >+ { ARM64_INS_TST, "tst" }, >+ { ARM64_INS_CSET, "cset" }, >+ { ARM64_INS_CINC, "cinc" }, >+ { ARM64_INS_CSETM, "csetm" }, >+ { ARM64_INS_CINV, "cinv" }, >+ { ARM64_INS_CNEG, "cneg" }, >+ { ARM64_INS_SXTB, "sxtb" }, >+ { ARM64_INS_SXTH, "sxth" }, >+ { ARM64_INS_SXTW, "sxtw" }, >+ { ARM64_INS_CMP, "cmp" }, >+ { ARM64_INS_UXTB, "uxtb" }, >+ { ARM64_INS_UXTH, "uxth" }, >+ { ARM64_INS_UXTW, "uxtw" }, >+ >+ { ARM64_INS_IC, "ic" }, >+ { ARM64_INS_DC, "dc" }, >+ { ARM64_INS_AT, "at" }, >+ { ARM64_INS_TLBI, "tlbi" }, >+}; >+ >+const char *AArch64_insn_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ unsigned int i; >+ >+ if (id >= ARM64_INS_ENDING) >+ return NULL; >+ >+ if (id < ARR_SIZE(insn_name_maps)) >+ return insn_name_maps[id].name; >+ >+ // then find alias insn >+ for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { >+ if (alias_insn_name_maps[i].id == id) >+ return alias_insn_name_maps[i].name; >+ } >+ >+ // not found >+ return NULL; >+#else >+ return NULL; >+#endif >+} >+ >+#ifndef CAPSTONE_DIET >+static const name_map group_name_maps[] = { >+ // generic groups >+ { ARM64_GRP_INVALID, NULL }, >+ { ARM64_GRP_JUMP, "jump" }, >+ >+ // architecture-specific groups >+ { ARM64_GRP_CRYPTO, "crypto" }, >+ { ARM64_GRP_FPARMV8, "fparmv8" }, >+ { ARM64_GRP_NEON, "neon" }, >+ { ARM64_GRP_CRC, "crc" }, >+ >+}; >+#endif >+ >+const char *AArch64_group_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ // verify group id >+ if (id >= ARM64_GRP_ENDING || (id > ARM64_GRP_JUMP && id < ARM64_GRP_CRYPTO)) >+ return NULL; >+ >+ // NOTE: when new generic groups are added, 2 must be changed accordingly >+ if (id >= 128) >+ return group_name_maps[id - 128 + 2].name; >+ else >+ return group_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+// map instruction name to public instruction ID >+arm64_reg AArch64_map_insn(const char *name) >+{ >+ // NOTE: skip first NULL name in insn_name_maps >+ int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); >+ >+ if (i == -1) >+ // try again with 'special' insn that is not available in insn_name_maps >+ i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); >+ >+ return (i != -1)? i : ARM64_REG_INVALID; >+} >+ >+// map internal raw vregister to 'public' register >+arm64_reg AArch64_map_vregister(unsigned int r) >+{ >+ // for some reasons different Arm64 can map different register number to >+ // the same register. this function handles the issue for exposing Mips >+ // operands by mapping internal registers to 'public' register. >+ static const unsigned int map[] = { 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, ARM64_REG_V0, >+ ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, >+ ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, >+ ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, >+ ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, >+ ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, >+ ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, >+ ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, >+ 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, >+ ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, >+ ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, >+ ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, >+ ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, >+ ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, >+ ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, 0, 0, 0, >+ 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, >+ ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, >+ ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, >+ ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, >+ ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, >+ ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, >+ ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, >+ ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, >+ ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, >+ ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, >+ ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, >+ ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, >+ ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, >+ ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, >+ ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, >+ ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, >+ ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, >+ ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, >+ ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, >+ ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, >+ ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, >+ ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, >+ ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, >+ ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, >+ ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, >+ ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, >+ ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, >+ ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, >+ ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, >+ ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, >+ ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, >+ ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, >+ ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, >+ ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, >+ ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, >+ ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, >+ ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, >+ ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, >+ ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, }; >+ >+ if (r < ARR_SIZE(map)) >+ return map[r]; >+ >+ // cannot find this register >+ return 0; >+} >+ >+void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vas = sp; >+ } >+} >+ >+void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp; >+ } >+} >+ >+void arm64_op_addFP(MCInst *MI, float fp) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = fp; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+void arm64_op_addImm(MCInst *MI, int64_t imm) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; >+ MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)imm; >+ MI->flat_insn->detail->arm64.op_count++; >+ } >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.h b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.h >new file mode 100644 >index 0000000000000000000000000000000000000000..69edef929aed84a749264234ba240f604933708f >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Mapping.h >@@ -0,0 +1,35 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_ARM64_MAP_H >+#define CS_ARM64_MAP_H >+ >+#include "../../include/capstone.h" >+ >+// return name of regiser in friendly string >+const char *AArch64_reg_name(csh handle, unsigned int reg); >+ >+// given internal insn id, return public instruction info >+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+const char *AArch64_insn_name(csh handle, unsigned int id); >+ >+const char *AArch64_group_name(csh handle, unsigned int id); >+ >+// map instruction name to public instruction ID >+arm64_reg AArch64_map_insn(const char *name); >+ >+// map internal vregister to public register >+arm64_reg AArch64_map_vregister(unsigned int r); >+ >+void arm64_op_addReg(MCInst *MI, int reg); >+ >+void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); >+ >+void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp); >+ >+void arm64_op_addFP(MCInst *MI, float fp); >+ >+void arm64_op_addImm(MCInst *MI, int64_t imm); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Module.c b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Module.c >new file mode 100644 >index 0000000000000000000000000000000000000000..3894455bfa11eec98dc03e9ccf7a53ad8ad86a16 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/AArch64/AArch64Module.c >@@ -0,0 +1,55 @@ >+/* Capstone Disassembly Engine */ >+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ >+ >+#ifdef CAPSTONE_HAS_ARM64 >+ >+#include "../../utils.h" >+#include "../../MCRegisterInfo.h" >+#include "AArch64Disassembler.h" >+#include "AArch64InstPrinter.h" >+#include "AArch64Mapping.h" >+ >+static cs_err init(cs_struct *ud) >+{ >+ MCRegisterInfo *mri; >+ mri = cs_mem_malloc(sizeof(*mri)); >+ >+ AArch64_init(mri); >+ ud->printer = AArch64_printInst; >+ ud->printer_info = mri; >+ ud->getinsn_info = mri; >+ ud->disasm = AArch64_getInstruction; >+ ud->reg_name = AArch64_reg_name; >+ ud->insn_id = AArch64_get_insn_id; >+ ud->insn_name = AArch64_insn_name; >+ ud->group_name = AArch64_group_name; >+ ud->post_printer = AArch64_post_printer; >+ >+ return CS_ERR_OK; >+} >+ >+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) >+{ >+ if (type == CS_OPT_MODE) { >+ handle->mode = (cs_mode)value; >+ } >+ >+ return CS_ERR_OK; >+} >+ >+static void destroy(cs_struct *handle) >+{ >+} >+ >+void AArch64_enable(void) >+{ >+ cs_arch_init[CS_ARCH_ARM64] = init; >+ cs_arch_option[CS_ARCH_ARM64] = option; >+ cs_arch_destroy[CS_ARCH_ARM64] = destroy; >+ cs_arch_disallowed_mode_mask[CS_ARCH_ARM64] = ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN); >+ >+ // support this arch >+ all_arch |= (1 << CS_ARCH_ARM64); >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h b/Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h >new file mode 100644 >index 0000000000000000000000000000000000000000..fcf0abfcfb82ca7b88bd9113c4c264740d3cfadb >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMAddressingModes.h >@@ -0,0 +1,670 @@ >+//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains the ARM addressing mode implementation stuff. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H >+#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H >+ >+#include "../../include/platform.h" >+#include "../../MathExtras.h" >+ >+/// ARM_AM - ARM Addressing Mode Stuff >+typedef enum ARM_AM_ShiftOpc { >+ ARM_AM_no_shift = 0, >+ ARM_AM_asr, >+ ARM_AM_lsl, >+ ARM_AM_lsr, >+ ARM_AM_ror, >+ ARM_AM_rrx >+} ARM_AM_ShiftOpc; >+ >+typedef enum ARM_AM_AddrOpc { >+ ARM_AM_sub = 0, >+ ARM_AM_add >+} ARM_AM_AddrOpc; >+ >+static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op) >+{ >+ return Op == ARM_AM_sub ? "-" : ""; >+} >+ >+static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op) >+{ >+ switch (Op) { >+ default: return ""; //llvm_unreachable("Unknown shift opc!"); >+ case ARM_AM_asr: return "asr"; >+ case ARM_AM_lsl: return "lsl"; >+ case ARM_AM_lsr: return "lsr"; >+ case ARM_AM_ror: return "ror"; >+ case ARM_AM_rrx: return "rrx"; >+ } >+} >+ >+static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op) >+{ >+ switch (Op) { >+ default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!"); >+ case ARM_AM_asr: return 2; >+ case ARM_AM_lsl: return 0; >+ case ARM_AM_lsr: return 1; >+ case ARM_AM_ror: return 3; >+ } >+} >+ >+typedef enum ARM_AM_AMSubMode { >+ ARM_AM_bad_am_submode = 0, >+ ARM_AM_ia, >+ ARM_AM_ib, >+ ARM_AM_da, >+ ARM_AM_db >+} ARM_AM_AMSubMode; >+ >+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode) >+{ >+ switch (Mode) { >+ default: return ""; >+ case ARM_AM_ia: return "ia"; >+ case ARM_AM_ib: return "ib"; >+ case ARM_AM_da: return "da"; >+ case ARM_AM_db: return "db"; >+ } >+} >+ >+/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. >+/// >+static inline unsigned rotr32(unsigned Val, unsigned Amt) >+{ >+ //assert(Amt < 32 && "Invalid rotate amount"); >+ return (Val >> Amt) | (Val << ((32-Amt)&31)); >+} >+ >+/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. >+/// >+static inline unsigned rotl32(unsigned Val, unsigned Amt) >+{ >+ //assert(Amt < 32 && "Invalid rotate amount"); >+ return (Val << Amt) | (Val >> ((32-Amt)&31)); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #1: shift_operand with registers >+//===--------------------------------------------------------------------===// >+// >+// This 'addressing mode' is used for arithmetic instructions. It can >+// represent things like: >+// reg >+// reg [asr|lsl|lsr|ror|rrx] reg >+// reg [asr|lsl|lsr|ror|rrx] imm >+// >+// This is stored three operands [rega, regb, opc]. The first is the base >+// reg, the second is the shift amount (or reg0 if not present or imm). The >+// third operand encodes the shift opcode and the imm if a reg isn't present. >+// >+static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) >+{ >+ return ShOp | (Imm << 3); >+} >+ >+static inline unsigned getSORegOffset(unsigned Op) >+{ >+ return Op >> 3; >+} >+ >+static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op) >+{ >+ return (ARM_AM_ShiftOpc)(Op & 7); >+} >+ >+/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return >+/// the 8-bit imm value. >+static inline unsigned getSOImmValImm(unsigned Imm) >+{ >+ return Imm & 0xFF; >+} >+ >+/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return >+/// the rotate amount. >+static inline unsigned getSOImmValRot(unsigned Imm) >+{ >+ return (Imm >> 8) * 2; >+} >+ >+/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, >+/// computing the rotate amount to use. If this immediate value cannot be >+/// handled with a single shifter-op, determine a good rotate amount that will >+/// take a maximal chunk of bits out of the immediate. >+static inline unsigned getSOImmValRotate(unsigned Imm) >+{ >+ unsigned TZ, RotAmt; >+ // 8-bit (or less) immediates are trivially shifter_operands with a rotate >+ // of zero. >+ if ((Imm & ~255U) == 0) return 0; >+ >+ // Use CTZ to compute the rotate amount. >+ TZ = CountTrailingZeros_32(Imm); >+ >+ // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, >+ // not 9. >+ RotAmt = TZ & ~1; >+ >+ // If we can handle this spread, return it. >+ if ((rotr32(Imm, RotAmt) & ~255U) == 0) >+ return (32-RotAmt)&31; // HW rotates right, not left. >+ >+ // For values like 0xF000000F, we should ignore the low 6 bits, then >+ // retry the hunt. >+ if (Imm & 63U) { >+ unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); >+ unsigned RotAmt2 = TZ2 & ~1; >+ if ((rotr32(Imm, RotAmt2) & ~255U) == 0) >+ return (32-RotAmt2)&31; // HW rotates right, not left. >+ } >+ >+ // Otherwise, we have no way to cover this span of bits with a single >+ // shifter_op immediate. Return a chunk of bits that will be useful to >+ // handle. >+ return (32-RotAmt)&31; // HW rotates right, not left. >+} >+ >+/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit >+/// into an shifter_operand immediate operand, return the 12-bit encoding for >+/// it. If not, return -1. >+static inline int getSOImmVal(unsigned Arg) >+{ >+ unsigned RotAmt; >+ // 8-bit (or less) immediates are trivially shifter_operands with a rotate >+ // of zero. >+ if ((Arg & ~255U) == 0) return Arg; >+ >+ RotAmt = getSOImmValRotate(Arg); >+ >+ // If this cannot be handled with a single shifter_op, bail out. >+ if (rotr32(~255U, RotAmt) & Arg) >+ return -1; >+ >+ // Encode this correctly. >+ return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); >+} >+ >+/// isSOImmTwoPartVal - Return true if the specified value can be obtained by >+/// or'ing together two SOImmVal's. >+static inline bool isSOImmTwoPartVal(unsigned V) >+{ >+ // If this can be handled with a single shifter_op, bail out. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ if (V == 0) >+ return false; >+ >+ // If this can be handled with two shifter_op's, accept. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ return V == 0; >+} >+ >+/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, >+/// return the first chunk of it. >+static inline unsigned getSOImmTwoPartFirst(unsigned V) >+{ >+ return rotr32(255U, getSOImmValRotate(V)) & V; >+} >+ >+/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, >+/// return the second chunk of it. >+static inline unsigned getSOImmTwoPartSecond(unsigned V) >+{ >+ // Mask out the first hunk. >+ V = rotr32(~255U, getSOImmValRotate(V)) & V; >+ >+ // Take what's left. >+ //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); >+ return V; >+} >+ >+/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed >+/// by a left shift. Returns the shift amount to use. >+static inline unsigned getThumbImmValShift(unsigned Imm) >+{ >+ // 8-bit (or less) immediates are trivially immediate operand with a shift >+ // of zero. >+ if ((Imm & ~255U) == 0) return 0; >+ >+ // Use CTZ to compute the shift amount. >+ return CountTrailingZeros_32(Imm); >+} >+ >+/// isThumbImmShiftedVal - Return true if the specified value can be obtained >+/// by left shifting a 8-bit immediate. >+static inline bool isThumbImmShiftedVal(unsigned V) >+{ >+ // If this can be handled with >+ V = (~255U << getThumbImmValShift(V)) & V; >+ return V == 0; >+} >+ >+/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed >+/// by a left shift. Returns the shift amount to use. >+static inline unsigned getThumbImm16ValShift(unsigned Imm) >+{ >+ // 16-bit (or less) immediates are trivially immediate operand with a shift >+ // of zero. >+ if ((Imm & ~65535U) == 0) return 0; >+ >+ // Use CTZ to compute the shift amount. >+ return CountTrailingZeros_32(Imm); >+} >+ >+/// isThumbImm16ShiftedVal - Return true if the specified value can be >+/// obtained by left shifting a 16-bit immediate. >+static inline bool isThumbImm16ShiftedVal(unsigned V) >+{ >+ // If this can be handled with >+ V = (~65535U << getThumbImm16ValShift(V)) & V; >+ return V == 0; >+} >+ >+/// getThumbImmNonShiftedVal - If V is a value that satisfies >+/// isThumbImmShiftedVal, return the non-shiftd value. >+static inline unsigned getThumbImmNonShiftedVal(unsigned V) >+{ >+ return V >> getThumbImmValShift(V); >+} >+ >+ >+/// getT2SOImmValSplat - Return the 12-bit encoded representation >+/// if the specified value can be obtained by splatting the low 8 bits >+/// into every other byte or every byte of a 32-bit value. i.e., >+/// 00000000 00000000 00000000 abcdefgh control = 0 >+/// 00000000 abcdefgh 00000000 abcdefgh control = 1 >+/// abcdefgh 00000000 abcdefgh 00000000 control = 2 >+/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 >+/// Return -1 if none of the above apply. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmValSplatVal(unsigned V) >+{ >+ unsigned u, Vs, Imm; >+ // control = 0 >+ if ((V & 0xffffff00) == 0) >+ return V; >+ >+ // If the value is zeroes in the first byte, just shift those off >+ Vs = ((V & 0xff) == 0) ? V >> 8 : V; >+ // Any passing value only has 8 bits of payload, splatted across the word >+ Imm = Vs & 0xff; >+ // Likewise, any passing values have the payload splatted into the 3rd byte >+ u = Imm | (Imm << 16); >+ >+ // control = 1 or 2 >+ if (Vs == u) >+ return (((Vs == V) ? 1 : 2) << 8) | Imm; >+ >+ // control = 3 >+ if (Vs == (u | (u << 8))) >+ return (3 << 8) | Imm; >+ >+ return -1; >+} >+ >+/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the >+/// specified value is a rotated 8-bit value. Return -1 if no rotation >+/// encoding is possible. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmValRotateVal(unsigned V) >+{ >+ unsigned RotAmt = CountLeadingZeros_32(V); >+ if (RotAmt >= 24) >+ return -1; >+ >+ // If 'Arg' can be handled with a single shifter_op return the value. >+ if ((rotr32(0xff000000U, RotAmt) & V) == V) >+ return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); >+ >+ return -1; >+} >+ >+/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit >+/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit >+/// encoding for it. If not, return -1. >+/// See ARM Reference Manual A6.3.2. >+static inline int getT2SOImmVal(unsigned Arg) >+{ >+ int Rot; >+ // If 'Arg' is an 8-bit splat, then get the encoded value. >+ int Splat = getT2SOImmValSplatVal(Arg); >+ if (Splat != -1) >+ return Splat; >+ >+ // If 'Arg' can be handled with a single shifter_op return the value. >+ Rot = getT2SOImmValRotateVal(Arg); >+ if (Rot != -1) >+ return Rot; >+ >+ return -1; >+} >+ >+static inline unsigned getT2SOImmValRotate(unsigned V) >+{ >+ unsigned RotAmt; >+ >+ if ((V & ~255U) == 0) >+ return 0; >+ >+ // Use CTZ to compute the rotate amount. >+ RotAmt = CountTrailingZeros_32(V); >+ return (32 - RotAmt) & 31; >+} >+ >+static inline bool isT2SOImmTwoPartVal (unsigned Imm) >+{ >+ unsigned V = Imm; >+ // Passing values can be any combination of splat values and shifter >+ // values. If this can be handled with a single shifter or splat, bail >+ // out. Those should be handled directly, not with a two-part val. >+ if (getT2SOImmValSplatVal(V) != -1) >+ return false; >+ V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; >+ if (V == 0) >+ return false; >+ >+ // If this can be handled as an immediate, accept. >+ if (getT2SOImmVal(V) != -1) return true; >+ >+ // Likewise, try masking out a splat value first. >+ V = Imm; >+ if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) >+ V &= ~0xff00ff00U; >+ else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) >+ V &= ~0x00ff00ffU; >+ // If what's left can be handled as an immediate, accept. >+ if (getT2SOImmVal(V) != -1) return true; >+ >+ // Otherwise, do not accept. >+ return false; >+} >+ >+static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) >+{ >+ //assert (isT2SOImmTwoPartVal(Imm) && >+ // "Immedate cannot be encoded as two part immediate!"); >+ // Try a shifter operand as one part >+ unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm; >+ // If the rest is encodable as an immediate, then return it. >+ if (getT2SOImmVal(V) != -1) return V; >+ >+ // Try masking out a splat value first. >+ if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) >+ return Imm & 0xff00ff00U; >+ >+ // The other splat is all that's left as an option. >+ //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); >+ return Imm & 0x00ff00ffU; >+} >+ >+static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) >+{ >+ // Mask out the first hunk >+ Imm ^= getT2SOImmTwoPartFirst(Imm); >+ // Return what's left >+ //assert (getT2SOImmVal(Imm) != -1 && >+ // "Unable to encode second part of T2 two part SO immediate"); >+ return Imm; >+} >+ >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #2 >+//===--------------------------------------------------------------------===// >+// >+// This is used for most simple load/store instructions. >+// >+// addrmode2 := reg +/- reg shop imm >+// addrmode2 := reg +/- imm12 >+// >+// The first operand is always a Reg. The second operand is a reg if in >+// reg/reg form, otherwise it's reg#0. The third field encodes the operation >+// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The >+// fourth operand 16-17 encodes the index mode. >+// >+// If this addressing mode is a frame index (before prolog/epilog insertion >+// and code rewriting), this operand will have the form: FI#, reg0, <offs> >+// with no shift amount for the frame offset. >+// >+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, >+ unsigned IdxMode) >+{ >+ //assert(Imm12 < (1 << 12) && "Imm too large!"); >+ bool isSub = Opc == ARM_AM_sub; >+ return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; >+} >+ >+static inline unsigned getAM2Offset(unsigned AM2Opc) >+{ >+ return AM2Opc & ((1 << 12)-1); >+} >+ >+static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc) >+{ >+ return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) >+{ >+ return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7); >+} >+ >+static inline unsigned getAM2IdxMode(unsigned AM2Opc) >+{ >+ return (AM2Opc >> 16); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #3 >+//===--------------------------------------------------------------------===// >+// >+// This is used for sign-extending loads, and load/store-pair instructions. >+// >+// addrmode3 := reg +/- reg >+// addrmode3 := reg +/- imm8 >+// >+// The first operand is always a Reg. The second operand is a reg if in >+// reg/reg form, otherwise it's reg#0. The third field encodes the operation >+// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the >+// index mode. >+ >+/// getAM3Opc - This function encodes the addrmode3 opc field. >+static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset, >+ unsigned IdxMode) >+{ >+ bool isSub = Opc == ARM_AM_sub; >+ return ((int)isSub << 8) | Offset | (IdxMode << 9); >+} >+ >+static inline unsigned char getAM3Offset(unsigned AM3Opc) >+{ >+ return AM3Opc & 0xFF; >+} >+ >+static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc) >+{ >+ return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+static inline unsigned getAM3IdxMode(unsigned AM3Opc) >+{ >+ return (AM3Opc >> 9); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #4 >+//===--------------------------------------------------------------------===// >+// >+// This is used for load / store multiple instructions. >+// >+// addrmode4 := reg, <mode> >+// >+// The four modes are: >+// IA - Increment after >+// IB - Increment before >+// DA - Decrement after >+// DB - Decrement before >+// For VFP instructions, only the IA and DB modes are valid. >+ >+static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode) >+{ >+ return (ARM_AM_AMSubMode)(Mode & 0x7); >+} >+ >+static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode) >+{ >+ return (int)SubMode; >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #5 >+//===--------------------------------------------------------------------===// >+// >+// This is used for coprocessor instructions, such as FP load/stores. >+// >+// addrmode5 := reg +/- imm8*4 >+// >+// The first operand is always a Reg. The second operand encodes the >+// operation in bit 8 and the immediate in bits 0-7. >+ >+/// getAM5Opc - This function encodes the addrmode5 opc field. >+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset) >+{ >+ bool isSub = Opc == ARM_AM_sub; >+ return ((int)isSub << 8) | Offset; >+} >+static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc) >+{ >+ return AM5Opc & 0xFF; >+} >+static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc) >+{ >+ return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add; >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #6 >+//===--------------------------------------------------------------------===// >+// >+// This is used for NEON load / store instructions. >+// >+// addrmode6 := reg with optional alignment >+// >+// This is stored in two operands [regaddr, align]. The first is the >+// address register. The second operand is the value of the alignment >+// specifier in bytes or zero if no explicit alignment. >+// Valid alignments depend on the specific instruction. >+ >+//===--------------------------------------------------------------------===// >+// NEON Modified Immediates >+//===--------------------------------------------------------------------===// >+// >+// Several NEON instructions (e.g., VMOV) take a "modified immediate" >+// vector operand, where a small immediate encoded in the instruction >+// specifies a full NEON vector value. These modified immediates are >+// represented here as encoded integers. The low 8 bits hold the immediate >+// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold >+// the "Cmode" field of the instruction. The interfaces below treat the >+// Op and Cmode values as a single 5-bit value. >+ >+static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) >+{ >+ return (OpCmode << 8) | Val; >+} >+static inline unsigned getNEONModImmOpCmode(unsigned ModImm) >+{ >+ return (ModImm >> 8) & 0x1f; >+} >+static inline unsigned getNEONModImmVal(unsigned ModImm) >+{ >+ return ModImm & 0xff; >+} >+ >+/// decodeNEONModImm - Decode a NEON modified immediate value into the >+/// element value and the element size in bits. (If the element size is >+/// smaller than the vector, it is splatted into all the elements.) >+static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits) >+{ >+ unsigned OpCmode = getNEONModImmOpCmode(ModImm); >+ unsigned Imm8 = getNEONModImmVal(ModImm); >+ uint64_t Val = 0; >+ unsigned ByteNum; >+ >+ if (OpCmode == 0xe) { >+ // 8-bit vector elements >+ Val = Imm8; >+ *EltBits = 8; >+ } else if ((OpCmode & 0xc) == 0x8) { >+ // 16-bit vector elements >+ ByteNum = (OpCmode & 0x6) >> 1; >+ Val = (uint64_t)Imm8 << (8 * ByteNum); >+ *EltBits = 16; >+ } else if ((OpCmode & 0x8) == 0) { >+ // 32-bit vector elements, zero with one byte set >+ ByteNum = (OpCmode & 0x6) >> 1; >+ Val = (uint64_t)Imm8 << (8 * ByteNum); >+ *EltBits = 32; >+ } else if ((OpCmode & 0xe) == 0xc) { >+ // 32-bit vector elements, one byte with low bits set >+ ByteNum = 1 + (OpCmode & 0x1); >+ Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); >+ *EltBits = 32; >+ } else if (OpCmode == 0x1e) { >+ // 64-bit vector elements >+ for (ByteNum = 0; ByteNum < 8; ++ByteNum) { >+ if ((ModImm >> ByteNum) & 1) >+ Val |= (uint64_t)0xff << (8 * ByteNum); >+ } >+ *EltBits = 64; >+ } else { >+ //llvm_unreachable("Unsupported NEON immediate"); >+ } >+ return Val; >+} >+ >+ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode); >+ >+//===--------------------------------------------------------------------===// >+// Floating-point Immediates >+// >+static inline float getFPImmFloat(unsigned Imm) >+{ >+ // We expect an 8-bit binary encoding of a floating-point number here. >+ union { >+ uint32_t I; >+ float F; >+ } FPUnion; >+ >+ uint8_t Sign = (Imm >> 7) & 0x1; >+ uint8_t Exp = (Imm >> 4) & 0x7; >+ uint8_t Mantissa = Imm & 0xf; >+ >+ // 8-bit FP iEEEE Float Encoding >+ // abcd efgh aBbbbbbc defgh000 00000000 00000000 >+ // >+ // where B = NOT(b); >+ >+ FPUnion.I = 0; >+ FPUnion.I |= Sign << 31; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; >+ FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; >+ FPUnion.I |= (Exp & 0x3) << 23; >+ FPUnion.I |= Mantissa << 19; >+ return FPUnion.F; >+} >+ >+#endif >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h b/Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h >new file mode 100644 >index 0000000000000000000000000000000000000000..3c3e6bc1eea002295bca834588e2753bbd517b3c >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMBaseInfo.h >@@ -0,0 +1,432 @@ >+//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains small standalone helper functions and enum definitions for >+// the ARM target useful for the compiler back-end and the MC libraries. >+// As such, it deliberately does not include references to LLVM core >+// code gen types, passes, etc.. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_ARMBASEINFO_H >+#define CS_ARMBASEINFO_H >+ >+#include "../../include/arm.h" >+ >+// Defines symbolic names for ARM registers. This defines a mapping from >+// register name to register number. >+// >+#define GET_REGINFO_ENUM >+#include "ARMGenRegisterInfo.inc" >+ >+// Enums corresponding to ARM condition codes >+// The CondCodes constants map directly to the 4-bit encoding of the >+// condition field for predicated instructions. >+typedef enum ARMCC_CondCodes { // Meaning (integer) Meaning (floating-point) >+ ARMCC_EQ, // Equal Equal >+ ARMCC_NE, // Not equal Not equal, or unordered >+ ARMCC_HS, // Carry set >, ==, or unordered >+ ARMCC_LO, // Carry clear Less than >+ ARMCC_MI, // Minus, negative Less than >+ ARMCC_PL, // Plus, positive or zero >, ==, or unordered >+ ARMCC_VS, // Overflow Unordered >+ ARMCC_VC, // No overflow Not unordered >+ ARMCC_HI, // Unsigned higher Greater than, or unordered >+ ARMCC_LS, // Unsigned lower or same Less than or equal >+ ARMCC_GE, // Greater than or equal Greater than or equal >+ ARMCC_LT, // Less than Less than, or unordered >+ ARMCC_GT, // Greater than Greater than >+ ARMCC_LE, // Less than or equal <, ==, or unordered >+ ARMCC_AL // Always (unconditional) Always (unconditional) >+} ARMCC_CondCodes; >+ >+inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC) >+{ >+ switch (CC) { >+ case ARMCC_EQ: return ARMCC_NE; >+ case ARMCC_NE: return ARMCC_EQ; >+ case ARMCC_HS: return ARMCC_LO; >+ case ARMCC_LO: return ARMCC_HS; >+ case ARMCC_MI: return ARMCC_PL; >+ case ARMCC_PL: return ARMCC_MI; >+ case ARMCC_VS: return ARMCC_VC; >+ case ARMCC_VC: return ARMCC_VS; >+ case ARMCC_HI: return ARMCC_LS; >+ case ARMCC_LS: return ARMCC_HI; >+ case ARMCC_GE: return ARMCC_LT; >+ case ARMCC_LT: return ARMCC_GE; >+ case ARMCC_GT: return ARMCC_LE; >+ case ARMCC_LE: return ARMCC_GT; >+ default: return ARMCC_AL; >+ } >+} >+ >+inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC) >+{ >+ switch (CC) { >+ case ARMCC_EQ: return "eq"; >+ case ARMCC_NE: return "ne"; >+ case ARMCC_HS: return "hs"; >+ case ARMCC_LO: return "lo"; >+ case ARMCC_MI: return "mi"; >+ case ARMCC_PL: return "pl"; >+ case ARMCC_VS: return "vs"; >+ case ARMCC_VC: return "vc"; >+ case ARMCC_HI: return "hi"; >+ case ARMCC_LS: return "ls"; >+ case ARMCC_GE: return "ge"; >+ case ARMCC_LT: return "lt"; >+ case ARMCC_GT: return "gt"; >+ case ARMCC_LE: return "le"; >+ case ARMCC_AL: return "al"; >+ default: return ""; >+ } >+} >+ >+inline static const char *ARM_PROC_IFlagsToString(unsigned val) >+{ >+ switch (val) { >+ case ARM_CPSFLAG_F: return "f"; >+ case ARM_CPSFLAG_I: return "i"; >+ case ARM_CPSFLAG_A: return "a"; >+ default: return ""; >+ } >+} >+ >+inline static const char *ARM_PROC_IModToString(unsigned val) >+{ >+ switch (val) { >+ case ARM_CPSMODE_IE: return "ie"; >+ case ARM_CPSMODE_ID: return "id"; >+ default: return ""; >+ } >+} >+ >+inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8) >+{ >+ switch (val) { >+ default: return "BUGBUG"; >+ case ARM_MB_SY: return "sy"; >+ case ARM_MB_ST: return "st"; >+ case ARM_MB_LD: return HasV8 ? "ld" : "#0xd"; >+ case ARM_MB_RESERVED_12: return "#0xc"; >+ case ARM_MB_ISH: return "ish"; >+ case ARM_MB_ISHST: return "ishst"; >+ case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#0x9"; >+ case ARM_MB_RESERVED_8: return "#0x8"; >+ case ARM_MB_NSH: return "nsh"; >+ case ARM_MB_NSHST: return "nshst"; >+ case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5"; >+ case ARM_MB_RESERVED_4: return "#0x4"; >+ case ARM_MB_OSH: return "osh"; >+ case ARM_MB_OSHST: return "oshst"; >+ case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1"; >+ case ARM_MB_RESERVED_0: return "#0x0"; >+ } >+} >+ >+enum ARM_ISB_InstSyncBOpt { >+ ARM_ISB_RESERVED_0 = 0, >+ ARM_ISB_RESERVED_1 = 1, >+ ARM_ISB_RESERVED_2 = 2, >+ ARM_ISB_RESERVED_3 = 3, >+ ARM_ISB_RESERVED_4 = 4, >+ ARM_ISB_RESERVED_5 = 5, >+ ARM_ISB_RESERVED_6 = 6, >+ ARM_ISB_RESERVED_7 = 7, >+ ARM_ISB_RESERVED_8 = 8, >+ ARM_ISB_RESERVED_9 = 9, >+ ARM_ISB_RESERVED_10 = 10, >+ ARM_ISB_RESERVED_11 = 11, >+ ARM_ISB_RESERVED_12 = 12, >+ ARM_ISB_RESERVED_13 = 13, >+ ARM_ISB_RESERVED_14 = 14, >+ ARM_ISB_SY = 15 >+}; >+ >+inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val) >+{ >+ switch (val) { >+ default: // never reach >+ case ARM_ISB_RESERVED_0: return "#0x0"; >+ case ARM_ISB_RESERVED_1: return "#0x1"; >+ case ARM_ISB_RESERVED_2: return "#0x2"; >+ case ARM_ISB_RESERVED_3: return "#0x3"; >+ case ARM_ISB_RESERVED_4: return "#0x4"; >+ case ARM_ISB_RESERVED_5: return "#0x5"; >+ case ARM_ISB_RESERVED_6: return "#0x6"; >+ case ARM_ISB_RESERVED_7: return "#0x7"; >+ case ARM_ISB_RESERVED_8: return "#0x8"; >+ case ARM_ISB_RESERVED_9: return "#0x9"; >+ case ARM_ISB_RESERVED_10: return "#0xa"; >+ case ARM_ISB_RESERVED_11: return "#0xb"; >+ case ARM_ISB_RESERVED_12: return "#0xc"; >+ case ARM_ISB_RESERVED_13: return "#0xd"; >+ case ARM_ISB_RESERVED_14: return "#0xe"; >+ case ARM_ISB_SY: return "sy"; >+ } >+} >+ >+/// isARMLowRegister - Returns true if the register is a low register (r0-r7). >+/// >+static inline bool isARMLowRegister(unsigned Reg) >+{ >+ //using namespace ARM; >+ switch (Reg) { >+ case ARM_R0: case ARM_R1: case ARM_R2: case ARM_R3: >+ case ARM_R4: case ARM_R5: case ARM_R6: case ARM_R7: >+ return true; >+ default: >+ return false; >+ } >+} >+ >+/// ARMII - This namespace holds all of the target specific flags that >+/// instruction info tracks. >+/// >+/// ARM Index Modes >+enum ARMII_IndexMode { >+ ARMII_IndexModeNone = 0, >+ ARMII_IndexModePre = 1, >+ ARMII_IndexModePost = 2, >+ ARMII_IndexModeUpd = 3 >+}; >+ >+/// ARM Addressing Modes >+typedef enum ARMII_AddrMode { >+ ARMII_AddrModeNone = 0, >+ ARMII_AddrMode1 = 1, >+ ARMII_AddrMode2 = 2, >+ ARMII_AddrMode3 = 3, >+ ARMII_AddrMode4 = 4, >+ ARMII_AddrMode5 = 5, >+ ARMII_AddrMode6 = 6, >+ ARMII_AddrModeT1_1 = 7, >+ ARMII_AddrModeT1_2 = 8, >+ ARMII_AddrModeT1_4 = 9, >+ ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data >+ ARMII_AddrModeT2_i12 = 11, >+ ARMII_AddrModeT2_i8 = 12, >+ ARMII_AddrModeT2_so = 13, >+ ARMII_AddrModeT2_pc = 14, // +/- i12 for pc relative data >+ ARMII_AddrModeT2_i8s4 = 15, // i8 * 4 >+ ARMII_AddrMode_i12 = 16 >+} ARMII_AddrMode; >+ >+inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode) >+{ >+ switch (addrmode) { >+ case ARMII_AddrModeNone: return "AddrModeNone"; >+ case ARMII_AddrMode1: return "AddrMode1"; >+ case ARMII_AddrMode2: return "AddrMode2"; >+ case ARMII_AddrMode3: return "AddrMode3"; >+ case ARMII_AddrMode4: return "AddrMode4"; >+ case ARMII_AddrMode5: return "AddrMode5"; >+ case ARMII_AddrMode6: return "AddrMode6"; >+ case ARMII_AddrModeT1_1: return "AddrModeT1_1"; >+ case ARMII_AddrModeT1_2: return "AddrModeT1_2"; >+ case ARMII_AddrModeT1_4: return "AddrModeT1_4"; >+ case ARMII_AddrModeT1_s: return "AddrModeT1_s"; >+ case ARMII_AddrModeT2_i12: return "AddrModeT2_i12"; >+ case ARMII_AddrModeT2_i8: return "AddrModeT2_i8"; >+ case ARMII_AddrModeT2_so: return "AddrModeT2_so"; >+ case ARMII_AddrModeT2_pc: return "AddrModeT2_pc"; >+ case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4"; >+ case ARMII_AddrMode_i12: return "AddrMode_i12"; >+ } >+} >+ >+/// Target Operand Flag enum. >+enum ARMII_TOF { >+ //===------------------------------------------------------------------===// >+ // ARM Specific MachineOperand flags. >+ >+ ARMII_MO_NO_FLAG, >+ >+ /// MO_LO16 - On a symbol operand, this represents a relocation containing >+ /// lower 16 bit of the address. Used only via movw instruction. >+ ARMII_MO_LO16, >+ >+ /// MO_HI16 - On a symbol operand, this represents a relocation containing >+ /// higher 16 bit of the address. Used only via movt instruction. >+ ARMII_MO_HI16, >+ >+ /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, >+ /// i.e. "FOO$non_lazy_ptr". >+ /// Used only via movw instruction. >+ ARMII_MO_LO16_NONLAZY, >+ >+ /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol, >+ /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction. >+ ARMII_MO_HI16_NONLAZY, >+ >+ /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the PC relative address of the >+ /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". >+ /// Used only via movw instruction. >+ ARMII_MO_LO16_NONLAZY_PIC, >+ >+ /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a >+ /// relocation containing lower 16 bit of the PC relative address of the >+ /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL". >+ /// Used only via movt instruction. >+ ARMII_MO_HI16_NONLAZY_PIC, >+ >+ /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a >+ /// call operand. >+ ARMII_MO_PLT >+}; >+ >+enum { >+ //===------------------------------------------------------------------===// >+ // Instruction Flags. >+ >+ //===------------------------------------------------------------------===// >+ // This four-bit field describes the addressing mode used. >+ ARMII_AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h >+ >+ // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load >+ // and store ops only. Generic "updating" flag is used for ld/st multiple. >+ // The index mode enums are declared in ARMBaseInfo.h >+ ARMII_IndexModeShift = 5, >+ ARMII_IndexModeMask = 3 << ARMII_IndexModeShift, >+ >+ //===------------------------------------------------------------------===// >+ // Instruction encoding formats. >+ // >+ ARMII_FormShift = 7, >+ ARMII_FormMask = 0x3f << ARMII_FormShift, >+ >+ // Pseudo instructions >+ ARMII_Pseudo = 0 << ARMII_FormShift, >+ >+ // Multiply instructions >+ ARMII_MulFrm = 1 << ARMII_FormShift, >+ >+ // Branch instructions >+ ARMII_BrFrm = 2 << ARMII_FormShift, >+ ARMII_BrMiscFrm = 3 << ARMII_FormShift, >+ >+ // Data Processing instructions >+ ARMII_DPFrm = 4 << ARMII_FormShift, >+ ARMII_DPSoRegFrm = 5 << ARMII_FormShift, >+ >+ // Load and Store >+ ARMII_LdFrm = 6 << ARMII_FormShift, >+ ARMII_StFrm = 7 << ARMII_FormShift, >+ ARMII_LdMiscFrm = 8 << ARMII_FormShift, >+ ARMII_StMiscFrm = 9 << ARMII_FormShift, >+ ARMII_LdStMulFrm = 10 << ARMII_FormShift, >+ >+ ARMII_LdStExFrm = 11 << ARMII_FormShift, >+ >+ // Miscellaneous arithmetic instructions >+ ARMII_ArithMiscFrm = 12 << ARMII_FormShift, >+ ARMII_SatFrm = 13 << ARMII_FormShift, >+ >+ // Extend instructions >+ ARMII_ExtFrm = 14 << ARMII_FormShift, >+ >+ // VFP formats >+ ARMII_VFPUnaryFrm = 15 << ARMII_FormShift, >+ ARMII_VFPBinaryFrm = 16 << ARMII_FormShift, >+ ARMII_VFPConv1Frm = 17 << ARMII_FormShift, >+ ARMII_VFPConv2Frm = 18 << ARMII_FormShift, >+ ARMII_VFPConv3Frm = 19 << ARMII_FormShift, >+ ARMII_VFPConv4Frm = 20 << ARMII_FormShift, >+ ARMII_VFPConv5Frm = 21 << ARMII_FormShift, >+ ARMII_VFPLdStFrm = 22 << ARMII_FormShift, >+ ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift, >+ ARMII_VFPMiscFrm = 24 << ARMII_FormShift, >+ >+ // Thumb format >+ ARMII_ThumbFrm = 25 << ARMII_FormShift, >+ >+ // Miscelleaneous format >+ ARMII_MiscFrm = 26 << ARMII_FormShift, >+ >+ // NEON formats >+ ARMII_NGetLnFrm = 27 << ARMII_FormShift, >+ ARMII_NSetLnFrm = 28 << ARMII_FormShift, >+ ARMII_NDupFrm = 29 << ARMII_FormShift, >+ ARMII_NLdStFrm = 30 << ARMII_FormShift, >+ ARMII_N1RegModImmFrm= 31 << ARMII_FormShift, >+ ARMII_N2RegFrm = 32 << ARMII_FormShift, >+ ARMII_NVCVTFrm = 33 << ARMII_FormShift, >+ ARMII_NVDupLnFrm = 34 << ARMII_FormShift, >+ ARMII_N2RegVShLFrm = 35 << ARMII_FormShift, >+ ARMII_N2RegVShRFrm = 36 << ARMII_FormShift, >+ ARMII_N3RegFrm = 37 << ARMII_FormShift, >+ ARMII_N3RegVShFrm = 38 << ARMII_FormShift, >+ ARMII_NVExtFrm = 39 << ARMII_FormShift, >+ ARMII_NVMulSLFrm = 40 << ARMII_FormShift, >+ ARMII_NVTBLFrm = 41 << ARMII_FormShift, >+ >+ //===------------------------------------------------------------------===// >+ // Misc flags. >+ >+ // UnaryDP - Indicates this is a unary data processing instruction, i.e. >+ // it doesn't have a Rn operand. >+ ARMII_UnaryDP = 1 << 13, >+ >+ // Xform16Bit - Indicates this Thumb2 instruction may be transformed into >+ // a 16-bit Thumb instruction if certain conditions are met. >+ ARMII_Xform16Bit = 1 << 14, >+ >+ // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb >+ // instruction. Used by the parser to determine whether to require the 'S' >+ // suffix on the mnemonic (when not in an IT block) or preclude it (when >+ // in an IT block). >+ ARMII_ThumbArithFlagSetting = 1 << 18, >+ >+ //===------------------------------------------------------------------===// >+ // Code domain. >+ ARMII_DomainShift = 15, >+ ARMII_DomainMask = 7 << ARMII_DomainShift, >+ ARMII_DomainGeneral = 0 << ARMII_DomainShift, >+ ARMII_DomainVFP = 1 << ARMII_DomainShift, >+ ARMII_DomainNEON = 2 << ARMII_DomainShift, >+ ARMII_DomainNEONA8 = 4 << ARMII_DomainShift, >+ >+ //===------------------------------------------------------------------===// >+ // Field shifts - such shifts are used to set field while generating >+ // machine instructions. >+ // >+ // FIXME: This list will need adjusting/fixing as the MC code emitter >+ // takes shape and the ARMCodeEmitter.cpp bits go away. >+ ARMII_ShiftTypeShift = 4, >+ >+ ARMII_M_BitShift = 5, >+ ARMII_ShiftImmShift = 5, >+ ARMII_ShiftShift = 7, >+ ARMII_N_BitShift = 7, >+ ARMII_ImmHiShift = 8, >+ ARMII_SoRotImmShift = 8, >+ ARMII_RegRsShift = 8, >+ ARMII_ExtRotImmShift = 10, >+ ARMII_RegRdLoShift = 12, >+ ARMII_RegRdShift = 12, >+ ARMII_RegRdHiShift = 16, >+ ARMII_RegRnShift = 16, >+ ARMII_S_BitShift = 20, >+ ARMII_W_BitShift = 21, >+ ARMII_AM3_I_BitShift = 22, >+ ARMII_D_BitShift = 22, >+ ARMII_U_BitShift = 23, >+ ARMII_P_BitShift = 24, >+ ARMII_I_BitShift = 25, >+ ARMII_CondShift = 28 >+}; >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c b/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c >new file mode 100644 >index 0000000000000000000000000000000000000000..076459573cac854b15e7df0e4bc725253b0ee33d >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.c >@@ -0,0 +1,5118 @@ >+//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> >+#include <string.h> >+#include <stdlib.h> >+#include <platform.h> >+ >+#include "ARMAddressingModes.h" >+#include "ARMBaseInfo.h" >+#include "../../MCFixedLenDisassembler.h" >+#include "../../MCInst.h" >+#include "../../MCInstrDesc.h" >+#include "../../MCRegisterInfo.h" >+#include "../../LEB128.h" >+#include "../../MCDisassembler.h" >+#include "../../cs_priv.h" >+#include "../../utils.h" >+ >+#include "ARMDisassembler.h" >+ >+//#define GET_REGINFO_ENUM >+//#include "X86GenRegisterInfo.inc" >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "ARMGenSubtargetInfo.inc" >+ >+#define GET_INSTRINFO_MC_DESC >+#include "ARMGenInstrInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+static bool ITStatus_push_back(ARM_ITStatus *it, char v) >+{ >+ if (it->size >= sizeof(it->ITStates)) { >+ // TODO: consider warning user. >+ it->size = 0; >+ } >+ it->ITStates[it->size] = v; >+ it->size++; >+ >+ return true; >+} >+ >+// Returns true if the current instruction is in an IT block >+static bool ITStatus_instrInITBlock(ARM_ITStatus *it) >+{ >+ //return !ITStates.empty(); >+ return (it->size > 0); >+} >+ >+// Returns true if current instruction is the last instruction in an IT block >+static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it) >+{ >+ return (it->size == 1); >+} >+ >+// Handles the condition code status of instructions in IT blocks >+ >+// Returns the condition code for instruction in IT block >+static unsigned ITStatus_getITCC(ARM_ITStatus *it) >+{ >+ unsigned CC = ARMCC_AL; >+ if (ITStatus_instrInITBlock(it)) >+ //CC = ITStates.back(); >+ CC = it->ITStates[it->size-1]; >+ return CC; >+} >+ >+// Advances the IT block state to the next T or E >+static void ITStatus_advanceITState(ARM_ITStatus *it) >+{ >+ //ITStates.pop_back(); >+ it->size--; >+} >+ >+// Called when decoding an IT instruction. Sets the IT state for the following >+// instructions that for the IT block. Firstcond and Mask correspond to the >+// fields in the IT instruction encoding. >+static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask) >+{ >+ // (3 - the number of trailing zeros) is the number of then / else. >+ unsigned CondBit0 = Firstcond & 1; >+ unsigned NumTZ = CountTrailingZeros_32(Mask); >+ unsigned char CCBits = (unsigned char)Firstcond & 0xf; >+ unsigned Pos; >+ //assert(NumTZ <= 3 && "Invalid IT mask!"); >+ // push condition codes onto the stack the correct order for the pops >+ for (Pos = NumTZ+1; Pos <= 3; ++Pos) { >+ bool T = ((Mask >> Pos) & 1) == (int)CondBit0; >+ if (T) >+ ITStatus_push_back(it, CCBits); >+ else >+ ITStatus_push_back(it, CCBits ^ 1); >+ } >+ ITStatus_push_back(it, CCBits); >+} >+ >+/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. >+ >+static bool Check(DecodeStatus *Out, DecodeStatus In) >+{ >+ switch (In) { >+ case MCDisassembler_Success: >+ // Out stays the same. >+ return true; >+ case MCDisassembler_SoftFail: >+ *Out = In; >+ return true; >+ case MCDisassembler_Fail: >+ *Out = In; >+ return false; >+ default: // never reached >+ return false; >+ } >+} >+ >+// Forward declare these because the autogenerated code will reference them. >+// Definitions are further down. >+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst, >+ unsigned Insn, uint64_t Adddress, const void *Decoder); >+static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder); >+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder); >+ >+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder); >+ >+// Hacky: enable all features for disassembler >+uint64_t ARM_getFeatureBits(unsigned int mode) >+{ >+ uint64_t Bits = (uint64_t)-1; // everything by default >+ >+ // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else?? >+ Bits &= (~ARM_FeatureVFPOnlySP); >+ >+ // FIXME: no Armv8 support? >+ //Bits -= ARM_HasV7Ops; >+ //Bits &= ~ARM_FeatureMP; >+ if ((mode & CS_MODE_V8) == 0) >+ Bits &= ~ARM_HasV8Ops; >+ //Bits &= ~ARM_HasV6Ops; >+ >+ if ((mode & CS_MODE_MCLASS) == 0) >+ Bits &= (~ARM_FeatureMClass); >+ >+ // some features are mutually exclusive >+ if (mode & CS_MODE_THUMB) { >+ //Bits &= ~ARM_HasV6Ops; >+ //Bits &= ~ARM_FeatureCRC; >+ //Bits &= ~ARM_HasV5TEOps; >+ //Bits &= ~ARM_HasV4TOps; >+ //Bits &= ~ARM_HasV6T2Ops; >+ //Bits &= ~ARM_FeatureDB; >+ //Bits &= ~ARM_FeatureHWDivARM; >+ //Bits &= ~ARM_FeatureNaClTrap; >+ //Bits &= ~ARM_FeatureMClass; >+ // ArmV8 >+ } else { // ARM mode >+ Bits &= ~ARM_ModeThumb; >+ Bits &= ~ARM_FeatureThumb2; >+ } >+ >+ return Bits; >+} >+ >+#include "ARMGenDisassemblerTables.inc" >+ >+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0xF) return MCDisassembler_Fail; >+ // AL predicate is not allowed on Thumb1 branches. >+ if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, Val); >+ if (Val == ARMCC_AL) { >+ MCOperand_CreateReg0(Inst, 0); >+ } else >+ MCOperand_CreateReg0(Inst, ARM_CPSR); >+ return MCDisassembler_Success; >+} >+ >+#define GET_REGINFO_MC_DESC >+#include "ARMGenRegisterInfo.inc" >+void ARM_init(MCRegisterInfo *MRI) >+{ >+ /* >+ InitMCRegisterInfo(ARMRegDesc, 289, >+ RA, PC, >+ ARMMCRegisterClasses, 100, >+ ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, >+ ARMSubRegIdxLists, 57, >+ ARMSubRegIdxRanges, ARMRegEncodingTable); >+ */ >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, >+ 0, 0, >+ ARMMCRegisterClasses, 100, >+ 0, 0, ARMRegDiffLists, 0, >+ ARMSubRegIdxLists, 57, >+ 0); >+} >+ >+static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, >+ uint16_t *Size, uint64_t Address) >+{ >+ uint32_t insn, i; >+ uint8_t bytes[4]; >+ DecodeStatus result; >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (MI->flat_insn->detail) { >+ memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); >+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) >+ MI->flat_insn->detail->arm.operands[i].vector_index = -1; >+ } >+ >+ memcpy(bytes, code, 4); >+ >+ if (MODE_IS_BIG_ENDIAN(ud->mode)) >+ insn = (bytes[3] << 0) | >+ (bytes[2] << 8) | >+ (bytes[1] << 16) | >+ (bytes[0] << 24); >+ else >+ insn = (bytes[3] << 24) | >+ (bytes[2] << 16) | >+ (bytes[1] << 8) | >+ (bytes[0] << 0); >+ >+ // Calling the auto-generated decoder function. >+ result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ // VFP and NEON instructions, similarly, are shared between ARM >+ // and Thumb modes. >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ // Add a fake predicate operand, because we share these instruction >+ // definitions with Thumb2 where these instructions are predicable. >+ if (!DecodePredicateOperand(MI, 0xE, Address, NULL)) >+ return MCDisassembler_Fail; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ *Size = 0; >+ return MCDisassembler_Fail; >+} >+ >+// Thumb1 instructions don't have explicit S bits. Rather, they >+// implicitly set CPSR. Since it's not represented in the encoding, the >+// auto-generated decoder won't inject the CPSR operand. We need to fix >+// that as a post-pass. >+static void AddThumb1SBit(MCInst *MI, bool InITBlock) >+{ >+ const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ unsigned i; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (i == MCInst_getNumOperands(MI)) break; >+ if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) { >+ if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue; >+ MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); >+ return; >+ } >+ } >+ >+ //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR)); >+ MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR)); >+} >+ >+// Most Thumb instructions don't have explicit predicates in the >+// encoding, but rather get their predicates from IT context. We need >+// to fix up the predicate operands using this context information as a >+// post-pass. >+static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ const MCOperandInfo *OpInfo; >+ unsigned short NumOps; >+ unsigned int i; >+ unsigned CC; >+ >+ // A few instructions actually have predicates encoded in them. Don't >+ // try to overwrite it if we're seeing one of those. >+ switch (MCInst_getOpcode(MI)) { >+ case ARM_tBcc: >+ case ARM_t2Bcc: >+ case ARM_tCBZ: >+ case ARM_tCBNZ: >+ case ARM_tCPS: >+ case ARM_t2CPS3p: >+ case ARM_t2CPS2p: >+ case ARM_t2CPS1p: >+ case ARM_tMOVSr: >+ case ARM_tSETEND: >+ // Some instructions (mostly conditional branches) are not >+ // allowed in IT blocks. >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ S = MCDisassembler_SoftFail; >+ else >+ return MCDisassembler_Success; >+ break; >+ case ARM_tB: >+ case ARM_t2B: >+ case ARM_t2TBB: >+ case ARM_t2TBH: >+ // Some instructions (mostly unconditional branches) can >+ // only appears at the end of, or outside of, an IT. >+ //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) >+ if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock))) >+ S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ >+ // If we're in an IT block, base the predicate on that. Otherwise, >+ // assume a predicate of AL. >+ CC = ITStatus_getITCC(&(ud->ITBlock)); >+ if (CC == 0xF) >+ CC = ARMCC_AL; >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ ITStatus_advanceITState(&(ud->ITBlock)); >+ >+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (i == MCInst_getNumOperands(MI)) break; >+ if (MCOperandInfo_isPredicate(&OpInfo[i])) { >+ MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); >+ if (CC == ARMCC_AL) >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); >+ else >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); >+ return S; >+ } >+ } >+ >+ MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC)); >+ if (CC == ARMCC_AL) >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0)); >+ else >+ MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR)); >+ >+ return S; >+} >+ >+// Thumb VFP instructions are a special case. Because we share their >+// encodings between ARM and Thumb modes, and they are predicable in ARM >+// mode, the auto-generated decoder will give them an (incorrect) >+// predicate operand. We need to rewrite these operands based on the IT >+// context as a post-pass. >+static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) >+{ >+ unsigned CC; >+ unsigned short NumOps; >+ const MCOperandInfo *OpInfo; >+ unsigned i; >+ >+ CC = ITStatus_getITCC(&(ud->ITBlock)); >+ if (ITStatus_instrInITBlock(&(ud->ITBlock))) >+ ITStatus_advanceITState(&(ud->ITBlock)); >+ >+ OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo; >+ NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands; >+ >+ for (i = 0; i < NumOps; ++i) { >+ if (MCOperandInfo_isPredicate(&OpInfo[i])) { >+ MCOperand_setImm(MCInst_getOperand(MI, i), CC); >+ if (CC == ARMCC_AL) >+ MCOperand_setReg(MCInst_getOperand(MI, i+1), 0); >+ else >+ MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR); >+ return; >+ } >+ } >+} >+ >+static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len, >+ uint16_t *Size, uint64_t Address) >+{ >+ uint8_t bytes[4]; >+ uint16_t insn16; >+ DecodeStatus result; >+ bool InITBlock; >+ unsigned Firstcond, Mask; >+ uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn; >+ size_t i; >+ >+ // We want to read exactly 2 bytes of data. >+ if (code_len < 2) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (MI->flat_insn->detail) { >+ memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm)); >+ for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) >+ MI->flat_insn->detail->arm.operands[i].vector_index = -1; >+ } >+ >+ memcpy(bytes, code, 2); >+ >+ if (MODE_IS_BIG_ENDIAN(ud->mode)) >+ insn16 = (bytes[0] << 8) | bytes[1]; >+ else >+ insn16 = (bytes[1] << 8) | bytes[0]; >+ >+ result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 2; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode); >+ if (result) { >+ *Size = 2; >+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); >+ Check(&result, AddThumbPredicate(ud, MI)); >+ AddThumb1SBit(MI, InITBlock); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 2; >+ >+ // Nested IT blocks are UNPREDICTABLE. Must be checked before we add >+ // the Thumb predicate. >+ if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock))) >+ return MCDisassembler_SoftFail; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ >+ // If we find an IT instruction, we need to parse its condition >+ // code and mask operands so that we can apply them correctly >+ // to the subsequent instructions. >+ if (MCInst_getOpcode(MI) == ARM_t2IT) { >+ >+ Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0)); >+ Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1)); >+ ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask); >+ } >+ >+ return result; >+ } >+ >+ // We want to read exactly 4 bytes of data. >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ memcpy(bytes, code, 4); >+ >+ if (MODE_IS_BIG_ENDIAN(ud->mode)) >+ insn32 = (bytes[3] << 0) | >+ (bytes[2] << 8) | >+ (bytes[1] << 16) | >+ (bytes[0] << 24); >+ else >+ insn32 = (bytes[3] << 8) | >+ (bytes[2] << 0) | >+ (bytes[1] << 24) | >+ (bytes[0] << 16); >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock)); >+ Check(&result, AddThumbPredicate(ud, MI)); >+ AddThumb1SBit(MI, InITBlock); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ UpdateThumbVFPPredicate(ud, MI); >+ return result; >+ } >+ >+ if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ UpdateThumbVFPPredicate(ud, MI); >+ return result; >+ } >+ } >+ >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) { >+ MCInst_clear(MI); >+ result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) { >+ MCInst_clear(MI); >+ NEONLdStInsn = insn32; >+ NEONLdStInsn &= 0xF0FFFFFF; >+ NEONLdStInsn |= 0x04000000; >+ result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) { >+ MCInst_clear(MI); >+ NEONDataInsn = insn32; >+ NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 >+ NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 >+ NEONDataInsn |= 0x12000000; // Set bits 28 and 25 >+ result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ Check(&result, AddThumbPredicate(ud, MI)); >+ return result; >+ } >+ } >+ >+ MCInst_clear(MI); >+ NEONCryptoInsn = insn32; >+ NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 >+ NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 >+ NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 >+ result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, >+ Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ NEONv8Insn = insn32; >+ NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 >+ result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode); >+ if (result != MCDisassembler_Fail) { >+ *Size = 4; >+ return result; >+ } >+ >+ MCInst_clear(MI); >+ *Size = 0; >+ return MCDisassembler_Fail; >+} >+ >+bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); >+ >+ //return status == MCDisassembler_Success; >+ return status != MCDisassembler_Fail; >+} >+ >+bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address); >+ >+ //return status == MCDisassembler_Success; >+ return status != MCDisassembler_Fail; >+} >+ >+static const uint16_t GPRDecoderTable[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, >+ ARM_R4, ARM_R5, ARM_R6, ARM_R7, >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, >+ ARM_R12, ARM_SP, ARM_LR, ARM_PC >+}; >+ >+static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 15) >+ return MCDisassembler_Fail; >+ >+ Register = GPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo == 15) >+ S = MCDisassembler_SoftFail; >+ >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo == 15) { >+ MCOperand_CreateReg0(Inst, ARM_APSR_NZCV); >+ return MCDisassembler_Success; >+ } >+ >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ return S; >+} >+ >+static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static const uint16_t GPRPairDecoderTable[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, >+ ARM_R8_R9, ARM_R10_R11, ARM_R12_SP >+}; >+ >+static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned RegisterPair; >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (RegNo > 13) >+ return MCDisassembler_Fail; >+ >+ if ((RegNo & 1) || RegNo == 0xe) >+ S = MCDisassembler_SoftFail; >+ >+ RegisterPair = GPRPairDecoderTable[RegNo/2]; >+ MCOperand_CreateReg0(Inst, RegisterPair); >+ return S; >+} >+ >+static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register = 0; >+ switch (RegNo) { >+ case 0: >+ Register = ARM_R0; >+ break; >+ case 1: >+ Register = ARM_R1; >+ break; >+ case 2: >+ Register = ARM_R2; >+ break; >+ case 3: >+ Register = ARM_R3; >+ break; >+ case 9: >+ Register = ARM_R9; >+ break; >+ case 12: >+ Register = ARM_R12; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ if (RegNo == 13 || RegNo == 15) >+ S = MCDisassembler_SoftFail; >+ Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); >+ return S; >+} >+ >+static const uint16_t SPRDecoderTable[] = { >+ ARM_S0, ARM_S1, ARM_S2, ARM_S3, >+ ARM_S4, ARM_S5, ARM_S6, ARM_S7, >+ ARM_S8, ARM_S9, ARM_S10, ARM_S11, >+ ARM_S12, ARM_S13, ARM_S14, ARM_S15, >+ ARM_S16, ARM_S17, ARM_S18, ARM_S19, >+ ARM_S20, ARM_S21, ARM_S22, ARM_S23, >+ ARM_S24, ARM_S25, ARM_S26, ARM_S27, >+ ARM_S28, ARM_S29, ARM_S30, ARM_S31 >+}; >+ >+static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Register = SPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPRDecoderTable[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, >+ ARM_D4, ARM_D5, ARM_D6, ARM_D7, >+ ARM_D8, ARM_D9, ARM_D10, ARM_D11, >+ ARM_D12, ARM_D13, ARM_D14, ARM_D15, >+ ARM_D16, ARM_D17, ARM_D18, ARM_D19, >+ ARM_D20, ARM_D21, ARM_D22, ARM_D23, >+ ARM_D24, ARM_D25, ARM_D26, ARM_D27, >+ ARM_D28, ARM_D29, ARM_D30, ARM_D31 >+}; >+ >+static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register = 0; >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Register = DPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+ static DecodeStatus >+DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ if (RegNo > 15) >+ return MCDisassembler_Fail; >+ return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static const uint16_t QPRDecoderTable[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, >+ ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, >+ ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, >+ ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15 >+}; >+ >+static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 31 || (RegNo & 1) != 0) >+ return MCDisassembler_Fail; >+ RegNo >>= 1; >+ >+ Register = QPRDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPairDecoderTable[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, >+ ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, >+ ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, >+ ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, >+ ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, >+ ARM_Q15 >+}; >+ >+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 30) >+ return MCDisassembler_Fail; >+ >+ Register = DPairDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static const uint16_t DPairSpacedDecoderTable[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, >+ ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, >+ ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, >+ ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, >+ ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, >+ ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, >+ ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, >+ ARM_D28_D30, ARM_D29_D31 >+}; >+ >+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const void *Decoder) >+{ >+ unsigned Register; >+ if (RegNo > 29) >+ return MCDisassembler_Fail; >+ >+ Register = DPairSpacedDecoderTable[RegNo]; >+ MCOperand_CreateReg0(Inst, Register); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val) >+ MCOperand_CreateReg0(Inst, ARM_CPSR); >+ else >+ MCOperand_CreateReg0(Inst, 0); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ uint32_t imm = Val & 0xFF; >+ uint32_t rot = (Val & 0xF00) >> 7; >+ uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); >+ MCOperand_CreateImm0(Inst, rot_imm); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc Shift; >+ unsigned Op; >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 7, 5); >+ >+ // Register-immediate >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Shift = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ Shift = ARM_AM_lsl; >+ break; >+ case 1: >+ Shift = ARM_AM_lsr; >+ break; >+ case 2: >+ Shift = ARM_AM_asr; >+ break; >+ case 3: >+ Shift = ARM_AM_ror; >+ break; >+ } >+ >+ if (Shift == ARM_AM_ror && imm == 0) >+ Shift = ARM_AM_rrx; >+ >+ Op = Shift | (imm << 3); >+ MCOperand_CreateImm0(Inst, Op); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc Shift; >+ >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned Rs = fieldFromInstruction_4(Val, 8, 4); >+ >+ // Register-register >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Shift = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ Shift = ARM_AM_lsl; >+ break; >+ case 1: >+ Shift = ARM_AM_lsr; >+ break; >+ case 2: >+ Shift = ARM_AM_asr; >+ break; >+ case 3: >+ Shift = ARM_AM_ror; >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, Shift); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned i; >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned opcode; >+ >+ bool NeedDisjointWriteback = false; >+ unsigned WritebackReg = 0; >+ >+ opcode = MCInst_getOpcode(Inst); >+ switch (opcode) { >+ default: >+ break; >+ case ARM_LDMIA_UPD: >+ case ARM_LDMDB_UPD: >+ case ARM_LDMIB_UPD: >+ case ARM_LDMDA_UPD: >+ case ARM_t2LDMIA_UPD: >+ case ARM_t2LDMDB_UPD: >+ case ARM_t2STMIA_UPD: >+ case ARM_t2STMDB_UPD: >+ NeedDisjointWriteback = true; >+ WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0)); >+ break; >+ } >+ >+ // Empty register lists are not allowed. >+ if (Val == 0) return MCDisassembler_Fail; >+ for (i = 0; i < 16; ++i) { >+ if (Val & (1 << i)) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Writeback not allowed if Rn is in the target list. >+ if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size-1]))) >+ Check(&S, MCDisassembler_SoftFail); >+ } >+ } >+ >+ if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) { >+ if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) { >+ // invalid thumb2 pop >+ // needs no sp in reglist and not both pc and lr set at the same time >+ return MCDisassembler_Fail; >+ } >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned i; >+ unsigned Vd = fieldFromInstruction_4(Val, 8, 5); >+ unsigned regs = fieldFromInstruction_4(Val, 0, 8); >+ >+ // In case of unpredictable encoding, tweak the operands. >+ if (regs == 0 || (Vd + regs) > 32) { >+ regs = Vd + regs > 32 ? 32 - Vd : regs; >+ regs = (1u > regs? 1u : regs); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ for (i = 0; i < (regs - 1); ++i) { >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned i; >+ unsigned Vd = fieldFromInstruction_4(Val, 8, 5); >+ unsigned regs = fieldFromInstruction_4(Val, 1, 7); >+ >+ // In case of unpredictable encoding, tweak the operands. >+ if (regs == 0 || regs > 16 || (Vd + regs) > 32) { >+ regs = Vd + regs > 32 ? 32 - Vd : regs; >+ regs = (1u > regs? 1u : regs); >+ regs = (16u > regs? regs : 16u); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ for (i = 0; i < (regs - 1); ++i) { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // This operand encodes a mask of contiguous zeros between a specified MSB >+ // and LSB. To decode it, we create the mask of all bits MSB-and-lower, >+ // the mask of all bits LSB-and-lower, and then xor them to create >+ // the mask of that's all ones on [msb, lsb]. Finally we not it to >+ // create the final mask. >+ unsigned msb = fieldFromInstruction_4(Val, 5, 5); >+ unsigned lsb = fieldFromInstruction_4(Val, 0, 5); >+ uint32_t lsb_mask, msb_mask; >+ >+ DecodeStatus S = MCDisassembler_Success; >+ if (lsb > msb) { >+ Check(&S, MCDisassembler_SoftFail); >+ // The check above will cause the warning for the "potentially undefined >+ // instruction encoding" but we can't build a bad MCOperand value here >+ // with a lsb > msb or else printing the MCInst will cause a crash. >+ lsb = msb; >+ } >+ >+ msb_mask = 0xFFFFFFFF; >+ if (msb != 31) msb_mask = (1U << (msb+1)) - 1; >+ lsb_mask = (1U << lsb) - 1; >+ >+ MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask)); >+ return S; >+} >+ >+static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned CRd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned coproc = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDC_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDC_POST: >+ case ARM_LDC_OPTION: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDCL_PRE: >+ case ARM_LDCL_POST: >+ case ARM_LDCL_OPTION: >+ case ARM_STC_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STC_POST: >+ case ARM_STC_OPTION: >+ case ARM_STCL_OFFSET: >+ case ARM_STCL_PRE: >+ case ARM_STCL_POST: >+ case ARM_STCL_OPTION: >+ case ARM_t2LDC_OFFSET: >+ case ARM_t2LDC_PRE: >+ case ARM_t2LDC_POST: >+ case ARM_t2LDC_OPTION: >+ case ARM_t2LDCL_OFFSET: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2LDCL_POST: >+ case ARM_t2LDCL_OPTION: >+ case ARM_t2STC_OFFSET: >+ case ARM_t2STC_PRE: >+ case ARM_t2STC_POST: >+ case ARM_t2STC_OPTION: >+ case ARM_t2STCL_OFFSET: >+ case ARM_t2STCL_PRE: >+ case ARM_t2STCL_POST: >+ case ARM_t2STCL_OPTION: >+ if (coproc == 0xA || coproc == 0xB) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, coproc); >+ MCOperand_CreateImm0(Inst, CRd); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDC2_OFFSET: >+ case ARM_t2LDC2L_OFFSET: >+ case ARM_t2LDC2_PRE: >+ case ARM_t2LDC2L_PRE: >+ case ARM_t2STC2_OFFSET: >+ case ARM_t2STC2L_OFFSET: >+ case ARM_t2STC2_PRE: >+ case ARM_t2STC2L_PRE: >+ case ARM_LDC2_OFFSET: >+ case ARM_LDC2L_OFFSET: >+ case ARM_LDC2_PRE: >+ case ARM_LDC2L_PRE: >+ case ARM_STC2_OFFSET: >+ case ARM_STC2L_OFFSET: >+ case ARM_STC2_PRE: >+ case ARM_STC2L_PRE: >+ case ARM_t2LDC_OFFSET: >+ case ARM_t2LDCL_OFFSET: >+ case ARM_t2LDC_PRE: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2STC_OFFSET: >+ case ARM_t2STCL_OFFSET: >+ case ARM_t2STC_PRE: >+ case ARM_t2STCL_PRE: >+ case ARM_LDC_OFFSET: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDCL_PRE: >+ case ARM_STC_OFFSET: >+ case ARM_STCL_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STCL_PRE: >+ imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm); >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ case ARM_t2LDC2_POST: >+ case ARM_t2LDC2L_POST: >+ case ARM_t2STC2_POST: >+ case ARM_t2STC2L_POST: >+ case ARM_LDC2_POST: >+ case ARM_LDC2L_POST: >+ case ARM_STC2_POST: >+ case ARM_STC2L_POST: >+ case ARM_t2LDC_POST: >+ case ARM_t2LDCL_POST: >+ case ARM_t2STC_POST: >+ case ARM_t2STCL_POST: >+ case ARM_LDC_POST: >+ case ARM_LDCL_POST: >+ case ARM_STC_POST: >+ case ARM_STCL_POST: >+ imm |= U << 8; >+ // fall through. >+ default: >+ // The 'option' variant doesn't encode 'U' in the immediate since >+ // the immediate is unsigned [0,255]. >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDC_OFFSET: >+ case ARM_LDC_PRE: >+ case ARM_LDC_POST: >+ case ARM_LDC_OPTION: >+ case ARM_LDCL_OFFSET: >+ case ARM_LDCL_PRE: >+ case ARM_LDCL_POST: >+ case ARM_LDCL_OPTION: >+ case ARM_STC_OFFSET: >+ case ARM_STC_PRE: >+ case ARM_STC_POST: >+ case ARM_STC_OPTION: >+ case ARM_STCL_OFFSET: >+ case ARM_STCL_PRE: >+ case ARM_STCL_POST: >+ case ARM_STCL_OPTION: >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_AddrOpc Op; >+ ARM_AM_ShiftOpc Opc; >+ bool writeback; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned reg = fieldFromInstruction_4(Insn, 25, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned idx_mode = 0, amt, tmp; >+ >+ // On stores, the writeback operand precedes Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STR_POST_IMM: >+ case ARM_STR_POST_REG: >+ case ARM_STRB_POST_IMM: >+ case ARM_STRB_POST_REG: >+ case ARM_STRT_POST_REG: >+ case ARM_STRT_POST_IMM: >+ case ARM_STRBT_POST_REG: >+ case ARM_STRBT_POST_IMM: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // On loads, the writeback operand comes after Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDR_POST_IMM: >+ case ARM_LDR_POST_REG: >+ case ARM_LDRB_POST_IMM: >+ case ARM_LDRB_POST_REG: >+ case ARM_LDRBT_POST_REG: >+ case ARM_LDRBT_POST_IMM: >+ case ARM_LDRT_POST_REG: >+ case ARM_LDRT_POST_IMM: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ Op = ARM_AM_add; >+ if (!fieldFromInstruction_4(Insn, 23, 1)) >+ Op = ARM_AM_sub; >+ >+ writeback = (P == 0) || (W == 1); >+ if (P && writeback) >+ idx_mode = ARMII_IndexModePre; >+ else if (!P && writeback) >+ idx_mode = ARMII_IndexModePost; >+ >+ if (writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; // UNPREDICTABLE >+ >+ if (reg) { >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ Opc = ARM_AM_lsl; >+ switch( fieldFromInstruction_4(Insn, 5, 2)) { >+ case 0: >+ Opc = ARM_AM_lsl; >+ break; >+ case 1: >+ Opc = ARM_AM_lsr; >+ break; >+ case 2: >+ Opc = ARM_AM_asr; >+ break; >+ case 3: >+ Opc = ARM_AM_ror; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ amt = fieldFromInstruction_4(Insn, 7, 5); >+ if (Opc == ARM_AM_ror && amt == 0) >+ Opc = ARM_AM_rrx; >+ imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); >+ >+ MCOperand_CreateImm0(Inst, imm); >+ } else { >+ MCOperand_CreateReg0(Inst, 0); >+ tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode); >+ MCOperand_CreateImm0(Inst, tmp); >+ } >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ ARM_AM_ShiftOpc ShOp; >+ unsigned shift; >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned type = fieldFromInstruction_4(Val, 5, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 7, 5); >+ unsigned U = fieldFromInstruction_4(Val, 12, 1); >+ >+ ShOp = ARM_AM_lsl; >+ switch (type) { >+ case 0: >+ ShOp = ARM_AM_lsl; >+ break; >+ case 1: >+ ShOp = ARM_AM_lsr; >+ break; >+ case 2: >+ ShOp = ARM_AM_asr; >+ break; >+ case 3: >+ ShOp = ARM_AM_ror; >+ break; >+ } >+ >+ if (ShOp == ARM_AM_ror && imm == 0) >+ ShOp = ARM_AM_rrx; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (U) >+ shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); >+ else >+ shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); >+ MCOperand_CreateImm0(Inst, shift); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned type = fieldFromInstruction_4(Insn, 22, 1); >+ unsigned imm = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8; >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ unsigned Rt2 = Rt + 1; >+ >+ bool writeback = (W == 1) | (P == 0); >+ >+ // For {LD,ST}RD, Rt must be even, else undefined. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (Rt & 0x1) S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ if (P == 0 && W == 1) >+ S = MCDisassembler_SoftFail; >+ >+ if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) >+ S = MCDisassembler_SoftFail; >+ if (type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ if (Rt2 == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && fieldFromInstruction_4(Insn, 8, 4)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_STRH: >+ case ARM_STRH_PRE: >+ case ARM_STRH_POST: >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ if (writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ if (!type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (type && Rn == 15){ >+ if (Rt2 == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (P == 0 && W == 1) >+ S = MCDisassembler_SoftFail; >+ if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && Rn == 15) >+ S = MCDisassembler_SoftFail; >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRH: >+ case ARM_LDRH_PRE: >+ case ARM_LDRH_POST: >+ if (type && Rn == 15){ >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && Rm == 15) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ break; >+ case ARM_LDRSH: >+ case ARM_LDRSH_PRE: >+ case ARM_LDRSH_POST: >+ case ARM_LDRSB: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSB_POST: >+ if (type && Rn == 15){ >+ if (Rt == 15) >+ S = MCDisassembler_SoftFail; >+ break; >+ } >+ if (type && (Rt == 15 || (writeback && Rn == Rt))) >+ S = MCDisassembler_SoftFail; >+ if (!type && (Rt == 15 || Rm == 15)) >+ S = MCDisassembler_SoftFail; >+ if (!type && writeback && (Rn == 15 || Rn == Rt)) >+ S = MCDisassembler_SoftFail; >+ break; >+ default: >+ break; >+ } >+ >+ if (writeback) { // Writeback >+ Inst->writeback = true; >+ if (P) >+ U |= ARMII_IndexModePre << 9; >+ else >+ U |= ARMII_IndexModePost << 9; >+ >+ // On stores, the writeback operand precedes Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_STRH: >+ case ARM_STRH_PRE: >+ case ARM_STRH_POST: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_STRD: >+ case ARM_STRD_PRE: >+ case ARM_STRD_POST: >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ if (writeback) { >+ // On loads, the writeback operand comes after Rt. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDRD: >+ case ARM_LDRD_PRE: >+ case ARM_LDRD_POST: >+ case ARM_LDRH: >+ case ARM_LDRH_PRE: >+ case ARM_LDRH_POST: >+ case ARM_LDRSH: >+ case ARM_LDRSH_PRE: >+ case ARM_LDRSH_POST: >+ case ARM_LDRSB: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSB_POST: >+ case ARM_LDRHTr: >+ case ARM_LDRSBTr: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (type) { >+ MCOperand_CreateReg0(Inst, 0); >+ MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm); >+ } else { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, U); >+ } >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned mode = fieldFromInstruction_4(Insn, 23, 2); >+ >+ switch (mode) { >+ case 0: >+ mode = ARM_AM_da; >+ break; >+ case 1: >+ mode = ARM_AM_ia; >+ break; >+ case 2: >+ mode = ARM_AM_db; >+ break; >+ case 3: >+ mode = ARM_AM_ib; >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, mode); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned reglist = fieldFromInstruction_4(Insn, 0, 16); >+ >+ if (pred == 0xF) { >+ // Ambiguous with RFE and SRS >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_LDMDA: >+ MCInst_setOpcode(Inst, ARM_RFEDA); >+ break; >+ case ARM_LDMDA_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEDA_UPD); >+ break; >+ case ARM_LDMDB: >+ MCInst_setOpcode(Inst, ARM_RFEDB); >+ break; >+ case ARM_LDMDB_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEDB_UPD); >+ break; >+ case ARM_LDMIA: >+ MCInst_setOpcode(Inst, ARM_RFEIA); >+ break; >+ case ARM_LDMIA_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEIA_UPD); >+ break; >+ case ARM_LDMIB: >+ MCInst_setOpcode(Inst, ARM_RFEIB); >+ break; >+ case ARM_LDMIB_UPD: >+ MCInst_setOpcode(Inst, ARM_RFEIB_UPD); >+ break; >+ case ARM_STMDA: >+ MCInst_setOpcode(Inst, ARM_SRSDA); >+ break; >+ case ARM_STMDA_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSDA_UPD); >+ break; >+ case ARM_STMDB: >+ MCInst_setOpcode(Inst, ARM_SRSDB); >+ break; >+ case ARM_STMDB_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSDB_UPD); >+ break; >+ case ARM_STMIA: >+ MCInst_setOpcode(Inst, ARM_SRSIA); >+ break; >+ case ARM_STMIA_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSIA_UPD); >+ break; >+ case ARM_STMIB: >+ MCInst_setOpcode(Inst, ARM_SRSIB); >+ break; >+ case ARM_STMIB_UPD: >+ MCInst_setOpcode(Inst, ARM_SRSIB_UPD); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ // For stores (which become SRS's, the only operand is the mode. >+ if (fieldFromInstruction_4(Insn, 20, 1) == 0) { >+ // Check SRS encoding constraints >+ if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 && >+ fieldFromInstruction_4(Insn, 20, 1) == 0)) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4)); >+ return S; >+ } >+ >+ return DecodeRFEInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; // Tied >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_4(Insn, 18, 2); >+ unsigned M = fieldFromInstruction_4(Insn, 17, 1); >+ unsigned iflags = fieldFromInstruction_4(Insn, 6, 3); >+ unsigned mode = fieldFromInstruction_4(Insn, 0, 5); >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // This decoder is called from multiple location that do not check >+ // the full encoding is valid before they do. >+ if (fieldFromInstruction_4(Insn, 5, 1) != 0 || >+ fieldFromInstruction_4(Insn, 16, 1) != 0 || >+ fieldFromInstruction_4(Insn, 20, 8) != 0x10) >+ return MCDisassembler_Fail; >+ >+ // imod == '01' --> UNPREDICTABLE >+ // NOTE: Even though this is technically UNPREDICTABLE, we choose to >+ // return failure here. The '01' imod value is unprintable, so there's >+ // nothing useful we could do even if we returned UNPREDICTABLE. >+ >+ if (imod == 1) return MCDisassembler_Fail; >+ >+ if (imod && M) { >+ MCInst_setOpcode(Inst, ARM_CPS3p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ MCOperand_CreateImm0(Inst, mode); >+ } else if (imod && !M) { >+ MCInst_setOpcode(Inst, ARM_CPS2p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ if (mode) S = MCDisassembler_SoftFail; >+ } else if (!imod && M) { >+ MCInst_setOpcode(Inst, ARM_CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ if (iflags) S = MCDisassembler_SoftFail; >+ } else { >+ // imod == '00' && M == '0' --> UNPREDICTABLE >+ MCInst_setOpcode(Inst, ARM_CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ S = MCDisassembler_SoftFail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_4(Insn, 9, 2); >+ unsigned M = fieldFromInstruction_4(Insn, 8, 1); >+ unsigned iflags = fieldFromInstruction_4(Insn, 5, 3); >+ unsigned mode = fieldFromInstruction_4(Insn, 0, 5); >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // imod == '01' --> UNPREDICTABLE >+ // NOTE: Even though this is technically UNPREDICTABLE, we choose to >+ // return failure here. The '01' imod value is unprintable, so there's >+ // nothing useful we could do even if we returned UNPREDICTABLE. >+ >+ if (imod == 1) return MCDisassembler_Fail; >+ >+ if (imod && M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS3p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ MCOperand_CreateImm0(Inst, mode); >+ } else if (imod && !M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS2p); >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, iflags); >+ if (mode) S = MCDisassembler_SoftFail; >+ } else if (!imod && M) { >+ MCInst_setOpcode(Inst, ARM_t2CPS1p); >+ MCOperand_CreateImm0(Inst, mode); >+ if (iflags) S = MCDisassembler_SoftFail; >+ } else { >+ // imod == '00' && M == '0' --> this is a HINT instruction >+ int imm = fieldFromInstruction_4(Insn, 0, 8); >+ // HINT are defined only for immediate in [0..4] >+ if(imm > 4) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_t2HINT); >+ MCOperand_CreateImm0(Inst, imm); >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned imm = 0; >+ >+ imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0); >+ imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8); >+ imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); >+ imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11); >+ >+ if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16) >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned imm = 0; >+ >+ imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0); >+ imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12); >+ >+ if (MCInst_getOpcode(Inst) == ARM_MOVTi16) >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Ra = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned add = fieldFromInstruction_4(Val, 12, 1); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 12); >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (!add) imm *= (unsigned int)-1; >+ if (imm == 0 && !add) imm = (unsigned int)INT32_MIN; >+ MCOperand_CreateImm0(Inst, imm); >+ //if (Rn == 15) >+ // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned U = fieldFromInstruction_4(Val, 8, 1); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (U) >+ MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)); >+ else >+ MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); >+} >+ >+static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus Status = MCDisassembler_Success; >+ >+ // Note the J1 and J2 values are from the encoded instruction. So here >+ // change them to I1 and I2 values via as documented: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with one trailing zero as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); >+ unsigned S = fieldFromInstruction_4(Insn, 26, 1); >+ unsigned J1 = fieldFromInstruction_4(Insn, 13, 1); >+ unsigned J2 = fieldFromInstruction_4(Insn, 11, 1); >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10); >+ unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11); >+ unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; >+ int imm32 = SignExtend32(tmp << 1, 25); >+ MCOperand_CreateImm0(Inst, imm32); >+ >+ return Status; >+} >+ >+static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2; >+ >+ if (pred == 0xF) { >+ MCInst_setOpcode(Inst, ARM_BLXi); >+ imm |= fieldFromInstruction_4(Insn, 24, 1) << 1; >+ MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); >+ return S; >+ } >+ >+ MCOperand_CreateImm0(Inst, SignExtend32(imm, 26)); >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+ >+static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned align = fieldFromInstruction_4(Val, 4, 2); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!align) >+ MCOperand_CreateImm0(Inst, 0); >+ else >+ MCOperand_CreateImm0(Inst, 4 << align); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned wb, Rn, Rm; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ wb = fieldFromInstruction_4(Insn, 16, 4); >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ // First output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8: >+ case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register: >+ case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register: >+ case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8: >+ case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register: >+ case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register: >+ case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2b16: >+ case ARM_VLD2b32: >+ case ARM_VLD2b8: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b16wb_register: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2b32wb_register: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b8wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ // Second output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD3d8: >+ case ARM_VLD3d16: >+ case ARM_VLD3d32: >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD3q8: >+ case ARM_VLD3q16: >+ case ARM_VLD3q32: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ // Third output register >+ switch(MCInst_getOpcode(Inst)) { >+ case ARM_VLD3d8: >+ case ARM_VLD3d16: >+ case ARM_VLD3d32: >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD3q8: >+ case ARM_VLD3q16: >+ case ARM_VLD3q32: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Fourth output register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD4d8: >+ case ARM_VLD4d16: >+ case ARM_VLD4d32: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD4q8: >+ case ARM_VLD4q16: >+ case ARM_VLD4q32: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Writeback operand >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1d8wb_fixed: >+ case ARM_VLD1d16wb_fixed: >+ case ARM_VLD1d32wb_fixed: >+ case ARM_VLD1d64wb_fixed: >+ case ARM_VLD1d8wb_register: >+ case ARM_VLD1d16wb_register: >+ case ARM_VLD1d32wb_register: >+ case ARM_VLD1d64wb_register: >+ case ARM_VLD1q8wb_fixed: >+ case ARM_VLD1q16wb_fixed: >+ case ARM_VLD1q32wb_fixed: >+ case ARM_VLD1q64wb_fixed: >+ case ARM_VLD1q8wb_register: >+ case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_register: >+ case ARM_VLD1d8Twb_fixed: >+ case ARM_VLD1d8Twb_register: >+ case ARM_VLD1d16Twb_fixed: >+ case ARM_VLD1d16Twb_register: >+ case ARM_VLD1d32Twb_fixed: >+ case ARM_VLD1d32Twb_register: >+ case ARM_VLD1d64Twb_fixed: >+ case ARM_VLD1d64Twb_register: >+ case ARM_VLD1d8Qwb_fixed: >+ case ARM_VLD1d8Qwb_register: >+ case ARM_VLD1d16Qwb_fixed: >+ case ARM_VLD1d16Qwb_register: >+ case ARM_VLD1d32Qwb_fixed: >+ case ARM_VLD1d32Qwb_register: >+ case ARM_VLD1d64Qwb_fixed: >+ case ARM_VLD1d64Qwb_register: >+ case ARM_VLD2d8wb_fixed: >+ case ARM_VLD2d16wb_fixed: >+ case ARM_VLD2d32wb_fixed: >+ case ARM_VLD2q8wb_fixed: >+ case ARM_VLD2q16wb_fixed: >+ case ARM_VLD2q32wb_fixed: >+ case ARM_VLD2d8wb_register: >+ case ARM_VLD2d16wb_register: >+ case ARM_VLD2d32wb_register: >+ case ARM_VLD2q8wb_register: >+ case ARM_VLD2q16wb_register: >+ case ARM_VLD2q32wb_register: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2b8wb_register: >+ case ARM_VLD2b16wb_register: >+ case ARM_VLD2b32wb_register: >+ MCOperand_CreateImm0(Inst, 0); >+ break; >+ case ARM_VLD3d8_UPD: >+ case ARM_VLD3d16_UPD: >+ case ARM_VLD3d32_UPD: >+ case ARM_VLD3q8_UPD: >+ case ARM_VLD3q16_UPD: >+ case ARM_VLD3q32_UPD: >+ case ARM_VLD4d8_UPD: >+ case ARM_VLD4d16_UPD: >+ case ARM_VLD4d32_UPD: >+ case ARM_VLD4q8_UPD: >+ case ARM_VLD4q16_UPD: >+ case ARM_VLD4q32_UPD: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // AddrMode6 Base (register+alignment) >+ if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // AddrMode6 Offset (register) >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ // The below have been updated to have explicit am6offset split >+ // between fixed and register offset. For those instructions not >+ // yet updated, we need to add an additional reg0 operand for the >+ // fixed variant. >+ // >+ // The fixed offset encodes as Rm == 0xd, so we check for that. >+ if (Rm == 0xd) { >+ MCOperand_CreateReg0(Inst, 0); >+ break; >+ } >+ // Fall through to handle the register offset variant. >+ case ARM_VLD1d8wb_fixed: >+ case ARM_VLD1d16wb_fixed: >+ case ARM_VLD1d32wb_fixed: >+ case ARM_VLD1d64wb_fixed: >+ case ARM_VLD1d8Twb_fixed: >+ case ARM_VLD1d16Twb_fixed: >+ case ARM_VLD1d32Twb_fixed: >+ case ARM_VLD1d64Twb_fixed: >+ case ARM_VLD1d8Qwb_fixed: >+ case ARM_VLD1d16Qwb_fixed: >+ case ARM_VLD1d32Qwb_fixed: >+ case ARM_VLD1d64Qwb_fixed: >+ case ARM_VLD1d8wb_register: >+ case ARM_VLD1d16wb_register: >+ case ARM_VLD1d32wb_register: >+ case ARM_VLD1d64wb_register: >+ case ARM_VLD1q8wb_fixed: >+ case ARM_VLD1q16wb_fixed: >+ case ARM_VLD1q32wb_fixed: >+ case ARM_VLD1q64wb_fixed: >+ case ARM_VLD1q8wb_register: >+ case ARM_VLD1q16wb_register: >+ case ARM_VLD1q32wb_register: >+ case ARM_VLD1q64wb_register: >+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback >+ // variant encodes Rm == 0xf. Anything else is a register offset post- >+ // increment and we need to add the register operand to the instruction. >+ if (Rm != 0xD && Rm != 0xF && >+ !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2d8wb_fixed: >+ case ARM_VLD2d16wb_fixed: >+ case ARM_VLD2d32wb_fixed: >+ case ARM_VLD2b8wb_fixed: >+ case ARM_VLD2b16wb_fixed: >+ case ARM_VLD2b32wb_fixed: >+ case ARM_VLD2q8wb_fixed: >+ case ARM_VLD2q16wb_fixed: >+ case ARM_VLD2q32wb_fixed: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned load; >+ unsigned type = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned align = fieldFromInstruction_4(Insn, 4, 2); >+ if (type == 6 && (align & 2)) return MCDisassembler_Fail; >+ if (type == 7 && (align & 2)) return MCDisassembler_Fail; >+ if (type == 10 && align == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned type, align, load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ type = fieldFromInstruction_4(Insn, 8, 4); >+ align = fieldFromInstruction_4(Insn, 4, 2); >+ if (type == 8 && align == 3) return MCDisassembler_Fail; >+ if (type == 9 && align == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned align, load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ align = fieldFromInstruction_4(Insn, 4, 2); >+ if (align & 2) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned load; >+ unsigned size = fieldFromInstruction_4(Insn, 6, 2); >+ if (size == 3) return MCDisassembler_Fail; >+ >+ load = fieldFromInstruction_4(Insn, 21, 1); >+ return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) >+ : DecodeVSTInstruction(Inst, Insn, Address, Decoder); >+} >+ >+static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned wb, Rn, Rm; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ wb = fieldFromInstruction_4(Insn, 16, 4); >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ // Writeback Operand >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST1d8wb_fixed: >+ case ARM_VST1d16wb_fixed: >+ case ARM_VST1d32wb_fixed: >+ case ARM_VST1d64wb_fixed: >+ case ARM_VST1d8wb_register: >+ case ARM_VST1d16wb_register: >+ case ARM_VST1d32wb_register: >+ case ARM_VST1d64wb_register: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1q8wb_register: >+ case ARM_VST1q16wb_register: >+ case ARM_VST1q32wb_register: >+ case ARM_VST1q64wb_register: >+ case ARM_VST1d8Twb_fixed: >+ case ARM_VST1d16Twb_fixed: >+ case ARM_VST1d32Twb_fixed: >+ case ARM_VST1d64Twb_fixed: >+ case ARM_VST1d8Twb_register: >+ case ARM_VST1d16Twb_register: >+ case ARM_VST1d32Twb_register: >+ case ARM_VST1d64Twb_register: >+ case ARM_VST1d8Qwb_fixed: >+ case ARM_VST1d16Qwb_fixed: >+ case ARM_VST1d32Qwb_fixed: >+ case ARM_VST1d64Qwb_fixed: >+ case ARM_VST1d8Qwb_register: >+ case ARM_VST1d16Qwb_register: >+ case ARM_VST1d32Qwb_register: >+ case ARM_VST1d64Qwb_register: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2d8wb_register: >+ case ARM_VST2d16wb_register: >+ case ARM_VST2d32wb_register: >+ case ARM_VST2q8wb_fixed: >+ case ARM_VST2q16wb_fixed: >+ case ARM_VST2q32wb_fixed: >+ case ARM_VST2q8wb_register: >+ case ARM_VST2q16wb_register: >+ case ARM_VST2q32wb_register: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b32wb_fixed: >+ case ARM_VST2b8wb_register: >+ case ARM_VST2b16wb_register: >+ case ARM_VST2b32wb_register: >+ if (Rm == 0xF) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 0); >+ break; >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // AddrMode6 Base (register+alignment) >+ if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ // AddrMode6 Offset (register) >+ switch (MCInst_getOpcode(Inst)) { >+ default: >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ break; >+ case ARM_VST1d8wb_fixed: >+ case ARM_VST1d16wb_fixed: >+ case ARM_VST1d32wb_fixed: >+ case ARM_VST1d64wb_fixed: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1d8Twb_fixed: >+ case ARM_VST1d16Twb_fixed: >+ case ARM_VST1d32Twb_fixed: >+ case ARM_VST1d64Twb_fixed: >+ case ARM_VST1d8Qwb_fixed: >+ case ARM_VST1d16Qwb_fixed: >+ case ARM_VST1d32Qwb_fixed: >+ case ARM_VST1d64Qwb_fixed: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2q8wb_fixed: >+ case ARM_VST2q16wb_fixed: >+ case ARM_VST2q32wb_fixed: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b32wb_fixed: >+ break; >+ } >+ >+ >+ // First input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST1q16: >+ case ARM_VST1q32: >+ case ARM_VST1q64: >+ case ARM_VST1q8: >+ case ARM_VST1q16wb_fixed: >+ case ARM_VST1q16wb_register: >+ case ARM_VST1q32wb_fixed: >+ case ARM_VST1q32wb_register: >+ case ARM_VST1q64wb_fixed: >+ case ARM_VST1q64wb_register: >+ case ARM_VST1q8wb_fixed: >+ case ARM_VST1q8wb_register: >+ case ARM_VST2d16: >+ case ARM_VST2d32: >+ case ARM_VST2d8: >+ case ARM_VST2d16wb_fixed: >+ case ARM_VST2d16wb_register: >+ case ARM_VST2d32wb_fixed: >+ case ARM_VST2d32wb_register: >+ case ARM_VST2d8wb_fixed: >+ case ARM_VST2d8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST2b16: >+ case ARM_VST2b32: >+ case ARM_VST2b8: >+ case ARM_VST2b16wb_fixed: >+ case ARM_VST2b16wb_register: >+ case ARM_VST2b32wb_fixed: >+ case ARM_VST2b32wb_register: >+ case ARM_VST2b8wb_fixed: >+ case ARM_VST2b8wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ // Second input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST3d8: >+ case ARM_VST3d16: >+ case ARM_VST3d32: >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST3q8: >+ case ARM_VST3q16: >+ case ARM_VST3q32: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Third input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST3d8: >+ case ARM_VST3d16: >+ case ARM_VST3d32: >+ case ARM_VST3d8_UPD: >+ case ARM_VST3d16_UPD: >+ case ARM_VST3d32_UPD: >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST3q8: >+ case ARM_VST3q16: >+ case ARM_VST3q32: >+ case ARM_VST3q8_UPD: >+ case ARM_VST3q16_UPD: >+ case ARM_VST3q32_UPD: >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Fourth input register >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VST4d8: >+ case ARM_VST4d16: >+ case ARM_VST4d32: >+ case ARM_VST4d8_UPD: >+ case ARM_VST4d16_UPD: >+ case ARM_VST4d32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VST4q8: >+ case ARM_VST4q16: >+ case ARM_VST4q32: >+ case ARM_VST4q8_UPD: >+ case ARM_VST4q16_UPD: >+ case ARM_VST4q32_UPD: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, align, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ size = fieldFromInstruction_4(Insn, 6, 2); >+ >+ if (size == 0 && align == 1) >+ return MCDisassembler_Fail; >+ align *= (1 << size); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8: >+ case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register: >+ case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register: >+ case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ } >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ // The fixed offset post-increment encodes Rm == 0xd. The no-writeback >+ // variant encodes Rm == 0xf. Anything else is a register offset post- >+ // increment and we need to add the register operand to the instruction. >+ if (Rm != 0xD && Rm != 0xF && >+ !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, align, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ size = 1 << fieldFromInstruction_4(Insn, 6, 2); >+ align *= 2*size; >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8: >+ case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register: >+ case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register: >+ case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2: >+ case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register: >+ case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register: >+ case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register: >+ if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ } >+ >+ if (Rm != 0xF) >+ MCOperand_CreateImm0(Inst, 0); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ if (Rm != 0xD && Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, inc; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1; >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 0); >+ >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, size, inc, align; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ size = fieldFromInstruction_4(Insn, 6, 2); >+ inc = fieldFromInstruction_4(Insn, 5, 1) + 1; >+ align = fieldFromInstruction_4(Insn, 4, 1); >+ >+ if (size == 0x3) { >+ if (align == 0) >+ return MCDisassembler_Fail; >+ align = 16; >+ } else { >+ if (size == 2) { >+ align *= 8; >+ } else { >+ size = 1 << size; >+ align *= 4 * size; >+ } >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ >+ if (Rm == 0xD) >+ MCOperand_CreateReg0(Inst, 0); >+ else if (Rm != 0xF) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned imm, Q; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ imm = fieldFromInstruction_4(Insn, 0, 4); >+ imm |= fieldFromInstruction_4(Insn, 16, 3) << 4; >+ imm |= fieldFromInstruction_4(Insn, 24, 1) << 7; >+ imm |= fieldFromInstruction_4(Insn, 8, 4) << 8; >+ imm |= fieldFromInstruction_4(Insn, 5, 1) << 12; >+ Q = fieldFromInstruction_4(Insn, 6, 1); >+ >+ if (Q) { >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VORRiv4i16: >+ case ARM_VORRiv2i32: >+ case ARM_VBICiv4i16: >+ case ARM_VBICiv2i32: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ case ARM_VORRiv8i16: >+ case ARM_VORRiv4i32: >+ case ARM_VBICiv8i16: >+ case ARM_VBICiv4i32: >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rm, size; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 18, 2); >+ >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 8 << size); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 8 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 16 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 32 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, 64 - Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rn, Rm, op; >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ Rn = fieldFromInstruction_4(Insn, 16, 4); >+ Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4; >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4; >+ op = fieldFromInstruction_4(Insn, 6, 1); >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (op) { >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; // Writeback >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_VTBL2: >+ case ARM_VTBX2: >+ if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned dst = fieldFromInstruction_2(Insn, 8, 3); >+ unsigned imm = fieldFromInstruction_2(Insn, 0, 8); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ switch(MCInst_getOpcode(Inst)) { >+ default: >+ return MCDisassembler_Fail; >+ case ARM_tADR: >+ break; // tADR does not explicitly represent the PC as an operand. >+ case ARM_tADDrSPi: >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ break; >+ } >+ >+ MCOperand_CreateImm0(Inst, imm); >+ return S; >+} >+ >+static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val, 21)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, Val << 1); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 0, 3); >+ unsigned Rm = fieldFromInstruction_4(Val, 3, 3); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 0, 3); >+ unsigned imm = fieldFromInstruction_4(Val, 3, 5); >+ >+ if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imm = Val << 2; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateImm0(Inst, Val); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 6, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 2, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 2); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRHs: >+ case ARM_t2STRBs: >+ case ARM_t2STRs: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned addrmode; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRBs: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRHs: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHs: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2LDRSBs: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRs: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2PLDs: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIs: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHs: >+ return MCDisassembler_Fail; >+ case ARM_t2LDRHs: >+ // FIXME: this instruction is only available with MP extensions, >+ // this should be checked first but we don't have access to the >+ // feature bits here. >+ MCInst_setOpcode(Inst, ARM_t2PLDWs); >+ break; >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDs: >+ case ARM_t2PLDWs: >+ case ARM_t2PLIs: >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ addrmode = fieldFromInstruction_4(Insn, 4, 2); >+ addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2; >+ addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6; >+ if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 9, 1); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ imm |= (U << 8); >+ imm |= (Rn << 9); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRBi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRSBi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRHi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHi8: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2PLDi8: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIi8: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHi8: >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDi8: >+ case ARM_t2PLIi8: >+ case ARM_t2PLDWi8: >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= (Rn << 13); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRHi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSHi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ case ARM_t2LDRBi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRSBi12: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2PLDi12: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2PLIi12: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRSHi12: >+ return MCDisassembler_Fail; >+ case ARM_t2LDRHi12: >+ MCInst_setOpcode(Inst, ARM_t2PLDi12); >+ break; >+ default: >+ break; >+ } >+ } >+ >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDi12: >+ case ARM_t2PLDWi12: >+ case ARM_t2PLIi12: >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 8); >+ imm |= (Rn << 9); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRT: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRBT: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRHT: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSBT: >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRSHT: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void* Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ int imm = fieldFromInstruction_4(Insn, 0, 12); >+ >+ if (Rt == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRBpci: >+ case ARM_t2LDRHpci: >+ MCInst_setOpcode(Inst, ARM_t2PLDpci); >+ break; >+ case ARM_t2LDRSBpci: >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ break; >+ case ARM_t2LDRSHpci: >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ } >+ >+ switch(MCInst_getOpcode(Inst)) { >+ case ARM_t2PLDpci: >+ case ARM_t2PLIpci: >+ break; >+ default: >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!U) { >+ // Special case for #-0. >+ if (imm == 0) >+ imm = INT32_MIN; >+ else >+ imm = -imm; >+ } >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0) >+ MCOperand_CreateImm0(Inst, INT32_MIN); >+ else { >+ int imm = Val & 0xFF; >+ >+ if (!(Val & 0x100)) imm *= -1; >+ MCOperand_CreateImm0(Inst, imm * 4); >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 9); >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 8, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ int imm = Val & 0xFF; >+ if (Val == 0) >+ imm = INT32_MIN; >+ else if (!(Val & 0x100)) >+ imm *= -1; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 9, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 9); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRT: >+ case ARM_t2STRBT: >+ case ARM_t2STRHT: >+ case ARM_t2STRi8: >+ case ARM_t2STRHi8: >+ case ARM_t2STRBi8: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ break; >+ default: >+ break; >+ } >+ >+ // Some instructions always use an additive offset. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDRT: >+ case ARM_t2LDRBT: >+ case ARM_t2LDRHT: >+ case ARM_t2LDRSBT: >+ case ARM_t2LDRSHT: >+ case ARM_t2STRT: >+ case ARM_t2STRBT: >+ case ARM_t2STRHT: >+ imm |= 0x100; >+ break; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned load; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ addr |= fieldFromInstruction_4(Insn, 9, 1) << 8; >+ addr |= Rn << 9; >+ load = fieldFromInstruction_4(Insn, 20, 1); >+ >+ if (Rn == 15) { >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2LDR_PRE: >+ case ARM_t2LDR_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRpci); >+ break; >+ case ARM_t2LDRB_PRE: >+ case ARM_t2LDRB_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRBpci); >+ break; >+ case ARM_t2LDRH_PRE: >+ case ARM_t2LDRH_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRHpci); >+ break; >+ case ARM_t2LDRSB_PRE: >+ case ARM_t2LDRSB_POST: >+ if (Rt == 15) >+ MCInst_setOpcode(Inst, ARM_t2PLIpci); >+ else >+ MCInst_setOpcode(Inst, ARM_t2LDRSBpci); >+ break; >+ case ARM_t2LDRSH_PRE: >+ case ARM_t2LDRSH_POST: >+ MCInst_setOpcode(Inst, ARM_t2LDRSHpci); >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!load) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (load) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Val, 13, 4); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 12); >+ >+ // Thumb stores cannot use PC as dest register. >+ switch (MCInst_getOpcode(Inst)) { >+ case ARM_t2STRi12: >+ case ARM_t2STRBi12: >+ case ARM_t2STRHi12: >+ if (Rn == 15) >+ return MCDisassembler_Fail; >+ default: >+ break; >+ } >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imm = fieldFromInstruction_2(Insn, 0, 7); >+ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateImm0(Inst, imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ if (MCInst_getOpcode(Inst) == ARM_tADDrSP) { >+ unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3); >+ Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) { >+ unsigned Rm = fieldFromInstruction_2(Insn, 3, 4); >+ >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ MCOperand_CreateReg0(Inst, ARM_SP); >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2; >+ unsigned flags = fieldFromInstruction_2(Insn, 0, 3); >+ >+ MCOperand_CreateImm0(Inst, imod); >+ MCOperand_CreateImm0(Inst, flags); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned add = fieldFromInstruction_4(Insn, 4, 1); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, add); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // Val is passed in as S:J1:J2:imm10H:imm10L:'0' >+ // Note only one trailing zero not two. Also the J1 and J2 values are from >+ // the encoded instruction. So here change to I1 and I2 values via: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with two trailing zeros as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); >+ unsigned S = (Val >> 23) & 1; >+ unsigned J1 = (Val >> 22) & 1; >+ unsigned J2 = (Val >> 21) & 1; >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); >+ int imm32 = SignExtend32(tmp << 1, 25); >+ >+ MCOperand_CreateImm0(Inst, imm32); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val == 0xA || Val == 0xB) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (Rn == ARM_SP) S = MCDisassembler_SoftFail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ return S; >+} >+ >+static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned brtarget; >+ unsigned pred = fieldFromInstruction_4(Insn, 22, 4); >+ if (pred == 0xE || pred == 0xF) { >+ unsigned imm; >+ unsigned opc = fieldFromInstruction_4(Insn, 4, 28); >+ switch (opc) { >+ default: >+ return MCDisassembler_Fail; >+ case 0xf3bf8f4: >+ MCInst_setOpcode(Inst, ARM_t2DSB); >+ break; >+ case 0xf3bf8f5: >+ MCInst_setOpcode(Inst, ARM_t2DMB); >+ break; >+ case 0xf3bf8f6: >+ MCInst_setOpcode(Inst, ARM_t2ISB); >+ break; >+ } >+ >+ imm = fieldFromInstruction_4(Insn, 0, 4); >+ return DecodeMemBarrierOption(Inst, imm, Address, Decoder); >+ } >+ >+ brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1; >+ brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19; >+ brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18; >+ brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12; >+ brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20; >+ >+ if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+// Decode a shifted immediate operand. These basically consist >+// of an 8-bit value, and a 4-bit directive that specifies either >+// a splat operation or a rotation. >+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned ctrl = fieldFromInstruction_4(Val, 10, 2); >+ if (ctrl == 0) { >+ unsigned byte = fieldFromInstruction_4(Val, 8, 2); >+ unsigned imm = fieldFromInstruction_4(Val, 0, 8); >+ switch (byte) { >+ case 0: >+ MCOperand_CreateImm0(Inst, imm); >+ break; >+ case 1: >+ MCOperand_CreateImm0(Inst, (imm << 16) | imm); >+ break; >+ case 2: >+ MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8)); >+ break; >+ case 3: >+ MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm); >+ break; >+ } >+ } else { >+ unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80; >+ unsigned rot = fieldFromInstruction_4(Val, 7, 5); >+ unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); >+ MCOperand_CreateImm0(Inst, imm); >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ // Val is passed in as S:J1:J2:imm10:imm11 >+ // Note no trailing zero after imm11. Also the J1 and J2 values are from >+ // the encoded instruction. So here change to I1 and I2 values via: >+ // I1 = NOT(J1 EOR S); >+ // I2 = NOT(J2 EOR S); >+ // and build the imm32 with one trailing zero as documented: >+ // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); >+ unsigned S = (Val >> 23) & 1; >+ unsigned J1 = (Val >> 22) & 1; >+ unsigned J2 = (Val >> 21) & 1; >+ unsigned I1 = !(J1 ^ S); >+ unsigned I2 = !(J2 ^ S); >+ unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); >+ int imm32 = SignExtend32(tmp << 1, 25); >+ >+ MCOperand_CreateImm0(Inst, imm32); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val & ~0xf) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ if (Val & ~0xf) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode); >+ if (FeatureBits & ARM_FeatureMClass) { >+ unsigned ValLow = Val & 0xff; >+ >+ // Validate the SYSm value first. >+ switch (ValLow) { >+ case 0: // apsr >+ case 1: // iapsr >+ case 2: // eapsr >+ case 3: // xpsr >+ case 5: // ipsr >+ case 6: // epsr >+ case 7: // iepsr >+ case 8: // msp >+ case 9: // psp >+ case 16: // primask >+ case 20: // control >+ break; >+ case 17: // basepri >+ case 18: // basepri_max >+ case 19: // faultmask >+ if (!(FeatureBits & ARM_HasV7Ops)) >+ // Values basepri, basepri_max and faultmask are only valid for v7m. >+ return MCDisassembler_Fail; >+ break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ >+ // The ARMv7-M architecture has an additional 2-bit mask value in the MSR >+ // instruction (bits {11,10}). The mask is used only with apsr, iapsr, >+ // eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates >+ // if the NZCVQ bits should be moved by the instruction. Bit mask{0} >+ // indicates the move for the GE{3:0} bits, the mask{0} bit can be set >+ // only if the processor includes the DSP extension. >+ if ((FeatureBits & ARM_HasV7Ops) && MCInst_getOpcode(Inst) == ARM_t2MSR_M) { >+ unsigned Mask = (Val >> 10) & 3; >+ if (Mask == 0 || (Mask != 2 && ValLow > 3) || >+ (!(FeatureBits & ARM_FeatureDSPThumb2) && Mask == 1)) >+ return MCDisassembler_Fail; >+ } >+ } else { >+ // A/R class >+ if (Val == 0) >+ return MCDisassembler_Fail; >+ } >+ >+ MCOperand_CreateImm0(Inst, Val); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred, Rm; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ if (Rm == 0xF) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned imm = fieldFromInstruction_4(Insn, 0, 12); >+ imm |= fieldFromInstruction_4(Insn, 16, 4) << 13; >+ imm |= fieldFromInstruction_4(Insn, 23, 1) << 12; >+ pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0 : >+ align = 0; break; >+ case 3: >+ align = 4; break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ align = 4; break; >+ default: >+ return MCDisassembler_Fail; >+ } >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 1: >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 4, 1) != 0) >+ align = 8; >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 2; >+ break; >+ case 1: >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 4, 1) != 0) >+ align = 8; >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 4, 2)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ if (fieldFromInstruction_4(Insn, 4, 2)) >+ return MCDisassembler_Fail; // UNDEFINED >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 8; >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ return MCDisassembler_Fail; >+ default: >+ align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; >+ } >+ >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned size, align = 0, index = 0, inc = 1; >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); >+ Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4; >+ size = fieldFromInstruction_4(Insn, 10, 2); >+ >+ switch (size) { >+ default: >+ return MCDisassembler_Fail; >+ case 0: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 4; >+ index = fieldFromInstruction_4(Insn, 5, 3); >+ break; >+ case 1: >+ if (fieldFromInstruction_4(Insn, 4, 1)) >+ align = 8; >+ index = fieldFromInstruction_4(Insn, 6, 2); >+ if (fieldFromInstruction_4(Insn, 5, 1)) >+ inc = 2; >+ break; >+ case 2: >+ switch (fieldFromInstruction_4(Insn, 4, 2)) { >+ case 0: >+ align = 0; break; >+ case 3: >+ return MCDisassembler_Fail; >+ default: >+ align = 4 << fieldFromInstruction_4(Insn, 4, 2); break; >+ } >+ >+ index = fieldFromInstruction_4(Insn, 7, 1); >+ if (fieldFromInstruction_4(Insn, 6, 1)) >+ inc = 2; >+ break; >+ } >+ >+ if (Rm != 0xF) { // Writeback >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, align); >+ if (Rm != 0xF) { >+ if (Rm != 0xD) { >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ } else >+ MCOperand_CreateReg0(Inst, 0); >+ } >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, index); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; >+ >+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned Rm = fieldFromInstruction_4(Insn, 5, 1); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1; >+ >+ if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned pred = fieldFromInstruction_4(Insn, 4, 4); >+ unsigned mask = fieldFromInstruction_4(Insn, 0, 4); >+ >+ if (pred == 0xF) { >+ pred = 0xE; >+ S = MCDisassembler_SoftFail; >+ } >+ >+ if (mask == 0x0) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateImm0(Inst, pred); >+ MCOperand_CreateImm0(Inst, mask); >+ return S; >+} >+ >+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ bool writeback = (W == 1) | (P == 0); >+ >+ addr |= (U << 8) | (Rn << 9); >+ >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ Check(&S, MCDisassembler_SoftFail); >+ if (Rt == Rt2) >+ Check(&S, MCDisassembler_SoftFail); >+ >+ // Rt >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt2 >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Writeback operand >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // addr >+ if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned addr = fieldFromInstruction_4(Insn, 0, 8); >+ unsigned W = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned U = fieldFromInstruction_4(Insn, 23, 1); >+ unsigned P = fieldFromInstruction_4(Insn, 24, 1); >+ bool writeback = (W == 1) | (P == 0); >+ >+ addr |= (U << 8) | (Rn << 9); >+ >+ if (writeback && (Rn == Rt || Rn == Rt2)) >+ Check(&S, MCDisassembler_SoftFail); >+ >+ // Writeback operand >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // Rt2 >+ if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ // addr >+ if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ unsigned Val; >+ unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1); >+ unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1); >+ if (sign1 != sign2) return MCDisassembler_Fail; >+ >+ Val = fieldFromInstruction_4(Insn, 0, 8); >+ Val |= fieldFromInstruction_4(Insn, 12, 3) << 8; >+ Val |= fieldFromInstruction_4(Insn, 26, 1) << 11; >+ Val |= sign1 << 12; >+ MCOperand_CreateImm0(Inst, SignExtend32(Val, 13)); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ // Shift of "asr #32" is not allowed in Thumb2 mode. >+ if (Val == 0x20) S = MCDisassembler_SoftFail; >+ MCOperand_CreateImm0(Inst, Val); >+ return S; >+} >+ >+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S; >+ >+ unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); >+ unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); >+ unsigned pred = fieldFromInstruction_4(Insn, 28, 4); >+ >+ if (pred == 0xF) >+ return DecodeCPSInstruction(Inst, Insn, Address, Decoder); >+ >+ S = MCDisassembler_Success; >+ >+ if (Rt == Rn || Rn == Rt2) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Vm, imm, cmode, op; >+ unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); >+ Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); >+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); >+ Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); >+ imm = fieldFromInstruction_4(Insn, 16, 6); >+ cmode = fieldFromInstruction_4(Insn, 8, 4); >+ op = fieldFromInstruction_4(Insn, 5, 1); >+ >+ // VMOVv2f32 is ambiguous with these decodings. >+ if (!(imm & 0x38) && cmode == 0xF) { >+ if (op == 1) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_VMOVv2f32); >+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!(imm & 0x20)) return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 64 - imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Vm, imm, cmode, op; >+ unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0); >+ Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4); >+ Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); >+ Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); >+ imm = fieldFromInstruction_4(Insn, 16, 6); >+ cmode = fieldFromInstruction_4(Insn, 8, 4); >+ op = fieldFromInstruction_4(Insn, 5, 1); >+ >+ // VMOVv4f32 is ambiguous with these decodings. >+ if (!(imm & 0x38) && cmode == 0xF) { >+ if (op == 1) return MCDisassembler_Fail; >+ MCInst_setOpcode(Inst, ARM_VMOVv4f32); >+ return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); >+ } >+ >+ if (!(imm & 0x20)) return MCDisassembler_Fail; >+ >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, 64 - imm); >+ >+ return S; >+} >+ >+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ DecodeStatus S = MCDisassembler_Success; >+ unsigned Cond; >+ unsigned Rn = fieldFromInstruction_4(Val, 16, 4); >+ unsigned Rt = fieldFromInstruction_4(Val, 12, 4); >+ unsigned Rm = fieldFromInstruction_4(Val, 0, 4); >+ Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4); >+ Cond = fieldFromInstruction_4(Val, 28, 4); >+ >+ if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt) >+ S = MCDisassembler_SoftFail; >+ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) >+ return MCDisassembler_Fail; >+ >+ return S; >+} >+ >+static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, >+ uint64_t Address, const void *Decoder) >+{ >+ >+ DecodeStatus S = MCDisassembler_Success; >+ >+ unsigned CRm = fieldFromInstruction_4(Val, 0, 4); >+ unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); >+ unsigned cop = fieldFromInstruction_4(Val, 8, 4); >+ unsigned Rt = fieldFromInstruction_4(Val, 12, 4); >+ unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4); >+ >+ if ((cop & ~0x1) == 0xa) >+ return MCDisassembler_Fail; >+ >+ if (Rt == Rt2) >+ S = MCDisassembler_SoftFail; >+ >+ MCOperand_CreateImm0(Inst, cop); >+ MCOperand_CreateImm0(Inst, opc1); >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) >+ return MCDisassembler_Fail; >+ if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) >+ return MCDisassembler_Fail; >+ MCOperand_CreateImm0(Inst, CRm); >+ >+ return S; >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h b/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..713b00d3aecfa25c80a168432a81a56bc9b6ec80 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMDisassembler.h >@@ -0,0 +1,18 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_ARMDISASSEMBLER_H >+#define CS_ARMDISASSEMBLER_H >+ >+#include "../../include/capstone.h" >+#include "../../MCRegisterInfo.h" >+ >+void ARM_init(MCRegisterInfo *MRI); >+ >+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+uint64_t ARM_getFeatureBits(unsigned int mode); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..e907a0122a68d18f4895ae4250ea95ac99ac166a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenAsmWriter.inc >@@ -0,0 +1,11814 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 1329U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 1322U, // BUNDLE >+ 1339U, // LIFETIME_START >+ 1309U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // ABS >+ 5768U, // ADCri >+ 5768U, // ADCrr >+ 9864U, // ADCrsi >+ 13960U, // ADCrsr >+ 0U, // ADDSri >+ 0U, // ADDSrr >+ 0U, // ADDSrsi >+ 0U, // ADDSrsr >+ 5829U, // ADDri >+ 5829U, // ADDrr >+ 9925U, // ADDrsi >+ 14021U, // ADDrsr >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 18806U, // ADR >+ 1090671288U, // AESD >+ 1090671296U, // AESE >+ 1107448485U, // AESIMC >+ 1107448495U, // AESMC >+ 5882U, // ANDri >+ 5882U, // ANDrr >+ 9978U, // ANDrsi >+ 14074U, // ANDrsr >+ 268708U, // ASRi >+ 268708U, // ASRr >+ 0U, // B >+ 0U, // BCCZi64 >+ 0U, // BCCi64 >+ 26256U, // BFC >+ 30677U, // BFI >+ 5781U, // BICri >+ 5781U, // BICrr >+ 9877U, // BICrsi >+ 13973U, // BICrsr >+ 414542U, // BKPT >+ 414522U, // BL >+ 414582U, // BLX >+ 1073777581U, // BLX_pred >+ 414582U, // BLXi >+ 1073776678U, // BL_pred >+ 0U, // BMOVPCB_CALL >+ 0U, // BMOVPCRX_CALL >+ 0U, // BR_JTadd >+ 0U, // BR_JTm >+ 0U, // BR_JTr >+ 414578U, // BX >+ 1073776615U, // BXJ >+ 0U, // BX_CALL >+ 564041U, // BX_RET >+ 1073777481U, // BX_pred >+ 1073776035U, // Bcc >+ 2197858625U, // CDP >+ 67809687U, // CDP2 >+ 2967U, // CLREX >+ 19417U, // CLZ >+ 18663U, // CMNri >+ 18663U, // CMNzrr >+ 26855U, // CMNzrsi >+ 30951U, // CMNzrsr >+ 18763U, // CMPri >+ 18763U, // CMPrr >+ 26955U, // CMPrsi >+ 31051U, // CMPrsr >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_STRUCT_BYVAL_I32 >+ 414526U, // CPS1p >+ 1157679610U, // CPS2p >+ 83937786U, // CPS3p >+ 33706710U, // CRC32B >+ 33706718U, // CRC32CB >+ 33706782U, // CRC32CH >+ 33706851U, // CRC32CW >+ 33706774U, // CRC32H >+ 33706843U, // CRC32W >+ 1073776474U, // DBG >+ 54005U, // DMB >+ 54010U, // DSB >+ 6546U, // EORri >+ 6546U, // EORrr >+ 10642U, // EORrsi >+ 14738U, // EORrsr >+ 3322694386U, // FCONSTD >+ 3322825458U, // FCONSTS >+ 33573700U, // FLDMXDB_UPD >+ 35597U, // FLDMXIA >+ 33573645U, // FLDMXIA_UPD >+ 1087998U, // FMSTAT >+ 33573708U, // FSTMXDB_UPD >+ 35605U, // FSTMXIA >+ 33573653U, // FSTMXIA_UPD >+ 1073777285U, // HINT >+ 414537U, // HLT >+ 58111U, // ISB >+ 117766771U, // ITasm >+ 0U, // Int_eh_sjlj_dispatchsetup >+ 0U, // Int_eh_sjlj_longjmp >+ 0U, // Int_eh_sjlj_setjmp >+ 0U, // Int_eh_sjlj_setjmp_nofp >+ 17743U, // LDA >+ 17824U, // LDAB >+ 19333U, // LDAEX >+ 18024U, // LDAEXB >+ 134235924U, // LDAEXD >+ 18361U, // LDAEXH >+ 18281U, // LDAH >+ 152220460U, // LDC2L_OFFSET >+ 1242739500U, // LDC2L_OPTION >+ 2316481324U, // LDC2L_POST >+ 185774892U, // LDC2L_PRE >+ 152220030U, // LDC2_OFFSET >+ 1242739070U, // LDC2_OPTION >+ 2316480894U, // LDC2_POST >+ 185774462U, // LDC2_PRE >+ 3271587887U, // LDCL_OFFSET >+ 3271587887U, // LDCL_OPTION >+ 3271587887U, // LDCL_POST >+ 3271587887U, // LDCL_PRE >+ 3271587468U, // LDC_OFFSET >+ 3271587468U, // LDC_OPTION >+ 3271587468U, // LDC_POST >+ 3271587468U, // LDC_PRE >+ 34131U, // LDMDA >+ 33572179U, // LDMDA_UPD >+ 34258U, // LDMDB >+ 33572306U, // LDMDB_UPD >+ 34998U, // LDMIA >+ 0U, // LDMIA_RET >+ 33573046U, // LDMIA_UPD >+ 34277U, // LDMIB >+ 33572325U, // LDMIB_UPD >+ 281152U, // LDRBT_POST >+ 68160U, // LDRBT_POST_IMM >+ 68160U, // LDRBT_POST_REG >+ 67071U, // LDRB_POST_IMM >+ 67071U, // LDRB_POST_REG >+ 30207U, // LDRB_PRE_IMM >+ 67071U, // LDRB_PRE_REG >+ 26111U, // LDRBi12 >+ 30207U, // LDRBrs >+ 67326U, // LDRD >+ 42750U, // LDRD_POST >+ 42750U, // LDRD_PRE >+ 19345U, // LDREX >+ 18038U, // LDREXB >+ 134235938U, // LDREXD >+ 18375U, // LDREXH >+ 30612U, // LDRH >+ 31326U, // LDRHTi >+ 68190U, // LDRHTr >+ 67476U, // LDRH_POST >+ 67476U, // LDRH_PRE >+ 0U, // LDRLIT_ga_abs >+ 0U, // LDRLIT_ga_pcrel >+ 0U, // LDRLIT_ga_pcrel_ldr >+ 30225U, // LDRSB >+ 31308U, // LDRSBTi >+ 68172U, // LDRSBTr >+ 67089U, // LDRSB_POST >+ 67089U, // LDRSB_PRE >+ 30622U, // LDRSH >+ 31338U, // LDRSHTi >+ 68202U, // LDRSHTr >+ 67486U, // LDRSH_POST >+ 67486U, // LDRSH_PRE >+ 281226U, // LDRT_POST >+ 68234U, // LDRT_POST_IMM >+ 68234U, // LDRT_POST_REG >+ 67963U, // LDR_POST_IMM >+ 67963U, // LDR_POST_REG >+ 31099U, // LDR_PRE_IMM >+ 67963U, // LDR_PRE_REG >+ 27003U, // LDRcp >+ 27003U, // LDRi12 >+ 31099U, // LDRrs >+ 0U, // LEApcrel >+ 0U, // LEApcrelJT >+ 268433U, // LSLi >+ 268433U, // LSLr >+ 268715U, // LSRi >+ 268715U, // LSRr >+ 2197858674U, // MCR >+ 17478045U, // MCR2 >+ 2197883290U, // MCRR >+ 17478051U, // MCRR2 >+ 9595U, // MLA >+ 0U, // MLAv5 >+ 31197U, // MLS >+ 0U, // MOVCCi >+ 0U, // MOVCCi16 >+ 0U, // MOVCCi32imm >+ 0U, // MOVCCr >+ 0U, // MOVCCsi >+ 0U, // MOVCCsr >+ 1350387U, // MOVPCLR >+ 0U, // MOVPCRX >+ 27328U, // MOVTi16 >+ 0U, // MOVTi16_ga_pcrel >+ 0U, // MOV_ga_pcrel >+ 0U, // MOV_ga_pcrel_ldr >+ 72435U, // MOVi >+ 19208U, // MOVi16 >+ 0U, // MOVi16_ga_pcrel >+ 0U, // MOVi32imm >+ 72435U, // MOVr >+ 72435U, // MOVr_TC >+ 6899U, // MOVsi >+ 10995U, // MOVsr >+ 0U, // MOVsra_flag >+ 0U, // MOVsrl_flag >+ 201369245U, // MRC >+ 74116U, // MRC2 >+ 2197882529U, // MRRC >+ 17478026U, // MRRC2 >+ 35327U, // MRS >+ 1073777151U, // MRSsys >+ 218122672U, // MSR >+ 218122672U, // MSRi >+ 6305U, // MUL >+ 0U, // MULv5 >+ 0U, // MVNCCi >+ 71979U, // MVNi >+ 71979U, // MVNr >+ 6443U, // MVNsi >+ 10539U, // MVNsr >+ 6560U, // ORRri >+ 6560U, // ORRrr >+ 10656U, // ORRrsi >+ 14752U, // ORRrsr >+ 0U, // PICADD >+ 0U, // PICLDR >+ 0U, // PICLDRB >+ 0U, // PICLDRH >+ 0U, // PICLDRSB >+ 0U, // PICLDRSH >+ 0U, // PICSTR >+ 0U, // PICSTRB >+ 0U, // PICSTRH >+ 31275U, // PKHBT >+ 30238U, // PKHTB >+ 78700U, // PLDWi12 >+ 82796U, // PLDWrs >+ 78596U, // PLDi12 >+ 82692U, // PLDrs >+ 78631U, // PLIi12 >+ 82727U, // PLIrs >+ 26333U, // QADD >+ 25764U, // QADD16 >+ 25867U, // QADD8 >+ 27586U, // QASX >+ 26307U, // QDADD >+ 26179U, // QDSUB >+ 27445U, // QSAX >+ 26192U, // QSUB >+ 25726U, // QSUB16 >+ 25828U, // QSUB8 >+ 19057U, // RBIT >+ 19167U, // REV >+ 17608U, // REV16 >+ 18345U, // REVSH >+ 414408U, // RFEDA >+ 1462984U, // RFEDA_UPD >+ 414439U, // RFEDB >+ 1463015U, // RFEDB_UPD >+ 414415U, // RFEIA >+ 1462991U, // RFEIA_UPD >+ 414446U, // RFEIB >+ 1463022U, // RFEIB_UPD >+ 268694U, // RORi >+ 268694U, // RORr >+ 0U, // RRX >+ 334769U, // RRXi >+ 0U, // RSBSri >+ 0U, // RSBSrsi >+ 0U, // RSBSrsr >+ 5651U, // RSBri >+ 5651U, // RSBrr >+ 9747U, // RSBrsi >+ 13843U, // RSBrsr >+ 5798U, // RSCri >+ 5798U, // RSCrr >+ 9894U, // RSCrsi >+ 13990U, // RSCrsr >+ 25771U, // SADD16 >+ 25873U, // SADD8 >+ 27591U, // SASX >+ 5764U, // SBCri >+ 5764U, // SBCrr >+ 9860U, // SBCrsi >+ 13956U, // SBCrsr >+ 31651U, // SBFX >+ 27363U, // SDIV >+ 26700U, // SEL >+ 86793U, // SETEND >+ 16928834U, // SHA1C >+ 1107447884U, // SHA1H >+ 16928866U, // SHA1M >+ 16928876U, // SHA1P >+ 16928769U, // SHA1SU0 >+ 1090670619U, // SHA1SU1 >+ 16928854U, // SHA256H >+ 16928821U, // SHA256H2 >+ 1090670605U, // SHA256SU0 >+ 16928807U, // SHA256SU1 >+ 25747U, // SHADD16 >+ 25852U, // SHADD8 >+ 27573U, // SHASX >+ 27432U, // SHSAX >+ 25709U, // SHSUB16 >+ 25813U, // SHSUB8 >+ 1073776281U, // SMC >+ 30129U, // SMLABB >+ 31268U, // SMLABT >+ 30386U, // SMLAD >+ 31577U, // SMLADX >+ 92178U, // SMLAL >+ 30136U, // SMLALBB >+ 31281U, // SMLALBT >+ 30439U, // SMLALD >+ 31591U, // SMLALDX >+ 30244U, // SMLALTB >+ 31398U, // SMLALTT >+ 0U, // SMLALv5 >+ 30231U, // SMLATB >+ 31391U, // SMLATT >+ 30298U, // SMLAWB >+ 31429U, // SMLAWT >+ 30472U, // SMLSD >+ 31607U, // SMLSDX >+ 30450U, // SMLSLD >+ 31599U, // SMLSLDX >+ 30073U, // SMMLA >+ 31083U, // SMMLAR >+ 31195U, // SMMLS >+ 31144U, // SMMLSR >+ 26783U, // SMMUL >+ 27018U, // SMMULR >+ 26296U, // SMUAD >+ 27488U, // SMUADX >+ 26048U, // SMULBB >+ 27193U, // SMULBT >+ 10358U, // SMULL >+ 0U, // SMULLv5 >+ 26156U, // SMULTB >+ 27310U, // SMULTT >+ 26209U, // SMULWB >+ 27340U, // SMULWT >+ 26382U, // SMUSD >+ 27518U, // SMUSDX >+ 414646U, // SRSDA >+ 414598U, // SRSDA_UPD >+ 414668U, // SRSDB >+ 414622U, // SRSDB_UPD >+ 414657U, // SRSIA >+ 414610U, // SRSIA_UPD >+ 414679U, // SRSIB >+ 414634U, // SRSIB_UPD >+ 31258U, // SSAT >+ 25785U, // SSAT16 >+ 27450U, // SSAX >+ 25733U, // SSUB16 >+ 25834U, // SSUB8 >+ 152220467U, // STC2L_OFFSET >+ 1242739507U, // STC2L_OPTION >+ 2316481331U, // STC2L_POST >+ 185774899U, // STC2L_PRE >+ 152220049U, // STC2_OFFSET >+ 1242739089U, // STC2_OPTION >+ 2316480913U, // STC2_POST >+ 185774481U, // STC2_PRE >+ 3271587892U, // STCL_OFFSET >+ 3271587892U, // STCL_OPTION >+ 3271587892U, // STCL_POST >+ 3271587892U, // STCL_PRE >+ 3271587498U, // STC_OFFSET >+ 3271587498U, // STC_OPTION >+ 3271587498U, // STC_POST >+ 3271587498U, // STC_PRE >+ 18587U, // STL >+ 17905U, // STLB >+ 27531U, // STLEX >+ 26223U, // STLEXB >+ 26395U, // STLEXD >+ 26560U, // STLEXH >+ 18302U, // STLH >+ 34137U, // STMDA >+ 33572185U, // STMDA_UPD >+ 34265U, // STMDB >+ 33572313U, // STMDB_UPD >+ 35002U, // STMIA >+ 33573050U, // STMIA_UPD >+ 34283U, // STMIB >+ 33572331U, // STMIB_UPD >+ 281158U, // STRBT_POST >+ 33622598U, // STRBT_POST_IMM >+ 33622598U, // STRBT_POST_REG >+ 33621508U, // STRB_POST_IMM >+ 33621508U, // STRB_POST_REG >+ 33584644U, // STRB_PRE_IMM >+ 33621508U, // STRB_PRE_REG >+ 26116U, // STRBi12 >+ 0U, // STRBi_preidx >+ 0U, // STRBr_preidx >+ 30212U, // STRBrs >+ 67331U, // STRD >+ 33597187U, // STRD_POST >+ 33597187U, // STRD_PRE >+ 27549U, // STREX >+ 26237U, // STREXB >+ 26409U, // STREXD >+ 26574U, // STREXH >+ 30617U, // STRH >+ 33585764U, // STRHTi >+ 33622628U, // STRHTr >+ 33621913U, // STRH_POST >+ 33621913U, // STRH_PRE >+ 0U, // STRH_preidx >+ 281237U, // STRT_POST >+ 33622677U, // STRT_POST_IMM >+ 33622677U, // STRT_POST_REG >+ 33622460U, // STR_POST_IMM >+ 33622460U, // STR_POST_REG >+ 33585596U, // STR_PRE_IMM >+ 33622460U, // STR_PRE_REG >+ 27068U, // STRi12 >+ 0U, // STRi_preidx >+ 0U, // STRr_preidx >+ 31164U, // STRrs >+ 0U, // SUBS_PC_LR >+ 0U, // SUBSri >+ 0U, // SUBSrr >+ 0U, // SUBSrsi >+ 0U, // SUBSrsr >+ 5701U, // SUBri >+ 5701U, // SUBrr >+ 9797U, // SUBrsi >+ 13893U, // SUBrsr >+ 1073776302U, // SVC >+ 26969U, // SWP >+ 26106U, // SWPB >+ 30117U, // SXTAB >+ 29775U, // SXTAB16 >+ 30574U, // SXTAH >+ 26169U, // SXTB >+ 25695U, // SXTB16 >+ 26543U, // SXTH >+ 0U, // TAILJMPd >+ 0U, // TAILJMPr >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 18791U, // TEQri >+ 18791U, // TEQrr >+ 26983U, // TEQrsi >+ 31079U, // TEQrsr >+ 0U, // TPsoft >+ 2364U, // TRAP >+ 2364U, // TRAPNaCl >+ 19099U, // TSTri >+ 19099U, // TSTrr >+ 27291U, // TSTrsi >+ 31387U, // TSTrsr >+ 25778U, // UADD16 >+ 25879U, // UADD8 >+ 27596U, // UASX >+ 31656U, // UBFX >+ 414481U, // UDF >+ 27368U, // UDIV >+ 25755U, // UHADD16 >+ 25859U, // UHADD8 >+ 27579U, // UHASX >+ 27438U, // UHSAX >+ 25717U, // UHSUB16 >+ 25820U, // UHSUB8 >+ 30711U, // UMAAL >+ 92184U, // UMLAL >+ 0U, // UMLALv5 >+ 10364U, // UMULL >+ 0U, // UMULLv5 >+ 25763U, // UQADD16 >+ 25866U, // UQADD8 >+ 27585U, // UQASX >+ 27444U, // UQSAX >+ 25725U, // UQSUB16 >+ 25827U, // UQSUB8 >+ 25846U, // USAD8 >+ 29902U, // USADA8 >+ 31263U, // USAT >+ 25792U, // USAT16 >+ 27455U, // USAX >+ 25740U, // USUB16 >+ 25840U, // USUB8 >+ 30123U, // UXTAB >+ 29783U, // UXTAB16 >+ 30580U, // UXTAH >+ 26174U, // UXTB >+ 25702U, // UXTB16 >+ 26548U, // UXTH >+ 18380797U, // VABALsv2i64 >+ 18511869U, // VABALsv4i32 >+ 18642941U, // VABALsv8i16 >+ 18774013U, // VABALuv2i64 >+ 18905085U, // VABALuv4i32 >+ 19036157U, // VABALuv8i16 >+ 18642250U, // VABAsv16i8 >+ 18380106U, // VABAsv2i32 >+ 18511178U, // VABAsv4i16 >+ 18380106U, // VABAsv4i32 >+ 18511178U, // VABAsv8i16 >+ 18642250U, // VABAsv8i8 >+ 19035466U, // VABAuv16i8 >+ 18773322U, // VABAuv2i32 >+ 18904394U, // VABAuv4i16 >+ 18773322U, // VABAuv4i32 >+ 18904394U, // VABAuv8i16 >+ 19035466U, // VABAuv8i8 >+ 35153977U, // VABDLsv2i64 >+ 35285049U, // VABDLsv4i32 >+ 35416121U, // VABDLsv8i16 >+ 35547193U, // VABDLuv2i64 >+ 35678265U, // VABDLuv4i32 >+ 35809337U, // VABDLuv8i16 >+ 2249090750U, // VABDfd >+ 2249090750U, // VABDfq >+ 35415742U, // VABDsv16i8 >+ 35153598U, // VABDsv2i32 >+ 35284670U, // VABDsv4i16 >+ 35153598U, // VABDsv4i32 >+ 35284670U, // VABDsv8i16 >+ 35415742U, // VABDsv8i8 >+ 35808958U, // VABDuv16i8 >+ 35546814U, // VABDuv2i32 >+ 35677886U, // VABDuv4i16 >+ 35546814U, // VABDuv4i32 >+ 35677886U, // VABDuv8i16 >+ 35808958U, // VABDuv8i8 >+ 2248952268U, // VABSD >+ 2249083340U, // VABSS >+ 2249083340U, // VABSfd >+ 2249083340U, // VABSfq >+ 1109150156U, // VABSv16i8 >+ 1108888012U, // VABSv2i32 >+ 1109019084U, // VABSv4i16 >+ 1108888012U, // VABSv4i32 >+ 1109019084U, // VABSv8i16 >+ 1109150156U, // VABSv8i8 >+ 2249090864U, // VACGEd >+ 2249090864U, // VACGEq >+ 2249091667U, // VACGTd >+ 2249091667U, // VACGTq >+ 2248959714U, // VADDD >+ 35940565U, // VADDHNv2i32 >+ 36071637U, // VADDHNv4i16 >+ 36202709U, // VADDHNv8i8 >+ 35153990U, // VADDLsv2i64 >+ 35285062U, // VADDLsv4i32 >+ 35416134U, // VADDLsv8i16 >+ 35547206U, // VADDLuv2i64 >+ 35678278U, // VADDLuv4i32 >+ 35809350U, // VADDLuv8i16 >+ 2249090786U, // VADDS >+ 35154685U, // VADDWsv2i64 >+ 35285757U, // VADDWsv4i32 >+ 35416829U, // VADDWsv8i16 >+ 35547901U, // VADDWuv2i64 >+ 35678973U, // VADDWuv4i32 >+ 35810045U, // VADDWuv8i16 >+ 2249090786U, // VADDfd >+ 2249090786U, // VADDfq >+ 36333282U, // VADDv16i8 >+ 35940066U, // VADDv1i64 >+ 36071138U, // VADDv2i32 >+ 35940066U, // VADDv2i64 >+ 36202210U, // VADDv4i16 >+ 36071138U, // VADDv4i32 >+ 36202210U, // VADDv8i16 >+ 36333282U, // VADDv8i8 >+ 26361U, // VANDd >+ 26361U, // VANDq >+ 26260U, // VBICd >+ 237397652U, // VBICiv2i32 >+ 237528724U, // VBICiv4i16 >+ 237397652U, // VBICiv4i32 >+ 237528724U, // VBICiv8i16 >+ 26260U, // VBICq >+ 30549U, // VBIFd >+ 30549U, // VBIFq >+ 31350U, // VBITd >+ 31350U, // VBITq >+ 30856U, // VBSLd >+ 30856U, // VBSLq >+ 2249091426U, // VCEQfd >+ 2249091426U, // VCEQfq >+ 36333922U, // VCEQv16i8 >+ 36071778U, // VCEQv2i32 >+ 36202850U, // VCEQv4i16 >+ 36071778U, // VCEQv4i32 >+ 36202850U, // VCEQv8i16 >+ 36333922U, // VCEQv8i8 >+ 2183809378U, // VCEQzv16i8 >+ 2249083234U, // VCEQzv2f32 >+ 2183547234U, // VCEQzv2i32 >+ 2249083234U, // VCEQzv4f32 >+ 2183678306U, // VCEQzv4i16 >+ 2183547234U, // VCEQzv4i32 >+ 2183678306U, // VCEQzv8i16 >+ 2183809378U, // VCEQzv8i8 >+ 2249090870U, // VCGEfd >+ 2249090870U, // VCGEfq >+ 35415862U, // VCGEsv16i8 >+ 35153718U, // VCGEsv2i32 >+ 35284790U, // VCGEsv4i16 >+ 35153718U, // VCGEsv4i32 >+ 35284790U, // VCGEsv8i16 >+ 35415862U, // VCGEsv8i8 >+ 35809078U, // VCGEuv16i8 >+ 35546934U, // VCGEuv2i32 >+ 35678006U, // VCGEuv4i16 >+ 35546934U, // VCGEuv4i32 >+ 35678006U, // VCGEuv8i16 >+ 35809078U, // VCGEuv8i8 >+ 2182891318U, // VCGEzv16i8 >+ 2249082678U, // VCGEzv2f32 >+ 2182629174U, // VCGEzv2i32 >+ 2249082678U, // VCGEzv4f32 >+ 2182760246U, // VCGEzv4i16 >+ 2182629174U, // VCGEzv4i32 >+ 2182760246U, // VCGEzv8i16 >+ 2182891318U, // VCGEzv8i8 >+ 2249091673U, // VCGTfd >+ 2249091673U, // VCGTfq >+ 35416665U, // VCGTsv16i8 >+ 35154521U, // VCGTsv2i32 >+ 35285593U, // VCGTsv4i16 >+ 35154521U, // VCGTsv4i32 >+ 35285593U, // VCGTsv8i16 >+ 35416665U, // VCGTsv8i8 >+ 35809881U, // VCGTuv16i8 >+ 35547737U, // VCGTuv2i32 >+ 35678809U, // VCGTuv4i16 >+ 35547737U, // VCGTuv4i32 >+ 35678809U, // VCGTuv8i16 >+ 35809881U, // VCGTuv8i8 >+ 2182892121U, // VCGTzv16i8 >+ 2249083481U, // VCGTzv2f32 >+ 2182629977U, // VCGTzv2i32 >+ 2249083481U, // VCGTzv4f32 >+ 2182761049U, // VCGTzv4i16 >+ 2182629977U, // VCGTzv4i32 >+ 2182761049U, // VCGTzv8i16 >+ 2182892121U, // VCGTzv8i8 >+ 2182891323U, // VCLEzv16i8 >+ 2249082683U, // VCLEzv2f32 >+ 2182629179U, // VCLEzv2i32 >+ 2249082683U, // VCLEzv4f32 >+ 2182760251U, // VCLEzv4i16 >+ 2182629179U, // VCLEzv4i32 >+ 2182760251U, // VCLEzv8i16 >+ 2182891323U, // VCLEzv8i8 >+ 1109150166U, // VCLSv16i8 >+ 1108888022U, // VCLSv2i32 >+ 1109019094U, // VCLSv4i16 >+ 1108888022U, // VCLSv4i32 >+ 1109019094U, // VCLSv8i16 >+ 1109150166U, // VCLSv8i8 >+ 2182892155U, // VCLTzv16i8 >+ 2249083515U, // VCLTzv2f32 >+ 2182630011U, // VCLTzv2i32 >+ 2249083515U, // VCLTzv4f32 >+ 2182761083U, // VCLTzv4i16 >+ 2182630011U, // VCLTzv4i32 >+ 2182761083U, // VCLTzv8i16 >+ 2182892155U, // VCLTzv8i8 >+ 1110068184U, // VCLZv16i8 >+ 1109806040U, // VCLZv2i32 >+ 1109937112U, // VCLZv4i16 >+ 1109806040U, // VCLZv4i32 >+ 1109937112U, // VCLZv8i16 >+ 1110068184U, // VCLZv8i8 >+ 2248952138U, // VCMPD >+ 2248951623U, // VCMPED >+ 2249082695U, // VCMPES >+ 252479303U, // VCMPEZD >+ 252610375U, // VCMPEZS >+ 2249083210U, // VCMPS >+ 252479818U, // VCMPZD >+ 252610890U, // VCMPZS >+ 2902656U, // VCNTd >+ 2902656U, // VCNTq >+ 1107447926U, // VCVTANSD >+ 1107447926U, // VCVTANSQ >+ 1107447986U, // VCVTANUD >+ 1107447986U, // VCVTANUQ >+ 1107448234U, // VCVTASD >+ 1107447926U, // VCVTASS >+ 1107448294U, // VCVTAUD >+ 1107447986U, // VCVTAUS >+ 3032627U, // VCVTBDH >+ 3163699U, // VCVTBHD >+ 3294771U, // VCVTBHS >+ 3425843U, // VCVTBSH >+ 3558075U, // VCVTDS >+ 1107447941U, // VCVTMNSD >+ 1107447941U, // VCVTMNSQ >+ 1107448001U, // VCVTMNUD >+ 1107448001U, // VCVTMNUQ >+ 1107448249U, // VCVTMSD >+ 1107447941U, // VCVTMSS >+ 1107448309U, // VCVTMUD >+ 1107448001U, // VCVTMUS >+ 1107447956U, // VCVTNNSD >+ 1107447956U, // VCVTNNSQ >+ 1107448016U, // VCVTNNUD >+ 1107448016U, // VCVTNNUQ >+ 1107448264U, // VCVTNSD >+ 1107447956U, // VCVTNSS >+ 1107448324U, // VCVTNUD >+ 1107448016U, // VCVTNUS >+ 1107447971U, // VCVTPNSD >+ 1107447971U, // VCVTPNSQ >+ 1107448031U, // VCVTPNUD >+ 1107448031U, // VCVTPNUQ >+ 1107448279U, // VCVTPSD >+ 1107447971U, // VCVTPSS >+ 1107448339U, // VCVTPUD >+ 1107448031U, // VCVTPUS >+ 3689147U, // VCVTSD >+ 3033781U, // VCVTTDH >+ 3164853U, // VCVTTHD >+ 3295925U, // VCVTTHS >+ 3426997U, // VCVTTSH >+ 3427003U, // VCVTf2h >+ 272255675U, // VCVTf2sd >+ 272255675U, // VCVTf2sq >+ 272386747U, // VCVTf2ud >+ 272386747U, // VCVTf2uq >+ 3325717179U, // VCVTf2xsd >+ 3325717179U, // VCVTf2xsq >+ 3325848251U, // VCVTf2xud >+ 3325848251U, // VCVTf2xuq >+ 3295931U, // VCVTh2f >+ 272517819U, // VCVTs2fd >+ 272517819U, // VCVTs2fq >+ 272648891U, // VCVTu2fd >+ 272648891U, // VCVTu2fq >+ 3325979323U, // VCVTxs2fd >+ 3325979323U, // VCVTxs2fq >+ 3326110395U, // VCVTxu2fd >+ 3326110395U, // VCVTxu2fq >+ 2248960749U, // VDIVD >+ 2249091821U, // VDIVS >+ 4344147U, // VDUP16d >+ 4344147U, // VDUP16q >+ 4475219U, // VDUP32d >+ 4475219U, // VDUP32q >+ 2902355U, // VDUP8d >+ 2902355U, // VDUP8q >+ 4352339U, // VDUPLN16d >+ 4352339U, // VDUPLN16q >+ 4483411U, // VDUPLN32d >+ 4483411U, // VDUPLN32q >+ 2910547U, // VDUPLN8d >+ 2910547U, // VDUPLN8q >+ 27025U, // VEORd >+ 27025U, // VEORq >+ 4356819U, // VEXTd16 >+ 4487891U, // VEXTd32 >+ 2915027U, // VEXTd8 >+ 4356819U, // VEXTq16 >+ 4487891U, // VEXTq32 >+ 4618963U, // VEXTq64 >+ 2915027U, // VEXTq8 >+ 3322705290U, // VFMAD >+ 3322836362U, // VFMAS >+ 3322836362U, // VFMAfd >+ 3322836362U, // VFMAfq >+ 3322706412U, // VFMSD >+ 3322837484U, // VFMSS >+ 3322837484U, // VFMSfd >+ 3322837484U, // VFMSfq >+ 3322705295U, // VFNMAD >+ 3322836367U, // VFNMAS >+ 3322706417U, // VFNMSD >+ 3322837489U, // VFNMSS >+ 4483826U, // VGETLNi32 >+ 35285746U, // VGETLNs16 >+ 35416818U, // VGETLNs8 >+ 35678962U, // VGETLNu16 >+ 35810034U, // VGETLNu8 >+ 35415760U, // VHADDsv16i8 >+ 35153616U, // VHADDsv2i32 >+ 35284688U, // VHADDsv4i16 >+ 35153616U, // VHADDsv4i32 >+ 35284688U, // VHADDsv8i16 >+ 35415760U, // VHADDsv8i8 >+ 35808976U, // VHADDuv16i8 >+ 35546832U, // VHADDuv2i32 >+ 35677904U, // VHADDuv4i16 >+ 35546832U, // VHADDuv4i32 >+ 35677904U, // VHADDuv8i16 >+ 35808976U, // VHADDuv8i8 >+ 35415625U, // VHSUBsv16i8 >+ 35153481U, // VHSUBsv2i32 >+ 35284553U, // VHSUBsv4i16 >+ 35153481U, // VHSUBsv4i32 >+ 35284553U, // VHSUBsv8i16 >+ 35415625U, // VHSUBsv8i8 >+ 35808841U, // VHSUBuv16i8 >+ 35546697U, // VHSUBuv2i32 >+ 35677769U, // VHSUBuv4i16 >+ 35546697U, // VHSUBuv4i32 >+ 35677769U, // VHSUBuv8i16 >+ 35808841U, // VHSUBuv8i8 >+ 1363305442U, // VLD1DUPd16 >+ 2437051362U, // VLD1DUPd16wb_fixed >+ 2437088226U, // VLD1DUPd16wb_register >+ 1363436514U, // VLD1DUPd32 >+ 2437182434U, // VLD1DUPd32wb_fixed >+ 2437219298U, // VLD1DUPd32wb_register >+ 1361863650U, // VLD1DUPd8 >+ 2435609570U, // VLD1DUPd8wb_fixed >+ 2435646434U, // VLD1DUPd8wb_register >+ 1380082658U, // VLD1DUPq16 >+ 2453828578U, // VLD1DUPq16wb_fixed >+ 2453865442U, // VLD1DUPq16wb_register >+ 1380213730U, // VLD1DUPq32 >+ 2453959650U, // VLD1DUPq32wb_fixed >+ 2453996514U, // VLD1DUPq32wb_register >+ 1378640866U, // VLD1DUPq8 >+ 2452386786U, // VLD1DUPq8wb_fixed >+ 2452423650U, // VLD1DUPq8wb_register >+ 3226010594U, // VLD1LNd16 >+ 3226039266U, // VLD1LNd16_UPD >+ 3226141666U, // VLD1LNd32 >+ 3226170338U, // VLD1LNd32_UPD >+ 3226272738U, // VLD1LNd8 >+ 3226301410U, // VLD1LNd8_UPD >+ 4355042U, // VLD1LNdAsm_16 >+ 4486114U, // VLD1LNdAsm_32 >+ 2913250U, // VLD1LNdAsm_8 >+ 4355042U, // VLD1LNdWB_fixed_Asm_16 >+ 4486114U, // VLD1LNdWB_fixed_Asm_32 >+ 2913250U, // VLD1LNdWB_fixed_Asm_8 >+ 4391906U, // VLD1LNdWB_register_Asm_16 >+ 4522978U, // VLD1LNdWB_register_Asm_32 >+ 2950114U, // VLD1LNdWB_register_Asm_8 >+ 0U, // VLD1LNq16Pseudo >+ 0U, // VLD1LNq16Pseudo_UPD >+ 0U, // VLD1LNq32Pseudo >+ 0U, // VLD1LNq32Pseudo_UPD >+ 0U, // VLD1LNq8Pseudo >+ 0U, // VLD1LNq8Pseudo_UPD >+ 1396859874U, // VLD1d16 >+ 1413637090U, // VLD1d16Q >+ 2487383010U, // VLD1d16Qwb_fixed >+ 2487419874U, // VLD1d16Qwb_register >+ 1430414306U, // VLD1d16T >+ 2504160226U, // VLD1d16Twb_fixed >+ 2504197090U, // VLD1d16Twb_register >+ 2470605794U, // VLD1d16wb_fixed >+ 2470642658U, // VLD1d16wb_register >+ 1396990946U, // VLD1d32 >+ 1413768162U, // VLD1d32Q >+ 2487514082U, // VLD1d32Qwb_fixed >+ 2487550946U, // VLD1d32Qwb_register >+ 1430545378U, // VLD1d32T >+ 2504291298U, // VLD1d32Twb_fixed >+ 2504328162U, // VLD1d32Twb_register >+ 2470736866U, // VLD1d32wb_fixed >+ 2470773730U, // VLD1d32wb_register >+ 1397122018U, // VLD1d64 >+ 1413899234U, // VLD1d64Q >+ 0U, // VLD1d64QPseudo >+ 0U, // VLD1d64QPseudoWB_fixed >+ 0U, // VLD1d64QPseudoWB_register >+ 2487645154U, // VLD1d64Qwb_fixed >+ 2487682018U, // VLD1d64Qwb_register >+ 1430676450U, // VLD1d64T >+ 0U, // VLD1d64TPseudo >+ 0U, // VLD1d64TPseudoWB_fixed >+ 0U, // VLD1d64TPseudoWB_register >+ 2504422370U, // VLD1d64Twb_fixed >+ 2504459234U, // VLD1d64Twb_register >+ 2470867938U, // VLD1d64wb_fixed >+ 2470904802U, // VLD1d64wb_register >+ 1395418082U, // VLD1d8 >+ 1412195298U, // VLD1d8Q >+ 2485941218U, // VLD1d8Qwb_fixed >+ 2485978082U, // VLD1d8Qwb_register >+ 1428972514U, // VLD1d8T >+ 2502718434U, // VLD1d8Twb_fixed >+ 2502755298U, // VLD1d8Twb_register >+ 2469164002U, // VLD1d8wb_fixed >+ 2469200866U, // VLD1d8wb_register >+ 1447191522U, // VLD1q16 >+ 2520937442U, // VLD1q16wb_fixed >+ 2520974306U, // VLD1q16wb_register >+ 1447322594U, // VLD1q32 >+ 2521068514U, // VLD1q32wb_fixed >+ 2521105378U, // VLD1q32wb_register >+ 1447453666U, // VLD1q64 >+ 2521199586U, // VLD1q64wb_fixed >+ 2521236450U, // VLD1q64wb_register >+ 1445749730U, // VLD1q8 >+ 2519495650U, // VLD1q8wb_fixed >+ 2519532514U, // VLD1q8wb_register >+ 1380082702U, // VLD2DUPd16 >+ 2453828622U, // VLD2DUPd16wb_fixed >+ 2453865486U, // VLD2DUPd16wb_register >+ 1463968782U, // VLD2DUPd16x2 >+ 2537714702U, // VLD2DUPd16x2wb_fixed >+ 2537751566U, // VLD2DUPd16x2wb_register >+ 1380213774U, // VLD2DUPd32 >+ 2453959694U, // VLD2DUPd32wb_fixed >+ 2453996558U, // VLD2DUPd32wb_register >+ 1464099854U, // VLD2DUPd32x2 >+ 2537845774U, // VLD2DUPd32x2wb_fixed >+ 2537882638U, // VLD2DUPd32x2wb_register >+ 1378640910U, // VLD2DUPd8 >+ 2452386830U, // VLD2DUPd8wb_fixed >+ 2452423694U, // VLD2DUPd8wb_register >+ 1462526990U, // VLD2DUPd8x2 >+ 2536272910U, // VLD2DUPd8x2wb_fixed >+ 2536309774U, // VLD2DUPd8x2wb_register >+ 3226039310U, // VLD2LNd16 >+ 0U, // VLD2LNd16Pseudo >+ 0U, // VLD2LNd16Pseudo_UPD >+ 3226043406U, // VLD2LNd16_UPD >+ 3226170382U, // VLD2LNd32 >+ 0U, // VLD2LNd32Pseudo >+ 0U, // VLD2LNd32Pseudo_UPD >+ 3226174478U, // VLD2LNd32_UPD >+ 3226301454U, // VLD2LNd8 >+ 0U, // VLD2LNd8Pseudo >+ 0U, // VLD2LNd8Pseudo_UPD >+ 3226305550U, // VLD2LNd8_UPD >+ 4355086U, // VLD2LNdAsm_16 >+ 4486158U, // VLD2LNdAsm_32 >+ 2913294U, // VLD2LNdAsm_8 >+ 4355086U, // VLD2LNdWB_fixed_Asm_16 >+ 4486158U, // VLD2LNdWB_fixed_Asm_32 >+ 2913294U, // VLD2LNdWB_fixed_Asm_8 >+ 4391950U, // VLD2LNdWB_register_Asm_16 >+ 4523022U, // VLD2LNdWB_register_Asm_32 >+ 2950158U, // VLD2LNdWB_register_Asm_8 >+ 3226039310U, // VLD2LNq16 >+ 0U, // VLD2LNq16Pseudo >+ 0U, // VLD2LNq16Pseudo_UPD >+ 3226043406U, // VLD2LNq16_UPD >+ 3226170382U, // VLD2LNq32 >+ 0U, // VLD2LNq32Pseudo >+ 0U, // VLD2LNq32Pseudo_UPD >+ 3226174478U, // VLD2LNq32_UPD >+ 4355086U, // VLD2LNqAsm_16 >+ 4486158U, // VLD2LNqAsm_32 >+ 4355086U, // VLD2LNqWB_fixed_Asm_16 >+ 4486158U, // VLD2LNqWB_fixed_Asm_32 >+ 4391950U, // VLD2LNqWB_register_Asm_16 >+ 4523022U, // VLD2LNqWB_register_Asm_32 >+ 1480745998U, // VLD2b16 >+ 2554491918U, // VLD2b16wb_fixed >+ 2554528782U, // VLD2b16wb_register >+ 1480877070U, // VLD2b32 >+ 2554622990U, // VLD2b32wb_fixed >+ 2554659854U, // VLD2b32wb_register >+ 1479304206U, // VLD2b8 >+ 2553050126U, // VLD2b8wb_fixed >+ 2553086990U, // VLD2b8wb_register >+ 1447191566U, // VLD2d16 >+ 2520937486U, // VLD2d16wb_fixed >+ 2520974350U, // VLD2d16wb_register >+ 1447322638U, // VLD2d32 >+ 2521068558U, // VLD2d32wb_fixed >+ 2521105422U, // VLD2d32wb_register >+ 1445749774U, // VLD2d8 >+ 2519495694U, // VLD2d8wb_fixed >+ 2519532558U, // VLD2d8wb_register >+ 1413637134U, // VLD2q16 >+ 0U, // VLD2q16Pseudo >+ 0U, // VLD2q16PseudoWB_fixed >+ 0U, // VLD2q16PseudoWB_register >+ 2487383054U, // VLD2q16wb_fixed >+ 2487419918U, // VLD2q16wb_register >+ 1413768206U, // VLD2q32 >+ 0U, // VLD2q32Pseudo >+ 0U, // VLD2q32PseudoWB_fixed >+ 0U, // VLD2q32PseudoWB_register >+ 2487514126U, // VLD2q32wb_fixed >+ 2487550990U, // VLD2q32wb_register >+ 1412195342U, // VLD2q8 >+ 0U, // VLD2q8Pseudo >+ 0U, // VLD2q8PseudoWB_fixed >+ 0U, // VLD2q8PseudoWB_register >+ 2485941262U, // VLD2q8wb_fixed >+ 2485978126U, // VLD2q8wb_register >+ 4785198U, // VLD3DUPd16 >+ 0U, // VLD3DUPd16Pseudo >+ 0U, // VLD3DUPd16Pseudo_UPD >+ 4813870U, // VLD3DUPd16_UPD >+ 4916270U, // VLD3DUPd32 >+ 0U, // VLD3DUPd32Pseudo >+ 0U, // VLD3DUPd32Pseudo_UPD >+ 4944942U, // VLD3DUPd32_UPD >+ 5047342U, // VLD3DUPd8 >+ 0U, // VLD3DUPd8Pseudo >+ 0U, // VLD3DUPd8Pseudo_UPD >+ 5076014U, // VLD3DUPd8_UPD >+ 1497523246U, // VLD3DUPdAsm_16 >+ 1497654318U, // VLD3DUPdAsm_32 >+ 1496081454U, // VLD3DUPdAsm_8 >+ 1497523246U, // VLD3DUPdWB_fixed_Asm_16 >+ 1497654318U, // VLD3DUPdWB_fixed_Asm_32 >+ 1496081454U, // VLD3DUPdWB_fixed_Asm_8 >+ 423785518U, // VLD3DUPdWB_register_Asm_16 >+ 423916590U, // VLD3DUPdWB_register_Asm_32 >+ 422343726U, // VLD3DUPdWB_register_Asm_8 >+ 4785198U, // VLD3DUPq16 >+ 4813870U, // VLD3DUPq16_UPD >+ 4916270U, // VLD3DUPq32 >+ 4944942U, // VLD3DUPq32_UPD >+ 5047342U, // VLD3DUPq8 >+ 5076014U, // VLD3DUPq8_UPD >+ 1514300462U, // VLD3DUPqAsm_16 >+ 1514431534U, // VLD3DUPqAsm_32 >+ 1512858670U, // VLD3DUPqAsm_8 >+ 1514300462U, // VLD3DUPqWB_fixed_Asm_16 >+ 1514431534U, // VLD3DUPqWB_fixed_Asm_32 >+ 1512858670U, // VLD3DUPqWB_fixed_Asm_8 >+ 440562734U, // VLD3DUPqWB_register_Asm_16 >+ 440693806U, // VLD3DUPqWB_register_Asm_32 >+ 439120942U, // VLD3DUPqWB_register_Asm_8 >+ 3226043438U, // VLD3LNd16 >+ 0U, // VLD3LNd16Pseudo >+ 0U, // VLD3LNd16Pseudo_UPD >+ 3226047534U, // VLD3LNd16_UPD >+ 3226174510U, // VLD3LNd32 >+ 0U, // VLD3LNd32Pseudo >+ 0U, // VLD3LNd32Pseudo_UPD >+ 3226178606U, // VLD3LNd32_UPD >+ 3226305582U, // VLD3LNd8 >+ 0U, // VLD3LNd8Pseudo >+ 0U, // VLD3LNd8Pseudo_UPD >+ 3226309678U, // VLD3LNd8_UPD >+ 4355118U, // VLD3LNdAsm_16 >+ 4486190U, // VLD3LNdAsm_32 >+ 2913326U, // VLD3LNdAsm_8 >+ 4355118U, // VLD3LNdWB_fixed_Asm_16 >+ 4486190U, // VLD3LNdWB_fixed_Asm_32 >+ 2913326U, // VLD3LNdWB_fixed_Asm_8 >+ 4391982U, // VLD3LNdWB_register_Asm_16 >+ 4523054U, // VLD3LNdWB_register_Asm_32 >+ 2950190U, // VLD3LNdWB_register_Asm_8 >+ 3226043438U, // VLD3LNq16 >+ 0U, // VLD3LNq16Pseudo >+ 0U, // VLD3LNq16Pseudo_UPD >+ 3226047534U, // VLD3LNq16_UPD >+ 3226174510U, // VLD3LNq32 >+ 0U, // VLD3LNq32Pseudo >+ 0U, // VLD3LNq32Pseudo_UPD >+ 3226178606U, // VLD3LNq32_UPD >+ 4355118U, // VLD3LNqAsm_16 >+ 4486190U, // VLD3LNqAsm_32 >+ 4355118U, // VLD3LNqWB_fixed_Asm_16 >+ 4486190U, // VLD3LNqWB_fixed_Asm_32 >+ 4391982U, // VLD3LNqWB_register_Asm_16 >+ 4523054U, // VLD3LNqWB_register_Asm_32 >+ 4785198U, // VLD3d16 >+ 0U, // VLD3d16Pseudo >+ 0U, // VLD3d16Pseudo_UPD >+ 4813870U, // VLD3d16_UPD >+ 4916270U, // VLD3d32 >+ 0U, // VLD3d32Pseudo >+ 0U, // VLD3d32Pseudo_UPD >+ 4944942U, // VLD3d32_UPD >+ 5047342U, // VLD3d8 >+ 0U, // VLD3d8Pseudo >+ 0U, // VLD3d8Pseudo_UPD >+ 5076014U, // VLD3d8_UPD >+ 1430414382U, // VLD3dAsm_16 >+ 1430545454U, // VLD3dAsm_32 >+ 1428972590U, // VLD3dAsm_8 >+ 1430414382U, // VLD3dWB_fixed_Asm_16 >+ 1430545454U, // VLD3dWB_fixed_Asm_32 >+ 1428972590U, // VLD3dWB_fixed_Asm_8 >+ 1430418478U, // VLD3dWB_register_Asm_16 >+ 1430549550U, // VLD3dWB_register_Asm_32 >+ 1428976686U, // VLD3dWB_register_Asm_8 >+ 4785198U, // VLD3q16 >+ 0U, // VLD3q16Pseudo_UPD >+ 4813870U, // VLD3q16_UPD >+ 0U, // VLD3q16oddPseudo >+ 0U, // VLD3q16oddPseudo_UPD >+ 4916270U, // VLD3q32 >+ 0U, // VLD3q32Pseudo_UPD >+ 4944942U, // VLD3q32_UPD >+ 0U, // VLD3q32oddPseudo >+ 0U, // VLD3q32oddPseudo_UPD >+ 5047342U, // VLD3q8 >+ 0U, // VLD3q8Pseudo_UPD >+ 5076014U, // VLD3q8_UPD >+ 0U, // VLD3q8oddPseudo >+ 0U, // VLD3q8oddPseudo_UPD >+ 1531077678U, // VLD3qAsm_16 >+ 1531208750U, // VLD3qAsm_32 >+ 1529635886U, // VLD3qAsm_8 >+ 1531077678U, // VLD3qWB_fixed_Asm_16 >+ 1531208750U, // VLD3qWB_fixed_Asm_32 >+ 1529635886U, // VLD3qWB_fixed_Asm_8 >+ 457339950U, // VLD3qWB_register_Asm_16 >+ 457471022U, // VLD3qWB_register_Asm_32 >+ 455898158U, // VLD3qWB_register_Asm_8 >+ 4760645U, // VLD4DUPd16 >+ 0U, // VLD4DUPd16Pseudo >+ 0U, // VLD4DUPd16Pseudo_UPD >+ 4826181U, // VLD4DUPd16_UPD >+ 4891717U, // VLD4DUPd32 >+ 0U, // VLD4DUPd32Pseudo >+ 0U, // VLD4DUPd32Pseudo_UPD >+ 4957253U, // VLD4DUPd32_UPD >+ 5022789U, // VLD4DUPd8 >+ 0U, // VLD4DUPd8Pseudo >+ 0U, // VLD4DUPd8Pseudo_UPD >+ 5088325U, // VLD4DUPd8_UPD >+ 1547854917U, // VLD4DUPdAsm_16 >+ 1547985989U, // VLD4DUPdAsm_32 >+ 1546413125U, // VLD4DUPdAsm_8 >+ 1547854917U, // VLD4DUPdWB_fixed_Asm_16 >+ 1547985989U, // VLD4DUPdWB_fixed_Asm_32 >+ 1546413125U, // VLD4DUPdWB_fixed_Asm_8 >+ 474117189U, // VLD4DUPdWB_register_Asm_16 >+ 474248261U, // VLD4DUPdWB_register_Asm_32 >+ 472675397U, // VLD4DUPdWB_register_Asm_8 >+ 4760645U, // VLD4DUPq16 >+ 4826181U, // VLD4DUPq16_UPD >+ 4891717U, // VLD4DUPq32 >+ 4957253U, // VLD4DUPq32_UPD >+ 5022789U, // VLD4DUPq8 >+ 5088325U, // VLD4DUPq8_UPD >+ 1564632133U, // VLD4DUPqAsm_16 >+ 1564763205U, // VLD4DUPqAsm_32 >+ 1563190341U, // VLD4DUPqAsm_8 >+ 1564632133U, // VLD4DUPqWB_fixed_Asm_16 >+ 1564763205U, // VLD4DUPqWB_fixed_Asm_32 >+ 1563190341U, // VLD4DUPqWB_fixed_Asm_8 >+ 490894405U, // VLD4DUPqWB_register_Asm_16 >+ 491025477U, // VLD4DUPqWB_register_Asm_32 >+ 489452613U, // VLD4DUPqWB_register_Asm_8 >+ 3226047557U, // VLD4LNd16 >+ 0U, // VLD4LNd16Pseudo >+ 0U, // VLD4LNd16Pseudo_UPD >+ 3226055749U, // VLD4LNd16_UPD >+ 3226178629U, // VLD4LNd32 >+ 0U, // VLD4LNd32Pseudo >+ 0U, // VLD4LNd32Pseudo_UPD >+ 3226186821U, // VLD4LNd32_UPD >+ 3226309701U, // VLD4LNd8 >+ 0U, // VLD4LNd8Pseudo >+ 0U, // VLD4LNd8Pseudo_UPD >+ 3226317893U, // VLD4LNd8_UPD >+ 4355141U, // VLD4LNdAsm_16 >+ 4486213U, // VLD4LNdAsm_32 >+ 2913349U, // VLD4LNdAsm_8 >+ 4355141U, // VLD4LNdWB_fixed_Asm_16 >+ 4486213U, // VLD4LNdWB_fixed_Asm_32 >+ 2913349U, // VLD4LNdWB_fixed_Asm_8 >+ 4392005U, // VLD4LNdWB_register_Asm_16 >+ 4523077U, // VLD4LNdWB_register_Asm_32 >+ 2950213U, // VLD4LNdWB_register_Asm_8 >+ 3226047557U, // VLD4LNq16 >+ 0U, // VLD4LNq16Pseudo >+ 0U, // VLD4LNq16Pseudo_UPD >+ 3226055749U, // VLD4LNq16_UPD >+ 3226178629U, // VLD4LNq32 >+ 0U, // VLD4LNq32Pseudo >+ 0U, // VLD4LNq32Pseudo_UPD >+ 3226186821U, // VLD4LNq32_UPD >+ 4355141U, // VLD4LNqAsm_16 >+ 4486213U, // VLD4LNqAsm_32 >+ 4355141U, // VLD4LNqWB_fixed_Asm_16 >+ 4486213U, // VLD4LNqWB_fixed_Asm_32 >+ 4392005U, // VLD4LNqWB_register_Asm_16 >+ 4523077U, // VLD4LNqWB_register_Asm_32 >+ 4760645U, // VLD4d16 >+ 0U, // VLD4d16Pseudo >+ 0U, // VLD4d16Pseudo_UPD >+ 4826181U, // VLD4d16_UPD >+ 4891717U, // VLD4d32 >+ 0U, // VLD4d32Pseudo >+ 0U, // VLD4d32Pseudo_UPD >+ 4957253U, // VLD4d32_UPD >+ 5022789U, // VLD4d8 >+ 0U, // VLD4d8Pseudo >+ 0U, // VLD4d8Pseudo_UPD >+ 5088325U, // VLD4d8_UPD >+ 1413637189U, // VLD4dAsm_16 >+ 1413768261U, // VLD4dAsm_32 >+ 1412195397U, // VLD4dAsm_8 >+ 1413637189U, // VLD4dWB_fixed_Asm_16 >+ 1413768261U, // VLD4dWB_fixed_Asm_32 >+ 1412195397U, // VLD4dWB_fixed_Asm_8 >+ 1413641285U, // VLD4dWB_register_Asm_16 >+ 1413772357U, // VLD4dWB_register_Asm_32 >+ 1412199493U, // VLD4dWB_register_Asm_8 >+ 4760645U, // VLD4q16 >+ 0U, // VLD4q16Pseudo_UPD >+ 4826181U, // VLD4q16_UPD >+ 0U, // VLD4q16oddPseudo >+ 0U, // VLD4q16oddPseudo_UPD >+ 4891717U, // VLD4q32 >+ 0U, // VLD4q32Pseudo_UPD >+ 4957253U, // VLD4q32_UPD >+ 0U, // VLD4q32oddPseudo >+ 0U, // VLD4q32oddPseudo_UPD >+ 5022789U, // VLD4q8 >+ 0U, // VLD4q8Pseudo_UPD >+ 5088325U, // VLD4q8_UPD >+ 0U, // VLD4q8oddPseudo >+ 0U, // VLD4q8oddPseudo_UPD >+ 1581409349U, // VLD4qAsm_16 >+ 1581540421U, // VLD4qAsm_32 >+ 1579967557U, // VLD4qAsm_8 >+ 1581409349U, // VLD4qWB_fixed_Asm_16 >+ 1581540421U, // VLD4qWB_fixed_Asm_32 >+ 1579967557U, // VLD4qWB_fixed_Asm_8 >+ 507671621U, // VLD4qWB_register_Asm_16 >+ 507802693U, // VLD4qWB_register_Asm_32 >+ 506229829U, // VLD4qWB_register_Asm_8 >+ 33572305U, // VLDMDDB_UPD >+ 34149U, // VLDMDIA >+ 33572197U, // VLDMDIA_UPD >+ 0U, // VLDMQIA >+ 33572305U, // VLDMSDB_UPD >+ 34149U, // VLDMSIA >+ 33572197U, // VLDMSIA_UPD >+ 27002U, // VLDRD >+ 27002U, // VLDRS >+ 33706566U, // VMAXNMD >+ 33706258U, // VMAXNMND >+ 33706258U, // VMAXNMNQ >+ 33706258U, // VMAXNMS >+ 2249091875U, // VMAXfd >+ 2249091875U, // VMAXfq >+ 35416867U, // VMAXsv16i8 >+ 35154723U, // VMAXsv2i32 >+ 35285795U, // VMAXsv4i16 >+ 35154723U, // VMAXsv4i32 >+ 35285795U, // VMAXsv8i16 >+ 35416867U, // VMAXsv8i8 >+ 35810083U, // VMAXuv16i8 >+ 35547939U, // VMAXuv2i32 >+ 35679011U, // VMAXuv4i16 >+ 35547939U, // VMAXuv4i32 >+ 35679011U, // VMAXuv8i16 >+ 35810083U, // VMAXuv8i8 >+ 33706554U, // VMINNMD >+ 33706246U, // VMINNMND >+ 33706246U, // VMINNMNQ >+ 33706246U, // VMINNMS >+ 2249091298U, // VMINfd >+ 2249091298U, // VMINfq >+ 35416290U, // VMINsv16i8 >+ 35154146U, // VMINsv2i32 >+ 35285218U, // VMINsv4i16 >+ 35154146U, // VMINsv4i32 >+ 35285218U, // VMINsv8i16 >+ 35416290U, // VMINsv8i8 >+ 35809506U, // VMINuv16i8 >+ 35547362U, // VMINuv2i32 >+ 35678434U, // VMINuv4i16 >+ 35547362U, // VMINuv4i32 >+ 35678434U, // VMINuv8i16 >+ 35809506U, // VMINuv8i8 >+ 3322705285U, // VMLAD >+ 18417694U, // VMLALslsv2i32 >+ 18548766U, // VMLALslsv4i16 >+ 18810910U, // VMLALsluv2i32 >+ 18941982U, // VMLALsluv4i16 >+ 18380830U, // VMLALsv2i64 >+ 18511902U, // VMLALsv4i32 >+ 18642974U, // VMLALsv8i16 >+ 18774046U, // VMLALuv2i64 >+ 18905118U, // VMLALuv4i32 >+ 19036190U, // VMLALuv8i16 >+ 3322836357U, // VMLAS >+ 3322836357U, // VMLAfd >+ 3322836357U, // VMLAfq >+ 3322873221U, // VMLAslfd >+ 3322873221U, // VMLAslfq >+ 19334533U, // VMLAslv2i32 >+ 19465605U, // VMLAslv4i16 >+ 19334533U, // VMLAslv4i32 >+ 19465605U, // VMLAslv8i16 >+ 19559813U, // VMLAv16i8 >+ 19297669U, // VMLAv2i32 >+ 19428741U, // VMLAv4i16 >+ 19297669U, // VMLAv4i32 >+ 19428741U, // VMLAv8i16 >+ 19559813U, // VMLAv8i8 >+ 3322706407U, // VMLSD >+ 18417813U, // VMLSLslsv2i32 >+ 18548885U, // VMLSLslsv4i16 >+ 18811029U, // VMLSLsluv2i32 >+ 18942101U, // VMLSLsluv4i16 >+ 18380949U, // VMLSLsv2i64 >+ 18512021U, // VMLSLsv4i32 >+ 18643093U, // VMLSLsv8i16 >+ 18774165U, // VMLSLuv2i64 >+ 18905237U, // VMLSLuv4i32 >+ 19036309U, // VMLSLuv8i16 >+ 3322837479U, // VMLSS >+ 3322837479U, // VMLSfd >+ 3322837479U, // VMLSfq >+ 3322874343U, // VMLSslfd >+ 3322874343U, // VMLSslfq >+ 19335655U, // VMLSslv2i32 >+ 19466727U, // VMLSslv4i16 >+ 19335655U, // VMLSslv4i32 >+ 19466727U, // VMLSslv8i16 >+ 19560935U, // VMLSv16i8 >+ 19298791U, // VMLSv2i32 >+ 19429863U, // VMLSv4i16 >+ 19298791U, // VMLSv4i32 >+ 19429863U, // VMLSv8i16 >+ 19560935U, // VMLSv8i8 >+ 2248952562U, // VMOVD >+ 0U, // VMOVD0 >+ 27378U, // VMOVDRR >+ 0U, // VMOVDcc >+ 1108887728U, // VMOVLsv2i64 >+ 1109018800U, // VMOVLsv4i32 >+ 1109149872U, // VMOVLsv8i16 >+ 1109280944U, // VMOVLuv2i64 >+ 1109412016U, // VMOVLuv4i32 >+ 1109543088U, // VMOVLuv8i16 >+ 1109674294U, // VMOVNv2i32 >+ 1109805366U, // VMOVNv4i16 >+ 1109936438U, // VMOVNv8i8 >+ 0U, // VMOVQ0 >+ 27378U, // VMOVRRD >+ 31474U, // VMOVRRS >+ 19186U, // VMOVRS >+ 2249083634U, // VMOVS >+ 19186U, // VMOVSR >+ 31474U, // VMOVSRR >+ 0U, // VMOVScc >+ 237652722U, // VMOVv16i8 >+ 237259506U, // VMOVv1i64 >+ 3322825458U, // VMOVv2f32 >+ 237390578U, // VMOVv2i32 >+ 237259506U, // VMOVv2i64 >+ 3322825458U, // VMOVv4f32 >+ 237521650U, // VMOVv4i16 >+ 237390578U, // VMOVv4i32 >+ 237521650U, // VMOVv8i16 >+ 237652722U, // VMOVv8i8 >+ 2147518974U, // VMRS >+ 3221260798U, // VMRS_FPEXC >+ 35326U, // VMRS_FPINST >+ 1073777150U, // VMRS_FPINST2 >+ 2147518974U, // VMRS_FPSID >+ 3221260798U, // VMRS_MVFR0 >+ 35326U, // VMRS_MVFR1 >+ 1073777150U, // VMRS_MVFR2 >+ 5147055U, // VMSR >+ 5278127U, // VMSR_FPEXC >+ 5409199U, // VMSR_FPINST >+ 5540271U, // VMSR_FPINST2 >+ 5671343U, // VMSR_FPSID >+ 2248960171U, // VMULD >+ 33706650U, // VMULLp64 >+ 5793922U, // VMULLp8 >+ 35158146U, // VMULLslsv2i32 >+ 35289218U, // VMULLslsv4i16 >+ 35551362U, // VMULLsluv2i32 >+ 35682434U, // VMULLsluv4i16 >+ 35154050U, // VMULLsv2i64 >+ 35285122U, // VMULLsv4i32 >+ 35416194U, // VMULLsv8i16 >+ 35547266U, // VMULLuv2i64 >+ 35678338U, // VMULLuv4i32 >+ 35809410U, // VMULLuv8i16 >+ 2249091243U, // VMULS >+ 2249091243U, // VMULfd >+ 2249091243U, // VMULfq >+ 5793963U, // VMULpd >+ 5793963U, // VMULpq >+ 2249095339U, // VMULslfd >+ 2249095339U, // VMULslfq >+ 36075691U, // VMULslv2i32 >+ 36206763U, // VMULslv4i16 >+ 36075691U, // VMULslv4i32 >+ 36206763U, // VMULslv8i16 >+ 36333739U, // VMULv16i8 >+ 36071595U, // VMULv2i32 >+ 36202667U, // VMULv4i16 >+ 36071595U, // VMULv4i32 >+ 36202667U, // VMULv8i16 >+ 36333739U, // VMULv8i8 >+ 18730U, // VMVNd >+ 18730U, // VMVNq >+ 237390122U, // VMVNv2i32 >+ 237521194U, // VMVNv4i16 >+ 237390122U, // VMVNv4i32 >+ 237521194U, // VMVNv8i16 >+ 2248951652U, // VNEGD >+ 2249082724U, // VNEGS >+ 2249082724U, // VNEGf32q >+ 2249082724U, // VNEGfd >+ 1109018468U, // VNEGs16d >+ 1109018468U, // VNEGs16q >+ 1108887396U, // VNEGs32d >+ 1108887396U, // VNEGs32q >+ 1109149540U, // VNEGs8d >+ 1109149540U, // VNEGs8q >+ 3322705279U, // VNMLAD >+ 3322836351U, // VNMLAS >+ 3322706401U, // VNMLSD >+ 3322837473U, // VNMLSS >+ 2248960165U, // VNMULD >+ 2249091237U, // VNMULS >+ 26887U, // VORNd >+ 26887U, // VORNq >+ 27039U, // VORRd >+ 237398431U, // VORRiv2i32 >+ 237529503U, // VORRiv4i16 >+ 237398431U, // VORRiv4i32 >+ 237529503U, // VORRiv8i16 >+ 27039U, // VORRq >+ 1092380675U, // VPADALsv16i8 >+ 1092118531U, // VPADALsv2i32 >+ 1092249603U, // VPADALsv4i16 >+ 1092118531U, // VPADALsv4i32 >+ 1092249603U, // VPADALsv8i16 >+ 1092380675U, // VPADALsv8i8 >+ 1092773891U, // VPADALuv16i8 >+ 1092511747U, // VPADALuv2i32 >+ 1092642819U, // VPADALuv4i16 >+ 1092511747U, // VPADALuv4i32 >+ 1092642819U, // VPADALuv8i16 >+ 1092773891U, // VPADALuv8i8 >+ 1109149759U, // VPADDLsv16i8 >+ 1108887615U, // VPADDLsv2i32 >+ 1109018687U, // VPADDLsv4i16 >+ 1108887615U, // VPADDLsv4i32 >+ 1109018687U, // VPADDLsv8i16 >+ 1109149759U, // VPADDLsv8i8 >+ 1109542975U, // VPADDLuv16i8 >+ 1109280831U, // VPADDLuv2i32 >+ 1109411903U, // VPADDLuv4i16 >+ 1109280831U, // VPADDLuv4i32 >+ 1109411903U, // VPADDLuv8i16 >+ 1109542975U, // VPADDLuv8i8 >+ 2249090774U, // VPADDf >+ 36202198U, // VPADDi16 >+ 36071126U, // VPADDi32 >+ 36333270U, // VPADDi8 >+ 2249091869U, // VPMAXf >+ 35285789U, // VPMAXs16 >+ 35154717U, // VPMAXs32 >+ 35416861U, // VPMAXs8 >+ 35679005U, // VPMAXu16 >+ 35547933U, // VPMAXu32 >+ 35810077U, // VPMAXu8 >+ 2249091292U, // VPMINf >+ 35285212U, // VPMINs16 >+ 35154140U, // VPMINs32 >+ 35416284U, // VPMINs8 >+ 35678428U, // VPMINu16 >+ 35547356U, // VPMINu32 >+ 35809500U, // VPMINu8 >+ 1109150150U, // VQABSv16i8 >+ 1108888006U, // VQABSv2i32 >+ 1109019078U, // VQABSv4i16 >+ 1108888006U, // VQABSv4i32 >+ 1109019078U, // VQABSv8i16 >+ 1109150150U, // VQABSv8i8 >+ 35415772U, // VQADDsv16i8 >+ 39479004U, // VQADDsv1i64 >+ 35153628U, // VQADDsv2i32 >+ 39479004U, // VQADDsv2i64 >+ 35284700U, // VQADDsv4i16 >+ 35153628U, // VQADDsv4i32 >+ 35284700U, // VQADDsv8i16 >+ 35415772U, // VQADDsv8i8 >+ 35808988U, // VQADDuv16i8 >+ 39610076U, // VQADDuv1i64 >+ 35546844U, // VQADDuv2i32 >+ 39610076U, // VQADDuv2i64 >+ 35677916U, // VQADDuv4i16 >+ 35546844U, // VQADDuv4i32 >+ 35677916U, // VQADDuv8i16 >+ 35808988U, // VQADDuv8i8 >+ 18417674U, // VQDMLALslv2i32 >+ 18548746U, // VQDMLALslv4i16 >+ 18380810U, // VQDMLALv2i64 >+ 18511882U, // VQDMLALv4i32 >+ 18417805U, // VQDMLSLslv2i32 >+ 18548877U, // VQDMLSLslv4i16 >+ 18380941U, // VQDMLSLv2i64 >+ 18512013U, // VQDMLSLv4i32 >+ 35157891U, // VQDMULHslv2i32 >+ 35288963U, // VQDMULHslv4i16 >+ 35157891U, // VQDMULHslv4i32 >+ 35288963U, // VQDMULHslv8i16 >+ 35153795U, // VQDMULHv2i32 >+ 35284867U, // VQDMULHv4i16 >+ 35153795U, // VQDMULHv4i32 >+ 35284867U, // VQDMULHv8i16 >+ 35158126U, // VQDMULLslv2i32 >+ 35289198U, // VQDMULLslv4i16 >+ 35154030U, // VQDMULLv2i64 >+ 35285102U, // VQDMULLv4i32 >+ 1113213218U, // VQMOVNsuv2i32 >+ 1108887842U, // VQMOVNsuv4i16 >+ 1109018914U, // VQMOVNsuv8i8 >+ 1113213231U, // VQMOVNsv2i32 >+ 1108887855U, // VQMOVNsv4i16 >+ 1109018927U, // VQMOVNsv8i8 >+ 1113344303U, // VQMOVNuv2i32 >+ 1109281071U, // VQMOVNuv4i16 >+ 1109412143U, // VQMOVNuv8i8 >+ 1109149534U, // VQNEGv16i8 >+ 1108887390U, // VQNEGv2i32 >+ 1109018462U, // VQNEGv4i16 >+ 1108887390U, // VQNEGv4i32 >+ 1109018462U, // VQNEGv8i16 >+ 1109149534U, // VQNEGv8i8 >+ 35157899U, // VQRDMULHslv2i32 >+ 35288971U, // VQRDMULHslv4i16 >+ 35157899U, // VQRDMULHslv4i32 >+ 35288971U, // VQRDMULHslv8i16 >+ 35153803U, // VQRDMULHv2i32 >+ 35284875U, // VQRDMULHv4i16 >+ 35153803U, // VQRDMULHv4i32 >+ 35284875U, // VQRDMULHv8i16 >+ 35416150U, // VQRSHLsv16i8 >+ 39479382U, // VQRSHLsv1i64 >+ 35154006U, // VQRSHLsv2i32 >+ 39479382U, // VQRSHLsv2i64 >+ 35285078U, // VQRSHLsv4i16 >+ 35154006U, // VQRSHLsv4i32 >+ 35285078U, // VQRSHLsv8i16 >+ 35416150U, // VQRSHLsv8i8 >+ 35809366U, // VQRSHLuv16i8 >+ 39610454U, // VQRSHLuv1i64 >+ 35547222U, // VQRSHLuv2i32 >+ 39610454U, // VQRSHLuv2i64 >+ 35678294U, // VQRSHLuv4i16 >+ 35547222U, // VQRSHLuv4i32 >+ 35678294U, // VQRSHLuv8i16 >+ 35809366U, // VQRSHLuv8i8 >+ 39479538U, // VQRSHRNsv2i32 >+ 35154162U, // VQRSHRNsv4i16 >+ 35285234U, // VQRSHRNsv8i8 >+ 39610610U, // VQRSHRNuv2i32 >+ 35547378U, // VQRSHRNuv4i16 >+ 35678450U, // VQRSHRNuv8i8 >+ 39479577U, // VQRSHRUNv2i32 >+ 35154201U, // VQRSHRUNv4i16 >+ 35285273U, // VQRSHRUNv8i8 >+ 35416144U, // VQSHLsiv16i8 >+ 39479376U, // VQSHLsiv1i64 >+ 35154000U, // VQSHLsiv2i32 >+ 39479376U, // VQSHLsiv2i64 >+ 35285072U, // VQSHLsiv4i16 >+ 35154000U, // VQSHLsiv4i32 >+ 35285072U, // VQSHLsiv8i16 >+ 35416144U, // VQSHLsiv8i8 >+ 35416792U, // VQSHLsuv16i8 >+ 39480024U, // VQSHLsuv1i64 >+ 35154648U, // VQSHLsuv2i32 >+ 39480024U, // VQSHLsuv2i64 >+ 35285720U, // VQSHLsuv4i16 >+ 35154648U, // VQSHLsuv4i32 >+ 35285720U, // VQSHLsuv8i16 >+ 35416792U, // VQSHLsuv8i8 >+ 35416144U, // VQSHLsv16i8 >+ 39479376U, // VQSHLsv1i64 >+ 35154000U, // VQSHLsv2i32 >+ 39479376U, // VQSHLsv2i64 >+ 35285072U, // VQSHLsv4i16 >+ 35154000U, // VQSHLsv4i32 >+ 35285072U, // VQSHLsv8i16 >+ 35416144U, // VQSHLsv8i8 >+ 35809360U, // VQSHLuiv16i8 >+ 39610448U, // VQSHLuiv1i64 >+ 35547216U, // VQSHLuiv2i32 >+ 39610448U, // VQSHLuiv2i64 >+ 35678288U, // VQSHLuiv4i16 >+ 35547216U, // VQSHLuiv4i32 >+ 35678288U, // VQSHLuiv8i16 >+ 35809360U, // VQSHLuiv8i8 >+ 35809360U, // VQSHLuv16i8 >+ 39610448U, // VQSHLuv1i64 >+ 35547216U, // VQSHLuv2i32 >+ 39610448U, // VQSHLuv2i64 >+ 35678288U, // VQSHLuv4i16 >+ 35547216U, // VQSHLuv4i32 >+ 35678288U, // VQSHLuv8i16 >+ 35809360U, // VQSHLuv8i8 >+ 39479531U, // VQSHRNsv2i32 >+ 35154155U, // VQSHRNsv4i16 >+ 35285227U, // VQSHRNsv8i8 >+ 39610603U, // VQSHRNuv2i32 >+ 35547371U, // VQSHRNuv4i16 >+ 35678443U, // VQSHRNuv8i8 >+ 39479569U, // VQSHRUNv2i32 >+ 35154193U, // VQSHRUNv4i16 >+ 35285265U, // VQSHRUNv8i8 >+ 35415631U, // VQSUBsv16i8 >+ 39478863U, // VQSUBsv1i64 >+ 35153487U, // VQSUBsv2i32 >+ 39478863U, // VQSUBsv2i64 >+ 35284559U, // VQSUBsv4i16 >+ 35153487U, // VQSUBsv4i32 >+ 35284559U, // VQSUBsv8i16 >+ 35415631U, // VQSUBsv8i8 >+ 35808847U, // VQSUBuv16i8 >+ 39609935U, // VQSUBuv1i64 >+ 35546703U, // VQSUBuv2i32 >+ 39609935U, // VQSUBuv2i64 >+ 35677775U, // VQSUBuv4i16 >+ 35546703U, // VQSUBuv4i32 >+ 35677775U, // VQSUBuv8i16 >+ 35808847U, // VQSUBuv8i8 >+ 35940557U, // VRADDHNv2i32 >+ 36071629U, // VRADDHNv4i16 >+ 36202701U, // VRADDHNv8i8 >+ 1109280576U, // VRECPEd >+ 2249082688U, // VRECPEfd >+ 2249082688U, // VRECPEfq >+ 1109280576U, // VRECPEq >+ 2249091575U, // VRECPSfd >+ 2249091575U, // VRECPSfq >+ 2901191U, // VREV16d8 >+ 2901191U, // VREV16q8 >+ 4342770U, // VREV32d16 >+ 2900978U, // VREV32d8 >+ 4342770U, // VREV32q16 >+ 2900978U, // VREV32q8 >+ 4342846U, // VREV64d16 >+ 4473918U, // VREV64d32 >+ 2901054U, // VREV64d8 >+ 4342846U, // VREV64q16 >+ 4473918U, // VREV64q32 >+ 2901054U, // VREV64q8 >+ 35415753U, // VRHADDsv16i8 >+ 35153609U, // VRHADDsv2i32 >+ 35284681U, // VRHADDsv4i16 >+ 35153609U, // VRHADDsv4i32 >+ 35284681U, // VRHADDsv8i16 >+ 35415753U, // VRHADDsv8i8 >+ 35808969U, // VRHADDuv16i8 >+ 35546825U, // VRHADDuv2i32 >+ 35677897U, // VRHADDuv4i16 >+ 35546825U, // VRHADDuv4i32 >+ 35677897U, // VRHADDuv8i16 >+ 35808969U, // VRHADDuv8i8 >+ 1107448354U, // VRINTAD >+ 1107448046U, // VRINTAND >+ 1107448046U, // VRINTANQ >+ 1107448046U, // VRINTAS >+ 1107448402U, // VRINTMD >+ 1107448094U, // VRINTMND >+ 1107448094U, // VRINTMNQ >+ 1107448094U, // VRINTMS >+ 1107448414U, // VRINTND >+ 1107448106U, // VRINTNND >+ 1107448106U, // VRINTNNQ >+ 1107448106U, // VRINTNS >+ 1107448426U, // VRINTPD >+ 1107448118U, // VRINTPND >+ 1107448118U, // VRINTPNQ >+ 1107448118U, // VRINTPS >+ 2248952244U, // VRINTRD >+ 2249083316U, // VRINTRS >+ 2248952785U, // VRINTXD >+ 1107448166U, // VRINTXND >+ 1107448166U, // VRINTXNQ >+ 2249083857U, // VRINTXS >+ 2248952797U, // VRINTZD >+ 1107448178U, // VRINTZND >+ 1107448178U, // VRINTZNQ >+ 2249083869U, // VRINTZS >+ 35416157U, // VRSHLsv16i8 >+ 39479389U, // VRSHLsv1i64 >+ 35154013U, // VRSHLsv2i32 >+ 39479389U, // VRSHLsv2i64 >+ 35285085U, // VRSHLsv4i16 >+ 35154013U, // VRSHLsv4i32 >+ 35285085U, // VRSHLsv8i16 >+ 35416157U, // VRSHLsv8i8 >+ 35809373U, // VRSHLuv16i8 >+ 39610461U, // VRSHLuv1i64 >+ 35547229U, // VRSHLuv2i32 >+ 39610461U, // VRSHLuv2i64 >+ 35678301U, // VRSHLuv4i16 >+ 35547229U, // VRSHLuv4i32 >+ 35678301U, // VRSHLuv8i16 >+ 35809373U, // VRSHLuv8i8 >+ 35940602U, // VRSHRNv2i32 >+ 36071674U, // VRSHRNv4i16 >+ 36202746U, // VRSHRNv8i8 >+ 35416447U, // VRSHRsv16i8 >+ 39479679U, // VRSHRsv1i64 >+ 35154303U, // VRSHRsv2i32 >+ 39479679U, // VRSHRsv2i64 >+ 35285375U, // VRSHRsv4i16 >+ 35154303U, // VRSHRsv4i32 >+ 35285375U, // VRSHRsv8i16 >+ 35416447U, // VRSHRsv8i8 >+ 35809663U, // VRSHRuv16i8 >+ 39610751U, // VRSHRuv1i64 >+ 35547519U, // VRSHRuv2i32 >+ 39610751U, // VRSHRuv2i64 >+ 35678591U, // VRSHRuv4i16 >+ 35547519U, // VRSHRuv4i32 >+ 35678591U, // VRSHRuv8i16 >+ 35809663U, // VRSHRuv8i8 >+ 1109280589U, // VRSQRTEd >+ 2249082701U, // VRSQRTEfd >+ 2249082701U, // VRSQRTEfq >+ 1109280589U, // VRSQRTEq >+ 2249091597U, // VRSQRTSfd >+ 2249091597U, // VRSQRTSfq >+ 18642325U, // VRSRAsv16i8 >+ 22705557U, // VRSRAsv1i64 >+ 18380181U, // VRSRAsv2i32 >+ 22705557U, // VRSRAsv2i64 >+ 18511253U, // VRSRAsv4i16 >+ 18380181U, // VRSRAsv4i32 >+ 18511253U, // VRSRAsv8i16 >+ 18642325U, // VRSRAsv8i8 >+ 19035541U, // VRSRAuv16i8 >+ 22836629U, // VRSRAuv1i64 >+ 18773397U, // VRSRAuv2i32 >+ 22836629U, // VRSRAuv2i64 >+ 18904469U, // VRSRAuv4i16 >+ 18773397U, // VRSRAuv4i32 >+ 18904469U, // VRSRAuv8i16 >+ 19035541U, // VRSRAuv8i8 >+ 35940542U, // VRSUBHNv2i32 >+ 36071614U, // VRSUBHNv4i16 >+ 36202686U, // VRSUBHNv8i8 >+ 33706614U, // VSELEQD >+ 33706306U, // VSELEQS >+ 33706542U, // VSELGED >+ 33706234U, // VSELGES >+ 33706638U, // VSELGTD >+ 33706330U, // VSELGTS >+ 33706626U, // VSELVSD >+ 33706318U, // VSELVSS >+ 2151840498U, // VSETLNi16 >+ 2151971570U, // VSETLNi32 >+ 2150398706U, // VSETLNi8 >+ 36202600U, // VSHLLi16 >+ 36071528U, // VSHLLi32 >+ 36333672U, // VSHLLi8 >+ 35154024U, // VSHLLsv2i64 >+ 35285096U, // VSHLLsv4i32 >+ 35416168U, // VSHLLsv8i16 >+ 35547240U, // VSHLLuv2i64 >+ 35678312U, // VSHLLuv4i32 >+ 35809384U, // VSHLLuv8i16 >+ 36333667U, // VSHLiv16i8 >+ 35940451U, // VSHLiv1i64 >+ 36071523U, // VSHLiv2i32 >+ 35940451U, // VSHLiv2i64 >+ 36202595U, // VSHLiv4i16 >+ 36071523U, // VSHLiv4i32 >+ 36202595U, // VSHLiv8i16 >+ 36333667U, // VSHLiv8i8 >+ 35416163U, // VSHLsv16i8 >+ 39479395U, // VSHLsv1i64 >+ 35154019U, // VSHLsv2i32 >+ 39479395U, // VSHLsv2i64 >+ 35285091U, // VSHLsv4i16 >+ 35154019U, // VSHLsv4i32 >+ 35285091U, // VSHLsv8i16 >+ 35416163U, // VSHLsv8i8 >+ 35809379U, // VSHLuv16i8 >+ 39610467U, // VSHLuv1i64 >+ 35547235U, // VSHLuv2i32 >+ 39610467U, // VSHLuv2i64 >+ 35678307U, // VSHLuv4i16 >+ 35547235U, // VSHLuv4i32 >+ 35678307U, // VSHLuv8i16 >+ 35809379U, // VSHLuv8i8 >+ 35940609U, // VSHRNv2i32 >+ 36071681U, // VSHRNv4i16 >+ 36202753U, // VSHRNv8i8 >+ 35416453U, // VSHRsv16i8 >+ 39479685U, // VSHRsv1i64 >+ 35154309U, // VSHRsv2i32 >+ 39479685U, // VSHRsv2i64 >+ 35285381U, // VSHRsv4i16 >+ 35154309U, // VSHRsv4i32 >+ 35285381U, // VSHRsv8i16 >+ 35416453U, // VSHRsv8i8 >+ 35809669U, // VSHRuv16i8 >+ 39610757U, // VSHRuv1i64 >+ 35547525U, // VSHRuv2i32 >+ 39610757U, // VSHRuv2i64 >+ 35678597U, // VSHRuv4i16 >+ 35547525U, // VSHRuv4i32 >+ 35678597U, // VSHRuv8i16 >+ 35809669U, // VSHRuv8i8 >+ 6187707U, // VSHTOD >+ 6318779U, // VSHTOS >+ 274877115U, // VSITOD >+ 272517819U, // VSITOS >+ 2914269U, // VSLIv16i8 >+ 4618205U, // VSLIv1i64 >+ 4487133U, // VSLIv2i32 >+ 4618205U, // VSLIv2i64 >+ 4356061U, // VSLIv4i16 >+ 4487133U, // VSLIv4i32 >+ 4356061U, // VSLIv8i16 >+ 2914269U, // VSLIv8i8 >+ 3328338619U, // VSLTOD >+ 3325979323U, // VSLTOS >+ 2248952463U, // VSQRTD >+ 2249083535U, // VSQRTS >+ 18642331U, // VSRAsv16i8 >+ 22705563U, // VSRAsv1i64 >+ 18380187U, // VSRAsv2i32 >+ 22705563U, // VSRAsv2i64 >+ 18511259U, // VSRAsv4i16 >+ 18380187U, // VSRAsv4i32 >+ 18511259U, // VSRAsv8i16 >+ 18642331U, // VSRAsv8i8 >+ 19035547U, // VSRAuv16i8 >+ 22836635U, // VSRAuv1i64 >+ 18773403U, // VSRAuv2i32 >+ 22836635U, // VSRAuv2i64 >+ 18904475U, // VSRAuv4i16 >+ 18773403U, // VSRAuv4i32 >+ 18904475U, // VSRAuv8i16 >+ 19035547U, // VSRAuv8i8 >+ 2914274U, // VSRIv16i8 >+ 4618210U, // VSRIv1i64 >+ 4487138U, // VSRIv2i32 >+ 4618210U, // VSRIv2i64 >+ 4356066U, // VSRIv4i16 >+ 4487138U, // VSRIv4i32 >+ 4356066U, // VSRIv8i16 >+ 2914274U, // VSRIv8i8 >+ 3242750957U, // VST1LNd16 >+ 3746079725U, // VST1LNd16_UPD >+ 3242882029U, // VST1LNd32 >+ 3746210797U, // VST1LNd32_UPD >+ 3243013101U, // VST1LNd8 >+ 3746341869U, // VST1LNd8_UPD >+ 4355053U, // VST1LNdAsm_16 >+ 4486125U, // VST1LNdAsm_32 >+ 2913261U, // VST1LNdAsm_8 >+ 4355053U, // VST1LNdWB_fixed_Asm_16 >+ 4486125U, // VST1LNdWB_fixed_Asm_32 >+ 2913261U, // VST1LNdWB_fixed_Asm_8 >+ 4391917U, // VST1LNdWB_register_Asm_16 >+ 4522989U, // VST1LNdWB_register_Asm_32 >+ 2950125U, // VST1LNdWB_register_Asm_8 >+ 0U, // VST1LNq16Pseudo >+ 0U, // VST1LNq16Pseudo_UPD >+ 0U, // VST1LNq32Pseudo >+ 0U, // VST1LNq32Pseudo_UPD >+ 0U, // VST1LNq8Pseudo >+ 0U, // VST1LNq8Pseudo_UPD >+ 541221869U, // VST1d16 >+ 557999085U, // VST1d16Q >+ 574780397U, // VST1d16Qwb_fixed >+ 591594477U, // VST1d16Qwb_register >+ 608330733U, // VST1d16T >+ 625112045U, // VST1d16Twb_fixed >+ 641926125U, // VST1d16Twb_register >+ 658666477U, // VST1d16wb_fixed >+ 675480557U, // VST1d16wb_register >+ 541352941U, // VST1d32 >+ 558130157U, // VST1d32Q >+ 574911469U, // VST1d32Qwb_fixed >+ 591725549U, // VST1d32Qwb_register >+ 608461805U, // VST1d32T >+ 625243117U, // VST1d32Twb_fixed >+ 642057197U, // VST1d32Twb_register >+ 658797549U, // VST1d32wb_fixed >+ 675611629U, // VST1d32wb_register >+ 541484013U, // VST1d64 >+ 558261229U, // VST1d64Q >+ 0U, // VST1d64QPseudo >+ 0U, // VST1d64QPseudoWB_fixed >+ 0U, // VST1d64QPseudoWB_register >+ 575042541U, // VST1d64Qwb_fixed >+ 591856621U, // VST1d64Qwb_register >+ 608592877U, // VST1d64T >+ 0U, // VST1d64TPseudo >+ 0U, // VST1d64TPseudoWB_fixed >+ 0U, // VST1d64TPseudoWB_register >+ 625374189U, // VST1d64Twb_fixed >+ 642188269U, // VST1d64Twb_register >+ 658928621U, // VST1d64wb_fixed >+ 675742701U, // VST1d64wb_register >+ 539780077U, // VST1d8 >+ 556557293U, // VST1d8Q >+ 573338605U, // VST1d8Qwb_fixed >+ 590152685U, // VST1d8Qwb_register >+ 606888941U, // VST1d8T >+ 623670253U, // VST1d8Twb_fixed >+ 640484333U, // VST1d8Twb_register >+ 657224685U, // VST1d8wb_fixed >+ 674038765U, // VST1d8wb_register >+ 692216813U, // VST1q16 >+ 708998125U, // VST1q16wb_fixed >+ 725812205U, // VST1q16wb_register >+ 692347885U, // VST1q32 >+ 709129197U, // VST1q32wb_fixed >+ 725943277U, // VST1q32wb_register >+ 692478957U, // VST1q64 >+ 709260269U, // VST1q64wb_fixed >+ 726074349U, // VST1q64wb_register >+ 690775021U, // VST1q8 >+ 707556333U, // VST1q8wb_fixed >+ 724370413U, // VST1q8wb_register >+ 3242787881U, // VST2LNd16 >+ 0U, // VST2LNd16Pseudo >+ 0U, // VST2LNd16Pseudo_UPD >+ 3746133033U, // VST2LNd16_UPD >+ 3242918953U, // VST2LNd32 >+ 0U, // VST2LNd32Pseudo >+ 0U, // VST2LNd32Pseudo_UPD >+ 3746264105U, // VST2LNd32_UPD >+ 3243050025U, // VST2LNd8 >+ 0U, // VST2LNd8Pseudo >+ 0U, // VST2LNd8Pseudo_UPD >+ 3746395177U, // VST2LNd8_UPD >+ 4355113U, // VST2LNdAsm_16 >+ 4486185U, // VST2LNdAsm_32 >+ 2913321U, // VST2LNdAsm_8 >+ 4355113U, // VST2LNdWB_fixed_Asm_16 >+ 4486185U, // VST2LNdWB_fixed_Asm_32 >+ 2913321U, // VST2LNdWB_fixed_Asm_8 >+ 4391977U, // VST2LNdWB_register_Asm_16 >+ 4523049U, // VST2LNdWB_register_Asm_32 >+ 2950185U, // VST2LNdWB_register_Asm_8 >+ 3242787881U, // VST2LNq16 >+ 0U, // VST2LNq16Pseudo >+ 0U, // VST2LNq16Pseudo_UPD >+ 3746133033U, // VST2LNq16_UPD >+ 3242918953U, // VST2LNq32 >+ 0U, // VST2LNq32Pseudo >+ 0U, // VST2LNq32Pseudo_UPD >+ 3746264105U, // VST2LNq32_UPD >+ 4355113U, // VST2LNqAsm_16 >+ 4486185U, // VST2LNqAsm_32 >+ 4355113U, // VST2LNqWB_fixed_Asm_16 >+ 4486185U, // VST2LNqWB_fixed_Asm_32 >+ 4391977U, // VST2LNqWB_register_Asm_16 >+ 4523049U, // VST2LNqWB_register_Asm_32 >+ 742548521U, // VST2b16 >+ 759329833U, // VST2b16wb_fixed >+ 776143913U, // VST2b16wb_register >+ 742679593U, // VST2b32 >+ 759460905U, // VST2b32wb_fixed >+ 776274985U, // VST2b32wb_register >+ 741106729U, // VST2b8 >+ 757888041U, // VST2b8wb_fixed >+ 774702121U, // VST2b8wb_register >+ 692216873U, // VST2d16 >+ 708998185U, // VST2d16wb_fixed >+ 725812265U, // VST2d16wb_register >+ 692347945U, // VST2d32 >+ 709129257U, // VST2d32wb_fixed >+ 725943337U, // VST2d32wb_register >+ 690775081U, // VST2d8 >+ 707556393U, // VST2d8wb_fixed >+ 724370473U, // VST2d8wb_register >+ 557999145U, // VST2q16 >+ 0U, // VST2q16Pseudo >+ 0U, // VST2q16PseudoWB_fixed >+ 0U, // VST2q16PseudoWB_register >+ 574780457U, // VST2q16wb_fixed >+ 591594537U, // VST2q16wb_register >+ 558130217U, // VST2q32 >+ 0U, // VST2q32Pseudo >+ 0U, // VST2q32PseudoWB_fixed >+ 0U, // VST2q32PseudoWB_register >+ 574911529U, // VST2q32wb_fixed >+ 591725609U, // VST2q32wb_register >+ 556557353U, // VST2q8 >+ 0U, // VST2q8Pseudo >+ 0U, // VST2q8PseudoWB_fixed >+ 0U, // VST2q8PseudoWB_register >+ 573338665U, // VST2q8wb_fixed >+ 590152745U, // VST2q8wb_register >+ 3242763321U, // VST3LNd16 >+ 0U, // VST3LNd16Pseudo >+ 0U, // VST3LNd16Pseudo_UPD >+ 3746145337U, // VST3LNd16_UPD >+ 3242894393U, // VST3LNd32 >+ 0U, // VST3LNd32Pseudo >+ 0U, // VST3LNd32Pseudo_UPD >+ 3746276409U, // VST3LNd32_UPD >+ 3243025465U, // VST3LNd8 >+ 0U, // VST3LNd8Pseudo >+ 0U, // VST3LNd8Pseudo_UPD >+ 3746407481U, // VST3LNd8_UPD >+ 4355129U, // VST3LNdAsm_16 >+ 4486201U, // VST3LNdAsm_32 >+ 2913337U, // VST3LNdAsm_8 >+ 4355129U, // VST3LNdWB_fixed_Asm_16 >+ 4486201U, // VST3LNdWB_fixed_Asm_32 >+ 2913337U, // VST3LNdWB_fixed_Asm_8 >+ 4391993U, // VST3LNdWB_register_Asm_16 >+ 4523065U, // VST3LNdWB_register_Asm_32 >+ 2950201U, // VST3LNdWB_register_Asm_8 >+ 3242763321U, // VST3LNq16 >+ 0U, // VST3LNq16Pseudo >+ 0U, // VST3LNq16Pseudo_UPD >+ 3746145337U, // VST3LNq16_UPD >+ 3242894393U, // VST3LNq32 >+ 0U, // VST3LNq32Pseudo >+ 0U, // VST3LNq32Pseudo_UPD >+ 3746276409U, // VST3LNq32_UPD >+ 4355129U, // VST3LNqAsm_16 >+ 4486201U, // VST3LNqAsm_32 >+ 4355129U, // VST3LNqWB_fixed_Asm_16 >+ 4486201U, // VST3LNqWB_fixed_Asm_32 >+ 4391993U, // VST3LNqWB_register_Asm_16 >+ 4523065U, // VST3LNqWB_register_Asm_32 >+ 21562425U, // VST3d16 >+ 0U, // VST3d16Pseudo >+ 0U, // VST3d16Pseudo_UPD >+ 524907577U, // VST3d16_UPD >+ 21693497U, // VST3d32 >+ 0U, // VST3d32Pseudo >+ 0U, // VST3d32Pseudo_UPD >+ 525038649U, // VST3d32_UPD >+ 21824569U, // VST3d8 >+ 0U, // VST3d8Pseudo >+ 0U, // VST3d8Pseudo_UPD >+ 525169721U, // VST3d8_UPD >+ 1430414393U, // VST3dAsm_16 >+ 1430545465U, // VST3dAsm_32 >+ 1428972601U, // VST3dAsm_8 >+ 1430414393U, // VST3dWB_fixed_Asm_16 >+ 1430545465U, // VST3dWB_fixed_Asm_32 >+ 1428972601U, // VST3dWB_fixed_Asm_8 >+ 1430418489U, // VST3dWB_register_Asm_16 >+ 1430549561U, // VST3dWB_register_Asm_32 >+ 1428976697U, // VST3dWB_register_Asm_8 >+ 21562425U, // VST3q16 >+ 0U, // VST3q16Pseudo_UPD >+ 524907577U, // VST3q16_UPD >+ 0U, // VST3q16oddPseudo >+ 0U, // VST3q16oddPseudo_UPD >+ 21693497U, // VST3q32 >+ 0U, // VST3q32Pseudo_UPD >+ 525038649U, // VST3q32_UPD >+ 0U, // VST3q32oddPseudo >+ 0U, // VST3q32oddPseudo_UPD >+ 21824569U, // VST3q8 >+ 0U, // VST3q8Pseudo_UPD >+ 525169721U, // VST3q8_UPD >+ 0U, // VST3q8oddPseudo >+ 0U, // VST3q8oddPseudo_UPD >+ 1531077689U, // VST3qAsm_16 >+ 1531208761U, // VST3qAsm_32 >+ 1529635897U, // VST3qAsm_8 >+ 1531077689U, // VST3qWB_fixed_Asm_16 >+ 1531208761U, // VST3qWB_fixed_Asm_32 >+ 1529635897U, // VST3qWB_fixed_Asm_8 >+ 457339961U, // VST3qWB_register_Asm_16 >+ 457471033U, // VST3qWB_register_Asm_32 >+ 455898169U, // VST3qWB_register_Asm_8 >+ 3242816586U, // VST4LNd16 >+ 0U, // VST4LNd16Pseudo >+ 0U, // VST4LNd16Pseudo_UPD >+ 3746137162U, // VST4LNd16_UPD >+ 3242947658U, // VST4LNd32 >+ 0U, // VST4LNd32Pseudo >+ 0U, // VST4LNd32Pseudo_UPD >+ 3746268234U, // VST4LNd32_UPD >+ 3243078730U, // VST4LNd8 >+ 0U, // VST4LNd8Pseudo >+ 0U, // VST4LNd8Pseudo_UPD >+ 3746399306U, // VST4LNd8_UPD >+ 4355146U, // VST4LNdAsm_16 >+ 4486218U, // VST4LNdAsm_32 >+ 2913354U, // VST4LNdAsm_8 >+ 4355146U, // VST4LNdWB_fixed_Asm_16 >+ 4486218U, // VST4LNdWB_fixed_Asm_32 >+ 2913354U, // VST4LNdWB_fixed_Asm_8 >+ 4392010U, // VST4LNdWB_register_Asm_16 >+ 4523082U, // VST4LNdWB_register_Asm_32 >+ 2950218U, // VST4LNdWB_register_Asm_8 >+ 3242816586U, // VST4LNq16 >+ 0U, // VST4LNq16Pseudo >+ 0U, // VST4LNq16Pseudo_UPD >+ 3746137162U, // VST4LNq16_UPD >+ 3242947658U, // VST4LNq32 >+ 0U, // VST4LNq32Pseudo >+ 0U, // VST4LNq32Pseudo_UPD >+ 3746268234U, // VST4LNq32_UPD >+ 4355146U, // VST4LNqAsm_16 >+ 4486218U, // VST4LNqAsm_32 >+ 4355146U, // VST4LNqWB_fixed_Asm_16 >+ 4486218U, // VST4LNqWB_fixed_Asm_32 >+ 4392010U, // VST4LNqWB_register_Asm_16 >+ 4523082U, // VST4LNqWB_register_Asm_32 >+ 21537866U, // VST4d16 >+ 0U, // VST4d16Pseudo >+ 0U, // VST4d16Pseudo_UPD >+ 524919882U, // VST4d16_UPD >+ 21668938U, // VST4d32 >+ 0U, // VST4d32Pseudo >+ 0U, // VST4d32Pseudo_UPD >+ 525050954U, // VST4d32_UPD >+ 21800010U, // VST4d8 >+ 0U, // VST4d8Pseudo >+ 0U, // VST4d8Pseudo_UPD >+ 525182026U, // VST4d8_UPD >+ 1413637194U, // VST4dAsm_16 >+ 1413768266U, // VST4dAsm_32 >+ 1412195402U, // VST4dAsm_8 >+ 1413637194U, // VST4dWB_fixed_Asm_16 >+ 1413768266U, // VST4dWB_fixed_Asm_32 >+ 1412195402U, // VST4dWB_fixed_Asm_8 >+ 1413641290U, // VST4dWB_register_Asm_16 >+ 1413772362U, // VST4dWB_register_Asm_32 >+ 1412199498U, // VST4dWB_register_Asm_8 >+ 21537866U, // VST4q16 >+ 0U, // VST4q16Pseudo_UPD >+ 524919882U, // VST4q16_UPD >+ 0U, // VST4q16oddPseudo >+ 0U, // VST4q16oddPseudo_UPD >+ 21668938U, // VST4q32 >+ 0U, // VST4q32Pseudo_UPD >+ 525050954U, // VST4q32_UPD >+ 0U, // VST4q32oddPseudo >+ 0U, // VST4q32oddPseudo_UPD >+ 21800010U, // VST4q8 >+ 0U, // VST4q8Pseudo_UPD >+ 525182026U, // VST4q8_UPD >+ 0U, // VST4q8oddPseudo >+ 0U, // VST4q8oddPseudo_UPD >+ 1581409354U, // VST4qAsm_16 >+ 1581540426U, // VST4qAsm_32 >+ 1579967562U, // VST4qAsm_8 >+ 1581409354U, // VST4qWB_fixed_Asm_16 >+ 1581540426U, // VST4qWB_fixed_Asm_32 >+ 1579967562U, // VST4qWB_fixed_Asm_8 >+ 507671626U, // VST4qWB_register_Asm_16 >+ 507802698U, // VST4qWB_register_Asm_32 >+ 506229834U, // VST4qWB_register_Asm_8 >+ 33572312U, // VSTMDDB_UPD >+ 34156U, // VSTMDIA >+ 33572204U, // VSTMDIA_UPD >+ 0U, // VSTMQIA >+ 33572312U, // VSTMSDB_UPD >+ 34156U, // VSTMSIA >+ 33572204U, // VSTMSIA_UPD >+ 27067U, // VSTRD >+ 27067U, // VSTRS >+ 2248959573U, // VSUBD >+ 35940550U, // VSUBHNv2i32 >+ 36071622U, // VSUBHNv4i16 >+ 36202694U, // VSUBHNv8i8 >+ 35153961U, // VSUBLsv2i64 >+ 35285033U, // VSUBLsv4i32 >+ 35416105U, // VSUBLsv8i16 >+ 35547177U, // VSUBLuv2i64 >+ 35678249U, // VSUBLuv4i32 >+ 35809321U, // VSUBLuv8i16 >+ 2249090645U, // VSUBS >+ 35154679U, // VSUBWsv2i64 >+ 35285751U, // VSUBWsv4i32 >+ 35416823U, // VSUBWsv8i16 >+ 35547895U, // VSUBWuv2i64 >+ 35678967U, // VSUBWuv4i32 >+ 35810039U, // VSUBWuv8i16 >+ 2249090645U, // VSUBfd >+ 2249090645U, // VSUBfq >+ 36333141U, // VSUBv16i8 >+ 35939925U, // VSUBv1i64 >+ 36070997U, // VSUBv2i32 >+ 35939925U, // VSUBv2i64 >+ 36202069U, // VSUBv4i16 >+ 36070997U, // VSUBv4i32 >+ 36202069U, // VSUBv8i16 >+ 36333141U, // VSUBv8i8 >+ 31064U, // VSWPd >+ 31064U, // VSWPq >+ 2910244U, // VTBL1 >+ 2910244U, // VTBL2 >+ 2910244U, // VTBL3 >+ 0U, // VTBL3Pseudo >+ 2910244U, // VTBL4 >+ 0U, // VTBL4Pseudo >+ 2915156U, // VTBX1 >+ 2915156U, // VTBX2 >+ 2915156U, // VTBX3 >+ 0U, // VTBX3Pseudo >+ 2915156U, // VTBX4 >+ 0U, // VTBX4Pseudo >+ 6580923U, // VTOSHD >+ 6711995U, // VTOSHS >+ 275270080U, // VTOSIRD >+ 272255424U, // VTOSIRS >+ 275270331U, // VTOSIZD >+ 272255675U, // VTOSIZS >+ 3328731835U, // VTOSLD >+ 3325717179U, // VTOSLS >+ 6974139U, // VTOUHD >+ 7105211U, // VTOUHS >+ 275663296U, // VTOUIRD >+ 272386496U, // VTOUIRS >+ 275663547U, // VTOUIZD >+ 272386747U, // VTOUIZS >+ 3329125051U, // VTOULD >+ 3325848251U, // VTOULS >+ 4356364U, // VTRNd16 >+ 4487436U, // VTRNd32 >+ 2914572U, // VTRNd8 >+ 4356364U, // VTRNq16 >+ 4487436U, // VTRNq32 >+ 2914572U, // VTRNq8 >+ 2910874U, // VTSTv16i8 >+ 4483738U, // VTSTv2i32 >+ 4352666U, // VTSTv4i16 >+ 4483738U, // VTSTv4i32 >+ 4352666U, // VTSTv8i16 >+ 2910874U, // VTSTv8i8 >+ 7367355U, // VUHTOD >+ 7498427U, // VUHTOS >+ 276056763U, // VUITOD >+ 272648891U, // VUITOS >+ 3329518267U, // VULTOD >+ 3326110395U, // VULTOS >+ 4356445U, // VUZPd16 >+ 2914653U, // VUZPd8 >+ 4356445U, // VUZPq16 >+ 4487517U, // VUZPq32 >+ 2914653U, // VUZPq8 >+ 4356421U, // VZIPd16 >+ 2914629U, // VZIPd8 >+ 4356421U, // VZIPq16 >+ 4487493U, // VZIPq32 >+ 2914629U, // VZIPq8 >+ 0U, // WIN__CHKSTK >+ 34131U, // sysLDMDA >+ 33572179U, // sysLDMDA_UPD >+ 34258U, // sysLDMDB >+ 33572306U, // sysLDMDB_UPD >+ 34998U, // sysLDMIA >+ 33573046U, // sysLDMIA_UPD >+ 34277U, // sysLDMIB >+ 33572325U, // sysLDMIB_UPD >+ 34137U, // sysSTMDA >+ 33572185U, // sysSTMDA_UPD >+ 34265U, // sysSTMDB >+ 33572313U, // sysSTMDB_UPD >+ 35002U, // sysSTMIA >+ 33573050U, // sysSTMIA_UPD >+ 34283U, // sysSTMIB >+ 33572331U, // sysSTMIB_UPD >+ 0U, // t2ABS >+ 5768U, // t2ADCri >+ 7739016U, // t2ADCrr >+ 7743112U, // t2ADCrs >+ 0U, // t2ADDSri >+ 0U, // t2ADDSrr >+ 0U, // t2ADDSrs >+ 7739077U, // t2ADDri >+ 27390U, // t2ADDri12 >+ 7739077U, // t2ADDrr >+ 7743173U, // t2ADDrs >+ 7752054U, // t2ADR >+ 5882U, // t2ANDri >+ 7739130U, // t2ANDrr >+ 7743226U, // t2ANDrs >+ 7739812U, // t2ASRri >+ 7739812U, // t2ASRrr >+ 1081509283U, // t2B >+ 26256U, // t2BFC >+ 30677U, // t2BFI >+ 5781U, // t2BICri >+ 7739029U, // t2BICrr >+ 7743125U, // t2BICrs >+ 0U, // t2BR_JT >+ 1073776615U, // t2BXJ >+ 1081509283U, // t2Bcc >+ 2197858625U, // t2CDP >+ 2197857299U, // t2CDP2 >+ 433047U, // t2CLREX >+ 19417U, // t2CLZ >+ 7751911U, // t2CMNri >+ 7751911U, // t2CMNzrr >+ 7760103U, // t2CMNzrs >+ 7752011U, // t2CMPri >+ 7752011U, // t2CMPrr >+ 7760203U, // t2CMPrs >+ 414526U, // t2CPS1p >+ 1165412858U, // t2CPS2p >+ 83937786U, // t2CPS3p >+ 33706710U, // t2CRC32B >+ 33706718U, // t2CRC32CB >+ 33706782U, // t2CRC32CH >+ 33706851U, // t2CRC32CW >+ 33706774U, // t2CRC32H >+ 33706843U, // t2CRC32W >+ 1073776474U, // t2DBG >+ 431079U, // t2DCPS1 >+ 431139U, // t2DCPS2 >+ 431155U, // t2DCPS3 >+ 788563446U, // t2DMB >+ 788563465U, // t2DSB >+ 6546U, // t2EORri >+ 7739794U, // t2EORrr >+ 7743890U, // t2EORrs >+ 1081510533U, // t2HINT >+ 805340685U, // t2ISB >+ 117504627U, // t2IT >+ 0U, // t2Int_eh_sjlj_setjmp >+ 0U, // t2Int_eh_sjlj_setjmp_nofp >+ 17743U, // t2LDA >+ 17824U, // t2LDAB >+ 19333U, // t2LDAEX >+ 18024U, // t2LDAEXB >+ 26388U, // t2LDAEXD >+ 18361U, // t2LDAEXH >+ 18281U, // t2LDAH >+ 3271587819U, // t2LDC2L_OFFSET >+ 3271587819U, // t2LDC2L_OPTION >+ 3271587819U, // t2LDC2L_POST >+ 3271587819U, // t2LDC2L_PRE >+ 3271586809U, // t2LDC2_OFFSET >+ 3271586809U, // t2LDC2_OPTION >+ 3271586809U, // t2LDC2_POST >+ 3271586809U, // t2LDC2_PRE >+ 3271587887U, // t2LDCL_OFFSET >+ 3271587887U, // t2LDCL_OPTION >+ 3271587887U, // t2LDCL_POST >+ 3271587887U, // t2LDCL_PRE >+ 3271587468U, // t2LDC_OFFSET >+ 3271587468U, // t2LDC_OPTION >+ 3271587468U, // t2LDC_POST >+ 3271587468U, // t2LDC_PRE >+ 34258U, // t2LDMDB >+ 33572306U, // t2LDMDB_UPD >+ 7768246U, // t2LDMIA >+ 0U, // t2LDMIA_RET >+ 41306294U, // t2LDMIA_UPD >+ 27200U, // t2LDRBT >+ 30207U, // t2LDRB_POST >+ 30207U, // t2LDRB_PRE >+ 7759359U, // t2LDRBi12 >+ 26111U, // t2LDRBi8 >+ 7751167U, // t2LDRBpci >+ 280063U, // t2LDRBpcrel >+ 7763455U, // t2LDRBs >+ 67326U, // t2LDRD_POST >+ 67326U, // t2LDRD_PRE >+ 30462U, // t2LDRDi8 >+ 27537U, // t2LDREX >+ 18038U, // t2LDREXB >+ 26402U, // t2LDREXD >+ 18375U, // t2LDREXH >+ 27230U, // t2LDRHT >+ 30612U, // t2LDRH_POST >+ 30612U, // t2LDRH_PRE >+ 7759764U, // t2LDRHi12 >+ 26516U, // t2LDRHi8 >+ 7751572U, // t2LDRHpci >+ 280468U, // t2LDRHpcrel >+ 7763860U, // t2LDRHs >+ 27212U, // t2LDRSBT >+ 30225U, // t2LDRSB_POST >+ 30225U, // t2LDRSB_PRE >+ 7759377U, // t2LDRSBi12 >+ 26129U, // t2LDRSBi8 >+ 7751185U, // t2LDRSBpci >+ 280081U, // t2LDRSBpcrel >+ 7763473U, // t2LDRSBs >+ 27242U, // t2LDRSHT >+ 30622U, // t2LDRSH_POST >+ 30622U, // t2LDRSH_PRE >+ 7759774U, // t2LDRSHi12 >+ 26526U, // t2LDRSHi8 >+ 7751582U, // t2LDRSHpci >+ 280478U, // t2LDRSHpcrel >+ 7763870U, // t2LDRSHs >+ 27274U, // t2LDRT >+ 31099U, // t2LDR_POST >+ 31099U, // t2LDR_PRE >+ 7760251U, // t2LDRi12 >+ 27003U, // t2LDRi8 >+ 7752059U, // t2LDRpci >+ 0U, // t2LDRpci_pic >+ 280955U, // t2LDRpcrel >+ 7764347U, // t2LDRs >+ 0U, // t2LEApcrel >+ 0U, // t2LEApcrelJT >+ 7739537U, // t2LSLri >+ 7739537U, // t2LSLrr >+ 7739819U, // t2LSRri >+ 7739819U, // t2LSRrr >+ 2197858674U, // t2MCR >+ 2197857304U, // t2MCR2 >+ 2197883290U, // t2MCRR >+ 2197881885U, // t2MCRR2 >+ 30075U, // t2MLA >+ 31197U, // t2MLS >+ 0U, // t2MOVCCasr >+ 0U, // t2MOVCCi >+ 0U, // t2MOVCCi16 >+ 0U, // t2MOVCCi32imm >+ 0U, // t2MOVCClsl >+ 0U, // t2MOVCClsr >+ 0U, // t2MOVCCr >+ 0U, // t2MOVCCror >+ 289301U, // t2MOVSsi >+ 293397U, // t2MOVSsr >+ 27328U, // t2MOVTi16 >+ 0U, // t2MOVTi16_ga_pcrel >+ 0U, // t2MOV_ga_pcrel >+ 7805683U, // t2MOVi >+ 19208U, // t2MOVi16 >+ 0U, // t2MOVi16_ga_pcrel >+ 0U, // t2MOVi32imm >+ 7805683U, // t2MOVr >+ 289523U, // t2MOVsi >+ 293619U, // t2MOVsr >+ 7752195U, // t2MOVsra_flag >+ 7752200U, // t2MOVsrl_flag >+ 201369245U, // t2MRC >+ 201368574U, // t2MRC2 >+ 2197882529U, // t2MRRC >+ 2197881859U, // t2MRRC2 >+ 35327U, // t2MRS_AR >+ 18943U, // t2MRS_M >+ 1073777151U, // t2MRSsys_AR >+ 218122672U, // t2MSR_AR >+ 218122672U, // t2MSR_M >+ 26785U, // t2MUL >+ 0U, // t2MVNCCi >+ 71979U, // t2MVNi >+ 7805227U, // t2MVNr >+ 7739691U, // t2MVNs >+ 6408U, // t2ORNri >+ 6408U, // t2ORNrr >+ 10504U, // t2ORNrs >+ 6560U, // t2ORRri >+ 7739808U, // t2ORRrr >+ 7743904U, // t2ORRrs >+ 31275U, // t2PKHBT >+ 30238U, // t2PKHTB >+ 822102787U, // t2PLDWi12 >+ 838880003U, // t2PLDWi8 >+ 855665411U, // t2PLDWs >+ 822101742U, // t2PLDi12 >+ 838878958U, // t2PLDi8 >+ 872449774U, // t2PLDpci >+ 855664366U, // t2PLDs >+ 822101977U, // t2PLIi12 >+ 838879193U, // t2PLIi8 >+ 872450009U, // t2PLIpci >+ 855664601U, // t2PLIs >+ 26333U, // t2QADD >+ 25764U, // t2QADD16 >+ 25867U, // t2QADD8 >+ 27586U, // t2QASX >+ 26307U, // t2QDADD >+ 26179U, // t2QDSUB >+ 27445U, // t2QSAX >+ 26192U, // t2QSUB >+ 25726U, // t2QSUB16 >+ 25828U, // t2QSUB8 >+ 19057U, // t2RBIT >+ 7752415U, // t2REV >+ 7750856U, // t2REV16 >+ 7751593U, // t2REVSH >+ 1073776075U, // t2RFEDB >+ 1073776075U, // t2RFEDBW >+ 1073775967U, // t2RFEIA >+ 1073775967U, // t2RFEIAW >+ 7739798U, // t2RORri >+ 7739798U, // t2RORrr >+ 72625U, // t2RRX >+ 0U, // t2RSBSri >+ 0U, // t2RSBSrs >+ 7738899U, // t2RSBri >+ 5651U, // t2RSBrr >+ 9747U, // t2RSBrs >+ 25771U, // t2SADD16 >+ 25873U, // t2SADD8 >+ 27591U, // t2SASX >+ 5764U, // t2SBCri >+ 7739012U, // t2SBCrr >+ 7743108U, // t2SBCrs >+ 31651U, // t2SBFX >+ 27363U, // t2SDIV >+ 26700U, // t2SEL >+ 25747U, // t2SHADD16 >+ 25852U, // t2SHADD8 >+ 27573U, // t2SHASX >+ 27432U, // t2SHSAX >+ 25709U, // t2SHSUB16 >+ 25813U, // t2SHSUB8 >+ 1073776281U, // t2SMC >+ 30129U, // t2SMLABB >+ 31268U, // t2SMLABT >+ 30386U, // t2SMLAD >+ 31577U, // t2SMLADX >+ 43026U, // t2SMLAL >+ 30136U, // t2SMLALBB >+ 31281U, // t2SMLALBT >+ 30439U, // t2SMLALD >+ 31591U, // t2SMLALDX >+ 30244U, // t2SMLALTB >+ 31398U, // t2SMLALTT >+ 30231U, // t2SMLATB >+ 31391U, // t2SMLATT >+ 30298U, // t2SMLAWB >+ 31429U, // t2SMLAWT >+ 30472U, // t2SMLSD >+ 31607U, // t2SMLSDX >+ 30450U, // t2SMLSLD >+ 31599U, // t2SMLSLDX >+ 30073U, // t2SMMLA >+ 31083U, // t2SMMLAR >+ 31195U, // t2SMMLS >+ 31144U, // t2SMMLSR >+ 26783U, // t2SMMUL >+ 27018U, // t2SMMULR >+ 26296U, // t2SMUAD >+ 27488U, // t2SMUADX >+ 26048U, // t2SMULBB >+ 27193U, // t2SMULBT >+ 30838U, // t2SMULL >+ 26156U, // t2SMULTB >+ 27310U, // t2SMULTT >+ 26209U, // t2SMULWB >+ 27340U, // t2SMULWT >+ 26382U, // t2SMUSD >+ 27518U, // t2SMUSDX >+ 7898591U, // t2SRSDB >+ 8029663U, // t2SRSDB_UPD >+ 7898483U, // t2SRSIA >+ 8029555U, // t2SRSIA_UPD >+ 31258U, // t2SSAT >+ 25785U, // t2SSAT16 >+ 27450U, // t2SSAX >+ 25733U, // t2SSUB16 >+ 25834U, // t2SSUB8 >+ 3271587825U, // t2STC2L_OFFSET >+ 3271587825U, // t2STC2L_OPTION >+ 3271587825U, // t2STC2L_POST >+ 3271587825U, // t2STC2L_PRE >+ 3271586825U, // t2STC2_OFFSET >+ 3271586825U, // t2STC2_OPTION >+ 3271586825U, // t2STC2_POST >+ 3271586825U, // t2STC2_PRE >+ 3271587892U, // t2STCL_OFFSET >+ 3271587892U, // t2STCL_OPTION >+ 3271587892U, // t2STCL_POST >+ 3271587892U, // t2STCL_PRE >+ 3271587498U, // t2STC_OFFSET >+ 3271587498U, // t2STC_OPTION >+ 3271587498U, // t2STC_POST >+ 3271587498U, // t2STC_PRE >+ 18587U, // t2STL >+ 17905U, // t2STLB >+ 27531U, // t2STLEX >+ 26223U, // t2STLEXB >+ 30491U, // t2STLEXD >+ 26560U, // t2STLEXH >+ 18302U, // t2STLH >+ 34265U, // t2STMDB >+ 33572313U, // t2STMDB_UPD >+ 7768250U, // t2STMIA >+ 41306298U, // t2STMIA_UPD >+ 27206U, // t2STRBT >+ 33584644U, // t2STRB_POST >+ 33584644U, // t2STRB_PRE >+ 0U, // t2STRB_preidx >+ 7759364U, // t2STRBi12 >+ 26116U, // t2STRBi8 >+ 7763460U, // t2STRBs >+ 33621763U, // t2STRD_POST >+ 33621763U, // t2STRD_PRE >+ 30467U, // t2STRDi8 >+ 31645U, // t2STREX >+ 26237U, // t2STREXB >+ 30505U, // t2STREXD >+ 26574U, // t2STREXH >+ 27236U, // t2STRHT >+ 33585049U, // t2STRH_POST >+ 33585049U, // t2STRH_PRE >+ 0U, // t2STRH_preidx >+ 7759769U, // t2STRHi12 >+ 26521U, // t2STRHi8 >+ 7763865U, // t2STRHs >+ 27285U, // t2STRT >+ 33585596U, // t2STR_POST >+ 33585596U, // t2STR_PRE >+ 0U, // t2STR_preidx >+ 7760316U, // t2STRi12 >+ 27068U, // t2STRi8 >+ 7764412U, // t2STRs >+ 8161745U, // t2SUBS_PC_LR >+ 0U, // t2SUBSri >+ 0U, // t2SUBSrr >+ 0U, // t2SUBSrs >+ 7738949U, // t2SUBri >+ 27384U, // t2SUBri12 >+ 7738949U, // t2SUBrr >+ 7743045U, // t2SUBrs >+ 30117U, // t2SXTAB >+ 29775U, // t2SXTAB16 >+ 30574U, // t2SXTAH >+ 7759417U, // t2SXTB >+ 25695U, // t2SXTB16 >+ 7759791U, // t2SXTH >+ 889210311U, // t2TBB >+ 0U, // t2TBB_JT >+ 905987962U, // t2TBH >+ 0U, // t2TBH_JT >+ 7752039U, // t2TEQri >+ 7752039U, // t2TEQrr >+ 7760231U, // t2TEQrs >+ 7752347U, // t2TSTri >+ 7752347U, // t2TSTrr >+ 7760539U, // t2TSTrs >+ 25778U, // t2UADD16 >+ 25879U, // t2UADD8 >+ 27596U, // t2UASX >+ 31656U, // t2UBFX >+ 414548U, // t2UDF >+ 27368U, // t2UDIV >+ 25755U, // t2UHADD16 >+ 25859U, // t2UHADD8 >+ 27579U, // t2UHASX >+ 27438U, // t2UHSAX >+ 25717U, // t2UHSUB16 >+ 25820U, // t2UHSUB8 >+ 30711U, // t2UMAAL >+ 43032U, // t2UMLAL >+ 30844U, // t2UMULL >+ 25763U, // t2UQADD16 >+ 25866U, // t2UQADD8 >+ 27585U, // t2UQASX >+ 27444U, // t2UQSAX >+ 25725U, // t2UQSUB16 >+ 25827U, // t2UQSUB8 >+ 25846U, // t2USAD8 >+ 29902U, // t2USADA8 >+ 31263U, // t2USAT >+ 25792U, // t2USAT16 >+ 27455U, // t2USAX >+ 25740U, // t2USUB16 >+ 25840U, // t2USUB8 >+ 30123U, // t2UXTAB >+ 29783U, // t2UXTAB16 >+ 30580U, // t2UXTAH >+ 7759422U, // t2UXTB >+ 25702U, // t2UXTB16 >+ 7759796U, // t2UXTH >+ 931120776U, // tADC >+ 26309U, // tADDhirr >+ 25151173U, // tADDi3 >+ 931120837U, // tADDi8 >+ 26309U, // tADDrSP >+ 26309U, // tADDrSPi >+ 25151173U, // tADDrr >+ 26309U, // tADDspi >+ 26309U, // tADDspr >+ 0U, // tADJCALLSTACKDOWN >+ 0U, // tADJCALLSTACKUP >+ 18806U, // tADR >+ 931120890U, // tAND >+ 25151908U, // tASRri >+ 931121572U, // tASRrr >+ 1073776035U, // tB >+ 931120789U, // tBIC >+ 414542U, // tBKPT >+ 1090557990U, // tBL >+ 1090558893U, // tBLXi >+ 1090558893U, // tBLXr >+ 0U, // tBRIND >+ 0U, // tBR_JTr >+ 1073777481U, // tBX >+ 0U, // tBX_CALL >+ 0U, // tBX_RET >+ 0U, // tBX_RET_vararg >+ 1073776035U, // tBcc >+ 0U, // tBfar >+ 1107448704U, // tCBNZ >+ 1107448699U, // tCBZ >+ 18663U, // tCMNz >+ 18763U, // tCMPhir >+ 18763U, // tCMPi8 >+ 18763U, // tCMPr >+ 1157941754U, // tCPS >+ 931121554U, // tEOR >+ 1073777285U, // tHINT >+ 414537U, // tHLT >+ 0U, // tInt_eh_sjlj_longjmp >+ 0U, // tInt_eh_sjlj_setjmp >+ 34998U, // tLDMIA >+ 0U, // tLDMIA_UPD >+ 26111U, // tLDRBi >+ 26111U, // tLDRBr >+ 26516U, // tLDRHi >+ 26516U, // tLDRHr >+ 0U, // tLDRLIT_ga_abs >+ 0U, // tLDRLIT_ga_pcrel >+ 26129U, // tLDRSB >+ 26526U, // tLDRSH >+ 27003U, // tLDRi >+ 18811U, // tLDRpci >+ 0U, // tLDRpci_pic >+ 27003U, // tLDRr >+ 27003U, // tLDRspi >+ 0U, // tLEApcrel >+ 0U, // tLEApcrelJT >+ 25151633U, // tLSLri >+ 931121297U, // tLSLrr >+ 25151915U, // tLSRri >+ 931121579U, // tLSRrr >+ 0U, // tMOVCCr_pseudo >+ 1107448643U, // tMOVSr >+ 276941555U, // tMOVi8 >+ 19187U, // tMOVr >+ 25151649U, // tMUL >+ 276941099U, // tMVN >+ 931121568U, // tORR >+ 0U, // tPICADD >+ 939563343U, // tPOP >+ 0U, // tPOP_RET >+ 939562916U, // tPUSH >+ 19167U, // tREV >+ 17608U, // tREV16 >+ 18345U, // tREVSH >+ 931121558U, // tROR >+ 260163091U, // tRSB >+ 931120772U, // tSBC >+ 86793U, // tSETEND >+ 33573050U, // tSTMIA_UPD >+ 26116U, // tSTRBi >+ 26116U, // tSTRBr >+ 26521U, // tSTRHi >+ 26521U, // tSTRHr >+ 27068U, // tSTRi >+ 27068U, // tSTRr >+ 27068U, // tSTRspi >+ 25151045U, // tSUBi3 >+ 931120709U, // tSUBi8 >+ 25151045U, // tSUBrr >+ 26181U, // tSUBspi >+ 1073776302U, // tSVC >+ 17977U, // tSXTB >+ 18351U, // tSXTH >+ 0U, // tTAILJMPd >+ 0U, // tTAILJMPdND >+ 0U, // tTAILJMPr >+ 0U, // tTPsoft >+ 2364U, // tTRAP >+ 19099U, // tTST >+ 414481U, // tUDF >+ 17982U, // tUXTB >+ 18356U, // tUXTH >+ 0U >+ }; >+ >+ static const uint32_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // ABS >+ 0U, // ADCri >+ 0U, // ADCrr >+ 16384U, // ADCrsi >+ 0U, // ADCrsr >+ 0U, // ADDSri >+ 0U, // ADDSrr >+ 0U, // ADDSrsi >+ 0U, // ADDSrsr >+ 0U, // ADDri >+ 0U, // ADDrr >+ 16384U, // ADDrsi >+ 0U, // ADDrsr >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 8U, // ADR >+ 0U, // AESD >+ 0U, // AESE >+ 0U, // AESIMC >+ 0U, // AESMC >+ 0U, // ANDri >+ 0U, // ANDrr >+ 16384U, // ANDrsi >+ 0U, // ANDrsr >+ 0U, // ASRi >+ 0U, // ASRr >+ 0U, // B >+ 0U, // BCCZi64 >+ 0U, // BCCi64 >+ 16U, // BFC >+ 32792U, // BFI >+ 0U, // BICri >+ 0U, // BICrr >+ 16384U, // BICrsi >+ 0U, // BICrsr >+ 0U, // BKPT >+ 0U, // BL >+ 0U, // BLX >+ 0U, // BLX_pred >+ 0U, // BLXi >+ 0U, // BL_pred >+ 0U, // BMOVPCB_CALL >+ 0U, // BMOVPCRX_CALL >+ 0U, // BR_JTadd >+ 0U, // BR_JTm >+ 0U, // BR_JTr >+ 0U, // BX >+ 0U, // BXJ >+ 0U, // BX_CALL >+ 0U, // BX_RET >+ 0U, // BX_pred >+ 0U, // Bcc >+ 544U, // CDP >+ 0U, // CDP2 >+ 0U, // CLREX >+ 1024U, // CLZ >+ 1024U, // CMNri >+ 1024U, // CMNzrr >+ 40U, // CMNzrsi >+ 48U, // CMNzrsr >+ 1024U, // CMPri >+ 1024U, // CMPrr >+ 40U, // CMPrsi >+ 48U, // CMPrsr >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_STRUCT_BYVAL_I32 >+ 0U, // CPS1p >+ 0U, // CPS2p >+ 1048U, // CPS3p >+ 1048U, // CRC32B >+ 1048U, // CRC32CB >+ 1048U, // CRC32CH >+ 1048U, // CRC32CW >+ 1048U, // CRC32H >+ 1048U, // CRC32W >+ 0U, // DBG >+ 0U, // DMB >+ 0U, // DSB >+ 0U, // EORri >+ 0U, // EORrr >+ 16384U, // EORrsi >+ 0U, // EORrsr >+ 0U, // FCONSTD >+ 0U, // FCONSTS >+ 57U, // FLDMXDB_UPD >+ 1088U, // FLDMXIA >+ 57U, // FLDMXIA_UPD >+ 0U, // FMSTAT >+ 57U, // FSTMXDB_UPD >+ 1088U, // FSTMXIA >+ 57U, // FSTMXIA_UPD >+ 0U, // HINT >+ 0U, // HLT >+ 0U, // ISB >+ 0U, // ITasm >+ 0U, // Int_eh_sjlj_dispatchsetup >+ 0U, // Int_eh_sjlj_longjmp >+ 0U, // Int_eh_sjlj_setjmp >+ 0U, // Int_eh_sjlj_setjmp_nofp >+ 72U, // LDA >+ 72U, // LDAB >+ 72U, // LDAEX >+ 72U, // LDAEXB >+ 0U, // LDAEXD >+ 72U, // LDAEXH >+ 72U, // LDAH >+ 0U, // LDC2L_OFFSET >+ 1U, // LDC2L_OPTION >+ 1U, // LDC2L_POST >+ 0U, // LDC2L_PRE >+ 0U, // LDC2_OFFSET >+ 1U, // LDC2_OPTION >+ 1U, // LDC2_POST >+ 0U, // LDC2_PRE >+ 81U, // LDCL_OFFSET >+ 49241U, // LDCL_OPTION >+ 65625U, // LDCL_POST >+ 97U, // LDCL_PRE >+ 81U, // LDC_OFFSET >+ 49241U, // LDC_OPTION >+ 65625U, // LDC_POST >+ 97U, // LDC_PRE >+ 1088U, // LDMDA >+ 57U, // LDMDA_UPD >+ 1088U, // LDMDB >+ 57U, // LDMDB_UPD >+ 1088U, // LDMIA >+ 0U, // LDMIA_RET >+ 57U, // LDMIA_UPD >+ 1088U, // LDMIB >+ 57U, // LDMIB_UPD >+ 72U, // LDRBT_POST >+ 82008U, // LDRBT_POST_IMM >+ 82008U, // LDRBT_POST_REG >+ 82008U, // LDRB_POST_IMM >+ 82008U, // LDRB_POST_REG >+ 104U, // LDRB_PRE_IMM >+ 112U, // LDRB_PRE_REG >+ 120U, // LDRBi12 >+ 128U, // LDRBrs >+ 98304U, // LDRD >+ 1163264U, // LDRD_POST >+ 131072U, // LDRD_PRE >+ 72U, // LDREX >+ 72U, // LDREXB >+ 0U, // LDREXD >+ 72U, // LDREXH >+ 136U, // LDRH >+ 147544U, // LDRHTi >+ 163928U, // LDRHTr >+ 180312U, // LDRH_POST >+ 144U, // LDRH_PRE >+ 0U, // LDRLIT_ga_abs >+ 0U, // LDRLIT_ga_pcrel >+ 0U, // LDRLIT_ga_pcrel_ldr >+ 136U, // LDRSB >+ 147544U, // LDRSBTi >+ 163928U, // LDRSBTr >+ 180312U, // LDRSB_POST >+ 144U, // LDRSB_PRE >+ 136U, // LDRSH >+ 147544U, // LDRSHTi >+ 163928U, // LDRSHTr >+ 180312U, // LDRSH_POST >+ 144U, // LDRSH_PRE >+ 72U, // LDRT_POST >+ 82008U, // LDRT_POST_IMM >+ 82008U, // LDRT_POST_REG >+ 82008U, // LDR_POST_IMM >+ 82008U, // LDR_POST_REG >+ 104U, // LDR_PRE_IMM >+ 112U, // LDR_PRE_REG >+ 120U, // LDRcp >+ 120U, // LDRi12 >+ 128U, // LDRrs >+ 0U, // LEApcrel >+ 0U, // LEApcrelJT >+ 0U, // LSLi >+ 0U, // LSLr >+ 0U, // LSRi >+ 0U, // LSRr >+ 2295328U, // MCR >+ 152U, // MCR2 >+ 3343904U, // MCRR >+ 213152U, // MCRR2 >+ 17825792U, // MLA >+ 0U, // MLAv5 >+ 17825792U, // MLS >+ 0U, // MOVCCi >+ 0U, // MOVCCi16 >+ 0U, // MOVCCi32imm >+ 0U, // MOVCCr >+ 0U, // MOVCCsi >+ 0U, // MOVCCsr >+ 0U, // MOVPCLR >+ 0U, // MOVPCRX >+ 1048U, // MOVTi16 >+ 0U, // MOVTi16_ga_pcrel >+ 0U, // MOV_ga_pcrel >+ 0U, // MOV_ga_pcrel_ldr >+ 1024U, // MOVi >+ 1024U, // MOVi16 >+ 0U, // MOVi16_ga_pcrel >+ 0U, // MOVi32imm >+ 1024U, // MOVr >+ 1024U, // MOVr_TC >+ 40U, // MOVsi >+ 48U, // MOVsr >+ 0U, // MOVsra_flag >+ 0U, // MOVsrl_flag >+ 0U, // MRC >+ 0U, // MRC2 >+ 3343904U, // MRRC >+ 213152U, // MRRC2 >+ 2U, // MRS >+ 2U, // MRSsys >+ 0U, // MSR >+ 0U, // MSRi >+ 0U, // MUL >+ 0U, // MULv5 >+ 0U, // MVNCCi >+ 1024U, // MVNi >+ 1024U, // MVNr >+ 40U, // MVNsi >+ 48U, // MVNsr >+ 0U, // ORRri >+ 0U, // ORRrr >+ 16384U, // ORRrsi >+ 0U, // ORRrsr >+ 0U, // PICADD >+ 0U, // PICLDR >+ 0U, // PICLDRB >+ 0U, // PICLDRH >+ 0U, // PICLDRSB >+ 0U, // PICLDRSH >+ 0U, // PICSTR >+ 0U, // PICSTRB >+ 0U, // PICSTRH >+ 4194304U, // PKHBT >+ 5242880U, // PKHTB >+ 0U, // PLDWi12 >+ 0U, // PLDWrs >+ 0U, // PLDi12 >+ 0U, // PLDrs >+ 0U, // PLIi12 >+ 0U, // PLIrs >+ 0U, // QADD >+ 0U, // QADD16 >+ 0U, // QADD8 >+ 0U, // QASX >+ 0U, // QDADD >+ 0U, // QDSUB >+ 0U, // QSAX >+ 0U, // QSUB >+ 0U, // QSUB16 >+ 0U, // QSUB8 >+ 1024U, // RBIT >+ 1024U, // REV >+ 1024U, // REV16 >+ 1024U, // REVSH >+ 0U, // RFEDA >+ 0U, // RFEDA_UPD >+ 0U, // RFEDB >+ 0U, // RFEDB_UPD >+ 0U, // RFEIA >+ 0U, // RFEIA_UPD >+ 0U, // RFEIB >+ 0U, // RFEIB_UPD >+ 0U, // RORi >+ 0U, // RORr >+ 0U, // RRX >+ 1024U, // RRXi >+ 0U, // RSBSri >+ 0U, // RSBSrsi >+ 0U, // RSBSrsr >+ 0U, // RSBri >+ 0U, // RSBrr >+ 16384U, // RSBrsi >+ 0U, // RSBrsr >+ 0U, // RSCri >+ 0U, // RSCrr >+ 16384U, // RSCrsi >+ 0U, // RSCrsr >+ 0U, // SADD16 >+ 0U, // SADD8 >+ 0U, // SASX >+ 0U, // SBCri >+ 0U, // SBCrr >+ 16384U, // SBCrsi >+ 0U, // SBCrsr >+ 34603008U, // SBFX >+ 0U, // SDIV >+ 0U, // SEL >+ 0U, // SETEND >+ 1184U, // SHA1C >+ 0U, // SHA1H >+ 1184U, // SHA1M >+ 1184U, // SHA1P >+ 1184U, // SHA1SU0 >+ 0U, // SHA1SU1 >+ 1184U, // SHA256H >+ 1184U, // SHA256H2 >+ 0U, // SHA256SU0 >+ 1184U, // SHA256SU1 >+ 0U, // SHADD16 >+ 0U, // SHADD8 >+ 0U, // SHASX >+ 0U, // SHSAX >+ 0U, // SHSUB16 >+ 0U, // SHSUB8 >+ 0U, // SMC >+ 17825792U, // SMLABB >+ 17825792U, // SMLABT >+ 17825792U, // SMLAD >+ 17825792U, // SMLADX >+ 0U, // SMLAL >+ 17825792U, // SMLALBB >+ 17825792U, // SMLALBT >+ 17825792U, // SMLALD >+ 17825792U, // SMLALDX >+ 17825792U, // SMLALTB >+ 17825792U, // SMLALTT >+ 0U, // SMLALv5 >+ 17825792U, // SMLATB >+ 17825792U, // SMLATT >+ 17825792U, // SMLAWB >+ 17825792U, // SMLAWT >+ 17825792U, // SMLSD >+ 17825792U, // SMLSDX >+ 17825792U, // SMLSLD >+ 17825792U, // SMLSLDX >+ 17825792U, // SMMLA >+ 17825792U, // SMMLAR >+ 17825792U, // SMMLS >+ 17825792U, // SMMLSR >+ 0U, // SMMUL >+ 0U, // SMMULR >+ 0U, // SMUAD >+ 0U, // SMUADX >+ 0U, // SMULBB >+ 0U, // SMULBT >+ 17825792U, // SMULL >+ 0U, // SMULLv5 >+ 0U, // SMULTB >+ 0U, // SMULTT >+ 0U, // SMULWB >+ 0U, // SMULWT >+ 0U, // SMUSD >+ 0U, // SMUSDX >+ 0U, // SRSDA >+ 0U, // SRSDA_UPD >+ 0U, // SRSDB >+ 0U, // SRSDB_UPD >+ 0U, // SRSIA >+ 0U, // SRSIA_UPD >+ 0U, // SRSIB >+ 0U, // SRSIB_UPD >+ 2216U, // SSAT >+ 1192U, // SSAT16 >+ 0U, // SSAX >+ 0U, // SSUB16 >+ 0U, // SSUB8 >+ 0U, // STC2L_OFFSET >+ 1U, // STC2L_OPTION >+ 1U, // STC2L_POST >+ 0U, // STC2L_PRE >+ 0U, // STC2_OFFSET >+ 1U, // STC2_OPTION >+ 1U, // STC2_POST >+ 0U, // STC2_PRE >+ 81U, // STCL_OFFSET >+ 49241U, // STCL_OPTION >+ 65625U, // STCL_POST >+ 97U, // STCL_PRE >+ 81U, // STC_OFFSET >+ 49241U, // STC_OPTION >+ 65625U, // STC_POST >+ 97U, // STC_PRE >+ 72U, // STL >+ 72U, // STLB >+ 229376U, // STLEX >+ 229376U, // STLEXB >+ 176U, // STLEXD >+ 229376U, // STLEXH >+ 72U, // STLH >+ 1088U, // STMDA >+ 57U, // STMDA_UPD >+ 1088U, // STMDB >+ 57U, // STMDB_UPD >+ 1088U, // STMIA >+ 57U, // STMIA_UPD >+ 1088U, // STMIB >+ 57U, // STMIB_UPD >+ 72U, // STRBT_POST >+ 82008U, // STRBT_POST_IMM >+ 82008U, // STRBT_POST_REG >+ 82008U, // STRB_POST_IMM >+ 82008U, // STRB_POST_REG >+ 104U, // STRB_PRE_IMM >+ 112U, // STRB_PRE_REG >+ 120U, // STRBi12 >+ 0U, // STRBi_preidx >+ 0U, // STRBr_preidx >+ 128U, // STRBrs >+ 98304U, // STRD >+ 1163288U, // STRD_POST >+ 131096U, // STRD_PRE >+ 229376U, // STREX >+ 229376U, // STREXB >+ 176U, // STREXD >+ 229376U, // STREXH >+ 136U, // STRH >+ 147544U, // STRHTi >+ 163928U, // STRHTr >+ 180312U, // STRH_POST >+ 144U, // STRH_PRE >+ 0U, // STRH_preidx >+ 72U, // STRT_POST >+ 82008U, // STRT_POST_IMM >+ 82008U, // STRT_POST_REG >+ 82008U, // STR_POST_IMM >+ 82008U, // STR_POST_REG >+ 104U, // STR_PRE_IMM >+ 112U, // STR_PRE_REG >+ 120U, // STRi12 >+ 0U, // STRi_preidx >+ 0U, // STRr_preidx >+ 128U, // STRrs >+ 0U, // SUBS_PC_LR >+ 0U, // SUBSri >+ 0U, // SUBSrr >+ 0U, // SUBSrsi >+ 0U, // SUBSrsr >+ 0U, // SUBri >+ 0U, // SUBrr >+ 16384U, // SUBrsi >+ 0U, // SUBrsr >+ 0U, // SVC >+ 229376U, // SWP >+ 229376U, // SWPB >+ 6291456U, // SXTAB >+ 6291456U, // SXTAB16 >+ 6291456U, // SXTAH >+ 2560U, // SXTB >+ 2560U, // SXTB16 >+ 2560U, // SXTH >+ 0U, // TAILJMPd >+ 0U, // TAILJMPr >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNri >+ 1024U, // TEQri >+ 1024U, // TEQrr >+ 40U, // TEQrsi >+ 48U, // TEQrsr >+ 0U, // TPsoft >+ 0U, // TRAP >+ 0U, // TRAPNaCl >+ 1024U, // TSTri >+ 1024U, // TSTrr >+ 40U, // TSTrsi >+ 48U, // TSTrsr >+ 0U, // UADD16 >+ 0U, // UADD8 >+ 0U, // UASX >+ 34603008U, // UBFX >+ 0U, // UDF >+ 0U, // UDIV >+ 0U, // UHADD16 >+ 0U, // UHADD8 >+ 0U, // UHASX >+ 0U, // UHSAX >+ 0U, // UHSUB16 >+ 0U, // UHSUB8 >+ 17825792U, // UMAAL >+ 0U, // UMLAL >+ 0U, // UMLALv5 >+ 17825792U, // UMULL >+ 0U, // UMULLv5 >+ 0U, // UQADD16 >+ 0U, // UQADD8 >+ 0U, // UQASX >+ 0U, // UQSAX >+ 0U, // UQSUB16 >+ 0U, // UQSUB8 >+ 0U, // USAD8 >+ 17825792U, // USADA8 >+ 7340032U, // USAT >+ 0U, // USAT16 >+ 0U, // USAX >+ 0U, // USUB16 >+ 0U, // USUB8 >+ 6291456U, // UXTAB >+ 6291456U, // UXTAB16 >+ 6291456U, // UXTAH >+ 2560U, // UXTB >+ 2560U, // UXTB16 >+ 2560U, // UXTH >+ 1184U, // VABALsv2i64 >+ 1184U, // VABALsv4i32 >+ 1184U, // VABALsv8i16 >+ 1184U, // VABALuv2i64 >+ 1184U, // VABALuv4i32 >+ 1184U, // VABALuv8i16 >+ 1184U, // VABAsv16i8 >+ 1184U, // VABAsv2i32 >+ 1184U, // VABAsv4i16 >+ 1184U, // VABAsv4i32 >+ 1184U, // VABAsv8i16 >+ 1184U, // VABAsv8i8 >+ 1184U, // VABAuv16i8 >+ 1184U, // VABAuv2i32 >+ 1184U, // VABAuv4i16 >+ 1184U, // VABAuv4i32 >+ 1184U, // VABAuv8i16 >+ 1184U, // VABAuv8i8 >+ 1048U, // VABDLsv2i64 >+ 1048U, // VABDLsv4i32 >+ 1048U, // VABDLsv8i16 >+ 1048U, // VABDLuv2i64 >+ 1048U, // VABDLuv4i32 >+ 1048U, // VABDLuv8i16 >+ 247328U, // VABDfd >+ 247328U, // VABDfq >+ 1048U, // VABDsv16i8 >+ 1048U, // VABDsv2i32 >+ 1048U, // VABDsv4i16 >+ 1048U, // VABDsv4i32 >+ 1048U, // VABDsv8i16 >+ 1048U, // VABDsv8i8 >+ 1048U, // VABDuv16i8 >+ 1048U, // VABDuv2i32 >+ 1048U, // VABDuv4i16 >+ 1048U, // VABDuv4i32 >+ 1048U, // VABDuv8i16 >+ 1048U, // VABDuv8i8 >+ 56U, // VABSD >+ 56U, // VABSS >+ 56U, // VABSfd >+ 56U, // VABSfq >+ 0U, // VABSv16i8 >+ 0U, // VABSv2i32 >+ 0U, // VABSv4i16 >+ 0U, // VABSv4i32 >+ 0U, // VABSv8i16 >+ 0U, // VABSv8i8 >+ 247328U, // VACGEd >+ 247328U, // VACGEq >+ 247328U, // VACGTd >+ 247328U, // VACGTq >+ 247328U, // VADDD >+ 1048U, // VADDHNv2i32 >+ 1048U, // VADDHNv4i16 >+ 1048U, // VADDHNv8i8 >+ 1048U, // VADDLsv2i64 >+ 1048U, // VADDLsv4i32 >+ 1048U, // VADDLsv8i16 >+ 1048U, // VADDLuv2i64 >+ 1048U, // VADDLuv4i32 >+ 1048U, // VADDLuv8i16 >+ 247328U, // VADDS >+ 1048U, // VADDWsv2i64 >+ 1048U, // VADDWsv4i32 >+ 1048U, // VADDWsv8i16 >+ 1048U, // VADDWuv2i64 >+ 1048U, // VADDWuv4i32 >+ 1048U, // VADDWuv8i16 >+ 247328U, // VADDfd >+ 247328U, // VADDfq >+ 1048U, // VADDv16i8 >+ 1048U, // VADDv1i64 >+ 1048U, // VADDv2i32 >+ 1048U, // VADDv2i64 >+ 1048U, // VADDv4i16 >+ 1048U, // VADDv4i32 >+ 1048U, // VADDv8i16 >+ 1048U, // VADDv8i8 >+ 0U, // VANDd >+ 0U, // VANDq >+ 0U, // VBICd >+ 0U, // VBICiv2i32 >+ 0U, // VBICiv4i16 >+ 0U, // VBICiv4i32 >+ 0U, // VBICiv8i16 >+ 0U, // VBICq >+ 262168U, // VBIFd >+ 262168U, // VBIFq >+ 262168U, // VBITd >+ 262168U, // VBITq >+ 262168U, // VBSLd >+ 262168U, // VBSLq >+ 247328U, // VCEQfd >+ 247328U, // VCEQfq >+ 1048U, // VCEQv16i8 >+ 1048U, // VCEQv2i32 >+ 1048U, // VCEQv4i16 >+ 1048U, // VCEQv4i32 >+ 1048U, // VCEQv8i16 >+ 1048U, // VCEQv8i8 >+ 2U, // VCEQzv16i8 >+ 184U, // VCEQzv2f32 >+ 2U, // VCEQzv2i32 >+ 184U, // VCEQzv4f32 >+ 2U, // VCEQzv4i16 >+ 2U, // VCEQzv4i32 >+ 2U, // VCEQzv8i16 >+ 2U, // VCEQzv8i8 >+ 247328U, // VCGEfd >+ 247328U, // VCGEfq >+ 1048U, // VCGEsv16i8 >+ 1048U, // VCGEsv2i32 >+ 1048U, // VCGEsv4i16 >+ 1048U, // VCGEsv4i32 >+ 1048U, // VCGEsv8i16 >+ 1048U, // VCGEsv8i8 >+ 1048U, // VCGEuv16i8 >+ 1048U, // VCGEuv2i32 >+ 1048U, // VCGEuv4i16 >+ 1048U, // VCGEuv4i32 >+ 1048U, // VCGEuv8i16 >+ 1048U, // VCGEuv8i8 >+ 2U, // VCGEzv16i8 >+ 184U, // VCGEzv2f32 >+ 2U, // VCGEzv2i32 >+ 184U, // VCGEzv4f32 >+ 2U, // VCGEzv4i16 >+ 2U, // VCGEzv4i32 >+ 2U, // VCGEzv8i16 >+ 2U, // VCGEzv8i8 >+ 247328U, // VCGTfd >+ 247328U, // VCGTfq >+ 1048U, // VCGTsv16i8 >+ 1048U, // VCGTsv2i32 >+ 1048U, // VCGTsv4i16 >+ 1048U, // VCGTsv4i32 >+ 1048U, // VCGTsv8i16 >+ 1048U, // VCGTsv8i8 >+ 1048U, // VCGTuv16i8 >+ 1048U, // VCGTuv2i32 >+ 1048U, // VCGTuv4i16 >+ 1048U, // VCGTuv4i32 >+ 1048U, // VCGTuv8i16 >+ 1048U, // VCGTuv8i8 >+ 2U, // VCGTzv16i8 >+ 184U, // VCGTzv2f32 >+ 2U, // VCGTzv2i32 >+ 184U, // VCGTzv4f32 >+ 2U, // VCGTzv4i16 >+ 2U, // VCGTzv4i32 >+ 2U, // VCGTzv8i16 >+ 2U, // VCGTzv8i8 >+ 2U, // VCLEzv16i8 >+ 184U, // VCLEzv2f32 >+ 2U, // VCLEzv2i32 >+ 184U, // VCLEzv4f32 >+ 2U, // VCLEzv4i16 >+ 2U, // VCLEzv4i32 >+ 2U, // VCLEzv8i16 >+ 2U, // VCLEzv8i8 >+ 0U, // VCLSv16i8 >+ 0U, // VCLSv2i32 >+ 0U, // VCLSv4i16 >+ 0U, // VCLSv4i32 >+ 0U, // VCLSv8i16 >+ 0U, // VCLSv8i8 >+ 2U, // VCLTzv16i8 >+ 184U, // VCLTzv2f32 >+ 2U, // VCLTzv2i32 >+ 184U, // VCLTzv4f32 >+ 2U, // VCLTzv4i16 >+ 2U, // VCLTzv4i32 >+ 2U, // VCLTzv8i16 >+ 2U, // VCLTzv8i8 >+ 0U, // VCLZv16i8 >+ 0U, // VCLZv2i32 >+ 0U, // VCLZv4i16 >+ 0U, // VCLZv4i32 >+ 0U, // VCLZv8i16 >+ 0U, // VCLZv8i8 >+ 56U, // VCMPD >+ 56U, // VCMPED >+ 56U, // VCMPES >+ 0U, // VCMPEZD >+ 0U, // VCMPEZS >+ 56U, // VCMPS >+ 0U, // VCMPZD >+ 0U, // VCMPZS >+ 1024U, // VCNTd >+ 1024U, // VCNTq >+ 0U, // VCVTANSD >+ 0U, // VCVTANSQ >+ 0U, // VCVTANUD >+ 0U, // VCVTANUQ >+ 0U, // VCVTASD >+ 0U, // VCVTASS >+ 0U, // VCVTAUD >+ 0U, // VCVTAUS >+ 0U, // VCVTBDH >+ 0U, // VCVTBHD >+ 0U, // VCVTBHS >+ 0U, // VCVTBSH >+ 0U, // VCVTDS >+ 0U, // VCVTMNSD >+ 0U, // VCVTMNSQ >+ 0U, // VCVTMNUD >+ 0U, // VCVTMNUQ >+ 0U, // VCVTMSD >+ 0U, // VCVTMSS >+ 0U, // VCVTMUD >+ 0U, // VCVTMUS >+ 0U, // VCVTNNSD >+ 0U, // VCVTNNSQ >+ 0U, // VCVTNNUD >+ 0U, // VCVTNNUQ >+ 0U, // VCVTNSD >+ 0U, // VCVTNSS >+ 0U, // VCVTNUD >+ 0U, // VCVTNUS >+ 0U, // VCVTPNSD >+ 0U, // VCVTPNSQ >+ 0U, // VCVTPNUD >+ 0U, // VCVTPNUQ >+ 0U, // VCVTPSD >+ 0U, // VCVTPSS >+ 0U, // VCVTPUD >+ 0U, // VCVTPUS >+ 0U, // VCVTSD >+ 0U, // VCVTTDH >+ 0U, // VCVTTHD >+ 0U, // VCVTTHS >+ 0U, // VCVTTSH >+ 0U, // VCVTf2h >+ 0U, // VCVTf2sd >+ 0U, // VCVTf2sq >+ 0U, // VCVTf2ud >+ 0U, // VCVTf2uq >+ 58U, // VCVTf2xsd >+ 58U, // VCVTf2xsq >+ 58U, // VCVTf2xud >+ 58U, // VCVTf2xuq >+ 0U, // VCVTh2f >+ 0U, // VCVTs2fd >+ 0U, // VCVTs2fq >+ 0U, // VCVTu2fd >+ 0U, // VCVTu2fq >+ 58U, // VCVTxs2fd >+ 58U, // VCVTxs2fq >+ 58U, // VCVTxu2fd >+ 58U, // VCVTxu2fq >+ 247328U, // VDIVD >+ 247328U, // VDIVS >+ 1024U, // VDUP16d >+ 1024U, // VDUP16q >+ 1024U, // VDUP32d >+ 1024U, // VDUP32q >+ 1024U, // VDUP8d >+ 1024U, // VDUP8q >+ 3072U, // VDUPLN16d >+ 3072U, // VDUPLN16q >+ 3072U, // VDUPLN32d >+ 3072U, // VDUPLN32q >+ 3072U, // VDUPLN8d >+ 3072U, // VDUPLN8q >+ 0U, // VEORd >+ 0U, // VEORq >+ 17825792U, // VEXTd16 >+ 17825792U, // VEXTd32 >+ 17825792U, // VEXTd8 >+ 17825792U, // VEXTq16 >+ 17825792U, // VEXTq32 >+ 17825792U, // VEXTq64 >+ 17825792U, // VEXTq8 >+ 249378U, // VFMAD >+ 249378U, // VFMAS >+ 249378U, // VFMAfd >+ 249378U, // VFMAfq >+ 249378U, // VFMSD >+ 249378U, // VFMSS >+ 249378U, // VFMSfd >+ 249378U, // VFMSfq >+ 249378U, // VFNMAD >+ 249378U, // VFNMAS >+ 249378U, // VFNMSD >+ 249378U, // VFNMSS >+ 3072U, // VGETLNi32 >+ 3U, // VGETLNs16 >+ 3U, // VGETLNs8 >+ 3U, // VGETLNu16 >+ 3U, // VGETLNu8 >+ 1048U, // VHADDsv16i8 >+ 1048U, // VHADDsv2i32 >+ 1048U, // VHADDsv4i16 >+ 1048U, // VHADDsv4i32 >+ 1048U, // VHADDsv8i16 >+ 1048U, // VHADDsv8i8 >+ 1048U, // VHADDuv16i8 >+ 1048U, // VHADDuv2i32 >+ 1048U, // VHADDuv4i16 >+ 1048U, // VHADDuv4i32 >+ 1048U, // VHADDuv8i16 >+ 1048U, // VHADDuv8i8 >+ 1048U, // VHSUBsv16i8 >+ 1048U, // VHSUBsv2i32 >+ 1048U, // VHSUBsv4i16 >+ 1048U, // VHSUBsv4i32 >+ 1048U, // VHSUBsv8i16 >+ 1048U, // VHSUBsv8i8 >+ 1048U, // VHSUBuv16i8 >+ 1048U, // VHSUBuv2i32 >+ 1048U, // VHSUBuv4i16 >+ 1048U, // VHSUBuv4i32 >+ 1048U, // VHSUBuv8i16 >+ 1048U, // VHSUBuv8i8 >+ 59U, // VLD1DUPd16 >+ 195U, // VLD1DUPd16wb_fixed >+ 4131U, // VLD1DUPd16wb_register >+ 59U, // VLD1DUPd32 >+ 195U, // VLD1DUPd32wb_fixed >+ 4131U, // VLD1DUPd32wb_register >+ 59U, // VLD1DUPd8 >+ 195U, // VLD1DUPd8wb_fixed >+ 4131U, // VLD1DUPd8wb_register >+ 59U, // VLD1DUPq16 >+ 195U, // VLD1DUPq16wb_fixed >+ 4131U, // VLD1DUPq16wb_register >+ 59U, // VLD1DUPq32 >+ 195U, // VLD1DUPq32wb_fixed >+ 4131U, // VLD1DUPq32wb_register >+ 59U, // VLD1DUPq8 >+ 195U, // VLD1DUPq8wb_fixed >+ 4131U, // VLD1DUPq8wb_register >+ 283339U, // VLD1LNd16 >+ 299731U, // VLD1LNd16_UPD >+ 283339U, // VLD1LNd32 >+ 299731U, // VLD1LNd32_UPD >+ 283339U, // VLD1LNd8 >+ 299731U, // VLD1LNd8_UPD >+ 1240U, // VLD1LNdAsm_16 >+ 1240U, // VLD1LNdAsm_32 >+ 1240U, // VLD1LNdAsm_8 >+ 5336U, // VLD1LNdWB_fixed_Asm_16 >+ 5336U, // VLD1LNdWB_fixed_Asm_32 >+ 5336U, // VLD1LNdWB_fixed_Asm_8 >+ 311512U, // VLD1LNdWB_register_Asm_16 >+ 311512U, // VLD1LNdWB_register_Asm_32 >+ 311512U, // VLD1LNdWB_register_Asm_8 >+ 0U, // VLD1LNq16Pseudo >+ 0U, // VLD1LNq16Pseudo_UPD >+ 0U, // VLD1LNq32Pseudo >+ 0U, // VLD1LNq32Pseudo_UPD >+ 0U, // VLD1LNq8Pseudo >+ 0U, // VLD1LNq8Pseudo_UPD >+ 59U, // VLD1d16 >+ 59U, // VLD1d16Q >+ 195U, // VLD1d16Qwb_fixed >+ 4131U, // VLD1d16Qwb_register >+ 59U, // VLD1d16T >+ 195U, // VLD1d16Twb_fixed >+ 4131U, // VLD1d16Twb_register >+ 195U, // VLD1d16wb_fixed >+ 4131U, // VLD1d16wb_register >+ 59U, // VLD1d32 >+ 59U, // VLD1d32Q >+ 195U, // VLD1d32Qwb_fixed >+ 4131U, // VLD1d32Qwb_register >+ 59U, // VLD1d32T >+ 195U, // VLD1d32Twb_fixed >+ 4131U, // VLD1d32Twb_register >+ 195U, // VLD1d32wb_fixed >+ 4131U, // VLD1d32wb_register >+ 59U, // VLD1d64 >+ 59U, // VLD1d64Q >+ 0U, // VLD1d64QPseudo >+ 0U, // VLD1d64QPseudoWB_fixed >+ 0U, // VLD1d64QPseudoWB_register >+ 195U, // VLD1d64Qwb_fixed >+ 4131U, // VLD1d64Qwb_register >+ 59U, // VLD1d64T >+ 0U, // VLD1d64TPseudo >+ 0U, // VLD1d64TPseudoWB_fixed >+ 0U, // VLD1d64TPseudoWB_register >+ 195U, // VLD1d64Twb_fixed >+ 4131U, // VLD1d64Twb_register >+ 195U, // VLD1d64wb_fixed >+ 4131U, // VLD1d64wb_register >+ 59U, // VLD1d8 >+ 59U, // VLD1d8Q >+ 195U, // VLD1d8Qwb_fixed >+ 4131U, // VLD1d8Qwb_register >+ 59U, // VLD1d8T >+ 195U, // VLD1d8Twb_fixed >+ 4131U, // VLD1d8Twb_register >+ 195U, // VLD1d8wb_fixed >+ 4131U, // VLD1d8wb_register >+ 59U, // VLD1q16 >+ 195U, // VLD1q16wb_fixed >+ 4131U, // VLD1q16wb_register >+ 59U, // VLD1q32 >+ 195U, // VLD1q32wb_fixed >+ 4131U, // VLD1q32wb_register >+ 59U, // VLD1q64 >+ 195U, // VLD1q64wb_fixed >+ 4131U, // VLD1q64wb_register >+ 59U, // VLD1q8 >+ 195U, // VLD1q8wb_fixed >+ 4131U, // VLD1q8wb_register >+ 59U, // VLD2DUPd16 >+ 195U, // VLD2DUPd16wb_fixed >+ 4131U, // VLD2DUPd16wb_register >+ 59U, // VLD2DUPd16x2 >+ 195U, // VLD2DUPd16x2wb_fixed >+ 4131U, // VLD2DUPd16x2wb_register >+ 59U, // VLD2DUPd32 >+ 195U, // VLD2DUPd32wb_fixed >+ 4131U, // VLD2DUPd32wb_register >+ 59U, // VLD2DUPd32x2 >+ 195U, // VLD2DUPd32x2wb_fixed >+ 4131U, // VLD2DUPd32x2wb_register >+ 59U, // VLD2DUPd8 >+ 195U, // VLD2DUPd8wb_fixed >+ 4131U, // VLD2DUPd8wb_register >+ 59U, // VLD2DUPd8x2 >+ 195U, // VLD2DUPd8x2wb_fixed >+ 4131U, // VLD2DUPd8x2wb_register >+ 333523U, // VLD2LNd16 >+ 0U, // VLD2LNd16Pseudo >+ 0U, // VLD2LNd16Pseudo_UPD >+ 350435U, // VLD2LNd16_UPD >+ 333523U, // VLD2LNd32 >+ 0U, // VLD2LNd32Pseudo >+ 0U, // VLD2LNd32Pseudo_UPD >+ 350435U, // VLD2LNd32_UPD >+ 333523U, // VLD2LNd8 >+ 0U, // VLD2LNd8Pseudo >+ 0U, // VLD2LNd8Pseudo_UPD >+ 350435U, // VLD2LNd8_UPD >+ 1240U, // VLD2LNdAsm_16 >+ 1240U, // VLD2LNdAsm_32 >+ 1240U, // VLD2LNdAsm_8 >+ 5336U, // VLD2LNdWB_fixed_Asm_16 >+ 5336U, // VLD2LNdWB_fixed_Asm_32 >+ 5336U, // VLD2LNdWB_fixed_Asm_8 >+ 311512U, // VLD2LNdWB_register_Asm_16 >+ 311512U, // VLD2LNdWB_register_Asm_32 >+ 311512U, // VLD2LNdWB_register_Asm_8 >+ 333523U, // VLD2LNq16 >+ 0U, // VLD2LNq16Pseudo >+ 0U, // VLD2LNq16Pseudo_UPD >+ 350435U, // VLD2LNq16_UPD >+ 333523U, // VLD2LNq32 >+ 0U, // VLD2LNq32Pseudo >+ 0U, // VLD2LNq32Pseudo_UPD >+ 350435U, // VLD2LNq32_UPD >+ 1240U, // VLD2LNqAsm_16 >+ 1240U, // VLD2LNqAsm_32 >+ 5336U, // VLD2LNqWB_fixed_Asm_16 >+ 5336U, // VLD2LNqWB_fixed_Asm_32 >+ 311512U, // VLD2LNqWB_register_Asm_16 >+ 311512U, // VLD2LNqWB_register_Asm_32 >+ 59U, // VLD2b16 >+ 195U, // VLD2b16wb_fixed >+ 4131U, // VLD2b16wb_register >+ 59U, // VLD2b32 >+ 195U, // VLD2b32wb_fixed >+ 4131U, // VLD2b32wb_register >+ 59U, // VLD2b8 >+ 195U, // VLD2b8wb_fixed >+ 4131U, // VLD2b8wb_register >+ 59U, // VLD2d16 >+ 195U, // VLD2d16wb_fixed >+ 4131U, // VLD2d16wb_register >+ 59U, // VLD2d32 >+ 195U, // VLD2d32wb_fixed >+ 4131U, // VLD2d32wb_register >+ 59U, // VLD2d8 >+ 195U, // VLD2d8wb_fixed >+ 4131U, // VLD2d8wb_register >+ 59U, // VLD2q16 >+ 0U, // VLD2q16Pseudo >+ 0U, // VLD2q16PseudoWB_fixed >+ 0U, // VLD2q16PseudoWB_register >+ 195U, // VLD2q16wb_fixed >+ 4131U, // VLD2q16wb_register >+ 59U, // VLD2q32 >+ 0U, // VLD2q32Pseudo >+ 0U, // VLD2q32PseudoWB_fixed >+ 0U, // VLD2q32PseudoWB_register >+ 195U, // VLD2q32wb_fixed >+ 4131U, // VLD2q32wb_register >+ 59U, // VLD2q8 >+ 0U, // VLD2q8Pseudo >+ 0U, // VLD2q8PseudoWB_fixed >+ 0U, // VLD2q8PseudoWB_register >+ 195U, // VLD2q8wb_fixed >+ 4131U, // VLD2q8wb_register >+ 6892U, // VLD3DUPd16 >+ 0U, // VLD3DUPd16Pseudo >+ 0U, // VLD3DUPd16Pseudo_UPD >+ 367852U, // VLD3DUPd16_UPD >+ 6892U, // VLD3DUPd32 >+ 0U, // VLD3DUPd32Pseudo >+ 0U, // VLD3DUPd32Pseudo_UPD >+ 367852U, // VLD3DUPd32_UPD >+ 6892U, // VLD3DUPd8 >+ 0U, // VLD3DUPd8Pseudo >+ 0U, // VLD3DUPd8Pseudo_UPD >+ 367852U, // VLD3DUPd8_UPD >+ 0U, // VLD3DUPdAsm_16 >+ 0U, // VLD3DUPdAsm_32 >+ 0U, // VLD3DUPdAsm_8 >+ 4U, // VLD3DUPdWB_fixed_Asm_16 >+ 4U, // VLD3DUPdWB_fixed_Asm_32 >+ 4U, // VLD3DUPdWB_fixed_Asm_8 >+ 1184U, // VLD3DUPdWB_register_Asm_16 >+ 1184U, // VLD3DUPdWB_register_Asm_32 >+ 1184U, // VLD3DUPdWB_register_Asm_8 >+ 6892U, // VLD3DUPq16 >+ 367852U, // VLD3DUPq16_UPD >+ 6892U, // VLD3DUPq32 >+ 367852U, // VLD3DUPq32_UPD >+ 6892U, // VLD3DUPq8 >+ 367852U, // VLD3DUPq8_UPD >+ 0U, // VLD3DUPqAsm_16 >+ 0U, // VLD3DUPqAsm_32 >+ 0U, // VLD3DUPqAsm_8 >+ 4U, // VLD3DUPqWB_fixed_Asm_16 >+ 4U, // VLD3DUPqWB_fixed_Asm_32 >+ 4U, // VLD3DUPqWB_fixed_Asm_8 >+ 1184U, // VLD3DUPqWB_register_Asm_16 >+ 1184U, // VLD3DUPqWB_register_Asm_32 >+ 1184U, // VLD3DUPqWB_register_Asm_8 >+ 383203U, // VLD3LNd16 >+ 0U, // VLD3LNd16Pseudo >+ 0U, // VLD3LNd16Pseudo_UPD >+ 398067U, // VLD3LNd16_UPD >+ 383203U, // VLD3LNd32 >+ 0U, // VLD3LNd32Pseudo >+ 0U, // VLD3LNd32Pseudo_UPD >+ 398067U, // VLD3LNd32_UPD >+ 383203U, // VLD3LNd8 >+ 0U, // VLD3LNd8Pseudo >+ 0U, // VLD3LNd8Pseudo_UPD >+ 398067U, // VLD3LNd8_UPD >+ 1240U, // VLD3LNdAsm_16 >+ 1240U, // VLD3LNdAsm_32 >+ 1240U, // VLD3LNdAsm_8 >+ 5336U, // VLD3LNdWB_fixed_Asm_16 >+ 5336U, // VLD3LNdWB_fixed_Asm_32 >+ 5336U, // VLD3LNdWB_fixed_Asm_8 >+ 311512U, // VLD3LNdWB_register_Asm_16 >+ 311512U, // VLD3LNdWB_register_Asm_32 >+ 311512U, // VLD3LNdWB_register_Asm_8 >+ 383203U, // VLD3LNq16 >+ 0U, // VLD3LNq16Pseudo >+ 0U, // VLD3LNq16Pseudo_UPD >+ 398067U, // VLD3LNq16_UPD >+ 383203U, // VLD3LNq32 >+ 0U, // VLD3LNq32Pseudo >+ 0U, // VLD3LNq32Pseudo_UPD >+ 398067U, // VLD3LNq32_UPD >+ 1240U, // VLD3LNqAsm_16 >+ 1240U, // VLD3LNqAsm_32 >+ 5336U, // VLD3LNqWB_fixed_Asm_16 >+ 5336U, // VLD3LNqWB_fixed_Asm_32 >+ 311512U, // VLD3LNqWB_register_Asm_16 >+ 311512U, // VLD3LNqWB_register_Asm_32 >+ 58720256U, // VLD3d16 >+ 0U, // VLD3d16Pseudo >+ 0U, // VLD3d16Pseudo_UPD >+ 75497472U, // VLD3d16_UPD >+ 58720256U, // VLD3d32 >+ 0U, // VLD3d32Pseudo >+ 0U, // VLD3d32Pseudo_UPD >+ 75497472U, // VLD3d32_UPD >+ 58720256U, // VLD3d8 >+ 0U, // VLD3d8Pseudo >+ 0U, // VLD3d8Pseudo_UPD >+ 75497472U, // VLD3d8_UPD >+ 59U, // VLD3dAsm_16 >+ 59U, // VLD3dAsm_32 >+ 59U, // VLD3dAsm_8 >+ 195U, // VLD3dWB_fixed_Asm_16 >+ 195U, // VLD3dWB_fixed_Asm_32 >+ 195U, // VLD3dWB_fixed_Asm_8 >+ 249379U, // VLD3dWB_register_Asm_16 >+ 249379U, // VLD3dWB_register_Asm_32 >+ 249379U, // VLD3dWB_register_Asm_8 >+ 58720256U, // VLD3q16 >+ 0U, // VLD3q16Pseudo_UPD >+ 75497472U, // VLD3q16_UPD >+ 0U, // VLD3q16oddPseudo >+ 0U, // VLD3q16oddPseudo_UPD >+ 58720256U, // VLD3q32 >+ 0U, // VLD3q32Pseudo_UPD >+ 75497472U, // VLD3q32_UPD >+ 0U, // VLD3q32oddPseudo >+ 0U, // VLD3q32oddPseudo_UPD >+ 58720256U, // VLD3q8 >+ 0U, // VLD3q8Pseudo_UPD >+ 75497472U, // VLD3q8_UPD >+ 0U, // VLD3q8oddPseudo >+ 0U, // VLD3q8oddPseudo_UPD >+ 0U, // VLD3qAsm_16 >+ 0U, // VLD3qAsm_32 >+ 0U, // VLD3qAsm_8 >+ 4U, // VLD3qWB_fixed_Asm_16 >+ 4U, // VLD3qWB_fixed_Asm_32 >+ 4U, // VLD3qWB_fixed_Asm_8 >+ 1184U, // VLD3qWB_register_Asm_16 >+ 1184U, // VLD3qWB_register_Asm_32 >+ 1184U, // VLD3qWB_register_Asm_8 >+ 253180U, // VLD4DUPd16 >+ 0U, // VLD4DUPd16Pseudo >+ 0U, // VLD4DUPd16Pseudo_UPD >+ 7932U, // VLD4DUPd16_UPD >+ 253180U, // VLD4DUPd32 >+ 0U, // VLD4DUPd32Pseudo >+ 0U, // VLD4DUPd32Pseudo_UPD >+ 7932U, // VLD4DUPd32_UPD >+ 253180U, // VLD4DUPd8 >+ 0U, // VLD4DUPd8Pseudo >+ 0U, // VLD4DUPd8Pseudo_UPD >+ 7932U, // VLD4DUPd8_UPD >+ 0U, // VLD4DUPdAsm_16 >+ 0U, // VLD4DUPdAsm_32 >+ 0U, // VLD4DUPdAsm_8 >+ 4U, // VLD4DUPdWB_fixed_Asm_16 >+ 4U, // VLD4DUPdWB_fixed_Asm_32 >+ 4U, // VLD4DUPdWB_fixed_Asm_8 >+ 1184U, // VLD4DUPdWB_register_Asm_16 >+ 1184U, // VLD4DUPdWB_register_Asm_32 >+ 1184U, // VLD4DUPdWB_register_Asm_8 >+ 253180U, // VLD4DUPq16 >+ 7932U, // VLD4DUPq16_UPD >+ 253180U, // VLD4DUPq32 >+ 7932U, // VLD4DUPq32_UPD >+ 253180U, // VLD4DUPq8 >+ 7932U, // VLD4DUPq8_UPD >+ 0U, // VLD4DUPqAsm_16 >+ 0U, // VLD4DUPqAsm_32 >+ 0U, // VLD4DUPqAsm_8 >+ 4U, // VLD4DUPqWB_fixed_Asm_16 >+ 4U, // VLD4DUPqWB_fixed_Asm_32 >+ 4U, // VLD4DUPqWB_fixed_Asm_8 >+ 1184U, // VLD4DUPqWB_register_Asm_16 >+ 1184U, // VLD4DUPqWB_register_Asm_32 >+ 1184U, // VLD4DUPqWB_register_Asm_8 >+ 93591283U, // VLD4LNd16 >+ 0U, // VLD4LNd16Pseudo >+ 0U, // VLD4LNd16Pseudo_UPD >+ 259U, // VLD4LNd16_UPD >+ 93591283U, // VLD4LNd32 >+ 0U, // VLD4LNd32Pseudo >+ 0U, // VLD4LNd32Pseudo_UPD >+ 259U, // VLD4LNd32_UPD >+ 93591283U, // VLD4LNd8 >+ 0U, // VLD4LNd8Pseudo >+ 0U, // VLD4LNd8Pseudo_UPD >+ 259U, // VLD4LNd8_UPD >+ 1240U, // VLD4LNdAsm_16 >+ 1240U, // VLD4LNdAsm_32 >+ 1240U, // VLD4LNdAsm_8 >+ 5336U, // VLD4LNdWB_fixed_Asm_16 >+ 5336U, // VLD4LNdWB_fixed_Asm_32 >+ 5336U, // VLD4LNdWB_fixed_Asm_8 >+ 311512U, // VLD4LNdWB_register_Asm_16 >+ 311512U, // VLD4LNdWB_register_Asm_32 >+ 311512U, // VLD4LNdWB_register_Asm_8 >+ 93591283U, // VLD4LNq16 >+ 0U, // VLD4LNq16Pseudo >+ 0U, // VLD4LNq16Pseudo_UPD >+ 259U, // VLD4LNq16_UPD >+ 93591283U, // VLD4LNq32 >+ 0U, // VLD4LNq32Pseudo >+ 0U, // VLD4LNq32Pseudo_UPD >+ 259U, // VLD4LNq32_UPD >+ 1240U, // VLD4LNqAsm_16 >+ 1240U, // VLD4LNqAsm_32 >+ 5336U, // VLD4LNqWB_fixed_Asm_16 >+ 5336U, // VLD4LNqWB_fixed_Asm_32 >+ 311512U, // VLD4LNqWB_register_Asm_16 >+ 311512U, // VLD4LNqWB_register_Asm_32 >+ 286261248U, // VLD4d16 >+ 0U, // VLD4d16Pseudo >+ 0U, // VLD4d16Pseudo_UPD >+ 823132160U, // VLD4d16_UPD >+ 286261248U, // VLD4d32 >+ 0U, // VLD4d32Pseudo >+ 0U, // VLD4d32Pseudo_UPD >+ 823132160U, // VLD4d32_UPD >+ 286261248U, // VLD4d8 >+ 0U, // VLD4d8Pseudo >+ 0U, // VLD4d8Pseudo_UPD >+ 823132160U, // VLD4d8_UPD >+ 59U, // VLD4dAsm_16 >+ 59U, // VLD4dAsm_32 >+ 59U, // VLD4dAsm_8 >+ 195U, // VLD4dWB_fixed_Asm_16 >+ 195U, // VLD4dWB_fixed_Asm_32 >+ 195U, // VLD4dWB_fixed_Asm_8 >+ 249379U, // VLD4dWB_register_Asm_16 >+ 249379U, // VLD4dWB_register_Asm_32 >+ 249379U, // VLD4dWB_register_Asm_8 >+ 286261248U, // VLD4q16 >+ 0U, // VLD4q16Pseudo_UPD >+ 823132160U, // VLD4q16_UPD >+ 0U, // VLD4q16oddPseudo >+ 0U, // VLD4q16oddPseudo_UPD >+ 286261248U, // VLD4q32 >+ 0U, // VLD4q32Pseudo_UPD >+ 823132160U, // VLD4q32_UPD >+ 0U, // VLD4q32oddPseudo >+ 0U, // VLD4q32oddPseudo_UPD >+ 286261248U, // VLD4q8 >+ 0U, // VLD4q8Pseudo_UPD >+ 823132160U, // VLD4q8_UPD >+ 0U, // VLD4q8oddPseudo >+ 0U, // VLD4q8oddPseudo_UPD >+ 0U, // VLD4qAsm_16 >+ 0U, // VLD4qAsm_32 >+ 0U, // VLD4qAsm_8 >+ 4U, // VLD4qWB_fixed_Asm_16 >+ 4U, // VLD4qWB_fixed_Asm_32 >+ 4U, // VLD4qWB_fixed_Asm_8 >+ 1184U, // VLD4qWB_register_Asm_16 >+ 1184U, // VLD4qWB_register_Asm_32 >+ 1184U, // VLD4qWB_register_Asm_8 >+ 57U, // VLDMDDB_UPD >+ 1088U, // VLDMDIA >+ 57U, // VLDMDIA_UPD >+ 0U, // VLDMQIA >+ 57U, // VLDMSDB_UPD >+ 1088U, // VLDMSIA >+ 57U, // VLDMSIA_UPD >+ 264U, // VLDRD >+ 264U, // VLDRS >+ 1048U, // VMAXNMD >+ 1048U, // VMAXNMND >+ 1048U, // VMAXNMNQ >+ 1048U, // VMAXNMS >+ 247328U, // VMAXfd >+ 247328U, // VMAXfq >+ 1048U, // VMAXsv16i8 >+ 1048U, // VMAXsv2i32 >+ 1048U, // VMAXsv4i16 >+ 1048U, // VMAXsv4i32 >+ 1048U, // VMAXsv8i16 >+ 1048U, // VMAXsv8i8 >+ 1048U, // VMAXuv16i8 >+ 1048U, // VMAXuv2i32 >+ 1048U, // VMAXuv4i16 >+ 1048U, // VMAXuv4i32 >+ 1048U, // VMAXuv8i16 >+ 1048U, // VMAXuv8i8 >+ 1048U, // VMINNMD >+ 1048U, // VMINNMND >+ 1048U, // VMINNMNQ >+ 1048U, // VMINNMS >+ 247328U, // VMINfd >+ 247328U, // VMINfq >+ 1048U, // VMINsv16i8 >+ 1048U, // VMINsv2i32 >+ 1048U, // VMINsv4i16 >+ 1048U, // VMINsv4i32 >+ 1048U, // VMINsv8i16 >+ 1048U, // VMINsv8i8 >+ 1048U, // VMINuv16i8 >+ 1048U, // VMINuv2i32 >+ 1048U, // VMINuv4i16 >+ 1048U, // VMINuv4i32 >+ 1048U, // VMINuv8i16 >+ 1048U, // VMINuv8i8 >+ 249378U, // VMLAD >+ 8352U, // VMLALslsv2i32 >+ 8352U, // VMLALslsv4i16 >+ 8352U, // VMLALsluv2i32 >+ 8352U, // VMLALsluv4i16 >+ 1184U, // VMLALsv2i64 >+ 1184U, // VMLALsv4i32 >+ 1184U, // VMLALsv8i16 >+ 1184U, // VMLALuv2i64 >+ 1184U, // VMLALuv4i32 >+ 1184U, // VMLALuv8i16 >+ 249378U, // VMLAS >+ 249378U, // VMLAfd >+ 249378U, // VMLAfq >+ 413218U, // VMLAslfd >+ 413218U, // VMLAslfq >+ 8352U, // VMLAslv2i32 >+ 8352U, // VMLAslv4i16 >+ 8352U, // VMLAslv4i32 >+ 8352U, // VMLAslv8i16 >+ 1184U, // VMLAv16i8 >+ 1184U, // VMLAv2i32 >+ 1184U, // VMLAv4i16 >+ 1184U, // VMLAv4i32 >+ 1184U, // VMLAv8i16 >+ 1184U, // VMLAv8i8 >+ 249378U, // VMLSD >+ 8352U, // VMLSLslsv2i32 >+ 8352U, // VMLSLslsv4i16 >+ 8352U, // VMLSLsluv2i32 >+ 8352U, // VMLSLsluv4i16 >+ 1184U, // VMLSLsv2i64 >+ 1184U, // VMLSLsv4i32 >+ 1184U, // VMLSLsv8i16 >+ 1184U, // VMLSLuv2i64 >+ 1184U, // VMLSLuv4i32 >+ 1184U, // VMLSLuv8i16 >+ 249378U, // VMLSS >+ 249378U, // VMLSfd >+ 249378U, // VMLSfq >+ 413218U, // VMLSslfd >+ 413218U, // VMLSslfq >+ 8352U, // VMLSslv2i32 >+ 8352U, // VMLSslv4i16 >+ 8352U, // VMLSslv4i32 >+ 8352U, // VMLSslv8i16 >+ 1184U, // VMLSv16i8 >+ 1184U, // VMLSv2i32 >+ 1184U, // VMLSv4i16 >+ 1184U, // VMLSv4i32 >+ 1184U, // VMLSv8i16 >+ 1184U, // VMLSv8i8 >+ 56U, // VMOVD >+ 0U, // VMOVD0 >+ 0U, // VMOVDRR >+ 0U, // VMOVDcc >+ 0U, // VMOVLsv2i64 >+ 0U, // VMOVLsv4i32 >+ 0U, // VMOVLsv8i16 >+ 0U, // VMOVLuv2i64 >+ 0U, // VMOVLuv4i32 >+ 0U, // VMOVLuv8i16 >+ 0U, // VMOVNv2i32 >+ 0U, // VMOVNv4i16 >+ 0U, // VMOVNv8i8 >+ 0U, // VMOVQ0 >+ 0U, // VMOVRRD >+ 17825792U, // VMOVRRS >+ 1024U, // VMOVRS >+ 56U, // VMOVS >+ 1024U, // VMOVSR >+ 17825792U, // VMOVSRR >+ 0U, // VMOVScc >+ 0U, // VMOVv16i8 >+ 0U, // VMOVv1i64 >+ 0U, // VMOVv2f32 >+ 0U, // VMOVv2i32 >+ 0U, // VMOVv2i64 >+ 0U, // VMOVv4f32 >+ 0U, // VMOVv4i16 >+ 0U, // VMOVv4i32 >+ 0U, // VMOVv8i16 >+ 0U, // VMOVv8i8 >+ 4U, // VMRS >+ 4U, // VMRS_FPEXC >+ 5U, // VMRS_FPINST >+ 5U, // VMRS_FPINST2 >+ 5U, // VMRS_FPSID >+ 5U, // VMRS_MVFR0 >+ 6U, // VMRS_MVFR1 >+ 6U, // VMRS_MVFR2 >+ 0U, // VMSR >+ 0U, // VMSR_FPEXC >+ 0U, // VMSR_FPINST >+ 0U, // VMSR_FPINST2 >+ 0U, // VMSR_FPSID >+ 247328U, // VMULD >+ 1048U, // VMULLp64 >+ 0U, // VMULLp8 >+ 8728U, // VMULLslsv2i32 >+ 8728U, // VMULLslsv4i16 >+ 8728U, // VMULLsluv2i32 >+ 8728U, // VMULLsluv4i16 >+ 1048U, // VMULLsv2i64 >+ 1048U, // VMULLsv4i32 >+ 1048U, // VMULLsv8i16 >+ 1048U, // VMULLuv2i64 >+ 1048U, // VMULLuv4i32 >+ 1048U, // VMULLuv8i16 >+ 247328U, // VMULS >+ 247328U, // VMULfd >+ 247328U, // VMULfq >+ 0U, // VMULpd >+ 0U, // VMULpq >+ 427552U, // VMULslfd >+ 427552U, // VMULslfq >+ 8728U, // VMULslv2i32 >+ 8728U, // VMULslv4i16 >+ 8728U, // VMULslv4i32 >+ 8728U, // VMULslv8i16 >+ 1048U, // VMULv16i8 >+ 1048U, // VMULv2i32 >+ 1048U, // VMULv4i16 >+ 1048U, // VMULv4i32 >+ 1048U, // VMULv8i16 >+ 1048U, // VMULv8i8 >+ 1024U, // VMVNd >+ 1024U, // VMVNq >+ 0U, // VMVNv2i32 >+ 0U, // VMVNv4i16 >+ 0U, // VMVNv4i32 >+ 0U, // VMVNv8i16 >+ 56U, // VNEGD >+ 56U, // VNEGS >+ 56U, // VNEGf32q >+ 56U, // VNEGfd >+ 0U, // VNEGs16d >+ 0U, // VNEGs16q >+ 0U, // VNEGs32d >+ 0U, // VNEGs32q >+ 0U, // VNEGs8d >+ 0U, // VNEGs8q >+ 249378U, // VNMLAD >+ 249378U, // VNMLAS >+ 249378U, // VNMLSD >+ 249378U, // VNMLSS >+ 247328U, // VNMULD >+ 247328U, // VNMULS >+ 0U, // VORNd >+ 0U, // VORNq >+ 0U, // VORRd >+ 0U, // VORRiv2i32 >+ 0U, // VORRiv4i16 >+ 0U, // VORRiv4i32 >+ 0U, // VORRiv8i16 >+ 0U, // VORRq >+ 0U, // VPADALsv16i8 >+ 0U, // VPADALsv2i32 >+ 0U, // VPADALsv4i16 >+ 0U, // VPADALsv4i32 >+ 0U, // VPADALsv8i16 >+ 0U, // VPADALsv8i8 >+ 0U, // VPADALuv16i8 >+ 0U, // VPADALuv2i32 >+ 0U, // VPADALuv4i16 >+ 0U, // VPADALuv4i32 >+ 0U, // VPADALuv8i16 >+ 0U, // VPADALuv8i8 >+ 0U, // VPADDLsv16i8 >+ 0U, // VPADDLsv2i32 >+ 0U, // VPADDLsv4i16 >+ 0U, // VPADDLsv4i32 >+ 0U, // VPADDLsv8i16 >+ 0U, // VPADDLsv8i8 >+ 0U, // VPADDLuv16i8 >+ 0U, // VPADDLuv2i32 >+ 0U, // VPADDLuv4i16 >+ 0U, // VPADDLuv4i32 >+ 0U, // VPADDLuv8i16 >+ 0U, // VPADDLuv8i8 >+ 247328U, // VPADDf >+ 1048U, // VPADDi16 >+ 1048U, // VPADDi32 >+ 1048U, // VPADDi8 >+ 247328U, // VPMAXf >+ 1048U, // VPMAXs16 >+ 1048U, // VPMAXs32 >+ 1048U, // VPMAXs8 >+ 1048U, // VPMAXu16 >+ 1048U, // VPMAXu32 >+ 1048U, // VPMAXu8 >+ 247328U, // VPMINf >+ 1048U, // VPMINs16 >+ 1048U, // VPMINs32 >+ 1048U, // VPMINs8 >+ 1048U, // VPMINu16 >+ 1048U, // VPMINu32 >+ 1048U, // VPMINu8 >+ 0U, // VQABSv16i8 >+ 0U, // VQABSv2i32 >+ 0U, // VQABSv4i16 >+ 0U, // VQABSv4i32 >+ 0U, // VQABSv8i16 >+ 0U, // VQABSv8i8 >+ 1048U, // VQADDsv16i8 >+ 1048U, // VQADDsv1i64 >+ 1048U, // VQADDsv2i32 >+ 1048U, // VQADDsv2i64 >+ 1048U, // VQADDsv4i16 >+ 1048U, // VQADDsv4i32 >+ 1048U, // VQADDsv8i16 >+ 1048U, // VQADDsv8i8 >+ 1048U, // VQADDuv16i8 >+ 1048U, // VQADDuv1i64 >+ 1048U, // VQADDuv2i32 >+ 1048U, // VQADDuv2i64 >+ 1048U, // VQADDuv4i16 >+ 1048U, // VQADDuv4i32 >+ 1048U, // VQADDuv8i16 >+ 1048U, // VQADDuv8i8 >+ 8352U, // VQDMLALslv2i32 >+ 8352U, // VQDMLALslv4i16 >+ 1184U, // VQDMLALv2i64 >+ 1184U, // VQDMLALv4i32 >+ 8352U, // VQDMLSLslv2i32 >+ 8352U, // VQDMLSLslv4i16 >+ 1184U, // VQDMLSLv2i64 >+ 1184U, // VQDMLSLv4i32 >+ 8728U, // VQDMULHslv2i32 >+ 8728U, // VQDMULHslv4i16 >+ 8728U, // VQDMULHslv4i32 >+ 8728U, // VQDMULHslv8i16 >+ 1048U, // VQDMULHv2i32 >+ 1048U, // VQDMULHv4i16 >+ 1048U, // VQDMULHv4i32 >+ 1048U, // VQDMULHv8i16 >+ 8728U, // VQDMULLslv2i32 >+ 8728U, // VQDMULLslv4i16 >+ 1048U, // VQDMULLv2i64 >+ 1048U, // VQDMULLv4i32 >+ 0U, // VQMOVNsuv2i32 >+ 0U, // VQMOVNsuv4i16 >+ 0U, // VQMOVNsuv8i8 >+ 0U, // VQMOVNsv2i32 >+ 0U, // VQMOVNsv4i16 >+ 0U, // VQMOVNsv8i8 >+ 0U, // VQMOVNuv2i32 >+ 0U, // VQMOVNuv4i16 >+ 0U, // VQMOVNuv8i8 >+ 0U, // VQNEGv16i8 >+ 0U, // VQNEGv2i32 >+ 0U, // VQNEGv4i16 >+ 0U, // VQNEGv4i32 >+ 0U, // VQNEGv8i16 >+ 0U, // VQNEGv8i8 >+ 8728U, // VQRDMULHslv2i32 >+ 8728U, // VQRDMULHslv4i16 >+ 8728U, // VQRDMULHslv4i32 >+ 8728U, // VQRDMULHslv8i16 >+ 1048U, // VQRDMULHv2i32 >+ 1048U, // VQRDMULHv4i16 >+ 1048U, // VQRDMULHv4i32 >+ 1048U, // VQRDMULHv8i16 >+ 1048U, // VQRSHLsv16i8 >+ 1048U, // VQRSHLsv1i64 >+ 1048U, // VQRSHLsv2i32 >+ 1048U, // VQRSHLsv2i64 >+ 1048U, // VQRSHLsv4i16 >+ 1048U, // VQRSHLsv4i32 >+ 1048U, // VQRSHLsv8i16 >+ 1048U, // VQRSHLsv8i8 >+ 1048U, // VQRSHLuv16i8 >+ 1048U, // VQRSHLuv1i64 >+ 1048U, // VQRSHLuv2i32 >+ 1048U, // VQRSHLuv2i64 >+ 1048U, // VQRSHLuv4i16 >+ 1048U, // VQRSHLuv4i32 >+ 1048U, // VQRSHLuv8i16 >+ 1048U, // VQRSHLuv8i8 >+ 1048U, // VQRSHRNsv2i32 >+ 1048U, // VQRSHRNsv4i16 >+ 1048U, // VQRSHRNsv8i8 >+ 1048U, // VQRSHRNuv2i32 >+ 1048U, // VQRSHRNuv4i16 >+ 1048U, // VQRSHRNuv8i8 >+ 1048U, // VQRSHRUNv2i32 >+ 1048U, // VQRSHRUNv4i16 >+ 1048U, // VQRSHRUNv8i8 >+ 1048U, // VQSHLsiv16i8 >+ 1048U, // VQSHLsiv1i64 >+ 1048U, // VQSHLsiv2i32 >+ 1048U, // VQSHLsiv2i64 >+ 1048U, // VQSHLsiv4i16 >+ 1048U, // VQSHLsiv4i32 >+ 1048U, // VQSHLsiv8i16 >+ 1048U, // VQSHLsiv8i8 >+ 1048U, // VQSHLsuv16i8 >+ 1048U, // VQSHLsuv1i64 >+ 1048U, // VQSHLsuv2i32 >+ 1048U, // VQSHLsuv2i64 >+ 1048U, // VQSHLsuv4i16 >+ 1048U, // VQSHLsuv4i32 >+ 1048U, // VQSHLsuv8i16 >+ 1048U, // VQSHLsuv8i8 >+ 1048U, // VQSHLsv16i8 >+ 1048U, // VQSHLsv1i64 >+ 1048U, // VQSHLsv2i32 >+ 1048U, // VQSHLsv2i64 >+ 1048U, // VQSHLsv4i16 >+ 1048U, // VQSHLsv4i32 >+ 1048U, // VQSHLsv8i16 >+ 1048U, // VQSHLsv8i8 >+ 1048U, // VQSHLuiv16i8 >+ 1048U, // VQSHLuiv1i64 >+ 1048U, // VQSHLuiv2i32 >+ 1048U, // VQSHLuiv2i64 >+ 1048U, // VQSHLuiv4i16 >+ 1048U, // VQSHLuiv4i32 >+ 1048U, // VQSHLuiv8i16 >+ 1048U, // VQSHLuiv8i8 >+ 1048U, // VQSHLuv16i8 >+ 1048U, // VQSHLuv1i64 >+ 1048U, // VQSHLuv2i32 >+ 1048U, // VQSHLuv2i64 >+ 1048U, // VQSHLuv4i16 >+ 1048U, // VQSHLuv4i32 >+ 1048U, // VQSHLuv8i16 >+ 1048U, // VQSHLuv8i8 >+ 1048U, // VQSHRNsv2i32 >+ 1048U, // VQSHRNsv4i16 >+ 1048U, // VQSHRNsv8i8 >+ 1048U, // VQSHRNuv2i32 >+ 1048U, // VQSHRNuv4i16 >+ 1048U, // VQSHRNuv8i8 >+ 1048U, // VQSHRUNv2i32 >+ 1048U, // VQSHRUNv4i16 >+ 1048U, // VQSHRUNv8i8 >+ 1048U, // VQSUBsv16i8 >+ 1048U, // VQSUBsv1i64 >+ 1048U, // VQSUBsv2i32 >+ 1048U, // VQSUBsv2i64 >+ 1048U, // VQSUBsv4i16 >+ 1048U, // VQSUBsv4i32 >+ 1048U, // VQSUBsv8i16 >+ 1048U, // VQSUBsv8i8 >+ 1048U, // VQSUBuv16i8 >+ 1048U, // VQSUBuv1i64 >+ 1048U, // VQSUBuv2i32 >+ 1048U, // VQSUBuv2i64 >+ 1048U, // VQSUBuv4i16 >+ 1048U, // VQSUBuv4i32 >+ 1048U, // VQSUBuv8i16 >+ 1048U, // VQSUBuv8i8 >+ 1048U, // VRADDHNv2i32 >+ 1048U, // VRADDHNv4i16 >+ 1048U, // VRADDHNv8i8 >+ 0U, // VRECPEd >+ 56U, // VRECPEfd >+ 56U, // VRECPEfq >+ 0U, // VRECPEq >+ 247328U, // VRECPSfd >+ 247328U, // VRECPSfq >+ 1024U, // VREV16d8 >+ 1024U, // VREV16q8 >+ 1024U, // VREV32d16 >+ 1024U, // VREV32d8 >+ 1024U, // VREV32q16 >+ 1024U, // VREV32q8 >+ 1024U, // VREV64d16 >+ 1024U, // VREV64d32 >+ 1024U, // VREV64d8 >+ 1024U, // VREV64q16 >+ 1024U, // VREV64q32 >+ 1024U, // VREV64q8 >+ 1048U, // VRHADDsv16i8 >+ 1048U, // VRHADDsv2i32 >+ 1048U, // VRHADDsv4i16 >+ 1048U, // VRHADDsv4i32 >+ 1048U, // VRHADDsv8i16 >+ 1048U, // VRHADDsv8i8 >+ 1048U, // VRHADDuv16i8 >+ 1048U, // VRHADDuv2i32 >+ 1048U, // VRHADDuv4i16 >+ 1048U, // VRHADDuv4i32 >+ 1048U, // VRHADDuv8i16 >+ 1048U, // VRHADDuv8i8 >+ 0U, // VRINTAD >+ 0U, // VRINTAND >+ 0U, // VRINTANQ >+ 0U, // VRINTAS >+ 0U, // VRINTMD >+ 0U, // VRINTMND >+ 0U, // VRINTMNQ >+ 0U, // VRINTMS >+ 0U, // VRINTND >+ 0U, // VRINTNND >+ 0U, // VRINTNNQ >+ 0U, // VRINTNS >+ 0U, // VRINTPD >+ 0U, // VRINTPND >+ 0U, // VRINTPNQ >+ 0U, // VRINTPS >+ 56U, // VRINTRD >+ 56U, // VRINTRS >+ 56U, // VRINTXD >+ 0U, // VRINTXND >+ 0U, // VRINTXNQ >+ 56U, // VRINTXS >+ 56U, // VRINTZD >+ 0U, // VRINTZND >+ 0U, // VRINTZNQ >+ 56U, // VRINTZS >+ 1048U, // VRSHLsv16i8 >+ 1048U, // VRSHLsv1i64 >+ 1048U, // VRSHLsv2i32 >+ 1048U, // VRSHLsv2i64 >+ 1048U, // VRSHLsv4i16 >+ 1048U, // VRSHLsv4i32 >+ 1048U, // VRSHLsv8i16 >+ 1048U, // VRSHLsv8i8 >+ 1048U, // VRSHLuv16i8 >+ 1048U, // VRSHLuv1i64 >+ 1048U, // VRSHLuv2i32 >+ 1048U, // VRSHLuv2i64 >+ 1048U, // VRSHLuv4i16 >+ 1048U, // VRSHLuv4i32 >+ 1048U, // VRSHLuv8i16 >+ 1048U, // VRSHLuv8i8 >+ 1048U, // VRSHRNv2i32 >+ 1048U, // VRSHRNv4i16 >+ 1048U, // VRSHRNv8i8 >+ 1048U, // VRSHRsv16i8 >+ 1048U, // VRSHRsv1i64 >+ 1048U, // VRSHRsv2i32 >+ 1048U, // VRSHRsv2i64 >+ 1048U, // VRSHRsv4i16 >+ 1048U, // VRSHRsv4i32 >+ 1048U, // VRSHRsv8i16 >+ 1048U, // VRSHRsv8i8 >+ 1048U, // VRSHRuv16i8 >+ 1048U, // VRSHRuv1i64 >+ 1048U, // VRSHRuv2i32 >+ 1048U, // VRSHRuv2i64 >+ 1048U, // VRSHRuv4i16 >+ 1048U, // VRSHRuv4i32 >+ 1048U, // VRSHRuv8i16 >+ 1048U, // VRSHRuv8i8 >+ 0U, // VRSQRTEd >+ 56U, // VRSQRTEfd >+ 56U, // VRSQRTEfq >+ 0U, // VRSQRTEq >+ 247328U, // VRSQRTSfd >+ 247328U, // VRSQRTSfq >+ 1184U, // VRSRAsv16i8 >+ 1184U, // VRSRAsv1i64 >+ 1184U, // VRSRAsv2i32 >+ 1184U, // VRSRAsv2i64 >+ 1184U, // VRSRAsv4i16 >+ 1184U, // VRSRAsv4i32 >+ 1184U, // VRSRAsv8i16 >+ 1184U, // VRSRAsv8i8 >+ 1184U, // VRSRAuv16i8 >+ 1184U, // VRSRAuv1i64 >+ 1184U, // VRSRAuv2i32 >+ 1184U, // VRSRAuv2i64 >+ 1184U, // VRSRAuv4i16 >+ 1184U, // VRSRAuv4i32 >+ 1184U, // VRSRAuv8i16 >+ 1184U, // VRSRAuv8i8 >+ 1048U, // VRSUBHNv2i32 >+ 1048U, // VRSUBHNv4i16 >+ 1048U, // VRSUBHNv8i8 >+ 1048U, // VSELEQD >+ 1048U, // VSELEQS >+ 1048U, // VSELGED >+ 1048U, // VSELGES >+ 1048U, // VSELGTD >+ 1048U, // VSELGTS >+ 1048U, // VSELVSD >+ 1048U, // VSELVSS >+ 6U, // VSETLNi16 >+ 6U, // VSETLNi32 >+ 6U, // VSETLNi8 >+ 1048U, // VSHLLi16 >+ 1048U, // VSHLLi32 >+ 1048U, // VSHLLi8 >+ 1048U, // VSHLLsv2i64 >+ 1048U, // VSHLLsv4i32 >+ 1048U, // VSHLLsv8i16 >+ 1048U, // VSHLLuv2i64 >+ 1048U, // VSHLLuv4i32 >+ 1048U, // VSHLLuv8i16 >+ 1048U, // VSHLiv16i8 >+ 1048U, // VSHLiv1i64 >+ 1048U, // VSHLiv2i32 >+ 1048U, // VSHLiv2i64 >+ 1048U, // VSHLiv4i16 >+ 1048U, // VSHLiv4i32 >+ 1048U, // VSHLiv8i16 >+ 1048U, // VSHLiv8i8 >+ 1048U, // VSHLsv16i8 >+ 1048U, // VSHLsv1i64 >+ 1048U, // VSHLsv2i32 >+ 1048U, // VSHLsv2i64 >+ 1048U, // VSHLsv4i16 >+ 1048U, // VSHLsv4i32 >+ 1048U, // VSHLsv8i16 >+ 1048U, // VSHLsv8i8 >+ 1048U, // VSHLuv16i8 >+ 1048U, // VSHLuv1i64 >+ 1048U, // VSHLuv2i32 >+ 1048U, // VSHLuv2i64 >+ 1048U, // VSHLuv4i16 >+ 1048U, // VSHLuv4i32 >+ 1048U, // VSHLuv8i16 >+ 1048U, // VSHLuv8i8 >+ 1048U, // VSHRNv2i32 >+ 1048U, // VSHRNv4i16 >+ 1048U, // VSHRNv8i8 >+ 1048U, // VSHRsv16i8 >+ 1048U, // VSHRsv1i64 >+ 1048U, // VSHRsv2i32 >+ 1048U, // VSHRsv2i64 >+ 1048U, // VSHRsv4i16 >+ 1048U, // VSHRsv4i32 >+ 1048U, // VSHRsv8i16 >+ 1048U, // VSHRsv8i8 >+ 1048U, // VSHRuv16i8 >+ 1048U, // VSHRuv1i64 >+ 1048U, // VSHRuv2i32 >+ 1048U, // VSHRuv2i64 >+ 1048U, // VSHRuv4i16 >+ 1048U, // VSHRuv4i32 >+ 1048U, // VSHRuv8i16 >+ 1048U, // VSHRuv8i8 >+ 0U, // VSHTOD >+ 0U, // VSHTOS >+ 0U, // VSITOD >+ 0U, // VSITOS >+ 262168U, // VSLIv16i8 >+ 262168U, // VSLIv1i64 >+ 262168U, // VSLIv2i32 >+ 262168U, // VSLIv2i64 >+ 262168U, // VSLIv4i16 >+ 262168U, // VSLIv4i32 >+ 262168U, // VSLIv8i16 >+ 262168U, // VSLIv8i8 >+ 6U, // VSLTOD >+ 6U, // VSLTOS >+ 56U, // VSQRTD >+ 56U, // VSQRTS >+ 1184U, // VSRAsv16i8 >+ 1184U, // VSRAsv1i64 >+ 1184U, // VSRAsv2i32 >+ 1184U, // VSRAsv2i64 >+ 1184U, // VSRAsv4i16 >+ 1184U, // VSRAsv4i32 >+ 1184U, // VSRAsv8i16 >+ 1184U, // VSRAsv8i8 >+ 1184U, // VSRAuv16i8 >+ 1184U, // VSRAuv1i64 >+ 1184U, // VSRAuv2i32 >+ 1184U, // VSRAuv2i64 >+ 1184U, // VSRAuv4i16 >+ 1184U, // VSRAuv4i32 >+ 1184U, // VSRAuv8i16 >+ 1184U, // VSRAuv8i8 >+ 262168U, // VSRIv16i8 >+ 262168U, // VSRIv1i64 >+ 262168U, // VSRIv2i32 >+ 262168U, // VSRIv2i64 >+ 262168U, // VSRIv4i16 >+ 262168U, // VSRIv4i32 >+ 262168U, // VSRIv8i16 >+ 262168U, // VSRIv8i8 >+ 275U, // VST1LNd16 >+ 10769179U, // VST1LNd16_UPD >+ 275U, // VST1LNd32 >+ 10769179U, // VST1LNd32_UPD >+ 275U, // VST1LNd8 >+ 10769179U, // VST1LNd8_UPD >+ 1240U, // VST1LNdAsm_16 >+ 1240U, // VST1LNdAsm_32 >+ 1240U, // VST1LNdAsm_8 >+ 5336U, // VST1LNdWB_fixed_Asm_16 >+ 5336U, // VST1LNdWB_fixed_Asm_32 >+ 5336U, // VST1LNdWB_fixed_Asm_8 >+ 311512U, // VST1LNdWB_register_Asm_16 >+ 311512U, // VST1LNdWB_register_Asm_32 >+ 311512U, // VST1LNdWB_register_Asm_8 >+ 0U, // VST1LNq16Pseudo >+ 0U, // VST1LNq16Pseudo_UPD >+ 0U, // VST1LNq32Pseudo >+ 0U, // VST1LNq32Pseudo_UPD >+ 0U, // VST1LNq8Pseudo >+ 0U, // VST1LNq8Pseudo_UPD >+ 0U, // VST1d16 >+ 0U, // VST1d16Q >+ 0U, // VST1d16Qwb_fixed >+ 0U, // VST1d16Qwb_register >+ 0U, // VST1d16T >+ 0U, // VST1d16Twb_fixed >+ 0U, // VST1d16Twb_register >+ 0U, // VST1d16wb_fixed >+ 0U, // VST1d16wb_register >+ 0U, // VST1d32 >+ 0U, // VST1d32Q >+ 0U, // VST1d32Qwb_fixed >+ 0U, // VST1d32Qwb_register >+ 0U, // VST1d32T >+ 0U, // VST1d32Twb_fixed >+ 0U, // VST1d32Twb_register >+ 0U, // VST1d32wb_fixed >+ 0U, // VST1d32wb_register >+ 0U, // VST1d64 >+ 0U, // VST1d64Q >+ 0U, // VST1d64QPseudo >+ 0U, // VST1d64QPseudoWB_fixed >+ 0U, // VST1d64QPseudoWB_register >+ 0U, // VST1d64Qwb_fixed >+ 0U, // VST1d64Qwb_register >+ 0U, // VST1d64T >+ 0U, // VST1d64TPseudo >+ 0U, // VST1d64TPseudoWB_fixed >+ 0U, // VST1d64TPseudoWB_register >+ 0U, // VST1d64Twb_fixed >+ 0U, // VST1d64Twb_register >+ 0U, // VST1d64wb_fixed >+ 0U, // VST1d64wb_register >+ 0U, // VST1d8 >+ 0U, // VST1d8Q >+ 0U, // VST1d8Qwb_fixed >+ 0U, // VST1d8Qwb_register >+ 0U, // VST1d8T >+ 0U, // VST1d8Twb_fixed >+ 0U, // VST1d8Twb_register >+ 0U, // VST1d8wb_fixed >+ 0U, // VST1d8wb_register >+ 0U, // VST1q16 >+ 0U, // VST1q16wb_fixed >+ 0U, // VST1q16wb_register >+ 0U, // VST1q32 >+ 0U, // VST1q32wb_fixed >+ 0U, // VST1q32wb_register >+ 0U, // VST1q64 >+ 0U, // VST1q64wb_fixed >+ 0U, // VST1q64wb_register >+ 0U, // VST1q8 >+ 0U, // VST1q8wb_fixed >+ 0U, // VST1q8wb_register >+ 110368459U, // VST2LNd16 >+ 0U, // VST2LNd16Pseudo >+ 0U, // VST2LNd16Pseudo_UPD >+ 448211U, // VST2LNd16_UPD >+ 110368459U, // VST2LNd32 >+ 0U, // VST2LNd32Pseudo >+ 0U, // VST2LNd32Pseudo_UPD >+ 448211U, // VST2LNd32_UPD >+ 110368459U, // VST2LNd8 >+ 0U, // VST2LNd8Pseudo >+ 0U, // VST2LNd8Pseudo_UPD >+ 448211U, // VST2LNd8_UPD >+ 1240U, // VST2LNdAsm_16 >+ 1240U, // VST2LNdAsm_32 >+ 1240U, // VST2LNdAsm_8 >+ 5336U, // VST2LNdWB_fixed_Asm_16 >+ 5336U, // VST2LNdWB_fixed_Asm_32 >+ 5336U, // VST2LNdWB_fixed_Asm_8 >+ 311512U, // VST2LNdWB_register_Asm_16 >+ 311512U, // VST2LNdWB_register_Asm_32 >+ 311512U, // VST2LNdWB_register_Asm_8 >+ 110368459U, // VST2LNq16 >+ 0U, // VST2LNq16Pseudo >+ 0U, // VST2LNq16Pseudo_UPD >+ 448211U, // VST2LNq16_UPD >+ 110368459U, // VST2LNq32 >+ 0U, // VST2LNq32Pseudo >+ 0U, // VST2LNq32Pseudo_UPD >+ 448211U, // VST2LNq32_UPD >+ 1240U, // VST2LNqAsm_16 >+ 1240U, // VST2LNqAsm_32 >+ 5336U, // VST2LNqWB_fixed_Asm_16 >+ 5336U, // VST2LNqWB_fixed_Asm_32 >+ 311512U, // VST2LNqWB_register_Asm_16 >+ 311512U, // VST2LNqWB_register_Asm_32 >+ 0U, // VST2b16 >+ 0U, // VST2b16wb_fixed >+ 0U, // VST2b16wb_register >+ 0U, // VST2b32 >+ 0U, // VST2b32wb_fixed >+ 0U, // VST2b32wb_register >+ 0U, // VST2b8 >+ 0U, // VST2b8wb_fixed >+ 0U, // VST2b8wb_register >+ 0U, // VST2d16 >+ 0U, // VST2d16wb_fixed >+ 0U, // VST2d16wb_register >+ 0U, // VST2d32 >+ 0U, // VST2d32wb_fixed >+ 0U, // VST2d32wb_register >+ 0U, // VST2d8 >+ 0U, // VST2d8wb_fixed >+ 0U, // VST2d8wb_register >+ 0U, // VST2q16 >+ 0U, // VST2q16Pseudo >+ 0U, // VST2q16PseudoWB_fixed >+ 0U, // VST2q16PseudoWB_register >+ 0U, // VST2q16wb_fixed >+ 0U, // VST2q16wb_register >+ 0U, // VST2q32 >+ 0U, // VST2q32Pseudo >+ 0U, // VST2q32PseudoWB_fixed >+ 0U, // VST2q32PseudoWB_register >+ 0U, // VST2q32wb_fixed >+ 0U, // VST2q32wb_register >+ 0U, // VST2q8 >+ 0U, // VST2q8Pseudo >+ 0U, // VST2q8PseudoWB_fixed >+ 0U, // VST2q8PseudoWB_register >+ 0U, // VST2q8wb_fixed >+ 0U, // VST2q8wb_register >+ 127145755U, // VST3LNd16 >+ 0U, // VST3LNd16Pseudo >+ 0U, // VST3LNd16Pseudo_UPD >+ 291U, // VST3LNd16_UPD >+ 127145755U, // VST3LNd32 >+ 0U, // VST3LNd32Pseudo >+ 0U, // VST3LNd32Pseudo_UPD >+ 291U, // VST3LNd32_UPD >+ 127145755U, // VST3LNd8 >+ 0U, // VST3LNd8Pseudo >+ 0U, // VST3LNd8Pseudo_UPD >+ 291U, // VST3LNd8_UPD >+ 1240U, // VST3LNdAsm_16 >+ 1240U, // VST3LNdAsm_32 >+ 1240U, // VST3LNdAsm_8 >+ 5336U, // VST3LNdWB_fixed_Asm_16 >+ 5336U, // VST3LNdWB_fixed_Asm_32 >+ 5336U, // VST3LNdWB_fixed_Asm_8 >+ 311512U, // VST3LNdWB_register_Asm_16 >+ 311512U, // VST3LNdWB_register_Asm_32 >+ 311512U, // VST3LNdWB_register_Asm_8 >+ 127145755U, // VST3LNq16 >+ 0U, // VST3LNq16Pseudo >+ 0U, // VST3LNq16Pseudo_UPD >+ 291U, // VST3LNq16_UPD >+ 127145755U, // VST3LNq32 >+ 0U, // VST3LNq32Pseudo >+ 0U, // VST3LNq32Pseudo_UPD >+ 291U, // VST3LNq32_UPD >+ 1240U, // VST3LNqAsm_16 >+ 1240U, // VST3LNqAsm_32 >+ 5336U, // VST3LNqWB_fixed_Asm_16 >+ 5336U, // VST3LNqWB_fixed_Asm_32 >+ 311512U, // VST3LNqWB_register_Asm_16 >+ 311512U, // VST3LNqWB_register_Asm_32 >+ 142917792U, // VST3d16 >+ 0U, // VST3d16Pseudo >+ 0U, // VST3d16Pseudo_UPD >+ 9512U, // VST3d16_UPD >+ 142917792U, // VST3d32 >+ 0U, // VST3d32Pseudo >+ 0U, // VST3d32Pseudo_UPD >+ 9512U, // VST3d32_UPD >+ 142917792U, // VST3d8 >+ 0U, // VST3d8Pseudo >+ 0U, // VST3d8Pseudo_UPD >+ 9512U, // VST3d8_UPD >+ 59U, // VST3dAsm_16 >+ 59U, // VST3dAsm_32 >+ 59U, // VST3dAsm_8 >+ 195U, // VST3dWB_fixed_Asm_16 >+ 195U, // VST3dWB_fixed_Asm_32 >+ 195U, // VST3dWB_fixed_Asm_8 >+ 249379U, // VST3dWB_register_Asm_16 >+ 249379U, // VST3dWB_register_Asm_32 >+ 249379U, // VST3dWB_register_Asm_8 >+ 142917792U, // VST3q16 >+ 0U, // VST3q16Pseudo_UPD >+ 9512U, // VST3q16_UPD >+ 0U, // VST3q16oddPseudo >+ 0U, // VST3q16oddPseudo_UPD >+ 142917792U, // VST3q32 >+ 0U, // VST3q32Pseudo_UPD >+ 9512U, // VST3q32_UPD >+ 0U, // VST3q32oddPseudo >+ 0U, // VST3q32oddPseudo_UPD >+ 142917792U, // VST3q8 >+ 0U, // VST3q8Pseudo_UPD >+ 9512U, // VST3q8_UPD >+ 0U, // VST3q8oddPseudo >+ 0U, // VST3q8oddPseudo_UPD >+ 0U, // VST3qAsm_16 >+ 0U, // VST3qAsm_32 >+ 0U, // VST3qAsm_8 >+ 4U, // VST3qWB_fixed_Asm_16 >+ 4U, // VST3qWB_fixed_Asm_32 >+ 4U, // VST3qWB_fixed_Asm_8 >+ 1184U, // VST3qWB_register_Asm_16 >+ 1184U, // VST3qWB_register_Asm_32 >+ 1184U, // VST3qWB_register_Asm_8 >+ 160700115U, // VST4LNd16 >+ 0U, // VST4LNd16Pseudo >+ 0U, // VST4LNd16Pseudo_UPD >+ 9955U, // VST4LNd16_UPD >+ 160700115U, // VST4LNd32 >+ 0U, // VST4LNd32Pseudo >+ 0U, // VST4LNd32Pseudo_UPD >+ 9955U, // VST4LNd32_UPD >+ 160700115U, // VST4LNd8 >+ 0U, // VST4LNd8Pseudo >+ 0U, // VST4LNd8Pseudo_UPD >+ 9955U, // VST4LNd8_UPD >+ 1240U, // VST4LNdAsm_16 >+ 1240U, // VST4LNdAsm_32 >+ 1240U, // VST4LNdAsm_8 >+ 5336U, // VST4LNdWB_fixed_Asm_16 >+ 5336U, // VST4LNdWB_fixed_Asm_32 >+ 5336U, // VST4LNdWB_fixed_Asm_8 >+ 311512U, // VST4LNdWB_register_Asm_16 >+ 311512U, // VST4LNdWB_register_Asm_32 >+ 311512U, // VST4LNdWB_register_Asm_8 >+ 160700115U, // VST4LNq16 >+ 0U, // VST4LNq16Pseudo >+ 0U, // VST4LNq16Pseudo_UPD >+ 9955U, // VST4LNq16_UPD >+ 160700115U, // VST4LNq32 >+ 0U, // VST4LNq32Pseudo >+ 0U, // VST4LNq32Pseudo_UPD >+ 9955U, // VST4LNq32_UPD >+ 1240U, // VST4LNqAsm_16 >+ 1240U, // VST4LNqAsm_32 >+ 5336U, // VST4LNqWB_fixed_Asm_16 >+ 5336U, // VST4LNqWB_fixed_Asm_32 >+ 311512U, // VST4LNqWB_register_Asm_16 >+ 311512U, // VST4LNqWB_register_Asm_32 >+ 169132192U, // VST4d16 >+ 0U, // VST4d16Pseudo >+ 0U, // VST4d16Pseudo_UPD >+ 459048U, // VST4d16_UPD >+ 169132192U, // VST4d32 >+ 0U, // VST4d32Pseudo >+ 0U, // VST4d32Pseudo_UPD >+ 459048U, // VST4d32_UPD >+ 169132192U, // VST4d8 >+ 0U, // VST4d8Pseudo >+ 0U, // VST4d8Pseudo_UPD >+ 459048U, // VST4d8_UPD >+ 59U, // VST4dAsm_16 >+ 59U, // VST4dAsm_32 >+ 59U, // VST4dAsm_8 >+ 195U, // VST4dWB_fixed_Asm_16 >+ 195U, // VST4dWB_fixed_Asm_32 >+ 195U, // VST4dWB_fixed_Asm_8 >+ 249379U, // VST4dWB_register_Asm_16 >+ 249379U, // VST4dWB_register_Asm_32 >+ 249379U, // VST4dWB_register_Asm_8 >+ 169132192U, // VST4q16 >+ 0U, // VST4q16Pseudo_UPD >+ 459048U, // VST4q16_UPD >+ 0U, // VST4q16oddPseudo >+ 0U, // VST4q16oddPseudo_UPD >+ 169132192U, // VST4q32 >+ 0U, // VST4q32Pseudo_UPD >+ 459048U, // VST4q32_UPD >+ 0U, // VST4q32oddPseudo >+ 0U, // VST4q32oddPseudo_UPD >+ 169132192U, // VST4q8 >+ 0U, // VST4q8Pseudo_UPD >+ 459048U, // VST4q8_UPD >+ 0U, // VST4q8oddPseudo >+ 0U, // VST4q8oddPseudo_UPD >+ 0U, // VST4qAsm_16 >+ 0U, // VST4qAsm_32 >+ 0U, // VST4qAsm_8 >+ 4U, // VST4qWB_fixed_Asm_16 >+ 4U, // VST4qWB_fixed_Asm_32 >+ 4U, // VST4qWB_fixed_Asm_8 >+ 1184U, // VST4qWB_register_Asm_16 >+ 1184U, // VST4qWB_register_Asm_32 >+ 1184U, // VST4qWB_register_Asm_8 >+ 57U, // VSTMDDB_UPD >+ 1088U, // VSTMDIA >+ 57U, // VSTMDIA_UPD >+ 0U, // VSTMQIA >+ 57U, // VSTMSDB_UPD >+ 1088U, // VSTMSIA >+ 57U, // VSTMSIA_UPD >+ 264U, // VSTRD >+ 264U, // VSTRS >+ 247328U, // VSUBD >+ 1048U, // VSUBHNv2i32 >+ 1048U, // VSUBHNv4i16 >+ 1048U, // VSUBHNv8i8 >+ 1048U, // VSUBLsv2i64 >+ 1048U, // VSUBLsv4i32 >+ 1048U, // VSUBLsv8i16 >+ 1048U, // VSUBLuv2i64 >+ 1048U, // VSUBLuv4i32 >+ 1048U, // VSUBLuv8i16 >+ 247328U, // VSUBS >+ 1048U, // VSUBWsv2i64 >+ 1048U, // VSUBWsv4i32 >+ 1048U, // VSUBWsv8i16 >+ 1048U, // VSUBWuv2i64 >+ 1048U, // VSUBWuv4i32 >+ 1048U, // VSUBWuv8i16 >+ 247328U, // VSUBfd >+ 247328U, // VSUBfq >+ 1048U, // VSUBv16i8 >+ 1048U, // VSUBv1i64 >+ 1048U, // VSUBv2i32 >+ 1048U, // VSUBv2i64 >+ 1048U, // VSUBv4i16 >+ 1048U, // VSUBv4i32 >+ 1048U, // VSUBv8i16 >+ 1048U, // VSUBv8i8 >+ 1024U, // VSWPd >+ 1024U, // VSWPq >+ 304U, // VTBL1 >+ 312U, // VTBL2 >+ 320U, // VTBL3 >+ 0U, // VTBL3Pseudo >+ 328U, // VTBL4 >+ 0U, // VTBL4Pseudo >+ 336U, // VTBX1 >+ 344U, // VTBX2 >+ 352U, // VTBX3 >+ 0U, // VTBX3Pseudo >+ 360U, // VTBX4 >+ 0U, // VTBX4Pseudo >+ 0U, // VTOSHD >+ 0U, // VTOSHS >+ 0U, // VTOSIRD >+ 0U, // VTOSIRS >+ 0U, // VTOSIZD >+ 0U, // VTOSIZS >+ 6U, // VTOSLD >+ 6U, // VTOSLS >+ 0U, // VTOUHD >+ 0U, // VTOUHS >+ 0U, // VTOUIRD >+ 0U, // VTOUIRS >+ 0U, // VTOUIZD >+ 0U, // VTOUIZS >+ 6U, // VTOULD >+ 6U, // VTOULS >+ 1024U, // VTRNd16 >+ 1024U, // VTRNd32 >+ 1024U, // VTRNd8 >+ 1024U, // VTRNq16 >+ 1024U, // VTRNq32 >+ 1024U, // VTRNq8 >+ 0U, // VTSTv16i8 >+ 0U, // VTSTv2i32 >+ 0U, // VTSTv4i16 >+ 0U, // VTSTv4i32 >+ 0U, // VTSTv8i16 >+ 0U, // VTSTv8i8 >+ 0U, // VUHTOD >+ 0U, // VUHTOS >+ 0U, // VUITOD >+ 0U, // VUITOS >+ 6U, // VULTOD >+ 6U, // VULTOS >+ 1024U, // VUZPd16 >+ 1024U, // VUZPd8 >+ 1024U, // VUZPq16 >+ 1024U, // VUZPq32 >+ 1024U, // VUZPq8 >+ 1024U, // VZIPd16 >+ 1024U, // VZIPd8 >+ 1024U, // VZIPq16 >+ 1024U, // VZIPq32 >+ 1024U, // VZIPq8 >+ 0U, // WIN__CHKSTK >+ 10304U, // sysLDMDA >+ 369U, // sysLDMDA_UPD >+ 10304U, // sysLDMDB >+ 369U, // sysLDMDB_UPD >+ 10304U, // sysLDMIA >+ 369U, // sysLDMIA_UPD >+ 10304U, // sysLDMIB >+ 369U, // sysLDMIB_UPD >+ 10304U, // sysSTMDA >+ 369U, // sysSTMDA_UPD >+ 10304U, // sysSTMDB >+ 369U, // sysSTMDB_UPD >+ 10304U, // sysSTMIA >+ 369U, // sysSTMIA_UPD >+ 10304U, // sysSTMIB >+ 369U, // sysSTMIB_UPD >+ 0U, // t2ABS >+ 0U, // t2ADCri >+ 0U, // t2ADCrr >+ 475136U, // t2ADCrs >+ 0U, // t2ADDSri >+ 0U, // t2ADDSrr >+ 0U, // t2ADDSrs >+ 0U, // t2ADDri >+ 0U, // t2ADDri12 >+ 0U, // t2ADDrr >+ 475136U, // t2ADDrs >+ 8U, // t2ADR >+ 0U, // t2ANDri >+ 0U, // t2ANDrr >+ 475136U, // t2ANDrs >+ 491520U, // t2ASRri >+ 0U, // t2ASRrr >+ 0U, // t2B >+ 16U, // t2BFC >+ 32792U, // t2BFI >+ 0U, // t2BICri >+ 0U, // t2BICrr >+ 475136U, // t2BICrs >+ 0U, // t2BR_JT >+ 0U, // t2BXJ >+ 0U, // t2Bcc >+ 544U, // t2CDP >+ 544U, // t2CDP2 >+ 0U, // t2CLREX >+ 1024U, // t2CLZ >+ 1024U, // t2CMNri >+ 1024U, // t2CMNzrr >+ 376U, // t2CMNzrs >+ 1024U, // t2CMPri >+ 1024U, // t2CMPrr >+ 376U, // t2CMPrs >+ 0U, // t2CPS1p >+ 0U, // t2CPS2p >+ 1048U, // t2CPS3p >+ 1048U, // t2CRC32B >+ 1048U, // t2CRC32CB >+ 1048U, // t2CRC32CH >+ 1048U, // t2CRC32CW >+ 1048U, // t2CRC32H >+ 1048U, // t2CRC32W >+ 0U, // t2DBG >+ 0U, // t2DCPS1 >+ 0U, // t2DCPS2 >+ 0U, // t2DCPS3 >+ 0U, // t2DMB >+ 0U, // t2DSB >+ 0U, // t2EORri >+ 0U, // t2EORrr >+ 475136U, // t2EORrs >+ 0U, // t2HINT >+ 0U, // t2ISB >+ 0U, // t2IT >+ 0U, // t2Int_eh_sjlj_setjmp >+ 0U, // t2Int_eh_sjlj_setjmp_nofp >+ 72U, // t2LDA >+ 72U, // t2LDAB >+ 72U, // t2LDAEX >+ 72U, // t2LDAEXB >+ 229376U, // t2LDAEXD >+ 72U, // t2LDAEXH >+ 72U, // t2LDAH >+ 81U, // t2LDC2L_OFFSET >+ 49241U, // t2LDC2L_OPTION >+ 65625U, // t2LDC2L_POST >+ 97U, // t2LDC2L_PRE >+ 81U, // t2LDC2_OFFSET >+ 49241U, // t2LDC2_OPTION >+ 65625U, // t2LDC2_POST >+ 97U, // t2LDC2_PRE >+ 81U, // t2LDCL_OFFSET >+ 49241U, // t2LDCL_OPTION >+ 65625U, // t2LDCL_POST >+ 97U, // t2LDCL_PRE >+ 81U, // t2LDC_OFFSET >+ 49241U, // t2LDC_OPTION >+ 65625U, // t2LDC_POST >+ 97U, // t2LDC_PRE >+ 1088U, // t2LDMDB >+ 57U, // t2LDMDB_UPD >+ 1088U, // t2LDMIA >+ 0U, // t2LDMIA_RET >+ 57U, // t2LDMIA_UPD >+ 384U, // t2LDRBT >+ 10840U, // t2LDRB_POST >+ 392U, // t2LDRB_PRE >+ 120U, // t2LDRBi12 >+ 384U, // t2LDRBi8 >+ 400U, // t2LDRBpci >+ 1024U, // t2LDRBpcrel >+ 408U, // t2LDRBs >+ 11649024U, // t2LDRD_POST >+ 507904U, // t2LDRD_PRE >+ 524288U, // t2LDRDi8 >+ 416U, // t2LDREX >+ 72U, // t2LDREXB >+ 229376U, // t2LDREXD >+ 72U, // t2LDREXH >+ 384U, // t2LDRHT >+ 10840U, // t2LDRH_POST >+ 392U, // t2LDRH_PRE >+ 120U, // t2LDRHi12 >+ 384U, // t2LDRHi8 >+ 400U, // t2LDRHpci >+ 1024U, // t2LDRHpcrel >+ 408U, // t2LDRHs >+ 384U, // t2LDRSBT >+ 10840U, // t2LDRSB_POST >+ 392U, // t2LDRSB_PRE >+ 120U, // t2LDRSBi12 >+ 384U, // t2LDRSBi8 >+ 400U, // t2LDRSBpci >+ 1024U, // t2LDRSBpcrel >+ 408U, // t2LDRSBs >+ 384U, // t2LDRSHT >+ 10840U, // t2LDRSH_POST >+ 392U, // t2LDRSH_PRE >+ 120U, // t2LDRSHi12 >+ 384U, // t2LDRSHi8 >+ 400U, // t2LDRSHpci >+ 1024U, // t2LDRSHpcrel >+ 408U, // t2LDRSHs >+ 384U, // t2LDRT >+ 10840U, // t2LDR_POST >+ 392U, // t2LDR_PRE >+ 120U, // t2LDRi12 >+ 384U, // t2LDRi8 >+ 400U, // t2LDRpci >+ 0U, // t2LDRpci_pic >+ 1024U, // t2LDRpcrel >+ 408U, // t2LDRs >+ 0U, // t2LEApcrel >+ 0U, // t2LEApcrelJT >+ 0U, // t2LSLri >+ 0U, // t2LSLrr >+ 491520U, // t2LSRri >+ 0U, // t2LSRrr >+ 2295328U, // t2MCR >+ 2295328U, // t2MCR2 >+ 3343904U, // t2MCRR >+ 3343904U, // t2MCRR2 >+ 17825792U, // t2MLA >+ 17825792U, // t2MLS >+ 0U, // t2MOVCCasr >+ 0U, // t2MOVCCi >+ 0U, // t2MOVCCi16 >+ 0U, // t2MOVCCi32imm >+ 0U, // t2MOVCClsl >+ 0U, // t2MOVCClsr >+ 0U, // t2MOVCCr >+ 0U, // t2MOVCCror >+ 376U, // t2MOVSsi >+ 48U, // t2MOVSsr >+ 1048U, // t2MOVTi16 >+ 0U, // t2MOVTi16_ga_pcrel >+ 0U, // t2MOV_ga_pcrel >+ 1024U, // t2MOVi >+ 1024U, // t2MOVi16 >+ 0U, // t2MOVi16_ga_pcrel >+ 0U, // t2MOVi32imm >+ 1024U, // t2MOVr >+ 376U, // t2MOVsi >+ 48U, // t2MOVsr >+ 11264U, // t2MOVsra_flag >+ 11264U, // t2MOVsrl_flag >+ 0U, // t2MRC >+ 0U, // t2MRC2 >+ 3343904U, // t2MRRC >+ 3343904U, // t2MRRC2 >+ 2U, // t2MRS_AR >+ 424U, // t2MRS_M >+ 2U, // t2MRSsys_AR >+ 0U, // t2MSR_AR >+ 0U, // t2MSR_M >+ 0U, // t2MUL >+ 0U, // t2MVNCCi >+ 1024U, // t2MVNi >+ 1024U, // t2MVNr >+ 376U, // t2MVNs >+ 0U, // t2ORNri >+ 0U, // t2ORNrr >+ 475136U, // t2ORNrs >+ 0U, // t2ORRri >+ 0U, // t2ORRrr >+ 475136U, // t2ORRrs >+ 4194304U, // t2PKHBT >+ 5242880U, // t2PKHTB >+ 0U, // t2PLDWi12 >+ 0U, // t2PLDWi8 >+ 0U, // t2PLDWs >+ 0U, // t2PLDi12 >+ 0U, // t2PLDi8 >+ 0U, // t2PLDpci >+ 0U, // t2PLDs >+ 0U, // t2PLIi12 >+ 0U, // t2PLIi8 >+ 0U, // t2PLIpci >+ 0U, // t2PLIs >+ 0U, // t2QADD >+ 0U, // t2QADD16 >+ 0U, // t2QADD8 >+ 0U, // t2QASX >+ 0U, // t2QDADD >+ 0U, // t2QDSUB >+ 0U, // t2QSAX >+ 0U, // t2QSUB >+ 0U, // t2QSUB16 >+ 0U, // t2QSUB8 >+ 1024U, // t2RBIT >+ 1024U, // t2REV >+ 1024U, // t2REV16 >+ 1024U, // t2REVSH >+ 0U, // t2RFEDB >+ 4U, // t2RFEDBW >+ 0U, // t2RFEIA >+ 4U, // t2RFEIAW >+ 0U, // t2RORri >+ 0U, // t2RORrr >+ 1024U, // t2RRX >+ 0U, // t2RSBSri >+ 0U, // t2RSBSrs >+ 0U, // t2RSBri >+ 0U, // t2RSBrr >+ 475136U, // t2RSBrs >+ 0U, // t2SADD16 >+ 0U, // t2SADD8 >+ 0U, // t2SASX >+ 0U, // t2SBCri >+ 0U, // t2SBCrr >+ 475136U, // t2SBCrs >+ 34603008U, // t2SBFX >+ 0U, // t2SDIV >+ 0U, // t2SEL >+ 0U, // t2SHADD16 >+ 0U, // t2SHADD8 >+ 0U, // t2SHASX >+ 0U, // t2SHSAX >+ 0U, // t2SHSUB16 >+ 0U, // t2SHSUB8 >+ 0U, // t2SMC >+ 17825792U, // t2SMLABB >+ 17825792U, // t2SMLABT >+ 17825792U, // t2SMLAD >+ 17825792U, // t2SMLADX >+ 17825792U, // t2SMLAL >+ 17825792U, // t2SMLALBB >+ 17825792U, // t2SMLALBT >+ 17825792U, // t2SMLALD >+ 17825792U, // t2SMLALDX >+ 17825792U, // t2SMLALTB >+ 17825792U, // t2SMLALTT >+ 17825792U, // t2SMLATB >+ 17825792U, // t2SMLATT >+ 17825792U, // t2SMLAWB >+ 17825792U, // t2SMLAWT >+ 17825792U, // t2SMLSD >+ 17825792U, // t2SMLSDX >+ 17825792U, // t2SMLSLD >+ 185860096U, // t2SMLSLDX >+ 17825792U, // t2SMMLA >+ 17825792U, // t2SMMLAR >+ 17825792U, // t2SMMLS >+ 17825792U, // t2SMMLSR >+ 0U, // t2SMMUL >+ 0U, // t2SMMULR >+ 0U, // t2SMUAD >+ 0U, // t2SMUADX >+ 0U, // t2SMULBB >+ 0U, // t2SMULBT >+ 17825792U, // t2SMULL >+ 0U, // t2SMULTB >+ 0U, // t2SMULTT >+ 0U, // t2SMULWB >+ 0U, // t2SMULWT >+ 0U, // t2SMUSD >+ 0U, // t2SMUSDX >+ 0U, // t2SRSDB >+ 0U, // t2SRSDB_UPD >+ 0U, // t2SRSIA >+ 0U, // t2SRSIA_UPD >+ 2216U, // t2SSAT >+ 1192U, // t2SSAT16 >+ 0U, // t2SSAX >+ 0U, // t2SSUB16 >+ 0U, // t2SSUB8 >+ 81U, // t2STC2L_OFFSET >+ 49241U, // t2STC2L_OPTION >+ 65625U, // t2STC2L_POST >+ 97U, // t2STC2L_PRE >+ 81U, // t2STC2_OFFSET >+ 49241U, // t2STC2_OPTION >+ 65625U, // t2STC2_POST >+ 97U, // t2STC2_PRE >+ 81U, // t2STCL_OFFSET >+ 49241U, // t2STCL_OPTION >+ 65625U, // t2STCL_POST >+ 97U, // t2STCL_PRE >+ 81U, // t2STC_OFFSET >+ 49241U, // t2STC_OPTION >+ 65625U, // t2STC_POST >+ 97U, // t2STC_PRE >+ 72U, // t2STL >+ 72U, // t2STLB >+ 229376U, // t2STLEX >+ 229376U, // t2STLEXB >+ 202375168U, // t2STLEXD >+ 229376U, // t2STLEXH >+ 72U, // t2STLH >+ 1088U, // t2STMDB >+ 57U, // t2STMDB_UPD >+ 1088U, // t2STMIA >+ 57U, // t2STMIA_UPD >+ 384U, // t2STRBT >+ 10840U, // t2STRB_POST >+ 392U, // t2STRB_PRE >+ 0U, // t2STRB_preidx >+ 120U, // t2STRBi12 >+ 384U, // t2STRBi8 >+ 408U, // t2STRBs >+ 11649048U, // t2STRD_POST >+ 507928U, // t2STRD_PRE >+ 524288U, // t2STRDi8 >+ 540672U, // t2STREX >+ 229376U, // t2STREXB >+ 202375168U, // t2STREXD >+ 229376U, // t2STREXH >+ 384U, // t2STRHT >+ 10840U, // t2STRH_POST >+ 392U, // t2STRH_PRE >+ 0U, // t2STRH_preidx >+ 120U, // t2STRHi12 >+ 384U, // t2STRHi8 >+ 408U, // t2STRHs >+ 384U, // t2STRT >+ 10840U, // t2STR_POST >+ 392U, // t2STR_PRE >+ 0U, // t2STR_preidx >+ 120U, // t2STRi12 >+ 384U, // t2STRi8 >+ 408U, // t2STRs >+ 0U, // t2SUBS_PC_LR >+ 0U, // t2SUBSri >+ 0U, // t2SUBSrr >+ 0U, // t2SUBSrs >+ 0U, // t2SUBri >+ 0U, // t2SUBri12 >+ 0U, // t2SUBrr >+ 475136U, // t2SUBrs >+ 6291456U, // t2SXTAB >+ 6291456U, // t2SXTAB16 >+ 6291456U, // t2SXTAH >+ 2560U, // t2SXTB >+ 2560U, // t2SXTB16 >+ 2560U, // t2SXTH >+ 0U, // t2TBB >+ 0U, // t2TBB_JT >+ 0U, // t2TBH >+ 0U, // t2TBH_JT >+ 1024U, // t2TEQri >+ 1024U, // t2TEQrr >+ 376U, // t2TEQrs >+ 1024U, // t2TSTri >+ 1024U, // t2TSTrr >+ 376U, // t2TSTrs >+ 0U, // t2UADD16 >+ 0U, // t2UADD8 >+ 0U, // t2UASX >+ 34603008U, // t2UBFX >+ 0U, // t2UDF >+ 0U, // t2UDIV >+ 0U, // t2UHADD16 >+ 0U, // t2UHADD8 >+ 0U, // t2UHASX >+ 0U, // t2UHSAX >+ 0U, // t2UHSUB16 >+ 0U, // t2UHSUB8 >+ 17825792U, // t2UMAAL >+ 17825792U, // t2UMLAL >+ 17825792U, // t2UMULL >+ 0U, // t2UQADD16 >+ 0U, // t2UQADD8 >+ 0U, // t2UQASX >+ 0U, // t2UQSAX >+ 0U, // t2UQSUB16 >+ 0U, // t2UQSUB8 >+ 0U, // t2USAD8 >+ 17825792U, // t2USADA8 >+ 7340032U, // t2USAT >+ 0U, // t2USAT16 >+ 0U, // t2USAX >+ 0U, // t2USUB16 >+ 0U, // t2USUB8 >+ 6291456U, // t2UXTAB >+ 6291456U, // t2UXTAB16 >+ 6291456U, // t2UXTAH >+ 2560U, // t2UXTB >+ 2560U, // t2UXTB16 >+ 2560U, // t2UXTH >+ 0U, // tADC >+ 1048U, // tADDhirr >+ 1184U, // tADDi3 >+ 0U, // tADDi8 >+ 0U, // tADDrSP >+ 557056U, // tADDrSPi >+ 1184U, // tADDrr >+ 432U, // tADDspi >+ 1048U, // tADDspr >+ 0U, // tADJCALLSTACKDOWN >+ 0U, // tADJCALLSTACKUP >+ 440U, // tADR >+ 0U, // tAND >+ 448U, // tASRri >+ 0U, // tASRrr >+ 0U, // tB >+ 0U, // tBIC >+ 0U, // tBKPT >+ 0U, // tBL >+ 0U, // tBLXi >+ 0U, // tBLXr >+ 0U, // tBRIND >+ 0U, // tBR_JTr >+ 0U, // tBX >+ 0U, // tBX_CALL >+ 0U, // tBX_RET >+ 0U, // tBX_RET_vararg >+ 0U, // tBcc >+ 0U, // tBfar >+ 0U, // tCBNZ >+ 0U, // tCBZ >+ 1024U, // tCMNz >+ 1024U, // tCMPhir >+ 1024U, // tCMPi8 >+ 1024U, // tCMPr >+ 0U, // tCPS >+ 0U, // tEOR >+ 0U, // tHINT >+ 0U, // tHLT >+ 0U, // tInt_eh_sjlj_longjmp >+ 0U, // tInt_eh_sjlj_setjmp >+ 1088U, // tLDMIA >+ 0U, // tLDMIA_UPD >+ 456U, // tLDRBi >+ 464U, // tLDRBr >+ 472U, // tLDRHi >+ 464U, // tLDRHr >+ 0U, // tLDRLIT_ga_abs >+ 0U, // tLDRLIT_ga_pcrel >+ 464U, // tLDRSB >+ 464U, // tLDRSH >+ 480U, // tLDRi >+ 400U, // tLDRpci >+ 0U, // tLDRpci_pic >+ 464U, // tLDRr >+ 488U, // tLDRspi >+ 0U, // tLEApcrel >+ 0U, // tLEApcrelJT >+ 1184U, // tLSLri >+ 0U, // tLSLrr >+ 448U, // tLSRri >+ 0U, // tLSRrr >+ 0U, // tMOVCCr_pseudo >+ 0U, // tMOVSr >+ 0U, // tMOVi8 >+ 1024U, // tMOVr >+ 1184U, // tMUL >+ 0U, // tMVN >+ 0U, // tORR >+ 0U, // tPICADD >+ 0U, // tPOP >+ 0U, // tPOP_RET >+ 0U, // tPUSH >+ 1024U, // tREV >+ 1024U, // tREV16 >+ 1024U, // tREVSH >+ 0U, // tROR >+ 0U, // tRSB >+ 0U, // tSBC >+ 0U, // tSETEND >+ 57U, // tSTMIA_UPD >+ 456U, // tSTRBi >+ 464U, // tSTRBr >+ 472U, // tSTRHi >+ 464U, // tSTRHr >+ 480U, // tSTRi >+ 464U, // tSTRr >+ 488U, // tSTRspi >+ 1184U, // tSUBi3 >+ 0U, // tSUBi8 >+ 1184U, // tSUBrr >+ 432U, // tSUBspi >+ 0U, // tSVC >+ 1024U, // tSXTB >+ 1024U, // tSXTH >+ 0U, // tTAILJMPd >+ 0U, // tTAILJMPdND >+ 0U, // tTAILJMPr >+ 0U, // tTPsoft >+ 0U, // tTRAP >+ 1024U, // tTST >+ 0U, // tUDF >+ 1024U, // tUXTB >+ 1024U, // tUXTH >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0, >+ /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0, >+ /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0, >+ /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0, >+ /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0, >+ /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0, >+ /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0, >+ /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0, >+ /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0, >+ /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0, >+ /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0, >+ /* 237 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0, >+ /* 249 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0, >+ /* 261 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 273 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 285 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0, >+ /* 297 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0, >+ /* 309 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0, >+ /* 321 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0, >+ /* 333 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0, >+ /* 345 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0, >+ /* 357 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0, >+ /* 369 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0, >+ /* 381 */ 'l', 'd', 'c', '2', 9, 0, >+ /* 387 */ 'm', 'r', 'c', '2', 9, 0, >+ /* 393 */ 'm', 'r', 'r', 'c', '2', 9, 0, >+ /* 400 */ 's', 't', 'c', '2', 9, 0, >+ /* 406 */ 'c', 'd', 'p', '2', 9, 0, >+ /* 412 */ 'm', 'c', 'r', '2', 9, 0, >+ /* 418 */ 'm', 'c', 'r', 'r', '2', 9, 0, >+ /* 425 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 440 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 455 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 470 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 485 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 500 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 515 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 530 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0, >+ /* 545 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0, >+ /* 557 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0, >+ /* 569 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 581 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 593 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0, >+ /* 605 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0, >+ /* 617 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0, >+ /* 629 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0, >+ /* 641 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0, >+ /* 653 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0, >+ /* 665 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0, >+ /* 676 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0, >+ /* 686 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0, >+ /* 695 */ 'a', 'e', 's', 'd', '.', '8', 9, 0, >+ /* 703 */ 'a', 'e', 's', 'e', '.', '8', 9, 0, >+ /* 711 */ 'r', 'f', 'e', 'd', 'a', 9, 0, >+ /* 718 */ 'r', 'f', 'e', 'i', 'a', 9, 0, >+ /* 725 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, >+ /* 733 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, >+ /* 742 */ 'r', 'f', 'e', 'd', 'b', 9, 0, >+ /* 749 */ 'r', 'f', 'e', 'i', 'b', 9, 0, >+ /* 756 */ 'd', 'm', 'b', 9, 0, >+ /* 761 */ 'd', 's', 'b', 9, 0, >+ /* 766 */ 'i', 's', 'b', 9, 0, >+ /* 771 */ 'p', 'l', 'd', 9, 0, >+ /* 776 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0, >+ /* 784 */ 'u', 'd', 'f', 9, 0, >+ /* 789 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, >+ /* 797 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, >+ /* 806 */ 'p', 'l', 'i', 9, 0, >+ /* 811 */ 'l', 'd', 'c', '2', 'l', 9, 0, >+ /* 818 */ 's', 't', 'c', '2', 'l', 9, 0, >+ /* 825 */ 'b', 'l', 9, 0, >+ /* 829 */ 'c', 'p', 's', 9, 0, >+ /* 834 */ 'm', 'o', 'v', 's', 9, 0, >+ /* 840 */ 'h', 'l', 't', 9, 0, >+ /* 845 */ 'b', 'k', 'p', 't', 9, 0, >+ /* 851 */ 'u', 'd', 'f', '.', 'w', 9, 0, >+ /* 858 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, >+ /* 866 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, >+ /* 875 */ 'p', 'l', 'd', 'w', 9, 0, >+ /* 881 */ 'b', 'x', 9, 0, >+ /* 885 */ 'b', 'l', 'x', 9, 0, >+ /* 890 */ 'c', 'b', 'z', 9, 0, >+ /* 895 */ 'c', 'b', 'n', 'z', 9, 0, >+ /* 901 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0, >+ /* 913 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0, >+ /* 925 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0, >+ /* 937 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0, >+ /* 949 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0, >+ /* 960 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0, >+ /* 971 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0, >+ /* 982 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0, >+ /* 993 */ 'v', 'l', 'd', '1', 0, >+ /* 998 */ 'd', 'c', 'p', 's', '1', 0, >+ /* 1004 */ 'v', 's', 't', '1', 0, >+ /* 1009 */ 'v', 'r', 'e', 'v', '3', '2', 0, >+ /* 1016 */ 'l', 'd', 'c', '2', 0, >+ /* 1021 */ 'm', 'r', 'c', '2', 0, >+ /* 1026 */ 'm', 'r', 'r', 'c', '2', 0, >+ /* 1032 */ 's', 't', 'c', '2', 0, >+ /* 1037 */ 'v', 'l', 'd', '2', 0, >+ /* 1042 */ 'c', 'd', 'p', '2', 0, >+ /* 1047 */ 'm', 'c', 'r', '2', 0, >+ /* 1052 */ 'm', 'c', 'r', 'r', '2', 0, >+ /* 1058 */ 'd', 'c', 'p', 's', '2', 0, >+ /* 1064 */ 'v', 's', 't', '2', 0, >+ /* 1069 */ 'v', 'l', 'd', '3', 0, >+ /* 1074 */ 'd', 'c', 'p', 's', '3', 0, >+ /* 1080 */ 'v', 's', 't', '3', 0, >+ /* 1085 */ 'v', 'r', 'e', 'v', '6', '4', 0, >+ /* 1092 */ 'v', 'l', 'd', '4', 0, >+ /* 1097 */ 'v', 's', 't', '4', 0, >+ /* 1102 */ 's', 'x', 't', 'a', 'b', '1', '6', 0, >+ /* 1110 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0, >+ /* 1118 */ 's', 'x', 't', 'b', '1', '6', 0, >+ /* 1125 */ 'u', 'x', 't', 'b', '1', '6', 0, >+ /* 1132 */ 's', 'h', 's', 'u', 'b', '1', '6', 0, >+ /* 1140 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0, >+ /* 1148 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0, >+ /* 1156 */ 's', 's', 'u', 'b', '1', '6', 0, >+ /* 1163 */ 'u', 's', 'u', 'b', '1', '6', 0, >+ /* 1170 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0, >+ /* 1178 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0, >+ /* 1186 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0, >+ /* 1194 */ 's', 'a', 'd', 'd', '1', '6', 0, >+ /* 1201 */ 'u', 'a', 'd', 'd', '1', '6', 0, >+ /* 1208 */ 's', 's', 'a', 't', '1', '6', 0, >+ /* 1215 */ 'u', 's', 'a', 't', '1', '6', 0, >+ /* 1222 */ 'v', 'r', 'e', 'v', '1', '6', 0, >+ /* 1229 */ 'u', 's', 'a', 'd', 'a', '8', 0, >+ /* 1236 */ 's', 'h', 's', 'u', 'b', '8', 0, >+ /* 1243 */ 'u', 'h', 's', 'u', 'b', '8', 0, >+ /* 1250 */ 'u', 'q', 's', 'u', 'b', '8', 0, >+ /* 1257 */ 's', 's', 'u', 'b', '8', 0, >+ /* 1263 */ 'u', 's', 'u', 'b', '8', 0, >+ /* 1269 */ 'u', 's', 'a', 'd', '8', 0, >+ /* 1275 */ 's', 'h', 'a', 'd', 'd', '8', 0, >+ /* 1282 */ 'u', 'h', 'a', 'd', 'd', '8', 0, >+ /* 1289 */ 'u', 'q', 'a', 'd', 'd', '8', 0, >+ /* 1296 */ 's', 'a', 'd', 'd', '8', 0, >+ /* 1302 */ 'u', 'a', 'd', 'd', '8', 0, >+ /* 1308 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 1321 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 1328 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 1338 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 1353 */ 'v', 'a', 'b', 'a', 0, >+ /* 1358 */ 'l', 'd', 'a', 0, >+ /* 1362 */ 'l', 'd', 'm', 'd', 'a', 0, >+ /* 1368 */ 's', 't', 'm', 'd', 'a', 0, >+ /* 1374 */ 'r', 'f', 'e', 'i', 'a', 0, >+ /* 1380 */ 'v', 'l', 'd', 'm', 'i', 'a', 0, >+ /* 1387 */ 'v', 's', 't', 'm', 'i', 'a', 0, >+ /* 1394 */ 's', 'r', 's', 'i', 'a', 0, >+ /* 1400 */ 's', 'm', 'm', 'l', 'a', 0, >+ /* 1406 */ 'v', 'n', 'm', 'l', 'a', 0, >+ /* 1412 */ 'v', 'm', 'l', 'a', 0, >+ /* 1417 */ 'v', 'f', 'm', 'a', 0, >+ /* 1422 */ 'v', 'f', 'n', 'm', 'a', 0, >+ /* 1428 */ 'v', 'r', 's', 'r', 'a', 0, >+ /* 1434 */ 'v', 's', 'r', 'a', 0, >+ /* 1439 */ 'l', 'd', 'a', 'b', 0, >+ /* 1444 */ 's', 'x', 't', 'a', 'b', 0, >+ /* 1450 */ 'u', 'x', 't', 'a', 'b', 0, >+ /* 1456 */ 's', 'm', 'l', 'a', 'b', 'b', 0, >+ /* 1463 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0, >+ /* 1471 */ 's', 'm', 'u', 'l', 'b', 'b', 0, >+ /* 1478 */ 't', 'b', 'b', 0, >+ /* 1482 */ 'r', 'f', 'e', 'd', 'b', 0, >+ /* 1488 */ 'v', 'l', 'd', 'm', 'd', 'b', 0, >+ /* 1495 */ 'v', 's', 't', 'm', 'd', 'b', 0, >+ /* 1502 */ 's', 'r', 's', 'd', 'b', 0, >+ /* 1508 */ 'l', 'd', 'm', 'i', 'b', 0, >+ /* 1514 */ 's', 't', 'm', 'i', 'b', 0, >+ /* 1520 */ 's', 't', 'l', 'b', 0, >+ /* 1525 */ 'd', 'm', 'b', 0, >+ /* 1529 */ 's', 'w', 'p', 'b', 0, >+ /* 1534 */ 'l', 'd', 'r', 'b', 0, >+ /* 1539 */ 's', 't', 'r', 'b', 0, >+ /* 1544 */ 'd', 's', 'b', 0, >+ /* 1548 */ 'i', 's', 'b', 0, >+ /* 1552 */ 'l', 'd', 'r', 's', 'b', 0, >+ /* 1558 */ 's', 'm', 'l', 'a', 't', 'b', 0, >+ /* 1565 */ 'p', 'k', 'h', 't', 'b', 0, >+ /* 1571 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0, >+ /* 1579 */ 's', 'm', 'u', 'l', 't', 'b', 0, >+ /* 1586 */ 'v', 'c', 'v', 't', 'b', 0, >+ /* 1592 */ 's', 'x', 't', 'b', 0, >+ /* 1597 */ 'u', 'x', 't', 'b', 0, >+ /* 1602 */ 'q', 'd', 's', 'u', 'b', 0, >+ /* 1608 */ 'v', 'h', 's', 'u', 'b', 0, >+ /* 1614 */ 'v', 'q', 's', 'u', 'b', 0, >+ /* 1620 */ 'v', 's', 'u', 'b', 0, >+ /* 1625 */ 's', 'm', 'l', 'a', 'w', 'b', 0, >+ /* 1632 */ 's', 'm', 'u', 'l', 'w', 'b', 0, >+ /* 1639 */ 'l', 'd', 'a', 'e', 'x', 'b', 0, >+ /* 1646 */ 's', 't', 'l', 'e', 'x', 'b', 0, >+ /* 1653 */ 'l', 'd', 'r', 'e', 'x', 'b', 0, >+ /* 1660 */ 's', 't', 'r', 'e', 'x', 'b', 0, >+ /* 1667 */ 's', 'b', 'c', 0, >+ /* 1671 */ 'a', 'd', 'c', 0, >+ /* 1675 */ 'l', 'd', 'c', 0, >+ /* 1679 */ 'b', 'f', 'c', 0, >+ /* 1683 */ 'v', 'b', 'i', 'c', 0, >+ /* 1688 */ 's', 'm', 'c', 0, >+ /* 1692 */ 'm', 'r', 'c', 0, >+ /* 1696 */ 'm', 'r', 'r', 'c', 0, >+ /* 1701 */ 'r', 's', 'c', 0, >+ /* 1705 */ 's', 't', 'c', 0, >+ /* 1709 */ 's', 'v', 'c', 0, >+ /* 1713 */ 's', 'm', 'l', 'a', 'd', 0, >+ /* 1719 */ 's', 'm', 'u', 'a', 'd', 0, >+ /* 1725 */ 'v', 'a', 'b', 'd', 0, >+ /* 1730 */ 'q', 'd', 'a', 'd', 'd', 0, >+ /* 1736 */ 'v', 'r', 'h', 'a', 'd', 'd', 0, >+ /* 1743 */ 'v', 'h', 'a', 'd', 'd', 0, >+ /* 1749 */ 'v', 'p', 'a', 'd', 'd', 0, >+ /* 1755 */ 'v', 'q', 'a', 'd', 'd', 0, >+ /* 1761 */ 'v', 'a', 'd', 'd', 0, >+ /* 1766 */ 's', 'm', 'l', 'a', 'l', 'd', 0, >+ /* 1773 */ 'p', 'l', 'd', 0, >+ /* 1777 */ 's', 'm', 'l', 's', 'l', 'd', 0, >+ /* 1784 */ 'v', 'a', 'n', 'd', 0, >+ /* 1789 */ 'l', 'd', 'r', 'd', 0, >+ /* 1794 */ 's', 't', 'r', 'd', 0, >+ /* 1799 */ 's', 'm', 'l', 's', 'd', 0, >+ /* 1805 */ 's', 'm', 'u', 's', 'd', 0, >+ /* 1811 */ 'l', 'd', 'a', 'e', 'x', 'd', 0, >+ /* 1818 */ 's', 't', 'l', 'e', 'x', 'd', 0, >+ /* 1825 */ 'l', 'd', 'r', 'e', 'x', 'd', 0, >+ /* 1832 */ 's', 't', 'r', 'e', 'x', 'd', 0, >+ /* 1839 */ 'v', 'a', 'c', 'g', 'e', 0, >+ /* 1845 */ 'v', 'c', 'g', 'e', 0, >+ /* 1850 */ 'v', 'c', 'l', 'e', 0, >+ /* 1855 */ 'v', 'r', 'e', 'c', 'p', 'e', 0, >+ /* 1862 */ 'v', 'c', 'm', 'p', 'e', 0, >+ /* 1868 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0, >+ /* 1876 */ 'v', 'b', 'i', 'f', 0, >+ /* 1881 */ 'd', 'b', 'g', 0, >+ /* 1885 */ 'v', 'q', 'n', 'e', 'g', 0, >+ /* 1891 */ 'v', 'n', 'e', 'g', 0, >+ /* 1896 */ 'l', 'd', 'a', 'h', 0, >+ /* 1901 */ 's', 'x', 't', 'a', 'h', 0, >+ /* 1907 */ 'u', 'x', 't', 'a', 'h', 0, >+ /* 1913 */ 't', 'b', 'h', 0, >+ /* 1917 */ 's', 't', 'l', 'h', 0, >+ /* 1922 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0, >+ /* 1930 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0, >+ /* 1939 */ 'l', 'd', 'r', 'h', 0, >+ /* 1944 */ 's', 't', 'r', 'h', 0, >+ /* 1949 */ 'l', 'd', 'r', 's', 'h', 0, >+ /* 1955 */ 'p', 'u', 's', 'h', 0, >+ /* 1960 */ 'r', 'e', 'v', 's', 'h', 0, >+ /* 1966 */ 's', 'x', 't', 'h', 0, >+ /* 1971 */ 'u', 'x', 't', 'h', 0, >+ /* 1976 */ 'l', 'd', 'a', 'e', 'x', 'h', 0, >+ /* 1983 */ 's', 't', 'l', 'e', 'x', 'h', 0, >+ /* 1990 */ 'l', 'd', 'r', 'e', 'x', 'h', 0, >+ /* 1997 */ 's', 't', 'r', 'e', 'x', 'h', 0, >+ /* 2004 */ 'b', 'f', 'i', 0, >+ /* 2008 */ 'p', 'l', 'i', 0, >+ /* 2012 */ 'v', 's', 'l', 'i', 0, >+ /* 2017 */ 'v', 's', 'r', 'i', 0, >+ /* 2022 */ 'b', 'x', 'j', 0, >+ /* 2026 */ 'l', 'd', 'c', '2', 'l', 0, >+ /* 2032 */ 's', 't', 'c', '2', 'l', 0, >+ /* 2038 */ 'u', 'm', 'a', 'a', 'l', 0, >+ /* 2044 */ 'v', 'a', 'b', 'a', 'l', 0, >+ /* 2050 */ 'v', 'p', 'a', 'd', 'a', 'l', 0, >+ /* 2057 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0, >+ /* 2065 */ 's', 'm', 'l', 'a', 'l', 0, >+ /* 2071 */ 'u', 'm', 'l', 'a', 'l', 0, >+ /* 2077 */ 'v', 'm', 'l', 'a', 'l', 0, >+ /* 2083 */ 'v', 't', 'b', 'l', 0, >+ /* 2088 */ 'v', 's', 'u', 'b', 'l', 0, >+ /* 2094 */ 'l', 'd', 'c', 'l', 0, >+ /* 2099 */ 's', 't', 'c', 'l', 0, >+ /* 2104 */ 'v', 'a', 'b', 'd', 'l', 0, >+ /* 2110 */ 'v', 'p', 'a', 'd', 'd', 'l', 0, >+ /* 2117 */ 'v', 'a', 'd', 'd', 'l', 0, >+ /* 2123 */ 's', 'e', 'l', 0, >+ /* 2127 */ 'v', 'q', 's', 'h', 'l', 0, >+ /* 2133 */ 'v', 'q', 'r', 's', 'h', 'l', 0, >+ /* 2140 */ 'v', 'r', 's', 'h', 'l', 0, >+ /* 2146 */ 'v', 's', 'h', 'l', 0, >+ /* 2151 */ 'v', 's', 'h', 'l', 'l', 0, >+ /* 2157 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0, >+ /* 2165 */ 's', 'm', 'u', 'l', 'l', 0, >+ /* 2171 */ 'u', 'm', 'u', 'l', 'l', 0, >+ /* 2177 */ 'v', 'm', 'u', 'l', 'l', 0, >+ /* 2183 */ 'v', 'b', 's', 'l', 0, >+ /* 2188 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0, >+ /* 2196 */ 'v', 'm', 'l', 's', 'l', 0, >+ /* 2202 */ 's', 't', 'l', 0, >+ /* 2206 */ 's', 'm', 'm', 'u', 'l', 0, >+ /* 2212 */ 'v', 'n', 'm', 'u', 'l', 0, >+ /* 2218 */ 'v', 'm', 'u', 'l', 0, >+ /* 2223 */ 'v', 'm', 'o', 'v', 'l', 0, >+ /* 2229 */ 'l', 'd', 'm', 0, >+ /* 2233 */ 's', 't', 'm', 0, >+ /* 2237 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0, >+ /* 2245 */ 'v', 's', 'u', 'b', 'h', 'n', 0, >+ /* 2252 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0, >+ /* 2260 */ 'v', 'a', 'd', 'd', 'h', 'n', 0, >+ /* 2267 */ 'v', 'p', 'm', 'i', 'n', 0, >+ /* 2273 */ 'v', 'm', 'i', 'n', 0, >+ /* 2278 */ 'c', 'm', 'n', 0, >+ /* 2282 */ 'v', 'q', 's', 'h', 'r', 'n', 0, >+ /* 2289 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0, >+ /* 2297 */ 'v', 'r', 's', 'h', 'r', 'n', 0, >+ /* 2304 */ 'v', 's', 'h', 'r', 'n', 0, >+ /* 2310 */ 'v', 'o', 'r', 'n', 0, >+ /* 2315 */ 'v', 't', 'r', 'n', 0, >+ /* 2320 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0, >+ /* 2328 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0, >+ /* 2337 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0, >+ /* 2345 */ 'v', 'm', 'v', 'n', 0, >+ /* 2350 */ 'v', 'q', 'm', 'o', 'v', 'n', 0, >+ /* 2357 */ 'v', 'm', 'o', 'v', 'n', 0, >+ /* 2363 */ 't', 'r', 'a', 'p', 0, >+ /* 2368 */ 'c', 'd', 'p', 0, >+ /* 2372 */ 'v', 'z', 'i', 'p', 0, >+ /* 2377 */ 'v', 'c', 'm', 'p', 0, >+ /* 2382 */ 'p', 'o', 'p', 0, >+ /* 2386 */ 'v', 'd', 'u', 'p', 0, >+ /* 2391 */ 'v', 's', 'w', 'p', 0, >+ /* 2396 */ 'v', 'u', 'z', 'p', 0, >+ /* 2401 */ 'v', 'c', 'e', 'q', 0, >+ /* 2406 */ 't', 'e', 'q', 0, >+ /* 2410 */ 's', 'm', 'm', 'l', 'a', 'r', 0, >+ /* 2417 */ 'm', 'c', 'r', 0, >+ /* 2421 */ 'a', 'd', 'r', 0, >+ /* 2425 */ 'v', 'l', 'd', 'r', 0, >+ /* 2430 */ 'v', 'r', 's', 'h', 'r', 0, >+ /* 2436 */ 'v', 's', 'h', 'r', 0, >+ /* 2441 */ 's', 'm', 'm', 'u', 'l', 'r', 0, >+ /* 2448 */ 'v', 'e', 'o', 'r', 0, >+ /* 2453 */ 'r', 'o', 'r', 0, >+ /* 2457 */ 'm', 'c', 'r', 'r', 0, >+ /* 2462 */ 'v', 'o', 'r', 'r', 0, >+ /* 2467 */ 'a', 's', 'r', 0, >+ /* 2471 */ 's', 'm', 'm', 'l', 's', 'r', 0, >+ /* 2478 */ 'v', 'm', 's', 'r', 0, >+ /* 2483 */ 'v', 'r', 'i', 'n', 't', 'r', 0, >+ /* 2490 */ 'v', 's', 't', 'r', 0, >+ /* 2495 */ 'v', 'c', 'v', 't', 'r', 0, >+ /* 2501 */ 'v', 'q', 'a', 'b', 's', 0, >+ /* 2507 */ 'v', 'a', 'b', 's', 0, >+ /* 2512 */ 's', 'u', 'b', 's', 0, >+ /* 2517 */ 'v', 'c', 'l', 's', 0, >+ /* 2522 */ 's', 'm', 'm', 'l', 's', 0, >+ /* 2528 */ 'v', 'n', 'm', 'l', 's', 0, >+ /* 2534 */ 'v', 'm', 'l', 's', 0, >+ /* 2539 */ 'v', 'f', 'm', 's', 0, >+ /* 2544 */ 'v', 'f', 'n', 'm', 's', 0, >+ /* 2550 */ 'v', 'r', 'e', 'c', 'p', 's', 0, >+ /* 2557 */ 'v', 'm', 'r', 's', 0, >+ /* 2562 */ 'a', 's', 'r', 's', 0, >+ /* 2567 */ 'l', 's', 'r', 's', 0, >+ /* 2572 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0, >+ /* 2580 */ 'm', 'o', 'v', 's', 0, >+ /* 2585 */ 's', 's', 'a', 't', 0, >+ /* 2590 */ 'u', 's', 'a', 't', 0, >+ /* 2595 */ 's', 'm', 'l', 'a', 'b', 't', 0, >+ /* 2602 */ 'p', 'k', 'h', 'b', 't', 0, >+ /* 2608 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0, >+ /* 2616 */ 's', 'm', 'u', 'l', 'b', 't', 0, >+ /* 2623 */ 'l', 'd', 'r', 'b', 't', 0, >+ /* 2629 */ 's', 't', 'r', 'b', 't', 0, >+ /* 2635 */ 'l', 'd', 'r', 's', 'b', 't', 0, >+ /* 2642 */ 'v', 'a', 'c', 'g', 't', 0, >+ /* 2648 */ 'v', 'c', 'g', 't', 0, >+ /* 2653 */ 'l', 'd', 'r', 'h', 't', 0, >+ /* 2659 */ 's', 't', 'r', 'h', 't', 0, >+ /* 2665 */ 'l', 'd', 'r', 's', 'h', 't', 0, >+ /* 2672 */ 'r', 'b', 'i', 't', 0, >+ /* 2677 */ 'v', 'b', 'i', 't', 0, >+ /* 2682 */ 'v', 'c', 'l', 't', 0, >+ /* 2687 */ 'v', 'c', 'n', 't', 0, >+ /* 2692 */ 'h', 'i', 'n', 't', 0, >+ /* 2697 */ 'l', 'd', 'r', 't', 0, >+ /* 2702 */ 'v', 's', 'q', 'r', 't', 0, >+ /* 2708 */ 's', 't', 'r', 't', 0, >+ /* 2713 */ 'v', 't', 's', 't', 0, >+ /* 2718 */ 's', 'm', 'l', 'a', 't', 't', 0, >+ /* 2725 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0, >+ /* 2733 */ 's', 'm', 'u', 'l', 't', 't', 0, >+ /* 2740 */ 'v', 'c', 'v', 't', 't', 0, >+ /* 2746 */ 'v', 'c', 'v', 't', 0, >+ /* 2751 */ 'm', 'o', 'v', 't', 0, >+ /* 2756 */ 's', 'm', 'l', 'a', 'w', 't', 0, >+ /* 2763 */ 's', 'm', 'u', 'l', 'w', 't', 0, >+ /* 2770 */ 'v', 'e', 'x', 't', 0, >+ /* 2775 */ 'v', 'q', 's', 'h', 'l', 'u', 0, >+ /* 2782 */ 'r', 'e', 'v', 0, >+ /* 2786 */ 's', 'd', 'i', 'v', 0, >+ /* 2791 */ 'u', 'd', 'i', 'v', 0, >+ /* 2796 */ 'v', 'd', 'i', 'v', 0, >+ /* 2801 */ 'v', 'm', 'o', 'v', 0, >+ /* 2806 */ 'v', 's', 'u', 'b', 'w', 0, >+ /* 2812 */ 'v', 'a', 'd', 'd', 'w', 0, >+ /* 2818 */ 'p', 'l', 'd', 'w', 0, >+ /* 2823 */ 'm', 'o', 'v', 'w', 0, >+ /* 2828 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0, >+ /* 2836 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0, >+ /* 2844 */ 'v', 'p', 'm', 'a', 'x', 0, >+ /* 2850 */ 'v', 'm', 'a', 'x', 0, >+ /* 2855 */ 's', 'h', 's', 'a', 'x', 0, >+ /* 2861 */ 'u', 'h', 's', 'a', 'x', 0, >+ /* 2867 */ 'u', 'q', 's', 'a', 'x', 0, >+ /* 2873 */ 's', 's', 'a', 'x', 0, >+ /* 2878 */ 'u', 's', 'a', 'x', 0, >+ /* 2883 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0, >+ /* 2891 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0, >+ /* 2899 */ 'v', 't', 'b', 'x', 0, >+ /* 2904 */ 's', 'm', 'l', 'a', 'd', 'x', 0, >+ /* 2911 */ 's', 'm', 'u', 'a', 'd', 'x', 0, >+ /* 2918 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0, >+ /* 2926 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0, >+ /* 2934 */ 's', 'm', 'l', 's', 'd', 'x', 0, >+ /* 2941 */ 's', 'm', 'u', 's', 'd', 'x', 0, >+ /* 2948 */ 'l', 'd', 'a', 'e', 'x', 0, >+ /* 2954 */ 's', 't', 'l', 'e', 'x', 0, >+ /* 2960 */ 'l', 'd', 'r', 'e', 'x', 0, >+ /* 2966 */ 'c', 'l', 'r', 'e', 'x', 0, >+ /* 2972 */ 's', 't', 'r', 'e', 'x', 0, >+ /* 2978 */ 's', 'b', 'f', 'x', 0, >+ /* 2983 */ 'u', 'b', 'f', 'x', 0, >+ /* 2988 */ 'b', 'l', 'x', 0, >+ /* 2992 */ 'r', 'r', 'x', 0, >+ /* 2996 */ 's', 'h', 'a', 's', 'x', 0, >+ /* 3002 */ 'u', 'h', 'a', 's', 'x', 0, >+ /* 3008 */ 'u', 'q', 'a', 's', 'x', 0, >+ /* 3014 */ 's', 'a', 's', 'x', 0, >+ /* 3019 */ 'u', 'a', 's', 'x', 0, >+ /* 3024 */ 'v', 'r', 'i', 'n', 't', 'x', 0, >+ /* 3031 */ 'v', 'c', 'l', 'z', 0, >+ /* 3036 */ 'v', 'r', 'i', 'n', 't', 'z', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; >+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 4095)-1); >+#endif >+ >+ >+ // Fragment 0 encoded into 5 bits for 29 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 31); >+ switch ((Bits >> 12) & 31) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLREX, TRAP, TRAPNaCl... >+ return; >+ break; >+ case 1: >+ // ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, ASRi, ASRr, BICri, BICrr, EO... >+ printSBitModifierOperand(MI, 5, O); >+ printPredicateOperand(MI, 3, O); >+ break; >+ case 2: >+ // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, MLA, MOVsr, MVNsr, ORRrsi, RSB... >+ printSBitModifierOperand(MI, 6, O); >+ printPredicateOperand(MI, 4, O); >+ break; >+ case 3: >+ // ADCrsr, ADDrsr, ANDrsr, BICrsr, EORrsr, ORRrsr, RSBrsr, RSCrsr, SBCrsr... >+ printSBitModifierOperand(MI, 7, O); >+ printPredicateOperand(MI, 5, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printSORegRegOperand(MI, 2, O); >+ return; >+ break; >+ case 4: >+ // ADR, CLZ, CMNri, CMNzrr, CMPri, CMPrr, FCONSTD, FCONSTS, FLDMXDB_UPD, ... >+ printPredicateOperand(MI, 2, O); >+ break; >+ case 5: >+ // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC... >+ printOperand(MI, 0, O); >+ break; >+ case 6: >+ // BFC, CMNzrsi, CMPrsi, LDRBi12, LDRcp, LDRi12, MOVTi16, QADD, QADD16, Q... >+ printPredicateOperand(MI, 3, O); >+ break; >+ case 7: >+ // BFI, CMNzrsr, CMPrsr, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, L... >+ printPredicateOperand(MI, 4, O); >+ break; >+ case 8: >+ // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM... >+ printPredicateOperand(MI, 1, O); >+ break; >+ case 9: >+ // BX_RET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, tBL, tBLX... >+ printPredicateOperand(MI, 0, O); >+ break; >+ case 10: >+ // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD4DUPd16, V... >+ printPredicateOperand(MI, 6, O); >+ break; >+ case 11: >+ // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ... >+ printPImmediate(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 12: >+ // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS >+ printCPSIMod(MI, 0, O); >+ break; >+ case 13: >+ // DMB, DSB >+ printMemBOption(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // ISB >+ printInstSyncBOption(MI, 0, O); >+ return; >+ break; >+ case 15: >+ // ITasm, t2IT >+ printThumbITMask(MI, 1, O); >+ break; >+ case 16: >+ // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRB_PRE... >+ printPredicateOperand(MI, 5, O); >+ break; >+ case 17: >+ // MOVi, MOVr, MOVr_TC, MVNi, MVNr, RRXi, t2MOVi, t2MOVr, t2MVNi, t2MVNr,... >+ printSBitModifierOperand(MI, 4, O); >+ printPredicateOperand(MI, 2, O); >+ break; >+ case 18: >+ // MRC2 >+ printPImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 19: >+ // PLDWi12, PLDi12, PLIi12 >+ printAddrModeImm12Operand(MI, 0, O, false); >+ return; >+ break; >+ case 20: >+ // PLDWrs, PLDrs, PLIrs >+ printAddrMode2Operand(MI, 0, O); >+ return; >+ break; >+ case 21: >+ // SETEND, tSETEND >+ printSetendOperand(MI, 0, O); >+ return; >+ break; >+ case 22: >+ // SMLAL, UMLAL >+ printSBitModifierOperand(MI, 8, O); >+ printPredicateOperand(MI, 6, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 23: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... >+ printPredicateOperand(MI, 7, O); >+ break; >+ case 24: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printPredicateOperand(MI, 9, O); >+ break; >+ case 25: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printPredicateOperand(MI, 11, O); >+ break; >+ case 26: >+ // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... >+ printPredicateOperand(MI, 8, O); >+ break; >+ case 27: >+ // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... >+ printPredicateOperand(MI, 13, O); >+ break; >+ case 28: >+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... >+ printSBitModifierOperand(MI, 1, O); >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 7 bits for 65 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 17) & 127); >+ switch ((Bits >> 17) & 127) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ SStream_concat0(O, "\t"); >+ break; >+ case 1: >+ // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // ASRi, ASRr, ITasm, LDRBT_POST, LDRT_POST, LSLi, LSLr, LSRi, LSRr, RORi... >+ SStream_concat0(O, " "); >+ break; >+ case 3: >+ // BKPT, BL, BLX, BLXi, BX, CPS1p, HLT, RFEDA, RFEDB, RFEIA, RFEIB, SRSDA... >+ return; >+ break; >+ case 4: >+ // BX_RET >+ SStream_concat0(O, "\tlr"); >+ ARM_addReg(MI, ARM_REG_LR); >+ return; >+ break; >+ case 5: >+ // CDP2, MCR2, MCRR2, MRRC2 >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 6: >+ // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V... >+ SStream_concat0(O, ".f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64); >+ printOperand(MI, 0, O); >+ break; >+ case 7: >+ // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEd, VACGEq, VACGTd... >+ SStream_concat0(O, ".f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32); >+ printOperand(MI, 0, O); >+ break; >+ case 8: >+ // FMSTAT >+ SStream_concat0(O, "\tapsr_nzcv, fpscr"); >+ ARM_addReg(MI, ARM_REG_APSR_NZCV); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ return; >+ break; >+ case 9: >+ // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O... >+ printCImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 10: >+ // MOVPCLR >+ SStream_concat0(O, "\tpc, lr"); >+ ARM_addReg(MI, ARM_REG_PC); >+ ARM_addReg(MI, ARM_REG_LR); >+ return; >+ break; >+ case 11: >+ // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 12: >+ // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i... >+ SStream_concat0(O, ".s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 13: >+ // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i... >+ SStream_concat0(O, ".s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 14: >+ // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8... >+ SStream_concat0(O, ".s8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 15: >+ // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i... >+ SStream_concat0(O, ".u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 16: >+ // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i... >+ SStream_concat0(O, ".u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 17: >+ // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8... >+ SStream_concat0(O, ".u8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 18: >+ // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V... >+ SStream_concat0(O, ".i64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ... >+ SStream_concat0(O, ".i32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 20: >+ // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V... >+ SStream_concat0(O, ".i16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv... >+ SStream_concat0(O, ".i8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_I8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1... >+ SStream_concat0(O, ".8\t"); >+ ARM_addVectorDataSize(MI, 8); >+ break; >+ case 23: >+ // VCVTBDH, VCVTTDH >+ SStream_concat0(O, ".f16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 24: >+ // VCVTBHD, VCVTTHD >+ SStream_concat0(O, ".f64.f16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 25: >+ // VCVTBHS, VCVTTHS, VCVTh2f >+ SStream_concat0(O, ".f32.f16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 26: >+ // VCVTBSH, VCVTTSH, VCVTf2h >+ SStream_concat0(O, ".f16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 27: >+ // VCVTDS >+ SStream_concat0(O, ".f64.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 28: >+ // VCVTSD >+ SStream_concat0(O, ".f32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 29: >+ // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS >+ SStream_concat0(O, ".s32.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 30: >+ // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS >+ SStream_concat0(O, ".u32.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 31: >+ // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS >+ SStream_concat0(O, ".f32.s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 32: >+ // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS >+ SStream_concat0(O, ".f32.u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 33: >+ // VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1DUPd16, ... >+ SStream_concat0(O, ".16\t"); >+ ARM_addVectorDataSize(MI, 16); >+ break; >+ case 34: >+ // VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VEXTd32, VEXTq32, VGETLNi32, V... >+ SStream_concat0(O, ".32\t"); >+ ARM_addVectorDataSize(MI, 32); >+ break; >+ case 35: >+ // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD... >+ SStream_concat0(O, ".64\t"); >+ ARM_addVectorDataSize(MI, 64); >+ break; >+ case 36: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq... >+ SStream_concat0(O, ".16\t{"); >+ ARM_addVectorDataSize(MI, 16); >+ break; >+ case 37: >+ // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq... >+ SStream_concat0(O, ".32\t{"); >+ ARM_addVectorDataSize(MI, 32); >+ break; >+ case 38: >+ // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U... >+ SStream_concat0(O, ".8\t{"); >+ ARM_addVectorDataSize(MI, 8); >+ break; >+ case 39: >+ // VMSR >+ SStream_concat0(O, "\tfpscr, "); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 40: >+ // VMSR_FPEXC >+ SStream_concat0(O, "\tfpexc, "); >+ ARM_addReg(MI, ARM_REG_FPEXC); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 41: >+ // VMSR_FPINST >+ SStream_concat0(O, "\tfpinst, "); >+ ARM_addReg(MI, ARM_REG_FPINST); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 42: >+ // VMSR_FPINST2 >+ SStream_concat0(O, "\tfpinst2, "); >+ ARM_addReg(MI, ARM_REG_FPINST2); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 43: >+ // VMSR_FPSID >+ SStream_concat0(O, "\tfpsid, "); >+ ARM_addReg(MI, ARM_REG_FPSID); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 44: >+ // VMULLp8, VMULpd, VMULpq >+ SStream_concat0(O, ".p8\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_P8); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 45: >+ // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V... >+ SStream_concat0(O, ".s64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 46: >+ // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ... >+ SStream_concat0(O, ".u64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 47: >+ // VSHTOD >+ SStream_concat0(O, ".f64.s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 48: >+ // VSHTOS >+ SStream_concat0(O, ".f32.s16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 49: >+ // VSITOD, VSLTOD >+ SStream_concat0(O, ".f64.s32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 50: >+ // VTOSHD >+ SStream_concat0(O, ".s16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 51: >+ // VTOSHS >+ SStream_concat0(O, ".s16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 52: >+ // VTOSIRD, VTOSIZD, VTOSLD >+ SStream_concat0(O, ".s32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 53: >+ // VTOUHD >+ SStream_concat0(O, ".u16.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 54: >+ // VTOUHS >+ SStream_concat0(O, ".u16.f32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 55: >+ // VTOUIRD, VTOUIZD, VTOULD >+ SStream_concat0(O, ".u32.f64\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 56: >+ // VUHTOD >+ SStream_concat0(O, ".f64.u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 57: >+ // VUHTOS >+ SStream_concat0(O, ".f32.u16\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printFBits16(MI, 2, O); >+ return; >+ break; >+ case 58: >+ // VUITOD, VULTOD >+ SStream_concat0(O, ".f64.u32\t"); >+ ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ break; >+ case 59: >+ // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ... >+ SStream_concat0(O, ".w\t"); >+ break; >+ case 60: >+ // t2SRSDB, t2SRSIA >+ SStream_concat0(O, "\tsp, "); >+ ARM_addReg(MI, ARM_REG_SP); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 61: >+ // t2SRSDB_UPD, t2SRSIA_UPD >+ SStream_concat0(O, "\tsp!, "); >+ ARM_addReg(MI, ARM_REG_SP); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 62: >+ // t2SUBS_PC_LR >+ SStream_concat0(O, "\tpc, lr, "); >+ ARM_addReg(MI, ARM_REG_PC); >+ ARM_addReg(MI, ARM_REG_LR); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 63: >+ // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri... >+ printPredicateOperand(MI, 4, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 64: >+ // tMOVi8, tMVN, tRSB >+ printPredicateOperand(MI, 3, O); >+ SStream_concat0(O, "\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 6 bits for 57 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 63); >+ switch ((Bits >> 24) & 63) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ printOperand(MI, 0, O); >+ break; >+ case 1: >+ // AESD, AESE, MCR2, MCRR2, MRRC2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1,... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM... >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP... >+ printPImmediate(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // CDP2 >+ printCImmediate(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 5: >+ // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS >+ printCPSIFlag(MI, 1, O); >+ break; >+ case 6: >+ // FCONSTD, FCONSTS, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfq, VACGEd... >+ SStream_concat0(O, ", "); >+ break; >+ case 7: >+ // ITasm, t2IT >+ printMandatoryPredicateOperand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // LDAEXD, LDREXD >+ printGPRPairOperand(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode7Operand(MI, 1, O); >+ return; >+ break; >+ case 9: >+ // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET >+ printAddrMode5Operand(MI, 2, O, false); >+ return; >+ break; >+ case 10: >+ // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_... >+ printAddrMode7Operand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 11: >+ // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE >+ printAddrMode5Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 12: >+ // MRC, t2MRC, t2MRC2 >+ printPImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 13: >+ // MSR, MSRi, t2MSR_AR, t2MSR_M >+ printMSRMaskOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 14: >+ // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ... >+ printNEONModImmOperand(MI, 1, O); >+ return; >+ break; >+ case 15: >+ // VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 16: >+ // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTs2fd, VCVTs2fq, VCVTu2fd, ... >+ return; >+ break; >+ case 17: >+ // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD... >+ printVectorListOneAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 18: >+ // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD... >+ printVectorListTwoAllLanes(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed... >+ printVectorListOne(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 20: >+ // VLD1d16Q, VLD1d16Qwb_fixed, VLD1d16Qwb_register, VLD1d32Q, VLD1d32Qwb_... >+ printVectorListFour(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // VLD1d16T, VLD1d16Twb_fixed, VLD1d16Twb_register, VLD1d32T, VLD1d32Twb_... >+ printVectorListThree(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed... >+ printVectorListTwo(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 23: >+ // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3... >+ printVectorListTwoSpacedAllLanes(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 24: >+ // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed... >+ printVectorListTwoSpaced(MI, 0, O, MRI); >+ SStream_concat0(O, ", "); >+ break; >+ case 25: >+ // VLD3DUPdAsm_16, VLD3DUPdAsm_32, VLD3DUPdAsm_8, VLD3DUPdWB_fixed_Asm_16... >+ printVectorListThreeAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 26: >+ // VLD3DUPqAsm_16, VLD3DUPqAsm_32, VLD3DUPqAsm_8, VLD3DUPqWB_fixed_Asm_16... >+ printVectorListThreeSpacedAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 27: >+ // VLD3qAsm_16, VLD3qAsm_32, VLD3qAsm_8, VLD3qWB_fixed_Asm_16, VLD3qWB_fi... >+ printVectorListThreeSpaced(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 28: >+ // VLD4DUPdAsm_16, VLD4DUPdAsm_32, VLD4DUPdAsm_8, VLD4DUPdWB_fixed_Asm_16... >+ printVectorListFourAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 29: >+ // VLD4DUPqAsm_16, VLD4DUPqAsm_32, VLD4DUPqAsm_8, VLD4DUPqWB_fixed_Asm_16... >+ printVectorListFourSpacedAllLanes(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 30: >+ // VLD4qAsm_16, VLD4qAsm_32, VLD4qAsm_8, VLD4qWB_fixed_Asm_16, VLD4qWB_fi... >+ printVectorListFourSpaced(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 31: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U... >+ printOperand(MI, 4, O); >+ break; >+ case 32: >+ // VST1d16, VST1d32, VST1d64, VST1d8 >+ printVectorListOne(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 33: >+ // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8 >+ printVectorListFour(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 34: >+ // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,... >+ printVectorListFour(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 35: >+ // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q... >+ printVectorListFour(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 36: >+ // VST1d16T, VST1d32T, VST1d64T, VST1d8T >+ printVectorListThree(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 37: >+ // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed >+ printVectorListThree(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 38: >+ // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T... >+ printVectorListThree(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 39: >+ // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed >+ printVectorListOne(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 40: >+ // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r... >+ printVectorListOne(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 41: >+ // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8 >+ printVectorListTwo(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 42: >+ // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST... >+ printVectorListTwo(MI, 3, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 43: >+ // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r... >+ printVectorListTwo(MI, 4, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 44: >+ // VST2b16, VST2b32, VST2b8 >+ printVectorListTwoSpaced(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 45: >+ // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed >+ printVectorListTwoSpaced(MI, 3, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 46: >+ // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register >+ printVectorListTwoSpaced(MI, 4, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode6Operand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 47: >+ // t2DMB, t2DSB >+ printMemBOption(MI, 0, O); >+ return; >+ break; >+ case 48: >+ // t2ISB >+ printInstSyncBOption(MI, 0, O); >+ return; >+ break; >+ case 49: >+ // t2PLDWi12, t2PLDi12, t2PLIi12 >+ printAddrModeImm12Operand(MI, 0, O, false); >+ return; >+ break; >+ case 50: >+ // t2PLDWi8, t2PLDi8, t2PLIi8 >+ printT2AddrModeImm8Operand(MI, 0, O, false); >+ return; >+ break; >+ case 51: >+ // t2PLDWs, t2PLDs, t2PLIs >+ printT2AddrModeSoRegOperand(MI, 0, O); >+ return; >+ break; >+ case 52: >+ // t2PLDpci, t2PLIpci >+ printThumbLdrLabelOperand(MI, 0, O); >+ return; >+ break; >+ case 53: >+ // t2TBB >+ printAddrModeTBB(MI, 0, O); >+ return; >+ break; >+ case 54: >+ // t2TBH >+ printAddrModeTBH(MI, 0, O); >+ return; >+ break; >+ case 55: >+ // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS... >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 56: >+ // tPOP, tPUSH >+ printRegisterList(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 5 bits for 28 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 30) & 31); >+ switch ((Bits >> 30) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // AESD, AESE, AESIMC, AESMC, BLX_pred, BL_pred, BXJ, BX_pred, Bcc, CPS2p... >+ return; >+ break; >+ case 2: >+ // CDP, MCR, MCRR, MRRC, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfq, VA... >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // FCONSTD, FCONSTS, VMOVv2f32, VMOVv4f32 >+ printFPImmOperand(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... >+ SStream_concat0(O, "!, "); >+ printRegisterList(MI, 4, O); >+ break; >+ case 5: >+ // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION >+ printCoprocOptionImm(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST >+ printPostIdxImm8s4Operand(MI, 3, O); >+ return; >+ break; >+ case 7: >+ // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,... >+ printCImmediate(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 8: >+ // MRS, t2MRS_AR >+ SStream_concat0(O, ", apsr"); >+ ARM_addReg(MI, ARM_REG_APSR); >+ return; >+ break; >+ case 9: >+ // MRSsys, t2MRSsys_AR >+ SStream_concat0(O, ", spsr"); >+ ARM_addReg(MI, ARM_REG_SPSR); >+ return; >+ break; >+ case 10: >+ // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,... >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 11: >+ // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTxs2fd, VCVTxs2fq, VCVT... >+ printOperand(MI, 2, O); >+ break; >+ case 12: >+ // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8 >+ printVectorIndex(MI, 2, O); >+ return; >+ break; >+ case 13: >+ // VLD1DUPd16, VLD1DUPd32, VLD1DUPd8, VLD1DUPq16, VLD1DUPq32, VLD1DUPq8, ... >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 14: >+ // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP... >+ printAddrMode6Operand(MI, 2, O); >+ break; >+ case 15: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ break; >+ case 16: >+ // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 2, O); >+ break; >+ case 17: >+ // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 18: >+ // VMRS >+ SStream_concat0(O, ", fpscr"); >+ ARM_addReg(MI, ARM_REG_FPSCR); >+ return; >+ break; >+ case 19: >+ // VMRS_FPEXC >+ SStream_concat0(O, ", fpexc"); >+ ARM_addReg(MI, ARM_REG_FPEXC); >+ return; >+ break; >+ case 20: >+ // VMRS_FPINST >+ SStream_concat0(O, ", fpinst"); >+ ARM_addReg(MI, ARM_REG_FPINST); >+ return; >+ break; >+ case 21: >+ // VMRS_FPINST2 >+ SStream_concat0(O, ", fpinst2"); >+ ARM_addReg(MI, ARM_REG_FPINST2); >+ return; >+ break; >+ case 22: >+ // VMRS_FPSID >+ SStream_concat0(O, ", fpsid"); >+ ARM_addReg(MI, ARM_REG_FPSID); >+ return; >+ break; >+ case 23: >+ // VMRS_MVFR0 >+ SStream_concat0(O, ", mvfr0"); >+ ARM_addReg(MI, ARM_REG_MVFR0); >+ return; >+ break; >+ case 24: >+ // VMRS_MVFR1 >+ SStream_concat0(O, ", mvfr1"); >+ ARM_addReg(MI, ARM_REG_MVFR1); >+ return; >+ break; >+ case 25: >+ // VMRS_MVFR2 >+ SStream_concat0(O, ", mvfr2"); >+ ARM_addReg(MI, ARM_REG_MVFR2); >+ return; >+ break; >+ case 26: >+ // VSETLNi16, VSETLNi32, VSETLNi8 >+ printVectorIndex(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 27: >+ // VSLTOD, VSLTOS, VTOSLD, VTOSLS, VTOULD, VTOULS, VULTOD, VULTOS >+ printFBits32(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 6 bits for 62 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 63); >+ switch ((Bits >> 35) & 63) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ANDri, ANDrr, ANDrsi, ASRi... >+ printOperand(MI, 1, O); >+ break; >+ case 1: >+ // ADR, t2ADR >+ printAdrLabelOperand(MI, 1, O, 0); >+ return; >+ break; >+ case 2: >+ // BFC, t2BFC >+ printBitfieldInvMaskImmOperand(MI, 2, O); >+ return; >+ break; >+ case 3: >+ // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16... >+ printOperand(MI, 2, O); >+ break; >+ case 4: >+ // CDP, MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, ... >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi >+ printSORegImmOperand(MI, 1, O); >+ return; >+ break; >+ case 6: >+ // CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr, t2MOVSsr, t2MOVsr >+ printSORegRegOperand(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U... >+ return; >+ break; >+ case 8: >+ // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM... >+ printRegisterList(MI, 3, O); >+ break; >+ case 9: >+ // LDA, LDAB, LDAEX, LDAEXB, LDAEXH, LDAH, LDRBT_POST, LDREX, LDREXB, LDR... >+ printAddrMode7Operand(MI, 1, O); >+ return; >+ break; >+ case 10: >+ // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD... >+ printAddrMode5Operand(MI, 2, O, false); >+ return; >+ break; >+ case 11: >+ // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO... >+ printAddrMode7Operand(MI, 2, O); >+ break; >+ case 12: >+ // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_... >+ printAddrMode5Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 13: >+ // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM >+ printAddrModeImm12Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 14: >+ // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG >+ printAddrMode2Operand(MI, 2, O); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 15: >+ // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB... >+ printAddrModeImm12Operand(MI, 1, O, false); >+ return; >+ break; >+ case 16: >+ // LDRBrs, LDRrs, STRBrs, STRrs >+ printAddrMode2Operand(MI, 1, O); >+ return; >+ break; >+ case 17: >+ // LDRH, LDRSB, LDRSH, STRH >+ printAddrMode3Operand(MI, 1, O, false); >+ return; >+ break; >+ case 18: >+ // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE >+ printAddrMode3Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 19: >+ // MCR2 >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 20: >+ // MCRR2, MRRC2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA256H, SHA256H2, SHA256S... >+ printOperand(MI, 3, O); >+ break; >+ case 21: >+ // SSAT, SSAT16, t2SSAT, t2SSAT16 >+ printImmPlusOneOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ break; >+ case 22: >+ // STLEXD, STREXD >+ printGPRPairOperand(MI, 1, O, MRI); >+ SStream_concat0(O, ", "); >+ printAddrMode7Operand(MI, 2, O); >+ return; >+ break; >+ case 23: >+ // VCEQzv2f32, VCEQzv4f32, VCGEzv2f32, VCGEzv4f32, VCGTzv2f32, VCGTzv4f32... >+ SStream_concat0(O, ", #0"); >+ op_addImm(MI, 0); >+ return; >+ break; >+ case 24: >+ // VLD1DUPd16wb_fixed, VLD1DUPd32wb_fixed, VLD1DUPd8wb_fixed, VLD1DUPq16w... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 25: >+ // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN... >+ printNoHashImmediate(MI, 4, O); >+ break; >+ case 26: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2... >+ printNoHashImmediate(MI, 6, O); >+ break; >+ case 27: >+ // VLD1LNdAsm_16, VLD1LNdAsm_32, VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_16, VL... >+ printAddrMode6Operand(MI, 2, O); >+ break; >+ case 28: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 29: >+ // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD... >+ SStream_concat0(O, "[]}, "); >+ break; >+ case 30: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 10, O); >+ break; >+ case 31: >+ // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD... >+ SStream_concat0(O, "[], "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "[]}, "); >+ break; >+ case 32: >+ // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U... >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 12, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ break; >+ case 33: >+ // VLDRD, VLDRS, VSTRD, VSTRS >+ printAddrMode5Operand(MI, 1, O, false); >+ return; >+ break; >+ case 34: >+ // VST1LNd16, VST1LNd32, VST1LNd8 >+ printNoHashImmediate(MI, 3, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 35: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3... >+ printNoHashImmediate(MI, 5, O); >+ break; >+ case 36: >+ // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U... >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 7, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 37: >+ // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 6, O); >+ break; >+ case 38: >+ // VTBL1 >+ printVectorListOne(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 39: >+ // VTBL2 >+ printVectorListTwo(MI, 1, O, MRI); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 40: >+ // VTBL3 >+ printVectorListThree(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 41: >+ // VTBL4 >+ printVectorListFour(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 42: >+ // VTBX1 >+ printVectorListOne(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 43: >+ // VTBX2 >+ printVectorListTwo(MI, 2, O, MRI); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 44: >+ // VTBX3 >+ printVectorListThree(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 45: >+ // VTBX4 >+ printVectorListFour(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ return; >+ break; >+ case 46: >+ // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ... >+ SStream_concat0(O, " ^"); >+ ARM_addUserMode(MI); >+ return; >+ break; >+ case 47: >+ // t2CMNzrs, t2CMPrs, t2MOVSsi, t2MOVsi, t2MVNs, t2TEQrs, t2TSTrs >+ printT2SOOperand(MI, 1, O); >+ return; >+ break; >+ case 48: >+ // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t... >+ printT2AddrModeImm8Operand(MI, 1, O, false); >+ return; >+ break; >+ case 49: >+ // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR... >+ printT2AddrModeImm8Operand(MI, 2, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 50: >+ // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci >+ printThumbLdrLabelOperand(MI, 1, O); >+ return; >+ break; >+ case 51: >+ // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs >+ printT2AddrModeSoRegOperand(MI, 1, O); >+ return; >+ break; >+ case 52: >+ // t2LDREX >+ printT2AddrModeImm0_1020s4Operand(MI, 1, O); >+ return; >+ break; >+ case 53: >+ // t2MRS_M >+ printMSRMaskOperand(MI, 1, O); >+ return; >+ break; >+ case 54: >+ // tADDspi, tSUBspi >+ printThumbS4ImmOperand(MI, 2, O); >+ return; >+ break; >+ case 55: >+ // tADR >+ printAdrLabelOperand(MI, 1, O, 2); >+ return; >+ break; >+ case 56: >+ // tASRri, tLSRri >+ printThumbSRImm(MI, 3, O); >+ return; >+ break; >+ case 57: >+ // tLDRBi, tSTRBi >+ printThumbAddrModeImm5S1Operand(MI, 1, O); >+ return; >+ break; >+ case 58: >+ // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr >+ printThumbAddrModeRROperand(MI, 1, O); >+ return; >+ break; >+ case 59: >+ // tLDRHi, tSTRHi >+ printThumbAddrModeImm5S2Operand(MI, 1, O); >+ return; >+ break; >+ case 60: >+ // tLDRi, tSTRi >+ printThumbAddrModeImm5S4Operand(MI, 1, O); >+ return; >+ break; >+ case 61: >+ // tLDRspi, tSTRspi >+ printThumbAddrModeSPOperand(MI, 1, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 5 bits for 23 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 41) & 31); >+ switch ((Bits >> 41) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ANDri, ANDrr, ANDrsi, ASRi... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // CDP, t2CDP, t2CDP2 >+ printCImmediate(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 2: >+ // CLZ, CMNri, CMNzrr, CMPri, CMPrr, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC... >+ return; >+ break; >+ case 3: >+ // MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, VADDD... >+ printOperand(MI, 2, O); >+ break; >+ case 4: >+ // SSAT, t2SSAT >+ printShiftImmOperand(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX... >+ printRotImmOperand(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN... >+ printVectorIndex(MI, 2, O); >+ return; >+ break; >+ case 7: >+ // VFMAD, VFMAS, VFMAfd, VFMAfq, VFMSD, VFMSS, VFMSfd, VFMSfq, VFNMAD, VF... >+ printOperand(MI, 3, O); >+ break; >+ case 8: >+ // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL... >+ printOperand(MI, 4, O); >+ return; >+ break; >+ case 9: >+ // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8... >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ break; >+ case 10: >+ // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,... >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 11: >+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L... >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ break; >+ case 12: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ break; >+ case 13: >+ // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8 >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 14: >+ // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... >+ printAddrMode6Operand(MI, 4, O); >+ break; >+ case 15: >+ // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP... >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ break; >+ case 16: >+ // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslv2i3... >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 17: >+ // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3... >+ printVectorIndex(MI, 3, O); >+ return; >+ break; >+ case 18: >+ // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8... >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 19: >+ // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 7, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 20: >+ // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ... >+ SStream_concat0(O, " ^"); >+ ARM_addUserMode(MI); >+ return; >+ break; >+ case 21: >+ // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST... >+ printT2AddrModeImm8OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 22: >+ // t2MOVsra_flag, t2MOVsrl_flag >+ SStream_concat0(O, ", #1"); >+ op_addImm(MI, 1); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 6 bits for 35 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 46) & 63); >+ switch ((Bits >> 46) & 63) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, ASRi, ASRr, BICri, BICrr, EO... >+ printOperand(MI, 2, O); >+ break; >+ case 1: >+ // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi... >+ printSORegImmOperand(MI, 2, O); >+ return; >+ break; >+ case 2: >+ // BFI, t2BFI >+ printBitfieldInvMaskImmOperand(MI, 3, O); >+ return; >+ break; >+ case 3: >+ // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD... >+ printCoprocOptionImm(MI, 3, O); >+ return; >+ break; >+ case 4: >+ // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t... >+ printPostIdxImm8s4Operand(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS... >+ printAddrMode2OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // LDRD, STRD >+ printAddrMode3Operand(MI, 2, O, false); >+ return; >+ break; >+ case 7: >+ // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST >+ printAddrMode7Operand(MI, 3, O); >+ break; >+ case 8: >+ // LDRD_PRE, STRD_PRE >+ printAddrMode3Operand(MI, 3, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 9: >+ // LDRHTi, LDRSBTi, LDRSHTi, STRHTi >+ printPostIdxImm8Operand(MI, 3, O); >+ return; >+ break; >+ case 10: >+ // LDRHTr, LDRSBTr, LDRSHTr, STRHTr >+ printPostIdxRegOperand(MI, 3, O); >+ return; >+ break; >+ case 11: >+ // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST >+ printAddrMode3OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 12: >+ // MCR, MCRR, MRRC, t2MCR, t2MCR2, t2MCRR, t2MCRR2, t2MRRC, t2MRRC2 >+ SStream_concat0(O, ", "); >+ break; >+ case 13: >+ // MCRR2, MRRC2 >+ printCImmediate(MI, 4, O); >+ return; >+ break; >+ case 14: >+ // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L... >+ printAddrMode7Operand(MI, 2, O); >+ return; >+ break; >+ case 15: >+ // VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, VADDD, VADDS, VADDfd, ... >+ return; >+ break; >+ case 16: >+ // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN... >+ printOperand(MI, 3, O); >+ break; >+ case 17: >+ // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8... >+ printAddrMode6Operand(MI, 1, O); >+ break; >+ case 18: >+ // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD >+ printAddrMode6Operand(MI, 2, O); >+ printAddrMode6OffsetOperand(MI, 4, O); >+ return; >+ break; >+ case 19: >+ // VLD1LNdWB_register_Asm_16, VLD1LNdWB_register_Asm_32, VLD1LNdWB_regist... >+ printOperand(MI, 4, O); >+ break; >+ case 20: >+ // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32 >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 2, O); >+ return; >+ break; >+ case 21: >+ // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U... >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 3, O); >+ printAddrMode6OffsetOperand(MI, 5, O); >+ return; >+ break; >+ case 22: >+ // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP... >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 23: >+ // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32 >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 8, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 24: >+ // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U... >+ printAddrMode6Operand(MI, 4, O); >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 25: >+ // VMLAslfd, VMLAslfq, VMLSslfd, VMLSslfq >+ printVectorIndex(MI, 4, O); >+ return; >+ break; >+ case 26: >+ // VMULslfd, VMULslfq >+ printVectorIndex(MI, 3, O); >+ return; >+ break; >+ case 27: >+ // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 28: >+ // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8... >+ printOperand(MI, 7, O); >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 1, O); >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 29: >+ // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs... >+ printT2SOOperand(MI, 2, O); >+ return; >+ break; >+ case 30: >+ // t2ASRri, t2LSRri >+ printThumbSRImm(MI, 2, O); >+ return; >+ break; >+ case 31: >+ // t2LDRD_PRE, t2STRD_PRE >+ printT2AddrModeImm8s4Operand(MI, 3, O, true); >+ SStream_concat0(O, "!"); >+ return; >+ break; >+ case 32: >+ // t2LDRDi8, t2STRDi8 >+ printT2AddrModeImm8s4Operand(MI, 2, O, false); >+ return; >+ break; >+ case 33: >+ // t2STREX >+ printT2AddrModeImm0_1020s4Operand(MI, 2, O); >+ return; >+ break; >+ case 34: >+ // tADDrSPi >+ printThumbS4ImmOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 7 encoded into 4 bits for 12 unique commands. >+ //printf("Frag-7: %"PRIu64"\n", (Bits >> 52) & 15); >+ switch ((Bits >> 52) & 15) { >+ default: // unreachable. >+ case 0: >+ // ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, ASRi, ASRr, BICri, BICrr, EO... >+ return; >+ break; >+ case 1: >+ // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // MCR, t2MCR, t2MCR2 >+ printCImmediate(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 3: >+ // MCRR, MRRC, t2MCRR, t2MCRR2, t2MRRC, t2MRRC2 >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printCImmediate(MI, 4, O); >+ return; >+ break; >+ case 4: >+ // PKHBT, t2PKHBT >+ printPKHLSLShiftImm(MI, 3, O); >+ return; >+ break; >+ case 5: >+ // PKHTB, t2PKHTB >+ printPKHASRShiftImm(MI, 3, O); >+ return; >+ break; >+ case 6: >+ // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX... >+ printRotImmOperand(MI, 3, O); >+ return; >+ break; >+ case 7: >+ // USAT, t2USAT >+ printShiftImmOperand(MI, 3, O); >+ return; >+ break; >+ case 8: >+ // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1... >+ SStream_concat0(O, "}, "); >+ break; >+ case 9: >+ // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L... >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ break; >+ case 10: >+ // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD >+ printAddrMode6OffsetOperand(MI, 3, O); >+ return; >+ break; >+ case 11: >+ // t2LDRD_POST, t2STRD_POST >+ printT2AddrModeImm8s4OffsetOperand(MI, 4, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 8 encoded into 4 bits for 13 unique commands. >+ //printf("Frag-8: %"PRIu64"\n", (Bits >> 56) & 15); >+ switch ((Bits >> 56) & 15) { >+ default: // unreachable. >+ case 0: >+ // LDRD_POST, STRD_POST >+ printAddrMode3OffsetOperand(MI, 4, O); >+ return; >+ break; >+ case 1: >+ // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... >+ printOperand(MI, 3, O); >+ break; >+ case 2: >+ // SBFX, UBFX, t2SBFX, t2UBFX >+ printImmPlusOneOperand(MI, 3, O); >+ return; >+ break; >+ case 3: >+ // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8 >+ printAddrMode6Operand(MI, 3, O); >+ return; >+ break; >+ case 4: >+ // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8... >+ printAddrMode6Operand(MI, 4, O); >+ printAddrMode6OffsetOperand(MI, 6, O); >+ return; >+ break; >+ case 5: >+ // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32 >+ printNoHashImmediate(MI, 10, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 4, O); >+ return; >+ break; >+ case 6: >+ // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32 >+ printNoHashImmediate(MI, 4, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 7: >+ // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32 >+ printNoHashImmediate(MI, 5, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 5, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8 >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32 >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 4, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "], "); >+ set_mem_access(MI, false); >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printNoHashImmediate(MI, 6, O); >+ SStream_concat0(O, "]}, "); >+ set_mem_access(MI, false); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8 >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "}, "); >+ printAddrMode6Operand(MI, 0, O); >+ return; >+ break; >+ case 11: >+ // t2SMLSLDX >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 12: >+ // t2STLEXD, t2STREXD >+ printAddrMode7Operand(MI, 3, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 9 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-9: %"PRIu64"\n", (Bits >> 60) & 1); >+ if ((Bits >> 60) & 1) { >+ // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1... >+ SStream_concat0(O, "}, "); >+ } else { >+ // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML... >+ return; >+ } >+ >+ >+ // Fragment 10 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-10: %"PRIu64"\n", (Bits >> 61) & 1); >+ if ((Bits >> 61) & 1) { >+ // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8... >+ printAddrMode6Operand(MI, 5, O); >+ printAddrMode6OffsetOperand(MI, 7, O); >+ return; >+ } else { >+ // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8 >+ printAddrMode6Operand(MI, 4, O); >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 289 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, >+ /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, >+ /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, >+ /* 39 */ 'd', '1', '0', 0, >+ /* 43 */ 'q', '1', '0', 0, >+ /* 47 */ 's', '1', '0', 0, >+ /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, >+ /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, >+ /* 83 */ 'd', '2', '0', 0, >+ /* 87 */ 's', '2', '0', 0, >+ /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, >+ /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, >+ /* 123 */ 'd', '3', '0', 0, >+ /* 127 */ 's', '3', '0', 0, >+ /* 131 */ 'd', '0', 0, >+ /* 134 */ 'q', '0', 0, >+ /* 137 */ 'm', 'v', 'f', 'r', '0', 0, >+ /* 143 */ 's', '0', 0, >+ /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, >+ /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, >+ /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, >+ /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0, >+ /* 192 */ 'd', '1', '1', 0, >+ /* 196 */ 'q', '1', '1', 0, >+ /* 200 */ 's', '1', '1', 0, >+ /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, >+ /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, >+ /* 232 */ 'd', '2', '1', 0, >+ /* 236 */ 's', '2', '1', 0, >+ /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, >+ /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, >+ /* 268 */ 'd', '3', '1', 0, >+ /* 272 */ 's', '3', '1', 0, >+ /* 276 */ 'Q', '0', '_', 'Q', '1', 0, >+ /* 282 */ 'R', '0', '_', 'R', '1', 0, >+ /* 288 */ 'd', '1', 0, >+ /* 291 */ 'q', '1', 0, >+ /* 294 */ 'm', 'v', 'f', 'r', '1', 0, >+ /* 300 */ 's', '1', 0, >+ /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, >+ /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, >+ /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, >+ /* 347 */ 'd', '1', '2', 0, >+ /* 351 */ 'q', '1', '2', 0, >+ /* 355 */ 's', '1', '2', 0, >+ /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, >+ /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, >+ /* 391 */ 'd', '2', '2', 0, >+ /* 395 */ 's', '2', '2', 0, >+ /* 399 */ 'D', '0', '_', 'D', '2', 0, >+ /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, >+ /* 414 */ 'Q', '1', '_', 'Q', '2', 0, >+ /* 420 */ 'd', '2', 0, >+ /* 423 */ 'q', '2', 0, >+ /* 426 */ 'm', 'v', 'f', 'r', '2', 0, >+ /* 432 */ 's', '2', 0, >+ /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, >+ /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, >+ /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, >+ /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, >+ /* 485 */ 'd', '1', '3', 0, >+ /* 489 */ 'q', '1', '3', 0, >+ /* 493 */ 's', '1', '3', 0, >+ /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, >+ /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, >+ /* 525 */ 'd', '2', '3', 0, >+ /* 529 */ 's', '2', '3', 0, >+ /* 533 */ 'D', '1', '_', 'D', '3', 0, >+ /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, >+ /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, >+ /* 560 */ 'R', '2', '_', 'R', '3', 0, >+ /* 566 */ 'd', '3', 0, >+ /* 569 */ 'q', '3', 0, >+ /* 572 */ 'r', '3', 0, >+ /* 575 */ 's', '3', 0, >+ /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, >+ /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, >+ /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, >+ /* 625 */ 'd', '1', '4', 0, >+ /* 629 */ 'q', '1', '4', 0, >+ /* 633 */ 's', '1', '4', 0, >+ /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, >+ /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, >+ /* 669 */ 'd', '2', '4', 0, >+ /* 673 */ 's', '2', '4', 0, >+ /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, >+ /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, >+ /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, >+ /* 710 */ 'd', '4', 0, >+ /* 713 */ 'q', '4', 0, >+ /* 716 */ 'r', '4', 0, >+ /* 719 */ 's', '4', 0, >+ /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, >+ /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, >+ /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, >+ /* 765 */ 'd', '1', '5', 0, >+ /* 769 */ 'q', '1', '5', 0, >+ /* 773 */ 's', '1', '5', 0, >+ /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, >+ /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, >+ /* 805 */ 'd', '2', '5', 0, >+ /* 809 */ 's', '2', '5', 0, >+ /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, >+ /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, >+ /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, >+ /* 843 */ 'R', '4', '_', 'R', '5', 0, >+ /* 849 */ 'd', '5', 0, >+ /* 852 */ 'q', '5', 0, >+ /* 855 */ 'r', '5', 0, >+ /* 858 */ 's', '5', 0, >+ /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, >+ /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, >+ /* 893 */ 'd', '1', '6', 0, >+ /* 897 */ 's', '1', '6', 0, >+ /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, >+ /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, >+ /* 933 */ 'd', '2', '6', 0, >+ /* 937 */ 's', '2', '6', 0, >+ /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, >+ /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, >+ /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, >+ /* 977 */ 'd', '6', 0, >+ /* 980 */ 'q', '6', 0, >+ /* 983 */ 'r', '6', 0, >+ /* 986 */ 's', '6', 0, >+ /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, >+ /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, >+ /* 1017 */ 'd', '1', '7', 0, >+ /* 1021 */ 's', '1', '7', 0, >+ /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, >+ /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, >+ /* 1053 */ 'd', '2', '7', 0, >+ /* 1057 */ 's', '2', '7', 0, >+ /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, >+ /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, >+ /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, >+ /* 1094 */ 'R', '6', '_', 'R', '7', 0, >+ /* 1100 */ 'd', '7', 0, >+ /* 1103 */ 'q', '7', 0, >+ /* 1106 */ 'r', '7', 0, >+ /* 1109 */ 's', '7', 0, >+ /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, >+ /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, >+ /* 1144 */ 'd', '1', '8', 0, >+ /* 1148 */ 's', '1', '8', 0, >+ /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, >+ /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, >+ /* 1184 */ 'd', '2', '8', 0, >+ /* 1188 */ 's', '2', '8', 0, >+ /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, >+ /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, >+ /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, >+ /* 1228 */ 'd', '8', 0, >+ /* 1231 */ 'q', '8', 0, >+ /* 1234 */ 'r', '8', 0, >+ /* 1237 */ 's', '8', 0, >+ /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, >+ /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, >+ /* 1268 */ 'd', '1', '9', 0, >+ /* 1272 */ 's', '1', '9', 0, >+ /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, >+ /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, >+ /* 1304 */ 'd', '2', '9', 0, >+ /* 1308 */ 's', '2', '9', 0, >+ /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, >+ /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, >+ /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, >+ /* 1345 */ 'R', '8', '_', 'R', '9', 0, >+ /* 1351 */ 'd', '9', 0, >+ /* 1354 */ 'q', '9', 0, >+ /* 1357 */ 's', '9', 0, >+ /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0, >+ /* 1367 */ 's', 'b', 0, >+ /* 1370 */ 'p', 'c', 0, >+ /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0, >+ /* 1379 */ 'f', 'p', 's', 'i', 'd', 0, >+ /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, >+ /* 1393 */ 's', 'l', 0, >+ /* 1396 */ 'f', 'p', 0, >+ /* 1399 */ 'i', 'p', 0, >+ /* 1402 */ 's', 'p', 0, >+ /* 1405 */ 'f', 'p', 's', 'c', 'r', 0, >+ /* 1411 */ 'l', 'r', 0, >+ /* 1414 */ 'a', 'p', 's', 'r', 0, >+ /* 1419 */ 'c', 'p', 's', 'r', 0, >+ /* 1424 */ 's', 'p', 's', 'r', 0, >+ /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0, >+ /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131, >+ 288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625, >+ 765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184, >+ 1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980, >+ 1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716, >+ 855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858, >+ 986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272, >+ 87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533, >+ 680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997, >+ 1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260, >+ 276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617, >+ 757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749, >+ 1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207, >+ 1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379, >+ 513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195, >+ 1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363, >+ 501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0, >+ 157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637, >+ 777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601, >+ 885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593, >+ 877, 1128, 67, 375, 653, 917, 1168, 107, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+// get registers with number only >+static const char *getRegisterName2(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 289 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, >+ /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, >+ /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, >+ /* 39 */ 'd', '1', '0', 0, >+ /* 43 */ 'q', '1', '0', 0, >+ /* 47 */ 'r', '1', '0', 0, >+ /* 51 */ 's', '1', '0', 0, >+ /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, >+ /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, >+ /* 87 */ 'd', '2', '0', 0, >+ /* 91 */ 's', '2', '0', 0, >+ /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, >+ /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, >+ /* 127 */ 'd', '3', '0', 0, >+ /* 131 */ 's', '3', '0', 0, >+ /* 135 */ 'd', '0', 0, >+ /* 138 */ 'q', '0', 0, >+ /* 141 */ 'm', 'v', 'f', 'r', '0', 0, >+ /* 147 */ 's', '0', 0, >+ /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, >+ /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, >+ /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, >+ /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0, >+ /* 196 */ 'd', '1', '1', 0, >+ /* 200 */ 'q', '1', '1', 0, >+ /* 204 */ 'r', '1', '1', 0, >+ /* 208 */ 's', '1', '1', 0, >+ /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, >+ /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, >+ /* 240 */ 'd', '2', '1', 0, >+ /* 244 */ 's', '2', '1', 0, >+ /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, >+ /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, >+ /* 276 */ 'd', '3', '1', 0, >+ /* 280 */ 's', '3', '1', 0, >+ /* 284 */ 'Q', '0', '_', 'Q', '1', 0, >+ /* 290 */ 'R', '0', '_', 'R', '1', 0, >+ /* 296 */ 'd', '1', 0, >+ /* 299 */ 'q', '1', 0, >+ /* 302 */ 'm', 'v', 'f', 'r', '1', 0, >+ /* 308 */ 's', '1', 0, >+ /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, >+ /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, >+ /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, >+ /* 355 */ 'd', '1', '2', 0, >+ /* 359 */ 'q', '1', '2', 0, >+ /* 363 */ 'r', '1', '2', 0, >+ /* 367 */ 's', '1', '2', 0, >+ /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, >+ /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, >+ /* 403 */ 'd', '2', '2', 0, >+ /* 407 */ 's', '2', '2', 0, >+ /* 411 */ 'D', '0', '_', 'D', '2', 0, >+ /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, >+ /* 426 */ 'Q', '1', '_', 'Q', '2', 0, >+ /* 432 */ 'd', '2', 0, >+ /* 435 */ 'q', '2', 0, >+ /* 438 */ 'm', 'v', 'f', 'r', '2', 0, >+ /* 444 */ 's', '2', 0, >+ /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0, >+ /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, >+ /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, >+ /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, >+ /* 497 */ 'd', '1', '3', 0, >+ /* 501 */ 'q', '1', '3', 0, >+ /* 505 */ 's', '1', '3', 0, >+ /* 509 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, >+ /* 525 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, >+ /* 537 */ 'd', '2', '3', 0, >+ /* 541 */ 's', '2', '3', 0, >+ /* 545 */ 'D', '1', '_', 'D', '3', 0, >+ /* 551 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, >+ /* 560 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, >+ /* 572 */ 'R', '2', '_', 'R', '3', 0, >+ /* 578 */ 'd', '3', 0, >+ /* 581 */ 'q', '3', 0, >+ /* 584 */ 'r', '3', 0, >+ /* 587 */ 's', '3', 0, >+ /* 590 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, >+ /* 605 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, >+ /* 621 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, >+ /* 637 */ 'd', '1', '4', 0, >+ /* 641 */ 'q', '1', '4', 0, >+ /* 645 */ 's', '1', '4', 0, >+ /* 649 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, >+ /* 665 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, >+ /* 681 */ 'd', '2', '4', 0, >+ /* 685 */ 's', '2', '4', 0, >+ /* 689 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, >+ /* 698 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, >+ /* 710 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, >+ /* 722 */ 'd', '4', 0, >+ /* 725 */ 'q', '4', 0, >+ /* 728 */ 'r', '4', 0, >+ /* 731 */ 's', '4', 0, >+ /* 734 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, >+ /* 749 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, >+ /* 761 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, >+ /* 777 */ 'd', '1', '5', 0, >+ /* 781 */ 'q', '1', '5', 0, >+ /* 785 */ 's', '1', '5', 0, >+ /* 789 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, >+ /* 805 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, >+ /* 817 */ 'd', '2', '5', 0, >+ /* 821 */ 's', '2', '5', 0, >+ /* 825 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, >+ /* 834 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, >+ /* 843 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, >+ /* 855 */ 'R', '4', '_', 'R', '5', 0, >+ /* 861 */ 'd', '5', 0, >+ /* 864 */ 'q', '5', 0, >+ /* 867 */ 'r', '5', 0, >+ /* 870 */ 's', '5', 0, >+ /* 873 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, >+ /* 889 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, >+ /* 905 */ 'd', '1', '6', 0, >+ /* 909 */ 's', '1', '6', 0, >+ /* 913 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, >+ /* 929 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, >+ /* 945 */ 'd', '2', '6', 0, >+ /* 949 */ 's', '2', '6', 0, >+ /* 953 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, >+ /* 965 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, >+ /* 977 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, >+ /* 989 */ 'd', '6', 0, >+ /* 992 */ 'q', '6', 0, >+ /* 995 */ 'r', '6', 0, >+ /* 998 */ 's', '6', 0, >+ /* 1001 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, >+ /* 1017 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, >+ /* 1029 */ 'd', '1', '7', 0, >+ /* 1033 */ 's', '1', '7', 0, >+ /* 1037 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, >+ /* 1053 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, >+ /* 1065 */ 'd', '2', '7', 0, >+ /* 1069 */ 's', '2', '7', 0, >+ /* 1073 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, >+ /* 1085 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, >+ /* 1094 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, >+ /* 1106 */ 'R', '6', '_', 'R', '7', 0, >+ /* 1112 */ 'd', '7', 0, >+ /* 1115 */ 'q', '7', 0, >+ /* 1118 */ 'r', '7', 0, >+ /* 1121 */ 's', '7', 0, >+ /* 1124 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, >+ /* 1140 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, >+ /* 1156 */ 'd', '1', '8', 0, >+ /* 1160 */ 's', '1', '8', 0, >+ /* 1164 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, >+ /* 1180 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, >+ /* 1196 */ 'd', '2', '8', 0, >+ /* 1200 */ 's', '2', '8', 0, >+ /* 1204 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, >+ /* 1216 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, >+ /* 1228 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, >+ /* 1240 */ 'd', '8', 0, >+ /* 1243 */ 'q', '8', 0, >+ /* 1246 */ 'r', '8', 0, >+ /* 1249 */ 's', '8', 0, >+ /* 1252 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, >+ /* 1268 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, >+ /* 1280 */ 'd', '1', '9', 0, >+ /* 1284 */ 's', '1', '9', 0, >+ /* 1288 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, >+ /* 1304 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, >+ /* 1316 */ 'd', '2', '9', 0, >+ /* 1320 */ 's', '2', '9', 0, >+ /* 1324 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, >+ /* 1336 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, >+ /* 1345 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, >+ /* 1357 */ 'R', '8', '_', 'R', '9', 0, >+ /* 1363 */ 'd', '9', 0, >+ /* 1366 */ 'q', '9', 0, >+ /* 1369 */ 'r', '9', 0, >+ /* 1372 */ 's', '9', 0, >+ /* 1375 */ 'R', '1', '2', '_', 'S', 'P', 0, >+ /* 1382 */ 'p', 'c', 0, >+ /* 1385 */ 'f', 'p', 'e', 'x', 'c', 0, >+ /* 1391 */ 'f', 'p', 's', 'i', 'd', 0, >+ /* 1397 */ 'i', 't', 's', 't', 'a', 't', 'e', 0, >+ /* 1405 */ 's', 'p', 0, >+ /* 1408 */ 'f', 'p', 's', 'c', 'r', 0, >+ /* 1414 */ 'l', 'r', 0, >+ /* 1417 */ 'a', 'p', 's', 'r', 0, >+ /* 1422 */ 'c', 'p', 's', 'r', 0, >+ /* 1427 */ 's', 'p', 's', 'r', 0, >+ /* 1432 */ 'f', 'p', 'i', 'n', 's', 't', 0, >+ /* 1439 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ /* 1450 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 1417, 1450, 1422, 1385, 1432, 1408, 1439, 1391, 1397, 1414, 1382, 1405, 1427, 135, >+ 296, 432, 578, 722, 861, 989, 1112, 1240, 1363, 39, 196, 355, 497, 637, >+ 777, 905, 1029, 1156, 1280, 87, 240, 403, 537, 681, 817, 945, 1065, 1196, >+ 1316, 127, 276, 447, 141, 302, 438, 138, 299, 435, 581, 725, 864, 992, >+ 1115, 1243, 1366, 43, 200, 359, 501, 641, 781, 144, 305, 441, 584, 728, >+ 867, 995, 1118, 1246, 1369, 47, 204, 363, 147, 308, 444, 587, 731, 870, >+ 998, 1121, 1249, 1372, 51, 208, 367, 505, 645, 785, 909, 1033, 1160, 1284, >+ 91, 244, 407, 541, 685, 821, 949, 1069, 1200, 1320, 131, 280, 411, 545, >+ 692, 828, 959, 1079, 1210, 1330, 6, 167, 317, 461, 597, 741, 881, 1009, >+ 1132, 1260, 63, 232, 379, 517, 657, 797, 921, 1045, 1172, 1296, 103, 268, >+ 284, 426, 566, 716, 849, 983, 1100, 1234, 1351, 32, 180, 347, 489, 629, >+ 769, 560, 710, 843, 977, 1094, 1228, 1345, 26, 174, 340, 481, 621, 761, >+ 1375, 290, 572, 855, 1106, 1357, 188, 417, 551, 701, 834, 968, 1085, 1219, >+ 1336, 16, 150, 328, 469, 609, 749, 893, 1017, 1144, 1268, 75, 212, 391, >+ 525, 669, 805, 933, 1053, 1184, 1304, 115, 248, 689, 825, 956, 1076, 1207, >+ 1327, 3, 164, 314, 458, 593, 737, 877, 1005, 1128, 1256, 59, 228, 375, >+ 513, 653, 793, 917, 1041, 1168, 1292, 99, 264, 953, 1073, 1204, 1324, 0, >+ 161, 311, 455, 590, 734, 873, 1001, 1124, 1252, 55, 224, 371, 509, 649, >+ 789, 913, 1037, 1164, 1288, 95, 260, 420, 704, 971, 1222, 19, 332, 613, >+ 897, 1148, 79, 395, 673, 937, 1188, 119, 698, 965, 1216, 13, 325, 605, >+ 889, 1140, 71, 387, 665, 929, 1180, 111, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+ switch (PrintMethodIdx) { >+ default: >+ // llvm_unreachable("Unknown PrintMethod kind"); >+ break; >+ case 0: >+ printPredicateOperand(MI, OpIdx, OS); >+ break; >+ case 1: >+ printSBitModifierOperand(MI, OpIdx, OS); >+ break; >+ case 2: >+ printFPImmOperand(MI, OpIdx, OS); >+ break; >+ case 3: >+ printRegisterList(MI, OpIdx, OS); >+ break; >+ case 4: >+ printPImmediate(MI, OpIdx, OS); >+ break; >+ case 5: >+ printCImmediate(MI, OpIdx, OS); >+ break; >+ case 6: >+ printImmPlusOneOperand(MI, OpIdx, OS); >+ break; >+ case 7: >+ printAddrMode5Operand(MI, OpIdx, OS, false); >+ break; >+ case 8: >+ printNEONModImmOperand(MI, OpIdx, OS); >+ break; >+ case 9: >+ printT2SOOperand(MI, OpIdx, OS); >+ break; >+ case 10: >+ printAdrLabelOperand<0>(MI, OpIdx, OS, 0); >+ break; >+ case 11: >+ printThumbSRImm(MI, OpIdx, OS); >+ break; >+ case 12: >+ printAddrModeImm12Operand(MI, OpIdx, OS, false); >+ break; >+ case 13: >+ printThumbLdrLabelOperand(MI, OpIdx, OS); >+ break; >+ case 14: >+ printT2AddrModeSoRegOperand(MI, OpIdx, OS); >+ break; >+ case 15: >+ printRotImmOperand(MI, OpIdx, OS); >+ break; >+ case 16: >+ printCPSIMod(MI, OpIdx, OS); >+ break; >+ } >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case ARM_ANDri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_BICri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_BKPT: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (BKPT 0) >+ AsmString = "bkpt"; >+ break; >+ } >+ return NULL; >+ case ARM_CMNri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_CMPri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_DMB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (DMB 15) >+ AsmString = "dmb"; >+ break; >+ } >+ return NULL; >+ case ARM_DSB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (DSB 15) >+ AsmString = "dsb"; >+ break; >+ } >+ return NULL; >+ case ARM_FCONSTD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p) >+ AsmString = "fconstd$\xFF\x03\x01} $\x01, $\xFF\x02\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_FCONSTS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p) >+ AsmString = "fconsts$\xFF\x03\x01} $\x01, $\xFF\x02\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_FMSTAT: >+ if (MCInst_getNumOperands(MI) == 2) { >+ // (FMSTAT pred:$p) >+ AsmString = "fmstat$\xFF\x01\x01}"; >+ break; >+ } >+ return NULL; >+ case ARM_HINT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (HINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (HINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (HINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (HINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (HINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (HINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_ISB: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (ISB 15) >+ AsmString = "isb"; >+ break; >+ } >+ return NULL; >+ case ARM_LDMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (LDMIA_UPD SP, pred:$p, reglist:$regs) >+ AsmString = "pop$\xFF\x02\x01} $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_MCR: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr$\xFF\x07\x01} $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MCR2: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0) >+ AsmString = "mcr2 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MLA: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 3)) { >+ // (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s) >+ AsmString = "mla$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_MOVi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02}$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_MOVi16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p) >+ AsmString = "mov$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_MRC: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc$\xFF\x07\x01} $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MRC2: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0) >+ AsmString = "mrc2 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_MRS: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (MRS GPRnopc:$Rd, pred:$p) >+ AsmString = "mrs$\xFF\x02\x01} $\x01, cpsr"; >+ break; >+ } >+ return NULL; >+ case ARM_MUL: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2)) { >+ // (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s) >+ AsmString = "mul$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_MVNi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s) >+ AsmString = "mov$\xFF\x05\x02}$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_RSBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s) >+ AsmString = "neg$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SMLAL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "smlal$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SMULL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "smull$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDA: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDA imm0_31:$mode) >+ AsmString = "srsda $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDA_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDA_UPD imm0_31:$mode) >+ AsmString = "srsda $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDB: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDB imm0_31:$mode) >+ AsmString = "srsdb $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSDB_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSDB_UPD imm0_31:$mode) >+ AsmString = "srsdb $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIA: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIA imm0_31:$mode) >+ AsmString = "srsia $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIA_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIA_UPD imm0_31:$mode) >+ AsmString = "srsia $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIB: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIB imm0_31:$mode) >+ AsmString = "srsib $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_SRSIB_UPD: >+ if (MCInst_getNumOperands(MI) == 1) { >+ // (SRSIB_UPD imm0_31:$mode) >+ AsmString = "srsib $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_SSAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p) >+ AsmString = "ssat$\xFF\x05\x01} $\x01, $\xFF\x02\x07, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_STMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (STMDB_UPD SP, pred:$p, reglist:$regs) >+ AsmString = "push$\xFF\x02\x01} $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_SUBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1)) { >+ // (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtab$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtab16$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtah$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtb$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_SXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "sxth$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UMLAL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "umlal$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_UMULL: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isReg(MCInst_getOperand(MI, 3)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 3)) { >+ // (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "umull$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\x03, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_USAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p) >+ AsmString = "usat$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtab$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtab16$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtah$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtb$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_UXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p) >+ AsmString = "uxth$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGEd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01}.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGEq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p) >+ AsmString = "vacle$\xFF\x04\x01}.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGTd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01}.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VACGTq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p) >+ AsmString = "vaclt$\xFF\x04\x01}.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VADDD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p) >+ AsmString = "faddd$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VADDS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 2)) { >+ // (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p) >+ AsmString = "fadds$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEfd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEfq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEsv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGEuv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vcle$\xFF\x04\x01}.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTfd: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTfq: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.f32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTsv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.s8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv16i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv2i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv4i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv4i32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u32 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv8i16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 2)) { >+ // (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u16 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCGTuv8i8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p) >+ AsmString = "vclt$\xFF\x04\x01}.u8 $\x01, $\x03, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VCMPZD: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VCMPZD DPR:$val, pred:$p) >+ AsmString = "fcmpzd$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_VCMPZS: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VCMPZS SPR:$val, pred:$p) >+ AsmString = "fcmpzs$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_VLDRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p) >+ AsmString = "vldr$\xFF\x04\x01}.64 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VLDRS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p) >+ AsmString = "vldr$\xFF\x04\x01}.32 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVDRR: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2)) { >+ // (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p) >+ AsmString = "vmov$\xFF\x04\x01}.f64 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVRRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p) >+ AsmString = "vmov$\xFF\x04\x01}.f64 $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VMOVS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VMOVS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VMVNv2i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01}.i32 $\x01, $\xFF\x02\x09"; >+ break; >+ } >+ return NULL; >+ case ARM_VMVNv4i32: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0)) { >+ // (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p) >+ AsmString = "vmov$\xFF\x03\x01}.i32 $\x01, $\xFF\x02\x09"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTAD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrinta.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTAND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTANQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTANQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTAS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTAS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrinta.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTMD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintm.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTMND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTMNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTMS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTMS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintm.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintn.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTNND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTNNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTNS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTNS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintn.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPD: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTPD DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintp.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTPND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTPNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTPS: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTPS SPR:$Sd, SPR:$Sm) >+ AsmString = "vrintp.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTRD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTRD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintr$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTRS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTRS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintr$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTXD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintx$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTXND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintx.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTXNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintx.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTXS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTXS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintx$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTZD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vrintz$\xFF\x03\x01.f64.f64 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZND: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VRINTZND DPR:$Dd, DPR:$Dm) >+ AsmString = "vrintz.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZNQ: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_QPRRegClassID, 1)) { >+ // (VRINTZNQ QPR:$Qd, QPR:$Qm) >+ AsmString = "vrintz.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VRINTZS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VRINTZS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vrintz$\xFF\x03\x01.f32.f32 $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSETLNi32: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { >+ // (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p) >+ AsmString = "fmdhr$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p) >+ AsmString = "fmdlr$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSQRTD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1)) { >+ // (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p) >+ AsmString = "vsqrt$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSQRTS: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1)) { >+ // (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p) >+ AsmString = "vsqrt$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_VSTRD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0)) { >+ // (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p) >+ AsmString = "vstr$\xFF\x04\x01}.64 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VSTRS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0)) { >+ // (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p) >+ AsmString = "vstr$\xFF\x04\x01}.32 $\x01, $\xFF\x02\x08"; >+ break; >+ } >+ return NULL; >+ case ARM_VSUBD: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_DPRRegClassID, 2)) { >+ // (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p) >+ AsmString = "fsubd$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_VSUBS: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_SPRRegClassID, 2)) { >+ // (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p) >+ AsmString = "fsubs$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADCrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "adc$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADCrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "adc$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDri12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 1)) { >+ // (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p) >+ AsmString = "add$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p) >+ AsmString = "add$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADDrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "add$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ADR: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p) >+ AsmString = "adr$\xFF\x03\x01} $\x01, $\xFF\x02\x0B"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ANDrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ANDrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ANDrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ANDrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "and$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ASRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ASRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s) >+ AsmString = "asr$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\xFF\x03\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ASRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ASRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "asr$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2BICrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2BICrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2BICrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2BICrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "bic$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNzrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMNzrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "cmn$\xFF\x04\x01} $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMPri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p) >+ AsmString = "cmn$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMPri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "cmp$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2CMPrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2CMPrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "cmp$\xFF\x04\x01} $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2DMB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2DMB 15, pred:$p) >+ AsmString = "dmb$\xFF\x02\x01}"; >+ break; >+ } >+ return NULL; >+ case ARM_t2DSB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2DSB 15, pred:$p) >+ AsmString = "dsb$\xFF\x02\x01}"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2EORri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x06\x02}$\xFF\x04\x01}.w $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2EORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2EORrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2EORrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "eor$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2HINT: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2HINT imm0_239:$imm, pred:$p) >+ AsmString = "hint$\xFF\x02\x01 $\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (t2HINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (t2HINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (t2HINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (t2HINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (t2HINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01.w"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (t2HINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01.w"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ISB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15) { >+ // (t2ISB 15, pred:$p) >+ AsmString = "isb$\xFF\x02\x01}"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMDB: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldmdb$\xFF\x02\x01}.w $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldmdb$\xFF\x02\x01}.w $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMIA: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01} $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01} $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x03\x01} $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x03\x01}.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrb$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x03\x01} $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x03\x01}.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrh$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x03\x01} $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x03\x01}.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrsb$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x03\x01} $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHpcrel: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x03\x01}.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRSHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldrsh$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRpci: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2LDRpci GPRnopc:$Rt, t2ldrlabel:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x03\x01} $\x01, $\xFF\x02\x0E"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LDRs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "ldr$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSLri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2LSLri rGPR:$Rd, rGPR:$Rn, imm0_31:$imm, pred:$p, cc_out:$s) >+ AsmString = "lsl$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSLrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2LSLrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "lsl$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2LSRri rGPR:$Rd, rGPR:$Rn, imm_sr:$imm, pred:$p, cc_out:$s) >+ AsmString = "lsr$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\xFF\x03\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_t2LSRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2LSRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "lsr$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MCR: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr$\xFF\x07\x01} $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MCR2: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mcr2$\xFF\x07\x01} $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MOVi16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p) >+ AsmString = "mov$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRC: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc$\xFF\x07\x01} $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRC2: >+ if (MCInst_getNumOperands(MI) == 8 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRwithAPSRRegClassID, 0) && >+ MCOperand_isImm(MCInst_getOperand(MI, 5)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 5)) == 0) { >+ // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p) >+ AsmString = "mrc2$\xFF\x07\x01} $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MRS_AR: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2MRS_AR GPR:$Rd, pred:$p) >+ AsmString = "mrs$\xFF\x02\x01} $\x01, cpsr"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MUL: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p) >+ AsmString = "mul$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNi: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02}$\xFF\x03\x01}.w $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNr: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x05\x02}$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2MVNs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "mvn$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ORNrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORNrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2ORNrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "orn$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x06\x02}$\xFF\x04\x01}.w $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2ORRrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2ORRrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2ORRrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, pred:$p, cc_out:$s) >+ AsmString = "orr$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2PLDpci: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "pld$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2PLIpci: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p) >+ AsmString = "pli$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REV: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "rev$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REV16: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "rev16$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2REVSH: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p) >+ AsmString = "revsh$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RORri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2RORri rGPR:$Rd, rGPR:$Rn, imm0_31:$imm, pred:$p, cc_out:$s) >+ AsmString = "ror$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RORrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2RORrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "ror$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s) >+ AsmString = "neg$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2RSBrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "rsb$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SBCrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "sbc$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SBCrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sbc$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSDB: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSDB imm0_31:$mode, pred:$p) >+ AsmString = "srsdb$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSDB_UPD: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSDB_UPD imm0_31:$mode, pred:$p) >+ AsmString = "srsdb$\xFF\x02\x01} $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSIA: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSIA imm0_31:$mode, pred:$p) >+ AsmString = "srsia$\xFF\x02\x01} $\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SRSIA_UPD: >+ if (MCInst_getNumOperands(MI) == 3) { >+ // (t2SRSIA_UPD imm0_31:$mode, pred:$p) >+ AsmString = "srsia$\xFF\x02\x01} $\x01!"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SSAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p) >+ AsmString = "ssat$\xFF\x05\x01} $\x01, $\xFF\x02\x07, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMDB: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMDB GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stmdb$\xFF\x02\x01}.w $\x01, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMDB_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stmdb$\xFF\x02\x01}.w $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STMIA_UPD: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "stm$\xFF\x02\x01} $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRBi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "strb$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRBs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "strb$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRHi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "strh$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRHs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0)) { >+ // (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "strh$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRi12: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p) >+ AsmString = "str$\xFF\x04\x01} $\x01, $\xFF\x02\x0D"; >+ break; >+ } >+ return NULL; >+ case ARM_t2STRs: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRRegClassID, 0)) { >+ // (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p) >+ AsmString = "str$\xFF\x05\x01} $\x01, $\xFF\x02\x0F"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SUBrr: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2)) { >+ // (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x06\x02}$\xFF\x04\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SUBrs: >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 1)) { >+ // (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\x02, $\xFF\x03\x0A"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 7 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s) >+ AsmString = "sub$\xFF\x07\x02}$\xFF\x05\x01} $\x01, $\xFF\x03\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtab$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtab16$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtah$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxtb$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxtb16$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2SXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "sxth$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TEQri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "teq$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "teq$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TEQrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TEQrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "teq$\xFF\x04\x01} $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTri: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TSTri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p) >+ AsmString = "tst$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTrr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p) >+ AsmString = "tst$\xFF\x03\x01} $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case ARM_t2TSTrs: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_GPRnopcRegClassID, 0)) { >+ // (t2TSTrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p) >+ AsmString = "tst$\xFF\x04\x01} $\x01, $\xFF\x02\x0A"; >+ break; >+ } >+ return NULL; >+ case ARM_t2USAT: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p) >+ AsmString = "usat$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAB: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtab$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAB16: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtab16$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTAH: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 2) && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtah$\xFF\x05\x01} $\x01, $\x02, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxtb$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTB16: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01} $\x01, $\x02"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxtb16$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_t2UXTH: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(ARM_rGPRRegClassID, 1)) { >+ // (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p) >+ AsmString = "uxth$\xFF\x04\x01} $\x01, $\x02$\xFF\x03\x10"; >+ break; >+ } >+ return NULL; >+ case ARM_tASRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p) >+ AsmString = "asr$\xFF\x02\x02}$\xFF\x05\x01} $\x01, $\xFF\x04\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_tBKPT: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (tBKPT 0) >+ AsmString = "bkpt"; >+ break; >+ } >+ return NULL; >+ case ARM_tHINT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (tHINT 0, pred:$p) >+ AsmString = "nop$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1) { >+ // (tHINT 1, pred:$p) >+ AsmString = "yield$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2) { >+ // (tHINT 2, pred:$p) >+ AsmString = "wfe$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3) { >+ // (tHINT 3, pred:$p) >+ AsmString = "wfi$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4) { >+ // (tHINT 4, pred:$p) >+ AsmString = "sev$\xFF\x02\x01"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5) { >+ // (tHINT 5, pred:$p) >+ AsmString = "sevl$\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case ARM_tLDMIA: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0)) { >+ // (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs) >+ AsmString = "ldm$\xFF\x02\x01} $\x01!, $\xFF\x04\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_tLSLri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p) >+ AsmString = "lsl$\xFF\x02\x02}$\xFF\x05\x01} $\x01, $\x04"; >+ break; >+ } >+ return NULL; >+ case ARM_tLSRri: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) { >+ // (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p) >+ AsmString = "lsr$\xFF\x02\x02}$\xFF\x05\x01} $\x01, $\xFF\x04\x0C"; >+ break; >+ } >+ return NULL; >+ case ARM_tMOVi8: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == ARM_CPSR && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14 && >+ MCOperand_isImm(MCInst_getOperand(MI, 4)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { >+ // (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0) >+ AsmString = "movs $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tMOVr: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_R8 && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == ARM_R8 && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14 && >+ MCOperand_isImm(MCInst_getOperand(MI, 3)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { >+ // (tMOVr R8, R8, 14, 0) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case ARM_tMUL: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 2)) { >+ // (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, pred:$p) >+ AsmString = "mul$\xFF\x02\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tRSB: >+ if (MCInst_getNumOperands(MI) == 5 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(ARM_tGPRRegClassID, 2)) { >+ // (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p) >+ AsmString = "neg$\xFF\x02\x02}$\xFF\x04\x01} $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case ARM_tSUBspi: >+ if (MCInst_getNumOperands(MI) == 4 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ // (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p) >+ AsmString = "add$\xFF\x03\x01} sp, $\x02"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..f58bd4056c514d537322666ffeedbefe10022c69 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenDisassemblerTables.inc >@@ -0,0 +1,13538 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * ARM Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#include "../../MCInst.h" >+#include "../../LEB128.h" >+ >+// Helper function for extracting fields from encoded instructions. >+#define FieldFromInstruction(fname, InsnType) \ >+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ >+{ \ >+ InsnType fieldMask; \ >+ if (numBits == sizeof(InsnType)*8) \ >+ fieldMask = (InsnType)(-1LL); \ >+ else \ >+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ >+ return (insn & fieldMask) >> startBit; \ >+} >+ >+static const uint8_t DecoderTableARM32[] = { >+/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 160, 11, // Skip to: 2983 >+/* 7 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 9, 6, // Skip to: 1559 >+/* 14 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 80, 1, // Skip to: 357 >+/* 21 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 103, 0, // Skip to: 131 >+/* 28 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 31 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 55 >+/* 35 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 48 >+/* 39 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 48 >+/* 45 */ MCD_OPC_Decode, 41, 0, // Opcode: ANDrr >+/* 48 */ MCD_OPC_CheckPredicate, 0, 142, 29, // Skip to: 7618 >+/* 52 */ MCD_OPC_Decode, 42, 1, // Opcode: ANDrsi >+/* 55 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 81 >+/* 59 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 73 >+/* 63 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 73 >+/* 69 */ MCD_OPC_Decode, 198, 3, 0, // Opcode: SUBrr >+/* 73 */ MCD_OPC_CheckPredicate, 0, 117, 29, // Skip to: 7618 >+/* 77 */ MCD_OPC_Decode, 199, 3, 1, // Opcode: SUBrsi >+/* 81 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 105 >+/* 85 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 98 >+/* 89 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 98 >+/* 95 */ MCD_OPC_Decode, 30, 0, // Opcode: ADDrr >+/* 98 */ MCD_OPC_CheckPredicate, 0, 92, 29, // Skip to: 7618 >+/* 102 */ MCD_OPC_Decode, 31, 1, // Opcode: ADDrsi >+/* 105 */ MCD_OPC_FilterValue, 3, 85, 29, // Skip to: 7618 >+/* 109 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 123 >+/* 113 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 123 >+/* 119 */ MCD_OPC_Decode, 179, 2, 0, // Opcode: SBCrr >+/* 123 */ MCD_OPC_CheckPredicate, 0, 67, 29, // Skip to: 7618 >+/* 127 */ MCD_OPC_Decode, 180, 2, 1, // Opcode: SBCrsi >+/* 131 */ MCD_OPC_FilterValue, 1, 59, 29, // Skip to: 7618 >+/* 135 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 138 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 191 >+/* 142 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 145 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 156 >+/* 149 */ MCD_OPC_CheckPredicate, 0, 41, 29, // Skip to: 7618 >+/* 153 */ MCD_OPC_Decode, 43, 2, // Opcode: ANDrsr >+/* 156 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 168 >+/* 160 */ MCD_OPC_CheckPredicate, 0, 30, 29, // Skip to: 7618 >+/* 164 */ MCD_OPC_Decode, 200, 3, 2, // Opcode: SUBrsr >+/* 168 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 179 >+/* 172 */ MCD_OPC_CheckPredicate, 0, 18, 29, // Skip to: 7618 >+/* 176 */ MCD_OPC_Decode, 32, 2, // Opcode: ADDrsr >+/* 179 */ MCD_OPC_FilterValue, 3, 11, 29, // Skip to: 7618 >+/* 183 */ MCD_OPC_CheckPredicate, 0, 7, 29, // Skip to: 7618 >+/* 187 */ MCD_OPC_Decode, 181, 2, 3, // Opcode: SBCrsr >+/* 191 */ MCD_OPC_FilterValue, 1, 255, 28, // Skip to: 7618 >+/* 195 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 198 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 264 >+/* 202 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 205 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 222 >+/* 209 */ MCD_OPC_CheckPredicate, 1, 237, 28, // Skip to: 7618 >+/* 213 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 218 */ MCD_OPC_Decode, 238, 1, 4, // Opcode: MUL >+/* 222 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 240 >+/* 226 */ MCD_OPC_CheckPredicate, 1, 220, 28, // Skip to: 7618 >+/* 230 */ MCD_OPC_CheckField, 20, 1, 0, 214, 28, // Skip to: 7618 >+/* 236 */ MCD_OPC_Decode, 237, 3, 5, // Opcode: UMAAL >+/* 240 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 252 >+/* 244 */ MCD_OPC_CheckPredicate, 1, 202, 28, // Skip to: 7618 >+/* 248 */ MCD_OPC_Decode, 240, 3, 6, // Opcode: UMULL >+/* 252 */ MCD_OPC_FilterValue, 3, 194, 28, // Skip to: 7618 >+/* 256 */ MCD_OPC_CheckPredicate, 1, 190, 28, // Skip to: 7618 >+/* 260 */ MCD_OPC_Decode, 233, 2, 6, // Opcode: SMULL >+/* 264 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 295 >+/* 268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 271 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 283 >+/* 275 */ MCD_OPC_CheckPredicate, 0, 171, 28, // Skip to: 7618 >+/* 279 */ MCD_OPC_Decode, 178, 3, 7, // Opcode: STRH_POST >+/* 283 */ MCD_OPC_FilterValue, 1, 163, 28, // Skip to: 7618 >+/* 287 */ MCD_OPC_CheckPredicate, 0, 159, 28, // Skip to: 7618 >+/* 291 */ MCD_OPC_Decode, 170, 1, 7, // Opcode: LDRH_POST >+/* 295 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 326 >+/* 299 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 302 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 314 >+/* 306 */ MCD_OPC_CheckPredicate, 0, 140, 28, // Skip to: 7618 >+/* 310 */ MCD_OPC_Decode, 161, 1, 7, // Opcode: LDRD_POST >+/* 314 */ MCD_OPC_FilterValue, 1, 132, 28, // Skip to: 7618 >+/* 318 */ MCD_OPC_CheckPredicate, 0, 128, 28, // Skip to: 7618 >+/* 322 */ MCD_OPC_Decode, 178, 1, 7, // Opcode: LDRSB_POST >+/* 326 */ MCD_OPC_FilterValue, 3, 120, 28, // Skip to: 7618 >+/* 330 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 345 >+/* 337 */ MCD_OPC_CheckPredicate, 0, 109, 28, // Skip to: 7618 >+/* 341 */ MCD_OPC_Decode, 169, 3, 7, // Opcode: STRD_POST >+/* 345 */ MCD_OPC_FilterValue, 1, 101, 28, // Skip to: 7618 >+/* 349 */ MCD_OPC_CheckPredicate, 0, 97, 28, // Skip to: 7618 >+/* 353 */ MCD_OPC_Decode, 183, 1, 7, // Opcode: LDRSH_POST >+/* 357 */ MCD_OPC_FilterValue, 1, 89, 28, // Skip to: 7618 >+/* 361 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 364 */ MCD_OPC_FilterValue, 0, 166, 1, // Skip to: 790 >+/* 368 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 371 */ MCD_OPC_FilterValue, 0, 93, 1, // Skip to: 724 >+/* 375 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 378 */ MCD_OPC_FilterValue, 0, 20, 1, // Skip to: 658 >+/* 382 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... >+/* 385 */ MCD_OPC_FilterValue, 14, 57, 0, // Skip to: 446 >+/* 389 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 392 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 419 >+/* 396 */ MCD_OPC_CheckPredicate, 2, 144, 0, // Skip to: 544 >+/* 400 */ MCD_OPC_CheckField, 6, 2, 1, 138, 0, // Skip to: 544 >+/* 406 */ MCD_OPC_CheckField, 4, 1, 0, 132, 0, // Skip to: 544 >+/* 412 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 416 */ MCD_OPC_Decode, 89, 8, // Opcode: CRC32B >+/* 419 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 544 >+/* 423 */ MCD_OPC_CheckPredicate, 2, 117, 0, // Skip to: 544 >+/* 427 */ MCD_OPC_CheckField, 6, 2, 1, 111, 0, // Skip to: 544 >+/* 433 */ MCD_OPC_CheckField, 4, 1, 0, 105, 0, // Skip to: 544 >+/* 439 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 443 */ MCD_OPC_Decode, 90, 8, // Opcode: CRC32CB >+/* 446 */ MCD_OPC_FilterValue, 15, 94, 0, // Skip to: 544 >+/* 450 */ MCD_OPC_ExtractField, 10, 8, // Inst{17-10} ... >+/* 453 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 476 >+/* 457 */ MCD_OPC_CheckPredicate, 0, 83, 0, // Skip to: 544 >+/* 461 */ MCD_OPC_CheckField, 9, 1, 0, 77, 0, // Skip to: 544 >+/* 467 */ MCD_OPC_CheckField, 0, 5, 0, 71, 0, // Skip to: 544 >+/* 473 */ MCD_OPC_Decode, 87, 9, // Opcode: CPS2p >+/* 476 */ MCD_OPC_FilterValue, 64, 26, 0, // Skip to: 506 >+/* 480 */ MCD_OPC_CheckPredicate, 0, 60, 0, // Skip to: 544 >+/* 484 */ MCD_OPC_CheckField, 18, 2, 0, 54, 0, // Skip to: 544 >+/* 490 */ MCD_OPC_CheckField, 6, 3, 0, 48, 0, // Skip to: 544 >+/* 496 */ MCD_OPC_CheckField, 0, 5, 0, 42, 0, // Skip to: 544 >+/* 502 */ MCD_OPC_Decode, 185, 2, 10, // Opcode: SETEND >+/* 506 */ MCD_OPC_FilterValue, 128, 1, 33, 0, // Skip to: 544 >+/* 511 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 514 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 544 >+/* 518 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 537 >+/* 522 */ MCD_OPC_CheckField, 18, 2, 0, 9, 0, // Skip to: 537 >+/* 528 */ MCD_OPC_CheckField, 6, 3, 0, 3, 0, // Skip to: 537 >+/* 534 */ MCD_OPC_Decode, 86, 9, // Opcode: CPS1p >+/* 537 */ MCD_OPC_CheckPredicate, 0, 3, 0, // Skip to: 544 >+/* 541 */ MCD_OPC_Decode, 88, 9, // Opcode: CPS3p >+/* 544 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 547 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 583 >+/* 551 */ MCD_OPC_CheckPredicate, 0, 140, 3, // Skip to: 1463 >+/* 555 */ MCD_OPC_CheckField, 16, 1, 1, 134, 3, // Skip to: 1463 >+/* 561 */ MCD_OPC_CheckField, 9, 1, 0, 128, 3, // Skip to: 1463 >+/* 567 */ MCD_OPC_CheckField, 4, 1, 0, 122, 3, // Skip to: 1463 >+/* 573 */ MCD_OPC_SoftFail, 143, 26 /* 0xD0F */, 128, 128, 56 /* 0xE0000 */, >+/* 579 */ MCD_OPC_Decode, 234, 1, 11, // Opcode: MRS >+/* 583 */ MCD_OPC_FilterValue, 1, 18, 0, // Skip to: 605 >+/* 587 */ MCD_OPC_CheckPredicate, 0, 104, 3, // Skip to: 1463 >+/* 591 */ MCD_OPC_CheckField, 4, 1, 1, 98, 3, // Skip to: 1463 >+/* 597 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 601 */ MCD_OPC_Decode, 138, 2, 12, // Opcode: QADD >+/* 605 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 640 >+/* 609 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 612 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 624 >+/* 616 */ MCD_OPC_CheckPredicate, 3, 75, 3, // Skip to: 1463 >+/* 620 */ MCD_OPC_Decode, 203, 2, 13, // Opcode: SMLABB >+/* 624 */ MCD_OPC_FilterValue, 1, 67, 3, // Skip to: 1463 >+/* 628 */ MCD_OPC_CheckPredicate, 4, 63, 3, // Skip to: 1463 >+/* 632 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 636 */ MCD_OPC_Decode, 202, 3, 14, // Opcode: SWP >+/* 640 */ MCD_OPC_FilterValue, 3, 51, 3, // Skip to: 1463 >+/* 644 */ MCD_OPC_CheckPredicate, 3, 47, 3, // Skip to: 1463 >+/* 648 */ MCD_OPC_CheckField, 4, 1, 0, 41, 3, // Skip to: 1463 >+/* 654 */ MCD_OPC_Decode, 204, 2, 13, // Opcode: SMLABT >+/* 658 */ MCD_OPC_FilterValue, 1, 33, 3, // Skip to: 1463 >+/* 662 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 665 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 688 >+/* 669 */ MCD_OPC_CheckPredicate, 5, 22, 3, // Skip to: 1463 >+/* 673 */ MCD_OPC_CheckField, 28, 4, 14, 16, 3, // Skip to: 1463 >+/* 679 */ MCD_OPC_CheckField, 4, 1, 1, 10, 3, // Skip to: 1463 >+/* 685 */ MCD_OPC_Decode, 112, 15, // Opcode: HLT >+/* 688 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 706 >+/* 692 */ MCD_OPC_CheckPredicate, 3, 255, 2, // Skip to: 1463 >+/* 696 */ MCD_OPC_CheckField, 4, 1, 0, 249, 2, // Skip to: 1463 >+/* 702 */ MCD_OPC_Decode, 215, 2, 13, // Opcode: SMLATB >+/* 706 */ MCD_OPC_FilterValue, 3, 241, 2, // Skip to: 1463 >+/* 710 */ MCD_OPC_CheckPredicate, 3, 237, 2, // Skip to: 1463 >+/* 714 */ MCD_OPC_CheckField, 4, 1, 0, 231, 2, // Skip to: 1463 >+/* 720 */ MCD_OPC_Decode, 216, 2, 13, // Opcode: SMLATT >+/* 724 */ MCD_OPC_FilterValue, 1, 223, 2, // Skip to: 1463 >+/* 728 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 731 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 767 >+/* 735 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 754 >+/* 739 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, // Skip to: 754 >+/* 745 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 750 */ MCD_OPC_Decode, 222, 3, 16, // Opcode: TSTrr >+/* 754 */ MCD_OPC_CheckPredicate, 0, 193, 2, // Skip to: 1463 >+/* 758 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 763 */ MCD_OPC_Decode, 223, 3, 17, // Opcode: TSTrsi >+/* 767 */ MCD_OPC_FilterValue, 1, 180, 2, // Skip to: 1463 >+/* 771 */ MCD_OPC_CheckPredicate, 0, 176, 2, // Skip to: 1463 >+/* 775 */ MCD_OPC_CheckField, 7, 1, 0, 170, 2, // Skip to: 1463 >+/* 781 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 786 */ MCD_OPC_Decode, 224, 3, 18, // Opcode: TSTrsr >+/* 790 */ MCD_OPC_FilterValue, 1, 252, 0, // Skip to: 1046 >+/* 794 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 797 */ MCD_OPC_FilterValue, 0, 165, 0, // Skip to: 966 >+/* 801 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 804 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 932 >+/* 808 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 811 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 835 >+/* 815 */ MCD_OPC_CheckPredicate, 0, 132, 2, // Skip to: 1463 >+/* 819 */ MCD_OPC_CheckField, 9, 1, 0, 126, 2, // Skip to: 1463 >+/* 825 */ MCD_OPC_SoftFail, 143, 26 /* 0xD0F */, 128, 128, 60 /* 0xF0000 */, >+/* 831 */ MCD_OPC_Decode, 235, 1, 11, // Opcode: MRSsys >+/* 835 */ MCD_OPC_FilterValue, 2, 45, 0, // Skip to: 884 >+/* 839 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 842 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 863 >+/* 846 */ MCD_OPC_CheckPredicate, 2, 101, 2, // Skip to: 1463 >+/* 850 */ MCD_OPC_CheckField, 28, 4, 14, 95, 2, // Skip to: 1463 >+/* 856 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 860 */ MCD_OPC_Decode, 94, 8, // Opcode: CRC32W >+/* 863 */ MCD_OPC_FilterValue, 1, 84, 2, // Skip to: 1463 >+/* 867 */ MCD_OPC_CheckPredicate, 2, 80, 2, // Skip to: 1463 >+/* 871 */ MCD_OPC_CheckField, 28, 4, 14, 74, 2, // Skip to: 1463 >+/* 877 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 881 */ MCD_OPC_Decode, 92, 8, // Opcode: CRC32CW >+/* 884 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 896 >+/* 888 */ MCD_OPC_CheckPredicate, 3, 59, 2, // Skip to: 1463 >+/* 892 */ MCD_OPC_Decode, 208, 2, 19, // Opcode: SMLALBB >+/* 896 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 908 >+/* 900 */ MCD_OPC_CheckPredicate, 3, 47, 2, // Skip to: 1463 >+/* 904 */ MCD_OPC_Decode, 212, 2, 19, // Opcode: SMLALTB >+/* 908 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 920 >+/* 912 */ MCD_OPC_CheckPredicate, 3, 35, 2, // Skip to: 1463 >+/* 916 */ MCD_OPC_Decode, 209, 2, 19, // Opcode: SMLALBT >+/* 920 */ MCD_OPC_FilterValue, 7, 27, 2, // Skip to: 1463 >+/* 924 */ MCD_OPC_CheckPredicate, 3, 23, 2, // Skip to: 1463 >+/* 928 */ MCD_OPC_Decode, 213, 2, 19, // Opcode: SMLALTT >+/* 932 */ MCD_OPC_FilterValue, 1, 15, 2, // Skip to: 1463 >+/* 936 */ MCD_OPC_CheckPredicate, 0, 14, 0, // Skip to: 954 >+/* 940 */ MCD_OPC_CheckField, 5, 7, 0, 8, 0, // Skip to: 954 >+/* 946 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 951 */ MCD_OPC_Decode, 81, 16, // Opcode: CMPrr >+/* 954 */ MCD_OPC_CheckPredicate, 0, 249, 1, // Skip to: 1463 >+/* 958 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 963 */ MCD_OPC_Decode, 82, 17, // Opcode: CMPrsi >+/* 966 */ MCD_OPC_FilterValue, 1, 237, 1, // Skip to: 1463 >+/* 970 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 973 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 1018 >+/* 977 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 980 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1002 >+/* 984 */ MCD_OPC_CheckPredicate, 0, 219, 1, // Skip to: 1463 >+/* 988 */ MCD_OPC_CheckField, 5, 2, 2, 213, 1, // Skip to: 1463 >+/* 994 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 998 */ MCD_OPC_Decode, 142, 2, 20, // Opcode: QDADD >+/* 1002 */ MCD_OPC_FilterValue, 1, 201, 1, // Skip to: 1463 >+/* 1006 */ MCD_OPC_CheckPredicate, 0, 197, 1, // Skip to: 1463 >+/* 1010 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 1015 */ MCD_OPC_Decode, 83, 18, // Opcode: CMPrsr >+/* 1018 */ MCD_OPC_FilterValue, 1, 185, 1, // Skip to: 1463 >+/* 1022 */ MCD_OPC_CheckPredicate, 4, 181, 1, // Skip to: 1463 >+/* 1026 */ MCD_OPC_CheckField, 20, 1, 0, 175, 1, // Skip to: 1463 >+/* 1032 */ MCD_OPC_CheckField, 5, 2, 0, 169, 1, // Skip to: 1463 >+/* 1038 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 1042 */ MCD_OPC_Decode, 203, 3, 14, // Opcode: SWPB >+/* 1046 */ MCD_OPC_FilterValue, 2, 206, 0, // Skip to: 1256 >+/* 1050 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1053 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 1079 >+/* 1057 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1071 >+/* 1061 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1071 >+/* 1067 */ MCD_OPC_Decode, 246, 1, 0, // Opcode: ORRrr >+/* 1071 */ MCD_OPC_CheckPredicate, 0, 132, 1, // Skip to: 1463 >+/* 1075 */ MCD_OPC_Decode, 247, 1, 1, // Opcode: ORRrsi >+/* 1079 */ MCD_OPC_FilterValue, 1, 124, 1, // Skip to: 1463 >+/* 1083 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 1086 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1098 >+/* 1090 */ MCD_OPC_CheckPredicate, 0, 113, 1, // Skip to: 1463 >+/* 1094 */ MCD_OPC_Decode, 248, 1, 2, // Opcode: ORRrsr >+/* 1098 */ MCD_OPC_FilterValue, 1, 105, 1, // Skip to: 1463 >+/* 1102 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1105 */ MCD_OPC_FilterValue, 12, 50, 0, // Skip to: 1159 >+/* 1109 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1112 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1136 >+/* 1116 */ MCD_OPC_CheckPredicate, 5, 87, 1, // Skip to: 1463 >+/* 1120 */ MCD_OPC_CheckField, 12, 4, 15, 81, 1, // Skip to: 1463 >+/* 1126 */ MCD_OPC_CheckField, 5, 2, 0, 75, 1, // Skip to: 1463 >+/* 1132 */ MCD_OPC_Decode, 142, 3, 21, // Opcode: STL >+/* 1136 */ MCD_OPC_FilterValue, 1, 67, 1, // Skip to: 1463 >+/* 1140 */ MCD_OPC_CheckPredicate, 5, 63, 1, // Skip to: 1463 >+/* 1144 */ MCD_OPC_CheckField, 5, 2, 0, 57, 1, // Skip to: 1463 >+/* 1150 */ MCD_OPC_CheckField, 0, 4, 15, 51, 1, // Skip to: 1463 >+/* 1156 */ MCD_OPC_Decode, 119, 22, // Opcode: LDA >+/* 1159 */ MCD_OPC_FilterValue, 14, 44, 0, // Skip to: 1207 >+/* 1163 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1166 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1184 >+/* 1170 */ MCD_OPC_CheckPredicate, 5, 33, 1, // Skip to: 1463 >+/* 1174 */ MCD_OPC_CheckField, 5, 2, 0, 27, 1, // Skip to: 1463 >+/* 1180 */ MCD_OPC_Decode, 144, 3, 23, // Opcode: STLEX >+/* 1184 */ MCD_OPC_FilterValue, 1, 19, 1, // Skip to: 1463 >+/* 1188 */ MCD_OPC_CheckPredicate, 5, 15, 1, // Skip to: 1463 >+/* 1192 */ MCD_OPC_CheckField, 5, 2, 0, 9, 1, // Skip to: 1463 >+/* 1198 */ MCD_OPC_CheckField, 0, 4, 15, 3, 1, // Skip to: 1463 >+/* 1204 */ MCD_OPC_Decode, 121, 22, // Opcode: LDAEX >+/* 1207 */ MCD_OPC_FilterValue, 15, 252, 0, // Skip to: 1463 >+/* 1211 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1214 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1232 >+/* 1218 */ MCD_OPC_CheckPredicate, 0, 241, 0, // Skip to: 1463 >+/* 1222 */ MCD_OPC_CheckField, 5, 2, 0, 235, 0, // Skip to: 1463 >+/* 1228 */ MCD_OPC_Decode, 171, 3, 23, // Opcode: STREX >+/* 1232 */ MCD_OPC_FilterValue, 1, 227, 0, // Skip to: 1463 >+/* 1236 */ MCD_OPC_CheckPredicate, 0, 223, 0, // Skip to: 1463 >+/* 1240 */ MCD_OPC_CheckField, 5, 2, 0, 217, 0, // Skip to: 1463 >+/* 1246 */ MCD_OPC_CheckField, 0, 4, 15, 211, 0, // Skip to: 1463 >+/* 1252 */ MCD_OPC_Decode, 163, 1, 22, // Opcode: LDREX >+/* 1256 */ MCD_OPC_FilterValue, 3, 203, 0, // Skip to: 1463 >+/* 1260 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1263 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1287 >+/* 1267 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1280 >+/* 1271 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1280 >+/* 1277 */ MCD_OPC_Decode, 52, 0, // Opcode: BICrr >+/* 1280 */ MCD_OPC_CheckPredicate, 0, 179, 0, // Skip to: 1463 >+/* 1284 */ MCD_OPC_Decode, 53, 1, // Opcode: BICrsi >+/* 1287 */ MCD_OPC_FilterValue, 1, 172, 0, // Skip to: 1463 >+/* 1291 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 1294 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 1305 >+/* 1298 */ MCD_OPC_CheckPredicate, 0, 161, 0, // Skip to: 1463 >+/* 1302 */ MCD_OPC_Decode, 54, 2, // Opcode: BICrsr >+/* 1305 */ MCD_OPC_FilterValue, 1, 154, 0, // Skip to: 1463 >+/* 1309 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1312 */ MCD_OPC_FilterValue, 12, 50, 0, // Skip to: 1366 >+/* 1316 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1319 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1343 >+/* 1323 */ MCD_OPC_CheckPredicate, 5, 136, 0, // Skip to: 1463 >+/* 1327 */ MCD_OPC_CheckField, 12, 4, 15, 130, 0, // Skip to: 1463 >+/* 1333 */ MCD_OPC_CheckField, 5, 2, 0, 124, 0, // Skip to: 1463 >+/* 1339 */ MCD_OPC_Decode, 143, 3, 21, // Opcode: STLB >+/* 1343 */ MCD_OPC_FilterValue, 1, 116, 0, // Skip to: 1463 >+/* 1347 */ MCD_OPC_CheckPredicate, 5, 112, 0, // Skip to: 1463 >+/* 1351 */ MCD_OPC_CheckField, 5, 2, 0, 106, 0, // Skip to: 1463 >+/* 1357 */ MCD_OPC_CheckField, 0, 4, 15, 100, 0, // Skip to: 1463 >+/* 1363 */ MCD_OPC_Decode, 120, 22, // Opcode: LDAB >+/* 1366 */ MCD_OPC_FilterValue, 14, 44, 0, // Skip to: 1414 >+/* 1370 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1373 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1391 >+/* 1377 */ MCD_OPC_CheckPredicate, 5, 82, 0, // Skip to: 1463 >+/* 1381 */ MCD_OPC_CheckField, 5, 2, 0, 76, 0, // Skip to: 1463 >+/* 1387 */ MCD_OPC_Decode, 145, 3, 23, // Opcode: STLEXB >+/* 1391 */ MCD_OPC_FilterValue, 1, 68, 0, // Skip to: 1463 >+/* 1395 */ MCD_OPC_CheckPredicate, 5, 64, 0, // Skip to: 1463 >+/* 1399 */ MCD_OPC_CheckField, 5, 2, 0, 58, 0, // Skip to: 1463 >+/* 1405 */ MCD_OPC_CheckField, 0, 4, 15, 52, 0, // Skip to: 1463 >+/* 1411 */ MCD_OPC_Decode, 122, 22, // Opcode: LDAEXB >+/* 1414 */ MCD_OPC_FilterValue, 15, 45, 0, // Skip to: 1463 >+/* 1418 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1421 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1439 >+/* 1425 */ MCD_OPC_CheckPredicate, 0, 34, 0, // Skip to: 1463 >+/* 1429 */ MCD_OPC_CheckField, 5, 2, 0, 28, 0, // Skip to: 1463 >+/* 1435 */ MCD_OPC_Decode, 172, 3, 23, // Opcode: STREXB >+/* 1439 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 1463 >+/* 1443 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 1463 >+/* 1447 */ MCD_OPC_CheckField, 5, 2, 0, 10, 0, // Skip to: 1463 >+/* 1453 */ MCD_OPC_CheckField, 0, 4, 15, 4, 0, // Skip to: 1463 >+/* 1459 */ MCD_OPC_Decode, 164, 1, 22, // Opcode: LDREXB >+/* 1463 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1466 */ MCD_OPC_FilterValue, 11, 27, 0, // Skip to: 1497 >+/* 1470 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1473 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1485 >+/* 1477 */ MCD_OPC_CheckPredicate, 0, 249, 23, // Skip to: 7618 >+/* 1481 */ MCD_OPC_Decode, 175, 3, 7, // Opcode: STRH >+/* 1485 */ MCD_OPC_FilterValue, 1, 241, 23, // Skip to: 7618 >+/* 1489 */ MCD_OPC_CheckPredicate, 0, 237, 23, // Skip to: 7618 >+/* 1493 */ MCD_OPC_Decode, 167, 1, 7, // Opcode: LDRH >+/* 1497 */ MCD_OPC_FilterValue, 13, 27, 0, // Skip to: 1528 >+/* 1501 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1504 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1516 >+/* 1508 */ MCD_OPC_CheckPredicate, 3, 218, 23, // Skip to: 7618 >+/* 1512 */ MCD_OPC_Decode, 160, 1, 7, // Opcode: LDRD >+/* 1516 */ MCD_OPC_FilterValue, 1, 210, 23, // Skip to: 7618 >+/* 1520 */ MCD_OPC_CheckPredicate, 0, 206, 23, // Skip to: 7618 >+/* 1524 */ MCD_OPC_Decode, 175, 1, 7, // Opcode: LDRSB >+/* 1528 */ MCD_OPC_FilterValue, 15, 198, 23, // Skip to: 7618 >+/* 1532 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1535 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1547 >+/* 1539 */ MCD_OPC_CheckPredicate, 3, 187, 23, // Skip to: 7618 >+/* 1543 */ MCD_OPC_Decode, 168, 3, 7, // Opcode: STRD >+/* 1547 */ MCD_OPC_FilterValue, 1, 179, 23, // Skip to: 7618 >+/* 1551 */ MCD_OPC_CheckPredicate, 0, 175, 23, // Skip to: 7618 >+/* 1555 */ MCD_OPC_Decode, 180, 1, 7, // Opcode: LDRSH >+/* 1559 */ MCD_OPC_FilterValue, 1, 167, 23, // Skip to: 7618 >+/* 1563 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 1566 */ MCD_OPC_FilterValue, 0, 32, 2, // Skip to: 2114 >+/* 1570 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 1573 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 1630 >+/* 1577 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1580 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1604 >+/* 1584 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1597 >+/* 1588 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1597 >+/* 1594 */ MCD_OPC_Decode, 99, 0, // Opcode: EORrr >+/* 1597 */ MCD_OPC_CheckPredicate, 0, 129, 23, // Skip to: 7618 >+/* 1601 */ MCD_OPC_Decode, 100, 1, // Opcode: EORrsi >+/* 1604 */ MCD_OPC_FilterValue, 1, 122, 23, // Skip to: 7618 >+/* 1608 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1622 >+/* 1612 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1622 >+/* 1618 */ MCD_OPC_Decode, 168, 2, 0, // Opcode: RSBrr >+/* 1622 */ MCD_OPC_CheckPredicate, 0, 104, 23, // Skip to: 7618 >+/* 1626 */ MCD_OPC_Decode, 169, 2, 1, // Opcode: RSBrsi >+/* 1630 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 1687 >+/* 1634 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1637 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 1661 >+/* 1641 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 1654 >+/* 1645 */ MCD_OPC_CheckField, 5, 7, 0, 3, 0, // Skip to: 1654 >+/* 1651 */ MCD_OPC_Decode, 22, 0, // Opcode: ADCrr >+/* 1654 */ MCD_OPC_CheckPredicate, 0, 72, 23, // Skip to: 7618 >+/* 1658 */ MCD_OPC_Decode, 23, 1, // Opcode: ADCrsi >+/* 1661 */ MCD_OPC_FilterValue, 1, 65, 23, // Skip to: 7618 >+/* 1665 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 1679 >+/* 1669 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 1679 >+/* 1675 */ MCD_OPC_Decode, 172, 2, 0, // Opcode: RSCrr >+/* 1679 */ MCD_OPC_CheckPredicate, 0, 47, 23, // Skip to: 7618 >+/* 1683 */ MCD_OPC_Decode, 173, 2, 1, // Opcode: RSCrsi >+/* 1687 */ MCD_OPC_FilterValue, 2, 59, 1, // Skip to: 2006 >+/* 1691 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 1694 */ MCD_OPC_FilterValue, 0, 231, 0, // Skip to: 1929 >+/* 1698 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1701 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1720 >+/* 1705 */ MCD_OPC_CheckPredicate, 0, 21, 23, // Skip to: 7618 >+/* 1709 */ MCD_OPC_CheckField, 8, 8, 240, 1, 14, 23, // Skip to: 7618 >+/* 1716 */ MCD_OPC_Decode, 236, 1, 24, // Opcode: MSR >+/* 1720 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 1744 >+/* 1724 */ MCD_OPC_CheckPredicate, 0, 2, 23, // Skip to: 7618 >+/* 1728 */ MCD_OPC_CheckField, 22, 1, 0, 252, 22, // Skip to: 7618 >+/* 1734 */ MCD_OPC_CheckField, 8, 12, 255, 31, 245, 22, // Skip to: 7618 >+/* 1741 */ MCD_OPC_Decode, 67, 25, // Opcode: BXJ >+/* 1744 */ MCD_OPC_FilterValue, 2, 57, 0, // Skip to: 1805 >+/* 1748 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 1751 */ MCD_OPC_FilterValue, 0, 23, 0, // Skip to: 1778 >+/* 1755 */ MCD_OPC_CheckPredicate, 2, 227, 22, // Skip to: 7618 >+/* 1759 */ MCD_OPC_CheckField, 28, 4, 14, 221, 22, // Skip to: 7618 >+/* 1765 */ MCD_OPC_CheckField, 22, 1, 0, 215, 22, // Skip to: 7618 >+/* 1771 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 1775 */ MCD_OPC_Decode, 93, 8, // Opcode: CRC32H >+/* 1778 */ MCD_OPC_FilterValue, 1, 204, 22, // Skip to: 7618 >+/* 1782 */ MCD_OPC_CheckPredicate, 2, 200, 22, // Skip to: 7618 >+/* 1786 */ MCD_OPC_CheckField, 28, 4, 14, 194, 22, // Skip to: 7618 >+/* 1792 */ MCD_OPC_CheckField, 22, 1, 0, 188, 22, // Skip to: 7618 >+/* 1798 */ MCD_OPC_SoftFail, 128, 26 /* 0xD00 */, 0, >+/* 1802 */ MCD_OPC_Decode, 91, 8, // Opcode: CRC32CH >+/* 1805 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 1836 >+/* 1809 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1812 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1824 >+/* 1816 */ MCD_OPC_CheckPredicate, 3, 166, 22, // Skip to: 7618 >+/* 1820 */ MCD_OPC_Decode, 217, 2, 13, // Opcode: SMLAWB >+/* 1824 */ MCD_OPC_FilterValue, 1, 158, 22, // Skip to: 7618 >+/* 1828 */ MCD_OPC_CheckPredicate, 3, 154, 22, // Skip to: 7618 >+/* 1832 */ MCD_OPC_Decode, 231, 2, 26, // Opcode: SMULBB >+/* 1836 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 1867 >+/* 1840 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1843 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1855 >+/* 1847 */ MCD_OPC_CheckPredicate, 3, 135, 22, // Skip to: 7618 >+/* 1851 */ MCD_OPC_Decode, 237, 2, 26, // Opcode: SMULWB >+/* 1855 */ MCD_OPC_FilterValue, 1, 127, 22, // Skip to: 7618 >+/* 1859 */ MCD_OPC_CheckPredicate, 3, 123, 22, // Skip to: 7618 >+/* 1863 */ MCD_OPC_Decode, 235, 2, 26, // Opcode: SMULTB >+/* 1867 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 1898 >+/* 1871 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1874 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1886 >+/* 1878 */ MCD_OPC_CheckPredicate, 3, 104, 22, // Skip to: 7618 >+/* 1882 */ MCD_OPC_Decode, 218, 2, 13, // Opcode: SMLAWT >+/* 1886 */ MCD_OPC_FilterValue, 1, 96, 22, // Skip to: 7618 >+/* 1890 */ MCD_OPC_CheckPredicate, 3, 92, 22, // Skip to: 7618 >+/* 1894 */ MCD_OPC_Decode, 232, 2, 26, // Opcode: SMULBT >+/* 1898 */ MCD_OPC_FilterValue, 7, 84, 22, // Skip to: 7618 >+/* 1902 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1905 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1917 >+/* 1909 */ MCD_OPC_CheckPredicate, 3, 73, 22, // Skip to: 7618 >+/* 1913 */ MCD_OPC_Decode, 238, 2, 26, // Opcode: SMULWT >+/* 1917 */ MCD_OPC_FilterValue, 1, 65, 22, // Skip to: 7618 >+/* 1921 */ MCD_OPC_CheckPredicate, 3, 61, 22, // Skip to: 7618 >+/* 1925 */ MCD_OPC_Decode, 236, 2, 26, // Opcode: SMULTT >+/* 1929 */ MCD_OPC_FilterValue, 1, 53, 22, // Skip to: 7618 >+/* 1933 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1936 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 1972 >+/* 1940 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 1959 >+/* 1944 */ MCD_OPC_CheckField, 5, 7, 0, 9, 0, // Skip to: 1959 >+/* 1950 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 1955 */ MCD_OPC_Decode, 215, 3, 16, // Opcode: TEQrr >+/* 1959 */ MCD_OPC_CheckPredicate, 0, 23, 22, // Skip to: 7618 >+/* 1963 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 1968 */ MCD_OPC_Decode, 216, 3, 17, // Opcode: TEQrsi >+/* 1972 */ MCD_OPC_FilterValue, 1, 10, 22, // Skip to: 7618 >+/* 1976 */ MCD_OPC_CheckPredicate, 0, 14, 0, // Skip to: 1994 >+/* 1980 */ MCD_OPC_CheckField, 5, 7, 0, 8, 0, // Skip to: 1994 >+/* 1986 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 1991 */ MCD_OPC_Decode, 77, 16, // Opcode: CMNzrr >+/* 1994 */ MCD_OPC_CheckPredicate, 0, 244, 21, // Skip to: 7618 >+/* 1998 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2003 */ MCD_OPC_Decode, 78, 17, // Opcode: CMNzrsi >+/* 2006 */ MCD_OPC_FilterValue, 3, 232, 21, // Skip to: 7618 >+/* 2010 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2013 */ MCD_OPC_FilterValue, 0, 64, 0, // Skip to: 2081 >+/* 2017 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 2038 >+/* 2021 */ MCD_OPC_CheckField, 5, 16, 128, 15, 10, 0, // Skip to: 2038 >+/* 2028 */ MCD_OPC_CheckField, 0, 4, 14, 4, 0, // Skip to: 2038 >+/* 2034 */ MCD_OPC_Decode, 214, 1, 27, // Opcode: MOVPCLR >+/* 2038 */ MCD_OPC_ExtractField, 5, 7, // Inst{11-5} ... >+/* 2041 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 2067 >+/* 2045 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2059 >+/* 2049 */ MCD_OPC_CheckField, 16, 4, 0, 4, 0, // Skip to: 2059 >+/* 2055 */ MCD_OPC_Decode, 224, 1, 28, // Opcode: MOVr >+/* 2059 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 2067 >+/* 2063 */ MCD_OPC_Decode, 225, 1, 29, // Opcode: MOVr_TC >+/* 2067 */ MCD_OPC_CheckPredicate, 0, 171, 21, // Skip to: 7618 >+/* 2071 */ MCD_OPC_CheckField, 16, 4, 0, 165, 21, // Skip to: 7618 >+/* 2077 */ MCD_OPC_Decode, 226, 1, 30, // Opcode: MOVsi >+/* 2081 */ MCD_OPC_FilterValue, 1, 157, 21, // Skip to: 7618 >+/* 2085 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2088 */ MCD_OPC_FilterValue, 0, 150, 21, // Skip to: 7618 >+/* 2092 */ MCD_OPC_CheckPredicate, 0, 10, 0, // Skip to: 2106 >+/* 2096 */ MCD_OPC_CheckField, 5, 7, 0, 4, 0, // Skip to: 2106 >+/* 2102 */ MCD_OPC_Decode, 242, 1, 28, // Opcode: MVNr >+/* 2106 */ MCD_OPC_CheckPredicate, 0, 132, 21, // Skip to: 7618 >+/* 2110 */ MCD_OPC_Decode, 243, 1, 30, // Opcode: MVNsi >+/* 2114 */ MCD_OPC_FilterValue, 1, 124, 21, // Skip to: 7618 >+/* 2118 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 2121 */ MCD_OPC_FilterValue, 0, 57, 1, // Skip to: 2438 >+/* 2125 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... >+/* 2128 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 2139 >+/* 2132 */ MCD_OPC_CheckPredicate, 0, 106, 21, // Skip to: 7618 >+/* 2136 */ MCD_OPC_Decode, 101, 2, // Opcode: EORrsr >+/* 2139 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2151 >+/* 2143 */ MCD_OPC_CheckPredicate, 0, 95, 21, // Skip to: 7618 >+/* 2147 */ MCD_OPC_Decode, 170, 2, 2, // Opcode: RSBrsr >+/* 2151 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 2162 >+/* 2155 */ MCD_OPC_CheckPredicate, 0, 83, 21, // Skip to: 7618 >+/* 2159 */ MCD_OPC_Decode, 24, 3, // Opcode: ADCrsr >+/* 2162 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2174 >+/* 2166 */ MCD_OPC_CheckPredicate, 0, 72, 21, // Skip to: 7618 >+/* 2170 */ MCD_OPC_Decode, 174, 2, 2, // Opcode: RSCrsr >+/* 2174 */ MCD_OPC_FilterValue, 4, 137, 0, // Skip to: 2315 >+/* 2178 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2181 */ MCD_OPC_FilterValue, 0, 113, 0, // Skip to: 2298 >+/* 2185 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2188 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 2233 >+/* 2192 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... >+/* 2195 */ MCD_OPC_FilterValue, 255, 31, 42, 21, // Skip to: 7618 >+/* 2200 */ MCD_OPC_CheckPredicate, 6, 9, 0, // Skip to: 2213 >+/* 2204 */ MCD_OPC_CheckField, 0, 4, 14, 3, 0, // Skip to: 2213 >+/* 2210 */ MCD_OPC_Decode, 69, 27, // Opcode: BX_RET >+/* 2213 */ MCD_OPC_CheckPredicate, 6, 9, 0, // Skip to: 2226 >+/* 2217 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 2226 >+/* 2223 */ MCD_OPC_Decode, 66, 31, // Opcode: BX >+/* 2226 */ MCD_OPC_CheckPredicate, 6, 12, 21, // Skip to: 7618 >+/* 2230 */ MCD_OPC_Decode, 70, 25, // Opcode: BX_pred >+/* 2233 */ MCD_OPC_FilterValue, 1, 28, 0, // Skip to: 2265 >+/* 2237 */ MCD_OPC_ExtractField, 8, 12, // Inst{19-8} ... >+/* 2240 */ MCD_OPC_FilterValue, 255, 31, 253, 20, // Skip to: 7618 >+/* 2245 */ MCD_OPC_CheckPredicate, 7, 9, 0, // Skip to: 2258 >+/* 2249 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 2258 >+/* 2255 */ MCD_OPC_Decode, 57, 31, // Opcode: BLX >+/* 2258 */ MCD_OPC_CheckPredicate, 7, 236, 20, // Skip to: 7618 >+/* 2262 */ MCD_OPC_Decode, 58, 25, // Opcode: BLX_pred >+/* 2265 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 2281 >+/* 2269 */ MCD_OPC_CheckPredicate, 0, 225, 20, // Skip to: 7618 >+/* 2273 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2277 */ MCD_OPC_Decode, 145, 2, 20, // Opcode: QSUB >+/* 2281 */ MCD_OPC_FilterValue, 3, 213, 20, // Skip to: 7618 >+/* 2285 */ MCD_OPC_CheckPredicate, 0, 209, 20, // Skip to: 7618 >+/* 2289 */ MCD_OPC_CheckField, 28, 4, 14, 203, 20, // Skip to: 7618 >+/* 2295 */ MCD_OPC_Decode, 55, 15, // Opcode: BKPT >+/* 2298 */ MCD_OPC_FilterValue, 1, 196, 20, // Skip to: 7618 >+/* 2302 */ MCD_OPC_CheckPredicate, 0, 192, 20, // Skip to: 7618 >+/* 2306 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2311 */ MCD_OPC_Decode, 217, 3, 18, // Opcode: TEQrsr >+/* 2315 */ MCD_OPC_FilterValue, 5, 83, 0, // Skip to: 2402 >+/* 2319 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2322 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 2386 >+/* 2326 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2329 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 2352 >+/* 2333 */ MCD_OPC_CheckPredicate, 7, 161, 20, // Skip to: 7618 >+/* 2337 */ MCD_OPC_CheckField, 16, 4, 15, 155, 20, // Skip to: 7618 >+/* 2343 */ MCD_OPC_CheckField, 8, 4, 15, 149, 20, // Skip to: 7618 >+/* 2349 */ MCD_OPC_Decode, 75, 32, // Opcode: CLZ >+/* 2352 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 2368 >+/* 2356 */ MCD_OPC_CheckPredicate, 0, 138, 20, // Skip to: 7618 >+/* 2360 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2364 */ MCD_OPC_Decode, 143, 2, 20, // Opcode: QDSUB >+/* 2368 */ MCD_OPC_FilterValue, 3, 126, 20, // Skip to: 7618 >+/* 2372 */ MCD_OPC_CheckPredicate, 8, 122, 20, // Skip to: 7618 >+/* 2376 */ MCD_OPC_CheckField, 8, 12, 0, 116, 20, // Skip to: 7618 >+/* 2382 */ MCD_OPC_Decode, 202, 2, 33, // Opcode: SMC >+/* 2386 */ MCD_OPC_FilterValue, 1, 108, 20, // Skip to: 7618 >+/* 2390 */ MCD_OPC_CheckPredicate, 0, 104, 20, // Skip to: 7618 >+/* 2394 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 2399 */ MCD_OPC_Decode, 79, 18, // Opcode: CMNzrsr >+/* 2402 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2420 >+/* 2406 */ MCD_OPC_CheckPredicate, 0, 88, 20, // Skip to: 7618 >+/* 2410 */ MCD_OPC_CheckField, 16, 4, 0, 82, 20, // Skip to: 7618 >+/* 2416 */ MCD_OPC_Decode, 227, 1, 34, // Opcode: MOVsr >+/* 2420 */ MCD_OPC_FilterValue, 7, 74, 20, // Skip to: 7618 >+/* 2424 */ MCD_OPC_CheckPredicate, 0, 70, 20, // Skip to: 7618 >+/* 2428 */ MCD_OPC_CheckField, 16, 4, 0, 64, 20, // Skip to: 7618 >+/* 2434 */ MCD_OPC_Decode, 244, 1, 35, // Opcode: MVNsr >+/* 2438 */ MCD_OPC_FilterValue, 1, 56, 20, // Skip to: 7618 >+/* 2442 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 2445 */ MCD_OPC_FilterValue, 0, 3, 1, // Skip to: 2708 >+/* 2449 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ... >+/* 2452 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2464 >+/* 2456 */ MCD_OPC_CheckPredicate, 1, 38, 20, // Skip to: 7618 >+/* 2460 */ MCD_OPC_Decode, 205, 1, 36, // Opcode: MLA >+/* 2464 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2482 >+/* 2468 */ MCD_OPC_CheckPredicate, 9, 26, 20, // Skip to: 7618 >+/* 2472 */ MCD_OPC_CheckField, 20, 1, 0, 20, 20, // Skip to: 7618 >+/* 2478 */ MCD_OPC_Decode, 207, 1, 37, // Opcode: MLS >+/* 2482 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2494 >+/* 2486 */ MCD_OPC_CheckPredicate, 1, 8, 20, // Skip to: 7618 >+/* 2490 */ MCD_OPC_Decode, 238, 3, 38, // Opcode: UMLAL >+/* 2494 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2506 >+/* 2498 */ MCD_OPC_CheckPredicate, 1, 252, 19, // Skip to: 7618 >+/* 2502 */ MCD_OPC_Decode, 207, 2, 38, // Opcode: SMLAL >+/* 2506 */ MCD_OPC_FilterValue, 6, 76, 0, // Skip to: 2586 >+/* 2510 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2513 */ MCD_OPC_FilterValue, 14, 32, 0, // Skip to: 2549 >+/* 2517 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2520 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2532 >+/* 2524 */ MCD_OPC_CheckPredicate, 5, 226, 19, // Skip to: 7618 >+/* 2528 */ MCD_OPC_Decode, 146, 3, 39, // Opcode: STLEXD >+/* 2532 */ MCD_OPC_FilterValue, 1, 218, 19, // Skip to: 7618 >+/* 2536 */ MCD_OPC_CheckPredicate, 5, 214, 19, // Skip to: 7618 >+/* 2540 */ MCD_OPC_CheckField, 0, 4, 15, 208, 19, // Skip to: 7618 >+/* 2546 */ MCD_OPC_Decode, 123, 40, // Opcode: LDAEXD >+/* 2549 */ MCD_OPC_FilterValue, 15, 201, 19, // Skip to: 7618 >+/* 2553 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2556 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2568 >+/* 2560 */ MCD_OPC_CheckPredicate, 0, 190, 19, // Skip to: 7618 >+/* 2564 */ MCD_OPC_Decode, 173, 3, 39, // Opcode: STREXD >+/* 2568 */ MCD_OPC_FilterValue, 1, 182, 19, // Skip to: 7618 >+/* 2572 */ MCD_OPC_CheckPredicate, 0, 178, 19, // Skip to: 7618 >+/* 2576 */ MCD_OPC_CheckField, 0, 4, 15, 172, 19, // Skip to: 7618 >+/* 2582 */ MCD_OPC_Decode, 165, 1, 40, // Opcode: LDREXD >+/* 2586 */ MCD_OPC_FilterValue, 7, 164, 19, // Skip to: 7618 >+/* 2590 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2593 */ MCD_OPC_FilterValue, 12, 38, 0, // Skip to: 2635 >+/* 2597 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2600 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2618 >+/* 2604 */ MCD_OPC_CheckPredicate, 5, 146, 19, // Skip to: 7618 >+/* 2608 */ MCD_OPC_CheckField, 12, 4, 15, 140, 19, // Skip to: 7618 >+/* 2614 */ MCD_OPC_Decode, 148, 3, 21, // Opcode: STLH >+/* 2618 */ MCD_OPC_FilterValue, 1, 132, 19, // Skip to: 7618 >+/* 2622 */ MCD_OPC_CheckPredicate, 5, 128, 19, // Skip to: 7618 >+/* 2626 */ MCD_OPC_CheckField, 0, 4, 15, 122, 19, // Skip to: 7618 >+/* 2632 */ MCD_OPC_Decode, 125, 22, // Opcode: LDAH >+/* 2635 */ MCD_OPC_FilterValue, 14, 32, 0, // Skip to: 2671 >+/* 2639 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2642 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2654 >+/* 2646 */ MCD_OPC_CheckPredicate, 5, 104, 19, // Skip to: 7618 >+/* 2650 */ MCD_OPC_Decode, 147, 3, 23, // Opcode: STLEXH >+/* 2654 */ MCD_OPC_FilterValue, 1, 96, 19, // Skip to: 7618 >+/* 2658 */ MCD_OPC_CheckPredicate, 5, 92, 19, // Skip to: 7618 >+/* 2662 */ MCD_OPC_CheckField, 0, 4, 15, 86, 19, // Skip to: 7618 >+/* 2668 */ MCD_OPC_Decode, 124, 22, // Opcode: LDAEXH >+/* 2671 */ MCD_OPC_FilterValue, 15, 79, 19, // Skip to: 7618 >+/* 2675 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2678 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2690 >+/* 2682 */ MCD_OPC_CheckPredicate, 0, 68, 19, // Skip to: 7618 >+/* 2686 */ MCD_OPC_Decode, 174, 3, 23, // Opcode: STREXH >+/* 2690 */ MCD_OPC_FilterValue, 1, 60, 19, // Skip to: 7618 >+/* 2694 */ MCD_OPC_CheckPredicate, 0, 56, 19, // Skip to: 7618 >+/* 2698 */ MCD_OPC_CheckField, 0, 4, 15, 50, 19, // Skip to: 7618 >+/* 2704 */ MCD_OPC_Decode, 166, 1, 22, // Opcode: LDREXH >+/* 2708 */ MCD_OPC_FilterValue, 1, 113, 0, // Skip to: 2825 >+/* 2712 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2715 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 2771 >+/* 2719 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2722 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 2759 >+/* 2726 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2729 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2747 >+/* 2733 */ MCD_OPC_CheckPredicate, 0, 17, 19, // Skip to: 7618 >+/* 2737 */ MCD_OPC_CheckField, 8, 4, 0, 11, 19, // Skip to: 7618 >+/* 2743 */ MCD_OPC_Decode, 177, 3, 41, // Opcode: STRHTr >+/* 2747 */ MCD_OPC_FilterValue, 1, 3, 19, // Skip to: 7618 >+/* 2751 */ MCD_OPC_CheckPredicate, 0, 255, 18, // Skip to: 7618 >+/* 2755 */ MCD_OPC_Decode, 176, 3, 42, // Opcode: STRHTi >+/* 2759 */ MCD_OPC_FilterValue, 1, 247, 18, // Skip to: 7618 >+/* 2763 */ MCD_OPC_CheckPredicate, 0, 243, 18, // Skip to: 7618 >+/* 2767 */ MCD_OPC_Decode, 179, 3, 7, // Opcode: STRH_PRE >+/* 2771 */ MCD_OPC_FilterValue, 1, 235, 18, // Skip to: 7618 >+/* 2775 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2778 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 2813 >+/* 2782 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2785 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 2801 >+/* 2789 */ MCD_OPC_CheckPredicate, 0, 217, 18, // Skip to: 7618 >+/* 2793 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2797 */ MCD_OPC_Decode, 169, 1, 43, // Opcode: LDRHTr >+/* 2801 */ MCD_OPC_FilterValue, 1, 205, 18, // Skip to: 7618 >+/* 2805 */ MCD_OPC_CheckPredicate, 0, 201, 18, // Skip to: 7618 >+/* 2809 */ MCD_OPC_Decode, 168, 1, 44, // Opcode: LDRHTi >+/* 2813 */ MCD_OPC_FilterValue, 1, 193, 18, // Skip to: 7618 >+/* 2817 */ MCD_OPC_CheckPredicate, 0, 189, 18, // Skip to: 7618 >+/* 2821 */ MCD_OPC_Decode, 171, 1, 7, // Opcode: LDRH_PRE >+/* 2825 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 2904 >+/* 2829 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2832 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2850 >+/* 2836 */ MCD_OPC_CheckPredicate, 0, 170, 18, // Skip to: 7618 >+/* 2840 */ MCD_OPC_CheckField, 24, 1, 1, 164, 18, // Skip to: 7618 >+/* 2846 */ MCD_OPC_Decode, 162, 1, 7, // Opcode: LDRD_PRE >+/* 2850 */ MCD_OPC_FilterValue, 1, 156, 18, // Skip to: 7618 >+/* 2854 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2857 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 2892 >+/* 2861 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2864 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 2880 >+/* 2868 */ MCD_OPC_CheckPredicate, 0, 138, 18, // Skip to: 7618 >+/* 2872 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2876 */ MCD_OPC_Decode, 177, 1, 43, // Opcode: LDRSBTr >+/* 2880 */ MCD_OPC_FilterValue, 1, 126, 18, // Skip to: 7618 >+/* 2884 */ MCD_OPC_CheckPredicate, 0, 122, 18, // Skip to: 7618 >+/* 2888 */ MCD_OPC_Decode, 176, 1, 44, // Opcode: LDRSBTi >+/* 2892 */ MCD_OPC_FilterValue, 1, 114, 18, // Skip to: 7618 >+/* 2896 */ MCD_OPC_CheckPredicate, 0, 110, 18, // Skip to: 7618 >+/* 2900 */ MCD_OPC_Decode, 179, 1, 7, // Opcode: LDRSB_PRE >+/* 2904 */ MCD_OPC_FilterValue, 3, 102, 18, // Skip to: 7618 >+/* 2908 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2911 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2929 >+/* 2915 */ MCD_OPC_CheckPredicate, 0, 91, 18, // Skip to: 7618 >+/* 2919 */ MCD_OPC_CheckField, 24, 1, 1, 85, 18, // Skip to: 7618 >+/* 2925 */ MCD_OPC_Decode, 170, 3, 7, // Opcode: STRD_PRE >+/* 2929 */ MCD_OPC_FilterValue, 1, 77, 18, // Skip to: 7618 >+/* 2933 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2936 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 2971 >+/* 2940 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2943 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 2959 >+/* 2947 */ MCD_OPC_CheckPredicate, 0, 59, 18, // Skip to: 7618 >+/* 2951 */ MCD_OPC_SoftFail, 128, 30 /* 0xF00 */, 0, >+/* 2955 */ MCD_OPC_Decode, 182, 1, 43, // Opcode: LDRSHTr >+/* 2959 */ MCD_OPC_FilterValue, 1, 47, 18, // Skip to: 7618 >+/* 2963 */ MCD_OPC_CheckPredicate, 0, 43, 18, // Skip to: 7618 >+/* 2967 */ MCD_OPC_Decode, 181, 1, 44, // Opcode: LDRSHTi >+/* 2971 */ MCD_OPC_FilterValue, 1, 35, 18, // Skip to: 7618 >+/* 2975 */ MCD_OPC_CheckPredicate, 0, 31, 18, // Skip to: 7618 >+/* 2979 */ MCD_OPC_Decode, 184, 1, 7, // Opcode: LDRSH_PRE >+/* 2983 */ MCD_OPC_FilterValue, 1, 147, 1, // Skip to: 3390 >+/* 2987 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 2990 */ MCD_OPC_FilterValue, 0, 170, 0, // Skip to: 3164 >+/* 2994 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 2997 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 3063 >+/* 3001 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 3004 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3015 >+/* 3008 */ MCD_OPC_CheckPredicate, 0, 38, 0, // Skip to: 3050 >+/* 3012 */ MCD_OPC_Decode, 40, 45, // Opcode: ANDri >+/* 3015 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3027 >+/* 3019 */ MCD_OPC_CheckPredicate, 0, 27, 0, // Skip to: 3050 >+/* 3023 */ MCD_OPC_Decode, 197, 3, 45, // Opcode: SUBri >+/* 3027 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3038 >+/* 3031 */ MCD_OPC_CheckPredicate, 0, 15, 0, // Skip to: 3050 >+/* 3035 */ MCD_OPC_Decode, 29, 45, // Opcode: ADDri >+/* 3038 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3050 >+/* 3042 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 3050 >+/* 3046 */ MCD_OPC_Decode, 178, 2, 45, // Opcode: SBCri >+/* 3050 */ MCD_OPC_CheckPredicate, 0, 212, 17, // Skip to: 7618 >+/* 3054 */ MCD_OPC_CheckField, 16, 5, 15, 206, 17, // Skip to: 7618 >+/* 3060 */ MCD_OPC_Decode, 35, 46, // Opcode: ADR >+/* 3063 */ MCD_OPC_FilterValue, 1, 199, 17, // Skip to: 7618 >+/* 3067 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 3070 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 3106 >+/* 3074 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3077 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3089 >+/* 3081 */ MCD_OPC_CheckPredicate, 9, 181, 17, // Skip to: 7618 >+/* 3085 */ MCD_OPC_Decode, 221, 1, 47, // Opcode: MOVi16 >+/* 3089 */ MCD_OPC_FilterValue, 1, 173, 17, // Skip to: 7618 >+/* 3093 */ MCD_OPC_CheckPredicate, 0, 169, 17, // Skip to: 7618 >+/* 3097 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3102 */ MCD_OPC_Decode, 221, 3, 48, // Opcode: TSTri >+/* 3106 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 3141 >+/* 3110 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3113 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3125 >+/* 3117 */ MCD_OPC_CheckPredicate, 9, 145, 17, // Skip to: 7618 >+/* 3121 */ MCD_OPC_Decode, 216, 1, 47, // Opcode: MOVTi16 >+/* 3125 */ MCD_OPC_FilterValue, 1, 137, 17, // Skip to: 7618 >+/* 3129 */ MCD_OPC_CheckPredicate, 0, 133, 17, // Skip to: 7618 >+/* 3133 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3138 */ MCD_OPC_Decode, 80, 48, // Opcode: CMPri >+/* 3141 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3153 >+/* 3145 */ MCD_OPC_CheckPredicate, 0, 117, 17, // Skip to: 7618 >+/* 3149 */ MCD_OPC_Decode, 245, 1, 45, // Opcode: ORRri >+/* 3153 */ MCD_OPC_FilterValue, 3, 109, 17, // Skip to: 7618 >+/* 3157 */ MCD_OPC_CheckPredicate, 0, 105, 17, // Skip to: 7618 >+/* 3161 */ MCD_OPC_Decode, 51, 45, // Opcode: BICri >+/* 3164 */ MCD_OPC_FilterValue, 1, 98, 17, // Skip to: 7618 >+/* 3168 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 3171 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 3201 >+/* 3175 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3178 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3189 >+/* 3182 */ MCD_OPC_CheckPredicate, 0, 80, 17, // Skip to: 7618 >+/* 3186 */ MCD_OPC_Decode, 98, 45, // Opcode: EORri >+/* 3189 */ MCD_OPC_FilterValue, 1, 73, 17, // Skip to: 7618 >+/* 3193 */ MCD_OPC_CheckPredicate, 0, 69, 17, // Skip to: 7618 >+/* 3197 */ MCD_OPC_Decode, 167, 2, 45, // Opcode: RSBri >+/* 3201 */ MCD_OPC_FilterValue, 1, 26, 0, // Skip to: 3231 >+/* 3205 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3208 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3219 >+/* 3212 */ MCD_OPC_CheckPredicate, 0, 50, 17, // Skip to: 7618 >+/* 3216 */ MCD_OPC_Decode, 21, 45, // Opcode: ADCri >+/* 3219 */ MCD_OPC_FilterValue, 1, 43, 17, // Skip to: 7618 >+/* 3223 */ MCD_OPC_CheckPredicate, 0, 39, 17, // Skip to: 7618 >+/* 3227 */ MCD_OPC_Decode, 171, 2, 45, // Opcode: RSCri >+/* 3231 */ MCD_OPC_FilterValue, 2, 112, 0, // Skip to: 3347 >+/* 3235 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3238 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 3307 >+/* 3242 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 3245 */ MCD_OPC_FilterValue, 15, 17, 17, // Skip to: 7618 >+/* 3249 */ MCD_OPC_CheckPredicate, 10, 21, 0, // Skip to: 3274 >+/* 3253 */ MCD_OPC_CheckField, 22, 1, 0, 15, 0, // Skip to: 3274 >+/* 3259 */ MCD_OPC_CheckField, 16, 4, 0, 9, 0, // Skip to: 3274 >+/* 3265 */ MCD_OPC_CheckField, 4, 8, 15, 3, 0, // Skip to: 3274 >+/* 3271 */ MCD_OPC_Decode, 95, 33, // Opcode: DBG >+/* 3274 */ MCD_OPC_CheckPredicate, 1, 21, 0, // Skip to: 3299 >+/* 3278 */ MCD_OPC_CheckField, 22, 1, 0, 15, 0, // Skip to: 3299 >+/* 3284 */ MCD_OPC_CheckField, 16, 4, 0, 9, 0, // Skip to: 3299 >+/* 3290 */ MCD_OPC_CheckField, 8, 4, 0, 3, 0, // Skip to: 3299 >+/* 3296 */ MCD_OPC_Decode, 111, 49, // Opcode: HINT >+/* 3299 */ MCD_OPC_CheckPredicate, 0, 219, 16, // Skip to: 7618 >+/* 3303 */ MCD_OPC_Decode, 237, 1, 50, // Opcode: MSRi >+/* 3307 */ MCD_OPC_FilterValue, 1, 211, 16, // Skip to: 7618 >+/* 3311 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3314 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 3331 >+/* 3318 */ MCD_OPC_CheckPredicate, 0, 200, 16, // Skip to: 7618 >+/* 3322 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3327 */ MCD_OPC_Decode, 214, 3, 48, // Opcode: TEQri >+/* 3331 */ MCD_OPC_FilterValue, 1, 187, 16, // Skip to: 7618 >+/* 3335 */ MCD_OPC_CheckPredicate, 0, 183, 16, // Skip to: 7618 >+/* 3339 */ MCD_OPC_SoftFail, 128, 224, 3 /* 0xF000 */, 0, >+/* 3344 */ MCD_OPC_Decode, 76, 48, // Opcode: CMNri >+/* 3347 */ MCD_OPC_FilterValue, 3, 171, 16, // Skip to: 7618 >+/* 3351 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 3354 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3372 >+/* 3358 */ MCD_OPC_CheckPredicate, 0, 160, 16, // Skip to: 7618 >+/* 3362 */ MCD_OPC_CheckField, 16, 4, 0, 154, 16, // Skip to: 7618 >+/* 3368 */ MCD_OPC_Decode, 220, 1, 51, // Opcode: MOVi >+/* 3372 */ MCD_OPC_FilterValue, 1, 146, 16, // Skip to: 7618 >+/* 3376 */ MCD_OPC_CheckPredicate, 0, 142, 16, // Skip to: 7618 >+/* 3380 */ MCD_OPC_CheckField, 16, 4, 0, 136, 16, // Skip to: 7618 >+/* 3386 */ MCD_OPC_Decode, 241, 1, 51, // Opcode: MVNi >+/* 3390 */ MCD_OPC_FilterValue, 2, 160, 1, // Skip to: 3810 >+/* 3394 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 3397 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 3428 >+/* 3401 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3404 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3416 >+/* 3408 */ MCD_OPC_CheckPredicate, 0, 110, 16, // Skip to: 7618 >+/* 3412 */ MCD_OPC_Decode, 184, 3, 52, // Opcode: STR_POST_IMM >+/* 3416 */ MCD_OPC_FilterValue, 1, 102, 16, // Skip to: 7618 >+/* 3420 */ MCD_OPC_CheckPredicate, 0, 98, 16, // Skip to: 7618 >+/* 3424 */ MCD_OPC_Decode, 188, 3, 53, // Opcode: STRi12 >+/* 3428 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 3479 >+/* 3432 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3435 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3447 >+/* 3439 */ MCD_OPC_CheckPredicate, 0, 79, 16, // Skip to: 7618 >+/* 3443 */ MCD_OPC_Decode, 188, 1, 52, // Opcode: LDR_POST_IMM >+/* 3447 */ MCD_OPC_FilterValue, 1, 71, 16, // Skip to: 7618 >+/* 3451 */ MCD_OPC_CheckPredicate, 11, 16, 0, // Skip to: 3471 >+/* 3455 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3471 >+/* 3461 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3471 >+/* 3467 */ MCD_OPC_Decode, 132, 2, 54, // Opcode: PLDWi12 >+/* 3471 */ MCD_OPC_CheckPredicate, 0, 47, 16, // Skip to: 7618 >+/* 3475 */ MCD_OPC_Decode, 193, 1, 53, // Opcode: LDRi12 >+/* 3479 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 3510 >+/* 3483 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3486 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3498 >+/* 3490 */ MCD_OPC_CheckPredicate, 0, 28, 16, // Skip to: 7618 >+/* 3494 */ MCD_OPC_Decode, 182, 3, 52, // Opcode: STRT_POST_IMM >+/* 3498 */ MCD_OPC_FilterValue, 1, 20, 16, // Skip to: 7618 >+/* 3502 */ MCD_OPC_CheckPredicate, 0, 16, 16, // Skip to: 7618 >+/* 3506 */ MCD_OPC_Decode, 186, 3, 55, // Opcode: STR_PRE_IMM >+/* 3510 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 3541 >+/* 3514 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3517 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3529 >+/* 3521 */ MCD_OPC_CheckPredicate, 0, 253, 15, // Skip to: 7618 >+/* 3525 */ MCD_OPC_Decode, 186, 1, 52, // Opcode: LDRT_POST_IMM >+/* 3529 */ MCD_OPC_FilterValue, 1, 245, 15, // Skip to: 7618 >+/* 3533 */ MCD_OPC_CheckPredicate, 0, 241, 15, // Skip to: 7618 >+/* 3537 */ MCD_OPC_Decode, 190, 1, 56, // Opcode: LDR_PRE_IMM >+/* 3541 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 3572 >+/* 3545 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3548 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3560 >+/* 3552 */ MCD_OPC_CheckPredicate, 0, 222, 15, // Skip to: 7618 >+/* 3556 */ MCD_OPC_Decode, 160, 3, 52, // Opcode: STRB_POST_IMM >+/* 3560 */ MCD_OPC_FilterValue, 1, 214, 15, // Skip to: 7618 >+/* 3564 */ MCD_OPC_CheckPredicate, 0, 210, 15, // Skip to: 7618 >+/* 3568 */ MCD_OPC_Decode, 164, 3, 57, // Opcode: STRBi12 >+/* 3572 */ MCD_OPC_FilterValue, 5, 67, 0, // Skip to: 3643 >+/* 3576 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3579 */ MCD_OPC_FilterValue, 0, 28, 0, // Skip to: 3611 >+/* 3583 */ MCD_OPC_CheckPredicate, 10, 16, 0, // Skip to: 3603 >+/* 3587 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3603 >+/* 3593 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3603 >+/* 3599 */ MCD_OPC_Decode, 136, 2, 54, // Opcode: PLIi12 >+/* 3603 */ MCD_OPC_CheckPredicate, 0, 171, 15, // Skip to: 7618 >+/* 3607 */ MCD_OPC_Decode, 154, 1, 52, // Opcode: LDRB_POST_IMM >+/* 3611 */ MCD_OPC_FilterValue, 1, 163, 15, // Skip to: 7618 >+/* 3615 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 3635 >+/* 3619 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3635 >+/* 3625 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3635 >+/* 3631 */ MCD_OPC_Decode, 134, 2, 54, // Opcode: PLDi12 >+/* 3635 */ MCD_OPC_CheckPredicate, 0, 139, 15, // Skip to: 7618 >+/* 3639 */ MCD_OPC_Decode, 158, 1, 57, // Opcode: LDRBi12 >+/* 3643 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 3674 >+/* 3647 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3650 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3662 >+/* 3654 */ MCD_OPC_CheckPredicate, 0, 120, 15, // Skip to: 7618 >+/* 3658 */ MCD_OPC_Decode, 158, 3, 52, // Opcode: STRBT_POST_IMM >+/* 3662 */ MCD_OPC_FilterValue, 1, 112, 15, // Skip to: 7618 >+/* 3666 */ MCD_OPC_CheckPredicate, 0, 108, 15, // Skip to: 7618 >+/* 3670 */ MCD_OPC_Decode, 162, 3, 55, // Opcode: STRB_PRE_IMM >+/* 3674 */ MCD_OPC_FilterValue, 7, 100, 15, // Skip to: 7618 >+/* 3678 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3681 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3693 >+/* 3685 */ MCD_OPC_CheckPredicate, 0, 89, 15, // Skip to: 7618 >+/* 3689 */ MCD_OPC_Decode, 152, 1, 52, // Opcode: LDRBT_POST_IMM >+/* 3693 */ MCD_OPC_FilterValue, 1, 81, 15, // Skip to: 7618 >+/* 3697 */ MCD_OPC_CheckPredicate, 10, 23, 0, // Skip to: 3724 >+/* 3701 */ MCD_OPC_CheckField, 28, 4, 15, 17, 0, // Skip to: 3724 >+/* 3707 */ MCD_OPC_CheckField, 23, 1, 0, 11, 0, // Skip to: 3724 >+/* 3713 */ MCD_OPC_CheckField, 0, 20, 159, 224, 63, 3, 0, // Skip to: 3724 >+/* 3721 */ MCD_OPC_Decode, 74, 58, // Opcode: CLREX >+/* 3724 */ MCD_OPC_ExtractField, 4, 16, // Inst{19-4} ... >+/* 3727 */ MCD_OPC_FilterValue, 132, 254, 3, 19, 0, // Skip to: 3752 >+/* 3733 */ MCD_OPC_CheckPredicate, 12, 65, 0, // Skip to: 3802 >+/* 3737 */ MCD_OPC_CheckField, 28, 4, 15, 59, 0, // Skip to: 3802 >+/* 3743 */ MCD_OPC_CheckField, 23, 1, 0, 53, 0, // Skip to: 3802 >+/* 3749 */ MCD_OPC_Decode, 97, 59, // Opcode: DSB >+/* 3752 */ MCD_OPC_FilterValue, 133, 254, 3, 19, 0, // Skip to: 3777 >+/* 3758 */ MCD_OPC_CheckPredicate, 12, 40, 0, // Skip to: 3802 >+/* 3762 */ MCD_OPC_CheckField, 28, 4, 15, 34, 0, // Skip to: 3802 >+/* 3768 */ MCD_OPC_CheckField, 23, 1, 0, 28, 0, // Skip to: 3802 >+/* 3774 */ MCD_OPC_Decode, 96, 59, // Opcode: DMB >+/* 3777 */ MCD_OPC_FilterValue, 134, 254, 3, 19, 0, // Skip to: 3802 >+/* 3783 */ MCD_OPC_CheckPredicate, 12, 15, 0, // Skip to: 3802 >+/* 3787 */ MCD_OPC_CheckField, 28, 4, 15, 9, 0, // Skip to: 3802 >+/* 3793 */ MCD_OPC_CheckField, 23, 1, 0, 3, 0, // Skip to: 3802 >+/* 3799 */ MCD_OPC_Decode, 113, 60, // Opcode: ISB >+/* 3802 */ MCD_OPC_CheckPredicate, 0, 228, 14, // Skip to: 7618 >+/* 3806 */ MCD_OPC_Decode, 156, 1, 56, // Opcode: LDRB_PRE_IMM >+/* 3810 */ MCD_OPC_FilterValue, 3, 44, 9, // Skip to: 6162 >+/* 3814 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... >+/* 3817 */ MCD_OPC_FilterValue, 0, 109, 2, // Skip to: 4442 >+/* 3821 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 3824 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 3913 >+/* 3828 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 3831 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 3862 >+/* 3835 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3838 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3850 >+/* 3842 */ MCD_OPC_CheckPredicate, 0, 188, 14, // Skip to: 7618 >+/* 3846 */ MCD_OPC_Decode, 185, 3, 52, // Opcode: STR_POST_REG >+/* 3850 */ MCD_OPC_FilterValue, 1, 180, 14, // Skip to: 7618 >+/* 3854 */ MCD_OPC_CheckPredicate, 0, 176, 14, // Skip to: 7618 >+/* 3858 */ MCD_OPC_Decode, 191, 3, 61, // Opcode: STRrs >+/* 3862 */ MCD_OPC_FilterValue, 1, 168, 14, // Skip to: 7618 >+/* 3866 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 3869 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3881 >+/* 3873 */ MCD_OPC_CheckPredicate, 0, 157, 14, // Skip to: 7618 >+/* 3877 */ MCD_OPC_Decode, 189, 1, 52, // Opcode: LDR_POST_REG >+/* 3881 */ MCD_OPC_FilterValue, 1, 149, 14, // Skip to: 7618 >+/* 3885 */ MCD_OPC_CheckPredicate, 11, 16, 0, // Skip to: 3905 >+/* 3889 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 3905 >+/* 3895 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 3905 >+/* 3901 */ MCD_OPC_Decode, 133, 2, 62, // Opcode: PLDWrs >+/* 3905 */ MCD_OPC_CheckPredicate, 0, 125, 14, // Skip to: 7618 >+/* 3909 */ MCD_OPC_Decode, 194, 1, 61, // Opcode: LDRrs >+/* 3913 */ MCD_OPC_FilterValue, 1, 117, 14, // Skip to: 7618 >+/* 3917 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 3920 */ MCD_OPC_FilterValue, 0, 176, 0, // Skip to: 4100 >+/* 3924 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 3927 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 3978 >+/* 3931 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3934 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 3956 >+/* 3938 */ MCD_OPC_CheckPredicate, 0, 92, 14, // Skip to: 7618 >+/* 3942 */ MCD_OPC_CheckField, 20, 1, 1, 86, 14, // Skip to: 7618 >+/* 3948 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 3952 */ MCD_OPC_Decode, 175, 2, 63, // Opcode: SADD16 >+/* 3956 */ MCD_OPC_FilterValue, 1, 74, 14, // Skip to: 7618 >+/* 3960 */ MCD_OPC_CheckPredicate, 0, 70, 14, // Skip to: 7618 >+/* 3964 */ MCD_OPC_CheckField, 20, 1, 1, 64, 14, // Skip to: 7618 >+/* 3970 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 3974 */ MCD_OPC_Decode, 176, 2, 63, // Opcode: SADD8 >+/* 3978 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3996 >+/* 3982 */ MCD_OPC_CheckPredicate, 1, 48, 14, // Skip to: 7618 >+/* 3986 */ MCD_OPC_CheckField, 20, 1, 0, 42, 14, // Skip to: 7618 >+/* 3992 */ MCD_OPC_Decode, 130, 2, 64, // Opcode: PKHBT >+/* 3996 */ MCD_OPC_FilterValue, 2, 60, 0, // Skip to: 4060 >+/* 4000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4003 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4036 >+/* 4007 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4010 */ MCD_OPC_FilterValue, 0, 20, 14, // Skip to: 7618 >+/* 4014 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4028 >+/* 4018 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4028 >+/* 4024 */ MCD_OPC_Decode, 229, 2, 65, // Opcode: SMUAD >+/* 4028 */ MCD_OPC_CheckPredicate, 1, 2, 14, // Skip to: 7618 >+/* 4032 */ MCD_OPC_Decode, 205, 2, 66, // Opcode: SMLAD >+/* 4036 */ MCD_OPC_FilterValue, 1, 250, 13, // Skip to: 7618 >+/* 4040 */ MCD_OPC_CheckPredicate, 13, 246, 13, // Skip to: 7618 >+/* 4044 */ MCD_OPC_CheckField, 12, 4, 15, 240, 13, // Skip to: 7618 >+/* 4050 */ MCD_OPC_CheckField, 7, 1, 0, 234, 13, // Skip to: 7618 >+/* 4056 */ MCD_OPC_Decode, 183, 2, 26, // Opcode: SDIV >+/* 4060 */ MCD_OPC_FilterValue, 3, 226, 13, // Skip to: 7618 >+/* 4064 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4067 */ MCD_OPC_FilterValue, 0, 219, 13, // Skip to: 7618 >+/* 4071 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4074 */ MCD_OPC_FilterValue, 0, 212, 13, // Skip to: 7618 >+/* 4078 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4092 >+/* 4082 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4092 >+/* 4088 */ MCD_OPC_Decode, 248, 3, 26, // Opcode: USAD8 >+/* 4092 */ MCD_OPC_CheckPredicate, 1, 194, 13, // Skip to: 7618 >+/* 4096 */ MCD_OPC_Decode, 249, 3, 37, // Opcode: USADA8 >+/* 4100 */ MCD_OPC_FilterValue, 1, 99, 0, // Skip to: 4203 >+/* 4104 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4107 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4135 >+/* 4111 */ MCD_OPC_CheckPredicate, 0, 175, 13, // Skip to: 7618 >+/* 4115 */ MCD_OPC_CheckField, 20, 1, 1, 169, 13, // Skip to: 7618 >+/* 4121 */ MCD_OPC_CheckField, 7, 1, 0, 163, 13, // Skip to: 7618 >+/* 4127 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4131 */ MCD_OPC_Decode, 177, 2, 63, // Opcode: SASX >+/* 4135 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4163 >+/* 4139 */ MCD_OPC_CheckPredicate, 1, 147, 13, // Skip to: 7618 >+/* 4143 */ MCD_OPC_CheckField, 20, 1, 0, 141, 13, // Skip to: 7618 >+/* 4149 */ MCD_OPC_CheckField, 7, 1, 1, 135, 13, // Skip to: 7618 >+/* 4155 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4159 */ MCD_OPC_Decode, 184, 2, 67, // Opcode: SEL >+/* 4163 */ MCD_OPC_FilterValue, 2, 123, 13, // Skip to: 7618 >+/* 4167 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4170 */ MCD_OPC_FilterValue, 0, 116, 13, // Skip to: 7618 >+/* 4174 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4177 */ MCD_OPC_FilterValue, 0, 109, 13, // Skip to: 7618 >+/* 4181 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4195 >+/* 4185 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4195 >+/* 4191 */ MCD_OPC_Decode, 230, 2, 65, // Opcode: SMUADX >+/* 4195 */ MCD_OPC_CheckPredicate, 1, 91, 13, // Skip to: 7618 >+/* 4199 */ MCD_OPC_Decode, 206, 2, 66, // Opcode: SMLADX >+/* 4203 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 4296 >+/* 4207 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4210 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4238 >+/* 4214 */ MCD_OPC_CheckPredicate, 0, 72, 13, // Skip to: 7618 >+/* 4218 */ MCD_OPC_CheckField, 20, 1, 1, 66, 13, // Skip to: 7618 >+/* 4224 */ MCD_OPC_CheckField, 7, 1, 0, 60, 13, // Skip to: 7618 >+/* 4230 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4234 */ MCD_OPC_Decode, 251, 2, 63, // Opcode: SSAX >+/* 4238 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4256 >+/* 4242 */ MCD_OPC_CheckPredicate, 1, 44, 13, // Skip to: 7618 >+/* 4246 */ MCD_OPC_CheckField, 20, 1, 0, 38, 13, // Skip to: 7618 >+/* 4252 */ MCD_OPC_Decode, 131, 2, 64, // Opcode: PKHTB >+/* 4256 */ MCD_OPC_FilterValue, 2, 30, 13, // Skip to: 7618 >+/* 4260 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4263 */ MCD_OPC_FilterValue, 0, 23, 13, // Skip to: 7618 >+/* 4267 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4270 */ MCD_OPC_FilterValue, 0, 16, 13, // Skip to: 7618 >+/* 4274 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4288 >+/* 4278 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4288 >+/* 4284 */ MCD_OPC_Decode, 239, 2, 65, // Opcode: SMUSD >+/* 4288 */ MCD_OPC_CheckPredicate, 1, 254, 12, // Skip to: 7618 >+/* 4292 */ MCD_OPC_Decode, 219, 2, 66, // Opcode: SMLSD >+/* 4296 */ MCD_OPC_FilterValue, 3, 246, 12, // Skip to: 7618 >+/* 4300 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4303 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 4354 >+/* 4307 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4310 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 4332 >+/* 4314 */ MCD_OPC_CheckPredicate, 0, 228, 12, // Skip to: 7618 >+/* 4318 */ MCD_OPC_CheckField, 20, 1, 1, 222, 12, // Skip to: 7618 >+/* 4324 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4328 */ MCD_OPC_Decode, 252, 2, 63, // Opcode: SSUB16 >+/* 4332 */ MCD_OPC_FilterValue, 1, 210, 12, // Skip to: 7618 >+/* 4336 */ MCD_OPC_CheckPredicate, 0, 206, 12, // Skip to: 7618 >+/* 4340 */ MCD_OPC_CheckField, 20, 1, 1, 200, 12, // Skip to: 7618 >+/* 4346 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4350 */ MCD_OPC_Decode, 253, 2, 63, // Opcode: SSUB8 >+/* 4354 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 4402 >+/* 4358 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4361 */ MCD_OPC_FilterValue, 0, 181, 12, // Skip to: 7618 >+/* 4365 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4368 */ MCD_OPC_FilterValue, 0, 174, 12, // Skip to: 7618 >+/* 4372 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 4390 >+/* 4376 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 4390 >+/* 4382 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4386 */ MCD_OPC_Decode, 208, 3, 68, // Opcode: SXTB16 >+/* 4390 */ MCD_OPC_CheckPredicate, 1, 152, 12, // Skip to: 7618 >+/* 4394 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4398 */ MCD_OPC_Decode, 205, 3, 69, // Opcode: SXTAB16 >+/* 4402 */ MCD_OPC_FilterValue, 2, 140, 12, // Skip to: 7618 >+/* 4406 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4409 */ MCD_OPC_FilterValue, 0, 133, 12, // Skip to: 7618 >+/* 4413 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4416 */ MCD_OPC_FilterValue, 0, 126, 12, // Skip to: 7618 >+/* 4420 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 4434 >+/* 4424 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 4434 >+/* 4430 */ MCD_OPC_Decode, 240, 2, 65, // Opcode: SMUSDX >+/* 4434 */ MCD_OPC_CheckPredicate, 1, 108, 12, // Skip to: 7618 >+/* 4438 */ MCD_OPC_Decode, 220, 2, 66, // Opcode: SMLSDX >+/* 4442 */ MCD_OPC_FilterValue, 1, 30, 2, // Skip to: 4988 >+/* 4446 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 4449 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 4518 >+/* 4453 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4456 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 4487 >+/* 4460 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 4463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4475 >+/* 4467 */ MCD_OPC_CheckPredicate, 0, 75, 12, // Skip to: 7618 >+/* 4471 */ MCD_OPC_Decode, 183, 3, 52, // Opcode: STRT_POST_REG >+/* 4475 */ MCD_OPC_FilterValue, 1, 67, 12, // Skip to: 7618 >+/* 4479 */ MCD_OPC_CheckPredicate, 0, 63, 12, // Skip to: 7618 >+/* 4483 */ MCD_OPC_Decode, 187, 3, 70, // Opcode: STR_PRE_REG >+/* 4487 */ MCD_OPC_FilterValue, 1, 55, 12, // Skip to: 7618 >+/* 4491 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 4494 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4506 >+/* 4498 */ MCD_OPC_CheckPredicate, 0, 44, 12, // Skip to: 7618 >+/* 4502 */ MCD_OPC_Decode, 187, 1, 52, // Opcode: LDRT_POST_REG >+/* 4506 */ MCD_OPC_FilterValue, 1, 36, 12, // Skip to: 7618 >+/* 4510 */ MCD_OPC_CheckPredicate, 0, 32, 12, // Skip to: 7618 >+/* 4514 */ MCD_OPC_Decode, 191, 1, 71, // Opcode: LDR_PRE_REG >+/* 4518 */ MCD_OPC_FilterValue, 1, 24, 12, // Skip to: 7618 >+/* 4522 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 4525 */ MCD_OPC_FilterValue, 0, 237, 0, // Skip to: 4766 >+/* 4529 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4532 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 4571 >+/* 4536 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4539 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4555 >+/* 4543 */ MCD_OPC_CheckPredicate, 0, 255, 11, // Skip to: 7618 >+/* 4547 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4551 */ MCD_OPC_Decode, 139, 2, 63, // Opcode: QADD16 >+/* 4555 */ MCD_OPC_FilterValue, 1, 243, 11, // Skip to: 7618 >+/* 4559 */ MCD_OPC_CheckPredicate, 0, 239, 11, // Skip to: 7618 >+/* 4563 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4567 */ MCD_OPC_Decode, 196, 2, 63, // Opcode: SHADD16 >+/* 4571 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 4610 >+/* 4575 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4578 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4594 >+/* 4582 */ MCD_OPC_CheckPredicate, 0, 216, 11, // Skip to: 7618 >+/* 4586 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4590 */ MCD_OPC_Decode, 141, 2, 63, // Opcode: QASX >+/* 4594 */ MCD_OPC_FilterValue, 1, 204, 11, // Skip to: 7618 >+/* 4598 */ MCD_OPC_CheckPredicate, 0, 200, 11, // Skip to: 7618 >+/* 4602 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4606 */ MCD_OPC_Decode, 198, 2, 63, // Opcode: SHASX >+/* 4610 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 4649 >+/* 4614 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4617 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4633 >+/* 4621 */ MCD_OPC_CheckPredicate, 0, 177, 11, // Skip to: 7618 >+/* 4625 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4629 */ MCD_OPC_Decode, 144, 2, 63, // Opcode: QSAX >+/* 4633 */ MCD_OPC_FilterValue, 1, 165, 11, // Skip to: 7618 >+/* 4637 */ MCD_OPC_CheckPredicate, 0, 161, 11, // Skip to: 7618 >+/* 4641 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4645 */ MCD_OPC_Decode, 199, 2, 63, // Opcode: SHSAX >+/* 4649 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 4688 >+/* 4653 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4656 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4672 >+/* 4660 */ MCD_OPC_CheckPredicate, 0, 138, 11, // Skip to: 7618 >+/* 4664 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4668 */ MCD_OPC_Decode, 146, 2, 63, // Opcode: QSUB16 >+/* 4672 */ MCD_OPC_FilterValue, 1, 126, 11, // Skip to: 7618 >+/* 4676 */ MCD_OPC_CheckPredicate, 0, 122, 11, // Skip to: 7618 >+/* 4680 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4684 */ MCD_OPC_Decode, 200, 2, 63, // Opcode: SHSUB16 >+/* 4688 */ MCD_OPC_FilterValue, 4, 35, 0, // Skip to: 4727 >+/* 4692 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4695 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4711 >+/* 4699 */ MCD_OPC_CheckPredicate, 0, 99, 11, // Skip to: 7618 >+/* 4703 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4707 */ MCD_OPC_Decode, 140, 2, 63, // Opcode: QADD8 >+/* 4711 */ MCD_OPC_FilterValue, 1, 87, 11, // Skip to: 7618 >+/* 4715 */ MCD_OPC_CheckPredicate, 0, 83, 11, // Skip to: 7618 >+/* 4719 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4723 */ MCD_OPC_Decode, 197, 2, 63, // Opcode: SHADD8 >+/* 4727 */ MCD_OPC_FilterValue, 7, 71, 11, // Skip to: 7618 >+/* 4731 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4734 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 4750 >+/* 4738 */ MCD_OPC_CheckPredicate, 0, 60, 11, // Skip to: 7618 >+/* 4742 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4746 */ MCD_OPC_Decode, 147, 2, 63, // Opcode: QSUB8 >+/* 4750 */ MCD_OPC_FilterValue, 1, 48, 11, // Skip to: 7618 >+/* 4754 */ MCD_OPC_CheckPredicate, 0, 44, 11, // Skip to: 7618 >+/* 4758 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 4762 */ MCD_OPC_Decode, 201, 2, 63, // Opcode: SHSUB8 >+/* 4766 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 4940 >+/* 4770 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 4773 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4785 >+/* 4777 */ MCD_OPC_CheckPredicate, 0, 21, 11, // Skip to: 7618 >+/* 4781 */ MCD_OPC_Decode, 249, 2, 72, // Opcode: SSAT >+/* 4785 */ MCD_OPC_FilterValue, 1, 13, 11, // Skip to: 7618 >+/* 4789 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 4792 */ MCD_OPC_FilterValue, 0, 45, 0, // Skip to: 4841 >+/* 4796 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4799 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4817 >+/* 4803 */ MCD_OPC_CheckPredicate, 0, 251, 10, // Skip to: 7618 >+/* 4807 */ MCD_OPC_CheckField, 8, 4, 15, 245, 10, // Skip to: 7618 >+/* 4813 */ MCD_OPC_Decode, 250, 2, 73, // Opcode: SSAT16 >+/* 4817 */ MCD_OPC_FilterValue, 1, 237, 10, // Skip to: 7618 >+/* 4821 */ MCD_OPC_CheckPredicate, 1, 233, 10, // Skip to: 7618 >+/* 4825 */ MCD_OPC_CheckField, 16, 4, 15, 227, 10, // Skip to: 7618 >+/* 4831 */ MCD_OPC_CheckField, 8, 4, 15, 221, 10, // Skip to: 7618 >+/* 4837 */ MCD_OPC_Decode, 149, 2, 32, // Opcode: REV >+/* 4841 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 4916 >+/* 4845 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4848 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 4882 >+/* 4852 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 4870 >+/* 4856 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 4870 >+/* 4862 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4866 */ MCD_OPC_Decode, 207, 3, 68, // Opcode: SXTB >+/* 4870 */ MCD_OPC_CheckPredicate, 1, 184, 10, // Skip to: 7618 >+/* 4874 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4878 */ MCD_OPC_Decode, 204, 3, 69, // Opcode: SXTAB >+/* 4882 */ MCD_OPC_FilterValue, 1, 172, 10, // Skip to: 7618 >+/* 4886 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 4904 >+/* 4890 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 4904 >+/* 4896 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4900 */ MCD_OPC_Decode, 209, 3, 68, // Opcode: SXTH >+/* 4904 */ MCD_OPC_CheckPredicate, 1, 150, 10, // Skip to: 7618 >+/* 4908 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 4912 */ MCD_OPC_Decode, 206, 3, 69, // Opcode: SXTAH >+/* 4916 */ MCD_OPC_FilterValue, 2, 138, 10, // Skip to: 7618 >+/* 4920 */ MCD_OPC_CheckPredicate, 1, 134, 10, // Skip to: 7618 >+/* 4924 */ MCD_OPC_CheckField, 16, 5, 31, 128, 10, // Skip to: 7618 >+/* 4930 */ MCD_OPC_CheckField, 8, 4, 15, 122, 10, // Skip to: 7618 >+/* 4936 */ MCD_OPC_Decode, 150, 2, 32, // Opcode: REV16 >+/* 4940 */ MCD_OPC_FilterValue, 2, 26, 0, // Skip to: 4970 >+/* 4944 */ MCD_OPC_CheckPredicate, 13, 110, 10, // Skip to: 7618 >+/* 4948 */ MCD_OPC_CheckField, 20, 1, 1, 104, 10, // Skip to: 7618 >+/* 4954 */ MCD_OPC_CheckField, 12, 4, 15, 98, 10, // Skip to: 7618 >+/* 4960 */ MCD_OPC_CheckField, 5, 3, 0, 92, 10, // Skip to: 7618 >+/* 4966 */ MCD_OPC_Decode, 230, 3, 26, // Opcode: UDIV >+/* 4970 */ MCD_OPC_FilterValue, 3, 84, 10, // Skip to: 7618 >+/* 4974 */ MCD_OPC_CheckPredicate, 9, 80, 10, // Skip to: 7618 >+/* 4978 */ MCD_OPC_CheckField, 5, 2, 2, 74, 10, // Skip to: 7618 >+/* 4984 */ MCD_OPC_Decode, 182, 2, 74, // Opcode: SBFX >+/* 4988 */ MCD_OPC_FilterValue, 2, 67, 2, // Skip to: 5571 >+/* 4992 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 4995 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 5104 >+/* 4999 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5002 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5033 >+/* 5006 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5009 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5021 >+/* 5013 */ MCD_OPC_CheckPredicate, 0, 41, 10, // Skip to: 7618 >+/* 5017 */ MCD_OPC_Decode, 161, 3, 52, // Opcode: STRB_POST_REG >+/* 5021 */ MCD_OPC_FilterValue, 1, 33, 10, // Skip to: 7618 >+/* 5025 */ MCD_OPC_CheckPredicate, 0, 29, 10, // Skip to: 7618 >+/* 5029 */ MCD_OPC_Decode, 167, 3, 75, // Opcode: STRBrs >+/* 5033 */ MCD_OPC_FilterValue, 1, 21, 10, // Skip to: 7618 >+/* 5037 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5040 */ MCD_OPC_FilterValue, 0, 28, 0, // Skip to: 5072 >+/* 5044 */ MCD_OPC_CheckPredicate, 10, 16, 0, // Skip to: 5064 >+/* 5048 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 5064 >+/* 5054 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5064 >+/* 5060 */ MCD_OPC_Decode, 137, 2, 62, // Opcode: PLIrs >+/* 5064 */ MCD_OPC_CheckPredicate, 0, 246, 9, // Skip to: 7618 >+/* 5068 */ MCD_OPC_Decode, 155, 1, 52, // Opcode: LDRB_POST_REG >+/* 5072 */ MCD_OPC_FilterValue, 1, 238, 9, // Skip to: 7618 >+/* 5076 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 5096 >+/* 5080 */ MCD_OPC_CheckField, 28, 4, 15, 10, 0, // Skip to: 5096 >+/* 5086 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5096 >+/* 5092 */ MCD_OPC_Decode, 135, 2, 62, // Opcode: PLDrs >+/* 5096 */ MCD_OPC_CheckPredicate, 0, 214, 9, // Skip to: 7618 >+/* 5100 */ MCD_OPC_Decode, 159, 1, 75, // Opcode: LDRBrs >+/* 5104 */ MCD_OPC_FilterValue, 1, 206, 9, // Skip to: 7618 >+/* 5108 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 5111 */ MCD_OPC_FilterValue, 0, 136, 0, // Skip to: 5251 >+/* 5115 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5118 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 5169 >+/* 5122 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5125 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5147 >+/* 5129 */ MCD_OPC_CheckPredicate, 0, 181, 9, // Skip to: 7618 >+/* 5133 */ MCD_OPC_CheckField, 20, 1, 1, 175, 9, // Skip to: 7618 >+/* 5139 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5143 */ MCD_OPC_Decode, 225, 3, 63, // Opcode: UADD16 >+/* 5147 */ MCD_OPC_FilterValue, 1, 163, 9, // Skip to: 7618 >+/* 5151 */ MCD_OPC_CheckPredicate, 0, 159, 9, // Skip to: 7618 >+/* 5155 */ MCD_OPC_CheckField, 20, 1, 1, 153, 9, // Skip to: 7618 >+/* 5161 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5165 */ MCD_OPC_Decode, 226, 3, 63, // Opcode: UADD8 >+/* 5169 */ MCD_OPC_FilterValue, 2, 54, 0, // Skip to: 5227 >+/* 5173 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5176 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5194 >+/* 5180 */ MCD_OPC_CheckPredicate, 1, 130, 9, // Skip to: 7618 >+/* 5184 */ MCD_OPC_CheckField, 7, 1, 0, 124, 9, // Skip to: 7618 >+/* 5190 */ MCD_OPC_Decode, 210, 2, 19, // Opcode: SMLALD >+/* 5194 */ MCD_OPC_FilterValue, 1, 116, 9, // Skip to: 7618 >+/* 5198 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5201 */ MCD_OPC_FilterValue, 0, 109, 9, // Skip to: 7618 >+/* 5205 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 5219 >+/* 5209 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5219 >+/* 5215 */ MCD_OPC_Decode, 227, 2, 26, // Opcode: SMMUL >+/* 5219 */ MCD_OPC_CheckPredicate, 1, 91, 9, // Skip to: 7618 >+/* 5223 */ MCD_OPC_Decode, 223, 2, 37, // Opcode: SMMLA >+/* 5227 */ MCD_OPC_FilterValue, 3, 83, 9, // Skip to: 7618 >+/* 5231 */ MCD_OPC_CheckPredicate, 9, 9, 0, // Skip to: 5244 >+/* 5235 */ MCD_OPC_CheckField, 0, 4, 15, 3, 0, // Skip to: 5244 >+/* 5241 */ MCD_OPC_Decode, 49, 76, // Opcode: BFC >+/* 5244 */ MCD_OPC_CheckPredicate, 9, 66, 9, // Skip to: 7618 >+/* 5248 */ MCD_OPC_Decode, 50, 77, // Opcode: BFI >+/* 5251 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 5344 >+/* 5255 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5258 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5282 >+/* 5262 */ MCD_OPC_CheckPredicate, 1, 48, 9, // Skip to: 7618 >+/* 5266 */ MCD_OPC_CheckField, 23, 2, 2, 42, 9, // Skip to: 7618 >+/* 5272 */ MCD_OPC_CheckField, 7, 1, 0, 36, 9, // Skip to: 7618 >+/* 5278 */ MCD_OPC_Decode, 211, 2, 19, // Opcode: SMLALDX >+/* 5282 */ MCD_OPC_FilterValue, 1, 28, 9, // Skip to: 7618 >+/* 5286 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5289 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5311 >+/* 5293 */ MCD_OPC_CheckPredicate, 0, 17, 9, // Skip to: 7618 >+/* 5297 */ MCD_OPC_CheckField, 7, 1, 0, 11, 9, // Skip to: 7618 >+/* 5303 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5307 */ MCD_OPC_Decode, 227, 3, 63, // Opcode: UASX >+/* 5311 */ MCD_OPC_FilterValue, 2, 255, 8, // Skip to: 7618 >+/* 5315 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5318 */ MCD_OPC_FilterValue, 0, 248, 8, // Skip to: 7618 >+/* 5322 */ MCD_OPC_CheckPredicate, 1, 10, 0, // Skip to: 5336 >+/* 5326 */ MCD_OPC_CheckField, 12, 4, 15, 4, 0, // Skip to: 5336 >+/* 5332 */ MCD_OPC_Decode, 228, 2, 26, // Opcode: SMMULR >+/* 5336 */ MCD_OPC_CheckPredicate, 1, 230, 8, // Skip to: 7618 >+/* 5340 */ MCD_OPC_Decode, 224, 2, 37, // Opcode: SMMLAR >+/* 5344 */ MCD_OPC_FilterValue, 2, 74, 0, // Skip to: 5422 >+/* 5348 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5351 */ MCD_OPC_FilterValue, 0, 43, 0, // Skip to: 5398 >+/* 5355 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5358 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5376 >+/* 5362 */ MCD_OPC_CheckPredicate, 1, 204, 8, // Skip to: 7618 >+/* 5366 */ MCD_OPC_CheckField, 23, 2, 2, 198, 8, // Skip to: 7618 >+/* 5372 */ MCD_OPC_Decode, 221, 2, 19, // Opcode: SMLSLD >+/* 5376 */ MCD_OPC_FilterValue, 1, 190, 8, // Skip to: 7618 >+/* 5380 */ MCD_OPC_CheckPredicate, 0, 186, 8, // Skip to: 7618 >+/* 5384 */ MCD_OPC_CheckField, 23, 2, 0, 180, 8, // Skip to: 7618 >+/* 5390 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5394 */ MCD_OPC_Decode, 252, 3, 63, // Opcode: USAX >+/* 5398 */ MCD_OPC_FilterValue, 1, 168, 8, // Skip to: 7618 >+/* 5402 */ MCD_OPC_CheckPredicate, 1, 164, 8, // Skip to: 7618 >+/* 5406 */ MCD_OPC_CheckField, 23, 2, 2, 158, 8, // Skip to: 7618 >+/* 5412 */ MCD_OPC_CheckField, 20, 1, 1, 152, 8, // Skip to: 7618 >+/* 5418 */ MCD_OPC_Decode, 225, 2, 37, // Opcode: SMMLS >+/* 5422 */ MCD_OPC_FilterValue, 3, 144, 8, // Skip to: 7618 >+/* 5426 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5429 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 5480 >+/* 5433 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5436 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 5458 >+/* 5440 */ MCD_OPC_CheckPredicate, 0, 126, 8, // Skip to: 7618 >+/* 5444 */ MCD_OPC_CheckField, 20, 1, 1, 120, 8, // Skip to: 7618 >+/* 5450 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5454 */ MCD_OPC_Decode, 253, 3, 63, // Opcode: USUB16 >+/* 5458 */ MCD_OPC_FilterValue, 1, 108, 8, // Skip to: 7618 >+/* 5462 */ MCD_OPC_CheckPredicate, 0, 104, 8, // Skip to: 7618 >+/* 5466 */ MCD_OPC_CheckField, 20, 1, 1, 98, 8, // Skip to: 7618 >+/* 5472 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5476 */ MCD_OPC_Decode, 254, 3, 63, // Opcode: USUB8 >+/* 5480 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 5528 >+/* 5484 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5487 */ MCD_OPC_FilterValue, 0, 79, 8, // Skip to: 7618 >+/* 5491 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5494 */ MCD_OPC_FilterValue, 0, 72, 8, // Skip to: 7618 >+/* 5498 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 5516 >+/* 5502 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 5516 >+/* 5508 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5512 */ MCD_OPC_Decode, 131, 4, 68, // Opcode: UXTB16 >+/* 5516 */ MCD_OPC_CheckPredicate, 1, 50, 8, // Skip to: 7618 >+/* 5520 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5524 */ MCD_OPC_Decode, 128, 4, 69, // Opcode: UXTAB16 >+/* 5528 */ MCD_OPC_FilterValue, 2, 38, 8, // Skip to: 7618 >+/* 5532 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5535 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5553 >+/* 5539 */ MCD_OPC_CheckPredicate, 1, 27, 8, // Skip to: 7618 >+/* 5543 */ MCD_OPC_CheckField, 20, 1, 0, 21, 8, // Skip to: 7618 >+/* 5549 */ MCD_OPC_Decode, 222, 2, 19, // Opcode: SMLSLDX >+/* 5553 */ MCD_OPC_FilterValue, 1, 13, 8, // Skip to: 7618 >+/* 5557 */ MCD_OPC_CheckPredicate, 1, 9, 8, // Skip to: 7618 >+/* 5561 */ MCD_OPC_CheckField, 20, 1, 1, 3, 8, // Skip to: 7618 >+/* 5567 */ MCD_OPC_Decode, 226, 2, 37, // Opcode: SMMLSR >+/* 5571 */ MCD_OPC_FilterValue, 3, 251, 7, // Skip to: 7618 >+/* 5575 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 5578 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 5647 >+/* 5582 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5585 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5616 >+/* 5589 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5592 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5604 >+/* 5596 */ MCD_OPC_CheckPredicate, 0, 226, 7, // Skip to: 7618 >+/* 5600 */ MCD_OPC_Decode, 159, 3, 52, // Opcode: STRBT_POST_REG >+/* 5604 */ MCD_OPC_FilterValue, 1, 218, 7, // Skip to: 7618 >+/* 5608 */ MCD_OPC_CheckPredicate, 0, 214, 7, // Skip to: 7618 >+/* 5612 */ MCD_OPC_Decode, 163, 3, 70, // Opcode: STRB_PRE_REG >+/* 5616 */ MCD_OPC_FilterValue, 1, 206, 7, // Skip to: 7618 >+/* 5620 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 5623 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5635 >+/* 5627 */ MCD_OPC_CheckPredicate, 0, 195, 7, // Skip to: 7618 >+/* 5631 */ MCD_OPC_Decode, 153, 1, 52, // Opcode: LDRBT_POST_REG >+/* 5635 */ MCD_OPC_FilterValue, 1, 187, 7, // Skip to: 7618 >+/* 5639 */ MCD_OPC_CheckPredicate, 0, 183, 7, // Skip to: 7618 >+/* 5643 */ MCD_OPC_Decode, 157, 1, 71, // Opcode: LDRB_PRE_REG >+/* 5647 */ MCD_OPC_FilterValue, 1, 175, 7, // Skip to: 7618 >+/* 5651 */ MCD_OPC_ExtractField, 23, 2, // Inst{24-23} ... >+/* 5654 */ MCD_OPC_FilterValue, 0, 237, 0, // Skip to: 5895 >+/* 5658 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 5661 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 5700 >+/* 5665 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5668 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5684 >+/* 5672 */ MCD_OPC_CheckPredicate, 0, 150, 7, // Skip to: 7618 >+/* 5676 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5680 */ MCD_OPC_Decode, 242, 3, 63, // Opcode: UQADD16 >+/* 5684 */ MCD_OPC_FilterValue, 1, 138, 7, // Skip to: 7618 >+/* 5688 */ MCD_OPC_CheckPredicate, 0, 134, 7, // Skip to: 7618 >+/* 5692 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5696 */ MCD_OPC_Decode, 231, 3, 63, // Opcode: UHADD16 >+/* 5700 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 5739 >+/* 5704 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5707 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5723 >+/* 5711 */ MCD_OPC_CheckPredicate, 0, 111, 7, // Skip to: 7618 >+/* 5715 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5719 */ MCD_OPC_Decode, 244, 3, 63, // Opcode: UQASX >+/* 5723 */ MCD_OPC_FilterValue, 1, 99, 7, // Skip to: 7618 >+/* 5727 */ MCD_OPC_CheckPredicate, 0, 95, 7, // Skip to: 7618 >+/* 5731 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5735 */ MCD_OPC_Decode, 233, 3, 63, // Opcode: UHASX >+/* 5739 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 5778 >+/* 5743 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5746 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5762 >+/* 5750 */ MCD_OPC_CheckPredicate, 0, 72, 7, // Skip to: 7618 >+/* 5754 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5758 */ MCD_OPC_Decode, 245, 3, 63, // Opcode: UQSAX >+/* 5762 */ MCD_OPC_FilterValue, 1, 60, 7, // Skip to: 7618 >+/* 5766 */ MCD_OPC_CheckPredicate, 0, 56, 7, // Skip to: 7618 >+/* 5770 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5774 */ MCD_OPC_Decode, 234, 3, 63, // Opcode: UHSAX >+/* 5778 */ MCD_OPC_FilterValue, 3, 35, 0, // Skip to: 5817 >+/* 5782 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5785 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5801 >+/* 5789 */ MCD_OPC_CheckPredicate, 0, 33, 7, // Skip to: 7618 >+/* 5793 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5797 */ MCD_OPC_Decode, 246, 3, 63, // Opcode: UQSUB16 >+/* 5801 */ MCD_OPC_FilterValue, 1, 21, 7, // Skip to: 7618 >+/* 5805 */ MCD_OPC_CheckPredicate, 0, 17, 7, // Skip to: 7618 >+/* 5809 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5813 */ MCD_OPC_Decode, 235, 3, 63, // Opcode: UHSUB16 >+/* 5817 */ MCD_OPC_FilterValue, 4, 35, 0, // Skip to: 5856 >+/* 5821 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5824 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5840 >+/* 5828 */ MCD_OPC_CheckPredicate, 0, 250, 6, // Skip to: 7618 >+/* 5832 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5836 */ MCD_OPC_Decode, 243, 3, 63, // Opcode: UQADD8 >+/* 5840 */ MCD_OPC_FilterValue, 1, 238, 6, // Skip to: 7618 >+/* 5844 */ MCD_OPC_CheckPredicate, 0, 234, 6, // Skip to: 7618 >+/* 5848 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5852 */ MCD_OPC_Decode, 232, 3, 63, // Opcode: UHADD8 >+/* 5856 */ MCD_OPC_FilterValue, 7, 222, 6, // Skip to: 7618 >+/* 5860 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5863 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 5879 >+/* 5867 */ MCD_OPC_CheckPredicate, 0, 211, 6, // Skip to: 7618 >+/* 5871 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5875 */ MCD_OPC_Decode, 247, 3, 63, // Opcode: UQSUB8 >+/* 5879 */ MCD_OPC_FilterValue, 1, 199, 6, // Skip to: 7618 >+/* 5883 */ MCD_OPC_CheckPredicate, 0, 195, 6, // Skip to: 7618 >+/* 5887 */ MCD_OPC_SoftFail, 0, 128, 30 /* 0xF00 */, >+/* 5891 */ MCD_OPC_Decode, 236, 3, 63, // Opcode: UHSUB8 >+/* 5895 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 6069 >+/* 5899 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 5902 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5914 >+/* 5906 */ MCD_OPC_CheckPredicate, 0, 172, 6, // Skip to: 7618 >+/* 5910 */ MCD_OPC_Decode, 250, 3, 72, // Opcode: USAT >+/* 5914 */ MCD_OPC_FilterValue, 1, 164, 6, // Skip to: 7618 >+/* 5918 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5921 */ MCD_OPC_FilterValue, 0, 45, 0, // Skip to: 5970 >+/* 5925 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5928 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5946 >+/* 5932 */ MCD_OPC_CheckPredicate, 0, 146, 6, // Skip to: 7618 >+/* 5936 */ MCD_OPC_CheckField, 8, 4, 15, 140, 6, // Skip to: 7618 >+/* 5942 */ MCD_OPC_Decode, 251, 3, 73, // Opcode: USAT16 >+/* 5946 */ MCD_OPC_FilterValue, 1, 132, 6, // Skip to: 7618 >+/* 5950 */ MCD_OPC_CheckPredicate, 9, 128, 6, // Skip to: 7618 >+/* 5954 */ MCD_OPC_CheckField, 16, 4, 15, 122, 6, // Skip to: 7618 >+/* 5960 */ MCD_OPC_CheckField, 8, 4, 15, 116, 6, // Skip to: 7618 >+/* 5966 */ MCD_OPC_Decode, 148, 2, 32, // Opcode: RBIT >+/* 5970 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 6045 >+/* 5974 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5977 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 6011 >+/* 5981 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 5999 >+/* 5985 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 5999 >+/* 5991 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 5995 */ MCD_OPC_Decode, 130, 4, 68, // Opcode: UXTB >+/* 5999 */ MCD_OPC_CheckPredicate, 1, 79, 6, // Skip to: 7618 >+/* 6003 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6007 */ MCD_OPC_Decode, 255, 3, 69, // Opcode: UXTAB >+/* 6011 */ MCD_OPC_FilterValue, 1, 67, 6, // Skip to: 7618 >+/* 6015 */ MCD_OPC_CheckPredicate, 1, 14, 0, // Skip to: 6033 >+/* 6019 */ MCD_OPC_CheckField, 16, 4, 15, 8, 0, // Skip to: 6033 >+/* 6025 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6029 */ MCD_OPC_Decode, 132, 4, 68, // Opcode: UXTH >+/* 6033 */ MCD_OPC_CheckPredicate, 1, 45, 6, // Skip to: 7618 >+/* 6037 */ MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0, >+/* 6041 */ MCD_OPC_Decode, 129, 4, 69, // Opcode: UXTAH >+/* 6045 */ MCD_OPC_FilterValue, 2, 33, 6, // Skip to: 7618 >+/* 6049 */ MCD_OPC_CheckPredicate, 1, 29, 6, // Skip to: 7618 >+/* 6053 */ MCD_OPC_CheckField, 16, 5, 31, 23, 6, // Skip to: 7618 >+/* 6059 */ MCD_OPC_CheckField, 8, 4, 15, 17, 6, // Skip to: 7618 >+/* 6065 */ MCD_OPC_Decode, 151, 2, 32, // Opcode: REVSH >+/* 6069 */ MCD_OPC_FilterValue, 3, 9, 6, // Skip to: 7618 >+/* 6073 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... >+/* 6076 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6088 >+/* 6080 */ MCD_OPC_CheckPredicate, 9, 254, 5, // Skip to: 7618 >+/* 6084 */ MCD_OPC_Decode, 228, 3, 74, // Opcode: UBFX >+/* 6088 */ MCD_OPC_FilterValue, 3, 246, 5, // Skip to: 7618 >+/* 6092 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 6095 */ MCD_OPC_FilterValue, 1, 239, 5, // Skip to: 7618 >+/* 6099 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 6102 */ MCD_OPC_FilterValue, 1, 232, 5, // Skip to: 7618 >+/* 6106 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... >+/* 6109 */ MCD_OPC_FilterValue, 14, 225, 5, // Skip to: 7618 >+/* 6113 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 6116 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 6135 >+/* 6120 */ MCD_OPC_CheckPredicate, 14, 30, 0, // Skip to: 6154 >+/* 6124 */ MCD_OPC_CheckField, 8, 12, 222, 29, 23, 0, // Skip to: 6154 >+/* 6131 */ MCD_OPC_Decode, 220, 3, 58, // Opcode: TRAPNaCl >+/* 6135 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 6154 >+/* 6139 */ MCD_OPC_CheckPredicate, 0, 11, 0, // Skip to: 6154 >+/* 6143 */ MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, // Skip to: 6154 >+/* 6150 */ MCD_OPC_Decode, 219, 3, 58, // Opcode: TRAP >+/* 6154 */ MCD_OPC_CheckPredicate, 0, 180, 5, // Skip to: 7618 >+/* 6158 */ MCD_OPC_Decode, 229, 3, 15, // Opcode: UDF >+/* 6162 */ MCD_OPC_FilterValue, 4, 219, 2, // Skip to: 6897 >+/* 6166 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... >+/* 6169 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6181 >+/* 6173 */ MCD_OPC_CheckPredicate, 0, 161, 5, // Skip to: 7618 >+/* 6177 */ MCD_OPC_Decode, 149, 3, 78, // Opcode: STMDA >+/* 6181 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 6214 >+/* 6185 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6206 >+/* 6189 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6206 >+/* 6195 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6206 >+/* 6202 */ MCD_OPC_Decode, 152, 2, 79, // Opcode: RFEDA >+/* 6206 */ MCD_OPC_CheckPredicate, 0, 128, 5, // Skip to: 7618 >+/* 6210 */ MCD_OPC_Decode, 142, 1, 78, // Opcode: LDMDA >+/* 6214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6226 >+/* 6218 */ MCD_OPC_CheckPredicate, 0, 116, 5, // Skip to: 7618 >+/* 6222 */ MCD_OPC_Decode, 150, 3, 80, // Opcode: STMDA_UPD >+/* 6226 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 6259 >+/* 6230 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6251 >+/* 6234 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6251 >+/* 6240 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6251 >+/* 6247 */ MCD_OPC_Decode, 153, 2, 79, // Opcode: RFEDA_UPD >+/* 6251 */ MCD_OPC_CheckPredicate, 0, 83, 5, // Skip to: 7618 >+/* 6255 */ MCD_OPC_Decode, 143, 1, 80, // Opcode: LDMDA_UPD >+/* 6259 */ MCD_OPC_FilterValue, 4, 30, 0, // Skip to: 6293 >+/* 6263 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6285 >+/* 6267 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6285 >+/* 6273 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6285 >+/* 6281 */ MCD_OPC_Decode, 241, 2, 81, // Opcode: SRSDA >+/* 6285 */ MCD_OPC_CheckPredicate, 0, 49, 5, // Skip to: 7618 >+/* 6289 */ MCD_OPC_Decode, 227, 17, 78, // Opcode: sysSTMDA >+/* 6293 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6305 >+/* 6297 */ MCD_OPC_CheckPredicate, 0, 37, 5, // Skip to: 7618 >+/* 6301 */ MCD_OPC_Decode, 219, 17, 78, // Opcode: sysLDMDA >+/* 6305 */ MCD_OPC_FilterValue, 6, 30, 0, // Skip to: 6339 >+/* 6309 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6331 >+/* 6313 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6331 >+/* 6319 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6331 >+/* 6327 */ MCD_OPC_Decode, 242, 2, 81, // Opcode: SRSDA_UPD >+/* 6331 */ MCD_OPC_CheckPredicate, 0, 3, 5, // Skip to: 7618 >+/* 6335 */ MCD_OPC_Decode, 228, 17, 80, // Opcode: sysSTMDA_UPD >+/* 6339 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6351 >+/* 6343 */ MCD_OPC_CheckPredicate, 0, 247, 4, // Skip to: 7618 >+/* 6347 */ MCD_OPC_Decode, 220, 17, 80, // Opcode: sysLDMDA_UPD >+/* 6351 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6363 >+/* 6355 */ MCD_OPC_CheckPredicate, 0, 235, 4, // Skip to: 7618 >+/* 6359 */ MCD_OPC_Decode, 153, 3, 78, // Opcode: STMIA >+/* 6363 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 6396 >+/* 6367 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6388 >+/* 6371 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6388 >+/* 6377 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6388 >+/* 6384 */ MCD_OPC_Decode, 156, 2, 79, // Opcode: RFEIA >+/* 6388 */ MCD_OPC_CheckPredicate, 0, 202, 4, // Skip to: 7618 >+/* 6392 */ MCD_OPC_Decode, 146, 1, 78, // Opcode: LDMIA >+/* 6396 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6408 >+/* 6400 */ MCD_OPC_CheckPredicate, 0, 190, 4, // Skip to: 7618 >+/* 6404 */ MCD_OPC_Decode, 154, 3, 80, // Opcode: STMIA_UPD >+/* 6408 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 6441 >+/* 6412 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6433 >+/* 6416 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6433 >+/* 6422 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6433 >+/* 6429 */ MCD_OPC_Decode, 157, 2, 79, // Opcode: RFEIA_UPD >+/* 6433 */ MCD_OPC_CheckPredicate, 0, 157, 4, // Skip to: 7618 >+/* 6437 */ MCD_OPC_Decode, 148, 1, 80, // Opcode: LDMIA_UPD >+/* 6441 */ MCD_OPC_FilterValue, 12, 30, 0, // Skip to: 6475 >+/* 6445 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6467 >+/* 6449 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6467 >+/* 6455 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6467 >+/* 6463 */ MCD_OPC_Decode, 245, 2, 81, // Opcode: SRSIA >+/* 6467 */ MCD_OPC_CheckPredicate, 0, 123, 4, // Skip to: 7618 >+/* 6471 */ MCD_OPC_Decode, 231, 17, 78, // Opcode: sysSTMIA >+/* 6475 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6487 >+/* 6479 */ MCD_OPC_CheckPredicate, 0, 111, 4, // Skip to: 7618 >+/* 6483 */ MCD_OPC_Decode, 223, 17, 78, // Opcode: sysLDMIA >+/* 6487 */ MCD_OPC_FilterValue, 14, 30, 0, // Skip to: 6521 >+/* 6491 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6513 >+/* 6495 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6513 >+/* 6501 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6513 >+/* 6509 */ MCD_OPC_Decode, 246, 2, 81, // Opcode: SRSIA_UPD >+/* 6513 */ MCD_OPC_CheckPredicate, 0, 77, 4, // Skip to: 7618 >+/* 6517 */ MCD_OPC_Decode, 232, 17, 80, // Opcode: sysSTMIA_UPD >+/* 6521 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6533 >+/* 6525 */ MCD_OPC_CheckPredicate, 0, 65, 4, // Skip to: 7618 >+/* 6529 */ MCD_OPC_Decode, 224, 17, 80, // Opcode: sysLDMIA_UPD >+/* 6533 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 6545 >+/* 6537 */ MCD_OPC_CheckPredicate, 0, 53, 4, // Skip to: 7618 >+/* 6541 */ MCD_OPC_Decode, 151, 3, 78, // Opcode: STMDB >+/* 6545 */ MCD_OPC_FilterValue, 17, 29, 0, // Skip to: 6578 >+/* 6549 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6570 >+/* 6553 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6570 >+/* 6559 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6570 >+/* 6566 */ MCD_OPC_Decode, 154, 2, 79, // Opcode: RFEDB >+/* 6570 */ MCD_OPC_CheckPredicate, 0, 20, 4, // Skip to: 7618 >+/* 6574 */ MCD_OPC_Decode, 144, 1, 78, // Opcode: LDMDB >+/* 6578 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 6590 >+/* 6582 */ MCD_OPC_CheckPredicate, 0, 8, 4, // Skip to: 7618 >+/* 6586 */ MCD_OPC_Decode, 152, 3, 80, // Opcode: STMDB_UPD >+/* 6590 */ MCD_OPC_FilterValue, 19, 29, 0, // Skip to: 6623 >+/* 6594 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6615 >+/* 6598 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6615 >+/* 6604 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6615 >+/* 6611 */ MCD_OPC_Decode, 155, 2, 79, // Opcode: RFEDB_UPD >+/* 6615 */ MCD_OPC_CheckPredicate, 0, 231, 3, // Skip to: 7618 >+/* 6619 */ MCD_OPC_Decode, 145, 1, 80, // Opcode: LDMDB_UPD >+/* 6623 */ MCD_OPC_FilterValue, 20, 30, 0, // Skip to: 6657 >+/* 6627 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6649 >+/* 6631 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6649 >+/* 6637 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6649 >+/* 6645 */ MCD_OPC_Decode, 243, 2, 81, // Opcode: SRSDB >+/* 6649 */ MCD_OPC_CheckPredicate, 0, 197, 3, // Skip to: 7618 >+/* 6653 */ MCD_OPC_Decode, 229, 17, 78, // Opcode: sysSTMDB >+/* 6657 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 6669 >+/* 6661 */ MCD_OPC_CheckPredicate, 0, 185, 3, // Skip to: 7618 >+/* 6665 */ MCD_OPC_Decode, 221, 17, 78, // Opcode: sysLDMDB >+/* 6669 */ MCD_OPC_FilterValue, 22, 30, 0, // Skip to: 6703 >+/* 6673 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6695 >+/* 6677 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6695 >+/* 6683 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6695 >+/* 6691 */ MCD_OPC_Decode, 244, 2, 81, // Opcode: SRSDB_UPD >+/* 6695 */ MCD_OPC_CheckPredicate, 0, 151, 3, // Skip to: 7618 >+/* 6699 */ MCD_OPC_Decode, 230, 17, 80, // Opcode: sysSTMDB_UPD >+/* 6703 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 6715 >+/* 6707 */ MCD_OPC_CheckPredicate, 0, 139, 3, // Skip to: 7618 >+/* 6711 */ MCD_OPC_Decode, 222, 17, 80, // Opcode: sysLDMDB_UPD >+/* 6715 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 6727 >+/* 6719 */ MCD_OPC_CheckPredicate, 0, 127, 3, // Skip to: 7618 >+/* 6723 */ MCD_OPC_Decode, 155, 3, 78, // Opcode: STMIB >+/* 6727 */ MCD_OPC_FilterValue, 25, 29, 0, // Skip to: 6760 >+/* 6731 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6752 >+/* 6735 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6752 >+/* 6741 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6752 >+/* 6748 */ MCD_OPC_Decode, 158, 2, 79, // Opcode: RFEIB >+/* 6752 */ MCD_OPC_CheckPredicate, 0, 94, 3, // Skip to: 7618 >+/* 6756 */ MCD_OPC_Decode, 149, 1, 78, // Opcode: LDMIB >+/* 6760 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 6772 >+/* 6764 */ MCD_OPC_CheckPredicate, 0, 82, 3, // Skip to: 7618 >+/* 6768 */ MCD_OPC_Decode, 156, 3, 80, // Opcode: STMIB_UPD >+/* 6772 */ MCD_OPC_FilterValue, 27, 29, 0, // Skip to: 6805 >+/* 6776 */ MCD_OPC_CheckPredicate, 0, 17, 0, // Skip to: 6797 >+/* 6780 */ MCD_OPC_CheckField, 28, 4, 15, 11, 0, // Skip to: 6797 >+/* 6786 */ MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, // Skip to: 6797 >+/* 6793 */ MCD_OPC_Decode, 159, 2, 79, // Opcode: RFEIB_UPD >+/* 6797 */ MCD_OPC_CheckPredicate, 0, 49, 3, // Skip to: 7618 >+/* 6801 */ MCD_OPC_Decode, 150, 1, 80, // Opcode: LDMIB_UPD >+/* 6805 */ MCD_OPC_FilterValue, 28, 30, 0, // Skip to: 6839 >+/* 6809 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6831 >+/* 6813 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6831 >+/* 6819 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6831 >+/* 6827 */ MCD_OPC_Decode, 247, 2, 81, // Opcode: SRSIB >+/* 6831 */ MCD_OPC_CheckPredicate, 0, 15, 3, // Skip to: 7618 >+/* 6835 */ MCD_OPC_Decode, 233, 17, 78, // Opcode: sysSTMIB >+/* 6839 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 6851 >+/* 6843 */ MCD_OPC_CheckPredicate, 0, 3, 3, // Skip to: 7618 >+/* 6847 */ MCD_OPC_Decode, 225, 17, 78, // Opcode: sysLDMIB >+/* 6851 */ MCD_OPC_FilterValue, 30, 30, 0, // Skip to: 6885 >+/* 6855 */ MCD_OPC_CheckPredicate, 0, 18, 0, // Skip to: 6877 >+/* 6859 */ MCD_OPC_CheckField, 28, 4, 15, 12, 0, // Skip to: 6877 >+/* 6865 */ MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, // Skip to: 6877 >+/* 6873 */ MCD_OPC_Decode, 248, 2, 81, // Opcode: SRSIB_UPD >+/* 6877 */ MCD_OPC_CheckPredicate, 0, 225, 2, // Skip to: 7618 >+/* 6881 */ MCD_OPC_Decode, 234, 17, 80, // Opcode: sysSTMIB_UPD >+/* 6885 */ MCD_OPC_FilterValue, 31, 217, 2, // Skip to: 7618 >+/* 6889 */ MCD_OPC_CheckPredicate, 0, 213, 2, // Skip to: 7618 >+/* 6893 */ MCD_OPC_Decode, 226, 17, 80, // Opcode: sysLDMIB_UPD >+/* 6897 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 6952 >+/* 6901 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 6904 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 6915 >+/* 6908 */ MCD_OPC_CheckPredicate, 0, 27, 0, // Skip to: 6939 >+/* 6912 */ MCD_OPC_Decode, 71, 82, // Opcode: Bcc >+/* 6915 */ MCD_OPC_FilterValue, 1, 20, 0, // Skip to: 6939 >+/* 6919 */ MCD_OPC_CheckPredicate, 0, 9, 0, // Skip to: 6932 >+/* 6923 */ MCD_OPC_CheckField, 28, 4, 14, 3, 0, // Skip to: 6932 >+/* 6929 */ MCD_OPC_Decode, 56, 82, // Opcode: BL >+/* 6932 */ MCD_OPC_CheckPredicate, 0, 3, 0, // Skip to: 6939 >+/* 6936 */ MCD_OPC_Decode, 60, 82, // Opcode: BL_pred >+/* 6939 */ MCD_OPC_CheckPredicate, 7, 163, 2, // Skip to: 7618 >+/* 6943 */ MCD_OPC_CheckField, 28, 4, 15, 157, 2, // Skip to: 7618 >+/* 6949 */ MCD_OPC_Decode, 59, 83, // Opcode: BLXi >+/* 6952 */ MCD_OPC_FilterValue, 6, 41, 2, // Skip to: 7509 >+/* 6956 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 6959 */ MCD_OPC_FilterValue, 0, 62, 0, // Skip to: 7025 >+/* 6963 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 6966 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 6999 >+/* 6970 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 6973 */ MCD_OPC_FilterValue, 1, 129, 2, // Skip to: 7618 >+/* 6977 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 6991 >+/* 6981 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 6991 >+/* 6987 */ MCD_OPC_Decode, 131, 3, 84, // Opcode: STC2_OPTION >+/* 6991 */ MCD_OPC_CheckPredicate, 0, 111, 2, // Skip to: 7618 >+/* 6995 */ MCD_OPC_Decode, 139, 3, 84, // Opcode: STC_OPTION >+/* 6999 */ MCD_OPC_FilterValue, 1, 103, 2, // Skip to: 7618 >+/* 7003 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7017 >+/* 7007 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7017 >+/* 7013 */ MCD_OPC_Decode, 130, 3, 84, // Opcode: STC2_OFFSET >+/* 7017 */ MCD_OPC_CheckPredicate, 0, 85, 2, // Skip to: 7618 >+/* 7021 */ MCD_OPC_Decode, 138, 3, 84, // Opcode: STC_OFFSET >+/* 7025 */ MCD_OPC_FilterValue, 1, 62, 0, // Skip to: 7091 >+/* 7029 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7032 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 7065 >+/* 7036 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7039 */ MCD_OPC_FilterValue, 1, 63, 2, // Skip to: 7618 >+/* 7043 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7057 >+/* 7047 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7057 >+/* 7053 */ MCD_OPC_Decode, 131, 1, 84, // Opcode: LDC2_OPTION >+/* 7057 */ MCD_OPC_CheckPredicate, 0, 45, 2, // Skip to: 7618 >+/* 7061 */ MCD_OPC_Decode, 139, 1, 84, // Opcode: LDC_OPTION >+/* 7065 */ MCD_OPC_FilterValue, 1, 37, 2, // Skip to: 7618 >+/* 7069 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7083 >+/* 7073 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7083 >+/* 7079 */ MCD_OPC_Decode, 130, 1, 84, // Opcode: LDC2_OFFSET >+/* 7083 */ MCD_OPC_CheckPredicate, 0, 19, 2, // Skip to: 7618 >+/* 7087 */ MCD_OPC_Decode, 138, 1, 84, // Opcode: LDC_OFFSET >+/* 7091 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 7150 >+/* 7095 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7098 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7124 >+/* 7102 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7116 >+/* 7106 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7116 >+/* 7112 */ MCD_OPC_Decode, 132, 3, 84, // Opcode: STC2_POST >+/* 7116 */ MCD_OPC_CheckPredicate, 0, 242, 1, // Skip to: 7618 >+/* 7120 */ MCD_OPC_Decode, 140, 3, 84, // Opcode: STC_POST >+/* 7124 */ MCD_OPC_FilterValue, 1, 234, 1, // Skip to: 7618 >+/* 7128 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7142 >+/* 7132 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7142 >+/* 7138 */ MCD_OPC_Decode, 133, 3, 84, // Opcode: STC2_PRE >+/* 7142 */ MCD_OPC_CheckPredicate, 0, 216, 1, // Skip to: 7618 >+/* 7146 */ MCD_OPC_Decode, 141, 3, 84, // Opcode: STC_PRE >+/* 7150 */ MCD_OPC_FilterValue, 3, 55, 0, // Skip to: 7209 >+/* 7154 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7157 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7183 >+/* 7161 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7175 >+/* 7165 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7175 >+/* 7171 */ MCD_OPC_Decode, 132, 1, 84, // Opcode: LDC2_POST >+/* 7175 */ MCD_OPC_CheckPredicate, 0, 183, 1, // Skip to: 7618 >+/* 7179 */ MCD_OPC_Decode, 140, 1, 84, // Opcode: LDC_POST >+/* 7183 */ MCD_OPC_FilterValue, 1, 175, 1, // Skip to: 7618 >+/* 7187 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7201 >+/* 7191 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7201 >+/* 7197 */ MCD_OPC_Decode, 133, 1, 84, // Opcode: LDC2_PRE >+/* 7201 */ MCD_OPC_CheckPredicate, 0, 157, 1, // Skip to: 7618 >+/* 7205 */ MCD_OPC_Decode, 141, 1, 84, // Opcode: LDC_PRE >+/* 7209 */ MCD_OPC_FilterValue, 4, 88, 0, // Skip to: 7301 >+/* 7213 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7216 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7275 >+/* 7220 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7223 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7249 >+/* 7227 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7241 >+/* 7231 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7241 >+/* 7237 */ MCD_OPC_Decode, 204, 1, 85, // Opcode: MCRR2 >+/* 7241 */ MCD_OPC_CheckPredicate, 0, 117, 1, // Skip to: 7618 >+/* 7245 */ MCD_OPC_Decode, 203, 1, 86, // Opcode: MCRR >+/* 7249 */ MCD_OPC_FilterValue, 1, 109, 1, // Skip to: 7618 >+/* 7253 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7267 >+/* 7257 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7267 >+/* 7263 */ MCD_OPC_Decode, 255, 2, 84, // Opcode: STC2L_OPTION >+/* 7267 */ MCD_OPC_CheckPredicate, 0, 91, 1, // Skip to: 7618 >+/* 7271 */ MCD_OPC_Decode, 135, 3, 84, // Opcode: STCL_OPTION >+/* 7275 */ MCD_OPC_FilterValue, 1, 83, 1, // Skip to: 7618 >+/* 7279 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7293 >+/* 7283 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7293 >+/* 7289 */ MCD_OPC_Decode, 254, 2, 84, // Opcode: STC2L_OFFSET >+/* 7293 */ MCD_OPC_CheckPredicate, 0, 65, 1, // Skip to: 7618 >+/* 7297 */ MCD_OPC_Decode, 134, 3, 84, // Opcode: STCL_OFFSET >+/* 7301 */ MCD_OPC_FilterValue, 5, 86, 0, // Skip to: 7391 >+/* 7305 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7308 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 7366 >+/* 7312 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7315 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7341 >+/* 7319 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7333 >+/* 7323 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7333 >+/* 7329 */ MCD_OPC_Decode, 233, 1, 85, // Opcode: MRRC2 >+/* 7333 */ MCD_OPC_CheckPredicate, 0, 25, 1, // Skip to: 7618 >+/* 7337 */ MCD_OPC_Decode, 232, 1, 86, // Opcode: MRRC >+/* 7341 */ MCD_OPC_FilterValue, 1, 17, 1, // Skip to: 7618 >+/* 7345 */ MCD_OPC_CheckPredicate, 4, 9, 0, // Skip to: 7358 >+/* 7349 */ MCD_OPC_CheckField, 28, 4, 15, 3, 0, // Skip to: 7358 >+/* 7355 */ MCD_OPC_Decode, 127, 84, // Opcode: LDC2L_OPTION >+/* 7358 */ MCD_OPC_CheckPredicate, 0, 0, 1, // Skip to: 7618 >+/* 7362 */ MCD_OPC_Decode, 135, 1, 84, // Opcode: LDCL_OPTION >+/* 7366 */ MCD_OPC_FilterValue, 1, 248, 0, // Skip to: 7618 >+/* 7370 */ MCD_OPC_CheckPredicate, 4, 9, 0, // Skip to: 7383 >+/* 7374 */ MCD_OPC_CheckField, 28, 4, 15, 3, 0, // Skip to: 7383 >+/* 7380 */ MCD_OPC_Decode, 126, 84, // Opcode: LDC2L_OFFSET >+/* 7383 */ MCD_OPC_CheckPredicate, 0, 231, 0, // Skip to: 7618 >+/* 7387 */ MCD_OPC_Decode, 134, 1, 84, // Opcode: LDCL_OFFSET >+/* 7391 */ MCD_OPC_FilterValue, 6, 55, 0, // Skip to: 7450 >+/* 7395 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7398 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7424 >+/* 7402 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7416 >+/* 7406 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7416 >+/* 7412 */ MCD_OPC_Decode, 128, 3, 84, // Opcode: STC2L_POST >+/* 7416 */ MCD_OPC_CheckPredicate, 0, 198, 0, // Skip to: 7618 >+/* 7420 */ MCD_OPC_Decode, 136, 3, 84, // Opcode: STCL_POST >+/* 7424 */ MCD_OPC_FilterValue, 1, 190, 0, // Skip to: 7618 >+/* 7428 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7442 >+/* 7432 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7442 >+/* 7438 */ MCD_OPC_Decode, 129, 3, 84, // Opcode: STC2L_PRE >+/* 7442 */ MCD_OPC_CheckPredicate, 0, 172, 0, // Skip to: 7618 >+/* 7446 */ MCD_OPC_Decode, 137, 3, 84, // Opcode: STCL_PRE >+/* 7450 */ MCD_OPC_FilterValue, 7, 164, 0, // Skip to: 7618 >+/* 7454 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7457 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7483 >+/* 7461 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7475 >+/* 7465 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7475 >+/* 7471 */ MCD_OPC_Decode, 128, 1, 84, // Opcode: LDC2L_POST >+/* 7475 */ MCD_OPC_CheckPredicate, 0, 139, 0, // Skip to: 7618 >+/* 7479 */ MCD_OPC_Decode, 136, 1, 84, // Opcode: LDCL_POST >+/* 7483 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 7618 >+/* 7487 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7501 >+/* 7491 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7501 >+/* 7497 */ MCD_OPC_Decode, 129, 1, 84, // Opcode: LDC2L_PRE >+/* 7501 */ MCD_OPC_CheckPredicate, 0, 113, 0, // Skip to: 7618 >+/* 7505 */ MCD_OPC_Decode, 137, 1, 84, // Opcode: LDCL_PRE >+/* 7509 */ MCD_OPC_FilterValue, 7, 105, 0, // Skip to: 7618 >+/* 7513 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 7516 */ MCD_OPC_FilterValue, 0, 86, 0, // Skip to: 7606 >+/* 7520 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 7523 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 7547 >+/* 7527 */ MCD_OPC_CheckPredicate, 4, 9, 0, // Skip to: 7540 >+/* 7531 */ MCD_OPC_CheckField, 28, 4, 15, 3, 0, // Skip to: 7540 >+/* 7537 */ MCD_OPC_Decode, 73, 87, // Opcode: CDP2 >+/* 7540 */ MCD_OPC_CheckPredicate, 4, 74, 0, // Skip to: 7618 >+/* 7544 */ MCD_OPC_Decode, 72, 88, // Opcode: CDP >+/* 7547 */ MCD_OPC_FilterValue, 1, 67, 0, // Skip to: 7618 >+/* 7551 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 7554 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 7580 >+/* 7558 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7572 >+/* 7562 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7572 >+/* 7568 */ MCD_OPC_Decode, 202, 1, 89, // Opcode: MCR2 >+/* 7572 */ MCD_OPC_CheckPredicate, 0, 42, 0, // Skip to: 7618 >+/* 7576 */ MCD_OPC_Decode, 201, 1, 90, // Opcode: MCR >+/* 7580 */ MCD_OPC_FilterValue, 1, 34, 0, // Skip to: 7618 >+/* 7584 */ MCD_OPC_CheckPredicate, 4, 10, 0, // Skip to: 7598 >+/* 7588 */ MCD_OPC_CheckField, 28, 4, 15, 4, 0, // Skip to: 7598 >+/* 7594 */ MCD_OPC_Decode, 231, 1, 91, // Opcode: MRC2 >+/* 7598 */ MCD_OPC_CheckPredicate, 0, 16, 0, // Skip to: 7618 >+/* 7602 */ MCD_OPC_Decode, 230, 1, 92, // Opcode: MRC >+/* 7606 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7618 >+/* 7610 */ MCD_OPC_CheckPredicate, 0, 4, 0, // Skip to: 7618 >+/* 7614 */ MCD_OPC_Decode, 201, 3, 93, // Opcode: SVC >+/* 7618 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableNEONData32[] = { >+/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 207, 30, // Skip to: 7894 >+/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 113, 5, // Skip to: 1407 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 126 >+/* 21 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 24 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 56 >+/* 29 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 32 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 44 >+/* 36 */ MCD_OPC_CheckPredicate, 15, 172, 56, // Skip to: 14548 >+/* 40 */ MCD_OPC_Decode, 173, 6, 94, // Opcode: VHADDsv8i8 >+/* 44 */ MCD_OPC_FilterValue, 1, 164, 56, // Skip to: 14548 >+/* 48 */ MCD_OPC_CheckPredicate, 15, 160, 56, // Skip to: 14548 >+/* 52 */ MCD_OPC_Decode, 168, 6, 95, // Opcode: VHADDsv16i8 >+/* 56 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 75 >+/* 61 */ MCD_OPC_CheckPredicate, 15, 147, 56, // Skip to: 14548 >+/* 65 */ MCD_OPC_CheckField, 6, 1, 0, 141, 56, // Skip to: 14548 >+/* 71 */ MCD_OPC_Decode, 191, 4, 96, // Opcode: VADDLsv8i16 >+/* 75 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 107 >+/* 80 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 83 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 95 >+/* 87 */ MCD_OPC_CheckPredicate, 15, 121, 56, // Skip to: 14548 >+/* 91 */ MCD_OPC_Decode, 179, 6, 94, // Opcode: VHADDuv8i8 >+/* 95 */ MCD_OPC_FilterValue, 1, 113, 56, // Skip to: 14548 >+/* 99 */ MCD_OPC_CheckPredicate, 15, 109, 56, // Skip to: 14548 >+/* 103 */ MCD_OPC_Decode, 174, 6, 95, // Opcode: VHADDuv16i8 >+/* 107 */ MCD_OPC_FilterValue, 231, 3, 100, 56, // Skip to: 14548 >+/* 112 */ MCD_OPC_CheckPredicate, 15, 96, 56, // Skip to: 14548 >+/* 116 */ MCD_OPC_CheckField, 6, 1, 0, 90, 56, // Skip to: 14548 >+/* 122 */ MCD_OPC_Decode, 194, 4, 96, // Opcode: VADDLuv8i16 >+/* 126 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 235 >+/* 130 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 133 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 165 >+/* 138 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 141 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 153 >+/* 145 */ MCD_OPC_CheckPredicate, 15, 63, 56, // Skip to: 14548 >+/* 149 */ MCD_OPC_Decode, 134, 13, 94, // Opcode: VRHADDsv8i8 >+/* 153 */ MCD_OPC_FilterValue, 1, 55, 56, // Skip to: 14548 >+/* 157 */ MCD_OPC_CheckPredicate, 15, 51, 56, // Skip to: 14548 >+/* 161 */ MCD_OPC_Decode, 129, 13, 95, // Opcode: VRHADDsv16i8 >+/* 165 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 184 >+/* 170 */ MCD_OPC_CheckPredicate, 15, 38, 56, // Skip to: 14548 >+/* 174 */ MCD_OPC_CheckField, 6, 1, 0, 32, 56, // Skip to: 14548 >+/* 180 */ MCD_OPC_Decode, 198, 4, 97, // Opcode: VADDWsv8i16 >+/* 184 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 216 >+/* 189 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 192 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 204 >+/* 196 */ MCD_OPC_CheckPredicate, 15, 12, 56, // Skip to: 14548 >+/* 200 */ MCD_OPC_Decode, 140, 13, 94, // Opcode: VRHADDuv8i8 >+/* 204 */ MCD_OPC_FilterValue, 1, 4, 56, // Skip to: 14548 >+/* 208 */ MCD_OPC_CheckPredicate, 15, 0, 56, // Skip to: 14548 >+/* 212 */ MCD_OPC_Decode, 135, 13, 95, // Opcode: VRHADDuv16i8 >+/* 216 */ MCD_OPC_FilterValue, 231, 3, 247, 55, // Skip to: 14548 >+/* 221 */ MCD_OPC_CheckPredicate, 15, 243, 55, // Skip to: 14548 >+/* 225 */ MCD_OPC_CheckField, 6, 1, 0, 237, 55, // Skip to: 14548 >+/* 231 */ MCD_OPC_Decode, 201, 4, 97, // Opcode: VADDWuv8i16 >+/* 235 */ MCD_OPC_FilterValue, 2, 105, 0, // Skip to: 344 >+/* 239 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 242 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 274 >+/* 247 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 250 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 262 >+/* 254 */ MCD_OPC_CheckPredicate, 15, 210, 55, // Skip to: 14548 >+/* 258 */ MCD_OPC_Decode, 185, 6, 94, // Opcode: VHSUBsv8i8 >+/* 262 */ MCD_OPC_FilterValue, 1, 202, 55, // Skip to: 14548 >+/* 266 */ MCD_OPC_CheckPredicate, 15, 198, 55, // Skip to: 14548 >+/* 270 */ MCD_OPC_Decode, 180, 6, 95, // Opcode: VHSUBsv16i8 >+/* 274 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 293 >+/* 279 */ MCD_OPC_CheckPredicate, 15, 185, 55, // Skip to: 14548 >+/* 283 */ MCD_OPC_CheckField, 6, 1, 0, 179, 55, // Skip to: 14548 >+/* 289 */ MCD_OPC_Decode, 139, 17, 96, // Opcode: VSUBLsv8i16 >+/* 293 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 325 >+/* 298 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 301 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 313 >+/* 305 */ MCD_OPC_CheckPredicate, 15, 159, 55, // Skip to: 14548 >+/* 309 */ MCD_OPC_Decode, 191, 6, 94, // Opcode: VHSUBuv8i8 >+/* 313 */ MCD_OPC_FilterValue, 1, 151, 55, // Skip to: 14548 >+/* 317 */ MCD_OPC_CheckPredicate, 15, 147, 55, // Skip to: 14548 >+/* 321 */ MCD_OPC_Decode, 186, 6, 95, // Opcode: VHSUBuv16i8 >+/* 325 */ MCD_OPC_FilterValue, 231, 3, 138, 55, // Skip to: 14548 >+/* 330 */ MCD_OPC_CheckPredicate, 15, 134, 55, // Skip to: 14548 >+/* 334 */ MCD_OPC_CheckField, 6, 1, 0, 128, 55, // Skip to: 14548 >+/* 340 */ MCD_OPC_Decode, 142, 17, 96, // Opcode: VSUBLuv8i16 >+/* 344 */ MCD_OPC_FilterValue, 3, 105, 0, // Skip to: 453 >+/* 348 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 351 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 383 >+/* 356 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 359 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 371 >+/* 363 */ MCD_OPC_CheckPredicate, 15, 101, 55, // Skip to: 14548 >+/* 367 */ MCD_OPC_Decode, 143, 5, 94, // Opcode: VCGTsv8i8 >+/* 371 */ MCD_OPC_FilterValue, 1, 93, 55, // Skip to: 14548 >+/* 375 */ MCD_OPC_CheckPredicate, 15, 89, 55, // Skip to: 14548 >+/* 379 */ MCD_OPC_Decode, 138, 5, 95, // Opcode: VCGTsv16i8 >+/* 383 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 402 >+/* 388 */ MCD_OPC_CheckPredicate, 15, 76, 55, // Skip to: 14548 >+/* 392 */ MCD_OPC_CheckField, 6, 1, 0, 70, 55, // Skip to: 14548 >+/* 398 */ MCD_OPC_Decode, 146, 17, 97, // Opcode: VSUBWsv8i16 >+/* 402 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 434 >+/* 407 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 410 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 422 >+/* 414 */ MCD_OPC_CheckPredicate, 15, 50, 55, // Skip to: 14548 >+/* 418 */ MCD_OPC_Decode, 149, 5, 94, // Opcode: VCGTuv8i8 >+/* 422 */ MCD_OPC_FilterValue, 1, 42, 55, // Skip to: 14548 >+/* 426 */ MCD_OPC_CheckPredicate, 15, 38, 55, // Skip to: 14548 >+/* 430 */ MCD_OPC_Decode, 144, 5, 95, // Opcode: VCGTuv16i8 >+/* 434 */ MCD_OPC_FilterValue, 231, 3, 29, 55, // Skip to: 14548 >+/* 439 */ MCD_OPC_CheckPredicate, 15, 25, 55, // Skip to: 14548 >+/* 443 */ MCD_OPC_CheckField, 6, 1, 0, 19, 55, // Skip to: 14548 >+/* 449 */ MCD_OPC_Decode, 149, 17, 97, // Opcode: VSUBWuv8i16 >+/* 453 */ MCD_OPC_FilterValue, 4, 105, 0, // Skip to: 562 >+/* 457 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 460 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 492 >+/* 465 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 468 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 480 >+/* 472 */ MCD_OPC_CheckPredicate, 15, 248, 54, // Skip to: 14548 >+/* 476 */ MCD_OPC_Decode, 134, 14, 98, // Opcode: VSHLsv8i8 >+/* 480 */ MCD_OPC_FilterValue, 1, 240, 54, // Skip to: 14548 >+/* 484 */ MCD_OPC_CheckPredicate, 15, 236, 54, // Skip to: 14548 >+/* 488 */ MCD_OPC_Decode, 255, 13, 99, // Opcode: VSHLsv16i8 >+/* 492 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 511 >+/* 497 */ MCD_OPC_CheckPredicate, 15, 223, 54, // Skip to: 14548 >+/* 501 */ MCD_OPC_CheckField, 6, 1, 0, 217, 54, // Skip to: 14548 >+/* 507 */ MCD_OPC_Decode, 188, 4, 100, // Opcode: VADDHNv8i8 >+/* 511 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 543 >+/* 516 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 519 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 531 >+/* 523 */ MCD_OPC_CheckPredicate, 15, 197, 54, // Skip to: 14548 >+/* 527 */ MCD_OPC_Decode, 142, 14, 98, // Opcode: VSHLuv8i8 >+/* 531 */ MCD_OPC_FilterValue, 1, 189, 54, // Skip to: 14548 >+/* 535 */ MCD_OPC_CheckPredicate, 15, 185, 54, // Skip to: 14548 >+/* 539 */ MCD_OPC_Decode, 135, 14, 99, // Opcode: VSHLuv16i8 >+/* 543 */ MCD_OPC_FilterValue, 231, 3, 176, 54, // Skip to: 14548 >+/* 548 */ MCD_OPC_CheckPredicate, 15, 172, 54, // Skip to: 14548 >+/* 552 */ MCD_OPC_CheckField, 6, 1, 0, 166, 54, // Skip to: 14548 >+/* 558 */ MCD_OPC_Decode, 238, 12, 100, // Opcode: VRADDHNv8i8 >+/* 562 */ MCD_OPC_FilterValue, 5, 105, 0, // Skip to: 671 >+/* 566 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 569 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 601 >+/* 574 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 577 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 589 >+/* 581 */ MCD_OPC_CheckPredicate, 15, 139, 54, // Skip to: 14548 >+/* 585 */ MCD_OPC_Decode, 174, 13, 98, // Opcode: VRSHLsv8i8 >+/* 589 */ MCD_OPC_FilterValue, 1, 131, 54, // Skip to: 14548 >+/* 593 */ MCD_OPC_CheckPredicate, 15, 127, 54, // Skip to: 14548 >+/* 597 */ MCD_OPC_Decode, 167, 13, 99, // Opcode: VRSHLsv16i8 >+/* 601 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 620 >+/* 606 */ MCD_OPC_CheckPredicate, 15, 114, 54, // Skip to: 14548 >+/* 610 */ MCD_OPC_CheckField, 6, 1, 0, 108, 54, // Skip to: 14548 >+/* 616 */ MCD_OPC_Decode, 135, 4, 101, // Opcode: VABALsv8i16 >+/* 620 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 652 >+/* 625 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 628 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 640 >+/* 632 */ MCD_OPC_CheckPredicate, 15, 88, 54, // Skip to: 14548 >+/* 636 */ MCD_OPC_Decode, 182, 13, 98, // Opcode: VRSHLuv8i8 >+/* 640 */ MCD_OPC_FilterValue, 1, 80, 54, // Skip to: 14548 >+/* 644 */ MCD_OPC_CheckPredicate, 15, 76, 54, // Skip to: 14548 >+/* 648 */ MCD_OPC_Decode, 175, 13, 99, // Opcode: VRSHLuv16i8 >+/* 652 */ MCD_OPC_FilterValue, 231, 3, 67, 54, // Skip to: 14548 >+/* 657 */ MCD_OPC_CheckPredicate, 15, 63, 54, // Skip to: 14548 >+/* 661 */ MCD_OPC_CheckField, 6, 1, 0, 57, 54, // Skip to: 14548 >+/* 667 */ MCD_OPC_Decode, 138, 4, 101, // Opcode: VABALuv8i16 >+/* 671 */ MCD_OPC_FilterValue, 6, 105, 0, // Skip to: 780 >+/* 675 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 678 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 710 >+/* 683 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 686 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 698 >+/* 690 */ MCD_OPC_CheckPredicate, 15, 30, 54, // Skip to: 14548 >+/* 694 */ MCD_OPC_Decode, 242, 9, 94, // Opcode: VMAXsv8i8 >+/* 698 */ MCD_OPC_FilterValue, 1, 22, 54, // Skip to: 14548 >+/* 702 */ MCD_OPC_CheckPredicate, 15, 18, 54, // Skip to: 14548 >+/* 706 */ MCD_OPC_Decode, 237, 9, 95, // Opcode: VMAXsv16i8 >+/* 710 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 729 >+/* 715 */ MCD_OPC_CheckPredicate, 15, 5, 54, // Skip to: 14548 >+/* 719 */ MCD_OPC_CheckField, 6, 1, 0, 255, 53, // Skip to: 14548 >+/* 725 */ MCD_OPC_Decode, 136, 17, 100, // Opcode: VSUBHNv8i8 >+/* 729 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 761 >+/* 734 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 737 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 749 >+/* 741 */ MCD_OPC_CheckPredicate, 15, 235, 53, // Skip to: 14548 >+/* 745 */ MCD_OPC_Decode, 248, 9, 94, // Opcode: VMAXuv8i8 >+/* 749 */ MCD_OPC_FilterValue, 1, 227, 53, // Skip to: 14548 >+/* 753 */ MCD_OPC_CheckPredicate, 15, 223, 53, // Skip to: 14548 >+/* 757 */ MCD_OPC_Decode, 243, 9, 95, // Opcode: VMAXuv16i8 >+/* 761 */ MCD_OPC_FilterValue, 231, 3, 214, 53, // Skip to: 14548 >+/* 766 */ MCD_OPC_CheckPredicate, 15, 210, 53, // Skip to: 14548 >+/* 770 */ MCD_OPC_CheckField, 6, 1, 0, 204, 53, // Skip to: 14548 >+/* 776 */ MCD_OPC_Decode, 226, 13, 100, // Opcode: VRSUBHNv8i8 >+/* 780 */ MCD_OPC_FilterValue, 7, 105, 0, // Skip to: 889 >+/* 784 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 787 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 819 >+/* 792 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 795 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 807 >+/* 799 */ MCD_OPC_CheckPredicate, 15, 177, 53, // Skip to: 14548 >+/* 803 */ MCD_OPC_Decode, 164, 4, 94, // Opcode: VABDsv8i8 >+/* 807 */ MCD_OPC_FilterValue, 1, 169, 53, // Skip to: 14548 >+/* 811 */ MCD_OPC_CheckPredicate, 15, 165, 53, // Skip to: 14548 >+/* 815 */ MCD_OPC_Decode, 159, 4, 95, // Opcode: VABDsv16i8 >+/* 819 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 838 >+/* 824 */ MCD_OPC_CheckPredicate, 15, 152, 53, // Skip to: 14548 >+/* 828 */ MCD_OPC_CheckField, 6, 1, 0, 146, 53, // Skip to: 14548 >+/* 834 */ MCD_OPC_Decode, 153, 4, 96, // Opcode: VABDLsv8i16 >+/* 838 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 870 >+/* 843 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 846 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 858 >+/* 850 */ MCD_OPC_CheckPredicate, 15, 126, 53, // Skip to: 14548 >+/* 854 */ MCD_OPC_Decode, 170, 4, 94, // Opcode: VABDuv8i8 >+/* 858 */ MCD_OPC_FilterValue, 1, 118, 53, // Skip to: 14548 >+/* 862 */ MCD_OPC_CheckPredicate, 15, 114, 53, // Skip to: 14548 >+/* 866 */ MCD_OPC_Decode, 165, 4, 95, // Opcode: VABDuv16i8 >+/* 870 */ MCD_OPC_FilterValue, 231, 3, 105, 53, // Skip to: 14548 >+/* 875 */ MCD_OPC_CheckPredicate, 15, 101, 53, // Skip to: 14548 >+/* 879 */ MCD_OPC_CheckField, 6, 1, 0, 95, 53, // Skip to: 14548 >+/* 885 */ MCD_OPC_Decode, 156, 4, 96, // Opcode: VABDLuv8i16 >+/* 889 */ MCD_OPC_FilterValue, 8, 105, 0, // Skip to: 998 >+/* 893 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 896 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 928 >+/* 901 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 904 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 916 >+/* 908 */ MCD_OPC_CheckPredicate, 15, 68, 53, // Skip to: 14548 >+/* 912 */ MCD_OPC_Decode, 211, 4, 94, // Opcode: VADDv8i8 >+/* 916 */ MCD_OPC_FilterValue, 1, 60, 53, // Skip to: 14548 >+/* 920 */ MCD_OPC_CheckPredicate, 15, 56, 53, // Skip to: 14548 >+/* 924 */ MCD_OPC_Decode, 204, 4, 95, // Opcode: VADDv16i8 >+/* 928 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 947 >+/* 933 */ MCD_OPC_CheckPredicate, 15, 43, 53, // Skip to: 14548 >+/* 937 */ MCD_OPC_CheckField, 6, 1, 0, 37, 53, // Skip to: 14548 >+/* 943 */ MCD_OPC_Decode, 146, 10, 101, // Opcode: VMLALsv8i16 >+/* 947 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 979 >+/* 952 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 >+/* 959 */ MCD_OPC_CheckPredicate, 15, 17, 53, // Skip to: 14548 >+/* 963 */ MCD_OPC_Decode, 159, 17, 94, // Opcode: VSUBv8i8 >+/* 967 */ MCD_OPC_FilterValue, 1, 9, 53, // Skip to: 14548 >+/* 971 */ MCD_OPC_CheckPredicate, 15, 5, 53, // Skip to: 14548 >+/* 975 */ MCD_OPC_Decode, 152, 17, 95, // Opcode: VSUBv16i8 >+/* 979 */ MCD_OPC_FilterValue, 231, 3, 252, 52, // Skip to: 14548 >+/* 984 */ MCD_OPC_CheckPredicate, 15, 248, 52, // Skip to: 14548 >+/* 988 */ MCD_OPC_CheckField, 6, 1, 0, 242, 52, // Skip to: 14548 >+/* 994 */ MCD_OPC_Decode, 149, 10, 101, // Opcode: VMLALuv8i16 >+/* 998 */ MCD_OPC_FilterValue, 9, 69, 0, // Skip to: 1071 >+/* 1002 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1005 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1038 >+/* 1009 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1012 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1025 >+/* 1017 */ MCD_OPC_CheckPredicate, 15, 215, 52, // Skip to: 14548 >+/* 1021 */ MCD_OPC_Decode, 164, 10, 102, // Opcode: VMLAv8i8 >+/* 1025 */ MCD_OPC_FilterValue, 230, 3, 206, 52, // Skip to: 14548 >+/* 1030 */ MCD_OPC_CheckPredicate, 15, 202, 52, // Skip to: 14548 >+/* 1034 */ MCD_OPC_Decode, 190, 10, 102, // Opcode: VMLSv8i8 >+/* 1038 */ MCD_OPC_FilterValue, 1, 194, 52, // Skip to: 14548 >+/* 1042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1045 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1058 >+/* 1050 */ MCD_OPC_CheckPredicate, 15, 182, 52, // Skip to: 14548 >+/* 1054 */ MCD_OPC_Decode, 159, 10, 103, // Opcode: VMLAv16i8 >+/* 1058 */ MCD_OPC_FilterValue, 230, 3, 173, 52, // Skip to: 14548 >+/* 1063 */ MCD_OPC_CheckPredicate, 15, 169, 52, // Skip to: 14548 >+/* 1067 */ MCD_OPC_Decode, 185, 10, 103, // Opcode: VMLSv16i8 >+/* 1071 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 1154 >+/* 1075 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1078 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 1097 >+/* 1083 */ MCD_OPC_CheckPredicate, 15, 149, 52, // Skip to: 14548 >+/* 1087 */ MCD_OPC_CheckField, 6, 1, 0, 143, 52, // Skip to: 14548 >+/* 1093 */ MCD_OPC_Decode, 198, 11, 94, // Opcode: VPMAXs8 >+/* 1097 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1116 >+/* 1102 */ MCD_OPC_CheckPredicate, 15, 130, 52, // Skip to: 14548 >+/* 1106 */ MCD_OPC_CheckField, 6, 1, 0, 124, 52, // Skip to: 14548 >+/* 1112 */ MCD_OPC_Decode, 172, 10, 101, // Opcode: VMLSLsv8i16 >+/* 1116 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 1135 >+/* 1121 */ MCD_OPC_CheckPredicate, 15, 111, 52, // Skip to: 14548 >+/* 1125 */ MCD_OPC_CheckField, 6, 1, 0, 105, 52, // Skip to: 14548 >+/* 1131 */ MCD_OPC_Decode, 201, 11, 94, // Opcode: VPMAXu8 >+/* 1135 */ MCD_OPC_FilterValue, 231, 3, 96, 52, // Skip to: 14548 >+/* 1140 */ MCD_OPC_CheckPredicate, 15, 92, 52, // Skip to: 14548 >+/* 1144 */ MCD_OPC_CheckField, 6, 1, 0, 86, 52, // Skip to: 14548 >+/* 1150 */ MCD_OPC_Decode, 175, 10, 101, // Opcode: VMLSLuv8i16 >+/* 1154 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 1199 >+/* 1158 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1161 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1180 >+/* 1166 */ MCD_OPC_CheckPredicate, 15, 66, 52, // Skip to: 14548 >+/* 1170 */ MCD_OPC_CheckField, 6, 1, 0, 60, 52, // Skip to: 14548 >+/* 1176 */ MCD_OPC_Decode, 244, 10, 96, // Opcode: VMULLsv8i16 >+/* 1180 */ MCD_OPC_FilterValue, 231, 3, 51, 52, // Skip to: 14548 >+/* 1185 */ MCD_OPC_CheckPredicate, 15, 47, 52, // Skip to: 14548 >+/* 1189 */ MCD_OPC_CheckField, 6, 1, 0, 41, 52, // Skip to: 14548 >+/* 1195 */ MCD_OPC_Decode, 247, 10, 96, // Opcode: VMULLuv8i16 >+/* 1199 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 1258 >+/* 1203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1206 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1239 >+/* 1210 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1213 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1226 >+/* 1218 */ MCD_OPC_CheckPredicate, 15, 14, 52, // Skip to: 14548 >+/* 1222 */ MCD_OPC_Decode, 202, 4, 94, // Opcode: VADDfd >+/* 1226 */ MCD_OPC_FilterValue, 230, 3, 5, 52, // Skip to: 14548 >+/* 1231 */ MCD_OPC_CheckPredicate, 15, 1, 52, // Skip to: 14548 >+/* 1235 */ MCD_OPC_Decode, 191, 11, 94, // Opcode: VPADDf >+/* 1239 */ MCD_OPC_FilterValue, 1, 249, 51, // Skip to: 14548 >+/* 1243 */ MCD_OPC_CheckPredicate, 15, 245, 51, // Skip to: 14548 >+/* 1247 */ MCD_OPC_CheckField, 23, 9, 228, 3, 238, 51, // Skip to: 14548 >+/* 1254 */ MCD_OPC_Decode, 203, 4, 95, // Opcode: VADDfq >+/* 1258 */ MCD_OPC_FilterValue, 14, 86, 0, // Skip to: 1348 >+/* 1262 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1265 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1297 >+/* 1270 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1273 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1285 >+/* 1277 */ MCD_OPC_CheckPredicate, 15, 211, 51, // Skip to: 14548 >+/* 1281 */ MCD_OPC_Decode, 226, 4, 94, // Opcode: VCEQfd >+/* 1285 */ MCD_OPC_FilterValue, 1, 203, 51, // Skip to: 14548 >+/* 1289 */ MCD_OPC_CheckPredicate, 15, 199, 51, // Skip to: 14548 >+/* 1293 */ MCD_OPC_Decode, 227, 4, 95, // Opcode: VCEQfq >+/* 1297 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1316 >+/* 1302 */ MCD_OPC_CheckPredicate, 15, 186, 51, // Skip to: 14548 >+/* 1306 */ MCD_OPC_CheckField, 6, 1, 0, 180, 51, // Skip to: 14548 >+/* 1312 */ MCD_OPC_Decode, 237, 10, 96, // Opcode: VMULLp8 >+/* 1316 */ MCD_OPC_FilterValue, 230, 3, 171, 51, // Skip to: 14548 >+/* 1321 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1324 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1336 >+/* 1328 */ MCD_OPC_CheckPredicate, 15, 160, 51, // Skip to: 14548 >+/* 1332 */ MCD_OPC_Decode, 242, 4, 94, // Opcode: VCGEfd >+/* 1336 */ MCD_OPC_FilterValue, 1, 152, 51, // Skip to: 14548 >+/* 1340 */ MCD_OPC_CheckPredicate, 15, 148, 51, // Skip to: 14548 >+/* 1344 */ MCD_OPC_Decode, 243, 4, 95, // Opcode: VCGEfq >+/* 1348 */ MCD_OPC_FilterValue, 15, 140, 51, // Skip to: 14548 >+/* 1352 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1355 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 1388 >+/* 1359 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1362 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 1375 >+/* 1367 */ MCD_OPC_CheckPredicate, 15, 121, 51, // Skip to: 14548 >+/* 1371 */ MCD_OPC_Decode, 235, 9, 94, // Opcode: VMAXfd >+/* 1375 */ MCD_OPC_FilterValue, 230, 3, 112, 51, // Skip to: 14548 >+/* 1380 */ MCD_OPC_CheckPredicate, 15, 108, 51, // Skip to: 14548 >+/* 1384 */ MCD_OPC_Decode, 195, 11, 94, // Opcode: VPMAXf >+/* 1388 */ MCD_OPC_FilterValue, 1, 100, 51, // Skip to: 14548 >+/* 1392 */ MCD_OPC_CheckPredicate, 15, 96, 51, // Skip to: 14548 >+/* 1396 */ MCD_OPC_CheckField, 23, 9, 228, 3, 89, 51, // Skip to: 14548 >+/* 1403 */ MCD_OPC_Decode, 236, 9, 95, // Opcode: VMAXfq >+/* 1407 */ MCD_OPC_FilterValue, 1, 38, 6, // Skip to: 2985 >+/* 1411 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1414 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 1549 >+/* 1418 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1421 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1453 >+/* 1426 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1429 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1441 >+/* 1433 */ MCD_OPC_CheckPredicate, 15, 55, 51, // Skip to: 14548 >+/* 1437 */ MCD_OPC_Decode, 170, 6, 94, // Opcode: VHADDsv4i16 >+/* 1441 */ MCD_OPC_FilterValue, 1, 47, 51, // Skip to: 14548 >+/* 1445 */ MCD_OPC_CheckPredicate, 15, 43, 51, // Skip to: 14548 >+/* 1449 */ MCD_OPC_Decode, 172, 6, 95, // Opcode: VHADDsv8i16 >+/* 1453 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1485 >+/* 1458 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1461 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1473 >+/* 1465 */ MCD_OPC_CheckPredicate, 15, 23, 51, // Skip to: 14548 >+/* 1469 */ MCD_OPC_Decode, 190, 4, 96, // Opcode: VADDLsv4i32 >+/* 1473 */ MCD_OPC_FilterValue, 1, 15, 51, // Skip to: 14548 >+/* 1477 */ MCD_OPC_CheckPredicate, 15, 11, 51, // Skip to: 14548 >+/* 1481 */ MCD_OPC_Decode, 156, 10, 104, // Opcode: VMLAslv4i16 >+/* 1485 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1517 >+/* 1490 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1493 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1505 >+/* 1497 */ MCD_OPC_CheckPredicate, 15, 247, 50, // Skip to: 14548 >+/* 1501 */ MCD_OPC_Decode, 176, 6, 94, // Opcode: VHADDuv4i16 >+/* 1505 */ MCD_OPC_FilterValue, 1, 239, 50, // Skip to: 14548 >+/* 1509 */ MCD_OPC_CheckPredicate, 15, 235, 50, // Skip to: 14548 >+/* 1513 */ MCD_OPC_Decode, 178, 6, 95, // Opcode: VHADDuv8i16 >+/* 1517 */ MCD_OPC_FilterValue, 231, 3, 226, 50, // Skip to: 14548 >+/* 1522 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1525 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1537 >+/* 1529 */ MCD_OPC_CheckPredicate, 15, 215, 50, // Skip to: 14548 >+/* 1533 */ MCD_OPC_Decode, 193, 4, 96, // Opcode: VADDLuv4i32 >+/* 1537 */ MCD_OPC_FilterValue, 1, 207, 50, // Skip to: 14548 >+/* 1541 */ MCD_OPC_CheckPredicate, 15, 203, 50, // Skip to: 14548 >+/* 1545 */ MCD_OPC_Decode, 158, 10, 105, // Opcode: VMLAslv8i16 >+/* 1549 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 1658 >+/* 1553 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1556 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1588 >+/* 1561 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1564 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1576 >+/* 1568 */ MCD_OPC_CheckPredicate, 15, 176, 50, // Skip to: 14548 >+/* 1572 */ MCD_OPC_Decode, 131, 13, 94, // Opcode: VRHADDsv4i16 >+/* 1576 */ MCD_OPC_FilterValue, 1, 168, 50, // Skip to: 14548 >+/* 1580 */ MCD_OPC_CheckPredicate, 15, 164, 50, // Skip to: 14548 >+/* 1584 */ MCD_OPC_Decode, 133, 13, 95, // Opcode: VRHADDsv8i16 >+/* 1588 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 1607 >+/* 1593 */ MCD_OPC_CheckPredicate, 15, 151, 50, // Skip to: 14548 >+/* 1597 */ MCD_OPC_CheckField, 6, 1, 0, 145, 50, // Skip to: 14548 >+/* 1603 */ MCD_OPC_Decode, 197, 4, 97, // Opcode: VADDWsv4i32 >+/* 1607 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1639 >+/* 1612 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1615 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1627 >+/* 1619 */ MCD_OPC_CheckPredicate, 15, 125, 50, // Skip to: 14548 >+/* 1623 */ MCD_OPC_Decode, 137, 13, 94, // Opcode: VRHADDuv4i16 >+/* 1627 */ MCD_OPC_FilterValue, 1, 117, 50, // Skip to: 14548 >+/* 1631 */ MCD_OPC_CheckPredicate, 15, 113, 50, // Skip to: 14548 >+/* 1635 */ MCD_OPC_Decode, 139, 13, 95, // Opcode: VRHADDuv8i16 >+/* 1639 */ MCD_OPC_FilterValue, 231, 3, 104, 50, // Skip to: 14548 >+/* 1644 */ MCD_OPC_CheckPredicate, 15, 100, 50, // Skip to: 14548 >+/* 1648 */ MCD_OPC_CheckField, 6, 1, 0, 94, 50, // Skip to: 14548 >+/* 1654 */ MCD_OPC_Decode, 200, 4, 97, // Opcode: VADDWuv4i32 >+/* 1658 */ MCD_OPC_FilterValue, 2, 131, 0, // Skip to: 1793 >+/* 1662 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1665 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1697 >+/* 1670 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1673 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1685 >+/* 1677 */ MCD_OPC_CheckPredicate, 15, 67, 50, // Skip to: 14548 >+/* 1681 */ MCD_OPC_Decode, 182, 6, 94, // Opcode: VHSUBsv4i16 >+/* 1685 */ MCD_OPC_FilterValue, 1, 59, 50, // Skip to: 14548 >+/* 1689 */ MCD_OPC_CheckPredicate, 15, 55, 50, // Skip to: 14548 >+/* 1693 */ MCD_OPC_Decode, 184, 6, 95, // Opcode: VHSUBsv8i16 >+/* 1697 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1729 >+/* 1702 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1705 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1717 >+/* 1709 */ MCD_OPC_CheckPredicate, 15, 35, 50, // Skip to: 14548 >+/* 1713 */ MCD_OPC_Decode, 138, 17, 96, // Opcode: VSUBLsv4i32 >+/* 1717 */ MCD_OPC_FilterValue, 1, 27, 50, // Skip to: 14548 >+/* 1721 */ MCD_OPC_CheckPredicate, 15, 23, 50, // Skip to: 14548 >+/* 1725 */ MCD_OPC_Decode, 141, 10, 106, // Opcode: VMLALslsv4i16 >+/* 1729 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1761 >+/* 1734 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1737 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1749 >+/* 1741 */ MCD_OPC_CheckPredicate, 15, 3, 50, // Skip to: 14548 >+/* 1745 */ MCD_OPC_Decode, 188, 6, 94, // Opcode: VHSUBuv4i16 >+/* 1749 */ MCD_OPC_FilterValue, 1, 251, 49, // Skip to: 14548 >+/* 1753 */ MCD_OPC_CheckPredicate, 15, 247, 49, // Skip to: 14548 >+/* 1757 */ MCD_OPC_Decode, 190, 6, 95, // Opcode: VHSUBuv8i16 >+/* 1761 */ MCD_OPC_FilterValue, 231, 3, 238, 49, // Skip to: 14548 >+/* 1766 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1769 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1781 >+/* 1773 */ MCD_OPC_CheckPredicate, 15, 227, 49, // Skip to: 14548 >+/* 1777 */ MCD_OPC_Decode, 141, 17, 96, // Opcode: VSUBLuv4i32 >+/* 1781 */ MCD_OPC_FilterValue, 1, 219, 49, // Skip to: 14548 >+/* 1785 */ MCD_OPC_CheckPredicate, 15, 215, 49, // Skip to: 14548 >+/* 1789 */ MCD_OPC_Decode, 143, 10, 106, // Opcode: VMLALsluv4i16 >+/* 1793 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 1915 >+/* 1797 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1800 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1832 >+/* 1805 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1808 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1820 >+/* 1812 */ MCD_OPC_CheckPredicate, 15, 188, 49, // Skip to: 14548 >+/* 1816 */ MCD_OPC_Decode, 140, 5, 94, // Opcode: VCGTsv4i16 >+/* 1820 */ MCD_OPC_FilterValue, 1, 180, 49, // Skip to: 14548 >+/* 1824 */ MCD_OPC_CheckPredicate, 15, 176, 49, // Skip to: 14548 >+/* 1828 */ MCD_OPC_Decode, 142, 5, 95, // Opcode: VCGTsv8i16 >+/* 1832 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1864 >+/* 1837 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1840 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1852 >+/* 1844 */ MCD_OPC_CheckPredicate, 15, 156, 49, // Skip to: 14548 >+/* 1848 */ MCD_OPC_Decode, 145, 17, 97, // Opcode: VSUBWsv4i32 >+/* 1852 */ MCD_OPC_FilterValue, 1, 148, 49, // Skip to: 14548 >+/* 1856 */ MCD_OPC_CheckPredicate, 15, 144, 49, // Skip to: 14548 >+/* 1860 */ MCD_OPC_Decode, 232, 11, 106, // Opcode: VQDMLALslv4i16 >+/* 1864 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 1896 >+/* 1869 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1872 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1884 >+/* 1876 */ MCD_OPC_CheckPredicate, 15, 124, 49, // Skip to: 14548 >+/* 1880 */ MCD_OPC_Decode, 146, 5, 94, // Opcode: VCGTuv4i16 >+/* 1884 */ MCD_OPC_FilterValue, 1, 116, 49, // Skip to: 14548 >+/* 1888 */ MCD_OPC_CheckPredicate, 15, 112, 49, // Skip to: 14548 >+/* 1892 */ MCD_OPC_Decode, 148, 5, 95, // Opcode: VCGTuv8i16 >+/* 1896 */ MCD_OPC_FilterValue, 231, 3, 103, 49, // Skip to: 14548 >+/* 1901 */ MCD_OPC_CheckPredicate, 15, 99, 49, // Skip to: 14548 >+/* 1905 */ MCD_OPC_CheckField, 6, 1, 0, 93, 49, // Skip to: 14548 >+/* 1911 */ MCD_OPC_Decode, 148, 17, 97, // Opcode: VSUBWuv4i32 >+/* 1915 */ MCD_OPC_FilterValue, 4, 131, 0, // Skip to: 2050 >+/* 1919 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1922 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 1954 >+/* 1927 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1930 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1942 >+/* 1934 */ MCD_OPC_CheckPredicate, 15, 66, 49, // Skip to: 14548 >+/* 1938 */ MCD_OPC_Decode, 131, 14, 98, // Opcode: VSHLsv4i16 >+/* 1942 */ MCD_OPC_FilterValue, 1, 58, 49, // Skip to: 14548 >+/* 1946 */ MCD_OPC_CheckPredicate, 15, 54, 49, // Skip to: 14548 >+/* 1950 */ MCD_OPC_Decode, 133, 14, 99, // Opcode: VSHLsv8i16 >+/* 1954 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 1986 >+/* 1959 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1962 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1974 >+/* 1966 */ MCD_OPC_CheckPredicate, 15, 34, 49, // Skip to: 14548 >+/* 1970 */ MCD_OPC_Decode, 187, 4, 100, // Opcode: VADDHNv4i16 >+/* 1974 */ MCD_OPC_FilterValue, 1, 26, 49, // Skip to: 14548 >+/* 1978 */ MCD_OPC_CheckPredicate, 15, 22, 49, // Skip to: 14548 >+/* 1982 */ MCD_OPC_Decode, 182, 10, 104, // Opcode: VMLSslv4i16 >+/* 1986 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2018 >+/* 1991 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1994 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2006 >+/* 1998 */ MCD_OPC_CheckPredicate, 15, 2, 49, // Skip to: 14548 >+/* 2002 */ MCD_OPC_Decode, 139, 14, 98, // Opcode: VSHLuv4i16 >+/* 2006 */ MCD_OPC_FilterValue, 1, 250, 48, // Skip to: 14548 >+/* 2010 */ MCD_OPC_CheckPredicate, 15, 246, 48, // Skip to: 14548 >+/* 2014 */ MCD_OPC_Decode, 141, 14, 99, // Opcode: VSHLuv8i16 >+/* 2018 */ MCD_OPC_FilterValue, 231, 3, 237, 48, // Skip to: 14548 >+/* 2023 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2026 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2038 >+/* 2030 */ MCD_OPC_CheckPredicate, 15, 226, 48, // Skip to: 14548 >+/* 2034 */ MCD_OPC_Decode, 237, 12, 100, // Opcode: VRADDHNv4i16 >+/* 2038 */ MCD_OPC_FilterValue, 1, 218, 48, // Skip to: 14548 >+/* 2042 */ MCD_OPC_CheckPredicate, 15, 214, 48, // Skip to: 14548 >+/* 2046 */ MCD_OPC_Decode, 184, 10, 105, // Opcode: VMLSslv8i16 >+/* 2050 */ MCD_OPC_FilterValue, 5, 105, 0, // Skip to: 2159 >+/* 2054 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2057 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2089 >+/* 2062 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2065 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2077 >+/* 2069 */ MCD_OPC_CheckPredicate, 15, 187, 48, // Skip to: 14548 >+/* 2073 */ MCD_OPC_Decode, 171, 13, 98, // Opcode: VRSHLsv4i16 >+/* 2077 */ MCD_OPC_FilterValue, 1, 179, 48, // Skip to: 14548 >+/* 2081 */ MCD_OPC_CheckPredicate, 15, 175, 48, // Skip to: 14548 >+/* 2085 */ MCD_OPC_Decode, 173, 13, 99, // Opcode: VRSHLsv8i16 >+/* 2089 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 2108 >+/* 2094 */ MCD_OPC_CheckPredicate, 15, 162, 48, // Skip to: 14548 >+/* 2098 */ MCD_OPC_CheckField, 6, 1, 0, 156, 48, // Skip to: 14548 >+/* 2104 */ MCD_OPC_Decode, 134, 4, 101, // Opcode: VABALsv4i32 >+/* 2108 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2140 >+/* 2113 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2116 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2128 >+/* 2120 */ MCD_OPC_CheckPredicate, 15, 136, 48, // Skip to: 14548 >+/* 2124 */ MCD_OPC_Decode, 179, 13, 98, // Opcode: VRSHLuv4i16 >+/* 2128 */ MCD_OPC_FilterValue, 1, 128, 48, // Skip to: 14548 >+/* 2132 */ MCD_OPC_CheckPredicate, 15, 124, 48, // Skip to: 14548 >+/* 2136 */ MCD_OPC_Decode, 181, 13, 99, // Opcode: VRSHLuv8i16 >+/* 2140 */ MCD_OPC_FilterValue, 231, 3, 115, 48, // Skip to: 14548 >+/* 2145 */ MCD_OPC_CheckPredicate, 15, 111, 48, // Skip to: 14548 >+/* 2149 */ MCD_OPC_CheckField, 6, 1, 0, 105, 48, // Skip to: 14548 >+/* 2155 */ MCD_OPC_Decode, 137, 4, 101, // Opcode: VABALuv4i32 >+/* 2159 */ MCD_OPC_FilterValue, 6, 131, 0, // Skip to: 2294 >+/* 2163 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2166 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2198 >+/* 2171 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2174 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2186 >+/* 2178 */ MCD_OPC_CheckPredicate, 15, 78, 48, // Skip to: 14548 >+/* 2182 */ MCD_OPC_Decode, 239, 9, 94, // Opcode: VMAXsv4i16 >+/* 2186 */ MCD_OPC_FilterValue, 1, 70, 48, // Skip to: 14548 >+/* 2190 */ MCD_OPC_CheckPredicate, 15, 66, 48, // Skip to: 14548 >+/* 2194 */ MCD_OPC_Decode, 241, 9, 95, // Opcode: VMAXsv8i16 >+/* 2198 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2230 >+/* 2203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2206 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2218 >+/* 2210 */ MCD_OPC_CheckPredicate, 15, 46, 48, // Skip to: 14548 >+/* 2214 */ MCD_OPC_Decode, 135, 17, 100, // Opcode: VSUBHNv4i16 >+/* 2218 */ MCD_OPC_FilterValue, 1, 38, 48, // Skip to: 14548 >+/* 2222 */ MCD_OPC_CheckPredicate, 15, 34, 48, // Skip to: 14548 >+/* 2226 */ MCD_OPC_Decode, 167, 10, 106, // Opcode: VMLSLslsv4i16 >+/* 2230 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2262 >+/* 2235 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2250 >+/* 2242 */ MCD_OPC_CheckPredicate, 15, 14, 48, // Skip to: 14548 >+/* 2246 */ MCD_OPC_Decode, 245, 9, 94, // Opcode: VMAXuv4i16 >+/* 2250 */ MCD_OPC_FilterValue, 1, 6, 48, // Skip to: 14548 >+/* 2254 */ MCD_OPC_CheckPredicate, 15, 2, 48, // Skip to: 14548 >+/* 2258 */ MCD_OPC_Decode, 247, 9, 95, // Opcode: VMAXuv8i16 >+/* 2262 */ MCD_OPC_FilterValue, 231, 3, 249, 47, // Skip to: 14548 >+/* 2267 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2270 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2282 >+/* 2274 */ MCD_OPC_CheckPredicate, 15, 238, 47, // Skip to: 14548 >+/* 2278 */ MCD_OPC_Decode, 225, 13, 100, // Opcode: VRSUBHNv4i16 >+/* 2282 */ MCD_OPC_FilterValue, 1, 230, 47, // Skip to: 14548 >+/* 2286 */ MCD_OPC_CheckPredicate, 15, 226, 47, // Skip to: 14548 >+/* 2290 */ MCD_OPC_Decode, 169, 10, 106, // Opcode: VMLSLsluv4i16 >+/* 2294 */ MCD_OPC_FilterValue, 7, 118, 0, // Skip to: 2416 >+/* 2298 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2301 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2333 >+/* 2306 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2309 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2321 >+/* 2313 */ MCD_OPC_CheckPredicate, 15, 199, 47, // Skip to: 14548 >+/* 2317 */ MCD_OPC_Decode, 161, 4, 94, // Opcode: VABDsv4i16 >+/* 2321 */ MCD_OPC_FilterValue, 1, 191, 47, // Skip to: 14548 >+/* 2325 */ MCD_OPC_CheckPredicate, 15, 187, 47, // Skip to: 14548 >+/* 2329 */ MCD_OPC_Decode, 163, 4, 95, // Opcode: VABDsv8i16 >+/* 2333 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2365 >+/* 2338 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2341 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2353 >+/* 2345 */ MCD_OPC_CheckPredicate, 15, 167, 47, // Skip to: 14548 >+/* 2349 */ MCD_OPC_Decode, 152, 4, 96, // Opcode: VABDLsv4i32 >+/* 2353 */ MCD_OPC_FilterValue, 1, 159, 47, // Skip to: 14548 >+/* 2357 */ MCD_OPC_CheckPredicate, 15, 155, 47, // Skip to: 14548 >+/* 2361 */ MCD_OPC_Decode, 236, 11, 106, // Opcode: VQDMLSLslv4i16 >+/* 2365 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2397 >+/* 2370 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2373 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2385 >+/* 2377 */ MCD_OPC_CheckPredicate, 15, 135, 47, // Skip to: 14548 >+/* 2381 */ MCD_OPC_Decode, 167, 4, 94, // Opcode: VABDuv4i16 >+/* 2385 */ MCD_OPC_FilterValue, 1, 127, 47, // Skip to: 14548 >+/* 2389 */ MCD_OPC_CheckPredicate, 15, 123, 47, // Skip to: 14548 >+/* 2393 */ MCD_OPC_Decode, 169, 4, 95, // Opcode: VABDuv8i16 >+/* 2397 */ MCD_OPC_FilterValue, 231, 3, 114, 47, // Skip to: 14548 >+/* 2402 */ MCD_OPC_CheckPredicate, 15, 110, 47, // Skip to: 14548 >+/* 2406 */ MCD_OPC_CheckField, 6, 1, 0, 104, 47, // Skip to: 14548 >+/* 2412 */ MCD_OPC_Decode, 155, 4, 96, // Opcode: VABDLuv4i32 >+/* 2416 */ MCD_OPC_FilterValue, 8, 131, 0, // Skip to: 2551 >+/* 2420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2423 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2455 >+/* 2428 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2431 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2443 >+/* 2435 */ MCD_OPC_CheckPredicate, 15, 77, 47, // Skip to: 14548 >+/* 2439 */ MCD_OPC_Decode, 208, 4, 94, // Opcode: VADDv4i16 >+/* 2443 */ MCD_OPC_FilterValue, 1, 69, 47, // Skip to: 14548 >+/* 2447 */ MCD_OPC_CheckPredicate, 15, 65, 47, // Skip to: 14548 >+/* 2451 */ MCD_OPC_Decode, 210, 4, 95, // Opcode: VADDv8i16 >+/* 2455 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2487 >+/* 2460 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2475 >+/* 2467 */ MCD_OPC_CheckPredicate, 15, 45, 47, // Skip to: 14548 >+/* 2471 */ MCD_OPC_Decode, 145, 10, 101, // Opcode: VMLALsv4i32 >+/* 2475 */ MCD_OPC_FilterValue, 1, 37, 47, // Skip to: 14548 >+/* 2479 */ MCD_OPC_CheckPredicate, 15, 33, 47, // Skip to: 14548 >+/* 2483 */ MCD_OPC_Decode, 128, 11, 107, // Opcode: VMULslv4i16 >+/* 2487 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 2519 >+/* 2492 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2495 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2507 >+/* 2499 */ MCD_OPC_CheckPredicate, 15, 13, 47, // Skip to: 14548 >+/* 2503 */ MCD_OPC_Decode, 156, 17, 94, // Opcode: VSUBv4i16 >+/* 2507 */ MCD_OPC_FilterValue, 1, 5, 47, // Skip to: 14548 >+/* 2511 */ MCD_OPC_CheckPredicate, 15, 1, 47, // Skip to: 14548 >+/* 2515 */ MCD_OPC_Decode, 158, 17, 95, // Opcode: VSUBv8i16 >+/* 2519 */ MCD_OPC_FilterValue, 231, 3, 248, 46, // Skip to: 14548 >+/* 2524 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2527 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2539 >+/* 2531 */ MCD_OPC_CheckPredicate, 15, 237, 46, // Skip to: 14548 >+/* 2535 */ MCD_OPC_Decode, 148, 10, 101, // Opcode: VMLALuv4i32 >+/* 2539 */ MCD_OPC_FilterValue, 1, 229, 46, // Skip to: 14548 >+/* 2543 */ MCD_OPC_CheckPredicate, 15, 225, 46, // Skip to: 14548 >+/* 2547 */ MCD_OPC_Decode, 130, 11, 108, // Opcode: VMULslv8i16 >+/* 2551 */ MCD_OPC_FilterValue, 9, 86, 0, // Skip to: 2641 >+/* 2555 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2558 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2590 >+/* 2563 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2566 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2578 >+/* 2570 */ MCD_OPC_CheckPredicate, 15, 198, 46, // Skip to: 14548 >+/* 2574 */ MCD_OPC_Decode, 161, 10, 102, // Opcode: VMLAv4i16 >+/* 2578 */ MCD_OPC_FilterValue, 1, 190, 46, // Skip to: 14548 >+/* 2582 */ MCD_OPC_CheckPredicate, 15, 186, 46, // Skip to: 14548 >+/* 2586 */ MCD_OPC_Decode, 163, 10, 103, // Opcode: VMLAv8i16 >+/* 2590 */ MCD_OPC_FilterValue, 229, 3, 14, 0, // Skip to: 2609 >+/* 2595 */ MCD_OPC_CheckPredicate, 15, 173, 46, // Skip to: 14548 >+/* 2599 */ MCD_OPC_CheckField, 6, 1, 0, 167, 46, // Skip to: 14548 >+/* 2605 */ MCD_OPC_Decode, 234, 11, 101, // Opcode: VQDMLALv4i32 >+/* 2609 */ MCD_OPC_FilterValue, 230, 3, 158, 46, // Skip to: 14548 >+/* 2614 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2617 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2629 >+/* 2621 */ MCD_OPC_CheckPredicate, 15, 147, 46, // Skip to: 14548 >+/* 2625 */ MCD_OPC_Decode, 187, 10, 102, // Opcode: VMLSv4i16 >+/* 2629 */ MCD_OPC_FilterValue, 1, 139, 46, // Skip to: 14548 >+/* 2633 */ MCD_OPC_CheckPredicate, 15, 135, 46, // Skip to: 14548 >+/* 2637 */ MCD_OPC_Decode, 189, 10, 103, // Opcode: VMLSv8i16 >+/* 2641 */ MCD_OPC_FilterValue, 10, 105, 0, // Skip to: 2750 >+/* 2645 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2648 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 2667 >+/* 2653 */ MCD_OPC_CheckPredicate, 15, 115, 46, // Skip to: 14548 >+/* 2657 */ MCD_OPC_CheckField, 6, 1, 0, 109, 46, // Skip to: 14548 >+/* 2663 */ MCD_OPC_Decode, 196, 11, 94, // Opcode: VPMAXs16 >+/* 2667 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2699 >+/* 2672 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2675 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2687 >+/* 2679 */ MCD_OPC_CheckPredicate, 15, 89, 46, // Skip to: 14548 >+/* 2683 */ MCD_OPC_Decode, 171, 10, 101, // Opcode: VMLSLsv4i32 >+/* 2687 */ MCD_OPC_FilterValue, 1, 81, 46, // Skip to: 14548 >+/* 2691 */ MCD_OPC_CheckPredicate, 15, 77, 46, // Skip to: 14548 >+/* 2695 */ MCD_OPC_Decode, 239, 10, 109, // Opcode: VMULLslsv4i16 >+/* 2699 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 2718 >+/* 2704 */ MCD_OPC_CheckPredicate, 15, 64, 46, // Skip to: 14548 >+/* 2708 */ MCD_OPC_CheckField, 6, 1, 0, 58, 46, // Skip to: 14548 >+/* 2714 */ MCD_OPC_Decode, 199, 11, 94, // Opcode: VPMAXu16 >+/* 2718 */ MCD_OPC_FilterValue, 231, 3, 49, 46, // Skip to: 14548 >+/* 2723 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2726 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2738 >+/* 2730 */ MCD_OPC_CheckPredicate, 15, 38, 46, // Skip to: 14548 >+/* 2734 */ MCD_OPC_Decode, 174, 10, 101, // Opcode: VMLSLuv4i32 >+/* 2738 */ MCD_OPC_FilterValue, 1, 30, 46, // Skip to: 14548 >+/* 2742 */ MCD_OPC_CheckPredicate, 15, 26, 46, // Skip to: 14548 >+/* 2746 */ MCD_OPC_Decode, 241, 10, 109, // Opcode: VMULLsluv4i16 >+/* 2750 */ MCD_OPC_FilterValue, 11, 99, 0, // Skip to: 2853 >+/* 2754 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2757 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 2789 >+/* 2762 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2765 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2777 >+/* 2769 */ MCD_OPC_CheckPredicate, 15, 255, 45, // Skip to: 14548 >+/* 2773 */ MCD_OPC_Decode, 244, 11, 94, // Opcode: VQDMULHv4i16 >+/* 2777 */ MCD_OPC_FilterValue, 1, 247, 45, // Skip to: 14548 >+/* 2781 */ MCD_OPC_CheckPredicate, 15, 243, 45, // Skip to: 14548 >+/* 2785 */ MCD_OPC_Decode, 246, 11, 95, // Opcode: VQDMULHv8i16 >+/* 2789 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 2821 >+/* 2794 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2797 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2809 >+/* 2801 */ MCD_OPC_CheckPredicate, 15, 223, 45, // Skip to: 14548 >+/* 2805 */ MCD_OPC_Decode, 238, 11, 101, // Opcode: VQDMLSLv4i32 >+/* 2809 */ MCD_OPC_FilterValue, 1, 215, 45, // Skip to: 14548 >+/* 2813 */ MCD_OPC_CheckPredicate, 15, 211, 45, // Skip to: 14548 >+/* 2817 */ MCD_OPC_Decode, 248, 11, 109, // Opcode: VQDMULLslv4i16 >+/* 2821 */ MCD_OPC_FilterValue, 230, 3, 202, 45, // Skip to: 14548 >+/* 2826 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2829 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2841 >+/* 2833 */ MCD_OPC_CheckPredicate, 15, 191, 45, // Skip to: 14548 >+/* 2837 */ MCD_OPC_Decode, 143, 12, 94, // Opcode: VQRDMULHv4i16 >+/* 2841 */ MCD_OPC_FilterValue, 1, 183, 45, // Skip to: 14548 >+/* 2845 */ MCD_OPC_CheckPredicate, 15, 179, 45, // Skip to: 14548 >+/* 2849 */ MCD_OPC_Decode, 145, 12, 95, // Opcode: VQRDMULHv8i16 >+/* 2853 */ MCD_OPC_FilterValue, 12, 69, 0, // Skip to: 2926 >+/* 2857 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2860 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 2893 >+/* 2864 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2867 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2880 >+/* 2872 */ MCD_OPC_CheckPredicate, 15, 152, 45, // Skip to: 14548 >+/* 2876 */ MCD_OPC_Decode, 243, 10, 96, // Opcode: VMULLsv4i32 >+/* 2880 */ MCD_OPC_FilterValue, 231, 3, 143, 45, // Skip to: 14548 >+/* 2885 */ MCD_OPC_CheckPredicate, 15, 139, 45, // Skip to: 14548 >+/* 2889 */ MCD_OPC_Decode, 246, 10, 96, // Opcode: VMULLuv4i32 >+/* 2893 */ MCD_OPC_FilterValue, 1, 131, 45, // Skip to: 14548 >+/* 2897 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2900 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2913 >+/* 2905 */ MCD_OPC_CheckPredicate, 15, 119, 45, // Skip to: 14548 >+/* 2909 */ MCD_OPC_Decode, 240, 11, 107, // Opcode: VQDMULHslv4i16 >+/* 2913 */ MCD_OPC_FilterValue, 231, 3, 110, 45, // Skip to: 14548 >+/* 2918 */ MCD_OPC_CheckPredicate, 15, 106, 45, // Skip to: 14548 >+/* 2922 */ MCD_OPC_Decode, 242, 11, 108, // Opcode: VQDMULHslv8i16 >+/* 2926 */ MCD_OPC_FilterValue, 13, 98, 45, // Skip to: 14548 >+/* 2930 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 2933 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2952 >+/* 2937 */ MCD_OPC_CheckPredicate, 15, 87, 45, // Skip to: 14548 >+/* 2941 */ MCD_OPC_CheckField, 23, 9, 229, 3, 80, 45, // Skip to: 14548 >+/* 2948 */ MCD_OPC_Decode, 250, 11, 96, // Opcode: VQDMULLv4i32 >+/* 2952 */ MCD_OPC_FilterValue, 1, 72, 45, // Skip to: 14548 >+/* 2956 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2959 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 2972 >+/* 2964 */ MCD_OPC_CheckPredicate, 15, 60, 45, // Skip to: 14548 >+/* 2968 */ MCD_OPC_Decode, 139, 12, 107, // Opcode: VQRDMULHslv4i16 >+/* 2972 */ MCD_OPC_FilterValue, 231, 3, 51, 45, // Skip to: 14548 >+/* 2977 */ MCD_OPC_CheckPredicate, 15, 47, 45, // Skip to: 14548 >+/* 2981 */ MCD_OPC_Decode, 141, 12, 108, // Opcode: VQRDMULHslv8i16 >+/* 2985 */ MCD_OPC_FilterValue, 2, 47, 7, // Skip to: 4828 >+/* 2989 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 2992 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 3127 >+/* 2996 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2999 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3031 >+/* 3004 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3007 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3019 >+/* 3011 */ MCD_OPC_CheckPredicate, 15, 13, 45, // Skip to: 14548 >+/* 3015 */ MCD_OPC_Decode, 169, 6, 94, // Opcode: VHADDsv2i32 >+/* 3019 */ MCD_OPC_FilterValue, 1, 5, 45, // Skip to: 14548 >+/* 3023 */ MCD_OPC_CheckPredicate, 15, 1, 45, // Skip to: 14548 >+/* 3027 */ MCD_OPC_Decode, 171, 6, 95, // Opcode: VHADDsv4i32 >+/* 3031 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3063 >+/* 3036 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3039 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3051 >+/* 3043 */ MCD_OPC_CheckPredicate, 15, 237, 44, // Skip to: 14548 >+/* 3047 */ MCD_OPC_Decode, 189, 4, 96, // Opcode: VADDLsv2i64 >+/* 3051 */ MCD_OPC_FilterValue, 1, 229, 44, // Skip to: 14548 >+/* 3055 */ MCD_OPC_CheckPredicate, 15, 225, 44, // Skip to: 14548 >+/* 3059 */ MCD_OPC_Decode, 155, 10, 110, // Opcode: VMLAslv2i32 >+/* 3063 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3095 >+/* 3068 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3071 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3083 >+/* 3075 */ MCD_OPC_CheckPredicate, 15, 205, 44, // Skip to: 14548 >+/* 3079 */ MCD_OPC_Decode, 175, 6, 94, // Opcode: VHADDuv2i32 >+/* 3083 */ MCD_OPC_FilterValue, 1, 197, 44, // Skip to: 14548 >+/* 3087 */ MCD_OPC_CheckPredicate, 15, 193, 44, // Skip to: 14548 >+/* 3091 */ MCD_OPC_Decode, 177, 6, 95, // Opcode: VHADDuv4i32 >+/* 3095 */ MCD_OPC_FilterValue, 231, 3, 184, 44, // Skip to: 14548 >+/* 3100 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3103 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3115 >+/* 3107 */ MCD_OPC_CheckPredicate, 15, 173, 44, // Skip to: 14548 >+/* 3111 */ MCD_OPC_Decode, 192, 4, 96, // Opcode: VADDLuv2i64 >+/* 3115 */ MCD_OPC_FilterValue, 1, 165, 44, // Skip to: 14548 >+/* 3119 */ MCD_OPC_CheckPredicate, 15, 161, 44, // Skip to: 14548 >+/* 3123 */ MCD_OPC_Decode, 157, 10, 111, // Opcode: VMLAslv4i32 >+/* 3127 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 3262 >+/* 3131 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3134 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3166 >+/* 3139 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3142 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3154 >+/* 3146 */ MCD_OPC_CheckPredicate, 15, 134, 44, // Skip to: 14548 >+/* 3150 */ MCD_OPC_Decode, 130, 13, 94, // Opcode: VRHADDsv2i32 >+/* 3154 */ MCD_OPC_FilterValue, 1, 126, 44, // Skip to: 14548 >+/* 3158 */ MCD_OPC_CheckPredicate, 15, 122, 44, // Skip to: 14548 >+/* 3162 */ MCD_OPC_Decode, 132, 13, 95, // Opcode: VRHADDsv4i32 >+/* 3166 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3198 >+/* 3171 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3174 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3186 >+/* 3178 */ MCD_OPC_CheckPredicate, 15, 102, 44, // Skip to: 14548 >+/* 3182 */ MCD_OPC_Decode, 196, 4, 97, // Opcode: VADDWsv2i64 >+/* 3186 */ MCD_OPC_FilterValue, 1, 94, 44, // Skip to: 14548 >+/* 3190 */ MCD_OPC_CheckPredicate, 15, 90, 44, // Skip to: 14548 >+/* 3194 */ MCD_OPC_Decode, 153, 10, 110, // Opcode: VMLAslfd >+/* 3198 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3230 >+/* 3203 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3206 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3218 >+/* 3210 */ MCD_OPC_CheckPredicate, 15, 70, 44, // Skip to: 14548 >+/* 3214 */ MCD_OPC_Decode, 136, 13, 94, // Opcode: VRHADDuv2i32 >+/* 3218 */ MCD_OPC_FilterValue, 1, 62, 44, // Skip to: 14548 >+/* 3222 */ MCD_OPC_CheckPredicate, 15, 58, 44, // Skip to: 14548 >+/* 3226 */ MCD_OPC_Decode, 138, 13, 95, // Opcode: VRHADDuv4i32 >+/* 3230 */ MCD_OPC_FilterValue, 231, 3, 49, 44, // Skip to: 14548 >+/* 3235 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3238 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3250 >+/* 3242 */ MCD_OPC_CheckPredicate, 15, 38, 44, // Skip to: 14548 >+/* 3246 */ MCD_OPC_Decode, 199, 4, 97, // Opcode: VADDWuv2i64 >+/* 3250 */ MCD_OPC_FilterValue, 1, 30, 44, // Skip to: 14548 >+/* 3254 */ MCD_OPC_CheckPredicate, 15, 26, 44, // Skip to: 14548 >+/* 3258 */ MCD_OPC_Decode, 154, 10, 111, // Opcode: VMLAslfq >+/* 3262 */ MCD_OPC_FilterValue, 2, 131, 0, // Skip to: 3397 >+/* 3266 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3269 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3301 >+/* 3274 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3277 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3289 >+/* 3281 */ MCD_OPC_CheckPredicate, 15, 255, 43, // Skip to: 14548 >+/* 3285 */ MCD_OPC_Decode, 181, 6, 94, // Opcode: VHSUBsv2i32 >+/* 3289 */ MCD_OPC_FilterValue, 1, 247, 43, // Skip to: 14548 >+/* 3293 */ MCD_OPC_CheckPredicate, 15, 243, 43, // Skip to: 14548 >+/* 3297 */ MCD_OPC_Decode, 183, 6, 95, // Opcode: VHSUBsv4i32 >+/* 3301 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3333 >+/* 3306 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3309 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3321 >+/* 3313 */ MCD_OPC_CheckPredicate, 15, 223, 43, // Skip to: 14548 >+/* 3317 */ MCD_OPC_Decode, 137, 17, 96, // Opcode: VSUBLsv2i64 >+/* 3321 */ MCD_OPC_FilterValue, 1, 215, 43, // Skip to: 14548 >+/* 3325 */ MCD_OPC_CheckPredicate, 15, 211, 43, // Skip to: 14548 >+/* 3329 */ MCD_OPC_Decode, 140, 10, 112, // Opcode: VMLALslsv2i32 >+/* 3333 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3365 >+/* 3338 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3341 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3353 >+/* 3345 */ MCD_OPC_CheckPredicate, 15, 191, 43, // Skip to: 14548 >+/* 3349 */ MCD_OPC_Decode, 187, 6, 94, // Opcode: VHSUBuv2i32 >+/* 3353 */ MCD_OPC_FilterValue, 1, 183, 43, // Skip to: 14548 >+/* 3357 */ MCD_OPC_CheckPredicate, 15, 179, 43, // Skip to: 14548 >+/* 3361 */ MCD_OPC_Decode, 189, 6, 95, // Opcode: VHSUBuv4i32 >+/* 3365 */ MCD_OPC_FilterValue, 231, 3, 170, 43, // Skip to: 14548 >+/* 3370 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3373 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3385 >+/* 3377 */ MCD_OPC_CheckPredicate, 15, 159, 43, // Skip to: 14548 >+/* 3381 */ MCD_OPC_Decode, 140, 17, 96, // Opcode: VSUBLuv2i64 >+/* 3385 */ MCD_OPC_FilterValue, 1, 151, 43, // Skip to: 14548 >+/* 3389 */ MCD_OPC_CheckPredicate, 15, 147, 43, // Skip to: 14548 >+/* 3393 */ MCD_OPC_Decode, 142, 10, 112, // Opcode: VMLALsluv2i32 >+/* 3397 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 3519 >+/* 3401 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3404 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3436 >+/* 3409 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3412 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3424 >+/* 3416 */ MCD_OPC_CheckPredicate, 15, 120, 43, // Skip to: 14548 >+/* 3420 */ MCD_OPC_Decode, 139, 5, 94, // Opcode: VCGTsv2i32 >+/* 3424 */ MCD_OPC_FilterValue, 1, 112, 43, // Skip to: 14548 >+/* 3428 */ MCD_OPC_CheckPredicate, 15, 108, 43, // Skip to: 14548 >+/* 3432 */ MCD_OPC_Decode, 141, 5, 95, // Opcode: VCGTsv4i32 >+/* 3436 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3468 >+/* 3441 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3444 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3456 >+/* 3448 */ MCD_OPC_CheckPredicate, 15, 88, 43, // Skip to: 14548 >+/* 3452 */ MCD_OPC_Decode, 144, 17, 97, // Opcode: VSUBWsv2i64 >+/* 3456 */ MCD_OPC_FilterValue, 1, 80, 43, // Skip to: 14548 >+/* 3460 */ MCD_OPC_CheckPredicate, 15, 76, 43, // Skip to: 14548 >+/* 3464 */ MCD_OPC_Decode, 231, 11, 112, // Opcode: VQDMLALslv2i32 >+/* 3468 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3500 >+/* 3473 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3476 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3488 >+/* 3480 */ MCD_OPC_CheckPredicate, 15, 56, 43, // Skip to: 14548 >+/* 3484 */ MCD_OPC_Decode, 145, 5, 94, // Opcode: VCGTuv2i32 >+/* 3488 */ MCD_OPC_FilterValue, 1, 48, 43, // Skip to: 14548 >+/* 3492 */ MCD_OPC_CheckPredicate, 15, 44, 43, // Skip to: 14548 >+/* 3496 */ MCD_OPC_Decode, 147, 5, 95, // Opcode: VCGTuv4i32 >+/* 3500 */ MCD_OPC_FilterValue, 231, 3, 35, 43, // Skip to: 14548 >+/* 3505 */ MCD_OPC_CheckPredicate, 15, 31, 43, // Skip to: 14548 >+/* 3509 */ MCD_OPC_CheckField, 6, 1, 0, 25, 43, // Skip to: 14548 >+/* 3515 */ MCD_OPC_Decode, 147, 17, 97, // Opcode: VSUBWuv2i64 >+/* 3519 */ MCD_OPC_FilterValue, 4, 131, 0, // Skip to: 3654 >+/* 3523 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3526 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3558 >+/* 3531 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3534 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3546 >+/* 3538 */ MCD_OPC_CheckPredicate, 15, 254, 42, // Skip to: 14548 >+/* 3542 */ MCD_OPC_Decode, 129, 14, 98, // Opcode: VSHLsv2i32 >+/* 3546 */ MCD_OPC_FilterValue, 1, 246, 42, // Skip to: 14548 >+/* 3550 */ MCD_OPC_CheckPredicate, 15, 242, 42, // Skip to: 14548 >+/* 3554 */ MCD_OPC_Decode, 132, 14, 99, // Opcode: VSHLsv4i32 >+/* 3558 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3590 >+/* 3563 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3566 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3578 >+/* 3570 */ MCD_OPC_CheckPredicate, 15, 222, 42, // Skip to: 14548 >+/* 3574 */ MCD_OPC_Decode, 186, 4, 100, // Opcode: VADDHNv2i32 >+/* 3578 */ MCD_OPC_FilterValue, 1, 214, 42, // Skip to: 14548 >+/* 3582 */ MCD_OPC_CheckPredicate, 15, 210, 42, // Skip to: 14548 >+/* 3586 */ MCD_OPC_Decode, 181, 10, 110, // Opcode: VMLSslv2i32 >+/* 3590 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3622 >+/* 3595 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3598 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3610 >+/* 3602 */ MCD_OPC_CheckPredicate, 15, 190, 42, // Skip to: 14548 >+/* 3606 */ MCD_OPC_Decode, 137, 14, 98, // Opcode: VSHLuv2i32 >+/* 3610 */ MCD_OPC_FilterValue, 1, 182, 42, // Skip to: 14548 >+/* 3614 */ MCD_OPC_CheckPredicate, 15, 178, 42, // Skip to: 14548 >+/* 3618 */ MCD_OPC_Decode, 140, 14, 99, // Opcode: VSHLuv4i32 >+/* 3622 */ MCD_OPC_FilterValue, 231, 3, 169, 42, // Skip to: 14548 >+/* 3627 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3630 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3642 >+/* 3634 */ MCD_OPC_CheckPredicate, 15, 158, 42, // Skip to: 14548 >+/* 3638 */ MCD_OPC_Decode, 236, 12, 100, // Opcode: VRADDHNv2i32 >+/* 3642 */ MCD_OPC_FilterValue, 1, 150, 42, // Skip to: 14548 >+/* 3646 */ MCD_OPC_CheckPredicate, 15, 146, 42, // Skip to: 14548 >+/* 3650 */ MCD_OPC_Decode, 183, 10, 111, // Opcode: VMLSslv4i32 >+/* 3654 */ MCD_OPC_FilterValue, 5, 131, 0, // Skip to: 3789 >+/* 3658 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3661 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3693 >+/* 3666 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3669 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3681 >+/* 3673 */ MCD_OPC_CheckPredicate, 15, 119, 42, // Skip to: 14548 >+/* 3677 */ MCD_OPC_Decode, 169, 13, 98, // Opcode: VRSHLsv2i32 >+/* 3681 */ MCD_OPC_FilterValue, 1, 111, 42, // Skip to: 14548 >+/* 3685 */ MCD_OPC_CheckPredicate, 15, 107, 42, // Skip to: 14548 >+/* 3689 */ MCD_OPC_Decode, 172, 13, 99, // Opcode: VRSHLsv4i32 >+/* 3693 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3725 >+/* 3698 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3701 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3713 >+/* 3705 */ MCD_OPC_CheckPredicate, 15, 87, 42, // Skip to: 14548 >+/* 3709 */ MCD_OPC_Decode, 133, 4, 101, // Opcode: VABALsv2i64 >+/* 3713 */ MCD_OPC_FilterValue, 1, 79, 42, // Skip to: 14548 >+/* 3717 */ MCD_OPC_CheckPredicate, 15, 75, 42, // Skip to: 14548 >+/* 3721 */ MCD_OPC_Decode, 179, 10, 110, // Opcode: VMLSslfd >+/* 3725 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3757 >+/* 3730 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3733 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3745 >+/* 3737 */ MCD_OPC_CheckPredicate, 15, 55, 42, // Skip to: 14548 >+/* 3741 */ MCD_OPC_Decode, 177, 13, 98, // Opcode: VRSHLuv2i32 >+/* 3745 */ MCD_OPC_FilterValue, 1, 47, 42, // Skip to: 14548 >+/* 3749 */ MCD_OPC_CheckPredicate, 15, 43, 42, // Skip to: 14548 >+/* 3753 */ MCD_OPC_Decode, 180, 13, 99, // Opcode: VRSHLuv4i32 >+/* 3757 */ MCD_OPC_FilterValue, 231, 3, 34, 42, // Skip to: 14548 >+/* 3762 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3765 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3777 >+/* 3769 */ MCD_OPC_CheckPredicate, 15, 23, 42, // Skip to: 14548 >+/* 3773 */ MCD_OPC_Decode, 136, 4, 101, // Opcode: VABALuv2i64 >+/* 3777 */ MCD_OPC_FilterValue, 1, 15, 42, // Skip to: 14548 >+/* 3781 */ MCD_OPC_CheckPredicate, 15, 11, 42, // Skip to: 14548 >+/* 3785 */ MCD_OPC_Decode, 180, 10, 111, // Opcode: VMLSslfq >+/* 3789 */ MCD_OPC_FilterValue, 6, 131, 0, // Skip to: 3924 >+/* 3793 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3796 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3828 >+/* 3801 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3804 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3816 >+/* 3808 */ MCD_OPC_CheckPredicate, 15, 240, 41, // Skip to: 14548 >+/* 3812 */ MCD_OPC_Decode, 238, 9, 94, // Opcode: VMAXsv2i32 >+/* 3816 */ MCD_OPC_FilterValue, 1, 232, 41, // Skip to: 14548 >+/* 3820 */ MCD_OPC_CheckPredicate, 15, 228, 41, // Skip to: 14548 >+/* 3824 */ MCD_OPC_Decode, 240, 9, 95, // Opcode: VMAXsv4i32 >+/* 3828 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3860 >+/* 3833 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3836 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3848 >+/* 3840 */ MCD_OPC_CheckPredicate, 15, 208, 41, // Skip to: 14548 >+/* 3844 */ MCD_OPC_Decode, 134, 17, 100, // Opcode: VSUBHNv2i32 >+/* 3848 */ MCD_OPC_FilterValue, 1, 200, 41, // Skip to: 14548 >+/* 3852 */ MCD_OPC_CheckPredicate, 15, 196, 41, // Skip to: 14548 >+/* 3856 */ MCD_OPC_Decode, 166, 10, 112, // Opcode: VMLSLslsv2i32 >+/* 3860 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 3892 >+/* 3865 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3868 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3880 >+/* 3872 */ MCD_OPC_CheckPredicate, 15, 176, 41, // Skip to: 14548 >+/* 3876 */ MCD_OPC_Decode, 244, 9, 94, // Opcode: VMAXuv2i32 >+/* 3880 */ MCD_OPC_FilterValue, 1, 168, 41, // Skip to: 14548 >+/* 3884 */ MCD_OPC_CheckPredicate, 15, 164, 41, // Skip to: 14548 >+/* 3888 */ MCD_OPC_Decode, 246, 9, 95, // Opcode: VMAXuv4i32 >+/* 3892 */ MCD_OPC_FilterValue, 231, 3, 155, 41, // Skip to: 14548 >+/* 3897 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3900 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3912 >+/* 3904 */ MCD_OPC_CheckPredicate, 15, 144, 41, // Skip to: 14548 >+/* 3908 */ MCD_OPC_Decode, 224, 13, 100, // Opcode: VRSUBHNv2i32 >+/* 3912 */ MCD_OPC_FilterValue, 1, 136, 41, // Skip to: 14548 >+/* 3916 */ MCD_OPC_CheckPredicate, 15, 132, 41, // Skip to: 14548 >+/* 3920 */ MCD_OPC_Decode, 168, 10, 112, // Opcode: VMLSLsluv2i32 >+/* 3924 */ MCD_OPC_FilterValue, 7, 118, 0, // Skip to: 4046 >+/* 3928 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3931 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 3963 >+/* 3936 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3939 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3951 >+/* 3943 */ MCD_OPC_CheckPredicate, 15, 105, 41, // Skip to: 14548 >+/* 3947 */ MCD_OPC_Decode, 160, 4, 94, // Opcode: VABDsv2i32 >+/* 3951 */ MCD_OPC_FilterValue, 1, 97, 41, // Skip to: 14548 >+/* 3955 */ MCD_OPC_CheckPredicate, 15, 93, 41, // Skip to: 14548 >+/* 3959 */ MCD_OPC_Decode, 162, 4, 95, // Opcode: VABDsv4i32 >+/* 3963 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 3995 >+/* 3968 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3971 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3983 >+/* 3975 */ MCD_OPC_CheckPredicate, 15, 73, 41, // Skip to: 14548 >+/* 3979 */ MCD_OPC_Decode, 151, 4, 96, // Opcode: VABDLsv2i64 >+/* 3983 */ MCD_OPC_FilterValue, 1, 65, 41, // Skip to: 14548 >+/* 3987 */ MCD_OPC_CheckPredicate, 15, 61, 41, // Skip to: 14548 >+/* 3991 */ MCD_OPC_Decode, 235, 11, 112, // Opcode: VQDMLSLslv2i32 >+/* 3995 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4027 >+/* 4000 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4003 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4015 >+/* 4007 */ MCD_OPC_CheckPredicate, 15, 41, 41, // Skip to: 14548 >+/* 4011 */ MCD_OPC_Decode, 166, 4, 94, // Opcode: VABDuv2i32 >+/* 4015 */ MCD_OPC_FilterValue, 1, 33, 41, // Skip to: 14548 >+/* 4019 */ MCD_OPC_CheckPredicate, 15, 29, 41, // Skip to: 14548 >+/* 4023 */ MCD_OPC_Decode, 168, 4, 95, // Opcode: VABDuv4i32 >+/* 4027 */ MCD_OPC_FilterValue, 231, 3, 20, 41, // Skip to: 14548 >+/* 4032 */ MCD_OPC_CheckPredicate, 15, 16, 41, // Skip to: 14548 >+/* 4036 */ MCD_OPC_CheckField, 6, 1, 0, 10, 41, // Skip to: 14548 >+/* 4042 */ MCD_OPC_Decode, 154, 4, 96, // Opcode: VABDLuv2i64 >+/* 4046 */ MCD_OPC_FilterValue, 8, 131, 0, // Skip to: 4181 >+/* 4050 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4053 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4085 >+/* 4058 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4061 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4073 >+/* 4065 */ MCD_OPC_CheckPredicate, 15, 239, 40, // Skip to: 14548 >+/* 4069 */ MCD_OPC_Decode, 206, 4, 94, // Opcode: VADDv2i32 >+/* 4073 */ MCD_OPC_FilterValue, 1, 231, 40, // Skip to: 14548 >+/* 4077 */ MCD_OPC_CheckPredicate, 15, 227, 40, // Skip to: 14548 >+/* 4081 */ MCD_OPC_Decode, 209, 4, 95, // Opcode: VADDv4i32 >+/* 4085 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4117 >+/* 4090 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4105 >+/* 4097 */ MCD_OPC_CheckPredicate, 15, 207, 40, // Skip to: 14548 >+/* 4101 */ MCD_OPC_Decode, 144, 10, 101, // Opcode: VMLALsv2i64 >+/* 4105 */ MCD_OPC_FilterValue, 1, 199, 40, // Skip to: 14548 >+/* 4109 */ MCD_OPC_CheckPredicate, 15, 195, 40, // Skip to: 14548 >+/* 4113 */ MCD_OPC_Decode, 255, 10, 113, // Opcode: VMULslv2i32 >+/* 4117 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4149 >+/* 4122 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4125 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4137 >+/* 4129 */ MCD_OPC_CheckPredicate, 15, 175, 40, // Skip to: 14548 >+/* 4133 */ MCD_OPC_Decode, 154, 17, 94, // Opcode: VSUBv2i32 >+/* 4137 */ MCD_OPC_FilterValue, 1, 167, 40, // Skip to: 14548 >+/* 4141 */ MCD_OPC_CheckPredicate, 15, 163, 40, // Skip to: 14548 >+/* 4145 */ MCD_OPC_Decode, 157, 17, 95, // Opcode: VSUBv4i32 >+/* 4149 */ MCD_OPC_FilterValue, 231, 3, 154, 40, // Skip to: 14548 >+/* 4154 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4157 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4169 >+/* 4161 */ MCD_OPC_CheckPredicate, 15, 143, 40, // Skip to: 14548 >+/* 4165 */ MCD_OPC_Decode, 147, 10, 101, // Opcode: VMLALuv2i64 >+/* 4169 */ MCD_OPC_FilterValue, 1, 135, 40, // Skip to: 14548 >+/* 4173 */ MCD_OPC_CheckPredicate, 15, 131, 40, // Skip to: 14548 >+/* 4177 */ MCD_OPC_Decode, 129, 11, 114, // Opcode: VMULslv4i32 >+/* 4181 */ MCD_OPC_FilterValue, 9, 118, 0, // Skip to: 4303 >+/* 4185 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4188 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4220 >+/* 4193 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4196 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4208 >+/* 4200 */ MCD_OPC_CheckPredicate, 15, 104, 40, // Skip to: 14548 >+/* 4204 */ MCD_OPC_Decode, 160, 10, 102, // Opcode: VMLAv2i32 >+/* 4208 */ MCD_OPC_FilterValue, 1, 96, 40, // Skip to: 14548 >+/* 4212 */ MCD_OPC_CheckPredicate, 15, 92, 40, // Skip to: 14548 >+/* 4216 */ MCD_OPC_Decode, 162, 10, 103, // Opcode: VMLAv4i32 >+/* 4220 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4252 >+/* 4225 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4228 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4240 >+/* 4232 */ MCD_OPC_CheckPredicate, 15, 72, 40, // Skip to: 14548 >+/* 4236 */ MCD_OPC_Decode, 233, 11, 101, // Opcode: VQDMLALv2i64 >+/* 4240 */ MCD_OPC_FilterValue, 1, 64, 40, // Skip to: 14548 >+/* 4244 */ MCD_OPC_CheckPredicate, 15, 60, 40, // Skip to: 14548 >+/* 4248 */ MCD_OPC_Decode, 253, 10, 113, // Opcode: VMULslfd >+/* 4252 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4284 >+/* 4257 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4260 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4272 >+/* 4264 */ MCD_OPC_CheckPredicate, 15, 40, 40, // Skip to: 14548 >+/* 4268 */ MCD_OPC_Decode, 186, 10, 102, // Opcode: VMLSv2i32 >+/* 4272 */ MCD_OPC_FilterValue, 1, 32, 40, // Skip to: 14548 >+/* 4276 */ MCD_OPC_CheckPredicate, 15, 28, 40, // Skip to: 14548 >+/* 4280 */ MCD_OPC_Decode, 188, 10, 103, // Opcode: VMLSv4i32 >+/* 4284 */ MCD_OPC_FilterValue, 231, 3, 19, 40, // Skip to: 14548 >+/* 4289 */ MCD_OPC_CheckPredicate, 15, 15, 40, // Skip to: 14548 >+/* 4293 */ MCD_OPC_CheckField, 6, 1, 1, 9, 40, // Skip to: 14548 >+/* 4299 */ MCD_OPC_Decode, 254, 10, 114, // Opcode: VMULslfq >+/* 4303 */ MCD_OPC_FilterValue, 10, 105, 0, // Skip to: 4412 >+/* 4307 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4310 */ MCD_OPC_FilterValue, 228, 3, 14, 0, // Skip to: 4329 >+/* 4315 */ MCD_OPC_CheckPredicate, 15, 245, 39, // Skip to: 14548 >+/* 4319 */ MCD_OPC_CheckField, 6, 1, 0, 239, 39, // Skip to: 14548 >+/* 4325 */ MCD_OPC_Decode, 197, 11, 94, // Opcode: VPMAXs32 >+/* 4329 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4361 >+/* 4334 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4337 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4349 >+/* 4341 */ MCD_OPC_CheckPredicate, 15, 219, 39, // Skip to: 14548 >+/* 4345 */ MCD_OPC_Decode, 170, 10, 101, // Opcode: VMLSLsv2i64 >+/* 4349 */ MCD_OPC_FilterValue, 1, 211, 39, // Skip to: 14548 >+/* 4353 */ MCD_OPC_CheckPredicate, 15, 207, 39, // Skip to: 14548 >+/* 4357 */ MCD_OPC_Decode, 238, 10, 115, // Opcode: VMULLslsv2i32 >+/* 4361 */ MCD_OPC_FilterValue, 230, 3, 14, 0, // Skip to: 4380 >+/* 4366 */ MCD_OPC_CheckPredicate, 15, 194, 39, // Skip to: 14548 >+/* 4370 */ MCD_OPC_CheckField, 6, 1, 0, 188, 39, // Skip to: 14548 >+/* 4376 */ MCD_OPC_Decode, 200, 11, 94, // Opcode: VPMAXu32 >+/* 4380 */ MCD_OPC_FilterValue, 231, 3, 179, 39, // Skip to: 14548 >+/* 4385 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4400 >+/* 4392 */ MCD_OPC_CheckPredicate, 15, 168, 39, // Skip to: 14548 >+/* 4396 */ MCD_OPC_Decode, 173, 10, 101, // Opcode: VMLSLuv2i64 >+/* 4400 */ MCD_OPC_FilterValue, 1, 160, 39, // Skip to: 14548 >+/* 4404 */ MCD_OPC_CheckPredicate, 15, 156, 39, // Skip to: 14548 >+/* 4408 */ MCD_OPC_Decode, 240, 10, 115, // Opcode: VMULLsluv2i32 >+/* 4412 */ MCD_OPC_FilterValue, 11, 99, 0, // Skip to: 4515 >+/* 4416 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4419 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4451 >+/* 4424 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4427 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4439 >+/* 4431 */ MCD_OPC_CheckPredicate, 15, 129, 39, // Skip to: 14548 >+/* 4435 */ MCD_OPC_Decode, 243, 11, 94, // Opcode: VQDMULHv2i32 >+/* 4439 */ MCD_OPC_FilterValue, 1, 121, 39, // Skip to: 14548 >+/* 4443 */ MCD_OPC_CheckPredicate, 15, 117, 39, // Skip to: 14548 >+/* 4447 */ MCD_OPC_Decode, 245, 11, 95, // Opcode: VQDMULHv4i32 >+/* 4451 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4483 >+/* 4456 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4459 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4471 >+/* 4463 */ MCD_OPC_CheckPredicate, 15, 97, 39, // Skip to: 14548 >+/* 4467 */ MCD_OPC_Decode, 237, 11, 101, // Opcode: VQDMLSLv2i64 >+/* 4471 */ MCD_OPC_FilterValue, 1, 89, 39, // Skip to: 14548 >+/* 4475 */ MCD_OPC_CheckPredicate, 15, 85, 39, // Skip to: 14548 >+/* 4479 */ MCD_OPC_Decode, 247, 11, 115, // Opcode: VQDMULLslv2i32 >+/* 4483 */ MCD_OPC_FilterValue, 230, 3, 76, 39, // Skip to: 14548 >+/* 4488 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4491 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4503 >+/* 4495 */ MCD_OPC_CheckPredicate, 15, 65, 39, // Skip to: 14548 >+/* 4499 */ MCD_OPC_Decode, 142, 12, 94, // Opcode: VQRDMULHv2i32 >+/* 4503 */ MCD_OPC_FilterValue, 1, 57, 39, // Skip to: 14548 >+/* 4507 */ MCD_OPC_CheckPredicate, 15, 53, 39, // Skip to: 14548 >+/* 4511 */ MCD_OPC_Decode, 144, 12, 95, // Opcode: VQRDMULHv4i32 >+/* 4515 */ MCD_OPC_FilterValue, 12, 69, 0, // Skip to: 4588 >+/* 4519 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4522 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4555 >+/* 4526 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4529 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4542 >+/* 4534 */ MCD_OPC_CheckPredicate, 15, 26, 39, // Skip to: 14548 >+/* 4538 */ MCD_OPC_Decode, 242, 10, 96, // Opcode: VMULLsv2i64 >+/* 4542 */ MCD_OPC_FilterValue, 231, 3, 17, 39, // Skip to: 14548 >+/* 4547 */ MCD_OPC_CheckPredicate, 15, 13, 39, // Skip to: 14548 >+/* 4551 */ MCD_OPC_Decode, 245, 10, 96, // Opcode: VMULLuv2i64 >+/* 4555 */ MCD_OPC_FilterValue, 1, 5, 39, // Skip to: 14548 >+/* 4559 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4562 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4575 >+/* 4567 */ MCD_OPC_CheckPredicate, 15, 249, 38, // Skip to: 14548 >+/* 4571 */ MCD_OPC_Decode, 239, 11, 113, // Opcode: VQDMULHslv2i32 >+/* 4575 */ MCD_OPC_FilterValue, 231, 3, 240, 38, // Skip to: 14548 >+/* 4580 */ MCD_OPC_CheckPredicate, 15, 236, 38, // Skip to: 14548 >+/* 4584 */ MCD_OPC_Decode, 241, 11, 114, // Opcode: VQDMULHslv4i32 >+/* 4588 */ MCD_OPC_FilterValue, 13, 118, 0, // Skip to: 4710 >+/* 4592 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4595 */ MCD_OPC_FilterValue, 228, 3, 27, 0, // Skip to: 4627 >+/* 4600 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4603 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4615 >+/* 4607 */ MCD_OPC_CheckPredicate, 15, 209, 38, // Skip to: 14548 >+/* 4611 */ MCD_OPC_Decode, 150, 17, 94, // Opcode: VSUBfd >+/* 4615 */ MCD_OPC_FilterValue, 1, 201, 38, // Skip to: 14548 >+/* 4619 */ MCD_OPC_CheckPredicate, 15, 197, 38, // Skip to: 14548 >+/* 4623 */ MCD_OPC_Decode, 151, 17, 95, // Opcode: VSUBfq >+/* 4627 */ MCD_OPC_FilterValue, 229, 3, 27, 0, // Skip to: 4659 >+/* 4632 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4635 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4647 >+/* 4639 */ MCD_OPC_CheckPredicate, 15, 177, 38, // Skip to: 14548 >+/* 4643 */ MCD_OPC_Decode, 249, 11, 96, // Opcode: VQDMULLv2i64 >+/* 4647 */ MCD_OPC_FilterValue, 1, 169, 38, // Skip to: 14548 >+/* 4651 */ MCD_OPC_CheckPredicate, 15, 165, 38, // Skip to: 14548 >+/* 4655 */ MCD_OPC_Decode, 138, 12, 113, // Opcode: VQRDMULHslv2i32 >+/* 4659 */ MCD_OPC_FilterValue, 230, 3, 27, 0, // Skip to: 4691 >+/* 4664 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4679 >+/* 4671 */ MCD_OPC_CheckPredicate, 15, 145, 38, // Skip to: 14548 >+/* 4675 */ MCD_OPC_Decode, 157, 4, 94, // Opcode: VABDfd >+/* 4679 */ MCD_OPC_FilterValue, 1, 137, 38, // Skip to: 14548 >+/* 4683 */ MCD_OPC_CheckPredicate, 15, 133, 38, // Skip to: 14548 >+/* 4687 */ MCD_OPC_Decode, 158, 4, 95, // Opcode: VABDfq >+/* 4691 */ MCD_OPC_FilterValue, 231, 3, 124, 38, // Skip to: 14548 >+/* 4696 */ MCD_OPC_CheckPredicate, 15, 120, 38, // Skip to: 14548 >+/* 4700 */ MCD_OPC_CheckField, 6, 1, 1, 114, 38, // Skip to: 14548 >+/* 4706 */ MCD_OPC_Decode, 140, 12, 114, // Opcode: VQRDMULHslv4i32 >+/* 4710 */ MCD_OPC_FilterValue, 14, 55, 0, // Skip to: 4769 >+/* 4714 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4717 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4750 >+/* 4721 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4724 */ MCD_OPC_FilterValue, 229, 3, 8, 0, // Skip to: 4737 >+/* 4729 */ MCD_OPC_CheckPredicate, 16, 87, 38, // Skip to: 14548 >+/* 4733 */ MCD_OPC_Decode, 236, 10, 96, // Opcode: VMULLp64 >+/* 4737 */ MCD_OPC_FilterValue, 230, 3, 78, 38, // Skip to: 14548 >+/* 4742 */ MCD_OPC_CheckPredicate, 15, 74, 38, // Skip to: 14548 >+/* 4746 */ MCD_OPC_Decode, 136, 5, 94, // Opcode: VCGTfd >+/* 4750 */ MCD_OPC_FilterValue, 1, 66, 38, // Skip to: 14548 >+/* 4754 */ MCD_OPC_CheckPredicate, 15, 62, 38, // Skip to: 14548 >+/* 4758 */ MCD_OPC_CheckField, 23, 9, 230, 3, 55, 38, // Skip to: 14548 >+/* 4765 */ MCD_OPC_Decode, 137, 5, 95, // Opcode: VCGTfq >+/* 4769 */ MCD_OPC_FilterValue, 15, 47, 38, // Skip to: 14548 >+/* 4773 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4776 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 4809 >+/* 4780 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4783 */ MCD_OPC_FilterValue, 228, 3, 8, 0, // Skip to: 4796 >+/* 4788 */ MCD_OPC_CheckPredicate, 15, 28, 38, // Skip to: 14548 >+/* 4792 */ MCD_OPC_Decode, 253, 9, 94, // Opcode: VMINfd >+/* 4796 */ MCD_OPC_FilterValue, 230, 3, 19, 38, // Skip to: 14548 >+/* 4801 */ MCD_OPC_CheckPredicate, 15, 15, 38, // Skip to: 14548 >+/* 4805 */ MCD_OPC_Decode, 202, 11, 94, // Opcode: VPMINf >+/* 4809 */ MCD_OPC_FilterValue, 1, 7, 38, // Skip to: 14548 >+/* 4813 */ MCD_OPC_CheckPredicate, 15, 3, 38, // Skip to: 14548 >+/* 4817 */ MCD_OPC_CheckField, 23, 9, 228, 3, 252, 37, // Skip to: 14548 >+/* 4824 */ MCD_OPC_Decode, 254, 9, 95, // Opcode: VMINfq >+/* 4828 */ MCD_OPC_FilterValue, 3, 244, 37, // Skip to: 14548 >+/* 4832 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4835 */ MCD_OPC_FilterValue, 228, 3, 96, 0, // Skip to: 4936 >+/* 4840 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 4843 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 4874 >+/* 4847 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4850 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4862 >+/* 4854 */ MCD_OPC_CheckPredicate, 15, 218, 37, // Skip to: 14548 >+/* 4858 */ MCD_OPC_Decode, 128, 14, 98, // Opcode: VSHLsv1i64 >+/* 4862 */ MCD_OPC_FilterValue, 1, 210, 37, // Skip to: 14548 >+/* 4866 */ MCD_OPC_CheckPredicate, 15, 206, 37, // Skip to: 14548 >+/* 4870 */ MCD_OPC_Decode, 130, 14, 99, // Opcode: VSHLsv2i64 >+/* 4874 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 4905 >+/* 4878 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4881 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4893 >+/* 4885 */ MCD_OPC_CheckPredicate, 15, 187, 37, // Skip to: 14548 >+/* 4889 */ MCD_OPC_Decode, 168, 13, 98, // Opcode: VRSHLsv1i64 >+/* 4893 */ MCD_OPC_FilterValue, 1, 179, 37, // Skip to: 14548 >+/* 4897 */ MCD_OPC_CheckPredicate, 15, 175, 37, // Skip to: 14548 >+/* 4901 */ MCD_OPC_Decode, 170, 13, 99, // Opcode: VRSHLsv2i64 >+/* 4905 */ MCD_OPC_FilterValue, 8, 167, 37, // Skip to: 14548 >+/* 4909 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4912 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4924 >+/* 4916 */ MCD_OPC_CheckPredicate, 15, 156, 37, // Skip to: 14548 >+/* 4920 */ MCD_OPC_Decode, 205, 4, 94, // Opcode: VADDv1i64 >+/* 4924 */ MCD_OPC_FilterValue, 1, 148, 37, // Skip to: 14548 >+/* 4928 */ MCD_OPC_CheckPredicate, 15, 144, 37, // Skip to: 14548 >+/* 4932 */ MCD_OPC_Decode, 207, 4, 95, // Opcode: VADDv2i64 >+/* 4936 */ MCD_OPC_FilterValue, 229, 3, 104, 0, // Skip to: 5045 >+/* 4941 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4944 */ MCD_OPC_FilterValue, 0, 43, 0, // Skip to: 4991 >+/* 4948 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 4951 */ MCD_OPC_FilterValue, 0, 121, 37, // Skip to: 14548 >+/* 4955 */ MCD_OPC_CheckPredicate, 15, 10, 0, // Skip to: 4969 >+/* 4959 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, // Skip to: 4969 >+/* 4965 */ MCD_OPC_Decode, 145, 6, 116, // Opcode: VEXTd32 >+/* 4969 */ MCD_OPC_CheckPredicate, 15, 10, 0, // Skip to: 4983 >+/* 4973 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, // Skip to: 4983 >+/* 4979 */ MCD_OPC_Decode, 144, 6, 117, // Opcode: VEXTd16 >+/* 4983 */ MCD_OPC_CheckPredicate, 15, 89, 37, // Skip to: 14548 >+/* 4987 */ MCD_OPC_Decode, 146, 6, 118, // Opcode: VEXTd8 >+/* 4991 */ MCD_OPC_FilterValue, 1, 81, 37, // Skip to: 14548 >+/* 4995 */ MCD_OPC_CheckPredicate, 15, 10, 0, // Skip to: 5009 >+/* 4999 */ MCD_OPC_CheckField, 8, 3, 0, 4, 0, // Skip to: 5009 >+/* 5005 */ MCD_OPC_Decode, 149, 6, 119, // Opcode: VEXTq64 >+/* 5009 */ MCD_OPC_CheckPredicate, 15, 10, 0, // Skip to: 5023 >+/* 5013 */ MCD_OPC_CheckField, 8, 2, 0, 4, 0, // Skip to: 5023 >+/* 5019 */ MCD_OPC_Decode, 148, 6, 120, // Opcode: VEXTq32 >+/* 5023 */ MCD_OPC_CheckPredicate, 15, 10, 0, // Skip to: 5037 >+/* 5027 */ MCD_OPC_CheckField, 8, 1, 0, 4, 0, // Skip to: 5037 >+/* 5033 */ MCD_OPC_Decode, 147, 6, 121, // Opcode: VEXTq16 >+/* 5037 */ MCD_OPC_CheckPredicate, 15, 35, 37, // Skip to: 14548 >+/* 5041 */ MCD_OPC_Decode, 150, 6, 122, // Opcode: VEXTq8 >+/* 5045 */ MCD_OPC_FilterValue, 230, 3, 96, 0, // Skip to: 5146 >+/* 5050 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 5053 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 5084 >+/* 5057 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5060 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5072 >+/* 5064 */ MCD_OPC_CheckPredicate, 15, 8, 37, // Skip to: 14548 >+/* 5068 */ MCD_OPC_Decode, 136, 14, 98, // Opcode: VSHLuv1i64 >+/* 5072 */ MCD_OPC_FilterValue, 1, 0, 37, // Skip to: 14548 >+/* 5076 */ MCD_OPC_CheckPredicate, 15, 252, 36, // Skip to: 14548 >+/* 5080 */ MCD_OPC_Decode, 138, 14, 99, // Opcode: VSHLuv2i64 >+/* 5084 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 5115 >+/* 5088 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5091 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5103 >+/* 5095 */ MCD_OPC_CheckPredicate, 15, 233, 36, // Skip to: 14548 >+/* 5099 */ MCD_OPC_Decode, 176, 13, 98, // Opcode: VRSHLuv1i64 >+/* 5103 */ MCD_OPC_FilterValue, 1, 225, 36, // Skip to: 14548 >+/* 5107 */ MCD_OPC_CheckPredicate, 15, 221, 36, // Skip to: 14548 >+/* 5111 */ MCD_OPC_Decode, 178, 13, 99, // Opcode: VRSHLuv2i64 >+/* 5115 */ MCD_OPC_FilterValue, 8, 213, 36, // Skip to: 14548 >+/* 5119 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5122 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5134 >+/* 5126 */ MCD_OPC_CheckPredicate, 15, 202, 36, // Skip to: 14548 >+/* 5130 */ MCD_OPC_Decode, 153, 17, 94, // Opcode: VSUBv1i64 >+/* 5134 */ MCD_OPC_FilterValue, 1, 194, 36, // Skip to: 14548 >+/* 5138 */ MCD_OPC_CheckPredicate, 15, 190, 36, // Skip to: 14548 >+/* 5142 */ MCD_OPC_Decode, 155, 17, 95, // Opcode: VSUBv2i64 >+/* 5146 */ MCD_OPC_FilterValue, 231, 3, 181, 36, // Skip to: 14548 >+/* 5151 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 5154 */ MCD_OPC_FilterValue, 0, 170, 1, // Skip to: 5584 >+/* 5158 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5161 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 5216 >+/* 5165 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5168 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5180 >+/* 5172 */ MCD_OPC_CheckPredicate, 15, 156, 36, // Skip to: 14548 >+/* 5176 */ MCD_OPC_Decode, 253, 12, 123, // Opcode: VREV64d8 >+/* 5180 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5192 >+/* 5184 */ MCD_OPC_CheckPredicate, 15, 144, 36, // Skip to: 14548 >+/* 5188 */ MCD_OPC_Decode, 128, 13, 124, // Opcode: VREV64q8 >+/* 5192 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5204 >+/* 5196 */ MCD_OPC_CheckPredicate, 15, 132, 36, // Skip to: 14548 >+/* 5200 */ MCD_OPC_Decode, 248, 12, 123, // Opcode: VREV32d8 >+/* 5204 */ MCD_OPC_FilterValue, 3, 124, 36, // Skip to: 14548 >+/* 5208 */ MCD_OPC_CheckPredicate, 15, 120, 36, // Skip to: 14548 >+/* 5212 */ MCD_OPC_Decode, 250, 12, 124, // Opcode: VREV32q8 >+/* 5216 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 5271 >+/* 5220 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5223 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5235 >+/* 5227 */ MCD_OPC_CheckPredicate, 15, 101, 36, // Skip to: 14548 >+/* 5231 */ MCD_OPC_Decode, 157, 5, 123, // Opcode: VCGTzv8i8 >+/* 5235 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5247 >+/* 5239 */ MCD_OPC_CheckPredicate, 15, 89, 36, // Skip to: 14548 >+/* 5243 */ MCD_OPC_Decode, 150, 5, 124, // Opcode: VCGTzv16i8 >+/* 5247 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5259 >+/* 5251 */ MCD_OPC_CheckPredicate, 15, 77, 36, // Skip to: 14548 >+/* 5255 */ MCD_OPC_Decode, 135, 5, 123, // Opcode: VCGEzv8i8 >+/* 5259 */ MCD_OPC_FilterValue, 3, 69, 36, // Skip to: 14548 >+/* 5263 */ MCD_OPC_CheckPredicate, 15, 65, 36, // Skip to: 14548 >+/* 5267 */ MCD_OPC_Decode, 128, 5, 124, // Opcode: VCGEzv16i8 >+/* 5271 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 5326 >+/* 5275 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5278 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5290 >+/* 5282 */ MCD_OPC_CheckPredicate, 15, 46, 36, // Skip to: 14548 >+/* 5286 */ MCD_OPC_Decode, 160, 17, 125, // Opcode: VSWPd >+/* 5290 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5302 >+/* 5294 */ MCD_OPC_CheckPredicate, 15, 34, 36, // Skip to: 14548 >+/* 5298 */ MCD_OPC_Decode, 161, 17, 126, // Opcode: VSWPq >+/* 5302 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5314 >+/* 5306 */ MCD_OPC_CheckPredicate, 15, 22, 36, // Skip to: 14548 >+/* 5310 */ MCD_OPC_Decode, 192, 17, 125, // Opcode: VTRNd8 >+/* 5314 */ MCD_OPC_FilterValue, 3, 14, 36, // Skip to: 14548 >+/* 5318 */ MCD_OPC_CheckPredicate, 15, 10, 36, // Skip to: 14548 >+/* 5322 */ MCD_OPC_Decode, 195, 17, 126, // Opcode: VTRNq8 >+/* 5326 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 5381 >+/* 5330 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5345 >+/* 5337 */ MCD_OPC_CheckPredicate, 15, 247, 35, // Skip to: 14548 >+/* 5341 */ MCD_OPC_Decode, 251, 12, 123, // Opcode: VREV64d16 >+/* 5345 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5357 >+/* 5349 */ MCD_OPC_CheckPredicate, 15, 235, 35, // Skip to: 14548 >+/* 5353 */ MCD_OPC_Decode, 254, 12, 124, // Opcode: VREV64q16 >+/* 5357 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5369 >+/* 5361 */ MCD_OPC_CheckPredicate, 15, 223, 35, // Skip to: 14548 >+/* 5365 */ MCD_OPC_Decode, 247, 12, 123, // Opcode: VREV32d16 >+/* 5369 */ MCD_OPC_FilterValue, 3, 215, 35, // Skip to: 14548 >+/* 5373 */ MCD_OPC_CheckPredicate, 15, 211, 35, // Skip to: 14548 >+/* 5377 */ MCD_OPC_Decode, 249, 12, 124, // Opcode: VREV32q16 >+/* 5381 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 5436 >+/* 5385 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5388 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5400 >+/* 5392 */ MCD_OPC_CheckPredicate, 15, 192, 35, // Skip to: 14548 >+/* 5396 */ MCD_OPC_Decode, 154, 5, 123, // Opcode: VCGTzv4i16 >+/* 5400 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5412 >+/* 5404 */ MCD_OPC_CheckPredicate, 15, 180, 35, // Skip to: 14548 >+/* 5408 */ MCD_OPC_Decode, 156, 5, 124, // Opcode: VCGTzv8i16 >+/* 5412 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5424 >+/* 5416 */ MCD_OPC_CheckPredicate, 15, 168, 35, // Skip to: 14548 >+/* 5420 */ MCD_OPC_Decode, 132, 5, 123, // Opcode: VCGEzv4i16 >+/* 5424 */ MCD_OPC_FilterValue, 3, 160, 35, // Skip to: 14548 >+/* 5428 */ MCD_OPC_CheckPredicate, 15, 156, 35, // Skip to: 14548 >+/* 5432 */ MCD_OPC_Decode, 134, 5, 124, // Opcode: VCGEzv8i16 >+/* 5436 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 5467 >+/* 5440 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5443 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5455 >+/* 5447 */ MCD_OPC_CheckPredicate, 15, 137, 35, // Skip to: 14548 >+/* 5451 */ MCD_OPC_Decode, 190, 17, 125, // Opcode: VTRNd16 >+/* 5455 */ MCD_OPC_FilterValue, 3, 129, 35, // Skip to: 14548 >+/* 5459 */ MCD_OPC_CheckPredicate, 15, 125, 35, // Skip to: 14548 >+/* 5463 */ MCD_OPC_Decode, 193, 17, 126, // Opcode: VTRNq16 >+/* 5467 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 5498 >+/* 5471 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5474 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5486 >+/* 5478 */ MCD_OPC_CheckPredicate, 15, 106, 35, // Skip to: 14548 >+/* 5482 */ MCD_OPC_Decode, 252, 12, 123, // Opcode: VREV64d32 >+/* 5486 */ MCD_OPC_FilterValue, 1, 98, 35, // Skip to: 14548 >+/* 5490 */ MCD_OPC_CheckPredicate, 15, 94, 35, // Skip to: 14548 >+/* 5494 */ MCD_OPC_Decode, 255, 12, 124, // Opcode: VREV64q32 >+/* 5498 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 5553 >+/* 5502 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5505 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5517 >+/* 5509 */ MCD_OPC_CheckPredicate, 15, 75, 35, // Skip to: 14548 >+/* 5513 */ MCD_OPC_Decode, 152, 5, 123, // Opcode: VCGTzv2i32 >+/* 5517 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5529 >+/* 5521 */ MCD_OPC_CheckPredicate, 15, 63, 35, // Skip to: 14548 >+/* 5525 */ MCD_OPC_Decode, 155, 5, 124, // Opcode: VCGTzv4i32 >+/* 5529 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5541 >+/* 5533 */ MCD_OPC_CheckPredicate, 15, 51, 35, // Skip to: 14548 >+/* 5537 */ MCD_OPC_Decode, 130, 5, 123, // Opcode: VCGEzv2i32 >+/* 5541 */ MCD_OPC_FilterValue, 3, 43, 35, // Skip to: 14548 >+/* 5545 */ MCD_OPC_CheckPredicate, 15, 39, 35, // Skip to: 14548 >+/* 5549 */ MCD_OPC_Decode, 133, 5, 124, // Opcode: VCGEzv4i32 >+/* 5553 */ MCD_OPC_FilterValue, 10, 31, 35, // Skip to: 14548 >+/* 5557 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5560 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5572 >+/* 5564 */ MCD_OPC_CheckPredicate, 15, 20, 35, // Skip to: 14548 >+/* 5568 */ MCD_OPC_Decode, 191, 17, 125, // Opcode: VTRNd32 >+/* 5572 */ MCD_OPC_FilterValue, 3, 12, 35, // Skip to: 14548 >+/* 5576 */ MCD_OPC_CheckPredicate, 15, 8, 35, // Skip to: 14548 >+/* 5580 */ MCD_OPC_Decode, 194, 17, 126, // Opcode: VTRNq32 >+/* 5584 */ MCD_OPC_FilterValue, 1, 84, 1, // Skip to: 5928 >+/* 5588 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5591 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5622 >+/* 5595 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5598 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5610 >+/* 5602 */ MCD_OPC_CheckPredicate, 15, 238, 34, // Skip to: 14548 >+/* 5606 */ MCD_OPC_Decode, 245, 12, 123, // Opcode: VREV16d8 >+/* 5610 */ MCD_OPC_FilterValue, 1, 230, 34, // Skip to: 14548 >+/* 5614 */ MCD_OPC_CheckPredicate, 15, 226, 34, // Skip to: 14548 >+/* 5618 */ MCD_OPC_Decode, 246, 12, 124, // Opcode: VREV16q8 >+/* 5622 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 5677 >+/* 5626 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5629 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5641 >+/* 5633 */ MCD_OPC_CheckPredicate, 15, 207, 34, // Skip to: 14548 >+/* 5637 */ MCD_OPC_Decode, 241, 4, 123, // Opcode: VCEQzv8i8 >+/* 5641 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5653 >+/* 5645 */ MCD_OPC_CheckPredicate, 15, 195, 34, // Skip to: 14548 >+/* 5649 */ MCD_OPC_Decode, 234, 4, 124, // Opcode: VCEQzv16i8 >+/* 5653 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5665 >+/* 5657 */ MCD_OPC_CheckPredicate, 15, 183, 34, // Skip to: 14548 >+/* 5661 */ MCD_OPC_Decode, 165, 5, 123, // Opcode: VCLEzv8i8 >+/* 5665 */ MCD_OPC_FilterValue, 3, 175, 34, // Skip to: 14548 >+/* 5669 */ MCD_OPC_CheckPredicate, 15, 171, 34, // Skip to: 14548 >+/* 5673 */ MCD_OPC_Decode, 158, 5, 124, // Opcode: VCLEzv16i8 >+/* 5677 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 5732 >+/* 5681 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5684 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5696 >+/* 5688 */ MCD_OPC_CheckPredicate, 15, 152, 34, // Skip to: 14548 >+/* 5692 */ MCD_OPC_Decode, 209, 17, 125, // Opcode: VUZPd8 >+/* 5696 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5708 >+/* 5700 */ MCD_OPC_CheckPredicate, 15, 140, 34, // Skip to: 14548 >+/* 5704 */ MCD_OPC_Decode, 212, 17, 126, // Opcode: VUZPq8 >+/* 5708 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5720 >+/* 5712 */ MCD_OPC_CheckPredicate, 15, 128, 34, // Skip to: 14548 >+/* 5716 */ MCD_OPC_Decode, 214, 17, 125, // Opcode: VZIPd8 >+/* 5720 */ MCD_OPC_FilterValue, 3, 120, 34, // Skip to: 14548 >+/* 5724 */ MCD_OPC_CheckPredicate, 15, 116, 34, // Skip to: 14548 >+/* 5728 */ MCD_OPC_Decode, 217, 17, 126, // Opcode: VZIPq8 >+/* 5732 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 5787 >+/* 5736 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5739 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5751 >+/* 5743 */ MCD_OPC_CheckPredicate, 15, 97, 34, // Skip to: 14548 >+/* 5747 */ MCD_OPC_Decode, 238, 4, 123, // Opcode: VCEQzv4i16 >+/* 5751 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5763 >+/* 5755 */ MCD_OPC_CheckPredicate, 15, 85, 34, // Skip to: 14548 >+/* 5759 */ MCD_OPC_Decode, 240, 4, 124, // Opcode: VCEQzv8i16 >+/* 5763 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5775 >+/* 5767 */ MCD_OPC_CheckPredicate, 15, 73, 34, // Skip to: 14548 >+/* 5771 */ MCD_OPC_Decode, 162, 5, 123, // Opcode: VCLEzv4i16 >+/* 5775 */ MCD_OPC_FilterValue, 3, 65, 34, // Skip to: 14548 >+/* 5779 */ MCD_OPC_CheckPredicate, 15, 61, 34, // Skip to: 14548 >+/* 5783 */ MCD_OPC_Decode, 164, 5, 124, // Opcode: VCLEzv8i16 >+/* 5787 */ MCD_OPC_FilterValue, 6, 51, 0, // Skip to: 5842 >+/* 5791 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5794 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5806 >+/* 5798 */ MCD_OPC_CheckPredicate, 15, 42, 34, // Skip to: 14548 >+/* 5802 */ MCD_OPC_Decode, 208, 17, 125, // Opcode: VUZPd16 >+/* 5806 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5818 >+/* 5810 */ MCD_OPC_CheckPredicate, 15, 30, 34, // Skip to: 14548 >+/* 5814 */ MCD_OPC_Decode, 210, 17, 126, // Opcode: VUZPq16 >+/* 5818 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5830 >+/* 5822 */ MCD_OPC_CheckPredicate, 15, 18, 34, // Skip to: 14548 >+/* 5826 */ MCD_OPC_Decode, 213, 17, 125, // Opcode: VZIPd16 >+/* 5830 */ MCD_OPC_FilterValue, 3, 10, 34, // Skip to: 14548 >+/* 5834 */ MCD_OPC_CheckPredicate, 15, 6, 34, // Skip to: 14548 >+/* 5838 */ MCD_OPC_Decode, 215, 17, 126, // Opcode: VZIPq16 >+/* 5842 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 5897 >+/* 5846 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5849 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5861 >+/* 5853 */ MCD_OPC_CheckPredicate, 15, 243, 33, // Skip to: 14548 >+/* 5857 */ MCD_OPC_Decode, 236, 4, 123, // Opcode: VCEQzv2i32 >+/* 5861 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5873 >+/* 5865 */ MCD_OPC_CheckPredicate, 15, 231, 33, // Skip to: 14548 >+/* 5869 */ MCD_OPC_Decode, 239, 4, 124, // Opcode: VCEQzv4i32 >+/* 5873 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5885 >+/* 5877 */ MCD_OPC_CheckPredicate, 15, 219, 33, // Skip to: 14548 >+/* 5881 */ MCD_OPC_Decode, 160, 5, 123, // Opcode: VCLEzv2i32 >+/* 5885 */ MCD_OPC_FilterValue, 3, 211, 33, // Skip to: 14548 >+/* 5889 */ MCD_OPC_CheckPredicate, 15, 207, 33, // Skip to: 14548 >+/* 5893 */ MCD_OPC_Decode, 163, 5, 124, // Opcode: VCLEzv4i32 >+/* 5897 */ MCD_OPC_FilterValue, 10, 199, 33, // Skip to: 14548 >+/* 5901 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5904 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5916 >+/* 5908 */ MCD_OPC_CheckPredicate, 15, 188, 33, // Skip to: 14548 >+/* 5912 */ MCD_OPC_Decode, 211, 17, 126, // Opcode: VUZPq32 >+/* 5916 */ MCD_OPC_FilterValue, 3, 180, 33, // Skip to: 14548 >+/* 5920 */ MCD_OPC_CheckPredicate, 15, 176, 33, // Skip to: 14548 >+/* 5924 */ MCD_OPC_Decode, 216, 17, 126, // Opcode: VZIPq32 >+/* 5928 */ MCD_OPC_FilterValue, 2, 170, 1, // Skip to: 6358 >+/* 5932 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 5935 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 5990 >+/* 5939 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5942 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5954 >+/* 5946 */ MCD_OPC_CheckPredicate, 15, 150, 33, // Skip to: 14548 >+/* 5950 */ MCD_OPC_Decode, 184, 11, 123, // Opcode: VPADDLsv8i8 >+/* 5954 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5966 >+/* 5958 */ MCD_OPC_CheckPredicate, 15, 138, 33, // Skip to: 14548 >+/* 5962 */ MCD_OPC_Decode, 179, 11, 124, // Opcode: VPADDLsv16i8 >+/* 5966 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5978 >+/* 5970 */ MCD_OPC_CheckPredicate, 15, 126, 33, // Skip to: 14548 >+/* 5974 */ MCD_OPC_Decode, 190, 11, 123, // Opcode: VPADDLuv8i8 >+/* 5978 */ MCD_OPC_FilterValue, 3, 118, 33, // Skip to: 14548 >+/* 5982 */ MCD_OPC_CheckPredicate, 15, 114, 33, // Skip to: 14548 >+/* 5986 */ MCD_OPC_Decode, 185, 11, 124, // Opcode: VPADDLuv16i8 >+/* 5990 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 6021 >+/* 5994 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 5997 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6009 >+/* 6001 */ MCD_OPC_CheckPredicate, 15, 95, 33, // Skip to: 14548 >+/* 6005 */ MCD_OPC_Decode, 179, 5, 123, // Opcode: VCLTzv8i8 >+/* 6009 */ MCD_OPC_FilterValue, 1, 87, 33, // Skip to: 14548 >+/* 6013 */ MCD_OPC_CheckPredicate, 15, 83, 33, // Skip to: 14548 >+/* 6017 */ MCD_OPC_Decode, 172, 5, 124, // Opcode: VCLTzv16i8 >+/* 6021 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6076 >+/* 6025 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6028 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6040 >+/* 6032 */ MCD_OPC_CheckPredicate, 15, 64, 33, // Skip to: 14548 >+/* 6036 */ MCD_OPC_Decode, 203, 10, 127, // Opcode: VMOVNv8i8 >+/* 6040 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6052 >+/* 6044 */ MCD_OPC_CheckPredicate, 15, 52, 33, // Skip to: 14548 >+/* 6048 */ MCD_OPC_Decode, 253, 11, 127, // Opcode: VQMOVNsuv8i8 >+/* 6052 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6064 >+/* 6056 */ MCD_OPC_CheckPredicate, 15, 40, 33, // Skip to: 14548 >+/* 6060 */ MCD_OPC_Decode, 128, 12, 127, // Opcode: VQMOVNsv8i8 >+/* 6064 */ MCD_OPC_FilterValue, 3, 32, 33, // Skip to: 14548 >+/* 6068 */ MCD_OPC_CheckPredicate, 15, 28, 33, // Skip to: 14548 >+/* 6072 */ MCD_OPC_Decode, 131, 12, 127, // Opcode: VQMOVNuv8i8 >+/* 6076 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 6131 >+/* 6080 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6083 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6095 >+/* 6087 */ MCD_OPC_CheckPredicate, 15, 9, 33, // Skip to: 14548 >+/* 6091 */ MCD_OPC_Decode, 181, 11, 123, // Opcode: VPADDLsv4i16 >+/* 6095 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6107 >+/* 6099 */ MCD_OPC_CheckPredicate, 15, 253, 32, // Skip to: 14548 >+/* 6103 */ MCD_OPC_Decode, 183, 11, 124, // Opcode: VPADDLsv8i16 >+/* 6107 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6119 >+/* 6111 */ MCD_OPC_CheckPredicate, 15, 241, 32, // Skip to: 14548 >+/* 6115 */ MCD_OPC_Decode, 187, 11, 123, // Opcode: VPADDLuv4i16 >+/* 6119 */ MCD_OPC_FilterValue, 3, 233, 32, // Skip to: 14548 >+/* 6123 */ MCD_OPC_CheckPredicate, 15, 229, 32, // Skip to: 14548 >+/* 6127 */ MCD_OPC_Decode, 189, 11, 124, // Opcode: VPADDLuv8i16 >+/* 6131 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 6162 >+/* 6135 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6138 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6150 >+/* 6142 */ MCD_OPC_CheckPredicate, 15, 210, 32, // Skip to: 14548 >+/* 6146 */ MCD_OPC_Decode, 176, 5, 123, // Opcode: VCLTzv4i16 >+/* 6150 */ MCD_OPC_FilterValue, 1, 202, 32, // Skip to: 14548 >+/* 6154 */ MCD_OPC_CheckPredicate, 15, 198, 32, // Skip to: 14548 >+/* 6158 */ MCD_OPC_Decode, 178, 5, 124, // Opcode: VCLTzv8i16 >+/* 6162 */ MCD_OPC_FilterValue, 6, 51, 0, // Skip to: 6217 >+/* 6166 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6169 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6181 >+/* 6173 */ MCD_OPC_CheckPredicate, 15, 179, 32, // Skip to: 14548 >+/* 6177 */ MCD_OPC_Decode, 202, 10, 127, // Opcode: VMOVNv4i16 >+/* 6181 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6193 >+/* 6185 */ MCD_OPC_CheckPredicate, 15, 167, 32, // Skip to: 14548 >+/* 6189 */ MCD_OPC_Decode, 252, 11, 127, // Opcode: VQMOVNsuv4i16 >+/* 6193 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6205 >+/* 6197 */ MCD_OPC_CheckPredicate, 15, 155, 32, // Skip to: 14548 >+/* 6201 */ MCD_OPC_Decode, 255, 11, 127, // Opcode: VQMOVNsv4i16 >+/* 6205 */ MCD_OPC_FilterValue, 3, 147, 32, // Skip to: 14548 >+/* 6209 */ MCD_OPC_CheckPredicate, 15, 143, 32, // Skip to: 14548 >+/* 6213 */ MCD_OPC_Decode, 130, 12, 127, // Opcode: VQMOVNuv4i16 >+/* 6217 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 6272 >+/* 6221 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6224 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6236 >+/* 6228 */ MCD_OPC_CheckPredicate, 15, 124, 32, // Skip to: 14548 >+/* 6232 */ MCD_OPC_Decode, 180, 11, 123, // Opcode: VPADDLsv2i32 >+/* 6236 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6248 >+/* 6240 */ MCD_OPC_CheckPredicate, 15, 112, 32, // Skip to: 14548 >+/* 6244 */ MCD_OPC_Decode, 182, 11, 124, // Opcode: VPADDLsv4i32 >+/* 6248 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6260 >+/* 6252 */ MCD_OPC_CheckPredicate, 15, 100, 32, // Skip to: 14548 >+/* 6256 */ MCD_OPC_Decode, 186, 11, 123, // Opcode: VPADDLuv2i32 >+/* 6260 */ MCD_OPC_FilterValue, 3, 92, 32, // Skip to: 14548 >+/* 6264 */ MCD_OPC_CheckPredicate, 15, 88, 32, // Skip to: 14548 >+/* 6268 */ MCD_OPC_Decode, 188, 11, 124, // Opcode: VPADDLuv4i32 >+/* 6272 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 6303 >+/* 6276 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6279 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6291 >+/* 6283 */ MCD_OPC_CheckPredicate, 15, 69, 32, // Skip to: 14548 >+/* 6287 */ MCD_OPC_Decode, 174, 5, 123, // Opcode: VCLTzv2i32 >+/* 6291 */ MCD_OPC_FilterValue, 1, 61, 32, // Skip to: 14548 >+/* 6295 */ MCD_OPC_CheckPredicate, 15, 57, 32, // Skip to: 14548 >+/* 6299 */ MCD_OPC_Decode, 177, 5, 124, // Opcode: VCLTzv4i32 >+/* 6303 */ MCD_OPC_FilterValue, 10, 49, 32, // Skip to: 14548 >+/* 6307 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6310 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6322 >+/* 6314 */ MCD_OPC_CheckPredicate, 15, 38, 32, // Skip to: 14548 >+/* 6318 */ MCD_OPC_Decode, 201, 10, 127, // Opcode: VMOVNv2i32 >+/* 6322 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6334 >+/* 6326 */ MCD_OPC_CheckPredicate, 15, 26, 32, // Skip to: 14548 >+/* 6330 */ MCD_OPC_Decode, 251, 11, 127, // Opcode: VQMOVNsuv2i32 >+/* 6334 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6346 >+/* 6338 */ MCD_OPC_CheckPredicate, 15, 14, 32, // Skip to: 14548 >+/* 6342 */ MCD_OPC_Decode, 254, 11, 127, // Opcode: VQMOVNsv2i32 >+/* 6346 */ MCD_OPC_FilterValue, 3, 6, 32, // Skip to: 14548 >+/* 6350 */ MCD_OPC_CheckPredicate, 15, 2, 32, // Skip to: 14548 >+/* 6354 */ MCD_OPC_Decode, 129, 12, 127, // Opcode: VQMOVNuv2i32 >+/* 6358 */ MCD_OPC_FilterValue, 3, 225, 0, // Skip to: 6587 >+/* 6362 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6365 */ MCD_OPC_FilterValue, 1, 51, 0, // Skip to: 6420 >+/* 6369 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6372 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6384 >+/* 6376 */ MCD_OPC_CheckPredicate, 15, 232, 31, // Skip to: 14548 >+/* 6380 */ MCD_OPC_Decode, 180, 4, 123, // Opcode: VABSv8i8 >+/* 6384 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6396 >+/* 6388 */ MCD_OPC_CheckPredicate, 15, 220, 31, // Skip to: 14548 >+/* 6392 */ MCD_OPC_Decode, 175, 4, 124, // Opcode: VABSv16i8 >+/* 6396 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6408 >+/* 6400 */ MCD_OPC_CheckPredicate, 15, 208, 31, // Skip to: 14548 >+/* 6404 */ MCD_OPC_Decode, 151, 11, 123, // Opcode: VNEGs8d >+/* 6408 */ MCD_OPC_FilterValue, 3, 200, 31, // Skip to: 14548 >+/* 6412 */ MCD_OPC_CheckPredicate, 15, 196, 31, // Skip to: 14548 >+/* 6416 */ MCD_OPC_Decode, 152, 11, 124, // Opcode: VNEGs8q >+/* 6420 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 6439 >+/* 6424 */ MCD_OPC_CheckPredicate, 15, 184, 31, // Skip to: 14548 >+/* 6428 */ MCD_OPC_CheckField, 6, 2, 0, 178, 31, // Skip to: 14548 >+/* 6434 */ MCD_OPC_Decode, 240, 13, 128, 1, // Opcode: VSHLLi8 >+/* 6439 */ MCD_OPC_FilterValue, 5, 51, 0, // Skip to: 6494 >+/* 6443 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6446 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6458 >+/* 6450 */ MCD_OPC_CheckPredicate, 15, 158, 31, // Skip to: 14548 >+/* 6454 */ MCD_OPC_Decode, 177, 4, 123, // Opcode: VABSv4i16 >+/* 6458 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6470 >+/* 6462 */ MCD_OPC_CheckPredicate, 15, 146, 31, // Skip to: 14548 >+/* 6466 */ MCD_OPC_Decode, 179, 4, 124, // Opcode: VABSv8i16 >+/* 6470 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6482 >+/* 6474 */ MCD_OPC_CheckPredicate, 15, 134, 31, // Skip to: 14548 >+/* 6478 */ MCD_OPC_Decode, 147, 11, 123, // Opcode: VNEGs16d >+/* 6482 */ MCD_OPC_FilterValue, 3, 126, 31, // Skip to: 14548 >+/* 6486 */ MCD_OPC_CheckPredicate, 15, 122, 31, // Skip to: 14548 >+/* 6490 */ MCD_OPC_Decode, 148, 11, 124, // Opcode: VNEGs16q >+/* 6494 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 6513 >+/* 6498 */ MCD_OPC_CheckPredicate, 15, 110, 31, // Skip to: 14548 >+/* 6502 */ MCD_OPC_CheckField, 6, 2, 0, 104, 31, // Skip to: 14548 >+/* 6508 */ MCD_OPC_Decode, 238, 13, 128, 1, // Opcode: VSHLLi16 >+/* 6513 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 6568 >+/* 6517 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6520 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6532 >+/* 6524 */ MCD_OPC_CheckPredicate, 15, 84, 31, // Skip to: 14548 >+/* 6528 */ MCD_OPC_Decode, 176, 4, 123, // Opcode: VABSv2i32 >+/* 6532 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6544 >+/* 6536 */ MCD_OPC_CheckPredicate, 15, 72, 31, // Skip to: 14548 >+/* 6540 */ MCD_OPC_Decode, 178, 4, 124, // Opcode: VABSv4i32 >+/* 6544 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6556 >+/* 6548 */ MCD_OPC_CheckPredicate, 15, 60, 31, // Skip to: 14548 >+/* 6552 */ MCD_OPC_Decode, 149, 11, 123, // Opcode: VNEGs32d >+/* 6556 */ MCD_OPC_FilterValue, 3, 52, 31, // Skip to: 14548 >+/* 6560 */ MCD_OPC_CheckPredicate, 15, 48, 31, // Skip to: 14548 >+/* 6564 */ MCD_OPC_Decode, 150, 11, 124, // Opcode: VNEGs32q >+/* 6568 */ MCD_OPC_FilterValue, 10, 40, 31, // Skip to: 14548 >+/* 6572 */ MCD_OPC_CheckPredicate, 15, 36, 31, // Skip to: 14548 >+/* 6576 */ MCD_OPC_CheckField, 6, 2, 0, 30, 31, // Skip to: 14548 >+/* 6582 */ MCD_OPC_Decode, 239, 13, 128, 1, // Opcode: VSHLLi32 >+/* 6587 */ MCD_OPC_FilterValue, 4, 22, 1, // Skip to: 6869 >+/* 6591 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6594 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 6649 >+/* 6598 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6601 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6613 >+/* 6605 */ MCD_OPC_CheckPredicate, 15, 3, 31, // Skip to: 14548 >+/* 6609 */ MCD_OPC_Decode, 171, 5, 123, // Opcode: VCLSv8i8 >+/* 6613 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6625 >+/* 6617 */ MCD_OPC_CheckPredicate, 15, 247, 30, // Skip to: 14548 >+/* 6621 */ MCD_OPC_Decode, 166, 5, 124, // Opcode: VCLSv16i8 >+/* 6625 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6637 >+/* 6629 */ MCD_OPC_CheckPredicate, 15, 235, 30, // Skip to: 14548 >+/* 6633 */ MCD_OPC_Decode, 185, 5, 123, // Opcode: VCLZv8i8 >+/* 6637 */ MCD_OPC_FilterValue, 3, 227, 30, // Skip to: 14548 >+/* 6641 */ MCD_OPC_CheckPredicate, 15, 223, 30, // Skip to: 14548 >+/* 6645 */ MCD_OPC_Decode, 180, 5, 124, // Opcode: VCLZv16i8 >+/* 6649 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 6704 >+/* 6653 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6656 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6668 >+/* 6660 */ MCD_OPC_CheckPredicate, 15, 204, 30, // Skip to: 14548 >+/* 6664 */ MCD_OPC_Decode, 168, 5, 123, // Opcode: VCLSv4i16 >+/* 6668 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6680 >+/* 6672 */ MCD_OPC_CheckPredicate, 15, 192, 30, // Skip to: 14548 >+/* 6676 */ MCD_OPC_Decode, 170, 5, 124, // Opcode: VCLSv8i16 >+/* 6680 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6692 >+/* 6684 */ MCD_OPC_CheckPredicate, 15, 180, 30, // Skip to: 14548 >+/* 6688 */ MCD_OPC_Decode, 182, 5, 123, // Opcode: VCLZv4i16 >+/* 6692 */ MCD_OPC_FilterValue, 3, 172, 30, // Skip to: 14548 >+/* 6696 */ MCD_OPC_CheckPredicate, 15, 168, 30, // Skip to: 14548 >+/* 6700 */ MCD_OPC_Decode, 184, 5, 124, // Opcode: VCLZv8i16 >+/* 6704 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 6759 >+/* 6708 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6711 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6723 >+/* 6715 */ MCD_OPC_CheckPredicate, 15, 149, 30, // Skip to: 14548 >+/* 6719 */ MCD_OPC_Decode, 167, 5, 123, // Opcode: VCLSv2i32 >+/* 6723 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6735 >+/* 6727 */ MCD_OPC_CheckPredicate, 15, 137, 30, // Skip to: 14548 >+/* 6731 */ MCD_OPC_Decode, 169, 5, 124, // Opcode: VCLSv4i32 >+/* 6735 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6747 >+/* 6739 */ MCD_OPC_CheckPredicate, 15, 125, 30, // Skip to: 14548 >+/* 6743 */ MCD_OPC_Decode, 181, 5, 123, // Opcode: VCLZv2i32 >+/* 6747 */ MCD_OPC_FilterValue, 3, 117, 30, // Skip to: 14548 >+/* 6751 */ MCD_OPC_CheckPredicate, 15, 113, 30, // Skip to: 14548 >+/* 6755 */ MCD_OPC_Decode, 183, 5, 124, // Opcode: VCLZv4i32 >+/* 6759 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 6814 >+/* 6763 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6766 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6778 >+/* 6770 */ MCD_OPC_CheckPredicate, 15, 94, 30, // Skip to: 14548 >+/* 6774 */ MCD_OPC_Decode, 151, 5, 123, // Opcode: VCGTzv2f32 >+/* 6778 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6790 >+/* 6782 */ MCD_OPC_CheckPredicate, 15, 82, 30, // Skip to: 14548 >+/* 6786 */ MCD_OPC_Decode, 153, 5, 124, // Opcode: VCGTzv4f32 >+/* 6790 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6802 >+/* 6794 */ MCD_OPC_CheckPredicate, 15, 70, 30, // Skip to: 14548 >+/* 6798 */ MCD_OPC_Decode, 129, 5, 123, // Opcode: VCGEzv2f32 >+/* 6802 */ MCD_OPC_FilterValue, 3, 62, 30, // Skip to: 14548 >+/* 6806 */ MCD_OPC_CheckPredicate, 15, 58, 30, // Skip to: 14548 >+/* 6810 */ MCD_OPC_Decode, 131, 5, 124, // Opcode: VCGEzv4f32 >+/* 6814 */ MCD_OPC_FilterValue, 11, 50, 30, // Skip to: 14548 >+/* 6818 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6821 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6833 >+/* 6825 */ MCD_OPC_CheckPredicate, 15, 39, 30, // Skip to: 14548 >+/* 6829 */ MCD_OPC_Decode, 239, 12, 123, // Opcode: VRECPEd >+/* 6833 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6845 >+/* 6837 */ MCD_OPC_CheckPredicate, 15, 27, 30, // Skip to: 14548 >+/* 6841 */ MCD_OPC_Decode, 242, 12, 124, // Opcode: VRECPEq >+/* 6845 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6857 >+/* 6849 */ MCD_OPC_CheckPredicate, 15, 15, 30, // Skip to: 14548 >+/* 6853 */ MCD_OPC_Decode, 202, 13, 123, // Opcode: VRSQRTEd >+/* 6857 */ MCD_OPC_FilterValue, 3, 7, 30, // Skip to: 14548 >+/* 6861 */ MCD_OPC_CheckPredicate, 15, 3, 30, // Skip to: 14548 >+/* 6865 */ MCD_OPC_Decode, 205, 13, 124, // Opcode: VRSQRTEq >+/* 6869 */ MCD_OPC_FilterValue, 5, 175, 0, // Skip to: 7048 >+/* 6873 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 6876 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6919 >+/* 6880 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6883 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6895 >+/* 6887 */ MCD_OPC_CheckPredicate, 15, 233, 29, // Skip to: 14548 >+/* 6891 */ MCD_OPC_Decode, 194, 5, 123, // Opcode: VCNTd >+/* 6895 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6907 >+/* 6899 */ MCD_OPC_CheckPredicate, 15, 221, 29, // Skip to: 14548 >+/* 6903 */ MCD_OPC_Decode, 235, 4, 123, // Opcode: VCEQzv2f32 >+/* 6907 */ MCD_OPC_FilterValue, 11, 213, 29, // Skip to: 14548 >+/* 6911 */ MCD_OPC_CheckPredicate, 15, 209, 29, // Skip to: 14548 >+/* 6915 */ MCD_OPC_Decode, 240, 12, 123, // Opcode: VRECPEfd >+/* 6919 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 6962 >+/* 6923 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6926 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6938 >+/* 6930 */ MCD_OPC_CheckPredicate, 15, 190, 29, // Skip to: 14548 >+/* 6934 */ MCD_OPC_Decode, 195, 5, 124, // Opcode: VCNTq >+/* 6938 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6950 >+/* 6942 */ MCD_OPC_CheckPredicate, 15, 178, 29, // Skip to: 14548 >+/* 6946 */ MCD_OPC_Decode, 237, 4, 124, // Opcode: VCEQzv4f32 >+/* 6950 */ MCD_OPC_FilterValue, 11, 170, 29, // Skip to: 14548 >+/* 6954 */ MCD_OPC_CheckPredicate, 15, 166, 29, // Skip to: 14548 >+/* 6958 */ MCD_OPC_Decode, 241, 12, 124, // Opcode: VRECPEfq >+/* 6962 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 7005 >+/* 6966 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 6969 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6981 >+/* 6973 */ MCD_OPC_CheckPredicate, 15, 147, 29, // Skip to: 14548 >+/* 6977 */ MCD_OPC_Decode, 137, 11, 123, // Opcode: VMVNd >+/* 6981 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6993 >+/* 6985 */ MCD_OPC_CheckPredicate, 15, 135, 29, // Skip to: 14548 >+/* 6989 */ MCD_OPC_Decode, 159, 5, 123, // Opcode: VCLEzv2f32 >+/* 6993 */ MCD_OPC_FilterValue, 11, 127, 29, // Skip to: 14548 >+/* 6997 */ MCD_OPC_CheckPredicate, 15, 123, 29, // Skip to: 14548 >+/* 7001 */ MCD_OPC_Decode, 203, 13, 123, // Opcode: VRSQRTEfd >+/* 7005 */ MCD_OPC_FilterValue, 3, 115, 29, // Skip to: 14548 >+/* 7009 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7012 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7024 >+/* 7016 */ MCD_OPC_CheckPredicate, 15, 104, 29, // Skip to: 14548 >+/* 7020 */ MCD_OPC_Decode, 138, 11, 124, // Opcode: VMVNq >+/* 7024 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7036 >+/* 7028 */ MCD_OPC_CheckPredicate, 15, 92, 29, // Skip to: 14548 >+/* 7032 */ MCD_OPC_Decode, 161, 5, 124, // Opcode: VCLEzv4f32 >+/* 7036 */ MCD_OPC_FilterValue, 11, 84, 29, // Skip to: 14548 >+/* 7040 */ MCD_OPC_CheckPredicate, 15, 80, 29, // Skip to: 14548 >+/* 7044 */ MCD_OPC_Decode, 204, 13, 124, // Opcode: VRSQRTEfq >+/* 7048 */ MCD_OPC_FilterValue, 6, 28, 1, // Skip to: 7336 >+/* 7052 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7055 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7114 >+/* 7059 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7062 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7075 >+/* 7066 */ MCD_OPC_CheckPredicate, 15, 54, 29, // Skip to: 14548 >+/* 7070 */ MCD_OPC_Decode, 172, 11, 129, 1, // Opcode: VPADALsv8i8 >+/* 7075 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7088 >+/* 7079 */ MCD_OPC_CheckPredicate, 15, 41, 29, // Skip to: 14548 >+/* 7083 */ MCD_OPC_Decode, 167, 11, 130, 1, // Opcode: VPADALsv16i8 >+/* 7088 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7101 >+/* 7092 */ MCD_OPC_CheckPredicate, 15, 28, 29, // Skip to: 14548 >+/* 7096 */ MCD_OPC_Decode, 178, 11, 129, 1, // Opcode: VPADALuv8i8 >+/* 7101 */ MCD_OPC_FilterValue, 3, 19, 29, // Skip to: 14548 >+/* 7105 */ MCD_OPC_CheckPredicate, 15, 15, 29, // Skip to: 14548 >+/* 7109 */ MCD_OPC_Decode, 173, 11, 130, 1, // Opcode: VPADALuv16i8 >+/* 7114 */ MCD_OPC_FilterValue, 4, 55, 0, // Skip to: 7173 >+/* 7118 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7121 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7134 >+/* 7125 */ MCD_OPC_CheckPredicate, 15, 251, 28, // Skip to: 14548 >+/* 7129 */ MCD_OPC_Decode, 169, 11, 129, 1, // Opcode: VPADALsv4i16 >+/* 7134 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7147 >+/* 7138 */ MCD_OPC_CheckPredicate, 15, 238, 28, // Skip to: 14548 >+/* 7142 */ MCD_OPC_Decode, 171, 11, 130, 1, // Opcode: VPADALsv8i16 >+/* 7147 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7160 >+/* 7151 */ MCD_OPC_CheckPredicate, 15, 225, 28, // Skip to: 14548 >+/* 7155 */ MCD_OPC_Decode, 175, 11, 129, 1, // Opcode: VPADALuv4i16 >+/* 7160 */ MCD_OPC_FilterValue, 3, 216, 28, // Skip to: 14548 >+/* 7164 */ MCD_OPC_CheckPredicate, 15, 212, 28, // Skip to: 14548 >+/* 7168 */ MCD_OPC_Decode, 177, 11, 130, 1, // Opcode: VPADALuv8i16 >+/* 7173 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 7191 >+/* 7177 */ MCD_OPC_CheckPredicate, 17, 199, 28, // Skip to: 14548 >+/* 7181 */ MCD_OPC_CheckField, 6, 2, 0, 193, 28, // Skip to: 14548 >+/* 7187 */ MCD_OPC_Decode, 238, 5, 127, // Opcode: VCVTf2h >+/* 7191 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 7250 >+/* 7195 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7198 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7211 >+/* 7202 */ MCD_OPC_CheckPredicate, 15, 174, 28, // Skip to: 14548 >+/* 7206 */ MCD_OPC_Decode, 168, 11, 129, 1, // Opcode: VPADALsv2i32 >+/* 7211 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7224 >+/* 7215 */ MCD_OPC_CheckPredicate, 15, 161, 28, // Skip to: 14548 >+/* 7219 */ MCD_OPC_Decode, 170, 11, 130, 1, // Opcode: VPADALsv4i32 >+/* 7224 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7237 >+/* 7228 */ MCD_OPC_CheckPredicate, 15, 148, 28, // Skip to: 14548 >+/* 7232 */ MCD_OPC_Decode, 174, 11, 129, 1, // Opcode: VPADALuv2i32 >+/* 7237 */ MCD_OPC_FilterValue, 3, 139, 28, // Skip to: 14548 >+/* 7241 */ MCD_OPC_CheckPredicate, 15, 135, 28, // Skip to: 14548 >+/* 7245 */ MCD_OPC_Decode, 176, 11, 130, 1, // Opcode: VPADALuv4i32 >+/* 7250 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 7281 >+/* 7254 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7257 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7269 >+/* 7261 */ MCD_OPC_CheckPredicate, 15, 115, 28, // Skip to: 14548 >+/* 7265 */ MCD_OPC_Decode, 173, 5, 123, // Opcode: VCLTzv2f32 >+/* 7269 */ MCD_OPC_FilterValue, 1, 107, 28, // Skip to: 14548 >+/* 7273 */ MCD_OPC_CheckPredicate, 15, 103, 28, // Skip to: 14548 >+/* 7277 */ MCD_OPC_Decode, 175, 5, 124, // Opcode: VCLTzv4f32 >+/* 7281 */ MCD_OPC_FilterValue, 11, 95, 28, // Skip to: 14548 >+/* 7285 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7288 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7300 >+/* 7292 */ MCD_OPC_CheckPredicate, 15, 84, 28, // Skip to: 14548 >+/* 7296 */ MCD_OPC_Decode, 248, 5, 123, // Opcode: VCVTs2fd >+/* 7300 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7312 >+/* 7304 */ MCD_OPC_CheckPredicate, 15, 72, 28, // Skip to: 14548 >+/* 7308 */ MCD_OPC_Decode, 249, 5, 124, // Opcode: VCVTs2fq >+/* 7312 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7324 >+/* 7316 */ MCD_OPC_CheckPredicate, 15, 60, 28, // Skip to: 14548 >+/* 7320 */ MCD_OPC_Decode, 250, 5, 123, // Opcode: VCVTu2fd >+/* 7324 */ MCD_OPC_FilterValue, 3, 52, 28, // Skip to: 14548 >+/* 7328 */ MCD_OPC_CheckPredicate, 15, 48, 28, // Skip to: 14548 >+/* 7332 */ MCD_OPC_Decode, 251, 5, 124, // Opcode: VCVTu2fq >+/* 7336 */ MCD_OPC_FilterValue, 7, 41, 1, // Skip to: 7637 >+/* 7340 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 7343 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 7398 >+/* 7347 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7350 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7362 >+/* 7354 */ MCD_OPC_CheckPredicate, 15, 22, 28, // Skip to: 14548 >+/* 7358 */ MCD_OPC_Decode, 214, 11, 123, // Opcode: VQABSv8i8 >+/* 7362 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7374 >+/* 7366 */ MCD_OPC_CheckPredicate, 15, 10, 28, // Skip to: 14548 >+/* 7370 */ MCD_OPC_Decode, 209, 11, 124, // Opcode: VQABSv16i8 >+/* 7374 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7386 >+/* 7378 */ MCD_OPC_CheckPredicate, 15, 254, 27, // Skip to: 14548 >+/* 7382 */ MCD_OPC_Decode, 137, 12, 123, // Opcode: VQNEGv8i8 >+/* 7386 */ MCD_OPC_FilterValue, 3, 246, 27, // Skip to: 14548 >+/* 7390 */ MCD_OPC_CheckPredicate, 15, 242, 27, // Skip to: 14548 >+/* 7394 */ MCD_OPC_Decode, 132, 12, 124, // Opcode: VQNEGv16i8 >+/* 7398 */ MCD_OPC_FilterValue, 4, 51, 0, // Skip to: 7453 >+/* 7402 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7405 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7417 >+/* 7409 */ MCD_OPC_CheckPredicate, 15, 223, 27, // Skip to: 14548 >+/* 7413 */ MCD_OPC_Decode, 211, 11, 123, // Opcode: VQABSv4i16 >+/* 7417 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7429 >+/* 7421 */ MCD_OPC_CheckPredicate, 15, 211, 27, // Skip to: 14548 >+/* 7425 */ MCD_OPC_Decode, 213, 11, 124, // Opcode: VQABSv8i16 >+/* 7429 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7441 >+/* 7433 */ MCD_OPC_CheckPredicate, 15, 199, 27, // Skip to: 14548 >+/* 7437 */ MCD_OPC_Decode, 134, 12, 123, // Opcode: VQNEGv4i16 >+/* 7441 */ MCD_OPC_FilterValue, 3, 191, 27, // Skip to: 14548 >+/* 7445 */ MCD_OPC_CheckPredicate, 15, 187, 27, // Skip to: 14548 >+/* 7449 */ MCD_OPC_Decode, 136, 12, 124, // Opcode: VQNEGv8i16 >+/* 7453 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 7472 >+/* 7457 */ MCD_OPC_CheckPredicate, 17, 175, 27, // Skip to: 14548 >+/* 7461 */ MCD_OPC_CheckField, 6, 2, 0, 169, 27, // Skip to: 14548 >+/* 7467 */ MCD_OPC_Decode, 247, 5, 131, 1, // Opcode: VCVTh2f >+/* 7472 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 7527 >+/* 7476 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7479 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7491 >+/* 7483 */ MCD_OPC_CheckPredicate, 15, 149, 27, // Skip to: 14548 >+/* 7487 */ MCD_OPC_Decode, 210, 11, 123, // Opcode: VQABSv2i32 >+/* 7491 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7503 >+/* 7495 */ MCD_OPC_CheckPredicate, 15, 137, 27, // Skip to: 14548 >+/* 7499 */ MCD_OPC_Decode, 212, 11, 124, // Opcode: VQABSv4i32 >+/* 7503 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7515 >+/* 7507 */ MCD_OPC_CheckPredicate, 15, 125, 27, // Skip to: 14548 >+/* 7511 */ MCD_OPC_Decode, 133, 12, 123, // Opcode: VQNEGv2i32 >+/* 7515 */ MCD_OPC_FilterValue, 3, 117, 27, // Skip to: 14548 >+/* 7519 */ MCD_OPC_CheckPredicate, 15, 113, 27, // Skip to: 14548 >+/* 7523 */ MCD_OPC_Decode, 135, 12, 124, // Opcode: VQNEGv4i32 >+/* 7527 */ MCD_OPC_FilterValue, 9, 51, 0, // Skip to: 7582 >+/* 7531 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7534 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7546 >+/* 7538 */ MCD_OPC_CheckPredicate, 15, 94, 27, // Skip to: 14548 >+/* 7542 */ MCD_OPC_Decode, 173, 4, 123, // Opcode: VABSfd >+/* 7546 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7558 >+/* 7550 */ MCD_OPC_CheckPredicate, 15, 82, 27, // Skip to: 14548 >+/* 7554 */ MCD_OPC_Decode, 174, 4, 124, // Opcode: VABSfq >+/* 7558 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7570 >+/* 7562 */ MCD_OPC_CheckPredicate, 15, 70, 27, // Skip to: 14548 >+/* 7566 */ MCD_OPC_Decode, 146, 11, 123, // Opcode: VNEGfd >+/* 7570 */ MCD_OPC_FilterValue, 3, 62, 27, // Skip to: 14548 >+/* 7574 */ MCD_OPC_CheckPredicate, 15, 58, 27, // Skip to: 14548 >+/* 7578 */ MCD_OPC_Decode, 145, 11, 124, // Opcode: VNEGf32q >+/* 7582 */ MCD_OPC_FilterValue, 11, 50, 27, // Skip to: 14548 >+/* 7586 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7589 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7601 >+/* 7593 */ MCD_OPC_CheckPredicate, 15, 39, 27, // Skip to: 14548 >+/* 7597 */ MCD_OPC_Decode, 239, 5, 123, // Opcode: VCVTf2sd >+/* 7601 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7613 >+/* 7605 */ MCD_OPC_CheckPredicate, 15, 27, 27, // Skip to: 14548 >+/* 7609 */ MCD_OPC_Decode, 240, 5, 124, // Opcode: VCVTf2sq >+/* 7613 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7625 >+/* 7617 */ MCD_OPC_CheckPredicate, 15, 15, 27, // Skip to: 14548 >+/* 7621 */ MCD_OPC_Decode, 241, 5, 123, // Opcode: VCVTf2ud >+/* 7625 */ MCD_OPC_FilterValue, 3, 7, 27, // Skip to: 14548 >+/* 7629 */ MCD_OPC_CheckPredicate, 15, 3, 27, // Skip to: 14548 >+/* 7633 */ MCD_OPC_Decode, 242, 5, 124, // Opcode: VCVTf2uq >+/* 7637 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 7670 >+/* 7641 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7644 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7657 >+/* 7648 */ MCD_OPC_CheckPredicate, 15, 240, 26, // Skip to: 14548 >+/* 7652 */ MCD_OPC_Decode, 162, 17, 132, 1, // Opcode: VTBL1 >+/* 7657 */ MCD_OPC_FilterValue, 1, 231, 26, // Skip to: 14548 >+/* 7661 */ MCD_OPC_CheckPredicate, 15, 227, 26, // Skip to: 14548 >+/* 7665 */ MCD_OPC_Decode, 168, 17, 132, 1, // Opcode: VTBX1 >+/* 7670 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 7703 >+/* 7674 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7677 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7690 >+/* 7681 */ MCD_OPC_CheckPredicate, 15, 207, 26, // Skip to: 14548 >+/* 7685 */ MCD_OPC_Decode, 163, 17, 132, 1, // Opcode: VTBL2 >+/* 7690 */ MCD_OPC_FilterValue, 1, 198, 26, // Skip to: 14548 >+/* 7694 */ MCD_OPC_CheckPredicate, 15, 194, 26, // Skip to: 14548 >+/* 7698 */ MCD_OPC_Decode, 169, 17, 132, 1, // Opcode: VTBX2 >+/* 7703 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 7736 >+/* 7707 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7710 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7723 >+/* 7714 */ MCD_OPC_CheckPredicate, 15, 174, 26, // Skip to: 14548 >+/* 7718 */ MCD_OPC_Decode, 164, 17, 132, 1, // Opcode: VTBL3 >+/* 7723 */ MCD_OPC_FilterValue, 1, 165, 26, // Skip to: 14548 >+/* 7727 */ MCD_OPC_CheckPredicate, 15, 161, 26, // Skip to: 14548 >+/* 7731 */ MCD_OPC_Decode, 170, 17, 132, 1, // Opcode: VTBX3 >+/* 7736 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 7769 >+/* 7740 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7743 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7756 >+/* 7747 */ MCD_OPC_CheckPredicate, 15, 141, 26, // Skip to: 14548 >+/* 7751 */ MCD_OPC_Decode, 166, 17, 132, 1, // Opcode: VTBL4 >+/* 7756 */ MCD_OPC_FilterValue, 1, 132, 26, // Skip to: 14548 >+/* 7760 */ MCD_OPC_CheckPredicate, 15, 128, 26, // Skip to: 14548 >+/* 7764 */ MCD_OPC_Decode, 172, 17, 132, 1, // Opcode: VTBX4 >+/* 7769 */ MCD_OPC_FilterValue, 12, 119, 26, // Skip to: 14548 >+/* 7773 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 7776 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 7835 >+/* 7780 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7783 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 7822 >+/* 7787 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7790 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 7809 >+/* 7794 */ MCD_OPC_CheckPredicate, 15, 94, 26, // Skip to: 14548 >+/* 7798 */ MCD_OPC_CheckField, 18, 1, 1, 88, 26, // Skip to: 14548 >+/* 7804 */ MCD_OPC_Decode, 138, 6, 133, 1, // Opcode: VDUPLN32d >+/* 7809 */ MCD_OPC_FilterValue, 1, 79, 26, // Skip to: 14548 >+/* 7813 */ MCD_OPC_CheckPredicate, 15, 75, 26, // Skip to: 14548 >+/* 7817 */ MCD_OPC_Decode, 136, 6, 134, 1, // Opcode: VDUPLN16d >+/* 7822 */ MCD_OPC_FilterValue, 1, 66, 26, // Skip to: 14548 >+/* 7826 */ MCD_OPC_CheckPredicate, 15, 62, 26, // Skip to: 14548 >+/* 7830 */ MCD_OPC_Decode, 140, 6, 135, 1, // Opcode: VDUPLN8d >+/* 7835 */ MCD_OPC_FilterValue, 1, 53, 26, // Skip to: 14548 >+/* 7839 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... >+/* 7842 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 7881 >+/* 7846 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... >+/* 7849 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 7868 >+/* 7853 */ MCD_OPC_CheckPredicate, 15, 35, 26, // Skip to: 14548 >+/* 7857 */ MCD_OPC_CheckField, 18, 1, 1, 29, 26, // Skip to: 14548 >+/* 7863 */ MCD_OPC_Decode, 139, 6, 136, 1, // Opcode: VDUPLN32q >+/* 7868 */ MCD_OPC_FilterValue, 1, 20, 26, // Skip to: 14548 >+/* 7872 */ MCD_OPC_CheckPredicate, 15, 16, 26, // Skip to: 14548 >+/* 7876 */ MCD_OPC_Decode, 137, 6, 137, 1, // Opcode: VDUPLN16q >+/* 7881 */ MCD_OPC_FilterValue, 1, 7, 26, // Skip to: 14548 >+/* 7885 */ MCD_OPC_CheckPredicate, 15, 3, 26, // Skip to: 14548 >+/* 7889 */ MCD_OPC_Decode, 141, 6, 138, 1, // Opcode: VDUPLN8q >+/* 7894 */ MCD_OPC_FilterValue, 1, 250, 25, // Skip to: 14548 >+/* 7898 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 7901 */ MCD_OPC_FilterValue, 0, 185, 13, // Skip to: 11418 >+/* 7905 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 7908 */ MCD_OPC_FilterValue, 0, 28, 6, // Skip to: 9476 >+/* 7912 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 7915 */ MCD_OPC_FilterValue, 0, 135, 0, // Skip to: 8054 >+/* 7919 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 7922 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 7955 >+/* 7926 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 7929 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 7942 >+/* 7934 */ MCD_OPC_CheckPredicate, 15, 210, 25, // Skip to: 14548 >+/* 7938 */ MCD_OPC_Decode, 222, 11, 94, // Opcode: VQADDsv8i8 >+/* 7942 */ MCD_OPC_FilterValue, 243, 1, 201, 25, // Skip to: 14548 >+/* 7947 */ MCD_OPC_CheckPredicate, 15, 197, 25, // Skip to: 14548 >+/* 7951 */ MCD_OPC_Decode, 230, 11, 94, // Opcode: VQADDuv8i8 >+/* 7955 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 7988 >+/* 7959 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 7962 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 7975 >+/* 7967 */ MCD_OPC_CheckPredicate, 15, 177, 25, // Skip to: 14548 >+/* 7971 */ MCD_OPC_Decode, 219, 11, 94, // Opcode: VQADDsv4i16 >+/* 7975 */ MCD_OPC_FilterValue, 243, 1, 168, 25, // Skip to: 14548 >+/* 7980 */ MCD_OPC_CheckPredicate, 15, 164, 25, // Skip to: 14548 >+/* 7984 */ MCD_OPC_Decode, 227, 11, 94, // Opcode: VQADDuv4i16 >+/* 7988 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8021 >+/* 7992 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 7995 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8008 >+/* 8000 */ MCD_OPC_CheckPredicate, 15, 144, 25, // Skip to: 14548 >+/* 8004 */ MCD_OPC_Decode, 217, 11, 94, // Opcode: VQADDsv2i32 >+/* 8008 */ MCD_OPC_FilterValue, 243, 1, 135, 25, // Skip to: 14548 >+/* 8013 */ MCD_OPC_CheckPredicate, 15, 131, 25, // Skip to: 14548 >+/* 8017 */ MCD_OPC_Decode, 225, 11, 94, // Opcode: VQADDuv2i32 >+/* 8021 */ MCD_OPC_FilterValue, 3, 123, 25, // Skip to: 14548 >+/* 8025 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8028 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8041 >+/* 8033 */ MCD_OPC_CheckPredicate, 15, 111, 25, // Skip to: 14548 >+/* 8037 */ MCD_OPC_Decode, 216, 11, 94, // Opcode: VQADDsv1i64 >+/* 8041 */ MCD_OPC_FilterValue, 243, 1, 102, 25, // Skip to: 14548 >+/* 8046 */ MCD_OPC_CheckPredicate, 15, 98, 25, // Skip to: 14548 >+/* 8050 */ MCD_OPC_Decode, 224, 11, 94, // Opcode: VQADDuv1i64 >+/* 8054 */ MCD_OPC_FilterValue, 1, 135, 0, // Skip to: 8193 >+/* 8058 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8061 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8094 >+/* 8065 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8068 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8081 >+/* 8073 */ MCD_OPC_CheckPredicate, 15, 71, 25, // Skip to: 14548 >+/* 8077 */ MCD_OPC_Decode, 212, 4, 94, // Opcode: VANDd >+/* 8081 */ MCD_OPC_FilterValue, 243, 1, 62, 25, // Skip to: 14548 >+/* 8086 */ MCD_OPC_CheckPredicate, 15, 58, 25, // Skip to: 14548 >+/* 8090 */ MCD_OPC_Decode, 142, 6, 94, // Opcode: VEORd >+/* 8094 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8127 >+/* 8098 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8101 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8114 >+/* 8106 */ MCD_OPC_CheckPredicate, 15, 38, 25, // Skip to: 14548 >+/* 8110 */ MCD_OPC_Decode, 214, 4, 94, // Opcode: VBICd >+/* 8114 */ MCD_OPC_FilterValue, 243, 1, 29, 25, // Skip to: 14548 >+/* 8119 */ MCD_OPC_CheckPredicate, 15, 25, 25, // Skip to: 14548 >+/* 8123 */ MCD_OPC_Decode, 224, 4, 102, // Opcode: VBSLd >+/* 8127 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8160 >+/* 8131 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8134 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8147 >+/* 8139 */ MCD_OPC_CheckPredicate, 15, 5, 25, // Skip to: 14548 >+/* 8143 */ MCD_OPC_Decode, 161, 11, 94, // Opcode: VORRd >+/* 8147 */ MCD_OPC_FilterValue, 243, 1, 252, 24, // Skip to: 14548 >+/* 8152 */ MCD_OPC_CheckPredicate, 15, 248, 24, // Skip to: 14548 >+/* 8156 */ MCD_OPC_Decode, 222, 4, 102, // Opcode: VBITd >+/* 8160 */ MCD_OPC_FilterValue, 3, 240, 24, // Skip to: 14548 >+/* 8164 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8167 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8180 >+/* 8172 */ MCD_OPC_CheckPredicate, 15, 228, 24, // Skip to: 14548 >+/* 8176 */ MCD_OPC_Decode, 159, 11, 94, // Opcode: VORNd >+/* 8180 */ MCD_OPC_FilterValue, 243, 1, 219, 24, // Skip to: 14548 >+/* 8185 */ MCD_OPC_CheckPredicate, 15, 215, 24, // Skip to: 14548 >+/* 8189 */ MCD_OPC_Decode, 220, 4, 102, // Opcode: VBIFd >+/* 8193 */ MCD_OPC_FilterValue, 2, 135, 0, // Skip to: 8332 >+/* 8197 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8200 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8233 >+/* 8204 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8207 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8220 >+/* 8212 */ MCD_OPC_CheckPredicate, 15, 188, 24, // Skip to: 14548 >+/* 8216 */ MCD_OPC_Decode, 227, 12, 94, // Opcode: VQSUBsv8i8 >+/* 8220 */ MCD_OPC_FilterValue, 243, 1, 179, 24, // Skip to: 14548 >+/* 8225 */ MCD_OPC_CheckPredicate, 15, 175, 24, // Skip to: 14548 >+/* 8229 */ MCD_OPC_Decode, 235, 12, 94, // Opcode: VQSUBuv8i8 >+/* 8233 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8266 >+/* 8237 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8240 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8253 >+/* 8245 */ MCD_OPC_CheckPredicate, 15, 155, 24, // Skip to: 14548 >+/* 8249 */ MCD_OPC_Decode, 224, 12, 94, // Opcode: VQSUBsv4i16 >+/* 8253 */ MCD_OPC_FilterValue, 243, 1, 146, 24, // Skip to: 14548 >+/* 8258 */ MCD_OPC_CheckPredicate, 15, 142, 24, // Skip to: 14548 >+/* 8262 */ MCD_OPC_Decode, 232, 12, 94, // Opcode: VQSUBuv4i16 >+/* 8266 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8299 >+/* 8270 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8273 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8286 >+/* 8278 */ MCD_OPC_CheckPredicate, 15, 122, 24, // Skip to: 14548 >+/* 8282 */ MCD_OPC_Decode, 222, 12, 94, // Opcode: VQSUBsv2i32 >+/* 8286 */ MCD_OPC_FilterValue, 243, 1, 113, 24, // Skip to: 14548 >+/* 8291 */ MCD_OPC_CheckPredicate, 15, 109, 24, // Skip to: 14548 >+/* 8295 */ MCD_OPC_Decode, 230, 12, 94, // Opcode: VQSUBuv2i32 >+/* 8299 */ MCD_OPC_FilterValue, 3, 101, 24, // Skip to: 14548 >+/* 8303 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8306 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8319 >+/* 8311 */ MCD_OPC_CheckPredicate, 15, 89, 24, // Skip to: 14548 >+/* 8315 */ MCD_OPC_Decode, 221, 12, 94, // Opcode: VQSUBsv1i64 >+/* 8319 */ MCD_OPC_FilterValue, 243, 1, 80, 24, // Skip to: 14548 >+/* 8324 */ MCD_OPC_CheckPredicate, 15, 76, 24, // Skip to: 14548 >+/* 8328 */ MCD_OPC_Decode, 229, 12, 94, // Opcode: VQSUBuv1i64 >+/* 8332 */ MCD_OPC_FilterValue, 3, 102, 0, // Skip to: 8438 >+/* 8336 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8339 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8372 >+/* 8343 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8346 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8359 >+/* 8351 */ MCD_OPC_CheckPredicate, 15, 49, 24, // Skip to: 14548 >+/* 8355 */ MCD_OPC_Decode, 249, 4, 94, // Opcode: VCGEsv8i8 >+/* 8359 */ MCD_OPC_FilterValue, 243, 1, 40, 24, // Skip to: 14548 >+/* 8364 */ MCD_OPC_CheckPredicate, 15, 36, 24, // Skip to: 14548 >+/* 8368 */ MCD_OPC_Decode, 255, 4, 94, // Opcode: VCGEuv8i8 >+/* 8372 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8405 >+/* 8376 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8379 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8392 >+/* 8384 */ MCD_OPC_CheckPredicate, 15, 16, 24, // Skip to: 14548 >+/* 8388 */ MCD_OPC_Decode, 246, 4, 94, // Opcode: VCGEsv4i16 >+/* 8392 */ MCD_OPC_FilterValue, 243, 1, 7, 24, // Skip to: 14548 >+/* 8397 */ MCD_OPC_CheckPredicate, 15, 3, 24, // Skip to: 14548 >+/* 8401 */ MCD_OPC_Decode, 252, 4, 94, // Opcode: VCGEuv4i16 >+/* 8405 */ MCD_OPC_FilterValue, 2, 251, 23, // Skip to: 14548 >+/* 8409 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8412 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8425 >+/* 8417 */ MCD_OPC_CheckPredicate, 15, 239, 23, // Skip to: 14548 >+/* 8421 */ MCD_OPC_Decode, 245, 4, 94, // Opcode: VCGEsv2i32 >+/* 8425 */ MCD_OPC_FilterValue, 243, 1, 230, 23, // Skip to: 14548 >+/* 8430 */ MCD_OPC_CheckPredicate, 15, 226, 23, // Skip to: 14548 >+/* 8434 */ MCD_OPC_Decode, 251, 4, 94, // Opcode: VCGEuv2i32 >+/* 8438 */ MCD_OPC_FilterValue, 4, 135, 0, // Skip to: 8577 >+/* 8442 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8445 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8478 >+/* 8449 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8452 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8465 >+/* 8457 */ MCD_OPC_CheckPredicate, 15, 199, 23, // Skip to: 14548 >+/* 8461 */ MCD_OPC_Decode, 194, 12, 98, // Opcode: VQSHLsv8i8 >+/* 8465 */ MCD_OPC_FilterValue, 243, 1, 190, 23, // Skip to: 14548 >+/* 8470 */ MCD_OPC_CheckPredicate, 15, 186, 23, // Skip to: 14548 >+/* 8474 */ MCD_OPC_Decode, 210, 12, 98, // Opcode: VQSHLuv8i8 >+/* 8478 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8511 >+/* 8482 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8485 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8498 >+/* 8490 */ MCD_OPC_CheckPredicate, 15, 166, 23, // Skip to: 14548 >+/* 8494 */ MCD_OPC_Decode, 191, 12, 98, // Opcode: VQSHLsv4i16 >+/* 8498 */ MCD_OPC_FilterValue, 243, 1, 157, 23, // Skip to: 14548 >+/* 8503 */ MCD_OPC_CheckPredicate, 15, 153, 23, // Skip to: 14548 >+/* 8507 */ MCD_OPC_Decode, 207, 12, 98, // Opcode: VQSHLuv4i16 >+/* 8511 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8544 >+/* 8515 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8518 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8531 >+/* 8523 */ MCD_OPC_CheckPredicate, 15, 133, 23, // Skip to: 14548 >+/* 8527 */ MCD_OPC_Decode, 189, 12, 98, // Opcode: VQSHLsv2i32 >+/* 8531 */ MCD_OPC_FilterValue, 243, 1, 124, 23, // Skip to: 14548 >+/* 8536 */ MCD_OPC_CheckPredicate, 15, 120, 23, // Skip to: 14548 >+/* 8540 */ MCD_OPC_Decode, 205, 12, 98, // Opcode: VQSHLuv2i32 >+/* 8544 */ MCD_OPC_FilterValue, 3, 112, 23, // Skip to: 14548 >+/* 8548 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8551 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8564 >+/* 8556 */ MCD_OPC_CheckPredicate, 15, 100, 23, // Skip to: 14548 >+/* 8560 */ MCD_OPC_Decode, 188, 12, 98, // Opcode: VQSHLsv1i64 >+/* 8564 */ MCD_OPC_FilterValue, 243, 1, 91, 23, // Skip to: 14548 >+/* 8569 */ MCD_OPC_CheckPredicate, 15, 87, 23, // Skip to: 14548 >+/* 8573 */ MCD_OPC_Decode, 204, 12, 98, // Opcode: VQSHLuv1i64 >+/* 8577 */ MCD_OPC_FilterValue, 5, 135, 0, // Skip to: 8716 >+/* 8581 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8584 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8617 >+/* 8588 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8591 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8604 >+/* 8596 */ MCD_OPC_CheckPredicate, 15, 60, 23, // Skip to: 14548 >+/* 8600 */ MCD_OPC_Decode, 153, 12, 98, // Opcode: VQRSHLsv8i8 >+/* 8604 */ MCD_OPC_FilterValue, 243, 1, 51, 23, // Skip to: 14548 >+/* 8609 */ MCD_OPC_CheckPredicate, 15, 47, 23, // Skip to: 14548 >+/* 8613 */ MCD_OPC_Decode, 161, 12, 98, // Opcode: VQRSHLuv8i8 >+/* 8617 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8650 >+/* 8621 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8624 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8637 >+/* 8629 */ MCD_OPC_CheckPredicate, 15, 27, 23, // Skip to: 14548 >+/* 8633 */ MCD_OPC_Decode, 150, 12, 98, // Opcode: VQRSHLsv4i16 >+/* 8637 */ MCD_OPC_FilterValue, 243, 1, 18, 23, // Skip to: 14548 >+/* 8642 */ MCD_OPC_CheckPredicate, 15, 14, 23, // Skip to: 14548 >+/* 8646 */ MCD_OPC_Decode, 158, 12, 98, // Opcode: VQRSHLuv4i16 >+/* 8650 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 8683 >+/* 8654 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8657 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8670 >+/* 8662 */ MCD_OPC_CheckPredicate, 15, 250, 22, // Skip to: 14548 >+/* 8666 */ MCD_OPC_Decode, 148, 12, 98, // Opcode: VQRSHLsv2i32 >+/* 8670 */ MCD_OPC_FilterValue, 243, 1, 241, 22, // Skip to: 14548 >+/* 8675 */ MCD_OPC_CheckPredicate, 15, 237, 22, // Skip to: 14548 >+/* 8679 */ MCD_OPC_Decode, 156, 12, 98, // Opcode: VQRSHLuv2i32 >+/* 8683 */ MCD_OPC_FilterValue, 3, 229, 22, // Skip to: 14548 >+/* 8687 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8690 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8703 >+/* 8695 */ MCD_OPC_CheckPredicate, 15, 217, 22, // Skip to: 14548 >+/* 8699 */ MCD_OPC_Decode, 147, 12, 98, // Opcode: VQRSHLsv1i64 >+/* 8703 */ MCD_OPC_FilterValue, 243, 1, 208, 22, // Skip to: 14548 >+/* 8708 */ MCD_OPC_CheckPredicate, 15, 204, 22, // Skip to: 14548 >+/* 8712 */ MCD_OPC_Decode, 155, 12, 98, // Opcode: VQRSHLuv1i64 >+/* 8716 */ MCD_OPC_FilterValue, 6, 102, 0, // Skip to: 8822 >+/* 8720 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8723 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8756 >+/* 8727 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8730 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8743 >+/* 8735 */ MCD_OPC_CheckPredicate, 15, 177, 22, // Skip to: 14548 >+/* 8739 */ MCD_OPC_Decode, 132, 10, 94, // Opcode: VMINsv8i8 >+/* 8743 */ MCD_OPC_FilterValue, 243, 1, 168, 22, // Skip to: 14548 >+/* 8748 */ MCD_OPC_CheckPredicate, 15, 164, 22, // Skip to: 14548 >+/* 8752 */ MCD_OPC_Decode, 138, 10, 94, // Opcode: VMINuv8i8 >+/* 8756 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8789 >+/* 8760 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8763 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8776 >+/* 8768 */ MCD_OPC_CheckPredicate, 15, 144, 22, // Skip to: 14548 >+/* 8772 */ MCD_OPC_Decode, 129, 10, 94, // Opcode: VMINsv4i16 >+/* 8776 */ MCD_OPC_FilterValue, 243, 1, 135, 22, // Skip to: 14548 >+/* 8781 */ MCD_OPC_CheckPredicate, 15, 131, 22, // Skip to: 14548 >+/* 8785 */ MCD_OPC_Decode, 135, 10, 94, // Opcode: VMINuv4i16 >+/* 8789 */ MCD_OPC_FilterValue, 2, 123, 22, // Skip to: 14548 >+/* 8793 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8796 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8809 >+/* 8801 */ MCD_OPC_CheckPredicate, 15, 111, 22, // Skip to: 14548 >+/* 8805 */ MCD_OPC_Decode, 128, 10, 94, // Opcode: VMINsv2i32 >+/* 8809 */ MCD_OPC_FilterValue, 243, 1, 102, 22, // Skip to: 14548 >+/* 8814 */ MCD_OPC_CheckPredicate, 15, 98, 22, // Skip to: 14548 >+/* 8818 */ MCD_OPC_Decode, 134, 10, 94, // Opcode: VMINuv2i32 >+/* 8822 */ MCD_OPC_FilterValue, 7, 102, 0, // Skip to: 8928 >+/* 8826 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8829 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8862 >+/* 8833 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8836 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8849 >+/* 8841 */ MCD_OPC_CheckPredicate, 15, 71, 22, // Skip to: 14548 >+/* 8845 */ MCD_OPC_Decode, 144, 4, 102, // Opcode: VABAsv8i8 >+/* 8849 */ MCD_OPC_FilterValue, 243, 1, 62, 22, // Skip to: 14548 >+/* 8854 */ MCD_OPC_CheckPredicate, 15, 58, 22, // Skip to: 14548 >+/* 8858 */ MCD_OPC_Decode, 150, 4, 102, // Opcode: VABAuv8i8 >+/* 8862 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 8895 >+/* 8866 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8869 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8882 >+/* 8874 */ MCD_OPC_CheckPredicate, 15, 38, 22, // Skip to: 14548 >+/* 8878 */ MCD_OPC_Decode, 141, 4, 102, // Opcode: VABAsv4i16 >+/* 8882 */ MCD_OPC_FilterValue, 243, 1, 29, 22, // Skip to: 14548 >+/* 8887 */ MCD_OPC_CheckPredicate, 15, 25, 22, // Skip to: 14548 >+/* 8891 */ MCD_OPC_Decode, 147, 4, 102, // Opcode: VABAuv4i16 >+/* 8895 */ MCD_OPC_FilterValue, 2, 17, 22, // Skip to: 14548 >+/* 8899 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8902 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8915 >+/* 8907 */ MCD_OPC_CheckPredicate, 15, 5, 22, // Skip to: 14548 >+/* 8911 */ MCD_OPC_Decode, 140, 4, 102, // Opcode: VABAsv2i32 >+/* 8915 */ MCD_OPC_FilterValue, 243, 1, 252, 21, // Skip to: 14548 >+/* 8920 */ MCD_OPC_CheckPredicate, 15, 248, 21, // Skip to: 14548 >+/* 8924 */ MCD_OPC_Decode, 146, 4, 102, // Opcode: VABAuv2i32 >+/* 8928 */ MCD_OPC_FilterValue, 8, 102, 0, // Skip to: 9034 >+/* 8932 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 8935 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 8968 >+/* 8939 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8942 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8955 >+/* 8947 */ MCD_OPC_CheckPredicate, 15, 221, 21, // Skip to: 14548 >+/* 8951 */ MCD_OPC_Decode, 201, 17, 94, // Opcode: VTSTv8i8 >+/* 8955 */ MCD_OPC_FilterValue, 243, 1, 212, 21, // Skip to: 14548 >+/* 8960 */ MCD_OPC_CheckPredicate, 15, 208, 21, // Skip to: 14548 >+/* 8964 */ MCD_OPC_Decode, 233, 4, 94, // Opcode: VCEQv8i8 >+/* 8968 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 9001 >+/* 8972 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 8975 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 8988 >+/* 8980 */ MCD_OPC_CheckPredicate, 15, 188, 21, // Skip to: 14548 >+/* 8984 */ MCD_OPC_Decode, 198, 17, 94, // Opcode: VTSTv4i16 >+/* 8988 */ MCD_OPC_FilterValue, 243, 1, 179, 21, // Skip to: 14548 >+/* 8993 */ MCD_OPC_CheckPredicate, 15, 175, 21, // Skip to: 14548 >+/* 8997 */ MCD_OPC_Decode, 230, 4, 94, // Opcode: VCEQv4i16 >+/* 9001 */ MCD_OPC_FilterValue, 2, 167, 21, // Skip to: 14548 >+/* 9005 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9008 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9021 >+/* 9013 */ MCD_OPC_CheckPredicate, 15, 155, 21, // Skip to: 14548 >+/* 9017 */ MCD_OPC_Decode, 197, 17, 94, // Opcode: VTSTv2i32 >+/* 9021 */ MCD_OPC_FilterValue, 243, 1, 146, 21, // Skip to: 14548 >+/* 9026 */ MCD_OPC_CheckPredicate, 15, 142, 21, // Skip to: 14548 >+/* 9030 */ MCD_OPC_Decode, 229, 4, 94, // Opcode: VCEQv2i32 >+/* 9034 */ MCD_OPC_FilterValue, 9, 74, 0, // Skip to: 9112 >+/* 9038 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9041 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9074 >+/* 9045 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9048 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9061 >+/* 9053 */ MCD_OPC_CheckPredicate, 15, 115, 21, // Skip to: 14548 >+/* 9057 */ MCD_OPC_Decode, 136, 11, 94, // Opcode: VMULv8i8 >+/* 9061 */ MCD_OPC_FilterValue, 243, 1, 106, 21, // Skip to: 14548 >+/* 9066 */ MCD_OPC_CheckPredicate, 15, 102, 21, // Skip to: 14548 >+/* 9070 */ MCD_OPC_Decode, 251, 10, 94, // Opcode: VMULpd >+/* 9074 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 9093 >+/* 9078 */ MCD_OPC_CheckPredicate, 15, 90, 21, // Skip to: 14548 >+/* 9082 */ MCD_OPC_CheckField, 24, 8, 242, 1, 83, 21, // Skip to: 14548 >+/* 9089 */ MCD_OPC_Decode, 133, 11, 94, // Opcode: VMULv4i16 >+/* 9093 */ MCD_OPC_FilterValue, 2, 75, 21, // Skip to: 14548 >+/* 9097 */ MCD_OPC_CheckPredicate, 15, 71, 21, // Skip to: 14548 >+/* 9101 */ MCD_OPC_CheckField, 24, 8, 242, 1, 64, 21, // Skip to: 14548 >+/* 9108 */ MCD_OPC_Decode, 132, 11, 94, // Opcode: VMULv2i32 >+/* 9112 */ MCD_OPC_FilterValue, 10, 102, 0, // Skip to: 9218 >+/* 9116 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9119 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9152 >+/* 9123 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9126 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9139 >+/* 9131 */ MCD_OPC_CheckPredicate, 15, 37, 21, // Skip to: 14548 >+/* 9135 */ MCD_OPC_Decode, 205, 11, 94, // Opcode: VPMINs8 >+/* 9139 */ MCD_OPC_FilterValue, 243, 1, 28, 21, // Skip to: 14548 >+/* 9144 */ MCD_OPC_CheckPredicate, 15, 24, 21, // Skip to: 14548 >+/* 9148 */ MCD_OPC_Decode, 208, 11, 94, // Opcode: VPMINu8 >+/* 9152 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 9185 >+/* 9156 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9159 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9172 >+/* 9164 */ MCD_OPC_CheckPredicate, 15, 4, 21, // Skip to: 14548 >+/* 9168 */ MCD_OPC_Decode, 203, 11, 94, // Opcode: VPMINs16 >+/* 9172 */ MCD_OPC_FilterValue, 243, 1, 251, 20, // Skip to: 14548 >+/* 9177 */ MCD_OPC_CheckPredicate, 15, 247, 20, // Skip to: 14548 >+/* 9181 */ MCD_OPC_Decode, 206, 11, 94, // Opcode: VPMINu16 >+/* 9185 */ MCD_OPC_FilterValue, 2, 239, 20, // Skip to: 14548 >+/* 9189 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9192 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9205 >+/* 9197 */ MCD_OPC_CheckPredicate, 15, 227, 20, // Skip to: 14548 >+/* 9201 */ MCD_OPC_Decode, 204, 11, 94, // Opcode: VPMINs32 >+/* 9205 */ MCD_OPC_FilterValue, 243, 1, 218, 20, // Skip to: 14548 >+/* 9210 */ MCD_OPC_CheckPredicate, 15, 214, 20, // Skip to: 14548 >+/* 9214 */ MCD_OPC_Decode, 207, 11, 94, // Opcode: VPMINu32 >+/* 9218 */ MCD_OPC_FilterValue, 11, 60, 0, // Skip to: 9282 >+/* 9222 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9225 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9244 >+/* 9229 */ MCD_OPC_CheckPredicate, 15, 195, 20, // Skip to: 14548 >+/* 9233 */ MCD_OPC_CheckField, 24, 8, 242, 1, 188, 20, // Skip to: 14548 >+/* 9240 */ MCD_OPC_Decode, 194, 11, 94, // Opcode: VPADDi8 >+/* 9244 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 9263 >+/* 9248 */ MCD_OPC_CheckPredicate, 15, 176, 20, // Skip to: 14548 >+/* 9252 */ MCD_OPC_CheckField, 24, 8, 242, 1, 169, 20, // Skip to: 14548 >+/* 9259 */ MCD_OPC_Decode, 192, 11, 94, // Opcode: VPADDi16 >+/* 9263 */ MCD_OPC_FilterValue, 2, 161, 20, // Skip to: 14548 >+/* 9267 */ MCD_OPC_CheckPredicate, 15, 157, 20, // Skip to: 14548 >+/* 9271 */ MCD_OPC_CheckField, 24, 8, 242, 1, 150, 20, // Skip to: 14548 >+/* 9278 */ MCD_OPC_Decode, 193, 11, 94, // Opcode: VPADDi32 >+/* 9282 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 9327 >+/* 9286 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9289 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9308 >+/* 9293 */ MCD_OPC_CheckPredicate, 18, 131, 20, // Skip to: 14548 >+/* 9297 */ MCD_OPC_CheckField, 24, 8, 242, 1, 124, 20, // Skip to: 14548 >+/* 9304 */ MCD_OPC_Decode, 153, 6, 102, // Opcode: VFMAfd >+/* 9308 */ MCD_OPC_FilterValue, 2, 116, 20, // Skip to: 14548 >+/* 9312 */ MCD_OPC_CheckPredicate, 18, 112, 20, // Skip to: 14548 >+/* 9316 */ MCD_OPC_CheckField, 24, 8, 242, 1, 105, 20, // Skip to: 14548 >+/* 9323 */ MCD_OPC_Decode, 157, 6, 102, // Opcode: VFMSfd >+/* 9327 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 9386 >+/* 9331 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9334 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 9367 >+/* 9338 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 9341 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 9354 >+/* 9346 */ MCD_OPC_CheckPredicate, 15, 78, 20, // Skip to: 14548 >+/* 9350 */ MCD_OPC_Decode, 151, 10, 102, // Opcode: VMLAfd >+/* 9354 */ MCD_OPC_FilterValue, 243, 1, 69, 20, // Skip to: 14548 >+/* 9359 */ MCD_OPC_CheckPredicate, 15, 65, 20, // Skip to: 14548 >+/* 9363 */ MCD_OPC_Decode, 249, 10, 94, // Opcode: VMULfd >+/* 9367 */ MCD_OPC_FilterValue, 2, 57, 20, // Skip to: 14548 >+/* 9371 */ MCD_OPC_CheckPredicate, 15, 53, 20, // Skip to: 14548 >+/* 9375 */ MCD_OPC_CheckField, 24, 8, 242, 1, 46, 20, // Skip to: 14548 >+/* 9382 */ MCD_OPC_Decode, 177, 10, 102, // Opcode: VMLSfd >+/* 9386 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 9431 >+/* 9390 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9393 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9412 >+/* 9397 */ MCD_OPC_CheckPredicate, 15, 27, 20, // Skip to: 14548 >+/* 9401 */ MCD_OPC_CheckField, 24, 8, 243, 1, 20, 20, // Skip to: 14548 >+/* 9408 */ MCD_OPC_Decode, 181, 4, 94, // Opcode: VACGEd >+/* 9412 */ MCD_OPC_FilterValue, 2, 12, 20, // Skip to: 14548 >+/* 9416 */ MCD_OPC_CheckPredicate, 15, 8, 20, // Skip to: 14548 >+/* 9420 */ MCD_OPC_CheckField, 24, 8, 243, 1, 1, 20, // Skip to: 14548 >+/* 9427 */ MCD_OPC_Decode, 183, 4, 94, // Opcode: VACGTd >+/* 9431 */ MCD_OPC_FilterValue, 15, 249, 19, // Skip to: 14548 >+/* 9435 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 9438 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9457 >+/* 9442 */ MCD_OPC_CheckPredicate, 15, 238, 19, // Skip to: 14548 >+/* 9446 */ MCD_OPC_CheckField, 24, 8, 242, 1, 231, 19, // Skip to: 14548 >+/* 9453 */ MCD_OPC_Decode, 243, 12, 94, // Opcode: VRECPSfd >+/* 9457 */ MCD_OPC_FilterValue, 2, 223, 19, // Skip to: 14548 >+/* 9461 */ MCD_OPC_CheckPredicate, 15, 219, 19, // Skip to: 14548 >+/* 9465 */ MCD_OPC_CheckField, 24, 8, 242, 1, 212, 19, // Skip to: 14548 >+/* 9472 */ MCD_OPC_Decode, 206, 13, 94, // Opcode: VRSQRTSfd >+/* 9476 */ MCD_OPC_FilterValue, 1, 204, 19, // Skip to: 14548 >+/* 9480 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 9483 */ MCD_OPC_FilterValue, 0, 138, 6, // Skip to: 11161 >+/* 9487 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... >+/* 9490 */ MCD_OPC_FilterValue, 121, 190, 19, // Skip to: 14548 >+/* 9494 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 9497 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 9622 >+/* 9501 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9504 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9589 >+/* 9508 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9511 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9556 >+/* 9515 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9518 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9537 >+/* 9522 */ MCD_OPC_CheckPredicate, 15, 190, 5, // Skip to: 10996 >+/* 9526 */ MCD_OPC_CheckField, 19, 1, 1, 184, 5, // Skip to: 10996 >+/* 9532 */ MCD_OPC_Decode, 153, 14, 139, 1, // Opcode: VSHRsv8i8 >+/* 9537 */ MCD_OPC_FilterValue, 1, 175, 5, // Skip to: 10996 >+/* 9541 */ MCD_OPC_CheckPredicate, 15, 171, 5, // Skip to: 10996 >+/* 9545 */ MCD_OPC_CheckField, 19, 1, 1, 165, 5, // Skip to: 10996 >+/* 9551 */ MCD_OPC_Decode, 161, 14, 139, 1, // Opcode: VSHRuv8i8 >+/* 9556 */ MCD_OPC_FilterValue, 1, 156, 5, // Skip to: 10996 >+/* 9560 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9563 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9576 >+/* 9567 */ MCD_OPC_CheckPredicate, 15, 145, 5, // Skip to: 10996 >+/* 9571 */ MCD_OPC_Decode, 150, 14, 140, 1, // Opcode: VSHRsv4i16 >+/* 9576 */ MCD_OPC_FilterValue, 1, 136, 5, // Skip to: 10996 >+/* 9580 */ MCD_OPC_CheckPredicate, 15, 132, 5, // Skip to: 10996 >+/* 9584 */ MCD_OPC_Decode, 158, 14, 140, 1, // Opcode: VSHRuv4i16 >+/* 9589 */ MCD_OPC_FilterValue, 1, 123, 5, // Skip to: 10996 >+/* 9593 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9596 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9609 >+/* 9600 */ MCD_OPC_CheckPredicate, 15, 112, 5, // Skip to: 10996 >+/* 9604 */ MCD_OPC_Decode, 148, 14, 141, 1, // Opcode: VSHRsv2i32 >+/* 9609 */ MCD_OPC_FilterValue, 1, 103, 5, // Skip to: 10996 >+/* 9613 */ MCD_OPC_CheckPredicate, 15, 99, 5, // Skip to: 10996 >+/* 9617 */ MCD_OPC_Decode, 156, 14, 141, 1, // Opcode: VSHRuv2i32 >+/* 9622 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 9747 >+/* 9626 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9629 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9714 >+/* 9633 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9636 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9681 >+/* 9640 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9643 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9662 >+/* 9647 */ MCD_OPC_CheckPredicate, 15, 65, 5, // Skip to: 10996 >+/* 9651 */ MCD_OPC_CheckField, 19, 1, 1, 59, 5, // Skip to: 10996 >+/* 9657 */ MCD_OPC_Decode, 185, 14, 142, 1, // Opcode: VSRAsv8i8 >+/* 9662 */ MCD_OPC_FilterValue, 1, 50, 5, // Skip to: 10996 >+/* 9666 */ MCD_OPC_CheckPredicate, 15, 46, 5, // Skip to: 10996 >+/* 9670 */ MCD_OPC_CheckField, 19, 1, 1, 40, 5, // Skip to: 10996 >+/* 9676 */ MCD_OPC_Decode, 193, 14, 142, 1, // Opcode: VSRAuv8i8 >+/* 9681 */ MCD_OPC_FilterValue, 1, 31, 5, // Skip to: 10996 >+/* 9685 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9688 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9701 >+/* 9692 */ MCD_OPC_CheckPredicate, 15, 20, 5, // Skip to: 10996 >+/* 9696 */ MCD_OPC_Decode, 182, 14, 143, 1, // Opcode: VSRAsv4i16 >+/* 9701 */ MCD_OPC_FilterValue, 1, 11, 5, // Skip to: 10996 >+/* 9705 */ MCD_OPC_CheckPredicate, 15, 7, 5, // Skip to: 10996 >+/* 9709 */ MCD_OPC_Decode, 190, 14, 143, 1, // Opcode: VSRAuv4i16 >+/* 9714 */ MCD_OPC_FilterValue, 1, 254, 4, // Skip to: 10996 >+/* 9718 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9721 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9734 >+/* 9725 */ MCD_OPC_CheckPredicate, 15, 243, 4, // Skip to: 10996 >+/* 9729 */ MCD_OPC_Decode, 180, 14, 144, 1, // Opcode: VSRAsv2i32 >+/* 9734 */ MCD_OPC_FilterValue, 1, 234, 4, // Skip to: 10996 >+/* 9738 */ MCD_OPC_CheckPredicate, 15, 230, 4, // Skip to: 10996 >+/* 9742 */ MCD_OPC_Decode, 188, 14, 144, 1, // Opcode: VSRAuv2i32 >+/* 9747 */ MCD_OPC_FilterValue, 2, 121, 0, // Skip to: 9872 >+/* 9751 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9754 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9839 >+/* 9758 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9761 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9806 >+/* 9765 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9768 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9787 >+/* 9772 */ MCD_OPC_CheckPredicate, 15, 196, 4, // Skip to: 10996 >+/* 9776 */ MCD_OPC_CheckField, 19, 1, 1, 190, 4, // Skip to: 10996 >+/* 9782 */ MCD_OPC_Decode, 193, 13, 139, 1, // Opcode: VRSHRsv8i8 >+/* 9787 */ MCD_OPC_FilterValue, 1, 181, 4, // Skip to: 10996 >+/* 9791 */ MCD_OPC_CheckPredicate, 15, 177, 4, // Skip to: 10996 >+/* 9795 */ MCD_OPC_CheckField, 19, 1, 1, 171, 4, // Skip to: 10996 >+/* 9801 */ MCD_OPC_Decode, 201, 13, 139, 1, // Opcode: VRSHRuv8i8 >+/* 9806 */ MCD_OPC_FilterValue, 1, 162, 4, // Skip to: 10996 >+/* 9810 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9813 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9826 >+/* 9817 */ MCD_OPC_CheckPredicate, 15, 151, 4, // Skip to: 10996 >+/* 9821 */ MCD_OPC_Decode, 190, 13, 140, 1, // Opcode: VRSHRsv4i16 >+/* 9826 */ MCD_OPC_FilterValue, 1, 142, 4, // Skip to: 10996 >+/* 9830 */ MCD_OPC_CheckPredicate, 15, 138, 4, // Skip to: 10996 >+/* 9834 */ MCD_OPC_Decode, 198, 13, 140, 1, // Opcode: VRSHRuv4i16 >+/* 9839 */ MCD_OPC_FilterValue, 1, 129, 4, // Skip to: 10996 >+/* 9843 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9859 >+/* 9850 */ MCD_OPC_CheckPredicate, 15, 118, 4, // Skip to: 10996 >+/* 9854 */ MCD_OPC_Decode, 188, 13, 141, 1, // Opcode: VRSHRsv2i32 >+/* 9859 */ MCD_OPC_FilterValue, 1, 109, 4, // Skip to: 10996 >+/* 9863 */ MCD_OPC_CheckPredicate, 15, 105, 4, // Skip to: 10996 >+/* 9867 */ MCD_OPC_Decode, 196, 13, 141, 1, // Opcode: VRSHRuv2i32 >+/* 9872 */ MCD_OPC_FilterValue, 3, 121, 0, // Skip to: 9997 >+/* 9876 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 9879 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 9964 >+/* 9883 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 9886 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 9931 >+/* 9890 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9893 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 9912 >+/* 9897 */ MCD_OPC_CheckPredicate, 15, 71, 4, // Skip to: 10996 >+/* 9901 */ MCD_OPC_CheckField, 19, 1, 1, 65, 4, // Skip to: 10996 >+/* 9907 */ MCD_OPC_Decode, 215, 13, 142, 1, // Opcode: VRSRAsv8i8 >+/* 9912 */ MCD_OPC_FilterValue, 1, 56, 4, // Skip to: 10996 >+/* 9916 */ MCD_OPC_CheckPredicate, 15, 52, 4, // Skip to: 10996 >+/* 9920 */ MCD_OPC_CheckField, 19, 1, 1, 46, 4, // Skip to: 10996 >+/* 9926 */ MCD_OPC_Decode, 223, 13, 142, 1, // Opcode: VRSRAuv8i8 >+/* 9931 */ MCD_OPC_FilterValue, 1, 37, 4, // Skip to: 10996 >+/* 9935 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9938 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9951 >+/* 9942 */ MCD_OPC_CheckPredicate, 15, 26, 4, // Skip to: 10996 >+/* 9946 */ MCD_OPC_Decode, 212, 13, 143, 1, // Opcode: VRSRAsv4i16 >+/* 9951 */ MCD_OPC_FilterValue, 1, 17, 4, // Skip to: 10996 >+/* 9955 */ MCD_OPC_CheckPredicate, 15, 13, 4, // Skip to: 10996 >+/* 9959 */ MCD_OPC_Decode, 220, 13, 143, 1, // Opcode: VRSRAuv4i16 >+/* 9964 */ MCD_OPC_FilterValue, 1, 4, 4, // Skip to: 10996 >+/* 9968 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 9971 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9984 >+/* 9975 */ MCD_OPC_CheckPredicate, 15, 249, 3, // Skip to: 10996 >+/* 9979 */ MCD_OPC_Decode, 210, 13, 144, 1, // Opcode: VRSRAsv2i32 >+/* 9984 */ MCD_OPC_FilterValue, 1, 240, 3, // Skip to: 10996 >+/* 9988 */ MCD_OPC_CheckPredicate, 15, 236, 3, // Skip to: 10996 >+/* 9992 */ MCD_OPC_Decode, 218, 13, 144, 1, // Opcode: VRSRAuv2i32 >+/* 9997 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 10074 >+/* 10001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10004 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 10055 >+/* 10008 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10011 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 10036 >+/* 10015 */ MCD_OPC_CheckPredicate, 15, 209, 3, // Skip to: 10996 >+/* 10019 */ MCD_OPC_CheckField, 24, 1, 1, 203, 3, // Skip to: 10996 >+/* 10025 */ MCD_OPC_CheckField, 19, 1, 1, 197, 3, // Skip to: 10996 >+/* 10031 */ MCD_OPC_Decode, 201, 14, 142, 1, // Opcode: VSRIv8i8 >+/* 10036 */ MCD_OPC_FilterValue, 1, 188, 3, // Skip to: 10996 >+/* 10040 */ MCD_OPC_CheckPredicate, 15, 184, 3, // Skip to: 10996 >+/* 10044 */ MCD_OPC_CheckField, 24, 1, 1, 178, 3, // Skip to: 10996 >+/* 10050 */ MCD_OPC_Decode, 198, 14, 143, 1, // Opcode: VSRIv4i16 >+/* 10055 */ MCD_OPC_FilterValue, 1, 169, 3, // Skip to: 10996 >+/* 10059 */ MCD_OPC_CheckPredicate, 15, 165, 3, // Skip to: 10996 >+/* 10063 */ MCD_OPC_CheckField, 24, 1, 1, 159, 3, // Skip to: 10996 >+/* 10069 */ MCD_OPC_Decode, 196, 14, 144, 1, // Opcode: VSRIv2i32 >+/* 10074 */ MCD_OPC_FilterValue, 5, 121, 0, // Skip to: 10199 >+/* 10078 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10081 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10166 >+/* 10085 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10088 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10133 >+/* 10092 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10095 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10114 >+/* 10099 */ MCD_OPC_CheckPredicate, 15, 125, 3, // Skip to: 10996 >+/* 10103 */ MCD_OPC_CheckField, 19, 1, 1, 119, 3, // Skip to: 10996 >+/* 10109 */ MCD_OPC_Decode, 254, 13, 145, 1, // Opcode: VSHLiv8i8 >+/* 10114 */ MCD_OPC_FilterValue, 1, 110, 3, // Skip to: 10996 >+/* 10118 */ MCD_OPC_CheckPredicate, 15, 106, 3, // Skip to: 10996 >+/* 10122 */ MCD_OPC_CheckField, 19, 1, 1, 100, 3, // Skip to: 10996 >+/* 10128 */ MCD_OPC_Decode, 173, 14, 146, 1, // Opcode: VSLIv8i8 >+/* 10133 */ MCD_OPC_FilterValue, 1, 91, 3, // Skip to: 10996 >+/* 10137 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10140 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10153 >+/* 10144 */ MCD_OPC_CheckPredicate, 15, 80, 3, // Skip to: 10996 >+/* 10148 */ MCD_OPC_Decode, 251, 13, 147, 1, // Opcode: VSHLiv4i16 >+/* 10153 */ MCD_OPC_FilterValue, 1, 71, 3, // Skip to: 10996 >+/* 10157 */ MCD_OPC_CheckPredicate, 15, 67, 3, // Skip to: 10996 >+/* 10161 */ MCD_OPC_Decode, 170, 14, 148, 1, // Opcode: VSLIv4i16 >+/* 10166 */ MCD_OPC_FilterValue, 1, 58, 3, // Skip to: 10996 >+/* 10170 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10173 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10186 >+/* 10177 */ MCD_OPC_CheckPredicate, 15, 47, 3, // Skip to: 10996 >+/* 10181 */ MCD_OPC_Decode, 249, 13, 149, 1, // Opcode: VSHLiv2i32 >+/* 10186 */ MCD_OPC_FilterValue, 1, 38, 3, // Skip to: 10996 >+/* 10190 */ MCD_OPC_CheckPredicate, 15, 34, 3, // Skip to: 10996 >+/* 10194 */ MCD_OPC_Decode, 168, 14, 150, 1, // Opcode: VSLIv2i32 >+/* 10199 */ MCD_OPC_FilterValue, 6, 73, 0, // Skip to: 10276 >+/* 10203 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10206 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 10257 >+/* 10210 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10213 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 10238 >+/* 10217 */ MCD_OPC_CheckPredicate, 15, 7, 3, // Skip to: 10996 >+/* 10221 */ MCD_OPC_CheckField, 24, 1, 1, 1, 3, // Skip to: 10996 >+/* 10227 */ MCD_OPC_CheckField, 19, 1, 1, 251, 2, // Skip to: 10996 >+/* 10233 */ MCD_OPC_Decode, 186, 12, 145, 1, // Opcode: VQSHLsuv8i8 >+/* 10238 */ MCD_OPC_FilterValue, 1, 242, 2, // Skip to: 10996 >+/* 10242 */ MCD_OPC_CheckPredicate, 15, 238, 2, // Skip to: 10996 >+/* 10246 */ MCD_OPC_CheckField, 24, 1, 1, 232, 2, // Skip to: 10996 >+/* 10252 */ MCD_OPC_Decode, 183, 12, 147, 1, // Opcode: VQSHLsuv4i16 >+/* 10257 */ MCD_OPC_FilterValue, 1, 223, 2, // Skip to: 10996 >+/* 10261 */ MCD_OPC_CheckPredicate, 15, 219, 2, // Skip to: 10996 >+/* 10265 */ MCD_OPC_CheckField, 24, 1, 1, 213, 2, // Skip to: 10996 >+/* 10271 */ MCD_OPC_Decode, 181, 12, 149, 1, // Opcode: VQSHLsuv2i32 >+/* 10276 */ MCD_OPC_FilterValue, 7, 121, 0, // Skip to: 10401 >+/* 10280 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10283 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10368 >+/* 10287 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10290 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10335 >+/* 10294 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10297 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10316 >+/* 10301 */ MCD_OPC_CheckPredicate, 15, 179, 2, // Skip to: 10996 >+/* 10305 */ MCD_OPC_CheckField, 19, 1, 1, 173, 2, // Skip to: 10996 >+/* 10311 */ MCD_OPC_Decode, 178, 12, 145, 1, // Opcode: VQSHLsiv8i8 >+/* 10316 */ MCD_OPC_FilterValue, 1, 164, 2, // Skip to: 10996 >+/* 10320 */ MCD_OPC_CheckPredicate, 15, 160, 2, // Skip to: 10996 >+/* 10324 */ MCD_OPC_CheckField, 19, 1, 1, 154, 2, // Skip to: 10996 >+/* 10330 */ MCD_OPC_Decode, 202, 12, 145, 1, // Opcode: VQSHLuiv8i8 >+/* 10335 */ MCD_OPC_FilterValue, 1, 145, 2, // Skip to: 10996 >+/* 10339 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10342 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10355 >+/* 10346 */ MCD_OPC_CheckPredicate, 15, 134, 2, // Skip to: 10996 >+/* 10350 */ MCD_OPC_Decode, 175, 12, 147, 1, // Opcode: VQSHLsiv4i16 >+/* 10355 */ MCD_OPC_FilterValue, 1, 125, 2, // Skip to: 10996 >+/* 10359 */ MCD_OPC_CheckPredicate, 15, 121, 2, // Skip to: 10996 >+/* 10363 */ MCD_OPC_Decode, 199, 12, 147, 1, // Opcode: VQSHLuiv4i16 >+/* 10368 */ MCD_OPC_FilterValue, 1, 112, 2, // Skip to: 10996 >+/* 10372 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10375 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10388 >+/* 10379 */ MCD_OPC_CheckPredicate, 15, 101, 2, // Skip to: 10996 >+/* 10383 */ MCD_OPC_Decode, 173, 12, 149, 1, // Opcode: VQSHLsiv2i32 >+/* 10388 */ MCD_OPC_FilterValue, 1, 92, 2, // Skip to: 10996 >+/* 10392 */ MCD_OPC_CheckPredicate, 15, 88, 2, // Skip to: 10996 >+/* 10396 */ MCD_OPC_Decode, 197, 12, 149, 1, // Opcode: VQSHLuiv2i32 >+/* 10401 */ MCD_OPC_FilterValue, 8, 121, 0, // Skip to: 10526 >+/* 10405 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10408 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10493 >+/* 10412 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10415 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10460 >+/* 10419 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10422 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10441 >+/* 10426 */ MCD_OPC_CheckPredicate, 15, 54, 2, // Skip to: 10996 >+/* 10430 */ MCD_OPC_CheckField, 19, 1, 1, 48, 2, // Skip to: 10996 >+/* 10436 */ MCD_OPC_Decode, 145, 14, 151, 1, // Opcode: VSHRNv8i8 >+/* 10441 */ MCD_OPC_FilterValue, 1, 39, 2, // Skip to: 10996 >+/* 10445 */ MCD_OPC_CheckPredicate, 15, 35, 2, // Skip to: 10996 >+/* 10449 */ MCD_OPC_CheckField, 19, 1, 1, 29, 2, // Skip to: 10996 >+/* 10455 */ MCD_OPC_Decode, 219, 12, 151, 1, // Opcode: VQSHRUNv8i8 >+/* 10460 */ MCD_OPC_FilterValue, 1, 20, 2, // Skip to: 10996 >+/* 10464 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10467 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10480 >+/* 10471 */ MCD_OPC_CheckPredicate, 15, 9, 2, // Skip to: 10996 >+/* 10475 */ MCD_OPC_Decode, 144, 14, 152, 1, // Opcode: VSHRNv4i16 >+/* 10480 */ MCD_OPC_FilterValue, 1, 0, 2, // Skip to: 10996 >+/* 10484 */ MCD_OPC_CheckPredicate, 15, 252, 1, // Skip to: 10996 >+/* 10488 */ MCD_OPC_Decode, 218, 12, 152, 1, // Opcode: VQSHRUNv4i16 >+/* 10493 */ MCD_OPC_FilterValue, 1, 243, 1, // Skip to: 10996 >+/* 10497 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10500 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10513 >+/* 10504 */ MCD_OPC_CheckPredicate, 15, 232, 1, // Skip to: 10996 >+/* 10508 */ MCD_OPC_Decode, 143, 14, 153, 1, // Opcode: VSHRNv2i32 >+/* 10513 */ MCD_OPC_FilterValue, 1, 223, 1, // Skip to: 10996 >+/* 10517 */ MCD_OPC_CheckPredicate, 15, 219, 1, // Skip to: 10996 >+/* 10521 */ MCD_OPC_Decode, 217, 12, 153, 1, // Opcode: VQSHRUNv2i32 >+/* 10526 */ MCD_OPC_FilterValue, 9, 121, 0, // Skip to: 10651 >+/* 10530 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10533 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 10618 >+/* 10537 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10540 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 10585 >+/* 10544 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10547 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10566 >+/* 10551 */ MCD_OPC_CheckPredicate, 15, 185, 1, // Skip to: 10996 >+/* 10555 */ MCD_OPC_CheckField, 19, 1, 1, 179, 1, // Skip to: 10996 >+/* 10561 */ MCD_OPC_Decode, 213, 12, 151, 1, // Opcode: VQSHRNsv8i8 >+/* 10566 */ MCD_OPC_FilterValue, 1, 170, 1, // Skip to: 10996 >+/* 10570 */ MCD_OPC_CheckPredicate, 15, 166, 1, // Skip to: 10996 >+/* 10574 */ MCD_OPC_CheckField, 19, 1, 1, 160, 1, // Skip to: 10996 >+/* 10580 */ MCD_OPC_Decode, 216, 12, 151, 1, // Opcode: VQSHRNuv8i8 >+/* 10585 */ MCD_OPC_FilterValue, 1, 151, 1, // Skip to: 10996 >+/* 10589 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10592 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10605 >+/* 10596 */ MCD_OPC_CheckPredicate, 15, 140, 1, // Skip to: 10996 >+/* 10600 */ MCD_OPC_Decode, 212, 12, 152, 1, // Opcode: VQSHRNsv4i16 >+/* 10605 */ MCD_OPC_FilterValue, 1, 131, 1, // Skip to: 10996 >+/* 10609 */ MCD_OPC_CheckPredicate, 15, 127, 1, // Skip to: 10996 >+/* 10613 */ MCD_OPC_Decode, 215, 12, 152, 1, // Opcode: VQSHRNuv4i16 >+/* 10618 */ MCD_OPC_FilterValue, 1, 118, 1, // Skip to: 10996 >+/* 10622 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10625 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10638 >+/* 10629 */ MCD_OPC_CheckPredicate, 15, 107, 1, // Skip to: 10996 >+/* 10633 */ MCD_OPC_Decode, 211, 12, 153, 1, // Opcode: VQSHRNsv2i32 >+/* 10638 */ MCD_OPC_FilterValue, 1, 98, 1, // Skip to: 10996 >+/* 10642 */ MCD_OPC_CheckPredicate, 15, 94, 1, // Skip to: 10996 >+/* 10646 */ MCD_OPC_Decode, 214, 12, 153, 1, // Opcode: VQSHRNuv2i32 >+/* 10651 */ MCD_OPC_FilterValue, 10, 213, 0, // Skip to: 10868 >+/* 10655 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 10658 */ MCD_OPC_FilterValue, 0, 143, 0, // Skip to: 10805 >+/* 10662 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 10665 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 10742 >+/* 10669 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10672 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 10707 >+/* 10676 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 10679 */ MCD_OPC_FilterValue, 1, 57, 1, // Skip to: 10996 >+/* 10683 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10698 >+/* 10687 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, // Skip to: 10698 >+/* 10693 */ MCD_OPC_Decode, 197, 10, 131, 1, // Opcode: VMOVLsv8i16 >+/* 10698 */ MCD_OPC_CheckPredicate, 15, 38, 1, // Skip to: 10996 >+/* 10702 */ MCD_OPC_Decode, 243, 13, 154, 1, // Opcode: VSHLLsv8i16 >+/* 10707 */ MCD_OPC_FilterValue, 1, 29, 1, // Skip to: 10996 >+/* 10711 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... >+/* 10714 */ MCD_OPC_FilterValue, 1, 22, 1, // Skip to: 10996 >+/* 10718 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10733 >+/* 10722 */ MCD_OPC_CheckField, 16, 3, 0, 5, 0, // Skip to: 10733 >+/* 10728 */ MCD_OPC_Decode, 200, 10, 131, 1, // Opcode: VMOVLuv8i16 >+/* 10733 */ MCD_OPC_CheckPredicate, 15, 3, 1, // Skip to: 10996 >+/* 10737 */ MCD_OPC_Decode, 246, 13, 154, 1, // Opcode: VSHLLuv8i16 >+/* 10742 */ MCD_OPC_FilterValue, 1, 250, 0, // Skip to: 10996 >+/* 10746 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10749 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 10777 >+/* 10753 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10768 >+/* 10757 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, // Skip to: 10768 >+/* 10763 */ MCD_OPC_Decode, 196, 10, 131, 1, // Opcode: VMOVLsv4i32 >+/* 10768 */ MCD_OPC_CheckPredicate, 15, 224, 0, // Skip to: 10996 >+/* 10772 */ MCD_OPC_Decode, 242, 13, 155, 1, // Opcode: VSHLLsv4i32 >+/* 10777 */ MCD_OPC_FilterValue, 1, 215, 0, // Skip to: 10996 >+/* 10781 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10796 >+/* 10785 */ MCD_OPC_CheckField, 16, 4, 0, 5, 0, // Skip to: 10796 >+/* 10791 */ MCD_OPC_Decode, 199, 10, 131, 1, // Opcode: VMOVLuv4i32 >+/* 10796 */ MCD_OPC_CheckPredicate, 15, 196, 0, // Skip to: 10996 >+/* 10800 */ MCD_OPC_Decode, 245, 13, 155, 1, // Opcode: VSHLLuv4i32 >+/* 10805 */ MCD_OPC_FilterValue, 1, 187, 0, // Skip to: 10996 >+/* 10809 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10812 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 10840 >+/* 10816 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10831 >+/* 10820 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, // Skip to: 10831 >+/* 10826 */ MCD_OPC_Decode, 195, 10, 131, 1, // Opcode: VMOVLsv2i64 >+/* 10831 */ MCD_OPC_CheckPredicate, 15, 161, 0, // Skip to: 10996 >+/* 10835 */ MCD_OPC_Decode, 241, 13, 156, 1, // Opcode: VSHLLsv2i64 >+/* 10840 */ MCD_OPC_FilterValue, 1, 152, 0, // Skip to: 10996 >+/* 10844 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10859 >+/* 10848 */ MCD_OPC_CheckField, 16, 5, 0, 5, 0, // Skip to: 10859 >+/* 10854 */ MCD_OPC_Decode, 198, 10, 131, 1, // Opcode: VMOVLuv2i64 >+/* 10859 */ MCD_OPC_CheckPredicate, 15, 133, 0, // Skip to: 10996 >+/* 10863 */ MCD_OPC_Decode, 244, 13, 156, 1, // Opcode: VSHLLuv2i64 >+/* 10868 */ MCD_OPC_FilterValue, 14, 70, 0, // Skip to: 10942 >+/* 10872 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 10875 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10894 >+/* 10879 */ MCD_OPC_CheckPredicate, 15, 30, 0, // Skip to: 10913 >+/* 10883 */ MCD_OPC_CheckField, 19, 3, 0, 24, 0, // Skip to: 10913 >+/* 10889 */ MCD_OPC_Decode, 221, 10, 157, 1, // Opcode: VMOVv8i8 >+/* 10894 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 10913 >+/* 10898 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 10913 >+/* 10902 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, // Skip to: 10913 >+/* 10908 */ MCD_OPC_Decode, 213, 10, 157, 1, // Opcode: VMOVv1i64 >+/* 10913 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10916 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10929 >+/* 10920 */ MCD_OPC_CheckPredicate, 15, 72, 0, // Skip to: 10996 >+/* 10924 */ MCD_OPC_Decode, 252, 5, 158, 1, // Opcode: VCVTxs2fd >+/* 10929 */ MCD_OPC_FilterValue, 1, 63, 0, // Skip to: 10996 >+/* 10933 */ MCD_OPC_CheckPredicate, 15, 59, 0, // Skip to: 10996 >+/* 10937 */ MCD_OPC_Decode, 254, 5, 158, 1, // Opcode: VCVTxu2fd >+/* 10942 */ MCD_OPC_FilterValue, 15, 50, 0, // Skip to: 10996 >+/* 10946 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 10949 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10962 >+/* 10953 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 10975 >+/* 10957 */ MCD_OPC_Decode, 243, 5, 158, 1, // Opcode: VCVTf2xsd >+/* 10962 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10975 >+/* 10966 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 10975 >+/* 10970 */ MCD_OPC_Decode, 245, 5, 158, 1, // Opcode: VCVTf2xud >+/* 10975 */ MCD_OPC_CheckPredicate, 15, 17, 0, // Skip to: 10996 >+/* 10979 */ MCD_OPC_CheckField, 19, 3, 0, 11, 0, // Skip to: 10996 >+/* 10985 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 10996 >+/* 10991 */ MCD_OPC_Decode, 214, 10, 157, 1, // Opcode: VMOVv2f32 >+/* 10996 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 10999 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 11080 >+/* 11003 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 11006 */ MCD_OPC_FilterValue, 0, 210, 13, // Skip to: 14548 >+/* 11010 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 11013 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11032 >+/* 11017 */ MCD_OPC_CheckPredicate, 15, 50, 0, // Skip to: 11071 >+/* 11021 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 11071 >+/* 11027 */ MCD_OPC_Decode, 218, 10, 157, 1, // Opcode: VMOVv4i16 >+/* 11032 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 11071 >+/* 11036 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 11039 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11052 >+/* 11043 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 11071 >+/* 11047 */ MCD_OPC_Decode, 162, 11, 157, 1, // Opcode: VORRiv2i32 >+/* 11052 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11071 >+/* 11056 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 11071 >+/* 11060 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 11071 >+/* 11066 */ MCD_OPC_Decode, 163, 11, 157, 1, // Opcode: VORRiv4i16 >+/* 11071 */ MCD_OPC_CheckPredicate, 15, 145, 13, // Skip to: 14548 >+/* 11075 */ MCD_OPC_Decode, 215, 10, 157, 1, // Opcode: VMOVv2i32 >+/* 11080 */ MCD_OPC_FilterValue, 1, 136, 13, // Skip to: 14548 >+/* 11084 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 11087 */ MCD_OPC_FilterValue, 0, 129, 13, // Skip to: 14548 >+/* 11091 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 11094 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11113 >+/* 11098 */ MCD_OPC_CheckPredicate, 15, 50, 0, // Skip to: 11152 >+/* 11102 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 11152 >+/* 11108 */ MCD_OPC_Decode, 140, 11, 157, 1, // Opcode: VMVNv4i16 >+/* 11113 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 11152 >+/* 11117 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 11120 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11133 >+/* 11124 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 11152 >+/* 11128 */ MCD_OPC_Decode, 215, 4, 157, 1, // Opcode: VBICiv2i32 >+/* 11133 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11152 >+/* 11137 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 11152 >+/* 11141 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 11152 >+/* 11147 */ MCD_OPC_Decode, 216, 4, 157, 1, // Opcode: VBICiv4i16 >+/* 11152 */ MCD_OPC_CheckPredicate, 15, 64, 13, // Skip to: 14548 >+/* 11156 */ MCD_OPC_Decode, 139, 11, 157, 1, // Opcode: VMVNv2i32 >+/* 11161 */ MCD_OPC_FilterValue, 1, 55, 13, // Skip to: 14548 >+/* 11165 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 11168 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 11203 >+/* 11172 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11175 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11189 >+/* 11180 */ MCD_OPC_CheckPredicate, 15, 36, 13, // Skip to: 14548 >+/* 11184 */ MCD_OPC_Decode, 147, 14, 159, 1, // Opcode: VSHRsv1i64 >+/* 11189 */ MCD_OPC_FilterValue, 243, 1, 26, 13, // Skip to: 14548 >+/* 11194 */ MCD_OPC_CheckPredicate, 15, 22, 13, // Skip to: 14548 >+/* 11198 */ MCD_OPC_Decode, 155, 14, 159, 1, // Opcode: VSHRuv1i64 >+/* 11203 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 11238 >+/* 11207 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11210 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11224 >+/* 11215 */ MCD_OPC_CheckPredicate, 15, 1, 13, // Skip to: 14548 >+/* 11219 */ MCD_OPC_Decode, 179, 14, 160, 1, // Opcode: VSRAsv1i64 >+/* 11224 */ MCD_OPC_FilterValue, 243, 1, 247, 12, // Skip to: 14548 >+/* 11229 */ MCD_OPC_CheckPredicate, 15, 243, 12, // Skip to: 14548 >+/* 11233 */ MCD_OPC_Decode, 187, 14, 160, 1, // Opcode: VSRAuv1i64 >+/* 11238 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 11273 >+/* 11242 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11245 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11259 >+/* 11250 */ MCD_OPC_CheckPredicate, 15, 222, 12, // Skip to: 14548 >+/* 11254 */ MCD_OPC_Decode, 187, 13, 159, 1, // Opcode: VRSHRsv1i64 >+/* 11259 */ MCD_OPC_FilterValue, 243, 1, 212, 12, // Skip to: 14548 >+/* 11264 */ MCD_OPC_CheckPredicate, 15, 208, 12, // Skip to: 14548 >+/* 11268 */ MCD_OPC_Decode, 195, 13, 159, 1, // Opcode: VRSHRuv1i64 >+/* 11273 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 11308 >+/* 11277 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11280 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11294 >+/* 11285 */ MCD_OPC_CheckPredicate, 15, 187, 12, // Skip to: 14548 >+/* 11289 */ MCD_OPC_Decode, 209, 13, 160, 1, // Opcode: VRSRAsv1i64 >+/* 11294 */ MCD_OPC_FilterValue, 243, 1, 177, 12, // Skip to: 14548 >+/* 11299 */ MCD_OPC_CheckPredicate, 15, 173, 12, // Skip to: 14548 >+/* 11303 */ MCD_OPC_Decode, 217, 13, 160, 1, // Opcode: VRSRAuv1i64 >+/* 11308 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 11328 >+/* 11312 */ MCD_OPC_CheckPredicate, 15, 160, 12, // Skip to: 14548 >+/* 11316 */ MCD_OPC_CheckField, 24, 8, 243, 1, 153, 12, // Skip to: 14548 >+/* 11323 */ MCD_OPC_Decode, 195, 14, 160, 1, // Opcode: VSRIv1i64 >+/* 11328 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 11363 >+/* 11332 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11335 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11349 >+/* 11340 */ MCD_OPC_CheckPredicate, 15, 132, 12, // Skip to: 14548 >+/* 11344 */ MCD_OPC_Decode, 248, 13, 161, 1, // Opcode: VSHLiv1i64 >+/* 11349 */ MCD_OPC_FilterValue, 243, 1, 122, 12, // Skip to: 14548 >+/* 11354 */ MCD_OPC_CheckPredicate, 15, 118, 12, // Skip to: 14548 >+/* 11358 */ MCD_OPC_Decode, 167, 14, 162, 1, // Opcode: VSLIv1i64 >+/* 11363 */ MCD_OPC_FilterValue, 6, 16, 0, // Skip to: 11383 >+/* 11367 */ MCD_OPC_CheckPredicate, 15, 105, 12, // Skip to: 14548 >+/* 11371 */ MCD_OPC_CheckField, 24, 8, 243, 1, 98, 12, // Skip to: 14548 >+/* 11378 */ MCD_OPC_Decode, 180, 12, 161, 1, // Opcode: VQSHLsuv1i64 >+/* 11383 */ MCD_OPC_FilterValue, 7, 89, 12, // Skip to: 14548 >+/* 11387 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11390 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 11404 >+/* 11395 */ MCD_OPC_CheckPredicate, 15, 77, 12, // Skip to: 14548 >+/* 11399 */ MCD_OPC_Decode, 172, 12, 161, 1, // Opcode: VQSHLsiv1i64 >+/* 11404 */ MCD_OPC_FilterValue, 243, 1, 67, 12, // Skip to: 14548 >+/* 11409 */ MCD_OPC_CheckPredicate, 15, 63, 12, // Skip to: 14548 >+/* 11413 */ MCD_OPC_Decode, 196, 12, 161, 1, // Opcode: VQSHLuiv1i64 >+/* 11418 */ MCD_OPC_FilterValue, 1, 54, 12, // Skip to: 14548 >+/* 11422 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 11425 */ MCD_OPC_FilterValue, 0, 114, 5, // Skip to: 12823 >+/* 11429 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 11432 */ MCD_OPC_FilterValue, 0, 135, 0, // Skip to: 11571 >+/* 11436 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11439 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11472 >+/* 11443 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11446 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11459 >+/* 11451 */ MCD_OPC_CheckPredicate, 15, 21, 12, // Skip to: 14548 >+/* 11455 */ MCD_OPC_Decode, 215, 11, 95, // Opcode: VQADDsv16i8 >+/* 11459 */ MCD_OPC_FilterValue, 243, 1, 12, 12, // Skip to: 14548 >+/* 11464 */ MCD_OPC_CheckPredicate, 15, 8, 12, // Skip to: 14548 >+/* 11468 */ MCD_OPC_Decode, 223, 11, 95, // Opcode: VQADDuv16i8 >+/* 11472 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11505 >+/* 11476 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11479 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11492 >+/* 11484 */ MCD_OPC_CheckPredicate, 15, 244, 11, // Skip to: 14548 >+/* 11488 */ MCD_OPC_Decode, 221, 11, 95, // Opcode: VQADDsv8i16 >+/* 11492 */ MCD_OPC_FilterValue, 243, 1, 235, 11, // Skip to: 14548 >+/* 11497 */ MCD_OPC_CheckPredicate, 15, 231, 11, // Skip to: 14548 >+/* 11501 */ MCD_OPC_Decode, 229, 11, 95, // Opcode: VQADDuv8i16 >+/* 11505 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11538 >+/* 11509 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11512 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11525 >+/* 11517 */ MCD_OPC_CheckPredicate, 15, 211, 11, // Skip to: 14548 >+/* 11521 */ MCD_OPC_Decode, 220, 11, 95, // Opcode: VQADDsv4i32 >+/* 11525 */ MCD_OPC_FilterValue, 243, 1, 202, 11, // Skip to: 14548 >+/* 11530 */ MCD_OPC_CheckPredicate, 15, 198, 11, // Skip to: 14548 >+/* 11534 */ MCD_OPC_Decode, 228, 11, 95, // Opcode: VQADDuv4i32 >+/* 11538 */ MCD_OPC_FilterValue, 3, 190, 11, // Skip to: 14548 >+/* 11542 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11545 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11558 >+/* 11550 */ MCD_OPC_CheckPredicate, 15, 178, 11, // Skip to: 14548 >+/* 11554 */ MCD_OPC_Decode, 218, 11, 95, // Opcode: VQADDsv2i64 >+/* 11558 */ MCD_OPC_FilterValue, 243, 1, 169, 11, // Skip to: 14548 >+/* 11563 */ MCD_OPC_CheckPredicate, 15, 165, 11, // Skip to: 14548 >+/* 11567 */ MCD_OPC_Decode, 226, 11, 95, // Opcode: VQADDuv2i64 >+/* 11571 */ MCD_OPC_FilterValue, 1, 135, 0, // Skip to: 11710 >+/* 11575 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11578 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11611 >+/* 11582 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11585 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11598 >+/* 11590 */ MCD_OPC_CheckPredicate, 15, 138, 11, // Skip to: 14548 >+/* 11594 */ MCD_OPC_Decode, 213, 4, 95, // Opcode: VANDq >+/* 11598 */ MCD_OPC_FilterValue, 243, 1, 129, 11, // Skip to: 14548 >+/* 11603 */ MCD_OPC_CheckPredicate, 15, 125, 11, // Skip to: 14548 >+/* 11607 */ MCD_OPC_Decode, 143, 6, 95, // Opcode: VEORq >+/* 11611 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11644 >+/* 11615 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11618 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11631 >+/* 11623 */ MCD_OPC_CheckPredicate, 15, 105, 11, // Skip to: 14548 >+/* 11627 */ MCD_OPC_Decode, 219, 4, 95, // Opcode: VBICq >+/* 11631 */ MCD_OPC_FilterValue, 243, 1, 96, 11, // Skip to: 14548 >+/* 11636 */ MCD_OPC_CheckPredicate, 15, 92, 11, // Skip to: 14548 >+/* 11640 */ MCD_OPC_Decode, 225, 4, 103, // Opcode: VBSLq >+/* 11644 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11677 >+/* 11648 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11651 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11664 >+/* 11656 */ MCD_OPC_CheckPredicate, 15, 72, 11, // Skip to: 14548 >+/* 11660 */ MCD_OPC_Decode, 166, 11, 95, // Opcode: VORRq >+/* 11664 */ MCD_OPC_FilterValue, 243, 1, 63, 11, // Skip to: 14548 >+/* 11669 */ MCD_OPC_CheckPredicate, 15, 59, 11, // Skip to: 14548 >+/* 11673 */ MCD_OPC_Decode, 223, 4, 103, // Opcode: VBITq >+/* 11677 */ MCD_OPC_FilterValue, 3, 51, 11, // Skip to: 14548 >+/* 11681 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11684 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11697 >+/* 11689 */ MCD_OPC_CheckPredicate, 15, 39, 11, // Skip to: 14548 >+/* 11693 */ MCD_OPC_Decode, 160, 11, 95, // Opcode: VORNq >+/* 11697 */ MCD_OPC_FilterValue, 243, 1, 30, 11, // Skip to: 14548 >+/* 11702 */ MCD_OPC_CheckPredicate, 15, 26, 11, // Skip to: 14548 >+/* 11706 */ MCD_OPC_Decode, 221, 4, 103, // Opcode: VBIFq >+/* 11710 */ MCD_OPC_FilterValue, 2, 135, 0, // Skip to: 11849 >+/* 11714 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11717 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11750 >+/* 11721 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11724 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11737 >+/* 11729 */ MCD_OPC_CheckPredicate, 15, 255, 10, // Skip to: 14548 >+/* 11733 */ MCD_OPC_Decode, 220, 12, 95, // Opcode: VQSUBsv16i8 >+/* 11737 */ MCD_OPC_FilterValue, 243, 1, 246, 10, // Skip to: 14548 >+/* 11742 */ MCD_OPC_CheckPredicate, 15, 242, 10, // Skip to: 14548 >+/* 11746 */ MCD_OPC_Decode, 228, 12, 95, // Opcode: VQSUBuv16i8 >+/* 11750 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11783 >+/* 11754 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11757 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11770 >+/* 11762 */ MCD_OPC_CheckPredicate, 15, 222, 10, // Skip to: 14548 >+/* 11766 */ MCD_OPC_Decode, 226, 12, 95, // Opcode: VQSUBsv8i16 >+/* 11770 */ MCD_OPC_FilterValue, 243, 1, 213, 10, // Skip to: 14548 >+/* 11775 */ MCD_OPC_CheckPredicate, 15, 209, 10, // Skip to: 14548 >+/* 11779 */ MCD_OPC_Decode, 234, 12, 95, // Opcode: VQSUBuv8i16 >+/* 11783 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 11816 >+/* 11787 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11790 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11803 >+/* 11795 */ MCD_OPC_CheckPredicate, 15, 189, 10, // Skip to: 14548 >+/* 11799 */ MCD_OPC_Decode, 225, 12, 95, // Opcode: VQSUBsv4i32 >+/* 11803 */ MCD_OPC_FilterValue, 243, 1, 180, 10, // Skip to: 14548 >+/* 11808 */ MCD_OPC_CheckPredicate, 15, 176, 10, // Skip to: 14548 >+/* 11812 */ MCD_OPC_Decode, 233, 12, 95, // Opcode: VQSUBuv4i32 >+/* 11816 */ MCD_OPC_FilterValue, 3, 168, 10, // Skip to: 14548 >+/* 11820 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11823 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11836 >+/* 11828 */ MCD_OPC_CheckPredicate, 15, 156, 10, // Skip to: 14548 >+/* 11832 */ MCD_OPC_Decode, 223, 12, 95, // Opcode: VQSUBsv2i64 >+/* 11836 */ MCD_OPC_FilterValue, 243, 1, 147, 10, // Skip to: 14548 >+/* 11841 */ MCD_OPC_CheckPredicate, 15, 143, 10, // Skip to: 14548 >+/* 11845 */ MCD_OPC_Decode, 231, 12, 95, // Opcode: VQSUBuv2i64 >+/* 11849 */ MCD_OPC_FilterValue, 3, 102, 0, // Skip to: 11955 >+/* 11853 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11856 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11889 >+/* 11860 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11863 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11876 >+/* 11868 */ MCD_OPC_CheckPredicate, 15, 116, 10, // Skip to: 14548 >+/* 11872 */ MCD_OPC_Decode, 244, 4, 95, // Opcode: VCGEsv16i8 >+/* 11876 */ MCD_OPC_FilterValue, 243, 1, 107, 10, // Skip to: 14548 >+/* 11881 */ MCD_OPC_CheckPredicate, 15, 103, 10, // Skip to: 14548 >+/* 11885 */ MCD_OPC_Decode, 250, 4, 95, // Opcode: VCGEuv16i8 >+/* 11889 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 11922 >+/* 11893 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11896 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11909 >+/* 11901 */ MCD_OPC_CheckPredicate, 15, 83, 10, // Skip to: 14548 >+/* 11905 */ MCD_OPC_Decode, 248, 4, 95, // Opcode: VCGEsv8i16 >+/* 11909 */ MCD_OPC_FilterValue, 243, 1, 74, 10, // Skip to: 14548 >+/* 11914 */ MCD_OPC_CheckPredicate, 15, 70, 10, // Skip to: 14548 >+/* 11918 */ MCD_OPC_Decode, 254, 4, 95, // Opcode: VCGEuv8i16 >+/* 11922 */ MCD_OPC_FilterValue, 2, 62, 10, // Skip to: 14548 >+/* 11926 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11929 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11942 >+/* 11934 */ MCD_OPC_CheckPredicate, 15, 50, 10, // Skip to: 14548 >+/* 11938 */ MCD_OPC_Decode, 247, 4, 95, // Opcode: VCGEsv4i32 >+/* 11942 */ MCD_OPC_FilterValue, 243, 1, 41, 10, // Skip to: 14548 >+/* 11947 */ MCD_OPC_CheckPredicate, 15, 37, 10, // Skip to: 14548 >+/* 11951 */ MCD_OPC_Decode, 253, 4, 95, // Opcode: VCGEuv4i32 >+/* 11955 */ MCD_OPC_FilterValue, 4, 135, 0, // Skip to: 12094 >+/* 11959 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 11962 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 11995 >+/* 11966 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 11969 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 11982 >+/* 11974 */ MCD_OPC_CheckPredicate, 15, 10, 10, // Skip to: 14548 >+/* 11978 */ MCD_OPC_Decode, 187, 12, 99, // Opcode: VQSHLsv16i8 >+/* 11982 */ MCD_OPC_FilterValue, 243, 1, 1, 10, // Skip to: 14548 >+/* 11987 */ MCD_OPC_CheckPredicate, 15, 253, 9, // Skip to: 14548 >+/* 11991 */ MCD_OPC_Decode, 203, 12, 99, // Opcode: VQSHLuv16i8 >+/* 11995 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12028 >+/* 11999 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12002 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12015 >+/* 12007 */ MCD_OPC_CheckPredicate, 15, 233, 9, // Skip to: 14548 >+/* 12011 */ MCD_OPC_Decode, 193, 12, 99, // Opcode: VQSHLsv8i16 >+/* 12015 */ MCD_OPC_FilterValue, 243, 1, 224, 9, // Skip to: 14548 >+/* 12020 */ MCD_OPC_CheckPredicate, 15, 220, 9, // Skip to: 14548 >+/* 12024 */ MCD_OPC_Decode, 209, 12, 99, // Opcode: VQSHLuv8i16 >+/* 12028 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 12061 >+/* 12032 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12035 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12048 >+/* 12040 */ MCD_OPC_CheckPredicate, 15, 200, 9, // Skip to: 14548 >+/* 12044 */ MCD_OPC_Decode, 192, 12, 99, // Opcode: VQSHLsv4i32 >+/* 12048 */ MCD_OPC_FilterValue, 243, 1, 191, 9, // Skip to: 14548 >+/* 12053 */ MCD_OPC_CheckPredicate, 15, 187, 9, // Skip to: 14548 >+/* 12057 */ MCD_OPC_Decode, 208, 12, 99, // Opcode: VQSHLuv4i32 >+/* 12061 */ MCD_OPC_FilterValue, 3, 179, 9, // Skip to: 14548 >+/* 12065 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12068 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12081 >+/* 12073 */ MCD_OPC_CheckPredicate, 15, 167, 9, // Skip to: 14548 >+/* 12077 */ MCD_OPC_Decode, 190, 12, 99, // Opcode: VQSHLsv2i64 >+/* 12081 */ MCD_OPC_FilterValue, 243, 1, 158, 9, // Skip to: 14548 >+/* 12086 */ MCD_OPC_CheckPredicate, 15, 154, 9, // Skip to: 14548 >+/* 12090 */ MCD_OPC_Decode, 206, 12, 99, // Opcode: VQSHLuv2i64 >+/* 12094 */ MCD_OPC_FilterValue, 5, 135, 0, // Skip to: 12233 >+/* 12098 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12101 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12134 >+/* 12105 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12108 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12121 >+/* 12113 */ MCD_OPC_CheckPredicate, 15, 127, 9, // Skip to: 14548 >+/* 12117 */ MCD_OPC_Decode, 146, 12, 99, // Opcode: VQRSHLsv16i8 >+/* 12121 */ MCD_OPC_FilterValue, 243, 1, 118, 9, // Skip to: 14548 >+/* 12126 */ MCD_OPC_CheckPredicate, 15, 114, 9, // Skip to: 14548 >+/* 12130 */ MCD_OPC_Decode, 154, 12, 99, // Opcode: VQRSHLuv16i8 >+/* 12134 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12167 >+/* 12138 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12141 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12154 >+/* 12146 */ MCD_OPC_CheckPredicate, 15, 94, 9, // Skip to: 14548 >+/* 12150 */ MCD_OPC_Decode, 152, 12, 99, // Opcode: VQRSHLsv8i16 >+/* 12154 */ MCD_OPC_FilterValue, 243, 1, 85, 9, // Skip to: 14548 >+/* 12159 */ MCD_OPC_CheckPredicate, 15, 81, 9, // Skip to: 14548 >+/* 12163 */ MCD_OPC_Decode, 160, 12, 99, // Opcode: VQRSHLuv8i16 >+/* 12167 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 12200 >+/* 12171 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12174 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12187 >+/* 12179 */ MCD_OPC_CheckPredicate, 15, 61, 9, // Skip to: 14548 >+/* 12183 */ MCD_OPC_Decode, 151, 12, 99, // Opcode: VQRSHLsv4i32 >+/* 12187 */ MCD_OPC_FilterValue, 243, 1, 52, 9, // Skip to: 14548 >+/* 12192 */ MCD_OPC_CheckPredicate, 15, 48, 9, // Skip to: 14548 >+/* 12196 */ MCD_OPC_Decode, 159, 12, 99, // Opcode: VQRSHLuv4i32 >+/* 12200 */ MCD_OPC_FilterValue, 3, 40, 9, // Skip to: 14548 >+/* 12204 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12207 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12220 >+/* 12212 */ MCD_OPC_CheckPredicate, 15, 28, 9, // Skip to: 14548 >+/* 12216 */ MCD_OPC_Decode, 149, 12, 99, // Opcode: VQRSHLsv2i64 >+/* 12220 */ MCD_OPC_FilterValue, 243, 1, 19, 9, // Skip to: 14548 >+/* 12225 */ MCD_OPC_CheckPredicate, 15, 15, 9, // Skip to: 14548 >+/* 12229 */ MCD_OPC_Decode, 157, 12, 99, // Opcode: VQRSHLuv2i64 >+/* 12233 */ MCD_OPC_FilterValue, 6, 102, 0, // Skip to: 12339 >+/* 12237 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12240 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12273 >+/* 12244 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12247 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12260 >+/* 12252 */ MCD_OPC_CheckPredicate, 15, 244, 8, // Skip to: 14548 >+/* 12256 */ MCD_OPC_Decode, 255, 9, 95, // Opcode: VMINsv16i8 >+/* 12260 */ MCD_OPC_FilterValue, 243, 1, 235, 8, // Skip to: 14548 >+/* 12265 */ MCD_OPC_CheckPredicate, 15, 231, 8, // Skip to: 14548 >+/* 12269 */ MCD_OPC_Decode, 133, 10, 95, // Opcode: VMINuv16i8 >+/* 12273 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12306 >+/* 12277 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12280 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12293 >+/* 12285 */ MCD_OPC_CheckPredicate, 15, 211, 8, // Skip to: 14548 >+/* 12289 */ MCD_OPC_Decode, 131, 10, 95, // Opcode: VMINsv8i16 >+/* 12293 */ MCD_OPC_FilterValue, 243, 1, 202, 8, // Skip to: 14548 >+/* 12298 */ MCD_OPC_CheckPredicate, 15, 198, 8, // Skip to: 14548 >+/* 12302 */ MCD_OPC_Decode, 137, 10, 95, // Opcode: VMINuv8i16 >+/* 12306 */ MCD_OPC_FilterValue, 2, 190, 8, // Skip to: 14548 >+/* 12310 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12313 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12326 >+/* 12318 */ MCD_OPC_CheckPredicate, 15, 178, 8, // Skip to: 14548 >+/* 12322 */ MCD_OPC_Decode, 130, 10, 95, // Opcode: VMINsv4i32 >+/* 12326 */ MCD_OPC_FilterValue, 243, 1, 169, 8, // Skip to: 14548 >+/* 12331 */ MCD_OPC_CheckPredicate, 15, 165, 8, // Skip to: 14548 >+/* 12335 */ MCD_OPC_Decode, 136, 10, 95, // Opcode: VMINuv4i32 >+/* 12339 */ MCD_OPC_FilterValue, 7, 102, 0, // Skip to: 12445 >+/* 12343 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12346 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12379 >+/* 12350 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12353 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12366 >+/* 12358 */ MCD_OPC_CheckPredicate, 15, 138, 8, // Skip to: 14548 >+/* 12362 */ MCD_OPC_Decode, 139, 4, 103, // Opcode: VABAsv16i8 >+/* 12366 */ MCD_OPC_FilterValue, 243, 1, 129, 8, // Skip to: 14548 >+/* 12371 */ MCD_OPC_CheckPredicate, 15, 125, 8, // Skip to: 14548 >+/* 12375 */ MCD_OPC_Decode, 145, 4, 103, // Opcode: VABAuv16i8 >+/* 12379 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12412 >+/* 12383 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12386 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12399 >+/* 12391 */ MCD_OPC_CheckPredicate, 15, 105, 8, // Skip to: 14548 >+/* 12395 */ MCD_OPC_Decode, 143, 4, 103, // Opcode: VABAsv8i16 >+/* 12399 */ MCD_OPC_FilterValue, 243, 1, 96, 8, // Skip to: 14548 >+/* 12404 */ MCD_OPC_CheckPredicate, 15, 92, 8, // Skip to: 14548 >+/* 12408 */ MCD_OPC_Decode, 149, 4, 103, // Opcode: VABAuv8i16 >+/* 12412 */ MCD_OPC_FilterValue, 2, 84, 8, // Skip to: 14548 >+/* 12416 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12419 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12432 >+/* 12424 */ MCD_OPC_CheckPredicate, 15, 72, 8, // Skip to: 14548 >+/* 12428 */ MCD_OPC_Decode, 142, 4, 103, // Opcode: VABAsv4i32 >+/* 12432 */ MCD_OPC_FilterValue, 243, 1, 63, 8, // Skip to: 14548 >+/* 12437 */ MCD_OPC_CheckPredicate, 15, 59, 8, // Skip to: 14548 >+/* 12441 */ MCD_OPC_Decode, 148, 4, 103, // Opcode: VABAuv4i32 >+/* 12445 */ MCD_OPC_FilterValue, 8, 102, 0, // Skip to: 12551 >+/* 12449 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12452 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12485 >+/* 12456 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12459 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12472 >+/* 12464 */ MCD_OPC_CheckPredicate, 15, 32, 8, // Skip to: 14548 >+/* 12468 */ MCD_OPC_Decode, 196, 17, 95, // Opcode: VTSTv16i8 >+/* 12472 */ MCD_OPC_FilterValue, 243, 1, 23, 8, // Skip to: 14548 >+/* 12477 */ MCD_OPC_CheckPredicate, 15, 19, 8, // Skip to: 14548 >+/* 12481 */ MCD_OPC_Decode, 228, 4, 95, // Opcode: VCEQv16i8 >+/* 12485 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 12518 >+/* 12489 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12492 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12505 >+/* 12497 */ MCD_OPC_CheckPredicate, 15, 255, 7, // Skip to: 14548 >+/* 12501 */ MCD_OPC_Decode, 200, 17, 95, // Opcode: VTSTv8i16 >+/* 12505 */ MCD_OPC_FilterValue, 243, 1, 246, 7, // Skip to: 14548 >+/* 12510 */ MCD_OPC_CheckPredicate, 15, 242, 7, // Skip to: 14548 >+/* 12514 */ MCD_OPC_Decode, 232, 4, 95, // Opcode: VCEQv8i16 >+/* 12518 */ MCD_OPC_FilterValue, 2, 234, 7, // Skip to: 14548 >+/* 12522 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12525 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12538 >+/* 12530 */ MCD_OPC_CheckPredicate, 15, 222, 7, // Skip to: 14548 >+/* 12534 */ MCD_OPC_Decode, 199, 17, 95, // Opcode: VTSTv4i32 >+/* 12538 */ MCD_OPC_FilterValue, 243, 1, 213, 7, // Skip to: 14548 >+/* 12543 */ MCD_OPC_CheckPredicate, 15, 209, 7, // Skip to: 14548 >+/* 12547 */ MCD_OPC_Decode, 231, 4, 95, // Opcode: VCEQv4i32 >+/* 12551 */ MCD_OPC_FilterValue, 9, 74, 0, // Skip to: 12629 >+/* 12555 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12558 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12591 >+/* 12562 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12565 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12578 >+/* 12570 */ MCD_OPC_CheckPredicate, 15, 182, 7, // Skip to: 14548 >+/* 12574 */ MCD_OPC_Decode, 131, 11, 95, // Opcode: VMULv16i8 >+/* 12578 */ MCD_OPC_FilterValue, 243, 1, 173, 7, // Skip to: 14548 >+/* 12583 */ MCD_OPC_CheckPredicate, 15, 169, 7, // Skip to: 14548 >+/* 12587 */ MCD_OPC_Decode, 252, 10, 95, // Opcode: VMULpq >+/* 12591 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 12610 >+/* 12595 */ MCD_OPC_CheckPredicate, 15, 157, 7, // Skip to: 14548 >+/* 12599 */ MCD_OPC_CheckField, 24, 8, 242, 1, 150, 7, // Skip to: 14548 >+/* 12606 */ MCD_OPC_Decode, 135, 11, 95, // Opcode: VMULv8i16 >+/* 12610 */ MCD_OPC_FilterValue, 2, 142, 7, // Skip to: 14548 >+/* 12614 */ MCD_OPC_CheckPredicate, 15, 138, 7, // Skip to: 14548 >+/* 12618 */ MCD_OPC_CheckField, 24, 8, 242, 1, 131, 7, // Skip to: 14548 >+/* 12625 */ MCD_OPC_Decode, 134, 11, 95, // Opcode: VMULv4i32 >+/* 12629 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 12674 >+/* 12633 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12636 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12655 >+/* 12640 */ MCD_OPC_CheckPredicate, 18, 112, 7, // Skip to: 14548 >+/* 12644 */ MCD_OPC_CheckField, 24, 8, 242, 1, 105, 7, // Skip to: 14548 >+/* 12651 */ MCD_OPC_Decode, 154, 6, 103, // Opcode: VFMAfq >+/* 12655 */ MCD_OPC_FilterValue, 2, 97, 7, // Skip to: 14548 >+/* 12659 */ MCD_OPC_CheckPredicate, 18, 93, 7, // Skip to: 14548 >+/* 12663 */ MCD_OPC_CheckField, 24, 8, 242, 1, 86, 7, // Skip to: 14548 >+/* 12670 */ MCD_OPC_Decode, 158, 6, 103, // Opcode: VFMSfq >+/* 12674 */ MCD_OPC_FilterValue, 13, 55, 0, // Skip to: 12733 >+/* 12678 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12681 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 12714 >+/* 12685 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 12688 */ MCD_OPC_FilterValue, 242, 1, 8, 0, // Skip to: 12701 >+/* 12693 */ MCD_OPC_CheckPredicate, 15, 59, 7, // Skip to: 14548 >+/* 12697 */ MCD_OPC_Decode, 152, 10, 103, // Opcode: VMLAfq >+/* 12701 */ MCD_OPC_FilterValue, 243, 1, 50, 7, // Skip to: 14548 >+/* 12706 */ MCD_OPC_CheckPredicate, 15, 46, 7, // Skip to: 14548 >+/* 12710 */ MCD_OPC_Decode, 250, 10, 95, // Opcode: VMULfq >+/* 12714 */ MCD_OPC_FilterValue, 2, 38, 7, // Skip to: 14548 >+/* 12718 */ MCD_OPC_CheckPredicate, 15, 34, 7, // Skip to: 14548 >+/* 12722 */ MCD_OPC_CheckField, 24, 8, 242, 1, 27, 7, // Skip to: 14548 >+/* 12729 */ MCD_OPC_Decode, 178, 10, 103, // Opcode: VMLSfq >+/* 12733 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 12778 >+/* 12737 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12740 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12759 >+/* 12744 */ MCD_OPC_CheckPredicate, 15, 8, 7, // Skip to: 14548 >+/* 12748 */ MCD_OPC_CheckField, 24, 8, 243, 1, 1, 7, // Skip to: 14548 >+/* 12755 */ MCD_OPC_Decode, 182, 4, 95, // Opcode: VACGEq >+/* 12759 */ MCD_OPC_FilterValue, 2, 249, 6, // Skip to: 14548 >+/* 12763 */ MCD_OPC_CheckPredicate, 15, 245, 6, // Skip to: 14548 >+/* 12767 */ MCD_OPC_CheckField, 24, 8, 243, 1, 238, 6, // Skip to: 14548 >+/* 12774 */ MCD_OPC_Decode, 184, 4, 95, // Opcode: VACGTq >+/* 12778 */ MCD_OPC_FilterValue, 15, 230, 6, // Skip to: 14548 >+/* 12782 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 12785 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12804 >+/* 12789 */ MCD_OPC_CheckPredicate, 15, 219, 6, // Skip to: 14548 >+/* 12793 */ MCD_OPC_CheckField, 24, 8, 242, 1, 212, 6, // Skip to: 14548 >+/* 12800 */ MCD_OPC_Decode, 244, 12, 95, // Opcode: VRECPSfq >+/* 12804 */ MCD_OPC_FilterValue, 2, 204, 6, // Skip to: 14548 >+/* 12808 */ MCD_OPC_CheckPredicate, 15, 200, 6, // Skip to: 14548 >+/* 12812 */ MCD_OPC_CheckField, 24, 8, 242, 1, 193, 6, // Skip to: 14548 >+/* 12819 */ MCD_OPC_Decode, 207, 13, 95, // Opcode: VRSQRTSfq >+/* 12823 */ MCD_OPC_FilterValue, 1, 185, 6, // Skip to: 14548 >+/* 12827 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 12830 */ MCD_OPC_FilterValue, 0, 177, 5, // Skip to: 14291 >+/* 12834 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... >+/* 12837 */ MCD_OPC_FilterValue, 121, 171, 6, // Skip to: 14548 >+/* 12841 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 12844 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 12969 >+/* 12848 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 12851 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 12936 >+/* 12855 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 12858 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 12903 >+/* 12862 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12865 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12884 >+/* 12869 */ MCD_OPC_CheckPredicate, 15, 229, 4, // Skip to: 14126 >+/* 12873 */ MCD_OPC_CheckField, 19, 1, 1, 223, 4, // Skip to: 14126 >+/* 12879 */ MCD_OPC_Decode, 146, 14, 163, 1, // Opcode: VSHRsv16i8 >+/* 12884 */ MCD_OPC_FilterValue, 1, 214, 4, // Skip to: 14126 >+/* 12888 */ MCD_OPC_CheckPredicate, 15, 210, 4, // Skip to: 14126 >+/* 12892 */ MCD_OPC_CheckField, 19, 1, 1, 204, 4, // Skip to: 14126 >+/* 12898 */ MCD_OPC_Decode, 154, 14, 163, 1, // Opcode: VSHRuv16i8 >+/* 12903 */ MCD_OPC_FilterValue, 1, 195, 4, // Skip to: 14126 >+/* 12907 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12910 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12923 >+/* 12914 */ MCD_OPC_CheckPredicate, 15, 184, 4, // Skip to: 14126 >+/* 12918 */ MCD_OPC_Decode, 152, 14, 164, 1, // Opcode: VSHRsv8i16 >+/* 12923 */ MCD_OPC_FilterValue, 1, 175, 4, // Skip to: 14126 >+/* 12927 */ MCD_OPC_CheckPredicate, 15, 171, 4, // Skip to: 14126 >+/* 12931 */ MCD_OPC_Decode, 160, 14, 164, 1, // Opcode: VSHRuv8i16 >+/* 12936 */ MCD_OPC_FilterValue, 1, 162, 4, // Skip to: 14126 >+/* 12940 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12943 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 12956 >+/* 12947 */ MCD_OPC_CheckPredicate, 15, 151, 4, // Skip to: 14126 >+/* 12951 */ MCD_OPC_Decode, 151, 14, 165, 1, // Opcode: VSHRsv4i32 >+/* 12956 */ MCD_OPC_FilterValue, 1, 142, 4, // Skip to: 14126 >+/* 12960 */ MCD_OPC_CheckPredicate, 15, 138, 4, // Skip to: 14126 >+/* 12964 */ MCD_OPC_Decode, 159, 14, 165, 1, // Opcode: VSHRuv4i32 >+/* 12969 */ MCD_OPC_FilterValue, 1, 121, 0, // Skip to: 13094 >+/* 12973 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 12976 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13061 >+/* 12980 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 12983 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13028 >+/* 12987 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 12990 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13009 >+/* 12994 */ MCD_OPC_CheckPredicate, 15, 104, 4, // Skip to: 14126 >+/* 12998 */ MCD_OPC_CheckField, 19, 1, 1, 98, 4, // Skip to: 14126 >+/* 13004 */ MCD_OPC_Decode, 178, 14, 166, 1, // Opcode: VSRAsv16i8 >+/* 13009 */ MCD_OPC_FilterValue, 1, 89, 4, // Skip to: 14126 >+/* 13013 */ MCD_OPC_CheckPredicate, 15, 85, 4, // Skip to: 14126 >+/* 13017 */ MCD_OPC_CheckField, 19, 1, 1, 79, 4, // Skip to: 14126 >+/* 13023 */ MCD_OPC_Decode, 186, 14, 166, 1, // Opcode: VSRAuv16i8 >+/* 13028 */ MCD_OPC_FilterValue, 1, 70, 4, // Skip to: 14126 >+/* 13032 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13035 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13048 >+/* 13039 */ MCD_OPC_CheckPredicate, 15, 59, 4, // Skip to: 14126 >+/* 13043 */ MCD_OPC_Decode, 184, 14, 167, 1, // Opcode: VSRAsv8i16 >+/* 13048 */ MCD_OPC_FilterValue, 1, 50, 4, // Skip to: 14126 >+/* 13052 */ MCD_OPC_CheckPredicate, 15, 46, 4, // Skip to: 14126 >+/* 13056 */ MCD_OPC_Decode, 192, 14, 167, 1, // Opcode: VSRAuv8i16 >+/* 13061 */ MCD_OPC_FilterValue, 1, 37, 4, // Skip to: 14126 >+/* 13065 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13068 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13081 >+/* 13072 */ MCD_OPC_CheckPredicate, 15, 26, 4, // Skip to: 14126 >+/* 13076 */ MCD_OPC_Decode, 183, 14, 168, 1, // Opcode: VSRAsv4i32 >+/* 13081 */ MCD_OPC_FilterValue, 1, 17, 4, // Skip to: 14126 >+/* 13085 */ MCD_OPC_CheckPredicate, 15, 13, 4, // Skip to: 14126 >+/* 13089 */ MCD_OPC_Decode, 191, 14, 168, 1, // Opcode: VSRAuv4i32 >+/* 13094 */ MCD_OPC_FilterValue, 2, 121, 0, // Skip to: 13219 >+/* 13098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13101 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13186 >+/* 13105 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13108 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13153 >+/* 13112 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13115 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13134 >+/* 13119 */ MCD_OPC_CheckPredicate, 15, 235, 3, // Skip to: 14126 >+/* 13123 */ MCD_OPC_CheckField, 19, 1, 1, 229, 3, // Skip to: 14126 >+/* 13129 */ MCD_OPC_Decode, 186, 13, 163, 1, // Opcode: VRSHRsv16i8 >+/* 13134 */ MCD_OPC_FilterValue, 1, 220, 3, // Skip to: 14126 >+/* 13138 */ MCD_OPC_CheckPredicate, 15, 216, 3, // Skip to: 14126 >+/* 13142 */ MCD_OPC_CheckField, 19, 1, 1, 210, 3, // Skip to: 14126 >+/* 13148 */ MCD_OPC_Decode, 194, 13, 163, 1, // Opcode: VRSHRuv16i8 >+/* 13153 */ MCD_OPC_FilterValue, 1, 201, 3, // Skip to: 14126 >+/* 13157 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13160 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13173 >+/* 13164 */ MCD_OPC_CheckPredicate, 15, 190, 3, // Skip to: 14126 >+/* 13168 */ MCD_OPC_Decode, 192, 13, 164, 1, // Opcode: VRSHRsv8i16 >+/* 13173 */ MCD_OPC_FilterValue, 1, 181, 3, // Skip to: 14126 >+/* 13177 */ MCD_OPC_CheckPredicate, 15, 177, 3, // Skip to: 14126 >+/* 13181 */ MCD_OPC_Decode, 200, 13, 164, 1, // Opcode: VRSHRuv8i16 >+/* 13186 */ MCD_OPC_FilterValue, 1, 168, 3, // Skip to: 14126 >+/* 13190 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13193 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13206 >+/* 13197 */ MCD_OPC_CheckPredicate, 15, 157, 3, // Skip to: 14126 >+/* 13201 */ MCD_OPC_Decode, 191, 13, 165, 1, // Opcode: VRSHRsv4i32 >+/* 13206 */ MCD_OPC_FilterValue, 1, 148, 3, // Skip to: 14126 >+/* 13210 */ MCD_OPC_CheckPredicate, 15, 144, 3, // Skip to: 14126 >+/* 13214 */ MCD_OPC_Decode, 199, 13, 165, 1, // Opcode: VRSHRuv4i32 >+/* 13219 */ MCD_OPC_FilterValue, 3, 121, 0, // Skip to: 13344 >+/* 13223 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13226 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13311 >+/* 13230 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13233 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13278 >+/* 13237 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13240 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13259 >+/* 13244 */ MCD_OPC_CheckPredicate, 15, 110, 3, // Skip to: 14126 >+/* 13248 */ MCD_OPC_CheckField, 19, 1, 1, 104, 3, // Skip to: 14126 >+/* 13254 */ MCD_OPC_Decode, 208, 13, 166, 1, // Opcode: VRSRAsv16i8 >+/* 13259 */ MCD_OPC_FilterValue, 1, 95, 3, // Skip to: 14126 >+/* 13263 */ MCD_OPC_CheckPredicate, 15, 91, 3, // Skip to: 14126 >+/* 13267 */ MCD_OPC_CheckField, 19, 1, 1, 85, 3, // Skip to: 14126 >+/* 13273 */ MCD_OPC_Decode, 216, 13, 166, 1, // Opcode: VRSRAuv16i8 >+/* 13278 */ MCD_OPC_FilterValue, 1, 76, 3, // Skip to: 14126 >+/* 13282 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13285 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13298 >+/* 13289 */ MCD_OPC_CheckPredicate, 15, 65, 3, // Skip to: 14126 >+/* 13293 */ MCD_OPC_Decode, 214, 13, 167, 1, // Opcode: VRSRAsv8i16 >+/* 13298 */ MCD_OPC_FilterValue, 1, 56, 3, // Skip to: 14126 >+/* 13302 */ MCD_OPC_CheckPredicate, 15, 52, 3, // Skip to: 14126 >+/* 13306 */ MCD_OPC_Decode, 222, 13, 167, 1, // Opcode: VRSRAuv8i16 >+/* 13311 */ MCD_OPC_FilterValue, 1, 43, 3, // Skip to: 14126 >+/* 13315 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13318 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13331 >+/* 13322 */ MCD_OPC_CheckPredicate, 15, 32, 3, // Skip to: 14126 >+/* 13326 */ MCD_OPC_Decode, 213, 13, 168, 1, // Opcode: VRSRAsv4i32 >+/* 13331 */ MCD_OPC_FilterValue, 1, 23, 3, // Skip to: 14126 >+/* 13335 */ MCD_OPC_CheckPredicate, 15, 19, 3, // Skip to: 14126 >+/* 13339 */ MCD_OPC_Decode, 221, 13, 168, 1, // Opcode: VRSRAuv4i32 >+/* 13344 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 13421 >+/* 13348 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13351 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 13402 >+/* 13355 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13358 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 13383 >+/* 13362 */ MCD_OPC_CheckPredicate, 15, 248, 2, // Skip to: 14126 >+/* 13366 */ MCD_OPC_CheckField, 24, 1, 1, 242, 2, // Skip to: 14126 >+/* 13372 */ MCD_OPC_CheckField, 19, 1, 1, 236, 2, // Skip to: 14126 >+/* 13378 */ MCD_OPC_Decode, 194, 14, 166, 1, // Opcode: VSRIv16i8 >+/* 13383 */ MCD_OPC_FilterValue, 1, 227, 2, // Skip to: 14126 >+/* 13387 */ MCD_OPC_CheckPredicate, 15, 223, 2, // Skip to: 14126 >+/* 13391 */ MCD_OPC_CheckField, 24, 1, 1, 217, 2, // Skip to: 14126 >+/* 13397 */ MCD_OPC_Decode, 200, 14, 167, 1, // Opcode: VSRIv8i16 >+/* 13402 */ MCD_OPC_FilterValue, 1, 208, 2, // Skip to: 14126 >+/* 13406 */ MCD_OPC_CheckPredicate, 15, 204, 2, // Skip to: 14126 >+/* 13410 */ MCD_OPC_CheckField, 24, 1, 1, 198, 2, // Skip to: 14126 >+/* 13416 */ MCD_OPC_Decode, 199, 14, 168, 1, // Opcode: VSRIv4i32 >+/* 13421 */ MCD_OPC_FilterValue, 5, 121, 0, // Skip to: 13546 >+/* 13425 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13428 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13513 >+/* 13432 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13435 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13480 >+/* 13439 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13442 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13461 >+/* 13446 */ MCD_OPC_CheckPredicate, 15, 164, 2, // Skip to: 14126 >+/* 13450 */ MCD_OPC_CheckField, 19, 1, 1, 158, 2, // Skip to: 14126 >+/* 13456 */ MCD_OPC_Decode, 247, 13, 169, 1, // Opcode: VSHLiv16i8 >+/* 13461 */ MCD_OPC_FilterValue, 1, 149, 2, // Skip to: 14126 >+/* 13465 */ MCD_OPC_CheckPredicate, 15, 145, 2, // Skip to: 14126 >+/* 13469 */ MCD_OPC_CheckField, 19, 1, 1, 139, 2, // Skip to: 14126 >+/* 13475 */ MCD_OPC_Decode, 166, 14, 170, 1, // Opcode: VSLIv16i8 >+/* 13480 */ MCD_OPC_FilterValue, 1, 130, 2, // Skip to: 14126 >+/* 13484 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13487 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13500 >+/* 13491 */ MCD_OPC_CheckPredicate, 15, 119, 2, // Skip to: 14126 >+/* 13495 */ MCD_OPC_Decode, 253, 13, 171, 1, // Opcode: VSHLiv8i16 >+/* 13500 */ MCD_OPC_FilterValue, 1, 110, 2, // Skip to: 14126 >+/* 13504 */ MCD_OPC_CheckPredicate, 15, 106, 2, // Skip to: 14126 >+/* 13508 */ MCD_OPC_Decode, 172, 14, 172, 1, // Opcode: VSLIv8i16 >+/* 13513 */ MCD_OPC_FilterValue, 1, 97, 2, // Skip to: 14126 >+/* 13517 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13520 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13533 >+/* 13524 */ MCD_OPC_CheckPredicate, 15, 86, 2, // Skip to: 14126 >+/* 13528 */ MCD_OPC_Decode, 252, 13, 173, 1, // Opcode: VSHLiv4i32 >+/* 13533 */ MCD_OPC_FilterValue, 1, 77, 2, // Skip to: 14126 >+/* 13537 */ MCD_OPC_CheckPredicate, 15, 73, 2, // Skip to: 14126 >+/* 13541 */ MCD_OPC_Decode, 171, 14, 174, 1, // Opcode: VSLIv4i32 >+/* 13546 */ MCD_OPC_FilterValue, 6, 73, 0, // Skip to: 13623 >+/* 13550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13553 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 13604 >+/* 13557 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13560 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 13585 >+/* 13564 */ MCD_OPC_CheckPredicate, 15, 46, 2, // Skip to: 14126 >+/* 13568 */ MCD_OPC_CheckField, 24, 1, 1, 40, 2, // Skip to: 14126 >+/* 13574 */ MCD_OPC_CheckField, 19, 1, 1, 34, 2, // Skip to: 14126 >+/* 13580 */ MCD_OPC_Decode, 179, 12, 169, 1, // Opcode: VQSHLsuv16i8 >+/* 13585 */ MCD_OPC_FilterValue, 1, 25, 2, // Skip to: 14126 >+/* 13589 */ MCD_OPC_CheckPredicate, 15, 21, 2, // Skip to: 14126 >+/* 13593 */ MCD_OPC_CheckField, 24, 1, 1, 15, 2, // Skip to: 14126 >+/* 13599 */ MCD_OPC_Decode, 185, 12, 171, 1, // Opcode: VQSHLsuv8i16 >+/* 13604 */ MCD_OPC_FilterValue, 1, 6, 2, // Skip to: 14126 >+/* 13608 */ MCD_OPC_CheckPredicate, 15, 2, 2, // Skip to: 14126 >+/* 13612 */ MCD_OPC_CheckField, 24, 1, 1, 252, 1, // Skip to: 14126 >+/* 13618 */ MCD_OPC_Decode, 184, 12, 173, 1, // Opcode: VQSHLsuv4i32 >+/* 13623 */ MCD_OPC_FilterValue, 7, 121, 0, // Skip to: 13748 >+/* 13627 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13630 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13715 >+/* 13634 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13637 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13682 >+/* 13641 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13644 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13663 >+/* 13648 */ MCD_OPC_CheckPredicate, 15, 218, 1, // Skip to: 14126 >+/* 13652 */ MCD_OPC_CheckField, 19, 1, 1, 212, 1, // Skip to: 14126 >+/* 13658 */ MCD_OPC_Decode, 171, 12, 169, 1, // Opcode: VQSHLsiv16i8 >+/* 13663 */ MCD_OPC_FilterValue, 1, 203, 1, // Skip to: 14126 >+/* 13667 */ MCD_OPC_CheckPredicate, 15, 199, 1, // Skip to: 14126 >+/* 13671 */ MCD_OPC_CheckField, 19, 1, 1, 193, 1, // Skip to: 14126 >+/* 13677 */ MCD_OPC_Decode, 195, 12, 169, 1, // Opcode: VQSHLuiv16i8 >+/* 13682 */ MCD_OPC_FilterValue, 1, 184, 1, // Skip to: 14126 >+/* 13686 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13689 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13702 >+/* 13693 */ MCD_OPC_CheckPredicate, 15, 173, 1, // Skip to: 14126 >+/* 13697 */ MCD_OPC_Decode, 177, 12, 171, 1, // Opcode: VQSHLsiv8i16 >+/* 13702 */ MCD_OPC_FilterValue, 1, 164, 1, // Skip to: 14126 >+/* 13706 */ MCD_OPC_CheckPredicate, 15, 160, 1, // Skip to: 14126 >+/* 13710 */ MCD_OPC_Decode, 201, 12, 171, 1, // Opcode: VQSHLuiv8i16 >+/* 13715 */ MCD_OPC_FilterValue, 1, 151, 1, // Skip to: 14126 >+/* 13719 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13722 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13735 >+/* 13726 */ MCD_OPC_CheckPredicate, 15, 140, 1, // Skip to: 14126 >+/* 13730 */ MCD_OPC_Decode, 176, 12, 173, 1, // Opcode: VQSHLsiv4i32 >+/* 13735 */ MCD_OPC_FilterValue, 1, 131, 1, // Skip to: 14126 >+/* 13739 */ MCD_OPC_CheckPredicate, 15, 127, 1, // Skip to: 14126 >+/* 13743 */ MCD_OPC_Decode, 200, 12, 173, 1, // Opcode: VQSHLuiv4i32 >+/* 13748 */ MCD_OPC_FilterValue, 8, 121, 0, // Skip to: 13873 >+/* 13752 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13755 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13840 >+/* 13759 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13762 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13807 >+/* 13766 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13769 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13788 >+/* 13773 */ MCD_OPC_CheckPredicate, 15, 93, 1, // Skip to: 14126 >+/* 13777 */ MCD_OPC_CheckField, 19, 1, 1, 87, 1, // Skip to: 14126 >+/* 13783 */ MCD_OPC_Decode, 185, 13, 151, 1, // Opcode: VRSHRNv8i8 >+/* 13788 */ MCD_OPC_FilterValue, 1, 78, 1, // Skip to: 14126 >+/* 13792 */ MCD_OPC_CheckPredicate, 15, 74, 1, // Skip to: 14126 >+/* 13796 */ MCD_OPC_CheckField, 19, 1, 1, 68, 1, // Skip to: 14126 >+/* 13802 */ MCD_OPC_Decode, 170, 12, 151, 1, // Opcode: VQRSHRUNv8i8 >+/* 13807 */ MCD_OPC_FilterValue, 1, 59, 1, // Skip to: 14126 >+/* 13811 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13814 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13827 >+/* 13818 */ MCD_OPC_CheckPredicate, 15, 48, 1, // Skip to: 14126 >+/* 13822 */ MCD_OPC_Decode, 184, 13, 152, 1, // Opcode: VRSHRNv4i16 >+/* 13827 */ MCD_OPC_FilterValue, 1, 39, 1, // Skip to: 14126 >+/* 13831 */ MCD_OPC_CheckPredicate, 15, 35, 1, // Skip to: 14126 >+/* 13835 */ MCD_OPC_Decode, 169, 12, 152, 1, // Opcode: VQRSHRUNv4i16 >+/* 13840 */ MCD_OPC_FilterValue, 1, 26, 1, // Skip to: 14126 >+/* 13844 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13847 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13860 >+/* 13851 */ MCD_OPC_CheckPredicate, 15, 15, 1, // Skip to: 14126 >+/* 13855 */ MCD_OPC_Decode, 183, 13, 153, 1, // Opcode: VRSHRNv2i32 >+/* 13860 */ MCD_OPC_FilterValue, 1, 6, 1, // Skip to: 14126 >+/* 13864 */ MCD_OPC_CheckPredicate, 15, 2, 1, // Skip to: 14126 >+/* 13868 */ MCD_OPC_Decode, 168, 12, 153, 1, // Opcode: VQRSHRUNv2i32 >+/* 13873 */ MCD_OPC_FilterValue, 9, 121, 0, // Skip to: 13998 >+/* 13877 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 13880 */ MCD_OPC_FilterValue, 0, 81, 0, // Skip to: 13965 >+/* 13884 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 13887 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 13932 >+/* 13891 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13894 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 13913 >+/* 13898 */ MCD_OPC_CheckPredicate, 15, 224, 0, // Skip to: 14126 >+/* 13902 */ MCD_OPC_CheckField, 19, 1, 1, 218, 0, // Skip to: 14126 >+/* 13908 */ MCD_OPC_Decode, 164, 12, 151, 1, // Opcode: VQRSHRNsv8i8 >+/* 13913 */ MCD_OPC_FilterValue, 1, 209, 0, // Skip to: 14126 >+/* 13917 */ MCD_OPC_CheckPredicate, 15, 205, 0, // Skip to: 14126 >+/* 13921 */ MCD_OPC_CheckField, 19, 1, 1, 199, 0, // Skip to: 14126 >+/* 13927 */ MCD_OPC_Decode, 167, 12, 151, 1, // Opcode: VQRSHRNuv8i8 >+/* 13932 */ MCD_OPC_FilterValue, 1, 190, 0, // Skip to: 14126 >+/* 13936 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13939 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13952 >+/* 13943 */ MCD_OPC_CheckPredicate, 15, 179, 0, // Skip to: 14126 >+/* 13947 */ MCD_OPC_Decode, 163, 12, 152, 1, // Opcode: VQRSHRNsv4i16 >+/* 13952 */ MCD_OPC_FilterValue, 1, 170, 0, // Skip to: 14126 >+/* 13956 */ MCD_OPC_CheckPredicate, 15, 166, 0, // Skip to: 14126 >+/* 13960 */ MCD_OPC_Decode, 166, 12, 152, 1, // Opcode: VQRSHRNuv4i16 >+/* 13965 */ MCD_OPC_FilterValue, 1, 157, 0, // Skip to: 14126 >+/* 13969 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 13972 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 13985 >+/* 13976 */ MCD_OPC_CheckPredicate, 15, 146, 0, // Skip to: 14126 >+/* 13980 */ MCD_OPC_Decode, 162, 12, 153, 1, // Opcode: VQRSHRNsv2i32 >+/* 13985 */ MCD_OPC_FilterValue, 1, 137, 0, // Skip to: 14126 >+/* 13989 */ MCD_OPC_CheckPredicate, 15, 133, 0, // Skip to: 14126 >+/* 13993 */ MCD_OPC_Decode, 165, 12, 153, 1, // Opcode: VQRSHRNuv2i32 >+/* 13998 */ MCD_OPC_FilterValue, 14, 70, 0, // Skip to: 14072 >+/* 14002 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 14005 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14024 >+/* 14009 */ MCD_OPC_CheckPredicate, 15, 30, 0, // Skip to: 14043 >+/* 14013 */ MCD_OPC_CheckField, 19, 3, 0, 24, 0, // Skip to: 14043 >+/* 14019 */ MCD_OPC_Decode, 212, 10, 157, 1, // Opcode: VMOVv16i8 >+/* 14024 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14043 >+/* 14028 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 14043 >+/* 14032 */ MCD_OPC_CheckField, 19, 3, 0, 5, 0, // Skip to: 14043 >+/* 14038 */ MCD_OPC_Decode, 216, 10, 157, 1, // Opcode: VMOVv2i64 >+/* 14043 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 14046 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14059 >+/* 14050 */ MCD_OPC_CheckPredicate, 15, 72, 0, // Skip to: 14126 >+/* 14054 */ MCD_OPC_Decode, 253, 5, 175, 1, // Opcode: VCVTxs2fq >+/* 14059 */ MCD_OPC_FilterValue, 1, 63, 0, // Skip to: 14126 >+/* 14063 */ MCD_OPC_CheckPredicate, 15, 59, 0, // Skip to: 14126 >+/* 14067 */ MCD_OPC_Decode, 255, 5, 175, 1, // Opcode: VCVTxu2fq >+/* 14072 */ MCD_OPC_FilterValue, 15, 50, 0, // Skip to: 14126 >+/* 14076 */ MCD_OPC_ExtractField, 24, 1, // Inst{24} ... >+/* 14079 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14092 >+/* 14083 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 14105 >+/* 14087 */ MCD_OPC_Decode, 244, 5, 175, 1, // Opcode: VCVTf2xsq >+/* 14092 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 14105 >+/* 14096 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 14105 >+/* 14100 */ MCD_OPC_Decode, 246, 5, 175, 1, // Opcode: VCVTf2xuq >+/* 14105 */ MCD_OPC_CheckPredicate, 15, 17, 0, // Skip to: 14126 >+/* 14109 */ MCD_OPC_CheckField, 19, 3, 0, 11, 0, // Skip to: 14126 >+/* 14115 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 14126 >+/* 14121 */ MCD_OPC_Decode, 217, 10, 157, 1, // Opcode: VMOVv4f32 >+/* 14126 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 14129 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 14210 >+/* 14133 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 14136 */ MCD_OPC_FilterValue, 0, 152, 1, // Skip to: 14548 >+/* 14140 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 14143 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14162 >+/* 14147 */ MCD_OPC_CheckPredicate, 15, 50, 0, // Skip to: 14201 >+/* 14151 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 14201 >+/* 14157 */ MCD_OPC_Decode, 220, 10, 157, 1, // Opcode: VMOVv8i16 >+/* 14162 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 14201 >+/* 14166 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 14169 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14182 >+/* 14173 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 14201 >+/* 14177 */ MCD_OPC_Decode, 164, 11, 157, 1, // Opcode: VORRiv4i32 >+/* 14182 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14201 >+/* 14186 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 14201 >+/* 14190 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 14201 >+/* 14196 */ MCD_OPC_Decode, 165, 11, 157, 1, // Opcode: VORRiv8i16 >+/* 14201 */ MCD_OPC_CheckPredicate, 15, 87, 1, // Skip to: 14548 >+/* 14205 */ MCD_OPC_Decode, 219, 10, 157, 1, // Opcode: VMOVv4i32 >+/* 14210 */ MCD_OPC_FilterValue, 1, 78, 1, // Skip to: 14548 >+/* 14214 */ MCD_OPC_ExtractField, 19, 3, // Inst{21-19} ... >+/* 14217 */ MCD_OPC_FilterValue, 0, 71, 1, // Skip to: 14548 >+/* 14221 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 14224 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 14243 >+/* 14228 */ MCD_OPC_CheckPredicate, 15, 50, 0, // Skip to: 14282 >+/* 14232 */ MCD_OPC_CheckField, 10, 2, 2, 44, 0, // Skip to: 14282 >+/* 14238 */ MCD_OPC_Decode, 142, 11, 157, 1, // Opcode: VMVNv8i16 >+/* 14243 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 14282 >+/* 14247 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 14250 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 14263 >+/* 14254 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 14282 >+/* 14258 */ MCD_OPC_Decode, 217, 4, 157, 1, // Opcode: VBICiv4i32 >+/* 14263 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 14282 >+/* 14267 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 14282 >+/* 14271 */ MCD_OPC_CheckField, 10, 1, 0, 5, 0, // Skip to: 14282 >+/* 14277 */ MCD_OPC_Decode, 218, 4, 157, 1, // Opcode: VBICiv8i16 >+/* 14282 */ MCD_OPC_CheckPredicate, 15, 6, 1, // Skip to: 14548 >+/* 14286 */ MCD_OPC_Decode, 141, 11, 157, 1, // Opcode: VMVNv4i32 >+/* 14291 */ MCD_OPC_FilterValue, 1, 253, 0, // Skip to: 14548 >+/* 14295 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 14298 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 14333 >+/* 14302 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14305 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14319 >+/* 14310 */ MCD_OPC_CheckPredicate, 15, 234, 0, // Skip to: 14548 >+/* 14314 */ MCD_OPC_Decode, 149, 14, 176, 1, // Opcode: VSHRsv2i64 >+/* 14319 */ MCD_OPC_FilterValue, 243, 1, 224, 0, // Skip to: 14548 >+/* 14324 */ MCD_OPC_CheckPredicate, 15, 220, 0, // Skip to: 14548 >+/* 14328 */ MCD_OPC_Decode, 157, 14, 176, 1, // Opcode: VSHRuv2i64 >+/* 14333 */ MCD_OPC_FilterValue, 1, 31, 0, // Skip to: 14368 >+/* 14337 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14340 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14354 >+/* 14345 */ MCD_OPC_CheckPredicate, 15, 199, 0, // Skip to: 14548 >+/* 14349 */ MCD_OPC_Decode, 181, 14, 177, 1, // Opcode: VSRAsv2i64 >+/* 14354 */ MCD_OPC_FilterValue, 243, 1, 189, 0, // Skip to: 14548 >+/* 14359 */ MCD_OPC_CheckPredicate, 15, 185, 0, // Skip to: 14548 >+/* 14363 */ MCD_OPC_Decode, 189, 14, 177, 1, // Opcode: VSRAuv2i64 >+/* 14368 */ MCD_OPC_FilterValue, 2, 31, 0, // Skip to: 14403 >+/* 14372 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14375 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14389 >+/* 14380 */ MCD_OPC_CheckPredicate, 15, 164, 0, // Skip to: 14548 >+/* 14384 */ MCD_OPC_Decode, 189, 13, 176, 1, // Opcode: VRSHRsv2i64 >+/* 14389 */ MCD_OPC_FilterValue, 243, 1, 154, 0, // Skip to: 14548 >+/* 14394 */ MCD_OPC_CheckPredicate, 15, 150, 0, // Skip to: 14548 >+/* 14398 */ MCD_OPC_Decode, 197, 13, 176, 1, // Opcode: VRSHRuv2i64 >+/* 14403 */ MCD_OPC_FilterValue, 3, 31, 0, // Skip to: 14438 >+/* 14407 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14410 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14424 >+/* 14415 */ MCD_OPC_CheckPredicate, 15, 129, 0, // Skip to: 14548 >+/* 14419 */ MCD_OPC_Decode, 211, 13, 177, 1, // Opcode: VRSRAsv2i64 >+/* 14424 */ MCD_OPC_FilterValue, 243, 1, 119, 0, // Skip to: 14548 >+/* 14429 */ MCD_OPC_CheckPredicate, 15, 115, 0, // Skip to: 14548 >+/* 14433 */ MCD_OPC_Decode, 219, 13, 177, 1, // Opcode: VRSRAuv2i64 >+/* 14438 */ MCD_OPC_FilterValue, 4, 16, 0, // Skip to: 14458 >+/* 14442 */ MCD_OPC_CheckPredicate, 15, 102, 0, // Skip to: 14548 >+/* 14446 */ MCD_OPC_CheckField, 24, 8, 243, 1, 95, 0, // Skip to: 14548 >+/* 14453 */ MCD_OPC_Decode, 197, 14, 177, 1, // Opcode: VSRIv2i64 >+/* 14458 */ MCD_OPC_FilterValue, 5, 31, 0, // Skip to: 14493 >+/* 14462 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14465 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14479 >+/* 14470 */ MCD_OPC_CheckPredicate, 15, 74, 0, // Skip to: 14548 >+/* 14474 */ MCD_OPC_Decode, 250, 13, 178, 1, // Opcode: VSHLiv2i64 >+/* 14479 */ MCD_OPC_FilterValue, 243, 1, 64, 0, // Skip to: 14548 >+/* 14484 */ MCD_OPC_CheckPredicate, 15, 60, 0, // Skip to: 14548 >+/* 14488 */ MCD_OPC_Decode, 169, 14, 179, 1, // Opcode: VSLIv2i64 >+/* 14493 */ MCD_OPC_FilterValue, 6, 16, 0, // Skip to: 14513 >+/* 14497 */ MCD_OPC_CheckPredicate, 15, 47, 0, // Skip to: 14548 >+/* 14501 */ MCD_OPC_CheckField, 24, 8, 243, 1, 40, 0, // Skip to: 14548 >+/* 14508 */ MCD_OPC_Decode, 182, 12, 178, 1, // Opcode: VQSHLsuv2i64 >+/* 14513 */ MCD_OPC_FilterValue, 7, 31, 0, // Skip to: 14548 >+/* 14517 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ... >+/* 14520 */ MCD_OPC_FilterValue, 242, 1, 9, 0, // Skip to: 14534 >+/* 14525 */ MCD_OPC_CheckPredicate, 15, 19, 0, // Skip to: 14548 >+/* 14529 */ MCD_OPC_Decode, 174, 12, 178, 1, // Opcode: VQSHLsiv2i64 >+/* 14534 */ MCD_OPC_FilterValue, 243, 1, 9, 0, // Skip to: 14548 >+/* 14539 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 14548 >+/* 14543 */ MCD_OPC_Decode, 198, 12, 178, 1, // Opcode: VQSHLuiv2i64 >+/* 14548 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableNEONDup32[] = { >+/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ... >+/* 3 */ MCD_OPC_FilterValue, 56, 105, 0, // Skip to: 112 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 16, 53, 0, // Skip to: 67 >+/* 14 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 42 >+/* 21 */ MCD_OPC_CheckPredicate, 15, 124, 1, // Skip to: 405 >+/* 25 */ MCD_OPC_CheckField, 8, 4, 11, 118, 1, // Skip to: 405 >+/* 31 */ MCD_OPC_CheckField, 6, 1, 0, 112, 1, // Skip to: 405 >+/* 37 */ MCD_OPC_Decode, 236, 13, 180, 1, // Opcode: VSETLNi32 >+/* 42 */ MCD_OPC_FilterValue, 1, 103, 1, // Skip to: 405 >+/* 46 */ MCD_OPC_CheckPredicate, 15, 99, 1, // Skip to: 405 >+/* 50 */ MCD_OPC_CheckField, 8, 4, 11, 93, 1, // Skip to: 405 >+/* 56 */ MCD_OPC_CheckField, 6, 1, 0, 87, 1, // Skip to: 405 >+/* 62 */ MCD_OPC_Decode, 163, 6, 181, 1, // Opcode: VGETLNi32 >+/* 67 */ MCD_OPC_FilterValue, 48, 78, 1, // Skip to: 405 >+/* 71 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 74 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 93 >+/* 78 */ MCD_OPC_CheckPredicate, 15, 67, 1, // Skip to: 405 >+/* 82 */ MCD_OPC_CheckField, 8, 4, 11, 61, 1, // Skip to: 405 >+/* 88 */ MCD_OPC_Decode, 235, 13, 182, 1, // Opcode: VSETLNi16 >+/* 93 */ MCD_OPC_FilterValue, 1, 52, 1, // Skip to: 405 >+/* 97 */ MCD_OPC_CheckPredicate, 15, 48, 1, // Skip to: 405 >+/* 101 */ MCD_OPC_CheckField, 8, 4, 11, 42, 1, // Skip to: 405 >+/* 107 */ MCD_OPC_Decode, 164, 6, 183, 1, // Opcode: VGETLNs16 >+/* 112 */ MCD_OPC_FilterValue, 57, 53, 0, // Skip to: 169 >+/* 116 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 119 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 144 >+/* 123 */ MCD_OPC_CheckPredicate, 15, 22, 1, // Skip to: 405 >+/* 127 */ MCD_OPC_CheckField, 8, 4, 11, 16, 1, // Skip to: 405 >+/* 133 */ MCD_OPC_CheckField, 0, 5, 16, 10, 1, // Skip to: 405 >+/* 139 */ MCD_OPC_Decode, 237, 13, 184, 1, // Opcode: VSETLNi8 >+/* 144 */ MCD_OPC_FilterValue, 1, 1, 1, // Skip to: 405 >+/* 148 */ MCD_OPC_CheckPredicate, 15, 253, 0, // Skip to: 405 >+/* 152 */ MCD_OPC_CheckField, 8, 4, 11, 247, 0, // Skip to: 405 >+/* 158 */ MCD_OPC_CheckField, 0, 5, 16, 241, 0, // Skip to: 405 >+/* 164 */ MCD_OPC_Decode, 165, 6, 185, 1, // Opcode: VGETLNs8 >+/* 169 */ MCD_OPC_FilterValue, 58, 143, 0, // Skip to: 316 >+/* 173 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 176 */ MCD_OPC_FilterValue, 16, 53, 0, // Skip to: 233 >+/* 180 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 183 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 208 >+/* 187 */ MCD_OPC_CheckPredicate, 15, 214, 0, // Skip to: 405 >+/* 191 */ MCD_OPC_CheckField, 8, 4, 11, 208, 0, // Skip to: 405 >+/* 197 */ MCD_OPC_CheckField, 6, 1, 0, 202, 0, // Skip to: 405 >+/* 203 */ MCD_OPC_Decode, 132, 6, 186, 1, // Opcode: VDUP32d >+/* 208 */ MCD_OPC_FilterValue, 2, 193, 0, // Skip to: 405 >+/* 212 */ MCD_OPC_CheckPredicate, 15, 189, 0, // Skip to: 405 >+/* 216 */ MCD_OPC_CheckField, 8, 4, 11, 183, 0, // Skip to: 405 >+/* 222 */ MCD_OPC_CheckField, 6, 1, 0, 177, 0, // Skip to: 405 >+/* 228 */ MCD_OPC_Decode, 133, 6, 187, 1, // Opcode: VDUP32q >+/* 233 */ MCD_OPC_FilterValue, 48, 168, 0, // Skip to: 405 >+/* 237 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 240 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 297 >+/* 244 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 247 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 272 >+/* 251 */ MCD_OPC_CheckPredicate, 15, 150, 0, // Skip to: 405 >+/* 255 */ MCD_OPC_CheckField, 8, 4, 11, 144, 0, // Skip to: 405 >+/* 261 */ MCD_OPC_CheckField, 6, 1, 0, 138, 0, // Skip to: 405 >+/* 267 */ MCD_OPC_Decode, 130, 6, 186, 1, // Opcode: VDUP16d >+/* 272 */ MCD_OPC_FilterValue, 1, 129, 0, // Skip to: 405 >+/* 276 */ MCD_OPC_CheckPredicate, 15, 125, 0, // Skip to: 405 >+/* 280 */ MCD_OPC_CheckField, 8, 4, 11, 119, 0, // Skip to: 405 >+/* 286 */ MCD_OPC_CheckField, 6, 1, 0, 113, 0, // Skip to: 405 >+/* 292 */ MCD_OPC_Decode, 131, 6, 187, 1, // Opcode: VDUP16q >+/* 297 */ MCD_OPC_FilterValue, 1, 104, 0, // Skip to: 405 >+/* 301 */ MCD_OPC_CheckPredicate, 15, 100, 0, // Skip to: 405 >+/* 305 */ MCD_OPC_CheckField, 8, 4, 11, 94, 0, // Skip to: 405 >+/* 311 */ MCD_OPC_Decode, 166, 6, 183, 1, // Opcode: VGETLNu16 >+/* 316 */ MCD_OPC_FilterValue, 59, 85, 0, // Skip to: 405 >+/* 320 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 323 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 380 >+/* 327 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 355 >+/* 334 */ MCD_OPC_CheckPredicate, 15, 67, 0, // Skip to: 405 >+/* 338 */ MCD_OPC_CheckField, 8, 4, 11, 61, 0, // Skip to: 405 >+/* 344 */ MCD_OPC_CheckField, 0, 7, 16, 55, 0, // Skip to: 405 >+/* 350 */ MCD_OPC_Decode, 134, 6, 186, 1, // Opcode: VDUP8d >+/* 355 */ MCD_OPC_FilterValue, 1, 46, 0, // Skip to: 405 >+/* 359 */ MCD_OPC_CheckPredicate, 15, 42, 0, // Skip to: 405 >+/* 363 */ MCD_OPC_CheckField, 8, 4, 11, 36, 0, // Skip to: 405 >+/* 369 */ MCD_OPC_CheckField, 0, 7, 16, 30, 0, // Skip to: 405 >+/* 375 */ MCD_OPC_Decode, 135, 6, 187, 1, // Opcode: VDUP8q >+/* 380 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 405 >+/* 384 */ MCD_OPC_CheckPredicate, 15, 17, 0, // Skip to: 405 >+/* 388 */ MCD_OPC_CheckField, 8, 4, 11, 11, 0, // Skip to: 405 >+/* 394 */ MCD_OPC_CheckField, 0, 5, 16, 5, 0, // Skip to: 405 >+/* 400 */ MCD_OPC_Decode, 167, 6, 185, 1, // Opcode: VGETLNu8 >+/* 405 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableNEONLoadStore32[] = { >+/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 280 >+/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 145 >+/* 14 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 17 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 109 >+/* 22 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 25 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 53 >+/* 29 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 44 >+/* 33 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 44 >+/* 39 */ MCD_OPC_Decode, 215, 16, 188, 1, // Opcode: VST4d8 >+/* 44 */ MCD_OPC_CheckPredicate, 15, 194, 22, // Skip to: 5874 >+/* 48 */ MCD_OPC_Decode, 218, 16, 188, 1, // Opcode: VST4d8_UPD >+/* 53 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 81 >+/* 57 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 72 >+/* 61 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 72 >+/* 67 */ MCD_OPC_Decode, 207, 16, 188, 1, // Opcode: VST4d16 >+/* 72 */ MCD_OPC_CheckPredicate, 15, 166, 22, // Skip to: 5874 >+/* 76 */ MCD_OPC_Decode, 210, 16, 188, 1, // Opcode: VST4d16_UPD >+/* 81 */ MCD_OPC_FilterValue, 2, 157, 22, // Skip to: 5874 >+/* 85 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 100 >+/* 89 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 100 >+/* 95 */ MCD_OPC_Decode, 211, 16, 188, 1, // Opcode: VST4d32 >+/* 100 */ MCD_OPC_CheckPredicate, 15, 138, 22, // Skip to: 5874 >+/* 104 */ MCD_OPC_Decode, 214, 16, 188, 1, // Opcode: VST4d32_UPD >+/* 109 */ MCD_OPC_FilterValue, 233, 3, 128, 22, // Skip to: 5874 >+/* 114 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 117 */ MCD_OPC_FilterValue, 0, 121, 22, // Skip to: 5874 >+/* 121 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 136 >+/* 125 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 136 >+/* 131 */ MCD_OPC_Decode, 206, 14, 189, 1, // Opcode: VST1LNd8 >+/* 136 */ MCD_OPC_CheckPredicate, 15, 102, 22, // Skip to: 5874 >+/* 140 */ MCD_OPC_Decode, 207, 14, 189, 1, // Opcode: VST1LNd8_UPD >+/* 145 */ MCD_OPC_FilterValue, 2, 93, 22, // Skip to: 5874 >+/* 149 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 152 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 244 >+/* 157 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 160 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 188 >+/* 164 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 179 >+/* 168 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 179 >+/* 174 */ MCD_OPC_Decode, 185, 9, 188, 1, // Opcode: VLD4d8 >+/* 179 */ MCD_OPC_CheckPredicate, 15, 59, 22, // Skip to: 5874 >+/* 183 */ MCD_OPC_Decode, 188, 9, 188, 1, // Opcode: VLD4d8_UPD >+/* 188 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 216 >+/* 192 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 207 >+/* 196 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 207 >+/* 202 */ MCD_OPC_Decode, 177, 9, 188, 1, // Opcode: VLD4d16 >+/* 207 */ MCD_OPC_CheckPredicate, 15, 31, 22, // Skip to: 5874 >+/* 211 */ MCD_OPC_Decode, 180, 9, 188, 1, // Opcode: VLD4d16_UPD >+/* 216 */ MCD_OPC_FilterValue, 2, 22, 22, // Skip to: 5874 >+/* 220 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 235 >+/* 224 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 235 >+/* 230 */ MCD_OPC_Decode, 181, 9, 188, 1, // Opcode: VLD4d32 >+/* 235 */ MCD_OPC_CheckPredicate, 15, 3, 22, // Skip to: 5874 >+/* 239 */ MCD_OPC_Decode, 184, 9, 188, 1, // Opcode: VLD4d32_UPD >+/* 244 */ MCD_OPC_FilterValue, 233, 3, 249, 21, // Skip to: 5874 >+/* 249 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 252 */ MCD_OPC_FilterValue, 0, 242, 21, // Skip to: 5874 >+/* 256 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 271 >+/* 260 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 271 >+/* 266 */ MCD_OPC_Decode, 214, 6, 190, 1, // Opcode: VLD1LNd8 >+/* 271 */ MCD_OPC_CheckPredicate, 15, 223, 21, // Skip to: 5874 >+/* 275 */ MCD_OPC_Decode, 215, 6, 190, 1, // Opcode: VLD1LNd8_UPD >+/* 280 */ MCD_OPC_FilterValue, 1, 3, 1, // Skip to: 543 >+/* 284 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 287 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 415 >+/* 291 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 294 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 386 >+/* 299 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 302 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 330 >+/* 306 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 321 >+/* 310 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 321 >+/* 316 */ MCD_OPC_Decode, 238, 16, 188, 1, // Opcode: VST4q8 >+/* 321 */ MCD_OPC_CheckPredicate, 15, 173, 21, // Skip to: 5874 >+/* 325 */ MCD_OPC_Decode, 240, 16, 188, 1, // Opcode: VST4q8_UPD >+/* 330 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 358 >+/* 334 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 349 >+/* 338 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 349 >+/* 344 */ MCD_OPC_Decode, 228, 16, 188, 1, // Opcode: VST4q16 >+/* 349 */ MCD_OPC_CheckPredicate, 15, 145, 21, // Skip to: 5874 >+/* 353 */ MCD_OPC_Decode, 230, 16, 188, 1, // Opcode: VST4q16_UPD >+/* 358 */ MCD_OPC_FilterValue, 2, 136, 21, // Skip to: 5874 >+/* 362 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 377 >+/* 366 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 377 >+/* 372 */ MCD_OPC_Decode, 233, 16, 188, 1, // Opcode: VST4q32 >+/* 377 */ MCD_OPC_CheckPredicate, 15, 117, 21, // Skip to: 5874 >+/* 381 */ MCD_OPC_Decode, 235, 16, 188, 1, // Opcode: VST4q32_UPD >+/* 386 */ MCD_OPC_FilterValue, 233, 3, 107, 21, // Skip to: 5874 >+/* 391 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 406 >+/* 395 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 406 >+/* 401 */ MCD_OPC_Decode, 157, 15, 191, 1, // Opcode: VST2LNd8 >+/* 406 */ MCD_OPC_CheckPredicate, 15, 88, 21, // Skip to: 5874 >+/* 410 */ MCD_OPC_Decode, 160, 15, 191, 1, // Opcode: VST2LNd8_UPD >+/* 415 */ MCD_OPC_FilterValue, 2, 79, 21, // Skip to: 5874 >+/* 419 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 422 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 514 >+/* 427 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 430 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 458 >+/* 434 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 449 >+/* 438 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 449 >+/* 444 */ MCD_OPC_Decode, 208, 9, 188, 1, // Opcode: VLD4q8 >+/* 449 */ MCD_OPC_CheckPredicate, 15, 45, 21, // Skip to: 5874 >+/* 453 */ MCD_OPC_Decode, 210, 9, 188, 1, // Opcode: VLD4q8_UPD >+/* 458 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 486 >+/* 462 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 477 >+/* 466 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 477 >+/* 472 */ MCD_OPC_Decode, 198, 9, 188, 1, // Opcode: VLD4q16 >+/* 477 */ MCD_OPC_CheckPredicate, 15, 17, 21, // Skip to: 5874 >+/* 481 */ MCD_OPC_Decode, 200, 9, 188, 1, // Opcode: VLD4q16_UPD >+/* 486 */ MCD_OPC_FilterValue, 2, 8, 21, // Skip to: 5874 >+/* 490 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 505 >+/* 494 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 505 >+/* 500 */ MCD_OPC_Decode, 203, 9, 188, 1, // Opcode: VLD4q32 >+/* 505 */ MCD_OPC_CheckPredicate, 15, 245, 20, // Skip to: 5874 >+/* 509 */ MCD_OPC_Decode, 205, 9, 188, 1, // Opcode: VLD4q32_UPD >+/* 514 */ MCD_OPC_FilterValue, 233, 3, 235, 20, // Skip to: 5874 >+/* 519 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 534 >+/* 523 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 534 >+/* 529 */ MCD_OPC_Decode, 183, 7, 192, 1, // Opcode: VLD2LNd8 >+/* 534 */ MCD_OPC_CheckPredicate, 15, 216, 20, // Skip to: 5874 >+/* 538 */ MCD_OPC_Decode, 186, 7, 192, 1, // Opcode: VLD2LNd8_UPD >+/* 543 */ MCD_OPC_FilterValue, 2, 185, 1, // Skip to: 988 >+/* 547 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 550 */ MCD_OPC_FilterValue, 0, 215, 0, // Skip to: 769 >+/* 554 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 557 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 733 >+/* 562 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 565 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 607 >+/* 569 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 572 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 585 >+/* 576 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 598 >+/* 580 */ MCD_OPC_Decode, 130, 15, 193, 1, // Opcode: VST1d8Qwb_fixed >+/* 585 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 598 >+/* 589 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 598 >+/* 593 */ MCD_OPC_Decode, 129, 15, 193, 1, // Opcode: VST1d8Q >+/* 598 */ MCD_OPC_CheckPredicate, 15, 152, 20, // Skip to: 5874 >+/* 602 */ MCD_OPC_Decode, 131, 15, 193, 1, // Opcode: VST1d8Qwb_register >+/* 607 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 649 >+/* 611 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 614 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 627 >+/* 618 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 640 >+/* 622 */ MCD_OPC_Decode, 225, 14, 193, 1, // Opcode: VST1d16Qwb_fixed >+/* 627 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 640 >+/* 631 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 640 >+/* 635 */ MCD_OPC_Decode, 224, 14, 193, 1, // Opcode: VST1d16Q >+/* 640 */ MCD_OPC_CheckPredicate, 15, 110, 20, // Skip to: 5874 >+/* 644 */ MCD_OPC_Decode, 226, 14, 193, 1, // Opcode: VST1d16Qwb_register >+/* 649 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 691 >+/* 653 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 656 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 669 >+/* 660 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 682 >+/* 664 */ MCD_OPC_Decode, 234, 14, 193, 1, // Opcode: VST1d32Qwb_fixed >+/* 669 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 682 >+/* 673 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 682 >+/* 677 */ MCD_OPC_Decode, 233, 14, 193, 1, // Opcode: VST1d32Q >+/* 682 */ MCD_OPC_CheckPredicate, 15, 68, 20, // Skip to: 5874 >+/* 686 */ MCD_OPC_Decode, 235, 14, 193, 1, // Opcode: VST1d32Qwb_register >+/* 691 */ MCD_OPC_FilterValue, 3, 59, 20, // Skip to: 5874 >+/* 695 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 698 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 711 >+/* 702 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 724 >+/* 706 */ MCD_OPC_Decode, 246, 14, 193, 1, // Opcode: VST1d64Qwb_fixed >+/* 711 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 724 >+/* 715 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 724 >+/* 719 */ MCD_OPC_Decode, 242, 14, 193, 1, // Opcode: VST1d64Q >+/* 724 */ MCD_OPC_CheckPredicate, 15, 26, 20, // Skip to: 5874 >+/* 728 */ MCD_OPC_Decode, 247, 14, 193, 1, // Opcode: VST1d64Qwb_register >+/* 733 */ MCD_OPC_FilterValue, 233, 3, 16, 20, // Skip to: 5874 >+/* 738 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 741 */ MCD_OPC_FilterValue, 0, 9, 20, // Skip to: 5874 >+/* 745 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 760 >+/* 749 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 760 >+/* 755 */ MCD_OPC_Decode, 228, 15, 194, 1, // Opcode: VST3LNd8 >+/* 760 */ MCD_OPC_CheckPredicate, 15, 246, 19, // Skip to: 5874 >+/* 764 */ MCD_OPC_Decode, 231, 15, 194, 1, // Opcode: VST3LNd8_UPD >+/* 769 */ MCD_OPC_FilterValue, 2, 237, 19, // Skip to: 5874 >+/* 773 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 776 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 952 >+/* 781 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 784 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 826 >+/* 788 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 791 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 804 >+/* 795 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 817 >+/* 799 */ MCD_OPC_Decode, 138, 7, 193, 1, // Opcode: VLD1d8Qwb_fixed >+/* 804 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 817 >+/* 808 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 817 >+/* 812 */ MCD_OPC_Decode, 137, 7, 193, 1, // Opcode: VLD1d8Q >+/* 817 */ MCD_OPC_CheckPredicate, 15, 189, 19, // Skip to: 5874 >+/* 821 */ MCD_OPC_Decode, 139, 7, 193, 1, // Opcode: VLD1d8Qwb_register >+/* 826 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 868 >+/* 830 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 833 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 846 >+/* 837 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 859 >+/* 841 */ MCD_OPC_Decode, 233, 6, 193, 1, // Opcode: VLD1d16Qwb_fixed >+/* 846 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 859 >+/* 850 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 859 >+/* 854 */ MCD_OPC_Decode, 232, 6, 193, 1, // Opcode: VLD1d16Q >+/* 859 */ MCD_OPC_CheckPredicate, 15, 147, 19, // Skip to: 5874 >+/* 863 */ MCD_OPC_Decode, 234, 6, 193, 1, // Opcode: VLD1d16Qwb_register >+/* 868 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 910 >+/* 872 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 875 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 888 >+/* 879 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 901 >+/* 883 */ MCD_OPC_Decode, 242, 6, 193, 1, // Opcode: VLD1d32Qwb_fixed >+/* 888 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 901 >+/* 892 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 901 >+/* 896 */ MCD_OPC_Decode, 241, 6, 193, 1, // Opcode: VLD1d32Q >+/* 901 */ MCD_OPC_CheckPredicate, 15, 105, 19, // Skip to: 5874 >+/* 905 */ MCD_OPC_Decode, 243, 6, 193, 1, // Opcode: VLD1d32Qwb_register >+/* 910 */ MCD_OPC_FilterValue, 3, 96, 19, // Skip to: 5874 >+/* 914 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 917 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 930 >+/* 921 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 943 >+/* 925 */ MCD_OPC_Decode, 254, 6, 193, 1, // Opcode: VLD1d64Qwb_fixed >+/* 930 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 943 >+/* 934 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 943 >+/* 938 */ MCD_OPC_Decode, 250, 6, 193, 1, // Opcode: VLD1d64Q >+/* 943 */ MCD_OPC_CheckPredicate, 15, 63, 19, // Skip to: 5874 >+/* 947 */ MCD_OPC_Decode, 255, 6, 193, 1, // Opcode: VLD1d64Qwb_register >+/* 952 */ MCD_OPC_FilterValue, 233, 3, 53, 19, // Skip to: 5874 >+/* 957 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 960 */ MCD_OPC_FilterValue, 0, 46, 19, // Skip to: 5874 >+/* 964 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 979 >+/* 968 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 979 >+/* 974 */ MCD_OPC_Decode, 162, 8, 195, 1, // Opcode: VLD3LNd8 >+/* 979 */ MCD_OPC_CheckPredicate, 15, 27, 19, // Skip to: 5874 >+/* 983 */ MCD_OPC_Decode, 165, 8, 195, 1, // Opcode: VLD3LNd8_UPD >+/* 988 */ MCD_OPC_FilterValue, 3, 87, 1, // Skip to: 1335 >+/* 992 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 995 */ MCD_OPC_FilterValue, 0, 166, 0, // Skip to: 1165 >+/* 999 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1002 */ MCD_OPC_FilterValue, 232, 3, 129, 0, // Skip to: 1136 >+/* 1007 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1010 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 1052 >+/* 1014 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1017 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1030 >+/* 1021 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1043 >+/* 1025 */ MCD_OPC_Decode, 218, 15, 196, 1, // Opcode: VST2q8wb_fixed >+/* 1030 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1043 >+/* 1034 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1043 >+/* 1038 */ MCD_OPC_Decode, 214, 15, 196, 1, // Opcode: VST2q8 >+/* 1043 */ MCD_OPC_CheckPredicate, 15, 219, 18, // Skip to: 5874 >+/* 1047 */ MCD_OPC_Decode, 219, 15, 196, 1, // Opcode: VST2q8wb_register >+/* 1052 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 1094 >+/* 1056 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1059 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1072 >+/* 1063 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1085 >+/* 1067 */ MCD_OPC_Decode, 206, 15, 196, 1, // Opcode: VST2q16wb_fixed >+/* 1072 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1085 >+/* 1076 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1085 >+/* 1080 */ MCD_OPC_Decode, 202, 15, 196, 1, // Opcode: VST2q16 >+/* 1085 */ MCD_OPC_CheckPredicate, 15, 177, 18, // Skip to: 5874 >+/* 1089 */ MCD_OPC_Decode, 207, 15, 196, 1, // Opcode: VST2q16wb_register >+/* 1094 */ MCD_OPC_FilterValue, 2, 168, 18, // Skip to: 5874 >+/* 1098 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1101 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1114 >+/* 1105 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1127 >+/* 1109 */ MCD_OPC_Decode, 212, 15, 196, 1, // Opcode: VST2q32wb_fixed >+/* 1114 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1127 >+/* 1118 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1127 >+/* 1122 */ MCD_OPC_Decode, 208, 15, 196, 1, // Opcode: VST2q32 >+/* 1127 */ MCD_OPC_CheckPredicate, 15, 135, 18, // Skip to: 5874 >+/* 1131 */ MCD_OPC_Decode, 213, 15, 196, 1, // Opcode: VST2q32wb_register >+/* 1136 */ MCD_OPC_FilterValue, 233, 3, 125, 18, // Skip to: 5874 >+/* 1141 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1156 >+/* 1145 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1156 >+/* 1151 */ MCD_OPC_Decode, 180, 16, 197, 1, // Opcode: VST4LNd8 >+/* 1156 */ MCD_OPC_CheckPredicate, 15, 106, 18, // Skip to: 5874 >+/* 1160 */ MCD_OPC_Decode, 183, 16, 197, 1, // Opcode: VST4LNd8_UPD >+/* 1165 */ MCD_OPC_FilterValue, 2, 97, 18, // Skip to: 5874 >+/* 1169 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1172 */ MCD_OPC_FilterValue, 232, 3, 129, 0, // Skip to: 1306 >+/* 1177 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1180 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 1222 >+/* 1184 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1187 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1200 >+/* 1191 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1213 >+/* 1195 */ MCD_OPC_Decode, 244, 7, 196, 1, // Opcode: VLD2q8wb_fixed >+/* 1200 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1213 >+/* 1204 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1213 >+/* 1208 */ MCD_OPC_Decode, 240, 7, 196, 1, // Opcode: VLD2q8 >+/* 1213 */ MCD_OPC_CheckPredicate, 15, 49, 18, // Skip to: 5874 >+/* 1217 */ MCD_OPC_Decode, 245, 7, 196, 1, // Opcode: VLD2q8wb_register >+/* 1222 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 1264 >+/* 1226 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1229 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1242 >+/* 1233 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1255 >+/* 1237 */ MCD_OPC_Decode, 232, 7, 196, 1, // Opcode: VLD2q16wb_fixed >+/* 1242 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1255 >+/* 1246 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1255 >+/* 1250 */ MCD_OPC_Decode, 228, 7, 196, 1, // Opcode: VLD2q16 >+/* 1255 */ MCD_OPC_CheckPredicate, 15, 7, 18, // Skip to: 5874 >+/* 1259 */ MCD_OPC_Decode, 233, 7, 196, 1, // Opcode: VLD2q16wb_register >+/* 1264 */ MCD_OPC_FilterValue, 2, 254, 17, // Skip to: 5874 >+/* 1268 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1271 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1284 >+/* 1275 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 1297 >+/* 1279 */ MCD_OPC_Decode, 238, 7, 196, 1, // Opcode: VLD2q32wb_fixed >+/* 1284 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 1297 >+/* 1288 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 1297 >+/* 1292 */ MCD_OPC_Decode, 234, 7, 196, 1, // Opcode: VLD2q32 >+/* 1297 */ MCD_OPC_CheckPredicate, 15, 221, 17, // Skip to: 5874 >+/* 1301 */ MCD_OPC_Decode, 239, 7, 196, 1, // Opcode: VLD2q32wb_register >+/* 1306 */ MCD_OPC_FilterValue, 233, 3, 211, 17, // Skip to: 5874 >+/* 1311 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1326 >+/* 1315 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1326 >+/* 1321 */ MCD_OPC_Decode, 150, 9, 198, 1, // Opcode: VLD4LNd8 >+/* 1326 */ MCD_OPC_CheckPredicate, 15, 192, 17, // Skip to: 5874 >+/* 1330 */ MCD_OPC_Decode, 153, 9, 198, 1, // Opcode: VLD4LNd8_UPD >+/* 1335 */ MCD_OPC_FilterValue, 4, 16, 1, // Skip to: 1611 >+/* 1339 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1342 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 1477 >+/* 1346 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1349 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1441 >+/* 1354 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1357 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1385 >+/* 1361 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1376 >+/* 1365 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1376 >+/* 1371 */ MCD_OPC_Decode, 135, 16, 199, 1, // Opcode: VST3d8 >+/* 1376 */ MCD_OPC_CheckPredicate, 15, 142, 17, // Skip to: 5874 >+/* 1380 */ MCD_OPC_Decode, 138, 16, 199, 1, // Opcode: VST3d8_UPD >+/* 1385 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 1413 >+/* 1389 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1404 >+/* 1393 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1404 >+/* 1399 */ MCD_OPC_Decode, 255, 15, 199, 1, // Opcode: VST3d16 >+/* 1404 */ MCD_OPC_CheckPredicate, 15, 114, 17, // Skip to: 5874 >+/* 1408 */ MCD_OPC_Decode, 130, 16, 199, 1, // Opcode: VST3d16_UPD >+/* 1413 */ MCD_OPC_FilterValue, 4, 105, 17, // Skip to: 5874 >+/* 1417 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1432 >+/* 1421 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1432 >+/* 1427 */ MCD_OPC_Decode, 131, 16, 199, 1, // Opcode: VST3d32 >+/* 1432 */ MCD_OPC_CheckPredicate, 15, 86, 17, // Skip to: 5874 >+/* 1436 */ MCD_OPC_Decode, 134, 16, 199, 1, // Opcode: VST3d32_UPD >+/* 1441 */ MCD_OPC_FilterValue, 233, 3, 76, 17, // Skip to: 5874 >+/* 1446 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 1449 */ MCD_OPC_FilterValue, 0, 69, 17, // Skip to: 5874 >+/* 1453 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1468 >+/* 1457 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1468 >+/* 1463 */ MCD_OPC_Decode, 202, 14, 189, 1, // Opcode: VST1LNd16 >+/* 1468 */ MCD_OPC_CheckPredicate, 15, 50, 17, // Skip to: 5874 >+/* 1472 */ MCD_OPC_Decode, 203, 14, 189, 1, // Opcode: VST1LNd16_UPD >+/* 1477 */ MCD_OPC_FilterValue, 2, 41, 17, // Skip to: 5874 >+/* 1481 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1484 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1576 >+/* 1489 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 1492 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1520 >+/* 1496 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1511 >+/* 1500 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1511 >+/* 1506 */ MCD_OPC_Decode, 197, 8, 199, 1, // Opcode: VLD3d8 >+/* 1511 */ MCD_OPC_CheckPredicate, 15, 7, 17, // Skip to: 5874 >+/* 1515 */ MCD_OPC_Decode, 200, 8, 199, 1, // Opcode: VLD3d8_UPD >+/* 1520 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 1548 >+/* 1524 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1539 >+/* 1528 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1539 >+/* 1534 */ MCD_OPC_Decode, 189, 8, 199, 1, // Opcode: VLD3d16 >+/* 1539 */ MCD_OPC_CheckPredicate, 15, 235, 16, // Skip to: 5874 >+/* 1543 */ MCD_OPC_Decode, 192, 8, 199, 1, // Opcode: VLD3d16_UPD >+/* 1548 */ MCD_OPC_FilterValue, 4, 226, 16, // Skip to: 5874 >+/* 1552 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1567 >+/* 1556 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1567 >+/* 1562 */ MCD_OPC_Decode, 193, 8, 199, 1, // Opcode: VLD3d32 >+/* 1567 */ MCD_OPC_CheckPredicate, 15, 207, 16, // Skip to: 5874 >+/* 1571 */ MCD_OPC_Decode, 196, 8, 199, 1, // Opcode: VLD3d32_UPD >+/* 1576 */ MCD_OPC_FilterValue, 233, 3, 197, 16, // Skip to: 5874 >+/* 1581 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1596 >+/* 1585 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1596 >+/* 1591 */ MCD_OPC_Decode, 210, 6, 190, 1, // Opcode: VLD1LNd16 >+/* 1596 */ MCD_OPC_CheckPredicate, 15, 178, 16, // Skip to: 5874 >+/* 1600 */ MCD_OPC_CheckField, 5, 1, 0, 172, 16, // Skip to: 5874 >+/* 1606 */ MCD_OPC_Decode, 211, 6, 190, 1, // Opcode: VLD1LNd16_UPD >+/* 1611 */ MCD_OPC_FilterValue, 5, 89, 1, // Skip to: 1960 >+/* 1615 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 1618 */ MCD_OPC_FilterValue, 0, 3, 1, // Skip to: 1881 >+/* 1622 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1625 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 1753 >+/* 1629 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1632 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1724 >+/* 1637 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1640 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1668 >+/* 1644 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1659 >+/* 1648 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1659 >+/* 1654 */ MCD_OPC_Decode, 158, 16, 199, 1, // Opcode: VST3q8 >+/* 1659 */ MCD_OPC_CheckPredicate, 15, 115, 16, // Skip to: 5874 >+/* 1663 */ MCD_OPC_Decode, 160, 16, 199, 1, // Opcode: VST3q8_UPD >+/* 1668 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 1696 >+/* 1672 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1687 >+/* 1676 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1687 >+/* 1682 */ MCD_OPC_Decode, 148, 16, 199, 1, // Opcode: VST3q16 >+/* 1687 */ MCD_OPC_CheckPredicate, 15, 87, 16, // Skip to: 5874 >+/* 1691 */ MCD_OPC_Decode, 150, 16, 199, 1, // Opcode: VST3q16_UPD >+/* 1696 */ MCD_OPC_FilterValue, 2, 78, 16, // Skip to: 5874 >+/* 1700 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1715 >+/* 1704 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1715 >+/* 1710 */ MCD_OPC_Decode, 153, 16, 199, 1, // Opcode: VST3q32 >+/* 1715 */ MCD_OPC_CheckPredicate, 15, 59, 16, // Skip to: 5874 >+/* 1719 */ MCD_OPC_Decode, 155, 16, 199, 1, // Opcode: VST3q32_UPD >+/* 1724 */ MCD_OPC_FilterValue, 233, 3, 49, 16, // Skip to: 5874 >+/* 1729 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1744 >+/* 1733 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1744 >+/* 1739 */ MCD_OPC_Decode, 149, 15, 191, 1, // Opcode: VST2LNd16 >+/* 1744 */ MCD_OPC_CheckPredicate, 15, 30, 16, // Skip to: 5874 >+/* 1748 */ MCD_OPC_Decode, 152, 15, 191, 1, // Opcode: VST2LNd16_UPD >+/* 1753 */ MCD_OPC_FilterValue, 2, 21, 16, // Skip to: 5874 >+/* 1757 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1760 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 1852 >+/* 1765 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1768 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1796 >+/* 1772 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1787 >+/* 1776 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1787 >+/* 1782 */ MCD_OPC_Decode, 220, 8, 199, 1, // Opcode: VLD3q8 >+/* 1787 */ MCD_OPC_CheckPredicate, 15, 243, 15, // Skip to: 5874 >+/* 1791 */ MCD_OPC_Decode, 222, 8, 199, 1, // Opcode: VLD3q8_UPD >+/* 1796 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 1824 >+/* 1800 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1815 >+/* 1804 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1815 >+/* 1810 */ MCD_OPC_Decode, 210, 8, 199, 1, // Opcode: VLD3q16 >+/* 1815 */ MCD_OPC_CheckPredicate, 15, 215, 15, // Skip to: 5874 >+/* 1819 */ MCD_OPC_Decode, 212, 8, 199, 1, // Opcode: VLD3q16_UPD >+/* 1824 */ MCD_OPC_FilterValue, 2, 206, 15, // Skip to: 5874 >+/* 1828 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1843 >+/* 1832 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1843 >+/* 1838 */ MCD_OPC_Decode, 215, 8, 199, 1, // Opcode: VLD3q32 >+/* 1843 */ MCD_OPC_CheckPredicate, 15, 187, 15, // Skip to: 5874 >+/* 1847 */ MCD_OPC_Decode, 217, 8, 199, 1, // Opcode: VLD3q32_UPD >+/* 1852 */ MCD_OPC_FilterValue, 233, 3, 177, 15, // Skip to: 5874 >+/* 1857 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1872 >+/* 1861 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1872 >+/* 1867 */ MCD_OPC_Decode, 175, 7, 192, 1, // Opcode: VLD2LNd16 >+/* 1872 */ MCD_OPC_CheckPredicate, 15, 158, 15, // Skip to: 5874 >+/* 1876 */ MCD_OPC_Decode, 178, 7, 192, 1, // Opcode: VLD2LNd16_UPD >+/* 1881 */ MCD_OPC_FilterValue, 1, 149, 15, // Skip to: 5874 >+/* 1885 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1888 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 1924 >+/* 1892 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1895 */ MCD_OPC_FilterValue, 233, 3, 134, 15, // Skip to: 5874 >+/* 1900 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1915 >+/* 1904 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1915 >+/* 1910 */ MCD_OPC_Decode, 170, 15, 191, 1, // Opcode: VST2LNq16 >+/* 1915 */ MCD_OPC_CheckPredicate, 15, 115, 15, // Skip to: 5874 >+/* 1919 */ MCD_OPC_Decode, 173, 15, 191, 1, // Opcode: VST2LNq16_UPD >+/* 1924 */ MCD_OPC_FilterValue, 2, 106, 15, // Skip to: 5874 >+/* 1928 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1931 */ MCD_OPC_FilterValue, 233, 3, 98, 15, // Skip to: 5874 >+/* 1936 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 1951 >+/* 1940 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 1951 >+/* 1946 */ MCD_OPC_Decode, 196, 7, 192, 1, // Opcode: VLD2LNq16 >+/* 1951 */ MCD_OPC_CheckPredicate, 15, 79, 15, // Skip to: 5874 >+/* 1955 */ MCD_OPC_Decode, 199, 7, 192, 1, // Opcode: VLD2LNq16_UPD >+/* 1960 */ MCD_OPC_FilterValue, 6, 31, 2, // Skip to: 2507 >+/* 1964 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 1967 */ MCD_OPC_FilterValue, 0, 11, 1, // Skip to: 2238 >+/* 1971 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 1974 */ MCD_OPC_FilterValue, 232, 3, 195, 0, // Skip to: 2174 >+/* 1979 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 1982 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 2030 >+/* 1986 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1989 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2002 >+/* 1993 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 2021 >+/* 1997 */ MCD_OPC_Decode, 133, 15, 193, 1, // Opcode: VST1d8Twb_fixed >+/* 2002 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2021 >+/* 2006 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2021 >+/* 2010 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2021 >+/* 2016 */ MCD_OPC_Decode, 132, 15, 193, 1, // Opcode: VST1d8T >+/* 2021 */ MCD_OPC_CheckPredicate, 15, 9, 15, // Skip to: 5874 >+/* 2025 */ MCD_OPC_Decode, 134, 15, 193, 1, // Opcode: VST1d8Twb_register >+/* 2030 */ MCD_OPC_FilterValue, 1, 44, 0, // Skip to: 2078 >+/* 2034 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2037 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2050 >+/* 2041 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 2069 >+/* 2045 */ MCD_OPC_Decode, 228, 14, 193, 1, // Opcode: VST1d16Twb_fixed >+/* 2050 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2069 >+/* 2054 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2069 >+/* 2058 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2069 >+/* 2064 */ MCD_OPC_Decode, 227, 14, 193, 1, // Opcode: VST1d16T >+/* 2069 */ MCD_OPC_CheckPredicate, 15, 217, 14, // Skip to: 5874 >+/* 2073 */ MCD_OPC_Decode, 229, 14, 193, 1, // Opcode: VST1d16Twb_register >+/* 2078 */ MCD_OPC_FilterValue, 2, 44, 0, // Skip to: 2126 >+/* 2082 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2085 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2098 >+/* 2089 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 2117 >+/* 2093 */ MCD_OPC_Decode, 237, 14, 193, 1, // Opcode: VST1d32Twb_fixed >+/* 2098 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2117 >+/* 2102 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2117 >+/* 2106 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2117 >+/* 2112 */ MCD_OPC_Decode, 236, 14, 193, 1, // Opcode: VST1d32T >+/* 2117 */ MCD_OPC_CheckPredicate, 15, 169, 14, // Skip to: 5874 >+/* 2121 */ MCD_OPC_Decode, 238, 14, 193, 1, // Opcode: VST1d32Twb_register >+/* 2126 */ MCD_OPC_FilterValue, 3, 160, 14, // Skip to: 5874 >+/* 2130 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2133 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2146 >+/* 2137 */ MCD_OPC_CheckPredicate, 15, 24, 0, // Skip to: 2165 >+/* 2141 */ MCD_OPC_Decode, 252, 14, 193, 1, // Opcode: VST1d64Twb_fixed >+/* 2146 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2165 >+/* 2150 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2165 >+/* 2154 */ MCD_OPC_CheckField, 5, 1, 0, 5, 0, // Skip to: 2165 >+/* 2160 */ MCD_OPC_Decode, 248, 14, 193, 1, // Opcode: VST1d64T >+/* 2165 */ MCD_OPC_CheckPredicate, 15, 121, 14, // Skip to: 5874 >+/* 2169 */ MCD_OPC_Decode, 253, 14, 193, 1, // Opcode: VST1d64Twb_register >+/* 2174 */ MCD_OPC_FilterValue, 233, 3, 111, 14, // Skip to: 5874 >+/* 2179 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 2182 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 2210 >+/* 2186 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2201 >+/* 2190 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2201 >+/* 2196 */ MCD_OPC_Decode, 220, 15, 194, 1, // Opcode: VST3LNd16 >+/* 2201 */ MCD_OPC_CheckPredicate, 15, 85, 14, // Skip to: 5874 >+/* 2205 */ MCD_OPC_Decode, 223, 15, 194, 1, // Opcode: VST3LNd16_UPD >+/* 2210 */ MCD_OPC_FilterValue, 2, 76, 14, // Skip to: 5874 >+/* 2214 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2229 >+/* 2218 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2229 >+/* 2224 */ MCD_OPC_Decode, 241, 15, 194, 1, // Opcode: VST3LNq16 >+/* 2229 */ MCD_OPC_CheckPredicate, 15, 57, 14, // Skip to: 5874 >+/* 2233 */ MCD_OPC_Decode, 244, 15, 194, 1, // Opcode: VST3LNq16_UPD >+/* 2238 */ MCD_OPC_FilterValue, 2, 48, 14, // Skip to: 5874 >+/* 2242 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2245 */ MCD_OPC_FilterValue, 0, 215, 0, // Skip to: 2464 >+/* 2249 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2252 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2428 >+/* 2257 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2260 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2302 >+/* 2264 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2267 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2280 >+/* 2271 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2293 >+/* 2275 */ MCD_OPC_Decode, 141, 7, 193, 1, // Opcode: VLD1d8Twb_fixed >+/* 2280 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2293 >+/* 2284 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2293 >+/* 2288 */ MCD_OPC_Decode, 140, 7, 193, 1, // Opcode: VLD1d8T >+/* 2293 */ MCD_OPC_CheckPredicate, 15, 249, 13, // Skip to: 5874 >+/* 2297 */ MCD_OPC_Decode, 142, 7, 193, 1, // Opcode: VLD1d8Twb_register >+/* 2302 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2344 >+/* 2306 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2309 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2322 >+/* 2313 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2335 >+/* 2317 */ MCD_OPC_Decode, 236, 6, 193, 1, // Opcode: VLD1d16Twb_fixed >+/* 2322 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2335 >+/* 2326 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2335 >+/* 2330 */ MCD_OPC_Decode, 235, 6, 193, 1, // Opcode: VLD1d16T >+/* 2335 */ MCD_OPC_CheckPredicate, 15, 207, 13, // Skip to: 5874 >+/* 2339 */ MCD_OPC_Decode, 237, 6, 193, 1, // Opcode: VLD1d16Twb_register >+/* 2344 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2386 >+/* 2348 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2351 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2364 >+/* 2355 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2377 >+/* 2359 */ MCD_OPC_Decode, 245, 6, 193, 1, // Opcode: VLD1d32Twb_fixed >+/* 2364 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2377 >+/* 2368 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2377 >+/* 2372 */ MCD_OPC_Decode, 244, 6, 193, 1, // Opcode: VLD1d32T >+/* 2377 */ MCD_OPC_CheckPredicate, 15, 165, 13, // Skip to: 5874 >+/* 2381 */ MCD_OPC_Decode, 246, 6, 193, 1, // Opcode: VLD1d32Twb_register >+/* 2386 */ MCD_OPC_FilterValue, 3, 156, 13, // Skip to: 5874 >+/* 2390 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2393 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2406 >+/* 2397 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2419 >+/* 2401 */ MCD_OPC_Decode, 132, 7, 193, 1, // Opcode: VLD1d64Twb_fixed >+/* 2406 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2419 >+/* 2410 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2419 >+/* 2414 */ MCD_OPC_Decode, 128, 7, 193, 1, // Opcode: VLD1d64T >+/* 2419 */ MCD_OPC_CheckPredicate, 15, 123, 13, // Skip to: 5874 >+/* 2423 */ MCD_OPC_Decode, 133, 7, 193, 1, // Opcode: VLD1d64Twb_register >+/* 2428 */ MCD_OPC_FilterValue, 233, 3, 113, 13, // Skip to: 5874 >+/* 2433 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2436 */ MCD_OPC_FilterValue, 0, 106, 13, // Skip to: 5874 >+/* 2440 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2455 >+/* 2444 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2455 >+/* 2450 */ MCD_OPC_Decode, 154, 8, 195, 1, // Opcode: VLD3LNd16 >+/* 2455 */ MCD_OPC_CheckPredicate, 15, 87, 13, // Skip to: 5874 >+/* 2459 */ MCD_OPC_Decode, 157, 8, 195, 1, // Opcode: VLD3LNd16_UPD >+/* 2464 */ MCD_OPC_FilterValue, 1, 78, 13, // Skip to: 5874 >+/* 2468 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2471 */ MCD_OPC_FilterValue, 0, 71, 13, // Skip to: 5874 >+/* 2475 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2478 */ MCD_OPC_FilterValue, 233, 3, 63, 13, // Skip to: 5874 >+/* 2483 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2498 >+/* 2487 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2498 >+/* 2493 */ MCD_OPC_Decode, 175, 8, 195, 1, // Opcode: VLD3LNq16 >+/* 2498 */ MCD_OPC_CheckPredicate, 15, 44, 13, // Skip to: 5874 >+/* 2502 */ MCD_OPC_Decode, 178, 8, 195, 1, // Opcode: VLD3LNq16_UPD >+/* 2507 */ MCD_OPC_FilterValue, 7, 1, 2, // Skip to: 3024 >+/* 2511 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2514 */ MCD_OPC_FilterValue, 0, 171, 1, // Skip to: 2945 >+/* 2518 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2521 */ MCD_OPC_FilterValue, 0, 208, 0, // Skip to: 2733 >+/* 2525 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2528 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2704 >+/* 2533 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2536 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2578 >+/* 2540 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2543 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2556 >+/* 2547 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2569 >+/* 2551 */ MCD_OPC_Decode, 135, 15, 193, 1, // Opcode: VST1d8wb_fixed >+/* 2556 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2569 >+/* 2560 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2569 >+/* 2564 */ MCD_OPC_Decode, 128, 15, 193, 1, // Opcode: VST1d8 >+/* 2569 */ MCD_OPC_CheckPredicate, 15, 229, 12, // Skip to: 5874 >+/* 2573 */ MCD_OPC_Decode, 136, 15, 193, 1, // Opcode: VST1d8wb_register >+/* 2578 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2620 >+/* 2582 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2585 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2598 >+/* 2589 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2611 >+/* 2593 */ MCD_OPC_Decode, 230, 14, 193, 1, // Opcode: VST1d16wb_fixed >+/* 2598 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2611 >+/* 2602 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2611 >+/* 2606 */ MCD_OPC_Decode, 223, 14, 193, 1, // Opcode: VST1d16 >+/* 2611 */ MCD_OPC_CheckPredicate, 15, 187, 12, // Skip to: 5874 >+/* 2615 */ MCD_OPC_Decode, 231, 14, 193, 1, // Opcode: VST1d16wb_register >+/* 2620 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2662 >+/* 2624 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2627 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2640 >+/* 2631 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2653 >+/* 2635 */ MCD_OPC_Decode, 239, 14, 193, 1, // Opcode: VST1d32wb_fixed >+/* 2640 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2653 >+/* 2644 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2653 >+/* 2648 */ MCD_OPC_Decode, 232, 14, 193, 1, // Opcode: VST1d32 >+/* 2653 */ MCD_OPC_CheckPredicate, 15, 145, 12, // Skip to: 5874 >+/* 2657 */ MCD_OPC_Decode, 240, 14, 193, 1, // Opcode: VST1d32wb_register >+/* 2662 */ MCD_OPC_FilterValue, 3, 136, 12, // Skip to: 5874 >+/* 2666 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2669 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2682 >+/* 2673 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2695 >+/* 2677 */ MCD_OPC_Decode, 254, 14, 193, 1, // Opcode: VST1d64wb_fixed >+/* 2682 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2695 >+/* 2686 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2695 >+/* 2690 */ MCD_OPC_Decode, 241, 14, 193, 1, // Opcode: VST1d64 >+/* 2695 */ MCD_OPC_CheckPredicate, 15, 103, 12, // Skip to: 5874 >+/* 2699 */ MCD_OPC_Decode, 255, 14, 193, 1, // Opcode: VST1d64wb_register >+/* 2704 */ MCD_OPC_FilterValue, 233, 3, 93, 12, // Skip to: 5874 >+/* 2709 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2724 >+/* 2713 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2724 >+/* 2719 */ MCD_OPC_Decode, 172, 16, 197, 1, // Opcode: VST4LNd16 >+/* 2724 */ MCD_OPC_CheckPredicate, 15, 74, 12, // Skip to: 5874 >+/* 2728 */ MCD_OPC_Decode, 175, 16, 197, 1, // Opcode: VST4LNd16_UPD >+/* 2733 */ MCD_OPC_FilterValue, 2, 65, 12, // Skip to: 5874 >+/* 2737 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2740 */ MCD_OPC_FilterValue, 232, 3, 171, 0, // Skip to: 2916 >+/* 2745 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 2748 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 2790 >+/* 2752 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2755 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2768 >+/* 2759 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2781 >+/* 2763 */ MCD_OPC_Decode, 143, 7, 193, 1, // Opcode: VLD1d8wb_fixed >+/* 2768 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2781 >+/* 2772 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2781 >+/* 2776 */ MCD_OPC_Decode, 136, 7, 193, 1, // Opcode: VLD1d8 >+/* 2781 */ MCD_OPC_CheckPredicate, 15, 17, 12, // Skip to: 5874 >+/* 2785 */ MCD_OPC_Decode, 144, 7, 193, 1, // Opcode: VLD1d8wb_register >+/* 2790 */ MCD_OPC_FilterValue, 1, 38, 0, // Skip to: 2832 >+/* 2794 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2797 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2810 >+/* 2801 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2823 >+/* 2805 */ MCD_OPC_Decode, 238, 6, 193, 1, // Opcode: VLD1d16wb_fixed >+/* 2810 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2823 >+/* 2814 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2823 >+/* 2818 */ MCD_OPC_Decode, 231, 6, 193, 1, // Opcode: VLD1d16 >+/* 2823 */ MCD_OPC_CheckPredicate, 15, 231, 11, // Skip to: 5874 >+/* 2827 */ MCD_OPC_Decode, 239, 6, 193, 1, // Opcode: VLD1d16wb_register >+/* 2832 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 2874 >+/* 2836 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2839 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2852 >+/* 2843 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2865 >+/* 2847 */ MCD_OPC_Decode, 247, 6, 193, 1, // Opcode: VLD1d32wb_fixed >+/* 2852 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2865 >+/* 2856 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2865 >+/* 2860 */ MCD_OPC_Decode, 240, 6, 193, 1, // Opcode: VLD1d32 >+/* 2865 */ MCD_OPC_CheckPredicate, 15, 189, 11, // Skip to: 5874 >+/* 2869 */ MCD_OPC_Decode, 248, 6, 193, 1, // Opcode: VLD1d32wb_register >+/* 2874 */ MCD_OPC_FilterValue, 3, 180, 11, // Skip to: 5874 >+/* 2878 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 2881 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 2894 >+/* 2885 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 2907 >+/* 2889 */ MCD_OPC_Decode, 134, 7, 193, 1, // Opcode: VLD1d64wb_fixed >+/* 2894 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 2907 >+/* 2898 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 2907 >+/* 2902 */ MCD_OPC_Decode, 249, 6, 193, 1, // Opcode: VLD1d64 >+/* 2907 */ MCD_OPC_CheckPredicate, 15, 147, 11, // Skip to: 5874 >+/* 2911 */ MCD_OPC_Decode, 135, 7, 193, 1, // Opcode: VLD1d64wb_register >+/* 2916 */ MCD_OPC_FilterValue, 233, 3, 137, 11, // Skip to: 5874 >+/* 2921 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2936 >+/* 2925 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2936 >+/* 2931 */ MCD_OPC_Decode, 142, 9, 198, 1, // Opcode: VLD4LNd16 >+/* 2936 */ MCD_OPC_CheckPredicate, 15, 118, 11, // Skip to: 5874 >+/* 2940 */ MCD_OPC_Decode, 145, 9, 198, 1, // Opcode: VLD4LNd16_UPD >+/* 2945 */ MCD_OPC_FilterValue, 1, 109, 11, // Skip to: 5874 >+/* 2949 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2952 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 2988 >+/* 2956 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2959 */ MCD_OPC_FilterValue, 233, 3, 94, 11, // Skip to: 5874 >+/* 2964 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 2979 >+/* 2968 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 2979 >+/* 2974 */ MCD_OPC_Decode, 193, 16, 197, 1, // Opcode: VST4LNq16 >+/* 2979 */ MCD_OPC_CheckPredicate, 15, 75, 11, // Skip to: 5874 >+/* 2983 */ MCD_OPC_Decode, 196, 16, 197, 1, // Opcode: VST4LNq16_UPD >+/* 2988 */ MCD_OPC_FilterValue, 2, 66, 11, // Skip to: 5874 >+/* 2992 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 2995 */ MCD_OPC_FilterValue, 233, 3, 58, 11, // Skip to: 5874 >+/* 3000 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3015 >+/* 3004 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3015 >+/* 3010 */ MCD_OPC_Decode, 163, 9, 198, 1, // Opcode: VLD4LNq16 >+/* 3015 */ MCD_OPC_CheckPredicate, 15, 39, 11, // Skip to: 5874 >+/* 3019 */ MCD_OPC_Decode, 166, 9, 198, 1, // Opcode: VLD4LNq16_UPD >+/* 3024 */ MCD_OPC_FilterValue, 8, 131, 1, // Skip to: 3415 >+/* 3028 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3031 */ MCD_OPC_FilterValue, 0, 3, 1, // Skip to: 3294 >+/* 3035 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3038 */ MCD_OPC_FilterValue, 0, 124, 0, // Skip to: 3166 >+/* 3042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3045 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3137 >+/* 3050 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3053 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3095 >+/* 3057 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3060 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3073 >+/* 3064 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3086 >+/* 3068 */ MCD_OPC_Decode, 200, 15, 196, 1, // Opcode: VST2d8wb_fixed >+/* 3073 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3086 >+/* 3077 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3086 >+/* 3081 */ MCD_OPC_Decode, 199, 15, 196, 1, // Opcode: VST2d8 >+/* 3086 */ MCD_OPC_CheckPredicate, 15, 224, 10, // Skip to: 5874 >+/* 3090 */ MCD_OPC_Decode, 201, 15, 196, 1, // Opcode: VST2d8wb_register >+/* 3095 */ MCD_OPC_FilterValue, 1, 215, 10, // Skip to: 5874 >+/* 3099 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3102 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3115 >+/* 3106 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3128 >+/* 3110 */ MCD_OPC_Decode, 197, 15, 196, 1, // Opcode: VST2d32wb_fixed >+/* 3115 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3128 >+/* 3119 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3128 >+/* 3123 */ MCD_OPC_Decode, 196, 15, 196, 1, // Opcode: VST2d32 >+/* 3128 */ MCD_OPC_CheckPredicate, 15, 182, 10, // Skip to: 5874 >+/* 3132 */ MCD_OPC_Decode, 198, 15, 196, 1, // Opcode: VST2d32wb_register >+/* 3137 */ MCD_OPC_FilterValue, 233, 3, 172, 10, // Skip to: 5874 >+/* 3142 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3157 >+/* 3146 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3157 >+/* 3152 */ MCD_OPC_Decode, 204, 14, 189, 1, // Opcode: VST1LNd32 >+/* 3157 */ MCD_OPC_CheckPredicate, 15, 153, 10, // Skip to: 5874 >+/* 3161 */ MCD_OPC_Decode, 205, 14, 189, 1, // Opcode: VST1LNd32_UPD >+/* 3166 */ MCD_OPC_FilterValue, 2, 144, 10, // Skip to: 5874 >+/* 3170 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3173 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3265 >+/* 3178 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3181 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3223 >+/* 3185 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3188 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3201 >+/* 3192 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3214 >+/* 3196 */ MCD_OPC_Decode, 226, 7, 196, 1, // Opcode: VLD2d8wb_fixed >+/* 3201 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3214 >+/* 3205 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3214 >+/* 3209 */ MCD_OPC_Decode, 225, 7, 196, 1, // Opcode: VLD2d8 >+/* 3214 */ MCD_OPC_CheckPredicate, 15, 96, 10, // Skip to: 5874 >+/* 3218 */ MCD_OPC_Decode, 227, 7, 196, 1, // Opcode: VLD2d8wb_register >+/* 3223 */ MCD_OPC_FilterValue, 1, 87, 10, // Skip to: 5874 >+/* 3227 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3230 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3243 >+/* 3234 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3256 >+/* 3238 */ MCD_OPC_Decode, 223, 7, 196, 1, // Opcode: VLD2d32wb_fixed >+/* 3243 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3256 >+/* 3247 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3256 >+/* 3251 */ MCD_OPC_Decode, 222, 7, 196, 1, // Opcode: VLD2d32 >+/* 3256 */ MCD_OPC_CheckPredicate, 15, 54, 10, // Skip to: 5874 >+/* 3260 */ MCD_OPC_Decode, 224, 7, 196, 1, // Opcode: VLD2d32wb_register >+/* 3265 */ MCD_OPC_FilterValue, 233, 3, 44, 10, // Skip to: 5874 >+/* 3270 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3285 >+/* 3274 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3285 >+/* 3280 */ MCD_OPC_Decode, 212, 6, 190, 1, // Opcode: VLD1LNd32 >+/* 3285 */ MCD_OPC_CheckPredicate, 15, 25, 10, // Skip to: 5874 >+/* 3289 */ MCD_OPC_Decode, 213, 6, 190, 1, // Opcode: VLD1LNd32_UPD >+/* 3294 */ MCD_OPC_FilterValue, 1, 16, 10, // Skip to: 5874 >+/* 3298 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3301 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 3358 >+/* 3305 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3308 */ MCD_OPC_FilterValue, 0, 2, 10, // Skip to: 5874 >+/* 3312 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3315 */ MCD_OPC_FilterValue, 232, 3, 250, 9, // Skip to: 5874 >+/* 3320 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3323 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3336 >+/* 3327 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3349 >+/* 3331 */ MCD_OPC_Decode, 194, 15, 196, 1, // Opcode: VST2d16wb_fixed >+/* 3336 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3349 >+/* 3340 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3349 >+/* 3344 */ MCD_OPC_Decode, 193, 15, 196, 1, // Opcode: VST2d16 >+/* 3349 */ MCD_OPC_CheckPredicate, 15, 217, 9, // Skip to: 5874 >+/* 3353 */ MCD_OPC_Decode, 195, 15, 196, 1, // Opcode: VST2d16wb_register >+/* 3358 */ MCD_OPC_FilterValue, 2, 208, 9, // Skip to: 5874 >+/* 3362 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3365 */ MCD_OPC_FilterValue, 0, 201, 9, // Skip to: 5874 >+/* 3369 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3372 */ MCD_OPC_FilterValue, 232, 3, 193, 9, // Skip to: 5874 >+/* 3377 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3380 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3393 >+/* 3384 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3406 >+/* 3388 */ MCD_OPC_Decode, 220, 7, 196, 1, // Opcode: VLD2d16wb_fixed >+/* 3393 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3406 >+/* 3397 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3406 >+/* 3401 */ MCD_OPC_Decode, 219, 7, 196, 1, // Opcode: VLD2d16 >+/* 3406 */ MCD_OPC_CheckPredicate, 15, 160, 9, // Skip to: 5874 >+/* 3410 */ MCD_OPC_Decode, 221, 7, 196, 1, // Opcode: VLD2d16wb_register >+/* 3415 */ MCD_OPC_FilterValue, 9, 217, 1, // Skip to: 3892 >+/* 3419 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3422 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 3699 >+/* 3426 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3429 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 3564 >+/* 3433 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3436 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3528 >+/* 3441 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3444 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3486 >+/* 3448 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3451 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3464 >+/* 3455 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3477 >+/* 3459 */ MCD_OPC_Decode, 191, 15, 196, 1, // Opcode: VST2b8wb_fixed >+/* 3464 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3477 >+/* 3468 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3477 >+/* 3472 */ MCD_OPC_Decode, 190, 15, 196, 1, // Opcode: VST2b8 >+/* 3477 */ MCD_OPC_CheckPredicate, 15, 89, 9, // Skip to: 5874 >+/* 3481 */ MCD_OPC_Decode, 192, 15, 196, 1, // Opcode: VST2b8wb_register >+/* 3486 */ MCD_OPC_FilterValue, 1, 80, 9, // Skip to: 5874 >+/* 3490 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3493 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3506 >+/* 3497 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3519 >+/* 3501 */ MCD_OPC_Decode, 188, 15, 196, 1, // Opcode: VST2b32wb_fixed >+/* 3506 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3519 >+/* 3510 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3519 >+/* 3514 */ MCD_OPC_Decode, 187, 15, 196, 1, // Opcode: VST2b32 >+/* 3519 */ MCD_OPC_CheckPredicate, 15, 47, 9, // Skip to: 5874 >+/* 3523 */ MCD_OPC_Decode, 189, 15, 196, 1, // Opcode: VST2b32wb_register >+/* 3528 */ MCD_OPC_FilterValue, 233, 3, 37, 9, // Skip to: 5874 >+/* 3533 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3536 */ MCD_OPC_FilterValue, 0, 30, 9, // Skip to: 5874 >+/* 3540 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3555 >+/* 3544 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3555 >+/* 3550 */ MCD_OPC_Decode, 153, 15, 191, 1, // Opcode: VST2LNd32 >+/* 3555 */ MCD_OPC_CheckPredicate, 15, 11, 9, // Skip to: 5874 >+/* 3559 */ MCD_OPC_Decode, 156, 15, 191, 1, // Opcode: VST2LNd32_UPD >+/* 3564 */ MCD_OPC_FilterValue, 2, 2, 9, // Skip to: 5874 >+/* 3568 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3571 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 3663 >+/* 3576 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3579 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3621 >+/* 3583 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3586 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3599 >+/* 3590 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3612 >+/* 3594 */ MCD_OPC_Decode, 217, 7, 196, 1, // Opcode: VLD2b8wb_fixed >+/* 3599 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3612 >+/* 3603 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3612 >+/* 3607 */ MCD_OPC_Decode, 216, 7, 196, 1, // Opcode: VLD2b8 >+/* 3612 */ MCD_OPC_CheckPredicate, 15, 210, 8, // Skip to: 5874 >+/* 3616 */ MCD_OPC_Decode, 218, 7, 196, 1, // Opcode: VLD2b8wb_register >+/* 3621 */ MCD_OPC_FilterValue, 1, 201, 8, // Skip to: 5874 >+/* 3625 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3628 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3641 >+/* 3632 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3654 >+/* 3636 */ MCD_OPC_Decode, 214, 7, 196, 1, // Opcode: VLD2b32wb_fixed >+/* 3641 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3654 >+/* 3645 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3654 >+/* 3649 */ MCD_OPC_Decode, 213, 7, 196, 1, // Opcode: VLD2b32 >+/* 3654 */ MCD_OPC_CheckPredicate, 15, 168, 8, // Skip to: 5874 >+/* 3658 */ MCD_OPC_Decode, 215, 7, 196, 1, // Opcode: VLD2b32wb_register >+/* 3663 */ MCD_OPC_FilterValue, 233, 3, 158, 8, // Skip to: 5874 >+/* 3668 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3671 */ MCD_OPC_FilterValue, 0, 151, 8, // Skip to: 5874 >+/* 3675 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3690 >+/* 3679 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3690 >+/* 3685 */ MCD_OPC_Decode, 179, 7, 192, 1, // Opcode: VLD2LNd32 >+/* 3690 */ MCD_OPC_CheckPredicate, 15, 132, 8, // Skip to: 5874 >+/* 3694 */ MCD_OPC_Decode, 182, 7, 192, 1, // Opcode: VLD2LNd32_UPD >+/* 3699 */ MCD_OPC_FilterValue, 1, 123, 8, // Skip to: 5874 >+/* 3703 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3706 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3799 >+/* 3710 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3713 */ MCD_OPC_FilterValue, 232, 3, 45, 0, // Skip to: 3763 >+/* 3718 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3721 */ MCD_OPC_FilterValue, 0, 101, 8, // Skip to: 5874 >+/* 3725 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3728 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3741 >+/* 3732 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3754 >+/* 3736 */ MCD_OPC_Decode, 185, 15, 196, 1, // Opcode: VST2b16wb_fixed >+/* 3741 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3754 >+/* 3745 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3754 >+/* 3749 */ MCD_OPC_Decode, 184, 15, 196, 1, // Opcode: VST2b16 >+/* 3754 */ MCD_OPC_CheckPredicate, 15, 68, 8, // Skip to: 5874 >+/* 3758 */ MCD_OPC_Decode, 186, 15, 196, 1, // Opcode: VST2b16wb_register >+/* 3763 */ MCD_OPC_FilterValue, 233, 3, 58, 8, // Skip to: 5874 >+/* 3768 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3771 */ MCD_OPC_FilterValue, 0, 51, 8, // Skip to: 5874 >+/* 3775 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3790 >+/* 3779 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3790 >+/* 3785 */ MCD_OPC_Decode, 174, 15, 191, 1, // Opcode: VST2LNq32 >+/* 3790 */ MCD_OPC_CheckPredicate, 15, 32, 8, // Skip to: 5874 >+/* 3794 */ MCD_OPC_Decode, 177, 15, 191, 1, // Opcode: VST2LNq32_UPD >+/* 3799 */ MCD_OPC_FilterValue, 2, 23, 8, // Skip to: 5874 >+/* 3803 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3806 */ MCD_OPC_FilterValue, 232, 3, 45, 0, // Skip to: 3856 >+/* 3811 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3814 */ MCD_OPC_FilterValue, 0, 8, 8, // Skip to: 5874 >+/* 3818 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3821 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3834 >+/* 3825 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3847 >+/* 3829 */ MCD_OPC_Decode, 211, 7, 196, 1, // Opcode: VLD2b16wb_fixed >+/* 3834 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3847 >+/* 3838 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3847 >+/* 3842 */ MCD_OPC_Decode, 210, 7, 196, 1, // Opcode: VLD2b16 >+/* 3847 */ MCD_OPC_CheckPredicate, 15, 231, 7, // Skip to: 5874 >+/* 3851 */ MCD_OPC_Decode, 212, 7, 196, 1, // Opcode: VLD2b16wb_register >+/* 3856 */ MCD_OPC_FilterValue, 233, 3, 221, 7, // Skip to: 5874 >+/* 3861 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 3864 */ MCD_OPC_FilterValue, 0, 214, 7, // Skip to: 5874 >+/* 3868 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 3883 >+/* 3872 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 3883 >+/* 3878 */ MCD_OPC_Decode, 200, 7, 192, 1, // Opcode: VLD2LNq32 >+/* 3883 */ MCD_OPC_CheckPredicate, 15, 195, 7, // Skip to: 5874 >+/* 3887 */ MCD_OPC_Decode, 203, 7, 192, 1, // Opcode: VLD2LNq32_UPD >+/* 3892 */ MCD_OPC_FilterValue, 10, 45, 2, // Skip to: 4453 >+/* 3896 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 3899 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 4176 >+/* 3903 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3906 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 4041 >+/* 3910 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 3913 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4005 >+/* 3918 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 3921 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 3963 >+/* 3925 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3928 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3941 >+/* 3932 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3954 >+/* 3936 */ MCD_OPC_Decode, 147, 15, 193, 1, // Opcode: VST1q8wb_fixed >+/* 3941 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3954 >+/* 3945 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3954 >+/* 3949 */ MCD_OPC_Decode, 146, 15, 193, 1, // Opcode: VST1q8 >+/* 3954 */ MCD_OPC_CheckPredicate, 15, 124, 7, // Skip to: 5874 >+/* 3958 */ MCD_OPC_Decode, 148, 15, 193, 1, // Opcode: VST1q8wb_register >+/* 3963 */ MCD_OPC_FilterValue, 1, 115, 7, // Skip to: 5874 >+/* 3967 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 3970 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 3983 >+/* 3974 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 3996 >+/* 3978 */ MCD_OPC_Decode, 141, 15, 193, 1, // Opcode: VST1q32wb_fixed >+/* 3983 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 3996 >+/* 3987 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 3996 >+/* 3991 */ MCD_OPC_Decode, 140, 15, 193, 1, // Opcode: VST1q32 >+/* 3996 */ MCD_OPC_CheckPredicate, 15, 82, 7, // Skip to: 5874 >+/* 4000 */ MCD_OPC_Decode, 142, 15, 193, 1, // Opcode: VST1q32wb_register >+/* 4005 */ MCD_OPC_FilterValue, 233, 3, 72, 7, // Skip to: 5874 >+/* 4010 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4013 */ MCD_OPC_FilterValue, 0, 65, 7, // Skip to: 5874 >+/* 4017 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4032 >+/* 4021 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4032 >+/* 4027 */ MCD_OPC_Decode, 224, 15, 194, 1, // Opcode: VST3LNd32 >+/* 4032 */ MCD_OPC_CheckPredicate, 15, 46, 7, // Skip to: 5874 >+/* 4036 */ MCD_OPC_Decode, 227, 15, 194, 1, // Opcode: VST3LNd32_UPD >+/* 4041 */ MCD_OPC_FilterValue, 2, 37, 7, // Skip to: 5874 >+/* 4045 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4048 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4140 >+/* 4053 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4056 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4098 >+/* 4060 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4063 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4076 >+/* 4067 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4089 >+/* 4071 */ MCD_OPC_Decode, 155, 7, 193, 1, // Opcode: VLD1q8wb_fixed >+/* 4076 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4089 >+/* 4080 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4089 >+/* 4084 */ MCD_OPC_Decode, 154, 7, 193, 1, // Opcode: VLD1q8 >+/* 4089 */ MCD_OPC_CheckPredicate, 15, 245, 6, // Skip to: 5874 >+/* 4093 */ MCD_OPC_Decode, 156, 7, 193, 1, // Opcode: VLD1q8wb_register >+/* 4098 */ MCD_OPC_FilterValue, 1, 236, 6, // Skip to: 5874 >+/* 4102 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4105 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4118 >+/* 4109 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4131 >+/* 4113 */ MCD_OPC_Decode, 149, 7, 193, 1, // Opcode: VLD1q32wb_fixed >+/* 4118 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4131 >+/* 4122 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4131 >+/* 4126 */ MCD_OPC_Decode, 148, 7, 193, 1, // Opcode: VLD1q32 >+/* 4131 */ MCD_OPC_CheckPredicate, 15, 203, 6, // Skip to: 5874 >+/* 4135 */ MCD_OPC_Decode, 150, 7, 193, 1, // Opcode: VLD1q32wb_register >+/* 4140 */ MCD_OPC_FilterValue, 233, 3, 193, 6, // Skip to: 5874 >+/* 4145 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4148 */ MCD_OPC_FilterValue, 0, 186, 6, // Skip to: 5874 >+/* 4152 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4167 >+/* 4156 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4167 >+/* 4162 */ MCD_OPC_Decode, 158, 8, 195, 1, // Opcode: VLD3LNd32 >+/* 4167 */ MCD_OPC_CheckPredicate, 15, 167, 6, // Skip to: 5874 >+/* 4171 */ MCD_OPC_Decode, 161, 8, 195, 1, // Opcode: VLD3LNd32_UPD >+/* 4176 */ MCD_OPC_FilterValue, 1, 158, 6, // Skip to: 5874 >+/* 4180 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4183 */ MCD_OPC_FilterValue, 0, 131, 0, // Skip to: 4318 >+/* 4187 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4190 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4282 >+/* 4195 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4198 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4240 >+/* 4202 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4205 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4218 >+/* 4209 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4231 >+/* 4213 */ MCD_OPC_Decode, 138, 15, 193, 1, // Opcode: VST1q16wb_fixed >+/* 4218 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4231 >+/* 4222 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4231 >+/* 4226 */ MCD_OPC_Decode, 137, 15, 193, 1, // Opcode: VST1q16 >+/* 4231 */ MCD_OPC_CheckPredicate, 15, 103, 6, // Skip to: 5874 >+/* 4235 */ MCD_OPC_Decode, 139, 15, 193, 1, // Opcode: VST1q16wb_register >+/* 4240 */ MCD_OPC_FilterValue, 1, 94, 6, // Skip to: 5874 >+/* 4244 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4247 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4260 >+/* 4251 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4273 >+/* 4255 */ MCD_OPC_Decode, 144, 15, 193, 1, // Opcode: VST1q64wb_fixed >+/* 4260 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4273 >+/* 4264 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4273 >+/* 4268 */ MCD_OPC_Decode, 143, 15, 193, 1, // Opcode: VST1q64 >+/* 4273 */ MCD_OPC_CheckPredicate, 15, 61, 6, // Skip to: 5874 >+/* 4277 */ MCD_OPC_Decode, 145, 15, 193, 1, // Opcode: VST1q64wb_register >+/* 4282 */ MCD_OPC_FilterValue, 233, 3, 51, 6, // Skip to: 5874 >+/* 4287 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4290 */ MCD_OPC_FilterValue, 0, 44, 6, // Skip to: 5874 >+/* 4294 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4309 >+/* 4298 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4309 >+/* 4304 */ MCD_OPC_Decode, 245, 15, 194, 1, // Opcode: VST3LNq32 >+/* 4309 */ MCD_OPC_CheckPredicate, 15, 25, 6, // Skip to: 5874 >+/* 4313 */ MCD_OPC_Decode, 248, 15, 194, 1, // Opcode: VST3LNq32_UPD >+/* 4318 */ MCD_OPC_FilterValue, 2, 16, 6, // Skip to: 5874 >+/* 4322 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4325 */ MCD_OPC_FilterValue, 232, 3, 87, 0, // Skip to: 4417 >+/* 4330 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4333 */ MCD_OPC_FilterValue, 0, 38, 0, // Skip to: 4375 >+/* 4337 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4340 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4353 >+/* 4344 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4366 >+/* 4348 */ MCD_OPC_Decode, 146, 7, 193, 1, // Opcode: VLD1q16wb_fixed >+/* 4353 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4366 >+/* 4357 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4366 >+/* 4361 */ MCD_OPC_Decode, 145, 7, 193, 1, // Opcode: VLD1q16 >+/* 4366 */ MCD_OPC_CheckPredicate, 15, 224, 5, // Skip to: 5874 >+/* 4370 */ MCD_OPC_Decode, 147, 7, 193, 1, // Opcode: VLD1q16wb_register >+/* 4375 */ MCD_OPC_FilterValue, 1, 215, 5, // Skip to: 5874 >+/* 4379 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4382 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4395 >+/* 4386 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4408 >+/* 4390 */ MCD_OPC_Decode, 152, 7, 193, 1, // Opcode: VLD1q64wb_fixed >+/* 4395 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4408 >+/* 4399 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4408 >+/* 4403 */ MCD_OPC_Decode, 151, 7, 193, 1, // Opcode: VLD1q64 >+/* 4408 */ MCD_OPC_CheckPredicate, 15, 182, 5, // Skip to: 5874 >+/* 4412 */ MCD_OPC_Decode, 153, 7, 193, 1, // Opcode: VLD1q64wb_register >+/* 4417 */ MCD_OPC_FilterValue, 233, 3, 172, 5, // Skip to: 5874 >+/* 4422 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 4425 */ MCD_OPC_FilterValue, 0, 165, 5, // Skip to: 5874 >+/* 4429 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4444 >+/* 4433 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4444 >+/* 4439 */ MCD_OPC_Decode, 179, 8, 195, 1, // Opcode: VLD3LNq32 >+/* 4444 */ MCD_OPC_CheckPredicate, 15, 146, 5, // Skip to: 5874 >+/* 4448 */ MCD_OPC_Decode, 182, 8, 195, 1, // Opcode: VLD3LNq32_UPD >+/* 4453 */ MCD_OPC_FilterValue, 11, 161, 0, // Skip to: 4618 >+/* 4457 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 4460 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 4539 >+/* 4464 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4467 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 4503 >+/* 4471 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4474 */ MCD_OPC_FilterValue, 233, 3, 115, 5, // Skip to: 5874 >+/* 4479 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4494 >+/* 4483 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4494 >+/* 4489 */ MCD_OPC_Decode, 176, 16, 197, 1, // Opcode: VST4LNd32 >+/* 4494 */ MCD_OPC_CheckPredicate, 15, 96, 5, // Skip to: 5874 >+/* 4498 */ MCD_OPC_Decode, 179, 16, 197, 1, // Opcode: VST4LNd32_UPD >+/* 4503 */ MCD_OPC_FilterValue, 2, 87, 5, // Skip to: 5874 >+/* 4507 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4510 */ MCD_OPC_FilterValue, 233, 3, 79, 5, // Skip to: 5874 >+/* 4515 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4530 >+/* 4519 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4530 >+/* 4525 */ MCD_OPC_Decode, 146, 9, 198, 1, // Opcode: VLD4LNd32 >+/* 4530 */ MCD_OPC_CheckPredicate, 15, 60, 5, // Skip to: 5874 >+/* 4534 */ MCD_OPC_Decode, 149, 9, 198, 1, // Opcode: VLD4LNd32_UPD >+/* 4539 */ MCD_OPC_FilterValue, 1, 51, 5, // Skip to: 5874 >+/* 4543 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4546 */ MCD_OPC_FilterValue, 0, 32, 0, // Skip to: 4582 >+/* 4550 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4553 */ MCD_OPC_FilterValue, 233, 3, 36, 5, // Skip to: 5874 >+/* 4558 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4573 >+/* 4562 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4573 >+/* 4568 */ MCD_OPC_Decode, 197, 16, 197, 1, // Opcode: VST4LNq32 >+/* 4573 */ MCD_OPC_CheckPredicate, 15, 17, 5, // Skip to: 5874 >+/* 4577 */ MCD_OPC_Decode, 200, 16, 197, 1, // Opcode: VST4LNq32_UPD >+/* 4582 */ MCD_OPC_FilterValue, 2, 8, 5, // Skip to: 5874 >+/* 4586 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4589 */ MCD_OPC_FilterValue, 233, 3, 0, 5, // Skip to: 5874 >+/* 4594 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 4609 >+/* 4598 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 4609 >+/* 4604 */ MCD_OPC_Decode, 167, 9, 198, 1, // Opcode: VLD4LNq32 >+/* 4609 */ MCD_OPC_CheckPredicate, 15, 237, 4, // Skip to: 5874 >+/* 4613 */ MCD_OPC_Decode, 170, 9, 198, 1, // Opcode: VLD4LNq32_UPD >+/* 4618 */ MCD_OPC_FilterValue, 12, 89, 1, // Skip to: 4967 >+/* 4622 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4625 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 4682 >+/* 4629 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4632 */ MCD_OPC_FilterValue, 2, 214, 4, // Skip to: 5874 >+/* 4636 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4639 */ MCD_OPC_FilterValue, 233, 3, 206, 4, // Skip to: 5874 >+/* 4644 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4647 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4660 >+/* 4651 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4673 >+/* 4655 */ MCD_OPC_Decode, 199, 6, 200, 1, // Opcode: VLD1DUPd8wb_fixed >+/* 4660 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4673 >+/* 4664 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4673 >+/* 4668 */ MCD_OPC_Decode, 198, 6, 200, 1, // Opcode: VLD1DUPd8 >+/* 4673 */ MCD_OPC_CheckPredicate, 15, 173, 4, // Skip to: 5874 >+/* 4677 */ MCD_OPC_Decode, 200, 6, 200, 1, // Opcode: VLD1DUPd8wb_register >+/* 4682 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 4739 >+/* 4686 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4689 */ MCD_OPC_FilterValue, 2, 157, 4, // Skip to: 5874 >+/* 4693 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4696 */ MCD_OPC_FilterValue, 233, 3, 149, 4, // Skip to: 5874 >+/* 4701 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4704 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4717 >+/* 4708 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4730 >+/* 4712 */ MCD_OPC_Decode, 208, 6, 200, 1, // Opcode: VLD1DUPq8wb_fixed >+/* 4717 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4730 >+/* 4721 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4730 >+/* 4725 */ MCD_OPC_Decode, 207, 6, 200, 1, // Opcode: VLD1DUPq8 >+/* 4730 */ MCD_OPC_CheckPredicate, 15, 116, 4, // Skip to: 5874 >+/* 4734 */ MCD_OPC_Decode, 209, 6, 200, 1, // Opcode: VLD1DUPq8wb_register >+/* 4739 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 4796 >+/* 4743 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4746 */ MCD_OPC_FilterValue, 2, 100, 4, // Skip to: 5874 >+/* 4750 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4753 */ MCD_OPC_FilterValue, 233, 3, 92, 4, // Skip to: 5874 >+/* 4758 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4761 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4774 >+/* 4765 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4787 >+/* 4769 */ MCD_OPC_Decode, 193, 6, 200, 1, // Opcode: VLD1DUPd16wb_fixed >+/* 4774 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4787 >+/* 4778 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4787 >+/* 4782 */ MCD_OPC_Decode, 192, 6, 200, 1, // Opcode: VLD1DUPd16 >+/* 4787 */ MCD_OPC_CheckPredicate, 15, 59, 4, // Skip to: 5874 >+/* 4791 */ MCD_OPC_Decode, 194, 6, 200, 1, // Opcode: VLD1DUPd16wb_register >+/* 4796 */ MCD_OPC_FilterValue, 3, 53, 0, // Skip to: 4853 >+/* 4800 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4803 */ MCD_OPC_FilterValue, 2, 43, 4, // Skip to: 5874 >+/* 4807 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4810 */ MCD_OPC_FilterValue, 233, 3, 35, 4, // Skip to: 5874 >+/* 4815 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4818 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4831 >+/* 4822 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4844 >+/* 4826 */ MCD_OPC_Decode, 202, 6, 200, 1, // Opcode: VLD1DUPq16wb_fixed >+/* 4831 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4844 >+/* 4835 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4844 >+/* 4839 */ MCD_OPC_Decode, 201, 6, 200, 1, // Opcode: VLD1DUPq16 >+/* 4844 */ MCD_OPC_CheckPredicate, 15, 2, 4, // Skip to: 5874 >+/* 4848 */ MCD_OPC_Decode, 203, 6, 200, 1, // Opcode: VLD1DUPq16wb_register >+/* 4853 */ MCD_OPC_FilterValue, 4, 53, 0, // Skip to: 4910 >+/* 4857 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4860 */ MCD_OPC_FilterValue, 2, 242, 3, // Skip to: 5874 >+/* 4864 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4867 */ MCD_OPC_FilterValue, 233, 3, 234, 3, // Skip to: 5874 >+/* 4872 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4875 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4888 >+/* 4879 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4901 >+/* 4883 */ MCD_OPC_Decode, 196, 6, 200, 1, // Opcode: VLD1DUPd32wb_fixed >+/* 4888 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4901 >+/* 4892 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4901 >+/* 4896 */ MCD_OPC_Decode, 195, 6, 200, 1, // Opcode: VLD1DUPd32 >+/* 4901 */ MCD_OPC_CheckPredicate, 15, 201, 3, // Skip to: 5874 >+/* 4905 */ MCD_OPC_Decode, 197, 6, 200, 1, // Opcode: VLD1DUPd32wb_register >+/* 4910 */ MCD_OPC_FilterValue, 5, 192, 3, // Skip to: 5874 >+/* 4914 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4917 */ MCD_OPC_FilterValue, 2, 185, 3, // Skip to: 5874 >+/* 4921 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4924 */ MCD_OPC_FilterValue, 233, 3, 177, 3, // Skip to: 5874 >+/* 4929 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4932 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 4945 >+/* 4936 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 4958 >+/* 4940 */ MCD_OPC_Decode, 205, 6, 200, 1, // Opcode: VLD1DUPq32wb_fixed >+/* 4945 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 4958 >+/* 4949 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 4958 >+/* 4953 */ MCD_OPC_Decode, 204, 6, 200, 1, // Opcode: VLD1DUPq32 >+/* 4958 */ MCD_OPC_CheckPredicate, 15, 144, 3, // Skip to: 5874 >+/* 4962 */ MCD_OPC_Decode, 206, 6, 200, 1, // Opcode: VLD1DUPq32wb_register >+/* 4967 */ MCD_OPC_FilterValue, 13, 89, 1, // Skip to: 5316 >+/* 4971 */ MCD_OPC_ExtractField, 5, 3, // Inst{7-5} ... >+/* 4974 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 5031 >+/* 4978 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 4981 */ MCD_OPC_FilterValue, 2, 121, 3, // Skip to: 5874 >+/* 4985 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 4988 */ MCD_OPC_FilterValue, 233, 3, 113, 3, // Skip to: 5874 >+/* 4993 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 4996 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5009 >+/* 5000 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5022 >+/* 5004 */ MCD_OPC_Decode, 170, 7, 201, 1, // Opcode: VLD2DUPd8wb_fixed >+/* 5009 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5022 >+/* 5013 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5022 >+/* 5017 */ MCD_OPC_Decode, 169, 7, 201, 1, // Opcode: VLD2DUPd8 >+/* 5022 */ MCD_OPC_CheckPredicate, 15, 80, 3, // Skip to: 5874 >+/* 5026 */ MCD_OPC_Decode, 171, 7, 201, 1, // Opcode: VLD2DUPd8wb_register >+/* 5031 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 5088 >+/* 5035 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5038 */ MCD_OPC_FilterValue, 2, 64, 3, // Skip to: 5874 >+/* 5042 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5045 */ MCD_OPC_FilterValue, 233, 3, 56, 3, // Skip to: 5874 >+/* 5050 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5053 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5066 >+/* 5057 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5079 >+/* 5061 */ MCD_OPC_Decode, 173, 7, 201, 1, // Opcode: VLD2DUPd8x2wb_fixed >+/* 5066 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5079 >+/* 5070 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5079 >+/* 5074 */ MCD_OPC_Decode, 172, 7, 201, 1, // Opcode: VLD2DUPd8x2 >+/* 5079 */ MCD_OPC_CheckPredicate, 15, 23, 3, // Skip to: 5874 >+/* 5083 */ MCD_OPC_Decode, 174, 7, 201, 1, // Opcode: VLD2DUPd8x2wb_register >+/* 5088 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 5145 >+/* 5092 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5095 */ MCD_OPC_FilterValue, 2, 7, 3, // Skip to: 5874 >+/* 5099 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5102 */ MCD_OPC_FilterValue, 233, 3, 255, 2, // Skip to: 5874 >+/* 5107 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5110 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5123 >+/* 5114 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5136 >+/* 5118 */ MCD_OPC_Decode, 158, 7, 201, 1, // Opcode: VLD2DUPd16wb_fixed >+/* 5123 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5136 >+/* 5127 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5136 >+/* 5131 */ MCD_OPC_Decode, 157, 7, 201, 1, // Opcode: VLD2DUPd16 >+/* 5136 */ MCD_OPC_CheckPredicate, 15, 222, 2, // Skip to: 5874 >+/* 5140 */ MCD_OPC_Decode, 159, 7, 201, 1, // Opcode: VLD2DUPd16wb_register >+/* 5145 */ MCD_OPC_FilterValue, 3, 53, 0, // Skip to: 5202 >+/* 5149 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5152 */ MCD_OPC_FilterValue, 2, 206, 2, // Skip to: 5874 >+/* 5156 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5159 */ MCD_OPC_FilterValue, 233, 3, 198, 2, // Skip to: 5874 >+/* 5164 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5167 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5180 >+/* 5171 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5193 >+/* 5175 */ MCD_OPC_Decode, 161, 7, 201, 1, // Opcode: VLD2DUPd16x2wb_fixed >+/* 5180 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5193 >+/* 5184 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5193 >+/* 5188 */ MCD_OPC_Decode, 160, 7, 201, 1, // Opcode: VLD2DUPd16x2 >+/* 5193 */ MCD_OPC_CheckPredicate, 15, 165, 2, // Skip to: 5874 >+/* 5197 */ MCD_OPC_Decode, 162, 7, 201, 1, // Opcode: VLD2DUPd16x2wb_register >+/* 5202 */ MCD_OPC_FilterValue, 4, 53, 0, // Skip to: 5259 >+/* 5206 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5209 */ MCD_OPC_FilterValue, 2, 149, 2, // Skip to: 5874 >+/* 5213 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5216 */ MCD_OPC_FilterValue, 233, 3, 141, 2, // Skip to: 5874 >+/* 5221 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5224 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5237 >+/* 5228 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5250 >+/* 5232 */ MCD_OPC_Decode, 164, 7, 201, 1, // Opcode: VLD2DUPd32wb_fixed >+/* 5237 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5250 >+/* 5241 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5250 >+/* 5245 */ MCD_OPC_Decode, 163, 7, 201, 1, // Opcode: VLD2DUPd32 >+/* 5250 */ MCD_OPC_CheckPredicate, 15, 108, 2, // Skip to: 5874 >+/* 5254 */ MCD_OPC_Decode, 165, 7, 201, 1, // Opcode: VLD2DUPd32wb_register >+/* 5259 */ MCD_OPC_FilterValue, 5, 99, 2, // Skip to: 5874 >+/* 5263 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5266 */ MCD_OPC_FilterValue, 2, 92, 2, // Skip to: 5874 >+/* 5270 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5273 */ MCD_OPC_FilterValue, 233, 3, 84, 2, // Skip to: 5874 >+/* 5278 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 5281 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 5294 >+/* 5285 */ MCD_OPC_CheckPredicate, 15, 18, 0, // Skip to: 5307 >+/* 5289 */ MCD_OPC_Decode, 167, 7, 201, 1, // Opcode: VLD2DUPd32x2wb_fixed >+/* 5294 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 5307 >+/* 5298 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5307 >+/* 5302 */ MCD_OPC_Decode, 166, 7, 201, 1, // Opcode: VLD2DUPd32x2 >+/* 5307 */ MCD_OPC_CheckPredicate, 15, 51, 2, // Skip to: 5874 >+/* 5311 */ MCD_OPC_Decode, 168, 7, 201, 1, // Opcode: VLD2DUPd32x2wb_register >+/* 5316 */ MCD_OPC_FilterValue, 14, 5, 1, // Skip to: 5581 >+/* 5320 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5323 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5366 >+/* 5327 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5330 */ MCD_OPC_FilterValue, 2, 28, 2, // Skip to: 5874 >+/* 5334 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5337 */ MCD_OPC_FilterValue, 233, 3, 20, 2, // Skip to: 5874 >+/* 5342 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5357 >+/* 5346 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5357 >+/* 5352 */ MCD_OPC_Decode, 254, 7, 202, 1, // Opcode: VLD3DUPd8 >+/* 5357 */ MCD_OPC_CheckPredicate, 15, 1, 2, // Skip to: 5874 >+/* 5361 */ MCD_OPC_Decode, 129, 8, 202, 1, // Opcode: VLD3DUPd8_UPD >+/* 5366 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 5409 >+/* 5370 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5373 */ MCD_OPC_FilterValue, 2, 241, 1, // Skip to: 5874 >+/* 5377 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5380 */ MCD_OPC_FilterValue, 233, 3, 233, 1, // Skip to: 5874 >+/* 5385 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5400 >+/* 5389 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5400 >+/* 5395 */ MCD_OPC_Decode, 143, 8, 202, 1, // Opcode: VLD3DUPq8 >+/* 5400 */ MCD_OPC_CheckPredicate, 15, 214, 1, // Skip to: 5874 >+/* 5404 */ MCD_OPC_Decode, 144, 8, 202, 1, // Opcode: VLD3DUPq8_UPD >+/* 5409 */ MCD_OPC_FilterValue, 4, 39, 0, // Skip to: 5452 >+/* 5413 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5416 */ MCD_OPC_FilterValue, 2, 198, 1, // Skip to: 5874 >+/* 5420 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5423 */ MCD_OPC_FilterValue, 233, 3, 190, 1, // Skip to: 5874 >+/* 5428 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5443 >+/* 5432 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5443 >+/* 5438 */ MCD_OPC_Decode, 246, 7, 202, 1, // Opcode: VLD3DUPd16 >+/* 5443 */ MCD_OPC_CheckPredicate, 15, 171, 1, // Skip to: 5874 >+/* 5447 */ MCD_OPC_Decode, 249, 7, 202, 1, // Opcode: VLD3DUPd16_UPD >+/* 5452 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 5495 >+/* 5456 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5459 */ MCD_OPC_FilterValue, 2, 155, 1, // Skip to: 5874 >+/* 5463 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5466 */ MCD_OPC_FilterValue, 233, 3, 147, 1, // Skip to: 5874 >+/* 5471 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5486 >+/* 5475 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5486 >+/* 5481 */ MCD_OPC_Decode, 139, 8, 202, 1, // Opcode: VLD3DUPq16 >+/* 5486 */ MCD_OPC_CheckPredicate, 15, 128, 1, // Skip to: 5874 >+/* 5490 */ MCD_OPC_Decode, 140, 8, 202, 1, // Opcode: VLD3DUPq16_UPD >+/* 5495 */ MCD_OPC_FilterValue, 8, 39, 0, // Skip to: 5538 >+/* 5499 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5502 */ MCD_OPC_FilterValue, 2, 112, 1, // Skip to: 5874 >+/* 5506 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5509 */ MCD_OPC_FilterValue, 233, 3, 104, 1, // Skip to: 5874 >+/* 5514 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5529 >+/* 5518 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5529 >+/* 5524 */ MCD_OPC_Decode, 250, 7, 202, 1, // Opcode: VLD3DUPd32 >+/* 5529 */ MCD_OPC_CheckPredicate, 15, 85, 1, // Skip to: 5874 >+/* 5533 */ MCD_OPC_Decode, 253, 7, 202, 1, // Opcode: VLD3DUPd32_UPD >+/* 5538 */ MCD_OPC_FilterValue, 10, 76, 1, // Skip to: 5874 >+/* 5542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5545 */ MCD_OPC_FilterValue, 2, 69, 1, // Skip to: 5874 >+/* 5549 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5552 */ MCD_OPC_FilterValue, 233, 3, 61, 1, // Skip to: 5874 >+/* 5557 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5572 >+/* 5561 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5572 >+/* 5567 */ MCD_OPC_Decode, 141, 8, 202, 1, // Opcode: VLD3DUPq32 >+/* 5572 */ MCD_OPC_CheckPredicate, 15, 42, 1, // Skip to: 5874 >+/* 5576 */ MCD_OPC_Decode, 142, 8, 202, 1, // Opcode: VLD3DUPq32_UPD >+/* 5581 */ MCD_OPC_FilterValue, 15, 33, 1, // Skip to: 5874 >+/* 5585 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 5588 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 5731 >+/* 5592 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5595 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 5688 >+/* 5599 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5602 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5645 >+/* 5606 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5609 */ MCD_OPC_FilterValue, 2, 5, 1, // Skip to: 5874 >+/* 5613 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5616 */ MCD_OPC_FilterValue, 233, 3, 253, 0, // Skip to: 5874 >+/* 5621 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5636 >+/* 5625 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5636 >+/* 5631 */ MCD_OPC_Decode, 242, 8, 203, 1, // Opcode: VLD4DUPd8 >+/* 5636 */ MCD_OPC_CheckPredicate, 15, 234, 0, // Skip to: 5874 >+/* 5640 */ MCD_OPC_Decode, 245, 8, 203, 1, // Opcode: VLD4DUPd8_UPD >+/* 5645 */ MCD_OPC_FilterValue, 1, 225, 0, // Skip to: 5874 >+/* 5649 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5652 */ MCD_OPC_FilterValue, 2, 218, 0, // Skip to: 5874 >+/* 5656 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5659 */ MCD_OPC_FilterValue, 233, 3, 210, 0, // Skip to: 5874 >+/* 5664 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5679 >+/* 5668 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5679 >+/* 5674 */ MCD_OPC_Decode, 234, 8, 203, 1, // Opcode: VLD4DUPd16 >+/* 5679 */ MCD_OPC_CheckPredicate, 15, 191, 0, // Skip to: 5874 >+/* 5683 */ MCD_OPC_Decode, 237, 8, 203, 1, // Opcode: VLD4DUPd16_UPD >+/* 5688 */ MCD_OPC_FilterValue, 1, 182, 0, // Skip to: 5874 >+/* 5692 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5695 */ MCD_OPC_FilterValue, 2, 175, 0, // Skip to: 5874 >+/* 5699 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5702 */ MCD_OPC_FilterValue, 233, 3, 167, 0, // Skip to: 5874 >+/* 5707 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5722 >+/* 5711 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5722 >+/* 5717 */ MCD_OPC_Decode, 238, 8, 203, 1, // Opcode: VLD4DUPd32 >+/* 5722 */ MCD_OPC_CheckPredicate, 15, 148, 0, // Skip to: 5874 >+/* 5726 */ MCD_OPC_Decode, 241, 8, 203, 1, // Opcode: VLD4DUPd32_UPD >+/* 5731 */ MCD_OPC_FilterValue, 1, 139, 0, // Skip to: 5874 >+/* 5735 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 5738 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 5831 >+/* 5742 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 5745 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5788 >+/* 5749 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5752 */ MCD_OPC_FilterValue, 2, 118, 0, // Skip to: 5874 >+/* 5756 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5759 */ MCD_OPC_FilterValue, 233, 3, 110, 0, // Skip to: 5874 >+/* 5764 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5779 >+/* 5768 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5779 >+/* 5774 */ MCD_OPC_Decode, 131, 9, 203, 1, // Opcode: VLD4DUPq8 >+/* 5779 */ MCD_OPC_CheckPredicate, 15, 91, 0, // Skip to: 5874 >+/* 5783 */ MCD_OPC_Decode, 132, 9, 203, 1, // Opcode: VLD4DUPq8_UPD >+/* 5788 */ MCD_OPC_FilterValue, 1, 82, 0, // Skip to: 5874 >+/* 5792 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5795 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 5874 >+/* 5799 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5802 */ MCD_OPC_FilterValue, 233, 3, 67, 0, // Skip to: 5874 >+/* 5807 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5822 >+/* 5811 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5822 >+/* 5817 */ MCD_OPC_Decode, 255, 8, 203, 1, // Opcode: VLD4DUPq16 >+/* 5822 */ MCD_OPC_CheckPredicate, 15, 48, 0, // Skip to: 5874 >+/* 5826 */ MCD_OPC_Decode, 128, 9, 203, 1, // Opcode: VLD4DUPq16_UPD >+/* 5831 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 5874 >+/* 5835 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 5838 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 5874 >+/* 5842 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 5845 */ MCD_OPC_FilterValue, 233, 3, 24, 0, // Skip to: 5874 >+/* 5850 */ MCD_OPC_CheckPredicate, 15, 11, 0, // Skip to: 5865 >+/* 5854 */ MCD_OPC_CheckField, 0, 4, 15, 5, 0, // Skip to: 5865 >+/* 5860 */ MCD_OPC_Decode, 129, 9, 203, 1, // Opcode: VLD4DUPq32 >+/* 5865 */ MCD_OPC_CheckPredicate, 15, 5, 0, // Skip to: 5874 >+/* 5869 */ MCD_OPC_Decode, 130, 9, 203, 1, // Opcode: VLD4DUPq32_UPD >+/* 5874 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableThumb16[] = { >+/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 22 >+/* 7 */ MCD_OPC_CheckPredicate, 19, 210, 3, // Skip to: 989 >+/* 11 */ MCD_OPC_CheckField, 6, 6, 0, 204, 3, // Skip to: 989 >+/* 17 */ MCD_OPC_Decode, 188, 21, 204, 1, // Opcode: tMOVSr >+/* 22 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 41 >+/* 26 */ MCD_OPC_CheckPredicate, 19, 191, 3, // Skip to: 989 >+/* 30 */ MCD_OPC_CheckField, 11, 1, 1, 185, 3, // Skip to: 989 >+/* 36 */ MCD_OPC_Decode, 158, 21, 205, 1, // Opcode: tCMPi8 >+/* 41 */ MCD_OPC_FilterValue, 4, 186, 0, // Skip to: 231 >+/* 45 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 48 */ MCD_OPC_FilterValue, 0, 166, 0, // Skip to: 218 >+/* 52 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... >+/* 55 */ MCD_OPC_FilterValue, 2, 42, 0, // Skip to: 101 >+/* 59 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 62 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 75 >+/* 66 */ MCD_OPC_CheckPredicate, 19, 151, 3, // Skip to: 989 >+/* 70 */ MCD_OPC_Decode, 225, 21, 204, 1, // Opcode: tTST >+/* 75 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 88 >+/* 79 */ MCD_OPC_CheckPredicate, 19, 138, 3, // Skip to: 989 >+/* 83 */ MCD_OPC_Decode, 159, 21, 204, 1, // Opcode: tCMPr >+/* 88 */ MCD_OPC_FilterValue, 3, 129, 3, // Skip to: 989 >+/* 92 */ MCD_OPC_CheckPredicate, 19, 125, 3, // Skip to: 989 >+/* 96 */ MCD_OPC_Decode, 156, 21, 204, 1, // Opcode: tCMNz >+/* 101 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 150 >+/* 105 */ MCD_OPC_CheckPredicate, 19, 11, 0, // Skip to: 120 >+/* 109 */ MCD_OPC_CheckField, 3, 4, 13, 5, 0, // Skip to: 120 >+/* 115 */ MCD_OPC_Decode, 129, 21, 206, 1, // Opcode: tADDrSP >+/* 120 */ MCD_OPC_CheckPredicate, 19, 17, 0, // Skip to: 141 >+/* 124 */ MCD_OPC_CheckField, 7, 1, 1, 11, 0, // Skip to: 141 >+/* 130 */ MCD_OPC_CheckField, 0, 3, 5, 5, 0, // Skip to: 141 >+/* 136 */ MCD_OPC_Decode, 133, 21, 206, 1, // Opcode: tADDspr >+/* 141 */ MCD_OPC_CheckPredicate, 19, 76, 3, // Skip to: 989 >+/* 145 */ MCD_OPC_Decode, 254, 20, 207, 1, // Opcode: tADDhirr >+/* 150 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 163 >+/* 154 */ MCD_OPC_CheckPredicate, 19, 63, 3, // Skip to: 989 >+/* 158 */ MCD_OPC_Decode, 157, 21, 208, 1, // Opcode: tCMPhir >+/* 163 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 176 >+/* 167 */ MCD_OPC_CheckPredicate, 19, 50, 3, // Skip to: 989 >+/* 171 */ MCD_OPC_Decode, 190, 21, 208, 1, // Opcode: tMOVr >+/* 176 */ MCD_OPC_FilterValue, 7, 41, 3, // Skip to: 989 >+/* 180 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 183 */ MCD_OPC_FilterValue, 0, 12, 0, // Skip to: 199 >+/* 187 */ MCD_OPC_CheckPredicate, 19, 30, 3, // Skip to: 989 >+/* 191 */ MCD_OPC_SoftFail, 7, 0, >+/* 194 */ MCD_OPC_Decode, 148, 21, 209, 1, // Opcode: tBX >+/* 199 */ MCD_OPC_FilterValue, 1, 18, 3, // Skip to: 989 >+/* 203 */ MCD_OPC_CheckPredicate, 20, 14, 3, // Skip to: 989 >+/* 207 */ MCD_OPC_CheckField, 0, 3, 0, 8, 3, // Skip to: 989 >+/* 213 */ MCD_OPC_Decode, 145, 21, 209, 1, // Opcode: tBLXr >+/* 218 */ MCD_OPC_FilterValue, 1, 255, 2, // Skip to: 989 >+/* 222 */ MCD_OPC_CheckPredicate, 19, 251, 2, // Skip to: 989 >+/* 226 */ MCD_OPC_Decode, 177, 21, 210, 1, // Opcode: tLDRpci >+/* 231 */ MCD_OPC_FilterValue, 5, 107, 0, // Skip to: 342 >+/* 235 */ MCD_OPC_ExtractField, 9, 3, // Inst{11-9} ... >+/* 238 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 19, 231, 2, // Skip to: 989 >+/* 246 */ MCD_OPC_Decode, 211, 21, 211, 1, // Opcode: tSTRr >+/* 251 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 264 >+/* 255 */ MCD_OPC_CheckPredicate, 19, 218, 2, // Skip to: 989 >+/* 259 */ MCD_OPC_Decode, 209, 21, 211, 1, // Opcode: tSTRHr >+/* 264 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 277 >+/* 268 */ MCD_OPC_CheckPredicate, 19, 205, 2, // Skip to: 989 >+/* 272 */ MCD_OPC_Decode, 207, 21, 211, 1, // Opcode: tSTRBr >+/* 277 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 290 >+/* 281 */ MCD_OPC_CheckPredicate, 19, 192, 2, // Skip to: 989 >+/* 285 */ MCD_OPC_Decode, 174, 21, 211, 1, // Opcode: tLDRSB >+/* 290 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 303 >+/* 294 */ MCD_OPC_CheckPredicate, 19, 179, 2, // Skip to: 989 >+/* 298 */ MCD_OPC_Decode, 179, 21, 211, 1, // Opcode: tLDRr >+/* 303 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 316 >+/* 307 */ MCD_OPC_CheckPredicate, 19, 166, 2, // Skip to: 989 >+/* 311 */ MCD_OPC_Decode, 171, 21, 211, 1, // Opcode: tLDRHr >+/* 316 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 329 >+/* 320 */ MCD_OPC_CheckPredicate, 19, 153, 2, // Skip to: 989 >+/* 324 */ MCD_OPC_Decode, 169, 21, 211, 1, // Opcode: tLDRBr >+/* 329 */ MCD_OPC_FilterValue, 7, 144, 2, // Skip to: 989 >+/* 333 */ MCD_OPC_CheckPredicate, 19, 140, 2, // Skip to: 989 >+/* 337 */ MCD_OPC_Decode, 175, 21, 211, 1, // Opcode: tLDRSH >+/* 342 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 375 >+/* 346 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 349 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 362 >+/* 353 */ MCD_OPC_CheckPredicate, 19, 120, 2, // Skip to: 989 >+/* 357 */ MCD_OPC_Decode, 210, 21, 212, 1, // Opcode: tSTRi >+/* 362 */ MCD_OPC_FilterValue, 1, 111, 2, // Skip to: 989 >+/* 366 */ MCD_OPC_CheckPredicate, 19, 107, 2, // Skip to: 989 >+/* 370 */ MCD_OPC_Decode, 176, 21, 212, 1, // Opcode: tLDRi >+/* 375 */ MCD_OPC_FilterValue, 7, 29, 0, // Skip to: 408 >+/* 379 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 382 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 395 >+/* 386 */ MCD_OPC_CheckPredicate, 19, 87, 2, // Skip to: 989 >+/* 390 */ MCD_OPC_Decode, 206, 21, 212, 1, // Opcode: tSTRBi >+/* 395 */ MCD_OPC_FilterValue, 1, 78, 2, // Skip to: 989 >+/* 399 */ MCD_OPC_CheckPredicate, 19, 74, 2, // Skip to: 989 >+/* 403 */ MCD_OPC_Decode, 168, 21, 212, 1, // Opcode: tLDRBi >+/* 408 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 441 >+/* 412 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 415 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 428 >+/* 419 */ MCD_OPC_CheckPredicate, 19, 54, 2, // Skip to: 989 >+/* 423 */ MCD_OPC_Decode, 208, 21, 212, 1, // Opcode: tSTRHi >+/* 428 */ MCD_OPC_FilterValue, 1, 45, 2, // Skip to: 989 >+/* 432 */ MCD_OPC_CheckPredicate, 19, 41, 2, // Skip to: 989 >+/* 436 */ MCD_OPC_Decode, 170, 21, 212, 1, // Opcode: tLDRHi >+/* 441 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 474 >+/* 445 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 448 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 461 >+/* 452 */ MCD_OPC_CheckPredicate, 19, 21, 2, // Skip to: 989 >+/* 456 */ MCD_OPC_Decode, 212, 21, 213, 1, // Opcode: tSTRspi >+/* 461 */ MCD_OPC_FilterValue, 1, 12, 2, // Skip to: 989 >+/* 465 */ MCD_OPC_CheckPredicate, 19, 8, 2, // Skip to: 989 >+/* 469 */ MCD_OPC_Decode, 180, 21, 213, 1, // Opcode: tLDRspi >+/* 474 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 507 >+/* 478 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 481 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 494 >+/* 485 */ MCD_OPC_CheckPredicate, 19, 244, 1, // Skip to: 989 >+/* 489 */ MCD_OPC_Decode, 136, 21, 214, 1, // Opcode: tADR >+/* 494 */ MCD_OPC_FilterValue, 1, 235, 1, // Skip to: 989 >+/* 498 */ MCD_OPC_CheckPredicate, 19, 231, 1, // Skip to: 989 >+/* 502 */ MCD_OPC_Decode, 130, 21, 214, 1, // Opcode: tADDrSPi >+/* 507 */ MCD_OPC_FilterValue, 11, 113, 1, // Skip to: 880 >+/* 511 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 514 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 647 >+/* 518 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 521 */ MCD_OPC_FilterValue, 0, 109, 0, // Skip to: 634 >+/* 525 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 528 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 581 >+/* 532 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 535 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 548 >+/* 539 */ MCD_OPC_CheckPredicate, 19, 190, 1, // Skip to: 989 >+/* 543 */ MCD_OPC_Decode, 132, 21, 215, 1, // Opcode: tADDspi >+/* 548 */ MCD_OPC_FilterValue, 1, 181, 1, // Skip to: 989 >+/* 552 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 555 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 568 >+/* 559 */ MCD_OPC_CheckPredicate, 21, 170, 1, // Skip to: 989 >+/* 563 */ MCD_OPC_Decode, 219, 21, 204, 1, // Opcode: tSXTH >+/* 568 */ MCD_OPC_FilterValue, 1, 161, 1, // Skip to: 989 >+/* 572 */ MCD_OPC_CheckPredicate, 21, 157, 1, // Skip to: 989 >+/* 576 */ MCD_OPC_Decode, 218, 21, 204, 1, // Opcode: tSXTB >+/* 581 */ MCD_OPC_FilterValue, 1, 148, 1, // Skip to: 989 >+/* 585 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 588 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 601 >+/* 592 */ MCD_OPC_CheckPredicate, 19, 137, 1, // Skip to: 989 >+/* 596 */ MCD_OPC_Decode, 216, 21, 215, 1, // Opcode: tSUBspi >+/* 601 */ MCD_OPC_FilterValue, 1, 128, 1, // Skip to: 989 >+/* 605 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 608 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 621 >+/* 612 */ MCD_OPC_CheckPredicate, 21, 117, 1, // Skip to: 989 >+/* 616 */ MCD_OPC_Decode, 228, 21, 204, 1, // Opcode: tUXTH >+/* 621 */ MCD_OPC_FilterValue, 1, 108, 1, // Skip to: 989 >+/* 625 */ MCD_OPC_CheckPredicate, 21, 104, 1, // Skip to: 989 >+/* 629 */ MCD_OPC_Decode, 227, 21, 204, 1, // Opcode: tUXTB >+/* 634 */ MCD_OPC_FilterValue, 1, 95, 1, // Skip to: 989 >+/* 638 */ MCD_OPC_CheckPredicate, 22, 91, 1, // Skip to: 989 >+/* 642 */ MCD_OPC_Decode, 155, 21, 216, 1, // Opcode: tCBZ >+/* 647 */ MCD_OPC_FilterValue, 1, 67, 0, // Skip to: 718 >+/* 651 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 667 >+/* 658 */ MCD_OPC_CheckPredicate, 19, 71, 1, // Skip to: 989 >+/* 662 */ MCD_OPC_Decode, 197, 21, 217, 1, // Opcode: tPUSH >+/* 667 */ MCD_OPC_FilterValue, 1, 62, 1, // Skip to: 989 >+/* 671 */ MCD_OPC_ExtractField, 5, 4, // Inst{8-5} ... >+/* 674 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 699 >+/* 678 */ MCD_OPC_CheckPredicate, 23, 51, 1, // Skip to: 989 >+/* 682 */ MCD_OPC_CheckField, 4, 1, 1, 45, 1, // Skip to: 989 >+/* 688 */ MCD_OPC_CheckField, 0, 3, 0, 39, 1, // Skip to: 989 >+/* 694 */ MCD_OPC_Decode, 204, 21, 218, 1, // Opcode: tSETEND >+/* 699 */ MCD_OPC_FilterValue, 3, 30, 1, // Skip to: 989 >+/* 703 */ MCD_OPC_CheckPredicate, 19, 26, 1, // Skip to: 989 >+/* 707 */ MCD_OPC_CheckField, 3, 1, 0, 20, 1, // Skip to: 989 >+/* 713 */ MCD_OPC_Decode, 160, 21, 219, 1, // Opcode: tCPS >+/* 718 */ MCD_OPC_FilterValue, 2, 99, 0, // Skip to: 821 >+/* 722 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 725 */ MCD_OPC_FilterValue, 0, 79, 0, // Skip to: 808 >+/* 729 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 732 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 751 >+/* 736 */ MCD_OPC_CheckPredicate, 21, 249, 0, // Skip to: 989 >+/* 740 */ MCD_OPC_CheckField, 9, 1, 1, 243, 0, // Skip to: 989 >+/* 746 */ MCD_OPC_Decode, 198, 21, 204, 1, // Opcode: tREV >+/* 751 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 770 >+/* 755 */ MCD_OPC_CheckPredicate, 21, 230, 0, // Skip to: 989 >+/* 759 */ MCD_OPC_CheckField, 9, 1, 1, 224, 0, // Skip to: 989 >+/* 765 */ MCD_OPC_Decode, 199, 21, 204, 1, // Opcode: tREV16 >+/* 770 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 789 >+/* 774 */ MCD_OPC_CheckPredicate, 24, 211, 0, // Skip to: 989 >+/* 778 */ MCD_OPC_CheckField, 9, 1, 1, 205, 0, // Skip to: 989 >+/* 784 */ MCD_OPC_Decode, 163, 21, 220, 1, // Opcode: tHLT >+/* 789 */ MCD_OPC_FilterValue, 3, 196, 0, // Skip to: 989 >+/* 793 */ MCD_OPC_CheckPredicate, 21, 192, 0, // Skip to: 989 >+/* 797 */ MCD_OPC_CheckField, 9, 1, 1, 186, 0, // Skip to: 989 >+/* 803 */ MCD_OPC_Decode, 200, 21, 204, 1, // Opcode: tREVSH >+/* 808 */ MCD_OPC_FilterValue, 1, 177, 0, // Skip to: 989 >+/* 812 */ MCD_OPC_CheckPredicate, 22, 173, 0, // Skip to: 989 >+/* 816 */ MCD_OPC_Decode, 154, 21, 216, 1, // Opcode: tCBNZ >+/* 821 */ MCD_OPC_FilterValue, 3, 164, 0, // Skip to: 989 >+/* 825 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 828 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 841 >+/* 832 */ MCD_OPC_CheckPredicate, 19, 153, 0, // Skip to: 989 >+/* 836 */ MCD_OPC_Decode, 195, 21, 221, 1, // Opcode: tPOP >+/* 841 */ MCD_OPC_FilterValue, 1, 144, 0, // Skip to: 989 >+/* 845 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 848 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 861 >+/* 852 */ MCD_OPC_CheckPredicate, 19, 133, 0, // Skip to: 989 >+/* 856 */ MCD_OPC_Decode, 142, 21, 222, 1, // Opcode: tBKPT >+/* 861 */ MCD_OPC_FilterValue, 1, 124, 0, // Skip to: 989 >+/* 865 */ MCD_OPC_CheckPredicate, 25, 120, 0, // Skip to: 989 >+/* 869 */ MCD_OPC_CheckField, 0, 4, 0, 114, 0, // Skip to: 989 >+/* 875 */ MCD_OPC_Decode, 162, 21, 223, 1, // Opcode: tHINT >+/* 880 */ MCD_OPC_FilterValue, 12, 29, 0, // Skip to: 913 >+/* 884 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 887 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 900 >+/* 891 */ MCD_OPC_CheckPredicate, 19, 94, 0, // Skip to: 989 >+/* 895 */ MCD_OPC_Decode, 205, 21, 224, 1, // Opcode: tSTMIA_UPD >+/* 900 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 989 >+/* 904 */ MCD_OPC_CheckPredicate, 19, 81, 0, // Skip to: 989 >+/* 908 */ MCD_OPC_Decode, 166, 21, 225, 1, // Opcode: tLDMIA >+/* 913 */ MCD_OPC_FilterValue, 13, 53, 0, // Skip to: 970 >+/* 917 */ MCD_OPC_CheckPredicate, 19, 11, 0, // Skip to: 932 >+/* 921 */ MCD_OPC_CheckField, 0, 12, 254, 29, 4, 0, // Skip to: 932 >+/* 928 */ MCD_OPC_Decode, 224, 21, 58, // Opcode: tTRAP >+/* 932 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 935 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 948 >+/* 939 */ MCD_OPC_CheckPredicate, 19, 18, 0, // Skip to: 961 >+/* 943 */ MCD_OPC_Decode, 226, 21, 222, 1, // Opcode: tUDF >+/* 948 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 961 >+/* 952 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 961 >+/* 956 */ MCD_OPC_Decode, 217, 21, 222, 1, // Opcode: tSVC >+/* 961 */ MCD_OPC_CheckPredicate, 19, 24, 0, // Skip to: 989 >+/* 965 */ MCD_OPC_Decode, 152, 21, 226, 1, // Opcode: tBcc >+/* 970 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 989 >+/* 974 */ MCD_OPC_CheckPredicate, 19, 11, 0, // Skip to: 989 >+/* 978 */ MCD_OPC_CheckField, 11, 1, 0, 5, 0, // Skip to: 989 >+/* 984 */ MCD_OPC_Decode, 140, 21, 227, 1, // Opcode: tB >+/* 989 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableThumb32[] = { >+/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 34 >+/* 7 */ MCD_OPC_CheckPredicate, 26, 48, 0, // Skip to: 59 >+/* 11 */ MCD_OPC_CheckField, 27, 5, 30, 42, 0, // Skip to: 59 >+/* 17 */ MCD_OPC_CheckField, 14, 2, 3, 36, 0, // Skip to: 59 >+/* 23 */ MCD_OPC_CheckField, 0, 1, 0, 30, 0, // Skip to: 59 >+/* 29 */ MCD_OPC_Decode, 144, 21, 228, 1, // Opcode: tBLXi >+/* 34 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 59 >+/* 38 */ MCD_OPC_CheckPredicate, 19, 17, 0, // Skip to: 59 >+/* 42 */ MCD_OPC_CheckField, 27, 5, 30, 11, 0, // Skip to: 59 >+/* 48 */ MCD_OPC_CheckField, 14, 2, 3, 5, 0, // Skip to: 59 >+/* 54 */ MCD_OPC_Decode, 143, 21, 229, 1, // Opcode: tBL >+/* 59 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableThumb216[] = { >+/* 0 */ MCD_OPC_CheckPredicate, 22, 12, 0, // Skip to: 16 >+/* 4 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, // Skip to: 16 >+/* 11 */ MCD_OPC_Decode, 163, 18, 230, 1, // Opcode: t2IT >+/* 16 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableThumb232[] = { >+/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ... >+/* 3 */ MCD_OPC_FilterValue, 29, 25, 8, // Skip to: 2080 >+/* 7 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 1, 3, // Skip to: 783 >+/* 14 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 59, 0, // Skip to: 80 >+/* 21 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 49 >+/* 28 */ MCD_OPC_CheckPredicate, 22, 71, 27, // Skip to: 7015 >+/* 32 */ MCD_OPC_CheckField, 23, 1, 1, 65, 27, // Skip to: 7015 >+/* 38 */ MCD_OPC_CheckField, 13, 1, 0, 59, 27, // Skip to: 7015 >+/* 44 */ MCD_OPC_Decode, 165, 20, 231, 1, // Opcode: t2STMIA >+/* 49 */ MCD_OPC_FilterValue, 1, 50, 27, // Skip to: 7015 >+/* 53 */ MCD_OPC_CheckPredicate, 22, 46, 27, // Skip to: 7015 >+/* 57 */ MCD_OPC_CheckField, 23, 1, 0, 40, 27, // Skip to: 7015 >+/* 63 */ MCD_OPC_CheckField, 16, 4, 13, 34, 27, // Skip to: 7015 >+/* 69 */ MCD_OPC_CheckField, 5, 10, 128, 4, 27, 27, // Skip to: 7015 >+/* 76 */ MCD_OPC_Decode, 131, 20, 81, // Opcode: t2SRSDB >+/* 80 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 120 >+/* 84 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 87 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 107 >+/* 91 */ MCD_OPC_CheckPredicate, 22, 8, 27, // Skip to: 7015 >+/* 95 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 0, 27, // Skip to: 7015 >+/* 103 */ MCD_OPC_Decode, 195, 19, 79, // Opcode: t2RFEDB >+/* 107 */ MCD_OPC_FilterValue, 1, 248, 26, // Skip to: 7015 >+/* 111 */ MCD_OPC_CheckPredicate, 22, 244, 26, // Skip to: 7015 >+/* 115 */ MCD_OPC_Decode, 191, 18, 232, 1, // Opcode: t2LDMIA >+/* 120 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 183 >+/* 124 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 127 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 152 >+/* 131 */ MCD_OPC_CheckPredicate, 22, 224, 26, // Skip to: 7015 >+/* 135 */ MCD_OPC_CheckField, 23, 1, 1, 218, 26, // Skip to: 7015 >+/* 141 */ MCD_OPC_CheckField, 13, 1, 0, 212, 26, // Skip to: 7015 >+/* 147 */ MCD_OPC_Decode, 166, 20, 233, 1, // Opcode: t2STMIA_UPD >+/* 152 */ MCD_OPC_FilterValue, 1, 203, 26, // Skip to: 7015 >+/* 156 */ MCD_OPC_CheckPredicate, 22, 199, 26, // Skip to: 7015 >+/* 160 */ MCD_OPC_CheckField, 23, 1, 0, 193, 26, // Skip to: 7015 >+/* 166 */ MCD_OPC_CheckField, 16, 4, 13, 187, 26, // Skip to: 7015 >+/* 172 */ MCD_OPC_CheckField, 5, 10, 128, 4, 180, 26, // Skip to: 7015 >+/* 179 */ MCD_OPC_Decode, 132, 20, 81, // Opcode: t2SRSDB_UPD >+/* 183 */ MCD_OPC_FilterValue, 3, 36, 0, // Skip to: 223 >+/* 187 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 190 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 210 >+/* 194 */ MCD_OPC_CheckPredicate, 22, 161, 26, // Skip to: 7015 >+/* 198 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 153, 26, // Skip to: 7015 >+/* 206 */ MCD_OPC_Decode, 196, 19, 79, // Opcode: t2RFEDBW >+/* 210 */ MCD_OPC_FilterValue, 1, 145, 26, // Skip to: 7015 >+/* 214 */ MCD_OPC_CheckPredicate, 22, 141, 26, // Skip to: 7015 >+/* 218 */ MCD_OPC_Decode, 193, 18, 234, 1, // Opcode: t2LDMIA_UPD >+/* 223 */ MCD_OPC_FilterValue, 4, 219, 0, // Skip to: 446 >+/* 227 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 230 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 243 >+/* 234 */ MCD_OPC_CheckPredicate, 22, 121, 26, // Skip to: 7015 >+/* 238 */ MCD_OPC_Decode, 177, 20, 235, 1, // Opcode: t2STREX >+/* 243 */ MCD_OPC_FilterValue, 1, 112, 26, // Skip to: 7015 >+/* 247 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 250 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 269 >+/* 254 */ MCD_OPC_CheckPredicate, 22, 101, 26, // Skip to: 7015 >+/* 258 */ MCD_OPC_CheckField, 8, 4, 15, 95, 26, // Skip to: 7015 >+/* 264 */ MCD_OPC_Decode, 178, 20, 236, 1, // Opcode: t2STREXB >+/* 269 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 288 >+/* 273 */ MCD_OPC_CheckPredicate, 22, 82, 26, // Skip to: 7015 >+/* 277 */ MCD_OPC_CheckField, 8, 4, 15, 76, 26, // Skip to: 7015 >+/* 283 */ MCD_OPC_Decode, 180, 20, 236, 1, // Opcode: t2STREXH >+/* 288 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 301 >+/* 292 */ MCD_OPC_CheckPredicate, 22, 63, 26, // Skip to: 7015 >+/* 296 */ MCD_OPC_Decode, 179, 20, 237, 1, // Opcode: t2STREXD >+/* 301 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 326 >+/* 305 */ MCD_OPC_CheckPredicate, 24, 50, 26, // Skip to: 7015 >+/* 309 */ MCD_OPC_CheckField, 8, 4, 15, 44, 26, // Skip to: 7015 >+/* 315 */ MCD_OPC_CheckField, 0, 4, 15, 38, 26, // Skip to: 7015 >+/* 321 */ MCD_OPC_Decode, 157, 20, 238, 1, // Opcode: t2STLB >+/* 326 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 351 >+/* 330 */ MCD_OPC_CheckPredicate, 24, 25, 26, // Skip to: 7015 >+/* 334 */ MCD_OPC_CheckField, 8, 4, 15, 19, 26, // Skip to: 7015 >+/* 340 */ MCD_OPC_CheckField, 0, 4, 15, 13, 26, // Skip to: 7015 >+/* 346 */ MCD_OPC_Decode, 162, 20, 238, 1, // Opcode: t2STLH >+/* 351 */ MCD_OPC_FilterValue, 10, 21, 0, // Skip to: 376 >+/* 355 */ MCD_OPC_CheckPredicate, 24, 0, 26, // Skip to: 7015 >+/* 359 */ MCD_OPC_CheckField, 8, 4, 15, 250, 25, // Skip to: 7015 >+/* 365 */ MCD_OPC_CheckField, 0, 4, 15, 244, 25, // Skip to: 7015 >+/* 371 */ MCD_OPC_Decode, 156, 20, 238, 1, // Opcode: t2STL >+/* 376 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 395 >+/* 380 */ MCD_OPC_CheckPredicate, 24, 231, 25, // Skip to: 7015 >+/* 384 */ MCD_OPC_CheckField, 8, 4, 15, 225, 25, // Skip to: 7015 >+/* 390 */ MCD_OPC_Decode, 159, 20, 236, 1, // Opcode: t2STLEXB >+/* 395 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 414 >+/* 399 */ MCD_OPC_CheckPredicate, 24, 212, 25, // Skip to: 7015 >+/* 403 */ MCD_OPC_CheckField, 8, 4, 15, 206, 25, // Skip to: 7015 >+/* 409 */ MCD_OPC_Decode, 161, 20, 236, 1, // Opcode: t2STLEXH >+/* 414 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 433 >+/* 418 */ MCD_OPC_CheckPredicate, 24, 193, 25, // Skip to: 7015 >+/* 422 */ MCD_OPC_CheckField, 8, 4, 15, 187, 25, // Skip to: 7015 >+/* 428 */ MCD_OPC_Decode, 158, 20, 236, 1, // Opcode: t2STLEX >+/* 433 */ MCD_OPC_FilterValue, 15, 178, 25, // Skip to: 7015 >+/* 437 */ MCD_OPC_CheckPredicate, 24, 174, 25, // Skip to: 7015 >+/* 441 */ MCD_OPC_Decode, 160, 20, 237, 1, // Opcode: t2STLEXD >+/* 446 */ MCD_OPC_FilterValue, 5, 51, 1, // Skip to: 757 >+/* 450 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 453 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 472 >+/* 457 */ MCD_OPC_CheckPredicate, 22, 154, 25, // Skip to: 7015 >+/* 461 */ MCD_OPC_CheckField, 8, 4, 15, 148, 25, // Skip to: 7015 >+/* 467 */ MCD_OPC_Decode, 205, 18, 239, 1, // Opcode: t2LDREX >+/* 472 */ MCD_OPC_FilterValue, 1, 139, 25, // Skip to: 7015 >+/* 476 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 479 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 499 >+/* 483 */ MCD_OPC_CheckPredicate, 22, 128, 25, // Skip to: 7015 >+/* 487 */ MCD_OPC_CheckField, 8, 8, 240, 1, 121, 25, // Skip to: 7015 >+/* 494 */ MCD_OPC_Decode, 209, 20, 240, 1, // Opcode: t2TBB >+/* 499 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 519 >+/* 503 */ MCD_OPC_CheckPredicate, 22, 108, 25, // Skip to: 7015 >+/* 507 */ MCD_OPC_CheckField, 8, 8, 240, 1, 101, 25, // Skip to: 7015 >+/* 514 */ MCD_OPC_Decode, 211, 20, 240, 1, // Opcode: t2TBH >+/* 519 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 544 >+/* 523 */ MCD_OPC_CheckPredicate, 22, 88, 25, // Skip to: 7015 >+/* 527 */ MCD_OPC_CheckField, 8, 4, 15, 82, 25, // Skip to: 7015 >+/* 533 */ MCD_OPC_CheckField, 0, 4, 15, 76, 25, // Skip to: 7015 >+/* 539 */ MCD_OPC_Decode, 206, 18, 238, 1, // Opcode: t2LDREXB >+/* 544 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 569 >+/* 548 */ MCD_OPC_CheckPredicate, 22, 63, 25, // Skip to: 7015 >+/* 552 */ MCD_OPC_CheckField, 8, 4, 15, 57, 25, // Skip to: 7015 >+/* 558 */ MCD_OPC_CheckField, 0, 4, 15, 51, 25, // Skip to: 7015 >+/* 564 */ MCD_OPC_Decode, 208, 18, 238, 1, // Opcode: t2LDREXH >+/* 569 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 588 >+/* 573 */ MCD_OPC_CheckPredicate, 22, 38, 25, // Skip to: 7015 >+/* 577 */ MCD_OPC_CheckField, 0, 4, 15, 32, 25, // Skip to: 7015 >+/* 583 */ MCD_OPC_Decode, 207, 18, 241, 1, // Opcode: t2LDREXD >+/* 588 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 613 >+/* 592 */ MCD_OPC_CheckPredicate, 24, 19, 25, // Skip to: 7015 >+/* 596 */ MCD_OPC_CheckField, 8, 4, 15, 13, 25, // Skip to: 7015 >+/* 602 */ MCD_OPC_CheckField, 0, 4, 15, 7, 25, // Skip to: 7015 >+/* 608 */ MCD_OPC_Decode, 167, 18, 238, 1, // Opcode: t2LDAB >+/* 613 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 638 >+/* 617 */ MCD_OPC_CheckPredicate, 24, 250, 24, // Skip to: 7015 >+/* 621 */ MCD_OPC_CheckField, 8, 4, 15, 244, 24, // Skip to: 7015 >+/* 627 */ MCD_OPC_CheckField, 0, 4, 15, 238, 24, // Skip to: 7015 >+/* 633 */ MCD_OPC_Decode, 172, 18, 238, 1, // Opcode: t2LDAH >+/* 638 */ MCD_OPC_FilterValue, 10, 21, 0, // Skip to: 663 >+/* 642 */ MCD_OPC_CheckPredicate, 24, 225, 24, // Skip to: 7015 >+/* 646 */ MCD_OPC_CheckField, 8, 4, 15, 219, 24, // Skip to: 7015 >+/* 652 */ MCD_OPC_CheckField, 0, 4, 15, 213, 24, // Skip to: 7015 >+/* 658 */ MCD_OPC_Decode, 166, 18, 238, 1, // Opcode: t2LDA >+/* 663 */ MCD_OPC_FilterValue, 12, 21, 0, // Skip to: 688 >+/* 667 */ MCD_OPC_CheckPredicate, 24, 200, 24, // Skip to: 7015 >+/* 671 */ MCD_OPC_CheckField, 8, 4, 15, 194, 24, // Skip to: 7015 >+/* 677 */ MCD_OPC_CheckField, 0, 4, 15, 188, 24, // Skip to: 7015 >+/* 683 */ MCD_OPC_Decode, 169, 18, 238, 1, // Opcode: t2LDAEXB >+/* 688 */ MCD_OPC_FilterValue, 13, 21, 0, // Skip to: 713 >+/* 692 */ MCD_OPC_CheckPredicate, 24, 175, 24, // Skip to: 7015 >+/* 696 */ MCD_OPC_CheckField, 8, 4, 15, 169, 24, // Skip to: 7015 >+/* 702 */ MCD_OPC_CheckField, 0, 4, 15, 163, 24, // Skip to: 7015 >+/* 708 */ MCD_OPC_Decode, 171, 18, 238, 1, // Opcode: t2LDAEXH >+/* 713 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 738 >+/* 717 */ MCD_OPC_CheckPredicate, 24, 150, 24, // Skip to: 7015 >+/* 721 */ MCD_OPC_CheckField, 8, 4, 15, 144, 24, // Skip to: 7015 >+/* 727 */ MCD_OPC_CheckField, 0, 4, 15, 138, 24, // Skip to: 7015 >+/* 733 */ MCD_OPC_Decode, 168, 18, 238, 1, // Opcode: t2LDAEX >+/* 738 */ MCD_OPC_FilterValue, 15, 129, 24, // Skip to: 7015 >+/* 742 */ MCD_OPC_CheckPredicate, 24, 125, 24, // Skip to: 7015 >+/* 746 */ MCD_OPC_CheckField, 0, 4, 15, 119, 24, // Skip to: 7015 >+/* 752 */ MCD_OPC_Decode, 170, 18, 241, 1, // Opcode: t2LDAEXD >+/* 757 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 770 >+/* 761 */ MCD_OPC_CheckPredicate, 22, 106, 24, // Skip to: 7015 >+/* 765 */ MCD_OPC_Decode, 174, 20, 242, 1, // Opcode: t2STRD_POST >+/* 770 */ MCD_OPC_FilterValue, 7, 97, 24, // Skip to: 7015 >+/* 774 */ MCD_OPC_CheckPredicate, 22, 93, 24, // Skip to: 7015 >+/* 778 */ MCD_OPC_Decode, 202, 18, 243, 1, // Opcode: t2LDRD_POST >+/* 783 */ MCD_OPC_FilterValue, 1, 5, 1, // Skip to: 1048 >+/* 787 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 790 */ MCD_OPC_FilterValue, 0, 59, 0, // Skip to: 853 >+/* 794 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 797 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 822 >+/* 801 */ MCD_OPC_CheckPredicate, 22, 66, 24, // Skip to: 7015 >+/* 805 */ MCD_OPC_CheckField, 23, 1, 0, 60, 24, // Skip to: 7015 >+/* 811 */ MCD_OPC_CheckField, 13, 1, 0, 54, 24, // Skip to: 7015 >+/* 817 */ MCD_OPC_Decode, 163, 20, 231, 1, // Opcode: t2STMDB >+/* 822 */ MCD_OPC_FilterValue, 1, 45, 24, // Skip to: 7015 >+/* 826 */ MCD_OPC_CheckPredicate, 22, 41, 24, // Skip to: 7015 >+/* 830 */ MCD_OPC_CheckField, 23, 1, 1, 35, 24, // Skip to: 7015 >+/* 836 */ MCD_OPC_CheckField, 16, 4, 13, 29, 24, // Skip to: 7015 >+/* 842 */ MCD_OPC_CheckField, 5, 10, 128, 4, 22, 24, // Skip to: 7015 >+/* 849 */ MCD_OPC_Decode, 133, 20, 81, // Opcode: t2SRSIA >+/* 853 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 893 >+/* 857 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 860 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 873 >+/* 864 */ MCD_OPC_CheckPredicate, 22, 3, 24, // Skip to: 7015 >+/* 868 */ MCD_OPC_Decode, 189, 18, 232, 1, // Opcode: t2LDMDB >+/* 873 */ MCD_OPC_FilterValue, 1, 250, 23, // Skip to: 7015 >+/* 877 */ MCD_OPC_CheckPredicate, 22, 246, 23, // Skip to: 7015 >+/* 881 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 238, 23, // Skip to: 7015 >+/* 889 */ MCD_OPC_Decode, 197, 19, 79, // Opcode: t2RFEIA >+/* 893 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 956 >+/* 897 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 900 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 925 >+/* 904 */ MCD_OPC_CheckPredicate, 22, 219, 23, // Skip to: 7015 >+/* 908 */ MCD_OPC_CheckField, 23, 1, 0, 213, 23, // Skip to: 7015 >+/* 914 */ MCD_OPC_CheckField, 13, 1, 0, 207, 23, // Skip to: 7015 >+/* 920 */ MCD_OPC_Decode, 164, 20, 233, 1, // Opcode: t2STMDB_UPD >+/* 925 */ MCD_OPC_FilterValue, 1, 198, 23, // Skip to: 7015 >+/* 929 */ MCD_OPC_CheckPredicate, 22, 194, 23, // Skip to: 7015 >+/* 933 */ MCD_OPC_CheckField, 23, 1, 1, 188, 23, // Skip to: 7015 >+/* 939 */ MCD_OPC_CheckField, 16, 4, 13, 182, 23, // Skip to: 7015 >+/* 945 */ MCD_OPC_CheckField, 5, 10, 128, 4, 175, 23, // Skip to: 7015 >+/* 952 */ MCD_OPC_Decode, 134, 20, 81, // Opcode: t2SRSIA_UPD >+/* 956 */ MCD_OPC_FilterValue, 3, 36, 0, // Skip to: 996 >+/* 960 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 963 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 976 >+/* 967 */ MCD_OPC_CheckPredicate, 22, 156, 23, // Skip to: 7015 >+/* 971 */ MCD_OPC_Decode, 190, 18, 234, 1, // Opcode: t2LDMDB_UPD >+/* 976 */ MCD_OPC_FilterValue, 1, 147, 23, // Skip to: 7015 >+/* 980 */ MCD_OPC_CheckPredicate, 22, 143, 23, // Skip to: 7015 >+/* 984 */ MCD_OPC_CheckField, 0, 16, 128, 128, 3, 135, 23, // Skip to: 7015 >+/* 992 */ MCD_OPC_Decode, 198, 19, 79, // Opcode: t2RFEIAW >+/* 996 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1009 >+/* 1000 */ MCD_OPC_CheckPredicate, 22, 123, 23, // Skip to: 7015 >+/* 1004 */ MCD_OPC_Decode, 176, 20, 244, 1, // Opcode: t2STRDi8 >+/* 1009 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1022 >+/* 1013 */ MCD_OPC_CheckPredicate, 22, 110, 23, // Skip to: 7015 >+/* 1017 */ MCD_OPC_Decode, 204, 18, 244, 1, // Opcode: t2LDRDi8 >+/* 1022 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1035 >+/* 1026 */ MCD_OPC_CheckPredicate, 22, 97, 23, // Skip to: 7015 >+/* 1030 */ MCD_OPC_Decode, 175, 20, 245, 1, // Opcode: t2STRD_PRE >+/* 1035 */ MCD_OPC_FilterValue, 7, 88, 23, // Skip to: 7015 >+/* 1039 */ MCD_OPC_CheckPredicate, 22, 84, 23, // Skip to: 7015 >+/* 1043 */ MCD_OPC_Decode, 203, 18, 246, 1, // Opcode: t2LDRD_PRE >+/* 1048 */ MCD_OPC_FilterValue, 2, 201, 1, // Skip to: 1509 >+/* 1052 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 1055 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 1132 >+/* 1059 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 1081 >+/* 1063 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1081 >+/* 1069 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1081 >+/* 1076 */ MCD_OPC_Decode, 217, 20, 247, 1, // Opcode: t2TSTrr >+/* 1081 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1102 >+/* 1085 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1102 >+/* 1091 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1102 >+/* 1097 */ MCD_OPC_Decode, 218, 20, 248, 1, // Opcode: t2TSTrs >+/* 1102 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1123 >+/* 1106 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1123 >+/* 1112 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1123 >+/* 1118 */ MCD_OPC_Decode, 248, 17, 249, 1, // Opcode: t2ANDrr >+/* 1123 */ MCD_OPC_CheckPredicate, 22, 0, 23, // Skip to: 7015 >+/* 1127 */ MCD_OPC_Decode, 249, 17, 250, 1, // Opcode: t2ANDrs >+/* 1132 */ MCD_OPC_FilterValue, 1, 30, 0, // Skip to: 1166 >+/* 1136 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1157 >+/* 1140 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1157 >+/* 1146 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1157 >+/* 1152 */ MCD_OPC_Decode, 128, 18, 249, 1, // Opcode: t2BICrr >+/* 1157 */ MCD_OPC_CheckPredicate, 22, 222, 22, // Skip to: 7015 >+/* 1161 */ MCD_OPC_Decode, 129, 18, 250, 1, // Opcode: t2BICrs >+/* 1166 */ MCD_OPC_FilterValue, 2, 151, 0, // Skip to: 1321 >+/* 1170 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1173 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 1208 >+/* 1177 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... >+/* 1180 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 1233 >+/* 1184 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 1199 >+/* 1188 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1199 >+/* 1194 */ MCD_OPC_Decode, 143, 19, 251, 1, // Opcode: t2MOVr >+/* 1199 */ MCD_OPC_CheckPredicate, 22, 30, 0, // Skip to: 1233 >+/* 1203 */ MCD_OPC_Decode, 166, 19, 249, 1, // Opcode: t2ORRrr >+/* 1208 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 1233 >+/* 1212 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1233 >+/* 1216 */ MCD_OPC_CheckField, 16, 4, 15, 11, 0, // Skip to: 1233 >+/* 1222 */ MCD_OPC_CheckField, 12, 3, 0, 5, 0, // Skip to: 1233 >+/* 1228 */ MCD_OPC_Decode, 201, 19, 252, 1, // Opcode: t2RRX >+/* 1233 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1236 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1255 >+/* 1240 */ MCD_OPC_CheckPredicate, 22, 68, 0, // Skip to: 1312 >+/* 1244 */ MCD_OPC_CheckField, 16, 4, 15, 62, 0, // Skip to: 1312 >+/* 1250 */ MCD_OPC_Decode, 244, 18, 253, 1, // Opcode: t2LSLri >+/* 1255 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1274 >+/* 1259 */ MCD_OPC_CheckPredicate, 22, 49, 0, // Skip to: 1312 >+/* 1263 */ MCD_OPC_CheckField, 16, 4, 15, 43, 0, // Skip to: 1312 >+/* 1269 */ MCD_OPC_Decode, 246, 18, 253, 1, // Opcode: t2LSRri >+/* 1274 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1293 >+/* 1278 */ MCD_OPC_CheckPredicate, 22, 30, 0, // Skip to: 1312 >+/* 1282 */ MCD_OPC_CheckField, 16, 4, 15, 24, 0, // Skip to: 1312 >+/* 1288 */ MCD_OPC_Decode, 250, 17, 253, 1, // Opcode: t2ASRri >+/* 1293 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1312 >+/* 1297 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 1312 >+/* 1301 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1312 >+/* 1307 */ MCD_OPC_Decode, 199, 19, 253, 1, // Opcode: t2RORri >+/* 1312 */ MCD_OPC_CheckPredicate, 22, 67, 22, // Skip to: 7015 >+/* 1316 */ MCD_OPC_Decode, 167, 19, 250, 1, // Opcode: t2ORRrs >+/* 1321 */ MCD_OPC_FilterValue, 3, 62, 0, // Skip to: 1387 >+/* 1325 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 1328 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 1363 >+/* 1332 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... >+/* 1335 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 1363 >+/* 1339 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 1354 >+/* 1343 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1354 >+/* 1349 */ MCD_OPC_Decode, 160, 19, 252, 1, // Opcode: t2MVNr >+/* 1354 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 1363 >+/* 1358 */ MCD_OPC_Decode, 163, 19, 249, 1, // Opcode: t2ORNrr >+/* 1363 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 1378 >+/* 1367 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 1378 >+/* 1373 */ MCD_OPC_Decode, 161, 19, 254, 1, // Opcode: t2MVNs >+/* 1378 */ MCD_OPC_CheckPredicate, 22, 1, 22, // Skip to: 7015 >+/* 1382 */ MCD_OPC_Decode, 164, 19, 250, 1, // Opcode: t2ORNrs >+/* 1387 */ MCD_OPC_FilterValue, 4, 73, 0, // Skip to: 1464 >+/* 1391 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 1413 >+/* 1395 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1413 >+/* 1401 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1413 >+/* 1408 */ MCD_OPC_Decode, 214, 20, 247, 1, // Opcode: t2TEQrr >+/* 1413 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1434 >+/* 1417 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1434 >+/* 1423 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1434 >+/* 1429 */ MCD_OPC_Decode, 215, 20, 248, 1, // Opcode: t2TEQrs >+/* 1434 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1455 >+/* 1438 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1455 >+/* 1444 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1455 >+/* 1450 */ MCD_OPC_Decode, 159, 18, 249, 1, // Opcode: t2EORrr >+/* 1455 */ MCD_OPC_CheckPredicate, 22, 180, 21, // Skip to: 7015 >+/* 1459 */ MCD_OPC_Decode, 160, 18, 250, 1, // Opcode: t2EORrs >+/* 1464 */ MCD_OPC_FilterValue, 6, 171, 21, // Skip to: 7015 >+/* 1468 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1471 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1490 >+/* 1475 */ MCD_OPC_CheckPredicate, 27, 160, 21, // Skip to: 7015 >+/* 1479 */ MCD_OPC_CheckField, 20, 1, 0, 154, 21, // Skip to: 7015 >+/* 1485 */ MCD_OPC_Decode, 168, 19, 255, 1, // Opcode: t2PKHBT >+/* 1490 */ MCD_OPC_FilterValue, 2, 145, 21, // Skip to: 7015 >+/* 1494 */ MCD_OPC_CheckPredicate, 27, 141, 21, // Skip to: 7015 >+/* 1498 */ MCD_OPC_CheckField, 20, 1, 0, 135, 21, // Skip to: 7015 >+/* 1504 */ MCD_OPC_Decode, 169, 19, 255, 1, // Opcode: t2PKHTB >+/* 1509 */ MCD_OPC_FilterValue, 3, 3, 1, // Skip to: 1772 >+/* 1513 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 1516 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 1593 >+/* 1520 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 1542 >+/* 1524 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1542 >+/* 1530 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1542 >+/* 1537 */ MCD_OPC_Decode, 138, 18, 247, 1, // Opcode: t2CMNzrr >+/* 1542 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1563 >+/* 1546 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1563 >+/* 1552 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1563 >+/* 1558 */ MCD_OPC_Decode, 139, 18, 248, 1, // Opcode: t2CMNzrs >+/* 1563 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1584 >+/* 1567 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1584 >+/* 1573 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1584 >+/* 1579 */ MCD_OPC_Decode, 244, 17, 128, 2, // Opcode: t2ADDrr >+/* 1584 */ MCD_OPC_CheckPredicate, 22, 51, 21, // Skip to: 7015 >+/* 1588 */ MCD_OPC_Decode, 245, 17, 129, 2, // Opcode: t2ADDrs >+/* 1593 */ MCD_OPC_FilterValue, 2, 30, 0, // Skip to: 1627 >+/* 1597 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1618 >+/* 1601 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1618 >+/* 1607 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1618 >+/* 1613 */ MCD_OPC_Decode, 237, 17, 249, 1, // Opcode: t2ADCrr >+/* 1618 */ MCD_OPC_CheckPredicate, 22, 17, 21, // Skip to: 7015 >+/* 1622 */ MCD_OPC_Decode, 238, 17, 250, 1, // Opcode: t2ADCrs >+/* 1627 */ MCD_OPC_FilterValue, 3, 30, 0, // Skip to: 1661 >+/* 1631 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1652 >+/* 1635 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1652 >+/* 1641 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1652 >+/* 1647 */ MCD_OPC_Decode, 211, 19, 249, 1, // Opcode: t2SBCrr >+/* 1652 */ MCD_OPC_CheckPredicate, 22, 239, 20, // Skip to: 7015 >+/* 1656 */ MCD_OPC_Decode, 212, 19, 250, 1, // Opcode: t2SBCrs >+/* 1661 */ MCD_OPC_FilterValue, 5, 73, 0, // Skip to: 1738 >+/* 1665 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 1687 >+/* 1669 */ MCD_OPC_CheckField, 20, 1, 1, 12, 0, // Skip to: 1687 >+/* 1675 */ MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, // Skip to: 1687 >+/* 1682 */ MCD_OPC_Decode, 141, 18, 247, 1, // Opcode: t2CMPrr >+/* 1687 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1708 >+/* 1691 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 1708 >+/* 1697 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 1708 >+/* 1703 */ MCD_OPC_Decode, 142, 18, 248, 1, // Opcode: t2CMPrs >+/* 1708 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1729 >+/* 1712 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1729 >+/* 1718 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1729 >+/* 1724 */ MCD_OPC_Decode, 201, 20, 128, 2, // Opcode: t2SUBrr >+/* 1729 */ MCD_OPC_CheckPredicate, 22, 162, 20, // Skip to: 7015 >+/* 1733 */ MCD_OPC_Decode, 202, 20, 129, 2, // Opcode: t2SUBrs >+/* 1738 */ MCD_OPC_FilterValue, 6, 153, 20, // Skip to: 7015 >+/* 1742 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 1763 >+/* 1746 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 1763 >+/* 1752 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 1763 >+/* 1758 */ MCD_OPC_Decode, 205, 19, 249, 1, // Opcode: t2RSBrr >+/* 1763 */ MCD_OPC_CheckPredicate, 22, 128, 20, // Skip to: 7015 >+/* 1767 */ MCD_OPC_Decode, 206, 19, 250, 1, // Opcode: t2RSBrs >+/* 1772 */ MCD_OPC_FilterValue, 4, 151, 0, // Skip to: 1927 >+/* 1776 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 1779 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1797 >+/* 1783 */ MCD_OPC_CheckPredicate, 22, 108, 20, // Skip to: 7015 >+/* 1787 */ MCD_OPC_CheckField, 23, 1, 1, 102, 20, // Skip to: 7015 >+/* 1793 */ MCD_OPC_Decode, 153, 20, 84, // Opcode: t2STC_OPTION >+/* 1797 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1815 >+/* 1801 */ MCD_OPC_CheckPredicate, 22, 90, 20, // Skip to: 7015 >+/* 1805 */ MCD_OPC_CheckField, 23, 1, 1, 84, 20, // Skip to: 7015 >+/* 1811 */ MCD_OPC_Decode, 186, 18, 84, // Opcode: t2LDC_OPTION >+/* 1815 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1827 >+/* 1819 */ MCD_OPC_CheckPredicate, 22, 72, 20, // Skip to: 7015 >+/* 1823 */ MCD_OPC_Decode, 154, 20, 84, // Opcode: t2STC_POST >+/* 1827 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1839 >+/* 1831 */ MCD_OPC_CheckPredicate, 22, 60, 20, // Skip to: 7015 >+/* 1835 */ MCD_OPC_Decode, 187, 18, 84, // Opcode: t2LDC_POST >+/* 1839 */ MCD_OPC_FilterValue, 4, 28, 0, // Skip to: 1871 >+/* 1843 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 1846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1859 >+/* 1850 */ MCD_OPC_CheckPredicate, 22, 41, 20, // Skip to: 7015 >+/* 1854 */ MCD_OPC_Decode, 250, 18, 130, 2, // Opcode: t2MCRR >+/* 1859 */ MCD_OPC_FilterValue, 1, 32, 20, // Skip to: 7015 >+/* 1863 */ MCD_OPC_CheckPredicate, 22, 28, 20, // Skip to: 7015 >+/* 1867 */ MCD_OPC_Decode, 149, 20, 84, // Opcode: t2STCL_OPTION >+/* 1871 */ MCD_OPC_FilterValue, 5, 28, 0, // Skip to: 1903 >+/* 1875 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 1878 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1891 >+/* 1882 */ MCD_OPC_CheckPredicate, 22, 9, 20, // Skip to: 7015 >+/* 1886 */ MCD_OPC_Decode, 150, 19, 130, 2, // Opcode: t2MRRC >+/* 1891 */ MCD_OPC_FilterValue, 1, 0, 20, // Skip to: 7015 >+/* 1895 */ MCD_OPC_CheckPredicate, 22, 252, 19, // Skip to: 7015 >+/* 1899 */ MCD_OPC_Decode, 182, 18, 84, // Opcode: t2LDCL_OPTION >+/* 1903 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1915 >+/* 1907 */ MCD_OPC_CheckPredicate, 22, 240, 19, // Skip to: 7015 >+/* 1911 */ MCD_OPC_Decode, 150, 20, 84, // Opcode: t2STCL_POST >+/* 1915 */ MCD_OPC_FilterValue, 7, 232, 19, // Skip to: 7015 >+/* 1919 */ MCD_OPC_CheckPredicate, 22, 228, 19, // Skip to: 7015 >+/* 1923 */ MCD_OPC_Decode, 183, 18, 84, // Opcode: t2LDCL_POST >+/* 1927 */ MCD_OPC_FilterValue, 5, 99, 0, // Skip to: 2030 >+/* 1931 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 1934 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1946 >+/* 1938 */ MCD_OPC_CheckPredicate, 22, 209, 19, // Skip to: 7015 >+/* 1942 */ MCD_OPC_Decode, 152, 20, 84, // Opcode: t2STC_OFFSET >+/* 1946 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1958 >+/* 1950 */ MCD_OPC_CheckPredicate, 22, 197, 19, // Skip to: 7015 >+/* 1954 */ MCD_OPC_Decode, 185, 18, 84, // Opcode: t2LDC_OFFSET >+/* 1958 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1970 >+/* 1962 */ MCD_OPC_CheckPredicate, 22, 185, 19, // Skip to: 7015 >+/* 1966 */ MCD_OPC_Decode, 155, 20, 84, // Opcode: t2STC_PRE >+/* 1970 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1982 >+/* 1974 */ MCD_OPC_CheckPredicate, 22, 173, 19, // Skip to: 7015 >+/* 1978 */ MCD_OPC_Decode, 188, 18, 84, // Opcode: t2LDC_PRE >+/* 1982 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1994 >+/* 1986 */ MCD_OPC_CheckPredicate, 22, 161, 19, // Skip to: 7015 >+/* 1990 */ MCD_OPC_Decode, 148, 20, 84, // Opcode: t2STCL_OFFSET >+/* 1994 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 2006 >+/* 1998 */ MCD_OPC_CheckPredicate, 22, 149, 19, // Skip to: 7015 >+/* 2002 */ MCD_OPC_Decode, 181, 18, 84, // Opcode: t2LDCL_OFFSET >+/* 2006 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 2018 >+/* 2010 */ MCD_OPC_CheckPredicate, 22, 137, 19, // Skip to: 7015 >+/* 2014 */ MCD_OPC_Decode, 151, 20, 84, // Opcode: t2STCL_PRE >+/* 2018 */ MCD_OPC_FilterValue, 7, 129, 19, // Skip to: 7015 >+/* 2022 */ MCD_OPC_CheckPredicate, 22, 125, 19, // Skip to: 7015 >+/* 2026 */ MCD_OPC_Decode, 184, 18, 84, // Opcode: t2LDCL_PRE >+/* 2030 */ MCD_OPC_FilterValue, 6, 117, 19, // Skip to: 7015 >+/* 2034 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 2037 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2049 >+/* 2041 */ MCD_OPC_CheckPredicate, 28, 106, 19, // Skip to: 7015 >+/* 2045 */ MCD_OPC_Decode, 133, 18, 87, // Opcode: t2CDP >+/* 2049 */ MCD_OPC_FilterValue, 1, 98, 19, // Skip to: 7015 >+/* 2053 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2056 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2068 >+/* 2060 */ MCD_OPC_CheckPredicate, 22, 87, 19, // Skip to: 7015 >+/* 2064 */ MCD_OPC_Decode, 248, 18, 89, // Opcode: t2MCR >+/* 2068 */ MCD_OPC_FilterValue, 1, 79, 19, // Skip to: 7015 >+/* 2072 */ MCD_OPC_CheckPredicate, 22, 75, 19, // Skip to: 7015 >+/* 2076 */ MCD_OPC_Decode, 148, 19, 91, // Opcode: t2MRC >+/* 2080 */ MCD_OPC_FilterValue, 30, 81, 4, // Skip to: 3189 >+/* 2084 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... >+/* 2087 */ MCD_OPC_FilterValue, 0, 69, 2, // Skip to: 2672 >+/* 2091 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 2094 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 2238 >+/* 2098 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 2101 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 2135 >+/* 2105 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 2126 >+/* 2109 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2126 >+/* 2115 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2126 >+/* 2121 */ MCD_OPC_Decode, 216, 20, 131, 2, // Opcode: t2TSTri >+/* 2126 */ MCD_OPC_CheckPredicate, 22, 21, 19, // Skip to: 7015 >+/* 2130 */ MCD_OPC_Decode, 247, 17, 132, 2, // Opcode: t2ANDri >+/* 2135 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2148 >+/* 2139 */ MCD_OPC_CheckPredicate, 22, 8, 19, // Skip to: 7015 >+/* 2143 */ MCD_OPC_Decode, 255, 17, 132, 2, // Opcode: t2BICri >+/* 2148 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 2176 >+/* 2152 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 2167 >+/* 2156 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2167 >+/* 2162 */ MCD_OPC_Decode, 139, 19, 133, 2, // Opcode: t2MOVi >+/* 2167 */ MCD_OPC_CheckPredicate, 22, 236, 18, // Skip to: 7015 >+/* 2171 */ MCD_OPC_Decode, 165, 19, 132, 2, // Opcode: t2ORRri >+/* 2176 */ MCD_OPC_FilterValue, 3, 24, 0, // Skip to: 2204 >+/* 2180 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 2195 >+/* 2184 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2195 >+/* 2190 */ MCD_OPC_Decode, 159, 19, 133, 2, // Opcode: t2MVNi >+/* 2195 */ MCD_OPC_CheckPredicate, 22, 208, 18, // Skip to: 7015 >+/* 2199 */ MCD_OPC_Decode, 162, 19, 132, 2, // Opcode: t2ORNri >+/* 2204 */ MCD_OPC_FilterValue, 4, 199, 18, // Skip to: 7015 >+/* 2208 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 2229 >+/* 2212 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2229 >+/* 2218 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2229 >+/* 2224 */ MCD_OPC_Decode, 213, 20, 131, 2, // Opcode: t2TEQri >+/* 2229 */ MCD_OPC_CheckPredicate, 22, 174, 18, // Skip to: 7015 >+/* 2233 */ MCD_OPC_Decode, 158, 18, 132, 2, // Opcode: t2EORri >+/* 2238 */ MCD_OPC_FilterValue, 1, 110, 0, // Skip to: 2352 >+/* 2242 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 2245 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 2279 >+/* 2249 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 2270 >+/* 2253 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2270 >+/* 2259 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2270 >+/* 2265 */ MCD_OPC_Decode, 137, 18, 131, 2, // Opcode: t2CMNri >+/* 2270 */ MCD_OPC_CheckPredicate, 22, 133, 18, // Skip to: 7015 >+/* 2274 */ MCD_OPC_Decode, 242, 17, 134, 2, // Opcode: t2ADDri >+/* 2279 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2292 >+/* 2283 */ MCD_OPC_CheckPredicate, 22, 120, 18, // Skip to: 7015 >+/* 2287 */ MCD_OPC_Decode, 236, 17, 132, 2, // Opcode: t2ADCri >+/* 2292 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2305 >+/* 2296 */ MCD_OPC_CheckPredicate, 22, 107, 18, // Skip to: 7015 >+/* 2300 */ MCD_OPC_Decode, 210, 19, 132, 2, // Opcode: t2SBCri >+/* 2305 */ MCD_OPC_FilterValue, 5, 30, 0, // Skip to: 2339 >+/* 2309 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 2330 >+/* 2313 */ MCD_OPC_CheckField, 20, 1, 1, 11, 0, // Skip to: 2330 >+/* 2319 */ MCD_OPC_CheckField, 8, 4, 15, 5, 0, // Skip to: 2330 >+/* 2325 */ MCD_OPC_Decode, 140, 18, 131, 2, // Opcode: t2CMPri >+/* 2330 */ MCD_OPC_CheckPredicate, 22, 73, 18, // Skip to: 7015 >+/* 2334 */ MCD_OPC_Decode, 199, 20, 134, 2, // Opcode: t2SUBri >+/* 2339 */ MCD_OPC_FilterValue, 6, 64, 18, // Skip to: 7015 >+/* 2343 */ MCD_OPC_CheckPredicate, 22, 60, 18, // Skip to: 7015 >+/* 2347 */ MCD_OPC_Decode, 204, 19, 132, 2, // Opcode: t2RSBri >+/* 2352 */ MCD_OPC_FilterValue, 2, 115, 0, // Skip to: 2471 >+/* 2356 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 2359 */ MCD_OPC_FilterValue, 0, 63, 0, // Skip to: 2426 >+/* 2363 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2366 */ MCD_OPC_FilterValue, 0, 37, 18, // Skip to: 7015 >+/* 2370 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 2373 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2392 >+/* 2377 */ MCD_OPC_CheckPredicate, 22, 30, 0, // Skip to: 2411 >+/* 2381 */ MCD_OPC_CheckField, 23, 1, 0, 24, 0, // Skip to: 2411 >+/* 2387 */ MCD_OPC_Decode, 243, 17, 135, 2, // Opcode: t2ADDri12 >+/* 2392 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2411 >+/* 2396 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 2411 >+/* 2400 */ MCD_OPC_CheckField, 23, 1, 1, 5, 0, // Skip to: 2411 >+/* 2406 */ MCD_OPC_Decode, 200, 20, 135, 2, // Opcode: t2SUBri12 >+/* 2411 */ MCD_OPC_CheckPredicate, 22, 248, 17, // Skip to: 7015 >+/* 2415 */ MCD_OPC_CheckField, 16, 4, 15, 242, 17, // Skip to: 7015 >+/* 2421 */ MCD_OPC_Decode, 246, 17, 136, 2, // Opcode: t2ADR >+/* 2426 */ MCD_OPC_FilterValue, 1, 233, 17, // Skip to: 7015 >+/* 2430 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 2433 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2452 >+/* 2437 */ MCD_OPC_CheckPredicate, 22, 222, 17, // Skip to: 7015 >+/* 2441 */ MCD_OPC_CheckField, 20, 2, 0, 216, 17, // Skip to: 7015 >+/* 2447 */ MCD_OPC_Decode, 140, 19, 137, 2, // Opcode: t2MOVi16 >+/* 2452 */ MCD_OPC_FilterValue, 1, 207, 17, // Skip to: 7015 >+/* 2456 */ MCD_OPC_CheckPredicate, 22, 203, 17, // Skip to: 7015 >+/* 2460 */ MCD_OPC_CheckField, 20, 2, 0, 197, 17, // Skip to: 7015 >+/* 2466 */ MCD_OPC_Decode, 136, 19, 137, 2, // Opcode: t2MOVTi16 >+/* 2471 */ MCD_OPC_FilterValue, 3, 188, 17, // Skip to: 7015 >+/* 2475 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... >+/* 2478 */ MCD_OPC_FilterValue, 0, 56, 0, // Skip to: 2538 >+/* 2482 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2485 */ MCD_OPC_FilterValue, 0, 174, 17, // Skip to: 7015 >+/* 2489 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2492 */ MCD_OPC_FilterValue, 0, 167, 17, // Skip to: 7015 >+/* 2496 */ MCD_OPC_CheckPredicate, 29, 29, 0, // Skip to: 2529 >+/* 2500 */ MCD_OPC_CheckField, 21, 1, 1, 23, 0, // Skip to: 2529 >+/* 2506 */ MCD_OPC_CheckField, 12, 3, 0, 17, 0, // Skip to: 2529 >+/* 2512 */ MCD_OPC_CheckField, 6, 2, 0, 11, 0, // Skip to: 2529 >+/* 2518 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 2529 >+/* 2524 */ MCD_OPC_Decode, 136, 20, 138, 2, // Opcode: t2SSAT16 >+/* 2529 */ MCD_OPC_CheckPredicate, 22, 130, 17, // Skip to: 7015 >+/* 2533 */ MCD_OPC_Decode, 135, 20, 139, 2, // Opcode: t2SSAT >+/* 2538 */ MCD_OPC_FilterValue, 1, 58, 0, // Skip to: 2600 >+/* 2542 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 2545 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 2558 >+/* 2549 */ MCD_OPC_CheckPredicate, 22, 110, 17, // Skip to: 7015 >+/* 2553 */ MCD_OPC_Decode, 213, 19, 140, 2, // Opcode: t2SBFX >+/* 2558 */ MCD_OPC_FilterValue, 2, 101, 17, // Skip to: 7015 >+/* 2562 */ MCD_OPC_ExtractField, 5, 1, // Inst{5} ... >+/* 2565 */ MCD_OPC_FilterValue, 0, 94, 17, // Skip to: 7015 >+/* 2569 */ MCD_OPC_ExtractField, 26, 1, // Inst{26} ... >+/* 2572 */ MCD_OPC_FilterValue, 0, 87, 17, // Skip to: 7015 >+/* 2576 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 2591 >+/* 2580 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 2591 >+/* 2586 */ MCD_OPC_Decode, 253, 17, 141, 2, // Opcode: t2BFC >+/* 2591 */ MCD_OPC_CheckPredicate, 22, 68, 17, // Skip to: 7015 >+/* 2595 */ MCD_OPC_Decode, 254, 17, 142, 2, // Opcode: t2BFI >+/* 2600 */ MCD_OPC_FilterValue, 2, 49, 0, // Skip to: 2653 >+/* 2604 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 2607 */ MCD_OPC_FilterValue, 0, 52, 17, // Skip to: 7015 >+/* 2611 */ MCD_OPC_CheckPredicate, 29, 29, 0, // Skip to: 2644 >+/* 2615 */ MCD_OPC_CheckField, 26, 1, 0, 23, 0, // Skip to: 2644 >+/* 2621 */ MCD_OPC_CheckField, 21, 1, 1, 17, 0, // Skip to: 2644 >+/* 2627 */ MCD_OPC_CheckField, 12, 3, 0, 11, 0, // Skip to: 2644 >+/* 2633 */ MCD_OPC_CheckField, 4, 4, 0, 5, 0, // Skip to: 2644 >+/* 2639 */ MCD_OPC_Decode, 243, 20, 138, 2, // Opcode: t2USAT16 >+/* 2644 */ MCD_OPC_CheckPredicate, 22, 15, 17, // Skip to: 7015 >+/* 2648 */ MCD_OPC_Decode, 242, 20, 139, 2, // Opcode: t2USAT >+/* 2653 */ MCD_OPC_FilterValue, 3, 6, 17, // Skip to: 7015 >+/* 2657 */ MCD_OPC_CheckPredicate, 22, 2, 17, // Skip to: 7015 >+/* 2661 */ MCD_OPC_CheckField, 20, 2, 0, 252, 16, // Skip to: 7015 >+/* 2667 */ MCD_OPC_Decode, 222, 20, 140, 2, // Opcode: t2UBFX >+/* 2672 */ MCD_OPC_FilterValue, 1, 243, 16, // Skip to: 7015 >+/* 2676 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... >+/* 2679 */ MCD_OPC_FilterValue, 0, 231, 1, // Skip to: 3170 >+/* 2683 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... >+/* 2686 */ MCD_OPC_FilterValue, 0, 229, 16, // Skip to: 7015 >+/* 2690 */ MCD_OPC_ExtractField, 16, 11, // Inst{26-16} ... >+/* 2693 */ MCD_OPC_FilterValue, 175, 7, 115, 0, // Skip to: 2813 >+/* 2698 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 2701 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 2765 >+/* 2705 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 2708 */ MCD_OPC_FilterValue, 0, 85, 1, // Skip to: 3053 >+/* 2712 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 2715 */ MCD_OPC_FilterValue, 0, 78, 1, // Skip to: 3053 >+/* 2719 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 2722 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 2750 >+/* 2726 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 2741 >+/* 2730 */ MCD_OPC_CheckField, 4, 4, 15, 5, 0, // Skip to: 2741 >+/* 2736 */ MCD_OPC_Decode, 152, 18, 143, 2, // Opcode: t2DBG >+/* 2741 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 2750 >+/* 2745 */ MCD_OPC_Decode, 161, 18, 222, 1, // Opcode: t2HINT >+/* 2750 */ MCD_OPC_CheckPredicate, 22, 43, 1, // Skip to: 3053 >+/* 2754 */ MCD_OPC_CheckField, 0, 5, 0, 37, 1, // Skip to: 3053 >+/* 2760 */ MCD_OPC_Decode, 144, 18, 144, 2, // Opcode: t2CPS2p >+/* 2765 */ MCD_OPC_FilterValue, 1, 28, 1, // Skip to: 3053 >+/* 2769 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... >+/* 2772 */ MCD_OPC_FilterValue, 0, 21, 1, // Skip to: 3053 >+/* 2776 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 2779 */ MCD_OPC_FilterValue, 0, 14, 1, // Skip to: 3053 >+/* 2783 */ MCD_OPC_CheckPredicate, 22, 17, 0, // Skip to: 2804 >+/* 2787 */ MCD_OPC_CheckField, 9, 2, 0, 11, 0, // Skip to: 2804 >+/* 2793 */ MCD_OPC_CheckField, 5, 3, 0, 5, 0, // Skip to: 2804 >+/* 2799 */ MCD_OPC_Decode, 143, 18, 144, 2, // Opcode: t2CPS1p >+/* 2804 */ MCD_OPC_CheckPredicate, 22, 245, 0, // Skip to: 3053 >+/* 2808 */ MCD_OPC_Decode, 145, 18, 144, 2, // Opcode: t2CPS3p >+/* 2813 */ MCD_OPC_FilterValue, 191, 7, 85, 0, // Skip to: 2903 >+/* 2818 */ MCD_OPC_ExtractField, 4, 8, // Inst{11-4} ... >+/* 2821 */ MCD_OPC_FilterValue, 242, 1, 20, 0, // Skip to: 2846 >+/* 2826 */ MCD_OPC_CheckPredicate, 30, 223, 0, // Skip to: 3053 >+/* 2830 */ MCD_OPC_CheckField, 13, 1, 0, 217, 0, // Skip to: 3053 >+/* 2836 */ MCD_OPC_CheckField, 0, 4, 15, 211, 0, // Skip to: 3053 >+/* 2842 */ MCD_OPC_Decode, 135, 18, 58, // Opcode: t2CLREX >+/* 2846 */ MCD_OPC_FilterValue, 244, 1, 14, 0, // Skip to: 2865 >+/* 2851 */ MCD_OPC_CheckPredicate, 31, 198, 0, // Skip to: 3053 >+/* 2855 */ MCD_OPC_CheckField, 13, 1, 0, 192, 0, // Skip to: 3053 >+/* 2861 */ MCD_OPC_Decode, 157, 18, 59, // Opcode: t2DSB >+/* 2865 */ MCD_OPC_FilterValue, 245, 1, 14, 0, // Skip to: 2884 >+/* 2870 */ MCD_OPC_CheckPredicate, 31, 179, 0, // Skip to: 3053 >+/* 2874 */ MCD_OPC_CheckField, 13, 1, 0, 173, 0, // Skip to: 3053 >+/* 2880 */ MCD_OPC_Decode, 156, 18, 59, // Opcode: t2DMB >+/* 2884 */ MCD_OPC_FilterValue, 246, 1, 164, 0, // Skip to: 3053 >+/* 2889 */ MCD_OPC_CheckPredicate, 31, 160, 0, // Skip to: 3053 >+/* 2893 */ MCD_OPC_CheckField, 13, 1, 0, 154, 0, // Skip to: 3053 >+/* 2899 */ MCD_OPC_Decode, 162, 18, 60, // Opcode: t2ISB >+/* 2903 */ MCD_OPC_FilterValue, 222, 7, 21, 0, // Skip to: 2929 >+/* 2908 */ MCD_OPC_CheckPredicate, 22, 141, 0, // Skip to: 3053 >+/* 2912 */ MCD_OPC_CheckField, 13, 1, 0, 135, 0, // Skip to: 3053 >+/* 2918 */ MCD_OPC_CheckField, 8, 4, 15, 129, 0, // Skip to: 3053 >+/* 2924 */ MCD_OPC_Decode, 195, 20, 222, 1, // Opcode: t2SUBS_PC_LR >+/* 2929 */ MCD_OPC_FilterValue, 239, 7, 31, 0, // Skip to: 2965 >+/* 2934 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 2937 */ MCD_OPC_FilterValue, 0, 112, 0, // Skip to: 3053 >+/* 2941 */ MCD_OPC_CheckPredicate, 32, 11, 0, // Skip to: 2956 >+/* 2945 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, // Skip to: 2956 >+/* 2951 */ MCD_OPC_Decode, 152, 19, 145, 2, // Opcode: t2MRS_AR >+/* 2956 */ MCD_OPC_CheckPredicate, 33, 93, 0, // Skip to: 3053 >+/* 2960 */ MCD_OPC_Decode, 153, 19, 146, 2, // Opcode: t2MRS_M >+/* 2965 */ MCD_OPC_FilterValue, 255, 7, 21, 0, // Skip to: 2991 >+/* 2970 */ MCD_OPC_CheckPredicate, 32, 79, 0, // Skip to: 3053 >+/* 2974 */ MCD_OPC_CheckField, 13, 1, 0, 73, 0, // Skip to: 3053 >+/* 2980 */ MCD_OPC_CheckField, 0, 8, 0, 67, 0, // Skip to: 3053 >+/* 2986 */ MCD_OPC_Decode, 154, 19, 145, 2, // Opcode: t2MRSsys_AR >+/* 2991 */ MCD_OPC_FilterValue, 143, 15, 57, 0, // Skip to: 3053 >+/* 2996 */ MCD_OPC_ExtractField, 0, 12, // Inst{11-0} ... >+/* 2999 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3017 >+/* 3003 */ MCD_OPC_CheckPredicate, 34, 46, 0, // Skip to: 3053 >+/* 3007 */ MCD_OPC_CheckField, 13, 1, 0, 40, 0, // Skip to: 3053 >+/* 3013 */ MCD_OPC_Decode, 153, 18, 58, // Opcode: t2DCPS1 >+/* 3017 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3035 >+/* 3021 */ MCD_OPC_CheckPredicate, 34, 28, 0, // Skip to: 3053 >+/* 3025 */ MCD_OPC_CheckField, 13, 1, 0, 22, 0, // Skip to: 3053 >+/* 3031 */ MCD_OPC_Decode, 154, 18, 58, // Opcode: t2DCPS2 >+/* 3035 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3053 >+/* 3039 */ MCD_OPC_CheckPredicate, 34, 10, 0, // Skip to: 3053 >+/* 3043 */ MCD_OPC_CheckField, 13, 1, 0, 4, 0, // Skip to: 3053 >+/* 3049 */ MCD_OPC_Decode, 155, 18, 58, // Opcode: t2DCPS3 >+/* 3053 */ MCD_OPC_ExtractField, 20, 7, // Inst{26-20} ... >+/* 3056 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 3075 >+/* 3060 */ MCD_OPC_CheckPredicate, 33, 70, 0, // Skip to: 3134 >+/* 3064 */ MCD_OPC_CheckField, 13, 1, 0, 64, 0, // Skip to: 3134 >+/* 3070 */ MCD_OPC_Decode, 156, 19, 147, 2, // Opcode: t2MSR_M >+/* 3075 */ MCD_OPC_FilterValue, 60, 22, 0, // Skip to: 3101 >+/* 3079 */ MCD_OPC_CheckPredicate, 22, 51, 0, // Skip to: 3134 >+/* 3083 */ MCD_OPC_CheckField, 13, 1, 0, 45, 0, // Skip to: 3134 >+/* 3089 */ MCD_OPC_CheckField, 0, 12, 128, 30, 38, 0, // Skip to: 3134 >+/* 3096 */ MCD_OPC_Decode, 131, 18, 148, 2, // Opcode: t2BXJ >+/* 3101 */ MCD_OPC_FilterValue, 127, 29, 0, // Skip to: 3134 >+/* 3105 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... >+/* 3108 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 3121 >+/* 3112 */ MCD_OPC_CheckPredicate, 35, 18, 0, // Skip to: 3134 >+/* 3116 */ MCD_OPC_Decode, 222, 19, 149, 2, // Opcode: t2SMC >+/* 3121 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3134 >+/* 3125 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3134 >+/* 3129 */ MCD_OPC_Decode, 223, 20, 150, 2, // Opcode: t2UDF >+/* 3134 */ MCD_OPC_CheckPredicate, 32, 23, 0, // Skip to: 3161 >+/* 3138 */ MCD_OPC_CheckField, 21, 6, 28, 17, 0, // Skip to: 3161 >+/* 3144 */ MCD_OPC_CheckField, 13, 1, 0, 11, 0, // Skip to: 3161 >+/* 3150 */ MCD_OPC_CheckField, 0, 8, 0, 5, 0, // Skip to: 3161 >+/* 3156 */ MCD_OPC_Decode, 155, 19, 151, 2, // Opcode: t2MSR_AR >+/* 3161 */ MCD_OPC_CheckPredicate, 22, 10, 15, // Skip to: 7015 >+/* 3165 */ MCD_OPC_Decode, 132, 18, 152, 2, // Opcode: t2Bcc >+/* 3170 */ MCD_OPC_FilterValue, 1, 1, 15, // Skip to: 7015 >+/* 3174 */ MCD_OPC_CheckPredicate, 22, 253, 14, // Skip to: 7015 >+/* 3178 */ MCD_OPC_CheckField, 14, 1, 0, 247, 14, // Skip to: 7015 >+/* 3184 */ MCD_OPC_Decode, 252, 17, 153, 2, // Opcode: t2B >+/* 3189 */ MCD_OPC_FilterValue, 31, 238, 14, // Skip to: 7015 >+/* 3193 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ... >+/* 3196 */ MCD_OPC_FilterValue, 0, 76, 3, // Skip to: 4044 >+/* 3200 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 3203 */ MCD_OPC_FilterValue, 0, 109, 0, // Skip to: 3316 >+/* 3207 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3210 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3303 >+/* 3214 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3217 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3236 >+/* 3221 */ MCD_OPC_CheckPredicate, 22, 206, 14, // Skip to: 7015 >+/* 3225 */ MCD_OPC_CheckField, 6, 4, 0, 200, 14, // Skip to: 7015 >+/* 3231 */ MCD_OPC_Decode, 173, 20, 154, 2, // Opcode: t2STRBs >+/* 3236 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3255 >+/* 3240 */ MCD_OPC_CheckPredicate, 22, 187, 14, // Skip to: 7015 >+/* 3244 */ MCD_OPC_CheckField, 8, 1, 1, 181, 14, // Skip to: 7015 >+/* 3250 */ MCD_OPC_Decode, 168, 20, 155, 2, // Opcode: t2STRB_POST >+/* 3255 */ MCD_OPC_FilterValue, 3, 172, 14, // Skip to: 7015 >+/* 3259 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3262 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3290 >+/* 3266 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3281 >+/* 3270 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3281 >+/* 3276 */ MCD_OPC_Decode, 167, 20, 156, 2, // Opcode: t2STRBT >+/* 3281 */ MCD_OPC_CheckPredicate, 22, 146, 14, // Skip to: 7015 >+/* 3285 */ MCD_OPC_Decode, 172, 20, 157, 2, // Opcode: t2STRBi8 >+/* 3290 */ MCD_OPC_FilterValue, 1, 137, 14, // Skip to: 7015 >+/* 3294 */ MCD_OPC_CheckPredicate, 22, 133, 14, // Skip to: 7015 >+/* 3298 */ MCD_OPC_Decode, 169, 20, 155, 2, // Opcode: t2STRB_PRE >+/* 3303 */ MCD_OPC_FilterValue, 1, 124, 14, // Skip to: 7015 >+/* 3307 */ MCD_OPC_CheckPredicate, 22, 120, 14, // Skip to: 7015 >+/* 3311 */ MCD_OPC_Decode, 171, 20, 158, 2, // Opcode: t2STRBi12 >+/* 3316 */ MCD_OPC_FilterValue, 1, 191, 0, // Skip to: 3511 >+/* 3320 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3323 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 3452 >+/* 3327 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3330 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3365 >+/* 3334 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 3337 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 3480 >+/* 3341 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3356 >+/* 3345 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3356 >+/* 3351 */ MCD_OPC_Decode, 176, 19, 159, 2, // Opcode: t2PLDs >+/* 3356 */ MCD_OPC_CheckPredicate, 22, 120, 0, // Skip to: 3480 >+/* 3360 */ MCD_OPC_Decode, 201, 18, 159, 2, // Opcode: t2LDRBs >+/* 3365 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3384 >+/* 3369 */ MCD_OPC_CheckPredicate, 22, 107, 0, // Skip to: 3480 >+/* 3373 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 3480 >+/* 3379 */ MCD_OPC_Decode, 195, 18, 155, 2, // Opcode: t2LDRB_POST >+/* 3384 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 3480 >+/* 3388 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3391 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 3439 >+/* 3395 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 3398 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3417 >+/* 3402 */ MCD_OPC_CheckPredicate, 22, 24, 0, // Skip to: 3430 >+/* 3406 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 3430 >+/* 3412 */ MCD_OPC_Decode, 174, 19, 160, 2, // Opcode: t2PLDi8 >+/* 3417 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3430 >+/* 3421 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3430 >+/* 3425 */ MCD_OPC_Decode, 194, 18, 161, 2, // Opcode: t2LDRBT >+/* 3430 */ MCD_OPC_CheckPredicate, 22, 46, 0, // Skip to: 3480 >+/* 3434 */ MCD_OPC_Decode, 198, 18, 160, 2, // Opcode: t2LDRBi8 >+/* 3439 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 3480 >+/* 3443 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 3480 >+/* 3447 */ MCD_OPC_Decode, 196, 18, 155, 2, // Opcode: t2LDRB_PRE >+/* 3452 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 3480 >+/* 3456 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3471 >+/* 3460 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3471 >+/* 3466 */ MCD_OPC_Decode, 173, 19, 162, 2, // Opcode: t2PLDi12 >+/* 3471 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3480 >+/* 3475 */ MCD_OPC_Decode, 197, 18, 162, 2, // Opcode: t2LDRBi12 >+/* 3480 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 3483 */ MCD_OPC_FilterValue, 15, 200, 13, // Skip to: 7015 >+/* 3487 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3502 >+/* 3491 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3502 >+/* 3497 */ MCD_OPC_Decode, 175, 19, 163, 2, // Opcode: t2PLDpci >+/* 3502 */ MCD_OPC_CheckPredicate, 22, 181, 13, // Skip to: 7015 >+/* 3506 */ MCD_OPC_Decode, 199, 18, 163, 2, // Opcode: t2LDRBpci >+/* 3511 */ MCD_OPC_FilterValue, 2, 109, 0, // Skip to: 3624 >+/* 3515 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3518 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3611 >+/* 3522 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3525 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3544 >+/* 3529 */ MCD_OPC_CheckPredicate, 22, 154, 13, // Skip to: 7015 >+/* 3533 */ MCD_OPC_CheckField, 6, 4, 0, 148, 13, // Skip to: 7015 >+/* 3539 */ MCD_OPC_Decode, 187, 20, 154, 2, // Opcode: t2STRHs >+/* 3544 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3563 >+/* 3548 */ MCD_OPC_CheckPredicate, 22, 135, 13, // Skip to: 7015 >+/* 3552 */ MCD_OPC_CheckField, 8, 1, 1, 129, 13, // Skip to: 7015 >+/* 3558 */ MCD_OPC_Decode, 182, 20, 155, 2, // Opcode: t2STRH_POST >+/* 3563 */ MCD_OPC_FilterValue, 3, 120, 13, // Skip to: 7015 >+/* 3567 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3570 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3598 >+/* 3574 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3589 >+/* 3578 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3589 >+/* 3584 */ MCD_OPC_Decode, 181, 20, 156, 2, // Opcode: t2STRHT >+/* 3589 */ MCD_OPC_CheckPredicate, 22, 94, 13, // Skip to: 7015 >+/* 3593 */ MCD_OPC_Decode, 186, 20, 157, 2, // Opcode: t2STRHi8 >+/* 3598 */ MCD_OPC_FilterValue, 1, 85, 13, // Skip to: 7015 >+/* 3602 */ MCD_OPC_CheckPredicate, 22, 81, 13, // Skip to: 7015 >+/* 3606 */ MCD_OPC_Decode, 183, 20, 155, 2, // Opcode: t2STRH_PRE >+/* 3611 */ MCD_OPC_FilterValue, 1, 72, 13, // Skip to: 7015 >+/* 3615 */ MCD_OPC_CheckPredicate, 22, 68, 13, // Skip to: 7015 >+/* 3619 */ MCD_OPC_Decode, 185, 20, 158, 2, // Opcode: t2STRHi12 >+/* 3624 */ MCD_OPC_FilterValue, 3, 175, 0, // Skip to: 3803 >+/* 3628 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3631 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 3760 >+/* 3635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3638 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 3673 >+/* 3642 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 3645 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 3788 >+/* 3649 */ MCD_OPC_CheckPredicate, 36, 11, 0, // Skip to: 3664 >+/* 3653 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3664 >+/* 3659 */ MCD_OPC_Decode, 172, 19, 159, 2, // Opcode: t2PLDWs >+/* 3664 */ MCD_OPC_CheckPredicate, 22, 120, 0, // Skip to: 3788 >+/* 3668 */ MCD_OPC_Decode, 216, 18, 159, 2, // Opcode: t2LDRHs >+/* 3673 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3692 >+/* 3677 */ MCD_OPC_CheckPredicate, 22, 107, 0, // Skip to: 3788 >+/* 3681 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 3788 >+/* 3687 */ MCD_OPC_Decode, 210, 18, 155, 2, // Opcode: t2LDRH_POST >+/* 3692 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 3788 >+/* 3696 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3699 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 3747 >+/* 3703 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 3706 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3725 >+/* 3710 */ MCD_OPC_CheckPredicate, 36, 24, 0, // Skip to: 3738 >+/* 3714 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 3738 >+/* 3720 */ MCD_OPC_Decode, 171, 19, 160, 2, // Opcode: t2PLDWi8 >+/* 3725 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 3738 >+/* 3729 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3738 >+/* 3733 */ MCD_OPC_Decode, 209, 18, 161, 2, // Opcode: t2LDRHT >+/* 3738 */ MCD_OPC_CheckPredicate, 22, 46, 0, // Skip to: 3788 >+/* 3742 */ MCD_OPC_Decode, 213, 18, 160, 2, // Opcode: t2LDRHi8 >+/* 3747 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 3788 >+/* 3751 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 3788 >+/* 3755 */ MCD_OPC_Decode, 211, 18, 155, 2, // Opcode: t2LDRH_PRE >+/* 3760 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 3788 >+/* 3764 */ MCD_OPC_CheckPredicate, 36, 11, 0, // Skip to: 3779 >+/* 3768 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 3779 >+/* 3774 */ MCD_OPC_Decode, 170, 19, 162, 2, // Opcode: t2PLDWi12 >+/* 3779 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 3788 >+/* 3783 */ MCD_OPC_Decode, 212, 18, 162, 2, // Opcode: t2LDRHi12 >+/* 3788 */ MCD_OPC_CheckPredicate, 22, 151, 12, // Skip to: 7015 >+/* 3792 */ MCD_OPC_CheckField, 16, 4, 15, 145, 12, // Skip to: 7015 >+/* 3798 */ MCD_OPC_Decode, 214, 18, 163, 2, // Opcode: t2LDRHpci >+/* 3803 */ MCD_OPC_FilterValue, 4, 109, 0, // Skip to: 3916 >+/* 3807 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3810 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 3903 >+/* 3814 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3817 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3836 >+/* 3821 */ MCD_OPC_CheckPredicate, 22, 118, 12, // Skip to: 7015 >+/* 3825 */ MCD_OPC_CheckField, 6, 4, 0, 112, 12, // Skip to: 7015 >+/* 3831 */ MCD_OPC_Decode, 194, 20, 164, 2, // Opcode: t2STRs >+/* 3836 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3855 >+/* 3840 */ MCD_OPC_CheckPredicate, 22, 99, 12, // Skip to: 7015 >+/* 3844 */ MCD_OPC_CheckField, 8, 1, 1, 93, 12, // Skip to: 7015 >+/* 3850 */ MCD_OPC_Decode, 189, 20, 155, 2, // Opcode: t2STR_POST >+/* 3855 */ MCD_OPC_FilterValue, 3, 84, 12, // Skip to: 7015 >+/* 3859 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3862 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 3890 >+/* 3866 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3881 >+/* 3870 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3881 >+/* 3876 */ MCD_OPC_Decode, 188, 20, 156, 2, // Opcode: t2STRT >+/* 3881 */ MCD_OPC_CheckPredicate, 22, 58, 12, // Skip to: 7015 >+/* 3885 */ MCD_OPC_Decode, 193, 20, 165, 2, // Opcode: t2STRi8 >+/* 3890 */ MCD_OPC_FilterValue, 1, 49, 12, // Skip to: 7015 >+/* 3894 */ MCD_OPC_CheckPredicate, 22, 45, 12, // Skip to: 7015 >+/* 3898 */ MCD_OPC_Decode, 190, 20, 155, 2, // Opcode: t2STR_PRE >+/* 3903 */ MCD_OPC_FilterValue, 1, 36, 12, // Skip to: 7015 >+/* 3907 */ MCD_OPC_CheckPredicate, 22, 32, 12, // Skip to: 7015 >+/* 3911 */ MCD_OPC_Decode, 192, 20, 166, 2, // Opcode: t2STRi12 >+/* 3916 */ MCD_OPC_FilterValue, 5, 23, 12, // Skip to: 7015 >+/* 3920 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 3923 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 4016 >+/* 3927 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 3930 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 3949 >+/* 3934 */ MCD_OPC_CheckPredicate, 22, 91, 0, // Skip to: 4029 >+/* 3938 */ MCD_OPC_CheckField, 6, 4, 0, 85, 0, // Skip to: 4029 >+/* 3944 */ MCD_OPC_Decode, 241, 18, 159, 2, // Opcode: t2LDRs >+/* 3949 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 3968 >+/* 3953 */ MCD_OPC_CheckPredicate, 22, 72, 0, // Skip to: 4029 >+/* 3957 */ MCD_OPC_CheckField, 8, 1, 1, 66, 0, // Skip to: 4029 >+/* 3963 */ MCD_OPC_Decode, 234, 18, 155, 2, // Opcode: t2LDR_POST >+/* 3968 */ MCD_OPC_FilterValue, 3, 57, 0, // Skip to: 4029 >+/* 3972 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 3975 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4003 >+/* 3979 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 3994 >+/* 3983 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 3994 >+/* 3989 */ MCD_OPC_Decode, 233, 18, 161, 2, // Opcode: t2LDRT >+/* 3994 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4029 >+/* 3998 */ MCD_OPC_Decode, 237, 18, 160, 2, // Opcode: t2LDRi8 >+/* 4003 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 4029 >+/* 4007 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4029 >+/* 4011 */ MCD_OPC_Decode, 235, 18, 155, 2, // Opcode: t2LDR_PRE >+/* 4016 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4029 >+/* 4020 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4029 >+/* 4024 */ MCD_OPC_Decode, 236, 18, 162, 2, // Opcode: t2LDRi12 >+/* 4029 */ MCD_OPC_CheckPredicate, 22, 166, 11, // Skip to: 7015 >+/* 4033 */ MCD_OPC_CheckField, 16, 4, 15, 160, 11, // Skip to: 7015 >+/* 4039 */ MCD_OPC_Decode, 238, 18, 163, 2, // Opcode: t2LDRpci >+/* 4044 */ MCD_OPC_FilterValue, 1, 70, 1, // Skip to: 4374 >+/* 4048 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 4051 */ MCD_OPC_FilterValue, 1, 191, 0, // Skip to: 4246 >+/* 4055 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 4058 */ MCD_OPC_FilterValue, 0, 125, 0, // Skip to: 4187 >+/* 4062 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4065 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4100 >+/* 4069 */ MCD_OPC_ExtractField, 6, 4, // Inst{9-6} ... >+/* 4072 */ MCD_OPC_FilterValue, 0, 139, 0, // Skip to: 4215 >+/* 4076 */ MCD_OPC_CheckPredicate, 30, 11, 0, // Skip to: 4091 >+/* 4080 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4091 >+/* 4086 */ MCD_OPC_Decode, 180, 19, 159, 2, // Opcode: t2PLIs >+/* 4091 */ MCD_OPC_CheckPredicate, 22, 120, 0, // Skip to: 4215 >+/* 4095 */ MCD_OPC_Decode, 224, 18, 159, 2, // Opcode: t2LDRSBs >+/* 4100 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 4119 >+/* 4104 */ MCD_OPC_CheckPredicate, 22, 107, 0, // Skip to: 4215 >+/* 4108 */ MCD_OPC_CheckField, 8, 1, 1, 101, 0, // Skip to: 4215 >+/* 4114 */ MCD_OPC_Decode, 218, 18, 155, 2, // Opcode: t2LDRSB_POST >+/* 4119 */ MCD_OPC_FilterValue, 3, 92, 0, // Skip to: 4215 >+/* 4123 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 4126 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 4174 >+/* 4130 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... >+/* 4133 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4152 >+/* 4137 */ MCD_OPC_CheckPredicate, 30, 24, 0, // Skip to: 4165 >+/* 4141 */ MCD_OPC_CheckField, 12, 4, 15, 18, 0, // Skip to: 4165 >+/* 4147 */ MCD_OPC_Decode, 178, 19, 160, 2, // Opcode: t2PLIi8 >+/* 4152 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4165 >+/* 4156 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4165 >+/* 4160 */ MCD_OPC_Decode, 217, 18, 161, 2, // Opcode: t2LDRSBT >+/* 4165 */ MCD_OPC_CheckPredicate, 22, 46, 0, // Skip to: 4215 >+/* 4169 */ MCD_OPC_Decode, 221, 18, 160, 2, // Opcode: t2LDRSBi8 >+/* 4174 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 4215 >+/* 4178 */ MCD_OPC_CheckPredicate, 22, 33, 0, // Skip to: 4215 >+/* 4182 */ MCD_OPC_Decode, 219, 18, 155, 2, // Opcode: t2LDRSB_PRE >+/* 4187 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 4215 >+/* 4191 */ MCD_OPC_CheckPredicate, 30, 11, 0, // Skip to: 4206 >+/* 4195 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4206 >+/* 4201 */ MCD_OPC_Decode, 177, 19, 162, 2, // Opcode: t2PLIi12 >+/* 4206 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4215 >+/* 4210 */ MCD_OPC_Decode, 220, 18, 162, 2, // Opcode: t2LDRSBi12 >+/* 4215 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 4218 */ MCD_OPC_FilterValue, 15, 233, 10, // Skip to: 7015 >+/* 4222 */ MCD_OPC_CheckPredicate, 30, 11, 0, // Skip to: 4237 >+/* 4226 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 4237 >+/* 4232 */ MCD_OPC_Decode, 179, 19, 163, 2, // Opcode: t2PLIpci >+/* 4237 */ MCD_OPC_CheckPredicate, 22, 214, 10, // Skip to: 7015 >+/* 4241 */ MCD_OPC_Decode, 222, 18, 163, 2, // Opcode: t2LDRSBpci >+/* 4246 */ MCD_OPC_FilterValue, 3, 205, 10, // Skip to: 7015 >+/* 4250 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 4253 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 4346 >+/* 4257 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... >+/* 4260 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4279 >+/* 4264 */ MCD_OPC_CheckPredicate, 22, 91, 0, // Skip to: 4359 >+/* 4268 */ MCD_OPC_CheckField, 6, 4, 0, 85, 0, // Skip to: 4359 >+/* 4274 */ MCD_OPC_Decode, 232, 18, 159, 2, // Opcode: t2LDRSHs >+/* 4279 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 4298 >+/* 4283 */ MCD_OPC_CheckPredicate, 22, 72, 0, // Skip to: 4359 >+/* 4287 */ MCD_OPC_CheckField, 8, 1, 1, 66, 0, // Skip to: 4359 >+/* 4293 */ MCD_OPC_Decode, 226, 18, 155, 2, // Opcode: t2LDRSH_POST >+/* 4298 */ MCD_OPC_FilterValue, 3, 57, 0, // Skip to: 4359 >+/* 4302 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ... >+/* 4305 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 4333 >+/* 4309 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4324 >+/* 4313 */ MCD_OPC_CheckField, 9, 1, 1, 5, 0, // Skip to: 4324 >+/* 4319 */ MCD_OPC_Decode, 225, 18, 161, 2, // Opcode: t2LDRSHT >+/* 4324 */ MCD_OPC_CheckPredicate, 22, 31, 0, // Skip to: 4359 >+/* 4328 */ MCD_OPC_Decode, 229, 18, 160, 2, // Opcode: t2LDRSHi8 >+/* 4333 */ MCD_OPC_FilterValue, 1, 22, 0, // Skip to: 4359 >+/* 4337 */ MCD_OPC_CheckPredicate, 22, 18, 0, // Skip to: 4359 >+/* 4341 */ MCD_OPC_Decode, 227, 18, 155, 2, // Opcode: t2LDRSH_PRE >+/* 4346 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 4359 >+/* 4350 */ MCD_OPC_CheckPredicate, 22, 5, 0, // Skip to: 4359 >+/* 4354 */ MCD_OPC_Decode, 228, 18, 162, 2, // Opcode: t2LDRSHi12 >+/* 4359 */ MCD_OPC_CheckPredicate, 22, 92, 10, // Skip to: 7015 >+/* 4363 */ MCD_OPC_CheckField, 16, 4, 15, 86, 10, // Skip to: 7015 >+/* 4369 */ MCD_OPC_Decode, 230, 18, 163, 2, // Opcode: t2LDRSHpci >+/* 4374 */ MCD_OPC_FilterValue, 2, 47, 6, // Skip to: 5961 >+/* 4378 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... >+/* 4381 */ MCD_OPC_FilterValue, 0, 105, 0, // Skip to: 4490 >+/* 4385 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4388 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4413 >+/* 4392 */ MCD_OPC_CheckPredicate, 22, 59, 10, // Skip to: 7015 >+/* 4396 */ MCD_OPC_CheckField, 12, 4, 15, 53, 10, // Skip to: 7015 >+/* 4402 */ MCD_OPC_CheckField, 4, 3, 0, 47, 10, // Skip to: 7015 >+/* 4408 */ MCD_OPC_Decode, 245, 18, 249, 1, // Opcode: t2LSLrr >+/* 4413 */ MCD_OPC_FilterValue, 1, 38, 10, // Skip to: 7015 >+/* 4417 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4420 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4455 >+/* 4424 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4427 */ MCD_OPC_FilterValue, 15, 24, 10, // Skip to: 7015 >+/* 4431 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4446 >+/* 4435 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4446 >+/* 4441 */ MCD_OPC_Decode, 208, 20, 167, 2, // Opcode: t2SXTH >+/* 4446 */ MCD_OPC_CheckPredicate, 27, 5, 10, // Skip to: 7015 >+/* 4450 */ MCD_OPC_Decode, 205, 20, 168, 2, // Opcode: t2SXTAH >+/* 4455 */ MCD_OPC_FilterValue, 1, 252, 9, // Skip to: 7015 >+/* 4459 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4462 */ MCD_OPC_FilterValue, 15, 245, 9, // Skip to: 7015 >+/* 4466 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4481 >+/* 4470 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4481 >+/* 4476 */ MCD_OPC_Decode, 252, 20, 167, 2, // Opcode: t2UXTH >+/* 4481 */ MCD_OPC_CheckPredicate, 27, 226, 9, // Skip to: 7015 >+/* 4485 */ MCD_OPC_Decode, 249, 20, 168, 2, // Opcode: t2UXTAH >+/* 4490 */ MCD_OPC_FilterValue, 1, 105, 0, // Skip to: 4599 >+/* 4494 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4497 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4522 >+/* 4501 */ MCD_OPC_CheckPredicate, 22, 206, 9, // Skip to: 7015 >+/* 4505 */ MCD_OPC_CheckField, 12, 4, 15, 200, 9, // Skip to: 7015 >+/* 4511 */ MCD_OPC_CheckField, 4, 3, 0, 194, 9, // Skip to: 7015 >+/* 4517 */ MCD_OPC_Decode, 247, 18, 249, 1, // Opcode: t2LSRrr >+/* 4522 */ MCD_OPC_FilterValue, 1, 185, 9, // Skip to: 7015 >+/* 4526 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4529 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4564 >+/* 4533 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4536 */ MCD_OPC_FilterValue, 15, 171, 9, // Skip to: 7015 >+/* 4540 */ MCD_OPC_CheckPredicate, 37, 11, 0, // Skip to: 4555 >+/* 4544 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4555 >+/* 4550 */ MCD_OPC_Decode, 207, 20, 167, 2, // Opcode: t2SXTB16 >+/* 4555 */ MCD_OPC_CheckPredicate, 22, 152, 9, // Skip to: 7015 >+/* 4559 */ MCD_OPC_Decode, 204, 20, 168, 2, // Opcode: t2SXTAB16 >+/* 4564 */ MCD_OPC_FilterValue, 1, 143, 9, // Skip to: 7015 >+/* 4568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4571 */ MCD_OPC_FilterValue, 15, 136, 9, // Skip to: 7015 >+/* 4575 */ MCD_OPC_CheckPredicate, 27, 11, 0, // Skip to: 4590 >+/* 4579 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4590 >+/* 4585 */ MCD_OPC_Decode, 251, 20, 167, 2, // Opcode: t2UXTB16 >+/* 4590 */ MCD_OPC_CheckPredicate, 22, 117, 9, // Skip to: 7015 >+/* 4594 */ MCD_OPC_Decode, 248, 20, 168, 2, // Opcode: t2UXTAB16 >+/* 4599 */ MCD_OPC_FilterValue, 2, 105, 0, // Skip to: 4708 >+/* 4603 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ... >+/* 4606 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 4631 >+/* 4610 */ MCD_OPC_CheckPredicate, 22, 97, 9, // Skip to: 7015 >+/* 4614 */ MCD_OPC_CheckField, 12, 4, 15, 91, 9, // Skip to: 7015 >+/* 4620 */ MCD_OPC_CheckField, 4, 3, 0, 85, 9, // Skip to: 7015 >+/* 4626 */ MCD_OPC_Decode, 251, 17, 249, 1, // Opcode: t2ASRrr >+/* 4631 */ MCD_OPC_FilterValue, 1, 76, 9, // Skip to: 7015 >+/* 4635 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4638 */ MCD_OPC_FilterValue, 0, 31, 0, // Skip to: 4673 >+/* 4642 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4645 */ MCD_OPC_FilterValue, 15, 62, 9, // Skip to: 7015 >+/* 4649 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4664 >+/* 4653 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4664 >+/* 4659 */ MCD_OPC_Decode, 206, 20, 167, 2, // Opcode: t2SXTB >+/* 4664 */ MCD_OPC_CheckPredicate, 27, 43, 9, // Skip to: 7015 >+/* 4668 */ MCD_OPC_Decode, 203, 20, 168, 2, // Opcode: t2SXTAB >+/* 4673 */ MCD_OPC_FilterValue, 1, 34, 9, // Skip to: 7015 >+/* 4677 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 4680 */ MCD_OPC_FilterValue, 15, 27, 9, // Skip to: 7015 >+/* 4684 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 4699 >+/* 4688 */ MCD_OPC_CheckField, 16, 4, 15, 5, 0, // Skip to: 4699 >+/* 4694 */ MCD_OPC_Decode, 250, 20, 167, 2, // Opcode: t2UXTB >+/* 4699 */ MCD_OPC_CheckPredicate, 27, 8, 9, // Skip to: 7015 >+/* 4703 */ MCD_OPC_Decode, 247, 20, 168, 2, // Opcode: t2UXTAB >+/* 4708 */ MCD_OPC_FilterValue, 3, 21, 0, // Skip to: 4733 >+/* 4712 */ MCD_OPC_CheckPredicate, 22, 251, 8, // Skip to: 7015 >+/* 4716 */ MCD_OPC_CheckField, 12, 4, 15, 245, 8, // Skip to: 7015 >+/* 4722 */ MCD_OPC_CheckField, 4, 4, 0, 239, 8, // Skip to: 7015 >+/* 4728 */ MCD_OPC_Decode, 200, 19, 249, 1, // Opcode: t2RORrr >+/* 4733 */ MCD_OPC_FilterValue, 4, 197, 1, // Skip to: 5190 >+/* 4737 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 4740 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 4785 >+/* 4744 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4747 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4766 >+/* 4751 */ MCD_OPC_CheckPredicate, 29, 212, 8, // Skip to: 7015 >+/* 4755 */ MCD_OPC_CheckField, 12, 4, 15, 206, 8, // Skip to: 7015 >+/* 4761 */ MCD_OPC_Decode, 208, 19, 169, 2, // Opcode: t2SADD8 >+/* 4766 */ MCD_OPC_FilterValue, 1, 197, 8, // Skip to: 7015 >+/* 4770 */ MCD_OPC_CheckPredicate, 29, 193, 8, // Skip to: 7015 >+/* 4774 */ MCD_OPC_CheckField, 12, 4, 15, 187, 8, // Skip to: 7015 >+/* 4780 */ MCD_OPC_Decode, 207, 19, 169, 2, // Opcode: t2SADD16 >+/* 4785 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 4830 >+/* 4789 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4792 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4811 >+/* 4796 */ MCD_OPC_CheckPredicate, 29, 167, 8, // Skip to: 7015 >+/* 4800 */ MCD_OPC_CheckField, 12, 4, 15, 161, 8, // Skip to: 7015 >+/* 4806 */ MCD_OPC_Decode, 183, 19, 169, 2, // Opcode: t2QADD8 >+/* 4811 */ MCD_OPC_FilterValue, 1, 152, 8, // Skip to: 7015 >+/* 4815 */ MCD_OPC_CheckPredicate, 29, 148, 8, // Skip to: 7015 >+/* 4819 */ MCD_OPC_CheckField, 12, 4, 15, 142, 8, // Skip to: 7015 >+/* 4825 */ MCD_OPC_Decode, 182, 19, 169, 2, // Opcode: t2QADD16 >+/* 4830 */ MCD_OPC_FilterValue, 2, 41, 0, // Skip to: 4875 >+/* 4834 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4856 >+/* 4841 */ MCD_OPC_CheckPredicate, 29, 122, 8, // Skip to: 7015 >+/* 4845 */ MCD_OPC_CheckField, 12, 4, 15, 116, 8, // Skip to: 7015 >+/* 4851 */ MCD_OPC_Decode, 217, 19, 169, 2, // Opcode: t2SHADD8 >+/* 4856 */ MCD_OPC_FilterValue, 1, 107, 8, // Skip to: 7015 >+/* 4860 */ MCD_OPC_CheckPredicate, 29, 103, 8, // Skip to: 7015 >+/* 4864 */ MCD_OPC_CheckField, 12, 4, 15, 97, 8, // Skip to: 7015 >+/* 4870 */ MCD_OPC_Decode, 216, 19, 169, 2, // Opcode: t2SHADD16 >+/* 4875 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 4920 >+/* 4879 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4882 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4901 >+/* 4886 */ MCD_OPC_CheckPredicate, 29, 77, 8, // Skip to: 7015 >+/* 4890 */ MCD_OPC_CheckField, 12, 4, 15, 71, 8, // Skip to: 7015 >+/* 4896 */ MCD_OPC_Decode, 220, 20, 169, 2, // Opcode: t2UADD8 >+/* 4901 */ MCD_OPC_FilterValue, 1, 62, 8, // Skip to: 7015 >+/* 4905 */ MCD_OPC_CheckPredicate, 29, 58, 8, // Skip to: 7015 >+/* 4909 */ MCD_OPC_CheckField, 12, 4, 15, 52, 8, // Skip to: 7015 >+/* 4915 */ MCD_OPC_Decode, 219, 20, 169, 2, // Opcode: t2UADD16 >+/* 4920 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 4965 >+/* 4924 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4927 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4946 >+/* 4931 */ MCD_OPC_CheckPredicate, 29, 32, 8, // Skip to: 7015 >+/* 4935 */ MCD_OPC_CheckField, 12, 4, 15, 26, 8, // Skip to: 7015 >+/* 4941 */ MCD_OPC_Decode, 235, 20, 169, 2, // Opcode: t2UQADD8 >+/* 4946 */ MCD_OPC_FilterValue, 1, 17, 8, // Skip to: 7015 >+/* 4950 */ MCD_OPC_CheckPredicate, 29, 13, 8, // Skip to: 7015 >+/* 4954 */ MCD_OPC_CheckField, 12, 4, 15, 7, 8, // Skip to: 7015 >+/* 4960 */ MCD_OPC_Decode, 234, 20, 169, 2, // Opcode: t2UQADD16 >+/* 4965 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 5010 >+/* 4969 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4972 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 4991 >+/* 4976 */ MCD_OPC_CheckPredicate, 29, 243, 7, // Skip to: 7015 >+/* 4980 */ MCD_OPC_CheckField, 12, 4, 15, 237, 7, // Skip to: 7015 >+/* 4986 */ MCD_OPC_Decode, 226, 20, 169, 2, // Opcode: t2UHADD8 >+/* 4991 */ MCD_OPC_FilterValue, 1, 228, 7, // Skip to: 7015 >+/* 4995 */ MCD_OPC_CheckPredicate, 29, 224, 7, // Skip to: 7015 >+/* 4999 */ MCD_OPC_CheckField, 12, 4, 15, 218, 7, // Skip to: 7015 >+/* 5005 */ MCD_OPC_Decode, 225, 20, 169, 2, // Opcode: t2UHADD16 >+/* 5010 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 5055 >+/* 5014 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5017 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5036 >+/* 5021 */ MCD_OPC_CheckPredicate, 29, 198, 7, // Skip to: 7015 >+/* 5025 */ MCD_OPC_CheckField, 12, 4, 15, 192, 7, // Skip to: 7015 >+/* 5031 */ MCD_OPC_Decode, 181, 19, 170, 2, // Opcode: t2QADD >+/* 5036 */ MCD_OPC_FilterValue, 1, 183, 7, // Skip to: 7015 >+/* 5040 */ MCD_OPC_CheckPredicate, 22, 179, 7, // Skip to: 7015 >+/* 5044 */ MCD_OPC_CheckField, 12, 4, 15, 173, 7, // Skip to: 7015 >+/* 5050 */ MCD_OPC_Decode, 192, 19, 171, 2, // Opcode: t2REV >+/* 5055 */ MCD_OPC_FilterValue, 9, 41, 0, // Skip to: 5100 >+/* 5059 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5062 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5081 >+/* 5066 */ MCD_OPC_CheckPredicate, 29, 153, 7, // Skip to: 7015 >+/* 5070 */ MCD_OPC_CheckField, 12, 4, 15, 147, 7, // Skip to: 7015 >+/* 5076 */ MCD_OPC_Decode, 185, 19, 170, 2, // Opcode: t2QDADD >+/* 5081 */ MCD_OPC_FilterValue, 1, 138, 7, // Skip to: 7015 >+/* 5085 */ MCD_OPC_CheckPredicate, 22, 134, 7, // Skip to: 7015 >+/* 5089 */ MCD_OPC_CheckField, 12, 4, 15, 128, 7, // Skip to: 7015 >+/* 5095 */ MCD_OPC_Decode, 193, 19, 171, 2, // Opcode: t2REV16 >+/* 5100 */ MCD_OPC_FilterValue, 10, 41, 0, // Skip to: 5145 >+/* 5104 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5107 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5126 >+/* 5111 */ MCD_OPC_CheckPredicate, 29, 108, 7, // Skip to: 7015 >+/* 5115 */ MCD_OPC_CheckField, 12, 4, 15, 102, 7, // Skip to: 7015 >+/* 5121 */ MCD_OPC_Decode, 188, 19, 170, 2, // Opcode: t2QSUB >+/* 5126 */ MCD_OPC_FilterValue, 1, 93, 7, // Skip to: 7015 >+/* 5130 */ MCD_OPC_CheckPredicate, 22, 89, 7, // Skip to: 7015 >+/* 5134 */ MCD_OPC_CheckField, 12, 4, 15, 83, 7, // Skip to: 7015 >+/* 5140 */ MCD_OPC_Decode, 191, 19, 171, 2, // Opcode: t2RBIT >+/* 5145 */ MCD_OPC_FilterValue, 11, 74, 7, // Skip to: 7015 >+/* 5149 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5152 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5171 >+/* 5156 */ MCD_OPC_CheckPredicate, 29, 63, 7, // Skip to: 7015 >+/* 5160 */ MCD_OPC_CheckField, 12, 4, 15, 57, 7, // Skip to: 7015 >+/* 5166 */ MCD_OPC_Decode, 186, 19, 170, 2, // Opcode: t2QDSUB >+/* 5171 */ MCD_OPC_FilterValue, 1, 48, 7, // Skip to: 7015 >+/* 5175 */ MCD_OPC_CheckPredicate, 22, 44, 7, // Skip to: 7015 >+/* 5179 */ MCD_OPC_CheckField, 12, 4, 15, 38, 7, // Skip to: 7015 >+/* 5185 */ MCD_OPC_Decode, 194, 19, 171, 2, // Opcode: t2REVSH >+/* 5190 */ MCD_OPC_FilterValue, 5, 198, 0, // Skip to: 5392 >+/* 5194 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5197 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 5222 >+/* 5201 */ MCD_OPC_CheckPredicate, 29, 18, 7, // Skip to: 7015 >+/* 5205 */ MCD_OPC_CheckField, 20, 1, 0, 12, 7, // Skip to: 7015 >+/* 5211 */ MCD_OPC_CheckField, 12, 4, 15, 6, 7, // Skip to: 7015 >+/* 5217 */ MCD_OPC_Decode, 209, 19, 169, 2, // Opcode: t2SASX >+/* 5222 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 5247 >+/* 5226 */ MCD_OPC_CheckPredicate, 29, 249, 6, // Skip to: 7015 >+/* 5230 */ MCD_OPC_CheckField, 20, 1, 0, 243, 6, // Skip to: 7015 >+/* 5236 */ MCD_OPC_CheckField, 12, 4, 15, 237, 6, // Skip to: 7015 >+/* 5242 */ MCD_OPC_Decode, 184, 19, 169, 2, // Opcode: t2QASX >+/* 5247 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 5272 >+/* 5251 */ MCD_OPC_CheckPredicate, 29, 224, 6, // Skip to: 7015 >+/* 5255 */ MCD_OPC_CheckField, 20, 1, 0, 218, 6, // Skip to: 7015 >+/* 5261 */ MCD_OPC_CheckField, 12, 4, 15, 212, 6, // Skip to: 7015 >+/* 5267 */ MCD_OPC_Decode, 218, 19, 169, 2, // Opcode: t2SHASX >+/* 5272 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 5297 >+/* 5276 */ MCD_OPC_CheckPredicate, 29, 199, 6, // Skip to: 7015 >+/* 5280 */ MCD_OPC_CheckField, 20, 1, 0, 193, 6, // Skip to: 7015 >+/* 5286 */ MCD_OPC_CheckField, 12, 4, 15, 187, 6, // Skip to: 7015 >+/* 5292 */ MCD_OPC_Decode, 221, 20, 169, 2, // Opcode: t2UASX >+/* 5297 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 5322 >+/* 5301 */ MCD_OPC_CheckPredicate, 29, 174, 6, // Skip to: 7015 >+/* 5305 */ MCD_OPC_CheckField, 20, 1, 0, 168, 6, // Skip to: 7015 >+/* 5311 */ MCD_OPC_CheckField, 12, 4, 15, 162, 6, // Skip to: 7015 >+/* 5317 */ MCD_OPC_Decode, 236, 20, 169, 2, // Opcode: t2UQASX >+/* 5322 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 5347 >+/* 5326 */ MCD_OPC_CheckPredicate, 29, 149, 6, // Skip to: 7015 >+/* 5330 */ MCD_OPC_CheckField, 20, 1, 0, 143, 6, // Skip to: 7015 >+/* 5336 */ MCD_OPC_CheckField, 12, 4, 15, 137, 6, // Skip to: 7015 >+/* 5342 */ MCD_OPC_Decode, 227, 20, 169, 2, // Opcode: t2UHASX >+/* 5347 */ MCD_OPC_FilterValue, 8, 128, 6, // Skip to: 7015 >+/* 5351 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5354 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5373 >+/* 5358 */ MCD_OPC_CheckPredicate, 29, 117, 6, // Skip to: 7015 >+/* 5362 */ MCD_OPC_CheckField, 12, 4, 15, 111, 6, // Skip to: 7015 >+/* 5368 */ MCD_OPC_Decode, 215, 19, 172, 2, // Opcode: t2SEL >+/* 5373 */ MCD_OPC_FilterValue, 1, 102, 6, // Skip to: 7015 >+/* 5377 */ MCD_OPC_CheckPredicate, 22, 98, 6, // Skip to: 7015 >+/* 5381 */ MCD_OPC_CheckField, 12, 4, 15, 92, 6, // Skip to: 7015 >+/* 5387 */ MCD_OPC_Decode, 136, 18, 171, 2, // Opcode: t2CLZ >+/* 5392 */ MCD_OPC_FilterValue, 6, 152, 1, // Skip to: 5804 >+/* 5396 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5399 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 5444 >+/* 5403 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5406 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5425 >+/* 5410 */ MCD_OPC_CheckPredicate, 29, 65, 6, // Skip to: 7015 >+/* 5414 */ MCD_OPC_CheckField, 12, 4, 15, 59, 6, // Skip to: 7015 >+/* 5420 */ MCD_OPC_Decode, 139, 20, 169, 2, // Opcode: t2SSUB8 >+/* 5425 */ MCD_OPC_FilterValue, 1, 50, 6, // Skip to: 7015 >+/* 5429 */ MCD_OPC_CheckPredicate, 29, 46, 6, // Skip to: 7015 >+/* 5433 */ MCD_OPC_CheckField, 12, 4, 15, 40, 6, // Skip to: 7015 >+/* 5439 */ MCD_OPC_Decode, 138, 20, 169, 2, // Opcode: t2SSUB16 >+/* 5444 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 5489 >+/* 5448 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5451 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5470 >+/* 5455 */ MCD_OPC_CheckPredicate, 29, 20, 6, // Skip to: 7015 >+/* 5459 */ MCD_OPC_CheckField, 12, 4, 15, 14, 6, // Skip to: 7015 >+/* 5465 */ MCD_OPC_Decode, 190, 19, 169, 2, // Opcode: t2QSUB8 >+/* 5470 */ MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 7015 >+/* 5474 */ MCD_OPC_CheckPredicate, 29, 1, 6, // Skip to: 7015 >+/* 5478 */ MCD_OPC_CheckField, 12, 4, 15, 251, 5, // Skip to: 7015 >+/* 5484 */ MCD_OPC_Decode, 189, 19, 169, 2, // Opcode: t2QSUB16 >+/* 5489 */ MCD_OPC_FilterValue, 2, 41, 0, // Skip to: 5534 >+/* 5493 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5496 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5515 >+/* 5500 */ MCD_OPC_CheckPredicate, 29, 231, 5, // Skip to: 7015 >+/* 5504 */ MCD_OPC_CheckField, 12, 4, 15, 225, 5, // Skip to: 7015 >+/* 5510 */ MCD_OPC_Decode, 221, 19, 169, 2, // Opcode: t2SHSUB8 >+/* 5515 */ MCD_OPC_FilterValue, 1, 216, 5, // Skip to: 7015 >+/* 5519 */ MCD_OPC_CheckPredicate, 29, 212, 5, // Skip to: 7015 >+/* 5523 */ MCD_OPC_CheckField, 12, 4, 15, 206, 5, // Skip to: 7015 >+/* 5529 */ MCD_OPC_Decode, 220, 19, 169, 2, // Opcode: t2SHSUB16 >+/* 5534 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 5579 >+/* 5538 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5541 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5560 >+/* 5545 */ MCD_OPC_CheckPredicate, 29, 186, 5, // Skip to: 7015 >+/* 5549 */ MCD_OPC_CheckField, 12, 4, 15, 180, 5, // Skip to: 7015 >+/* 5555 */ MCD_OPC_Decode, 246, 20, 169, 2, // Opcode: t2USUB8 >+/* 5560 */ MCD_OPC_FilterValue, 1, 171, 5, // Skip to: 7015 >+/* 5564 */ MCD_OPC_CheckPredicate, 29, 167, 5, // Skip to: 7015 >+/* 5568 */ MCD_OPC_CheckField, 12, 4, 15, 161, 5, // Skip to: 7015 >+/* 5574 */ MCD_OPC_Decode, 245, 20, 169, 2, // Opcode: t2USUB16 >+/* 5579 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 5624 >+/* 5583 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5586 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5605 >+/* 5590 */ MCD_OPC_CheckPredicate, 29, 141, 5, // Skip to: 7015 >+/* 5594 */ MCD_OPC_CheckField, 12, 4, 15, 135, 5, // Skip to: 7015 >+/* 5600 */ MCD_OPC_Decode, 239, 20, 169, 2, // Opcode: t2UQSUB8 >+/* 5605 */ MCD_OPC_FilterValue, 1, 126, 5, // Skip to: 7015 >+/* 5609 */ MCD_OPC_CheckPredicate, 29, 122, 5, // Skip to: 7015 >+/* 5613 */ MCD_OPC_CheckField, 12, 4, 15, 116, 5, // Skip to: 7015 >+/* 5619 */ MCD_OPC_Decode, 238, 20, 169, 2, // Opcode: t2UQSUB16 >+/* 5624 */ MCD_OPC_FilterValue, 6, 41, 0, // Skip to: 5669 >+/* 5628 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5631 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5650 >+/* 5635 */ MCD_OPC_CheckPredicate, 29, 96, 5, // Skip to: 7015 >+/* 5639 */ MCD_OPC_CheckField, 12, 4, 15, 90, 5, // Skip to: 7015 >+/* 5645 */ MCD_OPC_Decode, 230, 20, 169, 2, // Opcode: t2UHSUB8 >+/* 5650 */ MCD_OPC_FilterValue, 1, 81, 5, // Skip to: 7015 >+/* 5654 */ MCD_OPC_CheckPredicate, 29, 77, 5, // Skip to: 7015 >+/* 5658 */ MCD_OPC_CheckField, 12, 4, 15, 71, 5, // Skip to: 7015 >+/* 5664 */ MCD_OPC_Decode, 229, 20, 169, 2, // Opcode: t2UHSUB16 >+/* 5669 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 5714 >+/* 5673 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5676 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5695 >+/* 5680 */ MCD_OPC_CheckPredicate, 38, 51, 5, // Skip to: 7015 >+/* 5684 */ MCD_OPC_CheckField, 12, 4, 15, 45, 5, // Skip to: 7015 >+/* 5690 */ MCD_OPC_Decode, 146, 18, 169, 2, // Opcode: t2CRC32B >+/* 5695 */ MCD_OPC_FilterValue, 1, 36, 5, // Skip to: 7015 >+/* 5699 */ MCD_OPC_CheckPredicate, 38, 32, 5, // Skip to: 7015 >+/* 5703 */ MCD_OPC_CheckField, 12, 4, 15, 26, 5, // Skip to: 7015 >+/* 5709 */ MCD_OPC_Decode, 147, 18, 169, 2, // Opcode: t2CRC32CB >+/* 5714 */ MCD_OPC_FilterValue, 9, 41, 0, // Skip to: 5759 >+/* 5718 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5721 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5740 >+/* 5725 */ MCD_OPC_CheckPredicate, 38, 6, 5, // Skip to: 7015 >+/* 5729 */ MCD_OPC_CheckField, 12, 4, 15, 0, 5, // Skip to: 7015 >+/* 5735 */ MCD_OPC_Decode, 150, 18, 169, 2, // Opcode: t2CRC32H >+/* 5740 */ MCD_OPC_FilterValue, 1, 247, 4, // Skip to: 7015 >+/* 5744 */ MCD_OPC_CheckPredicate, 38, 243, 4, // Skip to: 7015 >+/* 5748 */ MCD_OPC_CheckField, 12, 4, 15, 237, 4, // Skip to: 7015 >+/* 5754 */ MCD_OPC_Decode, 148, 18, 169, 2, // Opcode: t2CRC32CH >+/* 5759 */ MCD_OPC_FilterValue, 10, 228, 4, // Skip to: 7015 >+/* 5763 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5766 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 5785 >+/* 5770 */ MCD_OPC_CheckPredicate, 38, 217, 4, // Skip to: 7015 >+/* 5774 */ MCD_OPC_CheckField, 12, 4, 15, 211, 4, // Skip to: 7015 >+/* 5780 */ MCD_OPC_Decode, 151, 18, 169, 2, // Opcode: t2CRC32W >+/* 5785 */ MCD_OPC_FilterValue, 1, 202, 4, // Skip to: 7015 >+/* 5789 */ MCD_OPC_CheckPredicate, 38, 198, 4, // Skip to: 7015 >+/* 5793 */ MCD_OPC_CheckField, 12, 4, 15, 192, 4, // Skip to: 7015 >+/* 5799 */ MCD_OPC_Decode, 149, 18, 169, 2, // Opcode: t2CRC32CW >+/* 5804 */ MCD_OPC_FilterValue, 7, 183, 4, // Skip to: 7015 >+/* 5808 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5811 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 5836 >+/* 5815 */ MCD_OPC_CheckPredicate, 29, 172, 4, // Skip to: 7015 >+/* 5819 */ MCD_OPC_CheckField, 20, 1, 0, 166, 4, // Skip to: 7015 >+/* 5825 */ MCD_OPC_CheckField, 12, 4, 15, 160, 4, // Skip to: 7015 >+/* 5831 */ MCD_OPC_Decode, 137, 20, 169, 2, // Opcode: t2SSAX >+/* 5836 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 5861 >+/* 5840 */ MCD_OPC_CheckPredicate, 29, 147, 4, // Skip to: 7015 >+/* 5844 */ MCD_OPC_CheckField, 20, 1, 0, 141, 4, // Skip to: 7015 >+/* 5850 */ MCD_OPC_CheckField, 12, 4, 15, 135, 4, // Skip to: 7015 >+/* 5856 */ MCD_OPC_Decode, 187, 19, 169, 2, // Opcode: t2QSAX >+/* 5861 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 5886 >+/* 5865 */ MCD_OPC_CheckPredicate, 29, 122, 4, // Skip to: 7015 >+/* 5869 */ MCD_OPC_CheckField, 20, 1, 0, 116, 4, // Skip to: 7015 >+/* 5875 */ MCD_OPC_CheckField, 12, 4, 15, 110, 4, // Skip to: 7015 >+/* 5881 */ MCD_OPC_Decode, 219, 19, 169, 2, // Opcode: t2SHSAX >+/* 5886 */ MCD_OPC_FilterValue, 4, 21, 0, // Skip to: 5911 >+/* 5890 */ MCD_OPC_CheckPredicate, 29, 97, 4, // Skip to: 7015 >+/* 5894 */ MCD_OPC_CheckField, 20, 1, 0, 91, 4, // Skip to: 7015 >+/* 5900 */ MCD_OPC_CheckField, 12, 4, 15, 85, 4, // Skip to: 7015 >+/* 5906 */ MCD_OPC_Decode, 244, 20, 169, 2, // Opcode: t2USAX >+/* 5911 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 5936 >+/* 5915 */ MCD_OPC_CheckPredicate, 29, 72, 4, // Skip to: 7015 >+/* 5919 */ MCD_OPC_CheckField, 20, 1, 0, 66, 4, // Skip to: 7015 >+/* 5925 */ MCD_OPC_CheckField, 12, 4, 15, 60, 4, // Skip to: 7015 >+/* 5931 */ MCD_OPC_Decode, 237, 20, 169, 2, // Opcode: t2UQSAX >+/* 5936 */ MCD_OPC_FilterValue, 6, 51, 4, // Skip to: 7015 >+/* 5940 */ MCD_OPC_CheckPredicate, 29, 47, 4, // Skip to: 7015 >+/* 5944 */ MCD_OPC_CheckField, 20, 1, 0, 41, 4, // Skip to: 7015 >+/* 5950 */ MCD_OPC_CheckField, 12, 4, 15, 35, 4, // Skip to: 7015 >+/* 5956 */ MCD_OPC_Decode, 228, 20, 169, 2, // Opcode: t2UHSAX >+/* 5961 */ MCD_OPC_FilterValue, 3, 230, 2, // Skip to: 6707 >+/* 5965 */ MCD_OPC_ExtractField, 20, 4, // Inst{23-20} ... >+/* 5968 */ MCD_OPC_FilterValue, 0, 44, 0, // Skip to: 6016 >+/* 5972 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 5975 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6003 >+/* 5979 */ MCD_OPC_CheckPredicate, 22, 11, 0, // Skip to: 5994 >+/* 5983 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 5994 >+/* 5989 */ MCD_OPC_Decode, 157, 19, 169, 2, // Opcode: t2MUL >+/* 5994 */ MCD_OPC_CheckPredicate, 22, 249, 3, // Skip to: 7015 >+/* 5998 */ MCD_OPC_Decode, 252, 18, 173, 2, // Opcode: t2MLA >+/* 6003 */ MCD_OPC_FilterValue, 1, 240, 3, // Skip to: 7015 >+/* 6007 */ MCD_OPC_CheckPredicate, 22, 236, 3, // Skip to: 7015 >+/* 6011 */ MCD_OPC_Decode, 253, 18, 173, 2, // Opcode: t2MLS >+/* 6016 */ MCD_OPC_FilterValue, 1, 115, 0, // Skip to: 6135 >+/* 6020 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6023 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6051 >+/* 6027 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6042 >+/* 6031 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6042 >+/* 6037 */ MCD_OPC_Decode, 250, 19, 169, 2, // Opcode: t2SMULBB >+/* 6042 */ MCD_OPC_CheckPredicate, 29, 201, 3, // Skip to: 7015 >+/* 6046 */ MCD_OPC_Decode, 223, 19, 173, 2, // Opcode: t2SMLABB >+/* 6051 */ MCD_OPC_FilterValue, 1, 24, 0, // Skip to: 6079 >+/* 6055 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6070 >+/* 6059 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6070 >+/* 6065 */ MCD_OPC_Decode, 251, 19, 169, 2, // Opcode: t2SMULBT >+/* 6070 */ MCD_OPC_CheckPredicate, 29, 173, 3, // Skip to: 7015 >+/* 6074 */ MCD_OPC_Decode, 224, 19, 173, 2, // Opcode: t2SMLABT >+/* 6079 */ MCD_OPC_FilterValue, 2, 24, 0, // Skip to: 6107 >+/* 6083 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6098 >+/* 6087 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6098 >+/* 6093 */ MCD_OPC_Decode, 253, 19, 169, 2, // Opcode: t2SMULTB >+/* 6098 */ MCD_OPC_CheckPredicate, 29, 145, 3, // Skip to: 7015 >+/* 6102 */ MCD_OPC_Decode, 234, 19, 173, 2, // Opcode: t2SMLATB >+/* 6107 */ MCD_OPC_FilterValue, 3, 136, 3, // Skip to: 7015 >+/* 6111 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6126 >+/* 6115 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6126 >+/* 6121 */ MCD_OPC_Decode, 254, 19, 169, 2, // Opcode: t2SMULTT >+/* 6126 */ MCD_OPC_CheckPredicate, 29, 117, 3, // Skip to: 7015 >+/* 6130 */ MCD_OPC_Decode, 235, 19, 173, 2, // Opcode: t2SMLATT >+/* 6135 */ MCD_OPC_FilterValue, 2, 59, 0, // Skip to: 6198 >+/* 6139 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6142 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6170 >+/* 6146 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6161 >+/* 6150 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6161 >+/* 6156 */ MCD_OPC_Decode, 248, 19, 169, 2, // Opcode: t2SMUAD >+/* 6161 */ MCD_OPC_CheckPredicate, 29, 82, 3, // Skip to: 7015 >+/* 6165 */ MCD_OPC_Decode, 225, 19, 173, 2, // Opcode: t2SMLAD >+/* 6170 */ MCD_OPC_FilterValue, 1, 73, 3, // Skip to: 7015 >+/* 6174 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6189 >+/* 6178 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6189 >+/* 6184 */ MCD_OPC_Decode, 249, 19, 169, 2, // Opcode: t2SMUADX >+/* 6189 */ MCD_OPC_CheckPredicate, 29, 54, 3, // Skip to: 7015 >+/* 6193 */ MCD_OPC_Decode, 226, 19, 173, 2, // Opcode: t2SMLADX >+/* 6198 */ MCD_OPC_FilterValue, 3, 59, 0, // Skip to: 6261 >+/* 6202 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6205 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6233 >+/* 6209 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6224 >+/* 6213 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6224 >+/* 6219 */ MCD_OPC_Decode, 255, 19, 169, 2, // Opcode: t2SMULWB >+/* 6224 */ MCD_OPC_CheckPredicate, 29, 19, 3, // Skip to: 7015 >+/* 6228 */ MCD_OPC_Decode, 236, 19, 173, 2, // Opcode: t2SMLAWB >+/* 6233 */ MCD_OPC_FilterValue, 1, 10, 3, // Skip to: 7015 >+/* 6237 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6252 >+/* 6241 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6252 >+/* 6247 */ MCD_OPC_Decode, 128, 20, 169, 2, // Opcode: t2SMULWT >+/* 6252 */ MCD_OPC_CheckPredicate, 29, 247, 2, // Skip to: 7015 >+/* 6256 */ MCD_OPC_Decode, 237, 19, 173, 2, // Opcode: t2SMLAWT >+/* 6261 */ MCD_OPC_FilterValue, 4, 59, 0, // Skip to: 6324 >+/* 6265 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6268 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6296 >+/* 6272 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6287 >+/* 6276 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6287 >+/* 6282 */ MCD_OPC_Decode, 129, 20, 169, 2, // Opcode: t2SMUSD >+/* 6287 */ MCD_OPC_CheckPredicate, 29, 212, 2, // Skip to: 7015 >+/* 6291 */ MCD_OPC_Decode, 238, 19, 173, 2, // Opcode: t2SMLSD >+/* 6296 */ MCD_OPC_FilterValue, 1, 203, 2, // Skip to: 7015 >+/* 6300 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6315 >+/* 6304 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6315 >+/* 6310 */ MCD_OPC_Decode, 130, 20, 169, 2, // Opcode: t2SMUSDX >+/* 6315 */ MCD_OPC_CheckPredicate, 29, 184, 2, // Skip to: 7015 >+/* 6319 */ MCD_OPC_Decode, 239, 19, 173, 2, // Opcode: t2SMLSDX >+/* 6324 */ MCD_OPC_FilterValue, 5, 59, 0, // Skip to: 6387 >+/* 6328 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6331 */ MCD_OPC_FilterValue, 0, 24, 0, // Skip to: 6359 >+/* 6335 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6350 >+/* 6339 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6350 >+/* 6345 */ MCD_OPC_Decode, 246, 19, 169, 2, // Opcode: t2SMMUL >+/* 6350 */ MCD_OPC_CheckPredicate, 29, 149, 2, // Skip to: 7015 >+/* 6354 */ MCD_OPC_Decode, 242, 19, 173, 2, // Opcode: t2SMMLA >+/* 6359 */ MCD_OPC_FilterValue, 1, 140, 2, // Skip to: 7015 >+/* 6363 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6378 >+/* 6367 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6378 >+/* 6373 */ MCD_OPC_Decode, 247, 19, 169, 2, // Opcode: t2SMMULR >+/* 6378 */ MCD_OPC_CheckPredicate, 29, 121, 2, // Skip to: 7015 >+/* 6382 */ MCD_OPC_Decode, 243, 19, 173, 2, // Opcode: t2SMMLAR >+/* 6387 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 6420 >+/* 6391 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6394 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6407 >+/* 6398 */ MCD_OPC_CheckPredicate, 29, 101, 2, // Skip to: 7015 >+/* 6402 */ MCD_OPC_Decode, 244, 19, 173, 2, // Opcode: t2SMMLS >+/* 6407 */ MCD_OPC_FilterValue, 1, 92, 2, // Skip to: 7015 >+/* 6411 */ MCD_OPC_CheckPredicate, 29, 88, 2, // Skip to: 7015 >+/* 6415 */ MCD_OPC_Decode, 245, 19, 173, 2, // Opcode: t2SMMLSR >+/* 6420 */ MCD_OPC_FilterValue, 7, 31, 0, // Skip to: 6455 >+/* 6424 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6427 */ MCD_OPC_FilterValue, 0, 72, 2, // Skip to: 7015 >+/* 6431 */ MCD_OPC_CheckPredicate, 29, 11, 0, // Skip to: 6446 >+/* 6435 */ MCD_OPC_CheckField, 12, 4, 15, 5, 0, // Skip to: 6446 >+/* 6441 */ MCD_OPC_Decode, 240, 20, 169, 2, // Opcode: t2USAD8 >+/* 6446 */ MCD_OPC_CheckPredicate, 29, 53, 2, // Skip to: 7015 >+/* 6450 */ MCD_OPC_Decode, 241, 20, 173, 2, // Opcode: t2USADA8 >+/* 6455 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 6474 >+/* 6459 */ MCD_OPC_CheckPredicate, 22, 40, 2, // Skip to: 7015 >+/* 6463 */ MCD_OPC_CheckField, 4, 4, 0, 34, 2, // Skip to: 7015 >+/* 6469 */ MCD_OPC_Decode, 252, 19, 174, 2, // Opcode: t2SMULL >+/* 6474 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 6499 >+/* 6478 */ MCD_OPC_CheckPredicate, 39, 21, 2, // Skip to: 7015 >+/* 6482 */ MCD_OPC_CheckField, 12, 4, 15, 15, 2, // Skip to: 7015 >+/* 6488 */ MCD_OPC_CheckField, 4, 4, 15, 9, 2, // Skip to: 7015 >+/* 6494 */ MCD_OPC_Decode, 214, 19, 169, 2, // Opcode: t2SDIV >+/* 6499 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 6518 >+/* 6503 */ MCD_OPC_CheckPredicate, 22, 252, 1, // Skip to: 7015 >+/* 6507 */ MCD_OPC_CheckField, 4, 4, 0, 246, 1, // Skip to: 7015 >+/* 6513 */ MCD_OPC_Decode, 233, 20, 174, 2, // Opcode: t2UMULL >+/* 6518 */ MCD_OPC_FilterValue, 11, 21, 0, // Skip to: 6543 >+/* 6522 */ MCD_OPC_CheckPredicate, 39, 233, 1, // Skip to: 7015 >+/* 6526 */ MCD_OPC_CheckField, 12, 4, 15, 227, 1, // Skip to: 7015 >+/* 6532 */ MCD_OPC_CheckField, 4, 4, 15, 221, 1, // Skip to: 7015 >+/* 6538 */ MCD_OPC_Decode, 224, 20, 169, 2, // Opcode: t2UDIV >+/* 6543 */ MCD_OPC_FilterValue, 12, 94, 0, // Skip to: 6641 >+/* 6547 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6550 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6563 >+/* 6554 */ MCD_OPC_CheckPredicate, 22, 201, 1, // Skip to: 7015 >+/* 6558 */ MCD_OPC_Decode, 227, 19, 175, 2, // Opcode: t2SMLAL >+/* 6563 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 6576 >+/* 6567 */ MCD_OPC_CheckPredicate, 29, 188, 1, // Skip to: 7015 >+/* 6571 */ MCD_OPC_Decode, 228, 19, 174, 2, // Opcode: t2SMLALBB >+/* 6576 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 6589 >+/* 6580 */ MCD_OPC_CheckPredicate, 29, 175, 1, // Skip to: 7015 >+/* 6584 */ MCD_OPC_Decode, 229, 19, 174, 2, // Opcode: t2SMLALBT >+/* 6589 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 6602 >+/* 6593 */ MCD_OPC_CheckPredicate, 29, 162, 1, // Skip to: 7015 >+/* 6597 */ MCD_OPC_Decode, 232, 19, 174, 2, // Opcode: t2SMLALTB >+/* 6602 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 6615 >+/* 6606 */ MCD_OPC_CheckPredicate, 29, 149, 1, // Skip to: 7015 >+/* 6610 */ MCD_OPC_Decode, 233, 19, 174, 2, // Opcode: t2SMLALTT >+/* 6615 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6628 >+/* 6619 */ MCD_OPC_CheckPredicate, 29, 136, 1, // Skip to: 7015 >+/* 6623 */ MCD_OPC_Decode, 230, 19, 174, 2, // Opcode: t2SMLALD >+/* 6628 */ MCD_OPC_FilterValue, 13, 127, 1, // Skip to: 7015 >+/* 6632 */ MCD_OPC_CheckPredicate, 29, 123, 1, // Skip to: 7015 >+/* 6636 */ MCD_OPC_Decode, 231, 19, 174, 2, // Opcode: t2SMLALDX >+/* 6641 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 6674 >+/* 6645 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6648 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 6661 >+/* 6652 */ MCD_OPC_CheckPredicate, 29, 103, 1, // Skip to: 7015 >+/* 6656 */ MCD_OPC_Decode, 240, 19, 174, 2, // Opcode: t2SMLSLD >+/* 6661 */ MCD_OPC_FilterValue, 13, 94, 1, // Skip to: 7015 >+/* 6665 */ MCD_OPC_CheckPredicate, 29, 90, 1, // Skip to: 7015 >+/* 6669 */ MCD_OPC_Decode, 241, 19, 176, 2, // Opcode: t2SMLSLDX >+/* 6674 */ MCD_OPC_FilterValue, 14, 81, 1, // Skip to: 7015 >+/* 6678 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ... >+/* 6681 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6694 >+/* 6685 */ MCD_OPC_CheckPredicate, 22, 70, 1, // Skip to: 7015 >+/* 6689 */ MCD_OPC_Decode, 232, 20, 175, 2, // Opcode: t2UMLAL >+/* 6694 */ MCD_OPC_FilterValue, 6, 61, 1, // Skip to: 7015 >+/* 6698 */ MCD_OPC_CheckPredicate, 29, 57, 1, // Skip to: 7015 >+/* 6702 */ MCD_OPC_Decode, 231, 20, 174, 2, // Opcode: t2UMAAL >+/* 6707 */ MCD_OPC_FilterValue, 4, 151, 0, // Skip to: 6862 >+/* 6711 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 6714 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6732 >+/* 6718 */ MCD_OPC_CheckPredicate, 40, 37, 1, // Skip to: 7015 >+/* 6722 */ MCD_OPC_CheckField, 23, 1, 1, 31, 1, // Skip to: 7015 >+/* 6728 */ MCD_OPC_Decode, 145, 20, 84, // Opcode: t2STC2_OPTION >+/* 6732 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 6750 >+/* 6736 */ MCD_OPC_CheckPredicate, 40, 19, 1, // Skip to: 7015 >+/* 6740 */ MCD_OPC_CheckField, 23, 1, 1, 13, 1, // Skip to: 7015 >+/* 6746 */ MCD_OPC_Decode, 178, 18, 84, // Opcode: t2LDC2_OPTION >+/* 6750 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6762 >+/* 6754 */ MCD_OPC_CheckPredicate, 40, 1, 1, // Skip to: 7015 >+/* 6758 */ MCD_OPC_Decode, 146, 20, 84, // Opcode: t2STC2_POST >+/* 6762 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6774 >+/* 6766 */ MCD_OPC_CheckPredicate, 40, 245, 0, // Skip to: 7015 >+/* 6770 */ MCD_OPC_Decode, 179, 18, 84, // Opcode: t2LDC2_POST >+/* 6774 */ MCD_OPC_FilterValue, 4, 28, 0, // Skip to: 6806 >+/* 6778 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 6781 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6794 >+/* 6785 */ MCD_OPC_CheckPredicate, 28, 226, 0, // Skip to: 7015 >+/* 6789 */ MCD_OPC_Decode, 251, 18, 130, 2, // Opcode: t2MCRR2 >+/* 6794 */ MCD_OPC_FilterValue, 1, 217, 0, // Skip to: 7015 >+/* 6798 */ MCD_OPC_CheckPredicate, 40, 213, 0, // Skip to: 7015 >+/* 6802 */ MCD_OPC_Decode, 141, 20, 84, // Opcode: t2STC2L_OPTION >+/* 6806 */ MCD_OPC_FilterValue, 5, 28, 0, // Skip to: 6838 >+/* 6810 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 6813 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 6826 >+/* 6817 */ MCD_OPC_CheckPredicate, 28, 194, 0, // Skip to: 7015 >+/* 6821 */ MCD_OPC_Decode, 151, 19, 130, 2, // Opcode: t2MRRC2 >+/* 6826 */ MCD_OPC_FilterValue, 1, 185, 0, // Skip to: 7015 >+/* 6830 */ MCD_OPC_CheckPredicate, 40, 181, 0, // Skip to: 7015 >+/* 6834 */ MCD_OPC_Decode, 174, 18, 84, // Opcode: t2LDC2L_OPTION >+/* 6838 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6850 >+/* 6842 */ MCD_OPC_CheckPredicate, 40, 169, 0, // Skip to: 7015 >+/* 6846 */ MCD_OPC_Decode, 142, 20, 84, // Opcode: t2STC2L_POST >+/* 6850 */ MCD_OPC_FilterValue, 7, 161, 0, // Skip to: 7015 >+/* 6854 */ MCD_OPC_CheckPredicate, 40, 157, 0, // Skip to: 7015 >+/* 6858 */ MCD_OPC_Decode, 175, 18, 84, // Opcode: t2LDC2L_POST >+/* 6862 */ MCD_OPC_FilterValue, 5, 99, 0, // Skip to: 6965 >+/* 6866 */ MCD_OPC_ExtractField, 20, 3, // Inst{22-20} ... >+/* 6869 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6881 >+/* 6873 */ MCD_OPC_CheckPredicate, 40, 138, 0, // Skip to: 7015 >+/* 6877 */ MCD_OPC_Decode, 144, 20, 84, // Opcode: t2STC2_OFFSET >+/* 6881 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6893 >+/* 6885 */ MCD_OPC_CheckPredicate, 40, 126, 0, // Skip to: 7015 >+/* 6889 */ MCD_OPC_Decode, 177, 18, 84, // Opcode: t2LDC2_OFFSET >+/* 6893 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6905 >+/* 6897 */ MCD_OPC_CheckPredicate, 40, 114, 0, // Skip to: 7015 >+/* 6901 */ MCD_OPC_Decode, 147, 20, 84, // Opcode: t2STC2_PRE >+/* 6905 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6917 >+/* 6909 */ MCD_OPC_CheckPredicate, 40, 102, 0, // Skip to: 7015 >+/* 6913 */ MCD_OPC_Decode, 180, 18, 84, // Opcode: t2LDC2_PRE >+/* 6917 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6929 >+/* 6921 */ MCD_OPC_CheckPredicate, 40, 90, 0, // Skip to: 7015 >+/* 6925 */ MCD_OPC_Decode, 140, 20, 84, // Opcode: t2STC2L_OFFSET >+/* 6929 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6941 >+/* 6933 */ MCD_OPC_CheckPredicate, 40, 78, 0, // Skip to: 7015 >+/* 6937 */ MCD_OPC_Decode, 173, 18, 84, // Opcode: t2LDC2L_OFFSET >+/* 6941 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6953 >+/* 6945 */ MCD_OPC_CheckPredicate, 40, 66, 0, // Skip to: 7015 >+/* 6949 */ MCD_OPC_Decode, 143, 20, 84, // Opcode: t2STC2L_PRE >+/* 6953 */ MCD_OPC_FilterValue, 7, 58, 0, // Skip to: 7015 >+/* 6957 */ MCD_OPC_CheckPredicate, 40, 54, 0, // Skip to: 7015 >+/* 6961 */ MCD_OPC_Decode, 176, 18, 84, // Opcode: t2LDC2L_PRE >+/* 6965 */ MCD_OPC_FilterValue, 6, 46, 0, // Skip to: 7015 >+/* 6969 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 6972 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6984 >+/* 6976 */ MCD_OPC_CheckPredicate, 28, 35, 0, // Skip to: 7015 >+/* 6980 */ MCD_OPC_Decode, 134, 18, 87, // Opcode: t2CDP2 >+/* 6984 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 7015 >+/* 6988 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 6991 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7003 >+/* 6995 */ MCD_OPC_CheckPredicate, 28, 16, 0, // Skip to: 7015 >+/* 6999 */ MCD_OPC_Decode, 249, 18, 89, // Opcode: t2MCR2 >+/* 7003 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7015 >+/* 7007 */ MCD_OPC_CheckPredicate, 28, 4, 0, // Skip to: 7015 >+/* 7011 */ MCD_OPC_Decode, 149, 19, 91, // Opcode: t2MRC2 >+/* 7015 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableThumbSBit16[] = { >+/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 16 >+/* 7 */ MCD_OPC_CheckPredicate, 19, 49, 1, // Skip to: 316 >+/* 11 */ MCD_OPC_Decode, 183, 21, 177, 2, // Opcode: tLSLri >+/* 16 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 29 >+/* 20 */ MCD_OPC_CheckPredicate, 19, 36, 1, // Skip to: 316 >+/* 24 */ MCD_OPC_Decode, 185, 21, 177, 2, // Opcode: tLSRri >+/* 29 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 42 >+/* 33 */ MCD_OPC_CheckPredicate, 19, 23, 1, // Skip to: 316 >+/* 37 */ MCD_OPC_Decode, 138, 21, 177, 2, // Opcode: tASRri >+/* 42 */ MCD_OPC_FilterValue, 3, 55, 0, // Skip to: 101 >+/* 46 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 49 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 62 >+/* 53 */ MCD_OPC_CheckPredicate, 19, 3, 1, // Skip to: 316 >+/* 57 */ MCD_OPC_Decode, 131, 21, 178, 2, // Opcode: tADDrr >+/* 62 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 75 >+/* 66 */ MCD_OPC_CheckPredicate, 19, 246, 0, // Skip to: 316 >+/* 70 */ MCD_OPC_Decode, 215, 21, 178, 2, // Opcode: tSUBrr >+/* 75 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 88 >+/* 79 */ MCD_OPC_CheckPredicate, 19, 233, 0, // Skip to: 316 >+/* 83 */ MCD_OPC_Decode, 255, 20, 179, 2, // Opcode: tADDi3 >+/* 88 */ MCD_OPC_FilterValue, 3, 224, 0, // Skip to: 316 >+/* 92 */ MCD_OPC_CheckPredicate, 19, 220, 0, // Skip to: 316 >+/* 96 */ MCD_OPC_Decode, 213, 21, 179, 2, // Opcode: tSUBi3 >+/* 101 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 114 >+/* 105 */ MCD_OPC_CheckPredicate, 19, 207, 0, // Skip to: 316 >+/* 109 */ MCD_OPC_Decode, 189, 21, 205, 1, // Opcode: tMOVi8 >+/* 114 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 127 >+/* 118 */ MCD_OPC_CheckPredicate, 19, 194, 0, // Skip to: 316 >+/* 122 */ MCD_OPC_Decode, 128, 21, 180, 2, // Opcode: tADDi8 >+/* 127 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 140 >+/* 131 */ MCD_OPC_CheckPredicate, 19, 181, 0, // Skip to: 316 >+/* 135 */ MCD_OPC_Decode, 214, 21, 180, 2, // Opcode: tSUBi8 >+/* 140 */ MCD_OPC_FilterValue, 8, 172, 0, // Skip to: 316 >+/* 144 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 147 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 160 >+/* 151 */ MCD_OPC_CheckPredicate, 19, 161, 0, // Skip to: 316 >+/* 155 */ MCD_OPC_Decode, 137, 21, 181, 2, // Opcode: tAND >+/* 160 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 173 >+/* 164 */ MCD_OPC_CheckPredicate, 19, 148, 0, // Skip to: 316 >+/* 168 */ MCD_OPC_Decode, 161, 21, 181, 2, // Opcode: tEOR >+/* 173 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 186 >+/* 177 */ MCD_OPC_CheckPredicate, 19, 135, 0, // Skip to: 316 >+/* 181 */ MCD_OPC_Decode, 184, 21, 181, 2, // Opcode: tLSLrr >+/* 186 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 199 >+/* 190 */ MCD_OPC_CheckPredicate, 19, 122, 0, // Skip to: 316 >+/* 194 */ MCD_OPC_Decode, 186, 21, 181, 2, // Opcode: tLSRrr >+/* 199 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 212 >+/* 203 */ MCD_OPC_CheckPredicate, 19, 109, 0, // Skip to: 316 >+/* 207 */ MCD_OPC_Decode, 139, 21, 181, 2, // Opcode: tASRrr >+/* 212 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 225 >+/* 216 */ MCD_OPC_CheckPredicate, 19, 96, 0, // Skip to: 316 >+/* 220 */ MCD_OPC_Decode, 253, 20, 181, 2, // Opcode: tADC >+/* 225 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 238 >+/* 229 */ MCD_OPC_CheckPredicate, 19, 83, 0, // Skip to: 316 >+/* 233 */ MCD_OPC_Decode, 203, 21, 181, 2, // Opcode: tSBC >+/* 238 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 19, 70, 0, // Skip to: 316 >+/* 246 */ MCD_OPC_Decode, 201, 21, 181, 2, // Opcode: tROR >+/* 251 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 264 >+/* 255 */ MCD_OPC_CheckPredicate, 19, 57, 0, // Skip to: 316 >+/* 259 */ MCD_OPC_Decode, 202, 21, 204, 1, // Opcode: tRSB >+/* 264 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 277 >+/* 268 */ MCD_OPC_CheckPredicate, 19, 44, 0, // Skip to: 316 >+/* 272 */ MCD_OPC_Decode, 193, 21, 181, 2, // Opcode: tORR >+/* 277 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 290 >+/* 281 */ MCD_OPC_CheckPredicate, 19, 31, 0, // Skip to: 316 >+/* 285 */ MCD_OPC_Decode, 191, 21, 182, 2, // Opcode: tMUL >+/* 290 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 303 >+/* 294 */ MCD_OPC_CheckPredicate, 19, 18, 0, // Skip to: 316 >+/* 298 */ MCD_OPC_Decode, 141, 21, 181, 2, // Opcode: tBIC >+/* 303 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 316 >+/* 307 */ MCD_OPC_CheckPredicate, 19, 5, 0, // Skip to: 316 >+/* 311 */ MCD_OPC_Decode, 192, 21, 204, 1, // Opcode: tMVN >+/* 316 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableVFP32[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 83, 1, // Skip to: 346 >+/* 7 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... >+/* 10 */ MCD_OPC_FilterValue, 12, 130, 0, // Skip to: 144 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 10, 47, 0, // Skip to: 68 >+/* 21 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 24 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 55 >+/* 28 */ MCD_OPC_CheckPredicate, 41, 211, 10, // Skip to: 2803 >+/* 32 */ MCD_OPC_CheckField, 22, 1, 1, 205, 10, // Skip to: 2803 >+/* 38 */ MCD_OPC_CheckField, 6, 2, 0, 199, 10, // Skip to: 2803 >+/* 44 */ MCD_OPC_CheckField, 4, 1, 1, 193, 10, // Skip to: 2803 >+/* 50 */ MCD_OPC_Decode, 210, 10, 183, 2, // Opcode: VMOVSRR >+/* 55 */ MCD_OPC_FilterValue, 1, 184, 10, // Skip to: 2803 >+/* 59 */ MCD_OPC_CheckPredicate, 41, 180, 10, // Skip to: 2803 >+/* 63 */ MCD_OPC_Decode, 129, 17, 184, 2, // Opcode: VSTMSIA >+/* 68 */ MCD_OPC_FilterValue, 11, 171, 10, // Skip to: 2803 >+/* 72 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 75 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 106 >+/* 79 */ MCD_OPC_CheckPredicate, 41, 160, 10, // Skip to: 2803 >+/* 83 */ MCD_OPC_CheckField, 22, 1, 1, 154, 10, // Skip to: 2803 >+/* 89 */ MCD_OPC_CheckField, 6, 2, 0, 148, 10, // Skip to: 2803 >+/* 95 */ MCD_OPC_CheckField, 4, 1, 1, 142, 10, // Skip to: 2803 >+/* 101 */ MCD_OPC_Decode, 193, 10, 185, 2, // Opcode: VMOVDRR >+/* 106 */ MCD_OPC_FilterValue, 1, 133, 10, // Skip to: 2803 >+/* 110 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 113 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 126 >+/* 117 */ MCD_OPC_CheckPredicate, 41, 122, 10, // Skip to: 2803 >+/* 121 */ MCD_OPC_Decode, 253, 16, 186, 2, // Opcode: VSTMDIA >+/* 126 */ MCD_OPC_FilterValue, 1, 113, 10, // Skip to: 2803 >+/* 130 */ MCD_OPC_CheckPredicate, 41, 109, 10, // Skip to: 2803 >+/* 134 */ MCD_OPC_CheckField, 22, 1, 0, 103, 10, // Skip to: 2803 >+/* 140 */ MCD_OPC_Decode, 109, 187, 2, // Opcode: FSTMXIA >+/* 144 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 177 >+/* 148 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 151 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 164 >+/* 155 */ MCD_OPC_CheckPredicate, 41, 84, 10, // Skip to: 2803 >+/* 159 */ MCD_OPC_Decode, 132, 17, 188, 2, // Opcode: VSTRS >+/* 164 */ MCD_OPC_FilterValue, 11, 75, 10, // Skip to: 2803 >+/* 168 */ MCD_OPC_CheckPredicate, 41, 71, 10, // Skip to: 2803 >+/* 172 */ MCD_OPC_Decode, 131, 17, 189, 2, // Opcode: VSTRD >+/* 177 */ MCD_OPC_FilterValue, 14, 62, 10, // Skip to: 2803 >+/* 181 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 184 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 309 >+/* 188 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 191 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 264 >+/* 195 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 198 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 231 >+/* 202 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 205 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 218 >+/* 209 */ MCD_OPC_CheckPredicate, 41, 30, 10, // Skip to: 2803 >+/* 213 */ MCD_OPC_Decode, 150, 10, 190, 2, // Opcode: VMLAS >+/* 218 */ MCD_OPC_FilterValue, 1, 21, 10, // Skip to: 2803 >+/* 222 */ MCD_OPC_CheckPredicate, 41, 17, 10, // Skip to: 2803 >+/* 226 */ MCD_OPC_Decode, 129, 6, 191, 2, // Opcode: VDIVS >+/* 231 */ MCD_OPC_FilterValue, 11, 8, 10, // Skip to: 2803 >+/* 235 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 238 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 251 >+/* 242 */ MCD_OPC_CheckPredicate, 42, 253, 9, // Skip to: 2803 >+/* 246 */ MCD_OPC_Decode, 139, 10, 192, 2, // Opcode: VMLAD >+/* 251 */ MCD_OPC_FilterValue, 1, 244, 9, // Skip to: 2803 >+/* 255 */ MCD_OPC_CheckPredicate, 42, 240, 9, // Skip to: 2803 >+/* 259 */ MCD_OPC_Decode, 128, 6, 193, 2, // Opcode: VDIVD >+/* 264 */ MCD_OPC_FilterValue, 1, 231, 9, // Skip to: 2803 >+/* 268 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 271 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 290 >+/* 275 */ MCD_OPC_CheckPredicate, 41, 220, 9, // Skip to: 2803 >+/* 279 */ MCD_OPC_CheckField, 23, 1, 0, 214, 9, // Skip to: 2803 >+/* 285 */ MCD_OPC_Decode, 176, 10, 190, 2, // Opcode: VMLSS >+/* 290 */ MCD_OPC_FilterValue, 11, 205, 9, // Skip to: 2803 >+/* 294 */ MCD_OPC_CheckPredicate, 42, 201, 9, // Skip to: 2803 >+/* 298 */ MCD_OPC_CheckField, 23, 1, 0, 195, 9, // Skip to: 2803 >+/* 304 */ MCD_OPC_Decode, 165, 10, 192, 2, // Opcode: VMLSD >+/* 309 */ MCD_OPC_FilterValue, 1, 186, 9, // Skip to: 2803 >+/* 313 */ MCD_OPC_CheckPredicate, 41, 182, 9, // Skip to: 2803 >+/* 317 */ MCD_OPC_CheckField, 22, 2, 0, 176, 9, // Skip to: 2803 >+/* 323 */ MCD_OPC_CheckField, 8, 4, 10, 170, 9, // Skip to: 2803 >+/* 329 */ MCD_OPC_CheckField, 5, 2, 0, 164, 9, // Skip to: 2803 >+/* 335 */ MCD_OPC_CheckField, 0, 4, 0, 158, 9, // Skip to: 2803 >+/* 341 */ MCD_OPC_Decode, 209, 10, 194, 2, // Opcode: VMOVSR >+/* 346 */ MCD_OPC_FilterValue, 1, 111, 1, // Skip to: 717 >+/* 350 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ... >+/* 353 */ MCD_OPC_FilterValue, 12, 130, 0, // Skip to: 487 >+/* 357 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 360 */ MCD_OPC_FilterValue, 10, 47, 0, // Skip to: 411 >+/* 364 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 367 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 398 >+/* 371 */ MCD_OPC_CheckPredicate, 41, 124, 9, // Skip to: 2803 >+/* 375 */ MCD_OPC_CheckField, 22, 1, 1, 118, 9, // Skip to: 2803 >+/* 381 */ MCD_OPC_CheckField, 6, 2, 0, 112, 9, // Skip to: 2803 >+/* 387 */ MCD_OPC_CheckField, 4, 1, 1, 106, 9, // Skip to: 2803 >+/* 393 */ MCD_OPC_Decode, 206, 10, 195, 2, // Opcode: VMOVRRS >+/* 398 */ MCD_OPC_FilterValue, 1, 97, 9, // Skip to: 2803 >+/* 402 */ MCD_OPC_CheckPredicate, 41, 93, 9, // Skip to: 2803 >+/* 406 */ MCD_OPC_Decode, 227, 9, 184, 2, // Opcode: VLDMSIA >+/* 411 */ MCD_OPC_FilterValue, 11, 84, 9, // Skip to: 2803 >+/* 415 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 418 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 449 >+/* 422 */ MCD_OPC_CheckPredicate, 41, 73, 9, // Skip to: 2803 >+/* 426 */ MCD_OPC_CheckField, 22, 1, 1, 67, 9, // Skip to: 2803 >+/* 432 */ MCD_OPC_CheckField, 6, 2, 0, 61, 9, // Skip to: 2803 >+/* 438 */ MCD_OPC_CheckField, 4, 1, 1, 55, 9, // Skip to: 2803 >+/* 444 */ MCD_OPC_Decode, 205, 10, 196, 2, // Opcode: VMOVRRD >+/* 449 */ MCD_OPC_FilterValue, 1, 46, 9, // Skip to: 2803 >+/* 453 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 456 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 469 >+/* 460 */ MCD_OPC_CheckPredicate, 41, 35, 9, // Skip to: 2803 >+/* 464 */ MCD_OPC_Decode, 223, 9, 186, 2, // Opcode: VLDMDIA >+/* 469 */ MCD_OPC_FilterValue, 1, 26, 9, // Skip to: 2803 >+/* 473 */ MCD_OPC_CheckPredicate, 41, 22, 9, // Skip to: 2803 >+/* 477 */ MCD_OPC_CheckField, 22, 1, 0, 16, 9, // Skip to: 2803 >+/* 483 */ MCD_OPC_Decode, 105, 187, 2, // Opcode: FLDMXIA >+/* 487 */ MCD_OPC_FilterValue, 13, 29, 0, // Skip to: 520 >+/* 491 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 494 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 507 >+/* 498 */ MCD_OPC_CheckPredicate, 41, 253, 8, // Skip to: 2803 >+/* 502 */ MCD_OPC_Decode, 230, 9, 188, 2, // Opcode: VLDRS >+/* 507 */ MCD_OPC_FilterValue, 11, 244, 8, // Skip to: 2803 >+/* 511 */ MCD_OPC_CheckPredicate, 41, 240, 8, // Skip to: 2803 >+/* 515 */ MCD_OPC_Decode, 229, 9, 189, 2, // Opcode: VLDRD >+/* 520 */ MCD_OPC_FilterValue, 14, 231, 8, // Skip to: 2803 >+/* 524 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 527 */ MCD_OPC_FilterValue, 0, 149, 0, // Skip to: 680 >+/* 531 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 534 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 607 >+/* 538 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 541 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 574 >+/* 545 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 548 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 561 >+/* 552 */ MCD_OPC_CheckPredicate, 41, 199, 8, // Skip to: 2803 >+/* 556 */ MCD_OPC_Decode, 156, 11, 190, 2, // Opcode: VNMLSS >+/* 561 */ MCD_OPC_FilterValue, 1, 190, 8, // Skip to: 2803 >+/* 565 */ MCD_OPC_CheckPredicate, 43, 186, 8, // Skip to: 2803 >+/* 569 */ MCD_OPC_Decode, 162, 6, 190, 2, // Opcode: VFNMSS >+/* 574 */ MCD_OPC_FilterValue, 11, 177, 8, // Skip to: 2803 >+/* 578 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 581 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 594 >+/* 585 */ MCD_OPC_CheckPredicate, 42, 166, 8, // Skip to: 2803 >+/* 589 */ MCD_OPC_Decode, 155, 11, 192, 2, // Opcode: VNMLSD >+/* 594 */ MCD_OPC_FilterValue, 1, 157, 8, // Skip to: 2803 >+/* 598 */ MCD_OPC_CheckPredicate, 44, 153, 8, // Skip to: 2803 >+/* 602 */ MCD_OPC_Decode, 161, 6, 192, 2, // Opcode: VFNMSD >+/* 607 */ MCD_OPC_FilterValue, 1, 144, 8, // Skip to: 2803 >+/* 611 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 614 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 647 >+/* 618 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 621 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 634 >+/* 625 */ MCD_OPC_CheckPredicate, 41, 126, 8, // Skip to: 2803 >+/* 629 */ MCD_OPC_Decode, 154, 11, 190, 2, // Opcode: VNMLAS >+/* 634 */ MCD_OPC_FilterValue, 1, 117, 8, // Skip to: 2803 >+/* 638 */ MCD_OPC_CheckPredicate, 43, 113, 8, // Skip to: 2803 >+/* 642 */ MCD_OPC_Decode, 160, 6, 190, 2, // Opcode: VFNMAS >+/* 647 */ MCD_OPC_FilterValue, 11, 104, 8, // Skip to: 2803 >+/* 651 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... >+/* 654 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 667 >+/* 658 */ MCD_OPC_CheckPredicate, 42, 93, 8, // Skip to: 2803 >+/* 662 */ MCD_OPC_Decode, 153, 11, 192, 2, // Opcode: VNMLAD >+/* 667 */ MCD_OPC_FilterValue, 1, 84, 8, // Skip to: 2803 >+/* 671 */ MCD_OPC_CheckPredicate, 44, 80, 8, // Skip to: 2803 >+/* 675 */ MCD_OPC_Decode, 159, 6, 192, 2, // Opcode: VFNMAD >+/* 680 */ MCD_OPC_FilterValue, 1, 71, 8, // Skip to: 2803 >+/* 684 */ MCD_OPC_CheckPredicate, 41, 67, 8, // Skip to: 2803 >+/* 688 */ MCD_OPC_CheckField, 22, 2, 0, 61, 8, // Skip to: 2803 >+/* 694 */ MCD_OPC_CheckField, 8, 4, 10, 55, 8, // Skip to: 2803 >+/* 700 */ MCD_OPC_CheckField, 5, 2, 0, 49, 8, // Skip to: 2803 >+/* 706 */ MCD_OPC_CheckField, 0, 4, 0, 43, 8, // Skip to: 2803 >+/* 712 */ MCD_OPC_Decode, 207, 10, 197, 2, // Opcode: VMOVRS >+/* 717 */ MCD_OPC_FilterValue, 2, 172, 1, // Skip to: 1149 >+/* 721 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... >+/* 724 */ MCD_OPC_FilterValue, 25, 54, 0, // Skip to: 782 >+/* 728 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 731 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 744 >+/* 735 */ MCD_OPC_CheckPredicate, 41, 16, 8, // Skip to: 2803 >+/* 739 */ MCD_OPC_Decode, 130, 17, 198, 2, // Opcode: VSTMSIA_UPD >+/* 744 */ MCD_OPC_FilterValue, 11, 7, 8, // Skip to: 2803 >+/* 748 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 751 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 764 >+/* 755 */ MCD_OPC_CheckPredicate, 41, 252, 7, // Skip to: 2803 >+/* 759 */ MCD_OPC_Decode, 254, 16, 199, 2, // Opcode: VSTMDIA_UPD >+/* 764 */ MCD_OPC_FilterValue, 1, 243, 7, // Skip to: 2803 >+/* 768 */ MCD_OPC_CheckPredicate, 41, 239, 7, // Skip to: 2803 >+/* 772 */ MCD_OPC_CheckField, 22, 1, 0, 233, 7, // Skip to: 2803 >+/* 778 */ MCD_OPC_Decode, 110, 200, 2, // Opcode: FSTMXIA_UPD >+/* 782 */ MCD_OPC_FilterValue, 26, 54, 0, // Skip to: 840 >+/* 786 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 789 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 802 >+/* 793 */ MCD_OPC_CheckPredicate, 41, 214, 7, // Skip to: 2803 >+/* 797 */ MCD_OPC_Decode, 128, 17, 198, 2, // Opcode: VSTMSDB_UPD >+/* 802 */ MCD_OPC_FilterValue, 11, 205, 7, // Skip to: 2803 >+/* 806 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 809 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 822 >+/* 813 */ MCD_OPC_CheckPredicate, 41, 194, 7, // Skip to: 2803 >+/* 817 */ MCD_OPC_Decode, 252, 16, 199, 2, // Opcode: VSTMDDB_UPD >+/* 822 */ MCD_OPC_FilterValue, 1, 185, 7, // Skip to: 2803 >+/* 826 */ MCD_OPC_CheckPredicate, 41, 181, 7, // Skip to: 2803 >+/* 830 */ MCD_OPC_CheckField, 22, 1, 0, 175, 7, // Skip to: 2803 >+/* 836 */ MCD_OPC_Decode, 108, 200, 2, // Opcode: FSTMXDB_UPD >+/* 840 */ MCD_OPC_FilterValue, 28, 93, 0, // Skip to: 937 >+/* 844 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 847 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 892 >+/* 851 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 854 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 873 >+/* 858 */ MCD_OPC_CheckPredicate, 41, 149, 7, // Skip to: 2803 >+/* 862 */ MCD_OPC_CheckField, 4, 1, 0, 143, 7, // Skip to: 2803 >+/* 868 */ MCD_OPC_Decode, 248, 10, 191, 2, // Opcode: VMULS >+/* 873 */ MCD_OPC_FilterValue, 11, 134, 7, // Skip to: 2803 >+/* 877 */ MCD_OPC_CheckPredicate, 42, 130, 7, // Skip to: 2803 >+/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 124, 7, // Skip to: 2803 >+/* 887 */ MCD_OPC_Decode, 235, 10, 193, 2, // Opcode: VMULD >+/* 892 */ MCD_OPC_FilterValue, 1, 115, 7, // Skip to: 2803 >+/* 896 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 899 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 918 >+/* 903 */ MCD_OPC_CheckPredicate, 41, 104, 7, // Skip to: 2803 >+/* 907 */ MCD_OPC_CheckField, 4, 1, 0, 98, 7, // Skip to: 2803 >+/* 913 */ MCD_OPC_Decode, 158, 11, 191, 2, // Opcode: VNMULS >+/* 918 */ MCD_OPC_FilterValue, 11, 89, 7, // Skip to: 2803 >+/* 922 */ MCD_OPC_CheckPredicate, 42, 85, 7, // Skip to: 2803 >+/* 926 */ MCD_OPC_CheckField, 4, 1, 0, 79, 7, // Skip to: 2803 >+/* 932 */ MCD_OPC_Decode, 157, 11, 193, 2, // Opcode: VNMULD >+/* 937 */ MCD_OPC_FilterValue, 29, 70, 7, // Skip to: 2803 >+/* 941 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... >+/* 944 */ MCD_OPC_FilterValue, 0, 69, 0, // Skip to: 1017 >+/* 948 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 951 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 984 >+/* 955 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 958 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 971 >+/* 962 */ MCD_OPC_CheckPredicate, 43, 45, 7, // Skip to: 2803 >+/* 966 */ MCD_OPC_Decode, 152, 6, 190, 2, // Opcode: VFMAS >+/* 971 */ MCD_OPC_FilterValue, 11, 36, 7, // Skip to: 2803 >+/* 975 */ MCD_OPC_CheckPredicate, 44, 32, 7, // Skip to: 2803 >+/* 979 */ MCD_OPC_Decode, 151, 6, 192, 2, // Opcode: VFMAD >+/* 984 */ MCD_OPC_FilterValue, 1, 23, 7, // Skip to: 2803 >+/* 988 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 991 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1004 >+/* 995 */ MCD_OPC_CheckPredicate, 43, 12, 7, // Skip to: 2803 >+/* 999 */ MCD_OPC_Decode, 156, 6, 190, 2, // Opcode: VFMSS >+/* 1004 */ MCD_OPC_FilterValue, 11, 3, 7, // Skip to: 2803 >+/* 1008 */ MCD_OPC_CheckPredicate, 44, 255, 6, // Skip to: 2803 >+/* 1012 */ MCD_OPC_Decode, 155, 6, 192, 2, // Opcode: VFMSD >+/* 1017 */ MCD_OPC_FilterValue, 1, 246, 6, // Skip to: 2803 >+/* 1021 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1024 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1049 >+/* 1028 */ MCD_OPC_CheckPredicate, 41, 235, 6, // Skip to: 2803 >+/* 1032 */ MCD_OPC_CheckField, 22, 1, 1, 229, 6, // Skip to: 2803 >+/* 1038 */ MCD_OPC_CheckField, 7, 5, 20, 223, 6, // Skip to: 2803 >+/* 1044 */ MCD_OPC_Decode, 234, 10, 201, 2, // Opcode: VMSR_FPSID >+/* 1049 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 1074 >+/* 1053 */ MCD_OPC_CheckPredicate, 41, 210, 6, // Skip to: 2803 >+/* 1057 */ MCD_OPC_CheckField, 22, 1, 1, 204, 6, // Skip to: 2803 >+/* 1063 */ MCD_OPC_CheckField, 7, 5, 20, 198, 6, // Skip to: 2803 >+/* 1069 */ MCD_OPC_Decode, 230, 10, 201, 2, // Opcode: VMSR >+/* 1074 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 1099 >+/* 1078 */ MCD_OPC_CheckPredicate, 41, 185, 6, // Skip to: 2803 >+/* 1082 */ MCD_OPC_CheckField, 22, 1, 1, 179, 6, // Skip to: 2803 >+/* 1088 */ MCD_OPC_CheckField, 7, 5, 20, 173, 6, // Skip to: 2803 >+/* 1094 */ MCD_OPC_Decode, 231, 10, 201, 2, // Opcode: VMSR_FPEXC >+/* 1099 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 1124 >+/* 1103 */ MCD_OPC_CheckPredicate, 41, 160, 6, // Skip to: 2803 >+/* 1107 */ MCD_OPC_CheckField, 22, 1, 1, 154, 6, // Skip to: 2803 >+/* 1113 */ MCD_OPC_CheckField, 7, 5, 20, 148, 6, // Skip to: 2803 >+/* 1119 */ MCD_OPC_Decode, 232, 10, 201, 2, // Opcode: VMSR_FPINST >+/* 1124 */ MCD_OPC_FilterValue, 10, 139, 6, // Skip to: 2803 >+/* 1128 */ MCD_OPC_CheckPredicate, 41, 135, 6, // Skip to: 2803 >+/* 1132 */ MCD_OPC_CheckField, 22, 1, 1, 129, 6, // Skip to: 2803 >+/* 1138 */ MCD_OPC_CheckField, 7, 5, 20, 123, 6, // Skip to: 2803 >+/* 1144 */ MCD_OPC_Decode, 233, 10, 201, 2, // Opcode: VMSR_FPINST2 >+/* 1149 */ MCD_OPC_FilterValue, 3, 114, 6, // Skip to: 2803 >+/* 1153 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ... >+/* 1156 */ MCD_OPC_FilterValue, 25, 54, 0, // Skip to: 1214 >+/* 1160 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1163 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1176 >+/* 1167 */ MCD_OPC_CheckPredicate, 41, 96, 6, // Skip to: 2803 >+/* 1171 */ MCD_OPC_Decode, 228, 9, 198, 2, // Opcode: VLDMSIA_UPD >+/* 1176 */ MCD_OPC_FilterValue, 11, 87, 6, // Skip to: 2803 >+/* 1180 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 1183 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1196 >+/* 1187 */ MCD_OPC_CheckPredicate, 41, 76, 6, // Skip to: 2803 >+/* 1191 */ MCD_OPC_Decode, 224, 9, 199, 2, // Opcode: VLDMDIA_UPD >+/* 1196 */ MCD_OPC_FilterValue, 1, 67, 6, // Skip to: 2803 >+/* 1200 */ MCD_OPC_CheckPredicate, 41, 63, 6, // Skip to: 2803 >+/* 1204 */ MCD_OPC_CheckField, 22, 1, 0, 57, 6, // Skip to: 2803 >+/* 1210 */ MCD_OPC_Decode, 106, 200, 2, // Opcode: FLDMXIA_UPD >+/* 1214 */ MCD_OPC_FilterValue, 26, 54, 0, // Skip to: 1272 >+/* 1218 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1221 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1234 >+/* 1225 */ MCD_OPC_CheckPredicate, 41, 38, 6, // Skip to: 2803 >+/* 1229 */ MCD_OPC_Decode, 226, 9, 198, 2, // Opcode: VLDMSDB_UPD >+/* 1234 */ MCD_OPC_FilterValue, 11, 29, 6, // Skip to: 2803 >+/* 1238 */ MCD_OPC_ExtractField, 0, 1, // Inst{0} ... >+/* 1241 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1254 >+/* 1245 */ MCD_OPC_CheckPredicate, 41, 18, 6, // Skip to: 2803 >+/* 1249 */ MCD_OPC_Decode, 222, 9, 199, 2, // Opcode: VLDMDDB_UPD >+/* 1254 */ MCD_OPC_FilterValue, 1, 9, 6, // Skip to: 2803 >+/* 1258 */ MCD_OPC_CheckPredicate, 41, 5, 6, // Skip to: 2803 >+/* 1262 */ MCD_OPC_CheckField, 22, 1, 0, 255, 5, // Skip to: 2803 >+/* 1268 */ MCD_OPC_Decode, 104, 200, 2, // Opcode: FLDMXDB_UPD >+/* 1272 */ MCD_OPC_FilterValue, 28, 93, 0, // Skip to: 1369 >+/* 1276 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 1279 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 1324 >+/* 1283 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1286 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1305 >+/* 1290 */ MCD_OPC_CheckPredicate, 41, 229, 5, // Skip to: 2803 >+/* 1294 */ MCD_OPC_CheckField, 4, 1, 0, 223, 5, // Skip to: 2803 >+/* 1300 */ MCD_OPC_Decode, 195, 4, 191, 2, // Opcode: VADDS >+/* 1305 */ MCD_OPC_FilterValue, 11, 214, 5, // Skip to: 2803 >+/* 1309 */ MCD_OPC_CheckPredicate, 42, 210, 5, // Skip to: 2803 >+/* 1313 */ MCD_OPC_CheckField, 4, 1, 0, 204, 5, // Skip to: 2803 >+/* 1319 */ MCD_OPC_Decode, 185, 4, 193, 2, // Opcode: VADDD >+/* 1324 */ MCD_OPC_FilterValue, 1, 195, 5, // Skip to: 2803 >+/* 1328 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 1331 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1350 >+/* 1335 */ MCD_OPC_CheckPredicate, 41, 184, 5, // Skip to: 2803 >+/* 1339 */ MCD_OPC_CheckField, 4, 1, 0, 178, 5, // Skip to: 2803 >+/* 1345 */ MCD_OPC_Decode, 143, 17, 191, 2, // Opcode: VSUBS >+/* 1350 */ MCD_OPC_FilterValue, 11, 169, 5, // Skip to: 2803 >+/* 1354 */ MCD_OPC_CheckPredicate, 42, 165, 5, // Skip to: 2803 >+/* 1358 */ MCD_OPC_CheckField, 4, 1, 0, 159, 5, // Skip to: 2803 >+/* 1364 */ MCD_OPC_Decode, 133, 17, 193, 2, // Opcode: VSUBD >+/* 1369 */ MCD_OPC_FilterValue, 29, 150, 5, // Skip to: 2803 >+/* 1373 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... >+/* 1376 */ MCD_OPC_FilterValue, 40, 237, 0, // Skip to: 1617 >+/* 1380 */ MCD_OPC_ExtractField, 4, 2, // Inst{5-4} ... >+/* 1383 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1395 >+/* 1387 */ MCD_OPC_CheckPredicate, 45, 132, 5, // Skip to: 2803 >+/* 1391 */ MCD_OPC_Decode, 103, 202, 2, // Opcode: FCONSTS >+/* 1395 */ MCD_OPC_FilterValue, 1, 124, 5, // Skip to: 2803 >+/* 1399 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1402 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1427 >+/* 1406 */ MCD_OPC_CheckPredicate, 41, 113, 5, // Skip to: 2803 >+/* 1410 */ MCD_OPC_CheckField, 22, 1, 1, 107, 5, // Skip to: 2803 >+/* 1416 */ MCD_OPC_CheckField, 0, 4, 0, 101, 5, // Skip to: 2803 >+/* 1422 */ MCD_OPC_Decode, 226, 10, 201, 2, // Opcode: VMRS_FPSID >+/* 1427 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 1467 >+/* 1431 */ MCD_OPC_ExtractField, 0, 4, // Inst{3-0} ... >+/* 1434 */ MCD_OPC_FilterValue, 0, 85, 5, // Skip to: 2803 >+/* 1438 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... >+/* 1441 */ MCD_OPC_FilterValue, 1, 78, 5, // Skip to: 2803 >+/* 1445 */ MCD_OPC_CheckPredicate, 41, 9, 0, // Skip to: 1458 >+/* 1449 */ MCD_OPC_CheckField, 12, 4, 15, 3, 0, // Skip to: 1458 >+/* 1455 */ MCD_OPC_Decode, 107, 27, // Opcode: FMSTAT >+/* 1458 */ MCD_OPC_CheckPredicate, 41, 61, 5, // Skip to: 2803 >+/* 1462 */ MCD_OPC_Decode, 222, 10, 201, 2, // Opcode: VMRS >+/* 1467 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 1492 >+/* 1471 */ MCD_OPC_CheckPredicate, 46, 48, 5, // Skip to: 2803 >+/* 1475 */ MCD_OPC_CheckField, 22, 1, 1, 42, 5, // Skip to: 2803 >+/* 1481 */ MCD_OPC_CheckField, 0, 4, 0, 36, 5, // Skip to: 2803 >+/* 1487 */ MCD_OPC_Decode, 229, 10, 201, 2, // Opcode: VMRS_MVFR2 >+/* 1492 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 1517 >+/* 1496 */ MCD_OPC_CheckPredicate, 41, 23, 5, // Skip to: 2803 >+/* 1500 */ MCD_OPC_CheckField, 22, 1, 1, 17, 5, // Skip to: 2803 >+/* 1506 */ MCD_OPC_CheckField, 0, 4, 0, 11, 5, // Skip to: 2803 >+/* 1512 */ MCD_OPC_Decode, 228, 10, 201, 2, // Opcode: VMRS_MVFR1 >+/* 1517 */ MCD_OPC_FilterValue, 7, 21, 0, // Skip to: 1542 >+/* 1521 */ MCD_OPC_CheckPredicate, 41, 254, 4, // Skip to: 2803 >+/* 1525 */ MCD_OPC_CheckField, 22, 1, 1, 248, 4, // Skip to: 2803 >+/* 1531 */ MCD_OPC_CheckField, 0, 4, 0, 242, 4, // Skip to: 2803 >+/* 1537 */ MCD_OPC_Decode, 227, 10, 201, 2, // Opcode: VMRS_MVFR0 >+/* 1542 */ MCD_OPC_FilterValue, 8, 21, 0, // Skip to: 1567 >+/* 1546 */ MCD_OPC_CheckPredicate, 41, 229, 4, // Skip to: 2803 >+/* 1550 */ MCD_OPC_CheckField, 22, 1, 1, 223, 4, // Skip to: 2803 >+/* 1556 */ MCD_OPC_CheckField, 0, 4, 0, 217, 4, // Skip to: 2803 >+/* 1562 */ MCD_OPC_Decode, 223, 10, 201, 2, // Opcode: VMRS_FPEXC >+/* 1567 */ MCD_OPC_FilterValue, 9, 21, 0, // Skip to: 1592 >+/* 1571 */ MCD_OPC_CheckPredicate, 41, 204, 4, // Skip to: 2803 >+/* 1575 */ MCD_OPC_CheckField, 22, 1, 1, 198, 4, // Skip to: 2803 >+/* 1581 */ MCD_OPC_CheckField, 0, 4, 0, 192, 4, // Skip to: 2803 >+/* 1587 */ MCD_OPC_Decode, 224, 10, 201, 2, // Opcode: VMRS_FPINST >+/* 1592 */ MCD_OPC_FilterValue, 10, 183, 4, // Skip to: 2803 >+/* 1596 */ MCD_OPC_CheckPredicate, 41, 179, 4, // Skip to: 2803 >+/* 1600 */ MCD_OPC_CheckField, 22, 1, 1, 173, 4, // Skip to: 2803 >+/* 1606 */ MCD_OPC_CheckField, 0, 4, 0, 167, 4, // Skip to: 2803 >+/* 1612 */ MCD_OPC_Decode, 225, 10, 201, 2, // Opcode: VMRS_FPINST2 >+/* 1617 */ MCD_OPC_FilterValue, 41, 32, 1, // Skip to: 1909 >+/* 1621 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1624 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1643 >+/* 1628 */ MCD_OPC_CheckPredicate, 41, 147, 4, // Skip to: 2803 >+/* 1632 */ MCD_OPC_CheckField, 4, 1, 0, 141, 4, // Skip to: 2803 >+/* 1638 */ MCD_OPC_Decode, 208, 10, 203, 2, // Opcode: VMOVS >+/* 1643 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1662 >+/* 1647 */ MCD_OPC_CheckPredicate, 41, 128, 4, // Skip to: 2803 >+/* 1651 */ MCD_OPC_CheckField, 4, 1, 0, 122, 4, // Skip to: 2803 >+/* 1657 */ MCD_OPC_Decode, 144, 11, 203, 2, // Opcode: VNEGS >+/* 1662 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1681 >+/* 1666 */ MCD_OPC_CheckPredicate, 41, 109, 4, // Skip to: 2803 >+/* 1670 */ MCD_OPC_CheckField, 4, 1, 0, 103, 4, // Skip to: 2803 >+/* 1676 */ MCD_OPC_Decode, 206, 5, 203, 2, // Opcode: VCVTBHS >+/* 1681 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1700 >+/* 1685 */ MCD_OPC_CheckPredicate, 41, 90, 4, // Skip to: 2803 >+/* 1689 */ MCD_OPC_CheckField, 4, 1, 0, 84, 4, // Skip to: 2803 >+/* 1695 */ MCD_OPC_Decode, 207, 5, 203, 2, // Opcode: VCVTBSH >+/* 1700 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 1719 >+/* 1704 */ MCD_OPC_CheckPredicate, 41, 71, 4, // Skip to: 2803 >+/* 1708 */ MCD_OPC_CheckField, 4, 1, 0, 65, 4, // Skip to: 2803 >+/* 1714 */ MCD_OPC_Decode, 191, 5, 203, 2, // Opcode: VCMPS >+/* 1719 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1738 >+/* 1723 */ MCD_OPC_CheckPredicate, 41, 52, 4, // Skip to: 2803 >+/* 1727 */ MCD_OPC_CheckField, 0, 6, 0, 46, 4, // Skip to: 2803 >+/* 1733 */ MCD_OPC_Decode, 193, 5, 204, 2, // Opcode: VCMPZS >+/* 1738 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 1757 >+/* 1742 */ MCD_OPC_CheckPredicate, 46, 33, 4, // Skip to: 2803 >+/* 1746 */ MCD_OPC_CheckField, 4, 1, 0, 27, 4, // Skip to: 2803 >+/* 1752 */ MCD_OPC_Decode, 158, 13, 203, 2, // Opcode: VRINTRS >+/* 1757 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 1776 >+/* 1761 */ MCD_OPC_CheckPredicate, 46, 14, 4, // Skip to: 2803 >+/* 1765 */ MCD_OPC_CheckField, 4, 1, 0, 8, 4, // Skip to: 2803 >+/* 1771 */ MCD_OPC_Decode, 162, 13, 203, 2, // Opcode: VRINTXS >+/* 1776 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1795 >+/* 1780 */ MCD_OPC_CheckPredicate, 41, 251, 3, // Skip to: 2803 >+/* 1784 */ MCD_OPC_CheckField, 4, 1, 0, 245, 3, // Skip to: 2803 >+/* 1790 */ MCD_OPC_Decode, 205, 17, 203, 2, // Opcode: VUITOS >+/* 1795 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1814 >+/* 1799 */ MCD_OPC_CheckPredicate, 41, 232, 3, // Skip to: 2803 >+/* 1803 */ MCD_OPC_CheckField, 4, 1, 0, 226, 3, // Skip to: 2803 >+/* 1809 */ MCD_OPC_Decode, 163, 14, 205, 2, // Opcode: VSHTOS >+/* 1814 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1833 >+/* 1818 */ MCD_OPC_CheckPredicate, 41, 213, 3, // Skip to: 2803 >+/* 1822 */ MCD_OPC_CheckField, 4, 1, 0, 207, 3, // Skip to: 2803 >+/* 1828 */ MCD_OPC_Decode, 203, 17, 205, 2, // Opcode: VUHTOS >+/* 1833 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1852 >+/* 1837 */ MCD_OPC_CheckPredicate, 41, 194, 3, // Skip to: 2803 >+/* 1841 */ MCD_OPC_CheckField, 4, 1, 0, 188, 3, // Skip to: 2803 >+/* 1847 */ MCD_OPC_Decode, 185, 17, 203, 2, // Opcode: VTOUIRS >+/* 1852 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1871 >+/* 1856 */ MCD_OPC_CheckPredicate, 41, 175, 3, // Skip to: 2803 >+/* 1860 */ MCD_OPC_CheckField, 4, 1, 0, 169, 3, // Skip to: 2803 >+/* 1866 */ MCD_OPC_Decode, 177, 17, 203, 2, // Opcode: VTOSIRS >+/* 1871 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 1890 >+/* 1875 */ MCD_OPC_CheckPredicate, 41, 156, 3, // Skip to: 2803 >+/* 1879 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 2803 >+/* 1885 */ MCD_OPC_Decode, 175, 17, 205, 2, // Opcode: VTOSHS >+/* 1890 */ MCD_OPC_FilterValue, 15, 141, 3, // Skip to: 2803 >+/* 1894 */ MCD_OPC_CheckPredicate, 41, 137, 3, // Skip to: 2803 >+/* 1898 */ MCD_OPC_CheckField, 4, 1, 0, 131, 3, // Skip to: 2803 >+/* 1904 */ MCD_OPC_Decode, 183, 17, 205, 2, // Opcode: VTOUHS >+/* 1909 */ MCD_OPC_FilterValue, 43, 32, 1, // Skip to: 2201 >+/* 1913 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 1916 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 1935 >+/* 1920 */ MCD_OPC_CheckPredicate, 41, 111, 3, // Skip to: 2803 >+/* 1924 */ MCD_OPC_CheckField, 4, 1, 0, 105, 3, // Skip to: 2803 >+/* 1930 */ MCD_OPC_Decode, 172, 4, 203, 2, // Opcode: VABSS >+/* 1935 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1954 >+/* 1939 */ MCD_OPC_CheckPredicate, 41, 92, 3, // Skip to: 2803 >+/* 1943 */ MCD_OPC_CheckField, 4, 1, 0, 86, 3, // Skip to: 2803 >+/* 1949 */ MCD_OPC_Decode, 177, 14, 203, 2, // Opcode: VSQRTS >+/* 1954 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 1973 >+/* 1958 */ MCD_OPC_CheckPredicate, 41, 73, 3, // Skip to: 2803 >+/* 1962 */ MCD_OPC_CheckField, 4, 1, 0, 67, 3, // Skip to: 2803 >+/* 1968 */ MCD_OPC_Decode, 236, 5, 203, 2, // Opcode: VCVTTHS >+/* 1973 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1992 >+/* 1977 */ MCD_OPC_CheckPredicate, 41, 54, 3, // Skip to: 2803 >+/* 1981 */ MCD_OPC_CheckField, 4, 1, 0, 48, 3, // Skip to: 2803 >+/* 1987 */ MCD_OPC_Decode, 237, 5, 203, 2, // Opcode: VCVTTSH >+/* 1992 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2011 >+/* 1996 */ MCD_OPC_CheckPredicate, 41, 35, 3, // Skip to: 2803 >+/* 2000 */ MCD_OPC_CheckField, 4, 1, 0, 29, 3, // Skip to: 2803 >+/* 2006 */ MCD_OPC_Decode, 188, 5, 203, 2, // Opcode: VCMPES >+/* 2011 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2030 >+/* 2015 */ MCD_OPC_CheckPredicate, 41, 16, 3, // Skip to: 2803 >+/* 2019 */ MCD_OPC_CheckField, 0, 6, 0, 10, 3, // Skip to: 2803 >+/* 2025 */ MCD_OPC_Decode, 190, 5, 204, 2, // Opcode: VCMPEZS >+/* 2030 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2049 >+/* 2034 */ MCD_OPC_CheckPredicate, 46, 253, 2, // Skip to: 2803 >+/* 2038 */ MCD_OPC_CheckField, 4, 1, 0, 247, 2, // Skip to: 2803 >+/* 2044 */ MCD_OPC_Decode, 166, 13, 203, 2, // Opcode: VRINTZS >+/* 2049 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2068 >+/* 2053 */ MCD_OPC_CheckPredicate, 41, 234, 2, // Skip to: 2803 >+/* 2057 */ MCD_OPC_CheckField, 4, 1, 0, 228, 2, // Skip to: 2803 >+/* 2063 */ MCD_OPC_Decode, 208, 5, 206, 2, // Opcode: VCVTDS >+/* 2068 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2087 >+/* 2072 */ MCD_OPC_CheckPredicate, 41, 215, 2, // Skip to: 2803 >+/* 2076 */ MCD_OPC_CheckField, 4, 1, 0, 209, 2, // Skip to: 2803 >+/* 2082 */ MCD_OPC_Decode, 165, 14, 203, 2, // Opcode: VSITOS >+/* 2087 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2106 >+/* 2091 */ MCD_OPC_CheckPredicate, 41, 196, 2, // Skip to: 2803 >+/* 2095 */ MCD_OPC_CheckField, 4, 1, 0, 190, 2, // Skip to: 2803 >+/* 2101 */ MCD_OPC_Decode, 175, 14, 205, 2, // Opcode: VSLTOS >+/* 2106 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2125 >+/* 2110 */ MCD_OPC_CheckPredicate, 41, 177, 2, // Skip to: 2803 >+/* 2114 */ MCD_OPC_CheckField, 4, 1, 0, 171, 2, // Skip to: 2803 >+/* 2120 */ MCD_OPC_Decode, 207, 17, 205, 2, // Opcode: VULTOS >+/* 2125 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2144 >+/* 2129 */ MCD_OPC_CheckPredicate, 41, 158, 2, // Skip to: 2803 >+/* 2133 */ MCD_OPC_CheckField, 4, 1, 0, 152, 2, // Skip to: 2803 >+/* 2139 */ MCD_OPC_Decode, 187, 17, 203, 2, // Opcode: VTOUIZS >+/* 2144 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2163 >+/* 2148 */ MCD_OPC_CheckPredicate, 41, 139, 2, // Skip to: 2803 >+/* 2152 */ MCD_OPC_CheckField, 4, 1, 0, 133, 2, // Skip to: 2803 >+/* 2158 */ MCD_OPC_Decode, 179, 17, 203, 2, // Opcode: VTOSIZS >+/* 2163 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2182 >+/* 2167 */ MCD_OPC_CheckPredicate, 41, 120, 2, // Skip to: 2803 >+/* 2171 */ MCD_OPC_CheckField, 4, 1, 0, 114, 2, // Skip to: 2803 >+/* 2177 */ MCD_OPC_Decode, 181, 17, 205, 2, // Opcode: VTOSLS >+/* 2182 */ MCD_OPC_FilterValue, 15, 105, 2, // Skip to: 2803 >+/* 2186 */ MCD_OPC_CheckPredicate, 41, 101, 2, // Skip to: 2803 >+/* 2190 */ MCD_OPC_CheckField, 4, 1, 0, 95, 2, // Skip to: 2803 >+/* 2196 */ MCD_OPC_Decode, 189, 17, 205, 2, // Opcode: VTOULS >+/* 2201 */ MCD_OPC_FilterValue, 44, 14, 0, // Skip to: 2219 >+/* 2205 */ MCD_OPC_CheckPredicate, 47, 82, 2, // Skip to: 2803 >+/* 2209 */ MCD_OPC_CheckField, 4, 2, 0, 76, 2, // Skip to: 2803 >+/* 2215 */ MCD_OPC_Decode, 102, 207, 2, // Opcode: FCONSTD >+/* 2219 */ MCD_OPC_FilterValue, 45, 32, 1, // Skip to: 2511 >+/* 2223 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2226 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2245 >+/* 2230 */ MCD_OPC_CheckPredicate, 42, 57, 2, // Skip to: 2803 >+/* 2234 */ MCD_OPC_CheckField, 4, 1, 0, 51, 2, // Skip to: 2803 >+/* 2240 */ MCD_OPC_Decode, 191, 10, 208, 2, // Opcode: VMOVD >+/* 2245 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2264 >+/* 2249 */ MCD_OPC_CheckPredicate, 42, 38, 2, // Skip to: 2803 >+/* 2253 */ MCD_OPC_CheckField, 4, 1, 0, 32, 2, // Skip to: 2803 >+/* 2259 */ MCD_OPC_Decode, 143, 11, 208, 2, // Opcode: VNEGD >+/* 2264 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2283 >+/* 2268 */ MCD_OPC_CheckPredicate, 48, 19, 2, // Skip to: 2803 >+/* 2272 */ MCD_OPC_CheckField, 4, 1, 0, 13, 2, // Skip to: 2803 >+/* 2278 */ MCD_OPC_Decode, 205, 5, 206, 2, // Opcode: VCVTBHD >+/* 2283 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 2302 >+/* 2287 */ MCD_OPC_CheckPredicate, 48, 0, 2, // Skip to: 2803 >+/* 2291 */ MCD_OPC_CheckField, 4, 1, 0, 250, 1, // Skip to: 2803 >+/* 2297 */ MCD_OPC_Decode, 204, 5, 209, 2, // Opcode: VCVTBDH >+/* 2302 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2321 >+/* 2306 */ MCD_OPC_CheckPredicate, 42, 237, 1, // Skip to: 2803 >+/* 2310 */ MCD_OPC_CheckField, 4, 1, 0, 231, 1, // Skip to: 2803 >+/* 2316 */ MCD_OPC_Decode, 186, 5, 208, 2, // Opcode: VCMPD >+/* 2321 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2340 >+/* 2325 */ MCD_OPC_CheckPredicate, 42, 218, 1, // Skip to: 2803 >+/* 2329 */ MCD_OPC_CheckField, 0, 6, 0, 212, 1, // Skip to: 2803 >+/* 2335 */ MCD_OPC_Decode, 192, 5, 210, 2, // Opcode: VCMPZD >+/* 2340 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2359 >+/* 2344 */ MCD_OPC_CheckPredicate, 48, 199, 1, // Skip to: 2803 >+/* 2348 */ MCD_OPC_CheckField, 4, 1, 0, 193, 1, // Skip to: 2803 >+/* 2354 */ MCD_OPC_Decode, 157, 13, 208, 2, // Opcode: VRINTRD >+/* 2359 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2378 >+/* 2363 */ MCD_OPC_CheckPredicate, 48, 180, 1, // Skip to: 2803 >+/* 2367 */ MCD_OPC_CheckField, 4, 1, 0, 174, 1, // Skip to: 2803 >+/* 2373 */ MCD_OPC_Decode, 159, 13, 208, 2, // Opcode: VRINTXD >+/* 2378 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2397 >+/* 2382 */ MCD_OPC_CheckPredicate, 42, 161, 1, // Skip to: 2803 >+/* 2386 */ MCD_OPC_CheckField, 4, 1, 0, 155, 1, // Skip to: 2803 >+/* 2392 */ MCD_OPC_Decode, 204, 17, 206, 2, // Opcode: VUITOD >+/* 2397 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2416 >+/* 2401 */ MCD_OPC_CheckPredicate, 42, 142, 1, // Skip to: 2803 >+/* 2405 */ MCD_OPC_CheckField, 4, 1, 0, 136, 1, // Skip to: 2803 >+/* 2411 */ MCD_OPC_Decode, 162, 14, 211, 2, // Opcode: VSHTOD >+/* 2416 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2435 >+/* 2420 */ MCD_OPC_CheckPredicate, 42, 123, 1, // Skip to: 2803 >+/* 2424 */ MCD_OPC_CheckField, 4, 1, 0, 117, 1, // Skip to: 2803 >+/* 2430 */ MCD_OPC_Decode, 202, 17, 211, 2, // Opcode: VUHTOD >+/* 2435 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2454 >+/* 2439 */ MCD_OPC_CheckPredicate, 42, 104, 1, // Skip to: 2803 >+/* 2443 */ MCD_OPC_CheckField, 4, 1, 0, 98, 1, // Skip to: 2803 >+/* 2449 */ MCD_OPC_Decode, 184, 17, 209, 2, // Opcode: VTOUIRD >+/* 2454 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2473 >+/* 2458 */ MCD_OPC_CheckPredicate, 42, 85, 1, // Skip to: 2803 >+/* 2462 */ MCD_OPC_CheckField, 4, 1, 0, 79, 1, // Skip to: 2803 >+/* 2468 */ MCD_OPC_Decode, 176, 17, 209, 2, // Opcode: VTOSIRD >+/* 2473 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2492 >+/* 2477 */ MCD_OPC_CheckPredicate, 42, 66, 1, // Skip to: 2803 >+/* 2481 */ MCD_OPC_CheckField, 4, 1, 0, 60, 1, // Skip to: 2803 >+/* 2487 */ MCD_OPC_Decode, 174, 17, 211, 2, // Opcode: VTOSHD >+/* 2492 */ MCD_OPC_FilterValue, 15, 51, 1, // Skip to: 2803 >+/* 2496 */ MCD_OPC_CheckPredicate, 42, 47, 1, // Skip to: 2803 >+/* 2500 */ MCD_OPC_CheckField, 4, 1, 0, 41, 1, // Skip to: 2803 >+/* 2506 */ MCD_OPC_Decode, 182, 17, 211, 2, // Opcode: VTOUHD >+/* 2511 */ MCD_OPC_FilterValue, 47, 32, 1, // Skip to: 2803 >+/* 2515 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 2518 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 2537 >+/* 2522 */ MCD_OPC_CheckPredicate, 42, 21, 1, // Skip to: 2803 >+/* 2526 */ MCD_OPC_CheckField, 4, 1, 0, 15, 1, // Skip to: 2803 >+/* 2532 */ MCD_OPC_Decode, 171, 4, 208, 2, // Opcode: VABSD >+/* 2537 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 2556 >+/* 2541 */ MCD_OPC_CheckPredicate, 42, 2, 1, // Skip to: 2803 >+/* 2545 */ MCD_OPC_CheckField, 4, 1, 0, 252, 0, // Skip to: 2803 >+/* 2551 */ MCD_OPC_Decode, 176, 14, 208, 2, // Opcode: VSQRTD >+/* 2556 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2575 >+/* 2560 */ MCD_OPC_CheckPredicate, 48, 239, 0, // Skip to: 2803 >+/* 2564 */ MCD_OPC_CheckField, 4, 1, 0, 233, 0, // Skip to: 2803 >+/* 2570 */ MCD_OPC_Decode, 235, 5, 206, 2, // Opcode: VCVTTHD >+/* 2575 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 2594 >+/* 2579 */ MCD_OPC_CheckPredicate, 48, 220, 0, // Skip to: 2803 >+/* 2583 */ MCD_OPC_CheckField, 4, 1, 0, 214, 0, // Skip to: 2803 >+/* 2589 */ MCD_OPC_Decode, 234, 5, 209, 2, // Opcode: VCVTTDH >+/* 2594 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 2613 >+/* 2598 */ MCD_OPC_CheckPredicate, 42, 201, 0, // Skip to: 2803 >+/* 2602 */ MCD_OPC_CheckField, 4, 1, 0, 195, 0, // Skip to: 2803 >+/* 2608 */ MCD_OPC_Decode, 187, 5, 208, 2, // Opcode: VCMPED >+/* 2613 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 2632 >+/* 2617 */ MCD_OPC_CheckPredicate, 42, 182, 0, // Skip to: 2803 >+/* 2621 */ MCD_OPC_CheckField, 0, 6, 0, 176, 0, // Skip to: 2803 >+/* 2627 */ MCD_OPC_Decode, 189, 5, 210, 2, // Opcode: VCMPEZD >+/* 2632 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 2651 >+/* 2636 */ MCD_OPC_CheckPredicate, 48, 163, 0, // Skip to: 2803 >+/* 2640 */ MCD_OPC_CheckField, 4, 1, 0, 157, 0, // Skip to: 2803 >+/* 2646 */ MCD_OPC_Decode, 163, 13, 208, 2, // Opcode: VRINTZD >+/* 2651 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 2670 >+/* 2655 */ MCD_OPC_CheckPredicate, 42, 144, 0, // Skip to: 2803 >+/* 2659 */ MCD_OPC_CheckField, 4, 1, 0, 138, 0, // Skip to: 2803 >+/* 2665 */ MCD_OPC_Decode, 233, 5, 209, 2, // Opcode: VCVTSD >+/* 2670 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 2689 >+/* 2674 */ MCD_OPC_CheckPredicate, 42, 125, 0, // Skip to: 2803 >+/* 2678 */ MCD_OPC_CheckField, 4, 1, 0, 119, 0, // Skip to: 2803 >+/* 2684 */ MCD_OPC_Decode, 164, 14, 206, 2, // Opcode: VSITOD >+/* 2689 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 2708 >+/* 2693 */ MCD_OPC_CheckPredicate, 42, 106, 0, // Skip to: 2803 >+/* 2697 */ MCD_OPC_CheckField, 4, 1, 0, 100, 0, // Skip to: 2803 >+/* 2703 */ MCD_OPC_Decode, 174, 14, 211, 2, // Opcode: VSLTOD >+/* 2708 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 2727 >+/* 2712 */ MCD_OPC_CheckPredicate, 42, 87, 0, // Skip to: 2803 >+/* 2716 */ MCD_OPC_CheckField, 4, 1, 0, 81, 0, // Skip to: 2803 >+/* 2722 */ MCD_OPC_Decode, 206, 17, 211, 2, // Opcode: VULTOD >+/* 2727 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 2746 >+/* 2731 */ MCD_OPC_CheckPredicate, 42, 68, 0, // Skip to: 2803 >+/* 2735 */ MCD_OPC_CheckField, 4, 1, 0, 62, 0, // Skip to: 2803 >+/* 2741 */ MCD_OPC_Decode, 186, 17, 209, 2, // Opcode: VTOUIZD >+/* 2746 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 2765 >+/* 2750 */ MCD_OPC_CheckPredicate, 42, 49, 0, // Skip to: 2803 >+/* 2754 */ MCD_OPC_CheckField, 4, 1, 0, 43, 0, // Skip to: 2803 >+/* 2760 */ MCD_OPC_Decode, 178, 17, 209, 2, // Opcode: VTOSIZD >+/* 2765 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 2784 >+/* 2769 */ MCD_OPC_CheckPredicate, 42, 30, 0, // Skip to: 2803 >+/* 2773 */ MCD_OPC_CheckField, 4, 1, 0, 24, 0, // Skip to: 2803 >+/* 2779 */ MCD_OPC_Decode, 180, 17, 211, 2, // Opcode: VTOSLD >+/* 2784 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 2803 >+/* 2788 */ MCD_OPC_CheckPredicate, 42, 11, 0, // Skip to: 2803 >+/* 2792 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 2803 >+/* 2798 */ MCD_OPC_Decode, 188, 17, 211, 2, // Opcode: VTOULD >+/* 2803 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableVFPV832[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 160, 0, // Skip to: 167 >+/* 7 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 95, 0, // Skip to: 109 >+/* 14 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 17 */ MCD_OPC_FilterValue, 10, 43, 0, // Skip to: 64 >+/* 21 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 24 */ MCD_OPC_FilterValue, 252, 3, 15, 0, // Skip to: 44 >+/* 29 */ MCD_OPC_CheckPredicate, 46, 254, 3, // Skip to: 1055 >+/* 33 */ MCD_OPC_CheckField, 4, 1, 0, 248, 3, // Skip to: 1055 >+/* 39 */ MCD_OPC_Decode, 228, 13, 212, 2, // Opcode: VSELEQS >+/* 44 */ MCD_OPC_FilterValue, 253, 3, 238, 3, // Skip to: 1055 >+/* 49 */ MCD_OPC_CheckPredicate, 46, 234, 3, // Skip to: 1055 >+/* 53 */ MCD_OPC_CheckField, 4, 1, 0, 228, 3, // Skip to: 1055 >+/* 59 */ MCD_OPC_Decode, 234, 9, 212, 2, // Opcode: VMAXNMS >+/* 64 */ MCD_OPC_FilterValue, 11, 219, 3, // Skip to: 1055 >+/* 68 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 71 */ MCD_OPC_FilterValue, 252, 3, 14, 0, // Skip to: 90 >+/* 76 */ MCD_OPC_CheckPredicate, 48, 207, 3, // Skip to: 1055 >+/* 80 */ MCD_OPC_CheckField, 4, 1, 0, 201, 3, // Skip to: 1055 >+/* 86 */ MCD_OPC_Decode, 227, 13, 94, // Opcode: VSELEQD >+/* 90 */ MCD_OPC_FilterValue, 253, 3, 192, 3, // Skip to: 1055 >+/* 95 */ MCD_OPC_CheckPredicate, 48, 188, 3, // Skip to: 1055 >+/* 99 */ MCD_OPC_CheckField, 4, 1, 0, 182, 3, // Skip to: 1055 >+/* 105 */ MCD_OPC_Decode, 231, 9, 94, // Opcode: VMAXNMD >+/* 109 */ MCD_OPC_FilterValue, 1, 174, 3, // Skip to: 1055 >+/* 113 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 116 */ MCD_OPC_FilterValue, 10, 22, 0, // Skip to: 142 >+/* 120 */ MCD_OPC_CheckPredicate, 46, 163, 3, // Skip to: 1055 >+/* 124 */ MCD_OPC_CheckField, 23, 9, 253, 3, 156, 3, // Skip to: 1055 >+/* 131 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 1055 >+/* 137 */ MCD_OPC_Decode, 252, 9, 212, 2, // Opcode: VMINNMS >+/* 142 */ MCD_OPC_FilterValue, 11, 141, 3, // Skip to: 1055 >+/* 146 */ MCD_OPC_CheckPredicate, 48, 137, 3, // Skip to: 1055 >+/* 150 */ MCD_OPC_CheckField, 23, 9, 253, 3, 130, 3, // Skip to: 1055 >+/* 157 */ MCD_OPC_CheckField, 4, 1, 0, 124, 3, // Skip to: 1055 >+/* 163 */ MCD_OPC_Decode, 249, 9, 94, // Opcode: VMINNMD >+/* 167 */ MCD_OPC_FilterValue, 1, 66, 0, // Skip to: 237 >+/* 171 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 174 */ MCD_OPC_FilterValue, 10, 28, 0, // Skip to: 206 >+/* 178 */ MCD_OPC_CheckPredicate, 46, 105, 3, // Skip to: 1055 >+/* 182 */ MCD_OPC_CheckField, 23, 9, 252, 3, 98, 3, // Skip to: 1055 >+/* 189 */ MCD_OPC_CheckField, 6, 1, 0, 92, 3, // Skip to: 1055 >+/* 195 */ MCD_OPC_CheckField, 4, 1, 0, 86, 3, // Skip to: 1055 >+/* 201 */ MCD_OPC_Decode, 234, 13, 212, 2, // Opcode: VSELVSS >+/* 206 */ MCD_OPC_FilterValue, 11, 77, 3, // Skip to: 1055 >+/* 210 */ MCD_OPC_CheckPredicate, 48, 73, 3, // Skip to: 1055 >+/* 214 */ MCD_OPC_CheckField, 23, 9, 252, 3, 66, 3, // Skip to: 1055 >+/* 221 */ MCD_OPC_CheckField, 6, 1, 0, 60, 3, // Skip to: 1055 >+/* 227 */ MCD_OPC_CheckField, 4, 1, 0, 54, 3, // Skip to: 1055 >+/* 233 */ MCD_OPC_Decode, 233, 13, 94, // Opcode: VSELVSD >+/* 237 */ MCD_OPC_FilterValue, 2, 66, 0, // Skip to: 307 >+/* 241 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 244 */ MCD_OPC_FilterValue, 10, 28, 0, // Skip to: 276 >+/* 248 */ MCD_OPC_CheckPredicate, 46, 35, 3, // Skip to: 1055 >+/* 252 */ MCD_OPC_CheckField, 23, 9, 252, 3, 28, 3, // Skip to: 1055 >+/* 259 */ MCD_OPC_CheckField, 6, 1, 0, 22, 3, // Skip to: 1055 >+/* 265 */ MCD_OPC_CheckField, 4, 1, 0, 16, 3, // Skip to: 1055 >+/* 271 */ MCD_OPC_Decode, 230, 13, 212, 2, // Opcode: VSELGES >+/* 276 */ MCD_OPC_FilterValue, 11, 7, 3, // Skip to: 1055 >+/* 280 */ MCD_OPC_CheckPredicate, 48, 3, 3, // Skip to: 1055 >+/* 284 */ MCD_OPC_CheckField, 23, 9, 252, 3, 252, 2, // Skip to: 1055 >+/* 291 */ MCD_OPC_CheckField, 6, 1, 0, 246, 2, // Skip to: 1055 >+/* 297 */ MCD_OPC_CheckField, 4, 1, 0, 240, 2, // Skip to: 1055 >+/* 303 */ MCD_OPC_Decode, 229, 13, 94, // Opcode: VSELGED >+/* 307 */ MCD_OPC_FilterValue, 3, 232, 2, // Skip to: 1055 >+/* 311 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 314 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 372 >+/* 318 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 321 */ MCD_OPC_FilterValue, 10, 22, 0, // Skip to: 347 >+/* 325 */ MCD_OPC_CheckPredicate, 46, 214, 2, // Skip to: 1055 >+/* 329 */ MCD_OPC_CheckField, 23, 9, 252, 3, 207, 2, // Skip to: 1055 >+/* 336 */ MCD_OPC_CheckField, 4, 1, 0, 201, 2, // Skip to: 1055 >+/* 342 */ MCD_OPC_Decode, 232, 13, 212, 2, // Opcode: VSELGTS >+/* 347 */ MCD_OPC_FilterValue, 11, 192, 2, // Skip to: 1055 >+/* 351 */ MCD_OPC_CheckPredicate, 48, 188, 2, // Skip to: 1055 >+/* 355 */ MCD_OPC_CheckField, 23, 9, 252, 3, 181, 2, // Skip to: 1055 >+/* 362 */ MCD_OPC_CheckField, 4, 1, 0, 175, 2, // Skip to: 1055 >+/* 368 */ MCD_OPC_Decode, 231, 13, 94, // Opcode: VSELGTD >+/* 372 */ MCD_OPC_FilterValue, 1, 167, 2, // Skip to: 1055 >+/* 376 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 379 */ MCD_OPC_FilterValue, 8, 54, 0, // Skip to: 437 >+/* 383 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 386 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 412 >+/* 390 */ MCD_OPC_CheckPredicate, 46, 149, 2, // Skip to: 1055 >+/* 394 */ MCD_OPC_CheckField, 23, 9, 253, 3, 142, 2, // Skip to: 1055 >+/* 401 */ MCD_OPC_CheckField, 4, 1, 0, 136, 2, // Skip to: 1055 >+/* 407 */ MCD_OPC_Decode, 144, 13, 213, 2, // Opcode: VRINTAS >+/* 412 */ MCD_OPC_FilterValue, 22, 127, 2, // Skip to: 1055 >+/* 416 */ MCD_OPC_CheckPredicate, 48, 123, 2, // Skip to: 1055 >+/* 420 */ MCD_OPC_CheckField, 23, 9, 253, 3, 116, 2, // Skip to: 1055 >+/* 427 */ MCD_OPC_CheckField, 4, 1, 0, 110, 2, // Skip to: 1055 >+/* 433 */ MCD_OPC_Decode, 141, 13, 123, // Opcode: VRINTAD >+/* 437 */ MCD_OPC_FilterValue, 9, 54, 0, // Skip to: 495 >+/* 441 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 444 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 470 >+/* 448 */ MCD_OPC_CheckPredicate, 46, 91, 2, // Skip to: 1055 >+/* 452 */ MCD_OPC_CheckField, 23, 9, 253, 3, 84, 2, // Skip to: 1055 >+/* 459 */ MCD_OPC_CheckField, 4, 1, 0, 78, 2, // Skip to: 1055 >+/* 465 */ MCD_OPC_Decode, 152, 13, 213, 2, // Opcode: VRINTNS >+/* 470 */ MCD_OPC_FilterValue, 22, 69, 2, // Skip to: 1055 >+/* 474 */ MCD_OPC_CheckPredicate, 48, 65, 2, // Skip to: 1055 >+/* 478 */ MCD_OPC_CheckField, 23, 9, 253, 3, 58, 2, // Skip to: 1055 >+/* 485 */ MCD_OPC_CheckField, 4, 1, 0, 52, 2, // Skip to: 1055 >+/* 491 */ MCD_OPC_Decode, 149, 13, 123, // Opcode: VRINTND >+/* 495 */ MCD_OPC_FilterValue, 10, 54, 0, // Skip to: 553 >+/* 499 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 502 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 528 >+/* 506 */ MCD_OPC_CheckPredicate, 46, 33, 2, // Skip to: 1055 >+/* 510 */ MCD_OPC_CheckField, 23, 9, 253, 3, 26, 2, // Skip to: 1055 >+/* 517 */ MCD_OPC_CheckField, 4, 1, 0, 20, 2, // Skip to: 1055 >+/* 523 */ MCD_OPC_Decode, 156, 13, 213, 2, // Opcode: VRINTPS >+/* 528 */ MCD_OPC_FilterValue, 22, 11, 2, // Skip to: 1055 >+/* 532 */ MCD_OPC_CheckPredicate, 48, 7, 2, // Skip to: 1055 >+/* 536 */ MCD_OPC_CheckField, 23, 9, 253, 3, 0, 2, // Skip to: 1055 >+/* 543 */ MCD_OPC_CheckField, 4, 1, 0, 250, 1, // Skip to: 1055 >+/* 549 */ MCD_OPC_Decode, 153, 13, 123, // Opcode: VRINTPD >+/* 553 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 611 >+/* 557 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 560 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 586 >+/* 564 */ MCD_OPC_CheckPredicate, 46, 231, 1, // Skip to: 1055 >+/* 568 */ MCD_OPC_CheckField, 23, 9, 253, 3, 224, 1, // Skip to: 1055 >+/* 575 */ MCD_OPC_CheckField, 4, 1, 0, 218, 1, // Skip to: 1055 >+/* 581 */ MCD_OPC_Decode, 148, 13, 213, 2, // Opcode: VRINTMS >+/* 586 */ MCD_OPC_FilterValue, 22, 209, 1, // Skip to: 1055 >+/* 590 */ MCD_OPC_CheckPredicate, 48, 205, 1, // Skip to: 1055 >+/* 594 */ MCD_OPC_CheckField, 23, 9, 253, 3, 198, 1, // Skip to: 1055 >+/* 601 */ MCD_OPC_CheckField, 4, 1, 0, 192, 1, // Skip to: 1055 >+/* 607 */ MCD_OPC_Decode, 145, 13, 123, // Opcode: VRINTMD >+/* 611 */ MCD_OPC_FilterValue, 12, 107, 0, // Skip to: 722 >+/* 615 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 618 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 644 >+/* 622 */ MCD_OPC_CheckPredicate, 46, 173, 1, // Skip to: 1055 >+/* 626 */ MCD_OPC_CheckField, 23, 9, 253, 3, 166, 1, // Skip to: 1055 >+/* 633 */ MCD_OPC_CheckField, 4, 1, 0, 160, 1, // Skip to: 1055 >+/* 639 */ MCD_OPC_Decode, 203, 5, 213, 2, // Opcode: VCVTAUS >+/* 644 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 670 >+/* 648 */ MCD_OPC_CheckPredicate, 46, 147, 1, // Skip to: 1055 >+/* 652 */ MCD_OPC_CheckField, 23, 9, 253, 3, 140, 1, // Skip to: 1055 >+/* 659 */ MCD_OPC_CheckField, 4, 1, 0, 134, 1, // Skip to: 1055 >+/* 665 */ MCD_OPC_Decode, 201, 5, 213, 2, // Opcode: VCVTASS >+/* 670 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 696 >+/* 674 */ MCD_OPC_CheckPredicate, 48, 121, 1, // Skip to: 1055 >+/* 678 */ MCD_OPC_CheckField, 23, 9, 253, 3, 114, 1, // Skip to: 1055 >+/* 685 */ MCD_OPC_CheckField, 4, 1, 0, 108, 1, // Skip to: 1055 >+/* 691 */ MCD_OPC_Decode, 202, 5, 214, 2, // Opcode: VCVTAUD >+/* 696 */ MCD_OPC_FilterValue, 23, 99, 1, // Skip to: 1055 >+/* 700 */ MCD_OPC_CheckPredicate, 48, 95, 1, // Skip to: 1055 >+/* 704 */ MCD_OPC_CheckField, 23, 9, 253, 3, 88, 1, // Skip to: 1055 >+/* 711 */ MCD_OPC_CheckField, 4, 1, 0, 82, 1, // Skip to: 1055 >+/* 717 */ MCD_OPC_Decode, 200, 5, 214, 2, // Opcode: VCVTASD >+/* 722 */ MCD_OPC_FilterValue, 13, 107, 0, // Skip to: 833 >+/* 726 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 729 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 755 >+/* 733 */ MCD_OPC_CheckPredicate, 46, 62, 1, // Skip to: 1055 >+/* 737 */ MCD_OPC_CheckField, 23, 9, 253, 3, 55, 1, // Skip to: 1055 >+/* 744 */ MCD_OPC_CheckField, 4, 1, 0, 49, 1, // Skip to: 1055 >+/* 750 */ MCD_OPC_Decode, 224, 5, 213, 2, // Opcode: VCVTNUS >+/* 755 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 781 >+/* 759 */ MCD_OPC_CheckPredicate, 46, 36, 1, // Skip to: 1055 >+/* 763 */ MCD_OPC_CheckField, 23, 9, 253, 3, 29, 1, // Skip to: 1055 >+/* 770 */ MCD_OPC_CheckField, 4, 1, 0, 23, 1, // Skip to: 1055 >+/* 776 */ MCD_OPC_Decode, 222, 5, 213, 2, // Opcode: VCVTNSS >+/* 781 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 807 >+/* 785 */ MCD_OPC_CheckPredicate, 48, 10, 1, // Skip to: 1055 >+/* 789 */ MCD_OPC_CheckField, 23, 9, 253, 3, 3, 1, // Skip to: 1055 >+/* 796 */ MCD_OPC_CheckField, 4, 1, 0, 253, 0, // Skip to: 1055 >+/* 802 */ MCD_OPC_Decode, 223, 5, 214, 2, // Opcode: VCVTNUD >+/* 807 */ MCD_OPC_FilterValue, 23, 244, 0, // Skip to: 1055 >+/* 811 */ MCD_OPC_CheckPredicate, 48, 240, 0, // Skip to: 1055 >+/* 815 */ MCD_OPC_CheckField, 23, 9, 253, 3, 233, 0, // Skip to: 1055 >+/* 822 */ MCD_OPC_CheckField, 4, 1, 0, 227, 0, // Skip to: 1055 >+/* 828 */ MCD_OPC_Decode, 221, 5, 214, 2, // Opcode: VCVTNSD >+/* 833 */ MCD_OPC_FilterValue, 14, 107, 0, // Skip to: 944 >+/* 837 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 840 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 866 >+/* 844 */ MCD_OPC_CheckPredicate, 46, 207, 0, // Skip to: 1055 >+/* 848 */ MCD_OPC_CheckField, 23, 9, 253, 3, 200, 0, // Skip to: 1055 >+/* 855 */ MCD_OPC_CheckField, 4, 1, 0, 194, 0, // Skip to: 1055 >+/* 861 */ MCD_OPC_Decode, 232, 5, 213, 2, // Opcode: VCVTPUS >+/* 866 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 892 >+/* 870 */ MCD_OPC_CheckPredicate, 46, 181, 0, // Skip to: 1055 >+/* 874 */ MCD_OPC_CheckField, 23, 9, 253, 3, 174, 0, // Skip to: 1055 >+/* 881 */ MCD_OPC_CheckField, 4, 1, 0, 168, 0, // Skip to: 1055 >+/* 887 */ MCD_OPC_Decode, 230, 5, 213, 2, // Opcode: VCVTPSS >+/* 892 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 918 >+/* 896 */ MCD_OPC_CheckPredicate, 48, 155, 0, // Skip to: 1055 >+/* 900 */ MCD_OPC_CheckField, 23, 9, 253, 3, 148, 0, // Skip to: 1055 >+/* 907 */ MCD_OPC_CheckField, 4, 1, 0, 142, 0, // Skip to: 1055 >+/* 913 */ MCD_OPC_Decode, 231, 5, 214, 2, // Opcode: VCVTPUD >+/* 918 */ MCD_OPC_FilterValue, 23, 133, 0, // Skip to: 1055 >+/* 922 */ MCD_OPC_CheckPredicate, 48, 129, 0, // Skip to: 1055 >+/* 926 */ MCD_OPC_CheckField, 23, 9, 253, 3, 122, 0, // Skip to: 1055 >+/* 933 */ MCD_OPC_CheckField, 4, 1, 0, 116, 0, // Skip to: 1055 >+/* 939 */ MCD_OPC_Decode, 229, 5, 214, 2, // Opcode: VCVTPSD >+/* 944 */ MCD_OPC_FilterValue, 15, 107, 0, // Skip to: 1055 >+/* 948 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ... >+/* 951 */ MCD_OPC_FilterValue, 20, 22, 0, // Skip to: 977 >+/* 955 */ MCD_OPC_CheckPredicate, 46, 96, 0, // Skip to: 1055 >+/* 959 */ MCD_OPC_CheckField, 23, 9, 253, 3, 89, 0, // Skip to: 1055 >+/* 966 */ MCD_OPC_CheckField, 4, 1, 0, 83, 0, // Skip to: 1055 >+/* 972 */ MCD_OPC_Decode, 216, 5, 213, 2, // Opcode: VCVTMUS >+/* 977 */ MCD_OPC_FilterValue, 21, 22, 0, // Skip to: 1003 >+/* 981 */ MCD_OPC_CheckPredicate, 46, 70, 0, // Skip to: 1055 >+/* 985 */ MCD_OPC_CheckField, 23, 9, 253, 3, 63, 0, // Skip to: 1055 >+/* 992 */ MCD_OPC_CheckField, 4, 1, 0, 57, 0, // Skip to: 1055 >+/* 998 */ MCD_OPC_Decode, 214, 5, 213, 2, // Opcode: VCVTMSS >+/* 1003 */ MCD_OPC_FilterValue, 22, 22, 0, // Skip to: 1029 >+/* 1007 */ MCD_OPC_CheckPredicate, 48, 44, 0, // Skip to: 1055 >+/* 1011 */ MCD_OPC_CheckField, 23, 9, 253, 3, 37, 0, // Skip to: 1055 >+/* 1018 */ MCD_OPC_CheckField, 4, 1, 0, 31, 0, // Skip to: 1055 >+/* 1024 */ MCD_OPC_Decode, 215, 5, 214, 2, // Opcode: VCVTMUD >+/* 1029 */ MCD_OPC_FilterValue, 23, 22, 0, // Skip to: 1055 >+/* 1033 */ MCD_OPC_CheckPredicate, 48, 18, 0, // Skip to: 1055 >+/* 1037 */ MCD_OPC_CheckField, 23, 9, 253, 3, 11, 0, // Skip to: 1055 >+/* 1044 */ MCD_OPC_CheckField, 4, 1, 0, 5, 0, // Skip to: 1055 >+/* 1050 */ MCD_OPC_Decode, 213, 5, 214, 2, // Opcode: VCVTMSD >+/* 1055 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTablev8Crypto32[] = { >+/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 72 >+/* 7 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 10 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 41 >+/* 15 */ MCD_OPC_CheckPredicate, 16, 193, 1, // Skip to: 468 >+/* 19 */ MCD_OPC_CheckField, 8, 4, 12, 187, 1, // Skip to: 468 >+/* 25 */ MCD_OPC_CheckField, 6, 1, 1, 181, 1, // Skip to: 468 >+/* 31 */ MCD_OPC_CheckField, 4, 1, 0, 175, 1, // Skip to: 468 >+/* 37 */ MCD_OPC_Decode, 186, 2, 103, // Opcode: SHA1C >+/* 41 */ MCD_OPC_FilterValue, 230, 3, 166, 1, // Skip to: 468 >+/* 46 */ MCD_OPC_CheckPredicate, 16, 162, 1, // Skip to: 468 >+/* 50 */ MCD_OPC_CheckField, 8, 4, 12, 156, 1, // Skip to: 468 >+/* 56 */ MCD_OPC_CheckField, 6, 1, 1, 150, 1, // Skip to: 468 >+/* 62 */ MCD_OPC_CheckField, 4, 1, 0, 144, 1, // Skip to: 468 >+/* 68 */ MCD_OPC_Decode, 192, 2, 103, // Opcode: SHA256H >+/* 72 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 141 >+/* 76 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 79 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 110 >+/* 84 */ MCD_OPC_CheckPredicate, 16, 124, 1, // Skip to: 468 >+/* 88 */ MCD_OPC_CheckField, 8, 4, 12, 118, 1, // Skip to: 468 >+/* 94 */ MCD_OPC_CheckField, 6, 1, 1, 112, 1, // Skip to: 468 >+/* 100 */ MCD_OPC_CheckField, 4, 1, 0, 106, 1, // Skip to: 468 >+/* 106 */ MCD_OPC_Decode, 189, 2, 103, // Opcode: SHA1P >+/* 110 */ MCD_OPC_FilterValue, 230, 3, 97, 1, // Skip to: 468 >+/* 115 */ MCD_OPC_CheckPredicate, 16, 93, 1, // Skip to: 468 >+/* 119 */ MCD_OPC_CheckField, 8, 4, 12, 87, 1, // Skip to: 468 >+/* 125 */ MCD_OPC_CheckField, 6, 1, 1, 81, 1, // Skip to: 468 >+/* 131 */ MCD_OPC_CheckField, 4, 1, 0, 75, 1, // Skip to: 468 >+/* 137 */ MCD_OPC_Decode, 193, 2, 103, // Opcode: SHA256H2 >+/* 141 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 210 >+/* 145 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ... >+/* 148 */ MCD_OPC_FilterValue, 228, 3, 26, 0, // Skip to: 179 >+/* 153 */ MCD_OPC_CheckPredicate, 16, 55, 1, // Skip to: 468 >+/* 157 */ MCD_OPC_CheckField, 8, 4, 12, 49, 1, // Skip to: 468 >+/* 163 */ MCD_OPC_CheckField, 6, 1, 1, 43, 1, // Skip to: 468 >+/* 169 */ MCD_OPC_CheckField, 4, 1, 0, 37, 1, // Skip to: 468 >+/* 175 */ MCD_OPC_Decode, 188, 2, 103, // Opcode: SHA1M >+/* 179 */ MCD_OPC_FilterValue, 230, 3, 28, 1, // Skip to: 468 >+/* 184 */ MCD_OPC_CheckPredicate, 16, 24, 1, // Skip to: 468 >+/* 188 */ MCD_OPC_CheckField, 8, 4, 12, 18, 1, // Skip to: 468 >+/* 194 */ MCD_OPC_CheckField, 6, 1, 1, 12, 1, // Skip to: 468 >+/* 200 */ MCD_OPC_CheckField, 4, 1, 0, 6, 1, // Skip to: 468 >+/* 206 */ MCD_OPC_Decode, 195, 2, 103, // Opcode: SHA256SU1 >+/* 210 */ MCD_OPC_FilterValue, 3, 254, 0, // Skip to: 468 >+/* 214 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 217 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 254 >+/* 221 */ MCD_OPC_CheckPredicate, 16, 243, 0, // Skip to: 468 >+/* 225 */ MCD_OPC_CheckField, 23, 9, 231, 3, 236, 0, // Skip to: 468 >+/* 232 */ MCD_OPC_CheckField, 16, 4, 9, 230, 0, // Skip to: 468 >+/* 238 */ MCD_OPC_CheckField, 6, 2, 3, 224, 0, // Skip to: 468 >+/* 244 */ MCD_OPC_CheckField, 4, 1, 0, 218, 0, // Skip to: 468 >+/* 250 */ MCD_OPC_Decode, 187, 2, 124, // Opcode: SHA1H >+/* 254 */ MCD_OPC_FilterValue, 3, 179, 0, // Skip to: 437 >+/* 258 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 261 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 292 >+/* 265 */ MCD_OPC_CheckPredicate, 16, 199, 0, // Skip to: 468 >+/* 269 */ MCD_OPC_CheckField, 23, 9, 231, 3, 192, 0, // Skip to: 468 >+/* 276 */ MCD_OPC_CheckField, 16, 4, 0, 186, 0, // Skip to: 468 >+/* 282 */ MCD_OPC_CheckField, 4, 1, 0, 180, 0, // Skip to: 468 >+/* 288 */ MCD_OPC_Decode, 37, 130, 1, // Opcode: AESE >+/* 292 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 323 >+/* 296 */ MCD_OPC_CheckPredicate, 16, 168, 0, // Skip to: 468 >+/* 300 */ MCD_OPC_CheckField, 23, 9, 231, 3, 161, 0, // Skip to: 468 >+/* 307 */ MCD_OPC_CheckField, 16, 4, 0, 155, 0, // Skip to: 468 >+/* 313 */ MCD_OPC_CheckField, 4, 1, 0, 149, 0, // Skip to: 468 >+/* 319 */ MCD_OPC_Decode, 36, 130, 1, // Opcode: AESD >+/* 323 */ MCD_OPC_FilterValue, 2, 53, 0, // Skip to: 380 >+/* 327 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 354 >+/* 334 */ MCD_OPC_CheckPredicate, 16, 130, 0, // Skip to: 468 >+/* 338 */ MCD_OPC_CheckField, 23, 9, 231, 3, 123, 0, // Skip to: 468 >+/* 345 */ MCD_OPC_CheckField, 4, 1, 0, 117, 0, // Skip to: 468 >+/* 351 */ MCD_OPC_Decode, 39, 124, // Opcode: AESMC >+/* 354 */ MCD_OPC_FilterValue, 10, 110, 0, // Skip to: 468 >+/* 358 */ MCD_OPC_CheckPredicate, 16, 106, 0, // Skip to: 468 >+/* 362 */ MCD_OPC_CheckField, 23, 9, 231, 3, 99, 0, // Skip to: 468 >+/* 369 */ MCD_OPC_CheckField, 4, 1, 0, 93, 0, // Skip to: 468 >+/* 375 */ MCD_OPC_Decode, 191, 2, 130, 1, // Opcode: SHA1SU1 >+/* 380 */ MCD_OPC_FilterValue, 3, 84, 0, // Skip to: 468 >+/* 384 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... >+/* 387 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 411 >+/* 391 */ MCD_OPC_CheckPredicate, 16, 73, 0, // Skip to: 468 >+/* 395 */ MCD_OPC_CheckField, 23, 9, 231, 3, 66, 0, // Skip to: 468 >+/* 402 */ MCD_OPC_CheckField, 4, 1, 0, 60, 0, // Skip to: 468 >+/* 408 */ MCD_OPC_Decode, 38, 124, // Opcode: AESIMC >+/* 411 */ MCD_OPC_FilterValue, 10, 53, 0, // Skip to: 468 >+/* 415 */ MCD_OPC_CheckPredicate, 16, 49, 0, // Skip to: 468 >+/* 419 */ MCD_OPC_CheckField, 23, 9, 231, 3, 42, 0, // Skip to: 468 >+/* 426 */ MCD_OPC_CheckField, 4, 1, 0, 36, 0, // Skip to: 468 >+/* 432 */ MCD_OPC_Decode, 194, 2, 130, 1, // Opcode: SHA256SU0 >+/* 437 */ MCD_OPC_FilterValue, 12, 27, 0, // Skip to: 468 >+/* 441 */ MCD_OPC_CheckPredicate, 16, 23, 0, // Skip to: 468 >+/* 445 */ MCD_OPC_CheckField, 23, 9, 228, 3, 16, 0, // Skip to: 468 >+/* 452 */ MCD_OPC_CheckField, 6, 1, 1, 10, 0, // Skip to: 468 >+/* 458 */ MCD_OPC_CheckField, 4, 1, 0, 4, 0, // Skip to: 468 >+/* 464 */ MCD_OPC_Decode, 190, 2, 103, // Opcode: SHA1SU0 >+/* 468 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTablev8NEON32[] = { >+/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 127, 0, // Skip to: 134 >+/* 7 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 41 >+/* 14 */ MCD_OPC_CheckPredicate, 49, 6, 4, // Skip to: 1048 >+/* 18 */ MCD_OPC_CheckField, 23, 9, 231, 3, 255, 3, // Skip to: 1048 >+/* 25 */ MCD_OPC_CheckField, 16, 6, 59, 249, 3, // Skip to: 1048 >+/* 31 */ MCD_OPC_CheckField, 4, 1, 0, 243, 3, // Skip to: 1048 >+/* 37 */ MCD_OPC_Decode, 196, 5, 123, // Opcode: VCVTANSD >+/* 41 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 72 >+/* 45 */ MCD_OPC_CheckPredicate, 49, 231, 3, // Skip to: 1048 >+/* 49 */ MCD_OPC_CheckField, 23, 9, 231, 3, 224, 3, // Skip to: 1048 >+/* 56 */ MCD_OPC_CheckField, 16, 6, 59, 218, 3, // Skip to: 1048 >+/* 62 */ MCD_OPC_CheckField, 4, 1, 0, 212, 3, // Skip to: 1048 >+/* 68 */ MCD_OPC_Decode, 197, 5, 124, // Opcode: VCVTANSQ >+/* 72 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 103 >+/* 76 */ MCD_OPC_CheckPredicate, 49, 200, 3, // Skip to: 1048 >+/* 80 */ MCD_OPC_CheckField, 23, 9, 231, 3, 193, 3, // Skip to: 1048 >+/* 87 */ MCD_OPC_CheckField, 16, 6, 59, 187, 3, // Skip to: 1048 >+/* 93 */ MCD_OPC_CheckField, 4, 1, 0, 181, 3, // Skip to: 1048 >+/* 99 */ MCD_OPC_Decode, 198, 5, 123, // Opcode: VCVTANUD >+/* 103 */ MCD_OPC_FilterValue, 3, 173, 3, // Skip to: 1048 >+/* 107 */ MCD_OPC_CheckPredicate, 49, 169, 3, // Skip to: 1048 >+/* 111 */ MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, // Skip to: 1048 >+/* 118 */ MCD_OPC_CheckField, 16, 6, 59, 156, 3, // Skip to: 1048 >+/* 124 */ MCD_OPC_CheckField, 4, 1, 0, 150, 3, // Skip to: 1048 >+/* 130 */ MCD_OPC_Decode, 199, 5, 124, // Opcode: VCVTANUQ >+/* 134 */ MCD_OPC_FilterValue, 1, 127, 0, // Skip to: 265 >+/* 138 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 141 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 172 >+/* 145 */ MCD_OPC_CheckPredicate, 49, 131, 3, // Skip to: 1048 >+/* 149 */ MCD_OPC_CheckField, 23, 9, 231, 3, 124, 3, // Skip to: 1048 >+/* 156 */ MCD_OPC_CheckField, 16, 6, 59, 118, 3, // Skip to: 1048 >+/* 162 */ MCD_OPC_CheckField, 4, 1, 0, 112, 3, // Skip to: 1048 >+/* 168 */ MCD_OPC_Decode, 217, 5, 123, // Opcode: VCVTNNSD >+/* 172 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 203 >+/* 176 */ MCD_OPC_CheckPredicate, 49, 100, 3, // Skip to: 1048 >+/* 180 */ MCD_OPC_CheckField, 23, 9, 231, 3, 93, 3, // Skip to: 1048 >+/* 187 */ MCD_OPC_CheckField, 16, 6, 59, 87, 3, // Skip to: 1048 >+/* 193 */ MCD_OPC_CheckField, 4, 1, 0, 81, 3, // Skip to: 1048 >+/* 199 */ MCD_OPC_Decode, 218, 5, 124, // Opcode: VCVTNNSQ >+/* 203 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 234 >+/* 207 */ MCD_OPC_CheckPredicate, 49, 69, 3, // Skip to: 1048 >+/* 211 */ MCD_OPC_CheckField, 23, 9, 231, 3, 62, 3, // Skip to: 1048 >+/* 218 */ MCD_OPC_CheckField, 16, 6, 59, 56, 3, // Skip to: 1048 >+/* 224 */ MCD_OPC_CheckField, 4, 1, 0, 50, 3, // Skip to: 1048 >+/* 230 */ MCD_OPC_Decode, 219, 5, 123, // Opcode: VCVTNNUD >+/* 234 */ MCD_OPC_FilterValue, 3, 42, 3, // Skip to: 1048 >+/* 238 */ MCD_OPC_CheckPredicate, 49, 38, 3, // Skip to: 1048 >+/* 242 */ MCD_OPC_CheckField, 23, 9, 231, 3, 31, 3, // Skip to: 1048 >+/* 249 */ MCD_OPC_CheckField, 16, 6, 59, 25, 3, // Skip to: 1048 >+/* 255 */ MCD_OPC_CheckField, 4, 1, 0, 19, 3, // Skip to: 1048 >+/* 261 */ MCD_OPC_Decode, 220, 5, 124, // Opcode: VCVTNNUQ >+/* 265 */ MCD_OPC_FilterValue, 2, 127, 0, // Skip to: 396 >+/* 269 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 272 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 303 >+/* 276 */ MCD_OPC_CheckPredicate, 49, 0, 3, // Skip to: 1048 >+/* 280 */ MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, // Skip to: 1048 >+/* 287 */ MCD_OPC_CheckField, 16, 6, 59, 243, 2, // Skip to: 1048 >+/* 293 */ MCD_OPC_CheckField, 4, 1, 0, 237, 2, // Skip to: 1048 >+/* 299 */ MCD_OPC_Decode, 225, 5, 123, // Opcode: VCVTPNSD >+/* 303 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 334 >+/* 307 */ MCD_OPC_CheckPredicate, 49, 225, 2, // Skip to: 1048 >+/* 311 */ MCD_OPC_CheckField, 23, 9, 231, 3, 218, 2, // Skip to: 1048 >+/* 318 */ MCD_OPC_CheckField, 16, 6, 59, 212, 2, // Skip to: 1048 >+/* 324 */ MCD_OPC_CheckField, 4, 1, 0, 206, 2, // Skip to: 1048 >+/* 330 */ MCD_OPC_Decode, 226, 5, 124, // Opcode: VCVTPNSQ >+/* 334 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 365 >+/* 338 */ MCD_OPC_CheckPredicate, 49, 194, 2, // Skip to: 1048 >+/* 342 */ MCD_OPC_CheckField, 23, 9, 231, 3, 187, 2, // Skip to: 1048 >+/* 349 */ MCD_OPC_CheckField, 16, 6, 59, 181, 2, // Skip to: 1048 >+/* 355 */ MCD_OPC_CheckField, 4, 1, 0, 175, 2, // Skip to: 1048 >+/* 361 */ MCD_OPC_Decode, 227, 5, 123, // Opcode: VCVTPNUD >+/* 365 */ MCD_OPC_FilterValue, 3, 167, 2, // Skip to: 1048 >+/* 369 */ MCD_OPC_CheckPredicate, 49, 163, 2, // Skip to: 1048 >+/* 373 */ MCD_OPC_CheckField, 23, 9, 231, 3, 156, 2, // Skip to: 1048 >+/* 380 */ MCD_OPC_CheckField, 16, 6, 59, 150, 2, // Skip to: 1048 >+/* 386 */ MCD_OPC_CheckField, 4, 1, 0, 144, 2, // Skip to: 1048 >+/* 392 */ MCD_OPC_Decode, 228, 5, 124, // Opcode: VCVTPNUQ >+/* 396 */ MCD_OPC_FilterValue, 3, 127, 0, // Skip to: 527 >+/* 400 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 403 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 434 >+/* 407 */ MCD_OPC_CheckPredicate, 49, 125, 2, // Skip to: 1048 >+/* 411 */ MCD_OPC_CheckField, 23, 9, 231, 3, 118, 2, // Skip to: 1048 >+/* 418 */ MCD_OPC_CheckField, 16, 6, 59, 112, 2, // Skip to: 1048 >+/* 424 */ MCD_OPC_CheckField, 4, 1, 0, 106, 2, // Skip to: 1048 >+/* 430 */ MCD_OPC_Decode, 209, 5, 123, // Opcode: VCVTMNSD >+/* 434 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 465 >+/* 438 */ MCD_OPC_CheckPredicate, 49, 94, 2, // Skip to: 1048 >+/* 442 */ MCD_OPC_CheckField, 23, 9, 231, 3, 87, 2, // Skip to: 1048 >+/* 449 */ MCD_OPC_CheckField, 16, 6, 59, 81, 2, // Skip to: 1048 >+/* 455 */ MCD_OPC_CheckField, 4, 1, 0, 75, 2, // Skip to: 1048 >+/* 461 */ MCD_OPC_Decode, 210, 5, 124, // Opcode: VCVTMNSQ >+/* 465 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 496 >+/* 469 */ MCD_OPC_CheckPredicate, 49, 63, 2, // Skip to: 1048 >+/* 473 */ MCD_OPC_CheckField, 23, 9, 231, 3, 56, 2, // Skip to: 1048 >+/* 480 */ MCD_OPC_CheckField, 16, 6, 59, 50, 2, // Skip to: 1048 >+/* 486 */ MCD_OPC_CheckField, 4, 1, 0, 44, 2, // Skip to: 1048 >+/* 492 */ MCD_OPC_Decode, 211, 5, 123, // Opcode: VCVTMNUD >+/* 496 */ MCD_OPC_FilterValue, 3, 36, 2, // Skip to: 1048 >+/* 500 */ MCD_OPC_CheckPredicate, 49, 32, 2, // Skip to: 1048 >+/* 504 */ MCD_OPC_CheckField, 23, 9, 231, 3, 25, 2, // Skip to: 1048 >+/* 511 */ MCD_OPC_CheckField, 16, 6, 59, 19, 2, // Skip to: 1048 >+/* 517 */ MCD_OPC_CheckField, 4, 1, 0, 13, 2, // Skip to: 1048 >+/* 523 */ MCD_OPC_Decode, 212, 5, 124, // Opcode: VCVTMNUQ >+/* 527 */ MCD_OPC_FilterValue, 4, 127, 0, // Skip to: 658 >+/* 531 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 534 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 565 >+/* 538 */ MCD_OPC_CheckPredicate, 49, 250, 1, // Skip to: 1048 >+/* 542 */ MCD_OPC_CheckField, 23, 9, 231, 3, 243, 1, // Skip to: 1048 >+/* 549 */ MCD_OPC_CheckField, 16, 6, 58, 237, 1, // Skip to: 1048 >+/* 555 */ MCD_OPC_CheckField, 4, 1, 0, 231, 1, // Skip to: 1048 >+/* 561 */ MCD_OPC_Decode, 150, 13, 123, // Opcode: VRINTNND >+/* 565 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 596 >+/* 569 */ MCD_OPC_CheckPredicate, 49, 219, 1, // Skip to: 1048 >+/* 573 */ MCD_OPC_CheckField, 23, 9, 231, 3, 212, 1, // Skip to: 1048 >+/* 580 */ MCD_OPC_CheckField, 16, 6, 58, 206, 1, // Skip to: 1048 >+/* 586 */ MCD_OPC_CheckField, 4, 1, 0, 200, 1, // Skip to: 1048 >+/* 592 */ MCD_OPC_Decode, 151, 13, 124, // Opcode: VRINTNNQ >+/* 596 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 627 >+/* 600 */ MCD_OPC_CheckPredicate, 49, 188, 1, // Skip to: 1048 >+/* 604 */ MCD_OPC_CheckField, 23, 9, 231, 3, 181, 1, // Skip to: 1048 >+/* 611 */ MCD_OPC_CheckField, 16, 6, 58, 175, 1, // Skip to: 1048 >+/* 617 */ MCD_OPC_CheckField, 4, 1, 0, 169, 1, // Skip to: 1048 >+/* 623 */ MCD_OPC_Decode, 160, 13, 123, // Opcode: VRINTXND >+/* 627 */ MCD_OPC_FilterValue, 3, 161, 1, // Skip to: 1048 >+/* 631 */ MCD_OPC_CheckPredicate, 49, 157, 1, // Skip to: 1048 >+/* 635 */ MCD_OPC_CheckField, 23, 9, 231, 3, 150, 1, // Skip to: 1048 >+/* 642 */ MCD_OPC_CheckField, 16, 6, 58, 144, 1, // Skip to: 1048 >+/* 648 */ MCD_OPC_CheckField, 4, 1, 0, 138, 1, // Skip to: 1048 >+/* 654 */ MCD_OPC_Decode, 161, 13, 124, // Opcode: VRINTXNQ >+/* 658 */ MCD_OPC_FilterValue, 5, 127, 0, // Skip to: 789 >+/* 662 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 665 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 696 >+/* 669 */ MCD_OPC_CheckPredicate, 49, 119, 1, // Skip to: 1048 >+/* 673 */ MCD_OPC_CheckField, 23, 9, 231, 3, 112, 1, // Skip to: 1048 >+/* 680 */ MCD_OPC_CheckField, 16, 6, 58, 106, 1, // Skip to: 1048 >+/* 686 */ MCD_OPC_CheckField, 4, 1, 0, 100, 1, // Skip to: 1048 >+/* 692 */ MCD_OPC_Decode, 142, 13, 123, // Opcode: VRINTAND >+/* 696 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 727 >+/* 700 */ MCD_OPC_CheckPredicate, 49, 88, 1, // Skip to: 1048 >+/* 704 */ MCD_OPC_CheckField, 23, 9, 231, 3, 81, 1, // Skip to: 1048 >+/* 711 */ MCD_OPC_CheckField, 16, 6, 58, 75, 1, // Skip to: 1048 >+/* 717 */ MCD_OPC_CheckField, 4, 1, 0, 69, 1, // Skip to: 1048 >+/* 723 */ MCD_OPC_Decode, 143, 13, 124, // Opcode: VRINTANQ >+/* 727 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 758 >+/* 731 */ MCD_OPC_CheckPredicate, 49, 57, 1, // Skip to: 1048 >+/* 735 */ MCD_OPC_CheckField, 23, 9, 231, 3, 50, 1, // Skip to: 1048 >+/* 742 */ MCD_OPC_CheckField, 16, 6, 58, 44, 1, // Skip to: 1048 >+/* 748 */ MCD_OPC_CheckField, 4, 1, 0, 38, 1, // Skip to: 1048 >+/* 754 */ MCD_OPC_Decode, 164, 13, 123, // Opcode: VRINTZND >+/* 758 */ MCD_OPC_FilterValue, 3, 30, 1, // Skip to: 1048 >+/* 762 */ MCD_OPC_CheckPredicate, 49, 26, 1, // Skip to: 1048 >+/* 766 */ MCD_OPC_CheckField, 23, 9, 231, 3, 19, 1, // Skip to: 1048 >+/* 773 */ MCD_OPC_CheckField, 16, 6, 58, 13, 1, // Skip to: 1048 >+/* 779 */ MCD_OPC_CheckField, 4, 1, 0, 7, 1, // Skip to: 1048 >+/* 785 */ MCD_OPC_Decode, 165, 13, 124, // Opcode: VRINTZNQ >+/* 789 */ MCD_OPC_FilterValue, 6, 65, 0, // Skip to: 858 >+/* 793 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 796 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 827 >+/* 800 */ MCD_OPC_CheckPredicate, 49, 244, 0, // Skip to: 1048 >+/* 804 */ MCD_OPC_CheckField, 23, 9, 231, 3, 237, 0, // Skip to: 1048 >+/* 811 */ MCD_OPC_CheckField, 16, 6, 58, 231, 0, // Skip to: 1048 >+/* 817 */ MCD_OPC_CheckField, 4, 1, 0, 225, 0, // Skip to: 1048 >+/* 823 */ MCD_OPC_Decode, 146, 13, 123, // Opcode: VRINTMND >+/* 827 */ MCD_OPC_FilterValue, 3, 217, 0, // Skip to: 1048 >+/* 831 */ MCD_OPC_CheckPredicate, 49, 213, 0, // Skip to: 1048 >+/* 835 */ MCD_OPC_CheckField, 23, 9, 231, 3, 206, 0, // Skip to: 1048 >+/* 842 */ MCD_OPC_CheckField, 16, 6, 58, 200, 0, // Skip to: 1048 >+/* 848 */ MCD_OPC_CheckField, 4, 1, 0, 194, 0, // Skip to: 1048 >+/* 854 */ MCD_OPC_Decode, 147, 13, 124, // Opcode: VRINTMNQ >+/* 858 */ MCD_OPC_FilterValue, 7, 65, 0, // Skip to: 927 >+/* 862 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ... >+/* 865 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 896 >+/* 869 */ MCD_OPC_CheckPredicate, 49, 175, 0, // Skip to: 1048 >+/* 873 */ MCD_OPC_CheckField, 23, 9, 231, 3, 168, 0, // Skip to: 1048 >+/* 880 */ MCD_OPC_CheckField, 16, 6, 58, 162, 0, // Skip to: 1048 >+/* 886 */ MCD_OPC_CheckField, 4, 1, 0, 156, 0, // Skip to: 1048 >+/* 892 */ MCD_OPC_Decode, 154, 13, 123, // Opcode: VRINTPND >+/* 896 */ MCD_OPC_FilterValue, 3, 148, 0, // Skip to: 1048 >+/* 900 */ MCD_OPC_CheckPredicate, 49, 144, 0, // Skip to: 1048 >+/* 904 */ MCD_OPC_CheckField, 23, 9, 231, 3, 137, 0, // Skip to: 1048 >+/* 911 */ MCD_OPC_CheckField, 16, 6, 58, 131, 0, // Skip to: 1048 >+/* 917 */ MCD_OPC_CheckField, 4, 1, 0, 125, 0, // Skip to: 1048 >+/* 923 */ MCD_OPC_Decode, 155, 13, 124, // Opcode: VRINTPNQ >+/* 927 */ MCD_OPC_FilterValue, 15, 117, 0, // Skip to: 1048 >+/* 931 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ... >+/* 934 */ MCD_OPC_FilterValue, 0, 53, 0, // Skip to: 991 >+/* 938 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 941 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 966 >+/* 945 */ MCD_OPC_CheckPredicate, 49, 99, 0, // Skip to: 1048 >+/* 949 */ MCD_OPC_CheckField, 23, 9, 230, 3, 92, 0, // Skip to: 1048 >+/* 956 */ MCD_OPC_CheckField, 4, 1, 1, 86, 0, // Skip to: 1048 >+/* 962 */ MCD_OPC_Decode, 232, 9, 94, // Opcode: VMAXNMND >+/* 966 */ MCD_OPC_FilterValue, 2, 78, 0, // Skip to: 1048 >+/* 970 */ MCD_OPC_CheckPredicate, 49, 74, 0, // Skip to: 1048 >+/* 974 */ MCD_OPC_CheckField, 23, 9, 230, 3, 67, 0, // Skip to: 1048 >+/* 981 */ MCD_OPC_CheckField, 4, 1, 1, 61, 0, // Skip to: 1048 >+/* 987 */ MCD_OPC_Decode, 250, 9, 94, // Opcode: VMINNMND >+/* 991 */ MCD_OPC_FilterValue, 1, 53, 0, // Skip to: 1048 >+/* 995 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... >+/* 998 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1023 >+/* 1002 */ MCD_OPC_CheckPredicate, 49, 42, 0, // Skip to: 1048 >+/* 1006 */ MCD_OPC_CheckField, 23, 9, 230, 3, 35, 0, // Skip to: 1048 >+/* 1013 */ MCD_OPC_CheckField, 4, 1, 1, 29, 0, // Skip to: 1048 >+/* 1019 */ MCD_OPC_Decode, 233, 9, 95, // Opcode: VMAXNMNQ >+/* 1023 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 1048 >+/* 1027 */ MCD_OPC_CheckPredicate, 49, 17, 0, // Skip to: 1048 >+/* 1031 */ MCD_OPC_CheckField, 23, 9, 230, 3, 10, 0, // Skip to: 1048 >+/* 1038 */ MCD_OPC_CheckField, 4, 1, 1, 4, 0, // Skip to: 1048 >+/* 1044 */ MCD_OPC_Decode, 251, 9, 95, // Opcode: VMINNMNQ >+/* 1048 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static bool getbool(uint64_t b) >+{ >+ return b != 0; >+} >+ >+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) >+{ >+ switch (Idx) { >+ default: // llvm_unreachable("Invalid index!"); >+ case 0: >+ return getbool(!(Bits & ARM_ModeThumb)); >+ case 1: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops)); >+ case 2: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC)); >+ case 3: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TEOps)); >+ case 4: >+ return getbool(!(Bits & ARM_HasV8Ops)); >+ case 5: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops)); >+ case 6: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV4TOps)); >+ case 7: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps)); >+ case 8: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureTrustZone)); >+ case 9: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6T2Ops)); >+ case 10: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops)); >+ case 11: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP)); >+ case 12: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB)); >+ case 13: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureHWDivARM)); >+ case 14: >+ return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureNaClTrap)); >+ case 15: >+ return getbool((Bits & ARM_FeatureNEON)); >+ case 16: >+ return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCrypto)); >+ case 17: >+ return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureFP16)); >+ case 18: >+ return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureVFP4)); >+ case 19: >+ return getbool((Bits & ARM_ModeThumb)); >+ case 20: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps)); >+ case 21: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops)); >+ case 22: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 23: >+ return getbool(!(Bits & ARM_FeatureMClass)); >+ case 24: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops)); >+ case 25: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6MOps)); >+ case 26: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps) && !(Bits & ARM_FeatureMClass)); >+ case 27: >+ return getbool((Bits & ARM_FeatureT2XtPk) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 28: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_HasV8Ops)); >+ case 29: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureDSPThumb2)); >+ case 30: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops)); >+ case 31: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB)); >+ case 32: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_FeatureMClass)); >+ case 33: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureMClass)); >+ case 34: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops)); >+ case 35: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureTrustZone)); >+ case 36: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP)); >+ case 37: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureT2XtPk)); >+ case 38: >+ return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC)); >+ case 39: >+ return getbool((Bits & ARM_FeatureHWDiv) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 40: >+ return getbool(!(Bits & ARM_HasV8Ops) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2)); >+ case 41: >+ return getbool((Bits & ARM_FeatureVFP2)); >+ case 42: >+ return getbool((Bits & ARM_FeatureVFP2) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 43: >+ return getbool((Bits & ARM_FeatureVFP4)); >+ case 44: >+ return getbool((Bits & ARM_FeatureVFP4) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 45: >+ return getbool((Bits & ARM_FeatureVFP3)); >+ case 46: >+ return getbool((Bits & ARM_FeatureFPARMv8)); >+ case 47: >+ return getbool((Bits & ARM_FeatureVFP3) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 48: >+ return getbool((Bits & ARM_FeatureFPARMv8) && !(Bits & ARM_FeatureVFPOnlySP)); >+ case 49: >+ return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureNEON)); >+ } >+} >+ >+#define DecodeToMCInst(fname,fieldname, InsnType) \ >+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ >+ uint64_t Address, const void *Decoder) \ >+{ \ >+ InsnType tmp; \ >+ switch (Idx) { \ >+ default: \ >+ case 0: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 1: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 2: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 2) << 5); \ >+ tmp |= (fieldname(insn, 8, 4) << 8); \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 3: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 2) << 5); \ >+ tmp |= (fieldname(insn, 8, 4) << 8); \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 4: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 5: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 6: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 7: \ >+ if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 8: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 9: \ >+ if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 10: \ >+ tmp = fieldname(insn, 9, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 11: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 12: \ >+ if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 13: \ >+ if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 14: \ >+ if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 15: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 8, 12) << 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 16: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 17: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 18: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 2) << 5); \ >+ tmp |= (fieldname(insn, 8, 4) << 8); \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 19: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 20: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 21: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 22: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 23: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 24: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 25: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 26: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 27: \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 28: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 29: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 30: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 31: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 32: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 33: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 34: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 2) << 5); \ >+ tmp |= (fieldname(insn, 8, 4) << 8); \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 35: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 2) << 5); \ >+ tmp |= (fieldname(insn, 8, 4) << 8); \ >+ if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 36: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 37: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 38: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 39: \ >+ if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 40: \ >+ if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 41: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 23, 1) << 4); \ >+ if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 42: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 8, 4) << 4); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 43: \ >+ if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 44: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 8, 4) << 4); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 45: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ if (!Check(&S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 46: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 22, 2) << 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 47: \ >+ if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 48: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ if (!Check(&S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 49: \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 50: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ if (!Check(&S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 51: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 12); \ >+ if (!Check(&S, DecodeSOImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 52: \ >+ if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 53: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 54: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 55: \ >+ if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 56: \ >+ if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 57: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 58: \ >+ return S; \ >+ case 59: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 60: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 61: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 62: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 63: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 64: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 7, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 65: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 66: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 67: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 68: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 69: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 70: \ >+ if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 71: \ >+ if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 72: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 1) << 5); \ >+ tmp |= (fieldname(insn, 7, 5) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 73: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 74: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 7, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 75: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 7) << 5); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ tmp |= (fieldname(insn, 23, 1) << 12); \ >+ if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 76: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 5) << 0); \ >+ tmp |= (fieldname(insn, 16, 5) << 5); \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 77: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 5) << 0); \ >+ tmp |= (fieldname(insn, 16, 5) << 5); \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 78: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 79: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 80: \ >+ if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 81: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 82: \ >+ if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 83: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 24) << 1); \ >+ tmp |= (fieldname(insn, 24, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 84: \ >+ if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 85: \ >+ if (!Check(&S, DecodeMRRC2(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 86: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 87: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 88: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 89: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 90: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 91: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 92: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 5, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 93: \ >+ tmp = fieldname(insn, 0, 24); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 94: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 95: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 96: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 97: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 98: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 99: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 100: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 101: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 102: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 103: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 104: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 105: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 106: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 107: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 108: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 109: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 1) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 110: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 111: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 112: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 113: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 114: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 115: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 116: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 117: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 9, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 118: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 119: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 120: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 10, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 121: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 9, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 122: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 123: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 124: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 125: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 126: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 127: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 128: \ >+ if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 129: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 130: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 131: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 132: \ >+ if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 133: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 134: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 135: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 136: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 19, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 137: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 138: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 17, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 139: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 140: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 141: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 142: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 143: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 144: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 145: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 146: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 147: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 148: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 149: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 150: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 151: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 152: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 153: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 154: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 155: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 156: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 157: \ >+ if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 158: \ >+ if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 159: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 160: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 161: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 162: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 163: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 164: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 165: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 166: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 167: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 168: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 169: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 170: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 171: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 172: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 173: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 174: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 175: \ >+ if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 176: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 177: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 178: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 179: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 180: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 181: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 182: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 1) << 0); \ >+ tmp |= (fieldname(insn, 21, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 183: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 1) << 0); \ >+ tmp |= (fieldname(insn, 21, 1) << 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 184: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 5, 2) << 0); \ >+ tmp |= (fieldname(insn, 21, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 185: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 5, 2) << 0); \ >+ tmp |= (fieldname(insn, 21, 1) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 186: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 187: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 188: \ >+ if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 189: \ >+ if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 190: \ >+ if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 191: \ >+ if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 192: \ >+ if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 193: \ >+ if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 194: \ >+ if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 195: \ >+ if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 196: \ >+ if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 197: \ >+ if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 198: \ >+ if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 199: \ >+ if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 200: \ >+ if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 201: \ >+ if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 202: \ >+ if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 203: \ >+ if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 204: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 205: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 206: \ >+ if (!Check(&S, DecodeThumbAddSPReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 207: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 3) << 0); \ >+ tmp |= (fieldname(insn, 7, 1) << 3); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 3) << 0); \ >+ tmp |= (fieldname(insn, 7, 1) << 3); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 208: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 3) << 0); \ >+ tmp |= (fieldname(insn, 7, 1) << 3); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 209: \ >+ tmp = fieldname(insn, 3, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 210: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 211: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 6); \ >+ if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 212: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 8); \ >+ if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 213: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 214: \ >+ if (!Check(&S, DecodeThumbAddSpecialReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 215: \ >+ if (!Check(&S, DecodeThumbAddSPImm(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 216: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 5) << 0); \ >+ tmp |= (fieldname(insn, 9, 1) << 5); \ >+ if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 217: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 8, 1) << 14); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 218: \ >+ tmp = fieldname(insn, 3, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 219: \ >+ if (!Check(&S, DecodeThumbCPS(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 220: \ >+ tmp = fieldname(insn, 0, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 221: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 8, 1) << 15); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 222: \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 223: \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 224: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 225: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 226: \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 227: \ >+ tmp = fieldname(insn, 0, 11); \ >+ if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 228: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 1, 10) << 1); \ >+ tmp |= (fieldname(insn, 11, 1) << 21); \ >+ tmp |= (fieldname(insn, 13, 1) << 22); \ >+ tmp |= (fieldname(insn, 16, 10) << 11); \ >+ tmp |= (fieldname(insn, 26, 1) << 23); \ >+ if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 229: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 11) << 0); \ >+ tmp |= (fieldname(insn, 11, 1) << 21); \ >+ tmp |= (fieldname(insn, 13, 1) << 22); \ >+ tmp |= (fieldname(insn, 16, 10) << 11); \ >+ tmp |= (fieldname(insn, 26, 1) << 23); \ >+ if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 230: \ >+ if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 231: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 13) << 0); \ >+ tmp |= (fieldname(insn, 14, 1) << 14); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 232: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 233: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 13) << 0); \ >+ tmp |= (fieldname(insn, 14, 1) << 14); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 234: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 235: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 8); \ >+ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 236: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 237: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 238: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 239: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 8); \ >+ if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 240: \ >+ if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 241: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 242: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 243: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 244: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 245: \ >+ if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 246: \ >+ if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 247: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 248: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 4, 4) << 5); \ >+ tmp |= (fieldname(insn, 12, 3) << 9); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 249: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 250: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 4, 4) << 5); \ >+ tmp |= (fieldname(insn, 12, 3) << 9); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 251: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 252: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 253: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 254: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 4, 4) << 5); \ >+ tmp |= (fieldname(insn, 12, 3) << 9); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 255: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 256: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 257: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 4, 4) << 5); \ >+ tmp |= (fieldname(insn, 12, 3) << 9); \ >+ if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 258: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 259: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 8); \ >+ tmp |= (fieldname(insn, 26, 1) << 11); \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 260: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 8); \ >+ tmp |= (fieldname(insn, 26, 1) << 11); \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 261: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 8); \ >+ tmp |= (fieldname(insn, 26, 1) << 11); \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 262: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 8); \ >+ tmp |= (fieldname(insn, 26, 1) << 11); \ >+ if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 1); \ >+ if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 263: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 8); \ >+ tmp |= (fieldname(insn, 26, 1) << 11); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 264: \ >+ if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 265: \ >+ if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 266: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 267: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ tmp |= (fieldname(insn, 21, 1) << 5); \ >+ if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 268: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 269: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 5) << 5); \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 270: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 5) << 5); \ >+ tmp |= (fieldname(insn, 6, 2) << 0); \ >+ tmp |= (fieldname(insn, 12, 3) << 2); \ >+ if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 271: \ >+ tmp = fieldname(insn, 0, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 272: \ >+ if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 273: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 274: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 275: \ >+ tmp = fieldname(insn, 0, 12); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 276: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 277: \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 278: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 12); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 279: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 8, 4) << 0); \ >+ tmp |= (fieldname(insn, 20, 1) << 4); \ >+ if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 280: \ >+ if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 281: \ >+ if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 282: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 2); \ >+ tmp |= (fieldname(insn, 4, 2) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 6); \ >+ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 283: \ >+ if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 284: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 285: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 9, 1) << 8); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 286: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 287: \ >+ if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 288: \ >+ if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 289: \ >+ if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 290: \ >+ if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 291: \ >+ if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 292: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 2); \ >+ tmp |= (fieldname(insn, 4, 2) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 6); \ >+ if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 293: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 9, 1) << 8); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 294: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 12) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 13); \ >+ if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 295: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 296: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 4, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 297: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 298: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 299: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 300: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 301: \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 302: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 303: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 304: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 305: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 306: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 307: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 308: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 309: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 310: \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 3, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 311: \ >+ if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 312: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 4) << 9); \ >+ tmp |= (fieldname(insn, 22, 1) << 8); \ >+ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 313: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 314: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 1, 7) << 1); \ >+ tmp |= (fieldname(insn, 12, 4) << 8); \ >+ tmp |= (fieldname(insn, 22, 1) << 12); \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 315: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 1, 7) << 1); \ >+ tmp |= (fieldname(insn, 12, 4) << 8); \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 316: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 317: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 9); \ >+ tmp |= (fieldname(insn, 23, 1) << 8); \ >+ if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 318: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 1); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 319: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 1); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 320: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 321: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 4); \ >+ tmp |= (fieldname(insn, 16, 4) << 0); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 322: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 1); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 323: \ >+ if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 324: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 325: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 1); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 326: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 8) << 0); \ >+ tmp |= (fieldname(insn, 12, 4) << 9); \ >+ tmp |= (fieldname(insn, 22, 1) << 8); \ >+ if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 327: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 1, 7) << 1); \ >+ tmp |= (fieldname(insn, 12, 4) << 8); \ >+ tmp |= (fieldname(insn, 22, 1) << 12); \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 328: \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 1, 7) << 1); \ >+ tmp |= (fieldname(insn, 12, 4) << 8); \ >+ if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 329: \ >+ tmp = fieldname(insn, 12, 4); \ >+ if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 330: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 331: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 332: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 333: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 334: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 335: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 336: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 337: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 338: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 339: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 0); \ >+ tmp |= (fieldname(insn, 22, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 28, 4); \ >+ if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 340: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 1) << 0); \ >+ tmp |= (fieldname(insn, 16, 4) << 1); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 341: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 1); \ >+ tmp |= (fieldname(insn, 5, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ case 342: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 12, 4) << 1); \ >+ tmp |= (fieldname(insn, 22, 1) << 0); \ >+ if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 4) << 0); \ >+ tmp |= (fieldname(insn, 5, 1) << 4); \ >+ if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ >+ return S; \ >+ } \ >+} >+ >+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ >+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ >+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ >+{ \ >+ uint64_t Bits = ARM_getFeatureBits(feature); \ >+ const uint8_t *Ptr = DecodeTable; \ >+ uint32_t CurFieldValue = 0, ExpectedValue; \ >+ DecodeStatus S = MCDisassembler_Success; \ >+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ >+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ >+ bool Pred, Fail; \ >+ for (;;) { \ >+ switch (*Ptr) { \ >+ default: \ >+ return MCDisassembler_Fail; \ >+ case MCD_OPC_ExtractField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ ++Ptr; \ >+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ >+ break; \ >+ } \ >+ case MCD_OPC_FilterValue: { \ >+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (Val != CurFieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ FieldValue = fieldname(insn, Start, Len); \ >+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (ExpectedValue != FieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckPredicate: { \ >+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ Pred = checkDecoderPredicate(PIdx, Bits); \ >+ if (!Pred) \ >+ Ptr += NumToSkip; \ >+ (void)Pred; \ >+ break; \ >+ } \ >+ case MCD_OPC_Decode: { \ >+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ MCInst_setOpcode(MI, Opc); \ >+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ >+ } \ >+ case MCD_OPC_SoftFail: { \ >+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ >+ if (Fail) \ >+ S = MCDisassembler_SoftFail; \ >+ break; \ >+ } \ >+ case MCD_OPC_Fail: { \ >+ return MCDisassembler_Fail; \ >+ } \ >+ } \ >+ } \ >+} >+ >+FieldFromInstruction(fieldFromInstruction_2, uint16_t) >+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t) >+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t) >+FieldFromInstruction(fieldFromInstruction_4, uint32_t) >+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) >+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..69296581ab583f914e875de2ae431e37430741a1 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenInstrInfo.inc >@@ -0,0 +1,5987 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Instruction Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_INSTRINFO_ENUM >+#undef GET_INSTRINFO_ENUM >+ >+enum { >+ ARM_PHI = 0, >+ ARM_INLINEASM = 1, >+ ARM_CFI_INSTRUCTION = 2, >+ ARM_EH_LABEL = 3, >+ ARM_GC_LABEL = 4, >+ ARM_KILL = 5, >+ ARM_EXTRACT_SUBREG = 6, >+ ARM_INSERT_SUBREG = 7, >+ ARM_IMPLICIT_DEF = 8, >+ ARM_SUBREG_TO_REG = 9, >+ ARM_COPY_TO_REGCLASS = 10, >+ ARM_DBG_VALUE = 11, >+ ARM_REG_SEQUENCE = 12, >+ ARM_COPY = 13, >+ ARM_BUNDLE = 14, >+ ARM_LIFETIME_START = 15, >+ ARM_LIFETIME_END = 16, >+ ARM_STACKMAP = 17, >+ ARM_PATCHPOINT = 18, >+ ARM_LOAD_STACK_GUARD = 19, >+ ARM_ABS = 20, >+ ARM_ADCri = 21, >+ ARM_ADCrr = 22, >+ ARM_ADCrsi = 23, >+ ARM_ADCrsr = 24, >+ ARM_ADDSri = 25, >+ ARM_ADDSrr = 26, >+ ARM_ADDSrsi = 27, >+ ARM_ADDSrsr = 28, >+ ARM_ADDri = 29, >+ ARM_ADDrr = 30, >+ ARM_ADDrsi = 31, >+ ARM_ADDrsr = 32, >+ ARM_ADJCALLSTACKDOWN = 33, >+ ARM_ADJCALLSTACKUP = 34, >+ ARM_ADR = 35, >+ ARM_AESD = 36, >+ ARM_AESE = 37, >+ ARM_AESIMC = 38, >+ ARM_AESMC = 39, >+ ARM_ANDri = 40, >+ ARM_ANDrr = 41, >+ ARM_ANDrsi = 42, >+ ARM_ANDrsr = 43, >+ ARM_ASRi = 44, >+ ARM_ASRr = 45, >+ ARM_B = 46, >+ ARM_BCCZi64 = 47, >+ ARM_BCCi64 = 48, >+ ARM_BFC = 49, >+ ARM_BFI = 50, >+ ARM_BICri = 51, >+ ARM_BICrr = 52, >+ ARM_BICrsi = 53, >+ ARM_BICrsr = 54, >+ ARM_BKPT = 55, >+ ARM_BL = 56, >+ ARM_BLX = 57, >+ ARM_BLX_pred = 58, >+ ARM_BLXi = 59, >+ ARM_BL_pred = 60, >+ ARM_BMOVPCB_CALL = 61, >+ ARM_BMOVPCRX_CALL = 62, >+ ARM_BR_JTadd = 63, >+ ARM_BR_JTm = 64, >+ ARM_BR_JTr = 65, >+ ARM_BX = 66, >+ ARM_BXJ = 67, >+ ARM_BX_CALL = 68, >+ ARM_BX_RET = 69, >+ ARM_BX_pred = 70, >+ ARM_Bcc = 71, >+ ARM_CDP = 72, >+ ARM_CDP2 = 73, >+ ARM_CLREX = 74, >+ ARM_CLZ = 75, >+ ARM_CMNri = 76, >+ ARM_CMNzrr = 77, >+ ARM_CMNzrsi = 78, >+ ARM_CMNzrsr = 79, >+ ARM_CMPri = 80, >+ ARM_CMPrr = 81, >+ ARM_CMPrsi = 82, >+ ARM_CMPrsr = 83, >+ ARM_CONSTPOOL_ENTRY = 84, >+ ARM_COPY_STRUCT_BYVAL_I32 = 85, >+ ARM_CPS1p = 86, >+ ARM_CPS2p = 87, >+ ARM_CPS3p = 88, >+ ARM_CRC32B = 89, >+ ARM_CRC32CB = 90, >+ ARM_CRC32CH = 91, >+ ARM_CRC32CW = 92, >+ ARM_CRC32H = 93, >+ ARM_CRC32W = 94, >+ ARM_DBG = 95, >+ ARM_DMB = 96, >+ ARM_DSB = 97, >+ ARM_EORri = 98, >+ ARM_EORrr = 99, >+ ARM_EORrsi = 100, >+ ARM_EORrsr = 101, >+ ARM_FCONSTD = 102, >+ ARM_FCONSTS = 103, >+ ARM_FLDMXDB_UPD = 104, >+ ARM_FLDMXIA = 105, >+ ARM_FLDMXIA_UPD = 106, >+ ARM_FMSTAT = 107, >+ ARM_FSTMXDB_UPD = 108, >+ ARM_FSTMXIA = 109, >+ ARM_FSTMXIA_UPD = 110, >+ ARM_HINT = 111, >+ ARM_HLT = 112, >+ ARM_ISB = 113, >+ ARM_ITasm = 114, >+ ARM_Int_eh_sjlj_dispatchsetup = 115, >+ ARM_Int_eh_sjlj_longjmp = 116, >+ ARM_Int_eh_sjlj_setjmp = 117, >+ ARM_Int_eh_sjlj_setjmp_nofp = 118, >+ ARM_LDA = 119, >+ ARM_LDAB = 120, >+ ARM_LDAEX = 121, >+ ARM_LDAEXB = 122, >+ ARM_LDAEXD = 123, >+ ARM_LDAEXH = 124, >+ ARM_LDAH = 125, >+ ARM_LDC2L_OFFSET = 126, >+ ARM_LDC2L_OPTION = 127, >+ ARM_LDC2L_POST = 128, >+ ARM_LDC2L_PRE = 129, >+ ARM_LDC2_OFFSET = 130, >+ ARM_LDC2_OPTION = 131, >+ ARM_LDC2_POST = 132, >+ ARM_LDC2_PRE = 133, >+ ARM_LDCL_OFFSET = 134, >+ ARM_LDCL_OPTION = 135, >+ ARM_LDCL_POST = 136, >+ ARM_LDCL_PRE = 137, >+ ARM_LDC_OFFSET = 138, >+ ARM_LDC_OPTION = 139, >+ ARM_LDC_POST = 140, >+ ARM_LDC_PRE = 141, >+ ARM_LDMDA = 142, >+ ARM_LDMDA_UPD = 143, >+ ARM_LDMDB = 144, >+ ARM_LDMDB_UPD = 145, >+ ARM_LDMIA = 146, >+ ARM_LDMIA_RET = 147, >+ ARM_LDMIA_UPD = 148, >+ ARM_LDMIB = 149, >+ ARM_LDMIB_UPD = 150, >+ ARM_LDRBT_POST = 151, >+ ARM_LDRBT_POST_IMM = 152, >+ ARM_LDRBT_POST_REG = 153, >+ ARM_LDRB_POST_IMM = 154, >+ ARM_LDRB_POST_REG = 155, >+ ARM_LDRB_PRE_IMM = 156, >+ ARM_LDRB_PRE_REG = 157, >+ ARM_LDRBi12 = 158, >+ ARM_LDRBrs = 159, >+ ARM_LDRD = 160, >+ ARM_LDRD_POST = 161, >+ ARM_LDRD_PRE = 162, >+ ARM_LDREX = 163, >+ ARM_LDREXB = 164, >+ ARM_LDREXD = 165, >+ ARM_LDREXH = 166, >+ ARM_LDRH = 167, >+ ARM_LDRHTi = 168, >+ ARM_LDRHTr = 169, >+ ARM_LDRH_POST = 170, >+ ARM_LDRH_PRE = 171, >+ ARM_LDRLIT_ga_abs = 172, >+ ARM_LDRLIT_ga_pcrel = 173, >+ ARM_LDRLIT_ga_pcrel_ldr = 174, >+ ARM_LDRSB = 175, >+ ARM_LDRSBTi = 176, >+ ARM_LDRSBTr = 177, >+ ARM_LDRSB_POST = 178, >+ ARM_LDRSB_PRE = 179, >+ ARM_LDRSH = 180, >+ ARM_LDRSHTi = 181, >+ ARM_LDRSHTr = 182, >+ ARM_LDRSH_POST = 183, >+ ARM_LDRSH_PRE = 184, >+ ARM_LDRT_POST = 185, >+ ARM_LDRT_POST_IMM = 186, >+ ARM_LDRT_POST_REG = 187, >+ ARM_LDR_POST_IMM = 188, >+ ARM_LDR_POST_REG = 189, >+ ARM_LDR_PRE_IMM = 190, >+ ARM_LDR_PRE_REG = 191, >+ ARM_LDRcp = 192, >+ ARM_LDRi12 = 193, >+ ARM_LDRrs = 194, >+ ARM_LEApcrel = 195, >+ ARM_LEApcrelJT = 196, >+ ARM_LSLi = 197, >+ ARM_LSLr = 198, >+ ARM_LSRi = 199, >+ ARM_LSRr = 200, >+ ARM_MCR = 201, >+ ARM_MCR2 = 202, >+ ARM_MCRR = 203, >+ ARM_MCRR2 = 204, >+ ARM_MLA = 205, >+ ARM_MLAv5 = 206, >+ ARM_MLS = 207, >+ ARM_MOVCCi = 208, >+ ARM_MOVCCi16 = 209, >+ ARM_MOVCCi32imm = 210, >+ ARM_MOVCCr = 211, >+ ARM_MOVCCsi = 212, >+ ARM_MOVCCsr = 213, >+ ARM_MOVPCLR = 214, >+ ARM_MOVPCRX = 215, >+ ARM_MOVTi16 = 216, >+ ARM_MOVTi16_ga_pcrel = 217, >+ ARM_MOV_ga_pcrel = 218, >+ ARM_MOV_ga_pcrel_ldr = 219, >+ ARM_MOVi = 220, >+ ARM_MOVi16 = 221, >+ ARM_MOVi16_ga_pcrel = 222, >+ ARM_MOVi32imm = 223, >+ ARM_MOVr = 224, >+ ARM_MOVr_TC = 225, >+ ARM_MOVsi = 226, >+ ARM_MOVsr = 227, >+ ARM_MOVsra_flag = 228, >+ ARM_MOVsrl_flag = 229, >+ ARM_MRC = 230, >+ ARM_MRC2 = 231, >+ ARM_MRRC = 232, >+ ARM_MRRC2 = 233, >+ ARM_MRS = 234, >+ ARM_MRSsys = 235, >+ ARM_MSR = 236, >+ ARM_MSRi = 237, >+ ARM_MUL = 238, >+ ARM_MULv5 = 239, >+ ARM_MVNCCi = 240, >+ ARM_MVNi = 241, >+ ARM_MVNr = 242, >+ ARM_MVNsi = 243, >+ ARM_MVNsr = 244, >+ ARM_ORRri = 245, >+ ARM_ORRrr = 246, >+ ARM_ORRrsi = 247, >+ ARM_ORRrsr = 248, >+ ARM_PICADD = 249, >+ ARM_PICLDR = 250, >+ ARM_PICLDRB = 251, >+ ARM_PICLDRH = 252, >+ ARM_PICLDRSB = 253, >+ ARM_PICLDRSH = 254, >+ ARM_PICSTR = 255, >+ ARM_PICSTRB = 256, >+ ARM_PICSTRH = 257, >+ ARM_PKHBT = 258, >+ ARM_PKHTB = 259, >+ ARM_PLDWi12 = 260, >+ ARM_PLDWrs = 261, >+ ARM_PLDi12 = 262, >+ ARM_PLDrs = 263, >+ ARM_PLIi12 = 264, >+ ARM_PLIrs = 265, >+ ARM_QADD = 266, >+ ARM_QADD16 = 267, >+ ARM_QADD8 = 268, >+ ARM_QASX = 269, >+ ARM_QDADD = 270, >+ ARM_QDSUB = 271, >+ ARM_QSAX = 272, >+ ARM_QSUB = 273, >+ ARM_QSUB16 = 274, >+ ARM_QSUB8 = 275, >+ ARM_RBIT = 276, >+ ARM_REV = 277, >+ ARM_REV16 = 278, >+ ARM_REVSH = 279, >+ ARM_RFEDA = 280, >+ ARM_RFEDA_UPD = 281, >+ ARM_RFEDB = 282, >+ ARM_RFEDB_UPD = 283, >+ ARM_RFEIA = 284, >+ ARM_RFEIA_UPD = 285, >+ ARM_RFEIB = 286, >+ ARM_RFEIB_UPD = 287, >+ ARM_RORi = 288, >+ ARM_RORr = 289, >+ ARM_RRX = 290, >+ ARM_RRXi = 291, >+ ARM_RSBSri = 292, >+ ARM_RSBSrsi = 293, >+ ARM_RSBSrsr = 294, >+ ARM_RSBri = 295, >+ ARM_RSBrr = 296, >+ ARM_RSBrsi = 297, >+ ARM_RSBrsr = 298, >+ ARM_RSCri = 299, >+ ARM_RSCrr = 300, >+ ARM_RSCrsi = 301, >+ ARM_RSCrsr = 302, >+ ARM_SADD16 = 303, >+ ARM_SADD8 = 304, >+ ARM_SASX = 305, >+ ARM_SBCri = 306, >+ ARM_SBCrr = 307, >+ ARM_SBCrsi = 308, >+ ARM_SBCrsr = 309, >+ ARM_SBFX = 310, >+ ARM_SDIV = 311, >+ ARM_SEL = 312, >+ ARM_SETEND = 313, >+ ARM_SHA1C = 314, >+ ARM_SHA1H = 315, >+ ARM_SHA1M = 316, >+ ARM_SHA1P = 317, >+ ARM_SHA1SU0 = 318, >+ ARM_SHA1SU1 = 319, >+ ARM_SHA256H = 320, >+ ARM_SHA256H2 = 321, >+ ARM_SHA256SU0 = 322, >+ ARM_SHA256SU1 = 323, >+ ARM_SHADD16 = 324, >+ ARM_SHADD8 = 325, >+ ARM_SHASX = 326, >+ ARM_SHSAX = 327, >+ ARM_SHSUB16 = 328, >+ ARM_SHSUB8 = 329, >+ ARM_SMC = 330, >+ ARM_SMLABB = 331, >+ ARM_SMLABT = 332, >+ ARM_SMLAD = 333, >+ ARM_SMLADX = 334, >+ ARM_SMLAL = 335, >+ ARM_SMLALBB = 336, >+ ARM_SMLALBT = 337, >+ ARM_SMLALD = 338, >+ ARM_SMLALDX = 339, >+ ARM_SMLALTB = 340, >+ ARM_SMLALTT = 341, >+ ARM_SMLALv5 = 342, >+ ARM_SMLATB = 343, >+ ARM_SMLATT = 344, >+ ARM_SMLAWB = 345, >+ ARM_SMLAWT = 346, >+ ARM_SMLSD = 347, >+ ARM_SMLSDX = 348, >+ ARM_SMLSLD = 349, >+ ARM_SMLSLDX = 350, >+ ARM_SMMLA = 351, >+ ARM_SMMLAR = 352, >+ ARM_SMMLS = 353, >+ ARM_SMMLSR = 354, >+ ARM_SMMUL = 355, >+ ARM_SMMULR = 356, >+ ARM_SMUAD = 357, >+ ARM_SMUADX = 358, >+ ARM_SMULBB = 359, >+ ARM_SMULBT = 360, >+ ARM_SMULL = 361, >+ ARM_SMULLv5 = 362, >+ ARM_SMULTB = 363, >+ ARM_SMULTT = 364, >+ ARM_SMULWB = 365, >+ ARM_SMULWT = 366, >+ ARM_SMUSD = 367, >+ ARM_SMUSDX = 368, >+ ARM_SRSDA = 369, >+ ARM_SRSDA_UPD = 370, >+ ARM_SRSDB = 371, >+ ARM_SRSDB_UPD = 372, >+ ARM_SRSIA = 373, >+ ARM_SRSIA_UPD = 374, >+ ARM_SRSIB = 375, >+ ARM_SRSIB_UPD = 376, >+ ARM_SSAT = 377, >+ ARM_SSAT16 = 378, >+ ARM_SSAX = 379, >+ ARM_SSUB16 = 380, >+ ARM_SSUB8 = 381, >+ ARM_STC2L_OFFSET = 382, >+ ARM_STC2L_OPTION = 383, >+ ARM_STC2L_POST = 384, >+ ARM_STC2L_PRE = 385, >+ ARM_STC2_OFFSET = 386, >+ ARM_STC2_OPTION = 387, >+ ARM_STC2_POST = 388, >+ ARM_STC2_PRE = 389, >+ ARM_STCL_OFFSET = 390, >+ ARM_STCL_OPTION = 391, >+ ARM_STCL_POST = 392, >+ ARM_STCL_PRE = 393, >+ ARM_STC_OFFSET = 394, >+ ARM_STC_OPTION = 395, >+ ARM_STC_POST = 396, >+ ARM_STC_PRE = 397, >+ ARM_STL = 398, >+ ARM_STLB = 399, >+ ARM_STLEX = 400, >+ ARM_STLEXB = 401, >+ ARM_STLEXD = 402, >+ ARM_STLEXH = 403, >+ ARM_STLH = 404, >+ ARM_STMDA = 405, >+ ARM_STMDA_UPD = 406, >+ ARM_STMDB = 407, >+ ARM_STMDB_UPD = 408, >+ ARM_STMIA = 409, >+ ARM_STMIA_UPD = 410, >+ ARM_STMIB = 411, >+ ARM_STMIB_UPD = 412, >+ ARM_STRBT_POST = 413, >+ ARM_STRBT_POST_IMM = 414, >+ ARM_STRBT_POST_REG = 415, >+ ARM_STRB_POST_IMM = 416, >+ ARM_STRB_POST_REG = 417, >+ ARM_STRB_PRE_IMM = 418, >+ ARM_STRB_PRE_REG = 419, >+ ARM_STRBi12 = 420, >+ ARM_STRBi_preidx = 421, >+ ARM_STRBr_preidx = 422, >+ ARM_STRBrs = 423, >+ ARM_STRD = 424, >+ ARM_STRD_POST = 425, >+ ARM_STRD_PRE = 426, >+ ARM_STREX = 427, >+ ARM_STREXB = 428, >+ ARM_STREXD = 429, >+ ARM_STREXH = 430, >+ ARM_STRH = 431, >+ ARM_STRHTi = 432, >+ ARM_STRHTr = 433, >+ ARM_STRH_POST = 434, >+ ARM_STRH_PRE = 435, >+ ARM_STRH_preidx = 436, >+ ARM_STRT_POST = 437, >+ ARM_STRT_POST_IMM = 438, >+ ARM_STRT_POST_REG = 439, >+ ARM_STR_POST_IMM = 440, >+ ARM_STR_POST_REG = 441, >+ ARM_STR_PRE_IMM = 442, >+ ARM_STR_PRE_REG = 443, >+ ARM_STRi12 = 444, >+ ARM_STRi_preidx = 445, >+ ARM_STRr_preidx = 446, >+ ARM_STRrs = 447, >+ ARM_SUBS_PC_LR = 448, >+ ARM_SUBSri = 449, >+ ARM_SUBSrr = 450, >+ ARM_SUBSrsi = 451, >+ ARM_SUBSrsr = 452, >+ ARM_SUBri = 453, >+ ARM_SUBrr = 454, >+ ARM_SUBrsi = 455, >+ ARM_SUBrsr = 456, >+ ARM_SVC = 457, >+ ARM_SWP = 458, >+ ARM_SWPB = 459, >+ ARM_SXTAB = 460, >+ ARM_SXTAB16 = 461, >+ ARM_SXTAH = 462, >+ ARM_SXTB = 463, >+ ARM_SXTB16 = 464, >+ ARM_SXTH = 465, >+ ARM_TAILJMPd = 466, >+ ARM_TAILJMPr = 467, >+ ARM_TCRETURNdi = 468, >+ ARM_TCRETURNri = 469, >+ ARM_TEQri = 470, >+ ARM_TEQrr = 471, >+ ARM_TEQrsi = 472, >+ ARM_TEQrsr = 473, >+ ARM_TPsoft = 474, >+ ARM_TRAP = 475, >+ ARM_TRAPNaCl = 476, >+ ARM_TSTri = 477, >+ ARM_TSTrr = 478, >+ ARM_TSTrsi = 479, >+ ARM_TSTrsr = 480, >+ ARM_UADD16 = 481, >+ ARM_UADD8 = 482, >+ ARM_UASX = 483, >+ ARM_UBFX = 484, >+ ARM_UDF = 485, >+ ARM_UDIV = 486, >+ ARM_UHADD16 = 487, >+ ARM_UHADD8 = 488, >+ ARM_UHASX = 489, >+ ARM_UHSAX = 490, >+ ARM_UHSUB16 = 491, >+ ARM_UHSUB8 = 492, >+ ARM_UMAAL = 493, >+ ARM_UMLAL = 494, >+ ARM_UMLALv5 = 495, >+ ARM_UMULL = 496, >+ ARM_UMULLv5 = 497, >+ ARM_UQADD16 = 498, >+ ARM_UQADD8 = 499, >+ ARM_UQASX = 500, >+ ARM_UQSAX = 501, >+ ARM_UQSUB16 = 502, >+ ARM_UQSUB8 = 503, >+ ARM_USAD8 = 504, >+ ARM_USADA8 = 505, >+ ARM_USAT = 506, >+ ARM_USAT16 = 507, >+ ARM_USAX = 508, >+ ARM_USUB16 = 509, >+ ARM_USUB8 = 510, >+ ARM_UXTAB = 511, >+ ARM_UXTAB16 = 512, >+ ARM_UXTAH = 513, >+ ARM_UXTB = 514, >+ ARM_UXTB16 = 515, >+ ARM_UXTH = 516, >+ ARM_VABALsv2i64 = 517, >+ ARM_VABALsv4i32 = 518, >+ ARM_VABALsv8i16 = 519, >+ ARM_VABALuv2i64 = 520, >+ ARM_VABALuv4i32 = 521, >+ ARM_VABALuv8i16 = 522, >+ ARM_VABAsv16i8 = 523, >+ ARM_VABAsv2i32 = 524, >+ ARM_VABAsv4i16 = 525, >+ ARM_VABAsv4i32 = 526, >+ ARM_VABAsv8i16 = 527, >+ ARM_VABAsv8i8 = 528, >+ ARM_VABAuv16i8 = 529, >+ ARM_VABAuv2i32 = 530, >+ ARM_VABAuv4i16 = 531, >+ ARM_VABAuv4i32 = 532, >+ ARM_VABAuv8i16 = 533, >+ ARM_VABAuv8i8 = 534, >+ ARM_VABDLsv2i64 = 535, >+ ARM_VABDLsv4i32 = 536, >+ ARM_VABDLsv8i16 = 537, >+ ARM_VABDLuv2i64 = 538, >+ ARM_VABDLuv4i32 = 539, >+ ARM_VABDLuv8i16 = 540, >+ ARM_VABDfd = 541, >+ ARM_VABDfq = 542, >+ ARM_VABDsv16i8 = 543, >+ ARM_VABDsv2i32 = 544, >+ ARM_VABDsv4i16 = 545, >+ ARM_VABDsv4i32 = 546, >+ ARM_VABDsv8i16 = 547, >+ ARM_VABDsv8i8 = 548, >+ ARM_VABDuv16i8 = 549, >+ ARM_VABDuv2i32 = 550, >+ ARM_VABDuv4i16 = 551, >+ ARM_VABDuv4i32 = 552, >+ ARM_VABDuv8i16 = 553, >+ ARM_VABDuv8i8 = 554, >+ ARM_VABSD = 555, >+ ARM_VABSS = 556, >+ ARM_VABSfd = 557, >+ ARM_VABSfq = 558, >+ ARM_VABSv16i8 = 559, >+ ARM_VABSv2i32 = 560, >+ ARM_VABSv4i16 = 561, >+ ARM_VABSv4i32 = 562, >+ ARM_VABSv8i16 = 563, >+ ARM_VABSv8i8 = 564, >+ ARM_VACGEd = 565, >+ ARM_VACGEq = 566, >+ ARM_VACGTd = 567, >+ ARM_VACGTq = 568, >+ ARM_VADDD = 569, >+ ARM_VADDHNv2i32 = 570, >+ ARM_VADDHNv4i16 = 571, >+ ARM_VADDHNv8i8 = 572, >+ ARM_VADDLsv2i64 = 573, >+ ARM_VADDLsv4i32 = 574, >+ ARM_VADDLsv8i16 = 575, >+ ARM_VADDLuv2i64 = 576, >+ ARM_VADDLuv4i32 = 577, >+ ARM_VADDLuv8i16 = 578, >+ ARM_VADDS = 579, >+ ARM_VADDWsv2i64 = 580, >+ ARM_VADDWsv4i32 = 581, >+ ARM_VADDWsv8i16 = 582, >+ ARM_VADDWuv2i64 = 583, >+ ARM_VADDWuv4i32 = 584, >+ ARM_VADDWuv8i16 = 585, >+ ARM_VADDfd = 586, >+ ARM_VADDfq = 587, >+ ARM_VADDv16i8 = 588, >+ ARM_VADDv1i64 = 589, >+ ARM_VADDv2i32 = 590, >+ ARM_VADDv2i64 = 591, >+ ARM_VADDv4i16 = 592, >+ ARM_VADDv4i32 = 593, >+ ARM_VADDv8i16 = 594, >+ ARM_VADDv8i8 = 595, >+ ARM_VANDd = 596, >+ ARM_VANDq = 597, >+ ARM_VBICd = 598, >+ ARM_VBICiv2i32 = 599, >+ ARM_VBICiv4i16 = 600, >+ ARM_VBICiv4i32 = 601, >+ ARM_VBICiv8i16 = 602, >+ ARM_VBICq = 603, >+ ARM_VBIFd = 604, >+ ARM_VBIFq = 605, >+ ARM_VBITd = 606, >+ ARM_VBITq = 607, >+ ARM_VBSLd = 608, >+ ARM_VBSLq = 609, >+ ARM_VCEQfd = 610, >+ ARM_VCEQfq = 611, >+ ARM_VCEQv16i8 = 612, >+ ARM_VCEQv2i32 = 613, >+ ARM_VCEQv4i16 = 614, >+ ARM_VCEQv4i32 = 615, >+ ARM_VCEQv8i16 = 616, >+ ARM_VCEQv8i8 = 617, >+ ARM_VCEQzv16i8 = 618, >+ ARM_VCEQzv2f32 = 619, >+ ARM_VCEQzv2i32 = 620, >+ ARM_VCEQzv4f32 = 621, >+ ARM_VCEQzv4i16 = 622, >+ ARM_VCEQzv4i32 = 623, >+ ARM_VCEQzv8i16 = 624, >+ ARM_VCEQzv8i8 = 625, >+ ARM_VCGEfd = 626, >+ ARM_VCGEfq = 627, >+ ARM_VCGEsv16i8 = 628, >+ ARM_VCGEsv2i32 = 629, >+ ARM_VCGEsv4i16 = 630, >+ ARM_VCGEsv4i32 = 631, >+ ARM_VCGEsv8i16 = 632, >+ ARM_VCGEsv8i8 = 633, >+ ARM_VCGEuv16i8 = 634, >+ ARM_VCGEuv2i32 = 635, >+ ARM_VCGEuv4i16 = 636, >+ ARM_VCGEuv4i32 = 637, >+ ARM_VCGEuv8i16 = 638, >+ ARM_VCGEuv8i8 = 639, >+ ARM_VCGEzv16i8 = 640, >+ ARM_VCGEzv2f32 = 641, >+ ARM_VCGEzv2i32 = 642, >+ ARM_VCGEzv4f32 = 643, >+ ARM_VCGEzv4i16 = 644, >+ ARM_VCGEzv4i32 = 645, >+ ARM_VCGEzv8i16 = 646, >+ ARM_VCGEzv8i8 = 647, >+ ARM_VCGTfd = 648, >+ ARM_VCGTfq = 649, >+ ARM_VCGTsv16i8 = 650, >+ ARM_VCGTsv2i32 = 651, >+ ARM_VCGTsv4i16 = 652, >+ ARM_VCGTsv4i32 = 653, >+ ARM_VCGTsv8i16 = 654, >+ ARM_VCGTsv8i8 = 655, >+ ARM_VCGTuv16i8 = 656, >+ ARM_VCGTuv2i32 = 657, >+ ARM_VCGTuv4i16 = 658, >+ ARM_VCGTuv4i32 = 659, >+ ARM_VCGTuv8i16 = 660, >+ ARM_VCGTuv8i8 = 661, >+ ARM_VCGTzv16i8 = 662, >+ ARM_VCGTzv2f32 = 663, >+ ARM_VCGTzv2i32 = 664, >+ ARM_VCGTzv4f32 = 665, >+ ARM_VCGTzv4i16 = 666, >+ ARM_VCGTzv4i32 = 667, >+ ARM_VCGTzv8i16 = 668, >+ ARM_VCGTzv8i8 = 669, >+ ARM_VCLEzv16i8 = 670, >+ ARM_VCLEzv2f32 = 671, >+ ARM_VCLEzv2i32 = 672, >+ ARM_VCLEzv4f32 = 673, >+ ARM_VCLEzv4i16 = 674, >+ ARM_VCLEzv4i32 = 675, >+ ARM_VCLEzv8i16 = 676, >+ ARM_VCLEzv8i8 = 677, >+ ARM_VCLSv16i8 = 678, >+ ARM_VCLSv2i32 = 679, >+ ARM_VCLSv4i16 = 680, >+ ARM_VCLSv4i32 = 681, >+ ARM_VCLSv8i16 = 682, >+ ARM_VCLSv8i8 = 683, >+ ARM_VCLTzv16i8 = 684, >+ ARM_VCLTzv2f32 = 685, >+ ARM_VCLTzv2i32 = 686, >+ ARM_VCLTzv4f32 = 687, >+ ARM_VCLTzv4i16 = 688, >+ ARM_VCLTzv4i32 = 689, >+ ARM_VCLTzv8i16 = 690, >+ ARM_VCLTzv8i8 = 691, >+ ARM_VCLZv16i8 = 692, >+ ARM_VCLZv2i32 = 693, >+ ARM_VCLZv4i16 = 694, >+ ARM_VCLZv4i32 = 695, >+ ARM_VCLZv8i16 = 696, >+ ARM_VCLZv8i8 = 697, >+ ARM_VCMPD = 698, >+ ARM_VCMPED = 699, >+ ARM_VCMPES = 700, >+ ARM_VCMPEZD = 701, >+ ARM_VCMPEZS = 702, >+ ARM_VCMPS = 703, >+ ARM_VCMPZD = 704, >+ ARM_VCMPZS = 705, >+ ARM_VCNTd = 706, >+ ARM_VCNTq = 707, >+ ARM_VCVTANSD = 708, >+ ARM_VCVTANSQ = 709, >+ ARM_VCVTANUD = 710, >+ ARM_VCVTANUQ = 711, >+ ARM_VCVTASD = 712, >+ ARM_VCVTASS = 713, >+ ARM_VCVTAUD = 714, >+ ARM_VCVTAUS = 715, >+ ARM_VCVTBDH = 716, >+ ARM_VCVTBHD = 717, >+ ARM_VCVTBHS = 718, >+ ARM_VCVTBSH = 719, >+ ARM_VCVTDS = 720, >+ ARM_VCVTMNSD = 721, >+ ARM_VCVTMNSQ = 722, >+ ARM_VCVTMNUD = 723, >+ ARM_VCVTMNUQ = 724, >+ ARM_VCVTMSD = 725, >+ ARM_VCVTMSS = 726, >+ ARM_VCVTMUD = 727, >+ ARM_VCVTMUS = 728, >+ ARM_VCVTNNSD = 729, >+ ARM_VCVTNNSQ = 730, >+ ARM_VCVTNNUD = 731, >+ ARM_VCVTNNUQ = 732, >+ ARM_VCVTNSD = 733, >+ ARM_VCVTNSS = 734, >+ ARM_VCVTNUD = 735, >+ ARM_VCVTNUS = 736, >+ ARM_VCVTPNSD = 737, >+ ARM_VCVTPNSQ = 738, >+ ARM_VCVTPNUD = 739, >+ ARM_VCVTPNUQ = 740, >+ ARM_VCVTPSD = 741, >+ ARM_VCVTPSS = 742, >+ ARM_VCVTPUD = 743, >+ ARM_VCVTPUS = 744, >+ ARM_VCVTSD = 745, >+ ARM_VCVTTDH = 746, >+ ARM_VCVTTHD = 747, >+ ARM_VCVTTHS = 748, >+ ARM_VCVTTSH = 749, >+ ARM_VCVTf2h = 750, >+ ARM_VCVTf2sd = 751, >+ ARM_VCVTf2sq = 752, >+ ARM_VCVTf2ud = 753, >+ ARM_VCVTf2uq = 754, >+ ARM_VCVTf2xsd = 755, >+ ARM_VCVTf2xsq = 756, >+ ARM_VCVTf2xud = 757, >+ ARM_VCVTf2xuq = 758, >+ ARM_VCVTh2f = 759, >+ ARM_VCVTs2fd = 760, >+ ARM_VCVTs2fq = 761, >+ ARM_VCVTu2fd = 762, >+ ARM_VCVTu2fq = 763, >+ ARM_VCVTxs2fd = 764, >+ ARM_VCVTxs2fq = 765, >+ ARM_VCVTxu2fd = 766, >+ ARM_VCVTxu2fq = 767, >+ ARM_VDIVD = 768, >+ ARM_VDIVS = 769, >+ ARM_VDUP16d = 770, >+ ARM_VDUP16q = 771, >+ ARM_VDUP32d = 772, >+ ARM_VDUP32q = 773, >+ ARM_VDUP8d = 774, >+ ARM_VDUP8q = 775, >+ ARM_VDUPLN16d = 776, >+ ARM_VDUPLN16q = 777, >+ ARM_VDUPLN32d = 778, >+ ARM_VDUPLN32q = 779, >+ ARM_VDUPLN8d = 780, >+ ARM_VDUPLN8q = 781, >+ ARM_VEORd = 782, >+ ARM_VEORq = 783, >+ ARM_VEXTd16 = 784, >+ ARM_VEXTd32 = 785, >+ ARM_VEXTd8 = 786, >+ ARM_VEXTq16 = 787, >+ ARM_VEXTq32 = 788, >+ ARM_VEXTq64 = 789, >+ ARM_VEXTq8 = 790, >+ ARM_VFMAD = 791, >+ ARM_VFMAS = 792, >+ ARM_VFMAfd = 793, >+ ARM_VFMAfq = 794, >+ ARM_VFMSD = 795, >+ ARM_VFMSS = 796, >+ ARM_VFMSfd = 797, >+ ARM_VFMSfq = 798, >+ ARM_VFNMAD = 799, >+ ARM_VFNMAS = 800, >+ ARM_VFNMSD = 801, >+ ARM_VFNMSS = 802, >+ ARM_VGETLNi32 = 803, >+ ARM_VGETLNs16 = 804, >+ ARM_VGETLNs8 = 805, >+ ARM_VGETLNu16 = 806, >+ ARM_VGETLNu8 = 807, >+ ARM_VHADDsv16i8 = 808, >+ ARM_VHADDsv2i32 = 809, >+ ARM_VHADDsv4i16 = 810, >+ ARM_VHADDsv4i32 = 811, >+ ARM_VHADDsv8i16 = 812, >+ ARM_VHADDsv8i8 = 813, >+ ARM_VHADDuv16i8 = 814, >+ ARM_VHADDuv2i32 = 815, >+ ARM_VHADDuv4i16 = 816, >+ ARM_VHADDuv4i32 = 817, >+ ARM_VHADDuv8i16 = 818, >+ ARM_VHADDuv8i8 = 819, >+ ARM_VHSUBsv16i8 = 820, >+ ARM_VHSUBsv2i32 = 821, >+ ARM_VHSUBsv4i16 = 822, >+ ARM_VHSUBsv4i32 = 823, >+ ARM_VHSUBsv8i16 = 824, >+ ARM_VHSUBsv8i8 = 825, >+ ARM_VHSUBuv16i8 = 826, >+ ARM_VHSUBuv2i32 = 827, >+ ARM_VHSUBuv4i16 = 828, >+ ARM_VHSUBuv4i32 = 829, >+ ARM_VHSUBuv8i16 = 830, >+ ARM_VHSUBuv8i8 = 831, >+ ARM_VLD1DUPd16 = 832, >+ ARM_VLD1DUPd16wb_fixed = 833, >+ ARM_VLD1DUPd16wb_register = 834, >+ ARM_VLD1DUPd32 = 835, >+ ARM_VLD1DUPd32wb_fixed = 836, >+ ARM_VLD1DUPd32wb_register = 837, >+ ARM_VLD1DUPd8 = 838, >+ ARM_VLD1DUPd8wb_fixed = 839, >+ ARM_VLD1DUPd8wb_register = 840, >+ ARM_VLD1DUPq16 = 841, >+ ARM_VLD1DUPq16wb_fixed = 842, >+ ARM_VLD1DUPq16wb_register = 843, >+ ARM_VLD1DUPq32 = 844, >+ ARM_VLD1DUPq32wb_fixed = 845, >+ ARM_VLD1DUPq32wb_register = 846, >+ ARM_VLD1DUPq8 = 847, >+ ARM_VLD1DUPq8wb_fixed = 848, >+ ARM_VLD1DUPq8wb_register = 849, >+ ARM_VLD1LNd16 = 850, >+ ARM_VLD1LNd16_UPD = 851, >+ ARM_VLD1LNd32 = 852, >+ ARM_VLD1LNd32_UPD = 853, >+ ARM_VLD1LNd8 = 854, >+ ARM_VLD1LNd8_UPD = 855, >+ ARM_VLD1LNdAsm_16 = 856, >+ ARM_VLD1LNdAsm_32 = 857, >+ ARM_VLD1LNdAsm_8 = 858, >+ ARM_VLD1LNdWB_fixed_Asm_16 = 859, >+ ARM_VLD1LNdWB_fixed_Asm_32 = 860, >+ ARM_VLD1LNdWB_fixed_Asm_8 = 861, >+ ARM_VLD1LNdWB_register_Asm_16 = 862, >+ ARM_VLD1LNdWB_register_Asm_32 = 863, >+ ARM_VLD1LNdWB_register_Asm_8 = 864, >+ ARM_VLD1LNq16Pseudo = 865, >+ ARM_VLD1LNq16Pseudo_UPD = 866, >+ ARM_VLD1LNq32Pseudo = 867, >+ ARM_VLD1LNq32Pseudo_UPD = 868, >+ ARM_VLD1LNq8Pseudo = 869, >+ ARM_VLD1LNq8Pseudo_UPD = 870, >+ ARM_VLD1d16 = 871, >+ ARM_VLD1d16Q = 872, >+ ARM_VLD1d16Qwb_fixed = 873, >+ ARM_VLD1d16Qwb_register = 874, >+ ARM_VLD1d16T = 875, >+ ARM_VLD1d16Twb_fixed = 876, >+ ARM_VLD1d16Twb_register = 877, >+ ARM_VLD1d16wb_fixed = 878, >+ ARM_VLD1d16wb_register = 879, >+ ARM_VLD1d32 = 880, >+ ARM_VLD1d32Q = 881, >+ ARM_VLD1d32Qwb_fixed = 882, >+ ARM_VLD1d32Qwb_register = 883, >+ ARM_VLD1d32T = 884, >+ ARM_VLD1d32Twb_fixed = 885, >+ ARM_VLD1d32Twb_register = 886, >+ ARM_VLD1d32wb_fixed = 887, >+ ARM_VLD1d32wb_register = 888, >+ ARM_VLD1d64 = 889, >+ ARM_VLD1d64Q = 890, >+ ARM_VLD1d64QPseudo = 891, >+ ARM_VLD1d64QPseudoWB_fixed = 892, >+ ARM_VLD1d64QPseudoWB_register = 893, >+ ARM_VLD1d64Qwb_fixed = 894, >+ ARM_VLD1d64Qwb_register = 895, >+ ARM_VLD1d64T = 896, >+ ARM_VLD1d64TPseudo = 897, >+ ARM_VLD1d64TPseudoWB_fixed = 898, >+ ARM_VLD1d64TPseudoWB_register = 899, >+ ARM_VLD1d64Twb_fixed = 900, >+ ARM_VLD1d64Twb_register = 901, >+ ARM_VLD1d64wb_fixed = 902, >+ ARM_VLD1d64wb_register = 903, >+ ARM_VLD1d8 = 904, >+ ARM_VLD1d8Q = 905, >+ ARM_VLD1d8Qwb_fixed = 906, >+ ARM_VLD1d8Qwb_register = 907, >+ ARM_VLD1d8T = 908, >+ ARM_VLD1d8Twb_fixed = 909, >+ ARM_VLD1d8Twb_register = 910, >+ ARM_VLD1d8wb_fixed = 911, >+ ARM_VLD1d8wb_register = 912, >+ ARM_VLD1q16 = 913, >+ ARM_VLD1q16wb_fixed = 914, >+ ARM_VLD1q16wb_register = 915, >+ ARM_VLD1q32 = 916, >+ ARM_VLD1q32wb_fixed = 917, >+ ARM_VLD1q32wb_register = 918, >+ ARM_VLD1q64 = 919, >+ ARM_VLD1q64wb_fixed = 920, >+ ARM_VLD1q64wb_register = 921, >+ ARM_VLD1q8 = 922, >+ ARM_VLD1q8wb_fixed = 923, >+ ARM_VLD1q8wb_register = 924, >+ ARM_VLD2DUPd16 = 925, >+ ARM_VLD2DUPd16wb_fixed = 926, >+ ARM_VLD2DUPd16wb_register = 927, >+ ARM_VLD2DUPd16x2 = 928, >+ ARM_VLD2DUPd16x2wb_fixed = 929, >+ ARM_VLD2DUPd16x2wb_register = 930, >+ ARM_VLD2DUPd32 = 931, >+ ARM_VLD2DUPd32wb_fixed = 932, >+ ARM_VLD2DUPd32wb_register = 933, >+ ARM_VLD2DUPd32x2 = 934, >+ ARM_VLD2DUPd32x2wb_fixed = 935, >+ ARM_VLD2DUPd32x2wb_register = 936, >+ ARM_VLD2DUPd8 = 937, >+ ARM_VLD2DUPd8wb_fixed = 938, >+ ARM_VLD2DUPd8wb_register = 939, >+ ARM_VLD2DUPd8x2 = 940, >+ ARM_VLD2DUPd8x2wb_fixed = 941, >+ ARM_VLD2DUPd8x2wb_register = 942, >+ ARM_VLD2LNd16 = 943, >+ ARM_VLD2LNd16Pseudo = 944, >+ ARM_VLD2LNd16Pseudo_UPD = 945, >+ ARM_VLD2LNd16_UPD = 946, >+ ARM_VLD2LNd32 = 947, >+ ARM_VLD2LNd32Pseudo = 948, >+ ARM_VLD2LNd32Pseudo_UPD = 949, >+ ARM_VLD2LNd32_UPD = 950, >+ ARM_VLD2LNd8 = 951, >+ ARM_VLD2LNd8Pseudo = 952, >+ ARM_VLD2LNd8Pseudo_UPD = 953, >+ ARM_VLD2LNd8_UPD = 954, >+ ARM_VLD2LNdAsm_16 = 955, >+ ARM_VLD2LNdAsm_32 = 956, >+ ARM_VLD2LNdAsm_8 = 957, >+ ARM_VLD2LNdWB_fixed_Asm_16 = 958, >+ ARM_VLD2LNdWB_fixed_Asm_32 = 959, >+ ARM_VLD2LNdWB_fixed_Asm_8 = 960, >+ ARM_VLD2LNdWB_register_Asm_16 = 961, >+ ARM_VLD2LNdWB_register_Asm_32 = 962, >+ ARM_VLD2LNdWB_register_Asm_8 = 963, >+ ARM_VLD2LNq16 = 964, >+ ARM_VLD2LNq16Pseudo = 965, >+ ARM_VLD2LNq16Pseudo_UPD = 966, >+ ARM_VLD2LNq16_UPD = 967, >+ ARM_VLD2LNq32 = 968, >+ ARM_VLD2LNq32Pseudo = 969, >+ ARM_VLD2LNq32Pseudo_UPD = 970, >+ ARM_VLD2LNq32_UPD = 971, >+ ARM_VLD2LNqAsm_16 = 972, >+ ARM_VLD2LNqAsm_32 = 973, >+ ARM_VLD2LNqWB_fixed_Asm_16 = 974, >+ ARM_VLD2LNqWB_fixed_Asm_32 = 975, >+ ARM_VLD2LNqWB_register_Asm_16 = 976, >+ ARM_VLD2LNqWB_register_Asm_32 = 977, >+ ARM_VLD2b16 = 978, >+ ARM_VLD2b16wb_fixed = 979, >+ ARM_VLD2b16wb_register = 980, >+ ARM_VLD2b32 = 981, >+ ARM_VLD2b32wb_fixed = 982, >+ ARM_VLD2b32wb_register = 983, >+ ARM_VLD2b8 = 984, >+ ARM_VLD2b8wb_fixed = 985, >+ ARM_VLD2b8wb_register = 986, >+ ARM_VLD2d16 = 987, >+ ARM_VLD2d16wb_fixed = 988, >+ ARM_VLD2d16wb_register = 989, >+ ARM_VLD2d32 = 990, >+ ARM_VLD2d32wb_fixed = 991, >+ ARM_VLD2d32wb_register = 992, >+ ARM_VLD2d8 = 993, >+ ARM_VLD2d8wb_fixed = 994, >+ ARM_VLD2d8wb_register = 995, >+ ARM_VLD2q16 = 996, >+ ARM_VLD2q16Pseudo = 997, >+ ARM_VLD2q16PseudoWB_fixed = 998, >+ ARM_VLD2q16PseudoWB_register = 999, >+ ARM_VLD2q16wb_fixed = 1000, >+ ARM_VLD2q16wb_register = 1001, >+ ARM_VLD2q32 = 1002, >+ ARM_VLD2q32Pseudo = 1003, >+ ARM_VLD2q32PseudoWB_fixed = 1004, >+ ARM_VLD2q32PseudoWB_register = 1005, >+ ARM_VLD2q32wb_fixed = 1006, >+ ARM_VLD2q32wb_register = 1007, >+ ARM_VLD2q8 = 1008, >+ ARM_VLD2q8Pseudo = 1009, >+ ARM_VLD2q8PseudoWB_fixed = 1010, >+ ARM_VLD2q8PseudoWB_register = 1011, >+ ARM_VLD2q8wb_fixed = 1012, >+ ARM_VLD2q8wb_register = 1013, >+ ARM_VLD3DUPd16 = 1014, >+ ARM_VLD3DUPd16Pseudo = 1015, >+ ARM_VLD3DUPd16Pseudo_UPD = 1016, >+ ARM_VLD3DUPd16_UPD = 1017, >+ ARM_VLD3DUPd32 = 1018, >+ ARM_VLD3DUPd32Pseudo = 1019, >+ ARM_VLD3DUPd32Pseudo_UPD = 1020, >+ ARM_VLD3DUPd32_UPD = 1021, >+ ARM_VLD3DUPd8 = 1022, >+ ARM_VLD3DUPd8Pseudo = 1023, >+ ARM_VLD3DUPd8Pseudo_UPD = 1024, >+ ARM_VLD3DUPd8_UPD = 1025, >+ ARM_VLD3DUPdAsm_16 = 1026, >+ ARM_VLD3DUPdAsm_32 = 1027, >+ ARM_VLD3DUPdAsm_8 = 1028, >+ ARM_VLD3DUPdWB_fixed_Asm_16 = 1029, >+ ARM_VLD3DUPdWB_fixed_Asm_32 = 1030, >+ ARM_VLD3DUPdWB_fixed_Asm_8 = 1031, >+ ARM_VLD3DUPdWB_register_Asm_16 = 1032, >+ ARM_VLD3DUPdWB_register_Asm_32 = 1033, >+ ARM_VLD3DUPdWB_register_Asm_8 = 1034, >+ ARM_VLD3DUPq16 = 1035, >+ ARM_VLD3DUPq16_UPD = 1036, >+ ARM_VLD3DUPq32 = 1037, >+ ARM_VLD3DUPq32_UPD = 1038, >+ ARM_VLD3DUPq8 = 1039, >+ ARM_VLD3DUPq8_UPD = 1040, >+ ARM_VLD3DUPqAsm_16 = 1041, >+ ARM_VLD3DUPqAsm_32 = 1042, >+ ARM_VLD3DUPqAsm_8 = 1043, >+ ARM_VLD3DUPqWB_fixed_Asm_16 = 1044, >+ ARM_VLD3DUPqWB_fixed_Asm_32 = 1045, >+ ARM_VLD3DUPqWB_fixed_Asm_8 = 1046, >+ ARM_VLD3DUPqWB_register_Asm_16 = 1047, >+ ARM_VLD3DUPqWB_register_Asm_32 = 1048, >+ ARM_VLD3DUPqWB_register_Asm_8 = 1049, >+ ARM_VLD3LNd16 = 1050, >+ ARM_VLD3LNd16Pseudo = 1051, >+ ARM_VLD3LNd16Pseudo_UPD = 1052, >+ ARM_VLD3LNd16_UPD = 1053, >+ ARM_VLD3LNd32 = 1054, >+ ARM_VLD3LNd32Pseudo = 1055, >+ ARM_VLD3LNd32Pseudo_UPD = 1056, >+ ARM_VLD3LNd32_UPD = 1057, >+ ARM_VLD3LNd8 = 1058, >+ ARM_VLD3LNd8Pseudo = 1059, >+ ARM_VLD3LNd8Pseudo_UPD = 1060, >+ ARM_VLD3LNd8_UPD = 1061, >+ ARM_VLD3LNdAsm_16 = 1062, >+ ARM_VLD3LNdAsm_32 = 1063, >+ ARM_VLD3LNdAsm_8 = 1064, >+ ARM_VLD3LNdWB_fixed_Asm_16 = 1065, >+ ARM_VLD3LNdWB_fixed_Asm_32 = 1066, >+ ARM_VLD3LNdWB_fixed_Asm_8 = 1067, >+ ARM_VLD3LNdWB_register_Asm_16 = 1068, >+ ARM_VLD3LNdWB_register_Asm_32 = 1069, >+ ARM_VLD3LNdWB_register_Asm_8 = 1070, >+ ARM_VLD3LNq16 = 1071, >+ ARM_VLD3LNq16Pseudo = 1072, >+ ARM_VLD3LNq16Pseudo_UPD = 1073, >+ ARM_VLD3LNq16_UPD = 1074, >+ ARM_VLD3LNq32 = 1075, >+ ARM_VLD3LNq32Pseudo = 1076, >+ ARM_VLD3LNq32Pseudo_UPD = 1077, >+ ARM_VLD3LNq32_UPD = 1078, >+ ARM_VLD3LNqAsm_16 = 1079, >+ ARM_VLD3LNqAsm_32 = 1080, >+ ARM_VLD3LNqWB_fixed_Asm_16 = 1081, >+ ARM_VLD3LNqWB_fixed_Asm_32 = 1082, >+ ARM_VLD3LNqWB_register_Asm_16 = 1083, >+ ARM_VLD3LNqWB_register_Asm_32 = 1084, >+ ARM_VLD3d16 = 1085, >+ ARM_VLD3d16Pseudo = 1086, >+ ARM_VLD3d16Pseudo_UPD = 1087, >+ ARM_VLD3d16_UPD = 1088, >+ ARM_VLD3d32 = 1089, >+ ARM_VLD3d32Pseudo = 1090, >+ ARM_VLD3d32Pseudo_UPD = 1091, >+ ARM_VLD3d32_UPD = 1092, >+ ARM_VLD3d8 = 1093, >+ ARM_VLD3d8Pseudo = 1094, >+ ARM_VLD3d8Pseudo_UPD = 1095, >+ ARM_VLD3d8_UPD = 1096, >+ ARM_VLD3dAsm_16 = 1097, >+ ARM_VLD3dAsm_32 = 1098, >+ ARM_VLD3dAsm_8 = 1099, >+ ARM_VLD3dWB_fixed_Asm_16 = 1100, >+ ARM_VLD3dWB_fixed_Asm_32 = 1101, >+ ARM_VLD3dWB_fixed_Asm_8 = 1102, >+ ARM_VLD3dWB_register_Asm_16 = 1103, >+ ARM_VLD3dWB_register_Asm_32 = 1104, >+ ARM_VLD3dWB_register_Asm_8 = 1105, >+ ARM_VLD3q16 = 1106, >+ ARM_VLD3q16Pseudo_UPD = 1107, >+ ARM_VLD3q16_UPD = 1108, >+ ARM_VLD3q16oddPseudo = 1109, >+ ARM_VLD3q16oddPseudo_UPD = 1110, >+ ARM_VLD3q32 = 1111, >+ ARM_VLD3q32Pseudo_UPD = 1112, >+ ARM_VLD3q32_UPD = 1113, >+ ARM_VLD3q32oddPseudo = 1114, >+ ARM_VLD3q32oddPseudo_UPD = 1115, >+ ARM_VLD3q8 = 1116, >+ ARM_VLD3q8Pseudo_UPD = 1117, >+ ARM_VLD3q8_UPD = 1118, >+ ARM_VLD3q8oddPseudo = 1119, >+ ARM_VLD3q8oddPseudo_UPD = 1120, >+ ARM_VLD3qAsm_16 = 1121, >+ ARM_VLD3qAsm_32 = 1122, >+ ARM_VLD3qAsm_8 = 1123, >+ ARM_VLD3qWB_fixed_Asm_16 = 1124, >+ ARM_VLD3qWB_fixed_Asm_32 = 1125, >+ ARM_VLD3qWB_fixed_Asm_8 = 1126, >+ ARM_VLD3qWB_register_Asm_16 = 1127, >+ ARM_VLD3qWB_register_Asm_32 = 1128, >+ ARM_VLD3qWB_register_Asm_8 = 1129, >+ ARM_VLD4DUPd16 = 1130, >+ ARM_VLD4DUPd16Pseudo = 1131, >+ ARM_VLD4DUPd16Pseudo_UPD = 1132, >+ ARM_VLD4DUPd16_UPD = 1133, >+ ARM_VLD4DUPd32 = 1134, >+ ARM_VLD4DUPd32Pseudo = 1135, >+ ARM_VLD4DUPd32Pseudo_UPD = 1136, >+ ARM_VLD4DUPd32_UPD = 1137, >+ ARM_VLD4DUPd8 = 1138, >+ ARM_VLD4DUPd8Pseudo = 1139, >+ ARM_VLD4DUPd8Pseudo_UPD = 1140, >+ ARM_VLD4DUPd8_UPD = 1141, >+ ARM_VLD4DUPdAsm_16 = 1142, >+ ARM_VLD4DUPdAsm_32 = 1143, >+ ARM_VLD4DUPdAsm_8 = 1144, >+ ARM_VLD4DUPdWB_fixed_Asm_16 = 1145, >+ ARM_VLD4DUPdWB_fixed_Asm_32 = 1146, >+ ARM_VLD4DUPdWB_fixed_Asm_8 = 1147, >+ ARM_VLD4DUPdWB_register_Asm_16 = 1148, >+ ARM_VLD4DUPdWB_register_Asm_32 = 1149, >+ ARM_VLD4DUPdWB_register_Asm_8 = 1150, >+ ARM_VLD4DUPq16 = 1151, >+ ARM_VLD4DUPq16_UPD = 1152, >+ ARM_VLD4DUPq32 = 1153, >+ ARM_VLD4DUPq32_UPD = 1154, >+ ARM_VLD4DUPq8 = 1155, >+ ARM_VLD4DUPq8_UPD = 1156, >+ ARM_VLD4DUPqAsm_16 = 1157, >+ ARM_VLD4DUPqAsm_32 = 1158, >+ ARM_VLD4DUPqAsm_8 = 1159, >+ ARM_VLD4DUPqWB_fixed_Asm_16 = 1160, >+ ARM_VLD4DUPqWB_fixed_Asm_32 = 1161, >+ ARM_VLD4DUPqWB_fixed_Asm_8 = 1162, >+ ARM_VLD4DUPqWB_register_Asm_16 = 1163, >+ ARM_VLD4DUPqWB_register_Asm_32 = 1164, >+ ARM_VLD4DUPqWB_register_Asm_8 = 1165, >+ ARM_VLD4LNd16 = 1166, >+ ARM_VLD4LNd16Pseudo = 1167, >+ ARM_VLD4LNd16Pseudo_UPD = 1168, >+ ARM_VLD4LNd16_UPD = 1169, >+ ARM_VLD4LNd32 = 1170, >+ ARM_VLD4LNd32Pseudo = 1171, >+ ARM_VLD4LNd32Pseudo_UPD = 1172, >+ ARM_VLD4LNd32_UPD = 1173, >+ ARM_VLD4LNd8 = 1174, >+ ARM_VLD4LNd8Pseudo = 1175, >+ ARM_VLD4LNd8Pseudo_UPD = 1176, >+ ARM_VLD4LNd8_UPD = 1177, >+ ARM_VLD4LNdAsm_16 = 1178, >+ ARM_VLD4LNdAsm_32 = 1179, >+ ARM_VLD4LNdAsm_8 = 1180, >+ ARM_VLD4LNdWB_fixed_Asm_16 = 1181, >+ ARM_VLD4LNdWB_fixed_Asm_32 = 1182, >+ ARM_VLD4LNdWB_fixed_Asm_8 = 1183, >+ ARM_VLD4LNdWB_register_Asm_16 = 1184, >+ ARM_VLD4LNdWB_register_Asm_32 = 1185, >+ ARM_VLD4LNdWB_register_Asm_8 = 1186, >+ ARM_VLD4LNq16 = 1187, >+ ARM_VLD4LNq16Pseudo = 1188, >+ ARM_VLD4LNq16Pseudo_UPD = 1189, >+ ARM_VLD4LNq16_UPD = 1190, >+ ARM_VLD4LNq32 = 1191, >+ ARM_VLD4LNq32Pseudo = 1192, >+ ARM_VLD4LNq32Pseudo_UPD = 1193, >+ ARM_VLD4LNq32_UPD = 1194, >+ ARM_VLD4LNqAsm_16 = 1195, >+ ARM_VLD4LNqAsm_32 = 1196, >+ ARM_VLD4LNqWB_fixed_Asm_16 = 1197, >+ ARM_VLD4LNqWB_fixed_Asm_32 = 1198, >+ ARM_VLD4LNqWB_register_Asm_16 = 1199, >+ ARM_VLD4LNqWB_register_Asm_32 = 1200, >+ ARM_VLD4d16 = 1201, >+ ARM_VLD4d16Pseudo = 1202, >+ ARM_VLD4d16Pseudo_UPD = 1203, >+ ARM_VLD4d16_UPD = 1204, >+ ARM_VLD4d32 = 1205, >+ ARM_VLD4d32Pseudo = 1206, >+ ARM_VLD4d32Pseudo_UPD = 1207, >+ ARM_VLD4d32_UPD = 1208, >+ ARM_VLD4d8 = 1209, >+ ARM_VLD4d8Pseudo = 1210, >+ ARM_VLD4d8Pseudo_UPD = 1211, >+ ARM_VLD4d8_UPD = 1212, >+ ARM_VLD4dAsm_16 = 1213, >+ ARM_VLD4dAsm_32 = 1214, >+ ARM_VLD4dAsm_8 = 1215, >+ ARM_VLD4dWB_fixed_Asm_16 = 1216, >+ ARM_VLD4dWB_fixed_Asm_32 = 1217, >+ ARM_VLD4dWB_fixed_Asm_8 = 1218, >+ ARM_VLD4dWB_register_Asm_16 = 1219, >+ ARM_VLD4dWB_register_Asm_32 = 1220, >+ ARM_VLD4dWB_register_Asm_8 = 1221, >+ ARM_VLD4q16 = 1222, >+ ARM_VLD4q16Pseudo_UPD = 1223, >+ ARM_VLD4q16_UPD = 1224, >+ ARM_VLD4q16oddPseudo = 1225, >+ ARM_VLD4q16oddPseudo_UPD = 1226, >+ ARM_VLD4q32 = 1227, >+ ARM_VLD4q32Pseudo_UPD = 1228, >+ ARM_VLD4q32_UPD = 1229, >+ ARM_VLD4q32oddPseudo = 1230, >+ ARM_VLD4q32oddPseudo_UPD = 1231, >+ ARM_VLD4q8 = 1232, >+ ARM_VLD4q8Pseudo_UPD = 1233, >+ ARM_VLD4q8_UPD = 1234, >+ ARM_VLD4q8oddPseudo = 1235, >+ ARM_VLD4q8oddPseudo_UPD = 1236, >+ ARM_VLD4qAsm_16 = 1237, >+ ARM_VLD4qAsm_32 = 1238, >+ ARM_VLD4qAsm_8 = 1239, >+ ARM_VLD4qWB_fixed_Asm_16 = 1240, >+ ARM_VLD4qWB_fixed_Asm_32 = 1241, >+ ARM_VLD4qWB_fixed_Asm_8 = 1242, >+ ARM_VLD4qWB_register_Asm_16 = 1243, >+ ARM_VLD4qWB_register_Asm_32 = 1244, >+ ARM_VLD4qWB_register_Asm_8 = 1245, >+ ARM_VLDMDDB_UPD = 1246, >+ ARM_VLDMDIA = 1247, >+ ARM_VLDMDIA_UPD = 1248, >+ ARM_VLDMQIA = 1249, >+ ARM_VLDMSDB_UPD = 1250, >+ ARM_VLDMSIA = 1251, >+ ARM_VLDMSIA_UPD = 1252, >+ ARM_VLDRD = 1253, >+ ARM_VLDRS = 1254, >+ ARM_VMAXNMD = 1255, >+ ARM_VMAXNMND = 1256, >+ ARM_VMAXNMNQ = 1257, >+ ARM_VMAXNMS = 1258, >+ ARM_VMAXfd = 1259, >+ ARM_VMAXfq = 1260, >+ ARM_VMAXsv16i8 = 1261, >+ ARM_VMAXsv2i32 = 1262, >+ ARM_VMAXsv4i16 = 1263, >+ ARM_VMAXsv4i32 = 1264, >+ ARM_VMAXsv8i16 = 1265, >+ ARM_VMAXsv8i8 = 1266, >+ ARM_VMAXuv16i8 = 1267, >+ ARM_VMAXuv2i32 = 1268, >+ ARM_VMAXuv4i16 = 1269, >+ ARM_VMAXuv4i32 = 1270, >+ ARM_VMAXuv8i16 = 1271, >+ ARM_VMAXuv8i8 = 1272, >+ ARM_VMINNMD = 1273, >+ ARM_VMINNMND = 1274, >+ ARM_VMINNMNQ = 1275, >+ ARM_VMINNMS = 1276, >+ ARM_VMINfd = 1277, >+ ARM_VMINfq = 1278, >+ ARM_VMINsv16i8 = 1279, >+ ARM_VMINsv2i32 = 1280, >+ ARM_VMINsv4i16 = 1281, >+ ARM_VMINsv4i32 = 1282, >+ ARM_VMINsv8i16 = 1283, >+ ARM_VMINsv8i8 = 1284, >+ ARM_VMINuv16i8 = 1285, >+ ARM_VMINuv2i32 = 1286, >+ ARM_VMINuv4i16 = 1287, >+ ARM_VMINuv4i32 = 1288, >+ ARM_VMINuv8i16 = 1289, >+ ARM_VMINuv8i8 = 1290, >+ ARM_VMLAD = 1291, >+ ARM_VMLALslsv2i32 = 1292, >+ ARM_VMLALslsv4i16 = 1293, >+ ARM_VMLALsluv2i32 = 1294, >+ ARM_VMLALsluv4i16 = 1295, >+ ARM_VMLALsv2i64 = 1296, >+ ARM_VMLALsv4i32 = 1297, >+ ARM_VMLALsv8i16 = 1298, >+ ARM_VMLALuv2i64 = 1299, >+ ARM_VMLALuv4i32 = 1300, >+ ARM_VMLALuv8i16 = 1301, >+ ARM_VMLAS = 1302, >+ ARM_VMLAfd = 1303, >+ ARM_VMLAfq = 1304, >+ ARM_VMLAslfd = 1305, >+ ARM_VMLAslfq = 1306, >+ ARM_VMLAslv2i32 = 1307, >+ ARM_VMLAslv4i16 = 1308, >+ ARM_VMLAslv4i32 = 1309, >+ ARM_VMLAslv8i16 = 1310, >+ ARM_VMLAv16i8 = 1311, >+ ARM_VMLAv2i32 = 1312, >+ ARM_VMLAv4i16 = 1313, >+ ARM_VMLAv4i32 = 1314, >+ ARM_VMLAv8i16 = 1315, >+ ARM_VMLAv8i8 = 1316, >+ ARM_VMLSD = 1317, >+ ARM_VMLSLslsv2i32 = 1318, >+ ARM_VMLSLslsv4i16 = 1319, >+ ARM_VMLSLsluv2i32 = 1320, >+ ARM_VMLSLsluv4i16 = 1321, >+ ARM_VMLSLsv2i64 = 1322, >+ ARM_VMLSLsv4i32 = 1323, >+ ARM_VMLSLsv8i16 = 1324, >+ ARM_VMLSLuv2i64 = 1325, >+ ARM_VMLSLuv4i32 = 1326, >+ ARM_VMLSLuv8i16 = 1327, >+ ARM_VMLSS = 1328, >+ ARM_VMLSfd = 1329, >+ ARM_VMLSfq = 1330, >+ ARM_VMLSslfd = 1331, >+ ARM_VMLSslfq = 1332, >+ ARM_VMLSslv2i32 = 1333, >+ ARM_VMLSslv4i16 = 1334, >+ ARM_VMLSslv4i32 = 1335, >+ ARM_VMLSslv8i16 = 1336, >+ ARM_VMLSv16i8 = 1337, >+ ARM_VMLSv2i32 = 1338, >+ ARM_VMLSv4i16 = 1339, >+ ARM_VMLSv4i32 = 1340, >+ ARM_VMLSv8i16 = 1341, >+ ARM_VMLSv8i8 = 1342, >+ ARM_VMOVD = 1343, >+ ARM_VMOVD0 = 1344, >+ ARM_VMOVDRR = 1345, >+ ARM_VMOVDcc = 1346, >+ ARM_VMOVLsv2i64 = 1347, >+ ARM_VMOVLsv4i32 = 1348, >+ ARM_VMOVLsv8i16 = 1349, >+ ARM_VMOVLuv2i64 = 1350, >+ ARM_VMOVLuv4i32 = 1351, >+ ARM_VMOVLuv8i16 = 1352, >+ ARM_VMOVNv2i32 = 1353, >+ ARM_VMOVNv4i16 = 1354, >+ ARM_VMOVNv8i8 = 1355, >+ ARM_VMOVQ0 = 1356, >+ ARM_VMOVRRD = 1357, >+ ARM_VMOVRRS = 1358, >+ ARM_VMOVRS = 1359, >+ ARM_VMOVS = 1360, >+ ARM_VMOVSR = 1361, >+ ARM_VMOVSRR = 1362, >+ ARM_VMOVScc = 1363, >+ ARM_VMOVv16i8 = 1364, >+ ARM_VMOVv1i64 = 1365, >+ ARM_VMOVv2f32 = 1366, >+ ARM_VMOVv2i32 = 1367, >+ ARM_VMOVv2i64 = 1368, >+ ARM_VMOVv4f32 = 1369, >+ ARM_VMOVv4i16 = 1370, >+ ARM_VMOVv4i32 = 1371, >+ ARM_VMOVv8i16 = 1372, >+ ARM_VMOVv8i8 = 1373, >+ ARM_VMRS = 1374, >+ ARM_VMRS_FPEXC = 1375, >+ ARM_VMRS_FPINST = 1376, >+ ARM_VMRS_FPINST2 = 1377, >+ ARM_VMRS_FPSID = 1378, >+ ARM_VMRS_MVFR0 = 1379, >+ ARM_VMRS_MVFR1 = 1380, >+ ARM_VMRS_MVFR2 = 1381, >+ ARM_VMSR = 1382, >+ ARM_VMSR_FPEXC = 1383, >+ ARM_VMSR_FPINST = 1384, >+ ARM_VMSR_FPINST2 = 1385, >+ ARM_VMSR_FPSID = 1386, >+ ARM_VMULD = 1387, >+ ARM_VMULLp64 = 1388, >+ ARM_VMULLp8 = 1389, >+ ARM_VMULLslsv2i32 = 1390, >+ ARM_VMULLslsv4i16 = 1391, >+ ARM_VMULLsluv2i32 = 1392, >+ ARM_VMULLsluv4i16 = 1393, >+ ARM_VMULLsv2i64 = 1394, >+ ARM_VMULLsv4i32 = 1395, >+ ARM_VMULLsv8i16 = 1396, >+ ARM_VMULLuv2i64 = 1397, >+ ARM_VMULLuv4i32 = 1398, >+ ARM_VMULLuv8i16 = 1399, >+ ARM_VMULS = 1400, >+ ARM_VMULfd = 1401, >+ ARM_VMULfq = 1402, >+ ARM_VMULpd = 1403, >+ ARM_VMULpq = 1404, >+ ARM_VMULslfd = 1405, >+ ARM_VMULslfq = 1406, >+ ARM_VMULslv2i32 = 1407, >+ ARM_VMULslv4i16 = 1408, >+ ARM_VMULslv4i32 = 1409, >+ ARM_VMULslv8i16 = 1410, >+ ARM_VMULv16i8 = 1411, >+ ARM_VMULv2i32 = 1412, >+ ARM_VMULv4i16 = 1413, >+ ARM_VMULv4i32 = 1414, >+ ARM_VMULv8i16 = 1415, >+ ARM_VMULv8i8 = 1416, >+ ARM_VMVNd = 1417, >+ ARM_VMVNq = 1418, >+ ARM_VMVNv2i32 = 1419, >+ ARM_VMVNv4i16 = 1420, >+ ARM_VMVNv4i32 = 1421, >+ ARM_VMVNv8i16 = 1422, >+ ARM_VNEGD = 1423, >+ ARM_VNEGS = 1424, >+ ARM_VNEGf32q = 1425, >+ ARM_VNEGfd = 1426, >+ ARM_VNEGs16d = 1427, >+ ARM_VNEGs16q = 1428, >+ ARM_VNEGs32d = 1429, >+ ARM_VNEGs32q = 1430, >+ ARM_VNEGs8d = 1431, >+ ARM_VNEGs8q = 1432, >+ ARM_VNMLAD = 1433, >+ ARM_VNMLAS = 1434, >+ ARM_VNMLSD = 1435, >+ ARM_VNMLSS = 1436, >+ ARM_VNMULD = 1437, >+ ARM_VNMULS = 1438, >+ ARM_VORNd = 1439, >+ ARM_VORNq = 1440, >+ ARM_VORRd = 1441, >+ ARM_VORRiv2i32 = 1442, >+ ARM_VORRiv4i16 = 1443, >+ ARM_VORRiv4i32 = 1444, >+ ARM_VORRiv8i16 = 1445, >+ ARM_VORRq = 1446, >+ ARM_VPADALsv16i8 = 1447, >+ ARM_VPADALsv2i32 = 1448, >+ ARM_VPADALsv4i16 = 1449, >+ ARM_VPADALsv4i32 = 1450, >+ ARM_VPADALsv8i16 = 1451, >+ ARM_VPADALsv8i8 = 1452, >+ ARM_VPADALuv16i8 = 1453, >+ ARM_VPADALuv2i32 = 1454, >+ ARM_VPADALuv4i16 = 1455, >+ ARM_VPADALuv4i32 = 1456, >+ ARM_VPADALuv8i16 = 1457, >+ ARM_VPADALuv8i8 = 1458, >+ ARM_VPADDLsv16i8 = 1459, >+ ARM_VPADDLsv2i32 = 1460, >+ ARM_VPADDLsv4i16 = 1461, >+ ARM_VPADDLsv4i32 = 1462, >+ ARM_VPADDLsv8i16 = 1463, >+ ARM_VPADDLsv8i8 = 1464, >+ ARM_VPADDLuv16i8 = 1465, >+ ARM_VPADDLuv2i32 = 1466, >+ ARM_VPADDLuv4i16 = 1467, >+ ARM_VPADDLuv4i32 = 1468, >+ ARM_VPADDLuv8i16 = 1469, >+ ARM_VPADDLuv8i8 = 1470, >+ ARM_VPADDf = 1471, >+ ARM_VPADDi16 = 1472, >+ ARM_VPADDi32 = 1473, >+ ARM_VPADDi8 = 1474, >+ ARM_VPMAXf = 1475, >+ ARM_VPMAXs16 = 1476, >+ ARM_VPMAXs32 = 1477, >+ ARM_VPMAXs8 = 1478, >+ ARM_VPMAXu16 = 1479, >+ ARM_VPMAXu32 = 1480, >+ ARM_VPMAXu8 = 1481, >+ ARM_VPMINf = 1482, >+ ARM_VPMINs16 = 1483, >+ ARM_VPMINs32 = 1484, >+ ARM_VPMINs8 = 1485, >+ ARM_VPMINu16 = 1486, >+ ARM_VPMINu32 = 1487, >+ ARM_VPMINu8 = 1488, >+ ARM_VQABSv16i8 = 1489, >+ ARM_VQABSv2i32 = 1490, >+ ARM_VQABSv4i16 = 1491, >+ ARM_VQABSv4i32 = 1492, >+ ARM_VQABSv8i16 = 1493, >+ ARM_VQABSv8i8 = 1494, >+ ARM_VQADDsv16i8 = 1495, >+ ARM_VQADDsv1i64 = 1496, >+ ARM_VQADDsv2i32 = 1497, >+ ARM_VQADDsv2i64 = 1498, >+ ARM_VQADDsv4i16 = 1499, >+ ARM_VQADDsv4i32 = 1500, >+ ARM_VQADDsv8i16 = 1501, >+ ARM_VQADDsv8i8 = 1502, >+ ARM_VQADDuv16i8 = 1503, >+ ARM_VQADDuv1i64 = 1504, >+ ARM_VQADDuv2i32 = 1505, >+ ARM_VQADDuv2i64 = 1506, >+ ARM_VQADDuv4i16 = 1507, >+ ARM_VQADDuv4i32 = 1508, >+ ARM_VQADDuv8i16 = 1509, >+ ARM_VQADDuv8i8 = 1510, >+ ARM_VQDMLALslv2i32 = 1511, >+ ARM_VQDMLALslv4i16 = 1512, >+ ARM_VQDMLALv2i64 = 1513, >+ ARM_VQDMLALv4i32 = 1514, >+ ARM_VQDMLSLslv2i32 = 1515, >+ ARM_VQDMLSLslv4i16 = 1516, >+ ARM_VQDMLSLv2i64 = 1517, >+ ARM_VQDMLSLv4i32 = 1518, >+ ARM_VQDMULHslv2i32 = 1519, >+ ARM_VQDMULHslv4i16 = 1520, >+ ARM_VQDMULHslv4i32 = 1521, >+ ARM_VQDMULHslv8i16 = 1522, >+ ARM_VQDMULHv2i32 = 1523, >+ ARM_VQDMULHv4i16 = 1524, >+ ARM_VQDMULHv4i32 = 1525, >+ ARM_VQDMULHv8i16 = 1526, >+ ARM_VQDMULLslv2i32 = 1527, >+ ARM_VQDMULLslv4i16 = 1528, >+ ARM_VQDMULLv2i64 = 1529, >+ ARM_VQDMULLv4i32 = 1530, >+ ARM_VQMOVNsuv2i32 = 1531, >+ ARM_VQMOVNsuv4i16 = 1532, >+ ARM_VQMOVNsuv8i8 = 1533, >+ ARM_VQMOVNsv2i32 = 1534, >+ ARM_VQMOVNsv4i16 = 1535, >+ ARM_VQMOVNsv8i8 = 1536, >+ ARM_VQMOVNuv2i32 = 1537, >+ ARM_VQMOVNuv4i16 = 1538, >+ ARM_VQMOVNuv8i8 = 1539, >+ ARM_VQNEGv16i8 = 1540, >+ ARM_VQNEGv2i32 = 1541, >+ ARM_VQNEGv4i16 = 1542, >+ ARM_VQNEGv4i32 = 1543, >+ ARM_VQNEGv8i16 = 1544, >+ ARM_VQNEGv8i8 = 1545, >+ ARM_VQRDMULHslv2i32 = 1546, >+ ARM_VQRDMULHslv4i16 = 1547, >+ ARM_VQRDMULHslv4i32 = 1548, >+ ARM_VQRDMULHslv8i16 = 1549, >+ ARM_VQRDMULHv2i32 = 1550, >+ ARM_VQRDMULHv4i16 = 1551, >+ ARM_VQRDMULHv4i32 = 1552, >+ ARM_VQRDMULHv8i16 = 1553, >+ ARM_VQRSHLsv16i8 = 1554, >+ ARM_VQRSHLsv1i64 = 1555, >+ ARM_VQRSHLsv2i32 = 1556, >+ ARM_VQRSHLsv2i64 = 1557, >+ ARM_VQRSHLsv4i16 = 1558, >+ ARM_VQRSHLsv4i32 = 1559, >+ ARM_VQRSHLsv8i16 = 1560, >+ ARM_VQRSHLsv8i8 = 1561, >+ ARM_VQRSHLuv16i8 = 1562, >+ ARM_VQRSHLuv1i64 = 1563, >+ ARM_VQRSHLuv2i32 = 1564, >+ ARM_VQRSHLuv2i64 = 1565, >+ ARM_VQRSHLuv4i16 = 1566, >+ ARM_VQRSHLuv4i32 = 1567, >+ ARM_VQRSHLuv8i16 = 1568, >+ ARM_VQRSHLuv8i8 = 1569, >+ ARM_VQRSHRNsv2i32 = 1570, >+ ARM_VQRSHRNsv4i16 = 1571, >+ ARM_VQRSHRNsv8i8 = 1572, >+ ARM_VQRSHRNuv2i32 = 1573, >+ ARM_VQRSHRNuv4i16 = 1574, >+ ARM_VQRSHRNuv8i8 = 1575, >+ ARM_VQRSHRUNv2i32 = 1576, >+ ARM_VQRSHRUNv4i16 = 1577, >+ ARM_VQRSHRUNv8i8 = 1578, >+ ARM_VQSHLsiv16i8 = 1579, >+ ARM_VQSHLsiv1i64 = 1580, >+ ARM_VQSHLsiv2i32 = 1581, >+ ARM_VQSHLsiv2i64 = 1582, >+ ARM_VQSHLsiv4i16 = 1583, >+ ARM_VQSHLsiv4i32 = 1584, >+ ARM_VQSHLsiv8i16 = 1585, >+ ARM_VQSHLsiv8i8 = 1586, >+ ARM_VQSHLsuv16i8 = 1587, >+ ARM_VQSHLsuv1i64 = 1588, >+ ARM_VQSHLsuv2i32 = 1589, >+ ARM_VQSHLsuv2i64 = 1590, >+ ARM_VQSHLsuv4i16 = 1591, >+ ARM_VQSHLsuv4i32 = 1592, >+ ARM_VQSHLsuv8i16 = 1593, >+ ARM_VQSHLsuv8i8 = 1594, >+ ARM_VQSHLsv16i8 = 1595, >+ ARM_VQSHLsv1i64 = 1596, >+ ARM_VQSHLsv2i32 = 1597, >+ ARM_VQSHLsv2i64 = 1598, >+ ARM_VQSHLsv4i16 = 1599, >+ ARM_VQSHLsv4i32 = 1600, >+ ARM_VQSHLsv8i16 = 1601, >+ ARM_VQSHLsv8i8 = 1602, >+ ARM_VQSHLuiv16i8 = 1603, >+ ARM_VQSHLuiv1i64 = 1604, >+ ARM_VQSHLuiv2i32 = 1605, >+ ARM_VQSHLuiv2i64 = 1606, >+ ARM_VQSHLuiv4i16 = 1607, >+ ARM_VQSHLuiv4i32 = 1608, >+ ARM_VQSHLuiv8i16 = 1609, >+ ARM_VQSHLuiv8i8 = 1610, >+ ARM_VQSHLuv16i8 = 1611, >+ ARM_VQSHLuv1i64 = 1612, >+ ARM_VQSHLuv2i32 = 1613, >+ ARM_VQSHLuv2i64 = 1614, >+ ARM_VQSHLuv4i16 = 1615, >+ ARM_VQSHLuv4i32 = 1616, >+ ARM_VQSHLuv8i16 = 1617, >+ ARM_VQSHLuv8i8 = 1618, >+ ARM_VQSHRNsv2i32 = 1619, >+ ARM_VQSHRNsv4i16 = 1620, >+ ARM_VQSHRNsv8i8 = 1621, >+ ARM_VQSHRNuv2i32 = 1622, >+ ARM_VQSHRNuv4i16 = 1623, >+ ARM_VQSHRNuv8i8 = 1624, >+ ARM_VQSHRUNv2i32 = 1625, >+ ARM_VQSHRUNv4i16 = 1626, >+ ARM_VQSHRUNv8i8 = 1627, >+ ARM_VQSUBsv16i8 = 1628, >+ ARM_VQSUBsv1i64 = 1629, >+ ARM_VQSUBsv2i32 = 1630, >+ ARM_VQSUBsv2i64 = 1631, >+ ARM_VQSUBsv4i16 = 1632, >+ ARM_VQSUBsv4i32 = 1633, >+ ARM_VQSUBsv8i16 = 1634, >+ ARM_VQSUBsv8i8 = 1635, >+ ARM_VQSUBuv16i8 = 1636, >+ ARM_VQSUBuv1i64 = 1637, >+ ARM_VQSUBuv2i32 = 1638, >+ ARM_VQSUBuv2i64 = 1639, >+ ARM_VQSUBuv4i16 = 1640, >+ ARM_VQSUBuv4i32 = 1641, >+ ARM_VQSUBuv8i16 = 1642, >+ ARM_VQSUBuv8i8 = 1643, >+ ARM_VRADDHNv2i32 = 1644, >+ ARM_VRADDHNv4i16 = 1645, >+ ARM_VRADDHNv8i8 = 1646, >+ ARM_VRECPEd = 1647, >+ ARM_VRECPEfd = 1648, >+ ARM_VRECPEfq = 1649, >+ ARM_VRECPEq = 1650, >+ ARM_VRECPSfd = 1651, >+ ARM_VRECPSfq = 1652, >+ ARM_VREV16d8 = 1653, >+ ARM_VREV16q8 = 1654, >+ ARM_VREV32d16 = 1655, >+ ARM_VREV32d8 = 1656, >+ ARM_VREV32q16 = 1657, >+ ARM_VREV32q8 = 1658, >+ ARM_VREV64d16 = 1659, >+ ARM_VREV64d32 = 1660, >+ ARM_VREV64d8 = 1661, >+ ARM_VREV64q16 = 1662, >+ ARM_VREV64q32 = 1663, >+ ARM_VREV64q8 = 1664, >+ ARM_VRHADDsv16i8 = 1665, >+ ARM_VRHADDsv2i32 = 1666, >+ ARM_VRHADDsv4i16 = 1667, >+ ARM_VRHADDsv4i32 = 1668, >+ ARM_VRHADDsv8i16 = 1669, >+ ARM_VRHADDsv8i8 = 1670, >+ ARM_VRHADDuv16i8 = 1671, >+ ARM_VRHADDuv2i32 = 1672, >+ ARM_VRHADDuv4i16 = 1673, >+ ARM_VRHADDuv4i32 = 1674, >+ ARM_VRHADDuv8i16 = 1675, >+ ARM_VRHADDuv8i8 = 1676, >+ ARM_VRINTAD = 1677, >+ ARM_VRINTAND = 1678, >+ ARM_VRINTANQ = 1679, >+ ARM_VRINTAS = 1680, >+ ARM_VRINTMD = 1681, >+ ARM_VRINTMND = 1682, >+ ARM_VRINTMNQ = 1683, >+ ARM_VRINTMS = 1684, >+ ARM_VRINTND = 1685, >+ ARM_VRINTNND = 1686, >+ ARM_VRINTNNQ = 1687, >+ ARM_VRINTNS = 1688, >+ ARM_VRINTPD = 1689, >+ ARM_VRINTPND = 1690, >+ ARM_VRINTPNQ = 1691, >+ ARM_VRINTPS = 1692, >+ ARM_VRINTRD = 1693, >+ ARM_VRINTRS = 1694, >+ ARM_VRINTXD = 1695, >+ ARM_VRINTXND = 1696, >+ ARM_VRINTXNQ = 1697, >+ ARM_VRINTXS = 1698, >+ ARM_VRINTZD = 1699, >+ ARM_VRINTZND = 1700, >+ ARM_VRINTZNQ = 1701, >+ ARM_VRINTZS = 1702, >+ ARM_VRSHLsv16i8 = 1703, >+ ARM_VRSHLsv1i64 = 1704, >+ ARM_VRSHLsv2i32 = 1705, >+ ARM_VRSHLsv2i64 = 1706, >+ ARM_VRSHLsv4i16 = 1707, >+ ARM_VRSHLsv4i32 = 1708, >+ ARM_VRSHLsv8i16 = 1709, >+ ARM_VRSHLsv8i8 = 1710, >+ ARM_VRSHLuv16i8 = 1711, >+ ARM_VRSHLuv1i64 = 1712, >+ ARM_VRSHLuv2i32 = 1713, >+ ARM_VRSHLuv2i64 = 1714, >+ ARM_VRSHLuv4i16 = 1715, >+ ARM_VRSHLuv4i32 = 1716, >+ ARM_VRSHLuv8i16 = 1717, >+ ARM_VRSHLuv8i8 = 1718, >+ ARM_VRSHRNv2i32 = 1719, >+ ARM_VRSHRNv4i16 = 1720, >+ ARM_VRSHRNv8i8 = 1721, >+ ARM_VRSHRsv16i8 = 1722, >+ ARM_VRSHRsv1i64 = 1723, >+ ARM_VRSHRsv2i32 = 1724, >+ ARM_VRSHRsv2i64 = 1725, >+ ARM_VRSHRsv4i16 = 1726, >+ ARM_VRSHRsv4i32 = 1727, >+ ARM_VRSHRsv8i16 = 1728, >+ ARM_VRSHRsv8i8 = 1729, >+ ARM_VRSHRuv16i8 = 1730, >+ ARM_VRSHRuv1i64 = 1731, >+ ARM_VRSHRuv2i32 = 1732, >+ ARM_VRSHRuv2i64 = 1733, >+ ARM_VRSHRuv4i16 = 1734, >+ ARM_VRSHRuv4i32 = 1735, >+ ARM_VRSHRuv8i16 = 1736, >+ ARM_VRSHRuv8i8 = 1737, >+ ARM_VRSQRTEd = 1738, >+ ARM_VRSQRTEfd = 1739, >+ ARM_VRSQRTEfq = 1740, >+ ARM_VRSQRTEq = 1741, >+ ARM_VRSQRTSfd = 1742, >+ ARM_VRSQRTSfq = 1743, >+ ARM_VRSRAsv16i8 = 1744, >+ ARM_VRSRAsv1i64 = 1745, >+ ARM_VRSRAsv2i32 = 1746, >+ ARM_VRSRAsv2i64 = 1747, >+ ARM_VRSRAsv4i16 = 1748, >+ ARM_VRSRAsv4i32 = 1749, >+ ARM_VRSRAsv8i16 = 1750, >+ ARM_VRSRAsv8i8 = 1751, >+ ARM_VRSRAuv16i8 = 1752, >+ ARM_VRSRAuv1i64 = 1753, >+ ARM_VRSRAuv2i32 = 1754, >+ ARM_VRSRAuv2i64 = 1755, >+ ARM_VRSRAuv4i16 = 1756, >+ ARM_VRSRAuv4i32 = 1757, >+ ARM_VRSRAuv8i16 = 1758, >+ ARM_VRSRAuv8i8 = 1759, >+ ARM_VRSUBHNv2i32 = 1760, >+ ARM_VRSUBHNv4i16 = 1761, >+ ARM_VRSUBHNv8i8 = 1762, >+ ARM_VSELEQD = 1763, >+ ARM_VSELEQS = 1764, >+ ARM_VSELGED = 1765, >+ ARM_VSELGES = 1766, >+ ARM_VSELGTD = 1767, >+ ARM_VSELGTS = 1768, >+ ARM_VSELVSD = 1769, >+ ARM_VSELVSS = 1770, >+ ARM_VSETLNi16 = 1771, >+ ARM_VSETLNi32 = 1772, >+ ARM_VSETLNi8 = 1773, >+ ARM_VSHLLi16 = 1774, >+ ARM_VSHLLi32 = 1775, >+ ARM_VSHLLi8 = 1776, >+ ARM_VSHLLsv2i64 = 1777, >+ ARM_VSHLLsv4i32 = 1778, >+ ARM_VSHLLsv8i16 = 1779, >+ ARM_VSHLLuv2i64 = 1780, >+ ARM_VSHLLuv4i32 = 1781, >+ ARM_VSHLLuv8i16 = 1782, >+ ARM_VSHLiv16i8 = 1783, >+ ARM_VSHLiv1i64 = 1784, >+ ARM_VSHLiv2i32 = 1785, >+ ARM_VSHLiv2i64 = 1786, >+ ARM_VSHLiv4i16 = 1787, >+ ARM_VSHLiv4i32 = 1788, >+ ARM_VSHLiv8i16 = 1789, >+ ARM_VSHLiv8i8 = 1790, >+ ARM_VSHLsv16i8 = 1791, >+ ARM_VSHLsv1i64 = 1792, >+ ARM_VSHLsv2i32 = 1793, >+ ARM_VSHLsv2i64 = 1794, >+ ARM_VSHLsv4i16 = 1795, >+ ARM_VSHLsv4i32 = 1796, >+ ARM_VSHLsv8i16 = 1797, >+ ARM_VSHLsv8i8 = 1798, >+ ARM_VSHLuv16i8 = 1799, >+ ARM_VSHLuv1i64 = 1800, >+ ARM_VSHLuv2i32 = 1801, >+ ARM_VSHLuv2i64 = 1802, >+ ARM_VSHLuv4i16 = 1803, >+ ARM_VSHLuv4i32 = 1804, >+ ARM_VSHLuv8i16 = 1805, >+ ARM_VSHLuv8i8 = 1806, >+ ARM_VSHRNv2i32 = 1807, >+ ARM_VSHRNv4i16 = 1808, >+ ARM_VSHRNv8i8 = 1809, >+ ARM_VSHRsv16i8 = 1810, >+ ARM_VSHRsv1i64 = 1811, >+ ARM_VSHRsv2i32 = 1812, >+ ARM_VSHRsv2i64 = 1813, >+ ARM_VSHRsv4i16 = 1814, >+ ARM_VSHRsv4i32 = 1815, >+ ARM_VSHRsv8i16 = 1816, >+ ARM_VSHRsv8i8 = 1817, >+ ARM_VSHRuv16i8 = 1818, >+ ARM_VSHRuv1i64 = 1819, >+ ARM_VSHRuv2i32 = 1820, >+ ARM_VSHRuv2i64 = 1821, >+ ARM_VSHRuv4i16 = 1822, >+ ARM_VSHRuv4i32 = 1823, >+ ARM_VSHRuv8i16 = 1824, >+ ARM_VSHRuv8i8 = 1825, >+ ARM_VSHTOD = 1826, >+ ARM_VSHTOS = 1827, >+ ARM_VSITOD = 1828, >+ ARM_VSITOS = 1829, >+ ARM_VSLIv16i8 = 1830, >+ ARM_VSLIv1i64 = 1831, >+ ARM_VSLIv2i32 = 1832, >+ ARM_VSLIv2i64 = 1833, >+ ARM_VSLIv4i16 = 1834, >+ ARM_VSLIv4i32 = 1835, >+ ARM_VSLIv8i16 = 1836, >+ ARM_VSLIv8i8 = 1837, >+ ARM_VSLTOD = 1838, >+ ARM_VSLTOS = 1839, >+ ARM_VSQRTD = 1840, >+ ARM_VSQRTS = 1841, >+ ARM_VSRAsv16i8 = 1842, >+ ARM_VSRAsv1i64 = 1843, >+ ARM_VSRAsv2i32 = 1844, >+ ARM_VSRAsv2i64 = 1845, >+ ARM_VSRAsv4i16 = 1846, >+ ARM_VSRAsv4i32 = 1847, >+ ARM_VSRAsv8i16 = 1848, >+ ARM_VSRAsv8i8 = 1849, >+ ARM_VSRAuv16i8 = 1850, >+ ARM_VSRAuv1i64 = 1851, >+ ARM_VSRAuv2i32 = 1852, >+ ARM_VSRAuv2i64 = 1853, >+ ARM_VSRAuv4i16 = 1854, >+ ARM_VSRAuv4i32 = 1855, >+ ARM_VSRAuv8i16 = 1856, >+ ARM_VSRAuv8i8 = 1857, >+ ARM_VSRIv16i8 = 1858, >+ ARM_VSRIv1i64 = 1859, >+ ARM_VSRIv2i32 = 1860, >+ ARM_VSRIv2i64 = 1861, >+ ARM_VSRIv4i16 = 1862, >+ ARM_VSRIv4i32 = 1863, >+ ARM_VSRIv8i16 = 1864, >+ ARM_VSRIv8i8 = 1865, >+ ARM_VST1LNd16 = 1866, >+ ARM_VST1LNd16_UPD = 1867, >+ ARM_VST1LNd32 = 1868, >+ ARM_VST1LNd32_UPD = 1869, >+ ARM_VST1LNd8 = 1870, >+ ARM_VST1LNd8_UPD = 1871, >+ ARM_VST1LNdAsm_16 = 1872, >+ ARM_VST1LNdAsm_32 = 1873, >+ ARM_VST1LNdAsm_8 = 1874, >+ ARM_VST1LNdWB_fixed_Asm_16 = 1875, >+ ARM_VST1LNdWB_fixed_Asm_32 = 1876, >+ ARM_VST1LNdWB_fixed_Asm_8 = 1877, >+ ARM_VST1LNdWB_register_Asm_16 = 1878, >+ ARM_VST1LNdWB_register_Asm_32 = 1879, >+ ARM_VST1LNdWB_register_Asm_8 = 1880, >+ ARM_VST1LNq16Pseudo = 1881, >+ ARM_VST1LNq16Pseudo_UPD = 1882, >+ ARM_VST1LNq32Pseudo = 1883, >+ ARM_VST1LNq32Pseudo_UPD = 1884, >+ ARM_VST1LNq8Pseudo = 1885, >+ ARM_VST1LNq8Pseudo_UPD = 1886, >+ ARM_VST1d16 = 1887, >+ ARM_VST1d16Q = 1888, >+ ARM_VST1d16Qwb_fixed = 1889, >+ ARM_VST1d16Qwb_register = 1890, >+ ARM_VST1d16T = 1891, >+ ARM_VST1d16Twb_fixed = 1892, >+ ARM_VST1d16Twb_register = 1893, >+ ARM_VST1d16wb_fixed = 1894, >+ ARM_VST1d16wb_register = 1895, >+ ARM_VST1d32 = 1896, >+ ARM_VST1d32Q = 1897, >+ ARM_VST1d32Qwb_fixed = 1898, >+ ARM_VST1d32Qwb_register = 1899, >+ ARM_VST1d32T = 1900, >+ ARM_VST1d32Twb_fixed = 1901, >+ ARM_VST1d32Twb_register = 1902, >+ ARM_VST1d32wb_fixed = 1903, >+ ARM_VST1d32wb_register = 1904, >+ ARM_VST1d64 = 1905, >+ ARM_VST1d64Q = 1906, >+ ARM_VST1d64QPseudo = 1907, >+ ARM_VST1d64QPseudoWB_fixed = 1908, >+ ARM_VST1d64QPseudoWB_register = 1909, >+ ARM_VST1d64Qwb_fixed = 1910, >+ ARM_VST1d64Qwb_register = 1911, >+ ARM_VST1d64T = 1912, >+ ARM_VST1d64TPseudo = 1913, >+ ARM_VST1d64TPseudoWB_fixed = 1914, >+ ARM_VST1d64TPseudoWB_register = 1915, >+ ARM_VST1d64Twb_fixed = 1916, >+ ARM_VST1d64Twb_register = 1917, >+ ARM_VST1d64wb_fixed = 1918, >+ ARM_VST1d64wb_register = 1919, >+ ARM_VST1d8 = 1920, >+ ARM_VST1d8Q = 1921, >+ ARM_VST1d8Qwb_fixed = 1922, >+ ARM_VST1d8Qwb_register = 1923, >+ ARM_VST1d8T = 1924, >+ ARM_VST1d8Twb_fixed = 1925, >+ ARM_VST1d8Twb_register = 1926, >+ ARM_VST1d8wb_fixed = 1927, >+ ARM_VST1d8wb_register = 1928, >+ ARM_VST1q16 = 1929, >+ ARM_VST1q16wb_fixed = 1930, >+ ARM_VST1q16wb_register = 1931, >+ ARM_VST1q32 = 1932, >+ ARM_VST1q32wb_fixed = 1933, >+ ARM_VST1q32wb_register = 1934, >+ ARM_VST1q64 = 1935, >+ ARM_VST1q64wb_fixed = 1936, >+ ARM_VST1q64wb_register = 1937, >+ ARM_VST1q8 = 1938, >+ ARM_VST1q8wb_fixed = 1939, >+ ARM_VST1q8wb_register = 1940, >+ ARM_VST2LNd16 = 1941, >+ ARM_VST2LNd16Pseudo = 1942, >+ ARM_VST2LNd16Pseudo_UPD = 1943, >+ ARM_VST2LNd16_UPD = 1944, >+ ARM_VST2LNd32 = 1945, >+ ARM_VST2LNd32Pseudo = 1946, >+ ARM_VST2LNd32Pseudo_UPD = 1947, >+ ARM_VST2LNd32_UPD = 1948, >+ ARM_VST2LNd8 = 1949, >+ ARM_VST2LNd8Pseudo = 1950, >+ ARM_VST2LNd8Pseudo_UPD = 1951, >+ ARM_VST2LNd8_UPD = 1952, >+ ARM_VST2LNdAsm_16 = 1953, >+ ARM_VST2LNdAsm_32 = 1954, >+ ARM_VST2LNdAsm_8 = 1955, >+ ARM_VST2LNdWB_fixed_Asm_16 = 1956, >+ ARM_VST2LNdWB_fixed_Asm_32 = 1957, >+ ARM_VST2LNdWB_fixed_Asm_8 = 1958, >+ ARM_VST2LNdWB_register_Asm_16 = 1959, >+ ARM_VST2LNdWB_register_Asm_32 = 1960, >+ ARM_VST2LNdWB_register_Asm_8 = 1961, >+ ARM_VST2LNq16 = 1962, >+ ARM_VST2LNq16Pseudo = 1963, >+ ARM_VST2LNq16Pseudo_UPD = 1964, >+ ARM_VST2LNq16_UPD = 1965, >+ ARM_VST2LNq32 = 1966, >+ ARM_VST2LNq32Pseudo = 1967, >+ ARM_VST2LNq32Pseudo_UPD = 1968, >+ ARM_VST2LNq32_UPD = 1969, >+ ARM_VST2LNqAsm_16 = 1970, >+ ARM_VST2LNqAsm_32 = 1971, >+ ARM_VST2LNqWB_fixed_Asm_16 = 1972, >+ ARM_VST2LNqWB_fixed_Asm_32 = 1973, >+ ARM_VST2LNqWB_register_Asm_16 = 1974, >+ ARM_VST2LNqWB_register_Asm_32 = 1975, >+ ARM_VST2b16 = 1976, >+ ARM_VST2b16wb_fixed = 1977, >+ ARM_VST2b16wb_register = 1978, >+ ARM_VST2b32 = 1979, >+ ARM_VST2b32wb_fixed = 1980, >+ ARM_VST2b32wb_register = 1981, >+ ARM_VST2b8 = 1982, >+ ARM_VST2b8wb_fixed = 1983, >+ ARM_VST2b8wb_register = 1984, >+ ARM_VST2d16 = 1985, >+ ARM_VST2d16wb_fixed = 1986, >+ ARM_VST2d16wb_register = 1987, >+ ARM_VST2d32 = 1988, >+ ARM_VST2d32wb_fixed = 1989, >+ ARM_VST2d32wb_register = 1990, >+ ARM_VST2d8 = 1991, >+ ARM_VST2d8wb_fixed = 1992, >+ ARM_VST2d8wb_register = 1993, >+ ARM_VST2q16 = 1994, >+ ARM_VST2q16Pseudo = 1995, >+ ARM_VST2q16PseudoWB_fixed = 1996, >+ ARM_VST2q16PseudoWB_register = 1997, >+ ARM_VST2q16wb_fixed = 1998, >+ ARM_VST2q16wb_register = 1999, >+ ARM_VST2q32 = 2000, >+ ARM_VST2q32Pseudo = 2001, >+ ARM_VST2q32PseudoWB_fixed = 2002, >+ ARM_VST2q32PseudoWB_register = 2003, >+ ARM_VST2q32wb_fixed = 2004, >+ ARM_VST2q32wb_register = 2005, >+ ARM_VST2q8 = 2006, >+ ARM_VST2q8Pseudo = 2007, >+ ARM_VST2q8PseudoWB_fixed = 2008, >+ ARM_VST2q8PseudoWB_register = 2009, >+ ARM_VST2q8wb_fixed = 2010, >+ ARM_VST2q8wb_register = 2011, >+ ARM_VST3LNd16 = 2012, >+ ARM_VST3LNd16Pseudo = 2013, >+ ARM_VST3LNd16Pseudo_UPD = 2014, >+ ARM_VST3LNd16_UPD = 2015, >+ ARM_VST3LNd32 = 2016, >+ ARM_VST3LNd32Pseudo = 2017, >+ ARM_VST3LNd32Pseudo_UPD = 2018, >+ ARM_VST3LNd32_UPD = 2019, >+ ARM_VST3LNd8 = 2020, >+ ARM_VST3LNd8Pseudo = 2021, >+ ARM_VST3LNd8Pseudo_UPD = 2022, >+ ARM_VST3LNd8_UPD = 2023, >+ ARM_VST3LNdAsm_16 = 2024, >+ ARM_VST3LNdAsm_32 = 2025, >+ ARM_VST3LNdAsm_8 = 2026, >+ ARM_VST3LNdWB_fixed_Asm_16 = 2027, >+ ARM_VST3LNdWB_fixed_Asm_32 = 2028, >+ ARM_VST3LNdWB_fixed_Asm_8 = 2029, >+ ARM_VST3LNdWB_register_Asm_16 = 2030, >+ ARM_VST3LNdWB_register_Asm_32 = 2031, >+ ARM_VST3LNdWB_register_Asm_8 = 2032, >+ ARM_VST3LNq16 = 2033, >+ ARM_VST3LNq16Pseudo = 2034, >+ ARM_VST3LNq16Pseudo_UPD = 2035, >+ ARM_VST3LNq16_UPD = 2036, >+ ARM_VST3LNq32 = 2037, >+ ARM_VST3LNq32Pseudo = 2038, >+ ARM_VST3LNq32Pseudo_UPD = 2039, >+ ARM_VST3LNq32_UPD = 2040, >+ ARM_VST3LNqAsm_16 = 2041, >+ ARM_VST3LNqAsm_32 = 2042, >+ ARM_VST3LNqWB_fixed_Asm_16 = 2043, >+ ARM_VST3LNqWB_fixed_Asm_32 = 2044, >+ ARM_VST3LNqWB_register_Asm_16 = 2045, >+ ARM_VST3LNqWB_register_Asm_32 = 2046, >+ ARM_VST3d16 = 2047, >+ ARM_VST3d16Pseudo = 2048, >+ ARM_VST3d16Pseudo_UPD = 2049, >+ ARM_VST3d16_UPD = 2050, >+ ARM_VST3d32 = 2051, >+ ARM_VST3d32Pseudo = 2052, >+ ARM_VST3d32Pseudo_UPD = 2053, >+ ARM_VST3d32_UPD = 2054, >+ ARM_VST3d8 = 2055, >+ ARM_VST3d8Pseudo = 2056, >+ ARM_VST3d8Pseudo_UPD = 2057, >+ ARM_VST3d8_UPD = 2058, >+ ARM_VST3dAsm_16 = 2059, >+ ARM_VST3dAsm_32 = 2060, >+ ARM_VST3dAsm_8 = 2061, >+ ARM_VST3dWB_fixed_Asm_16 = 2062, >+ ARM_VST3dWB_fixed_Asm_32 = 2063, >+ ARM_VST3dWB_fixed_Asm_8 = 2064, >+ ARM_VST3dWB_register_Asm_16 = 2065, >+ ARM_VST3dWB_register_Asm_32 = 2066, >+ ARM_VST3dWB_register_Asm_8 = 2067, >+ ARM_VST3q16 = 2068, >+ ARM_VST3q16Pseudo_UPD = 2069, >+ ARM_VST3q16_UPD = 2070, >+ ARM_VST3q16oddPseudo = 2071, >+ ARM_VST3q16oddPseudo_UPD = 2072, >+ ARM_VST3q32 = 2073, >+ ARM_VST3q32Pseudo_UPD = 2074, >+ ARM_VST3q32_UPD = 2075, >+ ARM_VST3q32oddPseudo = 2076, >+ ARM_VST3q32oddPseudo_UPD = 2077, >+ ARM_VST3q8 = 2078, >+ ARM_VST3q8Pseudo_UPD = 2079, >+ ARM_VST3q8_UPD = 2080, >+ ARM_VST3q8oddPseudo = 2081, >+ ARM_VST3q8oddPseudo_UPD = 2082, >+ ARM_VST3qAsm_16 = 2083, >+ ARM_VST3qAsm_32 = 2084, >+ ARM_VST3qAsm_8 = 2085, >+ ARM_VST3qWB_fixed_Asm_16 = 2086, >+ ARM_VST3qWB_fixed_Asm_32 = 2087, >+ ARM_VST3qWB_fixed_Asm_8 = 2088, >+ ARM_VST3qWB_register_Asm_16 = 2089, >+ ARM_VST3qWB_register_Asm_32 = 2090, >+ ARM_VST3qWB_register_Asm_8 = 2091, >+ ARM_VST4LNd16 = 2092, >+ ARM_VST4LNd16Pseudo = 2093, >+ ARM_VST4LNd16Pseudo_UPD = 2094, >+ ARM_VST4LNd16_UPD = 2095, >+ ARM_VST4LNd32 = 2096, >+ ARM_VST4LNd32Pseudo = 2097, >+ ARM_VST4LNd32Pseudo_UPD = 2098, >+ ARM_VST4LNd32_UPD = 2099, >+ ARM_VST4LNd8 = 2100, >+ ARM_VST4LNd8Pseudo = 2101, >+ ARM_VST4LNd8Pseudo_UPD = 2102, >+ ARM_VST4LNd8_UPD = 2103, >+ ARM_VST4LNdAsm_16 = 2104, >+ ARM_VST4LNdAsm_32 = 2105, >+ ARM_VST4LNdAsm_8 = 2106, >+ ARM_VST4LNdWB_fixed_Asm_16 = 2107, >+ ARM_VST4LNdWB_fixed_Asm_32 = 2108, >+ ARM_VST4LNdWB_fixed_Asm_8 = 2109, >+ ARM_VST4LNdWB_register_Asm_16 = 2110, >+ ARM_VST4LNdWB_register_Asm_32 = 2111, >+ ARM_VST4LNdWB_register_Asm_8 = 2112, >+ ARM_VST4LNq16 = 2113, >+ ARM_VST4LNq16Pseudo = 2114, >+ ARM_VST4LNq16Pseudo_UPD = 2115, >+ ARM_VST4LNq16_UPD = 2116, >+ ARM_VST4LNq32 = 2117, >+ ARM_VST4LNq32Pseudo = 2118, >+ ARM_VST4LNq32Pseudo_UPD = 2119, >+ ARM_VST4LNq32_UPD = 2120, >+ ARM_VST4LNqAsm_16 = 2121, >+ ARM_VST4LNqAsm_32 = 2122, >+ ARM_VST4LNqWB_fixed_Asm_16 = 2123, >+ ARM_VST4LNqWB_fixed_Asm_32 = 2124, >+ ARM_VST4LNqWB_register_Asm_16 = 2125, >+ ARM_VST4LNqWB_register_Asm_32 = 2126, >+ ARM_VST4d16 = 2127, >+ ARM_VST4d16Pseudo = 2128, >+ ARM_VST4d16Pseudo_UPD = 2129, >+ ARM_VST4d16_UPD = 2130, >+ ARM_VST4d32 = 2131, >+ ARM_VST4d32Pseudo = 2132, >+ ARM_VST4d32Pseudo_UPD = 2133, >+ ARM_VST4d32_UPD = 2134, >+ ARM_VST4d8 = 2135, >+ ARM_VST4d8Pseudo = 2136, >+ ARM_VST4d8Pseudo_UPD = 2137, >+ ARM_VST4d8_UPD = 2138, >+ ARM_VST4dAsm_16 = 2139, >+ ARM_VST4dAsm_32 = 2140, >+ ARM_VST4dAsm_8 = 2141, >+ ARM_VST4dWB_fixed_Asm_16 = 2142, >+ ARM_VST4dWB_fixed_Asm_32 = 2143, >+ ARM_VST4dWB_fixed_Asm_8 = 2144, >+ ARM_VST4dWB_register_Asm_16 = 2145, >+ ARM_VST4dWB_register_Asm_32 = 2146, >+ ARM_VST4dWB_register_Asm_8 = 2147, >+ ARM_VST4q16 = 2148, >+ ARM_VST4q16Pseudo_UPD = 2149, >+ ARM_VST4q16_UPD = 2150, >+ ARM_VST4q16oddPseudo = 2151, >+ ARM_VST4q16oddPseudo_UPD = 2152, >+ ARM_VST4q32 = 2153, >+ ARM_VST4q32Pseudo_UPD = 2154, >+ ARM_VST4q32_UPD = 2155, >+ ARM_VST4q32oddPseudo = 2156, >+ ARM_VST4q32oddPseudo_UPD = 2157, >+ ARM_VST4q8 = 2158, >+ ARM_VST4q8Pseudo_UPD = 2159, >+ ARM_VST4q8_UPD = 2160, >+ ARM_VST4q8oddPseudo = 2161, >+ ARM_VST4q8oddPseudo_UPD = 2162, >+ ARM_VST4qAsm_16 = 2163, >+ ARM_VST4qAsm_32 = 2164, >+ ARM_VST4qAsm_8 = 2165, >+ ARM_VST4qWB_fixed_Asm_16 = 2166, >+ ARM_VST4qWB_fixed_Asm_32 = 2167, >+ ARM_VST4qWB_fixed_Asm_8 = 2168, >+ ARM_VST4qWB_register_Asm_16 = 2169, >+ ARM_VST4qWB_register_Asm_32 = 2170, >+ ARM_VST4qWB_register_Asm_8 = 2171, >+ ARM_VSTMDDB_UPD = 2172, >+ ARM_VSTMDIA = 2173, >+ ARM_VSTMDIA_UPD = 2174, >+ ARM_VSTMQIA = 2175, >+ ARM_VSTMSDB_UPD = 2176, >+ ARM_VSTMSIA = 2177, >+ ARM_VSTMSIA_UPD = 2178, >+ ARM_VSTRD = 2179, >+ ARM_VSTRS = 2180, >+ ARM_VSUBD = 2181, >+ ARM_VSUBHNv2i32 = 2182, >+ ARM_VSUBHNv4i16 = 2183, >+ ARM_VSUBHNv8i8 = 2184, >+ ARM_VSUBLsv2i64 = 2185, >+ ARM_VSUBLsv4i32 = 2186, >+ ARM_VSUBLsv8i16 = 2187, >+ ARM_VSUBLuv2i64 = 2188, >+ ARM_VSUBLuv4i32 = 2189, >+ ARM_VSUBLuv8i16 = 2190, >+ ARM_VSUBS = 2191, >+ ARM_VSUBWsv2i64 = 2192, >+ ARM_VSUBWsv4i32 = 2193, >+ ARM_VSUBWsv8i16 = 2194, >+ ARM_VSUBWuv2i64 = 2195, >+ ARM_VSUBWuv4i32 = 2196, >+ ARM_VSUBWuv8i16 = 2197, >+ ARM_VSUBfd = 2198, >+ ARM_VSUBfq = 2199, >+ ARM_VSUBv16i8 = 2200, >+ ARM_VSUBv1i64 = 2201, >+ ARM_VSUBv2i32 = 2202, >+ ARM_VSUBv2i64 = 2203, >+ ARM_VSUBv4i16 = 2204, >+ ARM_VSUBv4i32 = 2205, >+ ARM_VSUBv8i16 = 2206, >+ ARM_VSUBv8i8 = 2207, >+ ARM_VSWPd = 2208, >+ ARM_VSWPq = 2209, >+ ARM_VTBL1 = 2210, >+ ARM_VTBL2 = 2211, >+ ARM_VTBL3 = 2212, >+ ARM_VTBL3Pseudo = 2213, >+ ARM_VTBL4 = 2214, >+ ARM_VTBL4Pseudo = 2215, >+ ARM_VTBX1 = 2216, >+ ARM_VTBX2 = 2217, >+ ARM_VTBX3 = 2218, >+ ARM_VTBX3Pseudo = 2219, >+ ARM_VTBX4 = 2220, >+ ARM_VTBX4Pseudo = 2221, >+ ARM_VTOSHD = 2222, >+ ARM_VTOSHS = 2223, >+ ARM_VTOSIRD = 2224, >+ ARM_VTOSIRS = 2225, >+ ARM_VTOSIZD = 2226, >+ ARM_VTOSIZS = 2227, >+ ARM_VTOSLD = 2228, >+ ARM_VTOSLS = 2229, >+ ARM_VTOUHD = 2230, >+ ARM_VTOUHS = 2231, >+ ARM_VTOUIRD = 2232, >+ ARM_VTOUIRS = 2233, >+ ARM_VTOUIZD = 2234, >+ ARM_VTOUIZS = 2235, >+ ARM_VTOULD = 2236, >+ ARM_VTOULS = 2237, >+ ARM_VTRNd16 = 2238, >+ ARM_VTRNd32 = 2239, >+ ARM_VTRNd8 = 2240, >+ ARM_VTRNq16 = 2241, >+ ARM_VTRNq32 = 2242, >+ ARM_VTRNq8 = 2243, >+ ARM_VTSTv16i8 = 2244, >+ ARM_VTSTv2i32 = 2245, >+ ARM_VTSTv4i16 = 2246, >+ ARM_VTSTv4i32 = 2247, >+ ARM_VTSTv8i16 = 2248, >+ ARM_VTSTv8i8 = 2249, >+ ARM_VUHTOD = 2250, >+ ARM_VUHTOS = 2251, >+ ARM_VUITOD = 2252, >+ ARM_VUITOS = 2253, >+ ARM_VULTOD = 2254, >+ ARM_VULTOS = 2255, >+ ARM_VUZPd16 = 2256, >+ ARM_VUZPd8 = 2257, >+ ARM_VUZPq16 = 2258, >+ ARM_VUZPq32 = 2259, >+ ARM_VUZPq8 = 2260, >+ ARM_VZIPd16 = 2261, >+ ARM_VZIPd8 = 2262, >+ ARM_VZIPq16 = 2263, >+ ARM_VZIPq32 = 2264, >+ ARM_VZIPq8 = 2265, >+ ARM_WIN__CHKSTK = 2266, >+ ARM_sysLDMDA = 2267, >+ ARM_sysLDMDA_UPD = 2268, >+ ARM_sysLDMDB = 2269, >+ ARM_sysLDMDB_UPD = 2270, >+ ARM_sysLDMIA = 2271, >+ ARM_sysLDMIA_UPD = 2272, >+ ARM_sysLDMIB = 2273, >+ ARM_sysLDMIB_UPD = 2274, >+ ARM_sysSTMDA = 2275, >+ ARM_sysSTMDA_UPD = 2276, >+ ARM_sysSTMDB = 2277, >+ ARM_sysSTMDB_UPD = 2278, >+ ARM_sysSTMIA = 2279, >+ ARM_sysSTMIA_UPD = 2280, >+ ARM_sysSTMIB = 2281, >+ ARM_sysSTMIB_UPD = 2282, >+ ARM_t2ABS = 2283, >+ ARM_t2ADCri = 2284, >+ ARM_t2ADCrr = 2285, >+ ARM_t2ADCrs = 2286, >+ ARM_t2ADDSri = 2287, >+ ARM_t2ADDSrr = 2288, >+ ARM_t2ADDSrs = 2289, >+ ARM_t2ADDri = 2290, >+ ARM_t2ADDri12 = 2291, >+ ARM_t2ADDrr = 2292, >+ ARM_t2ADDrs = 2293, >+ ARM_t2ADR = 2294, >+ ARM_t2ANDri = 2295, >+ ARM_t2ANDrr = 2296, >+ ARM_t2ANDrs = 2297, >+ ARM_t2ASRri = 2298, >+ ARM_t2ASRrr = 2299, >+ ARM_t2B = 2300, >+ ARM_t2BFC = 2301, >+ ARM_t2BFI = 2302, >+ ARM_t2BICri = 2303, >+ ARM_t2BICrr = 2304, >+ ARM_t2BICrs = 2305, >+ ARM_t2BR_JT = 2306, >+ ARM_t2BXJ = 2307, >+ ARM_t2Bcc = 2308, >+ ARM_t2CDP = 2309, >+ ARM_t2CDP2 = 2310, >+ ARM_t2CLREX = 2311, >+ ARM_t2CLZ = 2312, >+ ARM_t2CMNri = 2313, >+ ARM_t2CMNzrr = 2314, >+ ARM_t2CMNzrs = 2315, >+ ARM_t2CMPri = 2316, >+ ARM_t2CMPrr = 2317, >+ ARM_t2CMPrs = 2318, >+ ARM_t2CPS1p = 2319, >+ ARM_t2CPS2p = 2320, >+ ARM_t2CPS3p = 2321, >+ ARM_t2CRC32B = 2322, >+ ARM_t2CRC32CB = 2323, >+ ARM_t2CRC32CH = 2324, >+ ARM_t2CRC32CW = 2325, >+ ARM_t2CRC32H = 2326, >+ ARM_t2CRC32W = 2327, >+ ARM_t2DBG = 2328, >+ ARM_t2DCPS1 = 2329, >+ ARM_t2DCPS2 = 2330, >+ ARM_t2DCPS3 = 2331, >+ ARM_t2DMB = 2332, >+ ARM_t2DSB = 2333, >+ ARM_t2EORri = 2334, >+ ARM_t2EORrr = 2335, >+ ARM_t2EORrs = 2336, >+ ARM_t2HINT = 2337, >+ ARM_t2ISB = 2338, >+ ARM_t2IT = 2339, >+ ARM_t2Int_eh_sjlj_setjmp = 2340, >+ ARM_t2Int_eh_sjlj_setjmp_nofp = 2341, >+ ARM_t2LDA = 2342, >+ ARM_t2LDAB = 2343, >+ ARM_t2LDAEX = 2344, >+ ARM_t2LDAEXB = 2345, >+ ARM_t2LDAEXD = 2346, >+ ARM_t2LDAEXH = 2347, >+ ARM_t2LDAH = 2348, >+ ARM_t2LDC2L_OFFSET = 2349, >+ ARM_t2LDC2L_OPTION = 2350, >+ ARM_t2LDC2L_POST = 2351, >+ ARM_t2LDC2L_PRE = 2352, >+ ARM_t2LDC2_OFFSET = 2353, >+ ARM_t2LDC2_OPTION = 2354, >+ ARM_t2LDC2_POST = 2355, >+ ARM_t2LDC2_PRE = 2356, >+ ARM_t2LDCL_OFFSET = 2357, >+ ARM_t2LDCL_OPTION = 2358, >+ ARM_t2LDCL_POST = 2359, >+ ARM_t2LDCL_PRE = 2360, >+ ARM_t2LDC_OFFSET = 2361, >+ ARM_t2LDC_OPTION = 2362, >+ ARM_t2LDC_POST = 2363, >+ ARM_t2LDC_PRE = 2364, >+ ARM_t2LDMDB = 2365, >+ ARM_t2LDMDB_UPD = 2366, >+ ARM_t2LDMIA = 2367, >+ ARM_t2LDMIA_RET = 2368, >+ ARM_t2LDMIA_UPD = 2369, >+ ARM_t2LDRBT = 2370, >+ ARM_t2LDRB_POST = 2371, >+ ARM_t2LDRB_PRE = 2372, >+ ARM_t2LDRBi12 = 2373, >+ ARM_t2LDRBi8 = 2374, >+ ARM_t2LDRBpci = 2375, >+ ARM_t2LDRBpcrel = 2376, >+ ARM_t2LDRBs = 2377, >+ ARM_t2LDRD_POST = 2378, >+ ARM_t2LDRD_PRE = 2379, >+ ARM_t2LDRDi8 = 2380, >+ ARM_t2LDREX = 2381, >+ ARM_t2LDREXB = 2382, >+ ARM_t2LDREXD = 2383, >+ ARM_t2LDREXH = 2384, >+ ARM_t2LDRHT = 2385, >+ ARM_t2LDRH_POST = 2386, >+ ARM_t2LDRH_PRE = 2387, >+ ARM_t2LDRHi12 = 2388, >+ ARM_t2LDRHi8 = 2389, >+ ARM_t2LDRHpci = 2390, >+ ARM_t2LDRHpcrel = 2391, >+ ARM_t2LDRHs = 2392, >+ ARM_t2LDRSBT = 2393, >+ ARM_t2LDRSB_POST = 2394, >+ ARM_t2LDRSB_PRE = 2395, >+ ARM_t2LDRSBi12 = 2396, >+ ARM_t2LDRSBi8 = 2397, >+ ARM_t2LDRSBpci = 2398, >+ ARM_t2LDRSBpcrel = 2399, >+ ARM_t2LDRSBs = 2400, >+ ARM_t2LDRSHT = 2401, >+ ARM_t2LDRSH_POST = 2402, >+ ARM_t2LDRSH_PRE = 2403, >+ ARM_t2LDRSHi12 = 2404, >+ ARM_t2LDRSHi8 = 2405, >+ ARM_t2LDRSHpci = 2406, >+ ARM_t2LDRSHpcrel = 2407, >+ ARM_t2LDRSHs = 2408, >+ ARM_t2LDRT = 2409, >+ ARM_t2LDR_POST = 2410, >+ ARM_t2LDR_PRE = 2411, >+ ARM_t2LDRi12 = 2412, >+ ARM_t2LDRi8 = 2413, >+ ARM_t2LDRpci = 2414, >+ ARM_t2LDRpci_pic = 2415, >+ ARM_t2LDRpcrel = 2416, >+ ARM_t2LDRs = 2417, >+ ARM_t2LEApcrel = 2418, >+ ARM_t2LEApcrelJT = 2419, >+ ARM_t2LSLri = 2420, >+ ARM_t2LSLrr = 2421, >+ ARM_t2LSRri = 2422, >+ ARM_t2LSRrr = 2423, >+ ARM_t2MCR = 2424, >+ ARM_t2MCR2 = 2425, >+ ARM_t2MCRR = 2426, >+ ARM_t2MCRR2 = 2427, >+ ARM_t2MLA = 2428, >+ ARM_t2MLS = 2429, >+ ARM_t2MOVCCasr = 2430, >+ ARM_t2MOVCCi = 2431, >+ ARM_t2MOVCCi16 = 2432, >+ ARM_t2MOVCCi32imm = 2433, >+ ARM_t2MOVCClsl = 2434, >+ ARM_t2MOVCClsr = 2435, >+ ARM_t2MOVCCr = 2436, >+ ARM_t2MOVCCror = 2437, >+ ARM_t2MOVSsi = 2438, >+ ARM_t2MOVSsr = 2439, >+ ARM_t2MOVTi16 = 2440, >+ ARM_t2MOVTi16_ga_pcrel = 2441, >+ ARM_t2MOV_ga_pcrel = 2442, >+ ARM_t2MOVi = 2443, >+ ARM_t2MOVi16 = 2444, >+ ARM_t2MOVi16_ga_pcrel = 2445, >+ ARM_t2MOVi32imm = 2446, >+ ARM_t2MOVr = 2447, >+ ARM_t2MOVsi = 2448, >+ ARM_t2MOVsr = 2449, >+ ARM_t2MOVsra_flag = 2450, >+ ARM_t2MOVsrl_flag = 2451, >+ ARM_t2MRC = 2452, >+ ARM_t2MRC2 = 2453, >+ ARM_t2MRRC = 2454, >+ ARM_t2MRRC2 = 2455, >+ ARM_t2MRS_AR = 2456, >+ ARM_t2MRS_M = 2457, >+ ARM_t2MRSsys_AR = 2458, >+ ARM_t2MSR_AR = 2459, >+ ARM_t2MSR_M = 2460, >+ ARM_t2MUL = 2461, >+ ARM_t2MVNCCi = 2462, >+ ARM_t2MVNi = 2463, >+ ARM_t2MVNr = 2464, >+ ARM_t2MVNs = 2465, >+ ARM_t2ORNri = 2466, >+ ARM_t2ORNrr = 2467, >+ ARM_t2ORNrs = 2468, >+ ARM_t2ORRri = 2469, >+ ARM_t2ORRrr = 2470, >+ ARM_t2ORRrs = 2471, >+ ARM_t2PKHBT = 2472, >+ ARM_t2PKHTB = 2473, >+ ARM_t2PLDWi12 = 2474, >+ ARM_t2PLDWi8 = 2475, >+ ARM_t2PLDWs = 2476, >+ ARM_t2PLDi12 = 2477, >+ ARM_t2PLDi8 = 2478, >+ ARM_t2PLDpci = 2479, >+ ARM_t2PLDs = 2480, >+ ARM_t2PLIi12 = 2481, >+ ARM_t2PLIi8 = 2482, >+ ARM_t2PLIpci = 2483, >+ ARM_t2PLIs = 2484, >+ ARM_t2QADD = 2485, >+ ARM_t2QADD16 = 2486, >+ ARM_t2QADD8 = 2487, >+ ARM_t2QASX = 2488, >+ ARM_t2QDADD = 2489, >+ ARM_t2QDSUB = 2490, >+ ARM_t2QSAX = 2491, >+ ARM_t2QSUB = 2492, >+ ARM_t2QSUB16 = 2493, >+ ARM_t2QSUB8 = 2494, >+ ARM_t2RBIT = 2495, >+ ARM_t2REV = 2496, >+ ARM_t2REV16 = 2497, >+ ARM_t2REVSH = 2498, >+ ARM_t2RFEDB = 2499, >+ ARM_t2RFEDBW = 2500, >+ ARM_t2RFEIA = 2501, >+ ARM_t2RFEIAW = 2502, >+ ARM_t2RORri = 2503, >+ ARM_t2RORrr = 2504, >+ ARM_t2RRX = 2505, >+ ARM_t2RSBSri = 2506, >+ ARM_t2RSBSrs = 2507, >+ ARM_t2RSBri = 2508, >+ ARM_t2RSBrr = 2509, >+ ARM_t2RSBrs = 2510, >+ ARM_t2SADD16 = 2511, >+ ARM_t2SADD8 = 2512, >+ ARM_t2SASX = 2513, >+ ARM_t2SBCri = 2514, >+ ARM_t2SBCrr = 2515, >+ ARM_t2SBCrs = 2516, >+ ARM_t2SBFX = 2517, >+ ARM_t2SDIV = 2518, >+ ARM_t2SEL = 2519, >+ ARM_t2SHADD16 = 2520, >+ ARM_t2SHADD8 = 2521, >+ ARM_t2SHASX = 2522, >+ ARM_t2SHSAX = 2523, >+ ARM_t2SHSUB16 = 2524, >+ ARM_t2SHSUB8 = 2525, >+ ARM_t2SMC = 2526, >+ ARM_t2SMLABB = 2527, >+ ARM_t2SMLABT = 2528, >+ ARM_t2SMLAD = 2529, >+ ARM_t2SMLADX = 2530, >+ ARM_t2SMLAL = 2531, >+ ARM_t2SMLALBB = 2532, >+ ARM_t2SMLALBT = 2533, >+ ARM_t2SMLALD = 2534, >+ ARM_t2SMLALDX = 2535, >+ ARM_t2SMLALTB = 2536, >+ ARM_t2SMLALTT = 2537, >+ ARM_t2SMLATB = 2538, >+ ARM_t2SMLATT = 2539, >+ ARM_t2SMLAWB = 2540, >+ ARM_t2SMLAWT = 2541, >+ ARM_t2SMLSD = 2542, >+ ARM_t2SMLSDX = 2543, >+ ARM_t2SMLSLD = 2544, >+ ARM_t2SMLSLDX = 2545, >+ ARM_t2SMMLA = 2546, >+ ARM_t2SMMLAR = 2547, >+ ARM_t2SMMLS = 2548, >+ ARM_t2SMMLSR = 2549, >+ ARM_t2SMMUL = 2550, >+ ARM_t2SMMULR = 2551, >+ ARM_t2SMUAD = 2552, >+ ARM_t2SMUADX = 2553, >+ ARM_t2SMULBB = 2554, >+ ARM_t2SMULBT = 2555, >+ ARM_t2SMULL = 2556, >+ ARM_t2SMULTB = 2557, >+ ARM_t2SMULTT = 2558, >+ ARM_t2SMULWB = 2559, >+ ARM_t2SMULWT = 2560, >+ ARM_t2SMUSD = 2561, >+ ARM_t2SMUSDX = 2562, >+ ARM_t2SRSDB = 2563, >+ ARM_t2SRSDB_UPD = 2564, >+ ARM_t2SRSIA = 2565, >+ ARM_t2SRSIA_UPD = 2566, >+ ARM_t2SSAT = 2567, >+ ARM_t2SSAT16 = 2568, >+ ARM_t2SSAX = 2569, >+ ARM_t2SSUB16 = 2570, >+ ARM_t2SSUB8 = 2571, >+ ARM_t2STC2L_OFFSET = 2572, >+ ARM_t2STC2L_OPTION = 2573, >+ ARM_t2STC2L_POST = 2574, >+ ARM_t2STC2L_PRE = 2575, >+ ARM_t2STC2_OFFSET = 2576, >+ ARM_t2STC2_OPTION = 2577, >+ ARM_t2STC2_POST = 2578, >+ ARM_t2STC2_PRE = 2579, >+ ARM_t2STCL_OFFSET = 2580, >+ ARM_t2STCL_OPTION = 2581, >+ ARM_t2STCL_POST = 2582, >+ ARM_t2STCL_PRE = 2583, >+ ARM_t2STC_OFFSET = 2584, >+ ARM_t2STC_OPTION = 2585, >+ ARM_t2STC_POST = 2586, >+ ARM_t2STC_PRE = 2587, >+ ARM_t2STL = 2588, >+ ARM_t2STLB = 2589, >+ ARM_t2STLEX = 2590, >+ ARM_t2STLEXB = 2591, >+ ARM_t2STLEXD = 2592, >+ ARM_t2STLEXH = 2593, >+ ARM_t2STLH = 2594, >+ ARM_t2STMDB = 2595, >+ ARM_t2STMDB_UPD = 2596, >+ ARM_t2STMIA = 2597, >+ ARM_t2STMIA_UPD = 2598, >+ ARM_t2STRBT = 2599, >+ ARM_t2STRB_POST = 2600, >+ ARM_t2STRB_PRE = 2601, >+ ARM_t2STRB_preidx = 2602, >+ ARM_t2STRBi12 = 2603, >+ ARM_t2STRBi8 = 2604, >+ ARM_t2STRBs = 2605, >+ ARM_t2STRD_POST = 2606, >+ ARM_t2STRD_PRE = 2607, >+ ARM_t2STRDi8 = 2608, >+ ARM_t2STREX = 2609, >+ ARM_t2STREXB = 2610, >+ ARM_t2STREXD = 2611, >+ ARM_t2STREXH = 2612, >+ ARM_t2STRHT = 2613, >+ ARM_t2STRH_POST = 2614, >+ ARM_t2STRH_PRE = 2615, >+ ARM_t2STRH_preidx = 2616, >+ ARM_t2STRHi12 = 2617, >+ ARM_t2STRHi8 = 2618, >+ ARM_t2STRHs = 2619, >+ ARM_t2STRT = 2620, >+ ARM_t2STR_POST = 2621, >+ ARM_t2STR_PRE = 2622, >+ ARM_t2STR_preidx = 2623, >+ ARM_t2STRi12 = 2624, >+ ARM_t2STRi8 = 2625, >+ ARM_t2STRs = 2626, >+ ARM_t2SUBS_PC_LR = 2627, >+ ARM_t2SUBSri = 2628, >+ ARM_t2SUBSrr = 2629, >+ ARM_t2SUBSrs = 2630, >+ ARM_t2SUBri = 2631, >+ ARM_t2SUBri12 = 2632, >+ ARM_t2SUBrr = 2633, >+ ARM_t2SUBrs = 2634, >+ ARM_t2SXTAB = 2635, >+ ARM_t2SXTAB16 = 2636, >+ ARM_t2SXTAH = 2637, >+ ARM_t2SXTB = 2638, >+ ARM_t2SXTB16 = 2639, >+ ARM_t2SXTH = 2640, >+ ARM_t2TBB = 2641, >+ ARM_t2TBB_JT = 2642, >+ ARM_t2TBH = 2643, >+ ARM_t2TBH_JT = 2644, >+ ARM_t2TEQri = 2645, >+ ARM_t2TEQrr = 2646, >+ ARM_t2TEQrs = 2647, >+ ARM_t2TSTri = 2648, >+ ARM_t2TSTrr = 2649, >+ ARM_t2TSTrs = 2650, >+ ARM_t2UADD16 = 2651, >+ ARM_t2UADD8 = 2652, >+ ARM_t2UASX = 2653, >+ ARM_t2UBFX = 2654, >+ ARM_t2UDF = 2655, >+ ARM_t2UDIV = 2656, >+ ARM_t2UHADD16 = 2657, >+ ARM_t2UHADD8 = 2658, >+ ARM_t2UHASX = 2659, >+ ARM_t2UHSAX = 2660, >+ ARM_t2UHSUB16 = 2661, >+ ARM_t2UHSUB8 = 2662, >+ ARM_t2UMAAL = 2663, >+ ARM_t2UMLAL = 2664, >+ ARM_t2UMULL = 2665, >+ ARM_t2UQADD16 = 2666, >+ ARM_t2UQADD8 = 2667, >+ ARM_t2UQASX = 2668, >+ ARM_t2UQSAX = 2669, >+ ARM_t2UQSUB16 = 2670, >+ ARM_t2UQSUB8 = 2671, >+ ARM_t2USAD8 = 2672, >+ ARM_t2USADA8 = 2673, >+ ARM_t2USAT = 2674, >+ ARM_t2USAT16 = 2675, >+ ARM_t2USAX = 2676, >+ ARM_t2USUB16 = 2677, >+ ARM_t2USUB8 = 2678, >+ ARM_t2UXTAB = 2679, >+ ARM_t2UXTAB16 = 2680, >+ ARM_t2UXTAH = 2681, >+ ARM_t2UXTB = 2682, >+ ARM_t2UXTB16 = 2683, >+ ARM_t2UXTH = 2684, >+ ARM_tADC = 2685, >+ ARM_tADDhirr = 2686, >+ ARM_tADDi3 = 2687, >+ ARM_tADDi8 = 2688, >+ ARM_tADDrSP = 2689, >+ ARM_tADDrSPi = 2690, >+ ARM_tADDrr = 2691, >+ ARM_tADDspi = 2692, >+ ARM_tADDspr = 2693, >+ ARM_tADJCALLSTACKDOWN = 2694, >+ ARM_tADJCALLSTACKUP = 2695, >+ ARM_tADR = 2696, >+ ARM_tAND = 2697, >+ ARM_tASRri = 2698, >+ ARM_tASRrr = 2699, >+ ARM_tB = 2700, >+ ARM_tBIC = 2701, >+ ARM_tBKPT = 2702, >+ ARM_tBL = 2703, >+ ARM_tBLXi = 2704, >+ ARM_tBLXr = 2705, >+ ARM_tBRIND = 2706, >+ ARM_tBR_JTr = 2707, >+ ARM_tBX = 2708, >+ ARM_tBX_CALL = 2709, >+ ARM_tBX_RET = 2710, >+ ARM_tBX_RET_vararg = 2711, >+ ARM_tBcc = 2712, >+ ARM_tBfar = 2713, >+ ARM_tCBNZ = 2714, >+ ARM_tCBZ = 2715, >+ ARM_tCMNz = 2716, >+ ARM_tCMPhir = 2717, >+ ARM_tCMPi8 = 2718, >+ ARM_tCMPr = 2719, >+ ARM_tCPS = 2720, >+ ARM_tEOR = 2721, >+ ARM_tHINT = 2722, >+ ARM_tHLT = 2723, >+ ARM_tInt_eh_sjlj_longjmp = 2724, >+ ARM_tInt_eh_sjlj_setjmp = 2725, >+ ARM_tLDMIA = 2726, >+ ARM_tLDMIA_UPD = 2727, >+ ARM_tLDRBi = 2728, >+ ARM_tLDRBr = 2729, >+ ARM_tLDRHi = 2730, >+ ARM_tLDRHr = 2731, >+ ARM_tLDRLIT_ga_abs = 2732, >+ ARM_tLDRLIT_ga_pcrel = 2733, >+ ARM_tLDRSB = 2734, >+ ARM_tLDRSH = 2735, >+ ARM_tLDRi = 2736, >+ ARM_tLDRpci = 2737, >+ ARM_tLDRpci_pic = 2738, >+ ARM_tLDRr = 2739, >+ ARM_tLDRspi = 2740, >+ ARM_tLEApcrel = 2741, >+ ARM_tLEApcrelJT = 2742, >+ ARM_tLSLri = 2743, >+ ARM_tLSLrr = 2744, >+ ARM_tLSRri = 2745, >+ ARM_tLSRrr = 2746, >+ ARM_tMOVCCr_pseudo = 2747, >+ ARM_tMOVSr = 2748, >+ ARM_tMOVi8 = 2749, >+ ARM_tMOVr = 2750, >+ ARM_tMUL = 2751, >+ ARM_tMVN = 2752, >+ ARM_tORR = 2753, >+ ARM_tPICADD = 2754, >+ ARM_tPOP = 2755, >+ ARM_tPOP_RET = 2756, >+ ARM_tPUSH = 2757, >+ ARM_tREV = 2758, >+ ARM_tREV16 = 2759, >+ ARM_tREVSH = 2760, >+ ARM_tROR = 2761, >+ ARM_tRSB = 2762, >+ ARM_tSBC = 2763, >+ ARM_tSETEND = 2764, >+ ARM_tSTMIA_UPD = 2765, >+ ARM_tSTRBi = 2766, >+ ARM_tSTRBr = 2767, >+ ARM_tSTRHi = 2768, >+ ARM_tSTRHr = 2769, >+ ARM_tSTRi = 2770, >+ ARM_tSTRr = 2771, >+ ARM_tSTRspi = 2772, >+ ARM_tSUBi3 = 2773, >+ ARM_tSUBi8 = 2774, >+ ARM_tSUBrr = 2775, >+ ARM_tSUBspi = 2776, >+ ARM_tSVC = 2777, >+ ARM_tSXTB = 2778, >+ ARM_tSXTH = 2779, >+ ARM_tTAILJMPd = 2780, >+ ARM_tTAILJMPdND = 2781, >+ ARM_tTAILJMPr = 2782, >+ ARM_tTPsoft = 2783, >+ ARM_tTRAP = 2784, >+ ARM_tTST = 2785, >+ ARM_tUDF = 2786, >+ ARM_tUXTB = 2787, >+ ARM_tUXTH = 2788, >+ ARM_INSTRUCTION_LIST_END = 2789 >+}; >+ >+#endif // GET_INSTRINFO_ENUM >+ >+ >+#ifdef GET_INSTRINFO_MC_DESC >+#undef GET_INSTRINFO_MC_DESC >+ >+#define nullptr 0 >+ >+#define ImplicitList1 0 >+#define ImplicitList2 0 >+#define ImplicitList3 0 >+#define ImplicitList4 0 >+#define ImplicitList5 0 >+#define ImplicitList6 0 >+#define ImplicitList7 0 >+#define ImplicitList8 0 >+#define ImplicitList9 0 >+#define ImplicitList10 0 >+#define ImplicitList11 0 >+#define ImplicitList12 0 >+#define ImplicitList13 0 >+#define ImplicitList14 0 >+#define ImplicitList15 0 >+ >+static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo15[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo23[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo26[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static const MCOperandInfo OperandInfo30[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo31[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo35[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo39[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo42[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo44[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo46[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo47[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo48[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo49[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo53[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo58[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo63[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo64[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo69[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo73[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo80[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo85[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo87[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo88[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo90[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo92[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo93[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo94[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo95[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo96[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo100[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo102[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo103[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo104[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo106[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo107[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo108[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo111[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo119[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo121[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo122[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo123[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo124[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo125[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo126[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo127[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo130[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo131[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo132[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo133[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo134[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo135[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo136[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo137[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo138[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo140[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo141[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo144[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo146[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo147[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo149[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo151[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo153[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo154[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo156[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo157[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo158[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo159[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo160[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo162[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo165[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo166[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo167[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo168[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo169[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo170[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo176[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo177[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo180[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo181[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo182[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo184[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo185[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo186[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo188[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo190[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo194[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo199[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo200[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo203[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo204[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo207[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo210[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo214[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo217[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo221[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo222[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo223[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo226[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo259[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo260[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo267[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo274[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo283[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo291[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo299[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo308[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo309[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo310[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo316[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo324[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo326[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo328[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo329[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo331[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo337[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo339[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo340[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static const MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; >+static const MCOperandInfo OperandInfo342[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, }; >+static const MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; >+static const MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo358[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo359[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+static const MCOperandInfo OperandInfo360[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; >+ >+static const MCInstrDesc ARMInsts[] = { >+ { 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI >+ { 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM >+ { 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION >+ { 3, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #3 = EH_LABEL >+ { 4, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #4 = GC_LABEL >+ { 5, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #5 = KILL >+ { 6, 3, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #6 = EXTRACT_SUBREG >+ { 7, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4,0,nullptr }, // Inst #7 = INSERT_SUBREG >+ { 8, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #8 = IMPLICIT_DEF >+ { 9, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6,0,nullptr }, // Inst #9 = SUBREG_TO_REG >+ { 10, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #10 = COPY_TO_REGCLASS >+ { 11, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #11 = DBG_VALUE >+ { 12, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #12 = REG_SEQUENCE >+ { 13, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #13 = COPY >+ { 14, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #14 = BUNDLE >+ { 15, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #15 = LIFETIME_START >+ { 16, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #16 = LIFETIME_END >+ { 17, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8,0,nullptr }, // Inst #17 = STACKMAP >+ { 18, 6, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9,0,nullptr }, // Inst #18 = PATCHPOINT >+ { 19, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10,0,nullptr }, // Inst #19 = LOAD_STACK_GUARD >+ { 20, 2, 1, 590, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #20 = ABS >+ { 21, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #21 = ADCri >+ { 22, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #22 = ADCrr >+ { 23, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #23 = ADCrsi >+ { 24, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #24 = ADCrsr >+ { 25, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #25 = ADDSri >+ { 26, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #26 = ADDSrr >+ { 27, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #27 = ADDSrsi >+ { 28, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #28 = ADDSrsr >+ { 29, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #29 = ADDri >+ { 30, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #30 = ADDrr >+ { 31, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #31 = ADDrsi >+ { 32, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #32 = ADDrsr >+ { 33, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo21,0,nullptr }, // Inst #33 = ADJCALLSTACKDOWN >+ { 34, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo22,0,nullptr }, // Inst #34 = ADJCALLSTACKUP >+ { 35, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #35 = ADR >+ { 36, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #36 = AESD >+ { 37, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #37 = AESE >+ { 38, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #38 = AESIMC >+ { 39, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #39 = AESMC >+ { 40, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #40 = ANDri >+ { 41, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #41 = ANDrr >+ { 42, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #42 = ANDrsi >+ { 43, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #43 = ANDrsr >+ { 44, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #44 = ASRi >+ { 45, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #45 = ASRr >+ { 46, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #46 = B >+ { 47, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28,0,nullptr }, // Inst #47 = BCCZi64 >+ { 48, 6, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo29,0,nullptr }, // Inst #48 = BCCi64 >+ { 49, 5, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #49 = BFC >+ { 50, 6, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #50 = BFI >+ { 51, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #51 = BICri >+ { 52, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #52 = BICrr >+ { 53, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #53 = BICrsi >+ { 54, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #54 = BICrsr >+ { 55, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #55 = BKPT >+ { 56, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo27,0,nullptr }, // Inst #56 = BL >+ { 57, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo32,0,nullptr }, // Inst #57 = BLX >+ { 58, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo33,0,nullptr }, // Inst #58 = BLX_pred >+ { 59, 1, 0, 13, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #59 = BLXi >+ { 60, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #60 = BL_pred >+ { 61, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo27,0,nullptr }, // Inst #61 = BMOVPCB_CALL >+ { 62, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #62 = BMOVPCRX_CALL >+ { 63, 4, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #63 = BR_JTadd >+ { 64, 5, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #64 = BR_JTm >+ { 65, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #65 = BR_JTr >+ { 66, 1, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #66 = BX >+ { 67, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #67 = BXJ >+ { 68, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #68 = BX_CALL >+ { 69, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #69 = BX_RET >+ { 70, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #70 = BX_pred >+ { 71, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #71 = Bcc >+ { 72, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #72 = CDP >+ { 73, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #73 = CDP2 >+ { 74, 0, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #74 = CLREX >+ { 75, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #75 = CLZ >+ { 76, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #76 = CMNri >+ { 77, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #77 = CMNzrr >+ { 78, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #78 = CMNzrsi >+ { 79, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #79 = CMNzrsr >+ { 80, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #80 = CMPri >+ { 81, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #81 = CMPrr >+ { 82, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #82 = CMPrsi >+ { 83, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #83 = CMPrsr >+ { 84, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #84 = CONSTPOOL_ENTRY >+ { 85, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #85 = COPY_STRUCT_BYVAL_I32 >+ { 86, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #86 = CPS1p >+ { 87, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #87 = CPS2p >+ { 88, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo45,0,nullptr }, // Inst #88 = CPS3p >+ { 89, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #89 = CRC32B >+ { 90, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #90 = CRC32CB >+ { 91, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #91 = CRC32CH >+ { 92, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #92 = CRC32CW >+ { 93, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #93 = CRC32H >+ { 94, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #94 = CRC32W >+ { 95, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #95 = DBG >+ { 96, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #96 = DMB >+ { 97, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #97 = DSB >+ { 98, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #98 = EORri >+ { 99, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #99 = EORrr >+ { 100, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #100 = EORrsi >+ { 101, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #101 = EORrsr >+ { 102, 4, 1, 487, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #102 = FCONSTD >+ { 103, 4, 1, 488, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #103 = FCONSTS >+ { 104, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #104 = FLDMXDB_UPD >+ { 105, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #105 = FLDMXIA >+ { 106, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #106 = FLDMXIA_UPD >+ { 107, 2, 0, 507, 4, 0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList4, ImplicitList1, OperandInfo39,0,nullptr }, // Inst #107 = FMSTAT >+ { 108, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #108 = FSTMXDB_UPD >+ { 109, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #109 = FSTMXIA >+ { 110, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #110 = FSTMXIA_UPD >+ { 111, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #111 = HINT >+ { 112, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #112 = HLT >+ { 113, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #113 = ISB >+ { 114, 2, 0, 377, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7,0,0 }, // Inst #114 = ITasm >+ { 115, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #115 = Int_eh_sjlj_dispatchsetup >+ { 116, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo11,0,nullptr }, // Inst #116 = Int_eh_sjlj_longjmp >+ { 117, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo11,0,nullptr }, // Inst #117 = Int_eh_sjlj_setjmp >+ { 118, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo11,0,nullptr }, // Inst #118 = Int_eh_sjlj_setjmp_nofp >+ { 119, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #119 = LDA >+ { 120, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #120 = LDAB >+ { 121, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #121 = LDAEX >+ { 122, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #122 = LDAEXB >+ { 123, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #123 = LDAEXD >+ { 124, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #124 = LDAEXH >+ { 125, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #125 = LDAH >+ { 126, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #126 = LDC2L_OFFSET >+ { 127, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #127 = LDC2L_OPTION >+ { 128, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #128 = LDC2L_POST >+ { 129, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #129 = LDC2L_PRE >+ { 130, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #130 = LDC2_OFFSET >+ { 131, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #131 = LDC2_OPTION >+ { 132, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #132 = LDC2_POST >+ { 133, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #133 = LDC2_PRE >+ { 134, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #134 = LDCL_OFFSET >+ { 135, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #135 = LDCL_OPTION >+ { 136, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #136 = LDCL_POST >+ { 137, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #137 = LDCL_PRE >+ { 138, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #138 = LDC_OFFSET >+ { 139, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #139 = LDC_OPTION >+ { 140, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #140 = LDC_POST >+ { 141, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #141 = LDC_PRE >+ { 142, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #142 = LDMDA >+ { 143, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #143 = LDMDA_UPD >+ { 144, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #144 = LDMDB >+ { 145, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #145 = LDMDB_UPD >+ { 146, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #146 = LDMIA >+ { 147, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #147 = LDMIA_RET >+ { 148, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #148 = LDMIA_UPD >+ { 149, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #149 = LDMIB >+ { 150, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #150 = LDMIB_UPD >+ { 151, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #151 = LDRBT_POST >+ { 152, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #152 = LDRBT_POST_IMM >+ { 153, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #153 = LDRBT_POST_REG >+ { 154, 7, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #154 = LDRB_POST_IMM >+ { 155, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #155 = LDRB_POST_REG >+ { 156, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #156 = LDRB_PRE_IMM >+ { 157, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #157 = LDRB_PRE_REG >+ { 158, 5, 1, 325, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #158 = LDRBi12 >+ { 159, 6, 1, 326, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #159 = LDRBrs >+ { 160, 7, 2, 350, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #160 = LDRD >+ { 161, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #161 = LDRD_POST >+ { 162, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #162 = LDRD_PRE >+ { 163, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #163 = LDREX >+ { 164, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #164 = LDREXB >+ { 165, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #165 = LDREXD >+ { 166, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #166 = LDREXH >+ { 167, 6, 1, 335, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #167 = LDRH >+ { 168, 6, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #168 = LDRHTi >+ { 169, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #169 = LDRHTr >+ { 170, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #170 = LDRH_POST >+ { 171, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #171 = LDRH_PRE >+ { 172, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #172 = LDRLIT_ga_abs >+ { 173, 2, 1, 34, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #173 = LDRLIT_ga_pcrel >+ { 174, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #174 = LDRLIT_ga_pcrel_ldr >+ { 175, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #175 = LDRSB >+ { 176, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #176 = LDRSBTi >+ { 177, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #177 = LDRSBTr >+ { 178, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #178 = LDRSB_POST >+ { 179, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #179 = LDRSB_PRE >+ { 180, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #180 = LDRSH >+ { 181, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #181 = LDRSHTi >+ { 182, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #182 = LDRSHTr >+ { 183, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #183 = LDRSH_POST >+ { 184, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #184 = LDRSH_PRE >+ { 185, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #185 = LDRT_POST >+ { 186, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #186 = LDRT_POST_IMM >+ { 187, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #187 = LDRT_POST_REG >+ { 188, 7, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #188 = LDR_POST_IMM >+ { 189, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #189 = LDR_POST_REG >+ { 190, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #190 = LDR_PRE_IMM >+ { 191, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #191 = LDR_PRE_REG >+ { 192, 5, 1, 336, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #192 = LDRcp >+ { 193, 5, 1, 328, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #193 = LDRi12 >+ { 194, 6, 1, 287, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #194 = LDRrs >+ { 195, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #195 = LEApcrel >+ { 196, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68,0,nullptr }, // Inst #196 = LEApcrelJT >+ { 197, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #197 = LSLi >+ { 198, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #198 = LSLr >+ { 199, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #199 = LSRi >+ { 200, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #200 = LSRr >+ { 201, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo69,0,0 }, // Inst #201 = MCR >+ { 202, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo70,0,nullptr }, // Inst #202 = MCR2 >+ { 203, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #203 = MCRR >+ { 204, 5, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #204 = MCRR2 >+ { 205, 7, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #205 = MLA >+ { 206, 7, 1, 279, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74,0,nullptr }, // Inst #206 = MLAv5 >+ { 207, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #207 = MLS >+ { 208, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #208 = MOVCCi >+ { 209, 5, 1, 41, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #209 = MOVCCi16 >+ { 210, 5, 1, 273, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #210 = MOVCCi32imm >+ { 211, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #211 = MOVCCr >+ { 212, 6, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #212 = MOVCCsi >+ { 213, 7, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo79,0,nullptr }, // Inst #213 = MOVCCsr >+ { 214, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #214 = MOVPCLR >+ { 215, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #215 = MOVPCRX >+ { 216, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo80,0,nullptr }, // Inst #216 = MOVTi16 >+ { 217, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81,0,nullptr }, // Inst #217 = MOVTi16_ga_pcrel >+ { 218, 2, 1, 275, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #218 = MOV_ga_pcrel >+ { 219, 2, 1, 276, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #219 = MOV_ga_pcrel_ldr >+ { 220, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #220 = MOVi >+ { 221, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #221 = MOVi16 >+ { 222, 3, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #222 = MOVi16_ga_pcrel >+ { 223, 2, 1, 274, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #223 = MOVi32imm >+ { 224, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #224 = MOVr >+ { 225, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #225 = MOVr_TC >+ { 226, 6, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #226 = MOVsi >+ { 227, 7, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #227 = MOVsr >+ { 228, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #228 = MOVsra_flag >+ { 229, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo11,0,nullptr }, // Inst #229 = MOVsrl_flag >+ { 230, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #230 = MRC >+ { 231, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #231 = MRC2 >+ { 232, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #232 = MRRC >+ { 233, 5, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #233 = MRRC2 >+ { 234, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #234 = MRS >+ { 235, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #235 = MRSsys >+ { 236, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #236 = MSR >+ { 237, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #237 = MSRi >+ { 238, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #238 = MUL >+ { 239, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #239 = MULv5 >+ { 240, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo30,0,nullptr }, // Inst #240 = MVNCCi >+ { 241, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #241 = MVNi >+ { 242, 5, 1, 272, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #242 = MVNr >+ { 243, 6, 1, 54, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #243 = MVNsi >+ { 244, 7, 1, 271, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo94,0,nullptr }, // Inst #244 = MVNsr >+ { 245, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #245 = ORRri >+ { 246, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #246 = ORRrr >+ { 247, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #247 = ORRrsi >+ { 248, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #248 = ORRrsr >+ { 249, 5, 1, 55, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo16,0,nullptr }, // Inst #249 = PICADD >+ { 250, 5, 1, 286, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #250 = PICLDR >+ { 251, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #251 = PICLDRB >+ { 252, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #252 = PICLDRH >+ { 253, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #253 = PICLDRSB >+ { 254, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #254 = PICLDRSH >+ { 255, 5, 0, 358, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #255 = PICSTR >+ { 256, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #256 = PICSTRB >+ { 257, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #257 = PICSTRH >+ { 258, 6, 1, 58, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #258 = PKHBT >+ { 259, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #259 = PKHTB >+ { 260, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #260 = PLDWi12 >+ { 261, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #261 = PLDWrs >+ { 262, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #262 = PLDi12 >+ { 263, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #263 = PLDrs >+ { 264, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #264 = PLIi12 >+ { 265, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #265 = PLIrs >+ { 266, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #266 = QADD >+ { 267, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #267 = QADD16 >+ { 268, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #268 = QADD8 >+ { 269, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #269 = QASX >+ { 270, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #270 = QDADD >+ { 271, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #271 = QDSUB >+ { 272, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #272 = QSAX >+ { 273, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #273 = QSUB >+ { 274, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #274 = QSUB16 >+ { 275, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #275 = QSUB8 >+ { 276, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #276 = RBIT >+ { 277, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #277 = REV >+ { 278, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #278 = REV16 >+ { 279, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #279 = REVSH >+ { 280, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #280 = RFEDA >+ { 281, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #281 = RFEDA_UPD >+ { 282, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #282 = RFEDB >+ { 283, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #283 = RFEDB_UPD >+ { 284, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #284 = RFEIA >+ { 285, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #285 = RFEIA_UPD >+ { 286, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #286 = RFEIB >+ { 287, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #287 = RFEIB_UPD >+ { 288, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #288 = RORi >+ { 289, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #289 = RORr >+ { 290, 2, 1, 50, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo11,0,nullptr }, // Inst #290 = RRX >+ { 291, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #291 = RRXi >+ { 292, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #292 = RSBSri >+ { 293, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #293 = RSBSrsi >+ { 294, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #294 = RSBSrsr >+ { 295, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #295 = RSBri >+ { 296, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #296 = RSBrr >+ { 297, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #297 = RSBrsi >+ { 298, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #298 = RSBrsr >+ { 299, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #299 = RSCri >+ { 300, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #300 = RSCrr >+ { 301, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #301 = RSCrsi >+ { 302, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #302 = RSCrsr >+ { 303, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #303 = SADD16 >+ { 304, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #304 = SADD8 >+ { 305, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #305 = SASX >+ { 306, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #306 = SBCri >+ { 307, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #307 = SBCrr >+ { 308, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #308 = SBCrsi >+ { 309, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #309 = SBCrsr >+ { 310, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #310 = SBFX >+ { 311, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #311 = SDIV >+ { 312, 5, 1, 277, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #312 = SEL >+ { 313, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #313 = SETEND >+ { 314, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #314 = SHA1C >+ { 315, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #315 = SHA1H >+ { 316, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #316 = SHA1M >+ { 317, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #317 = SHA1P >+ { 318, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #318 = SHA1SU0 >+ { 319, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #319 = SHA1SU1 >+ { 320, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #320 = SHA256H >+ { 321, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #321 = SHA256H2 >+ { 322, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #322 = SHA256SU0 >+ { 323, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #323 = SHA256SU1 >+ { 324, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #324 = SHADD16 >+ { 325, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #325 = SHADD8 >+ { 326, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #326 = SHASX >+ { 327, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #327 = SHSAX >+ { 328, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #328 = SHSUB16 >+ { 329, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #329 = SHSUB8 >+ { 330, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #330 = SMC >+ { 331, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #331 = SMLABB >+ { 332, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #332 = SMLABT >+ { 333, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #333 = SMLAD >+ { 334, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #334 = SMLADX >+ { 335, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #335 = SMLAL >+ { 336, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #336 = SMLALBB >+ { 337, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #337 = SMLALBT >+ { 338, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #338 = SMLALD >+ { 339, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #339 = SMLALDX >+ { 340, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #340 = SMLALTB >+ { 341, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #341 = SMLALTT >+ { 342, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #342 = SMLALv5 >+ { 343, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #343 = SMLATB >+ { 344, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #344 = SMLATT >+ { 345, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #345 = SMLAWB >+ { 346, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #346 = SMLAWT >+ { 347, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #347 = SMLSD >+ { 348, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #348 = SMLSDX >+ { 349, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #349 = SMLSLD >+ { 350, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #350 = SMLSLDX >+ { 351, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #351 = SMMLA >+ { 352, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #352 = SMMLAR >+ { 353, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #353 = SMMLS >+ { 354, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #354 = SMMLSR >+ { 355, 5, 1, 280, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #355 = SMMUL >+ { 356, 5, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #356 = SMMULR >+ { 357, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #357 = SMUAD >+ { 358, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #358 = SMUADX >+ { 359, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #359 = SMULBB >+ { 360, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #360 = SMULBT >+ { 361, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #361 = SMULL >+ { 362, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #362 = SMULLv5 >+ { 363, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #363 = SMULTB >+ { 364, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #364 = SMULTT >+ { 365, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #365 = SMULWB >+ { 366, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #366 = SMULWT >+ { 367, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #367 = SMUSD >+ { 368, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #368 = SMUSDX >+ { 369, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #369 = SRSDA >+ { 370, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #370 = SRSDA_UPD >+ { 371, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #371 = SRSDB >+ { 372, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #372 = SRSDB_UPD >+ { 373, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #373 = SRSIA >+ { 374, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #374 = SRSIA_UPD >+ { 375, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #375 = SRSIB >+ { 376, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #376 = SRSIB_UPD >+ { 377, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #377 = SSAT >+ { 378, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #378 = SSAT16 >+ { 379, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #379 = SSAX >+ { 380, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #380 = SSUB16 >+ { 381, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #381 = SSUB8 >+ { 382, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #382 = STC2L_OFFSET >+ { 383, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #383 = STC2L_OPTION >+ { 384, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #384 = STC2L_POST >+ { 385, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #385 = STC2L_PRE >+ { 386, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #386 = STC2_OFFSET >+ { 387, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #387 = STC2_OPTION >+ { 388, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #388 = STC2_POST >+ { 389, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #389 = STC2_PRE >+ { 390, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #390 = STCL_OFFSET >+ { 391, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #391 = STCL_OPTION >+ { 392, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #392 = STCL_POST >+ { 393, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #393 = STCL_PRE >+ { 394, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #394 = STC_OFFSET >+ { 395, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #395 = STC_OPTION >+ { 396, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #396 = STC_POST >+ { 397, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #397 = STC_PRE >+ { 398, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #398 = STL >+ { 399, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #399 = STLB >+ { 400, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #400 = STLEX >+ { 401, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #401 = STLEXB >+ { 402, 5, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #402 = STLEXD >+ { 403, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #403 = STLEXH >+ { 404, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #404 = STLH >+ { 405, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #405 = STMDA >+ { 406, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #406 = STMDA_UPD >+ { 407, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #407 = STMDB >+ { 408, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #408 = STMDB_UPD >+ { 409, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #409 = STMIA >+ { 410, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #410 = STMIA_UPD >+ { 411, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #411 = STMIB >+ { 412, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #412 = STMIB_UPD >+ { 413, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #413 = STRBT_POST >+ { 414, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #414 = STRBT_POST_IMM >+ { 415, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #415 = STRBT_POST_REG >+ { 416, 7, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #416 = STRB_POST_IMM >+ { 417, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #417 = STRB_POST_REG >+ { 418, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #418 = STRB_PRE_IMM >+ { 419, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #419 = STRB_PRE_REG >+ { 420, 5, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #420 = STRBi12 >+ { 421, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #421 = STRBi_preidx >+ { 422, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #422 = STRBr_preidx >+ { 423, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #423 = STRBrs >+ { 424, 7, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #424 = STRD >+ { 425, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #425 = STRD_POST >+ { 426, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #426 = STRD_PRE >+ { 427, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #427 = STREX >+ { 428, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #428 = STREXB >+ { 429, 5, 1, 361, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #429 = STREXD >+ { 430, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #430 = STREXH >+ { 431, 6, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #431 = STRH >+ { 432, 6, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #432 = STRHTi >+ { 433, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #433 = STRHTr >+ { 434, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #434 = STRH_POST >+ { 435, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #435 = STRH_PRE >+ { 436, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #436 = STRH_preidx >+ { 437, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #437 = STRT_POST >+ { 438, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #438 = STRT_POST_IMM >+ { 439, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #439 = STRT_POST_REG >+ { 440, 7, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #440 = STR_POST_IMM >+ { 441, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #441 = STR_POST_REG >+ { 442, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #442 = STR_PRE_IMM >+ { 443, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #443 = STR_PRE_REG >+ { 444, 5, 0, 358, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #444 = STRi12 >+ { 445, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #445 = STRi_preidx >+ { 446, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #446 = STRr_preidx >+ { 447, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #447 = STRrs >+ { 448, 3, 0, 76, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #448 = SUBS_PC_LR >+ { 449, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #449 = SUBSri >+ { 450, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #450 = SUBSrr >+ { 451, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #451 = SUBSrsi >+ { 452, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #452 = SUBSrsr >+ { 453, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #453 = SUBri >+ { 454, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #454 = SUBrr >+ { 455, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #455 = SUBrsi >+ { 456, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #456 = SUBrsr >+ { 457, 3, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo47,0,nullptr }, // Inst #457 = SVC >+ { 458, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #458 = SWP >+ { 459, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #459 = SWPB >+ { 460, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #460 = SXTAB >+ { 461, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #461 = SXTAB16 >+ { 462, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #462 = SXTAH >+ { 463, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #463 = SXTB >+ { 464, 5, 1, 290, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #464 = SXTB16 >+ { 465, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #465 = SXTH >+ { 466, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo27,0,nullptr }, // Inst #466 = TAILJMPd >+ { 467, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #467 = TAILJMPr >+ { 468, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2,0,nullptr }, // Inst #468 = TCRETURNdi >+ { 469, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #469 = TCRETURNri >+ { 470, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #470 = TEQri >+ { 471, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #471 = TEQrr >+ { 472, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #472 = TEQrsi >+ { 473, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #473 = TEQrsr >+ { 474, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, nullptr,0,nullptr }, // Inst #474 = TPsoft >+ { 475, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #475 = TRAP >+ { 476, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #476 = TRAPNaCl >+ { 477, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo23,0,nullptr }, // Inst #477 = TSTri >+ { 478, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #478 = TSTrr >+ { 479, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #479 = TSTrsi >+ { 480, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #480 = TSTrsr >+ { 481, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #481 = UADD16 >+ { 482, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #482 = UADD8 >+ { 483, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #483 = UASX >+ { 484, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #484 = UBFX >+ { 485, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #485 = UDF >+ { 486, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #486 = UDIV >+ { 487, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #487 = UHADD16 >+ { 488, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #488 = UHADD8 >+ { 489, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #489 = UHASX >+ { 490, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #490 = UHSAX >+ { 491, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #491 = UHSUB16 >+ { 492, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #492 = UHSUB8 >+ { 493, 6, 2, 281, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #493 = UMAAL >+ { 494, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #494 = UMLAL >+ { 495, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #495 = UMLALv5 >+ { 496, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #496 = UMULL >+ { 497, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #497 = UMULLv5 >+ { 498, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #498 = UQADD16 >+ { 499, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #499 = UQADD8 >+ { 500, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #500 = UQASX >+ { 501, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #501 = UQSAX >+ { 502, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #502 = UQSUB16 >+ { 503, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #503 = UQSUB8 >+ { 504, 5, 1, 307, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #504 = USAD8 >+ { 505, 6, 1, 308, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #505 = USADA8 >+ { 506, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #506 = USAT >+ { 507, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #507 = USAT16 >+ { 508, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #508 = USAX >+ { 509, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #509 = USUB16 >+ { 510, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #510 = USUB8 >+ { 511, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #511 = UXTAB >+ { 512, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #512 = UXTAB16 >+ { 513, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #513 = UXTAH >+ { 514, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #514 = UXTB >+ { 515, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #515 = UXTB16 >+ { 516, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #516 = UXTH >+ { 517, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #517 = VABALsv2i64 >+ { 518, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #518 = VABALsv4i32 >+ { 519, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #519 = VABALsv8i16 >+ { 520, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #520 = VABALuv2i64 >+ { 521, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #521 = VABALuv4i32 >+ { 522, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #522 = VABALuv8i16 >+ { 523, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #523 = VABAsv16i8 >+ { 524, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #524 = VABAsv2i32 >+ { 525, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #525 = VABAsv4i16 >+ { 526, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #526 = VABAsv4i32 >+ { 527, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #527 = VABAsv8i16 >+ { 528, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #528 = VABAsv8i8 >+ { 529, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #529 = VABAuv16i8 >+ { 530, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #530 = VABAuv2i32 >+ { 531, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #531 = VABAuv4i16 >+ { 532, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #532 = VABAuv4i32 >+ { 533, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #533 = VABAuv8i16 >+ { 534, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #534 = VABAuv8i8 >+ { 535, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #535 = VABDLsv2i64 >+ { 536, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #536 = VABDLsv4i32 >+ { 537, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #537 = VABDLsv8i16 >+ { 538, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #538 = VABDLuv2i64 >+ { 539, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #539 = VABDLuv4i32 >+ { 540, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #540 = VABDLuv8i16 >+ { 541, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #541 = VABDfd >+ { 542, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #542 = VABDfq >+ { 543, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #543 = VABDsv16i8 >+ { 544, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #544 = VABDsv2i32 >+ { 545, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #545 = VABDsv4i16 >+ { 546, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #546 = VABDsv4i32 >+ { 547, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #547 = VABDsv8i16 >+ { 548, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #548 = VABDsv8i8 >+ { 549, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #549 = VABDuv16i8 >+ { 550, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #550 = VABDuv2i32 >+ { 551, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #551 = VABDuv4i16 >+ { 552, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #552 = VABDuv4i32 >+ { 553, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #553 = VABDuv8i16 >+ { 554, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #554 = VABDuv8i8 >+ { 555, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #555 = VABSD >+ { 556, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #556 = VABSS >+ { 557, 4, 1, 402, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #557 = VABSfd >+ { 558, 4, 1, 403, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #558 = VABSfq >+ { 559, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #559 = VABSv16i8 >+ { 560, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #560 = VABSv2i32 >+ { 561, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #561 = VABSv4i16 >+ { 562, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #562 = VABSv4i32 >+ { 563, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #563 = VABSv8i16 >+ { 564, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #564 = VABSv8i8 >+ { 565, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #565 = VACGEd >+ { 566, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #566 = VACGEq >+ { 567, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #567 = VACGTd >+ { 568, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #568 = VACGTq >+ { 569, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #569 = VADDD >+ { 570, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #570 = VADDHNv2i32 >+ { 571, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #571 = VADDHNv4i16 >+ { 572, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #572 = VADDHNv8i8 >+ { 573, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #573 = VADDLsv2i64 >+ { 574, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #574 = VADDLsv4i32 >+ { 575, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #575 = VADDLsv8i16 >+ { 576, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #576 = VADDLuv2i64 >+ { 577, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #577 = VADDLuv4i32 >+ { 578, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #578 = VADDLuv8i16 >+ { 579, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #579 = VADDS >+ { 580, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #580 = VADDWsv2i64 >+ { 581, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #581 = VADDWsv4i32 >+ { 582, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #582 = VADDWsv8i16 >+ { 583, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #583 = VADDWuv2i64 >+ { 584, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #584 = VADDWuv4i32 >+ { 585, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #585 = VADDWuv8i16 >+ { 586, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #586 = VADDfd >+ { 587, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #587 = VADDfq >+ { 588, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #588 = VADDv16i8 >+ { 589, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #589 = VADDv1i64 >+ { 590, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #590 = VADDv2i32 >+ { 591, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #591 = VADDv2i64 >+ { 592, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #592 = VADDv4i16 >+ { 593, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #593 = VADDv4i32 >+ { 594, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #594 = VADDv8i16 >+ { 595, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #595 = VADDv8i8 >+ { 596, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #596 = VANDd >+ { 597, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #597 = VANDq >+ { 598, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #598 = VBICd >+ { 599, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #599 = VBICiv2i32 >+ { 600, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #600 = VBICiv4i16 >+ { 601, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #601 = VBICiv4i32 >+ { 602, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #602 = VBICiv8i16 >+ { 603, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #603 = VBICq >+ { 604, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #604 = VBIFd >+ { 605, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #605 = VBIFq >+ { 606, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #606 = VBITd >+ { 607, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #607 = VBITq >+ { 608, 6, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #608 = VBSLd >+ { 609, 6, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #609 = VBSLq >+ { 610, 5, 1, 406, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #610 = VCEQfd >+ { 611, 5, 1, 407, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #611 = VCEQfq >+ { 612, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #612 = VCEQv16i8 >+ { 613, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #613 = VCEQv2i32 >+ { 614, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #614 = VCEQv4i16 >+ { 615, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #615 = VCEQv4i32 >+ { 616, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #616 = VCEQv8i16 >+ { 617, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #617 = VCEQv8i8 >+ { 618, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #618 = VCEQzv16i8 >+ { 619, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #619 = VCEQzv2f32 >+ { 620, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #620 = VCEQzv2i32 >+ { 621, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #621 = VCEQzv4f32 >+ { 622, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #622 = VCEQzv4i16 >+ { 623, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #623 = VCEQzv4i32 >+ { 624, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #624 = VCEQzv8i16 >+ { 625, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #625 = VCEQzv8i8 >+ { 626, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #626 = VCGEfd >+ { 627, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #627 = VCGEfq >+ { 628, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #628 = VCGEsv16i8 >+ { 629, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #629 = VCGEsv2i32 >+ { 630, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #630 = VCGEsv4i16 >+ { 631, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #631 = VCGEsv4i32 >+ { 632, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #632 = VCGEsv8i16 >+ { 633, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #633 = VCGEsv8i8 >+ { 634, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #634 = VCGEuv16i8 >+ { 635, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #635 = VCGEuv2i32 >+ { 636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #636 = VCGEuv4i16 >+ { 637, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #637 = VCGEuv4i32 >+ { 638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #638 = VCGEuv8i16 >+ { 639, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #639 = VCGEuv8i8 >+ { 640, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #640 = VCGEzv16i8 >+ { 641, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #641 = VCGEzv2f32 >+ { 642, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #642 = VCGEzv2i32 >+ { 643, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #643 = VCGEzv4f32 >+ { 644, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #644 = VCGEzv4i16 >+ { 645, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #645 = VCGEzv4i32 >+ { 646, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #646 = VCGEzv8i16 >+ { 647, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #647 = VCGEzv8i8 >+ { 648, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #648 = VCGTfd >+ { 649, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #649 = VCGTfq >+ { 650, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #650 = VCGTsv16i8 >+ { 651, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #651 = VCGTsv2i32 >+ { 652, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #652 = VCGTsv4i16 >+ { 653, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #653 = VCGTsv4i32 >+ { 654, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #654 = VCGTsv8i16 >+ { 655, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #655 = VCGTsv8i8 >+ { 656, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #656 = VCGTuv16i8 >+ { 657, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #657 = VCGTuv2i32 >+ { 658, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #658 = VCGTuv4i16 >+ { 659, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #659 = VCGTuv4i32 >+ { 660, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #660 = VCGTuv8i16 >+ { 661, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #661 = VCGTuv8i8 >+ { 662, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #662 = VCGTzv16i8 >+ { 663, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #663 = VCGTzv2f32 >+ { 664, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #664 = VCGTzv2i32 >+ { 665, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #665 = VCGTzv4f32 >+ { 666, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #666 = VCGTzv4i16 >+ { 667, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #667 = VCGTzv4i32 >+ { 668, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #668 = VCGTzv8i16 >+ { 669, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #669 = VCGTzv8i8 >+ { 670, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #670 = VCLEzv16i8 >+ { 671, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #671 = VCLEzv2f32 >+ { 672, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #672 = VCLEzv2i32 >+ { 673, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #673 = VCLEzv4f32 >+ { 674, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #674 = VCLEzv4i16 >+ { 675, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #675 = VCLEzv4i32 >+ { 676, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #676 = VCLEzv8i16 >+ { 677, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #677 = VCLEzv8i8 >+ { 678, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #678 = VCLSv16i8 >+ { 679, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #679 = VCLSv2i32 >+ { 680, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #680 = VCLSv4i16 >+ { 681, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #681 = VCLSv4i32 >+ { 682, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #682 = VCLSv8i16 >+ { 683, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #683 = VCLSv8i8 >+ { 684, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #684 = VCLTzv16i8 >+ { 685, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #685 = VCLTzv2f32 >+ { 686, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #686 = VCLTzv2i32 >+ { 687, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #687 = VCLTzv4f32 >+ { 688, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #688 = VCLTzv4i16 >+ { 689, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #689 = VCLTzv4i32 >+ { 690, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #690 = VCLTzv8i16 >+ { 691, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #691 = VCLTzv8i8 >+ { 692, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #692 = VCLZv16i8 >+ { 693, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #693 = VCLZv2i32 >+ { 694, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #694 = VCLZv4i16 >+ { 695, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #695 = VCLZv4i32 >+ { 696, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #696 = VCLZv8i16 >+ { 697, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #697 = VCLZv8i8 >+ { 698, 4, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList4, OperandInfo129,0,nullptr }, // Inst #698 = VCMPD >+ { 699, 4, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList4, OperandInfo129,0,nullptr }, // Inst #699 = VCMPED >+ { 700, 4, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList4, OperandInfo130,0,nullptr }, // Inst #700 = VCMPES >+ { 701, 3, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList4, OperandInfo137,0,nullptr }, // Inst #701 = VCMPEZD >+ { 702, 3, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList4, OperandInfo138,0,nullptr }, // Inst #702 = VCMPEZS >+ { 703, 4, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList4, OperandInfo130,0,nullptr }, // Inst #703 = VCMPS >+ { 704, 3, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList4, OperandInfo137,0,nullptr }, // Inst #704 = VCMPZD >+ { 705, 3, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList4, OperandInfo138,0,nullptr }, // Inst #705 = VCMPZS >+ { 706, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #706 = VCNTd >+ { 707, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #707 = VCNTq >+ { 708, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #708 = VCVTANSD >+ { 709, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #709 = VCVTANSQ >+ { 710, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #710 = VCVTANUD >+ { 711, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #711 = VCVTANUQ >+ { 712, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #712 = VCVTASD >+ { 713, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #713 = VCVTASS >+ { 714, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #714 = VCVTAUD >+ { 715, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #715 = VCVTAUS >+ { 716, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #716 = VCVTBDH >+ { 717, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #717 = VCVTBHD >+ { 718, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #718 = VCVTBHS >+ { 719, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #719 = VCVTBSH >+ { 720, 4, 1, 477, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #720 = VCVTDS >+ { 721, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #721 = VCVTMNSD >+ { 722, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #722 = VCVTMNSQ >+ { 723, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #723 = VCVTMNUD >+ { 724, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #724 = VCVTMNUQ >+ { 725, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #725 = VCVTMSD >+ { 726, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #726 = VCVTMSS >+ { 727, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #727 = VCVTMUD >+ { 728, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #728 = VCVTMUS >+ { 729, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #729 = VCVTNNSD >+ { 730, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #730 = VCVTNNSQ >+ { 731, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #731 = VCVTNNUD >+ { 732, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #732 = VCVTNNUQ >+ { 733, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #733 = VCVTNSD >+ { 734, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #734 = VCVTNSS >+ { 735, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #735 = VCVTNUD >+ { 736, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #736 = VCVTNUS >+ { 737, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #737 = VCVTPNSD >+ { 738, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #738 = VCVTPNSQ >+ { 739, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #739 = VCVTPNUD >+ { 740, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #740 = VCVTPNUQ >+ { 741, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #741 = VCVTPSD >+ { 742, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #742 = VCVTPSS >+ { 743, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #743 = VCVTPUD >+ { 744, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #744 = VCVTPUS >+ { 745, 4, 1, 478, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #745 = VCVTSD >+ { 746, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #746 = VCVTTDH >+ { 747, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #747 = VCVTTHD >+ { 748, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #748 = VCVTTHS >+ { 749, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #749 = VCVTTSH >+ { 750, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #750 = VCVTf2h >+ { 751, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #751 = VCVTf2sd >+ { 752, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #752 = VCVTf2sq >+ { 753, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #753 = VCVTf2ud >+ { 754, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #754 = VCVTf2uq >+ { 755, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #755 = VCVTf2xsd >+ { 756, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #756 = VCVTf2xsq >+ { 757, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #757 = VCVTf2xud >+ { 758, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #758 = VCVTf2xuq >+ { 759, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #759 = VCVTh2f >+ { 760, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #760 = VCVTs2fd >+ { 761, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #761 = VCVTs2fq >+ { 762, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #762 = VCVTu2fd >+ { 763, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #763 = VCVTu2fq >+ { 764, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #764 = VCVTxs2fd >+ { 765, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #765 = VCVTxs2fq >+ { 766, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #766 = VCVTxu2fd >+ { 767, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #767 = VCVTxu2fq >+ { 768, 5, 1, 588, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #768 = VDIVD >+ { 769, 5, 1, 586, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #769 = VDIVS >+ { 770, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #770 = VDUP16d >+ { 771, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #771 = VDUP16q >+ { 772, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #772 = VDUP32d >+ { 773, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #773 = VDUP32q >+ { 774, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #774 = VDUP8d >+ { 775, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #775 = VDUP8q >+ { 776, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #776 = VDUPLN16d >+ { 777, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #777 = VDUPLN16q >+ { 778, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #778 = VDUPLN32d >+ { 779, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #779 = VDUPLN32q >+ { 780, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #780 = VDUPLN8d >+ { 781, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #781 = VDUPLN8q >+ { 782, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #782 = VEORd >+ { 783, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #783 = VEORq >+ { 784, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #784 = VEXTd16 >+ { 785, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #785 = VEXTd32 >+ { 786, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #786 = VEXTd8 >+ { 787, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #787 = VEXTq16 >+ { 788, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #788 = VEXTq32 >+ { 789, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #789 = VEXTq64 >+ { 790, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #790 = VEXTq8 >+ { 791, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #791 = VFMAD >+ { 792, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #792 = VFMAS >+ { 793, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #793 = VFMAfd >+ { 794, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #794 = VFMAfq >+ { 795, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #795 = VFMSD >+ { 796, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #796 = VFMSS >+ { 797, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #797 = VFMSfd >+ { 798, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #798 = VFMSfq >+ { 799, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #799 = VFNMAD >+ { 800, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #800 = VFNMAS >+ { 801, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #801 = VFNMSD >+ { 802, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #802 = VFNMSS >+ { 803, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #803 = VGETLNi32 >+ { 804, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #804 = VGETLNs16 >+ { 805, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #805 = VGETLNs8 >+ { 806, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #806 = VGETLNu16 >+ { 807, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #807 = VGETLNu8 >+ { 808, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #808 = VHADDsv16i8 >+ { 809, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #809 = VHADDsv2i32 >+ { 810, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #810 = VHADDsv4i16 >+ { 811, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #811 = VHADDsv4i32 >+ { 812, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #812 = VHADDsv8i16 >+ { 813, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #813 = VHADDsv8i8 >+ { 814, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #814 = VHADDuv16i8 >+ { 815, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #815 = VHADDuv2i32 >+ { 816, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #816 = VHADDuv4i16 >+ { 817, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #817 = VHADDuv4i32 >+ { 818, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #818 = VHADDuv8i16 >+ { 819, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #819 = VHADDuv8i8 >+ { 820, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #820 = VHSUBsv16i8 >+ { 821, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #821 = VHSUBsv2i32 >+ { 822, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #822 = VHSUBsv4i16 >+ { 823, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #823 = VHSUBsv4i32 >+ { 824, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #824 = VHSUBsv8i16 >+ { 825, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #825 = VHSUBsv8i8 >+ { 826, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #826 = VHSUBuv16i8 >+ { 827, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #827 = VHSUBuv2i32 >+ { 828, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #828 = VHSUBuv4i16 >+ { 829, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #829 = VHSUBuv4i32 >+ { 830, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #830 = VHSUBuv8i16 >+ { 831, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #831 = VHSUBuv8i8 >+ { 832, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #832 = VLD1DUPd16 >+ { 833, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #833 = VLD1DUPd16wb_fixed >+ { 834, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #834 = VLD1DUPd16wb_register >+ { 835, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #835 = VLD1DUPd32 >+ { 836, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #836 = VLD1DUPd32wb_fixed >+ { 837, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #837 = VLD1DUPd32wb_register >+ { 838, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #838 = VLD1DUPd8 >+ { 839, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #839 = VLD1DUPd8wb_fixed >+ { 840, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #840 = VLD1DUPd8wb_register >+ { 841, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #841 = VLD1DUPq16 >+ { 842, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #842 = VLD1DUPq16wb_fixed >+ { 843, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #843 = VLD1DUPq16wb_register >+ { 844, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #844 = VLD1DUPq32 >+ { 845, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #845 = VLD1DUPq32wb_fixed >+ { 846, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #846 = VLD1DUPq32wb_register >+ { 847, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #847 = VLD1DUPq8 >+ { 848, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #848 = VLD1DUPq8wb_fixed >+ { 849, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #849 = VLD1DUPq8wb_register >+ { 850, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #850 = VLD1LNd16 >+ { 851, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #851 = VLD1LNd16_UPD >+ { 852, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #852 = VLD1LNd32 >+ { 853, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #853 = VLD1LNd32_UPD >+ { 854, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #854 = VLD1LNd8 >+ { 855, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #855 = VLD1LNd8_UPD >+ { 856, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #856 = VLD1LNdAsm_16 >+ { 857, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #857 = VLD1LNdAsm_32 >+ { 858, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #858 = VLD1LNdAsm_8 >+ { 859, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #859 = VLD1LNdWB_fixed_Asm_16 >+ { 860, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #860 = VLD1LNdWB_fixed_Asm_32 >+ { 861, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #861 = VLD1LNdWB_fixed_Asm_8 >+ { 862, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #862 = VLD1LNdWB_register_Asm_16 >+ { 863, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #863 = VLD1LNdWB_register_Asm_32 >+ { 864, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #864 = VLD1LNdWB_register_Asm_8 >+ { 865, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #865 = VLD1LNq16Pseudo >+ { 866, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #866 = VLD1LNq16Pseudo_UPD >+ { 867, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #867 = VLD1LNq32Pseudo >+ { 868, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #868 = VLD1LNq32Pseudo_UPD >+ { 869, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #869 = VLD1LNq8Pseudo >+ { 870, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #870 = VLD1LNq8Pseudo_UPD >+ { 871, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #871 = VLD1d16 >+ { 872, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #872 = VLD1d16Q >+ { 873, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #873 = VLD1d16Qwb_fixed >+ { 874, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #874 = VLD1d16Qwb_register >+ { 875, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #875 = VLD1d16T >+ { 876, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #876 = VLD1d16Twb_fixed >+ { 877, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #877 = VLD1d16Twb_register >+ { 878, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #878 = VLD1d16wb_fixed >+ { 879, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #879 = VLD1d16wb_register >+ { 880, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #880 = VLD1d32 >+ { 881, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #881 = VLD1d32Q >+ { 882, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #882 = VLD1d32Qwb_fixed >+ { 883, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #883 = VLD1d32Qwb_register >+ { 884, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #884 = VLD1d32T >+ { 885, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #885 = VLD1d32Twb_fixed >+ { 886, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #886 = VLD1d32Twb_register >+ { 887, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #887 = VLD1d32wb_fixed >+ { 888, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #888 = VLD1d32wb_register >+ { 889, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #889 = VLD1d64 >+ { 890, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #890 = VLD1d64Q >+ { 891, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #891 = VLD1d64QPseudo >+ { 892, 6, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #892 = VLD1d64QPseudoWB_fixed >+ { 893, 7, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #893 = VLD1d64QPseudoWB_register >+ { 894, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #894 = VLD1d64Qwb_fixed >+ { 895, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #895 = VLD1d64Qwb_register >+ { 896, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #896 = VLD1d64T >+ { 897, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #897 = VLD1d64TPseudo >+ { 898, 6, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #898 = VLD1d64TPseudoWB_fixed >+ { 899, 7, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #899 = VLD1d64TPseudoWB_register >+ { 900, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #900 = VLD1d64Twb_fixed >+ { 901, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #901 = VLD1d64Twb_register >+ { 902, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #902 = VLD1d64wb_fixed >+ { 903, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #903 = VLD1d64wb_register >+ { 904, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #904 = VLD1d8 >+ { 905, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #905 = VLD1d8Q >+ { 906, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #906 = VLD1d8Qwb_fixed >+ { 907, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #907 = VLD1d8Qwb_register >+ { 908, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #908 = VLD1d8T >+ { 909, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #909 = VLD1d8Twb_fixed >+ { 910, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #910 = VLD1d8Twb_register >+ { 911, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #911 = VLD1d8wb_fixed >+ { 912, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #912 = VLD1d8wb_register >+ { 913, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #913 = VLD1q16 >+ { 914, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #914 = VLD1q16wb_fixed >+ { 915, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #915 = VLD1q16wb_register >+ { 916, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #916 = VLD1q32 >+ { 917, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #917 = VLD1q32wb_fixed >+ { 918, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #918 = VLD1q32wb_register >+ { 919, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #919 = VLD1q64 >+ { 920, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #920 = VLD1q64wb_fixed >+ { 921, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #921 = VLD1q64wb_register >+ { 922, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #922 = VLD1q8 >+ { 923, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #923 = VLD1q8wb_fixed >+ { 924, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #924 = VLD1q8wb_register >+ { 925, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #925 = VLD2DUPd16 >+ { 926, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #926 = VLD2DUPd16wb_fixed >+ { 927, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #927 = VLD2DUPd16wb_register >+ { 928, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #928 = VLD2DUPd16x2 >+ { 929, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #929 = VLD2DUPd16x2wb_fixed >+ { 930, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #930 = VLD2DUPd16x2wb_register >+ { 931, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #931 = VLD2DUPd32 >+ { 932, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #932 = VLD2DUPd32wb_fixed >+ { 933, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #933 = VLD2DUPd32wb_register >+ { 934, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #934 = VLD2DUPd32x2 >+ { 935, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #935 = VLD2DUPd32x2wb_fixed >+ { 936, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #936 = VLD2DUPd32x2wb_register >+ { 937, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #937 = VLD2DUPd8 >+ { 938, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #938 = VLD2DUPd8wb_fixed >+ { 939, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #939 = VLD2DUPd8wb_register >+ { 940, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #940 = VLD2DUPd8x2 >+ { 941, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #941 = VLD2DUPd8x2wb_fixed >+ { 942, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #942 = VLD2DUPd8x2wb_register >+ { 943, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #943 = VLD2LNd16 >+ { 944, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #944 = VLD2LNd16Pseudo >+ { 945, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #945 = VLD2LNd16Pseudo_UPD >+ { 946, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #946 = VLD2LNd16_UPD >+ { 947, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #947 = VLD2LNd32 >+ { 948, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #948 = VLD2LNd32Pseudo >+ { 949, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #949 = VLD2LNd32Pseudo_UPD >+ { 950, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #950 = VLD2LNd32_UPD >+ { 951, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #951 = VLD2LNd8 >+ { 952, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #952 = VLD2LNd8Pseudo >+ { 953, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #953 = VLD2LNd8Pseudo_UPD >+ { 954, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #954 = VLD2LNd8_UPD >+ { 955, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #955 = VLD2LNdAsm_16 >+ { 956, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #956 = VLD2LNdAsm_32 >+ { 957, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #957 = VLD2LNdAsm_8 >+ { 958, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #958 = VLD2LNdWB_fixed_Asm_16 >+ { 959, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #959 = VLD2LNdWB_fixed_Asm_32 >+ { 960, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #960 = VLD2LNdWB_fixed_Asm_8 >+ { 961, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #961 = VLD2LNdWB_register_Asm_16 >+ { 962, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #962 = VLD2LNdWB_register_Asm_32 >+ { 963, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #963 = VLD2LNdWB_register_Asm_8 >+ { 964, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #964 = VLD2LNq16 >+ { 965, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #965 = VLD2LNq16Pseudo >+ { 966, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #966 = VLD2LNq16Pseudo_UPD >+ { 967, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #967 = VLD2LNq16_UPD >+ { 968, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #968 = VLD2LNq32 >+ { 969, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #969 = VLD2LNq32Pseudo >+ { 970, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #970 = VLD2LNq32Pseudo_UPD >+ { 971, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #971 = VLD2LNq32_UPD >+ { 972, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #972 = VLD2LNqAsm_16 >+ { 973, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #973 = VLD2LNqAsm_32 >+ { 974, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #974 = VLD2LNqWB_fixed_Asm_16 >+ { 975, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #975 = VLD2LNqWB_fixed_Asm_32 >+ { 976, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #976 = VLD2LNqWB_register_Asm_16 >+ { 977, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #977 = VLD2LNqWB_register_Asm_32 >+ { 978, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #978 = VLD2b16 >+ { 979, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #979 = VLD2b16wb_fixed >+ { 980, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #980 = VLD2b16wb_register >+ { 981, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #981 = VLD2b32 >+ { 982, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #982 = VLD2b32wb_fixed >+ { 983, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #983 = VLD2b32wb_register >+ { 984, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #984 = VLD2b8 >+ { 985, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #985 = VLD2b8wb_fixed >+ { 986, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #986 = VLD2b8wb_register >+ { 987, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #987 = VLD2d16 >+ { 988, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #988 = VLD2d16wb_fixed >+ { 989, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #989 = VLD2d16wb_register >+ { 990, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #990 = VLD2d32 >+ { 991, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #991 = VLD2d32wb_fixed >+ { 992, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #992 = VLD2d32wb_register >+ { 993, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #993 = VLD2d8 >+ { 994, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #994 = VLD2d8wb_fixed >+ { 995, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #995 = VLD2d8wb_register >+ { 996, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #996 = VLD2q16 >+ { 997, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #997 = VLD2q16Pseudo >+ { 998, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #998 = VLD2q16PseudoWB_fixed >+ { 999, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #999 = VLD2q16PseudoWB_register >+ { 1000, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1000 = VLD2q16wb_fixed >+ { 1001, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1001 = VLD2q16wb_register >+ { 1002, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1002 = VLD2q32 >+ { 1003, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1003 = VLD2q32Pseudo >+ { 1004, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1004 = VLD2q32PseudoWB_fixed >+ { 1005, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #1005 = VLD2q32PseudoWB_register >+ { 1006, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1006 = VLD2q32wb_fixed >+ { 1007, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1007 = VLD2q32wb_register >+ { 1008, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1008 = VLD2q8 >+ { 1009, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1009 = VLD2q8Pseudo >+ { 1010, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1010 = VLD2q8PseudoWB_fixed >+ { 1011, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #1011 = VLD2q8PseudoWB_register >+ { 1012, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #1012 = VLD2q8wb_fixed >+ { 1013, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1013 = VLD2q8wb_register >+ { 1014, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1014 = VLD3DUPd16 >+ { 1015, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1015 = VLD3DUPd16Pseudo >+ { 1016, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1016 = VLD3DUPd16Pseudo_UPD >+ { 1017, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1017 = VLD3DUPd16_UPD >+ { 1018, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1018 = VLD3DUPd32 >+ { 1019, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1019 = VLD3DUPd32Pseudo >+ { 1020, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1020 = VLD3DUPd32Pseudo_UPD >+ { 1021, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1021 = VLD3DUPd32_UPD >+ { 1022, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1022 = VLD3DUPd8 >+ { 1023, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1023 = VLD3DUPd8Pseudo >+ { 1024, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1024 = VLD3DUPd8Pseudo_UPD >+ { 1025, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1025 = VLD3DUPd8_UPD >+ { 1026, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1026 = VLD3DUPdAsm_16 >+ { 1027, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1027 = VLD3DUPdAsm_32 >+ { 1028, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1028 = VLD3DUPdAsm_8 >+ { 1029, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1029 = VLD3DUPdWB_fixed_Asm_16 >+ { 1030, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1030 = VLD3DUPdWB_fixed_Asm_32 >+ { 1031, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1031 = VLD3DUPdWB_fixed_Asm_8 >+ { 1032, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1032 = VLD3DUPdWB_register_Asm_16 >+ { 1033, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1033 = VLD3DUPdWB_register_Asm_32 >+ { 1034, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1034 = VLD3DUPdWB_register_Asm_8 >+ { 1035, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1035 = VLD3DUPq16 >+ { 1036, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1036 = VLD3DUPq16_UPD >+ { 1037, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1037 = VLD3DUPq32 >+ { 1038, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1038 = VLD3DUPq32_UPD >+ { 1039, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1039 = VLD3DUPq8 >+ { 1040, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1040 = VLD3DUPq8_UPD >+ { 1041, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1041 = VLD3DUPqAsm_16 >+ { 1042, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1042 = VLD3DUPqAsm_32 >+ { 1043, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1043 = VLD3DUPqAsm_8 >+ { 1044, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1044 = VLD3DUPqWB_fixed_Asm_16 >+ { 1045, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1045 = VLD3DUPqWB_fixed_Asm_32 >+ { 1046, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1046 = VLD3DUPqWB_fixed_Asm_8 >+ { 1047, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1047 = VLD3DUPqWB_register_Asm_16 >+ { 1048, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1048 = VLD3DUPqWB_register_Asm_32 >+ { 1049, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1049 = VLD3DUPqWB_register_Asm_8 >+ { 1050, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1050 = VLD3LNd16 >+ { 1051, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1051 = VLD3LNd16Pseudo >+ { 1052, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1052 = VLD3LNd16Pseudo_UPD >+ { 1053, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1053 = VLD3LNd16_UPD >+ { 1054, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1054 = VLD3LNd32 >+ { 1055, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1055 = VLD3LNd32Pseudo >+ { 1056, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1056 = VLD3LNd32Pseudo_UPD >+ { 1057, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1057 = VLD3LNd32_UPD >+ { 1058, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1058 = VLD3LNd8 >+ { 1059, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1059 = VLD3LNd8Pseudo >+ { 1060, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1060 = VLD3LNd8Pseudo_UPD >+ { 1061, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1061 = VLD3LNd8_UPD >+ { 1062, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1062 = VLD3LNdAsm_16 >+ { 1063, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1063 = VLD3LNdAsm_32 >+ { 1064, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1064 = VLD3LNdAsm_8 >+ { 1065, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1065 = VLD3LNdWB_fixed_Asm_16 >+ { 1066, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1066 = VLD3LNdWB_fixed_Asm_32 >+ { 1067, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1067 = VLD3LNdWB_fixed_Asm_8 >+ { 1068, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1068 = VLD3LNdWB_register_Asm_16 >+ { 1069, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1069 = VLD3LNdWB_register_Asm_32 >+ { 1070, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1070 = VLD3LNdWB_register_Asm_8 >+ { 1071, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1071 = VLD3LNq16 >+ { 1072, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1072 = VLD3LNq16Pseudo >+ { 1073, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1073 = VLD3LNq16Pseudo_UPD >+ { 1074, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1074 = VLD3LNq16_UPD >+ { 1075, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1075 = VLD3LNq32 >+ { 1076, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1076 = VLD3LNq32Pseudo >+ { 1077, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1077 = VLD3LNq32Pseudo_UPD >+ { 1078, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1078 = VLD3LNq32_UPD >+ { 1079, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1079 = VLD3LNqAsm_16 >+ { 1080, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1080 = VLD3LNqAsm_32 >+ { 1081, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1081 = VLD3LNqWB_fixed_Asm_16 >+ { 1082, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1082 = VLD3LNqWB_fixed_Asm_32 >+ { 1083, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1083 = VLD3LNqWB_register_Asm_16 >+ { 1084, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1084 = VLD3LNqWB_register_Asm_32 >+ { 1085, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1085 = VLD3d16 >+ { 1086, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1086 = VLD3d16Pseudo >+ { 1087, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1087 = VLD3d16Pseudo_UPD >+ { 1088, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1088 = VLD3d16_UPD >+ { 1089, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1089 = VLD3d32 >+ { 1090, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1090 = VLD3d32Pseudo >+ { 1091, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1091 = VLD3d32Pseudo_UPD >+ { 1092, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1092 = VLD3d32_UPD >+ { 1093, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1093 = VLD3d8 >+ { 1094, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1094 = VLD3d8Pseudo >+ { 1095, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1095 = VLD3d8Pseudo_UPD >+ { 1096, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1096 = VLD3d8_UPD >+ { 1097, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1097 = VLD3dAsm_16 >+ { 1098, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1098 = VLD3dAsm_32 >+ { 1099, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1099 = VLD3dAsm_8 >+ { 1100, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1100 = VLD3dWB_fixed_Asm_16 >+ { 1101, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1101 = VLD3dWB_fixed_Asm_32 >+ { 1102, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1102 = VLD3dWB_fixed_Asm_8 >+ { 1103, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1103 = VLD3dWB_register_Asm_16 >+ { 1104, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1104 = VLD3dWB_register_Asm_32 >+ { 1105, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1105 = VLD3dWB_register_Asm_8 >+ { 1106, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1106 = VLD3q16 >+ { 1107, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1107 = VLD3q16Pseudo_UPD >+ { 1108, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1108 = VLD3q16_UPD >+ { 1109, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1109 = VLD3q16oddPseudo >+ { 1110, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1110 = VLD3q16oddPseudo_UPD >+ { 1111, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1111 = VLD3q32 >+ { 1112, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1112 = VLD3q32Pseudo_UPD >+ { 1113, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1113 = VLD3q32_UPD >+ { 1114, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1114 = VLD3q32oddPseudo >+ { 1115, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1115 = VLD3q32oddPseudo_UPD >+ { 1116, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #1116 = VLD3q8 >+ { 1117, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1117 = VLD3q8Pseudo_UPD >+ { 1118, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1118 = VLD3q8_UPD >+ { 1119, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1119 = VLD3q8oddPseudo >+ { 1120, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1120 = VLD3q8oddPseudo_UPD >+ { 1121, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1121 = VLD3qAsm_16 >+ { 1122, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1122 = VLD3qAsm_32 >+ { 1123, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1123 = VLD3qAsm_8 >+ { 1124, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1124 = VLD3qWB_fixed_Asm_16 >+ { 1125, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1125 = VLD3qWB_fixed_Asm_32 >+ { 1126, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1126 = VLD3qWB_fixed_Asm_8 >+ { 1127, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1127 = VLD3qWB_register_Asm_16 >+ { 1128, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1128 = VLD3qWB_register_Asm_32 >+ { 1129, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1129 = VLD3qWB_register_Asm_8 >+ { 1130, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1130 = VLD4DUPd16 >+ { 1131, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1131 = VLD4DUPd16Pseudo >+ { 1132, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1132 = VLD4DUPd16Pseudo_UPD >+ { 1133, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1133 = VLD4DUPd16_UPD >+ { 1134, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1134 = VLD4DUPd32 >+ { 1135, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1135 = VLD4DUPd32Pseudo >+ { 1136, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1136 = VLD4DUPd32Pseudo_UPD >+ { 1137, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1137 = VLD4DUPd32_UPD >+ { 1138, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1138 = VLD4DUPd8 >+ { 1139, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1139 = VLD4DUPd8Pseudo >+ { 1140, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1140 = VLD4DUPd8Pseudo_UPD >+ { 1141, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1141 = VLD4DUPd8_UPD >+ { 1142, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1142 = VLD4DUPdAsm_16 >+ { 1143, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1143 = VLD4DUPdAsm_32 >+ { 1144, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1144 = VLD4DUPdAsm_8 >+ { 1145, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1145 = VLD4DUPdWB_fixed_Asm_16 >+ { 1146, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1146 = VLD4DUPdWB_fixed_Asm_32 >+ { 1147, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1147 = VLD4DUPdWB_fixed_Asm_8 >+ { 1148, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1148 = VLD4DUPdWB_register_Asm_16 >+ { 1149, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1149 = VLD4DUPdWB_register_Asm_32 >+ { 1150, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1150 = VLD4DUPdWB_register_Asm_8 >+ { 1151, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1151 = VLD4DUPq16 >+ { 1152, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1152 = VLD4DUPq16_UPD >+ { 1153, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1153 = VLD4DUPq32 >+ { 1154, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1154 = VLD4DUPq32_UPD >+ { 1155, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1155 = VLD4DUPq8 >+ { 1156, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1156 = VLD4DUPq8_UPD >+ { 1157, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1157 = VLD4DUPqAsm_16 >+ { 1158, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1158 = VLD4DUPqAsm_32 >+ { 1159, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1159 = VLD4DUPqAsm_8 >+ { 1160, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1160 = VLD4DUPqWB_fixed_Asm_16 >+ { 1161, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1161 = VLD4DUPqWB_fixed_Asm_32 >+ { 1162, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1162 = VLD4DUPqWB_fixed_Asm_8 >+ { 1163, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1163 = VLD4DUPqWB_register_Asm_16 >+ { 1164, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1164 = VLD4DUPqWB_register_Asm_32 >+ { 1165, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1165 = VLD4DUPqWB_register_Asm_8 >+ { 1166, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1166 = VLD4LNd16 >+ { 1167, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1167 = VLD4LNd16Pseudo >+ { 1168, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1168 = VLD4LNd16Pseudo_UPD >+ { 1169, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1169 = VLD4LNd16_UPD >+ { 1170, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1170 = VLD4LNd32 >+ { 1171, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1171 = VLD4LNd32Pseudo >+ { 1172, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1172 = VLD4LNd32Pseudo_UPD >+ { 1173, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1173 = VLD4LNd32_UPD >+ { 1174, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1174 = VLD4LNd8 >+ { 1175, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1175 = VLD4LNd8Pseudo >+ { 1176, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1176 = VLD4LNd8Pseudo_UPD >+ { 1177, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1177 = VLD4LNd8_UPD >+ { 1178, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1178 = VLD4LNdAsm_16 >+ { 1179, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1179 = VLD4LNdAsm_32 >+ { 1180, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1180 = VLD4LNdAsm_8 >+ { 1181, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1181 = VLD4LNdWB_fixed_Asm_16 >+ { 1182, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1182 = VLD4LNdWB_fixed_Asm_32 >+ { 1183, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1183 = VLD4LNdWB_fixed_Asm_8 >+ { 1184, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1184 = VLD4LNdWB_register_Asm_16 >+ { 1185, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1185 = VLD4LNdWB_register_Asm_32 >+ { 1186, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1186 = VLD4LNdWB_register_Asm_8 >+ { 1187, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1187 = VLD4LNq16 >+ { 1188, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1188 = VLD4LNq16Pseudo >+ { 1189, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1189 = VLD4LNq16Pseudo_UPD >+ { 1190, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1190 = VLD4LNq16_UPD >+ { 1191, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1191 = VLD4LNq32 >+ { 1192, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1192 = VLD4LNq32Pseudo >+ { 1193, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1193 = VLD4LNq32Pseudo_UPD >+ { 1194, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1194 = VLD4LNq32_UPD >+ { 1195, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1195 = VLD4LNqAsm_16 >+ { 1196, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1196 = VLD4LNqAsm_32 >+ { 1197, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1197 = VLD4LNqWB_fixed_Asm_16 >+ { 1198, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1198 = VLD4LNqWB_fixed_Asm_32 >+ { 1199, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1199 = VLD4LNqWB_register_Asm_16 >+ { 1200, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1200 = VLD4LNqWB_register_Asm_32 >+ { 1201, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1201 = VLD4d16 >+ { 1202, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1202 = VLD4d16Pseudo >+ { 1203, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1203 = VLD4d16Pseudo_UPD >+ { 1204, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1204 = VLD4d16_UPD >+ { 1205, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1205 = VLD4d32 >+ { 1206, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1206 = VLD4d32Pseudo >+ { 1207, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1207 = VLD4d32Pseudo_UPD >+ { 1208, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1208 = VLD4d32_UPD >+ { 1209, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1209 = VLD4d8 >+ { 1210, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1210 = VLD4d8Pseudo >+ { 1211, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #1211 = VLD4d8Pseudo_UPD >+ { 1212, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1212 = VLD4d8_UPD >+ { 1213, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1213 = VLD4dAsm_16 >+ { 1214, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1214 = VLD4dAsm_32 >+ { 1215, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1215 = VLD4dAsm_8 >+ { 1216, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1216 = VLD4dWB_fixed_Asm_16 >+ { 1217, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1217 = VLD4dWB_fixed_Asm_32 >+ { 1218, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1218 = VLD4dWB_fixed_Asm_8 >+ { 1219, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1219 = VLD4dWB_register_Asm_16 >+ { 1220, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1220 = VLD4dWB_register_Asm_32 >+ { 1221, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1221 = VLD4dWB_register_Asm_8 >+ { 1222, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1222 = VLD4q16 >+ { 1223, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1223 = VLD4q16Pseudo_UPD >+ { 1224, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1224 = VLD4q16_UPD >+ { 1225, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1225 = VLD4q16oddPseudo >+ { 1226, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1226 = VLD4q16oddPseudo_UPD >+ { 1227, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1227 = VLD4q32 >+ { 1228, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1228 = VLD4q32Pseudo_UPD >+ { 1229, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1229 = VLD4q32_UPD >+ { 1230, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1230 = VLD4q32oddPseudo >+ { 1231, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1231 = VLD4q32oddPseudo_UPD >+ { 1232, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1232 = VLD4q8 >+ { 1233, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1233 = VLD4q8Pseudo_UPD >+ { 1234, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1234 = VLD4q8_UPD >+ { 1235, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1235 = VLD4q8oddPseudo >+ { 1236, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1236 = VLD4q8oddPseudo_UPD >+ { 1237, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1237 = VLD4qAsm_16 >+ { 1238, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1238 = VLD4qAsm_32 >+ { 1239, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1239 = VLD4qAsm_8 >+ { 1240, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1240 = VLD4qWB_fixed_Asm_16 >+ { 1241, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1241 = VLD4qWB_fixed_Asm_32 >+ { 1242, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #1242 = VLD4qWB_fixed_Asm_8 >+ { 1243, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1243 = VLD4qWB_register_Asm_16 >+ { 1244, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1244 = VLD4qWB_register_Asm_32 >+ { 1245, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1245 = VLD4qWB_register_Asm_8 >+ { 1246, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1246 = VLDMDDB_UPD >+ { 1247, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1247 = VLDMDIA >+ { 1248, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1248 = VLDMDIA_UPD >+ { 1249, 4, 1, 512, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1249 = VLDMQIA >+ { 1250, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1250 = VLDMSDB_UPD >+ { 1251, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1251 = VLDMSIA >+ { 1252, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #1252 = VLDMSIA_UPD >+ { 1253, 5, 1, 508, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1253 = VLDRD >+ { 1254, 5, 1, 509, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1254 = VLDRS >+ { 1255, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1255 = VMAXNMD >+ { 1256, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1256 = VMAXNMND >+ { 1257, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1257 = VMAXNMNQ >+ { 1258, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1258 = VMAXNMS >+ { 1259, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1259 = VMAXfd >+ { 1260, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1260 = VMAXfq >+ { 1261, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1261 = VMAXsv16i8 >+ { 1262, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1262 = VMAXsv2i32 >+ { 1263, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1263 = VMAXsv4i16 >+ { 1264, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1264 = VMAXsv4i32 >+ { 1265, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1265 = VMAXsv8i16 >+ { 1266, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1266 = VMAXsv8i8 >+ { 1267, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1267 = VMAXuv16i8 >+ { 1268, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1268 = VMAXuv2i32 >+ { 1269, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1269 = VMAXuv4i16 >+ { 1270, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1270 = VMAXuv4i32 >+ { 1271, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1271 = VMAXuv8i16 >+ { 1272, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1272 = VMAXuv8i8 >+ { 1273, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1273 = VMINNMD >+ { 1274, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1274 = VMINNMND >+ { 1275, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1275 = VMINNMNQ >+ { 1276, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1276 = VMINNMS >+ { 1277, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1277 = VMINfd >+ { 1278, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1278 = VMINfq >+ { 1279, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1279 = VMINsv16i8 >+ { 1280, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1280 = VMINsv2i32 >+ { 1281, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1281 = VMINsv4i16 >+ { 1282, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1282 = VMINsv4i32 >+ { 1283, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1283 = VMINsv8i16 >+ { 1284, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1284 = VMINsv8i8 >+ { 1285, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1285 = VMINuv16i8 >+ { 1286, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1286 = VMINuv2i32 >+ { 1287, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1287 = VMINuv4i16 >+ { 1288, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1288 = VMINuv4i32 >+ { 1289, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1289 = VMINuv8i16 >+ { 1290, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1290 = VMINuv8i8 >+ { 1291, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1291 = VMLAD >+ { 1292, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1292 = VMLALslsv2i32 >+ { 1293, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1293 = VMLALslsv4i16 >+ { 1294, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1294 = VMLALsluv2i32 >+ { 1295, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1295 = VMLALsluv4i16 >+ { 1296, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1296 = VMLALsv2i64 >+ { 1297, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1297 = VMLALsv4i32 >+ { 1298, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1298 = VMLALsv8i16 >+ { 1299, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1299 = VMLALuv2i64 >+ { 1300, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1300 = VMLALuv4i32 >+ { 1301, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1301 = VMLALuv8i16 >+ { 1302, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1302 = VMLAS >+ { 1303, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1303 = VMLAfd >+ { 1304, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1304 = VMLAfq >+ { 1305, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1305 = VMLAslfd >+ { 1306, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1306 = VMLAslfq >+ { 1307, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1307 = VMLAslv2i32 >+ { 1308, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1308 = VMLAslv4i16 >+ { 1309, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1309 = VMLAslv4i32 >+ { 1310, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1310 = VMLAslv8i16 >+ { 1311, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1311 = VMLAv16i8 >+ { 1312, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1312 = VMLAv2i32 >+ { 1313, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1313 = VMLAv4i16 >+ { 1314, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1314 = VMLAv4i32 >+ { 1315, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1315 = VMLAv8i16 >+ { 1316, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1316 = VMLAv8i8 >+ { 1317, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1317 = VMLSD >+ { 1318, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1318 = VMLSLslsv2i32 >+ { 1319, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1319 = VMLSLslsv4i16 >+ { 1320, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1320 = VMLSLsluv2i32 >+ { 1321, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1321 = VMLSLsluv4i16 >+ { 1322, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1322 = VMLSLsv2i64 >+ { 1323, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1323 = VMLSLsv4i32 >+ { 1324, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1324 = VMLSLsv8i16 >+ { 1325, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1325 = VMLSLuv2i64 >+ { 1326, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1326 = VMLSLuv4i32 >+ { 1327, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1327 = VMLSLuv8i16 >+ { 1328, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1328 = VMLSS >+ { 1329, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1329 = VMLSfd >+ { 1330, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1330 = VMLSfq >+ { 1331, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1331 = VMLSslfd >+ { 1332, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1332 = VMLSslfq >+ { 1333, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1333 = VMLSslv2i32 >+ { 1334, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1334 = VMLSslv4i16 >+ { 1335, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1335 = VMLSslv4i32 >+ { 1336, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1336 = VMLSslv8i16 >+ { 1337, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1337 = VMLSv16i8 >+ { 1338, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1338 = VMLSv2i32 >+ { 1339, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1339 = VMLSv4i16 >+ { 1340, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1340 = VMLSv4i32 >+ { 1341, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #1341 = VMLSv8i16 >+ { 1342, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1342 = VMLSv8i8 >+ { 1343, 4, 1, 487, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1343 = VMOVD >+ { 1344, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1344 = VMOVD0 >+ { 1345, 5, 1, 501, 4, 0|(1<<MCID_Predicable)|(1<<MCID_RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1345 = VMOVDRR >+ { 1346, 5, 1, 487, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1346 = VMOVDcc >+ { 1347, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1347 = VMOVLsv2i64 >+ { 1348, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1348 = VMOVLsv4i32 >+ { 1349, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1349 = VMOVLsv8i16 >+ { 1350, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1350 = VMOVLuv2i64 >+ { 1351, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1351 = VMOVLuv4i32 >+ { 1352, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1352 = VMOVLuv8i16 >+ { 1353, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1353 = VMOVNv2i32 >+ { 1354, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1354 = VMOVNv4i16 >+ { 1355, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1355 = VMOVNv8i8 >+ { 1356, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo203,0,nullptr }, // Inst #1356 = VMOVQ0 >+ { 1357, 5, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1357 = VMOVRRD >+ { 1358, 6, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1358 = VMOVRRS >+ { 1359, 4, 1, 497, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo206,0,nullptr }, // Inst #1359 = VMOVRS >+ { 1360, 4, 1, 488, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1360 = VMOVS >+ { 1361, 4, 1, 498, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo207,0,nullptr }, // Inst #1361 = VMOVSR >+ { 1362, 6, 2, 502, 4, 0|(1<<MCID_Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo208,0,nullptr }, // Inst #1362 = VMOVSRR >+ { 1363, 5, 1, 488, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo209,0,nullptr }, // Inst #1363 = VMOVScc >+ { 1364, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1364 = VMOVv16i8 >+ { 1365, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1365 = VMOVv1i64 >+ { 1366, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1366 = VMOVv2f32 >+ { 1367, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1367 = VMOVv2i32 >+ { 1368, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1368 = VMOVv2i64 >+ { 1369, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1369 = VMOVv4f32 >+ { 1370, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1370 = VMOVv4i16 >+ { 1371, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1371 = VMOVv4i32 >+ { 1372, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1372 = VMOVv8i16 >+ { 1373, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1373 = VMOVv8i8 >+ { 1374, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1374 = VMRS >+ { 1375, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1375 = VMRS_FPEXC >+ { 1376, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1376 = VMRS_FPINST >+ { 1377, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1377 = VMRS_FPINST2 >+ { 1378, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1378 = VMRS_FPSID >+ { 1379, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1379 = VMRS_MVFR0 >+ { 1380, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1380 = VMRS_MVFR1 >+ { 1381, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, nullptr, OperandInfo33,0,nullptr }, // Inst #1381 = VMRS_MVFR2 >+ { 1382, 3, 0, 506, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1382 = VMSR >+ { 1383, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1383 = VMSR_FPEXC >+ { 1384, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1384 = VMSR_FPINST >+ { 1385, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1385 = VMSR_FPINST2 >+ { 1386, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList9, OperandInfo33,0,nullptr }, // Inst #1386 = VMSR_FPSID >+ { 1387, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1387 = VMULD >+ { 1388, 3, 1, 451, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo211,0,nullptr }, // Inst #1388 = VMULLp64 >+ { 1389, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1389 = VMULLp8 >+ { 1390, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1390 = VMULLslsv2i32 >+ { 1391, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1391 = VMULLslsv4i16 >+ { 1392, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1392 = VMULLsluv2i32 >+ { 1393, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1393 = VMULLsluv4i16 >+ { 1394, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1394 = VMULLsv2i64 >+ { 1395, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1395 = VMULLsv4i32 >+ { 1396, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1396 = VMULLsv8i16 >+ { 1397, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1397 = VMULLuv2i64 >+ { 1398, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1398 = VMULLuv4i32 >+ { 1399, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1399 = VMULLuv8i16 >+ { 1400, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1400 = VMULS >+ { 1401, 5, 1, 455, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1401 = VMULfd >+ { 1402, 5, 1, 456, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1402 = VMULfq >+ { 1403, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1403 = VMULpd >+ { 1404, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1404 = VMULpq >+ { 1405, 6, 1, 458, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1405 = VMULslfd >+ { 1406, 6, 1, 459, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1406 = VMULslfq >+ { 1407, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1407 = VMULslv2i32 >+ { 1408, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1408 = VMULslv4i16 >+ { 1409, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1409 = VMULslv4i32 >+ { 1410, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1410 = VMULslv8i16 >+ { 1411, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1411 = VMULv16i8 >+ { 1412, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1412 = VMULv2i32 >+ { 1413, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1413 = VMULv4i16 >+ { 1414, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1414 = VMULv4i32 >+ { 1415, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1415 = VMULv8i16 >+ { 1416, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1416 = VMULv8i8 >+ { 1417, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1417 = VMVNd >+ { 1418, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1418 = VMVNq >+ { 1419, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1419 = VMVNv2i32 >+ { 1420, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #1420 = VMVNv4i16 >+ { 1421, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1421 = VMVNv4i32 >+ { 1422, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1422 = VMVNv8i16 >+ { 1423, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1423 = VNEGD >+ { 1424, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1424 = VNEGS >+ { 1425, 4, 1, 390, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1425 = VNEGf32q >+ { 1426, 4, 1, 391, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1426 = VNEGfd >+ { 1427, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1427 = VNEGs16d >+ { 1428, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1428 = VNEGs16q >+ { 1429, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1429 = VNEGs32d >+ { 1430, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1430 = VNEGs32q >+ { 1431, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1431 = VNEGs8d >+ { 1432, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1432 = VNEGs8q >+ { 1433, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1433 = VNMLAD >+ { 1434, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1434 = VNMLAS >+ { 1435, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #1435 = VNMLSD >+ { 1436, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #1436 = VNMLSS >+ { 1437, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1437 = VNMULD >+ { 1438, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1438 = VNMULS >+ { 1439, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1439 = VORNd >+ { 1440, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1440 = VORNq >+ { 1441, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1441 = VORRd >+ { 1442, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1442 = VORRiv2i32 >+ { 1443, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1443 = VORRiv4i16 >+ { 1444, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1444 = VORRiv4i32 >+ { 1445, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1445 = VORRiv8i16 >+ { 1446, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1446 = VORRq >+ { 1447, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1447 = VPADALsv16i8 >+ { 1448, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1448 = VPADALsv2i32 >+ { 1449, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1449 = VPADALsv4i16 >+ { 1450, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1450 = VPADALsv4i32 >+ { 1451, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1451 = VPADALsv8i16 >+ { 1452, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1452 = VPADALsv8i8 >+ { 1453, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1453 = VPADALuv16i8 >+ { 1454, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1454 = VPADALuv2i32 >+ { 1455, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1455 = VPADALuv4i16 >+ { 1456, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1456 = VPADALuv4i32 >+ { 1457, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1457 = VPADALuv8i16 >+ { 1458, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1458 = VPADALuv8i8 >+ { 1459, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1459 = VPADDLsv16i8 >+ { 1460, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1460 = VPADDLsv2i32 >+ { 1461, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1461 = VPADDLsv4i16 >+ { 1462, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1462 = VPADDLsv4i32 >+ { 1463, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1463 = VPADDLsv8i16 >+ { 1464, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1464 = VPADDLsv8i8 >+ { 1465, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1465 = VPADDLuv16i8 >+ { 1466, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1466 = VPADDLuv2i32 >+ { 1467, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1467 = VPADDLuv4i16 >+ { 1468, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1468 = VPADDLuv4i32 >+ { 1469, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1469 = VPADDLuv8i16 >+ { 1470, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1470 = VPADDLuv8i8 >+ { 1471, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1471 = VPADDf >+ { 1472, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1472 = VPADDi16 >+ { 1473, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1473 = VPADDi32 >+ { 1474, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1474 = VPADDi8 >+ { 1475, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1475 = VPMAXf >+ { 1476, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1476 = VPMAXs16 >+ { 1477, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1477 = VPMAXs32 >+ { 1478, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1478 = VPMAXs8 >+ { 1479, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1479 = VPMAXu16 >+ { 1480, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1480 = VPMAXu32 >+ { 1481, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1481 = VPMAXu8 >+ { 1482, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1482 = VPMINf >+ { 1483, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1483 = VPMINs16 >+ { 1484, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1484 = VPMINs32 >+ { 1485, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1485 = VPMINs8 >+ { 1486, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1486 = VPMINu16 >+ { 1487, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1487 = VPMINu32 >+ { 1488, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1488 = VPMINu8 >+ { 1489, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1489 = VQABSv16i8 >+ { 1490, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1490 = VQABSv2i32 >+ { 1491, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1491 = VQABSv4i16 >+ { 1492, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1492 = VQABSv4i32 >+ { 1493, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1493 = VQABSv8i16 >+ { 1494, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1494 = VQABSv8i8 >+ { 1495, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1495 = VQADDsv16i8 >+ { 1496, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1496 = VQADDsv1i64 >+ { 1497, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1497 = VQADDsv2i32 >+ { 1498, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1498 = VQADDsv2i64 >+ { 1499, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1499 = VQADDsv4i16 >+ { 1500, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1500 = VQADDsv4i32 >+ { 1501, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1501 = VQADDsv8i16 >+ { 1502, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1502 = VQADDsv8i8 >+ { 1503, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1503 = VQADDuv16i8 >+ { 1504, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1504 = VQADDuv1i64 >+ { 1505, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1505 = VQADDuv2i32 >+ { 1506, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1506 = VQADDuv2i64 >+ { 1507, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1507 = VQADDuv4i16 >+ { 1508, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1508 = VQADDuv4i32 >+ { 1509, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1509 = VQADDuv8i16 >+ { 1510, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1510 = VQADDuv8i8 >+ { 1511, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1511 = VQDMLALslv2i32 >+ { 1512, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1512 = VQDMLALslv4i16 >+ { 1513, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1513 = VQDMLALv2i64 >+ { 1514, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1514 = VQDMLALv4i32 >+ { 1515, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1515 = VQDMLSLslv2i32 >+ { 1516, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1516 = VQDMLSLslv4i16 >+ { 1517, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1517 = VQDMLSLv2i64 >+ { 1518, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #1518 = VQDMLSLv4i32 >+ { 1519, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1519 = VQDMULHslv2i32 >+ { 1520, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1520 = VQDMULHslv4i16 >+ { 1521, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1521 = VQDMULHslv4i32 >+ { 1522, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1522 = VQDMULHslv8i16 >+ { 1523, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1523 = VQDMULHv2i32 >+ { 1524, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1524 = VQDMULHv4i16 >+ { 1525, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1525 = VQDMULHv4i32 >+ { 1526, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1526 = VQDMULHv8i16 >+ { 1527, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1527 = VQDMULLslv2i32 >+ { 1528, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1528 = VQDMULLslv4i16 >+ { 1529, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1529 = VQDMULLv2i64 >+ { 1530, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1530 = VQDMULLv4i32 >+ { 1531, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1531 = VQMOVNsuv2i32 >+ { 1532, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1532 = VQMOVNsuv4i16 >+ { 1533, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1533 = VQMOVNsuv8i8 >+ { 1534, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1534 = VQMOVNsv2i32 >+ { 1535, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1535 = VQMOVNsv4i16 >+ { 1536, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1536 = VQMOVNsv8i8 >+ { 1537, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1537 = VQMOVNuv2i32 >+ { 1538, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1538 = VQMOVNuv4i16 >+ { 1539, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #1539 = VQMOVNuv8i8 >+ { 1540, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1540 = VQNEGv16i8 >+ { 1541, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1541 = VQNEGv2i32 >+ { 1542, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1542 = VQNEGv4i16 >+ { 1543, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1543 = VQNEGv4i32 >+ { 1544, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1544 = VQNEGv8i16 >+ { 1545, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1545 = VQNEGv8i8 >+ { 1546, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1546 = VQRDMULHslv2i32 >+ { 1547, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1547 = VQRDMULHslv4i16 >+ { 1548, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1548 = VQRDMULHslv4i32 >+ { 1549, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1549 = VQRDMULHslv8i16 >+ { 1550, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1550 = VQRDMULHv2i32 >+ { 1551, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1551 = VQRDMULHv4i16 >+ { 1552, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1552 = VQRDMULHv4i32 >+ { 1553, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1553 = VQRDMULHv8i16 >+ { 1554, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1554 = VQRSHLsv16i8 >+ { 1555, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1555 = VQRSHLsv1i64 >+ { 1556, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1556 = VQRSHLsv2i32 >+ { 1557, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1557 = VQRSHLsv2i64 >+ { 1558, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1558 = VQRSHLsv4i16 >+ { 1559, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1559 = VQRSHLsv4i32 >+ { 1560, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1560 = VQRSHLsv8i16 >+ { 1561, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1561 = VQRSHLsv8i8 >+ { 1562, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1562 = VQRSHLuv16i8 >+ { 1563, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1563 = VQRSHLuv1i64 >+ { 1564, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1564 = VQRSHLuv2i32 >+ { 1565, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1565 = VQRSHLuv2i64 >+ { 1566, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1566 = VQRSHLuv4i16 >+ { 1567, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1567 = VQRSHLuv4i32 >+ { 1568, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1568 = VQRSHLuv8i16 >+ { 1569, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1569 = VQRSHLuv8i8 >+ { 1570, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1570 = VQRSHRNsv2i32 >+ { 1571, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1571 = VQRSHRNsv4i16 >+ { 1572, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1572 = VQRSHRNsv8i8 >+ { 1573, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1573 = VQRSHRNuv2i32 >+ { 1574, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1574 = VQRSHRNuv4i16 >+ { 1575, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1575 = VQRSHRNuv8i8 >+ { 1576, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1576 = VQRSHRUNv2i32 >+ { 1577, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1577 = VQRSHRUNv4i16 >+ { 1578, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1578 = VQRSHRUNv8i8 >+ { 1579, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1579 = VQSHLsiv16i8 >+ { 1580, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1580 = VQSHLsiv1i64 >+ { 1581, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1581 = VQSHLsiv2i32 >+ { 1582, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1582 = VQSHLsiv2i64 >+ { 1583, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1583 = VQSHLsiv4i16 >+ { 1584, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1584 = VQSHLsiv4i32 >+ { 1585, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1585 = VQSHLsiv8i16 >+ { 1586, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1586 = VQSHLsiv8i8 >+ { 1587, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1587 = VQSHLsuv16i8 >+ { 1588, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1588 = VQSHLsuv1i64 >+ { 1589, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1589 = VQSHLsuv2i32 >+ { 1590, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1590 = VQSHLsuv2i64 >+ { 1591, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1591 = VQSHLsuv4i16 >+ { 1592, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1592 = VQSHLsuv4i32 >+ { 1593, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1593 = VQSHLsuv8i16 >+ { 1594, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1594 = VQSHLsuv8i8 >+ { 1595, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1595 = VQSHLsv16i8 >+ { 1596, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1596 = VQSHLsv1i64 >+ { 1597, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1597 = VQSHLsv2i32 >+ { 1598, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1598 = VQSHLsv2i64 >+ { 1599, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1599 = VQSHLsv4i16 >+ { 1600, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1600 = VQSHLsv4i32 >+ { 1601, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1601 = VQSHLsv8i16 >+ { 1602, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1602 = VQSHLsv8i8 >+ { 1603, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1603 = VQSHLuiv16i8 >+ { 1604, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1604 = VQSHLuiv1i64 >+ { 1605, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1605 = VQSHLuiv2i32 >+ { 1606, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1606 = VQSHLuiv2i64 >+ { 1607, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1607 = VQSHLuiv4i16 >+ { 1608, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1608 = VQSHLuiv4i32 >+ { 1609, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1609 = VQSHLuiv8i16 >+ { 1610, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1610 = VQSHLuiv8i8 >+ { 1611, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1611 = VQSHLuv16i8 >+ { 1612, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1612 = VQSHLuv1i64 >+ { 1613, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1613 = VQSHLuv2i32 >+ { 1614, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1614 = VQSHLuv2i64 >+ { 1615, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1615 = VQSHLuv4i16 >+ { 1616, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1616 = VQSHLuv4i32 >+ { 1617, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1617 = VQSHLuv8i16 >+ { 1618, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1618 = VQSHLuv8i8 >+ { 1619, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1619 = VQSHRNsv2i32 >+ { 1620, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1620 = VQSHRNsv4i16 >+ { 1621, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1621 = VQSHRNsv8i8 >+ { 1622, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1622 = VQSHRNuv2i32 >+ { 1623, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1623 = VQSHRNuv4i16 >+ { 1624, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1624 = VQSHRNuv8i8 >+ { 1625, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1625 = VQSHRUNv2i32 >+ { 1626, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1626 = VQSHRUNv4i16 >+ { 1627, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1627 = VQSHRUNv8i8 >+ { 1628, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1628 = VQSUBsv16i8 >+ { 1629, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1629 = VQSUBsv1i64 >+ { 1630, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1630 = VQSUBsv2i32 >+ { 1631, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1631 = VQSUBsv2i64 >+ { 1632, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1632 = VQSUBsv4i16 >+ { 1633, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1633 = VQSUBsv4i32 >+ { 1634, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1634 = VQSUBsv8i16 >+ { 1635, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1635 = VQSUBsv8i8 >+ { 1636, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1636 = VQSUBuv16i8 >+ { 1637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1637 = VQSUBuv1i64 >+ { 1638, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1638 = VQSUBuv2i32 >+ { 1639, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1639 = VQSUBuv2i64 >+ { 1640, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1640 = VQSUBuv4i16 >+ { 1641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1641 = VQSUBuv4i32 >+ { 1642, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1642 = VQSUBuv8i16 >+ { 1643, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1643 = VQSUBuv8i8 >+ { 1644, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1644 = VRADDHNv2i32 >+ { 1645, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1645 = VRADDHNv4i16 >+ { 1646, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1646 = VRADDHNv8i8 >+ { 1647, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1647 = VRECPEd >+ { 1648, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1648 = VRECPEfd >+ { 1649, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1649 = VRECPEfq >+ { 1650, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1650 = VRECPEq >+ { 1651, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1651 = VRECPSfd >+ { 1652, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1652 = VRECPSfq >+ { 1653, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1653 = VREV16d8 >+ { 1654, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1654 = VREV16q8 >+ { 1655, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1655 = VREV32d16 >+ { 1656, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1656 = VREV32d8 >+ { 1657, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1657 = VREV32q16 >+ { 1658, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1658 = VREV32q8 >+ { 1659, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1659 = VREV64d16 >+ { 1660, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1660 = VREV64d32 >+ { 1661, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1661 = VREV64d8 >+ { 1662, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1662 = VREV64q16 >+ { 1663, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1663 = VREV64q32 >+ { 1664, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1664 = VREV64q8 >+ { 1665, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1665 = VRHADDsv16i8 >+ { 1666, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1666 = VRHADDsv2i32 >+ { 1667, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1667 = VRHADDsv4i16 >+ { 1668, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1668 = VRHADDsv4i32 >+ { 1669, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1669 = VRHADDsv8i16 >+ { 1670, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1670 = VRHADDsv8i8 >+ { 1671, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1671 = VRHADDuv16i8 >+ { 1672, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1672 = VRHADDuv2i32 >+ { 1673, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1673 = VRHADDuv4i16 >+ { 1674, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1674 = VRHADDuv4i32 >+ { 1675, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1675 = VRHADDuv8i16 >+ { 1676, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1676 = VRHADDuv8i8 >+ { 1677, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1677 = VRINTAD >+ { 1678, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1678 = VRINTAND >+ { 1679, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1679 = VRINTANQ >+ { 1680, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1680 = VRINTAS >+ { 1681, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1681 = VRINTMD >+ { 1682, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1682 = VRINTMND >+ { 1683, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1683 = VRINTMNQ >+ { 1684, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1684 = VRINTMS >+ { 1685, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1685 = VRINTND >+ { 1686, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1686 = VRINTNND >+ { 1687, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1687 = VRINTNNQ >+ { 1688, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1688 = VRINTNS >+ { 1689, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1689 = VRINTPD >+ { 1690, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1690 = VRINTPND >+ { 1691, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1691 = VRINTPNQ >+ { 1692, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo141,0,nullptr }, // Inst #1692 = VRINTPS >+ { 1693, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1693 = VRINTRD >+ { 1694, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1694 = VRINTRS >+ { 1695, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1695 = VRINTXD >+ { 1696, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1696 = VRINTXND >+ { 1697, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1697 = VRINTXNQ >+ { 1698, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1698 = VRINTXS >+ { 1699, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1699 = VRINTZD >+ { 1700, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1700 = VRINTZND >+ { 1701, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #1701 = VRINTZNQ >+ { 1702, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1702 = VRINTZS >+ { 1703, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1703 = VRSHLsv16i8 >+ { 1704, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1704 = VRSHLsv1i64 >+ { 1705, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1705 = VRSHLsv2i32 >+ { 1706, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1706 = VRSHLsv2i64 >+ { 1707, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1707 = VRSHLsv4i16 >+ { 1708, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1708 = VRSHLsv4i32 >+ { 1709, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1709 = VRSHLsv8i16 >+ { 1710, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1710 = VRSHLsv8i8 >+ { 1711, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1711 = VRSHLuv16i8 >+ { 1712, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1712 = VRSHLuv1i64 >+ { 1713, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1713 = VRSHLuv2i32 >+ { 1714, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1714 = VRSHLuv2i64 >+ { 1715, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1715 = VRSHLuv4i16 >+ { 1716, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1716 = VRSHLuv4i32 >+ { 1717, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1717 = VRSHLuv8i16 >+ { 1718, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1718 = VRSHLuv8i8 >+ { 1719, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1719 = VRSHRNv2i32 >+ { 1720, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1720 = VRSHRNv4i16 >+ { 1721, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1721 = VRSHRNv8i8 >+ { 1722, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1722 = VRSHRsv16i8 >+ { 1723, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1723 = VRSHRsv1i64 >+ { 1724, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1724 = VRSHRsv2i32 >+ { 1725, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1725 = VRSHRsv2i64 >+ { 1726, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1726 = VRSHRsv4i16 >+ { 1727, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1727 = VRSHRsv4i32 >+ { 1728, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1728 = VRSHRsv8i16 >+ { 1729, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1729 = VRSHRsv8i8 >+ { 1730, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1730 = VRSHRuv16i8 >+ { 1731, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1731 = VRSHRuv1i64 >+ { 1732, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1732 = VRSHRuv2i32 >+ { 1733, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1733 = VRSHRuv2i64 >+ { 1734, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1734 = VRSHRuv4i16 >+ { 1735, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1735 = VRSHRuv4i32 >+ { 1736, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1736 = VRSHRuv8i16 >+ { 1737, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1737 = VRSHRuv8i8 >+ { 1738, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1738 = VRSQRTEd >+ { 1739, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1739 = VRSQRTEfd >+ { 1740, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1740 = VRSQRTEfq >+ { 1741, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1741 = VRSQRTEq >+ { 1742, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1742 = VRSQRTSfd >+ { 1743, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1743 = VRSQRTSfq >+ { 1744, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1744 = VRSRAsv16i8 >+ { 1745, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1745 = VRSRAsv1i64 >+ { 1746, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1746 = VRSRAsv2i32 >+ { 1747, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1747 = VRSRAsv2i64 >+ { 1748, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1748 = VRSRAsv4i16 >+ { 1749, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1749 = VRSRAsv4i32 >+ { 1750, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1750 = VRSRAsv8i16 >+ { 1751, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1751 = VRSRAsv8i8 >+ { 1752, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1752 = VRSRAuv16i8 >+ { 1753, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1753 = VRSRAuv1i64 >+ { 1754, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1754 = VRSRAuv2i32 >+ { 1755, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1755 = VRSRAuv2i64 >+ { 1756, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1756 = VRSRAuv4i16 >+ { 1757, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1757 = VRSRAuv4i32 >+ { 1758, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1758 = VRSRAuv8i16 >+ { 1759, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1759 = VRSRAuv8i8 >+ { 1760, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1760 = VRSUBHNv2i32 >+ { 1761, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1761 = VRSUBHNv4i16 >+ { 1762, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1762 = VRSUBHNv8i8 >+ { 1763, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1763 = VSELEQD >+ { 1764, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1764 = VSELEQS >+ { 1765, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1765 = VSELGED >+ { 1766, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1766 = VSELGES >+ { 1767, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1767 = VSELGTD >+ { 1768, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1768 = VSELGTS >+ { 1769, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo191,0,nullptr }, // Inst #1769 = VSELVSD >+ { 1770, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo193,0,nullptr }, // Inst #1770 = VSELVSS >+ { 1771, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1771 = VSETLNi16 >+ { 1772, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1772 = VSETLNi32 >+ { 1773, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1773 = VSETLNi8 >+ { 1774, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1774 = VSHLLi16 >+ { 1775, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1775 = VSHLLi32 >+ { 1776, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1776 = VSHLLi8 >+ { 1777, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1777 = VSHLLsv2i64 >+ { 1778, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1778 = VSHLLsv4i32 >+ { 1779, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1779 = VSHLLsv8i16 >+ { 1780, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1780 = VSHLLuv2i64 >+ { 1781, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1781 = VSHLLuv4i32 >+ { 1782, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1782 = VSHLLuv8i16 >+ { 1783, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1783 = VSHLiv16i8 >+ { 1784, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1784 = VSHLiv1i64 >+ { 1785, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1785 = VSHLiv2i32 >+ { 1786, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1786 = VSHLiv2i64 >+ { 1787, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1787 = VSHLiv4i16 >+ { 1788, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1788 = VSHLiv4i32 >+ { 1789, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1789 = VSHLiv8i16 >+ { 1790, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1790 = VSHLiv8i8 >+ { 1791, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1791 = VSHLsv16i8 >+ { 1792, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1792 = VSHLsv1i64 >+ { 1793, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1793 = VSHLsv2i32 >+ { 1794, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1794 = VSHLsv2i64 >+ { 1795, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1795 = VSHLsv4i16 >+ { 1796, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1796 = VSHLsv4i32 >+ { 1797, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1797 = VSHLsv8i16 >+ { 1798, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1798 = VSHLsv8i8 >+ { 1799, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1799 = VSHLuv16i8 >+ { 1800, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1800 = VSHLuv1i64 >+ { 1801, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1801 = VSHLuv2i32 >+ { 1802, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1802 = VSHLuv2i64 >+ { 1803, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1803 = VSHLuv4i16 >+ { 1804, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1804 = VSHLuv4i32 >+ { 1805, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1805 = VSHLuv8i16 >+ { 1806, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1806 = VSHLuv8i8 >+ { 1807, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1807 = VSHRNv2i32 >+ { 1808, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1808 = VSHRNv4i16 >+ { 1809, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1809 = VSHRNv8i8 >+ { 1810, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1810 = VSHRsv16i8 >+ { 1811, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1811 = VSHRsv1i64 >+ { 1812, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1812 = VSHRsv2i32 >+ { 1813, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1813 = VSHRsv2i64 >+ { 1814, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1814 = VSHRsv4i16 >+ { 1815, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1815 = VSHRsv4i32 >+ { 1816, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1816 = VSHRsv8i16 >+ { 1817, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1817 = VSHRsv8i8 >+ { 1818, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1818 = VSHRuv16i8 >+ { 1819, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1819 = VSHRuv1i64 >+ { 1820, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1820 = VSHRuv2i32 >+ { 1821, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1821 = VSHRuv2i64 >+ { 1822, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1822 = VSHRuv4i16 >+ { 1823, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1823 = VSHRuv4i32 >+ { 1824, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #1824 = VSHRuv8i16 >+ { 1825, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1825 = VSHRuv8i8 >+ { 1826, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1826 = VSHTOD >+ { 1827, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1827 = VSHTOS >+ { 1828, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1828 = VSITOD >+ { 1829, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1829 = VSITOS >+ { 1830, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1830 = VSLIv16i8 >+ { 1831, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1831 = VSLIv1i64 >+ { 1832, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1832 = VSLIv2i32 >+ { 1833, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1833 = VSLIv2i64 >+ { 1834, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1834 = VSLIv4i16 >+ { 1835, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1835 = VSLIv4i32 >+ { 1836, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1836 = VSLIv8i16 >+ { 1837, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1837 = VSLIv8i8 >+ { 1838, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1838 = VSLTOD >+ { 1839, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1839 = VSLTOS >+ { 1840, 4, 1, 589, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1840 = VSQRTD >+ { 1841, 4, 1, 587, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1841 = VSQRTS >+ { 1842, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1842 = VSRAsv16i8 >+ { 1843, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1843 = VSRAsv1i64 >+ { 1844, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1844 = VSRAsv2i32 >+ { 1845, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1845 = VSRAsv2i64 >+ { 1846, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1846 = VSRAsv4i16 >+ { 1847, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1847 = VSRAsv4i32 >+ { 1848, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1848 = VSRAsv8i16 >+ { 1849, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1849 = VSRAsv8i8 >+ { 1850, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1850 = VSRAuv16i8 >+ { 1851, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1851 = VSRAuv1i64 >+ { 1852, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1852 = VSRAuv2i32 >+ { 1853, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1853 = VSRAuv2i64 >+ { 1854, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1854 = VSRAuv4i16 >+ { 1855, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1855 = VSRAuv4i32 >+ { 1856, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1856 = VSRAuv8i16 >+ { 1857, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1857 = VSRAuv8i8 >+ { 1858, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1858 = VSRIv16i8 >+ { 1859, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1859 = VSRIv1i64 >+ { 1860, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1860 = VSRIv2i32 >+ { 1861, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1861 = VSRIv2i64 >+ { 1862, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1862 = VSRIv4i16 >+ { 1863, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1863 = VSRIv4i32 >+ { 1864, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1864 = VSRIv8i16 >+ { 1865, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1865 = VSRIv8i8 >+ { 1866, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1866 = VST1LNd16 >+ { 1867, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1867 = VST1LNd16_UPD >+ { 1868, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1868 = VST1LNd32 >+ { 1869, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1869 = VST1LNd32_UPD >+ { 1870, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1870 = VST1LNd8 >+ { 1871, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1871 = VST1LNd8_UPD >+ { 1872, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1872 = VST1LNdAsm_16 >+ { 1873, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1873 = VST1LNdAsm_32 >+ { 1874, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1874 = VST1LNdAsm_8 >+ { 1875, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1875 = VST1LNdWB_fixed_Asm_16 >+ { 1876, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1876 = VST1LNdWB_fixed_Asm_32 >+ { 1877, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1877 = VST1LNdWB_fixed_Asm_8 >+ { 1878, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1878 = VST1LNdWB_register_Asm_16 >+ { 1879, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1879 = VST1LNdWB_register_Asm_32 >+ { 1880, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1880 = VST1LNdWB_register_Asm_8 >+ { 1881, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1881 = VST1LNq16Pseudo >+ { 1882, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1882 = VST1LNq16Pseudo_UPD >+ { 1883, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1883 = VST1LNq32Pseudo >+ { 1884, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1884 = VST1LNq32Pseudo_UPD >+ { 1885, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1885 = VST1LNq8Pseudo >+ { 1886, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1886 = VST1LNq8Pseudo_UPD >+ { 1887, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1887 = VST1d16 >+ { 1888, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1888 = VST1d16Q >+ { 1889, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1889 = VST1d16Qwb_fixed >+ { 1890, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1890 = VST1d16Qwb_register >+ { 1891, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1891 = VST1d16T >+ { 1892, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1892 = VST1d16Twb_fixed >+ { 1893, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1893 = VST1d16Twb_register >+ { 1894, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1894 = VST1d16wb_fixed >+ { 1895, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1895 = VST1d16wb_register >+ { 1896, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1896 = VST1d32 >+ { 1897, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1897 = VST1d32Q >+ { 1898, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1898 = VST1d32Qwb_fixed >+ { 1899, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1899 = VST1d32Qwb_register >+ { 1900, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1900 = VST1d32T >+ { 1901, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1901 = VST1d32Twb_fixed >+ { 1902, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1902 = VST1d32Twb_register >+ { 1903, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1903 = VST1d32wb_fixed >+ { 1904, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1904 = VST1d32wb_register >+ { 1905, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1905 = VST1d64 >+ { 1906, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1906 = VST1d64Q >+ { 1907, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1907 = VST1d64QPseudo >+ { 1908, 6, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1908 = VST1d64QPseudoWB_fixed >+ { 1909, 7, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1909 = VST1d64QPseudoWB_register >+ { 1910, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1910 = VST1d64Qwb_fixed >+ { 1911, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1911 = VST1d64Qwb_register >+ { 1912, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1912 = VST1d64T >+ { 1913, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1913 = VST1d64TPseudo >+ { 1914, 6, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1914 = VST1d64TPseudoWB_fixed >+ { 1915, 7, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1915 = VST1d64TPseudoWB_register >+ { 1916, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1916 = VST1d64Twb_fixed >+ { 1917, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1917 = VST1d64Twb_register >+ { 1918, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1918 = VST1d64wb_fixed >+ { 1919, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1919 = VST1d64wb_register >+ { 1920, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1920 = VST1d8 >+ { 1921, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1921 = VST1d8Q >+ { 1922, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1922 = VST1d8Qwb_fixed >+ { 1923, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1923 = VST1d8Qwb_register >+ { 1924, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1924 = VST1d8T >+ { 1925, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1925 = VST1d8Twb_fixed >+ { 1926, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1926 = VST1d8Twb_register >+ { 1927, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1927 = VST1d8wb_fixed >+ { 1928, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1928 = VST1d8wb_register >+ { 1929, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1929 = VST1q16 >+ { 1930, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1930 = VST1q16wb_fixed >+ { 1931, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1931 = VST1q16wb_register >+ { 1932, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1932 = VST1q32 >+ { 1933, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1933 = VST1q32wb_fixed >+ { 1934, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1934 = VST1q32wb_register >+ { 1935, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1935 = VST1q64 >+ { 1936, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1936 = VST1q64wb_fixed >+ { 1937, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1937 = VST1q64wb_register >+ { 1938, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1938 = VST1q8 >+ { 1939, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1939 = VST1q8wb_fixed >+ { 1940, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1940 = VST1q8wb_register >+ { 1941, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1941 = VST2LNd16 >+ { 1942, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1942 = VST2LNd16Pseudo >+ { 1943, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1943 = VST2LNd16Pseudo_UPD >+ { 1944, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1944 = VST2LNd16_UPD >+ { 1945, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1945 = VST2LNd32 >+ { 1946, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1946 = VST2LNd32Pseudo >+ { 1947, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1947 = VST2LNd32Pseudo_UPD >+ { 1948, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1948 = VST2LNd32_UPD >+ { 1949, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1949 = VST2LNd8 >+ { 1950, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1950 = VST2LNd8Pseudo >+ { 1951, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1951 = VST2LNd8Pseudo_UPD >+ { 1952, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1952 = VST2LNd8_UPD >+ { 1953, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1953 = VST2LNdAsm_16 >+ { 1954, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1954 = VST2LNdAsm_32 >+ { 1955, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1955 = VST2LNdAsm_8 >+ { 1956, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1956 = VST2LNdWB_fixed_Asm_16 >+ { 1957, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1957 = VST2LNdWB_fixed_Asm_32 >+ { 1958, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1958 = VST2LNdWB_fixed_Asm_8 >+ { 1959, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1959 = VST2LNdWB_register_Asm_16 >+ { 1960, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1960 = VST2LNdWB_register_Asm_32 >+ { 1961, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1961 = VST2LNdWB_register_Asm_8 >+ { 1962, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1962 = VST2LNq16 >+ { 1963, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1963 = VST2LNq16Pseudo >+ { 1964, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1964 = VST2LNq16Pseudo_UPD >+ { 1965, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1965 = VST2LNq16_UPD >+ { 1966, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1966 = VST2LNq32 >+ { 1967, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1967 = VST2LNq32Pseudo >+ { 1968, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1968 = VST2LNq32Pseudo_UPD >+ { 1969, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1969 = VST2LNq32_UPD >+ { 1970, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1970 = VST2LNqAsm_16 >+ { 1971, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1971 = VST2LNqAsm_32 >+ { 1972, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1972 = VST2LNqWB_fixed_Asm_16 >+ { 1973, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1973 = VST2LNqWB_fixed_Asm_32 >+ { 1974, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1974 = VST2LNqWB_register_Asm_16 >+ { 1975, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1975 = VST2LNqWB_register_Asm_32 >+ { 1976, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1976 = VST2b16 >+ { 1977, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1977 = VST2b16wb_fixed >+ { 1978, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1978 = VST2b16wb_register >+ { 1979, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1979 = VST2b32 >+ { 1980, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1980 = VST2b32wb_fixed >+ { 1981, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1981 = VST2b32wb_register >+ { 1982, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1982 = VST2b8 >+ { 1983, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1983 = VST2b8wb_fixed >+ { 1984, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1984 = VST2b8wb_register >+ { 1985, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1985 = VST2d16 >+ { 1986, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1986 = VST2d16wb_fixed >+ { 1987, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1987 = VST2d16wb_register >+ { 1988, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1988 = VST2d32 >+ { 1989, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1989 = VST2d32wb_fixed >+ { 1990, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1990 = VST2d32wb_register >+ { 1991, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1991 = VST2d8 >+ { 1992, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1992 = VST2d8wb_fixed >+ { 1993, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1993 = VST2d8wb_register >+ { 1994, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1994 = VST2q16 >+ { 1995, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1995 = VST2q16Pseudo >+ { 1996, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1996 = VST2q16PseudoWB_fixed >+ { 1997, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1997 = VST2q16PseudoWB_register >+ { 1998, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1998 = VST2q16wb_fixed >+ { 1999, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1999 = VST2q16wb_register >+ { 2000, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #2000 = VST2q32 >+ { 2001, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2001 = VST2q32Pseudo >+ { 2002, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2002 = VST2q32PseudoWB_fixed >+ { 2003, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #2003 = VST2q32PseudoWB_register >+ { 2004, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #2004 = VST2q32wb_fixed >+ { 2005, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #2005 = VST2q32wb_register >+ { 2006, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #2006 = VST2q8 >+ { 2007, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2007 = VST2q8Pseudo >+ { 2008, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2008 = VST2q8PseudoWB_fixed >+ { 2009, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #2009 = VST2q8PseudoWB_register >+ { 2010, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #2010 = VST2q8wb_fixed >+ { 2011, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #2011 = VST2q8wb_register >+ { 2012, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2012 = VST3LNd16 >+ { 2013, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2013 = VST3LNd16Pseudo >+ { 2014, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2014 = VST3LNd16Pseudo_UPD >+ { 2015, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2015 = VST3LNd16_UPD >+ { 2016, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2016 = VST3LNd32 >+ { 2017, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2017 = VST3LNd32Pseudo >+ { 2018, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2018 = VST3LNd32Pseudo_UPD >+ { 2019, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2019 = VST3LNd32_UPD >+ { 2020, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2020 = VST3LNd8 >+ { 2021, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2021 = VST3LNd8Pseudo >+ { 2022, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2022 = VST3LNd8Pseudo_UPD >+ { 2023, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2023 = VST3LNd8_UPD >+ { 2024, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2024 = VST3LNdAsm_16 >+ { 2025, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2025 = VST3LNdAsm_32 >+ { 2026, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2026 = VST3LNdAsm_8 >+ { 2027, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2027 = VST3LNdWB_fixed_Asm_16 >+ { 2028, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2028 = VST3LNdWB_fixed_Asm_32 >+ { 2029, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2029 = VST3LNdWB_fixed_Asm_8 >+ { 2030, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2030 = VST3LNdWB_register_Asm_16 >+ { 2031, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2031 = VST3LNdWB_register_Asm_32 >+ { 2032, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2032 = VST3LNdWB_register_Asm_8 >+ { 2033, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2033 = VST3LNq16 >+ { 2034, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2034 = VST3LNq16Pseudo >+ { 2035, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2035 = VST3LNq16Pseudo_UPD >+ { 2036, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2036 = VST3LNq16_UPD >+ { 2037, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2037 = VST3LNq32 >+ { 2038, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2038 = VST3LNq32Pseudo >+ { 2039, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2039 = VST3LNq32Pseudo_UPD >+ { 2040, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2040 = VST3LNq32_UPD >+ { 2041, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2041 = VST3LNqAsm_16 >+ { 2042, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2042 = VST3LNqAsm_32 >+ { 2043, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2043 = VST3LNqWB_fixed_Asm_16 >+ { 2044, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2044 = VST3LNqWB_fixed_Asm_32 >+ { 2045, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2045 = VST3LNqWB_register_Asm_16 >+ { 2046, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2046 = VST3LNqWB_register_Asm_32 >+ { 2047, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2047 = VST3d16 >+ { 2048, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2048 = VST3d16Pseudo >+ { 2049, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2049 = VST3d16Pseudo_UPD >+ { 2050, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2050 = VST3d16_UPD >+ { 2051, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2051 = VST3d32 >+ { 2052, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2052 = VST3d32Pseudo >+ { 2053, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2053 = VST3d32Pseudo_UPD >+ { 2054, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2054 = VST3d32_UPD >+ { 2055, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2055 = VST3d8 >+ { 2056, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2056 = VST3d8Pseudo >+ { 2057, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2057 = VST3d8Pseudo_UPD >+ { 2058, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2058 = VST3d8_UPD >+ { 2059, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2059 = VST3dAsm_16 >+ { 2060, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2060 = VST3dAsm_32 >+ { 2061, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2061 = VST3dAsm_8 >+ { 2062, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2062 = VST3dWB_fixed_Asm_16 >+ { 2063, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2063 = VST3dWB_fixed_Asm_32 >+ { 2064, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2064 = VST3dWB_fixed_Asm_8 >+ { 2065, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2065 = VST3dWB_register_Asm_16 >+ { 2066, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2066 = VST3dWB_register_Asm_32 >+ { 2067, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2067 = VST3dWB_register_Asm_8 >+ { 2068, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2068 = VST3q16 >+ { 2069, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2069 = VST3q16Pseudo_UPD >+ { 2070, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2070 = VST3q16_UPD >+ { 2071, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2071 = VST3q16oddPseudo >+ { 2072, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2072 = VST3q16oddPseudo_UPD >+ { 2073, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2073 = VST3q32 >+ { 2074, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2074 = VST3q32Pseudo_UPD >+ { 2075, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2075 = VST3q32_UPD >+ { 2076, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2076 = VST3q32oddPseudo >+ { 2077, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2077 = VST3q32oddPseudo_UPD >+ { 2078, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2078 = VST3q8 >+ { 2079, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2079 = VST3q8Pseudo_UPD >+ { 2080, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2080 = VST3q8_UPD >+ { 2081, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2081 = VST3q8oddPseudo >+ { 2082, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2082 = VST3q8oddPseudo_UPD >+ { 2083, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2083 = VST3qAsm_16 >+ { 2084, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2084 = VST3qAsm_32 >+ { 2085, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2085 = VST3qAsm_8 >+ { 2086, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2086 = VST3qWB_fixed_Asm_16 >+ { 2087, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2087 = VST3qWB_fixed_Asm_32 >+ { 2088, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2088 = VST3qWB_fixed_Asm_8 >+ { 2089, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2089 = VST3qWB_register_Asm_16 >+ { 2090, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2090 = VST3qWB_register_Asm_32 >+ { 2091, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2091 = VST3qWB_register_Asm_8 >+ { 2092, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2092 = VST4LNd16 >+ { 2093, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2093 = VST4LNd16Pseudo >+ { 2094, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2094 = VST4LNd16Pseudo_UPD >+ { 2095, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2095 = VST4LNd16_UPD >+ { 2096, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2096 = VST4LNd32 >+ { 2097, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2097 = VST4LNd32Pseudo >+ { 2098, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2098 = VST4LNd32Pseudo_UPD >+ { 2099, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2099 = VST4LNd32_UPD >+ { 2100, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2100 = VST4LNd8 >+ { 2101, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2101 = VST4LNd8Pseudo >+ { 2102, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #2102 = VST4LNd8Pseudo_UPD >+ { 2103, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2103 = VST4LNd8_UPD >+ { 2104, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2104 = VST4LNdAsm_16 >+ { 2105, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2105 = VST4LNdAsm_32 >+ { 2106, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2106 = VST4LNdAsm_8 >+ { 2107, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2107 = VST4LNdWB_fixed_Asm_16 >+ { 2108, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2108 = VST4LNdWB_fixed_Asm_32 >+ { 2109, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2109 = VST4LNdWB_fixed_Asm_8 >+ { 2110, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2110 = VST4LNdWB_register_Asm_16 >+ { 2111, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2111 = VST4LNdWB_register_Asm_32 >+ { 2112, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2112 = VST4LNdWB_register_Asm_8 >+ { 2113, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2113 = VST4LNq16 >+ { 2114, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2114 = VST4LNq16Pseudo >+ { 2115, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2115 = VST4LNq16Pseudo_UPD >+ { 2116, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2116 = VST4LNq16_UPD >+ { 2117, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2117 = VST4LNq32 >+ { 2118, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2118 = VST4LNq32Pseudo >+ { 2119, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2119 = VST4LNq32Pseudo_UPD >+ { 2120, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2120 = VST4LNq32_UPD >+ { 2121, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2121 = VST4LNqAsm_16 >+ { 2122, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2122 = VST4LNqAsm_32 >+ { 2123, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2123 = VST4LNqWB_fixed_Asm_16 >+ { 2124, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #2124 = VST4LNqWB_fixed_Asm_32 >+ { 2125, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2125 = VST4LNqWB_register_Asm_16 >+ { 2126, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #2126 = VST4LNqWB_register_Asm_32 >+ { 2127, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2127 = VST4d16 >+ { 2128, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2128 = VST4d16Pseudo >+ { 2129, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2129 = VST4d16Pseudo_UPD >+ { 2130, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2130 = VST4d16_UPD >+ { 2131, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2131 = VST4d32 >+ { 2132, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2132 = VST4d32Pseudo >+ { 2133, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2133 = VST4d32Pseudo_UPD >+ { 2134, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2134 = VST4d32_UPD >+ { 2135, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2135 = VST4d8 >+ { 2136, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2136 = VST4d8Pseudo >+ { 2137, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2137 = VST4d8Pseudo_UPD >+ { 2138, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2138 = VST4d8_UPD >+ { 2139, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2139 = VST4dAsm_16 >+ { 2140, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2140 = VST4dAsm_32 >+ { 2141, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2141 = VST4dAsm_8 >+ { 2142, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2142 = VST4dWB_fixed_Asm_16 >+ { 2143, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2143 = VST4dWB_fixed_Asm_32 >+ { 2144, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2144 = VST4dWB_fixed_Asm_8 >+ { 2145, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2145 = VST4dWB_register_Asm_16 >+ { 2146, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2146 = VST4dWB_register_Asm_32 >+ { 2147, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2147 = VST4dWB_register_Asm_8 >+ { 2148, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2148 = VST4q16 >+ { 2149, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2149 = VST4q16Pseudo_UPD >+ { 2150, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2150 = VST4q16_UPD >+ { 2151, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2151 = VST4q16oddPseudo >+ { 2152, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2152 = VST4q16oddPseudo_UPD >+ { 2153, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2153 = VST4q32 >+ { 2154, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2154 = VST4q32Pseudo_UPD >+ { 2155, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2155 = VST4q32_UPD >+ { 2156, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2156 = VST4q32oddPseudo >+ { 2157, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2157 = VST4q32oddPseudo_UPD >+ { 2158, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2158 = VST4q8 >+ { 2159, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2159 = VST4q8Pseudo_UPD >+ { 2160, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2160 = VST4q8_UPD >+ { 2161, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2161 = VST4q8oddPseudo >+ { 2162, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2162 = VST4q8oddPseudo_UPD >+ { 2163, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2163 = VST4qAsm_16 >+ { 2164, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2164 = VST4qAsm_32 >+ { 2165, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2165 = VST4qAsm_8 >+ { 2166, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2166 = VST4qWB_fixed_Asm_16 >+ { 2167, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2167 = VST4qWB_fixed_Asm_32 >+ { 2168, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #2168 = VST4qWB_fixed_Asm_8 >+ { 2169, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2169 = VST4qWB_register_Asm_16 >+ { 2170, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2170 = VST4qWB_register_Asm_32 >+ { 2171, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #2171 = VST4qWB_register_Asm_8 >+ { 2172, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2172 = VSTMDDB_UPD >+ { 2173, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2173 = VSTMDIA >+ { 2174, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2174 = VSTMDIA_UPD >+ { 2175, 4, 0, 513, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #2175 = VSTMQIA >+ { 2176, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2176 = VSTMSDB_UPD >+ { 2177, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2177 = VSTMSIA >+ { 2178, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2178 = VSTMSIA_UPD >+ { 2179, 5, 0, 510, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #2179 = VSTRD >+ { 2180, 5, 0, 511, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #2180 = VSTRS >+ { 2181, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2181 = VSUBD >+ { 2182, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2182 = VSUBHNv2i32 >+ { 2183, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2183 = VSUBHNv4i16 >+ { 2184, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2184 = VSUBHNv8i8 >+ { 2185, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2185 = VSUBLsv2i64 >+ { 2186, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2186 = VSUBLsv4i32 >+ { 2187, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2187 = VSUBLsv8i16 >+ { 2188, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2188 = VSUBLuv2i64 >+ { 2189, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2189 = VSUBLuv4i32 >+ { 2190, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #2190 = VSUBLuv8i16 >+ { 2191, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #2191 = VSUBS >+ { 2192, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2192 = VSUBWsv2i64 >+ { 2193, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2193 = VSUBWsv4i32 >+ { 2194, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2194 = VSUBWsv8i16 >+ { 2195, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2195 = VSUBWuv2i64 >+ { 2196, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2196 = VSUBWuv4i32 >+ { 2197, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2197 = VSUBWuv8i16 >+ { 2198, 5, 1, 442, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2198 = VSUBfd >+ { 2199, 5, 1, 443, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2199 = VSUBfq >+ { 2200, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2200 = VSUBv16i8 >+ { 2201, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2201 = VSUBv1i64 >+ { 2202, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2202 = VSUBv2i32 >+ { 2203, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2203 = VSUBv2i64 >+ { 2204, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2204 = VSUBv4i16 >+ { 2205, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2205 = VSUBv4i32 >+ { 2206, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2206 = VSUBv8i16 >+ { 2207, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2207 = VSUBv8i8 >+ { 2208, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2208 = VSWPd >+ { 2209, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2209 = VSWPq >+ { 2210, 5, 1, 425, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2210 = VTBL1 >+ { 2211, 5, 1, 427, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2211 = VTBL2 >+ { 2212, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2212 = VTBL3 >+ { 2213, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2213 = VTBL3Pseudo >+ { 2214, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2214 = VTBL4 >+ { 2215, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2215 = VTBL4Pseudo >+ { 2216, 6, 1, 426, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2216 = VTBX1 >+ { 2217, 6, 1, 428, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2217 = VTBX2 >+ { 2218, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2218 = VTBX3 >+ { 2219, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2219 = VTBX3Pseudo >+ { 2220, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2220 = VTBX4 >+ { 2221, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2221 = VTBX4Pseudo >+ { 2222, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2222 = VTOSHD >+ { 2223, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2223 = VTOSHS >+ { 2224, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo142,0,nullptr }, // Inst #2224 = VTOSIRD >+ { 2225, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo130,0,nullptr }, // Inst #2225 = VTOSIRS >+ { 2226, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #2226 = VTOSIZD >+ { 2227, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2227 = VTOSIZS >+ { 2228, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2228 = VTOSLD >+ { 2229, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2229 = VTOSLS >+ { 2230, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2230 = VTOUHD >+ { 2231, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2231 = VTOUHS >+ { 2232, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo142,0,nullptr }, // Inst #2232 = VTOUIRD >+ { 2233, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, nullptr, OperandInfo130,0,nullptr }, // Inst #2233 = VTOUIRS >+ { 2234, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo142,0,nullptr }, // Inst #2234 = VTOUIZD >+ { 2235, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2235 = VTOUIZS >+ { 2236, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2236 = VTOULD >+ { 2237, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2237 = VTOULS >+ { 2238, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2238 = VTRNd16 >+ { 2239, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2239 = VTRNd32 >+ { 2240, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2240 = VTRNd8 >+ { 2241, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2241 = VTRNq16 >+ { 2242, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2242 = VTRNq32 >+ { 2243, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2243 = VTRNq8 >+ { 2244, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2244 = VTSTv16i8 >+ { 2245, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2245 = VTSTv2i32 >+ { 2246, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2246 = VTSTv4i16 >+ { 2247, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2247 = VTSTv4i32 >+ { 2248, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2248 = VTSTv8i16 >+ { 2249, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2249 = VTSTv8i8 >+ { 2250, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2250 = VUHTOD >+ { 2251, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2251 = VUHTOS >+ { 2252, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #2252 = VUITOD >+ { 2253, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2253 = VUITOS >+ { 2254, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #2254 = VULTOD >+ { 2255, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #2255 = VULTOS >+ { 2256, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2256 = VUZPd16 >+ { 2257, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2257 = VUZPd8 >+ { 2258, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2258 = VUZPq16 >+ { 2259, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2259 = VUZPq32 >+ { 2260, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2260 = VUZPq8 >+ { 2261, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2261 = VZIPd16 >+ { 2262, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2262 = VZIPd8 >+ { 2263, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2263 = VZIPq16 >+ { 2264, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2264 = VZIPq32 >+ { 2265, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2265 = VZIPq8 >+ { 2266, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, nullptr,0,nullptr }, // Inst #2266 = WIN__CHKSTK >+ { 2267, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2267 = sysLDMDA >+ { 2268, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2268 = sysLDMDA_UPD >+ { 2269, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2269 = sysLDMDB >+ { 2270, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2270 = sysLDMDB_UPD >+ { 2271, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2271 = sysLDMIA >+ { 2272, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2272 = sysLDMIA_UPD >+ { 2273, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2273 = sysLDMIB >+ { 2274, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2274 = sysLDMIB_UPD >+ { 2275, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2275 = sysSTMDA >+ { 2276, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2276 = sysSTMDA_UPD >+ { 2277, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2277 = sysSTMDB >+ { 2278, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2278 = sysSTMDB_UPD >+ { 2279, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2279 = sysSTMIA >+ { 2280, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2280 = sysSTMIA_UPD >+ { 2281, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2281 = sysSTMIB >+ { 2282, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2282 = sysSTMIB_UPD >+ { 2283, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo267,0,nullptr }, // Inst #2283 = t2ABS >+ { 2284, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2284 = t2ADCri >+ { 2285, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2285 = t2ADCrr >+ { 2286, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2286 = t2ADCrs >+ { 2287, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2287 = t2ADDSri >+ { 2288, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2288 = t2ADDSrr >+ { 2289, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2289 = t2ADDSrs >+ { 2290, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2290 = t2ADDri >+ { 2291, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2291 = t2ADDri12 >+ { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2292 = t2ADDrr >+ { 2293, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2293 = t2ADDrs >+ { 2294, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2294 = t2ADR >+ { 2295, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2295 = t2ANDri >+ { 2296, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2296 = t2ANDrr >+ { 2297, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2297 = t2ANDrs >+ { 2298, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2298 = t2ASRri >+ { 2299, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2299 = t2ASRrr >+ { 2300, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2300 = t2B >+ { 2301, 5, 1, 297, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2301 = t2BFC >+ { 2302, 6, 1, 298, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2302 = t2BFI >+ { 2303, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2303 = t2BICri >+ { 2304, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2304 = t2BICrr >+ { 2305, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2305 = t2BICrs >+ { 2306, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo36,0,nullptr }, // Inst #2306 = t2BR_JT >+ { 2307, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo281,0,nullptr }, // Inst #2307 = t2BXJ >+ { 2308, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2308 = t2Bcc >+ { 2309, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2309 = t2CDP >+ { 2310, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2310 = t2CDP2 >+ { 2311, 2, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2311 = t2CLREX >+ { 2312, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2312 = t2CLZ >+ { 2313, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2313 = t2CMNri >+ { 2314, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2314 = t2CMNzrr >+ { 2315, 5, 0, 240, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2315 = t2CMNzrs >+ { 2316, 4, 0, 241, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2316 = t2CMPri >+ { 2317, 4, 0, 242, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2317 = t2CMPrr >+ { 2318, 5, 0, 243, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2318 = t2CMPrs >+ { 2319, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2319 = t2CPS1p >+ { 2320, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2320 = t2CPS2p >+ { 2321, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #2321 = t2CPS3p >+ { 2322, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2322 = t2CRC32B >+ { 2323, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2323 = t2CRC32CB >+ { 2324, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2324 = t2CRC32CH >+ { 2325, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2325 = t2CRC32CW >+ { 2326, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2326 = t2CRC32H >+ { 2327, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2327 = t2CRC32W >+ { 2328, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2328 = t2DBG >+ { 2329, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2329 = t2DCPS1 >+ { 2330, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2330 = t2DCPS2 >+ { 2331, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2331 = t2DCPS3 >+ { 2332, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2332 = t2DMB >+ { 2333, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2333 = t2DSB >+ { 2334, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2334 = t2EORri >+ { 2335, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2335 = t2EORrr >+ { 2336, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2336 = t2EORrs >+ { 2337, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2337 = t2HINT >+ { 2338, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2338 = t2ISB >+ { 2339, 2, 0, 378, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList12, OperandInfo7,0,0 }, // Inst #2339 = t2IT >+ { 2340, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo287,0,nullptr }, // Inst #2340 = t2Int_eh_sjlj_setjmp >+ { 2341, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList7, OperandInfo287,0,nullptr }, // Inst #2341 = t2Int_eh_sjlj_setjmp_nofp >+ { 2342, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2342 = t2LDA >+ { 2343, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2343 = t2LDAB >+ { 2344, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2344 = t2LDAEX >+ { 2345, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2345 = t2LDAEXB >+ { 2346, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2346 = t2LDAEXD >+ { 2347, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2347 = t2LDAEXH >+ { 2348, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2348 = t2LDAH >+ { 2349, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2349 = t2LDC2L_OFFSET >+ { 2350, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2350 = t2LDC2L_OPTION >+ { 2351, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2351 = t2LDC2L_POST >+ { 2352, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2352 = t2LDC2L_PRE >+ { 2353, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2353 = t2LDC2_OFFSET >+ { 2354, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2354 = t2LDC2_OPTION >+ { 2355, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2355 = t2LDC2_POST >+ { 2356, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2356 = t2LDC2_PRE >+ { 2357, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2357 = t2LDCL_OFFSET >+ { 2358, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2358 = t2LDCL_OPTION >+ { 2359, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2359 = t2LDCL_POST >+ { 2360, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2360 = t2LDCL_PRE >+ { 2361, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2361 = t2LDC_OFFSET >+ { 2362, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2362 = t2LDC_OPTION >+ { 2363, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2363 = t2LDC_POST >+ { 2364, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2364 = t2LDC_PRE >+ { 2365, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2365 = t2LDMDB >+ { 2366, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2366 = t2LDMDB_UPD >+ { 2367, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2367 = t2LDMIA >+ { 2368, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2368 = t2LDMIA_RET >+ { 2369, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2369 = t2LDMIA_UPD >+ { 2370, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2370 = t2LDRBT >+ { 2371, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2371 = t2LDRB_POST >+ { 2372, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2372 = t2LDRB_PRE >+ { 2373, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2373 = t2LDRBi12 >+ { 2374, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2374 = t2LDRBi8 >+ { 2375, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2375 = t2LDRBpci >+ { 2376, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2376 = t2LDRBpcrel >+ { 2377, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2377 = t2LDRBs >+ { 2378, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2378 = t2LDRD_POST >+ { 2379, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2379 = t2LDRD_PRE >+ { 2380, 6, 2, 351, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2380 = t2LDRDi8 >+ { 2381, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo294,0,nullptr }, // Inst #2381 = t2LDREX >+ { 2382, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2382 = t2LDREXB >+ { 2383, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2383 = t2LDREXD >+ { 2384, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2384 = t2LDREXH >+ { 2385, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2385 = t2LDRHT >+ { 2386, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2386 = t2LDRH_POST >+ { 2387, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2387 = t2LDRH_PRE >+ { 2388, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2388 = t2LDRHi12 >+ { 2389, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2389 = t2LDRHi8 >+ { 2390, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2390 = t2LDRHpci >+ { 2391, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2391 = t2LDRHpcrel >+ { 2392, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2392 = t2LDRHs >+ { 2393, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2393 = t2LDRSBT >+ { 2394, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2394 = t2LDRSB_POST >+ { 2395, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2395 = t2LDRSB_PRE >+ { 2396, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2396 = t2LDRSBi12 >+ { 2397, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2397 = t2LDRSBi8 >+ { 2398, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2398 = t2LDRSBpci >+ { 2399, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2399 = t2LDRSBpcrel >+ { 2400, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2400 = t2LDRSBs >+ { 2401, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2401 = t2LDRSHT >+ { 2402, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2402 = t2LDRSH_POST >+ { 2403, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2403 = t2LDRSH_PRE >+ { 2404, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2404 = t2LDRSHi12 >+ { 2405, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2405 = t2LDRSHi8 >+ { 2406, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2406 = t2LDRSHpci >+ { 2407, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2407 = t2LDRSHpcrel >+ { 2408, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2408 = t2LDRSHs >+ { 2409, 5, 1, 347, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2409 = t2LDRT >+ { 2410, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2410 = t2LDR_POST >+ { 2411, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #2411 = t2LDR_PRE >+ { 2412, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2412 = t2LDRi12 >+ { 2413, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2413 = t2LDRi8 >+ { 2414, 4, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2414 = t2LDRpci >+ { 2415, 3, 1, 331, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2415 = t2LDRpci_pic >+ { 2416, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23,0,nullptr }, // Inst #2416 = t2LDRpcrel >+ { 2417, 6, 1, 332, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2417 = t2LDRs >+ { 2418, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2418 = t2LEApcrel >+ { 2419, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo297,0,nullptr }, // Inst #2419 = t2LEApcrelJT >+ { 2420, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2420 = t2LSLri >+ { 2421, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2421 = t2LSLrr >+ { 2422, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2422 = t2LSRri >+ { 2423, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2423 = t2LSRrr >+ { 2424, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo69,0,0 }, // Inst #2424 = t2MCR >+ { 2425, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo69,0,nullptr }, // Inst #2425 = t2MCR2 >+ { 2426, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2426 = t2MCRR >+ { 2427, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2427 = t2MCRR2 >+ { 2428, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2428 = t2MLA >+ { 2429, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2429 = t2MLS >+ { 2430, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2430 = t2MOVCCasr >+ { 2431, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2431 = t2MOVCCi >+ { 2432, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2432 = t2MOVCCi16 >+ { 2433, 5, 1, 292, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2433 = t2MOVCCi32imm >+ { 2434, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2434 = t2MOVCClsl >+ { 2435, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2435 = t2MOVCClsr >+ { 2436, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo302,0,nullptr }, // Inst #2436 = t2MOVCCr >+ { 2437, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2437 = t2MOVCCror >+ { 2438, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2438 = t2MOVSsi >+ { 2439, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2439 = t2MOVSsr >+ { 2440, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2440 = t2MOVTi16 >+ { 2441, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2441 = t2MOVTi16_ga_pcrel >+ { 2442, 2, 1, 294, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2442 = t2MOV_ga_pcrel >+ { 2443, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2443 = t2MOVi >+ { 2444, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2444 = t2MOVi16 >+ { 2445, 3, 1, 295, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2445 = t2MOVi16_ga_pcrel >+ { 2446, 2, 1, 293, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2446 = t2MOVi32imm >+ { 2447, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2447 = t2MOVr >+ { 2448, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2448 = t2MOVsi >+ { 2449, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2449 = t2MOVsr >+ { 2450, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo282,0,nullptr }, // Inst #2450 = t2MOVsra_flag >+ { 2451, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo282,0,nullptr }, // Inst #2451 = t2MOVsrl_flag >+ { 2452, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #2452 = t2MRC >+ { 2453, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #2453 = t2MRC2 >+ { 2454, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2454 = t2MRRC >+ { 2455, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2455 = t2MRRC2 >+ { 2456, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2456 = t2MRS_AR >+ { 2457, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2457 = t2MRS_M >+ { 2458, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2458 = t2MRSsys_AR >+ { 2459, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2459 = t2MSR_AR >+ { 2460, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2460 = t2MSR_M >+ { 2461, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2461 = t2MUL >+ { 2462, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2462 = t2MVNCCi >+ { 2463, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2463 = t2MVNi >+ { 2464, 5, 1, 53, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2464 = t2MVNr >+ { 2465, 6, 1, 249, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312,0,nullptr }, // Inst #2465 = t2MVNs >+ { 2466, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2466 = t2ORNri >+ { 2467, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2467 = t2ORNrr >+ { 2468, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2468 = t2ORNrs >+ { 2469, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2469 = t2ORRri >+ { 2470, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2470 = t2ORRrr >+ { 2471, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2471 = t2ORRrs >+ { 2472, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2472 = t2PKHBT >+ { 2473, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2473 = t2PKHTB >+ { 2474, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2474 = t2PLDWi12 >+ { 2475, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2475 = t2PLDWi8 >+ { 2476, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2476 = t2PLDWs >+ { 2477, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2477 = t2PLDi12 >+ { 2478, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2478 = t2PLDi8 >+ { 2479, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2479 = t2PLDpci >+ { 2480, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2480 = t2PLDs >+ { 2481, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2481 = t2PLIi12 >+ { 2482, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2482 = t2PLIi8 >+ { 2483, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2483 = t2PLIpci >+ { 2484, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2484 = t2PLIs >+ { 2485, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2485 = t2QADD >+ { 2486, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2486 = t2QADD16 >+ { 2487, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2487 = t2QADD8 >+ { 2488, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2488 = t2QASX >+ { 2489, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2489 = t2QDADD >+ { 2490, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2490 = t2QDSUB >+ { 2491, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2491 = t2QSAX >+ { 2492, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2492 = t2QSUB >+ { 2493, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2493 = t2QSUB16 >+ { 2494, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2494 = t2QSUB8 >+ { 2495, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2495 = t2RBIT >+ { 2496, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2496 = t2REV >+ { 2497, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2497 = t2REV16 >+ { 2498, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2498 = t2REVSH >+ { 2499, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2499 = t2RFEDB >+ { 2500, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2500 = t2RFEDBW >+ { 2501, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2501 = t2RFEIA >+ { 2502, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2502 = t2RFEIAW >+ { 2503, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2503 = t2RORri >+ { 2504, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2504 = t2RORrr >+ { 2505, 5, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo311,0,nullptr }, // Inst #2505 = t2RRX >+ { 2506, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo316,0,nullptr }, // Inst #2506 = t2RSBSri >+ { 2507, 6, 1, 58, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo317,0,nullptr }, // Inst #2507 = t2RSBSrs >+ { 2508, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2508 = t2RSBri >+ { 2509, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2509 = t2RSBrr >+ { 2510, 7, 1, 250, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2510 = t2RSBrs >+ { 2511, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2511 = t2SADD16 >+ { 2512, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2512 = t2SADD8 >+ { 2513, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2513 = t2SASX >+ { 2514, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2514 = t2SBCri >+ { 2515, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2515 = t2SBCrr >+ { 2516, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2516 = t2SBCrs >+ { 2517, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318,0,nullptr }, // Inst #2517 = t2SBFX >+ { 2518, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2518 = t2SDIV >+ { 2519, 5, 1, 296, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #2519 = t2SEL >+ { 2520, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2520 = t2SHADD16 >+ { 2521, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2521 = t2SHADD8 >+ { 2522, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2522 = t2SHASX >+ { 2523, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2523 = t2SHSAX >+ { 2524, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2524 = t2SHSUB16 >+ { 2525, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2525 = t2SHSUB8 >+ { 2526, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2526 = t2SMC >+ { 2527, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2527 = t2SMLABB >+ { 2528, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2528 = t2SMLABT >+ { 2529, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2529 = t2SMLAD >+ { 2530, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2530 = t2SMLADX >+ { 2531, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2531 = t2SMLAL >+ { 2532, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2532 = t2SMLALBB >+ { 2533, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2533 = t2SMLALBT >+ { 2534, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2534 = t2SMLALD >+ { 2535, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2535 = t2SMLALDX >+ { 2536, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2536 = t2SMLALTB >+ { 2537, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2537 = t2SMLALTT >+ { 2538, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2538 = t2SMLATB >+ { 2539, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2539 = t2SMLATT >+ { 2540, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2540 = t2SMLAWB >+ { 2541, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2541 = t2SMLAWT >+ { 2542, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2542 = t2SMLSD >+ { 2543, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2543 = t2SMLSDX >+ { 2544, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2544 = t2SMLSLD >+ { 2545, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2545 = t2SMLSLDX >+ { 2546, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2546 = t2SMMLA >+ { 2547, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2547 = t2SMMLAR >+ { 2548, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2548 = t2SMMLS >+ { 2549, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2549 = t2SMMLSR >+ { 2550, 5, 1, 310, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2550 = t2SMMUL >+ { 2551, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2551 = t2SMMULR >+ { 2552, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2552 = t2SMUAD >+ { 2553, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2553 = t2SMUADX >+ { 2554, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2554 = t2SMULBB >+ { 2555, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2555 = t2SMULBT >+ { 2556, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2556 = t2SMULL >+ { 2557, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2557 = t2SMULTB >+ { 2558, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2558 = t2SMULTT >+ { 2559, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2559 = t2SMULWB >+ { 2560, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2560 = t2SMULWT >+ { 2561, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2561 = t2SMUSD >+ { 2562, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2562 = t2SMUSDX >+ { 2563, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2563 = t2SRSDB >+ { 2564, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2564 = t2SRSDB_UPD >+ { 2565, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2565 = t2SRSIA >+ { 2566, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2566 = t2SRSIA_UPD >+ { 2567, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2567 = t2SSAT >+ { 2568, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2568 = t2SSAT16 >+ { 2569, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2569 = t2SSAX >+ { 2570, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2570 = t2SSUB16 >+ { 2571, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2571 = t2SSUB8 >+ { 2572, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2572 = t2STC2L_OFFSET >+ { 2573, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2573 = t2STC2L_OPTION >+ { 2574, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2574 = t2STC2L_POST >+ { 2575, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2575 = t2STC2L_PRE >+ { 2576, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2576 = t2STC2_OFFSET >+ { 2577, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2577 = t2STC2_OPTION >+ { 2578, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2578 = t2STC2_POST >+ { 2579, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2579 = t2STC2_PRE >+ { 2580, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2580 = t2STCL_OFFSET >+ { 2581, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2581 = t2STCL_OPTION >+ { 2582, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2582 = t2STCL_POST >+ { 2583, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2583 = t2STCL_PRE >+ { 2584, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2584 = t2STC_OFFSET >+ { 2585, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2585 = t2STC_OPTION >+ { 2586, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2586 = t2STC_POST >+ { 2587, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #2587 = t2STC_PRE >+ { 2588, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2588 = t2STL >+ { 2589, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2589 = t2STLB >+ { 2590, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2590 = t2STLEX >+ { 2591, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2591 = t2STLEXB >+ { 2592, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2592 = t2STLEXD >+ { 2593, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2593 = t2STLEXH >+ { 2594, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2594 = t2STLH >+ { 2595, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2595 = t2STMDB >+ { 2596, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2596 = t2STMDB_UPD >+ { 2597, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2597 = t2STMIA >+ { 2598, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2598 = t2STMIA_UPD >+ { 2599, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2599 = t2STRBT >+ { 2600, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2600 = t2STRB_POST >+ { 2601, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2601 = t2STRB_PRE >+ { 2602, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2602 = t2STRB_preidx >+ { 2603, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2603 = t2STRBi12 >+ { 2604, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2604 = t2STRBi8 >+ { 2605, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2605 = t2STRBs >+ { 2606, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2606 = t2STRD_POST >+ { 2607, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2607 = t2STRD_PRE >+ { 2608, 6, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2608 = t2STRDi8 >+ { 2609, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2609 = t2STREX >+ { 2610, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2610 = t2STREXB >+ { 2611, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2611 = t2STREXD >+ { 2612, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2612 = t2STREXH >+ { 2613, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2613 = t2STRHT >+ { 2614, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2614 = t2STRH_POST >+ { 2615, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2615 = t2STRH_PRE >+ { 2616, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2616 = t2STRH_preidx >+ { 2617, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2617 = t2STRHi12 >+ { 2618, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2618 = t2STRHi8 >+ { 2619, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2619 = t2STRHs >+ { 2620, 5, 1, 371, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2620 = t2STRT >+ { 2621, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2621 = t2STR_POST >+ { 2622, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2622 = t2STR_PRE >+ { 2623, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2623 = t2STR_preidx >+ { 2624, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2624 = t2STRi12 >+ { 2625, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2625 = t2STRi8 >+ { 2626, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2626 = t2STRs >+ { 2627, 3, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, ImplicitList14, OperandInfo47,0,nullptr }, // Inst #2627 = t2SUBS_PC_LR >+ { 2628, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2628 = t2SUBSri >+ { 2629, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2629 = t2SUBSrr >+ { 2630, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2630 = t2SUBSrs >+ { 2631, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2631 = t2SUBri >+ { 2632, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2632 = t2SUBri12 >+ { 2633, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2633 = t2SUBrr >+ { 2634, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2634 = t2SUBrs >+ { 2635, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2635 = t2SXTAB >+ { 2636, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2636 = t2SXTAB16 >+ { 2637, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2637 = t2SXTAH >+ { 2638, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2638 = t2SXTB >+ { 2639, 5, 1, 291, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2639 = t2SXTB16 >+ { 2640, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2640 = t2SXTH >+ { 2641, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2641 = t2TBB >+ { 2642, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #2642 = t2TBB_JT >+ { 2643, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2643 = t2TBH >+ { 2644, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #2644 = t2TBH_JT >+ { 2645, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2645 = t2TEQri >+ { 2646, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2646 = t2TEQrr >+ { 2647, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2647 = t2TEQrs >+ { 2648, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2648 = t2TSTri >+ { 2649, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2649 = t2TSTrr >+ { 2650, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2650 = t2TSTrs >+ { 2651, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2651 = t2UADD16 >+ { 2652, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2652 = t2UADD8 >+ { 2653, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2653 = t2UASX >+ { 2654, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318,0,nullptr }, // Inst #2654 = t2UBFX >+ { 2655, 1, 0, 76, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2655 = t2UDF >+ { 2656, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2656 = t2UDIV >+ { 2657, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2657 = t2UHADD16 >+ { 2658, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2658 = t2UHADD8 >+ { 2659, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2659 = t2UHASX >+ { 2660, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2660 = t2UHSAX >+ { 2661, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2661 = t2UHSUB16 >+ { 2662, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2662 = t2UHSUB8 >+ { 2663, 6, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2663 = t2UMAAL >+ { 2664, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2664 = t2UMLAL >+ { 2665, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2665 = t2UMULL >+ { 2666, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2666 = t2UQADD16 >+ { 2667, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2667 = t2UQADD8 >+ { 2668, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2668 = t2UQASX >+ { 2669, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2669 = t2UQSAX >+ { 2670, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2670 = t2UQSUB16 >+ { 2671, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2671 = t2UQSUB8 >+ { 2672, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2672 = t2USAD8 >+ { 2673, 6, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2673 = t2USADA8 >+ { 2674, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2674 = t2USAT >+ { 2675, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2675 = t2USAT16 >+ { 2676, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2676 = t2USAX >+ { 2677, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2677 = t2USUB16 >+ { 2678, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2678 = t2USUB8 >+ { 2679, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2679 = t2UXTAB >+ { 2680, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2680 = t2UXTAB16 >+ { 2681, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2681 = t2UXTAH >+ { 2682, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2682 = t2UXTB >+ { 2683, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2683 = t2UXTB16 >+ { 2684, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2684 = t2UXTH >+ { 2685, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2685 = tADC >+ { 2686, 5, 1, 258, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #2686 = tADDhirr >+ { 2687, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2687 = tADDi3 >+ { 2688, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2688 = tADDi8 >+ { 2689, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2689 = tADDrSP >+ { 2690, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2690 = tADDrSPi >+ { 2691, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2691 = tADDrr >+ { 2692, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2692 = tADDspi >+ { 2693, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2693 = tADDspr >+ { 2694, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,nullptr }, // Inst #2694 = tADJCALLSTACKDOWN >+ { 2695, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,nullptr }, // Inst #2695 = tADJCALLSTACKUP >+ { 2696, 4, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2696 = tADR >+ { 2697, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2697 = tAND >+ { 2698, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2698 = tASRri >+ { 2699, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2699 = tASRrr >+ { 2700, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2700 = tB >+ { 2701, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2701 = tBIC >+ { 2702, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2702 = tBKPT >+ { 2703, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,nullptr }, // Inst #2703 = tBL >+ { 2704, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,nullptr }, // Inst #2704 = tBLXi >+ { 2705, 3, 0, 12, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo341,0,nullptr }, // Inst #2705 = tBLXr >+ { 2706, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2706 = tBRIND >+ { 2707, 3, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo342,0,nullptr }, // Inst #2707 = tBR_JTr >+ { 2708, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #2708 = tBX >+ { 2709, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #2709 = tBX_CALL >+ { 2710, 2, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2710 = tBX_RET >+ { 2711, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo343,0,nullptr }, // Inst #2711 = tBX_RET_vararg >+ { 2712, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2712 = tBcc >+ { 2713, 3, 0, 14, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #2713 = tBfar >+ { 2714, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2714 = tCBNZ >+ { 2715, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2715 = tCBZ >+ { 2716, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2716 = tCMNz >+ { 2717, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #2717 = tCMPhir >+ { 2718, 4, 0, 241, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2718 = tCMPi8 >+ { 2719, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2719 = tCMPr >+ { 2720, 2, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2720 = tCPS >+ { 2721, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2721 = tEOR >+ { 2722, 3, 0, 0, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #2722 = tHINT >+ { 2723, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2723 = tHLT >+ { 2724, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo11,0,nullptr }, // Inst #2724 = tInt_eh_sjlj_longjmp >+ { 2725, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo287,0,nullptr }, // Inst #2725 = tInt_eh_sjlj_setjmp >+ { 2726, 4, 0, 353, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo347,0,nullptr }, // Inst #2726 = tLDMIA >+ { 2727, 5, 1, 354, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #2727 = tLDMIA_UPD >+ { 2728, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2728 = tLDRBi >+ { 2729, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2729 = tLDRBr >+ { 2730, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2730 = tLDRHi >+ { 2731, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2731 = tLDRHr >+ { 2732, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2732 = tLDRLIT_ga_abs >+ { 2733, 2, 1, 34, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2733 = tLDRLIT_ga_pcrel >+ { 2734, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2734 = tLDRSB >+ { 2735, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2735 = tLDRSH >+ { 2736, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2736 = tLDRi >+ { 2737, 4, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2737 = tLDRpci >+ { 2738, 3, 1, 327, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #2738 = tLDRpci_pic >+ { 2739, 5, 1, 334, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2739 = tLDRr >+ { 2740, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2740 = tLDRspi >+ { 2741, 4, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2741 = tLEApcrel >+ { 2742, 5, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo353,0,nullptr }, // Inst #2742 = tLEApcrelJT >+ { 2743, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2743 = tLSLri >+ { 2744, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2744 = tLSLrr >+ { 2745, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2745 = tLSRri >+ { 2746, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2746 = tLSRrr >+ { 2747, 5, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo354,0,nullptr }, // Inst #2747 = tMOVCCr_pseudo >+ { 2748, 2, 1, 48, 2, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo287,0,nullptr }, // Inst #2748 = tMOVSr >+ { 2749, 5, 2, 41, 2, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo355,0,nullptr }, // Inst #2749 = tMOVi8 >+ { 2750, 4, 1, 48, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #2750 = tMOVr >+ { 2751, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2751 = tMUL >+ { 2752, 5, 2, 53, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2752 = tMVN >+ { 2753, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2753 = tORR >+ { 2754, 3, 1, 258, 2, 0|(1<<MCID_NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2754 = tPICADD >+ { 2755, 3, 0, 356, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo359,0,nullptr }, // Inst #2755 = tPOP >+ { 2756, 3, 0, 357, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo359,0,nullptr }, // Inst #2756 = tPOP_RET >+ { 2757, 3, 0, 376, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo359,0,nullptr }, // Inst #2757 = tPUSH >+ { 2758, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2758 = tREV >+ { 2759, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2759 = tREV16 >+ { 2760, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2760 = tREVSH >+ { 2761, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2761 = tROR >+ { 2762, 5, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2762 = tRSB >+ { 2763, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2763 = tSBC >+ { 2764, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #2764 = tSETEND >+ { 2765, 5, 1, 375, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo360,0,nullptr }, // Inst #2765 = tSTMIA_UPD >+ { 2766, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2766 = tSTRBi >+ { 2767, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2767 = tSTRBr >+ { 2768, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2768 = tSTRHi >+ { 2769, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2769 = tSTRHr >+ { 2770, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2770 = tSTRi >+ { 2771, 5, 0, 358, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2771 = tSTRr >+ { 2772, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2772 = tSTRspi >+ { 2773, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2773 = tSUBi3 >+ { 2774, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2774 = tSUBi8 >+ { 2775, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2775 = tSUBrr >+ { 2776, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2776 = tSUBspi >+ { 2777, 3, 0, 10, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo47,0,nullptr }, // Inst #2777 = tSVC >+ { 2778, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2778 = tSXTB >+ { 2779, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2779 = tSXTH >+ { 2780, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo34,0,nullptr }, // Inst #2780 = tTAILJMPd >+ { 2781, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo34,0,nullptr }, // Inst #2781 = tTAILJMPdND >+ { 2782, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo122,0,nullptr }, // Inst #2782 = tTAILJMPr >+ { 2783, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, nullptr,0,nullptr }, // Inst #2783 = tTPsoft >+ { 2784, 0, 0, 10, 2, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #2784 = tTRAP >+ { 2785, 4, 0, 263, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2785 = tTST >+ { 2786, 1, 0, 76, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2786 = tUDF >+ { 2787, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2787 = tUXTB >+ { 2788, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2788 = tUXTH >+}; >+ >+ >+#endif // GET_INSTRINFO_MC_DESC >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..f5c9be6e95ec30af835d32e64595599ac2fa5f72 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenRegisterInfo.inc >@@ -0,0 +1,2281 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Register Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_ENUM >+#undef GET_REGINFO_ENUM >+ >+enum { >+ ARM_NoRegister, >+ ARM_APSR = 1, >+ ARM_APSR_NZCV = 2, >+ ARM_CPSR = 3, >+ ARM_FPEXC = 4, >+ ARM_FPINST = 5, >+ ARM_FPSCR = 6, >+ ARM_FPSCR_NZCV = 7, >+ ARM_FPSID = 8, >+ ARM_ITSTATE = 9, >+ ARM_LR = 10, >+ ARM_PC = 11, >+ ARM_SP = 12, >+ ARM_SPSR = 13, >+ ARM_D0 = 14, >+ ARM_D1 = 15, >+ ARM_D2 = 16, >+ ARM_D3 = 17, >+ ARM_D4 = 18, >+ ARM_D5 = 19, >+ ARM_D6 = 20, >+ ARM_D7 = 21, >+ ARM_D8 = 22, >+ ARM_D9 = 23, >+ ARM_D10 = 24, >+ ARM_D11 = 25, >+ ARM_D12 = 26, >+ ARM_D13 = 27, >+ ARM_D14 = 28, >+ ARM_D15 = 29, >+ ARM_D16 = 30, >+ ARM_D17 = 31, >+ ARM_D18 = 32, >+ ARM_D19 = 33, >+ ARM_D20 = 34, >+ ARM_D21 = 35, >+ ARM_D22 = 36, >+ ARM_D23 = 37, >+ ARM_D24 = 38, >+ ARM_D25 = 39, >+ ARM_D26 = 40, >+ ARM_D27 = 41, >+ ARM_D28 = 42, >+ ARM_D29 = 43, >+ ARM_D30 = 44, >+ ARM_D31 = 45, >+ ARM_FPINST2 = 46, >+ ARM_MVFR0 = 47, >+ ARM_MVFR1 = 48, >+ ARM_MVFR2 = 49, >+ ARM_Q0 = 50, >+ ARM_Q1 = 51, >+ ARM_Q2 = 52, >+ ARM_Q3 = 53, >+ ARM_Q4 = 54, >+ ARM_Q5 = 55, >+ ARM_Q6 = 56, >+ ARM_Q7 = 57, >+ ARM_Q8 = 58, >+ ARM_Q9 = 59, >+ ARM_Q10 = 60, >+ ARM_Q11 = 61, >+ ARM_Q12 = 62, >+ ARM_Q13 = 63, >+ ARM_Q14 = 64, >+ ARM_Q15 = 65, >+ ARM_R0 = 66, >+ ARM_R1 = 67, >+ ARM_R2 = 68, >+ ARM_R3 = 69, >+ ARM_R4 = 70, >+ ARM_R5 = 71, >+ ARM_R6 = 72, >+ ARM_R7 = 73, >+ ARM_R8 = 74, >+ ARM_R9 = 75, >+ ARM_R10 = 76, >+ ARM_R11 = 77, >+ ARM_R12 = 78, >+ ARM_S0 = 79, >+ ARM_S1 = 80, >+ ARM_S2 = 81, >+ ARM_S3 = 82, >+ ARM_S4 = 83, >+ ARM_S5 = 84, >+ ARM_S6 = 85, >+ ARM_S7 = 86, >+ ARM_S8 = 87, >+ ARM_S9 = 88, >+ ARM_S10 = 89, >+ ARM_S11 = 90, >+ ARM_S12 = 91, >+ ARM_S13 = 92, >+ ARM_S14 = 93, >+ ARM_S15 = 94, >+ ARM_S16 = 95, >+ ARM_S17 = 96, >+ ARM_S18 = 97, >+ ARM_S19 = 98, >+ ARM_S20 = 99, >+ ARM_S21 = 100, >+ ARM_S22 = 101, >+ ARM_S23 = 102, >+ ARM_S24 = 103, >+ ARM_S25 = 104, >+ ARM_S26 = 105, >+ ARM_S27 = 106, >+ ARM_S28 = 107, >+ ARM_S29 = 108, >+ ARM_S30 = 109, >+ ARM_S31 = 110, >+ ARM_D0_D2 = 111, >+ ARM_D1_D3 = 112, >+ ARM_D2_D4 = 113, >+ ARM_D3_D5 = 114, >+ ARM_D4_D6 = 115, >+ ARM_D5_D7 = 116, >+ ARM_D6_D8 = 117, >+ ARM_D7_D9 = 118, >+ ARM_D8_D10 = 119, >+ ARM_D9_D11 = 120, >+ ARM_D10_D12 = 121, >+ ARM_D11_D13 = 122, >+ ARM_D12_D14 = 123, >+ ARM_D13_D15 = 124, >+ ARM_D14_D16 = 125, >+ ARM_D15_D17 = 126, >+ ARM_D16_D18 = 127, >+ ARM_D17_D19 = 128, >+ ARM_D18_D20 = 129, >+ ARM_D19_D21 = 130, >+ ARM_D20_D22 = 131, >+ ARM_D21_D23 = 132, >+ ARM_D22_D24 = 133, >+ ARM_D23_D25 = 134, >+ ARM_D24_D26 = 135, >+ ARM_D25_D27 = 136, >+ ARM_D26_D28 = 137, >+ ARM_D27_D29 = 138, >+ ARM_D28_D30 = 139, >+ ARM_D29_D31 = 140, >+ ARM_Q0_Q1 = 141, >+ ARM_Q1_Q2 = 142, >+ ARM_Q2_Q3 = 143, >+ ARM_Q3_Q4 = 144, >+ ARM_Q4_Q5 = 145, >+ ARM_Q5_Q6 = 146, >+ ARM_Q6_Q7 = 147, >+ ARM_Q7_Q8 = 148, >+ ARM_Q8_Q9 = 149, >+ ARM_Q9_Q10 = 150, >+ ARM_Q10_Q11 = 151, >+ ARM_Q11_Q12 = 152, >+ ARM_Q12_Q13 = 153, >+ ARM_Q13_Q14 = 154, >+ ARM_Q14_Q15 = 155, >+ ARM_Q0_Q1_Q2_Q3 = 156, >+ ARM_Q1_Q2_Q3_Q4 = 157, >+ ARM_Q2_Q3_Q4_Q5 = 158, >+ ARM_Q3_Q4_Q5_Q6 = 159, >+ ARM_Q4_Q5_Q6_Q7 = 160, >+ ARM_Q5_Q6_Q7_Q8 = 161, >+ ARM_Q6_Q7_Q8_Q9 = 162, >+ ARM_Q7_Q8_Q9_Q10 = 163, >+ ARM_Q8_Q9_Q10_Q11 = 164, >+ ARM_Q9_Q10_Q11_Q12 = 165, >+ ARM_Q10_Q11_Q12_Q13 = 166, >+ ARM_Q11_Q12_Q13_Q14 = 167, >+ ARM_Q12_Q13_Q14_Q15 = 168, >+ ARM_R12_SP = 169, >+ ARM_R0_R1 = 170, >+ ARM_R2_R3 = 171, >+ ARM_R4_R5 = 172, >+ ARM_R6_R7 = 173, >+ ARM_R8_R9 = 174, >+ ARM_R10_R11 = 175, >+ ARM_D0_D1_D2 = 176, >+ ARM_D1_D2_D3 = 177, >+ ARM_D2_D3_D4 = 178, >+ ARM_D3_D4_D5 = 179, >+ ARM_D4_D5_D6 = 180, >+ ARM_D5_D6_D7 = 181, >+ ARM_D6_D7_D8 = 182, >+ ARM_D7_D8_D9 = 183, >+ ARM_D8_D9_D10 = 184, >+ ARM_D9_D10_D11 = 185, >+ ARM_D10_D11_D12 = 186, >+ ARM_D11_D12_D13 = 187, >+ ARM_D12_D13_D14 = 188, >+ ARM_D13_D14_D15 = 189, >+ ARM_D14_D15_D16 = 190, >+ ARM_D15_D16_D17 = 191, >+ ARM_D16_D17_D18 = 192, >+ ARM_D17_D18_D19 = 193, >+ ARM_D18_D19_D20 = 194, >+ ARM_D19_D20_D21 = 195, >+ ARM_D20_D21_D22 = 196, >+ ARM_D21_D22_D23 = 197, >+ ARM_D22_D23_D24 = 198, >+ ARM_D23_D24_D25 = 199, >+ ARM_D24_D25_D26 = 200, >+ ARM_D25_D26_D27 = 201, >+ ARM_D26_D27_D28 = 202, >+ ARM_D27_D28_D29 = 203, >+ ARM_D28_D29_D30 = 204, >+ ARM_D29_D30_D31 = 205, >+ ARM_D0_D2_D4 = 206, >+ ARM_D1_D3_D5 = 207, >+ ARM_D2_D4_D6 = 208, >+ ARM_D3_D5_D7 = 209, >+ ARM_D4_D6_D8 = 210, >+ ARM_D5_D7_D9 = 211, >+ ARM_D6_D8_D10 = 212, >+ ARM_D7_D9_D11 = 213, >+ ARM_D8_D10_D12 = 214, >+ ARM_D9_D11_D13 = 215, >+ ARM_D10_D12_D14 = 216, >+ ARM_D11_D13_D15 = 217, >+ ARM_D12_D14_D16 = 218, >+ ARM_D13_D15_D17 = 219, >+ ARM_D14_D16_D18 = 220, >+ ARM_D15_D17_D19 = 221, >+ ARM_D16_D18_D20 = 222, >+ ARM_D17_D19_D21 = 223, >+ ARM_D18_D20_D22 = 224, >+ ARM_D19_D21_D23 = 225, >+ ARM_D20_D22_D24 = 226, >+ ARM_D21_D23_D25 = 227, >+ ARM_D22_D24_D26 = 228, >+ ARM_D23_D25_D27 = 229, >+ ARM_D24_D26_D28 = 230, >+ ARM_D25_D27_D29 = 231, >+ ARM_D26_D28_D30 = 232, >+ ARM_D27_D29_D31 = 233, >+ ARM_D0_D2_D4_D6 = 234, >+ ARM_D1_D3_D5_D7 = 235, >+ ARM_D2_D4_D6_D8 = 236, >+ ARM_D3_D5_D7_D9 = 237, >+ ARM_D4_D6_D8_D10 = 238, >+ ARM_D5_D7_D9_D11 = 239, >+ ARM_D6_D8_D10_D12 = 240, >+ ARM_D7_D9_D11_D13 = 241, >+ ARM_D8_D10_D12_D14 = 242, >+ ARM_D9_D11_D13_D15 = 243, >+ ARM_D10_D12_D14_D16 = 244, >+ ARM_D11_D13_D15_D17 = 245, >+ ARM_D12_D14_D16_D18 = 246, >+ ARM_D13_D15_D17_D19 = 247, >+ ARM_D14_D16_D18_D20 = 248, >+ ARM_D15_D17_D19_D21 = 249, >+ ARM_D16_D18_D20_D22 = 250, >+ ARM_D17_D19_D21_D23 = 251, >+ ARM_D18_D20_D22_D24 = 252, >+ ARM_D19_D21_D23_D25 = 253, >+ ARM_D20_D22_D24_D26 = 254, >+ ARM_D21_D23_D25_D27 = 255, >+ ARM_D22_D24_D26_D28 = 256, >+ ARM_D23_D25_D27_D29 = 257, >+ ARM_D24_D26_D28_D30 = 258, >+ ARM_D25_D27_D29_D31 = 259, >+ ARM_D1_D2 = 260, >+ ARM_D3_D4 = 261, >+ ARM_D5_D6 = 262, >+ ARM_D7_D8 = 263, >+ ARM_D9_D10 = 264, >+ ARM_D11_D12 = 265, >+ ARM_D13_D14 = 266, >+ ARM_D15_D16 = 267, >+ ARM_D17_D18 = 268, >+ ARM_D19_D20 = 269, >+ ARM_D21_D22 = 270, >+ ARM_D23_D24 = 271, >+ ARM_D25_D26 = 272, >+ ARM_D27_D28 = 273, >+ ARM_D29_D30 = 274, >+ ARM_D1_D2_D3_D4 = 275, >+ ARM_D3_D4_D5_D6 = 276, >+ ARM_D5_D6_D7_D8 = 277, >+ ARM_D7_D8_D9_D10 = 278, >+ ARM_D9_D10_D11_D12 = 279, >+ ARM_D11_D12_D13_D14 = 280, >+ ARM_D13_D14_D15_D16 = 281, >+ ARM_D15_D16_D17_D18 = 282, >+ ARM_D17_D18_D19_D20 = 283, >+ ARM_D19_D20_D21_D22 = 284, >+ ARM_D21_D22_D23_D24 = 285, >+ ARM_D23_D24_D25_D26 = 286, >+ ARM_D25_D26_D27_D28 = 287, >+ ARM_D27_D28_D29_D30 = 288, >+ ARM_NUM_TARGET_REGS // 289 >+}; >+ >+// Register classes >+enum { >+ ARM_SPRRegClassID = 0, >+ ARM_GPRRegClassID = 1, >+ ARM_GPRwithAPSRRegClassID = 2, >+ ARM_SPR_8RegClassID = 3, >+ ARM_GPRnopcRegClassID = 4, >+ ARM_rGPRRegClassID = 5, >+ ARM_hGPRRegClassID = 6, >+ ARM_tGPRRegClassID = 7, >+ ARM_GPRnopc_and_hGPRRegClassID = 8, >+ ARM_hGPR_and_rGPRRegClassID = 9, >+ ARM_tcGPRRegClassID = 10, >+ ARM_tGPR_and_tcGPRRegClassID = 11, >+ ARM_CCRRegClassID = 12, >+ ARM_GPRspRegClassID = 13, >+ ARM_hGPR_and_tcGPRRegClassID = 14, >+ ARM_DPRRegClassID = 15, >+ ARM_DPR_VFP2RegClassID = 16, >+ ARM_DPR_8RegClassID = 17, >+ ARM_GPRPairRegClassID = 18, >+ ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 19, >+ ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 20, >+ ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 21, >+ ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 22, >+ ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 23, >+ ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 24, >+ ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 25, >+ ARM_DPairSpcRegClassID = 26, >+ ARM_DPairSpc_with_ssub_0RegClassID = 27, >+ ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID = 28, >+ ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 29, >+ ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 30, >+ ARM_DPairRegClassID = 31, >+ ARM_DPair_with_ssub_0RegClassID = 32, >+ ARM_QPRRegClassID = 33, >+ ARM_DPair_with_ssub_2RegClassID = 34, >+ ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 35, >+ ARM_QPR_VFP2RegClassID = 36, >+ ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 37, >+ ARM_QPR_8RegClassID = 38, >+ ARM_DTripleRegClassID = 39, >+ ARM_DTripleSpcRegClassID = 40, >+ ARM_DTripleSpc_with_ssub_0RegClassID = 41, >+ ARM_DTriple_with_ssub_0RegClassID = 42, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 43, >+ ARM_DTriple_with_qsub_0_in_QPRRegClassID = 44, >+ ARM_DTriple_with_ssub_2RegClassID = 45, >+ ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID = 46, >+ ARM_DTriple_with_dsub_2_then_ssub_0RegClassID = 47, >+ ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID = 48, >+ ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 49, >+ ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 50, >+ ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 51, >+ ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 52, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 53, >+ ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 54, >+ ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID = 55, >+ ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 56, >+ ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 57, >+ ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 58, >+ ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 59, >+ ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 60, >+ ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID = 61, >+ ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 62, >+ ARM_DQuadSpcRegClassID = 63, >+ ARM_DQuadSpc_with_ssub_0RegClassID = 64, >+ ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID = 65, >+ ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID = 66, >+ ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 67, >+ ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 68, >+ ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 69, >+ ARM_DQuadRegClassID = 70, >+ ARM_DQuad_with_ssub_0RegClassID = 71, >+ ARM_DQuad_with_ssub_2RegClassID = 72, >+ ARM_QQPRRegClassID = 73, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 74, >+ ARM_DQuad_with_dsub_2_then_ssub_0RegClassID = 75, >+ ARM_DQuad_with_dsub_3_then_ssub_0RegClassID = 76, >+ ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 77, >+ ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 78, >+ ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 79, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 80, >+ ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 81, >+ ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 82, >+ ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 83, >+ ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 84, >+ ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 85, >+ ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 86, >+ ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 87, >+ ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID = 88, >+ ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 89, >+ ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 90, >+ ARM_QQQQPRRegClassID = 91, >+ ARM_QQQQPR_with_ssub_0RegClassID = 92, >+ ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID = 93, >+ ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID = 94, >+ ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID = 95, >+ ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 96, >+ ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 97, >+ ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 98, >+ ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 99 >+}; >+ >+// Subregister indices >+enum { >+ ARM_NoSubRegister, >+ ARM_dsub_0, // 1 >+ ARM_dsub_1, // 2 >+ ARM_dsub_2, // 3 >+ ARM_dsub_3, // 4 >+ ARM_dsub_4, // 5 >+ ARM_dsub_5, // 6 >+ ARM_dsub_6, // 7 >+ ARM_dsub_7, // 8 >+ ARM_gsub_0, // 9 >+ ARM_gsub_1, // 10 >+ ARM_qqsub_0, // 11 >+ ARM_qqsub_1, // 12 >+ ARM_qsub_0, // 13 >+ ARM_qsub_1, // 14 >+ ARM_qsub_2, // 15 >+ ARM_qsub_3, // 16 >+ ARM_ssub_0, // 17 >+ ARM_ssub_1, // 18 >+ ARM_ssub_2, // 19 >+ ARM_ssub_3, // 20 >+ ARM_dsub_2_then_ssub_0, // 21 >+ ARM_dsub_2_then_ssub_1, // 22 >+ ARM_dsub_3_then_ssub_0, // 23 >+ ARM_dsub_3_then_ssub_1, // 24 >+ ARM_dsub_7_then_ssub_0, // 25 >+ ARM_dsub_7_then_ssub_1, // 26 >+ ARM_dsub_6_then_ssub_0, // 27 >+ ARM_dsub_6_then_ssub_1, // 28 >+ ARM_dsub_5_then_ssub_0, // 29 >+ ARM_dsub_5_then_ssub_1, // 30 >+ ARM_dsub_4_then_ssub_0, // 31 >+ ARM_dsub_4_then_ssub_1, // 32 >+ ARM_dsub_0_dsub_2, // 33 >+ ARM_dsub_0_dsub_1_dsub_2, // 34 >+ ARM_dsub_1_dsub_3, // 35 >+ ARM_dsub_1_dsub_2_dsub_3, // 36 >+ ARM_dsub_1_dsub_2, // 37 >+ ARM_dsub_0_dsub_2_dsub_4, // 38 >+ ARM_dsub_0_dsub_2_dsub_4_dsub_6, // 39 >+ ARM_dsub_1_dsub_3_dsub_5, // 40 >+ ARM_dsub_1_dsub_3_dsub_5_dsub_7, // 41 >+ ARM_dsub_1_dsub_2_dsub_3_dsub_4, // 42 >+ ARM_dsub_2_dsub_4, // 43 >+ ARM_dsub_2_dsub_3_dsub_4, // 44 >+ ARM_dsub_2_dsub_4_dsub_6, // 45 >+ ARM_dsub_3_dsub_5, // 46 >+ ARM_dsub_3_dsub_4_dsub_5, // 47 >+ ARM_dsub_3_dsub_5_dsub_7, // 48 >+ ARM_dsub_3_dsub_4, // 49 >+ ARM_dsub_3_dsub_4_dsub_5_dsub_6, // 50 >+ ARM_dsub_4_dsub_6, // 51 >+ ARM_dsub_4_dsub_5_dsub_6, // 52 >+ ARM_dsub_5_dsub_7, // 53 >+ ARM_dsub_5_dsub_6_dsub_7, // 54 >+ ARM_dsub_5_dsub_6, // 55 >+ ARM_qsub_1_qsub_2, // 56 >+ ARM_NUM_TARGET_SUBREGS >+}; >+ >+#endif // GET_REGINFO_ENUM >+ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*MC Register Information *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_MC_DESC >+#undef GET_REGINFO_MC_DESC >+ >+static const MCPhysReg ARMRegDiffLists[] = { >+ /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0, >+ /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0, >+ /* 91 */ 40, 1, 1, 1, 1, 1, 0, >+ /* 98 */ 65196, 1, 1, 1, 1, 1, 0, >+ /* 105 */ 40, 1, 1, 1, 1, 0, >+ /* 111 */ 42, 1, 1, 1, 1, 0, >+ /* 117 */ 42, 1, 1, 1, 0, >+ /* 122 */ 64510, 1, 1, 1, 0, >+ /* 127 */ 65015, 1, 1, 1, 0, >+ /* 132 */ 65282, 1, 1, 1, 0, >+ /* 137 */ 65348, 1, 1, 1, 0, >+ /* 142 */ 13, 1, 1, 0, >+ /* 146 */ 42, 1, 1, 0, >+ /* 150 */ 65388, 1, 1, 0, >+ /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, >+ /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, >+ /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, >+ /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, >+ /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, >+ /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, >+ /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, >+ /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, >+ /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, >+ /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, >+ /* 254 */ 65489, 133, 65416, 1, 1, 0, >+ /* 260 */ 65490, 133, 65416, 1, 1, 0, >+ /* 266 */ 65491, 133, 65416, 1, 1, 0, >+ /* 272 */ 65492, 133, 65416, 1, 1, 0, >+ /* 278 */ 65493, 133, 65416, 1, 1, 0, >+ /* 284 */ 65494, 133, 65416, 1, 1, 0, >+ /* 290 */ 65495, 133, 65416, 1, 1, 0, >+ /* 296 */ 65496, 133, 65416, 1, 1, 0, >+ /* 302 */ 65497, 133, 65416, 1, 1, 0, >+ /* 308 */ 65498, 133, 65416, 1, 1, 0, >+ /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, >+ /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0, >+ /* 332 */ 65136, 1, 3, 1, 3, 1, 0, >+ /* 339 */ 65326, 1, 3, 1, 0, >+ /* 344 */ 13, 1, 0, >+ /* 347 */ 14, 1, 0, >+ /* 350 */ 65, 1, 0, >+ /* 353 */ 65500, 65, 1, 65471, 66, 1, 0, >+ /* 360 */ 65291, 66, 1, 65470, 67, 1, 0, >+ /* 367 */ 65439, 65, 1, 65472, 67, 1, 0, >+ /* 374 */ 65501, 67, 1, 65469, 68, 1, 0, >+ /* 381 */ 65439, 66, 1, 65471, 68, 1, 0, >+ /* 388 */ 65292, 68, 1, 65468, 69, 1, 0, >+ /* 395 */ 65439, 67, 1, 65470, 69, 1, 0, >+ /* 402 */ 65502, 69, 1, 65467, 70, 1, 0, >+ /* 409 */ 65439, 68, 1, 65469, 70, 1, 0, >+ /* 416 */ 65293, 70, 1, 65466, 71, 1, 0, >+ /* 423 */ 65439, 69, 1, 65468, 71, 1, 0, >+ /* 430 */ 65503, 71, 1, 65465, 72, 1, 0, >+ /* 437 */ 65439, 70, 1, 65467, 72, 1, 0, >+ /* 444 */ 65294, 72, 1, 65464, 73, 1, 0, >+ /* 451 */ 65439, 71, 1, 65466, 73, 1, 0, >+ /* 458 */ 65504, 73, 1, 65463, 74, 1, 0, >+ /* 465 */ 65439, 72, 1, 65465, 74, 1, 0, >+ /* 472 */ 65295, 74, 1, 65462, 75, 1, 0, >+ /* 479 */ 65439, 73, 1, 65464, 75, 1, 0, >+ /* 486 */ 65505, 75, 1, 65461, 76, 1, 0, >+ /* 493 */ 65439, 74, 1, 65463, 76, 1, 0, >+ /* 500 */ 65296, 76, 1, 65460, 77, 1, 0, >+ /* 507 */ 65439, 75, 1, 65462, 77, 1, 0, >+ /* 514 */ 65506, 77, 1, 65459, 78, 1, 0, >+ /* 521 */ 65439, 76, 1, 65461, 78, 1, 0, >+ /* 528 */ 65297, 78, 1, 65458, 79, 1, 0, >+ /* 535 */ 65439, 77, 1, 65460, 79, 1, 0, >+ /* 542 */ 65507, 79, 1, 65457, 80, 1, 0, >+ /* 549 */ 65439, 78, 1, 65459, 80, 1, 0, >+ /* 556 */ 65045, 1, 0, >+ /* 559 */ 65260, 1, 0, >+ /* 562 */ 65299, 1, 0, >+ /* 565 */ 65300, 1, 0, >+ /* 568 */ 65301, 1, 0, >+ /* 571 */ 65302, 1, 0, >+ /* 574 */ 65303, 1, 0, >+ /* 577 */ 65304, 1, 0, >+ /* 580 */ 65305, 1, 0, >+ /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, >+ /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, >+ /* 600 */ 65488, 13, 121, 65416, 1, 0, >+ /* 606 */ 65489, 13, 121, 65416, 1, 0, >+ /* 612 */ 65490, 13, 121, 65416, 1, 0, >+ /* 618 */ 65491, 13, 121, 65416, 1, 0, >+ /* 624 */ 65492, 13, 121, 65416, 1, 0, >+ /* 630 */ 65493, 13, 121, 65416, 1, 0, >+ /* 636 */ 65494, 13, 121, 65416, 1, 0, >+ /* 642 */ 65495, 13, 121, 65416, 1, 0, >+ /* 648 */ 65496, 13, 121, 65416, 1, 0, >+ /* 654 */ 65497, 13, 121, 65416, 1, 0, >+ /* 660 */ 65498, 13, 121, 65416, 1, 0, >+ /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, >+ /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, >+ /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, >+ /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, >+ /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, >+ /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, >+ /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, >+ /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, >+ /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, >+ /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, >+ /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, >+ /* 765 */ 65488, 133, 65416, 1, 0, >+ /* 770 */ 65499, 134, 65416, 1, 0, >+ /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, >+ /* 783 */ 65432, 1, 0, >+ /* 786 */ 65433, 1, 0, >+ /* 789 */ 65434, 1, 0, >+ /* 792 */ 65435, 1, 0, >+ /* 795 */ 65436, 1, 0, >+ /* 798 */ 65437, 1, 0, >+ /* 801 */ 65464, 1, 0, >+ /* 804 */ 65508, 1, 0, >+ /* 807 */ 65509, 1, 0, >+ /* 810 */ 65510, 1, 0, >+ /* 813 */ 65511, 1, 0, >+ /* 816 */ 65512, 1, 0, >+ /* 819 */ 65513, 1, 0, >+ /* 822 */ 65514, 1, 0, >+ /* 825 */ 65515, 1, 0, >+ /* 828 */ 65520, 1, 0, >+ /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0, >+ /* 839 */ 65136, 1, 3, 1, 2, 0, >+ /* 845 */ 65326, 1, 2, 0, >+ /* 849 */ 65080, 1, 3, 1, 2, 2, 0, >+ /* 856 */ 65136, 1, 2, 2, 0, >+ /* 861 */ 65080, 1, 2, 2, 2, 0, >+ /* 867 */ 65330, 2, 2, 2, 0, >+ /* 872 */ 65080, 1, 3, 2, 2, 0, >+ /* 878 */ 65358, 2, 2, 0, >+ /* 882 */ 65080, 1, 3, 1, 3, 2, 0, >+ /* 889 */ 65136, 1, 3, 2, 0, >+ /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0, >+ /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0, >+ /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0, >+ /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0, >+ /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0, >+ /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0, >+ /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0, >+ /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0, >+ /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0, >+ /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0, >+ /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0, >+ /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0, >+ /* 1038 */ 65344, 2, 2, 93, 2, 0, >+ /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0, >+ /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0, >+ /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0, >+ /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0, >+ /* 1080 */ 65439, 2, 0, >+ /* 1083 */ 65453, 2, 0, >+ /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0, >+ /* 1094 */ 65136, 1, 3, 1, 3, 0, >+ /* 1100 */ 65326, 1, 3, 0, >+ /* 1104 */ 5, 0, >+ /* 1106 */ 140, 65486, 13, 0, >+ /* 1110 */ 14, 0, >+ /* 1112 */ 126, 65501, 15, 0, >+ /* 1116 */ 10, 66, 0, >+ /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0, >+ /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0, >+ /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0, >+ /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0, >+ /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0, >+ /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0, >+ /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0, >+ /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0, >+ /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0, >+ /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0, >+ /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0, >+ /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0, >+ /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0, >+ /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0, >+ /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0, >+ /* 1359 */ 91, 0, >+ /* 1361 */ 98, 0, >+ /* 1363 */ 99, 0, >+ /* 1365 */ 100, 0, >+ /* 1367 */ 101, 0, >+ /* 1369 */ 102, 0, >+ /* 1371 */ 103, 0, >+ /* 1373 */ 104, 0, >+ /* 1375 */ 65374, 1, 1, 20, 75, 135, 0, >+ /* 1382 */ 65374, 1, 1, 21, 74, 136, 0, >+ /* 1389 */ 65374, 1, 1, 22, 73, 137, 0, >+ /* 1396 */ 65374, 1, 1, 23, 72, 138, 0, >+ /* 1403 */ 65374, 1, 1, 24, 71, 139, 0, >+ /* 1410 */ 65374, 1, 1, 25, 70, 140, 0, >+ /* 1417 */ 65374, 1, 1, 26, 69, 141, 0, >+ /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0, >+ /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0, >+ /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0, >+ /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0, >+ /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0, >+ /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0, >+ /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0, >+ /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0, >+ /* 1526 */ 157, 0, >+ /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0, >+ /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0, >+ /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0, >+ /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0, >+ /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0, >+ /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0, >+ /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, >+ /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, >+ /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, >+ /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, >+ /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, >+ /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, >+ /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, >+ /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, >+ /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, >+ /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, >+ /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, >+ /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, >+ /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, >+ /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0, >+ /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0, >+ /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, >+ /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, >+ /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, >+ /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, >+ /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, >+ /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, >+ /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, >+ /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, >+ /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, >+ /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, >+ /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, >+ /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0, >+ /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, >+ /* 2455 */ 65487, 13, 121, 65416, 0, >+ /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, >+ /* 2468 */ 65466, 1, 65486, 133, 65416, 0, >+ /* 2474 */ 65487, 133, 65416, 0, >+ /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, >+ /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, >+ /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0, >+ /* 2509 */ 65452, 1, 65500, 134, 65417, 0, >+ /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0, >+ /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0, >+ /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0, >+ /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0, >+ /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0, >+ /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0, >+ /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0, >+ /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0, >+ /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0, >+ /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0, >+ /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0, >+ /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0, >+ /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0, >+ /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0, >+ /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, >+ /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, >+ /* 2832 */ 26, 65446, 92, 65445, 0, >+ /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, >+ /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, >+ /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, >+ /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, >+ /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, >+ /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, >+ /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, >+ /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, >+ /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, >+ /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, >+ /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, >+ /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, >+ /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, >+ /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, >+ /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, >+ /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, >+ /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, >+ /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, >+ /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, >+ /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, >+ /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, >+ /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, >+ /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, >+ /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, >+ /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, >+ /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, >+ /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, >+ /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, >+ /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, >+ /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, >+ /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, >+ /* 3839 */ 65298, 80, 1, 65456, 0, >+ /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, >+ /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, >+ /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, >+ /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, >+ /* 3948 */ 65439, 80, 1, 65457, 0, >+ /* 3953 */ 28, 65457, 0, >+ /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, >+ /* 4002 */ 26, 65458, 80, 65457, 0, >+ /* 4007 */ 65439, 79, 1, 65458, 0, >+ /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0, >+ /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0, >+ /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0, >+ /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0, >+ /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0, >+ /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0, >+ /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0, >+ /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0, >+ /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0, >+ /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0, >+ /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0, >+ /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0, >+ /* 4114 */ 65445, 65470, 0, >+ /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0, >+ /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0, >+ /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0, >+ /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0, >+ /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0, >+ /* 4182 */ 65534, 0, >+ /* 4184 */ 65535, 0, >+}; >+ >+static const uint16_t ARMSubRegIdxLists[] = { >+ /* 0 */ 1, 2, 0, >+ /* 3 */ 1, 17, 18, 2, 0, >+ /* 8 */ 1, 3, 0, >+ /* 11 */ 1, 17, 18, 3, 0, >+ /* 16 */ 9, 10, 0, >+ /* 19 */ 17, 18, 0, >+ /* 22 */ 1, 17, 18, 2, 19, 20, 0, >+ /* 29 */ 1, 17, 18, 3, 21, 22, 0, >+ /* 36 */ 1, 2, 3, 13, 33, 37, 0, >+ /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, >+ /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, >+ /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, >+ /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, >+ /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, >+ /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, >+ /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, >+ /* 188 */ 1, 3, 5, 33, 43, 0, >+ /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, >+ /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, >+ /* 212 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 33, 43, 0, >+ /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, >+ /* 260 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 33, 38, 43, 45, 51, 0, >+ /* 276 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 27, 28, 33, 38, 43, 45, 51, 0, >+ /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+ /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 27, 28, 8, 25, 26, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, >+}; >+ >+static const MCRegisterDesc ARMRegDesc[] = { // Descriptors >+ { 12, 0, 0, 0, 0 }, >+ { 1235, 16, 16, 2, 66945 }, >+ { 1268, 16, 16, 2, 66945 }, >+ { 1240, 16, 16, 2, 66945 }, >+ { 1199, 16, 16, 2, 66945 }, >+ { 1250, 16, 16, 2, 66945 }, >+ { 1226, 16, 16, 2, 17664 }, >+ { 1257, 16, 16, 2, 17664 }, >+ { 1205, 16, 16, 2, 66913 }, >+ { 1211, 16, 16, 2, 66913 }, >+ { 1232, 16, 16, 2, 66913 }, >+ { 1196, 16, 16, 2, 66913 }, >+ { 1223, 16, 1526, 2, 66913 }, >+ { 1245, 16, 16, 2, 66913 }, >+ { 119, 350, 4013, 19, 13250 }, >+ { 248, 357, 2479, 19, 13250 }, >+ { 363, 364, 3957, 19, 13250 }, >+ { 479, 378, 3845, 19, 13250 }, >+ { 605, 392, 3893, 19, 13250 }, >+ { 723, 406, 3724, 19, 13250 }, >+ { 837, 420, 3780, 19, 13250 }, >+ { 943, 434, 3604, 19, 13250 }, >+ { 1057, 448, 3664, 19, 13250 }, >+ { 1163, 462, 3484, 19, 13250 }, >+ { 9, 476, 3544, 19, 13250 }, >+ { 141, 490, 3364, 19, 13250 }, >+ { 282, 504, 3424, 19, 13250 }, >+ { 408, 518, 3244, 19, 13250 }, >+ { 523, 532, 3304, 19, 13250 }, >+ { 649, 546, 3149, 19, 13250 }, >+ { 768, 16, 3208, 2, 17761 }, >+ { 882, 16, 3078, 2, 17761 }, >+ { 988, 16, 3113, 2, 17761 }, >+ { 1102, 16, 3008, 2, 17761 }, >+ { 59, 16, 3043, 2, 17761 }, >+ { 192, 16, 2938, 2, 17761 }, >+ { 336, 16, 2973, 2, 17761 }, >+ { 456, 16, 2868, 2, 17761 }, >+ { 575, 16, 2903, 2, 17761 }, >+ { 697, 16, 2797, 2, 17761 }, >+ { 804, 16, 2837, 2, 17761 }, >+ { 914, 16, 2363, 2, 17761 }, >+ { 1024, 16, 2411, 2, 17761 }, >+ { 1134, 16, 2384, 2, 17761 }, >+ { 95, 16, 2429, 2, 17761 }, >+ { 224, 16, 2789, 2, 17761 }, >+ { 390, 16, 16, 2, 17761 }, >+ { 125, 16, 16, 2, 17761 }, >+ { 257, 16, 16, 2, 17761 }, >+ { 381, 16, 16, 2, 17761 }, >+ { 122, 353, 1112, 22, 2196 }, >+ { 254, 374, 775, 22, 2196 }, >+ { 378, 402, 314, 22, 2196 }, >+ { 500, 430, 244, 22, 2196 }, >+ { 629, 458, 234, 22, 2196 }, >+ { 744, 486, 224, 22, 2196 }, >+ { 861, 514, 214, 22, 2196 }, >+ { 964, 542, 204, 22, 2196 }, >+ { 1081, 804, 194, 0, 12818 }, >+ { 1184, 807, 184, 0, 12818 }, >+ { 35, 810, 174, 0, 12818 }, >+ { 168, 813, 164, 0, 12818 }, >+ { 312, 816, 154, 0, 12818 }, >+ { 436, 819, 591, 0, 12818 }, >+ { 555, 822, 2447, 0, 12818 }, >+ { 677, 825, 1106, 0, 12818 }, >+ { 128, 16, 1373, 2, 66913 }, >+ { 260, 16, 1371, 2, 66913 }, >+ { 384, 16, 1371, 2, 66913 }, >+ { 506, 16, 1369, 2, 66913 }, >+ { 632, 16, 1369, 2, 66913 }, >+ { 750, 16, 1367, 2, 66913 }, >+ { 864, 16, 1367, 2, 66913 }, >+ { 970, 16, 1365, 2, 66913 }, >+ { 1084, 16, 1365, 2, 66913 }, >+ { 1190, 16, 1363, 2, 66913 }, >+ { 39, 16, 1363, 2, 66913 }, >+ { 176, 16, 1361, 2, 66913 }, >+ { 316, 16, 1359, 2, 66913 }, >+ { 131, 16, 4021, 2, 65585 }, >+ { 269, 16, 4012, 2, 65585 }, >+ { 387, 16, 2490, 2, 65585 }, >+ { 509, 16, 2478, 2, 65585 }, >+ { 635, 16, 3974, 2, 65585 }, >+ { 753, 16, 3956, 2, 65585 }, >+ { 867, 16, 3863, 2, 65585 }, >+ { 973, 16, 3844, 2, 65585 }, >+ { 1087, 16, 3914, 2, 65585 }, >+ { 1193, 16, 3892, 2, 65585 }, >+ { 43, 16, 3745, 2, 65585 }, >+ { 180, 16, 3723, 2, 65585 }, >+ { 320, 16, 3803, 2, 65585 }, >+ { 440, 16, 3779, 2, 65585 }, >+ { 559, 16, 3627, 2, 65585 }, >+ { 681, 16, 3603, 2, 65585 }, >+ { 788, 16, 3687, 2, 65585 }, >+ { 898, 16, 3663, 2, 65585 }, >+ { 1008, 16, 3507, 2, 65585 }, >+ { 1118, 16, 3483, 2, 65585 }, >+ { 79, 16, 3567, 2, 65585 }, >+ { 212, 16, 3543, 2, 65585 }, >+ { 356, 16, 3387, 2, 65585 }, >+ { 472, 16, 3363, 2, 65585 }, >+ { 595, 16, 3447, 2, 65585 }, >+ { 713, 16, 3423, 2, 65585 }, >+ { 824, 16, 3267, 2, 65585 }, >+ { 930, 16, 3243, 2, 65585 }, >+ { 1044, 16, 3327, 2, 65585 }, >+ { 1150, 16, 3303, 2, 65585 }, >+ { 115, 16, 3172, 2, 65585 }, >+ { 244, 16, 3148, 2, 65585 }, >+ { 360, 367, 4015, 29, 5426 }, >+ { 476, 381, 2502, 29, 5426 }, >+ { 602, 395, 3992, 29, 5426 }, >+ { 720, 409, 3882, 29, 5426 }, >+ { 834, 423, 3936, 29, 5426 }, >+ { 940, 437, 3767, 29, 5426 }, >+ { 1054, 451, 3827, 29, 5426 }, >+ { 1160, 465, 3651, 29, 5426 }, >+ { 6, 479, 3711, 29, 5426 }, >+ { 151, 493, 3531, 29, 5426 }, >+ { 278, 507, 3591, 29, 5426 }, >+ { 404, 521, 3411, 29, 5426 }, >+ { 519, 535, 3471, 29, 5426 }, >+ { 645, 549, 3291, 29, 5426 }, >+ { 764, 4007, 3351, 11, 17602 }, >+ { 878, 3948, 3196, 11, 13522 }, >+ { 984, 1080, 3231, 8, 17329 }, >+ { 1098, 1080, 3101, 8, 17329 }, >+ { 55, 1080, 3136, 8, 17329 }, >+ { 204, 1080, 3031, 8, 17329 }, >+ { 332, 1080, 3066, 8, 17329 }, >+ { 452, 1080, 2961, 8, 17329 }, >+ { 571, 1080, 2996, 8, 17329 }, >+ { 693, 1080, 2891, 8, 17329 }, >+ { 800, 1080, 2926, 8, 17329 }, >+ { 910, 1080, 2820, 8, 17329 }, >+ { 1020, 1080, 2858, 8, 17329 }, >+ { 1130, 1080, 2401, 8, 17329 }, >+ { 91, 1080, 2440, 8, 17329 }, >+ { 236, 1080, 2791, 8, 17329 }, >+ { 251, 1339, 1114, 168, 1044 }, >+ { 375, 1319, 347, 168, 1044 }, >+ { 497, 1299, 142, 168, 1044 }, >+ { 626, 1279, 142, 168, 1044 }, >+ { 741, 1259, 142, 168, 1044 }, >+ { 858, 1239, 142, 168, 1044 }, >+ { 961, 1219, 142, 168, 1044 }, >+ { 1078, 1203, 142, 88, 1456 }, >+ { 1181, 1191, 142, 76, 2114 }, >+ { 32, 1179, 142, 76, 2114 }, >+ { 164, 1167, 142, 76, 2114 }, >+ { 308, 1155, 142, 76, 2114 }, >+ { 432, 1143, 142, 76, 2114 }, >+ { 551, 1131, 344, 76, 2114 }, >+ { 673, 1119, 1108, 76, 2114 }, >+ { 491, 2156, 16, 474, 4 }, >+ { 620, 2101, 16, 474, 4 }, >+ { 735, 2046, 16, 474, 4 }, >+ { 852, 1991, 16, 474, 4 }, >+ { 955, 1936, 16, 474, 4 }, >+ { 1072, 1885, 16, 423, 272 }, >+ { 1175, 1838, 16, 376, 512 }, >+ { 26, 1795, 16, 333, 720 }, >+ { 158, 1756, 16, 294, 1186 }, >+ { 301, 1717, 16, 294, 1186 }, >+ { 424, 1678, 16, 294, 1186 }, >+ { 543, 1639, 16, 294, 1186 }, >+ { 665, 1600, 16, 294, 1186 }, >+ { 1219, 4114, 16, 16, 17856 }, >+ { 263, 783, 16, 16, 8946 }, >+ { 503, 786, 16, 16, 8946 }, >+ { 747, 789, 16, 16, 8946 }, >+ { 967, 792, 16, 16, 8946 }, >+ { 1187, 795, 16, 16, 8946 }, >+ { 172, 798, 16, 16, 8946 }, >+ { 366, 1513, 1113, 63, 1570 }, >+ { 482, 4169, 2511, 63, 1570 }, >+ { 611, 1500, 778, 63, 1570 }, >+ { 726, 4156, 770, 63, 1570 }, >+ { 843, 1487, 317, 63, 1570 }, >+ { 946, 4143, 660, 63, 1570 }, >+ { 1063, 1474, 308, 63, 1570 }, >+ { 1166, 4130, 654, 63, 1570 }, >+ { 16, 1461, 302, 63, 1570 }, >+ { 134, 4117, 648, 63, 1570 }, >+ { 289, 1448, 296, 63, 1570 }, >+ { 412, 4101, 642, 63, 1570 }, >+ { 531, 1435, 290, 63, 1570 }, >+ { 653, 4088, 636, 63, 1570 }, >+ { 776, 1424, 284, 52, 1680 }, >+ { 886, 4079, 630, 43, 1872 }, >+ { 996, 1417, 278, 36, 2401 }, >+ { 1106, 4072, 624, 36, 2401 }, >+ { 67, 1410, 272, 36, 2401 }, >+ { 184, 4065, 618, 36, 2401 }, >+ { 344, 1403, 266, 36, 2401 }, >+ { 460, 4058, 612, 36, 2401 }, >+ { 583, 1396, 260, 36, 2401 }, >+ { 701, 4051, 606, 36, 2401 }, >+ { 812, 1389, 254, 36, 2401 }, >+ { 918, 4044, 600, 36, 2401 }, >+ { 1032, 1382, 765, 36, 2401 }, >+ { 1138, 4037, 2455, 36, 2401 }, >+ { 103, 1375, 2474, 36, 2401 }, >+ { 216, 4030, 1107, 36, 2401 }, >+ { 599, 1026, 4018, 212, 5314 }, >+ { 717, 1014, 3953, 212, 5314 }, >+ { 831, 1002, 4002, 212, 5314 }, >+ { 937, 990, 3909, 212, 5314 }, >+ { 1051, 978, 3909, 212, 5314 }, >+ { 1157, 966, 3798, 212, 5314 }, >+ { 3, 954, 3798, 212, 5314 }, >+ { 148, 942, 3682, 212, 5314 }, >+ { 275, 930, 3682, 212, 5314 }, >+ { 401, 918, 3562, 212, 5314 }, >+ { 515, 906, 3562, 212, 5314 }, >+ { 641, 894, 3442, 212, 5314 }, >+ { 760, 1070, 3442, 202, 17506 }, >+ { 874, 1060, 3322, 202, 13426 }, >+ { 980, 1052, 3322, 194, 14226 }, >+ { 1094, 1044, 3226, 194, 13698 }, >+ { 51, 1038, 3226, 188, 14049 }, >+ { 200, 1038, 3131, 188, 14049 }, >+ { 328, 1038, 3131, 188, 14049 }, >+ { 448, 1038, 3061, 188, 14049 }, >+ { 567, 1038, 3061, 188, 14049 }, >+ { 689, 1038, 2991, 188, 14049 }, >+ { 796, 1038, 2991, 188, 14049 }, >+ { 906, 1038, 2921, 188, 14049 }, >+ { 1016, 1038, 2921, 188, 14049 }, >+ { 1126, 1038, 2832, 188, 14049 }, >+ { 87, 1038, 2855, 188, 14049 }, >+ { 232, 1038, 2794, 188, 14049 }, >+ { 828, 2677, 4010, 276, 5170 }, >+ { 934, 2659, 3951, 276, 5170 }, >+ { 1048, 2641, 3951, 276, 5170 }, >+ { 1154, 2623, 3842, 276, 5170 }, >+ { 0, 2605, 3842, 276, 5170 }, >+ { 145, 2587, 3743, 276, 5170 }, >+ { 272, 2569, 3743, 276, 5170 }, >+ { 398, 2551, 3625, 276, 5170 }, >+ { 512, 2533, 3625, 276, 5170 }, >+ { 638, 2515, 3505, 276, 5170 }, >+ { 756, 2773, 3505, 260, 17378 }, >+ { 870, 2757, 3385, 260, 13298 }, >+ { 976, 2743, 3385, 246, 14114 }, >+ { 1090, 2729, 3265, 246, 13586 }, >+ { 47, 2717, 3265, 234, 13954 }, >+ { 196, 2705, 3170, 234, 13778 }, >+ { 324, 2695, 3170, 224, 13873 }, >+ { 444, 2695, 3099, 224, 13873 }, >+ { 563, 2695, 3099, 224, 13873 }, >+ { 685, 2695, 3029, 224, 13873 }, >+ { 792, 2695, 3029, 224, 13873 }, >+ { 902, 2695, 2959, 224, 13873 }, >+ { 1012, 2695, 2959, 224, 13873 }, >+ { 1122, 2695, 2856, 224, 13873 }, >+ { 83, 2695, 2856, 224, 13873 }, >+ { 228, 2695, 2795, 224, 13873 }, >+ { 369, 360, 2509, 22, 1956 }, >+ { 614, 388, 583, 22, 1956 }, >+ { 846, 416, 756, 22, 1956 }, >+ { 1066, 444, 747, 22, 1956 }, >+ { 19, 472, 738, 22, 1956 }, >+ { 293, 500, 729, 22, 1956 }, >+ { 535, 528, 720, 22, 1956 }, >+ { 780, 3839, 711, 3, 2336 }, >+ { 1000, 562, 702, 0, 8898 }, >+ { 71, 565, 693, 0, 8898 }, >+ { 348, 568, 684, 0, 8898 }, >+ { 587, 571, 675, 0, 8898 }, >+ { 816, 574, 666, 0, 8898 }, >+ { 1036, 577, 2460, 0, 8898 }, >+ { 107, 580, 2468, 0, 8898 }, >+ { 608, 2343, 2488, 148, 900 }, >+ { 840, 2323, 588, 148, 900 }, >+ { 1060, 2303, 588, 148, 900 }, >+ { 13, 2283, 588, 148, 900 }, >+ { 286, 2263, 588, 148, 900 }, >+ { 527, 2243, 588, 148, 900 }, >+ { 772, 2225, 588, 130, 1328 }, >+ { 992, 2211, 588, 116, 1776 }, >+ { 63, 1588, 588, 104, 2034 }, >+ { 340, 1576, 588, 104, 2034 }, >+ { 579, 1564, 588, 104, 2034 }, >+ { 808, 1552, 588, 104, 2034 }, >+ { 1028, 1540, 588, 104, 2034 }, >+ { 99, 1528, 2382, 104, 2034 }, >+}; >+ >+ // SPR Register Class... >+ static const uint16_t SPR[] = { >+ ARM_S0, ARM_S2, ARM_S4, ARM_S6, ARM_S8, ARM_S10, ARM_S12, ARM_S14, ARM_S16, ARM_S18, ARM_S20, ARM_S22, ARM_S24, ARM_S26, ARM_S28, ARM_S30, ARM_S1, ARM_S3, ARM_S5, ARM_S7, ARM_S9, ARM_S11, ARM_S13, ARM_S15, ARM_S17, ARM_S19, ARM_S21, ARM_S23, ARM_S25, ARM_S27, ARM_S29, ARM_S31, >+ }; >+ >+ // SPR Bit set. >+ static const uint8_t SPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, >+ }; >+ >+ // GPR Register Class... >+ static const uint16_t GPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, >+ }; >+ >+ // GPR Bit set. >+ static const uint8_t GPRBits[] = { >+ 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // GPRwithAPSR Register Class... >+ static const uint16_t GPRwithAPSR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, >+ }; >+ >+ // GPRwithAPSR Bit set. >+ static const uint8_t GPRwithAPSRBits[] = { >+ 0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // SPR_8 Register Class... >+ static const uint16_t SPR_8[] = { >+ ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, >+ }; >+ >+ // SPR_8 Bit set. >+ static const uint8_t SPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // GPRnopc Register Class... >+ static const uint16_t GPRnopc[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, >+ }; >+ >+ // GPRnopc Bit set. >+ static const uint8_t GPRnopcBits[] = { >+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // rGPR Register Class... >+ static const uint16_t rGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, >+ }; >+ >+ // rGPR Bit set. >+ static const uint8_t rGPRBits[] = { >+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, >+ }; >+ >+ // hGPR Register Class... >+ static const uint16_t hGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, >+ }; >+ >+ // hGPR Bit set. >+ static const uint8_t hGPRBits[] = { >+ 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // tGPR Register Class... >+ static const uint16_t tGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, >+ }; >+ >+ // tGPR Bit set. >+ static const uint8_t tGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, >+ }; >+ >+ // GPRnopc_and_hGPR Register Class... >+ static const uint16_t GPRnopc_and_hGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, >+ }; >+ >+ // GPRnopc_and_hGPR Bit set. >+ static const uint8_t GPRnopc_and_hGPRBits[] = { >+ 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // hGPR_and_rGPR Register Class... >+ static const uint16_t hGPR_and_rGPR[] = { >+ ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, >+ }; >+ >+ // hGPR_and_rGPR Bit set. >+ static const uint8_t hGPR_and_rGPRBits[] = { >+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, >+ }; >+ >+ // tcGPR Register Class... >+ static const uint16_t tcGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, >+ }; >+ >+ // tcGPR Bit set. >+ static const uint8_t tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, >+ }; >+ >+ // tGPR_and_tcGPR Register Class... >+ static const uint16_t tGPR_and_tcGPR[] = { >+ ARM_R0, ARM_R1, ARM_R2, ARM_R3, >+ }; >+ >+ // tGPR_and_tcGPR Bit set. >+ static const uint8_t tGPR_and_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // CCR Register Class... >+ static const uint16_t CCR[] = { >+ ARM_CPSR, >+ }; >+ >+ // CCR Bit set. >+ static const uint8_t CCRBits[] = { >+ 0x08, >+ }; >+ >+ // GPRsp Register Class... >+ static const uint16_t GPRsp[] = { >+ ARM_SP, >+ }; >+ >+ // GPRsp Bit set. >+ static const uint8_t GPRspBits[] = { >+ 0x00, 0x10, >+ }; >+ >+ // hGPR_and_tcGPR Register Class... >+ static const uint16_t hGPR_and_tcGPR[] = { >+ ARM_R12, >+ }; >+ >+ // hGPR_and_tcGPR Bit set. >+ static const uint8_t hGPR_and_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, >+ }; >+ >+ // DPR Register Class... >+ static const uint16_t DPR[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, >+ }; >+ >+ // DPR Bit set. >+ static const uint8_t DPRBits[] = { >+ 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, >+ }; >+ >+ // DPR_VFP2 Register Class... >+ static const uint16_t DPR_VFP2[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, >+ }; >+ >+ // DPR_VFP2 Bit set. >+ static const uint8_t DPR_VFP2Bits[] = { >+ 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DPR_8 Register Class... >+ static const uint16_t DPR_8[] = { >+ ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, >+ }; >+ >+ // DPR_8 Bit set. >+ static const uint8_t DPR_8Bits[] = { >+ 0x00, 0xc0, 0x3f, >+ }; >+ >+ // GPRPair Register Class... >+ static const uint16_t GPRPair[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, >+ }; >+ >+ // GPRPair Bit set. >+ static const uint8_t GPRPairBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, >+ }; >+ >+ // GPRPair_with_gsub_1_in_rGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_1_in_rGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, >+ }; >+ >+ // GPRPair_with_gsub_1_in_rGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_0_in_tGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // GPRPair_with_gsub_0_in_hGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_0_in_hGPR[] = { >+ ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_0_in_hGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tcGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_0_in_tcGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_0_in_tcGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, >+ }; >+ >+ // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = { >+ ARM_R8_R9, ARM_R10_R11, >+ }; >+ >+ // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, >+ }; >+ >+ // GPRPair_with_gsub_1_in_tcGPR Register Class... >+ static const uint16_t GPRPair_with_gsub_1_in_tcGPR[] = { >+ ARM_R0_R1, ARM_R2_R3, >+ }; >+ >+ // GPRPair_with_gsub_1_in_tcGPR Bit set. >+ static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, >+ }; >+ >+ // GPRPair_with_gsub_1_in_GPRsp Register Class... >+ static const uint16_t GPRPair_with_gsub_1_in_GPRsp[] = { >+ ARM_R12_SP, >+ }; >+ >+ // GPRPair_with_gsub_1_in_GPRsp Bit set. >+ static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, >+ }; >+ >+ // DPairSpc Register Class... >+ static const uint16_t DPairSpc[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, >+ }; >+ >+ // DPairSpc Bit set. >+ static const uint8_t DPairSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, >+ }; >+ >+ // DPairSpc_with_ssub_0 Register Class... >+ static const uint16_t DPairSpc_with_ssub_0[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, >+ }; >+ >+ // DPairSpc_with_ssub_0 Bit set. >+ static const uint8_t DPairSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // DPairSpc_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t DPairSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, >+ }; >+ >+ // DPairSpc_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, >+ }; >+ >+ // DPairSpc_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DPairSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, >+ }; >+ >+ // DPairSpc_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, >+ }; >+ >+ // DPairSpc_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t DPairSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, >+ }; >+ >+ // DPairSpc_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, >+ }; >+ >+ // DPair Register Class... >+ static const uint16_t DPair[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, >+ }; >+ >+ // DPair Bit set. >+ static const uint8_t DPairBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, >+ }; >+ >+ // DPair_with_ssub_0 Register Class... >+ static const uint16_t DPair_with_ssub_0[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, >+ }; >+ >+ // DPair_with_ssub_0 Bit set. >+ static const uint8_t DPair_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, >+ }; >+ >+ // QPR Register Class... >+ static const uint16_t QPR[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, >+ }; >+ >+ // QPR Bit set. >+ static const uint8_t QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, >+ }; >+ >+ // DPair_with_ssub_2 Register Class... >+ static const uint16_t DPair_with_ssub_2[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, >+ }; >+ >+ // DPair_with_ssub_2 Bit set. >+ static const uint8_t DPair_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, >+ }; >+ >+ // DPair_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DPair_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, >+ }; >+ >+ // DPair_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, >+ }; >+ >+ // QPR_VFP2 Register Class... >+ static const uint16_t QPR_VFP2[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, >+ }; >+ >+ // QPR_VFP2 Bit set. >+ static const uint8_t QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, >+ }; >+ >+ // DPair_with_dsub_1_in_DPR_8 Register Class... >+ static const uint16_t DPair_with_dsub_1_in_DPR_8[] = { >+ ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, >+ }; >+ >+ // DPair_with_dsub_1_in_DPR_8 Bit set. >+ static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, >+ }; >+ >+ // QPR_8 Register Class... >+ static const uint16_t QPR_8[] = { >+ ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, >+ }; >+ >+ // QPR_8 Bit set. >+ static const uint8_t QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // DTriple Register Class... >+ static const uint16_t DTriple[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, >+ }; >+ >+ // DTriple Bit set. >+ static const uint8_t DTripleBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, >+ }; >+ >+ // DTripleSpc Register Class... >+ static const uint16_t DTripleSpc[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, >+ }; >+ >+ // DTripleSpc Bit set. >+ static const uint8_t DTripleSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, >+ }; >+ >+ // DTripleSpc_with_ssub_0 Register Class... >+ static const uint16_t DTripleSpc_with_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, >+ }; >+ >+ // DTripleSpc_with_ssub_0 Bit set. >+ static const uint8_t DTripleSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DTriple_with_ssub_0 Register Class... >+ static const uint16_t DTriple_with_ssub_0[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, >+ }; >+ >+ // DTriple_with_ssub_0 Bit set. >+ static const uint8_t DTriple_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR Register Class... >+ static const uint16_t DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR Bit set. >+ static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, >+ }; >+ >+ // DTriple_with_ssub_2 Register Class... >+ static const uint16_t DTriple_with_ssub_2[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, >+ }; >+ >+ // DTriple_with_ssub_2 Bit set. >+ static const uint8_t DTriple_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, >+ }; >+ >+ // DTripleSpc_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t DTripleSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, >+ }; >+ >+ // DTripleSpc_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t DTriple_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, >+ }; >+ >+ // DTripleSpc_with_dsub_4_then_ssub_0 Register Class... >+ static const uint16_t DTripleSpc_with_dsub_4_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, >+ }; >+ >+ // DTripleSpc_with_dsub_4_then_ssub_0 Bit set. >+ static const uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, >+ }; >+ >+ // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DTripleSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, >+ }; >+ >+ // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DTriple_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_VFP2 Register Class... >+ static const uint16_t DTriple_with_qsub_0_in_QPR_VFP2[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_VFP2 Bit set. >+ static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, >+ }; >+ >+ // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... >+ static const uint16_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. >+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, >+ }; >+ >+ // DTriple_with_dsub_1_in_DPR_8 Register Class... >+ static const uint16_t DTriple_with_dsub_1_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, >+ }; >+ >+ // DTriple_with_dsub_1_in_DPR_8 Bit set. >+ static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Register Class... >+ static const uint16_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, >+ }; >+ >+ // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set. >+ static const uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, >+ }; >+ >+ // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t DTripleSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, >+ }; >+ >+ // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t DTriple_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, >+ }; >+ >+ // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... >+ static const uint16_t DTripleSpc_with_dsub_4_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, >+ }; >+ >+ // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. >+ static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, >+ }; >+ >+ // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_8 Register Class... >+ static const uint16_t DTriple_with_qsub_0_in_QPR_8[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, >+ }; >+ >+ // DTriple_with_qsub_0_in_QPR_8 Bit set. >+ static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_8 Register Class... >+ static const uint16_t DTriple_with_dsub_1_dsub_2_in_QPR_8[] = { >+ ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, >+ }; >+ >+ // DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set. >+ static const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class... >+ static const uint16_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = { >+ ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, >+ }; >+ >+ // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set. >+ static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, >+ }; >+ >+ // DQuadSpc Register Class... >+ static const uint16_t DQuadSpc[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, >+ }; >+ >+ // DQuadSpc Bit set. >+ static const uint8_t DQuadSpcBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, >+ }; >+ >+ // DQuadSpc_with_ssub_0 Register Class... >+ static const uint16_t DQuadSpc_with_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, >+ }; >+ >+ // DQuadSpc_with_ssub_0 Bit set. >+ static const uint8_t DQuadSpc_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, >+ }; >+ >+ // DQuadSpc_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t DQuadSpc_with_dsub_2_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, >+ }; >+ >+ // DQuadSpc_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, >+ }; >+ >+ // DQuadSpc_with_dsub_4_then_ssub_0 Register Class... >+ static const uint16_t DQuadSpc_with_dsub_4_then_ssub_0[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, >+ }; >+ >+ // DQuadSpc_with_dsub_4_then_ssub_0 Bit set. >+ static const uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, >+ }; >+ >+ // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DQuadSpc_with_dsub_0_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, >+ }; >+ >+ // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, >+ }; >+ >+ // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t DQuadSpc_with_dsub_2_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, >+ }; >+ >+ // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, >+ }; >+ >+ // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... >+ static const uint16_t DQuadSpc_with_dsub_4_in_DPR_8[] = { >+ ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, >+ }; >+ >+ // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. >+ static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, >+ }; >+ >+ // DQuad Register Class... >+ static const uint16_t DQuad[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, >+ }; >+ >+ // DQuad Bit set. >+ static const uint8_t DQuadBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, >+ }; >+ >+ // DQuad_with_ssub_0 Register Class... >+ static const uint16_t DQuad_with_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, >+ }; >+ >+ // DQuad_with_ssub_0 Bit set. >+ static const uint8_t DQuad_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // DQuad_with_ssub_2 Register Class... >+ static const uint16_t DQuad_with_ssub_2[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, >+ }; >+ >+ // DQuad_with_ssub_2 Bit set. >+ static const uint8_t DQuad_with_ssub_2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // QQPR Register Class... >+ static const uint16_t QQPR[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, >+ }; >+ >+ // QQPR Bit set. >+ static const uint8_t QQPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, >+ }; >+ >+ // DQuad_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t DQuad_with_dsub_2_then_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, >+ }; >+ >+ // DQuad_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0 Register Class... >+ static const uint16_t DQuad_with_dsub_3_then_ssub_0[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0 Bit set. >+ static const uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t DQuad_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_VFP2 Register Class... >+ static const uint16_t DQuad_with_qsub_0_in_QPR_VFP2[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_VFP2 Bit set. >+ static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, >+ }; >+ >+ // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, >+ }; >+ >+ // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class... >+ static const uint16_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set. >+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, >+ }; >+ >+ // DQuad_with_dsub_1_in_DPR_8 Register Class... >+ static const uint16_t DQuad_with_dsub_1_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, >+ }; >+ >+ // DQuad_with_dsub_1_in_DPR_8 Bit set. >+ static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_VFP2 Register Class... >+ static const uint16_t DQuad_with_qsub_1_in_QPR_VFP2[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_VFP2 Bit set. >+ static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, >+ }; >+ >+ // DQuad_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t DQuad_with_dsub_2_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, >+ }; >+ >+ // DQuad_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, >+ }; >+ >+ // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8 Register Class... >+ static const uint16_t DQuad_with_dsub_3_in_DPR_8[] = { >+ ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8 Bit set. >+ static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, >+ }; >+ >+ // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_8 Register Class... >+ static const uint16_t DQuad_with_qsub_0_in_QPR_8[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, >+ }; >+ >+ // DQuad_with_qsub_0_in_QPR_8 Bit set. >+ static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_8 Register Class... >+ static const uint16_t DQuad_with_dsub_1_dsub_2_in_QPR_8[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, >+ }; >+ >+ // DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set. >+ static const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_8 Register Class... >+ static const uint16_t DQuad_with_qsub_1_in_QPR_8[] = { >+ ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, >+ }; >+ >+ // DQuad_with_qsub_1_in_QPR_8 Bit set. >+ static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class... >+ static const uint16_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = { >+ ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, >+ }; >+ >+ // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set. >+ static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, >+ }; >+ >+ // QQQQPR Register Class... >+ static const uint16_t QQQQPR[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, >+ }; >+ >+ // QQQQPR Bit set. >+ static const uint8_t QQQQPRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, >+ }; >+ >+ // QQQQPR_with_ssub_0 Register Class... >+ static const uint16_t QQQQPR_with_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, >+ }; >+ >+ // QQQQPR_with_ssub_0 Bit set. >+ static const uint8_t QQQQPR_with_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, >+ }; >+ >+ // QQQQPR_with_dsub_2_then_ssub_0 Register Class... >+ static const uint16_t QQQQPR_with_dsub_2_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, >+ }; >+ >+ // QQQQPR_with_dsub_2_then_ssub_0 Bit set. >+ static const uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, >+ }; >+ >+ // QQQQPR_with_dsub_5_then_ssub_0 Register Class... >+ static const uint16_t QQQQPR_with_dsub_5_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, >+ }; >+ >+ // QQQQPR_with_dsub_5_then_ssub_0 Bit set. >+ static const uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, >+ }; >+ >+ // QQQQPR_with_dsub_7_then_ssub_0 Register Class... >+ static const uint16_t QQQQPR_with_dsub_7_then_ssub_0[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, >+ }; >+ >+ // QQQQPR_with_dsub_7_then_ssub_0 Bit set. >+ static const uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, >+ }; >+ >+ // QQQQPR_with_dsub_0_in_DPR_8 Register Class... >+ static const uint16_t QQQQPR_with_dsub_0_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, >+ }; >+ >+ // QQQQPR_with_dsub_0_in_DPR_8 Bit set. >+ static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, >+ }; >+ >+ // QQQQPR_with_dsub_2_in_DPR_8 Register Class... >+ static const uint16_t QQQQPR_with_dsub_2_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, >+ }; >+ >+ // QQQQPR_with_dsub_2_in_DPR_8 Bit set. >+ static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, >+ }; >+ >+ // QQQQPR_with_dsub_4_in_DPR_8 Register Class... >+ static const uint16_t QQQQPR_with_dsub_4_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, >+ }; >+ >+ // QQQQPR_with_dsub_4_in_DPR_8 Bit set. >+ static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, >+ }; >+ >+ // QQQQPR_with_dsub_6_in_DPR_8 Register Class... >+ static const uint16_t QQQQPR_with_dsub_6_in_DPR_8[] = { >+ ARM_Q0_Q1_Q2_Q3, >+ }; >+ >+ // QQQQPR_with_dsub_6_in_DPR_8 Bit set. >+ static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, >+ }; >+ >+static const MCRegisterClass ARMMCRegisterClasses[] = { >+ { "SPR", SPR, SPRBits, 32, sizeof(SPRBits), ARM_SPRRegClassID, 4, 4, 1, 1 }, >+ { "GPR", GPR, GPRBits, 16, sizeof(GPRBits), ARM_GPRRegClassID, 4, 4, 1, 1 }, >+ { "GPRwithAPSR", GPRwithAPSR, GPRwithAPSRBits, 16, sizeof(GPRwithAPSRBits), ARM_GPRwithAPSRRegClassID, 4, 4, 1, 1 }, >+ { "SPR_8", SPR_8, SPR_8Bits, 16, sizeof(SPR_8Bits), ARM_SPR_8RegClassID, 4, 4, 1, 1 }, >+ { "GPRnopc", GPRnopc, GPRnopcBits, 15, sizeof(GPRnopcBits), ARM_GPRnopcRegClassID, 4, 4, 1, 1 }, >+ { "rGPR", rGPR, rGPRBits, 14, sizeof(rGPRBits), ARM_rGPRRegClassID, 4, 4, 1, 1 }, >+ { "hGPR", hGPR, hGPRBits, 8, sizeof(hGPRBits), ARM_hGPRRegClassID, 4, 4, 1, 1 }, >+ { "tGPR", tGPR, tGPRBits, 8, sizeof(tGPRBits), ARM_tGPRRegClassID, 4, 4, 1, 1 }, >+ { "GPRnopc_and_hGPR", GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 7, sizeof(GPRnopc_and_hGPRBits), ARM_GPRnopc_and_hGPRRegClassID, 4, 4, 1, 1 }, >+ { "hGPR_and_rGPR", hGPR_and_rGPR, hGPR_and_rGPRBits, 6, sizeof(hGPR_and_rGPRBits), ARM_hGPR_and_rGPRRegClassID, 4, 4, 1, 1 }, >+ { "tcGPR", tcGPR, tcGPRBits, 5, sizeof(tcGPRBits), ARM_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { "tGPR_and_tcGPR", tGPR_and_tcGPR, tGPR_and_tcGPRBits, 4, sizeof(tGPR_and_tcGPRBits), ARM_tGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), ARM_CCRRegClassID, 4, 4, -1, 0 }, >+ { "GPRsp", GPRsp, GPRspBits, 1, sizeof(GPRspBits), ARM_GPRspRegClassID, 4, 4, 1, 1 }, >+ { "hGPR_and_tcGPR", hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1, sizeof(hGPR_and_tcGPRBits), ARM_hGPR_and_tcGPRRegClassID, 4, 4, 1, 1 }, >+ { "DPR", DPR, DPRBits, 32, sizeof(DPRBits), ARM_DPRRegClassID, 8, 8, 1, 1 }, >+ { "DPR_VFP2", DPR_VFP2, DPR_VFP2Bits, 16, sizeof(DPR_VFP2Bits), ARM_DPR_VFP2RegClassID, 8, 8, 1, 1 }, >+ { "DPR_8", DPR_8, DPR_8Bits, 8, sizeof(DPR_8Bits), ARM_DPR_8RegClassID, 8, 8, 1, 1 }, >+ { "GPRPair", GPRPair, GPRPairBits, 7, sizeof(GPRPairBits), ARM_GPRPairRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_1_in_rGPR", GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM_GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_0_in_tGPR", GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM_GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_0_in_hGPR", GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM_GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_0_in_tcGPR", GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_1_in_hGPR_and_rGPR", GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_1_in_tcGPR", GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 8, 1, 1 }, >+ { "GPRPair_with_gsub_1_in_GPRsp", GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM_GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 8, 1, 1 }, >+ { "DPairSpc", DPairSpc, DPairSpcBits, 30, sizeof(DPairSpcBits), ARM_DPairSpcRegClassID, 16, 8, 1, 1 }, >+ { "DPairSpc_with_ssub_0", DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM_DPairSpc_with_ssub_0RegClassID, 16, 8, 1, 1 }, >+ { "DPairSpc_with_dsub_2_then_ssub_0", DPairSpc_with_dsub_2_then_ssub_0, DPairSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DPairSpc_with_dsub_2_then_ssub_0Bits), ARM_DPairSpc_with_dsub_2_then_ssub_0RegClassID, 16, 8, 1, 1 }, >+ { "DPairSpc_with_dsub_0_in_DPR_8", DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 8, 1, 1 }, >+ { "DPairSpc_with_dsub_2_in_DPR_8", DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 8, 1, 1 }, >+ { "DPair", DPair, DPairBits, 31, sizeof(DPairBits), ARM_DPairRegClassID, 16, 16, 1, 1 }, >+ { "DPair_with_ssub_0", DPair_with_ssub_0, DPair_with_ssub_0Bits, 16, sizeof(DPair_with_ssub_0Bits), ARM_DPair_with_ssub_0RegClassID, 16, 16, 1, 1 }, >+ { "QPR", QPR, QPRBits, 16, sizeof(QPRBits), ARM_QPRRegClassID, 16, 16, 1, 1 }, >+ { "DPair_with_ssub_2", DPair_with_ssub_2, DPair_with_ssub_2Bits, 15, sizeof(DPair_with_ssub_2Bits), ARM_DPair_with_ssub_2RegClassID, 16, 16, 1, 1 }, >+ { "DPair_with_dsub_0_in_DPR_8", DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM_DPair_with_dsub_0_in_DPR_8RegClassID, 16, 16, 1, 1 }, >+ { "QPR_VFP2", QPR_VFP2, QPR_VFP2Bits, 8, sizeof(QPR_VFP2Bits), ARM_QPR_VFP2RegClassID, 16, 16, 1, 1 }, >+ { "DPair_with_dsub_1_in_DPR_8", DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM_DPair_with_dsub_1_in_DPR_8RegClassID, 16, 16, 1, 1 }, >+ { "QPR_8", QPR_8, QPR_8Bits, 4, sizeof(QPR_8Bits), ARM_QPR_8RegClassID, 16, 16, 1, 1 }, >+ { "DTriple", DTriple, DTripleBits, 30, sizeof(DTripleBits), ARM_DTripleRegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc", DTripleSpc, DTripleSpcBits, 28, sizeof(DTripleSpcBits), ARM_DTripleSpcRegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_ssub_0", DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM_DTripleSpc_with_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_ssub_0", DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 16, sizeof(DTriple_with_ssub_0Bits), ARM_DTriple_with_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_1_dsub_2_in_QPRBits, 15, sizeof(DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_qsub_0_in_QPR", DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_ssub_2", DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 15, sizeof(DTriple_with_ssub_2Bits), ARM_DTriple_with_ssub_2RegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_dsub_2_then_ssub_0", DTripleSpc_with_dsub_2_then_ssub_0, DTripleSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DTripleSpc_with_dsub_2_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_2_then_ssub_0", DTriple_with_dsub_2_then_ssub_0, DTriple_with_dsub_2_then_ssub_0Bits, 14, sizeof(DTriple_with_dsub_2_then_ssub_0Bits), ARM_DTriple_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_dsub_4_then_ssub_0", DTripleSpc_with_dsub_4_then_ssub_0, DTripleSpc_with_dsub_4_then_ssub_0Bits, 12, sizeof(DTripleSpc_with_dsub_4_then_ssub_0Bits), ARM_DTripleSpc_with_dsub_4_then_ssub_0RegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_dsub_0_in_DPR_8", DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_0_in_DPR_8", DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM_DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_qsub_0_in_QPR_VFP2", DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_1_dsub_2_in_QPR_VFP2", DTriple_with_dsub_1_dsub_2_in_QPR_VFP2, DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 7, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_1_in_DPR_8", DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM_DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR", DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits, 7, sizeof(DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_dsub_2_in_DPR_8", DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_2_in_DPR_8", DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM_DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTripleSpc_with_dsub_4_in_DPR_8", DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR", DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_qsub_0_in_QPR_8", DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM_DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_1_dsub_2_in_QPR_8", DTriple_with_dsub_1_dsub_2_in_QPR_8, DTriple_with_dsub_1_dsub_2_in_QPR_8Bits, 3, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID, 24, 8, 1, 1 }, >+ { "DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR", DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 }, >+ { "DQuadSpc", DQuadSpc, DQuadSpcBits, 28, sizeof(DQuadSpcBits), ARM_DQuadSpcRegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_ssub_0", DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM_DQuadSpc_with_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_dsub_2_then_ssub_0", DQuadSpc_with_dsub_2_then_ssub_0, DQuadSpc_with_dsub_2_then_ssub_0Bits, 14, sizeof(DQuadSpc_with_dsub_2_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_2_then_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_dsub_4_then_ssub_0", DQuadSpc_with_dsub_4_then_ssub_0, DQuadSpc_with_dsub_4_then_ssub_0Bits, 12, sizeof(DQuadSpc_with_dsub_4_then_ssub_0Bits), ARM_DQuadSpc_with_dsub_4_then_ssub_0RegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_dsub_0_in_DPR_8", DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_dsub_2_in_DPR_8", DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { "DQuadSpc_with_dsub_4_in_DPR_8", DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 8, 1, 1 }, >+ { "DQuad", DQuad, DQuadBits, 29, sizeof(DQuadBits), ARM_DQuadRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_ssub_0", DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 16, sizeof(DQuad_with_ssub_0Bits), ARM_DQuad_with_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_ssub_2", DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 15, sizeof(DQuad_with_ssub_2Bits), ARM_DQuad_with_ssub_2RegClassID, 32, 32, 1, 1 }, >+ { "QQPR", QQPR, QQPRBits, 15, sizeof(QQPRBits), ARM_QQPRRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_1_dsub_2_in_QPRBits, 14, sizeof(DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_2_then_ssub_0", DQuad_with_dsub_2_then_ssub_0, DQuad_with_dsub_2_then_ssub_0Bits, 14, sizeof(DQuad_with_dsub_2_then_ssub_0Bits), ARM_DQuad_with_dsub_2_then_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_3_then_ssub_0", DQuad_with_dsub_3_then_ssub_0, DQuad_with_dsub_3_then_ssub_0Bits, 13, sizeof(DQuad_with_dsub_3_then_ssub_0Bits), ARM_DQuad_with_dsub_3_then_ssub_0RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_0_in_DPR_8", DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM_DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_qsub_0_in_QPR_VFP2", DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_1_dsub_2_in_QPR_VFP2", DQuad_with_dsub_1_dsub_2_in_QPR_VFP2, DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 7, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_1_in_DPR_8", DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM_DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_qsub_1_in_QPR_VFP2", DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_2_in_DPR_8", DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM_DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 6, sizeof(DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_3_in_DPR_8", DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM_DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_qsub_0_in_QPR_8", DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM_DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_1_dsub_2_in_QPR_8", DQuad_with_dsub_1_dsub_2_in_QPR_8, DQuad_with_dsub_1_dsub_2_in_QPR_8Bits, 3, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_8Bits), ARM_DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_qsub_1_in_QPR_8", DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM_DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 32, 1, 1 }, >+ { "DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR", DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 }, >+ { "QQQQPR", QQQQPR, QQQQPRBits, 13, sizeof(QQQQPRBits), ARM_QQQQPRRegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_ssub_0", QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM_QQQQPR_with_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_2_then_ssub_0", QQQQPR_with_dsub_2_then_ssub_0, QQQQPR_with_dsub_2_then_ssub_0Bits, 7, sizeof(QQQQPR_with_dsub_2_then_ssub_0Bits), ARM_QQQQPR_with_dsub_2_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_5_then_ssub_0", QQQQPR_with_dsub_5_then_ssub_0, QQQQPR_with_dsub_5_then_ssub_0Bits, 6, sizeof(QQQQPR_with_dsub_5_then_ssub_0Bits), ARM_QQQQPR_with_dsub_5_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_7_then_ssub_0", QQQQPR_with_dsub_7_then_ssub_0, QQQQPR_with_dsub_7_then_ssub_0Bits, 5, sizeof(QQQQPR_with_dsub_7_then_ssub_0Bits), ARM_QQQQPR_with_dsub_7_then_ssub_0RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_0_in_DPR_8", QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_2_in_DPR_8", QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_4_in_DPR_8", QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+ { "QQQQPR_with_dsub_6_in_DPR_8", QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 32, 1, 1 }, >+}; >+ >+#endif // GET_REGINFO_MC_DESC >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..e64511300fb7ecc340bb534846d5e0212beeb0f4 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMGenSubtargetInfo.inc >@@ -0,0 +1,74 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Subtarget Enumeration Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_SUBTARGETINFO_ENUM >+#undef GET_SUBTARGETINFO_ENUM >+ >+#define ARM_FeatureAAPCS (1ULL << 0) >+#define ARM_FeatureAClass (1ULL << 1) >+#define ARM_FeatureAPCS (1ULL << 2) >+#define ARM_FeatureAvoidMOVsShOp (1ULL << 3) >+#define ARM_FeatureAvoidPartialCPSR (1ULL << 4) >+#define ARM_FeatureCRC (1ULL << 5) >+#define ARM_FeatureCrypto (1ULL << 6) >+#define ARM_FeatureD16 (1ULL << 7) >+#define ARM_FeatureDB (1ULL << 8) >+#define ARM_FeatureDSPThumb2 (1ULL << 9) >+#define ARM_FeatureFP16 (1ULL << 10) >+#define ARM_FeatureFPARMv8 (1ULL << 11) >+#define ARM_FeatureHWDiv (1ULL << 12) >+#define ARM_FeatureHWDivARM (1ULL << 13) >+#define ARM_FeatureHasRAS (1ULL << 14) >+#define ARM_FeatureHasSlowFPVMLx (1ULL << 15) >+#define ARM_FeatureMClass (1ULL << 16) >+#define ARM_FeatureMP (1ULL << 17) >+#define ARM_FeatureNEON (1ULL << 18) >+#define ARM_FeatureNEONForFP (1ULL << 19) >+#define ARM_FeatureNaClTrap (1ULL << 20) >+#define ARM_FeatureNoARM (1ULL << 21) >+#define ARM_FeaturePerfMon (1ULL << 22) >+#define ARM_FeaturePref32BitThumb (1ULL << 23) >+#define ARM_FeatureRClass (1ULL << 24) >+#define ARM_FeatureSlowFPBrcc (1ULL << 25) >+#define ARM_FeatureT2XtPk (1ULL << 26) >+#define ARM_FeatureThumb2 (1ULL << 27) >+#define ARM_FeatureTrustZone (1ULL << 28) >+#define ARM_FeatureVFP2 (1ULL << 29) >+#define ARM_FeatureVFP3 (1ULL << 30) >+#define ARM_FeatureVFP4 (1ULL << 31) >+#define ARM_FeatureVFPOnlySP (1ULL << 32) >+#define ARM_FeatureVMLxForwarding (1ULL << 33) >+#define ARM_FeatureVirtualization (1ULL << 34) >+#define ARM_FeatureZCZeroing (1ULL << 35) >+#define ARM_HasV4TOps (1ULL << 36) >+#define ARM_HasV5TEOps (1ULL << 37) >+#define ARM_HasV5TOps (1ULL << 38) >+#define ARM_HasV6MOps (1ULL << 39) >+#define ARM_HasV6Ops (1ULL << 40) >+#define ARM_HasV6T2Ops (1ULL << 41) >+#define ARM_HasV7Ops (1ULL << 42) >+#define ARM_HasV8Ops (1ULL << 43) >+#define ARM_ModeThumb (1ULL << 44) >+#define ARM_ProcA5 (1ULL << 45) >+#define ARM_ProcA7 (1ULL << 46) >+#define ARM_ProcA8 (1ULL << 47) >+#define ARM_ProcA9 (1ULL << 48) >+#define ARM_ProcA12 (1ULL << 49) >+#define ARM_ProcA15 (1ULL << 50) >+#define ARM_ProcA53 (1ULL << 51) >+#define ARM_ProcA57 (1ULL << 52) >+#define ARM_ProcKrait (1ULL << 53) >+#define ARM_ProcR5 (1ULL << 54) >+#define ARM_ProcSwift (1ULL << 55) >+ >+#endif // GET_SUBTARGETINFO_ENUM >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c b/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c >new file mode 100644 >index 0000000000000000000000000000000000000000..655b2ee0ecae19ee7927c72e4886b5456be308e3 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.c >@@ -0,0 +1,2649 @@ >+//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an ARM MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> // DEBUG >+#include <stdlib.h> >+#include <string.h> >+#include <platform.h> >+ >+#include "ARMInstPrinter.h" >+#include "ARMAddressingModes.h" >+#include "ARMBaseInfo.h" >+#include "ARMDisassembler.h" >+#include "../../MCInst.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "../../utils.h" >+#include "ARMMapping.h" >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "ARMGenSubtargetInfo.inc" >+ >+static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo); >+ >+// Autogenerated by tblgen. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); >+static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0); >+static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O); >+static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned); >+static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale); >+static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0); >+static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); >+static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool); >+static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O); >+static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O); >+static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O); >+static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); >+static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI); >+static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI); >+static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O); >+static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O); >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ MI->csh->doing_mem = status; >+ if (status) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; >+ } else { >+ // done, create the next operand slot >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void op_addImm(MCInst *MI, int v) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+//#define PRINT_ALIAS_INSTR >+#include "ARMGenAsmWriter.inc" >+ >+void ARM_getRegName(cs_struct *handle, int value) >+{ >+ if (value == CS_OPT_SYNTAX_NOREGNAME) { >+ handle->get_regname = getRegisterName2; >+ handle->reg_name = ARM_reg_name2;; >+ } else { >+ handle->get_regname = getRegisterName; >+ handle->reg_name = ARM_reg_name;; >+ } >+} >+ >+/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing. >+/// >+/// getSORegOffset returns an integer from 0-31, representing '32' as 0. >+static unsigned translateShiftImm(unsigned imm) >+{ >+ // lsr #32 and asr #32 exist, but should be encoded as a 0. >+ //assert((imm & ~0x1f) == 0 && "Invalid shift encoding"); >+ if (imm == 0) >+ return 32; >+ return imm; >+} >+ >+/// Prints the shift value with an immediate value. >+static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm) >+{ >+ if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) >+ return; >+ SStream_concat0(O, ", "); >+ >+ //assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0"); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc; >+ } >+ >+ if (ShOpc != ARM_AM_rrx) { >+ SStream_concat0(O, " "); >+ SStream_concat(O, "#%u", translateShiftImm(ShImm)); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm); >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm); >+ } >+ } >+} >+ >+static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) >+{ >+#ifndef CAPSTONE_DIET >+ SStream_concat0(OS, h->get_regname(RegNo)); >+#endif >+} >+ >+static const name_map insn_update_flgs[] = { >+ { ARM_INS_CMN, "cmn" }, >+ { ARM_INS_CMP, "cmp" }, >+ { ARM_INS_TEQ, "teq" }, >+ { ARM_INS_TST, "tst" }, >+ >+ { ARM_INS_ADC, "adcs" }, >+ { ARM_INS_ADD, "adds" }, >+ { ARM_INS_AND, "ands" }, >+ { ARM_INS_ASR, "asrs" }, >+ { ARM_INS_BIC, "bics" }, >+ { ARM_INS_EOR, "eors" }, >+ { ARM_INS_LSL, "lsls" }, >+ { ARM_INS_LSR, "lsrs" }, >+ { ARM_INS_MLA, "mlas" }, >+ { ARM_INS_MOV, "movs" }, >+ { ARM_INS_MUL, "muls" }, >+ { ARM_INS_MVN, "mvns" }, >+ { ARM_INS_ORN, "orns" }, >+ { ARM_INS_ORR, "orrs" }, >+ { ARM_INS_ROR, "rors" }, >+ { ARM_INS_RRX, "rrxs" }, >+ { ARM_INS_RSB, "rsbs" }, >+ { ARM_INS_RSC, "rscs" }, >+ { ARM_INS_SBC, "sbcs" }, >+ { ARM_INS_SMLAL, "smlals" }, >+ { ARM_INS_SMULL, "smulls" }, >+ { ARM_INS_SUB, "subs" }, >+ { ARM_INS_UMLAL, "umlals" }, >+ { ARM_INS_UMULL, "umulls" }, >+ >+ { ARM_INS_UADD8, "uadd8" }, >+}; >+ >+void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) >+{ >+ if (((cs_struct *)ud)->detail != CS_OPT_ON) >+ return; >+ >+ // check if this insn requests write-back >+ if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) { >+ insn->detail->arm.writeback = true; >+ } else if (mci->csh->mode & CS_MODE_THUMB) { >+ // handle some special instructions with writeback >+ //printf(">> Opcode = %u\n", mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_t2LDC2L_PRE: >+ case ARM_t2LDC2_PRE: >+ case ARM_t2LDCL_PRE: >+ case ARM_t2LDC_PRE: >+ >+ case ARM_t2LDRB_PRE: >+ case ARM_t2LDRD_PRE: >+ case ARM_t2LDRH_PRE: >+ case ARM_t2LDRSB_PRE: >+ case ARM_t2LDRSH_PRE: >+ case ARM_t2LDR_PRE: >+ >+ case ARM_t2STC2L_PRE: >+ case ARM_t2STC2_PRE: >+ case ARM_t2STCL_PRE: >+ case ARM_t2STC_PRE: >+ >+ case ARM_t2STRB_PRE: >+ case ARM_t2STRD_PRE: >+ case ARM_t2STRH_PRE: >+ case ARM_t2STR_PRE: >+ >+ case ARM_t2LDC2L_POST: >+ case ARM_t2LDC2_POST: >+ case ARM_t2LDCL_POST: >+ case ARM_t2LDC_POST: >+ >+ case ARM_t2LDRB_POST: >+ case ARM_t2LDRD_POST: >+ case ARM_t2LDRH_POST: >+ case ARM_t2LDRSB_POST: >+ case ARM_t2LDRSH_POST: >+ case ARM_t2LDR_POST: >+ >+ case ARM_t2STC2L_POST: >+ case ARM_t2STC2_POST: >+ case ARM_t2STCL_POST: >+ case ARM_t2STC_POST: >+ >+ case ARM_t2STRB_POST: >+ case ARM_t2STRD_POST: >+ case ARM_t2STRH_POST: >+ case ARM_t2STR_POST: >+ insn->detail->arm.writeback = true; >+ break; >+ } >+ } else { // ARM mode >+ // handle some special instructions with writeback >+ //printf(">> Opcode = %u\n", mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_LDC2L_PRE: >+ case ARM_LDC2_PRE: >+ case ARM_LDCL_PRE: >+ case ARM_LDC_PRE: >+ >+ case ARM_LDRD_PRE: >+ case ARM_LDRH_PRE: >+ case ARM_LDRSB_PRE: >+ case ARM_LDRSH_PRE: >+ >+ case ARM_STC2L_PRE: >+ case ARM_STC2_PRE: >+ case ARM_STCL_PRE: >+ case ARM_STC_PRE: >+ >+ case ARM_STRD_PRE: >+ case ARM_STRH_PRE: >+ >+ case ARM_LDC2L_POST: >+ case ARM_LDC2_POST: >+ case ARM_LDCL_POST: >+ case ARM_LDC_POST: >+ >+ case ARM_LDRBT_POST: >+ case ARM_LDRD_POST: >+ case ARM_LDRH_POST: >+ case ARM_LDRSB_POST: >+ case ARM_LDRSH_POST: >+ >+ case ARM_STC2L_POST: >+ case ARM_STC2_POST: >+ case ARM_STCL_POST: >+ case ARM_STC_POST: >+ >+ case ARM_STRBT_POST: >+ case ARM_STRD_POST: >+ case ARM_STRH_POST: >+ >+ case ARM_LDRB_POST_IMM: >+ case ARM_LDR_POST_IMM: >+ case ARM_LDR_POST_REG: >+ case ARM_STRB_POST_IMM: >+ case ARM_STR_POST_IMM: >+ >+ insn->detail->arm.writeback = true; >+ break; >+ } >+ } >+ >+ // check if this insn requests update flags >+ if (insn->detail->arm.update_flags == false) { >+ // some insn still update flags, regardless of tabgen info >+ unsigned int i, j; >+ >+ for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) { >+ if (insn->id == insn_update_flgs[i].id && >+ !strncmp(insn_asm, insn_update_flgs[i].name, >+ strlen(insn_update_flgs[i].name))) { >+ insn->detail->arm.update_flags = true; >+ // we have to update regs_write array as well >+ for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) { >+ if (insn->detail->regs_write[j] == 0) { >+ insn->detail->regs_write[j] = ARM_REG_CPSR; >+ break; >+ } >+ } >+ break; >+ } >+ } >+ } >+ >+ // instruction should not have invalid CC >+ if (insn->detail->arm.cc == ARM_CC_INVALID) { >+ insn->detail->arm.cc = ARM_CC_AL; >+ } >+ >+ // manual fix for some special instructions >+ // printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode); >+ switch(mci->Opcode) { >+ default: >+ break; >+ case ARM_MOVPCLR: >+ insn->detail->arm.operands[0].type = ARM_OP_REG; >+ insn->detail->arm.operands[0].reg = ARM_REG_PC; >+ insn->detail->arm.operands[1].type = ARM_OP_REG; >+ insn->detail->arm.operands[1].reg = ARM_REG_LR; >+ insn->detail->arm.op_count = 2; >+ break; >+ } >+} >+ >+void ARM_printInst(MCInst *MI, SStream *O, void *Info) >+{ >+ MCRegisterInfo *MRI = (MCRegisterInfo *)Info; >+ >+ unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode; >+ >+ switch(Opcode) { >+ // Check for HINT instructions w/ canonical names. >+ case ARM_HINT: >+ case ARM_tHINT: >+ case ARM_t2HINT: >+ switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) { >+ case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break; >+ case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break; >+ case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break; >+ case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break; >+ case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break; >+ case 5: >+ if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { >+ SStream_concat0(O, "sevl"); >+ pubOpcode = ARM_INS_SEVL; >+ break; >+ } >+ // Fallthrough for non-v8 >+ default: >+ // Anything else should just print normally. >+ printInstruction(MI, O, MRI); >+ return; >+ } >+ printPredicateOperand(MI, 1, O); >+ if (Opcode == ARM_t2HINT) >+ SStream_concat0(O, ".w"); >+ >+ MCInst_setOpcodePub(MI, pubOpcode); >+ >+ return; >+ >+ // Check for MOVs and print canonical forms, instead. >+ case ARM_MOVsr: { >+ // FIXME: Thumb variants? >+ MCOperand *Dst = MCInst_getOperand(MI, 0); >+ MCOperand *MO1 = MCInst_getOperand(MI, 1); >+ MCOperand *MO2 = MCInst_getOperand(MI, 2); >+ MCOperand *MO3 = MCInst_getOperand(MI, 3); >+ >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)))); >+ printSBitModifierOperand(MI, 6, O); >+ printPredicateOperand(MI, 4, O); >+ >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, MCOperand_getReg(Dst)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); >+ return; >+ } >+ >+ case ARM_MOVsi: { >+ // FIXME: Thumb variants? >+ MCOperand *Dst = MCInst_getOperand(MI, 0); >+ MCOperand *MO1 = MCInst_getOperand(MI, 1); >+ MCOperand *MO2 = MCInst_getOperand(MI, 2); >+ >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)))); >+ printSBitModifierOperand(MI, 5, O); >+ printPredicateOperand(MI, 3, O); >+ >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, MCOperand_getReg(Dst)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) { >+ //printAnnotation(O, Annot); >+ return; >+ } >+ >+ SStream_concat0(O, ", "); >+ tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = >+ (arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; >+ } >+ return; >+ } >+ >+ // A8.6.123 PUSH >+ case ARM_STMDB_UPD: >+ case ARM_t2STMDB_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && >+ MCInst_getNumOperands(MI) > 5) { >+ // Should only print PUSH if there are at least two registers in the list. >+ SStream_concat0(O, "push"); >+ MCInst_setOpcodePub(MI, ARM_INS_PUSH); >+ printPredicateOperand(MI, 2, O); >+ if (Opcode == ARM_t2STMDB_UPD) >+ SStream_concat0(O, ".w"); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_STR_PRE_IMM: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP && >+ MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) { >+ SStream_concat0(O, "push"); >+ MCInst_setOpcodePub(MI, ARM_INS_PUSH); >+ printPredicateOperand(MI, 4, O); >+ SStream_concat0(O, "\t{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+ return; >+ } >+ break; >+ >+ // A8.6.122 POP >+ case ARM_LDMIA_UPD: >+ case ARM_t2LDMIA_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP && >+ MCInst_getNumOperands(MI) > 5) { >+ // Should only print POP if there are at least two registers in the list. >+ SStream_concat0(O, "pop"); >+ MCInst_setOpcodePub(MI, ARM_INS_POP); >+ printPredicateOperand(MI, 2, O); >+ if (Opcode == ARM_t2LDMIA_UPD) >+ SStream_concat0(O, ".w"); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_LDR_POST_IMM: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) { >+ MCOperand *MO2 = MCInst_getOperand(MI, 4); >+ if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add && >+ getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) || >+ MCOperand_getImm(MO2) == 4) { >+ SStream_concat0(O, "pop"); >+ MCInst_setOpcodePub(MI, ARM_INS_POP); >+ printPredicateOperand(MI, 5, O); >+ SStream_concat0(O, "\t{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); >+ MI->flat_insn->detail->arm.op_count++; >+ // this instruction implicitly read/write SP register >+ MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_read_count++; >+ MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP; >+ MI->flat_insn->detail->regs_write_count++; >+ } >+ SStream_concat0(O, "}"); >+ return; >+ } >+ } >+ break; >+ >+ // A8.6.355 VPUSH >+ case ARM_VSTMSDB_UPD: >+ case ARM_VSTMDDB_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ SStream_concat0(O, "vpush"); >+ MCInst_setOpcodePub(MI, ARM_INS_VPUSH); >+ printPredicateOperand(MI, 2, O); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ // A8.6.354 VPOP >+ case ARM_VLDMSIA_UPD: >+ case ARM_VLDMDIA_UPD: >+ if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) { >+ SStream_concat0(O, "vpop"); >+ MCInst_setOpcodePub(MI, ARM_INS_VPOP); >+ printPredicateOperand(MI, 2, O); >+ SStream_concat0(O, "\t"); >+ printRegisterList(MI, 4, O); >+ return; >+ } >+ break; >+ >+ case ARM_tLDMIA: { >+ bool Writeback = true; >+ unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0)); >+ unsigned i; >+ for (i = 3; i < MCInst_getNumOperands(MI); ++i) { >+ if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg) >+ Writeback = false; >+ } >+ >+ SStream_concat0(O, "ldm"); >+ MCInst_setOpcodePub(MI, ARM_INS_LDM); >+ >+ printPredicateOperand(MI, 1, O); >+ SStream_concat0(O, "\t"); >+ printRegName(MI->csh, O, BaseReg); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ if (Writeback) { >+ MI->writeback = true; >+ SStream_concat0(O, "!"); >+ } >+ SStream_concat0(O, ", "); >+ printRegisterList(MI, 3, O); >+ return; >+ } >+ >+ // Combine 2 GPRs from disassember into a GPRPair to match with instr def. >+ // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, >+ // a single GPRPair reg operand is used in the .td file to replace the two >+ // GPRs. However, when decoding them, the two GRPs cannot be automatically >+ // expressed as a GPRPair, so we have to manually merge them. >+ // FIXME: We would really like to be able to tablegen'erate this. >+ case ARM_LDREXD: >+ case ARM_STREXD: >+ case ARM_LDAEXD: >+ case ARM_STLEXD: { >+ const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); >+ bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; >+ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); >+ if (MCRegisterClass_contains(MRC, Reg)) { >+ MCInst NewMI; >+ >+ MCInst_Init(&NewMI); >+ MCInst_setOpcode(&NewMI, Opcode); >+ >+ if (isStore) >+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); >+ >+ MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, >+ MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); >+ >+ // Copy the rest operands into NewMI. >+ for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) >+ MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); >+ >+ printInstruction(&NewMI, O, MRI); >+ return; >+ } >+ } >+ } >+ >+ //if (printAliasInstr(MI, O, MRI)) >+ // printInstruction(MI, O, MRI); >+ printInstruction(MI, O, MRI); >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ int32_t imm; >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ unsigned Reg = MCOperand_getReg(Op); >+ printRegName(MI->csh, O, Reg); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg; >+ } else { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ unsigned int opc = MCInst_getOpcode(MI); >+ >+ imm = (int32_t)MCOperand_getImm(Op); >+ >+ // relative branch only has relative offset, so we have to update it >+ // to reflect absolute address. >+ // Note: in ARM, PC is always 2 instructions ahead, so we have to >+ // add 8 in ARM mode, or 4 in Thumb mode >+ // printf(">> opcode: %u\n", MCInst_getOpcode(MI)); >+ if (ARM_rel_branch(MI->csh, opc)) { >+ uint32_t address; >+ >+ // only do this for relative branch >+ if (MI->csh->mode & CS_MODE_THUMB) { >+ address = (uint32_t)MI->address + 4; >+ if (ARM_blx_to_arm_mode(MI->csh, opc)) { >+ // here need to align down to the nearest 4-byte address >+#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width) >+ address = _ALIGN_DOWN(address, 4); >+#undef _ALIGN_DOWN >+ } >+ } else { >+ address = (uint32_t)MI->address + 8; >+ } >+ >+ imm += address; >+ >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", imm); >+ else >+ SStream_concat(O, "#%u", imm); >+ } else { >+ switch(MI->flat_insn->id) { >+ default: >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", imm); >+ else >+ SStream_concat(O, "#%u", imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ // cast first, then negate >+ SStream_concat(O, "#-0x%x", -(uint32_t)imm); >+ else >+ SStream_concat(O, "#-%u", -imm); >+ } >+ break; >+ case ARM_INS_AND: >+ case ARM_INS_ORR: >+ case ARM_INS_EOR: >+ case ARM_INS_BIC: >+ case ARM_INS_MVN: >+ // do not print number in negative form >+ if (imm >= 0 && imm <= HEX_THRESHOLD) >+ SStream_concat(O, "#%u", imm); >+ else >+ SStream_concat(O, "#0x%x", imm); >+ break; >+ } >+ } >+ >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm; >+ else { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ } >+} >+ >+static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm; >+ bool isSub; >+ SStream_concat0(O, "[pc, "); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO1); >+ isSub = OffImm < 0; >+ >+ // Special value for #-0. All others are normal. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ SStream_concat(O, "#-0x%x", -OffImm); >+ } else { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", OffImm); >+ else >+ SStream_concat(O, "#%u", OffImm); >+ } >+ >+ SStream_concat0(O, "]"); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+// so_reg is a 4-operand unit corresponding to register forms of the A5.1 >+// "Addressing Mode 1 - Data-processing operands" forms. This includes: >+// REG 0 0 - e.g. R5 >+// REG REG 0,SH_OPC - e.g. R5, ROR R3 >+// REG 0 IMM,SH_OPC - e.g. R5, LSL #3 >+static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); >+ ARM_AM_ShiftOpc ShOpc; >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3)); >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc)); >+ if (ShOpc == ARM_AM_rrx) >+ return; >+ >+ SStream_concat0(O, " "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2); >+ //assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0); >+} >+ >+static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), >+ getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #2 >+//===--------------------------------------------------------------------===// >+ >+static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ MCOperand *MO3 = MCInst_getOperand(MI, Op + 2); >+ ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ } >+ >+ if (!MCOperand_getReg(MO2)) { >+ unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3)); >+ if (tmp) { // Don't print +0. >+ subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ >+ SStream_concat0(O, ", "); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp); >+ else >+ SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3)); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ } >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ } >+ >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ } >+ >+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)), >+ getAM2Offset((unsigned int)MCOperand_getImm(MO3))); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ SStream_concat0(O, ", lsl #1]"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1; >+ } >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ printAM2PreOrOffsetIndexOp(MI, Op, O); >+} >+ >+static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2)); >+ >+ if (!MCOperand_getReg(MO1)) { >+ unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", >+ ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ else >+ SStream_concat(O, "#%s%u", >+ ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ return; >+ } >+ >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)), >+ getAM2Offset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+//===--------------------------------------------------------------------===// >+// Addressing Mode #3 >+//===--------------------------------------------------------------------===// >+ >+static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, Op+2); >+ ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3)); >+ unsigned ImmOffs; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ if (MCOperand_getReg(MO2)) { >+ SStream_concat0(O, ", "); >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(sign)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ if (!sign) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+ return; >+ } >+ >+ //If the op is sub we have to print the immediate even if it is 0 >+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3)); >+ >+ if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) { >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs); >+ else >+ SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs); >+ } >+ >+ if (MI->csh->detail) { >+ if (!sign) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs; >+ } >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ if (!MCOperand_isReg(MO1)) { // For label symbolic references. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0); >+} >+ >+static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2)); >+ unsigned ImmOffs; >+ >+ if (MCOperand_getReg(MO1)) { >+ SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted)); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ return; >+ } >+ >+ ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (ImmOffs > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ else >+ SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ >+ if (subtracted) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true; >+ } else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs; >+ >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ unsigned Imm = (unsigned int)MCOperand_getImm(MO); >+ if ((Imm & 0xff) > HEX_THRESHOLD) >+ SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); >+ else >+ SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-")); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ int Imm = (int)MCOperand_getImm(MO); >+ >+ if (((Imm & 0xff) << 2) > HEX_THRESHOLD) { >+ SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); >+ } else { >+ SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2)); >+ } >+ >+ if (MI->csh->detail) { >+ int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ unsigned ImmOffs; >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2)); >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0; >+ } >+ >+ ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2)); >+ if (AlwaysPrintImm0 || ImmOffs || subtracted == ARM_AM_sub) { >+ if (ImmOffs * 4 > HEX_THRESHOLD) >+ SStream_concat(O, ", #%s0x%x", >+ ARM_AM_getAddrOpcStr(subtracted), >+ ImmOffs * 4); >+ else >+ SStream_concat(O, ", #%s%u", >+ ARM_AM_getAddrOpcStr(subtracted), >+ ImmOffs * 4); >+ if (MI->csh->detail) { >+ if (subtracted) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4; >+ else >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4; >+ } >+ } >+ SStream_concat0(O, "]"); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ unsigned tmp; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ tmp = (unsigned int)MCOperand_getImm(MO2); >+ if (tmp) { >+ if (tmp << 3 > HEX_THRESHOLD) >+ SStream_concat(O, ":0x%x", (tmp << 3)); >+ else >+ SStream_concat(O, ":%u", (tmp << 3)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ if (MCOperand_getReg(MO) == 0) { >+ MI->writeback = true; >+ SStream_concat0(O, "!"); >+ } else { >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ uint32_t v = ~(uint32_t)MCOperand_getImm(MO); >+ int32_t lsb = CountTrailingZeros_32(v); >+ int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb; >+ >+ //assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); >+ if (lsb > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", lsb); >+ else >+ SStream_concat(O, "#%u", lsb); >+ >+ if (width > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", width); >+ else >+ SStream_concat(O, ", #%u", width); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb; >+ MI->flat_insn->detail->arm.op_count++; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARM_MB_MemBOptToString(val + 1, >+ (ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops) != 0)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1); >+ } >+} >+ >+void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); >+} >+ >+static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ bool isASR = (ShiftOp & (1 << 5)) != 0; >+ unsigned Amt = ShiftOp & 0x1f; >+ if (isASR) { >+ unsigned tmp = Amt == 0 ? 32 : Amt; >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, ", asr #0x%x", tmp); >+ else >+ SStream_concat(O, ", asr #%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp; >+ } >+ } else if (Amt) { >+ if (Amt > HEX_THRESHOLD) >+ SStream_concat(O, ", lsl #0x%x", Amt); >+ else >+ SStream_concat(O, ", lsl #%u", Amt); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt; >+ } >+ } >+} >+ >+static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm == 0) >+ return; >+ //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!"); >+ if (Imm > HEX_THRESHOLD) >+ SStream_concat(O, ", lsl #0x%x", Imm); >+ else >+ SStream_concat(O, ", lsl #%u", Imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; >+ } >+} >+ >+static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ // A shift amount of 32 is encoded as 0. >+ if (Imm == 0) >+ Imm = 32; >+ //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!"); >+ if (Imm > HEX_THRESHOLD) >+ SStream_concat(O, ", asr #0x%x", Imm); >+ else >+ SStream_concat(O, ", asr #%u", Imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm; >+ } >+} >+ >+// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct >+static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned i, e; >+ SStream_concat0(O, "{"); >+ for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) { >+ if (i != OpNum) SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, >+ MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1)); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+// SETEND BE/LE >+static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ if (MCOperand_getImm(Op)) { >+ SStream_concat0(O, "be"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ SStream_concat0(O, "le"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned int mode = (unsigned int)MCOperand_getImm(Op); >+ >+ SStream_concat0(O, ARM_PROC_IModToString(mode)); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.cps_mode = mode; >+ } >+} >+ >+static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned IFlags = (unsigned int)MCOperand_getImm(Op); >+ int i; >+ >+ for (i = 2; i >= 0; --i) >+ if (IFlags & (1 << i)) { >+ SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i)); >+ } >+ >+ if (IFlags == 0) { >+ SStream_concat0(O, "none"); >+ IFlags = ARM_CPSFLAG_NONE; >+ } >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.cps_flag = IFlags; >+ } >+} >+ >+static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNum); >+ unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4; >+ unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf; >+ unsigned reg; >+ >+ if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) { >+ unsigned SYSm = (unsigned)MCOperand_getImm(Op); >+ unsigned Opcode = MCInst_getOpcode(MI); >+ // For reads of the special registers ignore the "mask encoding" bits >+ // which are only for writes. >+ if (Opcode == ARM_t2MRS_M) >+ SYSm &= 0xff; >+ switch (SYSm) { >+ default: //llvm_unreachable("Unexpected mask value!"); >+ case 0: >+ case 0x800: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return; // with _nzcvq bits is an alias for aspr >+ case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; >+ case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; >+ case 1: >+ case 0x801: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return; // with _nzcvq bits is an alias for iapsr >+ case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return; >+ case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return; >+ case 2: >+ case 0x802: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return; // with _nzcvq bits is an alias for eapsr >+ case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return; >+ case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return; >+ case 3: >+ case 0x803: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return; // with _nzcvq bits is an alias for xpsr >+ case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return; >+ case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return; >+ case 5: >+ case 0x805: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return; >+ case 6: >+ case 0x806: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return; >+ case 7: >+ case 0x807: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return; >+ case 8: >+ case 0x808: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return; >+ case 9: >+ case 0x809: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return; >+ case 0x10: >+ case 0x810: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return; >+ case 0x11: >+ case 0x811: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return; >+ case 0x12: >+ case 0x812: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return; >+ case 0x13: >+ case 0x813: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return; >+ case 0x14: >+ case 0x814: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return; >+ } >+ } >+ >+ // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as >+ // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. >+ if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { >+ SStream_concat0(O, "apsr_"); >+ switch (Mask) { >+ default: // llvm_unreachable("Unexpected mask value!"); >+ case 4: SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return; >+ case 8: SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return; >+ case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return; >+ } >+ } >+ >+ reg = 0; >+ if (SpecRegRBit) { >+ SStream_concat0(O, "spsr"); >+ if (Mask) { >+ SStream_concat0(O, "_"); >+ if (Mask & 8) { >+ SStream_concat0(O, "f"); >+ reg += ARM_SYSREG_SPSR_F; >+ } >+ >+ if (Mask & 4) { >+ SStream_concat0(O, "s"); >+ reg += ARM_SYSREG_SPSR_S; >+ } >+ >+ if (Mask & 2) { >+ SStream_concat0(O, "x"); >+ reg += ARM_SYSREG_SPSR_X; >+ } >+ >+ if (Mask & 1) { >+ SStream_concat0(O, "c"); >+ reg += ARM_SYSREG_SPSR_C; >+ } >+ ARM_addSysReg(MI, reg); >+ } >+ } else { >+ SStream_concat0(O, "cpsr"); >+ if (Mask) { >+ SStream_concat0(O, "_"); >+ if (Mask & 8) { >+ SStream_concat0(O, "f"); >+ reg += ARM_SYSREG_CPSR_F; >+ } >+ >+ if (Mask & 4) { >+ SStream_concat0(O, "s"); >+ reg += ARM_SYSREG_CPSR_S; >+ } >+ >+ if (Mask & 2) { >+ SStream_concat0(O, "x"); >+ reg += ARM_SYSREG_CPSR_X; >+ } >+ >+ if (Mask & 1) { >+ SStream_concat0(O, "c"); >+ reg += ARM_SYSREG_CPSR_C; >+ } >+ ARM_addSysReg(MI, reg); >+ } >+ } >+} >+ >+static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ // Handle the undefined 15 CC value here for printing so we don't abort(). >+ if ((unsigned)CC == 15) { >+ SStream_concat0(O, "<und>"); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = ARM_CC_INVALID; >+ } else { >+ if (CC != ARMCC_AL) { >+ SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = CC + 1; >+ } >+} >+ >+// TODO: test this >+static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ SStream_concat0(O, ARMCC_ARMCondCodeToString(CC)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.cc = CC + 1; >+} >+ >+static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) { >+ //assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR && >+ // "Expect ARM CPSR register!"); >+ SStream_concat0(O, "s"); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.update_flags = true; >+ } >+} >+ >+static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", tmp); >+ else >+ SStream_concat(O, "%u", tmp); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; >+ } else { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ SStream_concat(O, "p%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ >+ SStream_concat(O, "c%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "{0x%x}", tmp); >+ else >+ SStream_concat(O, "{%u}", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale; >+ >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ if (OffImm < 0) >+ SStream_concat(O, "#-0x%x", -OffImm); >+ else { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", OffImm); >+ else >+ SStream_concat(O, "#%u", OffImm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4; >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned tmp = Imm == 0 ? 32 : Imm; >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // (3 - the number of trailing zeros) is the number of then / else. >+ unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1)); >+ unsigned CondBit0 = Firstcond & 1; >+ unsigned NumTZ = CountTrailingZeros_32(Mask); >+ //assert(NumTZ <= 3 && "Invalid IT mask!"); >+ unsigned Pos, e; >+ for (Pos = 3, e = NumTZ; Pos > e; --Pos) { >+ bool T = ((Mask >> Pos) & 1) == CondBit0; >+ if (T) >+ SStream_concat0(O, "t"); >+ else >+ SStream_concat0(O, "e"); >+ } >+} >+ >+static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ unsigned RegNum; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ RegNum = MCOperand_getReg(MO2); >+ if (RegNum) { >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, RegNum); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O, >+ unsigned Scale) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, Op); >+ MCOperand *MO2 = MCInst_getOperand(MI, Op + 1); >+ unsigned ImmOffs, tmp; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, Op, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ ImmOffs = (unsigned int)MCOperand_getImm(MO2); >+ if (ImmOffs) { >+ tmp = ImmOffs * Scale; >+ SStream_concat0(O, ", "); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 1); >+} >+ >+static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 2); >+} >+ >+static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 4); >+} >+ >+static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O) >+{ >+ printThumbAddrModeImm5SOperand(MI, Op, O, 4); >+} >+ >+// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2 >+// register with shift forms. >+// REG 0 0 - e.g. R5 >+// REG IMM, SH_OPC - e.g. R5, LSL #3 >+static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ >+ unsigned Reg = MCOperand_getReg(MO1); >+ printRegName(MI->csh, O, Reg); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ >+ // Print the shift opc. >+ //assert(MO2.isImm() && "Not a valid t2_so_reg value!"); >+ printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)), >+ getSORegOffset((unsigned int)MCOperand_getImm(MO2))); >+} >+ >+static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, >+ SStream *O, bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ // Special value for #-0. All others are normal. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else >+ SStream_concat(O, ", #-%u", -OffImm); >+ } else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm >= 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } else { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else >+ SStream_concat(O, ", #-%u", -OffImm); >+ } >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, >+ bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ // Don't print +0. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ >+ if (isSub) >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8s4Operand(MCInst *MI, >+ unsigned OpNum, SStream *O, bool AlwaysPrintImm0) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ int32_t OffImm; >+ bool isSub; >+ >+ if (!MCOperand_isReg(MO1)) { // For label symbolic references. >+ printOperand(MI, OpNum, O); >+ return; >+ } >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ OffImm = (int32_t)MCOperand_getImm(MO2); >+ isSub = OffImm < 0; >+ >+ //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); >+ >+ // Don't print +0. >+ if (OffImm == INT32_MIN) >+ OffImm = 0; >+ if (isSub) { >+ SStream_concat(O, ", #-0x%x", -OffImm); >+ } else if (AlwaysPrintImm0 || OffImm > 0) { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, ", #0x%x", OffImm); >+ else >+ SStream_concat(O, ", #%u", OffImm); >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm; >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ unsigned tmp; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ if (MCOperand_getImm(MO2)) { >+ SStream_concat0(O, ", "); >+ tmp = (unsigned int)MCOperand_getImm(MO2) * 4; >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp; >+ } >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printT2AddrModeImm8OffsetOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO1); >+ SStream_concat0(O, ", "); >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ if (OffImm < 0) { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%x", -OffImm); >+ else >+ SStream_concat(O, "#-%u", -OffImm); >+ } else { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", OffImm); >+ else >+ SStream_concat(O, "#%u", OffImm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ int32_t OffImm = (int32_t)MCOperand_getImm(MO1); >+ >+ //assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); >+ >+ SStream_concat0(O, ", "); >+ if (OffImm == INT32_MIN) { >+ SStream_concat0(O, "#-0"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } else { >+ if (OffImm < 0) { >+ if (OffImm < -HEX_THRESHOLD) >+ SStream_concat(O, "#-0x%x", -OffImm); >+ else >+ SStream_concat(O, "#-%u", -OffImm); >+ } else { >+ if (OffImm > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", OffImm); >+ else >+ SStream_concat(O, "#%u", OffImm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ } >+} >+ >+static void printT2AddrModeSoRegOperand(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO1 = MCInst_getOperand(MI, OpNum); >+ MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); >+ MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2); >+ unsigned ShAmt; >+ >+ SStream_concat0(O, "["); >+ set_mem_access(MI, true); >+ printRegName(MI->csh, O, MCOperand_getReg(MO1)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1); >+ >+ //assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!"); >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MO2)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2); >+ >+ ShAmt = (unsigned int)MCOperand_getImm(MO3); >+ if (ShAmt) { >+ //assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); >+ SStream_concat0(O, ", lsl "); >+ SStream_concat(O, "#%d", ShAmt); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt; >+ } >+ } >+ >+ SStream_concat0(O, "]"); >+ set_mem_access(MI, false); >+} >+ >+static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, OpNum); >+ >+#if defined(_KERNEL_MODE) >+ // Issue #681: Windows kernel does not support formatting float point >+ SStream_concat(O, "#<float_point_unsupported>"); >+#else >+ SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO))); >+#endif >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ unsigned EltBits; >+ uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits); >+ if (Val > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%"PRIx64, Val); >+ else >+ SStream_concat(O, "#%"PRIu64, Val); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm + 1 > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", Imm + 1); >+ else >+ SStream_concat(O, "#%u", Imm + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (Imm == 0) >+ return; >+ SStream_concat0(O, ", ror #"); >+ switch (Imm) { >+ default: //assert (0 && "illegal ror immediate!"); >+ case 1: SStream_concat0(O, "8"); break; >+ case 2: SStream_concat0(O, "16"); break; >+ case 3: SStream_concat0(O, "24"); break; >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8; >+ } >+} >+ >+static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp; >+ >+ tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp; >+ >+ tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "#0x%x", tmp); >+ else >+ SStream_concat(O, "#%u", tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); >+ if (tmp > HEX_THRESHOLD) >+ SStream_concat(O, "[0x%x]",tmp); >+ else >+ SStream_concat(O, "[%u]",tmp); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp; >+ } >+} >+ >+static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListTwo(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, >+ SStream *O, MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListTwoSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O, MCRegisterInfo *MRI) >+{ >+ unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); >+ unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, Reg0); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, Reg1); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListThreeSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListFourSpacedAllLanes(MCInst *MI, >+ unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[], "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "[]}"); >+} >+ >+static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) >+{ >+ // Normally, it's not safe to use register enum values directly with >+ // addition to get the next register, but for VFP registers, the >+ // sort order is guaranteed because they're all of the form D<n>. >+ SStream_concat0(O, "{"); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum))); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, ", "); >+ printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+ SStream_concat0(O, "}"); >+} >+ >+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.vector_data = vd; >+ } >+} >+ >+void ARM_addVectorDataSize(MCInst *MI, int size) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.vector_size = size; >+ } >+} >+ >+void ARM_addReg(MCInst *MI, int reg) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+void ARM_addUserMode(MCInst *MI) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.usermode = true; >+ } >+} >+ >+void ARM_addSysReg(MCInst *MI, arm_sysreg reg) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG; >+ MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg; >+ MI->flat_insn->detail->arm.op_count++; >+ } >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h b/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h >new file mode 100644 >index 0000000000000000000000000000000000000000..169d6109d4570cb51cda92b8018ef2e8d785e9e9 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMInstPrinter.h >@@ -0,0 +1,43 @@ >+//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an ARM MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_ARMINSTPRINTER_H >+#define CS_ARMINSTPRINTER_H >+ >+#include "../../MCInst.h" >+#include "../../MCRegisterInfo.h" >+#include "../../SStream.h" >+ >+void ARM_printInst(MCInst *MI, SStream *O, void *Info); >+void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci); >+ >+// setup handle->get_regname >+void ARM_getRegName(cs_struct *handle, int value); >+ >+// specify vector data type for vector instructions >+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd); >+ >+void ARM_addVectorDataSize(MCInst *MI, int size); >+ >+void ARM_addReg(MCInst *MI, int reg); >+ >+// load usermode registers (LDM, STM) >+void ARM_addUserMode(MCInst *MI); >+ >+// sysreg for MRS/MSR >+void ARM_addSysReg(MCInst *MI, arm_sysreg reg); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c b/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c >new file mode 100644 >index 0000000000000000000000000000000000000000..298e0c41001dd84610b4a56f5e9c6816a34cf848 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.c >@@ -0,0 +1,14142 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "../../cs_priv.h" >+ >+#include "ARMMapping.h" >+ >+#define GET_INSTRINFO_ENUM >+#include "ARMGenInstrInfo.inc" >+ >+#ifndef CAPSTONE_DIET >+static const name_map reg_name_maps[] = { >+ { ARM_REG_INVALID, NULL }, >+ { ARM_REG_APSR, "apsr"}, >+ { ARM_REG_APSR_NZCV, "apsr_nzcv"}, >+ { ARM_REG_CPSR, "cpsr"}, >+ { ARM_REG_FPEXC, "fpexc"}, >+ { ARM_REG_FPINST, "fpinst"}, >+ { ARM_REG_FPSCR, "fpscr"}, >+ { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, >+ { ARM_REG_FPSID, "fpsid"}, >+ { ARM_REG_ITSTATE, "itstate"}, >+ { ARM_REG_LR, "lr"}, >+ { ARM_REG_PC, "pc"}, >+ { ARM_REG_SP, "sp"}, >+ { ARM_REG_SPSR, "spsr"}, >+ { ARM_REG_D0, "d0"}, >+ { ARM_REG_D1, "d1"}, >+ { ARM_REG_D2, "d2"}, >+ { ARM_REG_D3, "d3"}, >+ { ARM_REG_D4, "d4"}, >+ { ARM_REG_D5, "d5"}, >+ { ARM_REG_D6, "d6"}, >+ { ARM_REG_D7, "d7"}, >+ { ARM_REG_D8, "d8"}, >+ { ARM_REG_D9, "d9"}, >+ { ARM_REG_D10, "d10"}, >+ { ARM_REG_D11, "d11"}, >+ { ARM_REG_D12, "d12"}, >+ { ARM_REG_D13, "d13"}, >+ { ARM_REG_D14, "d14"}, >+ { ARM_REG_D15, "d15"}, >+ { ARM_REG_D16, "d16"}, >+ { ARM_REG_D17, "d17"}, >+ { ARM_REG_D18, "d18"}, >+ { ARM_REG_D19, "d19"}, >+ { ARM_REG_D20, "d20"}, >+ { ARM_REG_D21, "d21"}, >+ { ARM_REG_D22, "d22"}, >+ { ARM_REG_D23, "d23"}, >+ { ARM_REG_D24, "d24"}, >+ { ARM_REG_D25, "d25"}, >+ { ARM_REG_D26, "d26"}, >+ { ARM_REG_D27, "d27"}, >+ { ARM_REG_D28, "d28"}, >+ { ARM_REG_D29, "d29"}, >+ { ARM_REG_D30, "d30"}, >+ { ARM_REG_D31, "d31"}, >+ { ARM_REG_FPINST2, "fpinst2"}, >+ { ARM_REG_MVFR0, "mvfr0"}, >+ { ARM_REG_MVFR1, "mvfr1"}, >+ { ARM_REG_MVFR2, "mvfr2"}, >+ { ARM_REG_Q0, "q0"}, >+ { ARM_REG_Q1, "q1"}, >+ { ARM_REG_Q2, "q2"}, >+ { ARM_REG_Q3, "q3"}, >+ { ARM_REG_Q4, "q4"}, >+ { ARM_REG_Q5, "q5"}, >+ { ARM_REG_Q6, "q6"}, >+ { ARM_REG_Q7, "q7"}, >+ { ARM_REG_Q8, "q8"}, >+ { ARM_REG_Q9, "q9"}, >+ { ARM_REG_Q10, "q10"}, >+ { ARM_REG_Q11, "q11"}, >+ { ARM_REG_Q12, "q12"}, >+ { ARM_REG_Q13, "q13"}, >+ { ARM_REG_Q14, "q14"}, >+ { ARM_REG_Q15, "q15"}, >+ { ARM_REG_R0, "r0"}, >+ { ARM_REG_R1, "r1"}, >+ { ARM_REG_R2, "r2"}, >+ { ARM_REG_R3, "r3"}, >+ { ARM_REG_R4, "r4"}, >+ { ARM_REG_R5, "r5"}, >+ { ARM_REG_R6, "r6"}, >+ { ARM_REG_R7, "r7"}, >+ { ARM_REG_R8, "r8"}, >+ { ARM_REG_R9, "sb"}, >+ { ARM_REG_R10, "sl"}, >+ { ARM_REG_R11, "fp"}, >+ { ARM_REG_R12, "ip"}, >+ { ARM_REG_S0, "s0"}, >+ { ARM_REG_S1, "s1"}, >+ { ARM_REG_S2, "s2"}, >+ { ARM_REG_S3, "s3"}, >+ { ARM_REG_S4, "s4"}, >+ { ARM_REG_S5, "s5"}, >+ { ARM_REG_S6, "s6"}, >+ { ARM_REG_S7, "s7"}, >+ { ARM_REG_S8, "s8"}, >+ { ARM_REG_S9, "s9"}, >+ { ARM_REG_S10, "s10"}, >+ { ARM_REG_S11, "s11"}, >+ { ARM_REG_S12, "s12"}, >+ { ARM_REG_S13, "s13"}, >+ { ARM_REG_S14, "s14"}, >+ { ARM_REG_S15, "s15"}, >+ { ARM_REG_S16, "s16"}, >+ { ARM_REG_S17, "s17"}, >+ { ARM_REG_S18, "s18"}, >+ { ARM_REG_S19, "s19"}, >+ { ARM_REG_S20, "s20"}, >+ { ARM_REG_S21, "s21"}, >+ { ARM_REG_S22, "s22"}, >+ { ARM_REG_S23, "s23"}, >+ { ARM_REG_S24, "s24"}, >+ { ARM_REG_S25, "s25"}, >+ { ARM_REG_S26, "s26"}, >+ { ARM_REG_S27, "s27"}, >+ { ARM_REG_S28, "s28"}, >+ { ARM_REG_S29, "s29"}, >+ { ARM_REG_S30, "s30"}, >+ { ARM_REG_S31, "s31"}, >+}; >+static const name_map reg_name_maps2[] = { >+ { ARM_REG_INVALID, NULL }, >+ { ARM_REG_APSR, "apsr"}, >+ { ARM_REG_APSR_NZCV, "apsr_nzcv"}, >+ { ARM_REG_CPSR, "cpsr"}, >+ { ARM_REG_FPEXC, "fpexc"}, >+ { ARM_REG_FPINST, "fpinst"}, >+ { ARM_REG_FPSCR, "fpscr"}, >+ { ARM_REG_FPSCR_NZCV, "fpscr_nzcv"}, >+ { ARM_REG_FPSID, "fpsid"}, >+ { ARM_REG_ITSTATE, "itstate"}, >+ { ARM_REG_LR, "lr"}, >+ { ARM_REG_PC, "pc"}, >+ { ARM_REG_SP, "sp"}, >+ { ARM_REG_SPSR, "spsr"}, >+ { ARM_REG_D0, "d0"}, >+ { ARM_REG_D1, "d1"}, >+ { ARM_REG_D2, "d2"}, >+ { ARM_REG_D3, "d3"}, >+ { ARM_REG_D4, "d4"}, >+ { ARM_REG_D5, "d5"}, >+ { ARM_REG_D6, "d6"}, >+ { ARM_REG_D7, "d7"}, >+ { ARM_REG_D8, "d8"}, >+ { ARM_REG_D9, "d9"}, >+ { ARM_REG_D10, "d10"}, >+ { ARM_REG_D11, "d11"}, >+ { ARM_REG_D12, "d12"}, >+ { ARM_REG_D13, "d13"}, >+ { ARM_REG_D14, "d14"}, >+ { ARM_REG_D15, "d15"}, >+ { ARM_REG_D16, "d16"}, >+ { ARM_REG_D17, "d17"}, >+ { ARM_REG_D18, "d18"}, >+ { ARM_REG_D19, "d19"}, >+ { ARM_REG_D20, "d20"}, >+ { ARM_REG_D21, "d21"}, >+ { ARM_REG_D22, "d22"}, >+ { ARM_REG_D23, "d23"}, >+ { ARM_REG_D24, "d24"}, >+ { ARM_REG_D25, "d25"}, >+ { ARM_REG_D26, "d26"}, >+ { ARM_REG_D27, "d27"}, >+ { ARM_REG_D28, "d28"}, >+ { ARM_REG_D29, "d29"}, >+ { ARM_REG_D30, "d30"}, >+ { ARM_REG_D31, "d31"}, >+ { ARM_REG_FPINST2, "fpinst2"}, >+ { ARM_REG_MVFR0, "mvfr0"}, >+ { ARM_REG_MVFR1, "mvfr1"}, >+ { ARM_REG_MVFR2, "mvfr2"}, >+ { ARM_REG_Q0, "q0"}, >+ { ARM_REG_Q1, "q1"}, >+ { ARM_REG_Q2, "q2"}, >+ { ARM_REG_Q3, "q3"}, >+ { ARM_REG_Q4, "q4"}, >+ { ARM_REG_Q5, "q5"}, >+ { ARM_REG_Q6, "q6"}, >+ { ARM_REG_Q7, "q7"}, >+ { ARM_REG_Q8, "q8"}, >+ { ARM_REG_Q9, "q9"}, >+ { ARM_REG_Q10, "q10"}, >+ { ARM_REG_Q11, "q11"}, >+ { ARM_REG_Q12, "q12"}, >+ { ARM_REG_Q13, "q13"}, >+ { ARM_REG_Q14, "q14"}, >+ { ARM_REG_Q15, "q15"}, >+ { ARM_REG_R0, "r0"}, >+ { ARM_REG_R1, "r1"}, >+ { ARM_REG_R2, "r2"}, >+ { ARM_REG_R3, "r3"}, >+ { ARM_REG_R4, "r4"}, >+ { ARM_REG_R5, "r5"}, >+ { ARM_REG_R6, "r6"}, >+ { ARM_REG_R7, "r7"}, >+ { ARM_REG_R8, "r8"}, >+ { ARM_REG_R9, "r9"}, >+ { ARM_REG_R10, "r10"}, >+ { ARM_REG_R11, "r11"}, >+ { ARM_REG_R12, "r12"}, >+ { ARM_REG_S0, "s0"}, >+ { ARM_REG_S1, "s1"}, >+ { ARM_REG_S2, "s2"}, >+ { ARM_REG_S3, "s3"}, >+ { ARM_REG_S4, "s4"}, >+ { ARM_REG_S5, "s5"}, >+ { ARM_REG_S6, "s6"}, >+ { ARM_REG_S7, "s7"}, >+ { ARM_REG_S8, "s8"}, >+ { ARM_REG_S9, "s9"}, >+ { ARM_REG_S10, "s10"}, >+ { ARM_REG_S11, "s11"}, >+ { ARM_REG_S12, "s12"}, >+ { ARM_REG_S13, "s13"}, >+ { ARM_REG_S14, "s14"}, >+ { ARM_REG_S15, "s15"}, >+ { ARM_REG_S16, "s16"}, >+ { ARM_REG_S17, "s17"}, >+ { ARM_REG_S18, "s18"}, >+ { ARM_REG_S19, "s19"}, >+ { ARM_REG_S20, "s20"}, >+ { ARM_REG_S21, "s21"}, >+ { ARM_REG_S22, "s22"}, >+ { ARM_REG_S23, "s23"}, >+ { ARM_REG_S24, "s24"}, >+ { ARM_REG_S25, "s25"}, >+ { ARM_REG_S26, "s26"}, >+ { ARM_REG_S27, "s27"}, >+ { ARM_REG_S28, "s28"}, >+ { ARM_REG_S29, "s29"}, >+ { ARM_REG_S30, "s30"}, >+ { ARM_REG_S31, "s31"}, >+}; >+#endif >+ >+const char *ARM_reg_name(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= ARM_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+const char *ARM_reg_name2(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= ARM_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps2[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+static const insn_map insns[] = { >+ // dummy item >+ { >+ 0, 0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ >+ { >+ ARM_ADCri, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADCrr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADCrsi, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADCrsr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADDri, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADDrsi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADDrsr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_AESD, ARM_INS_AESD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_AESE, ARM_INS_AESE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_AESIMC, ARM_INS_AESIMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_AESMC, ARM_INS_AESMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ANDri, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ANDrr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ANDrsi, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ANDrsr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BFC, ARM_INS_BFC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BFI, ARM_INS_BFI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BICri, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BICrr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BICrsi, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BICrsr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BKPT, ARM_INS_BKPT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_BL, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_BLX, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_BLX_pred, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_BLXi, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_BL_pred, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_BX, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_BXJ, ARM_INS_BXJ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_BX_RET, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_BX_pred, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_Bcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_CDP, ARM_INS_CDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CDP2, ARM_INS_CDP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CLREX, ARM_INS_CLREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CLZ, ARM_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMNri, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMNzrr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMNzrsi, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMNzrsr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMPri, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMPrr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMPrsi, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CMPrsr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CPS1p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CPS2p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CPS3p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32B, ARM_INS_CRC32B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32CB, ARM_INS_CRC32CB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32CH, ARM_INS_CRC32CH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32CW, ARM_INS_CRC32CW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32H, ARM_INS_CRC32H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_CRC32W, ARM_INS_CRC32W, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_DBG, ARM_INS_DBG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_DMB, ARM_INS_DMB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_DSB, ARM_INS_DSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_EORri, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_EORrr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_EORrsi, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_EORrsr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FCONSTD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FCONSTS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FLDMXIA, ARM_INS_FLDMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FMSTAT, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FSTMXIA, ARM_INS_FSTMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_HINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_HLT, ARM_INS_HLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ISB, ARM_INS_ISB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDA, ARM_INS_LDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAB, ARM_INS_LDAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAEX, ARM_INS_LDAEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAEXB, ARM_INS_LDAEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAEXD, ARM_INS_LDAEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAEXH, ARM_INS_LDAEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDAH, ARM_INS_LDAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2L_OFFSET, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2L_OPTION, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2L_POST, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2L_PRE, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2_OFFSET, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2_OPTION, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2_POST, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC2_PRE, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDCL_OFFSET, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDCL_OPTION, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDCL_POST, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDCL_PRE, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC_OFFSET, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC_OPTION, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC_POST, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDC_PRE, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMDA, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMDA_UPD, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMIB, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDMIB_UPD, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRBT_POST_REG, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRB_POST_IMM, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRB_POST_REG, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRB_PRE_IMM, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRB_PRE_REG, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRBi12, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRBrs, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRD, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRD_POST, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRD_PRE, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDREX, ARM_INS_LDREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDREXB, ARM_INS_LDREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDREXD, ARM_INS_LDREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDREXH, ARM_INS_LDREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRH, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRHTi, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRHTr, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRH_POST, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRH_PRE, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSB, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSBTi, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSBTr, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSB_POST, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSB_PRE, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSH, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSHTi, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSHTr, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSH_POST, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRSH_PRE, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRT_POST_IMM, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRT_POST_REG, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDR_POST_IMM, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDR_POST_REG, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDR_PRE_IMM, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDR_PRE_REG, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRcp, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRi12, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_LDRrs, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MCR, ARM_INS_MCR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MCR2, ARM_INS_MCR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MCRR, ARM_INS_MCRR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MCRR2, ARM_INS_MCRR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MLA, ARM_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MLS, ARM_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVPCLR, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVTi16, ARM_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVi16, ARM_INS_MOVW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVr_TC, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVsi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MOVsr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRC, ARM_INS_MRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRC2, ARM_INS_MRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRRC, ARM_INS_MRRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRRC2, ARM_INS_MRRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRS, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MRSsys, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MSR, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MSRi, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MVNi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MVNr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MVNsi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_MVNsr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ORRri, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ORRrr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ORRrsi, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_ORRrsr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PKHBT, ARM_INS_PKHBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PKHTB, ARM_INS_PKHTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLDWi12, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLDWrs, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLDi12, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLDrs, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLIi12, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_PLIrs, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QADD, ARM_INS_QADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QADD16, ARM_INS_QADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QADD8, ARM_INS_QADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QASX, ARM_INS_QASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QDADD, ARM_INS_QDADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QDSUB, ARM_INS_QDSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QSAX, ARM_INS_QSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QSUB, ARM_INS_QSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QSUB16, ARM_INS_QSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_QSUB8, ARM_INS_QSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RBIT, ARM_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_REV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_REV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_REVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEDA, ARM_INS_RFEDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEDA_UPD, ARM_INS_RFEDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEDB, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEDB_UPD, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEIA, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEIA_UPD, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEIB, ARM_INS_RFEIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RFEIB_UPD, ARM_INS_RFEIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSBri, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSBrr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSBrsi, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSBrsr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSCri, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSCrr, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSCrsi, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_RSCrsr, ARM_INS_RSC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SADD16, ARM_INS_SADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SADD8, ARM_INS_SADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SASX, ARM_INS_SASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SBCri, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SBCrr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SBCrsi, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SBCrsr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SBFX, ARM_INS_SBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SDIV, ARM_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SEL, ARM_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SETEND, ARM_INS_SETEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1C, ARM_INS_SHA1C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1H, ARM_INS_SHA1H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1M, ARM_INS_SHA1M, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1P, ARM_INS_SHA1P, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1SU0, ARM_INS_SHA1SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA1SU1, ARM_INS_SHA1SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA256H, ARM_INS_SHA256H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA256H2, ARM_INS_SHA256H2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA256SU0, ARM_INS_SHA256SU0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHA256SU1, ARM_INS_SHA256SU1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHADD16, ARM_INS_SHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHADD8, ARM_INS_SHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHASX, ARM_INS_SHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHSAX, ARM_INS_SHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHSUB16, ARM_INS_SHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SHSUB8, ARM_INS_SHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMC, ARM_INS_SMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLABB, ARM_INS_SMLABB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLABT, ARM_INS_SMLABT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLAD, ARM_INS_SMLAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLADX, ARM_INS_SMLADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLAL, ARM_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALBB, ARM_INS_SMLALBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALBT, ARM_INS_SMLALBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALD, ARM_INS_SMLALD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALDX, ARM_INS_SMLALDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALTB, ARM_INS_SMLALTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLALTT, ARM_INS_SMLALTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLATB, ARM_INS_SMLATB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLATT, ARM_INS_SMLATT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLAWB, ARM_INS_SMLAWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLAWT, ARM_INS_SMLAWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLSD, ARM_INS_SMLSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLSDX, ARM_INS_SMLSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLSLD, ARM_INS_SMLSLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMLSLDX, ARM_INS_SMLSLDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMLA, ARM_INS_SMMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMLAR, ARM_INS_SMMLAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMLS, ARM_INS_SMMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMLSR, ARM_INS_SMMLSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMUL, ARM_INS_SMMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMMULR, ARM_INS_SMMULR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMUAD, ARM_INS_SMUAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMUADX, ARM_INS_SMUADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULBB, ARM_INS_SMULBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULBT, ARM_INS_SMULBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULL, ARM_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULTB, ARM_INS_SMULTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULTT, ARM_INS_SMULTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULWB, ARM_INS_SMULWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMULWT, ARM_INS_SMULWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMUSD, ARM_INS_SMUSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SMUSDX, ARM_INS_SMUSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSDA, ARM_INS_SRSDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSDA_UPD, ARM_INS_SRSDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSDB, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSDB_UPD, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSIA, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSIA_UPD, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSIB, ARM_INS_SRSIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SRSIB_UPD, ARM_INS_SRSIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SSAT, ARM_INS_SSAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SSAT16, ARM_INS_SSAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SSAX, ARM_INS_SSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SSUB16, ARM_INS_SSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SSUB8, ARM_INS_SSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2L_OFFSET, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2L_OPTION, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2L_POST, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2L_PRE, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2_OFFSET, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2_OPTION, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2_POST, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC2_PRE, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STCL_OFFSET, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STCL_OPTION, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STCL_POST, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STCL_PRE, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC_OFFSET, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC_OPTION, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC_POST, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STC_PRE, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STL, ARM_INS_STL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLB, ARM_INS_STLB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLEX, ARM_INS_STLEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLEXB, ARM_INS_STLEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLEXD, ARM_INS_STLEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLEXH, ARM_INS_STLEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STLH, ARM_INS_STLH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMDA, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMDA_UPD, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMIB, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STMIB_UPD, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRBT_POST_IMM, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRBT_POST_REG, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRB_POST_IMM, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRB_POST_REG, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRB_PRE_IMM, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRB_PRE_REG, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRBi12, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRBrs, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRD, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRD_POST, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRD_PRE, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STREX, ARM_INS_STREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STREXB, ARM_INS_STREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STREXD, ARM_INS_STREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STREXH, ARM_INS_STREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRH, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRHTi, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRHTr, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRH_POST, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRH_PRE, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRT_POST_IMM, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRT_POST_REG, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STR_POST_IMM, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STR_POST_REG, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STR_PRE_IMM, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STR_PRE_REG, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRi12, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_STRrs, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SUBri, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SUBrsi, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SUBrsr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SVC, ARM_INS_SVC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SWP, ARM_INS_SWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SWPB, ARM_INS_SWPB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTAB, ARM_INS_SXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTAB16, ARM_INS_SXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTAH, ARM_INS_SXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTB16, ARM_INS_SXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_SXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TEQri, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TEQrr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TEQrsi, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TEQrsr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TRAP, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TRAPNaCl, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TSTri, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TSTrr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TSTrsi, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_TSTrsr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UADD16, ARM_INS_UADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UADD8, ARM_INS_UADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UASX, ARM_INS_UASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UBFX, ARM_INS_UBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UDIV, ARM_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHADD16, ARM_INS_UHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHADD8, ARM_INS_UHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHASX, ARM_INS_UHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHSAX, ARM_INS_UHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHSUB16, ARM_INS_UHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UHSUB8, ARM_INS_UHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UMAAL, ARM_INS_UMAAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UMLAL, ARM_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UMULL, ARM_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQADD16, ARM_INS_UQADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQADD8, ARM_INS_UQADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQASX, ARM_INS_UQASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQSAX, ARM_INS_UQSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQSUB16, ARM_INS_UQSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UQSUB8, ARM_INS_UQSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USAD8, ARM_INS_USAD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USADA8, ARM_INS_USADA8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USAT, ARM_INS_USAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USAT16, ARM_INS_USAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USAX, ARM_INS_USAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USUB16, ARM_INS_USUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_USUB8, ARM_INS_USUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTAB, ARM_INS_UXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTAB16, ARM_INS_UXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTAH, ARM_INS_UXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTB16, ARM_INS_UXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_UXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALsv2i64, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALsv4i32, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALsv8i16, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALuv2i64, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALuv4i32, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABALuv8i16, ARM_INS_VABAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv16i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv2i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv4i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv4i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv8i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAsv8i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv16i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv2i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv4i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv4i32, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv8i16, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABAuv8i8, ARM_INS_VABA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLsv2i64, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLsv4i32, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLsv8i16, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLuv2i64, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLuv4i32, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDLuv8i16, ARM_INS_VABDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDfd, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDfq, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv16i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv2i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv4i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv4i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv8i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDsv8i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv16i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv2i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv4i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv4i32, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv8i16, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABDuv8i8, ARM_INS_VABD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSD, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSS, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSfd, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSfq, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv16i8, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv2i32, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv4i16, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv4i32, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv8i16, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VABSv8i8, ARM_INS_VABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VACGEd, ARM_INS_VACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VACGEq, ARM_INS_VACGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VACGTd, ARM_INS_VACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VACGTq, ARM_INS_VACGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDD, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDHNv2i32, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDHNv4i16, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDHNv8i8, ARM_INS_VADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLsv2i64, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLsv4i32, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLsv8i16, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLuv2i64, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLuv4i32, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDLuv8i16, ARM_INS_VADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDS, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWsv2i64, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWsv4i32, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWsv8i16, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWuv2i64, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWuv4i32, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDWuv8i16, ARM_INS_VADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDfd, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDfq, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv16i8, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv1i64, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv2i32, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv2i64, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv4i16, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv4i32, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv8i16, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VADDv8i8, ARM_INS_VADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VANDd, ARM_INS_VAND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VANDq, ARM_INS_VAND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICd, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICiv2i32, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICiv4i16, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICiv4i32, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICiv8i16, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBICq, ARM_INS_VBIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBIFd, ARM_INS_VBIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBIFq, ARM_INS_VBIF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBITd, ARM_INS_VBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBITq, ARM_INS_VBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBSLd, ARM_INS_VBSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VBSLq, ARM_INS_VBSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQfd, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQfq, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv16i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv2i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv4i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv4i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv8i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQv8i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv16i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv2f32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv2i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv4f32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv4i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv4i32, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv8i16, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCEQzv8i8, ARM_INS_VCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEfd, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEfq, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEsv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEuv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv16i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv2f32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv2i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv4f32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv4i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv4i32, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv8i16, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGEzv8i8, ARM_INS_VCGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTfd, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTfq, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTsv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTuv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv16i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv2f32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv2i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv4f32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv4i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv4i32, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv8i16, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCGTzv8i8, ARM_INS_VCGT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv16i8, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv2f32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv2i32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv4f32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv4i16, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv4i32, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv8i16, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLEzv8i8, ARM_INS_VCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv16i8, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv2i32, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv4i16, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv4i32, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv8i16, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLSv8i8, ARM_INS_VCLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv16i8, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv2f32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv2i32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv4f32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv4i16, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv4i32, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv8i16, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLTzv8i8, ARM_INS_VCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv16i8, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv2i32, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv4i16, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv4i32, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv8i16, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCLZv8i8, ARM_INS_VCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPD, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPED, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPES, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPEZD, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPEZS, ARM_INS_VCMPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPS, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPZD, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCMPZS, ARM_INS_VCMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCNTd, ARM_INS_VCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCNTq, ARM_INS_VCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTANSD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTANSQ, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTANUD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTANUQ, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTASD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTASS, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTAUD, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTAUS, ARM_INS_VCVTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTBDH, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTBHD, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTBHS, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTBSH, ARM_INS_VCVTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTDS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMNSD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMNSQ, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMNUD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMNUQ, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMSD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMSS, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMUD, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTMUS, ARM_INS_VCVTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNNSD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNNSQ, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNNUD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNNUQ, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNSD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNSS, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNUD, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTNUS, ARM_INS_VCVTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPNSD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPNSQ, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPNUD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPNUQ, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPSD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPSS, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPUD, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTPUS, ARM_INS_VCVTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTSD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTTDH, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTTHD, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTTHS, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTTSH, ARM_INS_VCVTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2h, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2sd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2sq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2ud, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2uq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2xsd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2xsq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2xud, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTf2xuq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTh2f, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTs2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTs2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTu2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTu2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTxs2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTxs2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTxu2fd, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VCVTxu2fq, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDIVD, ARM_INS_VDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDIVS, ARM_INS_VDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP16d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP16q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP32d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP32q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP8d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUP8q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN16d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN16q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN32d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN32q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN8d, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VDUPLN8q, ARM_INS_VDUP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEORd, ARM_INS_VEOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEORq, ARM_INS_VEOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTd16, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTd32, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTd8, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTq16, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTq32, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTq64, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VEXTq8, ARM_INS_VEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMAD, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMAS, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMAfd, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMAfq, ARM_INS_VFMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMSD, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMSS, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMSfd, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFMSfq, ARM_INS_VFMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFNMAD, ARM_INS_VFNMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFNMAS, ARM_INS_VFNMA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFNMSD, ARM_INS_VFNMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VFNMSS, ARM_INS_VFNMS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP4, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VGETLNi32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VGETLNs16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VGETLNs8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VGETLNu16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VGETLNu8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv16i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv2i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv4i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv4i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv8i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDsv8i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv16i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv2i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv4i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv4i32, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv8i16, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHADDuv8i8, ARM_INS_VHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv16i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv2i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv4i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv4i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv8i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBsv8i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv16i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv2i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv4i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv4i32, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv8i16, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VHSUBuv8i8, ARM_INS_VHSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPd8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1DUPq8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd16_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd32_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1LNd8_UPD, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d64wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8Q, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8Qwb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8T, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8Twb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8Twb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1d8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q16, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q16wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q16wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q32, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q32wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q32wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q64, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q64wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q64wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q8, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q8wb_fixed, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD1q8wb_register, ARM_INS_VLD1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8x2, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd16_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd32_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNd8_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNq16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNq16_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNq32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2LNq32_UPD, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2b8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2d8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q16, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q16wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q16wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q32, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q32wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q32wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q8, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q8wb_fixed, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD2q8wb_register, ARM_INS_VLD2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPd8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3DUPq8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNd8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNq16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNq16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNq32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3LNq32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3d8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q16, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q16_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q32, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q32_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q8, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD3q8_UPD, ARM_INS_VLD3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPd8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4DUPq8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNd8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNq16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNq16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNq32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4LNq32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4d8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q16, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q16_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q32, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q32_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q8, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLD4q8_UPD, ARM_INS_VLD4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMDDB_UPD, ARM_INS_VLDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMDIA, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMDIA_UPD, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMSDB_UPD, ARM_INS_VLDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMSIA, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDMSIA_UPD, ARM_INS_VLDMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDRD, ARM_INS_VLDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VLDRS, ARM_INS_VLDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXNMD, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXNMND, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXNMNQ, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXNMS, ARM_INS_VMAXNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXfd, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXfq, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv16i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv2i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv4i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv4i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv8i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXsv8i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv16i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv2i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv4i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv4i32, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv8i16, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMAXuv8i8, ARM_INS_VMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINNMD, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINNMND, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINNMNQ, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINNMS, ARM_INS_VMINNM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINfd, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINfq, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv16i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv2i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv4i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv4i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv8i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINsv8i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv16i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv2i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv4i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv4i32, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv8i16, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMINuv8i8, ARM_INS_VMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAD, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALslsv2i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALslsv4i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALsluv2i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALsluv4i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALsv2i64, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALsv4i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALsv8i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALuv2i64, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALuv4i32, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLALuv8i16, ARM_INS_VMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAS, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAfd, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAfq, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslfd, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslfq, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslv2i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslv4i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslv4i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAslv8i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv16i8, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv2i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv4i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv4i32, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv8i16, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLAv8i8, ARM_INS_VMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSD, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLslsv2i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLslsv4i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLsluv2i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLsluv4i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLsv2i64, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLsv4i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLsv8i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLuv2i64, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLuv4i32, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSLuv8i16, ARM_INS_VMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSS, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSfd, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSfq, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslfd, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslfq, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslv2i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslv4i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslv4i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSslv8i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv16i8, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv2i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv4i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv4i32, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv8i16, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMLSv8i8, ARM_INS_VMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVDRR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLsv2i64, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLsv4i32, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLsv8i16, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLuv2i64, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLuv4i32, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVLuv8i16, ARM_INS_VMOVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVNv2i32, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVNv4i16, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVNv8i8, ARM_INS_VMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVRRD, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVRRS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVRS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVS, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVSR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVSRR, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv16i8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv1i64, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv2f32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv2i32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv2i64, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv4f32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv4i16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv4i32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv8i16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMOVv8i8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_FPEXC, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_FPINST, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_FPINST2, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_FPSID, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_MVFR0, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_MVFR1, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMRS_MVFR2, ARM_INS_VMRS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMSR, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMSR_FPEXC, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMSR_FPINST, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMSR_FPINST2, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMSR_FPSID, ARM_INS_VMSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULD, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLp64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLp8, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLslsv2i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLslsv4i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLsluv2i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLsluv4i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLsv2i64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLsv4i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLsv8i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLuv2i64, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLuv4i32, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULLuv8i16, ARM_INS_VMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULS, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULfd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULfq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULpd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULpq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslfd, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslfq, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslv2i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslv4i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslv4i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULslv8i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv16i8, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv2i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv4i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv4i32, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv8i16, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMULv8i8, ARM_INS_VMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNd, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNq, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNv2i32, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNv4i16, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNv4i32, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VMVNv8i16, ARM_INS_VMVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGD, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGS, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGf32q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGfd, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs16d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs16q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs32d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs32q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs8d, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNEGs8q, ARM_INS_VNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMLAD, ARM_INS_VNMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMLAS, ARM_INS_VNMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMLSD, ARM_INS_VNMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMLSS, ARM_INS_VNMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_FPVMLX, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMULD, ARM_INS_VNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VNMULS, ARM_INS_VNMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORNd, ARM_INS_VORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORNq, ARM_INS_VORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRd, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRiv2i32, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRiv4i16, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRiv4i32, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRiv8i16, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VORRq, ARM_INS_VORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv16i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv2i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv4i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv4i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv8i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALsv8i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv16i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv2i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv4i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv4i32, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv8i16, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADALuv8i8, ARM_INS_VPADAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv16i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv2i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv4i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv4i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv8i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLsv8i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv16i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv2i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv4i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv4i32, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv8i16, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDLuv8i8, ARM_INS_VPADDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDf, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDi16, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDi32, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPADDi8, ARM_INS_VPADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXf, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXs16, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXs32, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXs8, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXu16, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXu32, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMAXu8, ARM_INS_VPMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINf, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINs16, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINs32, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINs8, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINu16, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINu32, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VPMINu8, ARM_INS_VPMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv16i8, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv2i32, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv4i16, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv4i32, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv8i16, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQABSv8i8, ARM_INS_VQABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv16i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv1i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv2i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv2i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv4i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv4i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv8i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDsv8i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv16i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv1i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv2i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv2i64, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv4i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv4i32, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv8i16, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQADDuv8i8, ARM_INS_VQADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLALv2i64, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLALv4i32, ARM_INS_VQDMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHslv2i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHslv4i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHslv4i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHslv8i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHv2i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHv4i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHv4i32, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULHv8i16, ARM_INS_VQDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULLslv2i32, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULLslv4i16, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULLv2i64, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQDMULLv4i32, ARM_INS_VQDMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsv2i32, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsv4i16, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNsv8i8, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNuv2i32, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNuv4i16, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQMOVNuv8i8, ARM_INS_VQMOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv16i8, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv2i32, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv4i16, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv4i32, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv8i16, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQNEGv8i8, ARM_INS_VQNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv16i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv1i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv2i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv2i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv4i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv4i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv8i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLsv8i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv16i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv1i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv2i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv2i64, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv4i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv4i32, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv8i16, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHLuv8i8, ARM_INS_VQRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsiv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv16i8, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv1i64, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv2i32, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv2i64, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv4i16, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv4i32, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv8i16, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsuv8i8, ARM_INS_VQSHLU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLsv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuiv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv16i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv1i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv2i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv2i64, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv4i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv4i32, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv8i16, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHLuv8i8, ARM_INS_VQSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNsv2i32, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNsv4i16, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNsv8i8, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNuv2i32, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNuv4i16, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRNuv8i8, ARM_INS_VQSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv16i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv1i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv2i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv2i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv4i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv4i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv8i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBsv8i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv16i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv1i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv2i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv2i64, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv4i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv4i32, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv8i16, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VQSUBuv8i8, ARM_INS_VQSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRADDHNv2i32, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRADDHNv4i16, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRADDHNv8i8, ARM_INS_VRADDHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPEd, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPEfd, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPEfq, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPEq, ARM_INS_VRECPE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPSfd, ARM_INS_VRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRECPSfq, ARM_INS_VRECPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV16d8, ARM_INS_VREV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV16q8, ARM_INS_VREV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV32d16, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV32d8, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV32q16, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV32q8, ARM_INS_VREV32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64d16, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64d32, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64d8, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64q16, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64q32, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VREV64q8, ARM_INS_VREV64, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv16i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv2i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv4i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv4i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv8i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDsv8i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv16i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv2i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv4i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv4i32, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv8i16, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRHADDuv8i8, ARM_INS_VRHADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTAD, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTAND, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTANQ, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTAS, ARM_INS_VRINTA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTMD, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTMND, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTMNQ, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTMS, ARM_INS_VRINTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTND, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTNND, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTNNQ, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTNS, ARM_INS_VRINTN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTPD, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTPND, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTPNQ, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTPS, ARM_INS_VRINTP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTRD, ARM_INS_VRINTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTRS, ARM_INS_VRINTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTXD, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTXND, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTXNQ, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTXS, ARM_INS_VRINTX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTZD, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTZND, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTZNQ, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRINTZS, ARM_INS_VRINTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv16i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv1i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv2i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv2i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv4i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv4i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv8i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLsv8i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv16i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv1i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv2i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv2i64, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv4i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv4i32, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv8i16, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHLuv8i8, ARM_INS_VRSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRNv2i32, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRNv4i16, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRNv8i8, ARM_INS_VRSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv16i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv1i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv2i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv2i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv4i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv4i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv8i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRsv8i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv16i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv1i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv2i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv2i64, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv4i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv4i32, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv8i16, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSHRuv8i8, ARM_INS_VRSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTEd, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTEfd, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTEfq, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTEq, ARM_INS_VRSQRTE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTSfd, ARM_INS_VRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSQRTSfq, ARM_INS_VRSQRTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv16i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv1i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv2i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv2i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv4i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv4i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv8i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAsv8i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv16i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv1i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv2i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv2i64, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv4i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv4i32, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv8i16, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSRAuv8i8, ARM_INS_VRSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELEQD, ARM_INS_VSELEQ, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELEQS, ARM_INS_VSELEQ, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELGED, ARM_INS_VSELGE, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELGES, ARM_INS_VSELGE, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELGTD, ARM_INS_VSELGT, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELGTS, ARM_INS_VSELGT, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELVSD, ARM_INS_VSELVS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSELVSS, ARM_INS_VSELVS, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_FPARMV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSETLNi16, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSETLNi32, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSETLNi8, ARM_INS_VMOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLi16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLi32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLi8, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLsv2i64, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLsv4i32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLsv8i16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLuv2i64, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLuv4i32, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLLuv8i16, ARM_INS_VSHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLiv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLsv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv16i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv1i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv2i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv2i64, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv4i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv4i32, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv8i16, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHLuv8i8, ARM_INS_VSHL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRNv2i32, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRNv4i16, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRNv8i8, ARM_INS_VSHRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv16i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv1i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv2i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv2i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv4i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv4i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv8i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRsv8i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv16i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv1i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv2i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv2i64, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv4i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv4i32, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv8i16, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHRuv8i8, ARM_INS_VSHR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSHTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSITOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSITOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv16i8, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv1i64, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv2i32, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv2i64, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv4i16, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv4i32, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv8i16, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLIv8i8, ARM_INS_VSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSLTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSQRTD, ARM_INS_VSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSQRTS, ARM_INS_VSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv16i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv1i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv2i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv2i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv4i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv4i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv8i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAsv8i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv16i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv1i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv2i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv2i64, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv4i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv4i32, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv8i16, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRAuv8i8, ARM_INS_VSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv16i8, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv1i64, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv2i32, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv2i64, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv4i16, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv4i32, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv8i16, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSRIv8i8, ARM_INS_VSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd16_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd32_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1LNd8_UPD, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d16wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d32wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d64wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8Q, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8Qwb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8Qwb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8T, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8Twb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8Twb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1d8wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q16, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q16wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q16wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q32, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q32wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q32wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q64, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q64wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q64wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q8, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q8wb_fixed, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST1q8wb_register, ARM_INS_VST1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd16_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd32_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNd8_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNq16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNq16_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNq32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2LNq32_UPD, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2b8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2d8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q16, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q16wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q16wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q32, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q32wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q32wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q8, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q8wb_fixed, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST2q8wb_register, ARM_INS_VST2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNd8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNq16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNq16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNq32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3LNq32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3d8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q16, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q16_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q32, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q32_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q8, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST3q8_UPD, ARM_INS_VST3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNd8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNq16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNq16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNq32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4LNq32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4d8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q16, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q16_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q32, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q32_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q8, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VST4q8_UPD, ARM_INS_VST4, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMDDB_UPD, ARM_INS_VSTMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMDIA, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMDIA_UPD, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMSDB_UPD, ARM_INS_VSTMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMSIA, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTMSIA_UPD, ARM_INS_VSTMIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTRD, ARM_INS_VSTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSTRS, ARM_INS_VSTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBD, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBHNv2i32, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBHNv4i16, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBHNv8i8, ARM_INS_VSUBHN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLsv2i64, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLsv4i32, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLsv8i16, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLuv2i64, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLuv4i32, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBLuv8i16, ARM_INS_VSUBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBS, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWsv2i64, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWsv4i32, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWsv8i16, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWuv2i64, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWuv4i32, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBWuv8i16, ARM_INS_VSUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBfd, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBfq, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv16i8, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv1i64, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv2i32, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv2i64, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv4i16, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv4i32, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv8i16, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSUBv8i8, ARM_INS_VSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSWPd, ARM_INS_VSWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VSWPq, ARM_INS_VSWP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBL1, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBL2, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBL3, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBL4, ARM_INS_VTBL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBX1, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBX2, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBX3, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTBX4, ARM_INS_VTBX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSHD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSHS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSIRD, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSIRS, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSIZD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSIZS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSLD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOSLS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUHD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUHS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUIRD, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUIRS, ARM_INS_VCVTR, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUIZD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOUIZS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOULD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTOULS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNd16, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNd32, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNd8, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNq16, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNq32, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTRNq8, ARM_INS_VTRN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv16i8, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv2i32, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv4i16, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv4i32, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv8i16, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VTSTv8i8, ARM_INS_VTST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUHTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUHTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUITOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUITOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VULTOD, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VULTOS, ARM_INS_VCVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUZPd16, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUZPd8, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUZPq16, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUZPq32, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VUZPq8, ARM_INS_VUZP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VZIPd16, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VZIPd8, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VZIPq16, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VZIPq32, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_VZIPq8, ARM_INS_VZIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMDA, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMDA_UPD, ARM_INS_LDMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMIB, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysLDMIB_UPD, ARM_INS_LDMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMDA, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMDA_UPD, ARM_INS_STMDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMIB, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_sysSTMIB_UPD, ARM_INS_STMIB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADCri, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADCrr, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADCrs, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADDri, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADDri12, ARM_INS_ADDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADDrs, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ANDri, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ANDrr, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ANDrs, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ASRri, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ASRrr, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2B, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_t2BFC, ARM_INS_BFC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2BFI, ARM_INS_BFI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2BICri, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2BICrr, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2BICrs, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2BXJ, ARM_INS_BXJ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, ARM_GRP_PREV8, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_t2Bcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_t2CDP, ARM_INS_CDP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CDP2, ARM_INS_CDP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CLREX, ARM_INS_CLREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CLZ, ARM_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMNri, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMNzrr, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMNzrs, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMPri, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMPrr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CMPrs, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CPS1p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CPS2p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CPS3p, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32B, ARM_INS_CRC32B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32CB, ARM_INS_CRC32CB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32CH, ARM_INS_CRC32CH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32CW, ARM_INS_CRC32CW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32H, ARM_INS_CRC32H, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2CRC32W, ARM_INS_CRC32W, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DBG, ARM_INS_DBG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DCPS1, ARM_INS_DCPS1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DCPS2, ARM_INS_DCPS2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DCPS3, ARM_INS_DCPS3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DMB, ARM_INS_DMB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2DSB, ARM_INS_DSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2EORri, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2EORrr, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2EORrs, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2HINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ISB, ARM_INS_ISB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2IT, ARM_INS_IT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDA, ARM_INS_LDA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAB, ARM_INS_LDAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAEX, ARM_INS_LDAEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAEXB, ARM_INS_LDAEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAEXD, ARM_INS_LDAEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAEXH, ARM_INS_LDAEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDAH, ARM_INS_LDAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2L_OPTION, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2L_POST, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2L_PRE, ARM_INS_LDC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2_OFFSET, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2_OPTION, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2_POST, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC2_PRE, ARM_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDCL_OFFSET, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDCL_OPTION, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDCL_POST, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDCL_PRE, ARM_INS_LDCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC_OFFSET, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC_OPTION, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC_POST, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDC_PRE, ARM_INS_LDC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDMDB, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDMDB_UPD, ARM_INS_LDMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDMIA_UPD, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRBT, ARM_INS_LDRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRB_POST, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRB_PRE, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRBi12, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRBi8, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRBpci, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRBs, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRD_POST, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRD_PRE, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRDi8, ARM_INS_LDRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDREX, ARM_INS_LDREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDREXB, ARM_INS_LDREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDREXD, ARM_INS_LDREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDREXH, ARM_INS_LDREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRHT, ARM_INS_LDRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRH_POST, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRH_PRE, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRHi12, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRHi8, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRHpci, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRHs, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSBT, ARM_INS_LDRSBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSB_POST, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSB_PRE, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSBi12, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSBi8, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSBpci, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSBs, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSHT, ARM_INS_LDRSHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSH_POST, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSH_PRE, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSHi12, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSHi8, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSHpci, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRSHs, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRT, ARM_INS_LDRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDR_POST, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDR_PRE, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRi12, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRi8, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRpci, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LDRs, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LSLri, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LSLrr, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LSRri, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2LSRrr, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MCR, ARM_INS_MCR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MCR2, ARM_INS_MCR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MCRR, ARM_INS_MCRR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MCRR2, ARM_INS_MCRR2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MLA, ARM_INS_MLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MLS, ARM_INS_MLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVTi16, ARM_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVi, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVi16, ARM_INS_MOVW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVsra_flag, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MOVsrl_flag, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRC, ARM_INS_MRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRC2, ARM_INS_MRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRRC, ARM_INS_MRRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRRC2, ARM_INS_MRRC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_PREV8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRS_AR, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRS_M, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MRSsys_AR, ARM_INS_MRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MSR_AR, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MSR_M, ARM_INS_MSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_MCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MVNi, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MVNr, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2MVNs, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORNri, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORNrr, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORNrs, ARM_INS_ORN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORRri, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORRrr, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2ORRrs, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PKHBT, ARM_INS_PKHBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PKHTB, ARM_INS_PKHTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDWi12, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDWi8, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDWs, ARM_INS_PLDW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDi12, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDi8, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDpci, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLDs, ARM_INS_PLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLIi12, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLIi8, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLIpci, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2PLIs, ARM_INS_PLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_V7, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QADD, ARM_INS_QADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QADD16, ARM_INS_QADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QADD8, ARM_INS_QADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QASX, ARM_INS_QASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QDADD, ARM_INS_QDADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QDSUB, ARM_INS_QDSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QSAX, ARM_INS_QSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QSUB, ARM_INS_QSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QSUB16, ARM_INS_QSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2QSUB8, ARM_INS_QSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RBIT, ARM_INS_RBIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2REV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2REV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2REVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RFEDB, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RFEDBW, ARM_INS_RFEDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RFEIA, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RFEIAW, ARM_INS_RFEIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RORri, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RORrr, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RRX, ARM_INS_RRX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RSBri, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RSBrr, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2RSBrs, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SADD16, ARM_INS_SADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SADD8, ARM_INS_SADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SASX, ARM_INS_SASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SBCri, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SBCrr, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SBCrs, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SBFX, ARM_INS_SBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SDIV, ARM_INS_SDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SEL, ARM_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHADD16, ARM_INS_SHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHADD8, ARM_INS_SHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHASX, ARM_INS_SHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHSAX, ARM_INS_SHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHSUB16, ARM_INS_SHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SHSUB8, ARM_INS_SHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMC, ARM_INS_SMC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_TRUSTZONE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLABB, ARM_INS_SMLABB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLABT, ARM_INS_SMLABT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLAD, ARM_INS_SMLAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLADX, ARM_INS_SMLADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLAL, ARM_INS_SMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALBB, ARM_INS_SMLALBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALBT, ARM_INS_SMLALBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALD, ARM_INS_SMLALD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALDX, ARM_INS_SMLALDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALTB, ARM_INS_SMLALTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLALTT, ARM_INS_SMLALTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLATB, ARM_INS_SMLATB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLATT, ARM_INS_SMLATT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLAWB, ARM_INS_SMLAWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLAWT, ARM_INS_SMLAWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLSD, ARM_INS_SMLSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLSDX, ARM_INS_SMLSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLSLD, ARM_INS_SMLSLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMLSLDX, ARM_INS_SMLSLDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMLA, ARM_INS_SMMLA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMLAR, ARM_INS_SMMLAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMLS, ARM_INS_SMMLS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, ARM_GRP_MULOPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMLSR, ARM_INS_SMMLSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMUL, ARM_INS_SMMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMMULR, ARM_INS_SMMULR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMUAD, ARM_INS_SMUAD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMUADX, ARM_INS_SMUADX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULBB, ARM_INS_SMULBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULBT, ARM_INS_SMULBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULL, ARM_INS_SMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULTB, ARM_INS_SMULTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULTT, ARM_INS_SMULTT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULWB, ARM_INS_SMULWB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMULWT, ARM_INS_SMULWT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMUSD, ARM_INS_SMUSD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SMUSDX, ARM_INS_SMUSDX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SRSDB, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SRSDB_UPD, ARM_INS_SRSDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SRSIA, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SRSIA_UPD, ARM_INS_SRSIA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SSAT, ARM_INS_SSAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SSAT16, ARM_INS_SSAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SSAX, ARM_INS_SSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SSUB16, ARM_INS_SSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SSUB8, ARM_INS_SSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2L_OFFSET, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2L_OPTION, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2L_POST, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2L_PRE, ARM_INS_STC2L, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2_OFFSET, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2_OPTION, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2_POST, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC2_PRE, ARM_INS_STC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STCL_OFFSET, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STCL_OPTION, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STCL_POST, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STCL_PRE, ARM_INS_STCL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC_OFFSET, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC_OPTION, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC_POST, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STC_PRE, ARM_INS_STC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STL, ARM_INS_STL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLB, ARM_INS_STLB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLEX, ARM_INS_STLEX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLEXB, ARM_INS_STLEXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLEXD, ARM_INS_STLEXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLEXH, ARM_INS_STLEXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STLH, ARM_INS_STLH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STMDB, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STMDB_UPD, ARM_INS_STMDB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STMIA, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRBT, ARM_INS_STRBT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRB_POST, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRB_PRE, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRBi12, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRBi8, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRBs, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRD_POST, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRD_PRE, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRDi8, ARM_INS_STRD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STREX, ARM_INS_STREX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STREXB, ARM_INS_STREXB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STREXD, ARM_INS_STREXD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_NOTMCLASS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STREXH, ARM_INS_STREXH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRHT, ARM_INS_STRHT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRH_POST, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRH_PRE, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRHi12, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRHi8, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRHs, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRT, ARM_INS_STRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STR_POST, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STR_PRE, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRi12, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRi8, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2STRs, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SUBS_PC_LR, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SUBri, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SUBri12, ARM_INS_SUBW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SUBrs, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTAB, ARM_INS_SXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTAB16, ARM_INS_SXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTAH, ARM_INS_SXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTB16, ARM_INS_SXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_T2EXTRACTPACK, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2SXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TBB, ARM_INS_TBB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_t2TBH, ARM_INS_TBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_t2TEQri, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TEQrr, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TEQrs, ARM_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TSTri, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TSTrr, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2TSTrs, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UADD16, ARM_INS_UADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UADD8, ARM_INS_UADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UASX, ARM_INS_UASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UBFX, ARM_INS_UBFX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UDIV, ARM_INS_UDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_DIVIDE, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHADD16, ARM_INS_UHADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHADD8, ARM_INS_UHADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHASX, ARM_INS_UHASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHSAX, ARM_INS_UHSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHSUB16, ARM_INS_UHSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UHSUB8, ARM_INS_UHSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UMAAL, ARM_INS_UMAAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UMLAL, ARM_INS_UMLAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UMULL, ARM_INS_UMULL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQADD16, ARM_INS_UQADD16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQADD8, ARM_INS_UQADD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQASX, ARM_INS_UQASX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQSAX, ARM_INS_UQSAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQSUB16, ARM_INS_UQSUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UQSUB8, ARM_INS_UQSUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USAD8, ARM_INS_USAD8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USADA8, ARM_INS_USADA8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USAT, ARM_INS_USAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USAT16, ARM_INS_USAT16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USAX, ARM_INS_USAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USUB16, ARM_INS_USUB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2USUB8, ARM_INS_USUB8, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, ARM_GRP_THUMB2DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTAB, ARM_INS_UXTAB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTAB16, ARM_INS_UXTAB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTAH, ARM_INS_UXTAH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTB16, ARM_INS_UXTB16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_T2EXTRACTPACK, ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_t2UXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADC, ARM_INS_ADC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDhirr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDi3, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDi8, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDrSP, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDrSPi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDrr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDspi, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADDspr, ARM_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tADR, ARM_INS_ADR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tAND, ARM_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tASRri, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tASRrr, ARM_INS_ASR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tB, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tBIC, ARM_INS_BIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tBKPT, ARM_INS_BKPT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tBL, ARM_INS_BL, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tBLXi, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tBLXr, ARM_INS_BLX, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_tBX, ARM_INS_BX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 1 >+#endif >+ }, >+ { >+ ARM_tBcc, ARM_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tCBNZ, ARM_INS_CBNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tCBZ, ARM_INS_CBZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0 >+#endif >+ }, >+ { >+ ARM_tCMNz, ARM_INS_CMN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tCMPhir, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tCMPi8, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tCMPr, ARM_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tCPS, ARM_INS_CPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tEOR, ARM_INS_EOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tHINT, ARM_INS_HINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6M, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tHLT, ARM_INS_HLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V8, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDMIA, ARM_INS_LDM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRBi, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRBr, ARM_INS_LDRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRHi, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRHr, ARM_INS_LDRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRSB, ARM_INS_LDRSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRSH, ARM_INS_LDRSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRi, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRpci, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRr, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLDRspi, ARM_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLSLri, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLSLrr, ARM_INS_LSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLSRri, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tLSRrr, ARM_INS_LSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tMOVSr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tMOVi8, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tMOVr, ARM_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tMUL, ARM_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tMVN, ARM_INS_MVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tORR, ARM_INS_ORR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tPOP, ARM_INS_POP, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tPUSH, ARM_INS_PUSH, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tREV, ARM_INS_REV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tREV16, ARM_INS_REV16, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tREVSH, ARM_INS_REVSH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tROR, ARM_INS_ROR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tRSB, ARM_INS_RSB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSBC, ARM_INS_SBC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_CPSR, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSETEND, ARM_INS_SETEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_V6, ARM_GRP_NOTMCLASS, 0}, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTMIA_UPD, ARM_INS_STM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRBi, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRBr, ARM_INS_STRB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRHi, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRHr, ARM_INS_STRH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRi, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRr, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSTRspi, ARM_INS_STR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSUBi3, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSUBi8, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSUBrr, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSUBspi, ARM_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSVC, ARM_INS_SVC, >+#ifndef CAPSTONE_DIET >+ { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSXTB, ARM_INS_SXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tSXTH, ARM_INS_SXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tTRAP, ARM_INS_TRAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tTST, ARM_INS_TST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tUDF, ARM_INS_UDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tUXTB, ARM_INS_UXTB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ ARM_tUXTH, ARM_INS_UXTH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_V6, 0 }, 0, 0 >+#endif >+ }, >+}; >+ >+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) >+{ >+ int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ if (i != 0) { >+ insn->id = insns[i].mapid; >+ >+ if (h->detail) { >+#ifndef CAPSTONE_DIET >+ cs_struct handle; >+ handle.detail = h->detail; >+ >+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); >+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); >+ >+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); >+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); >+ >+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); >+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups); >+ >+ insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR); >+ >+ if (insns[i].branch || insns[i].indirect_branch) { >+ // this insn also belongs to JUMP group. add JUMP group >+ insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP; >+ insn->detail->groups_count++; >+ } >+#endif >+ } >+ } >+} >+ >+#ifndef CAPSTONE_DIET >+static const name_map insn_name_maps[] = { >+ { ARM_INS_INVALID, NULL }, >+ >+ { ARM_INS_ADC, "adc" }, >+ { ARM_INS_ADD, "add" }, >+ { ARM_INS_ADR, "adr" }, >+ { ARM_INS_AESD, "aesd" }, >+ { ARM_INS_AESE, "aese" }, >+ { ARM_INS_AESIMC, "aesimc" }, >+ { ARM_INS_AESMC, "aesmc" }, >+ { ARM_INS_AND, "and" }, >+ { ARM_INS_BFC, "bfc" }, >+ { ARM_INS_BFI, "bfi" }, >+ { ARM_INS_BIC, "bic" }, >+ { ARM_INS_BKPT, "bkpt" }, >+ { ARM_INS_BL, "bl" }, >+ { ARM_INS_BLX, "blx" }, >+ { ARM_INS_BX, "bx" }, >+ { ARM_INS_BXJ, "bxj" }, >+ { ARM_INS_B, "b" }, >+ { ARM_INS_CDP, "cdp" }, >+ { ARM_INS_CDP2, "cdp2" }, >+ { ARM_INS_CLREX, "clrex" }, >+ { ARM_INS_CLZ, "clz" }, >+ { ARM_INS_CMN, "cmn" }, >+ { ARM_INS_CMP, "cmp" }, >+ { ARM_INS_CPS, "cps" }, >+ { ARM_INS_CRC32B, "crc32b" }, >+ { ARM_INS_CRC32CB, "crc32cb" }, >+ { ARM_INS_CRC32CH, "crc32ch" }, >+ { ARM_INS_CRC32CW, "crc32cw" }, >+ { ARM_INS_CRC32H, "crc32h" }, >+ { ARM_INS_CRC32W, "crc32w" }, >+ { ARM_INS_DBG, "dbg" }, >+ { ARM_INS_DMB, "dmb" }, >+ { ARM_INS_DSB, "dsb" }, >+ { ARM_INS_EOR, "eor" }, >+ { ARM_INS_VMOV, "vmov" }, >+ { ARM_INS_FLDMDBX, "fldmdbx" }, >+ { ARM_INS_FLDMIAX, "fldmiax" }, >+ { ARM_INS_VMRS, "vmrs" }, >+ { ARM_INS_FSTMDBX, "fstmdbx" }, >+ { ARM_INS_FSTMIAX, "fstmiax" }, >+ { ARM_INS_HINT, "hint" }, >+ { ARM_INS_HLT, "hlt" }, >+ { ARM_INS_ISB, "isb" }, >+ { ARM_INS_LDA, "lda" }, >+ { ARM_INS_LDAB, "ldab" }, >+ { ARM_INS_LDAEX, "ldaex" }, >+ { ARM_INS_LDAEXB, "ldaexb" }, >+ { ARM_INS_LDAEXD, "ldaexd" }, >+ { ARM_INS_LDAEXH, "ldaexh" }, >+ { ARM_INS_LDAH, "ldah" }, >+ { ARM_INS_LDC2L, "ldc2l" }, >+ { ARM_INS_LDC2, "ldc2" }, >+ { ARM_INS_LDCL, "ldcl" }, >+ { ARM_INS_LDC, "ldc" }, >+ { ARM_INS_LDMDA, "ldmda" }, >+ { ARM_INS_LDMDB, "ldmdb" }, >+ { ARM_INS_LDM, "ldm" }, >+ { ARM_INS_LDMIB, "ldmib" }, >+ { ARM_INS_LDRBT, "ldrbt" }, >+ { ARM_INS_LDRB, "ldrb" }, >+ { ARM_INS_LDRD, "ldrd" }, >+ { ARM_INS_LDREX, "ldrex" }, >+ { ARM_INS_LDREXB, "ldrexb" }, >+ { ARM_INS_LDREXD, "ldrexd" }, >+ { ARM_INS_LDREXH, "ldrexh" }, >+ { ARM_INS_LDRH, "ldrh" }, >+ { ARM_INS_LDRHT, "ldrht" }, >+ { ARM_INS_LDRSB, "ldrsb" }, >+ { ARM_INS_LDRSBT, "ldrsbt" }, >+ { ARM_INS_LDRSH, "ldrsh" }, >+ { ARM_INS_LDRSHT, "ldrsht" }, >+ { ARM_INS_LDRT, "ldrt" }, >+ { ARM_INS_LDR, "ldr" }, >+ { ARM_INS_MCR, "mcr" }, >+ { ARM_INS_MCR2, "mcr2" }, >+ { ARM_INS_MCRR, "mcrr" }, >+ { ARM_INS_MCRR2, "mcrr2" }, >+ { ARM_INS_MLA, "mla" }, >+ { ARM_INS_MLS, "mls" }, >+ { ARM_INS_MOV, "mov" }, >+ { ARM_INS_MOVT, "movt" }, >+ { ARM_INS_MOVW, "movw" }, >+ { ARM_INS_MRC, "mrc" }, >+ { ARM_INS_MRC2, "mrc2" }, >+ { ARM_INS_MRRC, "mrrc" }, >+ { ARM_INS_MRRC2, "mrrc2" }, >+ { ARM_INS_MRS, "mrs" }, >+ { ARM_INS_MSR, "msr" }, >+ { ARM_INS_MUL, "mul" }, >+ { ARM_INS_MVN, "mvn" }, >+ { ARM_INS_ORR, "orr" }, >+ { ARM_INS_PKHBT, "pkhbt" }, >+ { ARM_INS_PKHTB, "pkhtb" }, >+ { ARM_INS_PLDW, "pldw" }, >+ { ARM_INS_PLD, "pld" }, >+ { ARM_INS_PLI, "pli" }, >+ { ARM_INS_QADD, "qadd" }, >+ { ARM_INS_QADD16, "qadd16" }, >+ { ARM_INS_QADD8, "qadd8" }, >+ { ARM_INS_QASX, "qasx" }, >+ { ARM_INS_QDADD, "qdadd" }, >+ { ARM_INS_QDSUB, "qdsub" }, >+ { ARM_INS_QSAX, "qsax" }, >+ { ARM_INS_QSUB, "qsub" }, >+ { ARM_INS_QSUB16, "qsub16" }, >+ { ARM_INS_QSUB8, "qsub8" }, >+ { ARM_INS_RBIT, "rbit" }, >+ { ARM_INS_REV, "rev" }, >+ { ARM_INS_REV16, "rev16" }, >+ { ARM_INS_REVSH, "revsh" }, >+ { ARM_INS_RFEDA, "rfeda" }, >+ { ARM_INS_RFEDB, "rfedb" }, >+ { ARM_INS_RFEIA, "rfeia" }, >+ { ARM_INS_RFEIB, "rfeib" }, >+ { ARM_INS_RSB, "rsb" }, >+ { ARM_INS_RSC, "rsc" }, >+ { ARM_INS_SADD16, "sadd16" }, >+ { ARM_INS_SADD8, "sadd8" }, >+ { ARM_INS_SASX, "sasx" }, >+ { ARM_INS_SBC, "sbc" }, >+ { ARM_INS_SBFX, "sbfx" }, >+ { ARM_INS_SDIV, "sdiv" }, >+ { ARM_INS_SEL, "sel" }, >+ { ARM_INS_SETEND, "setend" }, >+ { ARM_INS_SHA1C, "sha1c" }, >+ { ARM_INS_SHA1H, "sha1h" }, >+ { ARM_INS_SHA1M, "sha1m" }, >+ { ARM_INS_SHA1P, "sha1p" }, >+ { ARM_INS_SHA1SU0, "sha1su0" }, >+ { ARM_INS_SHA1SU1, "sha1su1" }, >+ { ARM_INS_SHA256H, "sha256h" }, >+ { ARM_INS_SHA256H2, "sha256h2" }, >+ { ARM_INS_SHA256SU0, "sha256su0" }, >+ { ARM_INS_SHA256SU1, "sha256su1" }, >+ { ARM_INS_SHADD16, "shadd16" }, >+ { ARM_INS_SHADD8, "shadd8" }, >+ { ARM_INS_SHASX, "shasx" }, >+ { ARM_INS_SHSAX, "shsax" }, >+ { ARM_INS_SHSUB16, "shsub16" }, >+ { ARM_INS_SHSUB8, "shsub8" }, >+ { ARM_INS_SMC, "smc" }, >+ { ARM_INS_SMLABB, "smlabb" }, >+ { ARM_INS_SMLABT, "smlabt" }, >+ { ARM_INS_SMLAD, "smlad" }, >+ { ARM_INS_SMLADX, "smladx" }, >+ { ARM_INS_SMLAL, "smlal" }, >+ { ARM_INS_SMLALBB, "smlalbb" }, >+ { ARM_INS_SMLALBT, "smlalbt" }, >+ { ARM_INS_SMLALD, "smlald" }, >+ { ARM_INS_SMLALDX, "smlaldx" }, >+ { ARM_INS_SMLALTB, "smlaltb" }, >+ { ARM_INS_SMLALTT, "smlaltt" }, >+ { ARM_INS_SMLATB, "smlatb" }, >+ { ARM_INS_SMLATT, "smlatt" }, >+ { ARM_INS_SMLAWB, "smlawb" }, >+ { ARM_INS_SMLAWT, "smlawt" }, >+ { ARM_INS_SMLSD, "smlsd" }, >+ { ARM_INS_SMLSDX, "smlsdx" }, >+ { ARM_INS_SMLSLD, "smlsld" }, >+ { ARM_INS_SMLSLDX, "smlsldx" }, >+ { ARM_INS_SMMLA, "smmla" }, >+ { ARM_INS_SMMLAR, "smmlar" }, >+ { ARM_INS_SMMLS, "smmls" }, >+ { ARM_INS_SMMLSR, "smmlsr" }, >+ { ARM_INS_SMMUL, "smmul" }, >+ { ARM_INS_SMMULR, "smmulr" }, >+ { ARM_INS_SMUAD, "smuad" }, >+ { ARM_INS_SMUADX, "smuadx" }, >+ { ARM_INS_SMULBB, "smulbb" }, >+ { ARM_INS_SMULBT, "smulbt" }, >+ { ARM_INS_SMULL, "smull" }, >+ { ARM_INS_SMULTB, "smultb" }, >+ { ARM_INS_SMULTT, "smultt" }, >+ { ARM_INS_SMULWB, "smulwb" }, >+ { ARM_INS_SMULWT, "smulwt" }, >+ { ARM_INS_SMUSD, "smusd" }, >+ { ARM_INS_SMUSDX, "smusdx" }, >+ { ARM_INS_SRSDA, "srsda" }, >+ { ARM_INS_SRSDB, "srsdb" }, >+ { ARM_INS_SRSIA, "srsia" }, >+ { ARM_INS_SRSIB, "srsib" }, >+ { ARM_INS_SSAT, "ssat" }, >+ { ARM_INS_SSAT16, "ssat16" }, >+ { ARM_INS_SSAX, "ssax" }, >+ { ARM_INS_SSUB16, "ssub16" }, >+ { ARM_INS_SSUB8, "ssub8" }, >+ { ARM_INS_STC2L, "stc2l" }, >+ { ARM_INS_STC2, "stc2" }, >+ { ARM_INS_STCL, "stcl" }, >+ { ARM_INS_STC, "stc" }, >+ { ARM_INS_STL, "stl" }, >+ { ARM_INS_STLB, "stlb" }, >+ { ARM_INS_STLEX, "stlex" }, >+ { ARM_INS_STLEXB, "stlexb" }, >+ { ARM_INS_STLEXD, "stlexd" }, >+ { ARM_INS_STLEXH, "stlexh" }, >+ { ARM_INS_STLH, "stlh" }, >+ { ARM_INS_STMDA, "stmda" }, >+ { ARM_INS_STMDB, "stmdb" }, >+ { ARM_INS_STM, "stm" }, >+ { ARM_INS_STMIB, "stmib" }, >+ { ARM_INS_STRBT, "strbt" }, >+ { ARM_INS_STRB, "strb" }, >+ { ARM_INS_STRD, "strd" }, >+ { ARM_INS_STREX, "strex" }, >+ { ARM_INS_STREXB, "strexb" }, >+ { ARM_INS_STREXD, "strexd" }, >+ { ARM_INS_STREXH, "strexh" }, >+ { ARM_INS_STRH, "strh" }, >+ { ARM_INS_STRHT, "strht" }, >+ { ARM_INS_STRT, "strt" }, >+ { ARM_INS_STR, "str" }, >+ { ARM_INS_SUB, "sub" }, >+ { ARM_INS_SVC, "svc" }, >+ { ARM_INS_SWP, "swp" }, >+ { ARM_INS_SWPB, "swpb" }, >+ { ARM_INS_SXTAB, "sxtab" }, >+ { ARM_INS_SXTAB16, "sxtab16" }, >+ { ARM_INS_SXTAH, "sxtah" }, >+ { ARM_INS_SXTB, "sxtb" }, >+ { ARM_INS_SXTB16, "sxtb16" }, >+ { ARM_INS_SXTH, "sxth" }, >+ { ARM_INS_TEQ, "teq" }, >+ { ARM_INS_TRAP, "trap" }, >+ { ARM_INS_TST, "tst" }, >+ { ARM_INS_UADD16, "uadd16" }, >+ { ARM_INS_UADD8, "uadd8" }, >+ { ARM_INS_UASX, "uasx" }, >+ { ARM_INS_UBFX, "ubfx" }, >+ { ARM_INS_UDF, "udf" }, >+ { ARM_INS_UDIV, "udiv" }, >+ { ARM_INS_UHADD16, "uhadd16" }, >+ { ARM_INS_UHADD8, "uhadd8" }, >+ { ARM_INS_UHASX, "uhasx" }, >+ { ARM_INS_UHSAX, "uhsax" }, >+ { ARM_INS_UHSUB16, "uhsub16" }, >+ { ARM_INS_UHSUB8, "uhsub8" }, >+ { ARM_INS_UMAAL, "umaal" }, >+ { ARM_INS_UMLAL, "umlal" }, >+ { ARM_INS_UMULL, "umull" }, >+ { ARM_INS_UQADD16, "uqadd16" }, >+ { ARM_INS_UQADD8, "uqadd8" }, >+ { ARM_INS_UQASX, "uqasx" }, >+ { ARM_INS_UQSAX, "uqsax" }, >+ { ARM_INS_UQSUB16, "uqsub16" }, >+ { ARM_INS_UQSUB8, "uqsub8" }, >+ { ARM_INS_USAD8, "usad8" }, >+ { ARM_INS_USADA8, "usada8" }, >+ { ARM_INS_USAT, "usat" }, >+ { ARM_INS_USAT16, "usat16" }, >+ { ARM_INS_USAX, "usax" }, >+ { ARM_INS_USUB16, "usub16" }, >+ { ARM_INS_USUB8, "usub8" }, >+ { ARM_INS_UXTAB, "uxtab" }, >+ { ARM_INS_UXTAB16, "uxtab16" }, >+ { ARM_INS_UXTAH, "uxtah" }, >+ { ARM_INS_UXTB, "uxtb" }, >+ { ARM_INS_UXTB16, "uxtb16" }, >+ { ARM_INS_UXTH, "uxth" }, >+ { ARM_INS_VABAL, "vabal" }, >+ { ARM_INS_VABA, "vaba" }, >+ { ARM_INS_VABDL, "vabdl" }, >+ { ARM_INS_VABD, "vabd" }, >+ { ARM_INS_VABS, "vabs" }, >+ { ARM_INS_VACGE, "vacge" }, >+ { ARM_INS_VACGT, "vacgt" }, >+ { ARM_INS_VADD, "vadd" }, >+ { ARM_INS_VADDHN, "vaddhn" }, >+ { ARM_INS_VADDL, "vaddl" }, >+ { ARM_INS_VADDW, "vaddw" }, >+ { ARM_INS_VAND, "vand" }, >+ { ARM_INS_VBIC, "vbic" }, >+ { ARM_INS_VBIF, "vbif" }, >+ { ARM_INS_VBIT, "vbit" }, >+ { ARM_INS_VBSL, "vbsl" }, >+ { ARM_INS_VCEQ, "vceq" }, >+ { ARM_INS_VCGE, "vcge" }, >+ { ARM_INS_VCGT, "vcgt" }, >+ { ARM_INS_VCLE, "vcle" }, >+ { ARM_INS_VCLS, "vcls" }, >+ { ARM_INS_VCLT, "vclt" }, >+ { ARM_INS_VCLZ, "vclz" }, >+ { ARM_INS_VCMP, "vcmp" }, >+ { ARM_INS_VCMPE, "vcmpe" }, >+ { ARM_INS_VCNT, "vcnt" }, >+ { ARM_INS_VCVTA, "vcvta" }, >+ { ARM_INS_VCVTB, "vcvtb" }, >+ { ARM_INS_VCVT, "vcvt" }, >+ { ARM_INS_VCVTM, "vcvtm" }, >+ { ARM_INS_VCVTN, "vcvtn" }, >+ { ARM_INS_VCVTP, "vcvtp" }, >+ { ARM_INS_VCVTT, "vcvtt" }, >+ { ARM_INS_VDIV, "vdiv" }, >+ { ARM_INS_VDUP, "vdup" }, >+ { ARM_INS_VEOR, "veor" }, >+ { ARM_INS_VEXT, "vext" }, >+ { ARM_INS_VFMA, "vfma" }, >+ { ARM_INS_VFMS, "vfms" }, >+ { ARM_INS_VFNMA, "vfnma" }, >+ { ARM_INS_VFNMS, "vfnms" }, >+ { ARM_INS_VHADD, "vhadd" }, >+ { ARM_INS_VHSUB, "vhsub" }, >+ { ARM_INS_VLD1, "vld1" }, >+ { ARM_INS_VLD2, "vld2" }, >+ { ARM_INS_VLD3, "vld3" }, >+ { ARM_INS_VLD4, "vld4" }, >+ { ARM_INS_VLDMDB, "vldmdb" }, >+ { ARM_INS_VLDMIA, "vldmia" }, >+ { ARM_INS_VLDR, "vldr" }, >+ { ARM_INS_VMAXNM, "vmaxnm" }, >+ { ARM_INS_VMAX, "vmax" }, >+ { ARM_INS_VMINNM, "vminnm" }, >+ { ARM_INS_VMIN, "vmin" }, >+ { ARM_INS_VMLA, "vmla" }, >+ { ARM_INS_VMLAL, "vmlal" }, >+ { ARM_INS_VMLS, "vmls" }, >+ { ARM_INS_VMLSL, "vmlsl" }, >+ { ARM_INS_VMOVL, "vmovl" }, >+ { ARM_INS_VMOVN, "vmovn" }, >+ { ARM_INS_VMSR, "vmsr" }, >+ { ARM_INS_VMUL, "vmul" }, >+ { ARM_INS_VMULL, "vmull" }, >+ { ARM_INS_VMVN, "vmvn" }, >+ { ARM_INS_VNEG, "vneg" }, >+ { ARM_INS_VNMLA, "vnmla" }, >+ { ARM_INS_VNMLS, "vnmls" }, >+ { ARM_INS_VNMUL, "vnmul" }, >+ { ARM_INS_VORN, "vorn" }, >+ { ARM_INS_VORR, "vorr" }, >+ { ARM_INS_VPADAL, "vpadal" }, >+ { ARM_INS_VPADDL, "vpaddl" }, >+ { ARM_INS_VPADD, "vpadd" }, >+ { ARM_INS_VPMAX, "vpmax" }, >+ { ARM_INS_VPMIN, "vpmin" }, >+ { ARM_INS_VQABS, "vqabs" }, >+ { ARM_INS_VQADD, "vqadd" }, >+ { ARM_INS_VQDMLAL, "vqdmlal" }, >+ { ARM_INS_VQDMLSL, "vqdmlsl" }, >+ { ARM_INS_VQDMULH, "vqdmulh" }, >+ { ARM_INS_VQDMULL, "vqdmull" }, >+ { ARM_INS_VQMOVUN, "vqmovun" }, >+ { ARM_INS_VQMOVN, "vqmovn" }, >+ { ARM_INS_VQNEG, "vqneg" }, >+ { ARM_INS_VQRDMULH, "vqrdmulh" }, >+ { ARM_INS_VQRSHL, "vqrshl" }, >+ { ARM_INS_VQRSHRN, "vqrshrn" }, >+ { ARM_INS_VQRSHRUN, "vqrshrun" }, >+ { ARM_INS_VQSHL, "vqshl" }, >+ { ARM_INS_VQSHLU, "vqshlu" }, >+ { ARM_INS_VQSHRN, "vqshrn" }, >+ { ARM_INS_VQSHRUN, "vqshrun" }, >+ { ARM_INS_VQSUB, "vqsub" }, >+ { ARM_INS_VRADDHN, "vraddhn" }, >+ { ARM_INS_VRECPE, "vrecpe" }, >+ { ARM_INS_VRECPS, "vrecps" }, >+ { ARM_INS_VREV16, "vrev16" }, >+ { ARM_INS_VREV32, "vrev32" }, >+ { ARM_INS_VREV64, "vrev64" }, >+ { ARM_INS_VRHADD, "vrhadd" }, >+ { ARM_INS_VRINTA, "vrinta" }, >+ { ARM_INS_VRINTM, "vrintm" }, >+ { ARM_INS_VRINTN, "vrintn" }, >+ { ARM_INS_VRINTP, "vrintp" }, >+ { ARM_INS_VRINTR, "vrintr" }, >+ { ARM_INS_VRINTX, "vrintx" }, >+ { ARM_INS_VRINTZ, "vrintz" }, >+ { ARM_INS_VRSHL, "vrshl" }, >+ { ARM_INS_VRSHRN, "vrshrn" }, >+ { ARM_INS_VRSHR, "vrshr" }, >+ { ARM_INS_VRSQRTE, "vrsqrte" }, >+ { ARM_INS_VRSQRTS, "vrsqrts" }, >+ { ARM_INS_VRSRA, "vrsra" }, >+ { ARM_INS_VRSUBHN, "vrsubhn" }, >+ { ARM_INS_VSELEQ, "vseleq" }, >+ { ARM_INS_VSELGE, "vselge" }, >+ { ARM_INS_VSELGT, "vselgt" }, >+ { ARM_INS_VSELVS, "vselvs" }, >+ { ARM_INS_VSHLL, "vshll" }, >+ { ARM_INS_VSHL, "vshl" }, >+ { ARM_INS_VSHRN, "vshrn" }, >+ { ARM_INS_VSHR, "vshr" }, >+ { ARM_INS_VSLI, "vsli" }, >+ { ARM_INS_VSQRT, "vsqrt" }, >+ { ARM_INS_VSRA, "vsra" }, >+ { ARM_INS_VSRI, "vsri" }, >+ { ARM_INS_VST1, "vst1" }, >+ { ARM_INS_VST2, "vst2" }, >+ { ARM_INS_VST3, "vst3" }, >+ { ARM_INS_VST4, "vst4" }, >+ { ARM_INS_VSTMDB, "vstmdb" }, >+ { ARM_INS_VSTMIA, "vstmia" }, >+ { ARM_INS_VSTR, "vstr" }, >+ { ARM_INS_VSUB, "vsub" }, >+ { ARM_INS_VSUBHN, "vsubhn" }, >+ { ARM_INS_VSUBL, "vsubl" }, >+ { ARM_INS_VSUBW, "vsubw" }, >+ { ARM_INS_VSWP, "vswp" }, >+ { ARM_INS_VTBL, "vtbl" }, >+ { ARM_INS_VTBX, "vtbx" }, >+ { ARM_INS_VCVTR, "vcvtr" }, >+ { ARM_INS_VTRN, "vtrn" }, >+ { ARM_INS_VTST, "vtst" }, >+ { ARM_INS_VUZP, "vuzp" }, >+ { ARM_INS_VZIP, "vzip" }, >+ { ARM_INS_ADDW, "addw" }, >+ { ARM_INS_ASR, "asr" }, >+ { ARM_INS_DCPS1, "dcps1" }, >+ { ARM_INS_DCPS2, "dcps2" }, >+ { ARM_INS_DCPS3, "dcps3" }, >+ { ARM_INS_IT, "it" }, >+ { ARM_INS_LSL, "lsl" }, >+ { ARM_INS_LSR, "lsr" }, >+ { ARM_INS_ASRS, "asrs" }, >+ { ARM_INS_LSRS, "lsrs" }, >+ { ARM_INS_ORN, "orn" }, >+ { ARM_INS_ROR, "ror" }, >+ { ARM_INS_RRX, "rrx" }, >+ { ARM_INS_SUBS, "subs" }, >+ { ARM_INS_SUBW, "subw" }, >+ { ARM_INS_TBB, "tbb" }, >+ { ARM_INS_TBH, "tbh" }, >+ { ARM_INS_CBNZ, "cbnz" }, >+ { ARM_INS_CBZ, "cbz" }, >+ { ARM_INS_MOVS, "movs" }, >+ { ARM_INS_POP, "pop" }, >+ { ARM_INS_PUSH, "push" }, >+ >+ // special instructions >+ { ARM_INS_NOP, "nop" }, >+ { ARM_INS_YIELD, "yield" }, >+ { ARM_INS_WFE, "wfe" }, >+ { ARM_INS_WFI, "wfi" }, >+ { ARM_INS_SEV, "sev" }, >+ { ARM_INS_SEVL, "sevl" }, >+ { ARM_INS_VPUSH, "vpush" }, >+ { ARM_INS_VPOP, "vpop" }, >+}; >+#endif >+ >+const char *ARM_insn_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ if (id >= ARM_INS_ENDING) >+ return NULL; >+ >+ return insn_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+#ifndef CAPSTONE_DIET >+static const name_map group_name_maps[] = { >+ // generic groups >+ { ARM_GRP_INVALID, NULL }, >+ { ARM_GRP_JUMP, "jump" }, >+ >+ // architecture-specific groups >+ { ARM_GRP_CRYPTO, "crypto" }, >+ { ARM_GRP_DATABARRIER, "databarrier" }, >+ { ARM_GRP_DIVIDE, "divide" }, >+ { ARM_GRP_FPARMV8, "fparmv8" }, >+ { ARM_GRP_MULTPRO, "multpro" }, >+ { ARM_GRP_NEON, "neon" }, >+ { ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" }, >+ { ARM_GRP_THUMB2DSP, "THUMB2DSP" }, >+ { ARM_GRP_TRUSTZONE, "TRUSTZONE" }, >+ { ARM_GRP_V4T, "v4t" }, >+ { ARM_GRP_V5T, "v5t" }, >+ { ARM_GRP_V5TE, "v5te" }, >+ { ARM_GRP_V6, "v6" }, >+ { ARM_GRP_V6T2, "v6t2" }, >+ { ARM_GRP_V7, "v7" }, >+ { ARM_GRP_V8, "v8" }, >+ { ARM_GRP_VFP2, "vfp2" }, >+ { ARM_GRP_VFP3, "vfp3" }, >+ { ARM_GRP_VFP4, "vfp4" }, >+ { ARM_GRP_ARM, "arm" }, >+ { ARM_GRP_MCLASS, "mclass" }, >+ { ARM_GRP_NOTMCLASS, "notmclass" }, >+ { ARM_GRP_THUMB, "thumb" }, >+ { ARM_GRP_THUMB1ONLY, "thumb1only" }, >+ { ARM_GRP_THUMB2, "thumb2" }, >+ { ARM_GRP_PREV8, "prev8" }, >+ { ARM_GRP_FPVMLX, "fpvmlx" }, >+ { ARM_GRP_MULOPS, "mulops" }, >+ { ARM_GRP_CRC, "crc" }, >+ { ARM_GRP_DPVFP, "dpvfp" }, >+ { ARM_GRP_V6M, "v6m" }, >+}; >+#endif >+ >+const char *ARM_group_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ // verify group id >+ if (id >= ARM_GRP_ENDING || (id > ARM_GRP_JUMP && id < ARM_GRP_CRYPTO)) >+ return NULL; >+ >+ // NOTE: when new generic groups are added, 2 must be changed accordingly >+ if (id >= 128) >+ return group_name_maps[id - 128 + 2].name; >+ else >+ return group_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+// list all relative branch instructions >+// ie: insns[i].branch && !insns[i].indirect_branch >+static const unsigned int insn_rel[] = { >+ ARM_BL, >+ ARM_BLX_pred, >+ ARM_Bcc, >+ ARM_t2B, >+ ARM_t2Bcc, >+ ARM_tB, >+ ARM_tBcc, >+ ARM_tCBNZ, >+ ARM_tCBZ, >+ ARM_BL_pred, >+ ARM_BLXi, >+ ARM_tBL, >+ ARM_tBLXi, >+ 0 >+}; >+ >+static const unsigned int insn_blx_rel_to_arm[] = { >+ ARM_tBLXi, >+ 0 >+}; >+ >+// check if this insn is relative branch >+bool ARM_rel_branch(cs_struct *h, unsigned int id) >+{ >+ int i; >+ >+ for (i = 0; insn_rel[i]; i++) { >+ if (id == insn_rel[i]) { >+ return true; >+ } >+ } >+ >+ // not found >+ return false; >+} >+ >+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) { >+ int i; >+ >+ for (i = 0; insn_blx_rel_to_arm[i]; i++) >+ if (id == insn_blx_rel_to_arm[i]) >+ return true; >+ >+ // not found >+ return false; >+ >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h b/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h >new file mode 100644 >index 0000000000000000000000000000000000000000..f537e555d1c5186cc32cc4093cdc36a6d9d64660 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMMapping.h >@@ -0,0 +1,26 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_ARM_MAP_H >+#define CS_ARM_MAP_H >+ >+#include "../../include/capstone.h" >+#include "../../utils.h" >+ >+// return name of regiser in friendly string >+const char *ARM_reg_name(csh handle, unsigned int reg); >+const char *ARM_reg_name2(csh handle, unsigned int reg); >+ >+// given internal insn id, return public instruction ID >+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+const char *ARM_insn_name(csh handle, unsigned int id); >+ >+const char *ARM_group_name(csh handle, unsigned int id); >+ >+// check if this insn is relative branch >+bool ARM_rel_branch(cs_struct *h, unsigned int insn_id); >+ >+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c b/Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c >new file mode 100644 >index 0000000000000000000000000000000000000000..a342c77cd8ebf4f4720bc2686d42089b67ebda2b >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/ARM/ARMModule.c >@@ -0,0 +1,76 @@ >+/* Capstone Disassembly Engine */ >+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ >+ >+#ifdef CAPSTONE_HAS_ARM >+ >+#include "../../cs_priv.h" >+#include "../../MCRegisterInfo.h" >+#include "ARMDisassembler.h" >+#include "ARMInstPrinter.h" >+#include "ARMMapping.h" >+ >+static cs_err init(cs_struct *ud) >+{ >+ MCRegisterInfo *mri; >+ mri = cs_mem_malloc(sizeof(*mri)); >+ >+ ARM_init(mri); >+ ARM_getRegName(ud, 0); // use default get_regname >+ >+ ud->printer = ARM_printInst; >+ ud->printer_info = mri; >+ ud->reg_name = ARM_reg_name; >+ ud->insn_id = ARM_get_insn_id; >+ ud->insn_name = ARM_insn_name; >+ ud->group_name = ARM_group_name; >+ ud->post_printer = ARM_post_printer; >+ >+ if (ud->mode & CS_MODE_THUMB) >+ ud->disasm = Thumb_getInstruction; >+ else >+ ud->disasm = ARM_getInstruction; >+ >+ return CS_ERR_OK; >+} >+ >+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) >+{ >+ switch(type) { >+ case CS_OPT_MODE: >+ if (value & CS_MODE_THUMB) >+ handle->disasm = Thumb_getInstruction; >+ else >+ handle->disasm = ARM_getInstruction; >+ >+ handle->mode = (cs_mode)value; >+ >+ break; >+ case CS_OPT_SYNTAX: >+ ARM_getRegName(handle, (int)value); >+ handle->syntax = (int)value; >+ break; >+ default: >+ break; >+ } >+ >+ return CS_ERR_OK; >+} >+ >+static void destroy(cs_struct *handle) >+{ >+} >+ >+void ARM_enable(void) >+{ >+ cs_arch_init[CS_ARCH_ARM] = init; >+ cs_arch_option[CS_ARCH_ARM] = option; >+ cs_arch_destroy[CS_ARCH_ARM] = destroy; >+ cs_arch_disallowed_mode_mask[CS_ARCH_ARM] = ~(CS_MODE_LITTLE_ENDIAN | >+ CS_MODE_ARM | CS_MODE_V8 | CS_MODE_MCLASS | CS_MODE_THUMB | >+ CS_MODE_BIG_ENDIAN); >+ >+ // support this arch >+ all_arch |= (1 << CS_ARCH_ARM); >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c b/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c >new file mode 100644 >index 0000000000000000000000000000000000000000..8fc5c7a977b4688d7a3e4a363e5bf2a105fa9a31 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.c >@@ -0,0 +1,1332 @@ >+//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file is part of the Mips Disassembler. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <stdio.h> >+#include <string.h> >+ >+#include <platform.h> >+ >+#include "../../utils.h" >+ >+#include "../../MCInst.h" >+#include "../../MCRegisterInfo.h" >+#include "../../SStream.h" >+ >+#include "../../MathExtras.h" >+ >+//#include "Mips.h" >+//#include "MipsRegisterInfo.h" >+//#include "MipsSubtarget.h" >+#include "../../MCFixedLenDisassembler.h" >+#include "../../MCInst.h" >+//#include "llvm/MC/MCSubtargetInfo.h" >+#include "../../MCRegisterInfo.h" >+#include "../../MCDisassembler.h" >+ >+// Forward declare these because the autogenerated code will reference them. >+// Definitions are further down. >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeJumpTarget(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget21(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBranchTarget26(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+// DecodeBranchTargetMM - Decode microMIPS branch offset, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+// DecodeJumpTargetMM - Decode microMIPS jump target, which is >+// shifted left by 1 bit. >+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCachePref(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMSA128Mem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMImm12(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeMemMMImm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+// Decode the immediate field of an LSA instruction which >+// is off by one. >+static DecodeStatus DecodeLSAImm(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeInsSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeExtSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't >+/// handle. >+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, >+ uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder); >+ >+ >+#define GET_SUBTARGETINFO_ENUM >+#include "MipsGenSubtargetInfo.inc" >+ >+// Hacky: enable all features for disassembler >+static uint64_t getFeatureBits(int mode) >+{ >+ uint64_t Bits = (uint64_t)-1; // include every features at first >+ >+ // By default we do not support Mips1 >+ Bits &= ~Mips_FeatureMips1; >+ >+ // No MicroMips >+ Bits &= ~Mips_FeatureMicroMips; >+ >+ // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() >+ // some features are mutually execlusive >+ if (mode & CS_MODE_16) { >+ //Bits &= ~Mips_FeatureMips32r2; >+ //Bits &= ~Mips_FeatureMips32; >+ //Bits &= ~Mips_FeatureFPIdx; >+ //Bits &= ~Mips_FeatureBitCount; >+ //Bits &= ~Mips_FeatureSwap; >+ //Bits &= ~Mips_FeatureSEInReg; >+ //Bits &= ~Mips_FeatureMips64r2; >+ //Bits &= ~Mips_FeatureFP64Bit; >+ } else if (mode & CS_MODE_32) { >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureFP64Bit; >+ Bits &= ~Mips_FeatureMips64r2; >+ Bits &= ~Mips_FeatureMips32r6; >+ Bits &= ~Mips_FeatureMips64r6; >+ } else if (mode & CS_MODE_64) { >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureMips64r6; >+ Bits &= ~Mips_FeatureMips32r6; >+ } else if (mode & CS_MODE_MIPS32R6) { >+ Bits |= Mips_FeatureMips32r6; >+ Bits &= ~Mips_FeatureMips16; >+ Bits &= ~Mips_FeatureFP64Bit; >+ Bits &= ~Mips_FeatureMips64r6; >+ Bits &= ~Mips_FeatureMips64r2; >+ } >+ >+ if (mode & CS_MODE_MICRO) { >+ Bits |= Mips_FeatureMicroMips; >+ Bits &= ~Mips_FeatureMips4_32r2; >+ Bits &= ~Mips_FeatureMips2; >+ } >+ >+ return Bits; >+} >+ >+#include "MipsGenDisassemblerTables.inc" >+ >+#define GET_REGINFO_ENUM >+#include "MipsGenRegisterInfo.inc" >+ >+#define GET_REGINFO_MC_DESC >+#include "MipsGenRegisterInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+void Mips_init(MCRegisterInfo *MRI) >+{ >+ // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC, >+ // MipsMCRegisterClasses, 48, >+ // MipsRegUnitRoots, >+ // 273, >+ // MipsRegDiffLists, >+ // MipsRegStrings, >+ // MipsSubRegIdxLists, >+ // 12, >+ // MipsSubRegIdxRanges, >+ // MipsRegEncodingTable); >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394, >+ 0, 0, >+ MipsMCRegisterClasses, 48, >+ 0, 0, >+ MipsRegDiffLists, >+ 0, >+ MipsSubRegIdxLists, 12, >+ 0); >+} >+ >+/// readInstruction - read four bytes from the MemoryObject >+/// and return 32 bit word sorted according to the given endianess >+static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) >+{ >+ // We want to read exactly 4 Bytes of data. >+ if (isBigEndian) { >+ // Encoded as a big-endian 32-bit word in the stream. >+ *insn = (code[3] << 0) | >+ (code[2] << 8) | >+ (code[1] << 16) | >+ (code[0] << 24); >+ } else { >+ // Encoded as a small-endian 32-bit word in the stream. >+ // Little-endian byte ordering: >+ // mips32r2: 4 | 3 | 2 | 1 >+ // microMIPS: 2 | 1 | 4 | 3 >+ if (isMicroMips) { >+ *insn = (code[2] << 0) | >+ (code[3] << 8) | >+ (code[0] << 16) | >+ (code[1] << 24); >+ } else { >+ *insn = (code[0] << 0) | >+ (code[1] << 8) | >+ (code[2] << 16) | >+ (code[3] << 24); >+ } >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, >+ const uint8_t *code, size_t code_len, >+ uint16_t *Size, >+ uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) >+{ >+ uint32_t Insn; >+ DecodeStatus Result; >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (instr->flat_insn->detail) { >+ memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); >+ } >+ >+ Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, >+ mode & CS_MODE_MICRO); >+ if (Result == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ if (mode & CS_MODE_MICRO) { >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ return MCDisassembler_Fail; >+ } >+ >+#if 0 >+ // TODO: properly handle this in the future with MIPS1/2 modes >+ if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) { // COP3 >+ // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+#endif >+ >+ if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) { >+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, >+ Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ if ((mode & CS_MODE_MIPS32R6) != 0) { >+ // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); >+ Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, >+ Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ } >+ >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ >+ return MCDisassembler_Fail; >+} >+ >+bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ cs_struct *handle = (cs_struct *)(uintptr_t)ud; >+ >+ DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, >+ code, code_len, >+ size, >+ address, MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); >+ >+ return status == MCDisassembler_Success; >+} >+ >+static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr, >+ const uint8_t *code, size_t code_len, >+ uint16_t *Size, >+ uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) >+{ >+ uint32_t Insn; >+ DecodeStatus Result; >+ >+ if (code_len < 4) >+ // not enough data >+ return MCDisassembler_Fail; >+ >+ if (instr->flat_insn->detail) { >+ memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); >+ } >+ >+ Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); >+ if (Result == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ if (instr->flat_insn->detail) { >+ memset(instr->flat_insn->detail, 0, sizeof(cs_detail)); >+ } >+ >+ // Calling the auto-generated decoder function. >+ Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ >+ // If we fail to decode in Mips64 decoder space we can try in Mips32 >+ Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); >+ if (Result != MCDisassembler_Fail) { >+ *Size = 4; >+ return Result; >+ } >+ >+ return MCDisassembler_Fail; >+} >+ >+bool Mips64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, >+ uint16_t *size, uint64_t address, void *info) >+{ >+ cs_struct *handle = (cs_struct *)(uintptr_t)ud; >+ >+ DecodeStatus status = Mips64Disassembler_getInstruction(handle->mode, instr, >+ code, code_len, size, address, >+ MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info); >+ >+ return status == MCDisassembler_Success; >+} >+ >+static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) >+{ >+ //MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); >+ //return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); >+ const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); >+ return rc->RegsBegin[RegNo]; >+} >+ >+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *); >+ // The size of the n field depends on the element size >+ // The register class also depends on this. >+ uint32_t tmp = fieldFromInstruction(insn, 17, 5); >+ unsigned NSize = 0; >+ DecodeFN RegDecoder = NULL; >+ >+ if ((tmp & 0x18) == 0x00) { // INSVE_B >+ NSize = 4; >+ RegDecoder = DecodeMSA128BRegisterClass; >+ } else if ((tmp & 0x1c) == 0x10) { // INSVE_H >+ NSize = 3; >+ RegDecoder = DecodeMSA128HRegisterClass; >+ } else if ((tmp & 0x1e) == 0x18) { // INSVE_W >+ NSize = 2; >+ RegDecoder = DecodeMSA128WRegisterClass; >+ } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D >+ NSize = 1; >+ RegDecoder = DecodeMSA128DRegisterClass; >+ } //else llvm_unreachable("Invalid encoding"); >+ >+ //assert(NSize != 0 && RegDecoder != nullptr); >+ if (NSize == 0 || RegDecoder == NULL) >+ return MCDisassembler_Fail; >+ >+ if (RegDecoder == NULL) >+ return MCDisassembler_Fail; >+ >+ // $wd >+ tmp = fieldFromInstruction(insn, 6, 5); >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $wd_in >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $n >+ tmp = fieldFromInstruction(insn, 16, NSize); >+ MCOperand_CreateImm0(MI, tmp); >+ >+ // $ws >+ tmp = fieldFromInstruction(insn, 11, 5); >+ if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) >+ return MCDisassembler_Fail; >+ >+ // $n2 >+ MCOperand_CreateImm0(MI, 0); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the ADDI instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b001000 sssss ttttt iiiiiiiiiiiiiiii >+ // BOVC if rs >= rt >+ // BEQZALC if rs == 0 && rt != 0 >+ // BEQC if rs < rt && rs != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rs >= Rt) { >+ MCInst_setOpcode(MI, Mips_BOVC); >+ HasRs = true; >+ } else if (Rs != 0 && Rs < Rt) { >+ MCInst_setOpcode(MI, Mips_BEQC); >+ HasRs = true; >+ } else >+ MCInst_setOpcode(MI, Mips_BEQZALC); >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the ADDI instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b011000 sssss ttttt iiiiiiiiiiiiiiii >+ // BNVC if rs >= rt >+ // BNEZALC if rs == 0 && rt != 0 >+ // BNEC if rs < rt && rs != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rs >= Rt) { >+ MCInst_setOpcode(MI, Mips_BNVC); >+ HasRs = true; >+ } else if (Rs != 0 && Rs < Rt) { >+ MCInst_setOpcode(MI, Mips_BNEC); >+ HasRs = true; >+ } else >+ MCInst_setOpcode(MI, Mips_BNEZALC); >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BLEZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b010110 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BLEZC if rs == 0 && rt != 0 >+ // BGEZC if rs == rt && rt != 0 >+ // BGEC if rs != rt && rs != 0 && rt != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BLEZC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BGEZC); >+ else { >+ HasRs = true; >+ MCInst_setOpcode(MI, Mips_BGEC); >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BGTZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b010111 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BGTZC if rs == 0 && rt != 0 >+ // BLTZC if rs == rt && rt != 0 >+ // BLTC if rs != rt && rs != 0 && rt != 0 >+ >+ bool HasRs = false; >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BGTZC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BLTZC); >+ else { >+ MCInst_setOpcode(MI, Mips_BLTC); >+ HasRs = true; >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BGTZ instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b000111 sssss ttttt iiiiiiiiiiiiiiii >+ // BGTZ if rt == 0 >+ // BGTZALC if rs == 0 && rt != 0 >+ // BLTZALC if rs != 0 && rs == rt >+ // BLTUC if rs != 0 && rs != rt >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ bool HasRt = false; >+ >+ if (Rt == 0) { >+ MCInst_setOpcode(MI, Mips_BGTZ); >+ HasRs = true; >+ } else if (Rs == 0) { >+ MCInst_setOpcode(MI, Mips_BGTZALC); >+ HasRt = true; >+ } else if (Rs == Rt) { >+ MCInst_setOpcode(MI, Mips_BLTZALC); >+ HasRs = true; >+ } else { >+ MCInst_setOpcode(MI, Mips_BLTUC); >+ HasRs = true; >+ HasRt = true; >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ if (HasRt) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled >+ // (otherwise we would have matched the BLEZL instruction from the earlier >+ // ISA's instead). >+ // >+ // We have: >+ // 0b000110 sssss ttttt iiiiiiiiiiiiiiii >+ // Invalid if rs == 0 >+ // BLEZALC if rs == 0 && rt != 0 >+ // BGEZALC if rs == rt && rt != 0 >+ // BGEUC if rs != rt && rs != 0 && rt != 0 >+ >+ uint32_t Rs = fieldFromInstruction(insn, 21, 5); >+ uint32_t Rt = fieldFromInstruction(insn, 16, 5); >+ uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; >+ bool HasRs = false; >+ >+ if (Rt == 0) >+ return MCDisassembler_Fail; >+ else if (Rs == 0) >+ MCInst_setOpcode(MI, Mips_BLEZALC); >+ else if (Rs == Rt) >+ MCInst_setOpcode(MI, Mips_BGEZALC); >+ else { >+ HasRs = true; >+ MCInst_setOpcode(MI, Mips_BGEUC); >+ } >+ >+ if (HasRs) >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs)); >+ >+ MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt)); >+ >+ MCOperand_CreateImm0(MI, Imm); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ return MCDisassembler_Fail; >+} >+ >+static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ if (Inst->csh->mode & CS_MODE_64) >+ return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); >+ >+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); >+} >+ >+static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_CCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ if (MCInst_getOpcode(Inst) == Mips_SC){ >+ MCOperand_CreateReg0(Inst, Reg); >+ } >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCachePref(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Hint = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ MCOperand_CreateImm0(Inst, Hint); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, >+ uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); >+ unsigned Reg = fieldFromInstruction(Insn, 6, 5); >+ unsigned Base = fieldFromInstruction(Insn, 11, 5); >+ >+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ // MCOperand_CreateImm0(Inst, Offset); >+ >+ // The immediate field of an LD/ST instruction is scaled which means it must >+ // be multiplied (when decoding) by the size (in bytes) of the instructions' >+ // data format. >+ // .b - 1 byte >+ // .h - 2 bytes >+ // .w - 4 bytes >+ // .d - 8 bytes >+ switch(MCInst_getOpcode(Inst)) { >+ default: >+ //assert (0 && "Unexpected instruction"); >+ return MCDisassembler_Fail; >+ break; >+ case Mips_LD_B: >+ case Mips_ST_B: >+ MCOperand_CreateImm0(Inst, Offset); >+ break; >+ case Mips_LD_H: >+ case Mips_ST_H: >+ MCOperand_CreateImm0(Inst, Offset * 2); >+ break; >+ case Mips_LD_W: >+ case Mips_ST_W: >+ MCOperand_CreateImm0(Inst, Offset * 4); >+ break; >+ case Mips_LD_D: >+ case Mips_ST_D: >+ MCOperand_CreateImm0(Inst, Offset * 8); >+ break; >+ } >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMImm12(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0x0fff, 12); >+ unsigned Reg = fieldFromInstruction(Insn, 21, 5); >+ unsigned Base = fieldFromInstruction(Insn, 16, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ if (MCInst_getOpcode(Inst) == Mips_SC_MM) >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMemMMImm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 21, 5); >+ unsigned Base = fieldFromInstruction(Insn, 16, 5); >+ >+ Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeFMem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCOP2Mem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_COP2RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCOP3Mem(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Offset = SignExtend32(Insn & 0xffff, 16); >+ unsigned Reg = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Reg = getReg(Decoder, Mips_COP3RegClassID, Reg); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ MCOperand_CreateReg0(Inst, Reg); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9); >+ unsigned Rt = fieldFromInstruction(Insn, 16, 5); >+ unsigned Base = fieldFromInstruction(Insn, 21, 5); >+ >+ Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt); >+ Base = getReg(Decoder, Mips_GPR32RegClassID, Base); >+ >+ if (MCInst_getOpcode(Inst) == Mips_SC_R6 || >+ MCInst_getOpcode(Inst) == Mips_SCD_R6) { >+ MCOperand_CreateReg0(Inst, Rt); >+ } >+ >+ MCOperand_CreateReg0(Inst, Rt); >+ MCOperand_CreateReg0(Inst, Base); >+ MCOperand_CreateImm0(Inst, Offset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // Currently only hardware register 29 is supported. >+ if (RegNo != 29) >+ return MCDisassembler_Fail; >+ >+ MCOperand_CreateReg0(Inst, Mips_HWR29); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 30 || RegNo % 2) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo >= 4) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 7) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, >+ unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned Reg; >+ >+ if (RegNo > 31) >+ return MCDisassembler_Fail; >+ >+ Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo); >+ MCOperand_CreateReg0(Inst, Reg); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4; >+ MCOperand_CreateImm0(Inst, TargetAddress); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeJumpTarget(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF); >+ MCOperand_CreateImm0(Inst, TargetAddress); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget21(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 21) * 4; >+ >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTarget26(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 26) * 4; >+ >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, >+ unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int32_t BranchOffset = SignExtend32(Offset, 16) * 2; >+ MCOperand_CreateImm0(Inst, BranchOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; >+ MCOperand_CreateImm0(Inst, JumpOffset); >+ >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm16(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeLSAImm(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // We add one to the immediate field as it was encoded as 'imm - 1'. >+ MCOperand_CreateImm0(Inst, Insn + 1); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeInsSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ // First we need to grab the pos(lsb) from MCInst. >+ int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2)); >+ int Size = (int) Insn - Pos + 1; >+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeExtSize(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ int Size = (int) Insn + 1; >+ MCOperand_CreateImm0(Inst, SignExtend32(Size, 16)); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4); >+ return MCDisassembler_Success; >+} >+ >+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, >+ unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder) >+{ >+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8); >+ return MCDisassembler_Success; >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h b/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..933a99eb94303d3ea8642640f84be3e4282db516 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsDisassembler.h >@@ -0,0 +1,20 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_MIPSDISASSEMBLER_H >+#define CS_MIPSDISASSEMBLER_H >+ >+#include "../../include/capstone.h" >+ >+#include "../../include/capstone.h" >+#include "../../MCRegisterInfo.h" >+ >+void Mips_init(MCRegisterInfo *MRI); >+ >+bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+bool Mips64_getInstruction(csh handle, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..32470a0bbbaff9b97656a3694ae860ec35c352fd >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenAsmWriter.inc >@@ -0,0 +1,5475 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 9110U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 9103U, // BUNDLE >+ 9120U, // LIFETIME_START >+ 9090U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 21425U, // ABSQ_S_PH >+ 17795U, // ABSQ_S_QB >+ 24564U, // ABSQ_S_W >+ 33574461U, // ADD >+ 18064U, // ADDIUPC >+ 33575662U, // ADDQH_PH >+ 33575779U, // ADDQH_R_PH >+ 33578671U, // ADDQH_R_W >+ 33578274U, // ADDQH_W >+ 33575736U, // ADDQ_PH >+ 33575835U, // ADDQ_S_PH >+ 33578976U, // ADDQ_S_W >+ 33572524U, // ADDSC >+ 33571204U, // ADDS_A_B >+ 33572649U, // ADDS_A_D >+ 33574607U, // ADDS_A_H >+ 33577982U, // ADDS_A_W >+ 33571672U, // ADDS_S_B >+ 33573738U, // ADDS_S_D >+ 33575164U, // ADDS_S_H >+ 33579026U, // ADDS_S_W >+ 33571887U, // ADDS_U_B >+ 33574205U, // ADDS_U_D >+ 33575442U, // ADDS_U_H >+ 33579444U, // ADDS_U_W >+ 33572095U, // ADDUH_QB >+ 33572203U, // ADDUH_R_QB >+ 33575934U, // ADDU_PH >+ 33572308U, // ADDU_QB >+ 33575879U, // ADDU_S_PH >+ 33572249U, // ADDU_S_QB >+ 570442365U, // ADDVI_B >+ 570444081U, // ADDVI_D >+ 570445735U, // ADDVI_H >+ 570449319U, // ADDVI_W >+ 33571965U, // ADDV_B >+ 33574305U, // ADDV_D >+ 33575520U, // ADDV_H >+ 33579544U, // ADDV_W >+ 33572563U, // ADDWC >+ 33571186U, // ADD_A_B >+ 33572630U, // ADD_A_D >+ 33574589U, // ADD_A_H >+ 33577963U, // ADD_A_W >+ 33574461U, // ADD_MM >+ 33576147U, // ADDi >+ 33576147U, // ADDi_MM >+ 33577725U, // ADDiu >+ 33577725U, // ADDiu_MM >+ 33577679U, // ADDu >+ 33577679U, // ADDu_MM >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 33576610U, // ALIGN >+ 18056U, // ALUIPC >+ 33574483U, // AND >+ 33574483U, // AND64 >+ 570442224U, // ANDI_B >+ 33574483U, // AND_MM >+ 33577807U, // AND_V >+ 0U, // AND_V_D_PSEUDO >+ 0U, // AND_V_H_PSEUDO >+ 0U, // AND_V_W_PSEUDO >+ 1107317977U, // ANDi >+ 1107317977U, // ANDi64 >+ 1107317977U, // ANDi_MM >+ 1107316321U, // APPEND >+ 33571566U, // ASUB_S_B >+ 33573568U, // ASUB_S_D >+ 33574996U, // ASUB_S_H >+ 33578806U, // ASUB_S_W >+ 33571781U, // ASUB_U_B >+ 33574035U, // ASUB_U_D >+ 33575284U, // ASUB_U_H >+ 33579274U, // ASUB_U_W >+ 0U, // ATOMIC_CMP_SWAP_I16 >+ 0U, // ATOMIC_CMP_SWAP_I32 >+ 0U, // ATOMIC_CMP_SWAP_I64 >+ 0U, // ATOMIC_CMP_SWAP_I8 >+ 0U, // ATOMIC_LOAD_ADD_I16 >+ 0U, // ATOMIC_LOAD_ADD_I32 >+ 0U, // ATOMIC_LOAD_ADD_I64 >+ 0U, // ATOMIC_LOAD_ADD_I8 >+ 0U, // ATOMIC_LOAD_AND_I16 >+ 0U, // ATOMIC_LOAD_AND_I32 >+ 0U, // ATOMIC_LOAD_AND_I64 >+ 0U, // ATOMIC_LOAD_AND_I8 >+ 0U, // ATOMIC_LOAD_NAND_I16 >+ 0U, // ATOMIC_LOAD_NAND_I32 >+ 0U, // ATOMIC_LOAD_NAND_I64 >+ 0U, // ATOMIC_LOAD_NAND_I8 >+ 0U, // ATOMIC_LOAD_OR_I16 >+ 0U, // ATOMIC_LOAD_OR_I32 >+ 0U, // ATOMIC_LOAD_OR_I64 >+ 0U, // ATOMIC_LOAD_OR_I8 >+ 0U, // ATOMIC_LOAD_SUB_I16 >+ 0U, // ATOMIC_LOAD_SUB_I32 >+ 0U, // ATOMIC_LOAD_SUB_I64 >+ 0U, // ATOMIC_LOAD_SUB_I8 >+ 0U, // ATOMIC_LOAD_XOR_I16 >+ 0U, // ATOMIC_LOAD_XOR_I32 >+ 0U, // ATOMIC_LOAD_XOR_I64 >+ 0U, // ATOMIC_LOAD_XOR_I8 >+ 0U, // ATOMIC_SWAP_I16 >+ 0U, // ATOMIC_SWAP_I32 >+ 0U, // ATOMIC_SWAP_I64 >+ 0U, // ATOMIC_SWAP_I8 >+ 33576257U, // AUI >+ 18049U, // AUIPC >+ 33571652U, // AVER_S_B >+ 33573718U, // AVER_S_D >+ 33575134U, // AVER_S_H >+ 33579006U, // AVER_S_W >+ 33571867U, // AVER_U_B >+ 33574185U, // AVER_U_D >+ 33575422U, // AVER_U_H >+ 33579424U, // AVER_U_W >+ 33571594U, // AVE_S_B >+ 33573650U, // AVE_S_D >+ 33575066U, // AVE_S_H >+ 33578888U, // AVE_S_W >+ 33571809U, // AVE_U_B >+ 33574117U, // AVE_U_D >+ 33575354U, // AVE_U_H >+ 33579356U, // AVE_U_W >+ 23293U, // AddiuRxImmX16 >+ 154365U, // AddiuRxPcImmX16 >+ 69229309U, // AddiuRxRxImm16 >+ 2120445U, // AddiuRxRxImmX16 >+ 4217597U, // AddiuRxRyOffMemX16 >+ 287481U, // AddiuSpImm16 >+ 418553U, // AddiuSpImmX16 >+ 33577679U, // AdduRxRyRz16 >+ 2117203U, // AndRxRxRy16 >+ 0U, // B >+ 33577678U, // BADDu >+ 415079U, // BAL >+ 411192U, // BALC >+ 1107318433U, // BALIGN >+ 0U, // BAL_BR >+ 411171U, // BC >+ 20116U, // BC0F >+ 21976U, // BC0FL >+ 23169U, // BC0T >+ 22105U, // BC0TL >+ 25447U, // BC1EQZ >+ 20122U, // BC1F >+ 21983U, // BC1FL >+ 20122U, // BC1F_MM >+ 25431U, // BC1NEZ >+ 23175U, // BC1T >+ 22112U, // BC1TL >+ 23175U, // BC1T_MM >+ 25455U, // BC2EQZ >+ 20128U, // BC2F >+ 21990U, // BC2FL >+ 25439U, // BC2NEZ >+ 23181U, // BC2T >+ 22119U, // BC2TL >+ 20134U, // BC3F >+ 21997U, // BC3FL >+ 23187U, // BC3T >+ 22126U, // BC3TL >+ 570442293U, // BCLRI_B >+ 570444025U, // BCLRI_D >+ 570445679U, // BCLRI_H >+ 570449263U, // BCLRI_W >+ 33571533U, // BCLR_B >+ 33573492U, // BCLR_D >+ 33574963U, // BCLR_H >+ 33578722U, // BCLR_W >+ 33576764U, // BEQ >+ 33576764U, // BEQ64 >+ 33572518U, // BEQC >+ 33576525U, // BEQL >+ 18016U, // BEQZALC >+ 18159U, // BEQZC >+ 18159U, // BEQZC_MM >+ 33576764U, // BEQ_MM >+ 33572391U, // BGEC >+ 33572537U, // BGEUC >+ 25214U, // BGEZ >+ 25214U, // BGEZ64 >+ 21873U, // BGEZAL >+ 17989U, // BGEZALC >+ 22069U, // BGEZALL >+ 23144U, // BGEZALS_MM >+ 21873U, // BGEZAL_MM >+ 18138U, // BGEZC >+ 22149U, // BGEZL >+ 25214U, // BGEZ_MM >+ 25274U, // BGTZ >+ 25274U, // BGTZ64 >+ 18025U, // BGTZALC >+ 18166U, // BGTZC >+ 22163U, // BGTZL >+ 25274U, // BGTZ_MM >+ 1646281242U, // BINSLI_B >+ 1646282974U, // BINSLI_D >+ 1646284628U, // BINSLI_H >+ 1646288212U, // BINSLI_W >+ 2183152301U, // BINSL_B >+ 2183154086U, // BINSL_D >+ 2183155654U, // BINSL_H >+ 2183159282U, // BINSL_W >+ 1646281303U, // BINSRI_B >+ 1646283019U, // BINSRI_D >+ 1646284673U, // BINSRI_H >+ 1646288257U, // BINSRI_W >+ 2183152349U, // BINSR_B >+ 2183154342U, // BINSR_D >+ 2183155779U, // BINSR_H >+ 2183159572U, // BINSR_W >+ 23447U, // BITREV >+ 22225U, // BITSWAP >+ 25220U, // BLEZ >+ 25220U, // BLEZ64 >+ 17998U, // BLEZALC >+ 18145U, // BLEZC >+ 22156U, // BLEZL >+ 25220U, // BLEZ_MM >+ 33572531U, // BLTC >+ 33572544U, // BLTUC >+ 25280U, // BLTZ >+ 25280U, // BLTZ64 >+ 21881U, // BLTZAL >+ 18034U, // BLTZALC >+ 22078U, // BLTZALL >+ 23153U, // BLTZALS_MM >+ 21881U, // BLTZAL_MM >+ 18173U, // BLTZC >+ 22170U, // BLTZL >+ 25280U, // BLTZ_MM >+ 1646281358U, // BMNZI_B >+ 2183158664U, // BMNZ_V >+ 1646281350U, // BMZI_B >+ 2183158650U, // BMZ_V >+ 33574527U, // BNE >+ 33574527U, // BNE64 >+ 33572397U, // BNEC >+ 570442232U, // BNEGI_B >+ 570443973U, // BNEGI_D >+ 570445627U, // BNEGI_H >+ 570449211U, // BNEGI_W >+ 33571288U, // BNEG_B >+ 33573037U, // BNEG_D >+ 33574691U, // BNEG_H >+ 33578194U, // BNEG_W >+ 33576402U, // BNEL >+ 18007U, // BNEZALC >+ 18152U, // BNEZC >+ 18152U, // BNEZC_MM >+ 33574527U, // BNE_MM >+ 33572551U, // BNVC >+ 17573U, // BNZ_B >+ 19998U, // BNZ_D >+ 21128U, // BNZ_H >+ 23425U, // BNZ_V >+ 25177U, // BNZ_W >+ 33572557U, // BOVC >+ 409767U, // BPOSGE32 >+ 0U, // BPOSGE32_PSEUDO >+ 21838U, // BREAK >+ 21838U, // BREAK_MM >+ 1646281217U, // BSELI_B >+ 0U, // BSEL_D_PSEUDO >+ 0U, // BSEL_FD_PSEUDO >+ 0U, // BSEL_FW_PSEUDO >+ 0U, // BSEL_H_PSEUDO >+ 2183158622U, // BSEL_V >+ 0U, // BSEL_W_PSEUDO >+ 570442347U, // BSETI_B >+ 570444063U, // BSETI_D >+ 570445717U, // BSETI_H >+ 570449301U, // BSETI_W >+ 33571749U, // BSET_B >+ 33573854U, // BSET_D >+ 33575252U, // BSET_H >+ 33579180U, // BSET_W >+ 17567U, // BZ_B >+ 19982U, // BZ_D >+ 21122U, // BZ_H >+ 23412U, // BZ_V >+ 25171U, // BZ_W >+ 100688549U, // BeqzRxImm16 >+ 25253U, // BeqzRxImmX16 >+ 278904U, // Bimm16 >+ 409976U, // BimmX16 >+ 100688522U, // BnezRxImm16 >+ 25226U, // BnezRxImmX16 >+ 9082U, // Break16 >+ 549555U, // Bteqz16 >+ 134239985U, // BteqzT8CmpX16 >+ 134239510U, // BteqzT8CmpiX16 >+ 134240927U, // BteqzT8SltX16 >+ 134239540U, // BteqzT8SltiX16 >+ 134241035U, // BteqzT8SltiuX16 >+ 134241071U, // BteqzT8SltuX16 >+ 418483U, // BteqzX16 >+ 549528U, // Btnez16 >+ 167794417U, // BtnezT8CmpX16 >+ 167793942U, // BtnezT8CmpiX16 >+ 167795359U, // BtnezT8SltX16 >+ 167793972U, // BtnezT8SltiX16 >+ 167795467U, // BtnezT8SltiuX16 >+ 167795503U, // BtnezT8SltuX16 >+ 418456U, // BtnezX16 >+ 0U, // BuildPairF64 >+ 0U, // BuildPairF64_64 >+ 36472U, // CACHE >+ 36472U, // CACHE_R6 >+ 18768U, // CEIL_L_D64 >+ 22751U, // CEIL_L_S >+ 19944U, // CEIL_W_D32 >+ 19944U, // CEIL_W_D64 >+ 19944U, // CEIL_W_MM >+ 23073U, // CEIL_W_S >+ 23073U, // CEIL_W_S_MM >+ 33571364U, // CEQI_B >+ 33573096U, // CEQI_D >+ 33574750U, // CEQI_H >+ 33578334U, // CEQI_W >+ 33571518U, // CEQ_B >+ 33573399U, // CEQ_D >+ 33574941U, // CEQ_H >+ 33578610U, // CEQ_W >+ 16437U, // CFC1 >+ 16437U, // CFC1_MM >+ 16738U, // CFCMSA >+ 1107321649U, // CINS >+ 1107321605U, // CINS32 >+ 19404U, // CLASS_D >+ 22925U, // CLASS_S >+ 33571603U, // CLEI_S_B >+ 33573659U, // CLEI_S_D >+ 33575075U, // CLEI_S_H >+ 33578897U, // CLEI_S_W >+ 570442730U, // CLEI_U_B >+ 570445038U, // CLEI_U_D >+ 570446275U, // CLEI_U_H >+ 570450277U, // CLEI_U_W >+ 33571585U, // CLE_S_B >+ 33573641U, // CLE_S_D >+ 33575057U, // CLE_S_H >+ 33578879U, // CLE_S_W >+ 33571800U, // CLE_U_B >+ 33574108U, // CLE_U_D >+ 33575345U, // CLE_U_H >+ 33579347U, // CLE_U_W >+ 22200U, // CLO >+ 22200U, // CLO_MM >+ 22200U, // CLO_R6 >+ 33571623U, // CLTI_S_B >+ 33573679U, // CLTI_S_D >+ 33575095U, // CLTI_S_H >+ 33578917U, // CLTI_S_W >+ 570442750U, // CLTI_U_B >+ 570445058U, // CLTI_U_D >+ 570446295U, // CLTI_U_H >+ 570450297U, // CLTI_U_W >+ 33571691U, // CLT_S_B >+ 33573757U, // CLT_S_D >+ 33575183U, // CLT_S_H >+ 33579045U, // CLT_S_W >+ 33571918U, // CLT_U_B >+ 33574236U, // CLT_U_D >+ 33575473U, // CLT_U_H >+ 33579475U, // CLT_U_W >+ 25248U, // CLZ >+ 25248U, // CLZ_MM >+ 25248U, // CLZ_R6 >+ 33572141U, // CMPGDU_EQ_QB >+ 33572046U, // CMPGDU_LE_QB >+ 33572260U, // CMPGDU_LT_QB >+ 33572155U, // CMPGU_EQ_QB >+ 33572060U, // CMPGU_LE_QB >+ 33572274U, // CMPGU_LT_QB >+ 17736U, // CMPU_EQ_QB >+ 17641U, // CMPU_LE_QB >+ 17855U, // CMPU_LT_QB >+ 33573388U, // CMP_EQ_D >+ 21313U, // CMP_EQ_PH >+ 33577288U, // CMP_EQ_S >+ 33572958U, // CMP_F_D >+ 33577099U, // CMP_F_S >+ 33572802U, // CMP_LE_D >+ 21209U, // CMP_LE_PH >+ 33577020U, // CMP_LE_S >+ 33573879U, // CMP_LT_D >+ 21482U, // CMP_LT_PH >+ 33577383U, // CMP_LT_S >+ 33572976U, // CMP_SAF_D >+ 33577109U, // CMP_SAF_S >+ 33573415U, // CMP_SEQ_D >+ 33577307U, // CMP_SEQ_S >+ 33572839U, // CMP_SLE_D >+ 33577049U, // CMP_SLE_S >+ 33573906U, // CMP_SLT_D >+ 33577402U, // CMP_SLT_S >+ 33573463U, // CMP_SUEQ_D >+ 33577338U, // CMP_SUEQ_S >+ 33572887U, // CMP_SULE_D >+ 33577080U, // CMP_SULE_S >+ 33573954U, // CMP_SULT_D >+ 33577433U, // CMP_SULT_S >+ 33573345U, // CMP_SUN_D >+ 33577261U, // CMP_SUN_S >+ 33573443U, // CMP_UEQ_D >+ 33577327U, // CMP_UEQ_S >+ 33572867U, // CMP_ULE_D >+ 33577069U, // CMP_ULE_S >+ 33573934U, // CMP_ULT_D >+ 33577422U, // CMP_ULT_S >+ 33573327U, // CMP_UN_D >+ 33577251U, // CMP_UN_S >+ 9168U, // CONSTPOOL_ENTRY >+ 0U, // COPY_FD_PSEUDO >+ 0U, // COPY_FW_PSEUDO >+ 738214802U, // COPY_S_B >+ 738216890U, // COPY_S_D >+ 738218305U, // COPY_S_H >+ 738222189U, // COPY_S_W >+ 738215017U, // COPY_U_B >+ 738217357U, // COPY_U_D >+ 738218572U, // COPY_U_H >+ 738222596U, // COPY_U_W >+ 704592U, // CTC1 >+ 704592U, // CTC1_MM >+ 16746U, // CTCMSA >+ 22553U, // CVT_D32_S >+ 23610U, // CVT_D32_W >+ 23610U, // CVT_D32_W_MM >+ 21845U, // CVT_D64_L >+ 22553U, // CVT_D64_S >+ 23610U, // CVT_D64_W >+ 22553U, // CVT_D_S_MM >+ 18789U, // CVT_L_D64 >+ 18789U, // CVT_L_D64_MM >+ 22772U, // CVT_L_S >+ 22772U, // CVT_L_S_MM >+ 19127U, // CVT_S_D32 >+ 19127U, // CVT_S_D32_MM >+ 19127U, // CVT_S_D64 >+ 21854U, // CVT_S_L >+ 24365U, // CVT_S_W >+ 24365U, // CVT_S_W_MM >+ 19965U, // CVT_W_D32 >+ 19965U, // CVT_W_D64 >+ 19965U, // CVT_W_MM >+ 23094U, // CVT_W_S >+ 23094U, // CVT_W_S_MM >+ 18948U, // C_EQ_D32 >+ 18948U, // C_EQ_D64 >+ 22848U, // C_EQ_S >+ 18519U, // C_F_D32 >+ 18519U, // C_F_D64 >+ 22660U, // C_F_S >+ 18362U, // C_LE_D32 >+ 18362U, // C_LE_D64 >+ 22580U, // C_LE_S >+ 19439U, // C_LT_D32 >+ 19439U, // C_LT_D64 >+ 22943U, // C_LT_S >+ 18353U, // C_NGE_D32 >+ 18353U, // C_NGE_D64 >+ 22571U, // C_NGE_S >+ 18388U, // C_NGLE_D32 >+ 18388U, // C_NGLE_D64 >+ 22598U, // C_NGLE_S >+ 18805U, // C_NGL_D32 >+ 18805U, // C_NGL_D64 >+ 22788U, // C_NGL_S >+ 19430U, // C_NGT_D32 >+ 19430U, // C_NGT_D64 >+ 22934U, // C_NGT_S >+ 18398U, // C_OLE_D32 >+ 18398U, // C_OLE_D64 >+ 22608U, // C_OLE_S >+ 19465U, // C_OLT_D32 >+ 19465U, // C_OLT_D64 >+ 22961U, // C_OLT_S >+ 18974U, // C_SEQ_D32 >+ 18974U, // C_SEQ_D64 >+ 22866U, // C_SEQ_S >+ 18589U, // C_SF_D32 >+ 18589U, // C_SF_D64 >+ 22706U, // C_SF_S >+ 19002U, // C_UEQ_D32 >+ 19002U, // C_UEQ_D64 >+ 22886U, // C_UEQ_S >+ 18426U, // C_ULE_D32 >+ 18426U, // C_ULE_D64 >+ 22628U, // C_ULE_S >+ 19493U, // C_ULT_D32 >+ 19493U, // C_ULT_D64 >+ 22981U, // C_ULT_S >+ 18887U, // C_UN_D32 >+ 18887U, // C_UN_D64 >+ 22811U, // C_UN_S >+ 22257U, // CmpRxRy16 >+ 234902806U, // CmpiRxImm16 >+ 21782U, // CmpiRxImmX16 >+ 418587U, // Constant32 >+ 33574460U, // DADD >+ 33576146U, // DADDi >+ 33577724U, // DADDiu >+ 33577685U, // DADDu >+ 7132401U, // DAHI >+ 33576617U, // DALIGN >+ 7132462U, // DATI >+ 33576256U, // DAUI >+ 22224U, // DBITSWAP >+ 22199U, // DCLO >+ 22199U, // DCLO_R6 >+ 25247U, // DCLZ >+ 25247U, // DCLZ_R6 >+ 33577887U, // DDIV >+ 33577795U, // DDIVU >+ 9194U, // DERET >+ 9194U, // DERET_MM >+ 1107321667U, // DEXT >+ 1107321642U, // DEXTM >+ 1107321680U, // DEXTU >+ 414933U, // DI >+ 1107321655U, // DINS >+ 1107321635U, // DINSM >+ 1107321673U, // DINSU >+ 33577888U, // DIV >+ 33577796U, // DIVU >+ 33571712U, // DIV_S_B >+ 33573800U, // DIV_S_D >+ 33575204U, // DIV_S_H >+ 33579088U, // DIV_S_W >+ 33571927U, // DIV_U_B >+ 33574267U, // DIV_U_D >+ 33575482U, // DIV_U_H >+ 33579506U, // DIV_U_W >+ 414933U, // DI_MM >+ 33571164U, // DLSA >+ 33571164U, // DLSA_R6 >+ 1107312649U, // DMFC0 >+ 16443U, // DMFC1 >+ 1107312854U, // DMFC2 >+ 33574505U, // DMOD >+ 33577699U, // DMODU >+ 1107312656U, // DMTC0 >+ 704598U, // DMTC1 >+ 1107312861U, // DMTC2 >+ 33576140U, // DMUH >+ 33577717U, // DMUHU >+ 33576565U, // DMUL >+ 23209U, // DMULT >+ 23355U, // DMULTu >+ 33577761U, // DMULU >+ 33576565U, // DMUL_R6 >+ 33573708U, // DOTP_S_D >+ 33575124U, // DOTP_S_H >+ 33578956U, // DOTP_S_W >+ 33574175U, // DOTP_U_D >+ 33575412U, // DOTP_U_H >+ 33579414U, // DOTP_U_W >+ 2183154421U, // DPADD_S_D >+ 2183155837U, // DPADD_S_H >+ 2183159659U, // DPADD_S_W >+ 2183154888U, // DPADD_U_D >+ 2183156125U, // DPADD_U_H >+ 2183160127U, // DPADD_U_W >+ 33575993U, // DPAQX_SA_W_PH >+ 33576076U, // DPAQX_S_W_PH >+ 33578416U, // DPAQ_SA_L_W >+ 33576035U, // DPAQ_S_W_PH >+ 33576321U, // DPAU_H_QBL >+ 33576779U, // DPAU_H_QBR >+ 33576114U, // DPAX_W_PH >+ 33575983U, // DPA_W_PH >+ 22262U, // DPOP >+ 33576008U, // DPSQX_SA_W_PH >+ 33576090U, // DPSQX_S_W_PH >+ 33578429U, // DPSQ_SA_L_W >+ 33576063U, // DPSQ_S_W_PH >+ 2183154388U, // DPSUB_S_D >+ 2183155816U, // DPSUB_S_H >+ 2183159626U, // DPSUB_S_W >+ 2183154855U, // DPSUB_U_D >+ 2183156104U, // DPSUB_U_H >+ 2183160094U, // DPSUB_U_W >+ 33576333U, // DPSU_H_QBL >+ 33576791U, // DPSU_H_QBR >+ 33576125U, // DPSX_W_PH >+ 33576104U, // DPS_W_PH >+ 1107318760U, // DROTR >+ 1107312833U, // DROTR32 >+ 33577931U, // DROTRV >+ 21135U, // DSBH >+ 25324U, // DSDIV >+ 20040U, // DSHD >+ 1107318343U, // DSLL >+ 1107312817U, // DSLL32 >+ 268457543U, // DSLL64_32 >+ 33577893U, // DSLLV >+ 1107312982U, // DSRA >+ 1107312799U, // DSRA32 >+ 33577872U, // DSRAV >+ 1107318355U, // DSRL >+ 1107312825U, // DSRL32 >+ 33577900U, // DSRLV >+ 33572375U, // DSUB >+ 33577664U, // DSUBu >+ 25310U, // DUDIV >+ 25325U, // DivRxRy16 >+ 25311U, // DivuRxRy16 >+ 9152U, // EHB >+ 414945U, // EI >+ 414945U, // EI_MM >+ 9195U, // ERET >+ 9195U, // ERET_MM >+ 1107321668U, // EXT >+ 1107318582U, // EXTP >+ 1107318497U, // EXTPDP >+ 33577915U, // EXTPDPV >+ 33577924U, // EXTPV >+ 33579149U, // EXTRV_RS_W >+ 33578703U, // EXTRV_R_W >+ 33575213U, // EXTRV_S_H >+ 33579586U, // EXTRV_W >+ 1107320962U, // EXTR_RS_W >+ 1107320506U, // EXTR_R_W >+ 1107316968U, // EXTR_S_H >+ 1107320605U, // EXTR_W >+ 1107321661U, // EXTS >+ 1107321613U, // EXTS32 >+ 1107321668U, // EXT_MM >+ 0U, // ExtractElementF64 >+ 0U, // ExtractElementF64_64 >+ 0U, // FABS_D >+ 19396U, // FABS_D32 >+ 19396U, // FABS_D64 >+ 19396U, // FABS_MM >+ 22918U, // FABS_S >+ 22918U, // FABS_S_MM >+ 0U, // FABS_W >+ 33572734U, // FADD_D >+ 33572735U, // FADD_D32 >+ 33572735U, // FADD_D64 >+ 33572735U, // FADD_MM >+ 33576996U, // FADD_S >+ 33576996U, // FADD_S_MM >+ 33578051U, // FADD_W >+ 33572968U, // FCAF_D >+ 33578170U, // FCAF_W >+ 33573398U, // FCEQ_D >+ 33578609U, // FCEQ_W >+ 19403U, // FCLASS_D >+ 24729U, // FCLASS_W >+ 33572812U, // FCLE_D >+ 33578093U, // FCLE_W >+ 33573889U, // FCLT_D >+ 33579188U, // FCLT_W >+ 992119U, // FCMP_D32 >+ 992119U, // FCMP_D32_MM >+ 992119U, // FCMP_D64 >+ 1123191U, // FCMP_S32 >+ 1123191U, // FCMP_S32_MM >+ 33572908U, // FCNE_D >+ 33578127U, // FCNE_W >+ 33573508U, // FCOR_D >+ 33578738U, // FCOR_W >+ 33573454U, // FCUEQ_D >+ 33578625U, // FCUEQ_W >+ 33572878U, // FCULE_D >+ 33578109U, // FCULE_W >+ 33573945U, // FCULT_D >+ 33579204U, // FCULT_W >+ 33572924U, // FCUNE_D >+ 33578143U, // FCUNE_W >+ 33573337U, // FCUN_D >+ 33578515U, // FCUN_W >+ 33574331U, // FDIV_D >+ 33574332U, // FDIV_D32 >+ 33574332U, // FDIV_D64 >+ 33574332U, // FDIV_MM >+ 33577469U, // FDIV_S >+ 33577469U, // FDIV_S_MM >+ 33579570U, // FDIV_W >+ 33574871U, // FEXDO_H >+ 33578531U, // FEXDO_W >+ 33572621U, // FEXP2_D >+ 0U, // FEXP2_D_1_PSEUDO >+ 33577954U, // FEXP2_W >+ 0U, // FEXP2_W_1_PSEUDO >+ 18829U, // FEXUPL_D >+ 24025U, // FEXUPL_W >+ 19092U, // FEXUPR_D >+ 24322U, // FEXUPR_W >+ 19334U, // FFINT_S_D >+ 24622U, // FFINT_S_W >+ 19813U, // FFINT_U_D >+ 25052U, // FFINT_U_W >+ 18839U, // FFQL_D >+ 24035U, // FFQL_W >+ 19102U, // FFQR_D >+ 24332U, // FFQR_W >+ 17047U, // FILL_B >+ 18814U, // FILL_D >+ 0U, // FILL_FD_PSEUDO >+ 0U, // FILL_FW_PSEUDO >+ 20400U, // FILL_H >+ 24010U, // FILL_W >+ 18180U, // FLOG2_D >+ 23513U, // FLOG2_W >+ 18778U, // FLOOR_L_D64 >+ 22761U, // FLOOR_L_S >+ 19954U, // FLOOR_W_D32 >+ 19954U, // FLOOR_W_D64 >+ 19954U, // FLOOR_W_MM >+ 23083U, // FLOOR_W_S >+ 23083U, // FLOOR_W_S_MM >+ 2183153542U, // FMADD_D >+ 2183158859U, // FMADD_W >+ 33572659U, // FMAX_A_D >+ 33577992U, // FMAX_A_W >+ 33574406U, // FMAX_D >+ 33579595U, // FMAX_W >+ 33572639U, // FMIN_A_D >+ 33577972U, // FMIN_A_W >+ 33573311U, // FMIN_D >+ 33578507U, // FMIN_W >+ 19915U, // FMOV_D32 >+ 19915U, // FMOV_D32_MM >+ 19915U, // FMOV_D64 >+ 23044U, // FMOV_S >+ 23044U, // FMOV_S_MM >+ 2183153500U, // FMSUB_D >+ 2183158817U, // FMSUB_W >+ 33573295U, // FMUL_D >+ 33573296U, // FMUL_D32 >+ 33573296U, // FMUL_D64 >+ 33573296U, // FMUL_MM >+ 33577229U, // FMUL_S >+ 33577229U, // FMUL_S_MM >+ 33578491U, // FMUL_W >+ 18606U, // FNEG_D32 >+ 18606U, // FNEG_D64 >+ 18606U, // FNEG_MM >+ 22722U, // FNEG_S >+ 22722U, // FNEG_S_MM >+ 18940U, // FRCP_D >+ 24108U, // FRCP_W >+ 19551U, // FRINT_D >+ 24798U, // FRINT_W >+ 19579U, // FRSQRT_D >+ 24826U, // FRSQRT_W >+ 33572987U, // FSAF_D >+ 33578178U, // FSAF_W >+ 33573426U, // FSEQ_D >+ 33578617U, // FSEQ_W >+ 33572850U, // FSLE_D >+ 33578101U, // FSLE_W >+ 33573917U, // FSLT_D >+ 33579196U, // FSLT_W >+ 33572916U, // FSNE_D >+ 33578135U, // FSNE_W >+ 33573516U, // FSOR_D >+ 33578746U, // FSOR_W >+ 19570U, // FSQRT_D >+ 19571U, // FSQRT_D32 >+ 19571U, // FSQRT_D64 >+ 19571U, // FSQRT_MM >+ 23021U, // FSQRT_S >+ 23021U, // FSQRT_S_MM >+ 24817U, // FSQRT_W >+ 33572692U, // FSUB_D >+ 33572693U, // FSUB_D32 >+ 33572693U, // FSUB_D64 >+ 33572693U, // FSUB_MM >+ 33576978U, // FSUB_S >+ 33576978U, // FSUB_S_MM >+ 33578009U, // FSUB_W >+ 33573475U, // FSUEQ_D >+ 33578634U, // FSUEQ_W >+ 33572899U, // FSULE_D >+ 33578118U, // FSULE_W >+ 33573966U, // FSULT_D >+ 33579213U, // FSULT_W >+ 33572933U, // FSUNE_D >+ 33578152U, // FSUNE_W >+ 33573356U, // FSUN_D >+ 33578523U, // FSUN_W >+ 19345U, // FTINT_S_D >+ 24633U, // FTINT_S_W >+ 19824U, // FTINT_U_D >+ 25063U, // FTINT_U_W >+ 33574948U, // FTQ_H >+ 33578643U, // FTQ_W >+ 19167U, // FTRUNC_S_D >+ 24405U, // FTRUNC_S_W >+ 19634U, // FTRUNC_U_D >+ 24873U, // FTRUNC_U_W >+ 304108813U, // GotPrologue16 >+ 33573611U, // HADD_S_D >+ 33575027U, // HADD_S_H >+ 33578849U, // HADD_S_W >+ 33574078U, // HADD_U_D >+ 33575315U, // HADD_U_H >+ 33579317U, // HADD_U_W >+ 33573578U, // HSUB_S_D >+ 33575006U, // HSUB_S_H >+ 33578816U, // HSUB_S_W >+ 33574045U, // HSUB_U_D >+ 33575294U, // HSUB_U_H >+ 33579284U, // HSUB_U_W >+ 33571982U, // ILVEV_B >+ 33574322U, // ILVEV_D >+ 33575537U, // ILVEV_H >+ 33579561U, // ILVEV_W >+ 33571510U, // ILVL_B >+ 33573303U, // ILVL_D >+ 33574863U, // ILVL_H >+ 33578499U, // ILVL_W >+ 33571262U, // ILVOD_B >+ 33572776U, // ILVOD_D >+ 33574665U, // ILVOD_H >+ 33578084U, // ILVOD_W >+ 33571558U, // ILVR_B >+ 33573551U, // ILVR_D >+ 33574988U, // ILVR_H >+ 33578789U, // ILVR_W >+ 1107321650U, // INS >+ 9585589U, // INSERT_B >+ 0U, // INSERT_B_VIDX_PSEUDO >+ 9587816U, // INSERT_D >+ 0U, // INSERT_D_VIDX_PSEUDO >+ 0U, // INSERT_FD_PSEUDO >+ 0U, // INSERT_FD_VIDX_PSEUDO >+ 0U, // INSERT_FW_PSEUDO >+ 0U, // INSERT_FW_VIDX_PSEUDO >+ 9589092U, // INSERT_H >+ 0U, // INSERT_H_VIDX_PSEUDO >+ 9593063U, // INSERT_W >+ 0U, // INSERT_W_VIDX_PSEUDO >+ 2120659U, // INSV >+ 11682247U, // INSVE_B >+ 11683918U, // INSVE_D >+ 11685650U, // INSVE_H >+ 11689137U, // INSVE_W >+ 1107321650U, // INS_MM >+ 415051U, // J >+ 415084U, // JAL >+ 22488U, // JALR >+ 415704U, // JALR16_MM >+ 22488U, // JALR64 >+ 0U, // JALR64Pseudo >+ 0U, // JALRPseudo >+ 23162U, // JALRS_MM >+ 17592U, // JALR_HB >+ 22488U, // JALR_MM >+ 416354U, // JALS_MM >+ 418413U, // JALX >+ 415084U, // JAL_MM >+ 17982U, // JIALC >+ 17971U, // JIC >+ 415700U, // JR >+ 415700U, // JR64 >+ 415531U, // JRADDIUSP >+ 410801U, // JR_HB >+ 410801U, // JR_HB_R6 >+ 415700U, // JR_MM >+ 415051U, // J_MM >+ 1332588U, // Jal16 >+ 1463660U, // JalB16 >+ 9144U, // JrRa16 >+ 9135U, // JrcRa16 >+ 418514U, // JrcRx16 >+ 409601U, // JumpLinkReg16 >+ 12600513U, // LB >+ 12600513U, // LB64 >+ 337666675U, // LBUX >+ 12600513U, // LB_MM >+ 12606139U, // LBu >+ 12606139U, // LBu64 >+ 12606139U, // LBu_MM >+ 12602959U, // LD >+ 12599337U, // LDC1 >+ 12599337U, // LDC164 >+ 12599337U, // LDC1_MM >+ 12599498U, // LDC2 >+ 12599498U, // LDC2_R6 >+ 12599548U, // LDC3 >+ 16873U, // LDI_B >+ 18622U, // LDI_D >+ 20276U, // LDI_H >+ 23860U, // LDI_W >+ 12604872U, // LDL >+ 18043U, // LDPC >+ 12605330U, // LDR >+ 337657961U, // LDXC1 >+ 337657961U, // LDXC164 >+ 12599727U, // LD_B >+ 12601241U, // LD_D >+ 12603130U, // LD_H >+ 12606549U, // LD_W >+ 4217597U, // LEA_ADDiu >+ 4217596U, // LEA_ADDiu64 >+ 4217597U, // LEA_ADDiu_MM >+ 12604064U, // LH >+ 12604064U, // LH64 >+ 337666664U, // LHX >+ 12604064U, // LH_MM >+ 12606192U, // LHu >+ 12606192U, // LHu64 >+ 12606192U, // LHu_MM >+ 12604977U, // LL >+ 12602958U, // LLD >+ 12602958U, // LLD_R6 >+ 12604977U, // LL_MM >+ 12604977U, // LL_R6 >+ 12599303U, // LOAD_ACC128 >+ 12599303U, // LOAD_ACC64 >+ 12599303U, // LOAD_ACC64DSP >+ 12605180U, // LOAD_CCOND_DSP >+ 0U, // LONG_BRANCH_ADDiu >+ 0U, // LONG_BRANCH_DADDiu >+ 0U, // LONG_BRANCH_LUi >+ 33571165U, // LSA >+ 33571165U, // LSA_R6 >+ 337657975U, // LUXC1 >+ 337657975U, // LUXC164 >+ 337657975U, // LUXC1_MM >+ 14701894U, // LUi >+ 14701894U, // LUi64 >+ 14701894U, // LUi_MM >+ 12608096U, // LW >+ 12608096U, // LW64 >+ 12599389U, // LWC1 >+ 12599389U, // LWC1_MM >+ 12599524U, // LWC2 >+ 12599524U, // LWC2_R6 >+ 12599560U, // LWC3 >+ 12605051U, // LWL >+ 12605051U, // LWL64 >+ 12605051U, // LWL_MM >+ 18080U, // LWPC >+ 12605430U, // LWR >+ 12605430U, // LWR64 >+ 12605430U, // LWR_MM >+ 18073U, // LWUPC >+ 12606282U, // LWU_MM >+ 337666681U, // LWX >+ 337657989U, // LWXC1 >+ 337657989U, // LWXC1_MM >+ 12608096U, // LW_MM >+ 12606282U, // LWu >+ 12600513U, // LbRxRyOffMemX16 >+ 12606139U, // LbuRxRyOffMemX16 >+ 12604064U, // LhRxRyOffMemX16 >+ 12606192U, // LhuRxRyOffMemX16 >+ 234902797U, // LiRxImm16 >+ 21763U, // LiRxImmAlignX16 >+ 21773U, // LiRxImmX16 >+ 14696736U, // LoadAddr32Imm >+ 12599584U, // LoadAddr32Reg >+ 14701837U, // LoadImm32Reg >+ 21777U, // LoadImm64Reg >+ 1598048U, // LwConstant32 >+ 67134048U, // LwRxPcTcp16 >+ 25184U, // LwRxPcTcpX16 >+ 12608096U, // LwRxRyOffMemX16 >+ 371221088U, // LwRxSpImmX16 >+ 20034U, // MADD >+ 2183153804U, // MADDF_D >+ 2183157929U, // MADDF_S >+ 2183155720U, // MADDR_Q_H >+ 2183159388U, // MADDR_Q_W >+ 23260U, // MADDU >+ 33577692U, // MADDU_DSP >+ 23260U, // MADDU_MM >+ 2183152764U, // MADDV_B >+ 2183155104U, // MADDV_D >+ 2183156319U, // MADDV_H >+ 2183160343U, // MADDV_W >+ 33572743U, // MADD_D32 >+ 33572743U, // MADD_D32_MM >+ 33572743U, // MADD_D64 >+ 33574466U, // MADD_DSP >+ 20034U, // MADD_MM >+ 2183155690U, // MADD_Q_H >+ 2183159358U, // MADD_Q_W >+ 33576995U, // MADD_S >+ 33576995U, // MADD_S_MM >+ 33576436U, // MAQ_SA_W_PHL >+ 33576860U, // MAQ_SA_W_PHR >+ 33576464U, // MAQ_S_W_PHL >+ 33576888U, // MAQ_S_W_PHR >+ 33572684U, // MAXA_D >+ 33576968U, // MAXA_S >+ 33571633U, // MAXI_S_B >+ 33573689U, // MAXI_S_D >+ 33575105U, // MAXI_S_H >+ 33578927U, // MAXI_S_W >+ 570442760U, // MAXI_U_B >+ 570445068U, // MAXI_U_D >+ 570446305U, // MAXI_U_H >+ 570450307U, // MAXI_U_W >+ 33571214U, // MAX_A_B >+ 33572660U, // MAX_A_D >+ 33574617U, // MAX_A_H >+ 33577993U, // MAX_A_W >+ 33574407U, // MAX_D >+ 33577535U, // MAX_S >+ 33571721U, // MAX_S_B >+ 33573809U, // MAX_S_D >+ 33575224U, // MAX_S_H >+ 33579108U, // MAX_S_W >+ 33571936U, // MAX_U_B >+ 33574276U, // MAX_U_D >+ 33575491U, // MAX_U_H >+ 33579515U, // MAX_U_W >+ 1107312650U, // MFC0 >+ 16444U, // MFC1 >+ 16444U, // MFC1_MM >+ 1107312855U, // MFC2 >+ 16450U, // MFHC1_D32 >+ 16450U, // MFHC1_D64 >+ 16450U, // MFHC1_MM >+ 414967U, // MFHI >+ 414967U, // MFHI16_MM >+ 414967U, // MFHI64 >+ 21751U, // MFHI_DSP >+ 414967U, // MFHI_MM >+ 415421U, // MFLO >+ 415421U, // MFLO16_MM >+ 415421U, // MFLO64 >+ 22205U, // MFLO_DSP >+ 415421U, // MFLO_MM >+ 33572669U, // MINA_D >+ 33576960U, // MINA_S >+ 33571613U, // MINI_S_B >+ 33573669U, // MINI_S_D >+ 33575085U, // MINI_S_H >+ 33578907U, // MINI_S_W >+ 570442740U, // MINI_U_B >+ 570445048U, // MINI_U_D >+ 570446285U, // MINI_U_H >+ 570450287U, // MINI_U_W >+ 33571195U, // MIN_A_B >+ 33572640U, // MIN_A_D >+ 33574598U, // MIN_A_H >+ 33577973U, // MIN_A_W >+ 33573312U, // MIN_D >+ 33577236U, // MIN_S >+ 33571643U, // MIN_S_B >+ 33573699U, // MIN_S_D >+ 33575115U, // MIN_S_H >+ 33578947U, // MIN_S_W >+ 33571858U, // MIN_U_B >+ 33574166U, // MIN_U_D >+ 33575403U, // MIN_U_H >+ 33579405U, // MIN_U_W >+ 0U, // MIPSeh_return32 >+ 0U, // MIPSeh_return64 >+ 33574506U, // MOD >+ 33572373U, // MODSUB >+ 33577700U, // MODU >+ 33571576U, // MOD_S_B >+ 33573632U, // MOD_S_D >+ 33575048U, // MOD_S_H >+ 33578870U, // MOD_S_W >+ 33571791U, // MOD_U_B >+ 33574099U, // MOD_U_D >+ 33575336U, // MOD_U_H >+ 33579338U, // MOD_U_W >+ 20110U, // MOVE16_MM >+ 23382U, // MOVE_V >+ 33573029U, // MOVF_D32 >+ 33573029U, // MOVF_D32_MM >+ 33573029U, // MOVF_D64 >+ 33574578U, // MOVF_I >+ 33574578U, // MOVF_I64 >+ 33574578U, // MOVF_I_MM >+ 33577146U, // MOVF_S >+ 33577146U, // MOVF_S_MM >+ 33573364U, // MOVN_I64_D64 >+ 33576625U, // MOVN_I64_I >+ 33576625U, // MOVN_I64_I64 >+ 33577272U, // MOVN_I64_S >+ 33573364U, // MOVN_I_D32 >+ 33573364U, // MOVN_I_D32_MM >+ 33573364U, // MOVN_I_D64 >+ 33576625U, // MOVN_I_I >+ 33576625U, // MOVN_I_I64 >+ 33576625U, // MOVN_I_MM >+ 33577272U, // MOVN_I_S >+ 33577272U, // MOVN_I_S_MM >+ 33574027U, // MOVT_D32 >+ 33574027U, // MOVT_D32_MM >+ 33574027U, // MOVT_D64 >+ 33577653U, // MOVT_I >+ 33577653U, // MOVT_I64 >+ 33577653U, // MOVT_I_MM >+ 33577461U, // MOVT_S >+ 33577461U, // MOVT_S_MM >+ 33574447U, // MOVZ_I64_D64 >+ 33579718U, // MOVZ_I64_I >+ 33579718U, // MOVZ_I64_I64 >+ 33577562U, // MOVZ_I64_S >+ 33574447U, // MOVZ_I_D32 >+ 33574447U, // MOVZ_I_D32_MM >+ 33574447U, // MOVZ_I_D64 >+ 33579718U, // MOVZ_I_I >+ 33579718U, // MOVZ_I_I64 >+ 33579718U, // MOVZ_I_MM >+ 33577562U, // MOVZ_I_S >+ 33577562U, // MOVZ_I_S_MM >+ 17949U, // MSUB >+ 2183153795U, // MSUBF_D >+ 2183157920U, // MSUBF_S >+ 2183155709U, // MSUBR_Q_H >+ 2183159377U, // MSUBR_Q_W >+ 23239U, // MSUBU >+ 33577671U, // MSUBU_DSP >+ 23239U, // MSUBU_MM >+ 2183152755U, // MSUBV_B >+ 2183155095U, // MSUBV_D >+ 2183156310U, // MSUBV_H >+ 2183160334U, // MSUBV_W >+ 33572701U, // MSUB_D32 >+ 33572701U, // MSUB_D32_MM >+ 33572701U, // MSUB_D64 >+ 33572381U, // MSUB_DSP >+ 17949U, // MSUB_MM >+ 2183155680U, // MSUB_Q_H >+ 2183159348U, // MSUB_Q_W >+ 33576977U, // MSUB_S >+ 33576977U, // MSUB_S_MM >+ 1107312657U, // MTC0 >+ 704599U, // MTC1 >+ 704599U, // MTC1_MM >+ 1107312862U, // MTC2 >+ 81993U, // MTHC1_D32 >+ 81993U, // MTHC1_D64 >+ 704585U, // MTHC1_MM >+ 414973U, // MTHI >+ 414973U, // MTHI64 >+ 709885U, // MTHI_DSP >+ 414973U, // MTHI_MM >+ 710377U, // MTHLIP >+ 415434U, // MTLO >+ 415434U, // MTLO64 >+ 710346U, // MTLO_DSP >+ 415434U, // MTLO_MM >+ 409629U, // MTM0 >+ 409747U, // MTM1 >+ 409840U, // MTM2 >+ 409635U, // MTP0 >+ 409753U, // MTP1 >+ 409846U, // MTP2 >+ 33576141U, // MUH >+ 33577718U, // MUHU >+ 33576566U, // MUL >+ 33576477U, // MULEQ_S_W_PHL >+ 33576901U, // MULEQ_S_W_PHR >+ 33576345U, // MULEU_S_PH_QBL >+ 33576803U, // MULEU_S_PH_QBR >+ 33575902U, // MULQ_RS_PH >+ 33579127U, // MULQ_RS_W >+ 33575846U, // MULQ_S_PH >+ 33578986U, // MULQ_S_W >+ 33574931U, // MULR_Q_H >+ 33578599U, // MULR_Q_W >+ 33576048U, // MULSAQ_S_W_PH >+ 33576023U, // MULSA_W_PH >+ 23210U, // MULT >+ 33577788U, // MULTU_DSP >+ 33577642U, // MULT_DSP >+ 23210U, // MULT_MM >+ 23356U, // MULTu >+ 23356U, // MULTu_MM >+ 33577755U, // MULU >+ 33571991U, // MULV_B >+ 33574339U, // MULV_D >+ 33575546U, // MULV_H >+ 33579578U, // MULV_W >+ 33576566U, // MUL_MM >+ 33575719U, // MUL_PH >+ 33574900U, // MUL_Q_H >+ 33578568U, // MUL_Q_W >+ 33576566U, // MUL_R6 >+ 33575814U, // MUL_S_PH >+ 414967U, // Mfhi16 >+ 415421U, // Mflo16 >+ 20110U, // Move32R16 >+ 20110U, // MoveR3216 >+ 23210U, // MultRxRy16 >+ 17619626U, // MultRxRyRz16 >+ 23356U, // MultuRxRy16 >+ 17619772U, // MultuRxRyRz16 >+ 16798U, // NLOC_B >+ 18286U, // NLOC_D >+ 20201U, // NLOC_H >+ 23594U, // NLOC_W >+ 16806U, // NLZC_B >+ 18294U, // NLZC_D >+ 20209U, // NLZC_H >+ 23602U, // NLZC_W >+ 33572751U, // NMADD_D32 >+ 33572751U, // NMADD_D32_MM >+ 33572751U, // NMADD_D64 >+ 33576994U, // NMADD_S >+ 33576994U, // NMADD_S_MM >+ 33572709U, // NMSUB_D32 >+ 33572709U, // NMSUB_D32_MM >+ 33572709U, // NMSUB_D64 >+ 33576976U, // NMSUB_S >+ 33576976U, // NMSUB_S_MM >+ 0U, // NOP >+ 33576926U, // NOR >+ 33576926U, // NOR64 >+ 570442311U, // NORI_B >+ 33576926U, // NOR_MM >+ 33577830U, // NOR_V >+ 0U, // NOR_V_D_PSEUDO >+ 0U, // NOR_V_H_PSEUDO >+ 0U, // NOR_V_W_PSEUDO >+ 20152U, // NegRxRy16 >+ 23216U, // NotRxRy16 >+ 33576927U, // OR >+ 33576927U, // OR64 >+ 570442312U, // ORI_B >+ 33576927U, // OR_MM >+ 33577831U, // OR_V >+ 0U, // OR_V_D_PSEUDO >+ 0U, // OR_V_H_PSEUDO >+ 0U, // OR_V_W_PSEUDO >+ 1107318057U, // ORi >+ 1107318057U, // ORi64 >+ 1107318057U, // ORi_MM >+ 2119647U, // OrRxRxRy16 >+ 33575708U, // PACKRL_PH >+ 9156U, // PAUSE >+ 33571973U, // PCKEV_B >+ 33574313U, // PCKEV_D >+ 33575528U, // PCKEV_H >+ 33579552U, // PCKEV_W >+ 33571253U, // PCKOD_B >+ 33572767U, // PCKOD_D >+ 33574656U, // PCKOD_H >+ 33578075U, // PCKOD_W >+ 17325U, // PCNT_B >+ 19543U, // PCNT_D >+ 20828U, // PCNT_H >+ 24790U, // PCNT_W >+ 33575672U, // PICK_PH >+ 33572105U, // PICK_QB >+ 22263U, // POP >+ 21944U, // PRECEQU_PH_QBL >+ 16676U, // PRECEQU_PH_QBLA >+ 22402U, // PRECEQU_PH_QBR >+ 16709U, // PRECEQU_PH_QBRA >+ 22018U, // PRECEQ_W_PHL >+ 22442U, // PRECEQ_W_PHR >+ 21929U, // PRECEU_PH_QBL >+ 16660U, // PRECEU_PH_QBLA >+ 22387U, // PRECEU_PH_QBR >+ 16693U, // PRECEU_PH_QBRA >+ 33575624U, // PRECRQU_S_QB_PH >+ 33578218U, // PRECRQ_PH_W >+ 33575597U, // PRECRQ_QB_PH >+ 33578249U, // PRECRQ_RS_PH_W >+ 33575611U, // PRECR_QB_PH >+ 1107320026U, // PRECR_SRA_PH_W >+ 1107320055U, // PRECR_SRA_R_PH_W >+ 36524U, // PREF >+ 36524U, // PREF_R6 >+ 1107316312U, // PREPEND >+ 0U, // PseudoCMPU_EQ_QB >+ 0U, // PseudoCMPU_LE_QB >+ 0U, // PseudoCMPU_LT_QB >+ 0U, // PseudoCMP_EQ_PH >+ 0U, // PseudoCMP_LE_PH >+ 0U, // PseudoCMP_LT_PH >+ 16391U, // PseudoCVT_D32_W >+ 16391U, // PseudoCVT_D64_L >+ 16391U, // PseudoCVT_D64_W >+ 16391U, // PseudoCVT_S_L >+ 16391U, // PseudoCVT_S_W >+ 0U, // PseudoDMULT >+ 0U, // PseudoDMULTu >+ 0U, // PseudoDSDIV >+ 0U, // PseudoDUDIV >+ 0U, // PseudoIndirectBranch >+ 0U, // PseudoIndirectBranch64 >+ 0U, // PseudoMADD >+ 0U, // PseudoMADDU >+ 0U, // PseudoMFHI >+ 0U, // PseudoMFHI64 >+ 0U, // PseudoMFLO >+ 0U, // PseudoMFLO64 >+ 0U, // PseudoMSUB >+ 0U, // PseudoMSUBU >+ 0U, // PseudoMTLOHI >+ 0U, // PseudoMTLOHI64 >+ 0U, // PseudoMTLOHI_DSP >+ 0U, // PseudoMULT >+ 0U, // PseudoMULTu >+ 0U, // PseudoPICK_PH >+ 0U, // PseudoPICK_QB >+ 0U, // PseudoReturn >+ 0U, // PseudoReturn64 >+ 0U, // PseudoSDIV >+ 0U, // PseudoUDIV >+ 17925U, // RADDU_W_QB >+ 14702365U, // RDDSP >+ 22511U, // RDHWR >+ 22511U, // RDHWR64 >+ 21531U, // REPLV_PH >+ 17905U, // REPLV_QB >+ 14701322U, // REPL_PH >+ 14697755U, // REPL_QB >+ 19552U, // RINT_D >+ 23013U, // RINT_S >+ 1107318761U, // ROTR >+ 33577932U, // ROTRV >+ 33577932U, // ROTRV_MM >+ 1107318761U, // ROTR_MM >+ 18757U, // ROUND_L_D64 >+ 22740U, // ROUND_L_S >+ 19933U, // ROUND_W_D32 >+ 19933U, // ROUND_W_D64 >+ 19933U, // ROUND_W_MM >+ 23062U, // ROUND_W_S >+ 23062U, // ROUND_W_S_MM >+ 0U, // Restore16 >+ 0U, // RestoreX16 >+ 0U, // RetRA >+ 0U, // RetRA16 >+ 1107313506U, // SAT_S_B >+ 1107315572U, // SAT_S_D >+ 570446086U, // SAT_S_H >+ 1107320860U, // SAT_S_W >+ 1107313733U, // SAT_U_B >+ 1107316051U, // SAT_U_D >+ 570446376U, // SAT_U_H >+ 1107321290U, // SAT_U_W >+ 12600849U, // SB >+ 12600849U, // SB64 >+ 12600849U, // SB_MM >+ 1754799U, // SC >+ 1756727U, // SCD >+ 1756727U, // SCD_R6 >+ 1754799U, // SC_MM >+ 1754799U, // SC_R6 >+ 12602991U, // SD >+ 415450U, // SDBBP >+ 415450U, // SDBBP_R6 >+ 12599343U, // SDC1 >+ 12599343U, // SDC164 >+ 12599343U, // SDC1_MM >+ 12599504U, // SDC2 >+ 12599504U, // SDC2_R6 >+ 12599554U, // SDC3 >+ 25325U, // SDIV >+ 25325U, // SDIV_MM >+ 12604877U, // SDL >+ 12605335U, // SDR >+ 337657968U, // SDXC1 >+ 337657968U, // SDXC164 >+ 17580U, // SEB >+ 17580U, // SEB64 >+ 17580U, // SEB_MM >+ 21147U, // SEH >+ 21147U, // SEH64 >+ 21147U, // SEH_MM >+ 33579691U, // SELEQZ >+ 33579691U, // SELEQZ64 >+ 33574437U, // SELEQZ_D >+ 33577552U, // SELEQZ_S >+ 33579664U, // SELNEZ >+ 33579664U, // SELNEZ64 >+ 33574420U, // SELNEZ_D >+ 33577542U, // SELNEZ_S >+ 2183154030U, // SEL_D >+ 2183158013U, // SEL_S >+ 33576769U, // SEQ >+ 33576220U, // SEQi >+ 12604616U, // SH >+ 12604616U, // SH64 >+ 570442193U, // SHF_B >+ 570445596U, // SHF_H >+ 570449099U, // SHF_W >+ 22211U, // SHILO >+ 23475U, // SHILOV >+ 33575953U, // SHLLV_PH >+ 33572327U, // SHLLV_QB >+ 33575890U, // SHLLV_S_PH >+ 33579097U, // SHLLV_S_W >+ 1107317505U, // SHLL_PH >+ 1107313938U, // SHLL_QB >+ 1107317627U, // SHLL_S_PH >+ 1107320761U, // SHLL_S_W >+ 33575943U, // SHRAV_PH >+ 33572317U, // SHRAV_QB >+ 33575791U, // SHRAV_R_PH >+ 33572215U, // SHRAV_R_QB >+ 33578692U, // SHRAV_R_W >+ 1107317412U, // SHRA_PH >+ 1107313861U, // SHRA_QB >+ 1107317580U, // SHRA_R_PH >+ 1107314004U, // SHRA_R_QB >+ 1107320474U, // SHRA_R_W >+ 33575973U, // SHRLV_PH >+ 33572347U, // SHRLV_QB >+ 1107317523U, // SHRL_PH >+ 1107313956U, // SHRL_QB >+ 12604616U, // SH_MM >+ 1814053352U, // SLDI_B >+ 1814055101U, // SLDI_D >+ 1814056755U, // SLDI_H >+ 1814060339U, // SLDI_W >+ 2350924206U, // SLD_B >+ 2350925720U, // SLD_D >+ 2350927609U, // SLD_H >+ 2350931028U, // SLD_W >+ 1107318344U, // SLL >+ 402675272U, // SLL64_32 >+ 402675272U, // SLL64_64 >+ 570442250U, // SLLI_B >+ 570443982U, // SLLI_D >+ 570445636U, // SLLI_H >+ 570449220U, // SLLI_W >+ 33577894U, // SLLV >+ 33577894U, // SLLV_MM >+ 33571487U, // SLL_B >+ 33573254U, // SLL_D >+ 33574840U, // SLL_H >+ 1107318344U, // SLL_MM >+ 33578450U, // SLL_W >+ 33577631U, // SLT >+ 33577631U, // SLT64 >+ 33577631U, // SLT_MM >+ 33576244U, // SLTi >+ 33576244U, // SLTi64 >+ 33576244U, // SLTi_MM >+ 33577739U, // SLTiu >+ 33577739U, // SLTiu64 >+ 33577739U, // SLTiu_MM >+ 33577775U, // SLTu >+ 33577775U, // SLTu64 >+ 33577775U, // SLTu_MM >+ 33574532U, // SNE >+ 33576165U, // SNEi >+ 0U, // SNZ_B_PSEUDO >+ 0U, // SNZ_D_PSEUDO >+ 0U, // SNZ_H_PSEUDO >+ 0U, // SNZ_V_PSEUDO >+ 0U, // SNZ_W_PSEUDO >+ 738214497U, // SPLATI_B >+ 738216213U, // SPLATI_D >+ 738217867U, // SPLATI_H >+ 738221451U, // SPLATI_W >+ 201343900U, // SPLAT_B >+ 201346005U, // SPLAT_D >+ 201347403U, // SPLAT_H >+ 201351331U, // SPLAT_W >+ 1107312983U, // SRA >+ 570442208U, // SRAI_B >+ 570443957U, // SRAI_D >+ 570445611U, // SRAI_H >+ 570449195U, // SRAI_W >+ 1107313196U, // SRARI_B >+ 1107314928U, // SRARI_D >+ 570445670U, // SRARI_H >+ 1107320166U, // SRARI_W >+ 33571525U, // SRAR_B >+ 33573484U, // SRAR_D >+ 33574955U, // SRAR_H >+ 33578714U, // SRAR_W >+ 33577873U, // SRAV >+ 33577873U, // SRAV_MM >+ 33571223U, // SRA_B >+ 33572677U, // SRA_D >+ 33574626U, // SRA_H >+ 1107312983U, // SRA_MM >+ 33578002U, // SRA_W >+ 1107318356U, // SRL >+ 570442258U, // SRLI_B >+ 570443990U, // SRLI_D >+ 570445644U, // SRLI_H >+ 570449228U, // SRLI_W >+ 1107313214U, // SRLRI_B >+ 1107314946U, // SRLRI_D >+ 570445688U, // SRLRI_H >+ 1107320184U, // SRLRI_W >+ 33571541U, // SRLR_B >+ 33573500U, // SRLR_D >+ 33574971U, // SRLR_H >+ 33578730U, // SRLR_W >+ 33577901U, // SRLV >+ 33577901U, // SRLV_MM >+ 33571494U, // SRL_B >+ 33573279U, // SRL_D >+ 33574847U, // SRL_H >+ 1107318356U, // SRL_MM >+ 33578475U, // SRL_W >+ 9177U, // SSNOP >+ 12599303U, // STORE_ACC128 >+ 12599303U, // STORE_ACC64 >+ 12599303U, // STORE_ACC64DSP >+ 12605196U, // STORE_CCOND_DSP >+ 12600255U, // ST_B >+ 12602501U, // ST_D >+ 12603758U, // ST_H >+ 12607748U, // ST_W >+ 33572376U, // SUB >+ 33575652U, // SUBQH_PH >+ 33575767U, // SUBQH_R_PH >+ 33578660U, // SUBQH_R_W >+ 33578265U, // SUBQH_W >+ 33575727U, // SUBQ_PH >+ 33575824U, // SUBQ_S_PH >+ 33578966U, // SUBQ_S_W >+ 33571897U, // SUBSUS_U_B >+ 33574215U, // SUBSUS_U_D >+ 33575452U, // SUBSUS_U_H >+ 33579454U, // SUBSUS_U_W >+ 33571700U, // SUBSUU_S_B >+ 33573788U, // SUBSUU_S_D >+ 33575192U, // SUBSUU_S_H >+ 33579076U, // SUBSUU_S_W >+ 33571662U, // SUBS_S_B >+ 33573728U, // SUBS_S_D >+ 33575154U, // SUBS_S_H >+ 33579016U, // SUBS_S_W >+ 33571877U, // SUBS_U_B >+ 33574195U, // SUBS_U_D >+ 33575432U, // SUBS_U_H >+ 33579434U, // SUBS_U_W >+ 33572085U, // SUBUH_QB >+ 33572191U, // SUBUH_R_QB >+ 33575925U, // SUBU_PH >+ 33572299U, // SUBU_QB >+ 33575868U, // SUBU_S_PH >+ 33572238U, // SUBU_S_QB >+ 570442356U, // SUBVI_B >+ 570444072U, // SUBVI_D >+ 570445726U, // SUBVI_H >+ 570449310U, // SUBVI_W >+ 33571956U, // SUBV_B >+ 33574296U, // SUBV_D >+ 33575511U, // SUBV_H >+ 33579535U, // SUBV_W >+ 33572376U, // SUB_MM >+ 33577665U, // SUBu >+ 33577665U, // SUBu_MM >+ 337657982U, // SUXC1 >+ 337657982U, // SUXC164 >+ 337657982U, // SUXC1_MM >+ 12608100U, // SW >+ 12608100U, // SW64 >+ 12599395U, // SWC1 >+ 12599395U, // SWC1_MM >+ 12599530U, // SWC2 >+ 12599530U, // SWC2_R6 >+ 12599566U, // SWC3 >+ 12605056U, // SWL >+ 12605056U, // SWL64 >+ 12605056U, // SWL_MM >+ 12605435U, // SWR >+ 12605435U, // SWR64 >+ 12605435U, // SWR_MM >+ 337657996U, // SWXC1 >+ 337657996U, // SWXC1_MM >+ 12608100U, // SW_MM >+ 418581U, // SYNC >+ 418581U, // SYNC_MM >+ 415276U, // SYSCALL >+ 415276U, // SYSCALL_MM >+ 0U, // SZ_B_PSEUDO >+ 0U, // SZ_D_PSEUDO >+ 0U, // SZ_H_PSEUDO >+ 0U, // SZ_V_PSEUDO >+ 0U, // SZ_W_PSEUDO >+ 0U, // Save16 >+ 0U, // SaveX16 >+ 12600849U, // SbRxRyOffMemX16 >+ 418508U, // SebRx16 >+ 418520U, // SehRx16 >+ 1942181U, // SelBeqZ >+ 1942154U, // SelBneZ >+ 455186161U, // SelTBteqZCmp >+ 455185686U, // SelTBteqZCmpi >+ 455187103U, // SelTBteqZSlt >+ 455185716U, // SelTBteqZSlti >+ 455187211U, // SelTBteqZSltiu >+ 455187247U, // SelTBteqZSltu >+ 488740593U, // SelTBtneZCmp >+ 488740118U, // SelTBtneZCmpi >+ 488741535U, // SelTBtneZSlt >+ 488740148U, // SelTBtneZSlti >+ 488741643U, // SelTBtneZSltiu >+ 488741679U, // SelTBtneZSltu >+ 12604616U, // ShRxRyOffMemX16 >+ 1107318344U, // SllX16 >+ 2120614U, // SllvRxRy16 >+ 21813919U, // SltCCRxRy16 >+ 23199U, // SltRxRy16 >+ 21812532U, // SltiCCRxImmX16 >+ 234902836U, // SltiRxImm16 >+ 21812U, // SltiRxImmX16 >+ 21814027U, // SltiuCCRxImmX16 >+ 234904331U, // SltiuRxImm16 >+ 23307U, // SltiuRxImmX16 >+ 21814063U, // SltuCCRxRy16 >+ 23343U, // SltuRxRy16 >+ 21814063U, // SltuRxRyRz16 >+ 1107312983U, // SraX16 >+ 2120593U, // SravRxRy16 >+ 1107318356U, // SrlX16 >+ 2120621U, // SrlvRxRy16 >+ 33577665U, // SubuRxRyRz16 >+ 12608100U, // SwRxRyOffMemX16 >+ 371221092U, // SwRxSpImmX16 >+ 0U, // TAILCALL >+ 0U, // TAILCALL64_R >+ 0U, // TAILCALL_R >+ 1107318598U, // TEQ >+ 14701858U, // TEQI >+ 14701858U, // TEQI_MM >+ 1107318598U, // TEQ_MM >+ 1107316339U, // TGE >+ 14701791U, // TGEI >+ 14703364U, // TGEIU >+ 14703364U, // TGEIU_MM >+ 14701791U, // TGEI_MM >+ 1107319530U, // TGEU >+ 1107319530U, // TGEU_MM >+ 1107316339U, // TGE_MM >+ 9172U, // TLBP >+ 9172U, // TLBP_MM >+ 9183U, // TLBR >+ 9183U, // TLBR_MM >+ 9162U, // TLBWI >+ 9162U, // TLBWI_MM >+ 9188U, // TLBWR >+ 9188U, // TLBWR_MM >+ 1107319460U, // TLT >+ 14701882U, // TLTI >+ 14703378U, // TLTIU_MM >+ 14701882U, // TLTI_MM >+ 1107319605U, // TLTU >+ 1107319605U, // TLTU_MM >+ 1107319460U, // TLT_MM >+ 1107316361U, // TNE >+ 14701803U, // TNEI >+ 14701803U, // TNEI_MM >+ 1107316361U, // TNE_MM >+ 0U, // TRAP >+ 18746U, // TRUNC_L_D64 >+ 22729U, // TRUNC_L_S >+ 19922U, // TRUNC_W_D32 >+ 19922U, // TRUNC_W_D64 >+ 19922U, // TRUNC_W_MM >+ 23051U, // TRUNC_W_S >+ 23051U, // TRUNC_W_S_MM >+ 14703378U, // TTLTIU >+ 25311U, // UDIV >+ 25311U, // UDIV_MM >+ 33577753U, // V3MULU >+ 33570839U, // VMM0 >+ 33577768U, // VMULU >+ 2183152080U, // VSHF_B >+ 2183153813U, // VSHF_D >+ 2183155483U, // VSHF_H >+ 2183158986U, // VSHF_W >+ 9200U, // WAIT >+ 416409U, // WAIT_MM >+ 14702372U, // WRDSP >+ 21141U, // WSBH >+ 21141U, // WSBH_MM >+ 33576931U, // XOR >+ 33576931U, // XOR64 >+ 570442319U, // XORI_B >+ 33576931U, // XOR_MM >+ 33577837U, // XOR_V >+ 0U, // XOR_V_D_PSEUDO >+ 0U, // XOR_V_H_PSEUDO >+ 0U, // XOR_V_W_PSEUDO >+ 1107318056U, // XORi >+ 1107318056U, // XORi64 >+ 1107318056U, // XORi_MM >+ 2119651U, // XorRxRxRy16 >+ 0U >+ }; >+ >+ static const uint8_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // ABSQ_S_PH >+ 0U, // ABSQ_S_QB >+ 0U, // ABSQ_S_W >+ 0U, // ADD >+ 0U, // ADDIUPC >+ 0U, // ADDQH_PH >+ 0U, // ADDQH_R_PH >+ 0U, // ADDQH_R_W >+ 0U, // ADDQH_W >+ 0U, // ADDQ_PH >+ 0U, // ADDQ_S_PH >+ 0U, // ADDQ_S_W >+ 0U, // ADDSC >+ 0U, // ADDS_A_B >+ 0U, // ADDS_A_D >+ 0U, // ADDS_A_H >+ 0U, // ADDS_A_W >+ 0U, // ADDS_S_B >+ 0U, // ADDS_S_D >+ 0U, // ADDS_S_H >+ 0U, // ADDS_S_W >+ 0U, // ADDS_U_B >+ 0U, // ADDS_U_D >+ 0U, // ADDS_U_H >+ 0U, // ADDS_U_W >+ 0U, // ADDUH_QB >+ 0U, // ADDUH_R_QB >+ 0U, // ADDU_PH >+ 0U, // ADDU_QB >+ 0U, // ADDU_S_PH >+ 0U, // ADDU_S_QB >+ 0U, // ADDVI_B >+ 0U, // ADDVI_D >+ 0U, // ADDVI_H >+ 0U, // ADDVI_W >+ 0U, // ADDV_B >+ 0U, // ADDV_D >+ 0U, // ADDV_H >+ 0U, // ADDV_W >+ 0U, // ADDWC >+ 0U, // ADD_A_B >+ 0U, // ADD_A_D >+ 0U, // ADD_A_H >+ 0U, // ADD_A_W >+ 0U, // ADD_MM >+ 0U, // ADDi >+ 0U, // ADDi_MM >+ 0U, // ADDiu >+ 0U, // ADDiu_MM >+ 0U, // ADDu >+ 0U, // ADDu_MM >+ 0U, // ADJCALLSTACKDOWN >+ 0U, // ADJCALLSTACKUP >+ 1U, // ALIGN >+ 0U, // ALUIPC >+ 0U, // AND >+ 0U, // AND64 >+ 0U, // ANDI_B >+ 0U, // AND_MM >+ 0U, // AND_V >+ 0U, // AND_V_D_PSEUDO >+ 0U, // AND_V_H_PSEUDO >+ 0U, // AND_V_W_PSEUDO >+ 0U, // ANDi >+ 0U, // ANDi64 >+ 0U, // ANDi_MM >+ 0U, // APPEND >+ 0U, // ASUB_S_B >+ 0U, // ASUB_S_D >+ 0U, // ASUB_S_H >+ 0U, // ASUB_S_W >+ 0U, // ASUB_U_B >+ 0U, // ASUB_U_D >+ 0U, // ASUB_U_H >+ 0U, // ASUB_U_W >+ 0U, // ATOMIC_CMP_SWAP_I16 >+ 0U, // ATOMIC_CMP_SWAP_I32 >+ 0U, // ATOMIC_CMP_SWAP_I64 >+ 0U, // ATOMIC_CMP_SWAP_I8 >+ 0U, // ATOMIC_LOAD_ADD_I16 >+ 0U, // ATOMIC_LOAD_ADD_I32 >+ 0U, // ATOMIC_LOAD_ADD_I64 >+ 0U, // ATOMIC_LOAD_ADD_I8 >+ 0U, // ATOMIC_LOAD_AND_I16 >+ 0U, // ATOMIC_LOAD_AND_I32 >+ 0U, // ATOMIC_LOAD_AND_I64 >+ 0U, // ATOMIC_LOAD_AND_I8 >+ 0U, // ATOMIC_LOAD_NAND_I16 >+ 0U, // ATOMIC_LOAD_NAND_I32 >+ 0U, // ATOMIC_LOAD_NAND_I64 >+ 0U, // ATOMIC_LOAD_NAND_I8 >+ 0U, // ATOMIC_LOAD_OR_I16 >+ 0U, // ATOMIC_LOAD_OR_I32 >+ 0U, // ATOMIC_LOAD_OR_I64 >+ 0U, // ATOMIC_LOAD_OR_I8 >+ 0U, // ATOMIC_LOAD_SUB_I16 >+ 0U, // ATOMIC_LOAD_SUB_I32 >+ 0U, // ATOMIC_LOAD_SUB_I64 >+ 0U, // ATOMIC_LOAD_SUB_I8 >+ 0U, // ATOMIC_LOAD_XOR_I16 >+ 0U, // ATOMIC_LOAD_XOR_I32 >+ 0U, // ATOMIC_LOAD_XOR_I64 >+ 0U, // ATOMIC_LOAD_XOR_I8 >+ 0U, // ATOMIC_SWAP_I16 >+ 0U, // ATOMIC_SWAP_I32 >+ 0U, // ATOMIC_SWAP_I64 >+ 0U, // ATOMIC_SWAP_I8 >+ 0U, // AUI >+ 0U, // AUIPC >+ 0U, // AVER_S_B >+ 0U, // AVER_S_D >+ 0U, // AVER_S_H >+ 0U, // AVER_S_W >+ 0U, // AVER_U_B >+ 0U, // AVER_U_D >+ 0U, // AVER_U_H >+ 0U, // AVER_U_W >+ 0U, // AVE_S_B >+ 0U, // AVE_S_D >+ 0U, // AVE_S_H >+ 0U, // AVE_S_W >+ 0U, // AVE_U_B >+ 0U, // AVE_U_D >+ 0U, // AVE_U_H >+ 0U, // AVE_U_W >+ 0U, // AddiuRxImmX16 >+ 0U, // AddiuRxPcImmX16 >+ 0U, // AddiuRxRxImm16 >+ 0U, // AddiuRxRxImmX16 >+ 0U, // AddiuRxRyOffMemX16 >+ 0U, // AddiuSpImm16 >+ 0U, // AddiuSpImmX16 >+ 0U, // AdduRxRyRz16 >+ 0U, // AndRxRxRy16 >+ 0U, // B >+ 0U, // BADDu >+ 0U, // BAL >+ 0U, // BALC >+ 0U, // BALIGN >+ 0U, // BAL_BR >+ 0U, // BC >+ 0U, // BC0F >+ 0U, // BC0FL >+ 0U, // BC0T >+ 0U, // BC0TL >+ 0U, // BC1EQZ >+ 0U, // BC1F >+ 0U, // BC1FL >+ 0U, // BC1F_MM >+ 0U, // BC1NEZ >+ 0U, // BC1T >+ 0U, // BC1TL >+ 0U, // BC1T_MM >+ 0U, // BC2EQZ >+ 0U, // BC2F >+ 0U, // BC2FL >+ 0U, // BC2NEZ >+ 0U, // BC2T >+ 0U, // BC2TL >+ 0U, // BC3F >+ 0U, // BC3FL >+ 0U, // BC3T >+ 0U, // BC3TL >+ 0U, // BCLRI_B >+ 0U, // BCLRI_D >+ 0U, // BCLRI_H >+ 0U, // BCLRI_W >+ 0U, // BCLR_B >+ 0U, // BCLR_D >+ 0U, // BCLR_H >+ 0U, // BCLR_W >+ 0U, // BEQ >+ 0U, // BEQ64 >+ 0U, // BEQC >+ 0U, // BEQL >+ 0U, // BEQZALC >+ 0U, // BEQZC >+ 0U, // BEQZC_MM >+ 0U, // BEQ_MM >+ 0U, // BGEC >+ 0U, // BGEUC >+ 0U, // BGEZ >+ 0U, // BGEZ64 >+ 0U, // BGEZAL >+ 0U, // BGEZALC >+ 0U, // BGEZALL >+ 0U, // BGEZALS_MM >+ 0U, // BGEZAL_MM >+ 0U, // BGEZC >+ 0U, // BGEZL >+ 0U, // BGEZ_MM >+ 0U, // BGTZ >+ 0U, // BGTZ64 >+ 0U, // BGTZALC >+ 0U, // BGTZC >+ 0U, // BGTZL >+ 0U, // BGTZ_MM >+ 0U, // BINSLI_B >+ 0U, // BINSLI_D >+ 0U, // BINSLI_H >+ 0U, // BINSLI_W >+ 0U, // BINSL_B >+ 0U, // BINSL_D >+ 0U, // BINSL_H >+ 0U, // BINSL_W >+ 0U, // BINSRI_B >+ 0U, // BINSRI_D >+ 0U, // BINSRI_H >+ 0U, // BINSRI_W >+ 0U, // BINSR_B >+ 0U, // BINSR_D >+ 0U, // BINSR_H >+ 0U, // BINSR_W >+ 0U, // BITREV >+ 0U, // BITSWAP >+ 0U, // BLEZ >+ 0U, // BLEZ64 >+ 0U, // BLEZALC >+ 0U, // BLEZC >+ 0U, // BLEZL >+ 0U, // BLEZ_MM >+ 0U, // BLTC >+ 0U, // BLTUC >+ 0U, // BLTZ >+ 0U, // BLTZ64 >+ 0U, // BLTZAL >+ 0U, // BLTZALC >+ 0U, // BLTZALL >+ 0U, // BLTZALS_MM >+ 0U, // BLTZAL_MM >+ 0U, // BLTZC >+ 0U, // BLTZL >+ 0U, // BLTZ_MM >+ 0U, // BMNZI_B >+ 0U, // BMNZ_V >+ 0U, // BMZI_B >+ 0U, // BMZ_V >+ 0U, // BNE >+ 0U, // BNE64 >+ 0U, // BNEC >+ 0U, // BNEGI_B >+ 0U, // BNEGI_D >+ 0U, // BNEGI_H >+ 0U, // BNEGI_W >+ 0U, // BNEG_B >+ 0U, // BNEG_D >+ 0U, // BNEG_H >+ 0U, // BNEG_W >+ 0U, // BNEL >+ 0U, // BNEZALC >+ 0U, // BNEZC >+ 0U, // BNEZC_MM >+ 0U, // BNE_MM >+ 0U, // BNVC >+ 0U, // BNZ_B >+ 0U, // BNZ_D >+ 0U, // BNZ_H >+ 0U, // BNZ_V >+ 0U, // BNZ_W >+ 0U, // BOVC >+ 0U, // BPOSGE32 >+ 0U, // BPOSGE32_PSEUDO >+ 0U, // BREAK >+ 0U, // BREAK_MM >+ 0U, // BSELI_B >+ 0U, // BSEL_D_PSEUDO >+ 0U, // BSEL_FD_PSEUDO >+ 0U, // BSEL_FW_PSEUDO >+ 0U, // BSEL_H_PSEUDO >+ 0U, // BSEL_V >+ 0U, // BSEL_W_PSEUDO >+ 0U, // BSETI_B >+ 0U, // BSETI_D >+ 0U, // BSETI_H >+ 0U, // BSETI_W >+ 0U, // BSET_B >+ 0U, // BSET_D >+ 0U, // BSET_H >+ 0U, // BSET_W >+ 0U, // BZ_B >+ 0U, // BZ_D >+ 0U, // BZ_H >+ 0U, // BZ_V >+ 0U, // BZ_W >+ 0U, // BeqzRxImm16 >+ 0U, // BeqzRxImmX16 >+ 0U, // Bimm16 >+ 0U, // BimmX16 >+ 0U, // BnezRxImm16 >+ 0U, // BnezRxImmX16 >+ 0U, // Break16 >+ 0U, // Bteqz16 >+ 0U, // BteqzT8CmpX16 >+ 0U, // BteqzT8CmpiX16 >+ 0U, // BteqzT8SltX16 >+ 0U, // BteqzT8SltiX16 >+ 0U, // BteqzT8SltiuX16 >+ 0U, // BteqzT8SltuX16 >+ 0U, // BteqzX16 >+ 0U, // Btnez16 >+ 0U, // BtnezT8CmpX16 >+ 0U, // BtnezT8CmpiX16 >+ 0U, // BtnezT8SltX16 >+ 0U, // BtnezT8SltiX16 >+ 0U, // BtnezT8SltiuX16 >+ 0U, // BtnezT8SltuX16 >+ 0U, // BtnezX16 >+ 0U, // BuildPairF64 >+ 0U, // BuildPairF64_64 >+ 0U, // CACHE >+ 0U, // CACHE_R6 >+ 0U, // CEIL_L_D64 >+ 0U, // CEIL_L_S >+ 0U, // CEIL_W_D32 >+ 0U, // CEIL_W_D64 >+ 0U, // CEIL_W_MM >+ 0U, // CEIL_W_S >+ 0U, // CEIL_W_S_MM >+ 0U, // CEQI_B >+ 0U, // CEQI_D >+ 0U, // CEQI_H >+ 0U, // CEQI_W >+ 0U, // CEQ_B >+ 0U, // CEQ_D >+ 0U, // CEQ_H >+ 0U, // CEQ_W >+ 0U, // CFC1 >+ 0U, // CFC1_MM >+ 0U, // CFCMSA >+ 1U, // CINS >+ 1U, // CINS32 >+ 0U, // CLASS_D >+ 0U, // CLASS_S >+ 0U, // CLEI_S_B >+ 0U, // CLEI_S_D >+ 0U, // CLEI_S_H >+ 0U, // CLEI_S_W >+ 0U, // CLEI_U_B >+ 0U, // CLEI_U_D >+ 0U, // CLEI_U_H >+ 0U, // CLEI_U_W >+ 0U, // CLE_S_B >+ 0U, // CLE_S_D >+ 0U, // CLE_S_H >+ 0U, // CLE_S_W >+ 0U, // CLE_U_B >+ 0U, // CLE_U_D >+ 0U, // CLE_U_H >+ 0U, // CLE_U_W >+ 0U, // CLO >+ 0U, // CLO_MM >+ 0U, // CLO_R6 >+ 0U, // CLTI_S_B >+ 0U, // CLTI_S_D >+ 0U, // CLTI_S_H >+ 0U, // CLTI_S_W >+ 0U, // CLTI_U_B >+ 0U, // CLTI_U_D >+ 0U, // CLTI_U_H >+ 0U, // CLTI_U_W >+ 0U, // CLT_S_B >+ 0U, // CLT_S_D >+ 0U, // CLT_S_H >+ 0U, // CLT_S_W >+ 0U, // CLT_U_B >+ 0U, // CLT_U_D >+ 0U, // CLT_U_H >+ 0U, // CLT_U_W >+ 0U, // CLZ >+ 0U, // CLZ_MM >+ 0U, // CLZ_R6 >+ 0U, // CMPGDU_EQ_QB >+ 0U, // CMPGDU_LE_QB >+ 0U, // CMPGDU_LT_QB >+ 0U, // CMPGU_EQ_QB >+ 0U, // CMPGU_LE_QB >+ 0U, // CMPGU_LT_QB >+ 0U, // CMPU_EQ_QB >+ 0U, // CMPU_LE_QB >+ 0U, // CMPU_LT_QB >+ 0U, // CMP_EQ_D >+ 0U, // CMP_EQ_PH >+ 0U, // CMP_EQ_S >+ 0U, // CMP_F_D >+ 0U, // CMP_F_S >+ 0U, // CMP_LE_D >+ 0U, // CMP_LE_PH >+ 0U, // CMP_LE_S >+ 0U, // CMP_LT_D >+ 0U, // CMP_LT_PH >+ 0U, // CMP_LT_S >+ 0U, // CMP_SAF_D >+ 0U, // CMP_SAF_S >+ 0U, // CMP_SEQ_D >+ 0U, // CMP_SEQ_S >+ 0U, // CMP_SLE_D >+ 0U, // CMP_SLE_S >+ 0U, // CMP_SLT_D >+ 0U, // CMP_SLT_S >+ 0U, // CMP_SUEQ_D >+ 0U, // CMP_SUEQ_S >+ 0U, // CMP_SULE_D >+ 0U, // CMP_SULE_S >+ 0U, // CMP_SULT_D >+ 0U, // CMP_SULT_S >+ 0U, // CMP_SUN_D >+ 0U, // CMP_SUN_S >+ 0U, // CMP_UEQ_D >+ 0U, // CMP_UEQ_S >+ 0U, // CMP_ULE_D >+ 0U, // CMP_ULE_S >+ 0U, // CMP_ULT_D >+ 0U, // CMP_ULT_S >+ 0U, // CMP_UN_D >+ 0U, // CMP_UN_S >+ 0U, // CONSTPOOL_ENTRY >+ 0U, // COPY_FD_PSEUDO >+ 0U, // COPY_FW_PSEUDO >+ 2U, // COPY_S_B >+ 2U, // COPY_S_D >+ 2U, // COPY_S_H >+ 2U, // COPY_S_W >+ 2U, // COPY_U_B >+ 2U, // COPY_U_D >+ 2U, // COPY_U_H >+ 2U, // COPY_U_W >+ 0U, // CTC1 >+ 0U, // CTC1_MM >+ 0U, // CTCMSA >+ 0U, // CVT_D32_S >+ 0U, // CVT_D32_W >+ 0U, // CVT_D32_W_MM >+ 0U, // CVT_D64_L >+ 0U, // CVT_D64_S >+ 0U, // CVT_D64_W >+ 0U, // CVT_D_S_MM >+ 0U, // CVT_L_D64 >+ 0U, // CVT_L_D64_MM >+ 0U, // CVT_L_S >+ 0U, // CVT_L_S_MM >+ 0U, // CVT_S_D32 >+ 0U, // CVT_S_D32_MM >+ 0U, // CVT_S_D64 >+ 0U, // CVT_S_L >+ 0U, // CVT_S_W >+ 0U, // CVT_S_W_MM >+ 0U, // CVT_W_D32 >+ 0U, // CVT_W_D64 >+ 0U, // CVT_W_MM >+ 0U, // CVT_W_S >+ 0U, // CVT_W_S_MM >+ 0U, // C_EQ_D32 >+ 0U, // C_EQ_D64 >+ 0U, // C_EQ_S >+ 0U, // C_F_D32 >+ 0U, // C_F_D64 >+ 0U, // C_F_S >+ 0U, // C_LE_D32 >+ 0U, // C_LE_D64 >+ 0U, // C_LE_S >+ 0U, // C_LT_D32 >+ 0U, // C_LT_D64 >+ 0U, // C_LT_S >+ 0U, // C_NGE_D32 >+ 0U, // C_NGE_D64 >+ 0U, // C_NGE_S >+ 0U, // C_NGLE_D32 >+ 0U, // C_NGLE_D64 >+ 0U, // C_NGLE_S >+ 0U, // C_NGL_D32 >+ 0U, // C_NGL_D64 >+ 0U, // C_NGL_S >+ 0U, // C_NGT_D32 >+ 0U, // C_NGT_D64 >+ 0U, // C_NGT_S >+ 0U, // C_OLE_D32 >+ 0U, // C_OLE_D64 >+ 0U, // C_OLE_S >+ 0U, // C_OLT_D32 >+ 0U, // C_OLT_D64 >+ 0U, // C_OLT_S >+ 0U, // C_SEQ_D32 >+ 0U, // C_SEQ_D64 >+ 0U, // C_SEQ_S >+ 0U, // C_SF_D32 >+ 0U, // C_SF_D64 >+ 0U, // C_SF_S >+ 0U, // C_UEQ_D32 >+ 0U, // C_UEQ_D64 >+ 0U, // C_UEQ_S >+ 0U, // C_ULE_D32 >+ 0U, // C_ULE_D64 >+ 0U, // C_ULE_S >+ 0U, // C_ULT_D32 >+ 0U, // C_ULT_D64 >+ 0U, // C_ULT_S >+ 0U, // C_UN_D32 >+ 0U, // C_UN_D64 >+ 0U, // C_UN_S >+ 0U, // CmpRxRy16 >+ 0U, // CmpiRxImm16 >+ 0U, // CmpiRxImmX16 >+ 0U, // Constant32 >+ 0U, // DADD >+ 0U, // DADDi >+ 0U, // DADDiu >+ 0U, // DADDu >+ 0U, // DAHI >+ 1U, // DALIGN >+ 0U, // DATI >+ 0U, // DAUI >+ 0U, // DBITSWAP >+ 0U, // DCLO >+ 0U, // DCLO_R6 >+ 0U, // DCLZ >+ 0U, // DCLZ_R6 >+ 0U, // DDIV >+ 0U, // DDIVU >+ 0U, // DERET >+ 0U, // DERET_MM >+ 5U, // DEXT >+ 5U, // DEXTM >+ 5U, // DEXTU >+ 0U, // DI >+ 5U, // DINS >+ 5U, // DINSM >+ 5U, // DINSU >+ 0U, // DIV >+ 0U, // DIVU >+ 0U, // DIV_S_B >+ 0U, // DIV_S_D >+ 0U, // DIV_S_H >+ 0U, // DIV_S_W >+ 0U, // DIV_U_B >+ 0U, // DIV_U_D >+ 0U, // DIV_U_H >+ 0U, // DIV_U_W >+ 0U, // DI_MM >+ 1U, // DLSA >+ 1U, // DLSA_R6 >+ 0U, // DMFC0 >+ 0U, // DMFC1 >+ 0U, // DMFC2 >+ 0U, // DMOD >+ 0U, // DMODU >+ 0U, // DMTC0 >+ 0U, // DMTC1 >+ 0U, // DMTC2 >+ 0U, // DMUH >+ 0U, // DMUHU >+ 0U, // DMUL >+ 0U, // DMULT >+ 0U, // DMULTu >+ 0U, // DMULU >+ 0U, // DMUL_R6 >+ 0U, // DOTP_S_D >+ 0U, // DOTP_S_H >+ 0U, // DOTP_S_W >+ 0U, // DOTP_U_D >+ 0U, // DOTP_U_H >+ 0U, // DOTP_U_W >+ 0U, // DPADD_S_D >+ 0U, // DPADD_S_H >+ 0U, // DPADD_S_W >+ 0U, // DPADD_U_D >+ 0U, // DPADD_U_H >+ 0U, // DPADD_U_W >+ 0U, // DPAQX_SA_W_PH >+ 0U, // DPAQX_S_W_PH >+ 0U, // DPAQ_SA_L_W >+ 0U, // DPAQ_S_W_PH >+ 0U, // DPAU_H_QBL >+ 0U, // DPAU_H_QBR >+ 0U, // DPAX_W_PH >+ 0U, // DPA_W_PH >+ 0U, // DPOP >+ 0U, // DPSQX_SA_W_PH >+ 0U, // DPSQX_S_W_PH >+ 0U, // DPSQ_SA_L_W >+ 0U, // DPSQ_S_W_PH >+ 0U, // DPSUB_S_D >+ 0U, // DPSUB_S_H >+ 0U, // DPSUB_S_W >+ 0U, // DPSUB_U_D >+ 0U, // DPSUB_U_H >+ 0U, // DPSUB_U_W >+ 0U, // DPSU_H_QBL >+ 0U, // DPSU_H_QBR >+ 0U, // DPSX_W_PH >+ 0U, // DPS_W_PH >+ 0U, // DROTR >+ 0U, // DROTR32 >+ 0U, // DROTRV >+ 0U, // DSBH >+ 0U, // DSDIV >+ 0U, // DSHD >+ 0U, // DSLL >+ 0U, // DSLL32 >+ 0U, // DSLL64_32 >+ 0U, // DSLLV >+ 0U, // DSRA >+ 0U, // DSRA32 >+ 0U, // DSRAV >+ 0U, // DSRL >+ 0U, // DSRL32 >+ 0U, // DSRLV >+ 0U, // DSUB >+ 0U, // DSUBu >+ 0U, // DUDIV >+ 0U, // DivRxRy16 >+ 0U, // DivuRxRy16 >+ 0U, // EHB >+ 0U, // EI >+ 0U, // EI_MM >+ 0U, // ERET >+ 0U, // ERET_MM >+ 5U, // EXT >+ 0U, // EXTP >+ 0U, // EXTPDP >+ 0U, // EXTPDPV >+ 0U, // EXTPV >+ 0U, // EXTRV_RS_W >+ 0U, // EXTRV_R_W >+ 0U, // EXTRV_S_H >+ 0U, // EXTRV_W >+ 0U, // EXTR_RS_W >+ 0U, // EXTR_R_W >+ 0U, // EXTR_S_H >+ 0U, // EXTR_W >+ 1U, // EXTS >+ 1U, // EXTS32 >+ 5U, // EXT_MM >+ 0U, // ExtractElementF64 >+ 0U, // ExtractElementF64_64 >+ 0U, // FABS_D >+ 0U, // FABS_D32 >+ 0U, // FABS_D64 >+ 0U, // FABS_MM >+ 0U, // FABS_S >+ 0U, // FABS_S_MM >+ 0U, // FABS_W >+ 0U, // FADD_D >+ 0U, // FADD_D32 >+ 0U, // FADD_D64 >+ 0U, // FADD_MM >+ 0U, // FADD_S >+ 0U, // FADD_S_MM >+ 0U, // FADD_W >+ 0U, // FCAF_D >+ 0U, // FCAF_W >+ 0U, // FCEQ_D >+ 0U, // FCEQ_W >+ 0U, // FCLASS_D >+ 0U, // FCLASS_W >+ 0U, // FCLE_D >+ 0U, // FCLE_W >+ 0U, // FCLT_D >+ 0U, // FCLT_W >+ 0U, // FCMP_D32 >+ 0U, // FCMP_D32_MM >+ 0U, // FCMP_D64 >+ 0U, // FCMP_S32 >+ 0U, // FCMP_S32_MM >+ 0U, // FCNE_D >+ 0U, // FCNE_W >+ 0U, // FCOR_D >+ 0U, // FCOR_W >+ 0U, // FCUEQ_D >+ 0U, // FCUEQ_W >+ 0U, // FCULE_D >+ 0U, // FCULE_W >+ 0U, // FCULT_D >+ 0U, // FCULT_W >+ 0U, // FCUNE_D >+ 0U, // FCUNE_W >+ 0U, // FCUN_D >+ 0U, // FCUN_W >+ 0U, // FDIV_D >+ 0U, // FDIV_D32 >+ 0U, // FDIV_D64 >+ 0U, // FDIV_MM >+ 0U, // FDIV_S >+ 0U, // FDIV_S_MM >+ 0U, // FDIV_W >+ 0U, // FEXDO_H >+ 0U, // FEXDO_W >+ 0U, // FEXP2_D >+ 0U, // FEXP2_D_1_PSEUDO >+ 0U, // FEXP2_W >+ 0U, // FEXP2_W_1_PSEUDO >+ 0U, // FEXUPL_D >+ 0U, // FEXUPL_W >+ 0U, // FEXUPR_D >+ 0U, // FEXUPR_W >+ 0U, // FFINT_S_D >+ 0U, // FFINT_S_W >+ 0U, // FFINT_U_D >+ 0U, // FFINT_U_W >+ 0U, // FFQL_D >+ 0U, // FFQL_W >+ 0U, // FFQR_D >+ 0U, // FFQR_W >+ 0U, // FILL_B >+ 0U, // FILL_D >+ 0U, // FILL_FD_PSEUDO >+ 0U, // FILL_FW_PSEUDO >+ 0U, // FILL_H >+ 0U, // FILL_W >+ 0U, // FLOG2_D >+ 0U, // FLOG2_W >+ 0U, // FLOOR_L_D64 >+ 0U, // FLOOR_L_S >+ 0U, // FLOOR_W_D32 >+ 0U, // FLOOR_W_D64 >+ 0U, // FLOOR_W_MM >+ 0U, // FLOOR_W_S >+ 0U, // FLOOR_W_S_MM >+ 0U, // FMADD_D >+ 0U, // FMADD_W >+ 0U, // FMAX_A_D >+ 0U, // FMAX_A_W >+ 0U, // FMAX_D >+ 0U, // FMAX_W >+ 0U, // FMIN_A_D >+ 0U, // FMIN_A_W >+ 0U, // FMIN_D >+ 0U, // FMIN_W >+ 0U, // FMOV_D32 >+ 0U, // FMOV_D32_MM >+ 0U, // FMOV_D64 >+ 0U, // FMOV_S >+ 0U, // FMOV_S_MM >+ 0U, // FMSUB_D >+ 0U, // FMSUB_W >+ 0U, // FMUL_D >+ 0U, // FMUL_D32 >+ 0U, // FMUL_D64 >+ 0U, // FMUL_MM >+ 0U, // FMUL_S >+ 0U, // FMUL_S_MM >+ 0U, // FMUL_W >+ 0U, // FNEG_D32 >+ 0U, // FNEG_D64 >+ 0U, // FNEG_MM >+ 0U, // FNEG_S >+ 0U, // FNEG_S_MM >+ 0U, // FRCP_D >+ 0U, // FRCP_W >+ 0U, // FRINT_D >+ 0U, // FRINT_W >+ 0U, // FRSQRT_D >+ 0U, // FRSQRT_W >+ 0U, // FSAF_D >+ 0U, // FSAF_W >+ 0U, // FSEQ_D >+ 0U, // FSEQ_W >+ 0U, // FSLE_D >+ 0U, // FSLE_W >+ 0U, // FSLT_D >+ 0U, // FSLT_W >+ 0U, // FSNE_D >+ 0U, // FSNE_W >+ 0U, // FSOR_D >+ 0U, // FSOR_W >+ 0U, // FSQRT_D >+ 0U, // FSQRT_D32 >+ 0U, // FSQRT_D64 >+ 0U, // FSQRT_MM >+ 0U, // FSQRT_S >+ 0U, // FSQRT_S_MM >+ 0U, // FSQRT_W >+ 0U, // FSUB_D >+ 0U, // FSUB_D32 >+ 0U, // FSUB_D64 >+ 0U, // FSUB_MM >+ 0U, // FSUB_S >+ 0U, // FSUB_S_MM >+ 0U, // FSUB_W >+ 0U, // FSUEQ_D >+ 0U, // FSUEQ_W >+ 0U, // FSULE_D >+ 0U, // FSULE_W >+ 0U, // FSULT_D >+ 0U, // FSULT_W >+ 0U, // FSUNE_D >+ 0U, // FSUNE_W >+ 0U, // FSUN_D >+ 0U, // FSUN_W >+ 0U, // FTINT_S_D >+ 0U, // FTINT_S_W >+ 0U, // FTINT_U_D >+ 0U, // FTINT_U_W >+ 0U, // FTQ_H >+ 0U, // FTQ_W >+ 0U, // FTRUNC_S_D >+ 0U, // FTRUNC_S_W >+ 0U, // FTRUNC_U_D >+ 0U, // FTRUNC_U_W >+ 0U, // GotPrologue16 >+ 0U, // HADD_S_D >+ 0U, // HADD_S_H >+ 0U, // HADD_S_W >+ 0U, // HADD_U_D >+ 0U, // HADD_U_H >+ 0U, // HADD_U_W >+ 0U, // HSUB_S_D >+ 0U, // HSUB_S_H >+ 0U, // HSUB_S_W >+ 0U, // HSUB_U_D >+ 0U, // HSUB_U_H >+ 0U, // HSUB_U_W >+ 0U, // ILVEV_B >+ 0U, // ILVEV_D >+ 0U, // ILVEV_H >+ 0U, // ILVEV_W >+ 0U, // ILVL_B >+ 0U, // ILVL_D >+ 0U, // ILVL_H >+ 0U, // ILVL_W >+ 0U, // ILVOD_B >+ 0U, // ILVOD_D >+ 0U, // ILVOD_H >+ 0U, // ILVOD_W >+ 0U, // ILVR_B >+ 0U, // ILVR_D >+ 0U, // ILVR_H >+ 0U, // ILVR_W >+ 5U, // INS >+ 0U, // INSERT_B >+ 0U, // INSERT_B_VIDX_PSEUDO >+ 0U, // INSERT_D >+ 0U, // INSERT_D_VIDX_PSEUDO >+ 0U, // INSERT_FD_PSEUDO >+ 0U, // INSERT_FD_VIDX_PSEUDO >+ 0U, // INSERT_FW_PSEUDO >+ 0U, // INSERT_FW_VIDX_PSEUDO >+ 0U, // INSERT_H >+ 0U, // INSERT_H_VIDX_PSEUDO >+ 0U, // INSERT_W >+ 0U, // INSERT_W_VIDX_PSEUDO >+ 0U, // INSV >+ 0U, // INSVE_B >+ 0U, // INSVE_D >+ 0U, // INSVE_H >+ 0U, // INSVE_W >+ 5U, // INS_MM >+ 0U, // J >+ 0U, // JAL >+ 0U, // JALR >+ 0U, // JALR16_MM >+ 0U, // JALR64 >+ 0U, // JALR64Pseudo >+ 0U, // JALRPseudo >+ 0U, // JALRS_MM >+ 0U, // JALR_HB >+ 0U, // JALR_MM >+ 0U, // JALS_MM >+ 0U, // JALX >+ 0U, // JAL_MM >+ 0U, // JIALC >+ 0U, // JIC >+ 0U, // JR >+ 0U, // JR64 >+ 0U, // JRADDIUSP >+ 0U, // JR_HB >+ 0U, // JR_HB_R6 >+ 0U, // JR_MM >+ 0U, // J_MM >+ 0U, // Jal16 >+ 0U, // JalB16 >+ 0U, // JrRa16 >+ 0U, // JrcRa16 >+ 0U, // JrcRx16 >+ 0U, // JumpLinkReg16 >+ 0U, // LB >+ 0U, // LB64 >+ 0U, // LBUX >+ 0U, // LB_MM >+ 0U, // LBu >+ 0U, // LBu64 >+ 0U, // LBu_MM >+ 0U, // LD >+ 0U, // LDC1 >+ 0U, // LDC164 >+ 0U, // LDC1_MM >+ 0U, // LDC2 >+ 0U, // LDC2_R6 >+ 0U, // LDC3 >+ 0U, // LDI_B >+ 0U, // LDI_D >+ 0U, // LDI_H >+ 0U, // LDI_W >+ 0U, // LDL >+ 0U, // LDPC >+ 0U, // LDR >+ 0U, // LDXC1 >+ 0U, // LDXC164 >+ 0U, // LD_B >+ 0U, // LD_D >+ 0U, // LD_H >+ 0U, // LD_W >+ 0U, // LEA_ADDiu >+ 0U, // LEA_ADDiu64 >+ 0U, // LEA_ADDiu_MM >+ 0U, // LH >+ 0U, // LH64 >+ 0U, // LHX >+ 0U, // LH_MM >+ 0U, // LHu >+ 0U, // LHu64 >+ 0U, // LHu_MM >+ 0U, // LL >+ 0U, // LLD >+ 0U, // LLD_R6 >+ 0U, // LL_MM >+ 0U, // LL_R6 >+ 0U, // LOAD_ACC128 >+ 0U, // LOAD_ACC64 >+ 0U, // LOAD_ACC64DSP >+ 0U, // LOAD_CCOND_DSP >+ 0U, // LONG_BRANCH_ADDiu >+ 0U, // LONG_BRANCH_DADDiu >+ 0U, // LONG_BRANCH_LUi >+ 1U, // LSA >+ 1U, // LSA_R6 >+ 0U, // LUXC1 >+ 0U, // LUXC164 >+ 0U, // LUXC1_MM >+ 0U, // LUi >+ 0U, // LUi64 >+ 0U, // LUi_MM >+ 0U, // LW >+ 0U, // LW64 >+ 0U, // LWC1 >+ 0U, // LWC1_MM >+ 0U, // LWC2 >+ 0U, // LWC2_R6 >+ 0U, // LWC3 >+ 0U, // LWL >+ 0U, // LWL64 >+ 0U, // LWL_MM >+ 0U, // LWPC >+ 0U, // LWR >+ 0U, // LWR64 >+ 0U, // LWR_MM >+ 0U, // LWUPC >+ 0U, // LWU_MM >+ 0U, // LWX >+ 0U, // LWXC1 >+ 0U, // LWXC1_MM >+ 0U, // LW_MM >+ 0U, // LWu >+ 0U, // LbRxRyOffMemX16 >+ 0U, // LbuRxRyOffMemX16 >+ 0U, // LhRxRyOffMemX16 >+ 0U, // LhuRxRyOffMemX16 >+ 0U, // LiRxImm16 >+ 0U, // LiRxImmAlignX16 >+ 0U, // LiRxImmX16 >+ 0U, // LoadAddr32Imm >+ 0U, // LoadAddr32Reg >+ 0U, // LoadImm32Reg >+ 0U, // LoadImm64Reg >+ 0U, // LwConstant32 >+ 0U, // LwRxPcTcp16 >+ 0U, // LwRxPcTcpX16 >+ 0U, // LwRxRyOffMemX16 >+ 0U, // LwRxSpImmX16 >+ 0U, // MADD >+ 0U, // MADDF_D >+ 0U, // MADDF_S >+ 0U, // MADDR_Q_H >+ 0U, // MADDR_Q_W >+ 0U, // MADDU >+ 0U, // MADDU_DSP >+ 0U, // MADDU_MM >+ 0U, // MADDV_B >+ 0U, // MADDV_D >+ 0U, // MADDV_H >+ 0U, // MADDV_W >+ 5U, // MADD_D32 >+ 5U, // MADD_D32_MM >+ 5U, // MADD_D64 >+ 0U, // MADD_DSP >+ 0U, // MADD_MM >+ 0U, // MADD_Q_H >+ 0U, // MADD_Q_W >+ 5U, // MADD_S >+ 5U, // MADD_S_MM >+ 0U, // MAQ_SA_W_PHL >+ 0U, // MAQ_SA_W_PHR >+ 0U, // MAQ_S_W_PHL >+ 0U, // MAQ_S_W_PHR >+ 0U, // MAXA_D >+ 0U, // MAXA_S >+ 0U, // MAXI_S_B >+ 0U, // MAXI_S_D >+ 0U, // MAXI_S_H >+ 0U, // MAXI_S_W >+ 0U, // MAXI_U_B >+ 0U, // MAXI_U_D >+ 0U, // MAXI_U_H >+ 0U, // MAXI_U_W >+ 0U, // MAX_A_B >+ 0U, // MAX_A_D >+ 0U, // MAX_A_H >+ 0U, // MAX_A_W >+ 0U, // MAX_D >+ 0U, // MAX_S >+ 0U, // MAX_S_B >+ 0U, // MAX_S_D >+ 0U, // MAX_S_H >+ 0U, // MAX_S_W >+ 0U, // MAX_U_B >+ 0U, // MAX_U_D >+ 0U, // MAX_U_H >+ 0U, // MAX_U_W >+ 0U, // MFC0 >+ 0U, // MFC1 >+ 0U, // MFC1_MM >+ 0U, // MFC2 >+ 0U, // MFHC1_D32 >+ 0U, // MFHC1_D64 >+ 0U, // MFHC1_MM >+ 0U, // MFHI >+ 0U, // MFHI16_MM >+ 0U, // MFHI64 >+ 0U, // MFHI_DSP >+ 0U, // MFHI_MM >+ 0U, // MFLO >+ 0U, // MFLO16_MM >+ 0U, // MFLO64 >+ 0U, // MFLO_DSP >+ 0U, // MFLO_MM >+ 0U, // MINA_D >+ 0U, // MINA_S >+ 0U, // MINI_S_B >+ 0U, // MINI_S_D >+ 0U, // MINI_S_H >+ 0U, // MINI_S_W >+ 0U, // MINI_U_B >+ 0U, // MINI_U_D >+ 0U, // MINI_U_H >+ 0U, // MINI_U_W >+ 0U, // MIN_A_B >+ 0U, // MIN_A_D >+ 0U, // MIN_A_H >+ 0U, // MIN_A_W >+ 0U, // MIN_D >+ 0U, // MIN_S >+ 0U, // MIN_S_B >+ 0U, // MIN_S_D >+ 0U, // MIN_S_H >+ 0U, // MIN_S_W >+ 0U, // MIN_U_B >+ 0U, // MIN_U_D >+ 0U, // MIN_U_H >+ 0U, // MIN_U_W >+ 0U, // MIPSeh_return32 >+ 0U, // MIPSeh_return64 >+ 0U, // MOD >+ 0U, // MODSUB >+ 0U, // MODU >+ 0U, // MOD_S_B >+ 0U, // MOD_S_D >+ 0U, // MOD_S_H >+ 0U, // MOD_S_W >+ 0U, // MOD_U_B >+ 0U, // MOD_U_D >+ 0U, // MOD_U_H >+ 0U, // MOD_U_W >+ 0U, // MOVE16_MM >+ 0U, // MOVE_V >+ 0U, // MOVF_D32 >+ 0U, // MOVF_D32_MM >+ 0U, // MOVF_D64 >+ 0U, // MOVF_I >+ 0U, // MOVF_I64 >+ 0U, // MOVF_I_MM >+ 0U, // MOVF_S >+ 0U, // MOVF_S_MM >+ 0U, // MOVN_I64_D64 >+ 0U, // MOVN_I64_I >+ 0U, // MOVN_I64_I64 >+ 0U, // MOVN_I64_S >+ 0U, // MOVN_I_D32 >+ 0U, // MOVN_I_D32_MM >+ 0U, // MOVN_I_D64 >+ 0U, // MOVN_I_I >+ 0U, // MOVN_I_I64 >+ 0U, // MOVN_I_MM >+ 0U, // MOVN_I_S >+ 0U, // MOVN_I_S_MM >+ 0U, // MOVT_D32 >+ 0U, // MOVT_D32_MM >+ 0U, // MOVT_D64 >+ 0U, // MOVT_I >+ 0U, // MOVT_I64 >+ 0U, // MOVT_I_MM >+ 0U, // MOVT_S >+ 0U, // MOVT_S_MM >+ 0U, // MOVZ_I64_D64 >+ 0U, // MOVZ_I64_I >+ 0U, // MOVZ_I64_I64 >+ 0U, // MOVZ_I64_S >+ 0U, // MOVZ_I_D32 >+ 0U, // MOVZ_I_D32_MM >+ 0U, // MOVZ_I_D64 >+ 0U, // MOVZ_I_I >+ 0U, // MOVZ_I_I64 >+ 0U, // MOVZ_I_MM >+ 0U, // MOVZ_I_S >+ 0U, // MOVZ_I_S_MM >+ 0U, // MSUB >+ 0U, // MSUBF_D >+ 0U, // MSUBF_S >+ 0U, // MSUBR_Q_H >+ 0U, // MSUBR_Q_W >+ 0U, // MSUBU >+ 0U, // MSUBU_DSP >+ 0U, // MSUBU_MM >+ 0U, // MSUBV_B >+ 0U, // MSUBV_D >+ 0U, // MSUBV_H >+ 0U, // MSUBV_W >+ 5U, // MSUB_D32 >+ 5U, // MSUB_D32_MM >+ 5U, // MSUB_D64 >+ 0U, // MSUB_DSP >+ 0U, // MSUB_MM >+ 0U, // MSUB_Q_H >+ 0U, // MSUB_Q_W >+ 5U, // MSUB_S >+ 5U, // MSUB_S_MM >+ 0U, // MTC0 >+ 0U, // MTC1 >+ 0U, // MTC1_MM >+ 0U, // MTC2 >+ 0U, // MTHC1_D32 >+ 0U, // MTHC1_D64 >+ 0U, // MTHC1_MM >+ 0U, // MTHI >+ 0U, // MTHI64 >+ 0U, // MTHI_DSP >+ 0U, // MTHI_MM >+ 0U, // MTHLIP >+ 0U, // MTLO >+ 0U, // MTLO64 >+ 0U, // MTLO_DSP >+ 0U, // MTLO_MM >+ 0U, // MTM0 >+ 0U, // MTM1 >+ 0U, // MTM2 >+ 0U, // MTP0 >+ 0U, // MTP1 >+ 0U, // MTP2 >+ 0U, // MUH >+ 0U, // MUHU >+ 0U, // MUL >+ 0U, // MULEQ_S_W_PHL >+ 0U, // MULEQ_S_W_PHR >+ 0U, // MULEU_S_PH_QBL >+ 0U, // MULEU_S_PH_QBR >+ 0U, // MULQ_RS_PH >+ 0U, // MULQ_RS_W >+ 0U, // MULQ_S_PH >+ 0U, // MULQ_S_W >+ 0U, // MULR_Q_H >+ 0U, // MULR_Q_W >+ 0U, // MULSAQ_S_W_PH >+ 0U, // MULSA_W_PH >+ 0U, // MULT >+ 0U, // MULTU_DSP >+ 0U, // MULT_DSP >+ 0U, // MULT_MM >+ 0U, // MULTu >+ 0U, // MULTu_MM >+ 0U, // MULU >+ 0U, // MULV_B >+ 0U, // MULV_D >+ 0U, // MULV_H >+ 0U, // MULV_W >+ 0U, // MUL_MM >+ 0U, // MUL_PH >+ 0U, // MUL_Q_H >+ 0U, // MUL_Q_W >+ 0U, // MUL_R6 >+ 0U, // MUL_S_PH >+ 0U, // Mfhi16 >+ 0U, // Mflo16 >+ 0U, // Move32R16 >+ 0U, // MoveR3216 >+ 0U, // MultRxRy16 >+ 0U, // MultRxRyRz16 >+ 0U, // MultuRxRy16 >+ 0U, // MultuRxRyRz16 >+ 0U, // NLOC_B >+ 0U, // NLOC_D >+ 0U, // NLOC_H >+ 0U, // NLOC_W >+ 0U, // NLZC_B >+ 0U, // NLZC_D >+ 0U, // NLZC_H >+ 0U, // NLZC_W >+ 5U, // NMADD_D32 >+ 5U, // NMADD_D32_MM >+ 5U, // NMADD_D64 >+ 5U, // NMADD_S >+ 5U, // NMADD_S_MM >+ 5U, // NMSUB_D32 >+ 5U, // NMSUB_D32_MM >+ 5U, // NMSUB_D64 >+ 5U, // NMSUB_S >+ 5U, // NMSUB_S_MM >+ 0U, // NOP >+ 0U, // NOR >+ 0U, // NOR64 >+ 0U, // NORI_B >+ 0U, // NOR_MM >+ 0U, // NOR_V >+ 0U, // NOR_V_D_PSEUDO >+ 0U, // NOR_V_H_PSEUDO >+ 0U, // NOR_V_W_PSEUDO >+ 0U, // NegRxRy16 >+ 0U, // NotRxRy16 >+ 0U, // OR >+ 0U, // OR64 >+ 0U, // ORI_B >+ 0U, // OR_MM >+ 0U, // OR_V >+ 0U, // OR_V_D_PSEUDO >+ 0U, // OR_V_H_PSEUDO >+ 0U, // OR_V_W_PSEUDO >+ 0U, // ORi >+ 0U, // ORi64 >+ 0U, // ORi_MM >+ 0U, // OrRxRxRy16 >+ 0U, // PACKRL_PH >+ 0U, // PAUSE >+ 0U, // PCKEV_B >+ 0U, // PCKEV_D >+ 0U, // PCKEV_H >+ 0U, // PCKEV_W >+ 0U, // PCKOD_B >+ 0U, // PCKOD_D >+ 0U, // PCKOD_H >+ 0U, // PCKOD_W >+ 0U, // PCNT_B >+ 0U, // PCNT_D >+ 0U, // PCNT_H >+ 0U, // PCNT_W >+ 0U, // PICK_PH >+ 0U, // PICK_QB >+ 0U, // POP >+ 0U, // PRECEQU_PH_QBL >+ 0U, // PRECEQU_PH_QBLA >+ 0U, // PRECEQU_PH_QBR >+ 0U, // PRECEQU_PH_QBRA >+ 0U, // PRECEQ_W_PHL >+ 0U, // PRECEQ_W_PHR >+ 0U, // PRECEU_PH_QBL >+ 0U, // PRECEU_PH_QBLA >+ 0U, // PRECEU_PH_QBR >+ 0U, // PRECEU_PH_QBRA >+ 0U, // PRECRQU_S_QB_PH >+ 0U, // PRECRQ_PH_W >+ 0U, // PRECRQ_QB_PH >+ 0U, // PRECRQ_RS_PH_W >+ 0U, // PRECR_QB_PH >+ 0U, // PRECR_SRA_PH_W >+ 0U, // PRECR_SRA_R_PH_W >+ 0U, // PREF >+ 0U, // PREF_R6 >+ 0U, // PREPEND >+ 0U, // PseudoCMPU_EQ_QB >+ 0U, // PseudoCMPU_LE_QB >+ 0U, // PseudoCMPU_LT_QB >+ 0U, // PseudoCMP_EQ_PH >+ 0U, // PseudoCMP_LE_PH >+ 0U, // PseudoCMP_LT_PH >+ 0U, // PseudoCVT_D32_W >+ 0U, // PseudoCVT_D64_L >+ 0U, // PseudoCVT_D64_W >+ 0U, // PseudoCVT_S_L >+ 0U, // PseudoCVT_S_W >+ 0U, // PseudoDMULT >+ 0U, // PseudoDMULTu >+ 0U, // PseudoDSDIV >+ 0U, // PseudoDUDIV >+ 0U, // PseudoIndirectBranch >+ 0U, // PseudoIndirectBranch64 >+ 0U, // PseudoMADD >+ 0U, // PseudoMADDU >+ 0U, // PseudoMFHI >+ 0U, // PseudoMFHI64 >+ 0U, // PseudoMFLO >+ 0U, // PseudoMFLO64 >+ 0U, // PseudoMSUB >+ 0U, // PseudoMSUBU >+ 0U, // PseudoMTLOHI >+ 0U, // PseudoMTLOHI64 >+ 0U, // PseudoMTLOHI_DSP >+ 0U, // PseudoMULT >+ 0U, // PseudoMULTu >+ 0U, // PseudoPICK_PH >+ 0U, // PseudoPICK_QB >+ 0U, // PseudoReturn >+ 0U, // PseudoReturn64 >+ 0U, // PseudoSDIV >+ 0U, // PseudoUDIV >+ 0U, // RADDU_W_QB >+ 0U, // RDDSP >+ 0U, // RDHWR >+ 0U, // RDHWR64 >+ 0U, // REPLV_PH >+ 0U, // REPLV_QB >+ 0U, // REPL_PH >+ 0U, // REPL_QB >+ 0U, // RINT_D >+ 0U, // RINT_S >+ 0U, // ROTR >+ 0U, // ROTRV >+ 0U, // ROTRV_MM >+ 0U, // ROTR_MM >+ 0U, // ROUND_L_D64 >+ 0U, // ROUND_L_S >+ 0U, // ROUND_W_D32 >+ 0U, // ROUND_W_D64 >+ 0U, // ROUND_W_MM >+ 0U, // ROUND_W_S >+ 0U, // ROUND_W_S_MM >+ 0U, // Restore16 >+ 0U, // RestoreX16 >+ 0U, // RetRA >+ 0U, // RetRA16 >+ 0U, // SAT_S_B >+ 0U, // SAT_S_D >+ 0U, // SAT_S_H >+ 0U, // SAT_S_W >+ 0U, // SAT_U_B >+ 0U, // SAT_U_D >+ 0U, // SAT_U_H >+ 0U, // SAT_U_W >+ 0U, // SB >+ 0U, // SB64 >+ 0U, // SB_MM >+ 0U, // SC >+ 0U, // SCD >+ 0U, // SCD_R6 >+ 0U, // SC_MM >+ 0U, // SC_R6 >+ 0U, // SD >+ 0U, // SDBBP >+ 0U, // SDBBP_R6 >+ 0U, // SDC1 >+ 0U, // SDC164 >+ 0U, // SDC1_MM >+ 0U, // SDC2 >+ 0U, // SDC2_R6 >+ 0U, // SDC3 >+ 0U, // SDIV >+ 0U, // SDIV_MM >+ 0U, // SDL >+ 0U, // SDR >+ 0U, // SDXC1 >+ 0U, // SDXC164 >+ 0U, // SEB >+ 0U, // SEB64 >+ 0U, // SEB_MM >+ 0U, // SEH >+ 0U, // SEH64 >+ 0U, // SEH_MM >+ 0U, // SELEQZ >+ 0U, // SELEQZ64 >+ 0U, // SELEQZ_D >+ 0U, // SELEQZ_S >+ 0U, // SELNEZ >+ 0U, // SELNEZ64 >+ 0U, // SELNEZ_D >+ 0U, // SELNEZ_S >+ 0U, // SEL_D >+ 0U, // SEL_S >+ 0U, // SEQ >+ 0U, // SEQi >+ 0U, // SH >+ 0U, // SH64 >+ 0U, // SHF_B >+ 0U, // SHF_H >+ 0U, // SHF_W >+ 0U, // SHILO >+ 0U, // SHILOV >+ 0U, // SHLLV_PH >+ 0U, // SHLLV_QB >+ 0U, // SHLLV_S_PH >+ 0U, // SHLLV_S_W >+ 0U, // SHLL_PH >+ 0U, // SHLL_QB >+ 0U, // SHLL_S_PH >+ 0U, // SHLL_S_W >+ 0U, // SHRAV_PH >+ 0U, // SHRAV_QB >+ 0U, // SHRAV_R_PH >+ 0U, // SHRAV_R_QB >+ 0U, // SHRAV_R_W >+ 0U, // SHRA_PH >+ 0U, // SHRA_QB >+ 0U, // SHRA_R_PH >+ 0U, // SHRA_R_QB >+ 0U, // SHRA_R_W >+ 0U, // SHRLV_PH >+ 0U, // SHRLV_QB >+ 0U, // SHRL_PH >+ 0U, // SHRL_QB >+ 0U, // SH_MM >+ 2U, // SLDI_B >+ 2U, // SLDI_D >+ 2U, // SLDI_H >+ 2U, // SLDI_W >+ 2U, // SLD_B >+ 2U, // SLD_D >+ 2U, // SLD_H >+ 2U, // SLD_W >+ 0U, // SLL >+ 0U, // SLL64_32 >+ 0U, // SLL64_64 >+ 0U, // SLLI_B >+ 0U, // SLLI_D >+ 0U, // SLLI_H >+ 0U, // SLLI_W >+ 0U, // SLLV >+ 0U, // SLLV_MM >+ 0U, // SLL_B >+ 0U, // SLL_D >+ 0U, // SLL_H >+ 0U, // SLL_MM >+ 0U, // SLL_W >+ 0U, // SLT >+ 0U, // SLT64 >+ 0U, // SLT_MM >+ 0U, // SLTi >+ 0U, // SLTi64 >+ 0U, // SLTi_MM >+ 0U, // SLTiu >+ 0U, // SLTiu64 >+ 0U, // SLTiu_MM >+ 0U, // SLTu >+ 0U, // SLTu64 >+ 0U, // SLTu_MM >+ 0U, // SNE >+ 0U, // SNEi >+ 0U, // SNZ_B_PSEUDO >+ 0U, // SNZ_D_PSEUDO >+ 0U, // SNZ_H_PSEUDO >+ 0U, // SNZ_V_PSEUDO >+ 0U, // SNZ_W_PSEUDO >+ 2U, // SPLATI_B >+ 2U, // SPLATI_D >+ 2U, // SPLATI_H >+ 2U, // SPLATI_W >+ 2U, // SPLAT_B >+ 2U, // SPLAT_D >+ 2U, // SPLAT_H >+ 2U, // SPLAT_W >+ 0U, // SRA >+ 0U, // SRAI_B >+ 0U, // SRAI_D >+ 0U, // SRAI_H >+ 0U, // SRAI_W >+ 0U, // SRARI_B >+ 0U, // SRARI_D >+ 0U, // SRARI_H >+ 0U, // SRARI_W >+ 0U, // SRAR_B >+ 0U, // SRAR_D >+ 0U, // SRAR_H >+ 0U, // SRAR_W >+ 0U, // SRAV >+ 0U, // SRAV_MM >+ 0U, // SRA_B >+ 0U, // SRA_D >+ 0U, // SRA_H >+ 0U, // SRA_MM >+ 0U, // SRA_W >+ 0U, // SRL >+ 0U, // SRLI_B >+ 0U, // SRLI_D >+ 0U, // SRLI_H >+ 0U, // SRLI_W >+ 0U, // SRLRI_B >+ 0U, // SRLRI_D >+ 0U, // SRLRI_H >+ 0U, // SRLRI_W >+ 0U, // SRLR_B >+ 0U, // SRLR_D >+ 0U, // SRLR_H >+ 0U, // SRLR_W >+ 0U, // SRLV >+ 0U, // SRLV_MM >+ 0U, // SRL_B >+ 0U, // SRL_D >+ 0U, // SRL_H >+ 0U, // SRL_MM >+ 0U, // SRL_W >+ 0U, // SSNOP >+ 0U, // STORE_ACC128 >+ 0U, // STORE_ACC64 >+ 0U, // STORE_ACC64DSP >+ 0U, // STORE_CCOND_DSP >+ 0U, // ST_B >+ 0U, // ST_D >+ 0U, // ST_H >+ 0U, // ST_W >+ 0U, // SUB >+ 0U, // SUBQH_PH >+ 0U, // SUBQH_R_PH >+ 0U, // SUBQH_R_W >+ 0U, // SUBQH_W >+ 0U, // SUBQ_PH >+ 0U, // SUBQ_S_PH >+ 0U, // SUBQ_S_W >+ 0U, // SUBSUS_U_B >+ 0U, // SUBSUS_U_D >+ 0U, // SUBSUS_U_H >+ 0U, // SUBSUS_U_W >+ 0U, // SUBSUU_S_B >+ 0U, // SUBSUU_S_D >+ 0U, // SUBSUU_S_H >+ 0U, // SUBSUU_S_W >+ 0U, // SUBS_S_B >+ 0U, // SUBS_S_D >+ 0U, // SUBS_S_H >+ 0U, // SUBS_S_W >+ 0U, // SUBS_U_B >+ 0U, // SUBS_U_D >+ 0U, // SUBS_U_H >+ 0U, // SUBS_U_W >+ 0U, // SUBUH_QB >+ 0U, // SUBUH_R_QB >+ 0U, // SUBU_PH >+ 0U, // SUBU_QB >+ 0U, // SUBU_S_PH >+ 0U, // SUBU_S_QB >+ 0U, // SUBVI_B >+ 0U, // SUBVI_D >+ 0U, // SUBVI_H >+ 0U, // SUBVI_W >+ 0U, // SUBV_B >+ 0U, // SUBV_D >+ 0U, // SUBV_H >+ 0U, // SUBV_W >+ 0U, // SUB_MM >+ 0U, // SUBu >+ 0U, // SUBu_MM >+ 0U, // SUXC1 >+ 0U, // SUXC164 >+ 0U, // SUXC1_MM >+ 0U, // SW >+ 0U, // SW64 >+ 0U, // SWC1 >+ 0U, // SWC1_MM >+ 0U, // SWC2 >+ 0U, // SWC2_R6 >+ 0U, // SWC3 >+ 0U, // SWL >+ 0U, // SWL64 >+ 0U, // SWL_MM >+ 0U, // SWR >+ 0U, // SWR64 >+ 0U, // SWR_MM >+ 0U, // SWXC1 >+ 0U, // SWXC1_MM >+ 0U, // SW_MM >+ 0U, // SYNC >+ 0U, // SYNC_MM >+ 0U, // SYSCALL >+ 0U, // SYSCALL_MM >+ 0U, // SZ_B_PSEUDO >+ 0U, // SZ_D_PSEUDO >+ 0U, // SZ_H_PSEUDO >+ 0U, // SZ_V_PSEUDO >+ 0U, // SZ_W_PSEUDO >+ 0U, // Save16 >+ 0U, // SaveX16 >+ 0U, // SbRxRyOffMemX16 >+ 0U, // SebRx16 >+ 0U, // SehRx16 >+ 0U, // SelBeqZ >+ 0U, // SelBneZ >+ 0U, // SelTBteqZCmp >+ 0U, // SelTBteqZCmpi >+ 0U, // SelTBteqZSlt >+ 0U, // SelTBteqZSlti >+ 0U, // SelTBteqZSltiu >+ 0U, // SelTBteqZSltu >+ 0U, // SelTBtneZCmp >+ 0U, // SelTBtneZCmpi >+ 0U, // SelTBtneZSlt >+ 0U, // SelTBtneZSlti >+ 0U, // SelTBtneZSltiu >+ 0U, // SelTBtneZSltu >+ 0U, // ShRxRyOffMemX16 >+ 0U, // SllX16 >+ 0U, // SllvRxRy16 >+ 0U, // SltCCRxRy16 >+ 0U, // SltRxRy16 >+ 0U, // SltiCCRxImmX16 >+ 0U, // SltiRxImm16 >+ 0U, // SltiRxImmX16 >+ 0U, // SltiuCCRxImmX16 >+ 0U, // SltiuRxImm16 >+ 0U, // SltiuRxImmX16 >+ 0U, // SltuCCRxRy16 >+ 0U, // SltuRxRy16 >+ 0U, // SltuRxRyRz16 >+ 0U, // SraX16 >+ 0U, // SravRxRy16 >+ 0U, // SrlX16 >+ 0U, // SrlvRxRy16 >+ 0U, // SubuRxRyRz16 >+ 0U, // SwRxRyOffMemX16 >+ 0U, // SwRxSpImmX16 >+ 0U, // TAILCALL >+ 0U, // TAILCALL64_R >+ 0U, // TAILCALL_R >+ 0U, // TEQ >+ 0U, // TEQI >+ 0U, // TEQI_MM >+ 0U, // TEQ_MM >+ 0U, // TGE >+ 0U, // TGEI >+ 0U, // TGEIU >+ 0U, // TGEIU_MM >+ 0U, // TGEI_MM >+ 0U, // TGEU >+ 0U, // TGEU_MM >+ 0U, // TGE_MM >+ 0U, // TLBP >+ 0U, // TLBP_MM >+ 0U, // TLBR >+ 0U, // TLBR_MM >+ 0U, // TLBWI >+ 0U, // TLBWI_MM >+ 0U, // TLBWR >+ 0U, // TLBWR_MM >+ 0U, // TLT >+ 0U, // TLTI >+ 0U, // TLTIU_MM >+ 0U, // TLTI_MM >+ 0U, // TLTU >+ 0U, // TLTU_MM >+ 0U, // TLT_MM >+ 0U, // TNE >+ 0U, // TNEI >+ 0U, // TNEI_MM >+ 0U, // TNE_MM >+ 0U, // TRAP >+ 0U, // TRUNC_L_D64 >+ 0U, // TRUNC_L_S >+ 0U, // TRUNC_W_D32 >+ 0U, // TRUNC_W_D64 >+ 0U, // TRUNC_W_MM >+ 0U, // TRUNC_W_S >+ 0U, // TRUNC_W_S_MM >+ 0U, // TTLTIU >+ 0U, // UDIV >+ 0U, // UDIV_MM >+ 0U, // V3MULU >+ 0U, // VMM0 >+ 0U, // VMULU >+ 0U, // VSHF_B >+ 0U, // VSHF_D >+ 0U, // VSHF_H >+ 0U, // VSHF_W >+ 0U, // WAIT >+ 0U, // WAIT_MM >+ 0U, // WRDSP >+ 0U, // WSBH >+ 0U, // WSBH_MM >+ 0U, // XOR >+ 0U, // XOR64 >+ 0U, // XORI_B >+ 0U, // XOR_MM >+ 0U, // XOR_V >+ 0U, // XOR_V_D_PSEUDO >+ 0U, // XOR_V_H_PSEUDO >+ 0U, // XOR_V_W_PSEUDO >+ 0U, // XORi >+ 0U, // XORi64 >+ 0U, // XORi_MM >+ 0U, // XorRxRxRy16 >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0, >+ /* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0, >+ /* 15 */ 'd', 'm', 't', 'c', '0', 9, 0, >+ /* 22 */ 'v', 'm', 'm', '0', 9, 0, >+ /* 28 */ 'm', 't', 'm', '0', 9, 0, >+ /* 34 */ 'm', 't', 'p', '0', 9, 0, >+ /* 40 */ 'l', 'd', 'c', '1', 9, 0, >+ /* 46 */ 's', 'd', 'c', '1', 9, 0, >+ /* 52 */ 'c', 'f', 'c', '1', 9, 0, >+ /* 58 */ 'd', 'm', 'f', 'c', '1', 9, 0, >+ /* 65 */ 'm', 'f', 'h', 'c', '1', 9, 0, >+ /* 72 */ 'm', 't', 'h', 'c', '1', 9, 0, >+ /* 79 */ 'c', 't', 'c', '1', 9, 0, >+ /* 85 */ 'd', 'm', 't', 'c', '1', 9, 0, >+ /* 92 */ 'l', 'w', 'c', '1', 9, 0, >+ /* 98 */ 's', 'w', 'c', '1', 9, 0, >+ /* 104 */ 'l', 'd', 'x', 'c', '1', 9, 0, >+ /* 111 */ 's', 'd', 'x', 'c', '1', 9, 0, >+ /* 118 */ 'l', 'u', 'x', 'c', '1', 9, 0, >+ /* 125 */ 's', 'u', 'x', 'c', '1', 9, 0, >+ /* 132 */ 'l', 'w', 'x', 'c', '1', 9, 0, >+ /* 139 */ 's', 'w', 'x', 'c', '1', 9, 0, >+ /* 146 */ 'm', 't', 'm', '1', 9, 0, >+ /* 152 */ 'm', 't', 'p', '1', 9, 0, >+ /* 158 */ 'd', 's', 'r', 'a', '3', '2', 9, 0, >+ /* 166 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0, >+ /* 176 */ 'd', 's', 'l', 'l', '3', '2', 9, 0, >+ /* 184 */ 'd', 's', 'r', 'l', '3', '2', 9, 0, >+ /* 192 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0, >+ /* 201 */ 'l', 'd', 'c', '2', 9, 0, >+ /* 207 */ 's', 'd', 'c', '2', 9, 0, >+ /* 213 */ 'd', 'm', 'f', 'c', '2', 9, 0, >+ /* 220 */ 'd', 'm', 't', 'c', '2', 9, 0, >+ /* 227 */ 'l', 'w', 'c', '2', 9, 0, >+ /* 233 */ 's', 'w', 'c', '2', 9, 0, >+ /* 239 */ 'm', 't', 'm', '2', 9, 0, >+ /* 245 */ 'm', 't', 'p', '2', 9, 0, >+ /* 251 */ 'l', 'd', 'c', '3', 9, 0, >+ /* 257 */ 's', 'd', 'c', '3', 9, 0, >+ /* 263 */ 'l', 'w', 'c', '3', 9, 0, >+ /* 269 */ 's', 'w', 'c', '3', 9, 0, >+ /* 275 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, >+ /* 291 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0, >+ /* 308 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, >+ /* 324 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0, >+ /* 341 */ 'd', 's', 'r', 'a', 9, 0, >+ /* 347 */ 'd', 'l', 's', 'a', 9, 0, >+ /* 353 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0, >+ /* 361 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0, >+ /* 369 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0, >+ /* 378 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0, >+ /* 387 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0, >+ /* 397 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0, >+ /* 406 */ 's', 'r', 'a', '.', 'b', 9, 0, >+ /* 413 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0, >+ /* 421 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0, >+ /* 429 */ 's', 'l', 'd', '.', 'b', 9, 0, >+ /* 436 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0, >+ /* 445 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0, >+ /* 454 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0, >+ /* 463 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0, >+ /* 471 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0, >+ /* 479 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0, >+ /* 487 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0, >+ /* 495 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0, >+ /* 503 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0, >+ /* 512 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0, >+ /* 521 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0, >+ /* 529 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0, >+ /* 537 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0, >+ /* 547 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0, >+ /* 555 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0, >+ /* 564 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0, >+ /* 573 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0, >+ /* 582 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0, >+ /* 590 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0, >+ /* 598 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0, >+ /* 608 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0, >+ /* 618 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0, >+ /* 627 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0, >+ /* 636 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0, >+ /* 645 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0, >+ /* 653 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0, >+ /* 662 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0, >+ /* 670 */ 's', 'l', 'l', '.', 'b', 9, 0, >+ /* 677 */ 's', 'r', 'l', '.', 'b', 9, 0, >+ /* 684 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0, >+ /* 693 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0, >+ /* 701 */ 'c', 'e', 'q', '.', 'b', 9, 0, >+ /* 708 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0, >+ /* 716 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0, >+ /* 724 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0, >+ /* 732 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0, >+ /* 741 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0, >+ /* 749 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0, >+ /* 759 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0, >+ /* 768 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0, >+ /* 777 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0, >+ /* 786 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 796 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 806 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 816 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0, >+ /* 826 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0, >+ /* 835 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0, >+ /* 845 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0, >+ /* 855 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0, >+ /* 865 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0, >+ /* 874 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0, >+ /* 883 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0, >+ /* 895 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0, >+ /* 904 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0, >+ /* 913 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0, >+ /* 923 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0, >+ /* 932 */ 'b', 's', 'e', 't', '.', 'b', 9, 0, >+ /* 940 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0, >+ /* 948 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0, >+ /* 958 */ 's', 't', '.', 'b', 9, 0, >+ /* 964 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0, >+ /* 974 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0, >+ /* 983 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0, >+ /* 992 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0, >+ /* 1001 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1011 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1021 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1031 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0, >+ /* 1041 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0, >+ /* 1050 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0, >+ /* 1060 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1070 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1080 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0, >+ /* 1092 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0, >+ /* 1101 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0, >+ /* 1110 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0, >+ /* 1119 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0, >+ /* 1128 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0, >+ /* 1138 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0, >+ /* 1147 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0, >+ /* 1156 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0, >+ /* 1165 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0, >+ /* 1174 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0, >+ /* 1182 */ 'b', 'z', '.', 'b', 9, 0, >+ /* 1188 */ 'b', 'n', 'z', '.', 'b', 9, 0, >+ /* 1195 */ 's', 'e', 'b', 9, 0, >+ /* 1200 */ 'j', 'r', '.', 'h', 'b', 9, 0, >+ /* 1207 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0, >+ /* 1216 */ 'l', 'b', 9, 0, >+ /* 1220 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0, >+ /* 1229 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1243 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1256 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0, >+ /* 1268 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0, >+ /* 1278 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0, >+ /* 1288 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0, >+ /* 1297 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0, >+ /* 1306 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0, >+ /* 1315 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0, >+ /* 1324 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1338 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1351 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0, >+ /* 1363 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1374 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1386 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1398 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0, >+ /* 1410 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1421 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1432 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0, >+ /* 1443 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1457 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1470 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0, >+ /* 1482 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0, >+ /* 1491 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0, >+ /* 1500 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0, >+ /* 1510 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1520 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1530 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0, >+ /* 1540 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0, >+ /* 1552 */ 's', 'b', 9, 0, >+ /* 1556 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0, >+ /* 1564 */ 'm', 's', 'u', 'b', 9, 0, >+ /* 1570 */ 'b', 'c', 9, 0, >+ /* 1574 */ 'b', 'g', 'e', 'c', 9, 0, >+ /* 1580 */ 'b', 'n', 'e', 'c', 9, 0, >+ /* 1586 */ 'j', 'i', 'c', 9, 0, >+ /* 1591 */ 'b', 'a', 'l', 'c', 9, 0, >+ /* 1597 */ 'j', 'i', 'a', 'l', 'c', 9, 0, >+ /* 1604 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1613 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1622 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1631 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1640 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1649 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0, >+ /* 1658 */ 'l', 'd', 'p', 'c', 9, 0, >+ /* 1664 */ 'a', 'u', 'i', 'p', 'c', 9, 0, >+ /* 1671 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0, >+ /* 1679 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0, >+ /* 1688 */ 'l', 'w', 'u', 'p', 'c', 9, 0, >+ /* 1695 */ 'l', 'w', 'p', 'c', 9, 0, >+ /* 1701 */ 'b', 'e', 'q', 'c', 9, 0, >+ /* 1707 */ 'a', 'd', 'd', 's', 'c', 9, 0, >+ /* 1714 */ 'b', 'l', 't', 'c', 9, 0, >+ /* 1720 */ 'b', 'g', 'e', 'u', 'c', 9, 0, >+ /* 1727 */ 'b', 'l', 't', 'u', 'c', 9, 0, >+ /* 1734 */ 'b', 'n', 'v', 'c', 9, 0, >+ /* 1740 */ 'b', 'o', 'v', 'c', 9, 0, >+ /* 1746 */ 'a', 'd', 'd', 'w', 'c', 9, 0, >+ /* 1753 */ 'b', 'g', 'e', 'z', 'c', 9, 0, >+ /* 1760 */ 'b', 'l', 'e', 'z', 'c', 9, 0, >+ /* 1767 */ 'b', 'n', 'e', 'z', 'c', 9, 0, >+ /* 1774 */ 'b', 'e', 'q', 'z', 'c', 9, 0, >+ /* 1781 */ 'b', 'g', 't', 'z', 'c', 9, 0, >+ /* 1788 */ 'b', 'l', 't', 'z', 'c', 9, 0, >+ /* 1795 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0, >+ /* 1804 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0, >+ /* 1813 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0, >+ /* 1822 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0, >+ /* 1832 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0, >+ /* 1842 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0, >+ /* 1852 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0, >+ /* 1860 */ 's', 'r', 'a', '.', 'd', 9, 0, >+ /* 1867 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0, >+ /* 1875 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 1883 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 1892 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, >+ /* 1901 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0, >+ /* 1909 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0, >+ /* 1917 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 1925 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 1934 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, >+ /* 1943 */ 's', 'l', 'd', '.', 'd', 9, 0, >+ /* 1950 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0, >+ /* 1959 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0, >+ /* 1968 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0, >+ /* 1977 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0, >+ /* 1985 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0, >+ /* 1995 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0, >+ /* 2003 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0, >+ /* 2013 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0, >+ /* 2022 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0, >+ /* 2033 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0, >+ /* 2041 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2050 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2061 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2070 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2082 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0, >+ /* 2091 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0, >+ /* 2099 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0, >+ /* 2107 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0, >+ /* 2116 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0, >+ /* 2125 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0, >+ /* 2134 */ 'c', '.', 'f', '.', 'd', 9, 0, >+ /* 2141 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0, >+ /* 2151 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0, >+ /* 2159 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0, >+ /* 2170 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0, >+ /* 2178 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0, >+ /* 2187 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0, >+ /* 2196 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0, >+ /* 2204 */ 'c', '.', 's', 'f', '.', 'd', 9, 0, >+ /* 2212 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0, >+ /* 2220 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0, >+ /* 2228 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0, >+ /* 2236 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0, >+ /* 2244 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0, >+ /* 2253 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0, >+ /* 2261 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0, >+ /* 2269 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0, >+ /* 2279 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0, >+ /* 2287 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0, >+ /* 2296 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0, >+ /* 2305 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0, >+ /* 2314 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0, >+ /* 2324 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0, >+ /* 2334 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0, >+ /* 2343 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0, >+ /* 2352 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0, >+ /* 2361 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0, >+ /* 2372 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0, >+ /* 2383 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0, >+ /* 2393 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0, >+ /* 2404 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, >+ /* 2413 */ 's', 'e', 'l', '.', 'd', 9, 0, >+ /* 2420 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0, >+ /* 2429 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0, >+ /* 2437 */ 's', 'l', 'l', '.', 'd', 9, 0, >+ /* 2444 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0, >+ /* 2454 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0, >+ /* 2462 */ 's', 'r', 'l', '.', 'd', 9, 0, >+ /* 2469 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0, >+ /* 2478 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, >+ /* 2486 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0, >+ /* 2494 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, >+ /* 2502 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0, >+ /* 2510 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0, >+ /* 2520 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0, >+ /* 2528 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0, >+ /* 2539 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0, >+ /* 2547 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0, >+ /* 2555 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0, >+ /* 2563 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0, >+ /* 2571 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0, >+ /* 2581 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0, >+ /* 2589 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2598 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2609 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0, >+ /* 2617 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2626 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2637 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2646 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2658 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0, >+ /* 2667 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0, >+ /* 2675 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0, >+ /* 2683 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0, >+ /* 2691 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0, >+ /* 2699 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0, >+ /* 2707 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0, >+ /* 2717 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0, >+ /* 2725 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0, >+ /* 2734 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0, >+ /* 2742 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, >+ /* 2751 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 2761 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 2771 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0, >+ /* 2782 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0, >+ /* 2794 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 2804 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 2815 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0, >+ /* 2824 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0, >+ /* 2833 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0, >+ /* 2842 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 2852 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 2862 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 2872 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0, >+ /* 2882 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0, >+ /* 2891 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0, >+ /* 2901 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0, >+ /* 2911 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0, >+ /* 2921 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0, >+ /* 2931 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0, >+ /* 2940 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0, >+ /* 2949 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, >+ /* 2960 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0, >+ /* 2971 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0, >+ /* 2983 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0, >+ /* 2992 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0, >+ /* 3001 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0, >+ /* 3011 */ 'a', 'b', 's', '.', 'd', 9, 0, >+ /* 3018 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, >+ /* 3028 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0, >+ /* 3037 */ 'b', 's', 'e', 't', '.', 'd', 9, 0, >+ /* 3045 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0, >+ /* 3054 */ 'c', '.', 'l', 't', '.', 'd', 9, 0, >+ /* 3062 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0, >+ /* 3072 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0, >+ /* 3080 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0, >+ /* 3089 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0, >+ /* 3100 */ 'f', 's', 'l', 't', '.', 'd', 9, 0, >+ /* 3108 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3117 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3128 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3137 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3149 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0, >+ /* 3158 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0, >+ /* 3166 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0, >+ /* 3175 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0, >+ /* 3185 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, >+ /* 3194 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0, >+ /* 3204 */ 's', 't', '.', 'd', 9, 0, >+ /* 3210 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0, >+ /* 3218 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3228 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3238 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0, >+ /* 3249 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0, >+ /* 3261 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3271 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3282 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0, >+ /* 3291 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0, >+ /* 3300 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0, >+ /* 3309 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3319 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3329 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3339 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0, >+ /* 3349 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0, >+ /* 3358 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0, >+ /* 3368 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0, >+ /* 3378 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3388 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3398 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0, >+ /* 3410 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3419 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3428 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3439 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0, >+ /* 3450 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0, >+ /* 3459 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0, >+ /* 3468 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'd', 9, 0, >+ /* 3478 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0, >+ /* 3487 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0, >+ /* 3496 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0, >+ /* 3505 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0, >+ /* 3514 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, >+ /* 3522 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0, >+ /* 3530 */ 'm', 'o', 'v', '.', 'd', 9, 0, >+ /* 3537 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0, >+ /* 3548 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0, >+ /* 3559 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0, >+ /* 3569 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0, >+ /* 3580 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, >+ /* 3589 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, >+ /* 3597 */ 'b', 'z', '.', 'd', 9, 0, >+ /* 3603 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0, >+ /* 3613 */ 'b', 'n', 'z', '.', 'd', 9, 0, >+ /* 3620 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0, >+ /* 3630 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0, >+ /* 3638 */ 's', 'c', 'd', 9, 0, >+ /* 3643 */ 'd', 'a', 'd', 'd', 9, 0, >+ /* 3649 */ 'm', 'a', 'd', 'd', 9, 0, >+ /* 3655 */ 'd', 's', 'h', 'd', 9, 0, >+ /* 3661 */ 'l', 'l', 'd', 9, 0, >+ /* 3666 */ 'a', 'n', 'd', 9, 0, >+ /* 3671 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0, >+ /* 3680 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0, >+ /* 3688 */ 'd', 'm', 'o', 'd', 9, 0, >+ /* 3694 */ 's', 'd', 9, 0, >+ /* 3698 */ 't', 'g', 'e', 9, 0, >+ /* 3703 */ 'c', 'a', 'c', 'h', 'e', 9, 0, >+ /* 3710 */ 'b', 'n', 'e', 9, 0, >+ /* 3715 */ 's', 'n', 'e', 9, 0, >+ /* 3720 */ 't', 'n', 'e', 9, 0, >+ /* 3725 */ 'm', 'o', 'v', 'e', 9, 0, >+ /* 3731 */ 'b', 'c', '0', 'f', 9, 0, >+ /* 3737 */ 'b', 'c', '1', 'f', 9, 0, >+ /* 3743 */ 'b', 'c', '2', 'f', 9, 0, >+ /* 3749 */ 'b', 'c', '3', 'f', 9, 0, >+ /* 3755 */ 'p', 'r', 'e', 'f', 9, 0, >+ /* 3761 */ 'm', 'o', 'v', 'f', 9, 0, >+ /* 3767 */ 'n', 'e', 'g', 9, 0, >+ /* 3772 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0, >+ /* 3781 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0, >+ /* 3790 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0, >+ /* 3800 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0, >+ /* 3809 */ 's', 'r', 'a', '.', 'h', 9, 0, >+ /* 3816 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0, >+ /* 3824 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0, >+ /* 3832 */ 's', 'l', 'd', '.', 'h', 9, 0, >+ /* 3839 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0, >+ /* 3848 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0, >+ /* 3857 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0, >+ /* 3866 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0, >+ /* 3874 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0, >+ /* 3882 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0, >+ /* 3890 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0, >+ /* 3898 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0, >+ /* 3907 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0, >+ /* 3915 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0, >+ /* 3923 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0, >+ /* 3933 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0, >+ /* 3941 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0, >+ /* 3950 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0, >+ /* 3959 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0, >+ /* 3968 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0, >+ /* 3978 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0, >+ /* 3988 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0, >+ /* 3997 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0, >+ /* 4006 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0, >+ /* 4015 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0, >+ /* 4023 */ 's', 'l', 'l', '.', 'h', 9, 0, >+ /* 4030 */ 's', 'r', 'l', '.', 'h', 9, 0, >+ /* 4037 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0, >+ /* 4046 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0, >+ /* 4054 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0, >+ /* 4063 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0, >+ /* 4073 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0, >+ /* 4083 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0, >+ /* 4092 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4103 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4114 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0, >+ /* 4124 */ 'c', 'e', 'q', '.', 'h', 9, 0, >+ /* 4131 */ 'f', 't', 'q', '.', 'h', 9, 0, >+ /* 4138 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0, >+ /* 4146 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0, >+ /* 4154 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0, >+ /* 4162 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0, >+ /* 4171 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0, >+ /* 4179 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4189 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4199 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0, >+ /* 4210 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4220 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4231 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0, >+ /* 4240 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0, >+ /* 4249 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0, >+ /* 4258 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4268 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4278 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4288 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0, >+ /* 4298 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0, >+ /* 4307 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0, >+ /* 4317 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0, >+ /* 4327 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0, >+ /* 4337 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0, >+ /* 4347 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0, >+ /* 4357 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0, >+ /* 4366 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0, >+ /* 4375 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0, >+ /* 4387 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0, >+ /* 4396 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0, >+ /* 4407 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0, >+ /* 4416 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0, >+ /* 4426 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0, >+ /* 4435 */ 'b', 's', 'e', 't', '.', 'h', 9, 0, >+ /* 4443 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0, >+ /* 4451 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0, >+ /* 4461 */ 's', 't', '.', 'h', 9, 0, >+ /* 4467 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, >+ /* 4477 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, >+ /* 4487 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0, >+ /* 4498 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, >+ /* 4508 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0, >+ /* 4519 */ 'm', 'o', 'd', '_', 'u', '.', 'h', 9, 0, >+ /* 4528 */ 'c', 'l', 'e', '_', 'u', '.', 'h', 9, 0, >+ /* 4537 */ 'a', 'v', 'e', '_', 'u', '.', 'h', 9, 0, >+ /* 4546 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'h', 9, 0, >+ /* 4556 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'h', 9, 0, >+ /* 4566 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'h', 9, 0, >+ /* 4576 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'h', 9, 0, >+ /* 4586 */ 'm', 'i', 'n', '_', 'u', '.', 'h', 9, 0, >+ /* 4595 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'h', 9, 0, >+ /* 4605 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'h', 9, 0, >+ /* 4615 */ 's', 'u', 'b', 's', '_', 'u', '.', 'h', 9, 0, >+ /* 4625 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0, >+ /* 4635 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0, >+ /* 4647 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0, >+ /* 4656 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0, >+ /* 4665 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0, >+ /* 4674 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0, >+ /* 4683 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0, >+ /* 4693 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0, >+ /* 4702 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0, >+ /* 4711 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0, >+ /* 4720 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0, >+ /* 4729 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0, >+ /* 4737 */ 'b', 'z', '.', 'h', 9, 0, >+ /* 4743 */ 'b', 'n', 'z', '.', 'h', 9, 0, >+ /* 4750 */ 'd', 's', 'b', 'h', 9, 0, >+ /* 4756 */ 'w', 's', 'b', 'h', 9, 0, >+ /* 4762 */ 's', 'e', 'h', 9, 0, >+ /* 4767 */ 'l', 'h', 9, 0, >+ /* 4771 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0, >+ /* 4780 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 4794 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 4807 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0, >+ /* 4824 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0, >+ /* 4835 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0, >+ /* 4845 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0, >+ /* 4855 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0, >+ /* 4864 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0, >+ /* 4873 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0, >+ /* 4882 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0, >+ /* 4891 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0, >+ /* 4902 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0, >+ /* 4910 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0, >+ /* 4919 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0, >+ /* 4928 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0, >+ /* 4939 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 4950 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 4962 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 4974 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0, >+ /* 4986 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 4997 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5007 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5018 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5029 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5040 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5051 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5062 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5073 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0, >+ /* 5085 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0, >+ /* 5097 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0, >+ /* 5108 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0, >+ /* 5117 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0, >+ /* 5126 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0, >+ /* 5136 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5146 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5156 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0, >+ /* 5166 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5176 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5191 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5206 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5218 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5231 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5246 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5259 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5273 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5287 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5297 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5308 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0, >+ /* 5319 */ 's', 'h', 9, 0, >+ /* 5323 */ 'd', 'm', 'u', 'h', 9, 0, >+ /* 5329 */ 'd', 'a', 'd', 'd', 'i', 9, 0, >+ /* 5336 */ 'a', 'n', 'd', 'i', 9, 0, >+ /* 5342 */ 't', 'g', 'e', 'i', 9, 0, >+ /* 5348 */ 's', 'n', 'e', 'i', 9, 0, >+ /* 5354 */ 't', 'n', 'e', 'i', 9, 0, >+ /* 5360 */ 'd', 'a', 'h', 'i', 9, 0, >+ /* 5366 */ 'm', 'f', 'h', 'i', 9, 0, >+ /* 5372 */ 'm', 't', 'h', 'i', 9, 0, >+ /* 5378 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0, >+ /* 5392 */ 'd', 'l', 'i', 9, 0, >+ /* 5397 */ 'c', 'm', 'p', 'i', 9, 0, >+ /* 5403 */ 's', 'e', 'q', 'i', 9, 0, >+ /* 5409 */ 't', 'e', 'q', 'i', 9, 0, >+ /* 5415 */ 'x', 'o', 'r', 'i', 9, 0, >+ /* 5421 */ 'd', 'a', 't', 'i', 9, 0, >+ /* 5427 */ 's', 'l', 't', 'i', 9, 0, >+ /* 5433 */ 't', 'l', 't', 'i', 9, 0, >+ /* 5439 */ 'd', 'a', 'u', 'i', 9, 0, >+ /* 5445 */ 'l', 'u', 'i', 9, 0, >+ /* 5450 */ 'j', 9, 0, >+ /* 5453 */ 'b', 'r', 'e', 'a', 'k', 9, 0, >+ /* 5460 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, >+ /* 5469 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, >+ /* 5478 */ 'b', 'a', 'l', 9, 0, >+ /* 5483 */ 'j', 'a', 'l', 9, 0, >+ /* 5488 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0, >+ /* 5496 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0, >+ /* 5504 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5516 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5528 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5544 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5559 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0, >+ /* 5575 */ 'l', 'd', 'l', 9, 0, >+ /* 5580 */ 's', 'd', 'l', 9, 0, >+ /* 5585 */ 'b', 'n', 'e', 'l', 9, 0, >+ /* 5591 */ 'b', 'c', '0', 'f', 'l', 9, 0, >+ /* 5598 */ 'b', 'c', '1', 'f', 'l', 9, 0, >+ /* 5605 */ 'b', 'c', '2', 'f', 'l', 9, 0, >+ /* 5612 */ 'b', 'c', '3', 'f', 'l', 9, 0, >+ /* 5619 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5633 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5647 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5660 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0, >+ /* 5675 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0, >+ /* 5684 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0, >+ /* 5693 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0, >+ /* 5702 */ 'd', 's', 'l', 'l', 9, 0, >+ /* 5708 */ 'b', 'e', 'q', 'l', 9, 0, >+ /* 5714 */ 'd', 's', 'r', 'l', 9, 0, >+ /* 5720 */ 'b', 'c', '0', 't', 'l', 9, 0, >+ /* 5727 */ 'b', 'c', '1', 't', 'l', 9, 0, >+ /* 5734 */ 'b', 'c', '2', 't', 'l', 9, 0, >+ /* 5741 */ 'b', 'c', '3', 't', 'l', 9, 0, >+ /* 5748 */ 'd', 'm', 'u', 'l', 9, 0, >+ /* 5754 */ 'l', 'w', 'l', 9, 0, >+ /* 5759 */ 's', 'w', 'l', 9, 0, >+ /* 5764 */ 'b', 'g', 'e', 'z', 'l', 9, 0, >+ /* 5771 */ 'b', 'l', 'e', 'z', 'l', 9, 0, >+ /* 5778 */ 'b', 'g', 't', 'z', 'l', 9, 0, >+ /* 5785 */ 'b', 'l', 't', 'z', 'l', 9, 0, >+ /* 5792 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0, >+ /* 5800 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0, >+ /* 5808 */ 'm', 'o', 'v', 'n', 9, 0, >+ /* 5814 */ 'd', 'c', 'l', 'o', 9, 0, >+ /* 5820 */ 'm', 'f', 'l', 'o', 9, 0, >+ /* 5826 */ 's', 'h', 'i', 'l', 'o', 9, 0, >+ /* 5833 */ 'm', 't', 'l', 'o', 9, 0, >+ /* 5839 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0, >+ /* 5849 */ 's', 'd', 'b', 'b', 'p', 9, 0, >+ /* 5856 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0, >+ /* 5864 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0, >+ /* 5872 */ 'c', 'm', 'p', 9, 0, >+ /* 5877 */ 'd', 'p', 'o', 'p', 9, 0, >+ /* 5883 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, >+ /* 5899 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0, >+ /* 5916 */ 'r', 'd', 'd', 's', 'p', 9, 0, >+ /* 5923 */ 'w', 'r', 'd', 's', 'p', 9, 0, >+ /* 5930 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0, >+ /* 5941 */ 'e', 'x', 't', 'p', 9, 0, >+ /* 5947 */ 'b', 'e', 'q', 9, 0, >+ /* 5952 */ 's', 'e', 'q', 9, 0, >+ /* 5957 */ 't', 'e', 'q', 9, 0, >+ /* 5962 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 5974 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 5986 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6002 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6017 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0, >+ /* 6033 */ 'l', 'd', 'r', 9, 0, >+ /* 6038 */ 's', 'd', 'r', 9, 0, >+ /* 6043 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6057 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6071 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6084 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0, >+ /* 6099 */ 'j', 'r', 9, 0, >+ /* 6103 */ 'j', 'a', 'l', 'r', 9, 0, >+ /* 6109 */ 'n', 'o', 'r', 9, 0, >+ /* 6114 */ 'x', 'o', 'r', 9, 0, >+ /* 6119 */ 'd', 'r', 'o', 't', 'r', 9, 0, >+ /* 6126 */ 'r', 'd', 'h', 'w', 'r', 9, 0, >+ /* 6133 */ 'l', 'w', 'r', 9, 0, >+ /* 6138 */ 's', 'w', 'r', 9, 0, >+ /* 6143 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0, >+ /* 6151 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0, >+ /* 6159 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, >+ /* 6168 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, >+ /* 6177 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, >+ /* 6186 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0, >+ /* 6195 */ 'c', '.', 'l', 'e', '.', 's', 9, 0, >+ /* 6203 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0, >+ /* 6213 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0, >+ /* 6223 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0, >+ /* 6232 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0, >+ /* 6243 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6252 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6263 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0, >+ /* 6275 */ 'c', '.', 'f', '.', 's', 9, 0, >+ /* 6282 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0, >+ /* 6292 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0, >+ /* 6303 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0, >+ /* 6312 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0, >+ /* 6321 */ 'c', '.', 's', 'f', '.', 's', 9, 0, >+ /* 6329 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0, >+ /* 6337 */ 'n', 'e', 'g', '.', 's', 9, 0, >+ /* 6344 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0, >+ /* 6355 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0, >+ /* 6366 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0, >+ /* 6376 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0, >+ /* 6387 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, >+ /* 6396 */ 's', 'e', 'l', '.', 's', 9, 0, >+ /* 6403 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0, >+ /* 6412 */ 'm', 'u', 'l', '.', 's', 9, 0, >+ /* 6419 */ 'm', 'i', 'n', '.', 's', 9, 0, >+ /* 6426 */ 'c', '.', 'u', 'n', '.', 's', 9, 0, >+ /* 6434 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0, >+ /* 6444 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0, >+ /* 6455 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0, >+ /* 6463 */ 'c', '.', 'e', 'q', '.', 's', 9, 0, >+ /* 6471 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0, >+ /* 6481 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0, >+ /* 6490 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0, >+ /* 6501 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6510 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6521 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0, >+ /* 6533 */ 'a', 'b', 's', '.', 's', 9, 0, >+ /* 6540 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, >+ /* 6549 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0, >+ /* 6558 */ 'c', '.', 'l', 't', '.', 's', 9, 0, >+ /* 6566 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0, >+ /* 6576 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0, >+ /* 6585 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0, >+ /* 6596 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6605 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6616 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0, >+ /* 6628 */ 'r', 'i', 'n', 't', '.', 's', 9, 0, >+ /* 6636 */ 's', 'q', 'r', 't', '.', 's', 9, 0, >+ /* 6644 */ 'm', 'o', 'v', 't', '.', 's', 9, 0, >+ /* 6652 */ 'd', 'i', 'v', '.', 's', 9, 0, >+ /* 6659 */ 'm', 'o', 'v', '.', 's', 9, 0, >+ /* 6666 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0, >+ /* 6677 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0, >+ /* 6688 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0, >+ /* 6698 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0, >+ /* 6709 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, >+ /* 6718 */ 'm', 'a', 'x', '.', 's', 9, 0, >+ /* 6725 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0, >+ /* 6735 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0, >+ /* 6745 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0, >+ /* 6753 */ 'j', 'a', 'l', 's', 9, 0, >+ /* 6759 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0, >+ /* 6768 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0, >+ /* 6777 */ 'j', 'a', 'l', 'r', 's', 9, 0, >+ /* 6784 */ 'b', 'c', '0', 't', 9, 0, >+ /* 6790 */ 'b', 'c', '1', 't', 9, 0, >+ /* 6796 */ 'b', 'c', '2', 't', 9, 0, >+ /* 6802 */ 'b', 'c', '3', 't', 9, 0, >+ /* 6808 */ 'w', 'a', 'i', 't', 9, 0, >+ /* 6814 */ 's', 'l', 't', 9, 0, >+ /* 6819 */ 't', 'l', 't', 9, 0, >+ /* 6824 */ 'd', 'm', 'u', 'l', 't', 9, 0, >+ /* 6831 */ 'n', 'o', 't', 9, 0, >+ /* 6836 */ 'm', 'o', 'v', 't', 9, 0, >+ /* 6842 */ 'l', 'b', 'u', 9, 0, >+ /* 6847 */ 'd', 's', 'u', 'b', 'u', 9, 0, >+ /* 6854 */ 'm', 's', 'u', 'b', 'u', 9, 0, >+ /* 6861 */ 'b', 'a', 'd', 'd', 'u', 9, 0, >+ /* 6868 */ 'd', 'a', 'd', 'd', 'u', 9, 0, >+ /* 6875 */ 'm', 'a', 'd', 'd', 'u', 9, 0, >+ /* 6882 */ 'd', 'm', 'o', 'd', 'u', 9, 0, >+ /* 6889 */ 't', 'g', 'e', 'u', 9, 0, >+ /* 6895 */ 'l', 'h', 'u', 9, 0, >+ /* 6900 */ 'd', 'm', 'u', 'h', 'u', 9, 0, >+ /* 6907 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0, >+ /* 6915 */ 't', 'g', 'e', 'i', 'u', 9, 0, >+ /* 6922 */ 's', 'l', 't', 'i', 'u', 9, 0, >+ /* 6929 */ 't', 'l', 't', 'i', 'u', 9, 0, >+ /* 6936 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0, >+ /* 6944 */ 'd', 'm', 'u', 'l', 'u', 9, 0, >+ /* 6951 */ 'v', 'm', 'u', 'l', 'u', 9, 0, >+ /* 6958 */ 's', 'l', 't', 'u', 9, 0, >+ /* 6964 */ 't', 'l', 't', 'u', 9, 0, >+ /* 6970 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0, >+ /* 6978 */ 'd', 'd', 'i', 'v', 'u', 9, 0, >+ /* 6985 */ 'l', 'w', 'u', 9, 0, >+ /* 6990 */ 'a', 'n', 'd', '.', 'v', 9, 0, >+ /* 6997 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0, >+ /* 7005 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0, >+ /* 7013 */ 'n', 'o', 'r', '.', 'v', 9, 0, >+ /* 7020 */ 'x', 'o', 'r', '.', 'v', 9, 0, >+ /* 7027 */ 'b', 'z', '.', 'v', 9, 0, >+ /* 7033 */ 'b', 'm', 'z', '.', 'v', 9, 0, >+ /* 7040 */ 'b', 'n', 'z', '.', 'v', 9, 0, >+ /* 7047 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0, >+ /* 7055 */ 'd', 's', 'r', 'a', 'v', 9, 0, >+ /* 7062 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0, >+ /* 7070 */ 'd', 'd', 'i', 'v', 9, 0, >+ /* 7076 */ 'd', 's', 'l', 'l', 'v', 9, 0, >+ /* 7083 */ 'd', 's', 'r', 'l', 'v', 9, 0, >+ /* 7090 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0, >+ /* 7098 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0, >+ /* 7107 */ 'e', 'x', 't', 'p', 'v', 9, 0, >+ /* 7114 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0, >+ /* 7122 */ 'i', 'n', 's', 'v', 9, 0, >+ /* 7128 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0, >+ /* 7137 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0, >+ /* 7146 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0, >+ /* 7155 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0, >+ /* 7165 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0, >+ /* 7175 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0, >+ /* 7185 */ 's', 'r', 'a', '.', 'w', 9, 0, >+ /* 7192 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0, >+ /* 7200 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0, >+ /* 7209 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0, >+ /* 7217 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0, >+ /* 7225 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, >+ /* 7234 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0, >+ /* 7242 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0, >+ /* 7251 */ 's', 'l', 'd', '.', 'w', 9, 0, >+ /* 7258 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0, >+ /* 7267 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0, >+ /* 7276 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0, >+ /* 7284 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0, >+ /* 7292 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0, >+ /* 7301 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0, >+ /* 7310 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0, >+ /* 7318 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0, >+ /* 7326 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0, >+ /* 7335 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0, >+ /* 7344 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0, >+ /* 7353 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0, >+ /* 7361 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0, >+ /* 7369 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0, >+ /* 7377 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0, >+ /* 7385 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7401 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7414 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7432 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0, >+ /* 7448 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0, >+ /* 7457 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0, >+ /* 7466 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0, >+ /* 7474 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0, >+ /* 7482 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0, >+ /* 7491 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0, >+ /* 7499 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0, >+ /* 7507 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0, >+ /* 7517 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0, >+ /* 7525 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0, >+ /* 7534 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0, >+ /* 7543 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0, >+ /* 7552 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0, >+ /* 7562 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0, >+ /* 7572 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0, >+ /* 7581 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0, >+ /* 7590 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0, >+ /* 7599 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, >+ /* 7612 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0, >+ /* 7625 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0, >+ /* 7633 */ 's', 'l', 'l', '.', 'w', 9, 0, >+ /* 7640 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0, >+ /* 7650 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0, >+ /* 7658 */ 's', 'r', 'l', '.', 'w', 9, 0, >+ /* 7665 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0, >+ /* 7674 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0, >+ /* 7682 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0, >+ /* 7690 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0, >+ /* 7698 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0, >+ /* 7706 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0, >+ /* 7714 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0, >+ /* 7723 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0, >+ /* 7731 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0, >+ /* 7741 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0, >+ /* 7751 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0, >+ /* 7760 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 7771 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 7782 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0, >+ /* 7792 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0, >+ /* 7800 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0, >+ /* 7808 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0, >+ /* 7817 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0, >+ /* 7826 */ 'f', 't', 'q', '.', 'w', 9, 0, >+ /* 7833 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0, >+ /* 7843 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0, >+ /* 7854 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0, >+ /* 7865 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0, >+ /* 7875 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0, >+ /* 7886 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0, >+ /* 7897 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0, >+ /* 7905 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0, >+ /* 7913 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0, >+ /* 7921 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0, >+ /* 7929 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0, >+ /* 7937 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0, >+ /* 7947 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0, >+ /* 7955 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0, >+ /* 7964 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0, >+ /* 7972 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0, >+ /* 7980 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, >+ /* 7989 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 7999 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 8009 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0, >+ /* 8020 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0, >+ /* 8032 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8042 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8053 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0, >+ /* 8062 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0, >+ /* 8071 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0, >+ /* 8080 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8090 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8100 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8110 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0, >+ /* 8120 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0, >+ /* 8130 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0, >+ /* 8139 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0, >+ /* 8149 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8159 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8169 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8179 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0, >+ /* 8189 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0, >+ /* 8199 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0, >+ /* 8209 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0, >+ /* 8219 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8228 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8237 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8248 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0, >+ /* 8259 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0, >+ /* 8271 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0, >+ /* 8280 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0, >+ /* 8291 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0, >+ /* 8300 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0, >+ /* 8310 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8321 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8332 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0, >+ /* 8344 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0, >+ /* 8354 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0, >+ /* 8363 */ 'b', 's', 'e', 't', '.', 'w', 9, 0, >+ /* 8371 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0, >+ /* 8379 */ 'f', 's', 'l', 't', '.', 'w', 9, 0, >+ /* 8387 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0, >+ /* 8396 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0, >+ /* 8405 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0, >+ /* 8413 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0, >+ /* 8422 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0, >+ /* 8432 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0, >+ /* 8441 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0, >+ /* 8451 */ 's', 't', '.', 'w', 9, 0, >+ /* 8457 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8467 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8477 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0, >+ /* 8488 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0, >+ /* 8500 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8510 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8521 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0, >+ /* 8530 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0, >+ /* 8539 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0, >+ /* 8548 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8558 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8568 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8578 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0, >+ /* 8588 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0, >+ /* 8597 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0, >+ /* 8607 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0, >+ /* 8617 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8627 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8637 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0, >+ /* 8649 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8658 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8667 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8678 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0, >+ /* 8689 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0, >+ /* 8698 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0, >+ /* 8707 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0, >+ /* 8717 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0, >+ /* 8726 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0, >+ /* 8735 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0, >+ /* 8744 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0, >+ /* 8753 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0, >+ /* 8761 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0, >+ /* 8769 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0, >+ /* 8778 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0, >+ /* 8786 */ 'b', 'z', '.', 'w', 9, 0, >+ /* 8792 */ 'b', 'n', 'z', '.', 'w', 9, 0, >+ /* 8799 */ 'l', 'w', 9, 0, >+ /* 8803 */ 's', 'w', 9, 0, >+ /* 8807 */ 'l', 'h', 'x', 9, 0, >+ /* 8812 */ 'j', 'a', 'l', 'x', 9, 0, >+ /* 8818 */ 'l', 'b', 'u', 'x', 9, 0, >+ /* 8824 */ 'l', 'w', 'x', 9, 0, >+ /* 8829 */ 'b', 'g', 'e', 'z', 9, 0, >+ /* 8835 */ 'b', 'l', 'e', 'z', 9, 0, >+ /* 8841 */ 'b', 'n', 'e', 'z', 9, 0, >+ /* 8847 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0, >+ /* 8855 */ 'b', 't', 'n', 'e', 'z', 9, 0, >+ /* 8862 */ 'd', 'c', 'l', 'z', 9, 0, >+ /* 8868 */ 'b', 'e', 'q', 'z', 9, 0, >+ /* 8874 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0, >+ /* 8882 */ 'b', 't', 'e', 'q', 'z', 9, 0, >+ /* 8889 */ 'b', 'g', 't', 'z', 9, 0, >+ /* 8895 */ 'b', 'l', 't', 'z', 9, 0, >+ /* 8901 */ 'm', 'o', 'v', 'z', 9, 0, >+ /* 8907 */ 's', 'e', 'b', 9, 32, 0, >+ /* 8913 */ 'j', 'r', 'c', 9, 32, 0, >+ /* 8919 */ 's', 'e', 'h', 9, 32, 0, >+ /* 8925 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, >+ /* 8939 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0, >+ /* 8952 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0, >+ /* 8964 */ 'c', 'i', 'n', 's', '3', '2', 32, 0, >+ /* 8972 */ 'e', 'x', 't', 's', '3', '2', 32, 0, >+ /* 8980 */ 's', 'y', 'n', 'c', 32, 0, >+ /* 8986 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0, >+ /* 8994 */ 'd', 'i', 'n', 's', 'm', 32, 0, >+ /* 9001 */ 'd', 'e', 'x', 't', 'm', 32, 0, >+ /* 9008 */ 'c', 'i', 'n', 's', 32, 0, >+ /* 9014 */ 'd', 'i', 'n', 's', 32, 0, >+ /* 9020 */ 'e', 'x', 't', 's', 32, 0, >+ /* 9026 */ 'd', 'e', 'x', 't', 32, 0, >+ /* 9032 */ 'd', 'i', 'n', 's', 'u', 32, 0, >+ /* 9039 */ 'd', 'e', 'x', 't', 'u', 32, 0, >+ /* 9046 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0, >+ /* 9054 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0, >+ /* 9062 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0, >+ /* 9070 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0, >+ /* 9078 */ 'c', '.', 0, >+ /* 9081 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0, >+ /* 9089 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 9102 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 9109 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 9119 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 9134 */ 'j', 'r', 'c', 9, 32, '$', 'r', 'a', 0, >+ /* 9143 */ 'j', 'r', 9, 32, '$', 'r', 'a', 0, >+ /* 9151 */ 'e', 'h', 'b', 0, >+ /* 9155 */ 'p', 'a', 'u', 's', 'e', 0, >+ /* 9161 */ 't', 'l', 'b', 'w', 'i', 0, >+ /* 9167 */ 'f', 'o', 'o', 0, >+ /* 9171 */ 't', 'l', 'b', 'p', 0, >+ /* 9176 */ 's', 's', 'n', 'o', 'p', 0, >+ /* 9182 */ 't', 'l', 'b', 'r', 0, >+ /* 9187 */ 't', 'l', 'b', 'w', 'r', 0, >+ /* 9193 */ 'd', 'e', 'r', 'e', 't', 0, >+ /* 9199 */ 'w', 'a', 'i', 't', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; >+ uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 16383)-1); >+#endif >+ >+ >+ // Fragment 0 encoded into 3 bits for 7 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 7); >+ switch ((Bits >> 14) & 7) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN... >+ return; >+ break; >+ case 1: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDQH_PH, ADDQH_R_PH, AD... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // CACHE, CACHE_R6, PREF, PREF_R6 >+ printUnsignedImm(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printMemOperand(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, M... >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM >+ printFCCOperand(MI, 2, O); >+ break; >+ case 5: >+ // MTHC1_D32, MTHC1_D64 >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 6: >+ // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ... >+ printOperand(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 4 bits for 15 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 17) & 15); >+ switch ((Bits >> 17) & 15) { >+ default: // unreachable. >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDQH_PH, ADDQH_R_PH, AD... >+ SStream_concat0(O, ", "); >+ break; >+ case 1: >+ // AddiuRxPcImmX16 >+ SStream_concat0(O, ", $pc, "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 2: >+ // AddiuSpImm16, Bimm16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 3: >+ // AddiuSpImmX16, BAL, BALC, BC, BPOSGE32, BimmX16, BteqzX16, BtnezX16, C... >+ return; >+ break; >+ case 4: >+ // Bteqz16, Btnez16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 5: >+ // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_MM, MTHI_DSP, MTHLIP, MTLO_... >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 6: >+ // DAHI, DATI, MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, ... >+ printOperand(MI, 2, O); >+ break; >+ case 7: >+ // FCMP_D32, FCMP_D32_MM, FCMP_D64 >+ SStream_concat0(O, ".d\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // FCMP_S32, FCMP_S32_MM >+ SStream_concat0(O, ".s\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 9: >+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS... >+ SStream_concat0(O, "["); >+ break; >+ case 10: >+ // Jal16 >+ SStream_concat0(O, "\n\tnop"); >+ return; >+ break; >+ case 11: >+ // JalB16 >+ SStream_concat0(O, "\t# branch\n\tnop"); >+ return; >+ break; >+ case 12: >+ // LwConstant32 >+ SStream_concat0(O, ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t"); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "\n2:"); >+ return; >+ break; >+ case 13: >+ // SC, SCD, SCD_R6, SC_MM, SC_R6 >+ printMemOperand(MI, 2, O); >+ return; >+ break; >+ case 14: >+ // SelBeqZ, SelBneZ >+ SStream_concat0(O, ", .+4\n\t\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 4 bits for 11 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 21) & 15); >+ switch ((Bits >> 21) & 15) { >+ default: // unreachable. >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDQH_PH, ADDQH_R_PH, AD... >+ printOperand(MI, 1, O); >+ break; >+ case 1: >+ // AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B, BINSLI_D, BINS... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM >+ printMemOperandEA(MI, 1, O); >+ return; >+ break; >+ case 3: >+ // DAHI, DATI >+ return; >+ break; >+ case 4: >+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W >+ printUnsignedImm(MI, 3, O); >+ SStream_concat0(O, "], "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 5: >+ // INSVE_B, INSVE_D, INSVE_H, INSVE_W >+ printUnsignedImm(MI, 2, O); >+ SStream_concat0(O, "], "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "["); >+ printUnsignedImm(MI, 4, O); >+ SStream_concat0(O, "]"); >+ return; >+ break; >+ case 6: >+ // LB, LB64, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_MM, LDC2, ... >+ printMemOperand(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // LUi, LUi64, LUi_MM, LoadAddr32Imm, LoadImm32Reg, RDDSP, REPL_PH, REPL_... >+ printUnsignedImm(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // MultRxRyRz16, MultuRxRyRz16 >+ SStream_concat0(O, "\n\tmflo\t"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... >+ printOperand(MI, 4, O); >+ break; >+ case 10: >+ // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz... >+ SStream_concat0(O, "\n\tmove\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", $t8"); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 4 bits for 15 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 25) & 15); >+ switch ((Bits >> 25) & 15) { >+ default: // unreachable. >+ case 0: >+ // ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ALUIPC, AUIPC, AddiuRxImmX16,... >+ return; >+ break; >+ case 1: >+ // ADD, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, ADDQ_S_PH, ADD... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // AddiuRxRxImm16, LwRxPcTcp16 >+ SStream_concat0(O, "\t# 16 bit inst"); >+ return; >+ break; >+ case 3: >+ // BeqzRxImm16, BnezRxImm16 >+ SStream_concat0(O, " # 16 bit inst"); >+ return; >+ break; >+ case 4: >+ // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S... >+ SStream_concat0(O, "\n\tbteqz\t"); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 5: >+ // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S... >+ SStream_concat0(O, "\n\tbtnez\t"); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... >+ SStream_concat0(O, "["); >+ break; >+ case 7: >+ // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16 >+ SStream_concat0(O, " \t# 16 bit inst"); >+ return; >+ break; >+ case 8: >+ // DSLL64_32 >+ SStream_concat0(O, ", 32"); >+ return; >+ break; >+ case 9: >+ // GotPrologue16 >+ SStream_concat0(O, "\n\taddiu\t"); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", $pc, "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "\n "); >+ return; >+ break; >+ case 10: >+ // LBUX, LDXC1, LDXC164, LHX, LUXC1, LUXC164, LUXC1_MM, LWX, LWXC1, LWXC1... >+ SStream_concat0(O, "("); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ")"); >+ return; >+ break; >+ case 11: >+ // LwRxSpImmX16, SwRxSpImmX16 >+ SStream_concat0(O, " ( "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, " ); "); >+ return; >+ break; >+ case 12: >+ // SLL64_32, SLL64_64 >+ SStream_concat0(O, ", 0"); >+ return; >+ break; >+ case 13: >+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt... >+ SStream_concat0(O, "\n\tbteqz\t.+4\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 14: >+ // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt... >+ SStream_concat0(O, "\n\tbtnez\t.+4\n\tmove "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 3 bits for 5 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 29) & 7); >+ switch ((Bits >> 29) & 7) { >+ default: // unreachable. >+ case 0: >+ // ADD, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, ADDQ_S_PH, ADD... >+ printOperand(MI, 2, O); >+ break; >+ case 1: >+ // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,... >+ printUnsignedImm8(MI, 2, O); >+ break; >+ case 2: >+ // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT... >+ printUnsignedImm(MI, 2, O); >+ break; >+ case 3: >+ // BINSLI_B, BINSLI_D, BINSLI_H, BINSLI_W, BINSRI_B, BINSRI_D, BINSRI_H, ... >+ printUnsignedImm8(MI, 3, O); >+ break; >+ case 4: >+ // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W... >+ printOperand(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 2 bits for 3 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 32) & 3); >+ switch ((Bits >> 32) & 3) { >+ default: // unreachable. >+ case 0: >+ // ADD, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, ADDQ_S_PH, ADD... >+ return; >+ break; >+ case 1: >+ // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_D, COPY_U_H, ... >+ SStream_concat0(O, "]"); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 34) & 1); >+ if ((Bits >> 34) & 1) { >+ // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD... >+ printOperand(MI, 3, O); >+ return; >+ } else { >+ // ALIGN, CINS, CINS32, DALIGN, DLSA, DLSA_R6, EXTS, EXTS32, LSA, LSA_R6 >+ printUnsignedImm(MI, 3, O); >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 394 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'f', '1', '0', 0, >+ /* 4 */ 'w', '1', '0', 0, >+ /* 8 */ 'f', '2', '0', 0, >+ /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, >+ /* 25 */ 'w', '2', '0', 0, >+ /* 29 */ 'f', '3', '0', 0, >+ /* 33 */ 'w', '3', '0', 0, >+ /* 37 */ 'a', '0', 0, >+ /* 40 */ 'a', 'c', '0', 0, >+ /* 44 */ 'f', 'c', 'c', '0', 0, >+ /* 49 */ 'f', '0', 0, >+ /* 52 */ 'k', '0', 0, >+ /* 55 */ 'm', 'p', 'l', '0', 0, >+ /* 60 */ 'p', '0', 0, >+ /* 63 */ 's', '0', 0, >+ /* 66 */ 't', '0', 0, >+ /* 69 */ 'v', '0', 0, >+ /* 72 */ 'w', '0', 0, >+ /* 75 */ 'f', '1', '1', 0, >+ /* 79 */ 'w', '1', '1', 0, >+ /* 83 */ 'f', '2', '1', 0, >+ /* 87 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, >+ /* 100 */ 'w', '2', '1', 0, >+ /* 104 */ 'f', '3', '1', 0, >+ /* 108 */ 'w', '3', '1', 0, >+ /* 112 */ 'a', '1', 0, >+ /* 115 */ 'a', 'c', '1', 0, >+ /* 119 */ 'f', 'c', 'c', '1', 0, >+ /* 124 */ 'f', '1', 0, >+ /* 127 */ 'k', '1', 0, >+ /* 130 */ 'm', 'p', 'l', '1', 0, >+ /* 135 */ 'p', '1', 0, >+ /* 138 */ 's', '1', 0, >+ /* 141 */ 't', '1', 0, >+ /* 144 */ 'v', '1', 0, >+ /* 147 */ 'w', '1', 0, >+ /* 150 */ 'f', '1', '2', 0, >+ /* 154 */ 'w', '1', '2', 0, >+ /* 158 */ 'f', '2', '2', 0, >+ /* 162 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, >+ /* 175 */ 'w', '2', '2', 0, >+ /* 179 */ 'a', '2', 0, >+ /* 182 */ 'a', 'c', '2', 0, >+ /* 186 */ 'f', 'c', 'c', '2', 0, >+ /* 191 */ 'f', '2', 0, >+ /* 194 */ 'm', 'p', 'l', '2', 0, >+ /* 199 */ 'p', '2', 0, >+ /* 202 */ 's', '2', 0, >+ /* 205 */ 't', '2', 0, >+ /* 208 */ 'w', '2', 0, >+ /* 211 */ 'f', '1', '3', 0, >+ /* 215 */ 'w', '1', '3', 0, >+ /* 219 */ 'f', '2', '3', 0, >+ /* 223 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, >+ /* 236 */ 'w', '2', '3', 0, >+ /* 240 */ 'a', '3', 0, >+ /* 243 */ 'a', 'c', '3', 0, >+ /* 247 */ 'f', 'c', 'c', '3', 0, >+ /* 252 */ 'f', '3', 0, >+ /* 255 */ 's', '3', 0, >+ /* 258 */ 't', '3', 0, >+ /* 261 */ 'w', '3', 0, >+ /* 264 */ 'f', '1', '4', 0, >+ /* 268 */ 'w', '1', '4', 0, >+ /* 272 */ 'f', '2', '4', 0, >+ /* 276 */ 'w', '2', '4', 0, >+ /* 280 */ 'f', 'c', 'c', '4', 0, >+ /* 285 */ 'f', '4', 0, >+ /* 288 */ 's', '4', 0, >+ /* 291 */ 't', '4', 0, >+ /* 294 */ 'w', '4', 0, >+ /* 297 */ 'f', '1', '5', 0, >+ /* 301 */ 'w', '1', '5', 0, >+ /* 305 */ 'f', '2', '5', 0, >+ /* 309 */ 'w', '2', '5', 0, >+ /* 313 */ 'f', 'c', 'c', '5', 0, >+ /* 318 */ 'f', '5', 0, >+ /* 321 */ 's', '5', 0, >+ /* 324 */ 't', '5', 0, >+ /* 327 */ 'w', '5', 0, >+ /* 330 */ 'f', '1', '6', 0, >+ /* 334 */ 'w', '1', '6', 0, >+ /* 338 */ 'f', '2', '6', 0, >+ /* 342 */ 'w', '2', '6', 0, >+ /* 346 */ 'f', 'c', 'c', '6', 0, >+ /* 351 */ 'f', '6', 0, >+ /* 354 */ 's', '6', 0, >+ /* 357 */ 't', '6', 0, >+ /* 360 */ 'w', '6', 0, >+ /* 363 */ 'f', '1', '7', 0, >+ /* 367 */ 'w', '1', '7', 0, >+ /* 371 */ 'f', '2', '7', 0, >+ /* 375 */ 'w', '2', '7', 0, >+ /* 379 */ 'f', 'c', 'c', '7', 0, >+ /* 384 */ 'f', '7', 0, >+ /* 387 */ 's', '7', 0, >+ /* 390 */ 't', '7', 0, >+ /* 393 */ 'w', '7', 0, >+ /* 396 */ 'f', '1', '8', 0, >+ /* 400 */ 'w', '1', '8', 0, >+ /* 404 */ 'f', '2', '8', 0, >+ /* 408 */ 'w', '2', '8', 0, >+ /* 412 */ 'f', '8', 0, >+ /* 415 */ 't', '8', 0, >+ /* 418 */ 'w', '8', 0, >+ /* 421 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, >+ /* 437 */ 'f', '1', '9', 0, >+ /* 441 */ 'w', '1', '9', 0, >+ /* 445 */ 'f', '2', '9', 0, >+ /* 449 */ 'w', '2', '9', 0, >+ /* 453 */ 'f', '9', 0, >+ /* 456 */ 't', '9', 0, >+ /* 459 */ 'w', '9', 0, >+ /* 462 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, >+ /* 469 */ 'r', 'a', 0, >+ /* 472 */ 'p', 'c', 0, >+ /* 475 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, >+ /* 484 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, >+ /* 495 */ 'h', 'i', 0, >+ /* 498 */ 'l', 'o', 0, >+ /* 501 */ 'z', 'e', 'r', 'o', 0, >+ /* 506 */ 'f', 'p', 0, >+ /* 509 */ 'g', 'p', 0, >+ /* 512 */ 's', 'p', 0, >+ /* 515 */ 'D', 'S', 'P', 'P', 'o', 's', 0, >+ /* 522 */ 'a', 't', 0, >+ /* 525 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, >+ /* 535 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 522, 475, 535, 462, 484, 515, 525, 506, 509, 152, 77, 2, 332, 266, >+ 299, 213, 365, 472, 469, 512, 501, 37, 112, 179, 240, 40, 115, 182, >+ 243, 522, 45, 120, 187, 248, 281, 314, 347, 380, 2, 77, 152, 213, >+ 266, 299, 332, 365, 398, 435, 2, 77, 152, 213, 266, 299, 332, 365, >+ 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, 9, 84, >+ 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 1, 76, 151, 212, >+ 265, 298, 331, 364, 397, 434, 9, 84, 159, 220, 273, 306, 339, 372, >+ 405, 446, 30, 105, 49, 191, 285, 351, 412, 0, 150, 264, 330, 396, >+ 8, 158, 272, 338, 404, 29, 12, 87, 162, 223, 49, 124, 191, 252, >+ 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, 297, 330, 363, >+ 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, 445, 29, 104, >+ 44, 119, 186, 247, 280, 313, 346, 379, 2, 77, 152, 213, 266, 299, >+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, >+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 506, 49, >+ 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, 264, >+ 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, 404, >+ 445, 29, 104, 509, 40, 115, 182, 243, 2, 77, 152, 213, 266, 299, >+ 332, 365, 398, 435, 1, 76, 151, 212, 265, 298, 331, 364, 397, 434, >+ 9, 84, 159, 220, 273, 306, 339, 372, 405, 446, 30, 105, 52, 127, >+ 40, 115, 182, 243, 55, 130, 194, 60, 135, 199, 469, 63, 138, 202, >+ 255, 288, 321, 354, 387, 512, 66, 141, 205, 258, 291, 324, 357, 390, >+ 415, 456, 69, 144, 72, 147, 208, 261, 294, 327, 360, 393, 418, 459, >+ 4, 79, 154, 215, 268, 301, 334, 367, 400, 441, 25, 100, 175, 236, >+ 276, 309, 342, 375, 408, 449, 33, 108, 501, 37, 112, 179, 240, 40, >+ 49, 124, 191, 252, 285, 318, 351, 384, 412, 453, 0, 75, 150, 211, >+ 264, 297, 330, 363, 396, 437, 8, 83, 158, 219, 272, 305, 338, 371, >+ 404, 445, 29, 104, 421, 495, 52, 127, 498, 63, 138, 202, 255, 288, >+ 321, 354, 387, 66, 141, 205, 258, 291, 324, 357, 390, 415, 456, 69, >+ 144, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case Mips_ADDu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) { >+ // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) >+ AsmString = "move $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0F CC0, brtarget:$offset) >+ AsmString = "bc0f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0FL CC0, brtarget:$offset) >+ AsmString = "bc0fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0T CC0, brtarget:$offset) >+ AsmString = "bc0t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC0TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC0TL CC0, brtarget:$offset) >+ AsmString = "bc0tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1F FCC0, brtarget:$offset) >+ AsmString = "bc1f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1FL FCC0, brtarget:$offset) >+ AsmString = "bc1fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1T FCC0, brtarget:$offset) >+ AsmString = "bc1t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC1TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) { >+ // (BC1TL FCC0, brtarget:$offset) >+ AsmString = "bc1tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2F CC0, brtarget:$offset) >+ AsmString = "bc2f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2FL CC0, brtarget:$offset) >+ AsmString = "bc2fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2T CC0, brtarget:$offset) >+ AsmString = "bc2t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC2TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC2TL CC0, brtarget:$offset) >+ AsmString = "bc2tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3F: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3F CC0, brtarget:$offset) >+ AsmString = "bc3f $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3FL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3FL CC0, brtarget:$offset) >+ AsmString = "bc3fl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3T: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3T CC0, brtarget:$offset) >+ AsmString = "bc3t $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BC3TL: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) { >+ // (BC3TL CC0, brtarget:$offset) >+ AsmString = "bc3tl $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_BREAK: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 && >+ MCOperand_isImm(MCInst_getOperand(MI, 1)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { >+ // (BREAK 0, 0) >+ AsmString = "break"; >+ break; >+ } >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_isImm(MCInst_getOperand(MI, 1)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) { >+ // (BREAK uimm10:$imm, 0) >+ AsmString = "break $\x01"; >+ break; >+ } >+ return NULL; >+ case Mips_DADDu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1) && >+ MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO_64) { >+ // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) >+ AsmString = "move $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_DI: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { >+ // (DI ZERO) >+ AsmString = "di"; >+ break; >+ } >+ return NULL; >+ case Mips_EI: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO) { >+ // (EI ZERO) >+ AsmString = "ei"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { >+ // (JALR ZERO, GPR32Opnd:$rs) >+ AsmString = "jr $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR64: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO_64 && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR64RegClassID, 1)) { >+ // (JALR64 ZERO_64, GPR64Opnd:$rs) >+ AsmString = "jr $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_JALR_HB: >+ if (MCInst_getNumOperands(MI) == 2 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_RA && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1)) { >+ // (JALR_HB RA, GPR32Opnd:$rs) >+ AsmString = "jalr.hb $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_SDBBP: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SDBBP 0) >+ AsmString = "sdbbp"; >+ break; >+ } >+ return NULL; >+ case Mips_SDBBP_R6: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SDBBP_R6 0) >+ AsmString = "sdbbp"; >+ break; >+ } >+ return NULL; >+ case Mips_SLL: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_ZERO && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (SLL ZERO, ZERO, 0) >+ AsmString = "nop"; >+ break; >+ } >+ return NULL; >+ case Mips_SUB: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { >+ // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) >+ AsmString = "neg $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case Mips_SUBu: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_getReg(MCInst_getOperand(MI, 1)) == Mips_ZERO && >+ MCOperand_isReg(MCInst_getOperand(MI, 2)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 2)) { >+ // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) >+ AsmString = "negu $\x01, $\x03"; >+ break; >+ } >+ return NULL; >+ case Mips_SYNC: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SYNC 0) >+ AsmString = "sync"; >+ break; >+ } >+ return NULL; >+ case Mips_SYSCALL: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (SYSCALL 0) >+ AsmString = "syscall"; >+ break; >+ } >+ return NULL; >+ case Mips_TEQ: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "teq $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TGE: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tge $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TGEU: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tgeu $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TLT: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tlt $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TLTU: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tltu $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_TNE: >+ if (MCInst_getNumOperands(MI) == 3 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 0) && >+ MCOperand_isReg(MCInst_getOperand(MI, 1)) && >+ GETREGCLASS_CONTAIN(Mips_GPR32RegClassID, 1) && >+ MCOperand_isImm(MCInst_getOperand(MI, 2)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { >+ // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) >+ AsmString = "tne $\x01, $\x02"; >+ break; >+ } >+ return NULL; >+ case Mips_WAIT_MM: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0) { >+ // (WAIT_MM 0) >+ AsmString = "wait"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..3679e450620b9fb09a2abdf1d847a201ff838be0 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenDisassemblerTables.inc >@@ -0,0 +1,6589 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * Mips Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#include "../../MCInst.h" >+#include "../../LEB128.h" >+ >+// Helper function for extracting fields from encoded instructions. >+#define FieldFromInstruction(fname, InsnType) \ >+static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ >+{ \ >+ InsnType fieldMask; \ >+ if (numBits == sizeof(InsnType)*8) \ >+ fieldMask = (InsnType)(-1LL); \ >+ else \ >+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ >+ return (insn & fieldMask) >> startBit; \ >+} >+ >+#if 0 >+// TODO: properly handle this in the future with MIPS1/2 modes >+static const uint8_t DecoderTableCOP3_32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15 >+/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51 >+/* 11 */ MCD_OPC_Decode, 189, 7, 10, // Opcode: LWC3 >+/* 15 */ MCD_OPC_FilterValue, 55, 8, 0, // Skip to: 27 >+/* 19 */ MCD_OPC_CheckPredicate, 2, 28, 0, // Skip to: 51 >+/* 23 */ MCD_OPC_Decode, 139, 7, 10, // Opcode: LDC3 >+/* 27 */ MCD_OPC_FilterValue, 59, 8, 0, // Skip to: 39 >+/* 31 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 51 >+/* 35 */ MCD_OPC_Decode, 174, 12, 10, // Opcode: SWC3 >+/* 39 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 51 >+/* 43 */ MCD_OPC_CheckPredicate, 2, 4, 0, // Skip to: 51 >+/* 47 */ MCD_OPC_Decode, 227, 10, 10, // Opcode: SDC3 >+/* 51 */ MCD_OPC_Fail, >+ 0 >+}; >+#endif >+ >+static const uint8_t DecoderTableMicroMips32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 114, 3, // Skip to: 889 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 65 >+/* 14 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 29 >+/* 21 */ MCD_OPC_CheckPredicate, 3, 156, 5, // Skip to: 1461 >+/* 25 */ MCD_OPC_Decode, 174, 11, 14, // Opcode: SLL_MM >+/* 29 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 41 >+/* 33 */ MCD_OPC_CheckPredicate, 3, 144, 5, // Skip to: 1461 >+/* 37 */ MCD_OPC_Decode, 241, 11, 14, // Opcode: SRL_MM >+/* 41 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 53 >+/* 45 */ MCD_OPC_CheckPredicate, 3, 132, 5, // Skip to: 1461 >+/* 49 */ MCD_OPC_Decode, 221, 11, 14, // Opcode: SRA_MM >+/* 53 */ MCD_OPC_FilterValue, 3, 124, 5, // Skip to: 1461 >+/* 57 */ MCD_OPC_CheckPredicate, 3, 120, 5, // Skip to: 1461 >+/* 61 */ MCD_OPC_Decode, 191, 10, 14, // Opcode: ROTR_MM >+/* 65 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 77 >+/* 69 */ MCD_OPC_CheckPredicate, 3, 108, 5, // Skip to: 1461 >+/* 73 */ MCD_OPC_Decode, 155, 2, 15, // Opcode: BREAK_MM >+/* 77 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 89 >+/* 81 */ MCD_OPC_CheckPredicate, 3, 96, 5, // Skip to: 1461 >+/* 85 */ MCD_OPC_Decode, 225, 6, 16, // Opcode: INS_MM >+/* 89 */ MCD_OPC_FilterValue, 16, 180, 0, // Skip to: 273 >+/* 93 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 96 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 108 >+/* 100 */ MCD_OPC_CheckPredicate, 3, 77, 5, // Skip to: 1461 >+/* 104 */ MCD_OPC_Decode, 170, 11, 17, // Opcode: SLLV_MM >+/* 108 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 120 >+/* 112 */ MCD_OPC_CheckPredicate, 3, 65, 5, // Skip to: 1461 >+/* 116 */ MCD_OPC_Decode, 237, 11, 17, // Opcode: SRLV_MM >+/* 120 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 132 >+/* 124 */ MCD_OPC_CheckPredicate, 3, 53, 5, // Skip to: 1461 >+/* 128 */ MCD_OPC_Decode, 217, 11, 17, // Opcode: SRAV_MM >+/* 132 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 144 >+/* 136 */ MCD_OPC_CheckPredicate, 3, 41, 5, // Skip to: 1461 >+/* 140 */ MCD_OPC_Decode, 190, 10, 17, // Opcode: ROTRV_MM >+/* 144 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 155 >+/* 148 */ MCD_OPC_CheckPredicate, 3, 29, 5, // Skip to: 1461 >+/* 152 */ MCD_OPC_Decode, 64, 18, // Opcode: ADD_MM >+/* 155 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 166 >+/* 159 */ MCD_OPC_CheckPredicate, 3, 18, 5, // Skip to: 1461 >+/* 163 */ MCD_OPC_Decode, 70, 18, // Opcode: ADDu_MM >+/* 166 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 178 >+/* 170 */ MCD_OPC_CheckPredicate, 3, 7, 5, // Skip to: 1461 >+/* 174 */ MCD_OPC_Decode, 162, 12, 18, // Opcode: SUB_MM >+/* 178 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 190 >+/* 182 */ MCD_OPC_CheckPredicate, 3, 251, 4, // Skip to: 1461 >+/* 186 */ MCD_OPC_Decode, 164, 12, 18, // Opcode: SUBu_MM >+/* 190 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 202 >+/* 194 */ MCD_OPC_CheckPredicate, 3, 239, 4, // Skip to: 1461 >+/* 198 */ MCD_OPC_Decode, 178, 9, 18, // Opcode: MUL_MM >+/* 202 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 213 >+/* 206 */ MCD_OPC_CheckPredicate, 3, 227, 4, // Skip to: 1461 >+/* 210 */ MCD_OPC_Decode, 78, 18, // Opcode: AND_MM >+/* 213 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 225 >+/* 217 */ MCD_OPC_CheckPredicate, 3, 216, 4, // Skip to: 1461 >+/* 221 */ MCD_OPC_Decode, 224, 9, 18, // Opcode: OR_MM >+/* 225 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 237 >+/* 229 */ MCD_OPC_CheckPredicate, 3, 204, 4, // Skip to: 1461 >+/* 233 */ MCD_OPC_Decode, 214, 9, 18, // Opcode: NOR_MM >+/* 237 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 249 >+/* 241 */ MCD_OPC_CheckPredicate, 3, 192, 4, // Skip to: 1461 >+/* 245 */ MCD_OPC_Decode, 165, 13, 18, // Opcode: XOR_MM >+/* 249 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 261 >+/* 253 */ MCD_OPC_CheckPredicate, 3, 180, 4, // Skip to: 1461 >+/* 257 */ MCD_OPC_Decode, 178, 11, 18, // Opcode: SLT_MM >+/* 261 */ MCD_OPC_FilterValue, 14, 172, 4, // Skip to: 1461 >+/* 265 */ MCD_OPC_CheckPredicate, 3, 168, 4, // Skip to: 1461 >+/* 269 */ MCD_OPC_Decode, 187, 11, 18, // Opcode: SLTu_MM >+/* 273 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 304 >+/* 277 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 280 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 292 >+/* 284 */ MCD_OPC_CheckPredicate, 3, 149, 4, // Skip to: 1461 >+/* 288 */ MCD_OPC_Decode, 214, 8, 19, // Opcode: MOVN_I_MM >+/* 292 */ MCD_OPC_FilterValue, 1, 141, 4, // Skip to: 1461 >+/* 296 */ MCD_OPC_CheckPredicate, 3, 137, 4, // Skip to: 1461 >+/* 300 */ MCD_OPC_Decode, 234, 8, 19, // Opcode: MOVZ_I_MM >+/* 304 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 316 >+/* 308 */ MCD_OPC_CheckPredicate, 3, 125, 4, // Skip to: 1461 >+/* 312 */ MCD_OPC_Decode, 139, 5, 20, // Opcode: EXT_MM >+/* 316 */ MCD_OPC_FilterValue, 60, 117, 4, // Skip to: 1461 >+/* 320 */ MCD_OPC_ExtractField, 6, 6, // Inst{11-6} ... >+/* 323 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 335 >+/* 327 */ MCD_OPC_CheckPredicate, 3, 106, 4, // Skip to: 1461 >+/* 331 */ MCD_OPC_Decode, 239, 12, 21, // Opcode: TEQ_MM >+/* 335 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 347 >+/* 339 */ MCD_OPC_CheckPredicate, 3, 94, 4, // Skip to: 1461 >+/* 343 */ MCD_OPC_Decode, 247, 12, 21, // Opcode: TGE_MM >+/* 347 */ MCD_OPC_FilterValue, 13, 123, 0, // Skip to: 474 >+/* 351 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 354 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 372 >+/* 358 */ MCD_OPC_CheckPredicate, 3, 75, 4, // Skip to: 1461 >+/* 362 */ MCD_OPC_CheckField, 16, 10, 0, 69, 4, // Skip to: 1461 >+/* 368 */ MCD_OPC_Decode, 249, 12, 0, // Opcode: TLBP_MM >+/* 372 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 390 >+/* 376 */ MCD_OPC_CheckPredicate, 3, 57, 4, // Skip to: 1461 >+/* 380 */ MCD_OPC_CheckField, 16, 10, 0, 51, 4, // Skip to: 1461 >+/* 386 */ MCD_OPC_Decode, 251, 12, 0, // Opcode: TLBR_MM >+/* 390 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 408 >+/* 394 */ MCD_OPC_CheckPredicate, 3, 39, 4, // Skip to: 1461 >+/* 398 */ MCD_OPC_CheckField, 16, 10, 0, 33, 4, // Skip to: 1461 >+/* 404 */ MCD_OPC_Decode, 253, 12, 0, // Opcode: TLBWI_MM >+/* 408 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 426 >+/* 412 */ MCD_OPC_CheckPredicate, 3, 21, 4, // Skip to: 1461 >+/* 416 */ MCD_OPC_CheckField, 16, 10, 0, 15, 4, // Skip to: 1461 >+/* 422 */ MCD_OPC_Decode, 255, 12, 0, // Opcode: TLBWR_MM >+/* 426 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 438 >+/* 430 */ MCD_OPC_CheckPredicate, 3, 3, 4, // Skip to: 1461 >+/* 434 */ MCD_OPC_Decode, 158, 13, 22, // Opcode: WAIT_MM >+/* 438 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 456 >+/* 442 */ MCD_OPC_CheckPredicate, 3, 247, 3, // Skip to: 1461 >+/* 446 */ MCD_OPC_CheckField, 16, 10, 0, 241, 3, // Skip to: 1461 >+/* 452 */ MCD_OPC_Decode, 155, 4, 0, // Opcode: DERET_MM >+/* 456 */ MCD_OPC_FilterValue, 15, 233, 3, // Skip to: 1461 >+/* 460 */ MCD_OPC_CheckPredicate, 3, 229, 3, // Skip to: 1461 >+/* 464 */ MCD_OPC_CheckField, 16, 10, 0, 223, 3, // Skip to: 1461 >+/* 470 */ MCD_OPC_Decode, 251, 4, 0, // Opcode: ERET_MM >+/* 474 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 486 >+/* 478 */ MCD_OPC_CheckPredicate, 3, 211, 3, // Skip to: 1461 >+/* 482 */ MCD_OPC_Decode, 246, 12, 21, // Opcode: TGEU_MM >+/* 486 */ MCD_OPC_FilterValue, 29, 39, 0, // Skip to: 529 >+/* 490 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 493 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 511 >+/* 497 */ MCD_OPC_CheckPredicate, 3, 192, 3, // Skip to: 1461 >+/* 501 */ MCD_OPC_CheckField, 21, 5, 0, 186, 3, // Skip to: 1461 >+/* 507 */ MCD_OPC_Decode, 173, 4, 23, // Opcode: DI_MM >+/* 511 */ MCD_OPC_FilterValue, 5, 178, 3, // Skip to: 1461 >+/* 515 */ MCD_OPC_CheckPredicate, 3, 174, 3, // Skip to: 1461 >+/* 519 */ MCD_OPC_CheckField, 21, 5, 0, 168, 3, // Skip to: 1461 >+/* 525 */ MCD_OPC_Decode, 249, 4, 23, // Opcode: EI_MM >+/* 529 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 541 >+/* 533 */ MCD_OPC_CheckPredicate, 3, 156, 3, // Skip to: 1461 >+/* 537 */ MCD_OPC_Decode, 134, 13, 21, // Opcode: TLT_MM >+/* 541 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 553 >+/* 545 */ MCD_OPC_CheckPredicate, 3, 144, 3, // Skip to: 1461 >+/* 549 */ MCD_OPC_Decode, 133, 13, 21, // Opcode: TLTU_MM >+/* 553 */ MCD_OPC_FilterValue, 44, 159, 0, // Skip to: 716 >+/* 557 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 560 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 572 >+/* 564 */ MCD_OPC_CheckPredicate, 3, 125, 3, // Skip to: 1461 >+/* 568 */ MCD_OPC_Decode, 236, 10, 24, // Opcode: SEB_MM >+/* 572 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 584 >+/* 576 */ MCD_OPC_CheckPredicate, 3, 113, 3, // Skip to: 1461 >+/* 580 */ MCD_OPC_Decode, 239, 10, 24, // Opcode: SEH_MM >+/* 584 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 596 >+/* 588 */ MCD_OPC_CheckPredicate, 3, 101, 3, // Skip to: 1461 >+/* 592 */ MCD_OPC_Decode, 242, 2, 24, // Opcode: CLO_MM >+/* 596 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 608 >+/* 600 */ MCD_OPC_CheckPredicate, 3, 89, 3, // Skip to: 1461 >+/* 604 */ MCD_OPC_Decode, 133, 3, 24, // Opcode: CLZ_MM >+/* 608 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 620 >+/* 612 */ MCD_OPC_CheckPredicate, 3, 77, 3, // Skip to: 1461 >+/* 616 */ MCD_OPC_Decode, 161, 13, 24, // Opcode: WSBH_MM >+/* 620 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 632 >+/* 624 */ MCD_OPC_CheckPredicate, 3, 65, 3, // Skip to: 1461 >+/* 628 */ MCD_OPC_Decode, 170, 9, 25, // Opcode: MULT_MM >+/* 632 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 644 >+/* 636 */ MCD_OPC_CheckPredicate, 3, 53, 3, // Skip to: 1461 >+/* 640 */ MCD_OPC_Decode, 172, 9, 25, // Opcode: MULTu_MM >+/* 644 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 656 >+/* 648 */ MCD_OPC_CheckPredicate, 3, 41, 3, // Skip to: 1461 >+/* 652 */ MCD_OPC_Decode, 229, 10, 25, // Opcode: SDIV_MM >+/* 656 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 668 >+/* 660 */ MCD_OPC_CheckPredicate, 3, 29, 3, // Skip to: 1461 >+/* 664 */ MCD_OPC_Decode, 149, 13, 25, // Opcode: UDIV_MM >+/* 668 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 680 >+/* 672 */ MCD_OPC_CheckPredicate, 3, 17, 3, // Skip to: 1461 >+/* 676 */ MCD_OPC_Decode, 236, 7, 25, // Opcode: MADD_MM >+/* 680 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 692 >+/* 684 */ MCD_OPC_CheckPredicate, 3, 5, 3, // Skip to: 1461 >+/* 688 */ MCD_OPC_Decode, 227, 7, 25, // Opcode: MADDU_MM >+/* 692 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 704 >+/* 696 */ MCD_OPC_CheckPredicate, 3, 249, 2, // Skip to: 1461 >+/* 700 */ MCD_OPC_Decode, 253, 8, 25, // Opcode: MSUB_MM >+/* 704 */ MCD_OPC_FilterValue, 15, 241, 2, // Skip to: 1461 >+/* 708 */ MCD_OPC_CheckPredicate, 3, 237, 2, // Skip to: 1461 >+/* 712 */ MCD_OPC_Decode, 244, 8, 25, // Opcode: MSUBU_MM >+/* 716 */ MCD_OPC_FilterValue, 45, 33, 0, // Skip to: 753 >+/* 720 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 723 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 741 >+/* 727 */ MCD_OPC_CheckPredicate, 3, 218, 2, // Skip to: 1461 >+/* 731 */ MCD_OPC_CheckField, 21, 5, 0, 212, 2, // Skip to: 1461 >+/* 737 */ MCD_OPC_Decode, 185, 12, 26, // Opcode: SYNC_MM >+/* 741 */ MCD_OPC_FilterValue, 8, 204, 2, // Skip to: 1461 >+/* 745 */ MCD_OPC_CheckPredicate, 3, 200, 2, // Skip to: 1461 >+/* 749 */ MCD_OPC_Decode, 187, 12, 22, // Opcode: SYSCALL_MM >+/* 753 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 765 >+/* 757 */ MCD_OPC_CheckPredicate, 3, 188, 2, // Skip to: 1461 >+/* 761 */ MCD_OPC_Decode, 138, 13, 21, // Opcode: TNE_MM >+/* 765 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 844 >+/* 769 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 772 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 790 >+/* 776 */ MCD_OPC_CheckPredicate, 3, 169, 2, // Skip to: 1461 >+/* 780 */ MCD_OPC_CheckField, 21, 5, 0, 163, 2, // Skip to: 1461 >+/* 786 */ MCD_OPC_Decode, 152, 8, 23, // Opcode: MFHI_MM >+/* 790 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 808 >+/* 794 */ MCD_OPC_CheckPredicate, 3, 151, 2, // Skip to: 1461 >+/* 798 */ MCD_OPC_CheckField, 21, 5, 0, 145, 2, // Skip to: 1461 >+/* 804 */ MCD_OPC_Decode, 157, 8, 23, // Opcode: MFLO_MM >+/* 808 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 826 >+/* 812 */ MCD_OPC_CheckPredicate, 3, 133, 2, // Skip to: 1461 >+/* 816 */ MCD_OPC_CheckField, 21, 5, 0, 127, 2, // Skip to: 1461 >+/* 822 */ MCD_OPC_Decode, 140, 9, 23, // Opcode: MTHI_MM >+/* 826 */ MCD_OPC_FilterValue, 3, 119, 2, // Skip to: 1461 >+/* 830 */ MCD_OPC_CheckPredicate, 3, 115, 2, // Skip to: 1461 >+/* 834 */ MCD_OPC_CheckField, 21, 5, 0, 109, 2, // Skip to: 1461 >+/* 840 */ MCD_OPC_Decode, 145, 9, 23, // Opcode: MTLO_MM >+/* 844 */ MCD_OPC_FilterValue, 60, 101, 2, // Skip to: 1461 >+/* 848 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 851 */ MCD_OPC_FilterValue, 0, 22, 0, // Skip to: 877 >+/* 855 */ MCD_OPC_CheckPredicate, 3, 10, 0, // Skip to: 869 >+/* 859 */ MCD_OPC_CheckField, 21, 5, 0, 4, 0, // Skip to: 869 >+/* 865 */ MCD_OPC_Decode, 246, 6, 23, // Opcode: JR_MM >+/* 869 */ MCD_OPC_CheckPredicate, 3, 76, 2, // Skip to: 1461 >+/* 873 */ MCD_OPC_Decode, 235, 6, 24, // Opcode: JALR_MM >+/* 877 */ MCD_OPC_FilterValue, 4, 68, 2, // Skip to: 1461 >+/* 881 */ MCD_OPC_CheckPredicate, 3, 64, 2, // Skip to: 1461 >+/* 885 */ MCD_OPC_Decode, 233, 6, 24, // Opcode: JALRS_MM >+/* 889 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 900 >+/* 893 */ MCD_OPC_CheckPredicate, 3, 52, 2, // Skip to: 1461 >+/* 897 */ MCD_OPC_Decode, 66, 27, // Opcode: ADDi_MM >+/* 900 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 912 >+/* 904 */ MCD_OPC_CheckPredicate, 3, 41, 2, // Skip to: 1461 >+/* 908 */ MCD_OPC_Decode, 132, 7, 28, // Opcode: LBu_MM >+/* 912 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 924 >+/* 916 */ MCD_OPC_CheckPredicate, 3, 29, 2, // Skip to: 1461 >+/* 920 */ MCD_OPC_Decode, 213, 10, 28, // Opcode: SB_MM >+/* 924 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 936 >+/* 928 */ MCD_OPC_CheckPredicate, 3, 17, 2, // Skip to: 1461 >+/* 932 */ MCD_OPC_Decode, 129, 7, 28, // Opcode: LB_MM >+/* 936 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 947 >+/* 940 */ MCD_OPC_CheckPredicate, 3, 5, 2, // Skip to: 1461 >+/* 944 */ MCD_OPC_Decode, 68, 27, // Opcode: ADDiu_MM >+/* 947 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 959 >+/* 951 */ MCD_OPC_CheckPredicate, 3, 250, 1, // Skip to: 1461 >+/* 955 */ MCD_OPC_Decode, 162, 7, 28, // Opcode: LHu_MM >+/* 959 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 971 >+/* 963 */ MCD_OPC_CheckPredicate, 3, 238, 1, // Skip to: 1461 >+/* 967 */ MCD_OPC_Decode, 153, 11, 28, // Opcode: SH_MM >+/* 971 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 983 >+/* 975 */ MCD_OPC_CheckPredicate, 3, 226, 1, // Skip to: 1461 >+/* 979 */ MCD_OPC_Decode, 159, 7, 28, // Opcode: LH_MM >+/* 983 */ MCD_OPC_FilterValue, 16, 207, 0, // Skip to: 1194 >+/* 987 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 990 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1002 >+/* 994 */ MCD_OPC_CheckPredicate, 3, 207, 1, // Skip to: 1461 >+/* 998 */ MCD_OPC_Decode, 252, 1, 29, // Opcode: BLTZ_MM >+/* 1002 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1014 >+/* 1006 */ MCD_OPC_CheckPredicate, 3, 195, 1, // Skip to: 1461 >+/* 1010 */ MCD_OPC_Decode, 249, 1, 29, // Opcode: BLTZAL_MM >+/* 1014 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1026 >+/* 1018 */ MCD_OPC_CheckPredicate, 3, 183, 1, // Skip to: 1461 >+/* 1022 */ MCD_OPC_Decode, 210, 1, 29, // Opcode: BGEZ_MM >+/* 1026 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1038 >+/* 1030 */ MCD_OPC_CheckPredicate, 3, 171, 1, // Skip to: 1461 >+/* 1034 */ MCD_OPC_Decode, 207, 1, 29, // Opcode: BGEZAL_MM >+/* 1038 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1050 >+/* 1042 */ MCD_OPC_CheckPredicate, 3, 159, 1, // Skip to: 1461 >+/* 1046 */ MCD_OPC_Decode, 240, 1, 29, // Opcode: BLEZ_MM >+/* 1050 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1062 >+/* 1054 */ MCD_OPC_CheckPredicate, 3, 147, 1, // Skip to: 1461 >+/* 1058 */ MCD_OPC_Decode, 143, 2, 29, // Opcode: BNEZC_MM >+/* 1062 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1074 >+/* 1066 */ MCD_OPC_CheckPredicate, 3, 135, 1, // Skip to: 1461 >+/* 1070 */ MCD_OPC_Decode, 216, 1, 29, // Opcode: BGTZ_MM >+/* 1074 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 1086 >+/* 1078 */ MCD_OPC_CheckPredicate, 3, 123, 1, // Skip to: 1461 >+/* 1082 */ MCD_OPC_Decode, 197, 1, 29, // Opcode: BEQZC_MM >+/* 1086 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1098 >+/* 1090 */ MCD_OPC_CheckPredicate, 3, 111, 1, // Skip to: 1461 >+/* 1094 */ MCD_OPC_Decode, 131, 13, 30, // Opcode: TLTI_MM >+/* 1098 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1110 >+/* 1102 */ MCD_OPC_CheckPredicate, 3, 99, 1, // Skip to: 1461 >+/* 1106 */ MCD_OPC_Decode, 244, 12, 30, // Opcode: TGEI_MM >+/* 1110 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1122 >+/* 1114 */ MCD_OPC_CheckPredicate, 3, 87, 1, // Skip to: 1461 >+/* 1118 */ MCD_OPC_Decode, 130, 13, 30, // Opcode: TLTIU_MM >+/* 1122 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1134 >+/* 1126 */ MCD_OPC_CheckPredicate, 3, 75, 1, // Skip to: 1461 >+/* 1130 */ MCD_OPC_Decode, 243, 12, 30, // Opcode: TGEIU_MM >+/* 1134 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1146 >+/* 1138 */ MCD_OPC_CheckPredicate, 3, 63, 1, // Skip to: 1461 >+/* 1142 */ MCD_OPC_Decode, 137, 13, 30, // Opcode: TNEI_MM >+/* 1146 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1158 >+/* 1150 */ MCD_OPC_CheckPredicate, 3, 51, 1, // Skip to: 1461 >+/* 1154 */ MCD_OPC_Decode, 182, 7, 30, // Opcode: LUi_MM >+/* 1158 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1170 >+/* 1162 */ MCD_OPC_CheckPredicate, 3, 39, 1, // Skip to: 1461 >+/* 1166 */ MCD_OPC_Decode, 238, 12, 30, // Opcode: TEQI_MM >+/* 1170 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1182 >+/* 1174 */ MCD_OPC_CheckPredicate, 3, 27, 1, // Skip to: 1461 >+/* 1178 */ MCD_OPC_Decode, 248, 1, 29, // Opcode: BLTZALS_MM >+/* 1182 */ MCD_OPC_FilterValue, 19, 19, 1, // Skip to: 1461 >+/* 1186 */ MCD_OPC_CheckPredicate, 3, 15, 1, // Skip to: 1461 >+/* 1190 */ MCD_OPC_Decode, 206, 1, 29, // Opcode: BGEZALS_MM >+/* 1194 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 1206 >+/* 1198 */ MCD_OPC_CheckPredicate, 3, 3, 1, // Skip to: 1461 >+/* 1202 */ MCD_OPC_Decode, 231, 9, 31, // Opcode: ORi_MM >+/* 1206 */ MCD_OPC_FilterValue, 21, 29, 0, // Skip to: 1239 >+/* 1210 */ MCD_OPC_ExtractField, 0, 13, // Inst{12-0} ... >+/* 1213 */ MCD_OPC_FilterValue, 251, 2, 8, 0, // Skip to: 1226 >+/* 1218 */ MCD_OPC_CheckPredicate, 3, 239, 0, // Skip to: 1461 >+/* 1222 */ MCD_OPC_Decode, 202, 8, 32, // Opcode: MOVF_I_MM >+/* 1226 */ MCD_OPC_FilterValue, 251, 18, 230, 0, // Skip to: 1461 >+/* 1231 */ MCD_OPC_CheckPredicate, 3, 226, 0, // Skip to: 1461 >+/* 1235 */ MCD_OPC_Decode, 222, 8, 32, // Opcode: MOVT_I_MM >+/* 1239 */ MCD_OPC_FilterValue, 24, 87, 0, // Skip to: 1330 >+/* 1243 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... >+/* 1246 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1258 >+/* 1250 */ MCD_OPC_CheckPredicate, 3, 207, 0, // Skip to: 1461 >+/* 1254 */ MCD_OPC_Decode, 192, 7, 33, // Opcode: LWL_MM >+/* 1258 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1270 >+/* 1262 */ MCD_OPC_CheckPredicate, 3, 195, 0, // Skip to: 1461 >+/* 1266 */ MCD_OPC_Decode, 196, 7, 33, // Opcode: LWR_MM >+/* 1270 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1282 >+/* 1274 */ MCD_OPC_CheckPredicate, 3, 183, 0, // Skip to: 1461 >+/* 1278 */ MCD_OPC_Decode, 166, 7, 33, // Opcode: LL_MM >+/* 1282 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1294 >+/* 1286 */ MCD_OPC_CheckPredicate, 3, 171, 0, // Skip to: 1461 >+/* 1290 */ MCD_OPC_Decode, 177, 12, 33, // Opcode: SWL_MM >+/* 1294 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1306 >+/* 1298 */ MCD_OPC_CheckPredicate, 3, 159, 0, // Skip to: 1461 >+/* 1302 */ MCD_OPC_Decode, 180, 12, 33, // Opcode: SWR_MM >+/* 1306 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1318 >+/* 1310 */ MCD_OPC_CheckPredicate, 3, 147, 0, // Skip to: 1461 >+/* 1314 */ MCD_OPC_Decode, 217, 10, 33, // Opcode: SC_MM >+/* 1318 */ MCD_OPC_FilterValue, 14, 139, 0, // Skip to: 1461 >+/* 1322 */ MCD_OPC_CheckPredicate, 3, 135, 0, // Skip to: 1461 >+/* 1326 */ MCD_OPC_Decode, 198, 7, 33, // Opcode: LWU_MM >+/* 1330 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1342 >+/* 1334 */ MCD_OPC_CheckPredicate, 3, 123, 0, // Skip to: 1461 >+/* 1338 */ MCD_OPC_Decode, 172, 13, 31, // Opcode: XORi_MM >+/* 1342 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1354 >+/* 1346 */ MCD_OPC_CheckPredicate, 3, 111, 0, // Skip to: 1461 >+/* 1350 */ MCD_OPC_Decode, 236, 6, 34, // Opcode: JALS_MM >+/* 1354 */ MCD_OPC_FilterValue, 36, 8, 0, // Skip to: 1366 >+/* 1358 */ MCD_OPC_CheckPredicate, 3, 99, 0, // Skip to: 1461 >+/* 1362 */ MCD_OPC_Decode, 181, 11, 27, // Opcode: SLTi_MM >+/* 1366 */ MCD_OPC_FilterValue, 37, 8, 0, // Skip to: 1378 >+/* 1370 */ MCD_OPC_CheckPredicate, 3, 87, 0, // Skip to: 1461 >+/* 1374 */ MCD_OPC_Decode, 198, 1, 35, // Opcode: BEQ_MM >+/* 1378 */ MCD_OPC_FilterValue, 44, 8, 0, // Skip to: 1390 >+/* 1382 */ MCD_OPC_CheckPredicate, 3, 75, 0, // Skip to: 1461 >+/* 1386 */ MCD_OPC_Decode, 184, 11, 27, // Opcode: SLTiu_MM >+/* 1390 */ MCD_OPC_FilterValue, 45, 8, 0, // Skip to: 1402 >+/* 1394 */ MCD_OPC_CheckPredicate, 3, 63, 0, // Skip to: 1461 >+/* 1398 */ MCD_OPC_Decode, 144, 2, 35, // Opcode: BNE_MM >+/* 1402 */ MCD_OPC_FilterValue, 52, 7, 0, // Skip to: 1413 >+/* 1406 */ MCD_OPC_CheckPredicate, 3, 51, 0, // Skip to: 1461 >+/* 1410 */ MCD_OPC_Decode, 85, 31, // Opcode: ANDi_MM >+/* 1413 */ MCD_OPC_FilterValue, 53, 8, 0, // Skip to: 1425 >+/* 1417 */ MCD_OPC_CheckPredicate, 3, 40, 0, // Skip to: 1461 >+/* 1421 */ MCD_OPC_Decode, 247, 6, 34, // Opcode: J_MM >+/* 1425 */ MCD_OPC_FilterValue, 61, 8, 0, // Skip to: 1437 >+/* 1429 */ MCD_OPC_CheckPredicate, 3, 28, 0, // Skip to: 1461 >+/* 1433 */ MCD_OPC_Decode, 238, 6, 34, // Opcode: JAL_MM >+/* 1437 */ MCD_OPC_FilterValue, 62, 8, 0, // Skip to: 1449 >+/* 1441 */ MCD_OPC_CheckPredicate, 3, 16, 0, // Skip to: 1461 >+/* 1445 */ MCD_OPC_Decode, 183, 12, 28, // Opcode: SW_MM >+/* 1449 */ MCD_OPC_FilterValue, 63, 8, 0, // Skip to: 1461 >+/* 1453 */ MCD_OPC_CheckPredicate, 3, 4, 0, // Skip to: 1461 >+/* 1457 */ MCD_OPC_Decode, 202, 7, 28, // Opcode: LW_MM >+/* 1461 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableMips32[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 68 >+/* 14 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 17 */ MCD_OPC_FilterValue, 0, 22, 52, // Skip to: 13355 >+/* 21 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... >+/* 24 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 36 >+/* 28 */ MCD_OPC_CheckPredicate, 1, 28, 0, // Skip to: 60 >+/* 32 */ MCD_OPC_Decode, 243, 11, 0, // Opcode: SSNOP >+/* 36 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 48 >+/* 40 */ MCD_OPC_CheckPredicate, 1, 16, 0, // Skip to: 60 >+/* 44 */ MCD_OPC_Decode, 247, 4, 0, // Opcode: EHB >+/* 48 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 60 >+/* 52 */ MCD_OPC_CheckPredicate, 4, 4, 0, // Skip to: 60 >+/* 56 */ MCD_OPC_Decode, 234, 9, 0, // Opcode: PAUSE >+/* 60 */ MCD_OPC_CheckPredicate, 1, 235, 51, // Skip to: 13355 >+/* 64 */ MCD_OPC_Decode, 162, 11, 36, // Opcode: SLL >+/* 68 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 111 >+/* 72 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 75 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 93 >+/* 79 */ MCD_OPC_CheckPredicate, 5, 216, 51, // Skip to: 13355 >+/* 83 */ MCD_OPC_CheckField, 6, 5, 0, 210, 51, // Skip to: 13355 >+/* 89 */ MCD_OPC_Decode, 200, 8, 37, // Opcode: MOVF_I >+/* 93 */ MCD_OPC_FilterValue, 1, 202, 51, // Skip to: 13355 >+/* 97 */ MCD_OPC_CheckPredicate, 5, 198, 51, // Skip to: 13355 >+/* 101 */ MCD_OPC_CheckField, 6, 5, 0, 192, 51, // Skip to: 13355 >+/* 107 */ MCD_OPC_Decode, 220, 8, 37, // Opcode: MOVT_I >+/* 111 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 142 >+/* 115 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 118 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 130 >+/* 122 */ MCD_OPC_CheckPredicate, 1, 173, 51, // Skip to: 13355 >+/* 126 */ MCD_OPC_Decode, 223, 11, 36, // Opcode: SRL >+/* 130 */ MCD_OPC_FilterValue, 1, 165, 51, // Skip to: 13355 >+/* 134 */ MCD_OPC_CheckPredicate, 4, 161, 51, // Skip to: 13355 >+/* 138 */ MCD_OPC_Decode, 188, 10, 36, // Opcode: ROTR >+/* 142 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 160 >+/* 146 */ MCD_OPC_CheckPredicate, 1, 149, 51, // Skip to: 13355 >+/* 150 */ MCD_OPC_CheckField, 21, 5, 0, 143, 51, // Skip to: 13355 >+/* 156 */ MCD_OPC_Decode, 203, 11, 36, // Opcode: SRA >+/* 160 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 178 >+/* 164 */ MCD_OPC_CheckPredicate, 1, 131, 51, // Skip to: 13355 >+/* 168 */ MCD_OPC_CheckField, 6, 5, 0, 125, 51, // Skip to: 13355 >+/* 174 */ MCD_OPC_Decode, 169, 11, 18, // Opcode: SLLV >+/* 178 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 196 >+/* 182 */ MCD_OPC_CheckPredicate, 6, 113, 51, // Skip to: 13355 >+/* 186 */ MCD_OPC_CheckField, 8, 3, 0, 107, 51, // Skip to: 13355 >+/* 192 */ MCD_OPC_Decode, 175, 7, 38, // Opcode: LSA >+/* 196 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 227 >+/* 200 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 203 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 215 >+/* 207 */ MCD_OPC_CheckPredicate, 1, 88, 51, // Skip to: 13355 >+/* 211 */ MCD_OPC_Decode, 236, 11, 18, // Opcode: SRLV >+/* 215 */ MCD_OPC_FilterValue, 1, 80, 51, // Skip to: 13355 >+/* 219 */ MCD_OPC_CheckPredicate, 4, 76, 51, // Skip to: 13355 >+/* 223 */ MCD_OPC_Decode, 189, 10, 18, // Opcode: ROTRV >+/* 227 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 245 >+/* 231 */ MCD_OPC_CheckPredicate, 1, 64, 51, // Skip to: 13355 >+/* 235 */ MCD_OPC_CheckField, 6, 5, 0, 58, 51, // Skip to: 13355 >+/* 241 */ MCD_OPC_Decode, 216, 11, 18, // Opcode: SRAV >+/* 245 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 276 >+/* 249 */ MCD_OPC_ExtractField, 6, 15, // Inst{20-6} ... >+/* 252 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 264 >+/* 256 */ MCD_OPC_CheckPredicate, 1, 39, 51, // Skip to: 13355 >+/* 260 */ MCD_OPC_Decode, 241, 6, 39, // Opcode: JR >+/* 264 */ MCD_OPC_FilterValue, 16, 31, 51, // Skip to: 13355 >+/* 268 */ MCD_OPC_CheckPredicate, 7, 27, 51, // Skip to: 13355 >+/* 272 */ MCD_OPC_Decode, 244, 6, 39, // Opcode: JR_HB >+/* 276 */ MCD_OPC_FilterValue, 9, 39, 0, // Skip to: 319 >+/* 280 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 283 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 301 >+/* 287 */ MCD_OPC_CheckPredicate, 8, 8, 51, // Skip to: 13355 >+/* 291 */ MCD_OPC_CheckField, 16, 5, 0, 2, 51, // Skip to: 13355 >+/* 297 */ MCD_OPC_Decode, 228, 6, 40, // Opcode: JALR >+/* 301 */ MCD_OPC_FilterValue, 16, 250, 50, // Skip to: 13355 >+/* 305 */ MCD_OPC_CheckPredicate, 9, 246, 50, // Skip to: 13355 >+/* 309 */ MCD_OPC_CheckField, 16, 5, 0, 240, 50, // Skip to: 13355 >+/* 315 */ MCD_OPC_Decode, 234, 6, 40, // Opcode: JALR_HB >+/* 319 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 337 >+/* 323 */ MCD_OPC_CheckPredicate, 5, 228, 50, // Skip to: 13355 >+/* 327 */ MCD_OPC_CheckField, 6, 5, 0, 222, 50, // Skip to: 13355 >+/* 333 */ MCD_OPC_Decode, 232, 8, 41, // Opcode: MOVZ_I_I >+/* 337 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 355 >+/* 341 */ MCD_OPC_CheckPredicate, 5, 210, 50, // Skip to: 13355 >+/* 345 */ MCD_OPC_CheckField, 6, 5, 0, 204, 50, // Skip to: 13355 >+/* 351 */ MCD_OPC_Decode, 212, 8, 41, // Opcode: MOVN_I_I >+/* 355 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 367 >+/* 359 */ MCD_OPC_CheckPredicate, 1, 192, 50, // Skip to: 13355 >+/* 363 */ MCD_OPC_Decode, 186, 12, 42, // Opcode: SYSCALL >+/* 367 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 379 >+/* 371 */ MCD_OPC_CheckPredicate, 1, 180, 50, // Skip to: 13355 >+/* 375 */ MCD_OPC_Decode, 154, 2, 15, // Opcode: BREAK >+/* 379 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 391 >+/* 383 */ MCD_OPC_CheckPredicate, 9, 168, 50, // Skip to: 13355 >+/* 387 */ MCD_OPC_Decode, 184, 12, 43, // Opcode: SYNC >+/* 391 */ MCD_OPC_FilterValue, 16, 43, 0, // Skip to: 438 >+/* 395 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 398 */ MCD_OPC_FilterValue, 0, 153, 50, // Skip to: 13355 >+/* 402 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 405 */ MCD_OPC_FilterValue, 0, 146, 50, // Skip to: 13355 >+/* 409 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... >+/* 412 */ MCD_OPC_FilterValue, 0, 139, 50, // Skip to: 13355 >+/* 416 */ MCD_OPC_CheckPredicate, 10, 10, 0, // Skip to: 430 >+/* 420 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 430 >+/* 426 */ MCD_OPC_Decode, 148, 8, 44, // Opcode: MFHI >+/* 430 */ MCD_OPC_CheckPredicate, 11, 121, 50, // Skip to: 13355 >+/* 434 */ MCD_OPC_Decode, 151, 8, 45, // Opcode: MFHI_DSP >+/* 438 */ MCD_OPC_FilterValue, 17, 36, 0, // Skip to: 478 >+/* 442 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 445 */ MCD_OPC_FilterValue, 0, 106, 50, // Skip to: 13355 >+/* 449 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... >+/* 452 */ MCD_OPC_FilterValue, 0, 99, 50, // Skip to: 13355 >+/* 456 */ MCD_OPC_CheckPredicate, 12, 10, 0, // Skip to: 470 >+/* 460 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 470 >+/* 466 */ MCD_OPC_Decode, 137, 9, 39, // Opcode: MTHI >+/* 470 */ MCD_OPC_CheckPredicate, 11, 81, 50, // Skip to: 13355 >+/* 474 */ MCD_OPC_Decode, 139, 9, 46, // Opcode: MTHI_DSP >+/* 478 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 525 >+/* 482 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 485 */ MCD_OPC_FilterValue, 0, 66, 50, // Skip to: 13355 >+/* 489 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 492 */ MCD_OPC_FilterValue, 0, 59, 50, // Skip to: 13355 >+/* 496 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... >+/* 499 */ MCD_OPC_FilterValue, 0, 52, 50, // Skip to: 13355 >+/* 503 */ MCD_OPC_CheckPredicate, 10, 10, 0, // Skip to: 517 >+/* 507 */ MCD_OPC_CheckField, 21, 2, 0, 4, 0, // Skip to: 517 >+/* 513 */ MCD_OPC_Decode, 153, 8, 44, // Opcode: MFLO >+/* 517 */ MCD_OPC_CheckPredicate, 11, 34, 50, // Skip to: 13355 >+/* 521 */ MCD_OPC_Decode, 156, 8, 45, // Opcode: MFLO_DSP >+/* 525 */ MCD_OPC_FilterValue, 19, 36, 0, // Skip to: 565 >+/* 529 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 532 */ MCD_OPC_FilterValue, 0, 19, 50, // Skip to: 13355 >+/* 536 */ MCD_OPC_ExtractField, 13, 8, // Inst{20-13} ... >+/* 539 */ MCD_OPC_FilterValue, 0, 12, 50, // Skip to: 13355 >+/* 543 */ MCD_OPC_CheckPredicate, 12, 10, 0, // Skip to: 557 >+/* 547 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 557 >+/* 553 */ MCD_OPC_Decode, 142, 9, 39, // Opcode: MTLO >+/* 557 */ MCD_OPC_CheckPredicate, 11, 250, 49, // Skip to: 13355 >+/* 561 */ MCD_OPC_Decode, 144, 9, 47, // Opcode: MTLO_DSP >+/* 565 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 583 >+/* 569 */ MCD_OPC_CheckPredicate, 13, 238, 49, // Skip to: 13355 >+/* 573 */ MCD_OPC_CheckField, 8, 3, 0, 232, 49, // Skip to: 13355 >+/* 579 */ MCD_OPC_Decode, 174, 4, 48, // Opcode: DLSA >+/* 583 */ MCD_OPC_FilterValue, 24, 36, 0, // Skip to: 623 >+/* 587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 590 */ MCD_OPC_FilterValue, 0, 217, 49, // Skip to: 13355 >+/* 594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 597 */ MCD_OPC_FilterValue, 0, 210, 49, // Skip to: 13355 >+/* 601 */ MCD_OPC_CheckPredicate, 12, 10, 0, // Skip to: 615 >+/* 605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 615 >+/* 611 */ MCD_OPC_Decode, 167, 9, 24, // Opcode: MULT >+/* 615 */ MCD_OPC_CheckPredicate, 11, 192, 49, // Skip to: 13355 >+/* 619 */ MCD_OPC_Decode, 169, 9, 49, // Opcode: MULT_DSP >+/* 623 */ MCD_OPC_FilterValue, 25, 36, 0, // Skip to: 663 >+/* 627 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 630 */ MCD_OPC_FilterValue, 0, 177, 49, // Skip to: 13355 >+/* 634 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 637 */ MCD_OPC_FilterValue, 0, 170, 49, // Skip to: 13355 >+/* 641 */ MCD_OPC_CheckPredicate, 12, 10, 0, // Skip to: 655 >+/* 645 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 655 >+/* 651 */ MCD_OPC_Decode, 171, 9, 24, // Opcode: MULTu >+/* 655 */ MCD_OPC_CheckPredicate, 11, 152, 49, // Skip to: 13355 >+/* 659 */ MCD_OPC_Decode, 168, 9, 49, // Opcode: MULTU_DSP >+/* 663 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 681 >+/* 667 */ MCD_OPC_CheckPredicate, 12, 140, 49, // Skip to: 13355 >+/* 671 */ MCD_OPC_CheckField, 6, 10, 0, 134, 49, // Skip to: 13355 >+/* 677 */ MCD_OPC_Decode, 228, 10, 24, // Opcode: SDIV >+/* 681 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 699 >+/* 685 */ MCD_OPC_CheckPredicate, 12, 122, 49, // Skip to: 13355 >+/* 689 */ MCD_OPC_CheckField, 6, 10, 0, 116, 49, // Skip to: 13355 >+/* 695 */ MCD_OPC_Decode, 148, 13, 24, // Opcode: UDIV >+/* 699 */ MCD_OPC_FilterValue, 32, 13, 0, // Skip to: 716 >+/* 703 */ MCD_OPC_CheckPredicate, 1, 104, 49, // Skip to: 13355 >+/* 707 */ MCD_OPC_CheckField, 6, 5, 0, 98, 49, // Skip to: 13355 >+/* 713 */ MCD_OPC_Decode, 23, 17, // Opcode: ADD >+/* 716 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 733 >+/* 720 */ MCD_OPC_CheckPredicate, 1, 87, 49, // Skip to: 13355 >+/* 724 */ MCD_OPC_CheckField, 6, 5, 0, 81, 49, // Skip to: 13355 >+/* 730 */ MCD_OPC_Decode, 69, 17, // Opcode: ADDu >+/* 733 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 751 >+/* 737 */ MCD_OPC_CheckPredicate, 1, 70, 49, // Skip to: 13355 >+/* 741 */ MCD_OPC_CheckField, 6, 5, 0, 64, 49, // Skip to: 13355 >+/* 747 */ MCD_OPC_Decode, 252, 11, 17, // Opcode: SUB >+/* 751 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 769 >+/* 755 */ MCD_OPC_CheckPredicate, 1, 52, 49, // Skip to: 13355 >+/* 759 */ MCD_OPC_CheckField, 6, 5, 0, 46, 49, // Skip to: 13355 >+/* 765 */ MCD_OPC_Decode, 163, 12, 17, // Opcode: SUBu >+/* 769 */ MCD_OPC_FilterValue, 36, 13, 0, // Skip to: 786 >+/* 773 */ MCD_OPC_CheckPredicate, 1, 34, 49, // Skip to: 13355 >+/* 777 */ MCD_OPC_CheckField, 6, 5, 0, 28, 49, // Skip to: 13355 >+/* 783 */ MCD_OPC_Decode, 75, 17, // Opcode: AND >+/* 786 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 804 >+/* 790 */ MCD_OPC_CheckPredicate, 1, 17, 49, // Skip to: 13355 >+/* 794 */ MCD_OPC_CheckField, 6, 5, 0, 11, 49, // Skip to: 13355 >+/* 800 */ MCD_OPC_Decode, 221, 9, 17, // Opcode: OR >+/* 804 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 822 >+/* 808 */ MCD_OPC_CheckPredicate, 1, 255, 48, // Skip to: 13355 >+/* 812 */ MCD_OPC_CheckField, 6, 5, 0, 249, 48, // Skip to: 13355 >+/* 818 */ MCD_OPC_Decode, 162, 13, 17, // Opcode: XOR >+/* 822 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 840 >+/* 826 */ MCD_OPC_CheckPredicate, 1, 237, 48, // Skip to: 13355 >+/* 830 */ MCD_OPC_CheckField, 6, 5, 0, 231, 48, // Skip to: 13355 >+/* 836 */ MCD_OPC_Decode, 211, 9, 17, // Opcode: NOR >+/* 840 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 858 >+/* 844 */ MCD_OPC_CheckPredicate, 1, 219, 48, // Skip to: 13355 >+/* 848 */ MCD_OPC_CheckField, 6, 5, 0, 213, 48, // Skip to: 13355 >+/* 854 */ MCD_OPC_Decode, 176, 11, 17, // Opcode: SLT >+/* 858 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 876 >+/* 862 */ MCD_OPC_CheckPredicate, 1, 201, 48, // Skip to: 13355 >+/* 866 */ MCD_OPC_CheckField, 6, 5, 0, 195, 48, // Skip to: 13355 >+/* 872 */ MCD_OPC_Decode, 185, 11, 17, // Opcode: SLTu >+/* 876 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 888 >+/* 880 */ MCD_OPC_CheckPredicate, 2, 183, 48, // Skip to: 13355 >+/* 884 */ MCD_OPC_Decode, 240, 12, 50, // Opcode: TGE >+/* 888 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 900 >+/* 892 */ MCD_OPC_CheckPredicate, 2, 171, 48, // Skip to: 13355 >+/* 896 */ MCD_OPC_Decode, 245, 12, 50, // Opcode: TGEU >+/* 900 */ MCD_OPC_FilterValue, 50, 8, 0, // Skip to: 912 >+/* 904 */ MCD_OPC_CheckPredicate, 2, 159, 48, // Skip to: 13355 >+/* 908 */ MCD_OPC_Decode, 128, 13, 50, // Opcode: TLT >+/* 912 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 924 >+/* 916 */ MCD_OPC_CheckPredicate, 2, 147, 48, // Skip to: 13355 >+/* 920 */ MCD_OPC_Decode, 132, 13, 50, // Opcode: TLTU >+/* 924 */ MCD_OPC_FilterValue, 52, 8, 0, // Skip to: 936 >+/* 928 */ MCD_OPC_CheckPredicate, 2, 135, 48, // Skip to: 13355 >+/* 932 */ MCD_OPC_Decode, 236, 12, 50, // Opcode: TEQ >+/* 936 */ MCD_OPC_FilterValue, 54, 127, 48, // Skip to: 13355 >+/* 940 */ MCD_OPC_CheckPredicate, 2, 123, 48, // Skip to: 13355 >+/* 944 */ MCD_OPC_Decode, 135, 13, 50, // Opcode: TNE >+/* 948 */ MCD_OPC_FilterValue, 1, 189, 0, // Skip to: 1141 >+/* 952 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 955 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 967 >+/* 959 */ MCD_OPC_CheckPredicate, 1, 104, 48, // Skip to: 13355 >+/* 963 */ MCD_OPC_Decode, 243, 1, 51, // Opcode: BLTZ >+/* 967 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 979 >+/* 971 */ MCD_OPC_CheckPredicate, 1, 92, 48, // Skip to: 13355 >+/* 975 */ MCD_OPC_Decode, 201, 1, 51, // Opcode: BGEZ >+/* 979 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 991 >+/* 983 */ MCD_OPC_CheckPredicate, 1, 80, 48, // Skip to: 13355 >+/* 987 */ MCD_OPC_Decode, 251, 1, 51, // Opcode: BLTZL >+/* 991 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1003 >+/* 995 */ MCD_OPC_CheckPredicate, 1, 68, 48, // Skip to: 13355 >+/* 999 */ MCD_OPC_Decode, 209, 1, 51, // Opcode: BGEZL >+/* 1003 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1015 >+/* 1007 */ MCD_OPC_CheckPredicate, 14, 56, 48, // Skip to: 13355 >+/* 1011 */ MCD_OPC_Decode, 241, 12, 52, // Opcode: TGEI >+/* 1015 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1027 >+/* 1019 */ MCD_OPC_CheckPredicate, 14, 44, 48, // Skip to: 13355 >+/* 1023 */ MCD_OPC_Decode, 242, 12, 52, // Opcode: TGEIU >+/* 1027 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1039 >+/* 1031 */ MCD_OPC_CheckPredicate, 14, 32, 48, // Skip to: 13355 >+/* 1035 */ MCD_OPC_Decode, 129, 13, 52, // Opcode: TLTI >+/* 1039 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1051 >+/* 1043 */ MCD_OPC_CheckPredicate, 14, 20, 48, // Skip to: 13355 >+/* 1047 */ MCD_OPC_Decode, 147, 13, 52, // Opcode: TTLTIU >+/* 1051 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 1063 >+/* 1055 */ MCD_OPC_CheckPredicate, 14, 8, 48, // Skip to: 13355 >+/* 1059 */ MCD_OPC_Decode, 237, 12, 52, // Opcode: TEQI >+/* 1063 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1075 >+/* 1067 */ MCD_OPC_CheckPredicate, 14, 252, 47, // Skip to: 13355 >+/* 1071 */ MCD_OPC_Decode, 136, 13, 52, // Opcode: TNEI >+/* 1075 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1087 >+/* 1079 */ MCD_OPC_CheckPredicate, 12, 240, 47, // Skip to: 13355 >+/* 1083 */ MCD_OPC_Decode, 245, 1, 51, // Opcode: BLTZAL >+/* 1087 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1099 >+/* 1091 */ MCD_OPC_CheckPredicate, 12, 228, 47, // Skip to: 13355 >+/* 1095 */ MCD_OPC_Decode, 203, 1, 51, // Opcode: BGEZAL >+/* 1099 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1111 >+/* 1103 */ MCD_OPC_CheckPredicate, 1, 216, 47, // Skip to: 13355 >+/* 1107 */ MCD_OPC_Decode, 247, 1, 51, // Opcode: BLTZALL >+/* 1111 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1123 >+/* 1115 */ MCD_OPC_CheckPredicate, 1, 204, 47, // Skip to: 13355 >+/* 1119 */ MCD_OPC_Decode, 205, 1, 51, // Opcode: BGEZALL >+/* 1123 */ MCD_OPC_FilterValue, 28, 196, 47, // Skip to: 13355 >+/* 1127 */ MCD_OPC_CheckPredicate, 11, 192, 47, // Skip to: 13355 >+/* 1131 */ MCD_OPC_CheckField, 21, 5, 0, 186, 47, // Skip to: 13355 >+/* 1137 */ MCD_OPC_Decode, 152, 2, 53, // Opcode: BPOSGE32 >+/* 1141 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1153 >+/* 1145 */ MCD_OPC_CheckPredicate, 9, 174, 47, // Skip to: 13355 >+/* 1149 */ MCD_OPC_Decode, 226, 6, 54, // Opcode: J >+/* 1153 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1165 >+/* 1157 */ MCD_OPC_CheckPredicate, 1, 162, 47, // Skip to: 13355 >+/* 1161 */ MCD_OPC_Decode, 227, 6, 54, // Opcode: JAL >+/* 1165 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 1177 >+/* 1169 */ MCD_OPC_CheckPredicate, 1, 150, 47, // Skip to: 13355 >+/* 1173 */ MCD_OPC_Decode, 191, 1, 55, // Opcode: BEQ >+/* 1177 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 1189 >+/* 1181 */ MCD_OPC_CheckPredicate, 1, 138, 47, // Skip to: 13355 >+/* 1185 */ MCD_OPC_Decode, 129, 2, 55, // Opcode: BNE >+/* 1189 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1207 >+/* 1193 */ MCD_OPC_CheckPredicate, 1, 126, 47, // Skip to: 13355 >+/* 1197 */ MCD_OPC_CheckField, 16, 5, 0, 120, 47, // Skip to: 13355 >+/* 1203 */ MCD_OPC_Decode, 235, 1, 51, // Opcode: BLEZ >+/* 1207 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1225 >+/* 1211 */ MCD_OPC_CheckPredicate, 1, 108, 47, // Skip to: 13355 >+/* 1215 */ MCD_OPC_CheckField, 16, 5, 0, 102, 47, // Skip to: 13355 >+/* 1221 */ MCD_OPC_Decode, 211, 1, 51, // Opcode: BGTZ >+/* 1225 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 1236 >+/* 1229 */ MCD_OPC_CheckPredicate, 12, 90, 47, // Skip to: 13355 >+/* 1233 */ MCD_OPC_Decode, 65, 56, // Opcode: ADDi >+/* 1236 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 1247 >+/* 1240 */ MCD_OPC_CheckPredicate, 1, 79, 47, // Skip to: 13355 >+/* 1244 */ MCD_OPC_Decode, 67, 56, // Opcode: ADDiu >+/* 1247 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1259 >+/* 1251 */ MCD_OPC_CheckPredicate, 1, 68, 47, // Skip to: 13355 >+/* 1255 */ MCD_OPC_Decode, 179, 11, 56, // Opcode: SLTi >+/* 1259 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1271 >+/* 1263 */ MCD_OPC_CheckPredicate, 1, 56, 47, // Skip to: 13355 >+/* 1267 */ MCD_OPC_Decode, 182, 11, 56, // Opcode: SLTiu >+/* 1271 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 1282 >+/* 1275 */ MCD_OPC_CheckPredicate, 1, 44, 47, // Skip to: 13355 >+/* 1279 */ MCD_OPC_Decode, 83, 57, // Opcode: ANDi >+/* 1282 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 1294 >+/* 1286 */ MCD_OPC_CheckPredicate, 1, 33, 47, // Skip to: 13355 >+/* 1290 */ MCD_OPC_Decode, 229, 9, 57, // Opcode: ORi >+/* 1294 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 1306 >+/* 1298 */ MCD_OPC_CheckPredicate, 1, 21, 47, // Skip to: 13355 >+/* 1302 */ MCD_OPC_Decode, 170, 13, 57, // Opcode: XORi >+/* 1306 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1324 >+/* 1310 */ MCD_OPC_CheckPredicate, 1, 9, 47, // Skip to: 13355 >+/* 1314 */ MCD_OPC_CheckField, 21, 5, 0, 3, 47, // Skip to: 13355 >+/* 1320 */ MCD_OPC_Decode, 180, 7, 30, // Opcode: LUi >+/* 1324 */ MCD_OPC_FilterValue, 16, 220, 0, // Skip to: 1548 >+/* 1328 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1331 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1349 >+/* 1335 */ MCD_OPC_CheckPredicate, 9, 240, 46, // Skip to: 13355 >+/* 1339 */ MCD_OPC_CheckField, 3, 8, 0, 234, 46, // Skip to: 13355 >+/* 1345 */ MCD_OPC_Decode, 141, 8, 58, // Opcode: MFC0 >+/* 1349 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1367 >+/* 1353 */ MCD_OPC_CheckPredicate, 9, 222, 46, // Skip to: 13355 >+/* 1357 */ MCD_OPC_CheckField, 3, 8, 0, 216, 46, // Skip to: 13355 >+/* 1363 */ MCD_OPC_Decode, 130, 9, 58, // Opcode: MTC0 >+/* 1367 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1422 >+/* 1371 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1374 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1386 >+/* 1378 */ MCD_OPC_CheckPredicate, 12, 197, 46, // Skip to: 13355 >+/* 1382 */ MCD_OPC_Decode, 161, 1, 59, // Opcode: BC0F >+/* 1386 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1398 >+/* 1390 */ MCD_OPC_CheckPredicate, 12, 185, 46, // Skip to: 13355 >+/* 1394 */ MCD_OPC_Decode, 163, 1, 59, // Opcode: BC0T >+/* 1398 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1410 >+/* 1402 */ MCD_OPC_CheckPredicate, 12, 173, 46, // Skip to: 13355 >+/* 1406 */ MCD_OPC_Decode, 162, 1, 59, // Opcode: BC0FL >+/* 1410 */ MCD_OPC_FilterValue, 3, 165, 46, // Skip to: 13355 >+/* 1414 */ MCD_OPC_CheckPredicate, 12, 161, 46, // Skip to: 13355 >+/* 1418 */ MCD_OPC_Decode, 164, 1, 59, // Opcode: BC0TL >+/* 1422 */ MCD_OPC_FilterValue, 11, 31, 0, // Skip to: 1457 >+/* 1426 */ MCD_OPC_ExtractField, 0, 16, // Inst{15-0} ... >+/* 1429 */ MCD_OPC_FilterValue, 128, 192, 1, 8, 0, // Skip to: 1443 >+/* 1435 */ MCD_OPC_CheckPredicate, 4, 140, 46, // Skip to: 13355 >+/* 1439 */ MCD_OPC_Decode, 159, 4, 23, // Opcode: DI >+/* 1443 */ MCD_OPC_FilterValue, 160, 192, 1, 130, 46, // Skip to: 13355 >+/* 1449 */ MCD_OPC_CheckPredicate, 4, 126, 46, // Skip to: 13355 >+/* 1453 */ MCD_OPC_Decode, 248, 4, 23, // Opcode: EI >+/* 1457 */ MCD_OPC_FilterValue, 16, 118, 46, // Skip to: 13355 >+/* 1461 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... >+/* 1464 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1476 >+/* 1468 */ MCD_OPC_CheckPredicate, 1, 107, 46, // Skip to: 13355 >+/* 1472 */ MCD_OPC_Decode, 250, 12, 0, // Opcode: TLBR >+/* 1476 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1488 >+/* 1480 */ MCD_OPC_CheckPredicate, 1, 95, 46, // Skip to: 13355 >+/* 1484 */ MCD_OPC_Decode, 252, 12, 0, // Opcode: TLBWI >+/* 1488 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 1500 >+/* 1492 */ MCD_OPC_CheckPredicate, 1, 83, 46, // Skip to: 13355 >+/* 1496 */ MCD_OPC_Decode, 254, 12, 0, // Opcode: TLBWR >+/* 1500 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1512 >+/* 1504 */ MCD_OPC_CheckPredicate, 1, 71, 46, // Skip to: 13355 >+/* 1508 */ MCD_OPC_Decode, 248, 12, 0, // Opcode: TLBP >+/* 1512 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1524 >+/* 1516 */ MCD_OPC_CheckPredicate, 15, 59, 46, // Skip to: 13355 >+/* 1520 */ MCD_OPC_Decode, 250, 4, 0, // Opcode: ERET >+/* 1524 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1536 >+/* 1528 */ MCD_OPC_CheckPredicate, 9, 47, 46, // Skip to: 13355 >+/* 1532 */ MCD_OPC_Decode, 154, 4, 0, // Opcode: DERET >+/* 1536 */ MCD_OPC_FilterValue, 32, 39, 46, // Skip to: 13355 >+/* 1540 */ MCD_OPC_CheckPredicate, 16, 35, 46, // Skip to: 13355 >+/* 1544 */ MCD_OPC_Decode, 157, 13, 0, // Opcode: WAIT >+/* 1548 */ MCD_OPC_FilterValue, 17, 21, 6, // Skip to: 3109 >+/* 1552 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1555 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 1573 >+/* 1559 */ MCD_OPC_CheckPredicate, 1, 16, 46, // Skip to: 13355 >+/* 1563 */ MCD_OPC_CheckField, 0, 11, 0, 10, 46, // Skip to: 13355 >+/* 1569 */ MCD_OPC_Decode, 142, 8, 60, // Opcode: MFC1 >+/* 1573 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 1591 >+/* 1577 */ MCD_OPC_CheckPredicate, 17, 254, 45, // Skip to: 13355 >+/* 1581 */ MCD_OPC_CheckField, 0, 11, 0, 248, 45, // Skip to: 13355 >+/* 1587 */ MCD_OPC_Decode, 177, 4, 61, // Opcode: DMFC1 >+/* 1591 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 1609 >+/* 1595 */ MCD_OPC_CheckPredicate, 1, 236, 45, // Skip to: 13355 >+/* 1599 */ MCD_OPC_CheckField, 0, 11, 0, 230, 45, // Skip to: 13355 >+/* 1605 */ MCD_OPC_Decode, 218, 2, 62, // Opcode: CFC1 >+/* 1609 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 1627 >+/* 1613 */ MCD_OPC_CheckPredicate, 18, 218, 45, // Skip to: 13355 >+/* 1617 */ MCD_OPC_CheckField, 0, 11, 0, 212, 45, // Skip to: 13355 >+/* 1623 */ MCD_OPC_Decode, 145, 8, 63, // Opcode: MFHC1_D32 >+/* 1627 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1645 >+/* 1631 */ MCD_OPC_CheckPredicate, 1, 200, 45, // Skip to: 13355 >+/* 1635 */ MCD_OPC_CheckField, 0, 11, 0, 194, 45, // Skip to: 13355 >+/* 1641 */ MCD_OPC_Decode, 131, 9, 64, // Opcode: MTC1 >+/* 1645 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1663 >+/* 1649 */ MCD_OPC_CheckPredicate, 17, 182, 45, // Skip to: 13355 >+/* 1653 */ MCD_OPC_CheckField, 0, 11, 0, 176, 45, // Skip to: 13355 >+/* 1659 */ MCD_OPC_Decode, 182, 4, 65, // Opcode: DMTC1 >+/* 1663 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1681 >+/* 1667 */ MCD_OPC_CheckPredicate, 1, 164, 45, // Skip to: 13355 >+/* 1671 */ MCD_OPC_CheckField, 0, 11, 0, 158, 45, // Skip to: 13355 >+/* 1677 */ MCD_OPC_Decode, 190, 3, 66, // Opcode: CTC1 >+/* 1681 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1699 >+/* 1685 */ MCD_OPC_CheckPredicate, 18, 146, 45, // Skip to: 13355 >+/* 1689 */ MCD_OPC_CheckField, 0, 11, 0, 140, 45, // Skip to: 13355 >+/* 1695 */ MCD_OPC_Decode, 134, 9, 67, // Opcode: MTHC1_D32 >+/* 1699 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 1754 >+/* 1703 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1706 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1718 >+/* 1710 */ MCD_OPC_CheckPredicate, 12, 121, 45, // Skip to: 13355 >+/* 1714 */ MCD_OPC_Decode, 166, 1, 68, // Opcode: BC1F >+/* 1718 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1730 >+/* 1722 */ MCD_OPC_CheckPredicate, 12, 109, 45, // Skip to: 13355 >+/* 1726 */ MCD_OPC_Decode, 170, 1, 68, // Opcode: BC1T >+/* 1730 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1742 >+/* 1734 */ MCD_OPC_CheckPredicate, 12, 97, 45, // Skip to: 13355 >+/* 1738 */ MCD_OPC_Decode, 167, 1, 68, // Opcode: BC1FL >+/* 1742 */ MCD_OPC_FilterValue, 3, 89, 45, // Skip to: 13355 >+/* 1746 */ MCD_OPC_CheckPredicate, 12, 85, 45, // Skip to: 13355 >+/* 1750 */ MCD_OPC_Decode, 171, 1, 68, // Opcode: BC1TL >+/* 1754 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1766 >+/* 1758 */ MCD_OPC_CheckPredicate, 6, 73, 45, // Skip to: 13355 >+/* 1762 */ MCD_OPC_Decode, 174, 2, 69, // Opcode: BZ_V >+/* 1766 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 1778 >+/* 1770 */ MCD_OPC_CheckPredicate, 6, 61, 45, // Skip to: 13355 >+/* 1774 */ MCD_OPC_Decode, 149, 2, 69, // Opcode: BNZ_V >+/* 1778 */ MCD_OPC_FilterValue, 16, 80, 2, // Skip to: 2374 >+/* 1782 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1785 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1797 >+/* 1789 */ MCD_OPC_CheckPredicate, 1, 42, 45, // Skip to: 13355 >+/* 1793 */ MCD_OPC_Decode, 153, 5, 70, // Opcode: FADD_S >+/* 1797 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1809 >+/* 1801 */ MCD_OPC_CheckPredicate, 1, 30, 45, // Skip to: 13355 >+/* 1805 */ MCD_OPC_Decode, 155, 6, 70, // Opcode: FSUB_S >+/* 1809 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1821 >+/* 1813 */ MCD_OPC_CheckPredicate, 1, 18, 45, // Skip to: 13355 >+/* 1817 */ MCD_OPC_Decode, 246, 5, 70, // Opcode: FMUL_S >+/* 1821 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1833 >+/* 1825 */ MCD_OPC_CheckPredicate, 1, 6, 45, // Skip to: 13355 >+/* 1829 */ MCD_OPC_Decode, 189, 5, 70, // Opcode: FDIV_S >+/* 1833 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 1851 >+/* 1837 */ MCD_OPC_CheckPredicate, 2, 250, 44, // Skip to: 13355 >+/* 1841 */ MCD_OPC_CheckField, 16, 5, 0, 244, 44, // Skip to: 13355 >+/* 1847 */ MCD_OPC_Decode, 148, 6, 71, // Opcode: FSQRT_S >+/* 1851 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 1869 >+/* 1855 */ MCD_OPC_CheckPredicate, 1, 232, 44, // Skip to: 13355 >+/* 1859 */ MCD_OPC_CheckField, 16, 5, 0, 226, 44, // Skip to: 13355 >+/* 1865 */ MCD_OPC_Decode, 146, 5, 71, // Opcode: FABS_S >+/* 1869 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 1887 >+/* 1873 */ MCD_OPC_CheckPredicate, 1, 214, 44, // Skip to: 13355 >+/* 1877 */ MCD_OPC_CheckField, 16, 5, 0, 208, 44, // Skip to: 13355 >+/* 1883 */ MCD_OPC_Decode, 238, 5, 71, // Opcode: FMOV_S >+/* 1887 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 1905 >+/* 1891 */ MCD_OPC_CheckPredicate, 1, 196, 44, // Skip to: 13355 >+/* 1895 */ MCD_OPC_CheckField, 16, 5, 0, 190, 44, // Skip to: 13355 >+/* 1901 */ MCD_OPC_Decode, 252, 5, 71, // Opcode: FNEG_S >+/* 1905 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 1923 >+/* 1909 */ MCD_OPC_CheckPredicate, 2, 178, 44, // Skip to: 13355 >+/* 1913 */ MCD_OPC_CheckField, 16, 5, 0, 172, 44, // Skip to: 13355 >+/* 1919 */ MCD_OPC_Decode, 197, 10, 71, // Opcode: ROUND_W_S >+/* 1923 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 1941 >+/* 1927 */ MCD_OPC_CheckPredicate, 2, 160, 44, // Skip to: 13355 >+/* 1931 */ MCD_OPC_CheckField, 16, 5, 0, 154, 44, // Skip to: 13355 >+/* 1937 */ MCD_OPC_Decode, 145, 13, 71, // Opcode: TRUNC_W_S >+/* 1941 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 1959 >+/* 1945 */ MCD_OPC_CheckPredicate, 2, 142, 44, // Skip to: 13355 >+/* 1949 */ MCD_OPC_CheckField, 16, 5, 0, 136, 44, // Skip to: 13355 >+/* 1955 */ MCD_OPC_Decode, 208, 2, 71, // Opcode: CEIL_W_S >+/* 1959 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 1977 >+/* 1963 */ MCD_OPC_CheckPredicate, 2, 124, 44, // Skip to: 13355 >+/* 1967 */ MCD_OPC_CheckField, 16, 5, 0, 118, 44, // Skip to: 13355 >+/* 1973 */ MCD_OPC_Decode, 223, 5, 71, // Opcode: FLOOR_W_S >+/* 1977 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2008 >+/* 1981 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1984 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1996 >+/* 1988 */ MCD_OPC_CheckPredicate, 5, 99, 44, // Skip to: 13355 >+/* 1992 */ MCD_OPC_Decode, 203, 8, 72, // Opcode: MOVF_S >+/* 1996 */ MCD_OPC_FilterValue, 1, 91, 44, // Skip to: 13355 >+/* 2000 */ MCD_OPC_CheckPredicate, 5, 87, 44, // Skip to: 13355 >+/* 2004 */ MCD_OPC_Decode, 223, 8, 72, // Opcode: MOVT_S >+/* 2008 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2020 >+/* 2012 */ MCD_OPC_CheckPredicate, 5, 75, 44, // Skip to: 13355 >+/* 2016 */ MCD_OPC_Decode, 235, 8, 73, // Opcode: MOVZ_I_S >+/* 2020 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2032 >+/* 2024 */ MCD_OPC_CheckPredicate, 5, 63, 44, // Skip to: 13355 >+/* 2028 */ MCD_OPC_Decode, 215, 8, 73, // Opcode: MOVN_I_S >+/* 2032 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2050 >+/* 2036 */ MCD_OPC_CheckPredicate, 19, 51, 44, // Skip to: 13355 >+/* 2040 */ MCD_OPC_CheckField, 16, 5, 0, 45, 44, // Skip to: 13355 >+/* 2046 */ MCD_OPC_Decode, 193, 3, 74, // Opcode: CVT_D32_S >+/* 2050 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2068 >+/* 2054 */ MCD_OPC_CheckPredicate, 1, 33, 44, // Skip to: 13355 >+/* 2058 */ MCD_OPC_CheckField, 16, 5, 0, 27, 44, // Skip to: 13355 >+/* 2064 */ MCD_OPC_Decode, 213, 3, 71, // Opcode: CVT_W_S >+/* 2068 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2086 >+/* 2072 */ MCD_OPC_CheckPredicate, 20, 15, 44, // Skip to: 13355 >+/* 2076 */ MCD_OPC_CheckField, 16, 5, 0, 9, 44, // Skip to: 13355 >+/* 2082 */ MCD_OPC_Decode, 202, 3, 75, // Opcode: CVT_L_S >+/* 2086 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2104 >+/* 2090 */ MCD_OPC_CheckPredicate, 12, 253, 43, // Skip to: 13355 >+/* 2094 */ MCD_OPC_CheckField, 6, 5, 0, 247, 43, // Skip to: 13355 >+/* 2100 */ MCD_OPC_Decode, 220, 3, 76, // Opcode: C_F_S >+/* 2104 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2122 >+/* 2108 */ MCD_OPC_CheckPredicate, 12, 235, 43, // Skip to: 13355 >+/* 2112 */ MCD_OPC_CheckField, 6, 5, 0, 229, 43, // Skip to: 13355 >+/* 2118 */ MCD_OPC_Decode, 134, 4, 76, // Opcode: C_UN_S >+/* 2122 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2140 >+/* 2126 */ MCD_OPC_CheckPredicate, 12, 217, 43, // Skip to: 13355 >+/* 2130 */ MCD_OPC_CheckField, 6, 5, 0, 211, 43, // Skip to: 13355 >+/* 2136 */ MCD_OPC_Decode, 217, 3, 76, // Opcode: C_EQ_S >+/* 2140 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2158 >+/* 2144 */ MCD_OPC_CheckPredicate, 12, 199, 43, // Skip to: 13355 >+/* 2148 */ MCD_OPC_CheckField, 6, 5, 0, 193, 43, // Skip to: 13355 >+/* 2154 */ MCD_OPC_Decode, 253, 3, 76, // Opcode: C_UEQ_S >+/* 2158 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2176 >+/* 2162 */ MCD_OPC_CheckPredicate, 12, 181, 43, // Skip to: 13355 >+/* 2166 */ MCD_OPC_CheckField, 6, 5, 0, 175, 43, // Skip to: 13355 >+/* 2172 */ MCD_OPC_Decode, 244, 3, 76, // Opcode: C_OLT_S >+/* 2176 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2194 >+/* 2180 */ MCD_OPC_CheckPredicate, 12, 163, 43, // Skip to: 13355 >+/* 2184 */ MCD_OPC_CheckField, 6, 5, 0, 157, 43, // Skip to: 13355 >+/* 2190 */ MCD_OPC_Decode, 131, 4, 76, // Opcode: C_ULT_S >+/* 2194 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2212 >+/* 2198 */ MCD_OPC_CheckPredicate, 12, 145, 43, // Skip to: 13355 >+/* 2202 */ MCD_OPC_CheckField, 6, 5, 0, 139, 43, // Skip to: 13355 >+/* 2208 */ MCD_OPC_Decode, 241, 3, 76, // Opcode: C_OLE_S >+/* 2212 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2230 >+/* 2216 */ MCD_OPC_CheckPredicate, 12, 127, 43, // Skip to: 13355 >+/* 2220 */ MCD_OPC_CheckField, 6, 5, 0, 121, 43, // Skip to: 13355 >+/* 2226 */ MCD_OPC_Decode, 128, 4, 76, // Opcode: C_ULE_S >+/* 2230 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2248 >+/* 2234 */ MCD_OPC_CheckPredicate, 12, 109, 43, // Skip to: 13355 >+/* 2238 */ MCD_OPC_CheckField, 6, 5, 0, 103, 43, // Skip to: 13355 >+/* 2244 */ MCD_OPC_Decode, 250, 3, 76, // Opcode: C_SF_S >+/* 2248 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2266 >+/* 2252 */ MCD_OPC_CheckPredicate, 12, 91, 43, // Skip to: 13355 >+/* 2256 */ MCD_OPC_CheckField, 6, 5, 0, 85, 43, // Skip to: 13355 >+/* 2262 */ MCD_OPC_Decode, 232, 3, 76, // Opcode: C_NGLE_S >+/* 2266 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2284 >+/* 2270 */ MCD_OPC_CheckPredicate, 12, 73, 43, // Skip to: 13355 >+/* 2274 */ MCD_OPC_CheckField, 6, 5, 0, 67, 43, // Skip to: 13355 >+/* 2280 */ MCD_OPC_Decode, 247, 3, 76, // Opcode: C_SEQ_S >+/* 2284 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2302 >+/* 2288 */ MCD_OPC_CheckPredicate, 12, 55, 43, // Skip to: 13355 >+/* 2292 */ MCD_OPC_CheckField, 6, 5, 0, 49, 43, // Skip to: 13355 >+/* 2298 */ MCD_OPC_Decode, 235, 3, 76, // Opcode: C_NGL_S >+/* 2302 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2320 >+/* 2306 */ MCD_OPC_CheckPredicate, 12, 37, 43, // Skip to: 13355 >+/* 2310 */ MCD_OPC_CheckField, 6, 5, 0, 31, 43, // Skip to: 13355 >+/* 2316 */ MCD_OPC_Decode, 226, 3, 76, // Opcode: C_LT_S >+/* 2320 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2338 >+/* 2324 */ MCD_OPC_CheckPredicate, 12, 19, 43, // Skip to: 13355 >+/* 2328 */ MCD_OPC_CheckField, 6, 5, 0, 13, 43, // Skip to: 13355 >+/* 2334 */ MCD_OPC_Decode, 229, 3, 76, // Opcode: C_NGE_S >+/* 2338 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2356 >+/* 2342 */ MCD_OPC_CheckPredicate, 12, 1, 43, // Skip to: 13355 >+/* 2346 */ MCD_OPC_CheckField, 6, 5, 0, 251, 42, // Skip to: 13355 >+/* 2352 */ MCD_OPC_Decode, 223, 3, 76, // Opcode: C_LE_S >+/* 2356 */ MCD_OPC_FilterValue, 63, 243, 42, // Skip to: 13355 >+/* 2360 */ MCD_OPC_CheckPredicate, 12, 239, 42, // Skip to: 13355 >+/* 2364 */ MCD_OPC_CheckField, 6, 5, 0, 233, 42, // Skip to: 13355 >+/* 2370 */ MCD_OPC_Decode, 238, 3, 76, // Opcode: C_NGT_S >+/* 2374 */ MCD_OPC_FilterValue, 17, 80, 2, // Skip to: 2970 >+/* 2378 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2381 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2393 >+/* 2385 */ MCD_OPC_CheckPredicate, 19, 214, 42, // Skip to: 13355 >+/* 2389 */ MCD_OPC_Decode, 150, 5, 77, // Opcode: FADD_D32 >+/* 2393 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2405 >+/* 2397 */ MCD_OPC_CheckPredicate, 19, 202, 42, // Skip to: 13355 >+/* 2401 */ MCD_OPC_Decode, 152, 6, 77, // Opcode: FSUB_D32 >+/* 2405 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2417 >+/* 2409 */ MCD_OPC_CheckPredicate, 19, 190, 42, // Skip to: 13355 >+/* 2413 */ MCD_OPC_Decode, 243, 5, 77, // Opcode: FMUL_D32 >+/* 2417 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2429 >+/* 2421 */ MCD_OPC_CheckPredicate, 19, 178, 42, // Skip to: 13355 >+/* 2425 */ MCD_OPC_Decode, 186, 5, 77, // Opcode: FDIV_D32 >+/* 2429 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 2447 >+/* 2433 */ MCD_OPC_CheckPredicate, 21, 166, 42, // Skip to: 13355 >+/* 2437 */ MCD_OPC_CheckField, 16, 5, 0, 160, 42, // Skip to: 13355 >+/* 2443 */ MCD_OPC_Decode, 145, 6, 78, // Opcode: FSQRT_D32 >+/* 2447 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 2465 >+/* 2451 */ MCD_OPC_CheckPredicate, 19, 148, 42, // Skip to: 13355 >+/* 2455 */ MCD_OPC_CheckField, 16, 5, 0, 142, 42, // Skip to: 13355 >+/* 2461 */ MCD_OPC_Decode, 143, 5, 78, // Opcode: FABS_D32 >+/* 2465 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 2483 >+/* 2469 */ MCD_OPC_CheckPredicate, 19, 130, 42, // Skip to: 13355 >+/* 2473 */ MCD_OPC_CheckField, 16, 5, 0, 124, 42, // Skip to: 13355 >+/* 2479 */ MCD_OPC_Decode, 235, 5, 78, // Opcode: FMOV_D32 >+/* 2483 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 2501 >+/* 2487 */ MCD_OPC_CheckPredicate, 19, 112, 42, // Skip to: 13355 >+/* 2491 */ MCD_OPC_CheckField, 16, 5, 0, 106, 42, // Skip to: 13355 >+/* 2497 */ MCD_OPC_Decode, 249, 5, 78, // Opcode: FNEG_D32 >+/* 2501 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 2519 >+/* 2505 */ MCD_OPC_CheckPredicate, 21, 94, 42, // Skip to: 13355 >+/* 2509 */ MCD_OPC_CheckField, 16, 5, 0, 88, 42, // Skip to: 13355 >+/* 2515 */ MCD_OPC_Decode, 194, 10, 79, // Opcode: ROUND_W_D32 >+/* 2519 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 2537 >+/* 2523 */ MCD_OPC_CheckPredicate, 21, 76, 42, // Skip to: 13355 >+/* 2527 */ MCD_OPC_CheckField, 16, 5, 0, 70, 42, // Skip to: 13355 >+/* 2533 */ MCD_OPC_Decode, 142, 13, 79, // Opcode: TRUNC_W_D32 >+/* 2537 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 2555 >+/* 2541 */ MCD_OPC_CheckPredicate, 21, 58, 42, // Skip to: 13355 >+/* 2545 */ MCD_OPC_CheckField, 16, 5, 0, 52, 42, // Skip to: 13355 >+/* 2551 */ MCD_OPC_Decode, 205, 2, 79, // Opcode: CEIL_W_D32 >+/* 2555 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 2573 >+/* 2559 */ MCD_OPC_CheckPredicate, 21, 40, 42, // Skip to: 13355 >+/* 2563 */ MCD_OPC_CheckField, 16, 5, 0, 34, 42, // Skip to: 13355 >+/* 2569 */ MCD_OPC_Decode, 220, 5, 79, // Opcode: FLOOR_W_D32 >+/* 2573 */ MCD_OPC_FilterValue, 17, 27, 0, // Skip to: 2604 >+/* 2577 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 2580 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2592 >+/* 2584 */ MCD_OPC_CheckPredicate, 22, 15, 42, // Skip to: 13355 >+/* 2588 */ MCD_OPC_Decode, 197, 8, 80, // Opcode: MOVF_D32 >+/* 2592 */ MCD_OPC_FilterValue, 1, 7, 42, // Skip to: 13355 >+/* 2596 */ MCD_OPC_CheckPredicate, 22, 3, 42, // Skip to: 13355 >+/* 2600 */ MCD_OPC_Decode, 217, 8, 80, // Opcode: MOVT_D32 >+/* 2604 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2616 >+/* 2608 */ MCD_OPC_CheckPredicate, 22, 247, 41, // Skip to: 13355 >+/* 2612 */ MCD_OPC_Decode, 229, 8, 81, // Opcode: MOVZ_I_D32 >+/* 2616 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2628 >+/* 2620 */ MCD_OPC_CheckPredicate, 22, 235, 41, // Skip to: 13355 >+/* 2624 */ MCD_OPC_Decode, 209, 8, 81, // Opcode: MOVN_I_D32 >+/* 2628 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2646 >+/* 2632 */ MCD_OPC_CheckPredicate, 19, 223, 41, // Skip to: 13355 >+/* 2636 */ MCD_OPC_CheckField, 16, 5, 0, 217, 41, // Skip to: 13355 >+/* 2642 */ MCD_OPC_Decode, 204, 3, 79, // Opcode: CVT_S_D32 >+/* 2646 */ MCD_OPC_FilterValue, 36, 14, 0, // Skip to: 2664 >+/* 2650 */ MCD_OPC_CheckPredicate, 19, 205, 41, // Skip to: 13355 >+/* 2654 */ MCD_OPC_CheckField, 16, 5, 0, 199, 41, // Skip to: 13355 >+/* 2660 */ MCD_OPC_Decode, 210, 3, 79, // Opcode: CVT_W_D32 >+/* 2664 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 2682 >+/* 2668 */ MCD_OPC_CheckPredicate, 20, 187, 41, // Skip to: 13355 >+/* 2672 */ MCD_OPC_CheckField, 16, 5, 0, 181, 41, // Skip to: 13355 >+/* 2678 */ MCD_OPC_Decode, 200, 3, 82, // Opcode: CVT_L_D64 >+/* 2682 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 2700 >+/* 2686 */ MCD_OPC_CheckPredicate, 23, 169, 41, // Skip to: 13355 >+/* 2690 */ MCD_OPC_CheckField, 6, 5, 0, 163, 41, // Skip to: 13355 >+/* 2696 */ MCD_OPC_Decode, 218, 3, 83, // Opcode: C_F_D32 >+/* 2700 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 2718 >+/* 2704 */ MCD_OPC_CheckPredicate, 23, 151, 41, // Skip to: 13355 >+/* 2708 */ MCD_OPC_CheckField, 6, 5, 0, 145, 41, // Skip to: 13355 >+/* 2714 */ MCD_OPC_Decode, 132, 4, 83, // Opcode: C_UN_D32 >+/* 2718 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 2736 >+/* 2722 */ MCD_OPC_CheckPredicate, 23, 133, 41, // Skip to: 13355 >+/* 2726 */ MCD_OPC_CheckField, 6, 5, 0, 127, 41, // Skip to: 13355 >+/* 2732 */ MCD_OPC_Decode, 215, 3, 83, // Opcode: C_EQ_D32 >+/* 2736 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 2754 >+/* 2740 */ MCD_OPC_CheckPredicate, 23, 115, 41, // Skip to: 13355 >+/* 2744 */ MCD_OPC_CheckField, 6, 5, 0, 109, 41, // Skip to: 13355 >+/* 2750 */ MCD_OPC_Decode, 251, 3, 83, // Opcode: C_UEQ_D32 >+/* 2754 */ MCD_OPC_FilterValue, 52, 14, 0, // Skip to: 2772 >+/* 2758 */ MCD_OPC_CheckPredicate, 23, 97, 41, // Skip to: 13355 >+/* 2762 */ MCD_OPC_CheckField, 6, 5, 0, 91, 41, // Skip to: 13355 >+/* 2768 */ MCD_OPC_Decode, 242, 3, 83, // Opcode: C_OLT_D32 >+/* 2772 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 2790 >+/* 2776 */ MCD_OPC_CheckPredicate, 23, 79, 41, // Skip to: 13355 >+/* 2780 */ MCD_OPC_CheckField, 6, 5, 0, 73, 41, // Skip to: 13355 >+/* 2786 */ MCD_OPC_Decode, 129, 4, 83, // Opcode: C_ULT_D32 >+/* 2790 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 2808 >+/* 2794 */ MCD_OPC_CheckPredicate, 23, 61, 41, // Skip to: 13355 >+/* 2798 */ MCD_OPC_CheckField, 6, 5, 0, 55, 41, // Skip to: 13355 >+/* 2804 */ MCD_OPC_Decode, 239, 3, 83, // Opcode: C_OLE_D32 >+/* 2808 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 2826 >+/* 2812 */ MCD_OPC_CheckPredicate, 23, 43, 41, // Skip to: 13355 >+/* 2816 */ MCD_OPC_CheckField, 6, 5, 0, 37, 41, // Skip to: 13355 >+/* 2822 */ MCD_OPC_Decode, 254, 3, 83, // Opcode: C_ULE_D32 >+/* 2826 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 2844 >+/* 2830 */ MCD_OPC_CheckPredicate, 23, 25, 41, // Skip to: 13355 >+/* 2834 */ MCD_OPC_CheckField, 6, 5, 0, 19, 41, // Skip to: 13355 >+/* 2840 */ MCD_OPC_Decode, 248, 3, 83, // Opcode: C_SF_D32 >+/* 2844 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 2862 >+/* 2848 */ MCD_OPC_CheckPredicate, 23, 7, 41, // Skip to: 13355 >+/* 2852 */ MCD_OPC_CheckField, 6, 5, 0, 1, 41, // Skip to: 13355 >+/* 2858 */ MCD_OPC_Decode, 230, 3, 83, // Opcode: C_NGLE_D32 >+/* 2862 */ MCD_OPC_FilterValue, 58, 14, 0, // Skip to: 2880 >+/* 2866 */ MCD_OPC_CheckPredicate, 23, 245, 40, // Skip to: 13355 >+/* 2870 */ MCD_OPC_CheckField, 6, 5, 0, 239, 40, // Skip to: 13355 >+/* 2876 */ MCD_OPC_Decode, 245, 3, 83, // Opcode: C_SEQ_D32 >+/* 2880 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 2898 >+/* 2884 */ MCD_OPC_CheckPredicate, 23, 227, 40, // Skip to: 13355 >+/* 2888 */ MCD_OPC_CheckField, 6, 5, 0, 221, 40, // Skip to: 13355 >+/* 2894 */ MCD_OPC_Decode, 233, 3, 83, // Opcode: C_NGL_D32 >+/* 2898 */ MCD_OPC_FilterValue, 60, 14, 0, // Skip to: 2916 >+/* 2902 */ MCD_OPC_CheckPredicate, 23, 209, 40, // Skip to: 13355 >+/* 2906 */ MCD_OPC_CheckField, 6, 5, 0, 203, 40, // Skip to: 13355 >+/* 2912 */ MCD_OPC_Decode, 224, 3, 83, // Opcode: C_LT_D32 >+/* 2916 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 2934 >+/* 2920 */ MCD_OPC_CheckPredicate, 23, 191, 40, // Skip to: 13355 >+/* 2924 */ MCD_OPC_CheckField, 6, 5, 0, 185, 40, // Skip to: 13355 >+/* 2930 */ MCD_OPC_Decode, 227, 3, 83, // Opcode: C_NGE_D32 >+/* 2934 */ MCD_OPC_FilterValue, 62, 14, 0, // Skip to: 2952 >+/* 2938 */ MCD_OPC_CheckPredicate, 23, 173, 40, // Skip to: 13355 >+/* 2942 */ MCD_OPC_CheckField, 6, 5, 0, 167, 40, // Skip to: 13355 >+/* 2948 */ MCD_OPC_Decode, 221, 3, 83, // Opcode: C_LE_D32 >+/* 2952 */ MCD_OPC_FilterValue, 63, 159, 40, // Skip to: 13355 >+/* 2956 */ MCD_OPC_CheckPredicate, 23, 155, 40, // Skip to: 13355 >+/* 2960 */ MCD_OPC_CheckField, 6, 5, 0, 149, 40, // Skip to: 13355 >+/* 2966 */ MCD_OPC_Decode, 236, 3, 83, // Opcode: C_NGT_D32 >+/* 2970 */ MCD_OPC_FilterValue, 20, 39, 0, // Skip to: 3013 >+/* 2974 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2977 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2995 >+/* 2981 */ MCD_OPC_CheckPredicate, 1, 130, 40, // Skip to: 13355 >+/* 2985 */ MCD_OPC_CheckField, 16, 5, 0, 124, 40, // Skip to: 13355 >+/* 2991 */ MCD_OPC_Decode, 208, 3, 71, // Opcode: CVT_S_W >+/* 2995 */ MCD_OPC_FilterValue, 33, 116, 40, // Skip to: 13355 >+/* 2999 */ MCD_OPC_CheckPredicate, 19, 112, 40, // Skip to: 13355 >+/* 3003 */ MCD_OPC_CheckField, 16, 5, 0, 106, 40, // Skip to: 13355 >+/* 3009 */ MCD_OPC_Decode, 194, 3, 74, // Opcode: CVT_D32_W >+/* 3013 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 3025 >+/* 3017 */ MCD_OPC_CheckPredicate, 6, 94, 40, // Skip to: 13355 >+/* 3021 */ MCD_OPC_Decode, 171, 2, 69, // Opcode: BZ_B >+/* 3025 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 3037 >+/* 3029 */ MCD_OPC_CheckPredicate, 6, 82, 40, // Skip to: 13355 >+/* 3033 */ MCD_OPC_Decode, 173, 2, 84, // Opcode: BZ_H >+/* 3037 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 3049 >+/* 3041 */ MCD_OPC_CheckPredicate, 6, 70, 40, // Skip to: 13355 >+/* 3045 */ MCD_OPC_Decode, 175, 2, 85, // Opcode: BZ_W >+/* 3049 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 3061 >+/* 3053 */ MCD_OPC_CheckPredicate, 6, 58, 40, // Skip to: 13355 >+/* 3057 */ MCD_OPC_Decode, 172, 2, 86, // Opcode: BZ_D >+/* 3061 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 3073 >+/* 3065 */ MCD_OPC_CheckPredicate, 6, 46, 40, // Skip to: 13355 >+/* 3069 */ MCD_OPC_Decode, 146, 2, 69, // Opcode: BNZ_B >+/* 3073 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3085 >+/* 3077 */ MCD_OPC_CheckPredicate, 6, 34, 40, // Skip to: 13355 >+/* 3081 */ MCD_OPC_Decode, 148, 2, 84, // Opcode: BNZ_H >+/* 3085 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 3097 >+/* 3089 */ MCD_OPC_CheckPredicate, 6, 22, 40, // Skip to: 13355 >+/* 3093 */ MCD_OPC_Decode, 150, 2, 85, // Opcode: BNZ_W >+/* 3097 */ MCD_OPC_FilterValue, 31, 14, 40, // Skip to: 13355 >+/* 3101 */ MCD_OPC_CheckPredicate, 6, 10, 40, // Skip to: 13355 >+/* 3105 */ MCD_OPC_Decode, 147, 2, 86, // Opcode: BNZ_D >+/* 3109 */ MCD_OPC_FilterValue, 18, 94, 0, // Skip to: 3207 >+/* 3113 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3116 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3134 >+/* 3120 */ MCD_OPC_CheckPredicate, 1, 247, 39, // Skip to: 13355 >+/* 3124 */ MCD_OPC_CheckField, 3, 8, 0, 241, 39, // Skip to: 13355 >+/* 3130 */ MCD_OPC_Decode, 144, 8, 58, // Opcode: MFC2 >+/* 3134 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 3152 >+/* 3138 */ MCD_OPC_CheckPredicate, 1, 229, 39, // Skip to: 13355 >+/* 3142 */ MCD_OPC_CheckField, 3, 8, 0, 223, 39, // Skip to: 13355 >+/* 3148 */ MCD_OPC_Decode, 133, 9, 58, // Opcode: MTC2 >+/* 3152 */ MCD_OPC_FilterValue, 8, 215, 39, // Skip to: 13355 >+/* 3156 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 3159 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3171 >+/* 3163 */ MCD_OPC_CheckPredicate, 12, 204, 39, // Skip to: 13355 >+/* 3167 */ MCD_OPC_Decode, 174, 1, 59, // Opcode: BC2F >+/* 3171 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3183 >+/* 3175 */ MCD_OPC_CheckPredicate, 12, 192, 39, // Skip to: 13355 >+/* 3179 */ MCD_OPC_Decode, 177, 1, 59, // Opcode: BC2T >+/* 3183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3195 >+/* 3187 */ MCD_OPC_CheckPredicate, 12, 180, 39, // Skip to: 13355 >+/* 3191 */ MCD_OPC_Decode, 175, 1, 59, // Opcode: BC2FL >+/* 3195 */ MCD_OPC_FilterValue, 3, 172, 39, // Skip to: 13355 >+/* 3199 */ MCD_OPC_CheckPredicate, 12, 168, 39, // Skip to: 13355 >+/* 3203 */ MCD_OPC_Decode, 178, 1, 59, // Opcode: BC2TL >+/* 3207 */ MCD_OPC_FilterValue, 19, 9, 1, // Skip to: 3476 >+/* 3211 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3214 */ MCD_OPC_FilterValue, 8, 51, 0, // Skip to: 3269 >+/* 3218 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 3221 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3233 >+/* 3225 */ MCD_OPC_CheckPredicate, 12, 40, 0, // Skip to: 3269 >+/* 3229 */ MCD_OPC_Decode, 179, 1, 59, // Opcode: BC3F >+/* 3233 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3245 >+/* 3237 */ MCD_OPC_CheckPredicate, 12, 28, 0, // Skip to: 3269 >+/* 3241 */ MCD_OPC_Decode, 181, 1, 59, // Opcode: BC3T >+/* 3245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3257 >+/* 3249 */ MCD_OPC_CheckPredicate, 12, 16, 0, // Skip to: 3269 >+/* 3253 */ MCD_OPC_Decode, 180, 1, 59, // Opcode: BC3FL >+/* 3257 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 3269 >+/* 3261 */ MCD_OPC_CheckPredicate, 12, 4, 0, // Skip to: 3269 >+/* 3265 */ MCD_OPC_Decode, 182, 1, 59, // Opcode: BC3TL >+/* 3269 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3272 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3290 >+/* 3276 */ MCD_OPC_CheckPredicate, 24, 91, 39, // Skip to: 13355 >+/* 3280 */ MCD_OPC_CheckField, 11, 5, 0, 85, 39, // Skip to: 13355 >+/* 3286 */ MCD_OPC_Decode, 200, 7, 87, // Opcode: LWXC1 >+/* 3290 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3308 >+/* 3294 */ MCD_OPC_CheckPredicate, 25, 73, 39, // Skip to: 13355 >+/* 3298 */ MCD_OPC_CheckField, 11, 5, 0, 67, 39, // Skip to: 13355 >+/* 3304 */ MCD_OPC_Decode, 147, 7, 88, // Opcode: LDXC1 >+/* 3308 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 3326 >+/* 3312 */ MCD_OPC_CheckPredicate, 26, 55, 39, // Skip to: 13355 >+/* 3316 */ MCD_OPC_CheckField, 11, 5, 0, 49, 39, // Skip to: 13355 >+/* 3322 */ MCD_OPC_Decode, 177, 7, 88, // Opcode: LUXC1 >+/* 3326 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3344 >+/* 3330 */ MCD_OPC_CheckPredicate, 24, 37, 39, // Skip to: 13355 >+/* 3334 */ MCD_OPC_CheckField, 6, 5, 0, 31, 39, // Skip to: 13355 >+/* 3340 */ MCD_OPC_Decode, 181, 12, 89, // Opcode: SWXC1 >+/* 3344 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3362 >+/* 3348 */ MCD_OPC_CheckPredicate, 25, 19, 39, // Skip to: 13355 >+/* 3352 */ MCD_OPC_CheckField, 6, 5, 0, 13, 39, // Skip to: 13355 >+/* 3358 */ MCD_OPC_Decode, 232, 10, 90, // Opcode: SDXC1 >+/* 3362 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 3380 >+/* 3366 */ MCD_OPC_CheckPredicate, 26, 1, 39, // Skip to: 13355 >+/* 3370 */ MCD_OPC_CheckField, 6, 5, 0, 251, 38, // Skip to: 13355 >+/* 3376 */ MCD_OPC_Decode, 165, 12, 90, // Opcode: SUXC1 >+/* 3380 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 3392 >+/* 3384 */ MCD_OPC_CheckPredicate, 27, 239, 38, // Skip to: 13355 >+/* 3388 */ MCD_OPC_Decode, 239, 7, 91, // Opcode: MADD_S >+/* 3392 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 3404 >+/* 3396 */ MCD_OPC_CheckPredicate, 28, 227, 38, // Skip to: 13355 >+/* 3400 */ MCD_OPC_Decode, 232, 7, 92, // Opcode: MADD_D32 >+/* 3404 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 3416 >+/* 3408 */ MCD_OPC_CheckPredicate, 27, 215, 38, // Skip to: 13355 >+/* 3412 */ MCD_OPC_Decode, 128, 9, 91, // Opcode: MSUB_S >+/* 3416 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 3428 >+/* 3420 */ MCD_OPC_CheckPredicate, 28, 203, 38, // Skip to: 13355 >+/* 3424 */ MCD_OPC_Decode, 249, 8, 92, // Opcode: MSUB_D32 >+/* 3428 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 3440 >+/* 3432 */ MCD_OPC_CheckPredicate, 27, 191, 38, // Skip to: 13355 >+/* 3436 */ MCD_OPC_Decode, 203, 9, 91, // Opcode: NMADD_S >+/* 3440 */ MCD_OPC_FilterValue, 49, 8, 0, // Skip to: 3452 >+/* 3444 */ MCD_OPC_CheckPredicate, 28, 179, 38, // Skip to: 13355 >+/* 3448 */ MCD_OPC_Decode, 200, 9, 92, // Opcode: NMADD_D32 >+/* 3452 */ MCD_OPC_FilterValue, 56, 8, 0, // Skip to: 3464 >+/* 3456 */ MCD_OPC_CheckPredicate, 27, 167, 38, // Skip to: 13355 >+/* 3460 */ MCD_OPC_Decode, 208, 9, 91, // Opcode: NMSUB_S >+/* 3464 */ MCD_OPC_FilterValue, 57, 159, 38, // Skip to: 13355 >+/* 3468 */ MCD_OPC_CheckPredicate, 28, 155, 38, // Skip to: 13355 >+/* 3472 */ MCD_OPC_Decode, 205, 9, 92, // Opcode: NMSUB_D32 >+/* 3476 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 3488 >+/* 3480 */ MCD_OPC_CheckPredicate, 1, 143, 38, // Skip to: 13355 >+/* 3484 */ MCD_OPC_Decode, 194, 1, 55, // Opcode: BEQL >+/* 3488 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 3500 >+/* 3492 */ MCD_OPC_CheckPredicate, 1, 131, 38, // Skip to: 13355 >+/* 3496 */ MCD_OPC_Decode, 140, 2, 55, // Opcode: BNEL >+/* 3500 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 3518 >+/* 3504 */ MCD_OPC_CheckPredicate, 1, 119, 38, // Skip to: 13355 >+/* 3508 */ MCD_OPC_CheckField, 16, 5, 0, 113, 38, // Skip to: 13355 >+/* 3514 */ MCD_OPC_Decode, 239, 1, 51, // Opcode: BLEZL >+/* 3518 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 3536 >+/* 3522 */ MCD_OPC_CheckPredicate, 1, 101, 38, // Skip to: 13355 >+/* 3526 */ MCD_OPC_CheckField, 16, 5, 0, 95, 38, // Skip to: 13355 >+/* 3532 */ MCD_OPC_Decode, 215, 1, 51, // Opcode: BGTZL >+/* 3536 */ MCD_OPC_FilterValue, 28, 229, 0, // Skip to: 3769 >+/* 3540 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3543 */ MCD_OPC_FilterValue, 0, 36, 0, // Skip to: 3583 >+/* 3547 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3550 */ MCD_OPC_FilterValue, 0, 73, 38, // Skip to: 13355 >+/* 3554 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3557 */ MCD_OPC_FilterValue, 0, 66, 38, // Skip to: 13355 >+/* 3561 */ MCD_OPC_CheckPredicate, 7, 10, 0, // Skip to: 3575 >+/* 3565 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3575 >+/* 3571 */ MCD_OPC_Decode, 220, 7, 24, // Opcode: MADD >+/* 3575 */ MCD_OPC_CheckPredicate, 11, 48, 38, // Skip to: 13355 >+/* 3579 */ MCD_OPC_Decode, 235, 7, 93, // Opcode: MADD_DSP >+/* 3583 */ MCD_OPC_FilterValue, 1, 36, 0, // Skip to: 3623 >+/* 3587 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3590 */ MCD_OPC_FilterValue, 0, 33, 38, // Skip to: 13355 >+/* 3594 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3597 */ MCD_OPC_FilterValue, 0, 26, 38, // Skip to: 13355 >+/* 3601 */ MCD_OPC_CheckPredicate, 7, 10, 0, // Skip to: 3615 >+/* 3605 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3615 >+/* 3611 */ MCD_OPC_Decode, 225, 7, 24, // Opcode: MADDU >+/* 3615 */ MCD_OPC_CheckPredicate, 11, 8, 38, // Skip to: 13355 >+/* 3619 */ MCD_OPC_Decode, 226, 7, 93, // Opcode: MADDU_DSP >+/* 3623 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3641 >+/* 3627 */ MCD_OPC_CheckPredicate, 7, 252, 37, // Skip to: 13355 >+/* 3631 */ MCD_OPC_CheckField, 6, 5, 0, 246, 37, // Skip to: 13355 >+/* 3637 */ MCD_OPC_Decode, 154, 9, 17, // Opcode: MUL >+/* 3641 */ MCD_OPC_FilterValue, 4, 36, 0, // Skip to: 3681 >+/* 3645 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3648 */ MCD_OPC_FilterValue, 0, 231, 37, // Skip to: 13355 >+/* 3652 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3655 */ MCD_OPC_FilterValue, 0, 224, 37, // Skip to: 13355 >+/* 3659 */ MCD_OPC_CheckPredicate, 7, 10, 0, // Skip to: 3673 >+/* 3663 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3673 >+/* 3669 */ MCD_OPC_Decode, 237, 8, 24, // Opcode: MSUB >+/* 3673 */ MCD_OPC_CheckPredicate, 11, 206, 37, // Skip to: 13355 >+/* 3677 */ MCD_OPC_Decode, 252, 8, 93, // Opcode: MSUB_DSP >+/* 3681 */ MCD_OPC_FilterValue, 5, 36, 0, // Skip to: 3721 >+/* 3685 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 3688 */ MCD_OPC_FilterValue, 0, 191, 37, // Skip to: 13355 >+/* 3692 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... >+/* 3695 */ MCD_OPC_FilterValue, 0, 184, 37, // Skip to: 13355 >+/* 3699 */ MCD_OPC_CheckPredicate, 7, 10, 0, // Skip to: 3713 >+/* 3703 */ MCD_OPC_CheckField, 11, 2, 0, 4, 0, // Skip to: 3713 >+/* 3709 */ MCD_OPC_Decode, 242, 8, 24, // Opcode: MSUBU >+/* 3713 */ MCD_OPC_CheckPredicate, 11, 166, 37, // Skip to: 13355 >+/* 3717 */ MCD_OPC_Decode, 243, 8, 93, // Opcode: MSUBU_DSP >+/* 3721 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3739 >+/* 3725 */ MCD_OPC_CheckPredicate, 7, 154, 37, // Skip to: 13355 >+/* 3729 */ MCD_OPC_CheckField, 6, 5, 0, 148, 37, // Skip to: 13355 >+/* 3735 */ MCD_OPC_Decode, 132, 3, 94, // Opcode: CLZ >+/* 3739 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3757 >+/* 3743 */ MCD_OPC_CheckPredicate, 7, 136, 37, // Skip to: 13355 >+/* 3747 */ MCD_OPC_CheckField, 6, 5, 0, 130, 37, // Skip to: 13355 >+/* 3753 */ MCD_OPC_Decode, 241, 2, 94, // Opcode: CLO >+/* 3757 */ MCD_OPC_FilterValue, 63, 122, 37, // Skip to: 13355 >+/* 3761 */ MCD_OPC_CheckPredicate, 7, 118, 37, // Skip to: 13355 >+/* 3765 */ MCD_OPC_Decode, 220, 10, 42, // Opcode: SDBBP >+/* 3769 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 3781 >+/* 3773 */ MCD_OPC_CheckPredicate, 7, 106, 37, // Skip to: 13355 >+/* 3777 */ MCD_OPC_Decode, 237, 6, 54, // Opcode: JALX >+/* 3781 */ MCD_OPC_FilterValue, 30, 181, 26, // Skip to: 10622 >+/* 3785 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 3788 */ MCD_OPC_FilterValue, 0, 50, 0, // Skip to: 3842 >+/* 3792 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3795 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3806 >+/* 3799 */ MCD_OPC_CheckPredicate, 6, 80, 37, // Skip to: 13355 >+/* 3803 */ MCD_OPC_Decode, 77, 95, // Opcode: ANDI_B >+/* 3806 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3818 >+/* 3810 */ MCD_OPC_CheckPredicate, 6, 69, 37, // Skip to: 13355 >+/* 3814 */ MCD_OPC_Decode, 223, 9, 95, // Opcode: ORI_B >+/* 3818 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 3830 >+/* 3822 */ MCD_OPC_CheckPredicate, 6, 57, 37, // Skip to: 13355 >+/* 3826 */ MCD_OPC_Decode, 213, 9, 95, // Opcode: NORI_B >+/* 3830 */ MCD_OPC_FilterValue, 3, 49, 37, // Skip to: 13355 >+/* 3834 */ MCD_OPC_CheckPredicate, 6, 45, 37, // Skip to: 13355 >+/* 3838 */ MCD_OPC_Decode, 164, 13, 95, // Opcode: XORI_B >+/* 3842 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 3885 >+/* 3846 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3849 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3861 >+/* 3853 */ MCD_OPC_CheckPredicate, 6, 26, 37, // Skip to: 13355 >+/* 3857 */ MCD_OPC_Decode, 253, 1, 96, // Opcode: BMNZI_B >+/* 3861 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3873 >+/* 3865 */ MCD_OPC_CheckPredicate, 6, 14, 37, // Skip to: 13355 >+/* 3869 */ MCD_OPC_Decode, 255, 1, 96, // Opcode: BMZI_B >+/* 3873 */ MCD_OPC_FilterValue, 2, 6, 37, // Skip to: 13355 >+/* 3877 */ MCD_OPC_CheckPredicate, 6, 2, 37, // Skip to: 13355 >+/* 3881 */ MCD_OPC_Decode, 156, 2, 96, // Opcode: BSELI_B >+/* 3885 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 3928 >+/* 3889 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... >+/* 3892 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 3904 >+/* 3896 */ MCD_OPC_CheckPredicate, 6, 239, 36, // Skip to: 13355 >+/* 3900 */ MCD_OPC_Decode, 254, 10, 95, // Opcode: SHF_B >+/* 3904 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 3916 >+/* 3908 */ MCD_OPC_CheckPredicate, 6, 227, 36, // Skip to: 13355 >+/* 3912 */ MCD_OPC_Decode, 255, 10, 97, // Opcode: SHF_H >+/* 3916 */ MCD_OPC_FilterValue, 2, 219, 36, // Skip to: 13355 >+/* 3920 */ MCD_OPC_CheckPredicate, 6, 215, 36, // Skip to: 13355 >+/* 3924 */ MCD_OPC_Decode, 128, 11, 98, // Opcode: SHF_W >+/* 3928 */ MCD_OPC_FilterValue, 6, 31, 1, // Skip to: 4219 >+/* 3932 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 3935 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 3946 >+/* 3939 */ MCD_OPC_CheckPredicate, 6, 196, 36, // Skip to: 13355 >+/* 3943 */ MCD_OPC_Decode, 51, 99, // Opcode: ADDVI_B >+/* 3946 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 3957 >+/* 3950 */ MCD_OPC_CheckPredicate, 6, 185, 36, // Skip to: 13355 >+/* 3954 */ MCD_OPC_Decode, 53, 100, // Opcode: ADDVI_H >+/* 3957 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 3968 >+/* 3961 */ MCD_OPC_CheckPredicate, 6, 174, 36, // Skip to: 13355 >+/* 3965 */ MCD_OPC_Decode, 54, 101, // Opcode: ADDVI_W >+/* 3968 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 3979 >+/* 3972 */ MCD_OPC_CheckPredicate, 6, 163, 36, // Skip to: 13355 >+/* 3976 */ MCD_OPC_Decode, 52, 102, // Opcode: ADDVI_D >+/* 3979 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 3991 >+/* 3983 */ MCD_OPC_CheckPredicate, 6, 152, 36, // Skip to: 13355 >+/* 3987 */ MCD_OPC_Decode, 154, 12, 99, // Opcode: SUBVI_B >+/* 3991 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 4003 >+/* 3995 */ MCD_OPC_CheckPredicate, 6, 140, 36, // Skip to: 13355 >+/* 3999 */ MCD_OPC_Decode, 156, 12, 100, // Opcode: SUBVI_H >+/* 4003 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4015 >+/* 4007 */ MCD_OPC_CheckPredicate, 6, 128, 36, // Skip to: 13355 >+/* 4011 */ MCD_OPC_Decode, 157, 12, 101, // Opcode: SUBVI_W >+/* 4015 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 4027 >+/* 4019 */ MCD_OPC_CheckPredicate, 6, 116, 36, // Skip to: 13355 >+/* 4023 */ MCD_OPC_Decode, 155, 12, 102, // Opcode: SUBVI_D >+/* 4027 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4039 >+/* 4031 */ MCD_OPC_CheckPredicate, 6, 104, 36, // Skip to: 13355 >+/* 4035 */ MCD_OPC_Decode, 247, 7, 99, // Opcode: MAXI_S_B >+/* 4039 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4051 >+/* 4043 */ MCD_OPC_CheckPredicate, 6, 92, 36, // Skip to: 13355 >+/* 4047 */ MCD_OPC_Decode, 249, 7, 100, // Opcode: MAXI_S_H >+/* 4051 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4063 >+/* 4055 */ MCD_OPC_CheckPredicate, 6, 80, 36, // Skip to: 13355 >+/* 4059 */ MCD_OPC_Decode, 250, 7, 101, // Opcode: MAXI_S_W >+/* 4063 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4075 >+/* 4067 */ MCD_OPC_CheckPredicate, 6, 68, 36, // Skip to: 13355 >+/* 4071 */ MCD_OPC_Decode, 248, 7, 102, // Opcode: MAXI_S_D >+/* 4075 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4087 >+/* 4079 */ MCD_OPC_CheckPredicate, 6, 56, 36, // Skip to: 13355 >+/* 4083 */ MCD_OPC_Decode, 251, 7, 99, // Opcode: MAXI_U_B >+/* 4087 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4099 >+/* 4091 */ MCD_OPC_CheckPredicate, 6, 44, 36, // Skip to: 13355 >+/* 4095 */ MCD_OPC_Decode, 253, 7, 100, // Opcode: MAXI_U_H >+/* 4099 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4111 >+/* 4103 */ MCD_OPC_CheckPredicate, 6, 32, 36, // Skip to: 13355 >+/* 4107 */ MCD_OPC_Decode, 254, 7, 101, // Opcode: MAXI_U_W >+/* 4111 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4123 >+/* 4115 */ MCD_OPC_CheckPredicate, 6, 20, 36, // Skip to: 13355 >+/* 4119 */ MCD_OPC_Decode, 252, 7, 102, // Opcode: MAXI_U_D >+/* 4123 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4135 >+/* 4127 */ MCD_OPC_CheckPredicate, 6, 8, 36, // Skip to: 13355 >+/* 4131 */ MCD_OPC_Decode, 160, 8, 99, // Opcode: MINI_S_B >+/* 4135 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4147 >+/* 4139 */ MCD_OPC_CheckPredicate, 6, 252, 35, // Skip to: 13355 >+/* 4143 */ MCD_OPC_Decode, 162, 8, 100, // Opcode: MINI_S_H >+/* 4147 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4159 >+/* 4151 */ MCD_OPC_CheckPredicate, 6, 240, 35, // Skip to: 13355 >+/* 4155 */ MCD_OPC_Decode, 163, 8, 101, // Opcode: MINI_S_W >+/* 4159 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4171 >+/* 4163 */ MCD_OPC_CheckPredicate, 6, 228, 35, // Skip to: 13355 >+/* 4167 */ MCD_OPC_Decode, 161, 8, 102, // Opcode: MINI_S_D >+/* 4171 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4183 >+/* 4175 */ MCD_OPC_CheckPredicate, 6, 216, 35, // Skip to: 13355 >+/* 4179 */ MCD_OPC_Decode, 164, 8, 99, // Opcode: MINI_U_B >+/* 4183 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4195 >+/* 4187 */ MCD_OPC_CheckPredicate, 6, 204, 35, // Skip to: 13355 >+/* 4191 */ MCD_OPC_Decode, 166, 8, 100, // Opcode: MINI_U_H >+/* 4195 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4207 >+/* 4199 */ MCD_OPC_CheckPredicate, 6, 192, 35, // Skip to: 13355 >+/* 4203 */ MCD_OPC_Decode, 167, 8, 101, // Opcode: MINI_U_W >+/* 4207 */ MCD_OPC_FilterValue, 23, 184, 35, // Skip to: 13355 >+/* 4211 */ MCD_OPC_CheckPredicate, 6, 180, 35, // Skip to: 13355 >+/* 4215 */ MCD_OPC_Decode, 165, 8, 102, // Opcode: MINI_U_D >+/* 4219 */ MCD_OPC_FilterValue, 7, 35, 1, // Skip to: 4514 >+/* 4223 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 4226 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4238 >+/* 4230 */ MCD_OPC_CheckPredicate, 6, 161, 35, // Skip to: 13355 >+/* 4234 */ MCD_OPC_Decode, 210, 2, 99, // Opcode: CEQI_B >+/* 4238 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 4250 >+/* 4242 */ MCD_OPC_CheckPredicate, 6, 149, 35, // Skip to: 13355 >+/* 4246 */ MCD_OPC_Decode, 212, 2, 100, // Opcode: CEQI_H >+/* 4250 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4262 >+/* 4254 */ MCD_OPC_CheckPredicate, 6, 137, 35, // Skip to: 13355 >+/* 4258 */ MCD_OPC_Decode, 213, 2, 101, // Opcode: CEQI_W >+/* 4262 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 4274 >+/* 4266 */ MCD_OPC_CheckPredicate, 6, 125, 35, // Skip to: 13355 >+/* 4270 */ MCD_OPC_Decode, 211, 2, 102, // Opcode: CEQI_D >+/* 4274 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4286 >+/* 4278 */ MCD_OPC_CheckPredicate, 6, 113, 35, // Skip to: 13355 >+/* 4282 */ MCD_OPC_Decode, 244, 2, 99, // Opcode: CLTI_S_B >+/* 4286 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 4298 >+/* 4290 */ MCD_OPC_CheckPredicate, 6, 101, 35, // Skip to: 13355 >+/* 4294 */ MCD_OPC_Decode, 246, 2, 100, // Opcode: CLTI_S_H >+/* 4298 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4310 >+/* 4302 */ MCD_OPC_CheckPredicate, 6, 89, 35, // Skip to: 13355 >+/* 4306 */ MCD_OPC_Decode, 247, 2, 101, // Opcode: CLTI_S_W >+/* 4310 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 4322 >+/* 4314 */ MCD_OPC_CheckPredicate, 6, 77, 35, // Skip to: 13355 >+/* 4318 */ MCD_OPC_Decode, 245, 2, 102, // Opcode: CLTI_S_D >+/* 4322 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4334 >+/* 4326 */ MCD_OPC_CheckPredicate, 6, 65, 35, // Skip to: 13355 >+/* 4330 */ MCD_OPC_Decode, 248, 2, 99, // Opcode: CLTI_U_B >+/* 4334 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 4346 >+/* 4338 */ MCD_OPC_CheckPredicate, 6, 53, 35, // Skip to: 13355 >+/* 4342 */ MCD_OPC_Decode, 250, 2, 100, // Opcode: CLTI_U_H >+/* 4346 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 4358 >+/* 4350 */ MCD_OPC_CheckPredicate, 6, 41, 35, // Skip to: 13355 >+/* 4354 */ MCD_OPC_Decode, 251, 2, 101, // Opcode: CLTI_U_W >+/* 4358 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 4370 >+/* 4362 */ MCD_OPC_CheckPredicate, 6, 29, 35, // Skip to: 13355 >+/* 4366 */ MCD_OPC_Decode, 249, 2, 102, // Opcode: CLTI_U_D >+/* 4370 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 4382 >+/* 4374 */ MCD_OPC_CheckPredicate, 6, 17, 35, // Skip to: 13355 >+/* 4378 */ MCD_OPC_Decode, 225, 2, 99, // Opcode: CLEI_S_B >+/* 4382 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 4394 >+/* 4386 */ MCD_OPC_CheckPredicate, 6, 5, 35, // Skip to: 13355 >+/* 4390 */ MCD_OPC_Decode, 227, 2, 100, // Opcode: CLEI_S_H >+/* 4394 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 4406 >+/* 4398 */ MCD_OPC_CheckPredicate, 6, 249, 34, // Skip to: 13355 >+/* 4402 */ MCD_OPC_Decode, 228, 2, 101, // Opcode: CLEI_S_W >+/* 4406 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 4418 >+/* 4410 */ MCD_OPC_CheckPredicate, 6, 237, 34, // Skip to: 13355 >+/* 4414 */ MCD_OPC_Decode, 226, 2, 102, // Opcode: CLEI_S_D >+/* 4418 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 4430 >+/* 4422 */ MCD_OPC_CheckPredicate, 6, 225, 34, // Skip to: 13355 >+/* 4426 */ MCD_OPC_Decode, 229, 2, 99, // Opcode: CLEI_U_B >+/* 4430 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 4442 >+/* 4434 */ MCD_OPC_CheckPredicate, 6, 213, 34, // Skip to: 13355 >+/* 4438 */ MCD_OPC_Decode, 231, 2, 100, // Opcode: CLEI_U_H >+/* 4442 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 4454 >+/* 4446 */ MCD_OPC_CheckPredicate, 6, 201, 34, // Skip to: 13355 >+/* 4450 */ MCD_OPC_Decode, 232, 2, 101, // Opcode: CLEI_U_W >+/* 4454 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 4466 >+/* 4458 */ MCD_OPC_CheckPredicate, 6, 189, 34, // Skip to: 13355 >+/* 4462 */ MCD_OPC_Decode, 230, 2, 102, // Opcode: CLEI_U_D >+/* 4466 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 4478 >+/* 4470 */ MCD_OPC_CheckPredicate, 6, 177, 34, // Skip to: 13355 >+/* 4474 */ MCD_OPC_Decode, 140, 7, 103, // Opcode: LDI_B >+/* 4478 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 4490 >+/* 4482 */ MCD_OPC_CheckPredicate, 6, 165, 34, // Skip to: 13355 >+/* 4486 */ MCD_OPC_Decode, 142, 7, 104, // Opcode: LDI_H >+/* 4490 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 4502 >+/* 4494 */ MCD_OPC_CheckPredicate, 6, 153, 34, // Skip to: 13355 >+/* 4498 */ MCD_OPC_Decode, 143, 7, 105, // Opcode: LDI_W >+/* 4502 */ MCD_OPC_FilterValue, 27, 145, 34, // Skip to: 13355 >+/* 4506 */ MCD_OPC_CheckPredicate, 6, 141, 34, // Skip to: 13355 >+/* 4510 */ MCD_OPC_Decode, 141, 7, 106, // Opcode: LDI_D >+/* 4514 */ MCD_OPC_FilterValue, 9, 35, 2, // Skip to: 5065 >+/* 4518 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 4521 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4533 >+/* 4525 */ MCD_OPC_CheckPredicate, 6, 122, 34, // Skip to: 13355 >+/* 4529 */ MCD_OPC_Decode, 166, 11, 107, // Opcode: SLLI_D >+/* 4533 */ MCD_OPC_FilterValue, 1, 52, 0, // Skip to: 4589 >+/* 4537 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4540 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4552 >+/* 4544 */ MCD_OPC_CheckPredicate, 6, 103, 34, // Skip to: 13355 >+/* 4548 */ MCD_OPC_Decode, 168, 11, 101, // Opcode: SLLI_W >+/* 4552 */ MCD_OPC_FilterValue, 1, 95, 34, // Skip to: 13355 >+/* 4556 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4559 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4571 >+/* 4563 */ MCD_OPC_CheckPredicate, 6, 84, 34, // Skip to: 13355 >+/* 4567 */ MCD_OPC_Decode, 167, 11, 108, // Opcode: SLLI_H >+/* 4571 */ MCD_OPC_FilterValue, 1, 76, 34, // Skip to: 13355 >+/* 4575 */ MCD_OPC_CheckPredicate, 6, 72, 34, // Skip to: 13355 >+/* 4579 */ MCD_OPC_CheckField, 19, 1, 0, 66, 34, // Skip to: 13355 >+/* 4585 */ MCD_OPC_Decode, 165, 11, 109, // Opcode: SLLI_B >+/* 4589 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 4601 >+/* 4593 */ MCD_OPC_CheckPredicate, 6, 54, 34, // Skip to: 13355 >+/* 4597 */ MCD_OPC_Decode, 205, 11, 107, // Opcode: SRAI_D >+/* 4601 */ MCD_OPC_FilterValue, 3, 52, 0, // Skip to: 4657 >+/* 4605 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4608 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4620 >+/* 4612 */ MCD_OPC_CheckPredicate, 6, 35, 34, // Skip to: 13355 >+/* 4616 */ MCD_OPC_Decode, 207, 11, 101, // Opcode: SRAI_W >+/* 4620 */ MCD_OPC_FilterValue, 1, 27, 34, // Skip to: 13355 >+/* 4624 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4627 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4639 >+/* 4631 */ MCD_OPC_CheckPredicate, 6, 16, 34, // Skip to: 13355 >+/* 4635 */ MCD_OPC_Decode, 206, 11, 108, // Opcode: SRAI_H >+/* 4639 */ MCD_OPC_FilterValue, 1, 8, 34, // Skip to: 13355 >+/* 4643 */ MCD_OPC_CheckPredicate, 6, 4, 34, // Skip to: 13355 >+/* 4647 */ MCD_OPC_CheckField, 19, 1, 0, 254, 33, // Skip to: 13355 >+/* 4653 */ MCD_OPC_Decode, 204, 11, 109, // Opcode: SRAI_B >+/* 4657 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 4669 >+/* 4661 */ MCD_OPC_CheckPredicate, 6, 242, 33, // Skip to: 13355 >+/* 4665 */ MCD_OPC_Decode, 225, 11, 107, // Opcode: SRLI_D >+/* 4669 */ MCD_OPC_FilterValue, 5, 52, 0, // Skip to: 4725 >+/* 4673 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4676 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4688 >+/* 4680 */ MCD_OPC_CheckPredicate, 6, 223, 33, // Skip to: 13355 >+/* 4684 */ MCD_OPC_Decode, 227, 11, 101, // Opcode: SRLI_W >+/* 4688 */ MCD_OPC_FilterValue, 1, 215, 33, // Skip to: 13355 >+/* 4692 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4695 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4707 >+/* 4699 */ MCD_OPC_CheckPredicate, 6, 204, 33, // Skip to: 13355 >+/* 4703 */ MCD_OPC_Decode, 226, 11, 108, // Opcode: SRLI_H >+/* 4707 */ MCD_OPC_FilterValue, 1, 196, 33, // Skip to: 13355 >+/* 4711 */ MCD_OPC_CheckPredicate, 6, 192, 33, // Skip to: 13355 >+/* 4715 */ MCD_OPC_CheckField, 19, 1, 0, 186, 33, // Skip to: 13355 >+/* 4721 */ MCD_OPC_Decode, 224, 11, 109, // Opcode: SRLI_B >+/* 4725 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 4737 >+/* 4729 */ MCD_OPC_CheckPredicate, 6, 174, 33, // Skip to: 13355 >+/* 4733 */ MCD_OPC_Decode, 184, 1, 107, // Opcode: BCLRI_D >+/* 4737 */ MCD_OPC_FilterValue, 7, 52, 0, // Skip to: 4793 >+/* 4741 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4744 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4756 >+/* 4748 */ MCD_OPC_CheckPredicate, 6, 155, 33, // Skip to: 13355 >+/* 4752 */ MCD_OPC_Decode, 186, 1, 101, // Opcode: BCLRI_W >+/* 4756 */ MCD_OPC_FilterValue, 1, 147, 33, // Skip to: 13355 >+/* 4760 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4763 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4775 >+/* 4767 */ MCD_OPC_CheckPredicate, 6, 136, 33, // Skip to: 13355 >+/* 4771 */ MCD_OPC_Decode, 185, 1, 108, // Opcode: BCLRI_H >+/* 4775 */ MCD_OPC_FilterValue, 1, 128, 33, // Skip to: 13355 >+/* 4779 */ MCD_OPC_CheckPredicate, 6, 124, 33, // Skip to: 13355 >+/* 4783 */ MCD_OPC_CheckField, 19, 1, 0, 118, 33, // Skip to: 13355 >+/* 4789 */ MCD_OPC_Decode, 183, 1, 109, // Opcode: BCLRI_B >+/* 4793 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 4805 >+/* 4797 */ MCD_OPC_CheckPredicate, 6, 106, 33, // Skip to: 13355 >+/* 4801 */ MCD_OPC_Decode, 164, 2, 107, // Opcode: BSETI_D >+/* 4805 */ MCD_OPC_FilterValue, 9, 52, 0, // Skip to: 4861 >+/* 4809 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4812 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4824 >+/* 4816 */ MCD_OPC_CheckPredicate, 6, 87, 33, // Skip to: 13355 >+/* 4820 */ MCD_OPC_Decode, 166, 2, 101, // Opcode: BSETI_W >+/* 4824 */ MCD_OPC_FilterValue, 1, 79, 33, // Skip to: 13355 >+/* 4828 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4831 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4843 >+/* 4835 */ MCD_OPC_CheckPredicate, 6, 68, 33, // Skip to: 13355 >+/* 4839 */ MCD_OPC_Decode, 165, 2, 108, // Opcode: BSETI_H >+/* 4843 */ MCD_OPC_FilterValue, 1, 60, 33, // Skip to: 13355 >+/* 4847 */ MCD_OPC_CheckPredicate, 6, 56, 33, // Skip to: 13355 >+/* 4851 */ MCD_OPC_CheckField, 19, 1, 0, 50, 33, // Skip to: 13355 >+/* 4857 */ MCD_OPC_Decode, 163, 2, 109, // Opcode: BSETI_B >+/* 4861 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 4873 >+/* 4865 */ MCD_OPC_CheckPredicate, 6, 38, 33, // Skip to: 13355 >+/* 4869 */ MCD_OPC_Decode, 133, 2, 107, // Opcode: BNEGI_D >+/* 4873 */ MCD_OPC_FilterValue, 11, 52, 0, // Skip to: 4929 >+/* 4877 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4880 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4892 >+/* 4884 */ MCD_OPC_CheckPredicate, 6, 19, 33, // Skip to: 13355 >+/* 4888 */ MCD_OPC_Decode, 135, 2, 101, // Opcode: BNEGI_W >+/* 4892 */ MCD_OPC_FilterValue, 1, 11, 33, // Skip to: 13355 >+/* 4896 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4899 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4911 >+/* 4903 */ MCD_OPC_CheckPredicate, 6, 0, 33, // Skip to: 13355 >+/* 4907 */ MCD_OPC_Decode, 134, 2, 108, // Opcode: BNEGI_H >+/* 4911 */ MCD_OPC_FilterValue, 1, 248, 32, // Skip to: 13355 >+/* 4915 */ MCD_OPC_CheckPredicate, 6, 244, 32, // Skip to: 13355 >+/* 4919 */ MCD_OPC_CheckField, 19, 1, 0, 238, 32, // Skip to: 13355 >+/* 4925 */ MCD_OPC_Decode, 132, 2, 109, // Opcode: BNEGI_B >+/* 4929 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 4941 >+/* 4933 */ MCD_OPC_CheckPredicate, 6, 226, 32, // Skip to: 13355 >+/* 4937 */ MCD_OPC_Decode, 218, 1, 110, // Opcode: BINSLI_D >+/* 4941 */ MCD_OPC_FilterValue, 13, 52, 0, // Skip to: 4997 >+/* 4945 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 4948 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4960 >+/* 4952 */ MCD_OPC_CheckPredicate, 6, 207, 32, // Skip to: 13355 >+/* 4956 */ MCD_OPC_Decode, 220, 1, 111, // Opcode: BINSLI_W >+/* 4960 */ MCD_OPC_FilterValue, 1, 199, 32, // Skip to: 13355 >+/* 4964 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 4967 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 4979 >+/* 4971 */ MCD_OPC_CheckPredicate, 6, 188, 32, // Skip to: 13355 >+/* 4975 */ MCD_OPC_Decode, 219, 1, 112, // Opcode: BINSLI_H >+/* 4979 */ MCD_OPC_FilterValue, 1, 180, 32, // Skip to: 13355 >+/* 4983 */ MCD_OPC_CheckPredicate, 6, 176, 32, // Skip to: 13355 >+/* 4987 */ MCD_OPC_CheckField, 19, 1, 0, 170, 32, // Skip to: 13355 >+/* 4993 */ MCD_OPC_Decode, 217, 1, 113, // Opcode: BINSLI_B >+/* 4997 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 5009 >+/* 5001 */ MCD_OPC_CheckPredicate, 6, 158, 32, // Skip to: 13355 >+/* 5005 */ MCD_OPC_Decode, 226, 1, 110, // Opcode: BINSRI_D >+/* 5009 */ MCD_OPC_FilterValue, 15, 150, 32, // Skip to: 13355 >+/* 5013 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5016 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5028 >+/* 5020 */ MCD_OPC_CheckPredicate, 6, 139, 32, // Skip to: 13355 >+/* 5024 */ MCD_OPC_Decode, 228, 1, 111, // Opcode: BINSRI_W >+/* 5028 */ MCD_OPC_FilterValue, 1, 131, 32, // Skip to: 13355 >+/* 5032 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5035 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5047 >+/* 5039 */ MCD_OPC_CheckPredicate, 6, 120, 32, // Skip to: 13355 >+/* 5043 */ MCD_OPC_Decode, 227, 1, 112, // Opcode: BINSRI_H >+/* 5047 */ MCD_OPC_FilterValue, 1, 112, 32, // Skip to: 13355 >+/* 5051 */ MCD_OPC_CheckPredicate, 6, 108, 32, // Skip to: 13355 >+/* 5055 */ MCD_OPC_CheckField, 19, 1, 0, 102, 32, // Skip to: 13355 >+/* 5061 */ MCD_OPC_Decode, 225, 1, 113, // Opcode: BINSRI_B >+/* 5065 */ MCD_OPC_FilterValue, 10, 19, 1, // Skip to: 5344 >+/* 5069 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... >+/* 5072 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5084 >+/* 5076 */ MCD_OPC_CheckPredicate, 6, 83, 32, // Skip to: 13355 >+/* 5080 */ MCD_OPC_Decode, 204, 10, 107, // Opcode: SAT_S_D >+/* 5084 */ MCD_OPC_FilterValue, 1, 52, 0, // Skip to: 5140 >+/* 5088 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5091 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5103 >+/* 5095 */ MCD_OPC_CheckPredicate, 6, 64, 32, // Skip to: 13355 >+/* 5099 */ MCD_OPC_Decode, 206, 10, 101, // Opcode: SAT_S_W >+/* 5103 */ MCD_OPC_FilterValue, 1, 56, 32, // Skip to: 13355 >+/* 5107 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5110 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5122 >+/* 5114 */ MCD_OPC_CheckPredicate, 6, 45, 32, // Skip to: 13355 >+/* 5118 */ MCD_OPC_Decode, 205, 10, 108, // Opcode: SAT_S_H >+/* 5122 */ MCD_OPC_FilterValue, 1, 37, 32, // Skip to: 13355 >+/* 5126 */ MCD_OPC_CheckPredicate, 6, 33, 32, // Skip to: 13355 >+/* 5130 */ MCD_OPC_CheckField, 19, 1, 0, 27, 32, // Skip to: 13355 >+/* 5136 */ MCD_OPC_Decode, 203, 10, 109, // Opcode: SAT_S_B >+/* 5140 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5152 >+/* 5144 */ MCD_OPC_CheckPredicate, 6, 15, 32, // Skip to: 13355 >+/* 5148 */ MCD_OPC_Decode, 208, 10, 107, // Opcode: SAT_U_D >+/* 5152 */ MCD_OPC_FilterValue, 3, 52, 0, // Skip to: 5208 >+/* 5156 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5159 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5171 >+/* 5163 */ MCD_OPC_CheckPredicate, 6, 252, 31, // Skip to: 13355 >+/* 5167 */ MCD_OPC_Decode, 210, 10, 101, // Opcode: SAT_U_W >+/* 5171 */ MCD_OPC_FilterValue, 1, 244, 31, // Skip to: 13355 >+/* 5175 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5178 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5190 >+/* 5182 */ MCD_OPC_CheckPredicate, 6, 233, 31, // Skip to: 13355 >+/* 5186 */ MCD_OPC_Decode, 209, 10, 108, // Opcode: SAT_U_H >+/* 5190 */ MCD_OPC_FilterValue, 1, 225, 31, // Skip to: 13355 >+/* 5194 */ MCD_OPC_CheckPredicate, 6, 221, 31, // Skip to: 13355 >+/* 5198 */ MCD_OPC_CheckField, 19, 1, 0, 215, 31, // Skip to: 13355 >+/* 5204 */ MCD_OPC_Decode, 207, 10, 109, // Opcode: SAT_U_B >+/* 5208 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 5220 >+/* 5212 */ MCD_OPC_CheckPredicate, 6, 203, 31, // Skip to: 13355 >+/* 5216 */ MCD_OPC_Decode, 209, 11, 107, // Opcode: SRARI_D >+/* 5220 */ MCD_OPC_FilterValue, 5, 52, 0, // Skip to: 5276 >+/* 5224 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5227 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5239 >+/* 5231 */ MCD_OPC_CheckPredicate, 6, 184, 31, // Skip to: 13355 >+/* 5235 */ MCD_OPC_Decode, 211, 11, 101, // Opcode: SRARI_W >+/* 5239 */ MCD_OPC_FilterValue, 1, 176, 31, // Skip to: 13355 >+/* 5243 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5246 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5258 >+/* 5250 */ MCD_OPC_CheckPredicate, 6, 165, 31, // Skip to: 13355 >+/* 5254 */ MCD_OPC_Decode, 210, 11, 108, // Opcode: SRARI_H >+/* 5258 */ MCD_OPC_FilterValue, 1, 157, 31, // Skip to: 13355 >+/* 5262 */ MCD_OPC_CheckPredicate, 6, 153, 31, // Skip to: 13355 >+/* 5266 */ MCD_OPC_CheckField, 19, 1, 0, 147, 31, // Skip to: 13355 >+/* 5272 */ MCD_OPC_Decode, 208, 11, 109, // Opcode: SRARI_B >+/* 5276 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 5288 >+/* 5280 */ MCD_OPC_CheckPredicate, 6, 135, 31, // Skip to: 13355 >+/* 5284 */ MCD_OPC_Decode, 229, 11, 107, // Opcode: SRLRI_D >+/* 5288 */ MCD_OPC_FilterValue, 7, 127, 31, // Skip to: 13355 >+/* 5292 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... >+/* 5295 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5307 >+/* 5299 */ MCD_OPC_CheckPredicate, 6, 116, 31, // Skip to: 13355 >+/* 5303 */ MCD_OPC_Decode, 231, 11, 101, // Opcode: SRLRI_W >+/* 5307 */ MCD_OPC_FilterValue, 1, 108, 31, // Skip to: 13355 >+/* 5311 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... >+/* 5314 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5326 >+/* 5318 */ MCD_OPC_CheckPredicate, 6, 97, 31, // Skip to: 13355 >+/* 5322 */ MCD_OPC_Decode, 230, 11, 108, // Opcode: SRLRI_H >+/* 5326 */ MCD_OPC_FilterValue, 1, 89, 31, // Skip to: 13355 >+/* 5330 */ MCD_OPC_CheckPredicate, 6, 85, 31, // Skip to: 13355 >+/* 5334 */ MCD_OPC_CheckField, 19, 1, 0, 79, 31, // Skip to: 13355 >+/* 5340 */ MCD_OPC_Decode, 228, 11, 109, // Opcode: SRLRI_B >+/* 5344 */ MCD_OPC_FilterValue, 13, 131, 1, // Skip to: 5735 >+/* 5348 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 5351 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5363 >+/* 5355 */ MCD_OPC_CheckPredicate, 6, 60, 31, // Skip to: 13355 >+/* 5359 */ MCD_OPC_Decode, 171, 11, 114, // Opcode: SLL_B >+/* 5363 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 5375 >+/* 5367 */ MCD_OPC_CheckPredicate, 6, 48, 31, // Skip to: 13355 >+/* 5371 */ MCD_OPC_Decode, 173, 11, 115, // Opcode: SLL_H >+/* 5375 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 5387 >+/* 5379 */ MCD_OPC_CheckPredicate, 6, 36, 31, // Skip to: 13355 >+/* 5383 */ MCD_OPC_Decode, 175, 11, 116, // Opcode: SLL_W >+/* 5387 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 5399 >+/* 5391 */ MCD_OPC_CheckPredicate, 6, 24, 31, // Skip to: 13355 >+/* 5395 */ MCD_OPC_Decode, 172, 11, 117, // Opcode: SLL_D >+/* 5399 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 5411 >+/* 5403 */ MCD_OPC_CheckPredicate, 6, 12, 31, // Skip to: 13355 >+/* 5407 */ MCD_OPC_Decode, 218, 11, 114, // Opcode: SRA_B >+/* 5411 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 5423 >+/* 5415 */ MCD_OPC_CheckPredicate, 6, 0, 31, // Skip to: 13355 >+/* 5419 */ MCD_OPC_Decode, 220, 11, 115, // Opcode: SRA_H >+/* 5423 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 5435 >+/* 5427 */ MCD_OPC_CheckPredicate, 6, 244, 30, // Skip to: 13355 >+/* 5431 */ MCD_OPC_Decode, 222, 11, 116, // Opcode: SRA_W >+/* 5435 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 5447 >+/* 5439 */ MCD_OPC_CheckPredicate, 6, 232, 30, // Skip to: 13355 >+/* 5443 */ MCD_OPC_Decode, 219, 11, 117, // Opcode: SRA_D >+/* 5447 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 5459 >+/* 5451 */ MCD_OPC_CheckPredicate, 6, 220, 30, // Skip to: 13355 >+/* 5455 */ MCD_OPC_Decode, 238, 11, 114, // Opcode: SRL_B >+/* 5459 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 5471 >+/* 5463 */ MCD_OPC_CheckPredicate, 6, 208, 30, // Skip to: 13355 >+/* 5467 */ MCD_OPC_Decode, 240, 11, 115, // Opcode: SRL_H >+/* 5471 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 5483 >+/* 5475 */ MCD_OPC_CheckPredicate, 6, 196, 30, // Skip to: 13355 >+/* 5479 */ MCD_OPC_Decode, 242, 11, 116, // Opcode: SRL_W >+/* 5483 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 5495 >+/* 5487 */ MCD_OPC_CheckPredicate, 6, 184, 30, // Skip to: 13355 >+/* 5491 */ MCD_OPC_Decode, 239, 11, 117, // Opcode: SRL_D >+/* 5495 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 5507 >+/* 5499 */ MCD_OPC_CheckPredicate, 6, 172, 30, // Skip to: 13355 >+/* 5503 */ MCD_OPC_Decode, 187, 1, 114, // Opcode: BCLR_B >+/* 5507 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 5519 >+/* 5511 */ MCD_OPC_CheckPredicate, 6, 160, 30, // Skip to: 13355 >+/* 5515 */ MCD_OPC_Decode, 189, 1, 115, // Opcode: BCLR_H >+/* 5519 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 5531 >+/* 5523 */ MCD_OPC_CheckPredicate, 6, 148, 30, // Skip to: 13355 >+/* 5527 */ MCD_OPC_Decode, 190, 1, 116, // Opcode: BCLR_W >+/* 5531 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 5543 >+/* 5535 */ MCD_OPC_CheckPredicate, 6, 136, 30, // Skip to: 13355 >+/* 5539 */ MCD_OPC_Decode, 188, 1, 117, // Opcode: BCLR_D >+/* 5543 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 5555 >+/* 5547 */ MCD_OPC_CheckPredicate, 6, 124, 30, // Skip to: 13355 >+/* 5551 */ MCD_OPC_Decode, 167, 2, 114, // Opcode: BSET_B >+/* 5555 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 5567 >+/* 5559 */ MCD_OPC_CheckPredicate, 6, 112, 30, // Skip to: 13355 >+/* 5563 */ MCD_OPC_Decode, 169, 2, 115, // Opcode: BSET_H >+/* 5567 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 5579 >+/* 5571 */ MCD_OPC_CheckPredicate, 6, 100, 30, // Skip to: 13355 >+/* 5575 */ MCD_OPC_Decode, 170, 2, 116, // Opcode: BSET_W >+/* 5579 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 5591 >+/* 5583 */ MCD_OPC_CheckPredicate, 6, 88, 30, // Skip to: 13355 >+/* 5587 */ MCD_OPC_Decode, 168, 2, 117, // Opcode: BSET_D >+/* 5591 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 5603 >+/* 5595 */ MCD_OPC_CheckPredicate, 6, 76, 30, // Skip to: 13355 >+/* 5599 */ MCD_OPC_Decode, 136, 2, 114, // Opcode: BNEG_B >+/* 5603 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 5615 >+/* 5607 */ MCD_OPC_CheckPredicate, 6, 64, 30, // Skip to: 13355 >+/* 5611 */ MCD_OPC_Decode, 138, 2, 115, // Opcode: BNEG_H >+/* 5615 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 5627 >+/* 5619 */ MCD_OPC_CheckPredicate, 6, 52, 30, // Skip to: 13355 >+/* 5623 */ MCD_OPC_Decode, 139, 2, 116, // Opcode: BNEG_W >+/* 5627 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 5639 >+/* 5631 */ MCD_OPC_CheckPredicate, 6, 40, 30, // Skip to: 13355 >+/* 5635 */ MCD_OPC_Decode, 137, 2, 117, // Opcode: BNEG_D >+/* 5639 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 5651 >+/* 5643 */ MCD_OPC_CheckPredicate, 6, 28, 30, // Skip to: 13355 >+/* 5647 */ MCD_OPC_Decode, 221, 1, 118, // Opcode: BINSL_B >+/* 5651 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 5663 >+/* 5655 */ MCD_OPC_CheckPredicate, 6, 16, 30, // Skip to: 13355 >+/* 5659 */ MCD_OPC_Decode, 223, 1, 119, // Opcode: BINSL_H >+/* 5663 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 5675 >+/* 5667 */ MCD_OPC_CheckPredicate, 6, 4, 30, // Skip to: 13355 >+/* 5671 */ MCD_OPC_Decode, 224, 1, 120, // Opcode: BINSL_W >+/* 5675 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 5687 >+/* 5679 */ MCD_OPC_CheckPredicate, 6, 248, 29, // Skip to: 13355 >+/* 5683 */ MCD_OPC_Decode, 222, 1, 121, // Opcode: BINSL_D >+/* 5687 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 5699 >+/* 5691 */ MCD_OPC_CheckPredicate, 6, 236, 29, // Skip to: 13355 >+/* 5695 */ MCD_OPC_Decode, 229, 1, 118, // Opcode: BINSR_B >+/* 5699 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 5711 >+/* 5703 */ MCD_OPC_CheckPredicate, 6, 224, 29, // Skip to: 13355 >+/* 5707 */ MCD_OPC_Decode, 231, 1, 119, // Opcode: BINSR_H >+/* 5711 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 5723 >+/* 5715 */ MCD_OPC_CheckPredicate, 6, 212, 29, // Skip to: 13355 >+/* 5719 */ MCD_OPC_Decode, 232, 1, 120, // Opcode: BINSR_W >+/* 5723 */ MCD_OPC_FilterValue, 31, 204, 29, // Skip to: 13355 >+/* 5727 */ MCD_OPC_CheckPredicate, 6, 200, 29, // Skip to: 13355 >+/* 5731 */ MCD_OPC_Decode, 230, 1, 121, // Opcode: BINSR_D >+/* 5735 */ MCD_OPC_FilterValue, 14, 127, 1, // Skip to: 6122 >+/* 5739 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 5742 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 5753 >+/* 5746 */ MCD_OPC_CheckPredicate, 6, 181, 29, // Skip to: 13355 >+/* 5750 */ MCD_OPC_Decode, 55, 114, // Opcode: ADDV_B >+/* 5753 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 5764 >+/* 5757 */ MCD_OPC_CheckPredicate, 6, 170, 29, // Skip to: 13355 >+/* 5761 */ MCD_OPC_Decode, 57, 115, // Opcode: ADDV_H >+/* 5764 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 5775 >+/* 5768 */ MCD_OPC_CheckPredicate, 6, 159, 29, // Skip to: 13355 >+/* 5772 */ MCD_OPC_Decode, 58, 116, // Opcode: ADDV_W >+/* 5775 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 5786 >+/* 5779 */ MCD_OPC_CheckPredicate, 6, 148, 29, // Skip to: 13355 >+/* 5783 */ MCD_OPC_Decode, 56, 117, // Opcode: ADDV_D >+/* 5786 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 5798 >+/* 5790 */ MCD_OPC_CheckPredicate, 6, 137, 29, // Skip to: 13355 >+/* 5794 */ MCD_OPC_Decode, 158, 12, 114, // Opcode: SUBV_B >+/* 5798 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 5810 >+/* 5802 */ MCD_OPC_CheckPredicate, 6, 125, 29, // Skip to: 13355 >+/* 5806 */ MCD_OPC_Decode, 160, 12, 115, // Opcode: SUBV_H >+/* 5810 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 5822 >+/* 5814 */ MCD_OPC_CheckPredicate, 6, 113, 29, // Skip to: 13355 >+/* 5818 */ MCD_OPC_Decode, 161, 12, 116, // Opcode: SUBV_W >+/* 5822 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 5834 >+/* 5826 */ MCD_OPC_CheckPredicate, 6, 101, 29, // Skip to: 13355 >+/* 5830 */ MCD_OPC_Decode, 159, 12, 117, // Opcode: SUBV_D >+/* 5834 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 5846 >+/* 5838 */ MCD_OPC_CheckPredicate, 6, 89, 29, // Skip to: 13355 >+/* 5842 */ MCD_OPC_Decode, 133, 8, 114, // Opcode: MAX_S_B >+/* 5846 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 5858 >+/* 5850 */ MCD_OPC_CheckPredicate, 6, 77, 29, // Skip to: 13355 >+/* 5854 */ MCD_OPC_Decode, 135, 8, 115, // Opcode: MAX_S_H >+/* 5858 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 5870 >+/* 5862 */ MCD_OPC_CheckPredicate, 6, 65, 29, // Skip to: 13355 >+/* 5866 */ MCD_OPC_Decode, 136, 8, 116, // Opcode: MAX_S_W >+/* 5870 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 5882 >+/* 5874 */ MCD_OPC_CheckPredicate, 6, 53, 29, // Skip to: 13355 >+/* 5878 */ MCD_OPC_Decode, 134, 8, 117, // Opcode: MAX_S_D >+/* 5882 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 5894 >+/* 5886 */ MCD_OPC_CheckPredicate, 6, 41, 29, // Skip to: 13355 >+/* 5890 */ MCD_OPC_Decode, 137, 8, 114, // Opcode: MAX_U_B >+/* 5894 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 5906 >+/* 5898 */ MCD_OPC_CheckPredicate, 6, 29, 29, // Skip to: 13355 >+/* 5902 */ MCD_OPC_Decode, 139, 8, 115, // Opcode: MAX_U_H >+/* 5906 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 5918 >+/* 5910 */ MCD_OPC_CheckPredicate, 6, 17, 29, // Skip to: 13355 >+/* 5914 */ MCD_OPC_Decode, 140, 8, 116, // Opcode: MAX_U_W >+/* 5918 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 5930 >+/* 5922 */ MCD_OPC_CheckPredicate, 6, 5, 29, // Skip to: 13355 >+/* 5926 */ MCD_OPC_Decode, 138, 8, 117, // Opcode: MAX_U_D >+/* 5930 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 5942 >+/* 5934 */ MCD_OPC_CheckPredicate, 6, 249, 28, // Skip to: 13355 >+/* 5938 */ MCD_OPC_Decode, 174, 8, 114, // Opcode: MIN_S_B >+/* 5942 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 5954 >+/* 5946 */ MCD_OPC_CheckPredicate, 6, 237, 28, // Skip to: 13355 >+/* 5950 */ MCD_OPC_Decode, 176, 8, 115, // Opcode: MIN_S_H >+/* 5954 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 5966 >+/* 5958 */ MCD_OPC_CheckPredicate, 6, 225, 28, // Skip to: 13355 >+/* 5962 */ MCD_OPC_Decode, 177, 8, 116, // Opcode: MIN_S_W >+/* 5966 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 5978 >+/* 5970 */ MCD_OPC_CheckPredicate, 6, 213, 28, // Skip to: 13355 >+/* 5974 */ MCD_OPC_Decode, 175, 8, 117, // Opcode: MIN_S_D >+/* 5978 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 5990 >+/* 5982 */ MCD_OPC_CheckPredicate, 6, 201, 28, // Skip to: 13355 >+/* 5986 */ MCD_OPC_Decode, 178, 8, 114, // Opcode: MIN_U_B >+/* 5990 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 6002 >+/* 5994 */ MCD_OPC_CheckPredicate, 6, 189, 28, // Skip to: 13355 >+/* 5998 */ MCD_OPC_Decode, 180, 8, 115, // Opcode: MIN_U_H >+/* 6002 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 6014 >+/* 6006 */ MCD_OPC_CheckPredicate, 6, 177, 28, // Skip to: 13355 >+/* 6010 */ MCD_OPC_Decode, 181, 8, 116, // Opcode: MIN_U_W >+/* 6014 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 6026 >+/* 6018 */ MCD_OPC_CheckPredicate, 6, 165, 28, // Skip to: 13355 >+/* 6022 */ MCD_OPC_Decode, 179, 8, 117, // Opcode: MIN_U_D >+/* 6026 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 6038 >+/* 6030 */ MCD_OPC_CheckPredicate, 6, 153, 28, // Skip to: 13355 >+/* 6034 */ MCD_OPC_Decode, 255, 7, 114, // Opcode: MAX_A_B >+/* 6038 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 6050 >+/* 6042 */ MCD_OPC_CheckPredicate, 6, 141, 28, // Skip to: 13355 >+/* 6046 */ MCD_OPC_Decode, 129, 8, 115, // Opcode: MAX_A_H >+/* 6050 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 6062 >+/* 6054 */ MCD_OPC_CheckPredicate, 6, 129, 28, // Skip to: 13355 >+/* 6058 */ MCD_OPC_Decode, 130, 8, 116, // Opcode: MAX_A_W >+/* 6062 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 6074 >+/* 6066 */ MCD_OPC_CheckPredicate, 6, 117, 28, // Skip to: 13355 >+/* 6070 */ MCD_OPC_Decode, 128, 8, 117, // Opcode: MAX_A_D >+/* 6074 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 6086 >+/* 6078 */ MCD_OPC_CheckPredicate, 6, 105, 28, // Skip to: 13355 >+/* 6082 */ MCD_OPC_Decode, 168, 8, 114, // Opcode: MIN_A_B >+/* 6086 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 6098 >+/* 6090 */ MCD_OPC_CheckPredicate, 6, 93, 28, // Skip to: 13355 >+/* 6094 */ MCD_OPC_Decode, 170, 8, 115, // Opcode: MIN_A_H >+/* 6098 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 6110 >+/* 6102 */ MCD_OPC_CheckPredicate, 6, 81, 28, // Skip to: 13355 >+/* 6106 */ MCD_OPC_Decode, 171, 8, 116, // Opcode: MIN_A_W >+/* 6110 */ MCD_OPC_FilterValue, 31, 73, 28, // Skip to: 13355 >+/* 6114 */ MCD_OPC_CheckPredicate, 6, 69, 28, // Skip to: 13355 >+/* 6118 */ MCD_OPC_Decode, 169, 8, 117, // Opcode: MIN_A_D >+/* 6122 */ MCD_OPC_FilterValue, 15, 243, 0, // Skip to: 6369 >+/* 6126 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6129 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6141 >+/* 6133 */ MCD_OPC_CheckPredicate, 6, 50, 28, // Skip to: 13355 >+/* 6137 */ MCD_OPC_Decode, 214, 2, 114, // Opcode: CEQ_B >+/* 6141 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6153 >+/* 6145 */ MCD_OPC_CheckPredicate, 6, 38, 28, // Skip to: 13355 >+/* 6149 */ MCD_OPC_Decode, 216, 2, 115, // Opcode: CEQ_H >+/* 6153 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6165 >+/* 6157 */ MCD_OPC_CheckPredicate, 6, 26, 28, // Skip to: 13355 >+/* 6161 */ MCD_OPC_Decode, 217, 2, 116, // Opcode: CEQ_W >+/* 6165 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6177 >+/* 6169 */ MCD_OPC_CheckPredicate, 6, 14, 28, // Skip to: 13355 >+/* 6173 */ MCD_OPC_Decode, 215, 2, 117, // Opcode: CEQ_D >+/* 6177 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6189 >+/* 6181 */ MCD_OPC_CheckPredicate, 6, 2, 28, // Skip to: 13355 >+/* 6185 */ MCD_OPC_Decode, 252, 2, 114, // Opcode: CLT_S_B >+/* 6189 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6201 >+/* 6193 */ MCD_OPC_CheckPredicate, 6, 246, 27, // Skip to: 13355 >+/* 6197 */ MCD_OPC_Decode, 254, 2, 115, // Opcode: CLT_S_H >+/* 6201 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6213 >+/* 6205 */ MCD_OPC_CheckPredicate, 6, 234, 27, // Skip to: 13355 >+/* 6209 */ MCD_OPC_Decode, 255, 2, 116, // Opcode: CLT_S_W >+/* 6213 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6225 >+/* 6217 */ MCD_OPC_CheckPredicate, 6, 222, 27, // Skip to: 13355 >+/* 6221 */ MCD_OPC_Decode, 253, 2, 117, // Opcode: CLT_S_D >+/* 6225 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6237 >+/* 6229 */ MCD_OPC_CheckPredicate, 6, 210, 27, // Skip to: 13355 >+/* 6233 */ MCD_OPC_Decode, 128, 3, 114, // Opcode: CLT_U_B >+/* 6237 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6249 >+/* 6241 */ MCD_OPC_CheckPredicate, 6, 198, 27, // Skip to: 13355 >+/* 6245 */ MCD_OPC_Decode, 130, 3, 115, // Opcode: CLT_U_H >+/* 6249 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6261 >+/* 6253 */ MCD_OPC_CheckPredicate, 6, 186, 27, // Skip to: 13355 >+/* 6257 */ MCD_OPC_Decode, 131, 3, 116, // Opcode: CLT_U_W >+/* 6261 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6273 >+/* 6265 */ MCD_OPC_CheckPredicate, 6, 174, 27, // Skip to: 13355 >+/* 6269 */ MCD_OPC_Decode, 129, 3, 117, // Opcode: CLT_U_D >+/* 6273 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 6285 >+/* 6277 */ MCD_OPC_CheckPredicate, 6, 162, 27, // Skip to: 13355 >+/* 6281 */ MCD_OPC_Decode, 233, 2, 114, // Opcode: CLE_S_B >+/* 6285 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 6297 >+/* 6289 */ MCD_OPC_CheckPredicate, 6, 150, 27, // Skip to: 13355 >+/* 6293 */ MCD_OPC_Decode, 235, 2, 115, // Opcode: CLE_S_H >+/* 6297 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 6309 >+/* 6301 */ MCD_OPC_CheckPredicate, 6, 138, 27, // Skip to: 13355 >+/* 6305 */ MCD_OPC_Decode, 236, 2, 116, // Opcode: CLE_S_W >+/* 6309 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 6321 >+/* 6313 */ MCD_OPC_CheckPredicate, 6, 126, 27, // Skip to: 13355 >+/* 6317 */ MCD_OPC_Decode, 234, 2, 117, // Opcode: CLE_S_D >+/* 6321 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 6333 >+/* 6325 */ MCD_OPC_CheckPredicate, 6, 114, 27, // Skip to: 13355 >+/* 6329 */ MCD_OPC_Decode, 237, 2, 114, // Opcode: CLE_U_B >+/* 6333 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 6345 >+/* 6337 */ MCD_OPC_CheckPredicate, 6, 102, 27, // Skip to: 13355 >+/* 6341 */ MCD_OPC_Decode, 239, 2, 115, // Opcode: CLE_U_H >+/* 6345 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 6357 >+/* 6349 */ MCD_OPC_CheckPredicate, 6, 90, 27, // Skip to: 13355 >+/* 6353 */ MCD_OPC_Decode, 240, 2, 116, // Opcode: CLE_U_W >+/* 6357 */ MCD_OPC_FilterValue, 23, 82, 27, // Skip to: 13355 >+/* 6361 */ MCD_OPC_CheckPredicate, 6, 78, 27, // Skip to: 13355 >+/* 6365 */ MCD_OPC_Decode, 238, 2, 117, // Opcode: CLE_U_D >+/* 6369 */ MCD_OPC_FilterValue, 16, 115, 1, // Skip to: 6744 >+/* 6373 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6376 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 6387 >+/* 6380 */ MCD_OPC_CheckPredicate, 6, 59, 27, // Skip to: 13355 >+/* 6384 */ MCD_OPC_Decode, 60, 114, // Opcode: ADD_A_B >+/* 6387 */ MCD_OPC_FilterValue, 1, 7, 0, // Skip to: 6398 >+/* 6391 */ MCD_OPC_CheckPredicate, 6, 48, 27, // Skip to: 13355 >+/* 6395 */ MCD_OPC_Decode, 62, 115, // Opcode: ADD_A_H >+/* 6398 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 6409 >+/* 6402 */ MCD_OPC_CheckPredicate, 6, 37, 27, // Skip to: 13355 >+/* 6406 */ MCD_OPC_Decode, 63, 116, // Opcode: ADD_A_W >+/* 6409 */ MCD_OPC_FilterValue, 3, 7, 0, // Skip to: 6420 >+/* 6413 */ MCD_OPC_CheckPredicate, 6, 26, 27, // Skip to: 13355 >+/* 6417 */ MCD_OPC_Decode, 61, 117, // Opcode: ADD_A_D >+/* 6420 */ MCD_OPC_FilterValue, 4, 7, 0, // Skip to: 6431 >+/* 6424 */ MCD_OPC_CheckPredicate, 6, 15, 27, // Skip to: 13355 >+/* 6428 */ MCD_OPC_Decode, 33, 114, // Opcode: ADDS_A_B >+/* 6431 */ MCD_OPC_FilterValue, 5, 7, 0, // Skip to: 6442 >+/* 6435 */ MCD_OPC_CheckPredicate, 6, 4, 27, // Skip to: 13355 >+/* 6439 */ MCD_OPC_Decode, 35, 115, // Opcode: ADDS_A_H >+/* 6442 */ MCD_OPC_FilterValue, 6, 7, 0, // Skip to: 6453 >+/* 6446 */ MCD_OPC_CheckPredicate, 6, 249, 26, // Skip to: 13355 >+/* 6450 */ MCD_OPC_Decode, 36, 116, // Opcode: ADDS_A_W >+/* 6453 */ MCD_OPC_FilterValue, 7, 7, 0, // Skip to: 6464 >+/* 6457 */ MCD_OPC_CheckPredicate, 6, 238, 26, // Skip to: 13355 >+/* 6461 */ MCD_OPC_Decode, 34, 117, // Opcode: ADDS_A_D >+/* 6464 */ MCD_OPC_FilterValue, 8, 7, 0, // Skip to: 6475 >+/* 6468 */ MCD_OPC_CheckPredicate, 6, 227, 26, // Skip to: 13355 >+/* 6472 */ MCD_OPC_Decode, 37, 114, // Opcode: ADDS_S_B >+/* 6475 */ MCD_OPC_FilterValue, 9, 7, 0, // Skip to: 6486 >+/* 6479 */ MCD_OPC_CheckPredicate, 6, 216, 26, // Skip to: 13355 >+/* 6483 */ MCD_OPC_Decode, 39, 115, // Opcode: ADDS_S_H >+/* 6486 */ MCD_OPC_FilterValue, 10, 7, 0, // Skip to: 6497 >+/* 6490 */ MCD_OPC_CheckPredicate, 6, 205, 26, // Skip to: 13355 >+/* 6494 */ MCD_OPC_Decode, 40, 116, // Opcode: ADDS_S_W >+/* 6497 */ MCD_OPC_FilterValue, 11, 7, 0, // Skip to: 6508 >+/* 6501 */ MCD_OPC_CheckPredicate, 6, 194, 26, // Skip to: 13355 >+/* 6505 */ MCD_OPC_Decode, 38, 117, // Opcode: ADDS_S_D >+/* 6508 */ MCD_OPC_FilterValue, 12, 7, 0, // Skip to: 6519 >+/* 6512 */ MCD_OPC_CheckPredicate, 6, 183, 26, // Skip to: 13355 >+/* 6516 */ MCD_OPC_Decode, 41, 114, // Opcode: ADDS_U_B >+/* 6519 */ MCD_OPC_FilterValue, 13, 7, 0, // Skip to: 6530 >+/* 6523 */ MCD_OPC_CheckPredicate, 6, 172, 26, // Skip to: 13355 >+/* 6527 */ MCD_OPC_Decode, 43, 115, // Opcode: ADDS_U_H >+/* 6530 */ MCD_OPC_FilterValue, 14, 7, 0, // Skip to: 6541 >+/* 6534 */ MCD_OPC_CheckPredicate, 6, 161, 26, // Skip to: 13355 >+/* 6538 */ MCD_OPC_Decode, 44, 116, // Opcode: ADDS_U_W >+/* 6541 */ MCD_OPC_FilterValue, 15, 7, 0, // Skip to: 6552 >+/* 6545 */ MCD_OPC_CheckPredicate, 6, 150, 26, // Skip to: 13355 >+/* 6549 */ MCD_OPC_Decode, 42, 117, // Opcode: ADDS_U_D >+/* 6552 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 6564 >+/* 6556 */ MCD_OPC_CheckPredicate, 6, 139, 26, // Skip to: 13355 >+/* 6560 */ MCD_OPC_Decode, 137, 1, 114, // Opcode: AVE_S_B >+/* 6564 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 6576 >+/* 6568 */ MCD_OPC_CheckPredicate, 6, 127, 26, // Skip to: 13355 >+/* 6572 */ MCD_OPC_Decode, 139, 1, 115, // Opcode: AVE_S_H >+/* 6576 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 6588 >+/* 6580 */ MCD_OPC_CheckPredicate, 6, 115, 26, // Skip to: 13355 >+/* 6584 */ MCD_OPC_Decode, 140, 1, 116, // Opcode: AVE_S_W >+/* 6588 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 6600 >+/* 6592 */ MCD_OPC_CheckPredicate, 6, 103, 26, // Skip to: 13355 >+/* 6596 */ MCD_OPC_Decode, 138, 1, 117, // Opcode: AVE_S_D >+/* 6600 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 6612 >+/* 6604 */ MCD_OPC_CheckPredicate, 6, 91, 26, // Skip to: 13355 >+/* 6608 */ MCD_OPC_Decode, 141, 1, 114, // Opcode: AVE_U_B >+/* 6612 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 6624 >+/* 6616 */ MCD_OPC_CheckPredicate, 6, 79, 26, // Skip to: 13355 >+/* 6620 */ MCD_OPC_Decode, 143, 1, 115, // Opcode: AVE_U_H >+/* 6624 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 6636 >+/* 6628 */ MCD_OPC_CheckPredicate, 6, 67, 26, // Skip to: 13355 >+/* 6632 */ MCD_OPC_Decode, 144, 1, 116, // Opcode: AVE_U_W >+/* 6636 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 6648 >+/* 6640 */ MCD_OPC_CheckPredicate, 6, 55, 26, // Skip to: 13355 >+/* 6644 */ MCD_OPC_Decode, 142, 1, 117, // Opcode: AVE_U_D >+/* 6648 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 6660 >+/* 6652 */ MCD_OPC_CheckPredicate, 6, 43, 26, // Skip to: 13355 >+/* 6656 */ MCD_OPC_Decode, 129, 1, 114, // Opcode: AVER_S_B >+/* 6660 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 6672 >+/* 6664 */ MCD_OPC_CheckPredicate, 6, 31, 26, // Skip to: 13355 >+/* 6668 */ MCD_OPC_Decode, 131, 1, 115, // Opcode: AVER_S_H >+/* 6672 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 6684 >+/* 6676 */ MCD_OPC_CheckPredicate, 6, 19, 26, // Skip to: 13355 >+/* 6680 */ MCD_OPC_Decode, 132, 1, 116, // Opcode: AVER_S_W >+/* 6684 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 6696 >+/* 6688 */ MCD_OPC_CheckPredicate, 6, 7, 26, // Skip to: 13355 >+/* 6692 */ MCD_OPC_Decode, 130, 1, 117, // Opcode: AVER_S_D >+/* 6696 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 6708 >+/* 6700 */ MCD_OPC_CheckPredicate, 6, 251, 25, // Skip to: 13355 >+/* 6704 */ MCD_OPC_Decode, 133, 1, 114, // Opcode: AVER_U_B >+/* 6708 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 6720 >+/* 6712 */ MCD_OPC_CheckPredicate, 6, 239, 25, // Skip to: 13355 >+/* 6716 */ MCD_OPC_Decode, 135, 1, 115, // Opcode: AVER_U_H >+/* 6720 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 6732 >+/* 6724 */ MCD_OPC_CheckPredicate, 6, 227, 25, // Skip to: 13355 >+/* 6728 */ MCD_OPC_Decode, 136, 1, 116, // Opcode: AVER_U_W >+/* 6732 */ MCD_OPC_FilterValue, 31, 219, 25, // Skip to: 13355 >+/* 6736 */ MCD_OPC_CheckPredicate, 6, 215, 25, // Skip to: 13355 >+/* 6740 */ MCD_OPC_Decode, 134, 1, 117, // Opcode: AVER_U_D >+/* 6744 */ MCD_OPC_FilterValue, 17, 27, 1, // Skip to: 7031 >+/* 6748 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 6751 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6763 >+/* 6755 */ MCD_OPC_CheckPredicate, 6, 196, 25, // Skip to: 13355 >+/* 6759 */ MCD_OPC_Decode, 140, 12, 114, // Opcode: SUBS_S_B >+/* 6763 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 6775 >+/* 6767 */ MCD_OPC_CheckPredicate, 6, 184, 25, // Skip to: 13355 >+/* 6771 */ MCD_OPC_Decode, 142, 12, 115, // Opcode: SUBS_S_H >+/* 6775 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 6787 >+/* 6779 */ MCD_OPC_CheckPredicate, 6, 172, 25, // Skip to: 13355 >+/* 6783 */ MCD_OPC_Decode, 143, 12, 116, // Opcode: SUBS_S_W >+/* 6787 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 6799 >+/* 6791 */ MCD_OPC_CheckPredicate, 6, 160, 25, // Skip to: 13355 >+/* 6795 */ MCD_OPC_Decode, 141, 12, 117, // Opcode: SUBS_S_D >+/* 6799 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 6811 >+/* 6803 */ MCD_OPC_CheckPredicate, 6, 148, 25, // Skip to: 13355 >+/* 6807 */ MCD_OPC_Decode, 144, 12, 114, // Opcode: SUBS_U_B >+/* 6811 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 6823 >+/* 6815 */ MCD_OPC_CheckPredicate, 6, 136, 25, // Skip to: 13355 >+/* 6819 */ MCD_OPC_Decode, 146, 12, 115, // Opcode: SUBS_U_H >+/* 6823 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 6835 >+/* 6827 */ MCD_OPC_CheckPredicate, 6, 124, 25, // Skip to: 13355 >+/* 6831 */ MCD_OPC_Decode, 147, 12, 116, // Opcode: SUBS_U_W >+/* 6835 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 6847 >+/* 6839 */ MCD_OPC_CheckPredicate, 6, 112, 25, // Skip to: 13355 >+/* 6843 */ MCD_OPC_Decode, 145, 12, 117, // Opcode: SUBS_U_D >+/* 6847 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 6859 >+/* 6851 */ MCD_OPC_CheckPredicate, 6, 100, 25, // Skip to: 13355 >+/* 6855 */ MCD_OPC_Decode, 132, 12, 114, // Opcode: SUBSUS_U_B >+/* 6859 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 6871 >+/* 6863 */ MCD_OPC_CheckPredicate, 6, 88, 25, // Skip to: 13355 >+/* 6867 */ MCD_OPC_Decode, 134, 12, 115, // Opcode: SUBSUS_U_H >+/* 6871 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 6883 >+/* 6875 */ MCD_OPC_CheckPredicate, 6, 76, 25, // Skip to: 13355 >+/* 6879 */ MCD_OPC_Decode, 135, 12, 116, // Opcode: SUBSUS_U_W >+/* 6883 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 6895 >+/* 6887 */ MCD_OPC_CheckPredicate, 6, 64, 25, // Skip to: 13355 >+/* 6891 */ MCD_OPC_Decode, 133, 12, 117, // Opcode: SUBSUS_U_D >+/* 6895 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 6907 >+/* 6899 */ MCD_OPC_CheckPredicate, 6, 52, 25, // Skip to: 13355 >+/* 6903 */ MCD_OPC_Decode, 136, 12, 114, // Opcode: SUBSUU_S_B >+/* 6907 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 6919 >+/* 6911 */ MCD_OPC_CheckPredicate, 6, 40, 25, // Skip to: 13355 >+/* 6915 */ MCD_OPC_Decode, 138, 12, 115, // Opcode: SUBSUU_S_H >+/* 6919 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 6931 >+/* 6923 */ MCD_OPC_CheckPredicate, 6, 28, 25, // Skip to: 13355 >+/* 6927 */ MCD_OPC_Decode, 139, 12, 116, // Opcode: SUBSUU_S_W >+/* 6931 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 6943 >+/* 6935 */ MCD_OPC_CheckPredicate, 6, 16, 25, // Skip to: 13355 >+/* 6939 */ MCD_OPC_Decode, 137, 12, 117, // Opcode: SUBSUU_S_D >+/* 6943 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 6954 >+/* 6947 */ MCD_OPC_CheckPredicate, 6, 4, 25, // Skip to: 13355 >+/* 6951 */ MCD_OPC_Decode, 87, 114, // Opcode: ASUB_S_B >+/* 6954 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 6965 >+/* 6958 */ MCD_OPC_CheckPredicate, 6, 249, 24, // Skip to: 13355 >+/* 6962 */ MCD_OPC_Decode, 89, 115, // Opcode: ASUB_S_H >+/* 6965 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 6976 >+/* 6969 */ MCD_OPC_CheckPredicate, 6, 238, 24, // Skip to: 13355 >+/* 6973 */ MCD_OPC_Decode, 90, 116, // Opcode: ASUB_S_W >+/* 6976 */ MCD_OPC_FilterValue, 19, 7, 0, // Skip to: 6987 >+/* 6980 */ MCD_OPC_CheckPredicate, 6, 227, 24, // Skip to: 13355 >+/* 6984 */ MCD_OPC_Decode, 88, 117, // Opcode: ASUB_S_D >+/* 6987 */ MCD_OPC_FilterValue, 20, 7, 0, // Skip to: 6998 >+/* 6991 */ MCD_OPC_CheckPredicate, 6, 216, 24, // Skip to: 13355 >+/* 6995 */ MCD_OPC_Decode, 91, 114, // Opcode: ASUB_U_B >+/* 6998 */ MCD_OPC_FilterValue, 21, 7, 0, // Skip to: 7009 >+/* 7002 */ MCD_OPC_CheckPredicate, 6, 205, 24, // Skip to: 13355 >+/* 7006 */ MCD_OPC_Decode, 93, 115, // Opcode: ASUB_U_H >+/* 7009 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 7020 >+/* 7013 */ MCD_OPC_CheckPredicate, 6, 194, 24, // Skip to: 13355 >+/* 7017 */ MCD_OPC_Decode, 94, 116, // Opcode: ASUB_U_W >+/* 7020 */ MCD_OPC_FilterValue, 23, 187, 24, // Skip to: 13355 >+/* 7024 */ MCD_OPC_CheckPredicate, 6, 183, 24, // Skip to: 13355 >+/* 7028 */ MCD_OPC_Decode, 92, 117, // Opcode: ASUB_U_D >+/* 7031 */ MCD_OPC_FilterValue, 18, 83, 1, // Skip to: 7374 >+/* 7035 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7038 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7050 >+/* 7042 */ MCD_OPC_CheckPredicate, 6, 165, 24, // Skip to: 13355 >+/* 7046 */ MCD_OPC_Decode, 174, 9, 114, // Opcode: MULV_B >+/* 7050 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7062 >+/* 7054 */ MCD_OPC_CheckPredicate, 6, 153, 24, // Skip to: 13355 >+/* 7058 */ MCD_OPC_Decode, 176, 9, 115, // Opcode: MULV_H >+/* 7062 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7074 >+/* 7066 */ MCD_OPC_CheckPredicate, 6, 141, 24, // Skip to: 13355 >+/* 7070 */ MCD_OPC_Decode, 177, 9, 116, // Opcode: MULV_W >+/* 7074 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 7086 >+/* 7078 */ MCD_OPC_CheckPredicate, 6, 129, 24, // Skip to: 13355 >+/* 7082 */ MCD_OPC_Decode, 175, 9, 117, // Opcode: MULV_D >+/* 7086 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 7098 >+/* 7090 */ MCD_OPC_CheckPredicate, 6, 117, 24, // Skip to: 13355 >+/* 7094 */ MCD_OPC_Decode, 228, 7, 118, // Opcode: MADDV_B >+/* 7098 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 7110 >+/* 7102 */ MCD_OPC_CheckPredicate, 6, 105, 24, // Skip to: 13355 >+/* 7106 */ MCD_OPC_Decode, 230, 7, 119, // Opcode: MADDV_H >+/* 7110 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 7122 >+/* 7114 */ MCD_OPC_CheckPredicate, 6, 93, 24, // Skip to: 13355 >+/* 7118 */ MCD_OPC_Decode, 231, 7, 120, // Opcode: MADDV_W >+/* 7122 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 7134 >+/* 7126 */ MCD_OPC_CheckPredicate, 6, 81, 24, // Skip to: 13355 >+/* 7130 */ MCD_OPC_Decode, 229, 7, 121, // Opcode: MADDV_D >+/* 7134 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 7146 >+/* 7138 */ MCD_OPC_CheckPredicate, 6, 69, 24, // Skip to: 13355 >+/* 7142 */ MCD_OPC_Decode, 245, 8, 118, // Opcode: MSUBV_B >+/* 7146 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7158 >+/* 7150 */ MCD_OPC_CheckPredicate, 6, 57, 24, // Skip to: 13355 >+/* 7154 */ MCD_OPC_Decode, 247, 8, 119, // Opcode: MSUBV_H >+/* 7158 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 7170 >+/* 7162 */ MCD_OPC_CheckPredicate, 6, 45, 24, // Skip to: 13355 >+/* 7166 */ MCD_OPC_Decode, 248, 8, 120, // Opcode: MSUBV_W >+/* 7170 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 7182 >+/* 7174 */ MCD_OPC_CheckPredicate, 6, 33, 24, // Skip to: 13355 >+/* 7178 */ MCD_OPC_Decode, 246, 8, 121, // Opcode: MSUBV_D >+/* 7182 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7194 >+/* 7186 */ MCD_OPC_CheckPredicate, 6, 21, 24, // Skip to: 13355 >+/* 7190 */ MCD_OPC_Decode, 165, 4, 114, // Opcode: DIV_S_B >+/* 7194 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7206 >+/* 7198 */ MCD_OPC_CheckPredicate, 6, 9, 24, // Skip to: 13355 >+/* 7202 */ MCD_OPC_Decode, 167, 4, 115, // Opcode: DIV_S_H >+/* 7206 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7218 >+/* 7210 */ MCD_OPC_CheckPredicate, 6, 253, 23, // Skip to: 13355 >+/* 7214 */ MCD_OPC_Decode, 168, 4, 116, // Opcode: DIV_S_W >+/* 7218 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7230 >+/* 7222 */ MCD_OPC_CheckPredicate, 6, 241, 23, // Skip to: 13355 >+/* 7226 */ MCD_OPC_Decode, 166, 4, 117, // Opcode: DIV_S_D >+/* 7230 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7242 >+/* 7234 */ MCD_OPC_CheckPredicate, 6, 229, 23, // Skip to: 13355 >+/* 7238 */ MCD_OPC_Decode, 169, 4, 114, // Opcode: DIV_U_B >+/* 7242 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7254 >+/* 7246 */ MCD_OPC_CheckPredicate, 6, 217, 23, // Skip to: 13355 >+/* 7250 */ MCD_OPC_Decode, 171, 4, 115, // Opcode: DIV_U_H >+/* 7254 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7266 >+/* 7258 */ MCD_OPC_CheckPredicate, 6, 205, 23, // Skip to: 13355 >+/* 7262 */ MCD_OPC_Decode, 172, 4, 116, // Opcode: DIV_U_W >+/* 7266 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 7278 >+/* 7270 */ MCD_OPC_CheckPredicate, 6, 193, 23, // Skip to: 13355 >+/* 7274 */ MCD_OPC_Decode, 170, 4, 117, // Opcode: DIV_U_D >+/* 7278 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 7290 >+/* 7282 */ MCD_OPC_CheckPredicate, 6, 181, 23, // Skip to: 13355 >+/* 7286 */ MCD_OPC_Decode, 187, 8, 114, // Opcode: MOD_S_B >+/* 7290 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 7302 >+/* 7294 */ MCD_OPC_CheckPredicate, 6, 169, 23, // Skip to: 13355 >+/* 7298 */ MCD_OPC_Decode, 189, 8, 115, // Opcode: MOD_S_H >+/* 7302 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 7314 >+/* 7306 */ MCD_OPC_CheckPredicate, 6, 157, 23, // Skip to: 13355 >+/* 7310 */ MCD_OPC_Decode, 190, 8, 116, // Opcode: MOD_S_W >+/* 7314 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 7326 >+/* 7318 */ MCD_OPC_CheckPredicate, 6, 145, 23, // Skip to: 13355 >+/* 7322 */ MCD_OPC_Decode, 188, 8, 117, // Opcode: MOD_S_D >+/* 7326 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 7338 >+/* 7330 */ MCD_OPC_CheckPredicate, 6, 133, 23, // Skip to: 13355 >+/* 7334 */ MCD_OPC_Decode, 191, 8, 114, // Opcode: MOD_U_B >+/* 7338 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 7350 >+/* 7342 */ MCD_OPC_CheckPredicate, 6, 121, 23, // Skip to: 13355 >+/* 7346 */ MCD_OPC_Decode, 193, 8, 115, // Opcode: MOD_U_H >+/* 7350 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 7362 >+/* 7354 */ MCD_OPC_CheckPredicate, 6, 109, 23, // Skip to: 13355 >+/* 7358 */ MCD_OPC_Decode, 194, 8, 116, // Opcode: MOD_U_W >+/* 7362 */ MCD_OPC_FilterValue, 31, 101, 23, // Skip to: 13355 >+/* 7366 */ MCD_OPC_CheckPredicate, 6, 97, 23, // Skip to: 13355 >+/* 7370 */ MCD_OPC_Decode, 192, 8, 117, // Opcode: MOD_U_D >+/* 7374 */ MCD_OPC_FilterValue, 19, 219, 0, // Skip to: 7597 >+/* 7378 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7381 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7393 >+/* 7385 */ MCD_OPC_CheckPredicate, 6, 78, 23, // Skip to: 13355 >+/* 7389 */ MCD_OPC_Decode, 192, 4, 122, // Opcode: DOTP_S_H >+/* 7393 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7405 >+/* 7397 */ MCD_OPC_CheckPredicate, 6, 66, 23, // Skip to: 13355 >+/* 7401 */ MCD_OPC_Decode, 193, 4, 123, // Opcode: DOTP_S_W >+/* 7405 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 7417 >+/* 7409 */ MCD_OPC_CheckPredicate, 6, 54, 23, // Skip to: 13355 >+/* 7413 */ MCD_OPC_Decode, 191, 4, 124, // Opcode: DOTP_S_D >+/* 7417 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 7429 >+/* 7421 */ MCD_OPC_CheckPredicate, 6, 42, 23, // Skip to: 13355 >+/* 7425 */ MCD_OPC_Decode, 195, 4, 122, // Opcode: DOTP_U_H >+/* 7429 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 7441 >+/* 7433 */ MCD_OPC_CheckPredicate, 6, 30, 23, // Skip to: 13355 >+/* 7437 */ MCD_OPC_Decode, 196, 4, 123, // Opcode: DOTP_U_W >+/* 7441 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 7453 >+/* 7445 */ MCD_OPC_CheckPredicate, 6, 18, 23, // Skip to: 13355 >+/* 7449 */ MCD_OPC_Decode, 194, 4, 124, // Opcode: DOTP_U_D >+/* 7453 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7465 >+/* 7457 */ MCD_OPC_CheckPredicate, 6, 6, 23, // Skip to: 13355 >+/* 7461 */ MCD_OPC_Decode, 198, 4, 125, // Opcode: DPADD_S_H >+/* 7465 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 7477 >+/* 7469 */ MCD_OPC_CheckPredicate, 6, 250, 22, // Skip to: 13355 >+/* 7473 */ MCD_OPC_Decode, 199, 4, 126, // Opcode: DPADD_S_W >+/* 7477 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 7489 >+/* 7481 */ MCD_OPC_CheckPredicate, 6, 238, 22, // Skip to: 13355 >+/* 7485 */ MCD_OPC_Decode, 197, 4, 127, // Opcode: DPADD_S_D >+/* 7489 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 7501 >+/* 7493 */ MCD_OPC_CheckPredicate, 6, 226, 22, // Skip to: 13355 >+/* 7497 */ MCD_OPC_Decode, 201, 4, 125, // Opcode: DPADD_U_H >+/* 7501 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 7513 >+/* 7505 */ MCD_OPC_CheckPredicate, 6, 214, 22, // Skip to: 13355 >+/* 7509 */ MCD_OPC_Decode, 202, 4, 126, // Opcode: DPADD_U_W >+/* 7513 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 7525 >+/* 7517 */ MCD_OPC_CheckPredicate, 6, 202, 22, // Skip to: 13355 >+/* 7521 */ MCD_OPC_Decode, 200, 4, 127, // Opcode: DPADD_U_D >+/* 7525 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7537 >+/* 7529 */ MCD_OPC_CheckPredicate, 6, 190, 22, // Skip to: 13355 >+/* 7533 */ MCD_OPC_Decode, 217, 4, 125, // Opcode: DPSUB_S_H >+/* 7537 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7549 >+/* 7541 */ MCD_OPC_CheckPredicate, 6, 178, 22, // Skip to: 13355 >+/* 7545 */ MCD_OPC_Decode, 218, 4, 126, // Opcode: DPSUB_S_W >+/* 7549 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7561 >+/* 7553 */ MCD_OPC_CheckPredicate, 6, 166, 22, // Skip to: 13355 >+/* 7557 */ MCD_OPC_Decode, 216, 4, 127, // Opcode: DPSUB_S_D >+/* 7561 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7573 >+/* 7565 */ MCD_OPC_CheckPredicate, 6, 154, 22, // Skip to: 13355 >+/* 7569 */ MCD_OPC_Decode, 220, 4, 125, // Opcode: DPSUB_U_H >+/* 7573 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7585 >+/* 7577 */ MCD_OPC_CheckPredicate, 6, 142, 22, // Skip to: 13355 >+/* 7581 */ MCD_OPC_Decode, 221, 4, 126, // Opcode: DPSUB_U_W >+/* 7585 */ MCD_OPC_FilterValue, 23, 134, 22, // Skip to: 13355 >+/* 7589 */ MCD_OPC_CheckPredicate, 6, 130, 22, // Skip to: 13355 >+/* 7593 */ MCD_OPC_Decode, 219, 4, 127, // Opcode: DPSUB_U_D >+/* 7597 */ MCD_OPC_FilterValue, 20, 139, 1, // Skip to: 7996 >+/* 7601 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 7604 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 7617 >+/* 7608 */ MCD_OPC_CheckPredicate, 6, 111, 22, // Skip to: 13355 >+/* 7612 */ MCD_OPC_Decode, 158, 11, 128, 1, // Opcode: SLD_B >+/* 7617 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 7630 >+/* 7621 */ MCD_OPC_CheckPredicate, 6, 98, 22, // Skip to: 13355 >+/* 7625 */ MCD_OPC_Decode, 160, 11, 129, 1, // Opcode: SLD_H >+/* 7630 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 7643 >+/* 7634 */ MCD_OPC_CheckPredicate, 6, 85, 22, // Skip to: 13355 >+/* 7638 */ MCD_OPC_Decode, 161, 11, 130, 1, // Opcode: SLD_W >+/* 7643 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 7656 >+/* 7647 */ MCD_OPC_CheckPredicate, 6, 72, 22, // Skip to: 13355 >+/* 7651 */ MCD_OPC_Decode, 159, 11, 131, 1, // Opcode: SLD_D >+/* 7656 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 7669 >+/* 7660 */ MCD_OPC_CheckPredicate, 6, 59, 22, // Skip to: 13355 >+/* 7664 */ MCD_OPC_Decode, 199, 11, 132, 1, // Opcode: SPLAT_B >+/* 7669 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 7682 >+/* 7673 */ MCD_OPC_CheckPredicate, 6, 46, 22, // Skip to: 13355 >+/* 7677 */ MCD_OPC_Decode, 201, 11, 133, 1, // Opcode: SPLAT_H >+/* 7682 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 7695 >+/* 7686 */ MCD_OPC_CheckPredicate, 6, 33, 22, // Skip to: 13355 >+/* 7690 */ MCD_OPC_Decode, 202, 11, 134, 1, // Opcode: SPLAT_W >+/* 7695 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 7708 >+/* 7699 */ MCD_OPC_CheckPredicate, 6, 20, 22, // Skip to: 13355 >+/* 7703 */ MCD_OPC_Decode, 200, 11, 135, 1, // Opcode: SPLAT_D >+/* 7708 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 7720 >+/* 7712 */ MCD_OPC_CheckPredicate, 6, 7, 22, // Skip to: 13355 >+/* 7716 */ MCD_OPC_Decode, 235, 9, 114, // Opcode: PCKEV_B >+/* 7720 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 7732 >+/* 7724 */ MCD_OPC_CheckPredicate, 6, 251, 21, // Skip to: 13355 >+/* 7728 */ MCD_OPC_Decode, 237, 9, 115, // Opcode: PCKEV_H >+/* 7732 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 7744 >+/* 7736 */ MCD_OPC_CheckPredicate, 6, 239, 21, // Skip to: 13355 >+/* 7740 */ MCD_OPC_Decode, 238, 9, 116, // Opcode: PCKEV_W >+/* 7744 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 7756 >+/* 7748 */ MCD_OPC_CheckPredicate, 6, 227, 21, // Skip to: 13355 >+/* 7752 */ MCD_OPC_Decode, 236, 9, 117, // Opcode: PCKEV_D >+/* 7756 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 7768 >+/* 7760 */ MCD_OPC_CheckPredicate, 6, 215, 21, // Skip to: 13355 >+/* 7764 */ MCD_OPC_Decode, 239, 9, 114, // Opcode: PCKOD_B >+/* 7768 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 7780 >+/* 7772 */ MCD_OPC_CheckPredicate, 6, 203, 21, // Skip to: 13355 >+/* 7776 */ MCD_OPC_Decode, 241, 9, 115, // Opcode: PCKOD_H >+/* 7780 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 7792 >+/* 7784 */ MCD_OPC_CheckPredicate, 6, 191, 21, // Skip to: 13355 >+/* 7788 */ MCD_OPC_Decode, 242, 9, 116, // Opcode: PCKOD_W >+/* 7792 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 7804 >+/* 7796 */ MCD_OPC_CheckPredicate, 6, 179, 21, // Skip to: 13355 >+/* 7800 */ MCD_OPC_Decode, 240, 9, 117, // Opcode: PCKOD_D >+/* 7804 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 7816 >+/* 7808 */ MCD_OPC_CheckPredicate, 6, 167, 21, // Skip to: 13355 >+/* 7812 */ MCD_OPC_Decode, 195, 6, 114, // Opcode: ILVL_B >+/* 7816 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 7828 >+/* 7820 */ MCD_OPC_CheckPredicate, 6, 155, 21, // Skip to: 13355 >+/* 7824 */ MCD_OPC_Decode, 197, 6, 115, // Opcode: ILVL_H >+/* 7828 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 7840 >+/* 7832 */ MCD_OPC_CheckPredicate, 6, 143, 21, // Skip to: 13355 >+/* 7836 */ MCD_OPC_Decode, 198, 6, 116, // Opcode: ILVL_W >+/* 7840 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 7852 >+/* 7844 */ MCD_OPC_CheckPredicate, 6, 131, 21, // Skip to: 13355 >+/* 7848 */ MCD_OPC_Decode, 196, 6, 117, // Opcode: ILVL_D >+/* 7852 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 7864 >+/* 7856 */ MCD_OPC_CheckPredicate, 6, 119, 21, // Skip to: 13355 >+/* 7860 */ MCD_OPC_Decode, 203, 6, 114, // Opcode: ILVR_B >+/* 7864 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 7876 >+/* 7868 */ MCD_OPC_CheckPredicate, 6, 107, 21, // Skip to: 13355 >+/* 7872 */ MCD_OPC_Decode, 205, 6, 115, // Opcode: ILVR_H >+/* 7876 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 7888 >+/* 7880 */ MCD_OPC_CheckPredicate, 6, 95, 21, // Skip to: 13355 >+/* 7884 */ MCD_OPC_Decode, 206, 6, 116, // Opcode: ILVR_W >+/* 7888 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 7900 >+/* 7892 */ MCD_OPC_CheckPredicate, 6, 83, 21, // Skip to: 13355 >+/* 7896 */ MCD_OPC_Decode, 204, 6, 117, // Opcode: ILVR_D >+/* 7900 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 7912 >+/* 7904 */ MCD_OPC_CheckPredicate, 6, 71, 21, // Skip to: 13355 >+/* 7908 */ MCD_OPC_Decode, 191, 6, 114, // Opcode: ILVEV_B >+/* 7912 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 7924 >+/* 7916 */ MCD_OPC_CheckPredicate, 6, 59, 21, // Skip to: 13355 >+/* 7920 */ MCD_OPC_Decode, 193, 6, 115, // Opcode: ILVEV_H >+/* 7924 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 7936 >+/* 7928 */ MCD_OPC_CheckPredicate, 6, 47, 21, // Skip to: 13355 >+/* 7932 */ MCD_OPC_Decode, 194, 6, 116, // Opcode: ILVEV_W >+/* 7936 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 7948 >+/* 7940 */ MCD_OPC_CheckPredicate, 6, 35, 21, // Skip to: 13355 >+/* 7944 */ MCD_OPC_Decode, 192, 6, 117, // Opcode: ILVEV_D >+/* 7948 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 7960 >+/* 7952 */ MCD_OPC_CheckPredicate, 6, 23, 21, // Skip to: 13355 >+/* 7956 */ MCD_OPC_Decode, 199, 6, 114, // Opcode: ILVOD_B >+/* 7960 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 7972 >+/* 7964 */ MCD_OPC_CheckPredicate, 6, 11, 21, // Skip to: 13355 >+/* 7968 */ MCD_OPC_Decode, 201, 6, 115, // Opcode: ILVOD_H >+/* 7972 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 7984 >+/* 7976 */ MCD_OPC_CheckPredicate, 6, 255, 20, // Skip to: 13355 >+/* 7980 */ MCD_OPC_Decode, 202, 6, 116, // Opcode: ILVOD_W >+/* 7984 */ MCD_OPC_FilterValue, 31, 247, 20, // Skip to: 13355 >+/* 7988 */ MCD_OPC_CheckPredicate, 6, 243, 20, // Skip to: 13355 >+/* 7992 */ MCD_OPC_Decode, 200, 6, 117, // Opcode: ILVOD_D >+/* 7996 */ MCD_OPC_FilterValue, 21, 35, 1, // Skip to: 8291 >+/* 8000 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 8003 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8015 >+/* 8007 */ MCD_OPC_CheckPredicate, 6, 224, 20, // Skip to: 13355 >+/* 8011 */ MCD_OPC_Decode, 153, 13, 118, // Opcode: VSHF_B >+/* 8015 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8027 >+/* 8019 */ MCD_OPC_CheckPredicate, 6, 212, 20, // Skip to: 13355 >+/* 8023 */ MCD_OPC_Decode, 155, 13, 119, // Opcode: VSHF_H >+/* 8027 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8039 >+/* 8031 */ MCD_OPC_CheckPredicate, 6, 200, 20, // Skip to: 13355 >+/* 8035 */ MCD_OPC_Decode, 156, 13, 120, // Opcode: VSHF_W >+/* 8039 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8051 >+/* 8043 */ MCD_OPC_CheckPredicate, 6, 188, 20, // Skip to: 13355 >+/* 8047 */ MCD_OPC_Decode, 154, 13, 121, // Opcode: VSHF_D >+/* 8051 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8063 >+/* 8055 */ MCD_OPC_CheckPredicate, 6, 176, 20, // Skip to: 13355 >+/* 8059 */ MCD_OPC_Decode, 212, 11, 114, // Opcode: SRAR_B >+/* 8063 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8075 >+/* 8067 */ MCD_OPC_CheckPredicate, 6, 164, 20, // Skip to: 13355 >+/* 8071 */ MCD_OPC_Decode, 214, 11, 115, // Opcode: SRAR_H >+/* 8075 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8087 >+/* 8079 */ MCD_OPC_CheckPredicate, 6, 152, 20, // Skip to: 13355 >+/* 8083 */ MCD_OPC_Decode, 215, 11, 116, // Opcode: SRAR_W >+/* 8087 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8099 >+/* 8091 */ MCD_OPC_CheckPredicate, 6, 140, 20, // Skip to: 13355 >+/* 8095 */ MCD_OPC_Decode, 213, 11, 117, // Opcode: SRAR_D >+/* 8099 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8111 >+/* 8103 */ MCD_OPC_CheckPredicate, 6, 128, 20, // Skip to: 13355 >+/* 8107 */ MCD_OPC_Decode, 232, 11, 114, // Opcode: SRLR_B >+/* 8111 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8123 >+/* 8115 */ MCD_OPC_CheckPredicate, 6, 116, 20, // Skip to: 13355 >+/* 8119 */ MCD_OPC_Decode, 234, 11, 115, // Opcode: SRLR_H >+/* 8123 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8135 >+/* 8127 */ MCD_OPC_CheckPredicate, 6, 104, 20, // Skip to: 13355 >+/* 8131 */ MCD_OPC_Decode, 235, 11, 116, // Opcode: SRLR_W >+/* 8135 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8147 >+/* 8139 */ MCD_OPC_CheckPredicate, 6, 92, 20, // Skip to: 13355 >+/* 8143 */ MCD_OPC_Decode, 233, 11, 117, // Opcode: SRLR_D >+/* 8147 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 8159 >+/* 8151 */ MCD_OPC_CheckPredicate, 6, 80, 20, // Skip to: 13355 >+/* 8155 */ MCD_OPC_Decode, 180, 6, 122, // Opcode: HADD_S_H >+/* 8159 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 8171 >+/* 8163 */ MCD_OPC_CheckPredicate, 6, 68, 20, // Skip to: 13355 >+/* 8167 */ MCD_OPC_Decode, 181, 6, 123, // Opcode: HADD_S_W >+/* 8171 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 8183 >+/* 8175 */ MCD_OPC_CheckPredicate, 6, 56, 20, // Skip to: 13355 >+/* 8179 */ MCD_OPC_Decode, 179, 6, 124, // Opcode: HADD_S_D >+/* 8183 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 8195 >+/* 8187 */ MCD_OPC_CheckPredicate, 6, 44, 20, // Skip to: 13355 >+/* 8191 */ MCD_OPC_Decode, 183, 6, 122, // Opcode: HADD_U_H >+/* 8195 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 8207 >+/* 8199 */ MCD_OPC_CheckPredicate, 6, 32, 20, // Skip to: 13355 >+/* 8203 */ MCD_OPC_Decode, 184, 6, 123, // Opcode: HADD_U_W >+/* 8207 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 8219 >+/* 8211 */ MCD_OPC_CheckPredicate, 6, 20, 20, // Skip to: 13355 >+/* 8215 */ MCD_OPC_Decode, 182, 6, 124, // Opcode: HADD_U_D >+/* 8219 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 8231 >+/* 8223 */ MCD_OPC_CheckPredicate, 6, 8, 20, // Skip to: 13355 >+/* 8227 */ MCD_OPC_Decode, 186, 6, 122, // Opcode: HSUB_S_H >+/* 8231 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 8243 >+/* 8235 */ MCD_OPC_CheckPredicate, 6, 252, 19, // Skip to: 13355 >+/* 8239 */ MCD_OPC_Decode, 187, 6, 123, // Opcode: HSUB_S_W >+/* 8243 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 8255 >+/* 8247 */ MCD_OPC_CheckPredicate, 6, 240, 19, // Skip to: 13355 >+/* 8251 */ MCD_OPC_Decode, 185, 6, 124, // Opcode: HSUB_S_D >+/* 8255 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 8267 >+/* 8259 */ MCD_OPC_CheckPredicate, 6, 228, 19, // Skip to: 13355 >+/* 8263 */ MCD_OPC_Decode, 189, 6, 122, // Opcode: HSUB_U_H >+/* 8267 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 8279 >+/* 8271 */ MCD_OPC_CheckPredicate, 6, 216, 19, // Skip to: 13355 >+/* 8275 */ MCD_OPC_Decode, 190, 6, 123, // Opcode: HSUB_U_W >+/* 8279 */ MCD_OPC_FilterValue, 31, 208, 19, // Skip to: 13355 >+/* 8283 */ MCD_OPC_CheckPredicate, 6, 204, 19, // Skip to: 13355 >+/* 8287 */ MCD_OPC_Decode, 188, 6, 124, // Opcode: HSUB_U_D >+/* 8291 */ MCD_OPC_FilterValue, 25, 230, 1, // Skip to: 8781 >+/* 8295 */ MCD_OPC_ExtractField, 20, 6, // Inst{25-20} ... >+/* 8298 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8311 >+/* 8302 */ MCD_OPC_CheckPredicate, 6, 185, 19, // Skip to: 13355 >+/* 8306 */ MCD_OPC_Decode, 154, 11, 136, 1, // Opcode: SLDI_B >+/* 8311 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8330 >+/* 8315 */ MCD_OPC_CheckPredicate, 6, 172, 19, // Skip to: 13355 >+/* 8319 */ MCD_OPC_CheckField, 19, 1, 0, 166, 19, // Skip to: 13355 >+/* 8325 */ MCD_OPC_Decode, 156, 11, 137, 1, // Opcode: SLDI_H >+/* 8330 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 8388 >+/* 8334 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8337 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8350 >+/* 8341 */ MCD_OPC_CheckPredicate, 6, 146, 19, // Skip to: 13355 >+/* 8345 */ MCD_OPC_Decode, 157, 11, 138, 1, // Opcode: SLDI_W >+/* 8350 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8369 >+/* 8354 */ MCD_OPC_CheckPredicate, 6, 133, 19, // Skip to: 13355 >+/* 8358 */ MCD_OPC_CheckField, 17, 1, 0, 127, 19, // Skip to: 13355 >+/* 8364 */ MCD_OPC_Decode, 155, 11, 139, 1, // Opcode: SLDI_D >+/* 8369 */ MCD_OPC_FilterValue, 3, 118, 19, // Skip to: 13355 >+/* 8373 */ MCD_OPC_CheckPredicate, 6, 114, 19, // Skip to: 13355 >+/* 8377 */ MCD_OPC_CheckField, 16, 2, 2, 108, 19, // Skip to: 13355 >+/* 8383 */ MCD_OPC_Decode, 192, 3, 140, 1, // Opcode: CTCMSA >+/* 8388 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 8401 >+/* 8392 */ MCD_OPC_CheckPredicate, 6, 95, 19, // Skip to: 13355 >+/* 8396 */ MCD_OPC_Decode, 195, 11, 141, 1, // Opcode: SPLATI_B >+/* 8401 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 8420 >+/* 8405 */ MCD_OPC_CheckPredicate, 6, 82, 19, // Skip to: 13355 >+/* 8409 */ MCD_OPC_CheckField, 19, 1, 0, 76, 19, // Skip to: 13355 >+/* 8415 */ MCD_OPC_Decode, 197, 11, 142, 1, // Opcode: SPLATI_H >+/* 8420 */ MCD_OPC_FilterValue, 7, 54, 0, // Skip to: 8478 >+/* 8424 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8427 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8440 >+/* 8431 */ MCD_OPC_CheckPredicate, 6, 56, 19, // Skip to: 13355 >+/* 8435 */ MCD_OPC_Decode, 198, 11, 143, 1, // Opcode: SPLATI_W >+/* 8440 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8459 >+/* 8444 */ MCD_OPC_CheckPredicate, 6, 43, 19, // Skip to: 13355 >+/* 8448 */ MCD_OPC_CheckField, 17, 1, 0, 37, 19, // Skip to: 13355 >+/* 8454 */ MCD_OPC_Decode, 196, 11, 144, 1, // Opcode: SPLATI_D >+/* 8459 */ MCD_OPC_FilterValue, 3, 28, 19, // Skip to: 13355 >+/* 8463 */ MCD_OPC_CheckPredicate, 6, 24, 19, // Skip to: 13355 >+/* 8467 */ MCD_OPC_CheckField, 16, 2, 2, 18, 19, // Skip to: 13355 >+/* 8473 */ MCD_OPC_Decode, 220, 2, 145, 1, // Opcode: CFCMSA >+/* 8478 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 8491 >+/* 8482 */ MCD_OPC_CheckPredicate, 6, 5, 19, // Skip to: 13355 >+/* 8486 */ MCD_OPC_Decode, 182, 3, 146, 1, // Opcode: COPY_S_B >+/* 8491 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 8510 >+/* 8495 */ MCD_OPC_CheckPredicate, 6, 248, 18, // Skip to: 13355 >+/* 8499 */ MCD_OPC_CheckField, 19, 1, 0, 242, 18, // Skip to: 13355 >+/* 8505 */ MCD_OPC_Decode, 184, 3, 147, 1, // Opcode: COPY_S_H >+/* 8510 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 8568 >+/* 8514 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8517 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8530 >+/* 8521 */ MCD_OPC_CheckPredicate, 6, 222, 18, // Skip to: 13355 >+/* 8525 */ MCD_OPC_Decode, 185, 3, 148, 1, // Opcode: COPY_S_W >+/* 8530 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 8549 >+/* 8534 */ MCD_OPC_CheckPredicate, 13, 209, 18, // Skip to: 13355 >+/* 8538 */ MCD_OPC_CheckField, 17, 1, 0, 203, 18, // Skip to: 13355 >+/* 8544 */ MCD_OPC_Decode, 183, 3, 149, 1, // Opcode: COPY_S_D >+/* 8549 */ MCD_OPC_FilterValue, 3, 194, 18, // Skip to: 13355 >+/* 8553 */ MCD_OPC_CheckPredicate, 6, 190, 18, // Skip to: 13355 >+/* 8557 */ MCD_OPC_CheckField, 16, 2, 2, 184, 18, // Skip to: 13355 >+/* 8563 */ MCD_OPC_Decode, 196, 8, 150, 1, // Opcode: MOVE_V >+/* 8568 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 8581 >+/* 8572 */ MCD_OPC_CheckPredicate, 6, 171, 18, // Skip to: 13355 >+/* 8576 */ MCD_OPC_Decode, 186, 3, 146, 1, // Opcode: COPY_U_B >+/* 8581 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 8600 >+/* 8585 */ MCD_OPC_CheckPredicate, 6, 158, 18, // Skip to: 13355 >+/* 8589 */ MCD_OPC_CheckField, 19, 1, 0, 152, 18, // Skip to: 13355 >+/* 8595 */ MCD_OPC_Decode, 188, 3, 147, 1, // Opcode: COPY_U_H >+/* 8600 */ MCD_OPC_FilterValue, 15, 35, 0, // Skip to: 8639 >+/* 8604 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8607 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8620 >+/* 8611 */ MCD_OPC_CheckPredicate, 6, 132, 18, // Skip to: 13355 >+/* 8615 */ MCD_OPC_Decode, 189, 3, 148, 1, // Opcode: COPY_U_W >+/* 8620 */ MCD_OPC_FilterValue, 2, 123, 18, // Skip to: 13355 >+/* 8624 */ MCD_OPC_CheckPredicate, 13, 119, 18, // Skip to: 13355 >+/* 8628 */ MCD_OPC_CheckField, 17, 1, 0, 113, 18, // Skip to: 13355 >+/* 8634 */ MCD_OPC_Decode, 187, 3, 149, 1, // Opcode: COPY_U_D >+/* 8639 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 8652 >+/* 8643 */ MCD_OPC_CheckPredicate, 6, 100, 18, // Skip to: 13355 >+/* 8647 */ MCD_OPC_Decode, 208, 6, 151, 1, // Opcode: INSERT_B >+/* 8652 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 8671 >+/* 8656 */ MCD_OPC_CheckPredicate, 6, 87, 18, // Skip to: 13355 >+/* 8660 */ MCD_OPC_CheckField, 19, 1, 0, 81, 18, // Skip to: 13355 >+/* 8666 */ MCD_OPC_Decode, 216, 6, 152, 1, // Opcode: INSERT_H >+/* 8671 */ MCD_OPC_FilterValue, 19, 35, 0, // Skip to: 8710 >+/* 8675 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8678 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8691 >+/* 8682 */ MCD_OPC_CheckPredicate, 6, 61, 18, // Skip to: 13355 >+/* 8686 */ MCD_OPC_Decode, 218, 6, 153, 1, // Opcode: INSERT_W >+/* 8691 */ MCD_OPC_FilterValue, 2, 52, 18, // Skip to: 13355 >+/* 8695 */ MCD_OPC_CheckPredicate, 13, 48, 18, // Skip to: 13355 >+/* 8699 */ MCD_OPC_CheckField, 17, 1, 0, 42, 18, // Skip to: 13355 >+/* 8705 */ MCD_OPC_Decode, 210, 6, 154, 1, // Opcode: INSERT_D >+/* 8710 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 8723 >+/* 8714 */ MCD_OPC_CheckPredicate, 6, 29, 18, // Skip to: 13355 >+/* 8718 */ MCD_OPC_Decode, 221, 6, 155, 1, // Opcode: INSVE_B >+/* 8723 */ MCD_OPC_FilterValue, 22, 15, 0, // Skip to: 8742 >+/* 8727 */ MCD_OPC_CheckPredicate, 6, 16, 18, // Skip to: 13355 >+/* 8731 */ MCD_OPC_CheckField, 19, 1, 0, 10, 18, // Skip to: 13355 >+/* 8737 */ MCD_OPC_Decode, 223, 6, 155, 1, // Opcode: INSVE_H >+/* 8742 */ MCD_OPC_FilterValue, 23, 1, 18, // Skip to: 13355 >+/* 8746 */ MCD_OPC_ExtractField, 18, 2, // Inst{19-18} ... >+/* 8749 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 8762 >+/* 8753 */ MCD_OPC_CheckPredicate, 6, 246, 17, // Skip to: 13355 >+/* 8757 */ MCD_OPC_Decode, 224, 6, 155, 1, // Opcode: INSVE_W >+/* 8762 */ MCD_OPC_FilterValue, 2, 237, 17, // Skip to: 13355 >+/* 8766 */ MCD_OPC_CheckPredicate, 6, 233, 17, // Skip to: 13355 >+/* 8770 */ MCD_OPC_CheckField, 17, 1, 0, 227, 17, // Skip to: 13355 >+/* 8776 */ MCD_OPC_Decode, 222, 6, 155, 1, // Opcode: INSVE_D >+/* 8781 */ MCD_OPC_FilterValue, 26, 131, 1, // Skip to: 9172 >+/* 8785 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 8788 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8800 >+/* 8792 */ MCD_OPC_CheckPredicate, 6, 207, 17, // Skip to: 13355 >+/* 8796 */ MCD_OPC_Decode, 157, 5, 116, // Opcode: FCAF_W >+/* 8800 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 8812 >+/* 8804 */ MCD_OPC_CheckPredicate, 6, 195, 17, // Skip to: 13355 >+/* 8808 */ MCD_OPC_Decode, 156, 5, 117, // Opcode: FCAF_D >+/* 8812 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8824 >+/* 8816 */ MCD_OPC_CheckPredicate, 6, 183, 17, // Skip to: 13355 >+/* 8820 */ MCD_OPC_Decode, 184, 5, 116, // Opcode: FCUN_W >+/* 8824 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 8836 >+/* 8828 */ MCD_OPC_CheckPredicate, 6, 171, 17, // Skip to: 13355 >+/* 8832 */ MCD_OPC_Decode, 183, 5, 117, // Opcode: FCUN_D >+/* 8836 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8848 >+/* 8840 */ MCD_OPC_CheckPredicate, 6, 159, 17, // Skip to: 13355 >+/* 8844 */ MCD_OPC_Decode, 159, 5, 116, // Opcode: FCEQ_W >+/* 8848 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 8860 >+/* 8852 */ MCD_OPC_CheckPredicate, 6, 147, 17, // Skip to: 13355 >+/* 8856 */ MCD_OPC_Decode, 158, 5, 117, // Opcode: FCEQ_D >+/* 8860 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 8872 >+/* 8864 */ MCD_OPC_CheckPredicate, 6, 135, 17, // Skip to: 13355 >+/* 8868 */ MCD_OPC_Decode, 176, 5, 116, // Opcode: FCUEQ_W >+/* 8872 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 8884 >+/* 8876 */ MCD_OPC_CheckPredicate, 6, 123, 17, // Skip to: 13355 >+/* 8880 */ MCD_OPC_Decode, 175, 5, 117, // Opcode: FCUEQ_D >+/* 8884 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 8896 >+/* 8888 */ MCD_OPC_CheckPredicate, 6, 111, 17, // Skip to: 13355 >+/* 8892 */ MCD_OPC_Decode, 165, 5, 116, // Opcode: FCLT_W >+/* 8896 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 8908 >+/* 8900 */ MCD_OPC_CheckPredicate, 6, 99, 17, // Skip to: 13355 >+/* 8904 */ MCD_OPC_Decode, 164, 5, 117, // Opcode: FCLT_D >+/* 8908 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 8920 >+/* 8912 */ MCD_OPC_CheckPredicate, 6, 87, 17, // Skip to: 13355 >+/* 8916 */ MCD_OPC_Decode, 180, 5, 116, // Opcode: FCULT_W >+/* 8920 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 8932 >+/* 8924 */ MCD_OPC_CheckPredicate, 6, 75, 17, // Skip to: 13355 >+/* 8928 */ MCD_OPC_Decode, 179, 5, 117, // Opcode: FCULT_D >+/* 8932 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 8944 >+/* 8936 */ MCD_OPC_CheckPredicate, 6, 63, 17, // Skip to: 13355 >+/* 8940 */ MCD_OPC_Decode, 163, 5, 116, // Opcode: FCLE_W >+/* 8944 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 8956 >+/* 8948 */ MCD_OPC_CheckPredicate, 6, 51, 17, // Skip to: 13355 >+/* 8952 */ MCD_OPC_Decode, 162, 5, 117, // Opcode: FCLE_D >+/* 8956 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 8968 >+/* 8960 */ MCD_OPC_CheckPredicate, 6, 39, 17, // Skip to: 13355 >+/* 8964 */ MCD_OPC_Decode, 178, 5, 116, // Opcode: FCULE_W >+/* 8968 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 8980 >+/* 8972 */ MCD_OPC_CheckPredicate, 6, 27, 17, // Skip to: 13355 >+/* 8976 */ MCD_OPC_Decode, 177, 5, 117, // Opcode: FCULE_D >+/* 8980 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 8992 >+/* 8984 */ MCD_OPC_CheckPredicate, 6, 15, 17, // Skip to: 13355 >+/* 8988 */ MCD_OPC_Decode, 133, 6, 116, // Opcode: FSAF_W >+/* 8992 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 9004 >+/* 8996 */ MCD_OPC_CheckPredicate, 6, 3, 17, // Skip to: 13355 >+/* 9000 */ MCD_OPC_Decode, 132, 6, 117, // Opcode: FSAF_D >+/* 9004 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 9016 >+/* 9008 */ MCD_OPC_CheckPredicate, 6, 247, 16, // Skip to: 13355 >+/* 9012 */ MCD_OPC_Decode, 167, 6, 116, // Opcode: FSUN_W >+/* 9016 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 9028 >+/* 9020 */ MCD_OPC_CheckPredicate, 6, 235, 16, // Skip to: 13355 >+/* 9024 */ MCD_OPC_Decode, 166, 6, 117, // Opcode: FSUN_D >+/* 9028 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 9040 >+/* 9032 */ MCD_OPC_CheckPredicate, 6, 223, 16, // Skip to: 13355 >+/* 9036 */ MCD_OPC_Decode, 135, 6, 116, // Opcode: FSEQ_W >+/* 9040 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 9052 >+/* 9044 */ MCD_OPC_CheckPredicate, 6, 211, 16, // Skip to: 13355 >+/* 9048 */ MCD_OPC_Decode, 134, 6, 117, // Opcode: FSEQ_D >+/* 9052 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 9064 >+/* 9056 */ MCD_OPC_CheckPredicate, 6, 199, 16, // Skip to: 13355 >+/* 9060 */ MCD_OPC_Decode, 159, 6, 116, // Opcode: FSUEQ_W >+/* 9064 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 9076 >+/* 9068 */ MCD_OPC_CheckPredicate, 6, 187, 16, // Skip to: 13355 >+/* 9072 */ MCD_OPC_Decode, 158, 6, 117, // Opcode: FSUEQ_D >+/* 9076 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 9088 >+/* 9080 */ MCD_OPC_CheckPredicate, 6, 175, 16, // Skip to: 13355 >+/* 9084 */ MCD_OPC_Decode, 139, 6, 116, // Opcode: FSLT_W >+/* 9088 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 9100 >+/* 9092 */ MCD_OPC_CheckPredicate, 6, 163, 16, // Skip to: 13355 >+/* 9096 */ MCD_OPC_Decode, 138, 6, 117, // Opcode: FSLT_D >+/* 9100 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 9112 >+/* 9104 */ MCD_OPC_CheckPredicate, 6, 151, 16, // Skip to: 13355 >+/* 9108 */ MCD_OPC_Decode, 163, 6, 116, // Opcode: FSULT_W >+/* 9112 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 9124 >+/* 9116 */ MCD_OPC_CheckPredicate, 6, 139, 16, // Skip to: 13355 >+/* 9120 */ MCD_OPC_Decode, 162, 6, 117, // Opcode: FSULT_D >+/* 9124 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 9136 >+/* 9128 */ MCD_OPC_CheckPredicate, 6, 127, 16, // Skip to: 13355 >+/* 9132 */ MCD_OPC_Decode, 137, 6, 116, // Opcode: FSLE_W >+/* 9136 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 9148 >+/* 9140 */ MCD_OPC_CheckPredicate, 6, 115, 16, // Skip to: 13355 >+/* 9144 */ MCD_OPC_Decode, 136, 6, 117, // Opcode: FSLE_D >+/* 9148 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 9160 >+/* 9152 */ MCD_OPC_CheckPredicate, 6, 103, 16, // Skip to: 13355 >+/* 9156 */ MCD_OPC_Decode, 161, 6, 116, // Opcode: FSULE_W >+/* 9160 */ MCD_OPC_FilterValue, 31, 95, 16, // Skip to: 13355 >+/* 9164 */ MCD_OPC_CheckPredicate, 6, 91, 16, // Skip to: 13355 >+/* 9168 */ MCD_OPC_Decode, 160, 6, 117, // Opcode: FSULE_D >+/* 9172 */ MCD_OPC_FilterValue, 27, 63, 1, // Skip to: 9495 >+/* 9176 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9179 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9191 >+/* 9183 */ MCD_OPC_CheckPredicate, 6, 72, 16, // Skip to: 13355 >+/* 9187 */ MCD_OPC_Decode, 155, 5, 116, // Opcode: FADD_W >+/* 9191 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 9203 >+/* 9195 */ MCD_OPC_CheckPredicate, 6, 60, 16, // Skip to: 13355 >+/* 9199 */ MCD_OPC_Decode, 149, 5, 117, // Opcode: FADD_D >+/* 9203 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 9215 >+/* 9207 */ MCD_OPC_CheckPredicate, 6, 48, 16, // Skip to: 13355 >+/* 9211 */ MCD_OPC_Decode, 157, 6, 116, // Opcode: FSUB_W >+/* 9215 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 9227 >+/* 9219 */ MCD_OPC_CheckPredicate, 6, 36, 16, // Skip to: 13355 >+/* 9223 */ MCD_OPC_Decode, 151, 6, 117, // Opcode: FSUB_D >+/* 9227 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 9239 >+/* 9231 */ MCD_OPC_CheckPredicate, 6, 24, 16, // Skip to: 13355 >+/* 9235 */ MCD_OPC_Decode, 248, 5, 116, // Opcode: FMUL_W >+/* 9239 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 9251 >+/* 9243 */ MCD_OPC_CheckPredicate, 6, 12, 16, // Skip to: 13355 >+/* 9247 */ MCD_OPC_Decode, 242, 5, 117, // Opcode: FMUL_D >+/* 9251 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9263 >+/* 9255 */ MCD_OPC_CheckPredicate, 6, 0, 16, // Skip to: 13355 >+/* 9259 */ MCD_OPC_Decode, 191, 5, 116, // Opcode: FDIV_W >+/* 9263 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 9275 >+/* 9267 */ MCD_OPC_CheckPredicate, 6, 244, 15, // Skip to: 13355 >+/* 9271 */ MCD_OPC_Decode, 185, 5, 117, // Opcode: FDIV_D >+/* 9275 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 9287 >+/* 9279 */ MCD_OPC_CheckPredicate, 6, 232, 15, // Skip to: 13355 >+/* 9283 */ MCD_OPC_Decode, 226, 5, 120, // Opcode: FMADD_W >+/* 9287 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 9299 >+/* 9291 */ MCD_OPC_CheckPredicate, 6, 220, 15, // Skip to: 13355 >+/* 9295 */ MCD_OPC_Decode, 225, 5, 121, // Opcode: FMADD_D >+/* 9299 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 9311 >+/* 9303 */ MCD_OPC_CheckPredicate, 6, 208, 15, // Skip to: 13355 >+/* 9307 */ MCD_OPC_Decode, 241, 5, 120, // Opcode: FMSUB_W >+/* 9311 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 9323 >+/* 9315 */ MCD_OPC_CheckPredicate, 6, 196, 15, // Skip to: 13355 >+/* 9319 */ MCD_OPC_Decode, 240, 5, 121, // Opcode: FMSUB_D >+/* 9323 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 9335 >+/* 9327 */ MCD_OPC_CheckPredicate, 6, 184, 15, // Skip to: 13355 >+/* 9331 */ MCD_OPC_Decode, 196, 5, 116, // Opcode: FEXP2_W >+/* 9335 */ MCD_OPC_FilterValue, 15, 8, 0, // Skip to: 9347 >+/* 9339 */ MCD_OPC_CheckPredicate, 6, 172, 15, // Skip to: 13355 >+/* 9343 */ MCD_OPC_Decode, 194, 5, 117, // Opcode: FEXP2_D >+/* 9347 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 9360 >+/* 9351 */ MCD_OPC_CheckPredicate, 6, 160, 15, // Skip to: 13355 >+/* 9355 */ MCD_OPC_Decode, 192, 5, 156, 1, // Opcode: FEXDO_H >+/* 9360 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 9373 >+/* 9364 */ MCD_OPC_CheckPredicate, 6, 147, 15, // Skip to: 13355 >+/* 9368 */ MCD_OPC_Decode, 193, 5, 157, 1, // Opcode: FEXDO_W >+/* 9373 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 9386 >+/* 9377 */ MCD_OPC_CheckPredicate, 6, 134, 15, // Skip to: 13355 >+/* 9381 */ MCD_OPC_Decode, 172, 6, 156, 1, // Opcode: FTQ_H >+/* 9386 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 9399 >+/* 9390 */ MCD_OPC_CheckPredicate, 6, 121, 15, // Skip to: 13355 >+/* 9394 */ MCD_OPC_Decode, 173, 6, 157, 1, // Opcode: FTQ_W >+/* 9399 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 9411 >+/* 9403 */ MCD_OPC_CheckPredicate, 6, 108, 15, // Skip to: 13355 >+/* 9407 */ MCD_OPC_Decode, 234, 5, 116, // Opcode: FMIN_W >+/* 9411 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 9423 >+/* 9415 */ MCD_OPC_CheckPredicate, 6, 96, 15, // Skip to: 13355 >+/* 9419 */ MCD_OPC_Decode, 233, 5, 117, // Opcode: FMIN_D >+/* 9423 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 9435 >+/* 9427 */ MCD_OPC_CheckPredicate, 6, 84, 15, // Skip to: 13355 >+/* 9431 */ MCD_OPC_Decode, 232, 5, 116, // Opcode: FMIN_A_W >+/* 9435 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 9447 >+/* 9439 */ MCD_OPC_CheckPredicate, 6, 72, 15, // Skip to: 13355 >+/* 9443 */ MCD_OPC_Decode, 231, 5, 117, // Opcode: FMIN_A_D >+/* 9447 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 9459 >+/* 9451 */ MCD_OPC_CheckPredicate, 6, 60, 15, // Skip to: 13355 >+/* 9455 */ MCD_OPC_Decode, 230, 5, 116, // Opcode: FMAX_W >+/* 9459 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 9471 >+/* 9463 */ MCD_OPC_CheckPredicate, 6, 48, 15, // Skip to: 13355 >+/* 9467 */ MCD_OPC_Decode, 229, 5, 117, // Opcode: FMAX_D >+/* 9471 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 9483 >+/* 9475 */ MCD_OPC_CheckPredicate, 6, 36, 15, // Skip to: 13355 >+/* 9479 */ MCD_OPC_Decode, 228, 5, 116, // Opcode: FMAX_A_W >+/* 9483 */ MCD_OPC_FilterValue, 31, 28, 15, // Skip to: 13355 >+/* 9487 */ MCD_OPC_CheckPredicate, 6, 24, 15, // Skip to: 13355 >+/* 9491 */ MCD_OPC_Decode, 227, 5, 117, // Opcode: FMAX_A_D >+/* 9495 */ MCD_OPC_FilterValue, 28, 35, 1, // Skip to: 9790 >+/* 9499 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9502 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 9514 >+/* 9506 */ MCD_OPC_CheckPredicate, 6, 5, 15, // Skip to: 13355 >+/* 9510 */ MCD_OPC_Decode, 174, 5, 116, // Opcode: FCOR_W >+/* 9514 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 9526 >+/* 9518 */ MCD_OPC_CheckPredicate, 6, 249, 14, // Skip to: 13355 >+/* 9522 */ MCD_OPC_Decode, 173, 5, 117, // Opcode: FCOR_D >+/* 9526 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 9538 >+/* 9530 */ MCD_OPC_CheckPredicate, 6, 237, 14, // Skip to: 13355 >+/* 9534 */ MCD_OPC_Decode, 182, 5, 116, // Opcode: FCUNE_W >+/* 9538 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 9550 >+/* 9542 */ MCD_OPC_CheckPredicate, 6, 225, 14, // Skip to: 13355 >+/* 9546 */ MCD_OPC_Decode, 181, 5, 117, // Opcode: FCUNE_D >+/* 9550 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9562 >+/* 9554 */ MCD_OPC_CheckPredicate, 6, 213, 14, // Skip to: 13355 >+/* 9558 */ MCD_OPC_Decode, 172, 5, 116, // Opcode: FCNE_W >+/* 9562 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 9574 >+/* 9566 */ MCD_OPC_CheckPredicate, 6, 201, 14, // Skip to: 13355 >+/* 9570 */ MCD_OPC_Decode, 171, 5, 117, // Opcode: FCNE_D >+/* 9574 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 9586 >+/* 9578 */ MCD_OPC_CheckPredicate, 6, 189, 14, // Skip to: 13355 >+/* 9582 */ MCD_OPC_Decode, 180, 9, 115, // Opcode: MUL_Q_H >+/* 9586 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 9598 >+/* 9590 */ MCD_OPC_CheckPredicate, 6, 177, 14, // Skip to: 13355 >+/* 9594 */ MCD_OPC_Decode, 181, 9, 116, // Opcode: MUL_Q_W >+/* 9598 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 9610 >+/* 9602 */ MCD_OPC_CheckPredicate, 6, 165, 14, // Skip to: 13355 >+/* 9606 */ MCD_OPC_Decode, 237, 7, 119, // Opcode: MADD_Q_H >+/* 9610 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 9622 >+/* 9614 */ MCD_OPC_CheckPredicate, 6, 153, 14, // Skip to: 13355 >+/* 9618 */ MCD_OPC_Decode, 238, 7, 120, // Opcode: MADD_Q_W >+/* 9622 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 9634 >+/* 9626 */ MCD_OPC_CheckPredicate, 6, 141, 14, // Skip to: 13355 >+/* 9630 */ MCD_OPC_Decode, 254, 8, 119, // Opcode: MSUB_Q_H >+/* 9634 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 9646 >+/* 9638 */ MCD_OPC_CheckPredicate, 6, 129, 14, // Skip to: 13355 >+/* 9642 */ MCD_OPC_Decode, 255, 8, 120, // Opcode: MSUB_Q_W >+/* 9646 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 9658 >+/* 9650 */ MCD_OPC_CheckPredicate, 6, 117, 14, // Skip to: 13355 >+/* 9654 */ MCD_OPC_Decode, 143, 6, 116, // Opcode: FSOR_W >+/* 9658 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 9670 >+/* 9662 */ MCD_OPC_CheckPredicate, 6, 105, 14, // Skip to: 13355 >+/* 9666 */ MCD_OPC_Decode, 142, 6, 117, // Opcode: FSOR_D >+/* 9670 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 9682 >+/* 9674 */ MCD_OPC_CheckPredicate, 6, 93, 14, // Skip to: 13355 >+/* 9678 */ MCD_OPC_Decode, 165, 6, 116, // Opcode: FSUNE_W >+/* 9682 */ MCD_OPC_FilterValue, 21, 8, 0, // Skip to: 9694 >+/* 9686 */ MCD_OPC_CheckPredicate, 6, 81, 14, // Skip to: 13355 >+/* 9690 */ MCD_OPC_Decode, 164, 6, 117, // Opcode: FSUNE_D >+/* 9694 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 9706 >+/* 9698 */ MCD_OPC_CheckPredicate, 6, 69, 14, // Skip to: 13355 >+/* 9702 */ MCD_OPC_Decode, 141, 6, 116, // Opcode: FSNE_W >+/* 9706 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 9718 >+/* 9710 */ MCD_OPC_CheckPredicate, 6, 57, 14, // Skip to: 13355 >+/* 9714 */ MCD_OPC_Decode, 140, 6, 117, // Opcode: FSNE_D >+/* 9718 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 9730 >+/* 9722 */ MCD_OPC_CheckPredicate, 6, 45, 14, // Skip to: 13355 >+/* 9726 */ MCD_OPC_Decode, 163, 9, 115, // Opcode: MULR_Q_H >+/* 9730 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 9742 >+/* 9734 */ MCD_OPC_CheckPredicate, 6, 33, 14, // Skip to: 13355 >+/* 9738 */ MCD_OPC_Decode, 164, 9, 116, // Opcode: MULR_Q_W >+/* 9742 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 9754 >+/* 9746 */ MCD_OPC_CheckPredicate, 6, 21, 14, // Skip to: 13355 >+/* 9750 */ MCD_OPC_Decode, 223, 7, 119, // Opcode: MADDR_Q_H >+/* 9754 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 9766 >+/* 9758 */ MCD_OPC_CheckPredicate, 6, 9, 14, // Skip to: 13355 >+/* 9762 */ MCD_OPC_Decode, 224, 7, 120, // Opcode: MADDR_Q_W >+/* 9766 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 9778 >+/* 9770 */ MCD_OPC_CheckPredicate, 6, 253, 13, // Skip to: 13355 >+/* 9774 */ MCD_OPC_Decode, 240, 8, 119, // Opcode: MSUBR_Q_H >+/* 9778 */ MCD_OPC_FilterValue, 29, 245, 13, // Skip to: 13355 >+/* 9782 */ MCD_OPC_CheckPredicate, 6, 241, 13, // Skip to: 13355 >+/* 9786 */ MCD_OPC_Decode, 241, 8, 120, // Opcode: MSUBR_Q_W >+/* 9790 */ MCD_OPC_FilterValue, 30, 212, 2, // Skip to: 10518 >+/* 9794 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 9797 */ MCD_OPC_FilterValue, 0, 7, 0, // Skip to: 9808 >+/* 9801 */ MCD_OPC_CheckPredicate, 6, 222, 13, // Skip to: 13355 >+/* 9805 */ MCD_OPC_Decode, 79, 114, // Opcode: AND_V >+/* 9808 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 9820 >+/* 9812 */ MCD_OPC_CheckPredicate, 6, 211, 13, // Skip to: 13355 >+/* 9816 */ MCD_OPC_Decode, 225, 9, 114, // Opcode: OR_V >+/* 9820 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 9832 >+/* 9824 */ MCD_OPC_CheckPredicate, 6, 199, 13, // Skip to: 13355 >+/* 9828 */ MCD_OPC_Decode, 215, 9, 114, // Opcode: NOR_V >+/* 9832 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 9844 >+/* 9836 */ MCD_OPC_CheckPredicate, 6, 187, 13, // Skip to: 13355 >+/* 9840 */ MCD_OPC_Decode, 166, 13, 114, // Opcode: XOR_V >+/* 9844 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 9856 >+/* 9848 */ MCD_OPC_CheckPredicate, 6, 175, 13, // Skip to: 13355 >+/* 9852 */ MCD_OPC_Decode, 254, 1, 118, // Opcode: BMNZ_V >+/* 9856 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 9868 >+/* 9860 */ MCD_OPC_CheckPredicate, 6, 163, 13, // Skip to: 13355 >+/* 9864 */ MCD_OPC_Decode, 128, 2, 118, // Opcode: BMZ_V >+/* 9868 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9880 >+/* 9872 */ MCD_OPC_CheckPredicate, 6, 151, 13, // Skip to: 13355 >+/* 9876 */ MCD_OPC_Decode, 161, 2, 118, // Opcode: BSEL_V >+/* 9880 */ MCD_OPC_FilterValue, 24, 211, 0, // Skip to: 10095 >+/* 9884 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 9887 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 9900 >+/* 9891 */ MCD_OPC_CheckPredicate, 6, 132, 13, // Skip to: 13355 >+/* 9895 */ MCD_OPC_Decode, 210, 5, 158, 1, // Opcode: FILL_B >+/* 9900 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 9913 >+/* 9904 */ MCD_OPC_CheckPredicate, 6, 119, 13, // Skip to: 13355 >+/* 9908 */ MCD_OPC_Decode, 214, 5, 159, 1, // Opcode: FILL_H >+/* 9913 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 9926 >+/* 9917 */ MCD_OPC_CheckPredicate, 6, 106, 13, // Skip to: 13355 >+/* 9921 */ MCD_OPC_Decode, 215, 5, 160, 1, // Opcode: FILL_W >+/* 9926 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 9939 >+/* 9930 */ MCD_OPC_CheckPredicate, 13, 93, 13, // Skip to: 13355 >+/* 9934 */ MCD_OPC_Decode, 211, 5, 161, 1, // Opcode: FILL_D >+/* 9939 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 9952 >+/* 9943 */ MCD_OPC_CheckPredicate, 6, 80, 13, // Skip to: 13355 >+/* 9947 */ MCD_OPC_Decode, 243, 9, 150, 1, // Opcode: PCNT_B >+/* 9952 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 9965 >+/* 9956 */ MCD_OPC_CheckPredicate, 6, 67, 13, // Skip to: 13355 >+/* 9960 */ MCD_OPC_Decode, 245, 9, 162, 1, // Opcode: PCNT_H >+/* 9965 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 9978 >+/* 9969 */ MCD_OPC_CheckPredicate, 6, 54, 13, // Skip to: 13355 >+/* 9973 */ MCD_OPC_Decode, 246, 9, 163, 1, // Opcode: PCNT_W >+/* 9978 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 9991 >+/* 9982 */ MCD_OPC_CheckPredicate, 6, 41, 13, // Skip to: 13355 >+/* 9986 */ MCD_OPC_Decode, 244, 9, 164, 1, // Opcode: PCNT_D >+/* 9991 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10004 >+/* 9995 */ MCD_OPC_CheckPredicate, 6, 28, 13, // Skip to: 13355 >+/* 9999 */ MCD_OPC_Decode, 192, 9, 150, 1, // Opcode: NLOC_B >+/* 10004 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10017 >+/* 10008 */ MCD_OPC_CheckPredicate, 6, 15, 13, // Skip to: 13355 >+/* 10012 */ MCD_OPC_Decode, 194, 9, 162, 1, // Opcode: NLOC_H >+/* 10017 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10030 >+/* 10021 */ MCD_OPC_CheckPredicate, 6, 2, 13, // Skip to: 13355 >+/* 10025 */ MCD_OPC_Decode, 195, 9, 163, 1, // Opcode: NLOC_W >+/* 10030 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10043 >+/* 10034 */ MCD_OPC_CheckPredicate, 6, 245, 12, // Skip to: 13355 >+/* 10038 */ MCD_OPC_Decode, 193, 9, 164, 1, // Opcode: NLOC_D >+/* 10043 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10056 >+/* 10047 */ MCD_OPC_CheckPredicate, 6, 232, 12, // Skip to: 13355 >+/* 10051 */ MCD_OPC_Decode, 196, 9, 150, 1, // Opcode: NLZC_B >+/* 10056 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10069 >+/* 10060 */ MCD_OPC_CheckPredicate, 6, 219, 12, // Skip to: 13355 >+/* 10064 */ MCD_OPC_Decode, 198, 9, 162, 1, // Opcode: NLZC_H >+/* 10069 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10082 >+/* 10073 */ MCD_OPC_CheckPredicate, 6, 206, 12, // Skip to: 13355 >+/* 10077 */ MCD_OPC_Decode, 199, 9, 163, 1, // Opcode: NLZC_W >+/* 10082 */ MCD_OPC_FilterValue, 15, 197, 12, // Skip to: 13355 >+/* 10086 */ MCD_OPC_CheckPredicate, 6, 193, 12, // Skip to: 13355 >+/* 10090 */ MCD_OPC_Decode, 197, 9, 164, 1, // Opcode: NLZC_D >+/* 10095 */ MCD_OPC_FilterValue, 25, 184, 12, // Skip to: 13355 >+/* 10099 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 10102 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10115 >+/* 10106 */ MCD_OPC_CheckPredicate, 6, 173, 12, // Skip to: 13355 >+/* 10110 */ MCD_OPC_Decode, 161, 5, 163, 1, // Opcode: FCLASS_W >+/* 10115 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10128 >+/* 10119 */ MCD_OPC_CheckPredicate, 6, 160, 12, // Skip to: 13355 >+/* 10123 */ MCD_OPC_Decode, 160, 5, 164, 1, // Opcode: FCLASS_D >+/* 10128 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 10141 >+/* 10132 */ MCD_OPC_CheckPredicate, 6, 147, 12, // Skip to: 13355 >+/* 10136 */ MCD_OPC_Decode, 175, 6, 163, 1, // Opcode: FTRUNC_S_W >+/* 10141 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 10154 >+/* 10145 */ MCD_OPC_CheckPredicate, 6, 134, 12, // Skip to: 13355 >+/* 10149 */ MCD_OPC_Decode, 174, 6, 164, 1, // Opcode: FTRUNC_S_D >+/* 10154 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10167 >+/* 10158 */ MCD_OPC_CheckPredicate, 6, 121, 12, // Skip to: 13355 >+/* 10162 */ MCD_OPC_Decode, 177, 6, 163, 1, // Opcode: FTRUNC_U_W >+/* 10167 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10180 >+/* 10171 */ MCD_OPC_CheckPredicate, 6, 108, 12, // Skip to: 13355 >+/* 10175 */ MCD_OPC_Decode, 176, 6, 164, 1, // Opcode: FTRUNC_U_D >+/* 10180 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10193 >+/* 10184 */ MCD_OPC_CheckPredicate, 6, 95, 12, // Skip to: 13355 >+/* 10188 */ MCD_OPC_Decode, 150, 6, 163, 1, // Opcode: FSQRT_W >+/* 10193 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10206 >+/* 10197 */ MCD_OPC_CheckPredicate, 6, 82, 12, // Skip to: 13355 >+/* 10201 */ MCD_OPC_Decode, 144, 6, 164, 1, // Opcode: FSQRT_D >+/* 10206 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 10219 >+/* 10210 */ MCD_OPC_CheckPredicate, 6, 69, 12, // Skip to: 13355 >+/* 10214 */ MCD_OPC_Decode, 131, 6, 163, 1, // Opcode: FRSQRT_W >+/* 10219 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10232 >+/* 10223 */ MCD_OPC_CheckPredicate, 6, 56, 12, // Skip to: 13355 >+/* 10227 */ MCD_OPC_Decode, 130, 6, 164, 1, // Opcode: FRSQRT_D >+/* 10232 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 10245 >+/* 10236 */ MCD_OPC_CheckPredicate, 6, 43, 12, // Skip to: 13355 >+/* 10240 */ MCD_OPC_Decode, 255, 5, 163, 1, // Opcode: FRCP_W >+/* 10245 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10258 >+/* 10249 */ MCD_OPC_CheckPredicate, 6, 30, 12, // Skip to: 13355 >+/* 10253 */ MCD_OPC_Decode, 254, 5, 164, 1, // Opcode: FRCP_D >+/* 10258 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 10271 >+/* 10262 */ MCD_OPC_CheckPredicate, 6, 17, 12, // Skip to: 13355 >+/* 10266 */ MCD_OPC_Decode, 129, 6, 163, 1, // Opcode: FRINT_W >+/* 10271 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10284 >+/* 10275 */ MCD_OPC_CheckPredicate, 6, 4, 12, // Skip to: 13355 >+/* 10279 */ MCD_OPC_Decode, 128, 6, 164, 1, // Opcode: FRINT_D >+/* 10284 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 10297 >+/* 10288 */ MCD_OPC_CheckPredicate, 6, 247, 11, // Skip to: 13355 >+/* 10292 */ MCD_OPC_Decode, 217, 5, 163, 1, // Opcode: FLOG2_W >+/* 10297 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10310 >+/* 10301 */ MCD_OPC_CheckPredicate, 6, 234, 11, // Skip to: 13355 >+/* 10305 */ MCD_OPC_Decode, 216, 5, 164, 1, // Opcode: FLOG2_D >+/* 10310 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 10323 >+/* 10314 */ MCD_OPC_CheckPredicate, 6, 221, 11, // Skip to: 13355 >+/* 10318 */ MCD_OPC_Decode, 199, 5, 165, 1, // Opcode: FEXUPL_W >+/* 10323 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 10336 >+/* 10327 */ MCD_OPC_CheckPredicate, 6, 208, 11, // Skip to: 13355 >+/* 10331 */ MCD_OPC_Decode, 198, 5, 166, 1, // Opcode: FEXUPL_D >+/* 10336 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 10349 >+/* 10340 */ MCD_OPC_CheckPredicate, 6, 195, 11, // Skip to: 13355 >+/* 10344 */ MCD_OPC_Decode, 201, 5, 165, 1, // Opcode: FEXUPR_W >+/* 10349 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 10362 >+/* 10353 */ MCD_OPC_CheckPredicate, 6, 182, 11, // Skip to: 13355 >+/* 10357 */ MCD_OPC_Decode, 200, 5, 166, 1, // Opcode: FEXUPR_D >+/* 10362 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 10375 >+/* 10366 */ MCD_OPC_CheckPredicate, 6, 169, 11, // Skip to: 13355 >+/* 10370 */ MCD_OPC_Decode, 207, 5, 165, 1, // Opcode: FFQL_W >+/* 10375 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 10388 >+/* 10379 */ MCD_OPC_CheckPredicate, 6, 156, 11, // Skip to: 13355 >+/* 10383 */ MCD_OPC_Decode, 206, 5, 166, 1, // Opcode: FFQL_D >+/* 10388 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 10401 >+/* 10392 */ MCD_OPC_CheckPredicate, 6, 143, 11, // Skip to: 13355 >+/* 10396 */ MCD_OPC_Decode, 209, 5, 165, 1, // Opcode: FFQR_W >+/* 10401 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 10414 >+/* 10405 */ MCD_OPC_CheckPredicate, 6, 130, 11, // Skip to: 13355 >+/* 10409 */ MCD_OPC_Decode, 208, 5, 166, 1, // Opcode: FFQR_D >+/* 10414 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 10427 >+/* 10418 */ MCD_OPC_CheckPredicate, 6, 117, 11, // Skip to: 13355 >+/* 10422 */ MCD_OPC_Decode, 169, 6, 163, 1, // Opcode: FTINT_S_W >+/* 10427 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 10440 >+/* 10431 */ MCD_OPC_CheckPredicate, 6, 104, 11, // Skip to: 13355 >+/* 10435 */ MCD_OPC_Decode, 168, 6, 164, 1, // Opcode: FTINT_S_D >+/* 10440 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 10453 >+/* 10444 */ MCD_OPC_CheckPredicate, 6, 91, 11, // Skip to: 13355 >+/* 10448 */ MCD_OPC_Decode, 171, 6, 163, 1, // Opcode: FTINT_U_W >+/* 10453 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 10466 >+/* 10457 */ MCD_OPC_CheckPredicate, 6, 78, 11, // Skip to: 13355 >+/* 10461 */ MCD_OPC_Decode, 170, 6, 164, 1, // Opcode: FTINT_U_D >+/* 10466 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10479 >+/* 10470 */ MCD_OPC_CheckPredicate, 6, 65, 11, // Skip to: 13355 >+/* 10474 */ MCD_OPC_Decode, 203, 5, 163, 1, // Opcode: FFINT_S_W >+/* 10479 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 10492 >+/* 10483 */ MCD_OPC_CheckPredicate, 6, 52, 11, // Skip to: 13355 >+/* 10487 */ MCD_OPC_Decode, 202, 5, 164, 1, // Opcode: FFINT_S_D >+/* 10492 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 10505 >+/* 10496 */ MCD_OPC_CheckPredicate, 6, 39, 11, // Skip to: 13355 >+/* 10500 */ MCD_OPC_Decode, 205, 5, 163, 1, // Opcode: FFINT_U_W >+/* 10505 */ MCD_OPC_FilterValue, 31, 30, 11, // Skip to: 13355 >+/* 10509 */ MCD_OPC_CheckPredicate, 6, 26, 11, // Skip to: 13355 >+/* 10513 */ MCD_OPC_Decode, 204, 5, 164, 1, // Opcode: FFINT_U_D >+/* 10518 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 10531 >+/* 10522 */ MCD_OPC_CheckPredicate, 6, 13, 11, // Skip to: 13355 >+/* 10526 */ MCD_OPC_Decode, 149, 7, 167, 1, // Opcode: LD_B >+/* 10531 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 10544 >+/* 10535 */ MCD_OPC_CheckPredicate, 6, 0, 11, // Skip to: 13355 >+/* 10539 */ MCD_OPC_Decode, 151, 7, 167, 1, // Opcode: LD_H >+/* 10544 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 10557 >+/* 10548 */ MCD_OPC_CheckPredicate, 6, 243, 10, // Skip to: 13355 >+/* 10552 */ MCD_OPC_Decode, 152, 7, 167, 1, // Opcode: LD_W >+/* 10557 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 10570 >+/* 10561 */ MCD_OPC_CheckPredicate, 6, 230, 10, // Skip to: 13355 >+/* 10565 */ MCD_OPC_Decode, 150, 7, 167, 1, // Opcode: LD_D >+/* 10570 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 10583 >+/* 10574 */ MCD_OPC_CheckPredicate, 6, 217, 10, // Skip to: 13355 >+/* 10578 */ MCD_OPC_Decode, 248, 11, 167, 1, // Opcode: ST_B >+/* 10583 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 10596 >+/* 10587 */ MCD_OPC_CheckPredicate, 6, 204, 10, // Skip to: 13355 >+/* 10591 */ MCD_OPC_Decode, 250, 11, 167, 1, // Opcode: ST_H >+/* 10596 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 10609 >+/* 10600 */ MCD_OPC_CheckPredicate, 6, 191, 10, // Skip to: 13355 >+/* 10604 */ MCD_OPC_Decode, 251, 11, 167, 1, // Opcode: ST_W >+/* 10609 */ MCD_OPC_FilterValue, 39, 182, 10, // Skip to: 13355 >+/* 10613 */ MCD_OPC_CheckPredicate, 6, 178, 10, // Skip to: 13355 >+/* 10617 */ MCD_OPC_Decode, 249, 11, 167, 1, // Opcode: ST_D >+/* 10622 */ MCD_OPC_FilterValue, 31, 113, 9, // Skip to: 13043 >+/* 10626 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10629 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10642 >+/* 10633 */ MCD_OPC_CheckPredicate, 4, 158, 10, // Skip to: 13355 >+/* 10637 */ MCD_OPC_Decode, 252, 4, 168, 1, // Opcode: EXT >+/* 10642 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10655 >+/* 10646 */ MCD_OPC_CheckPredicate, 4, 145, 10, // Skip to: 13355 >+/* 10650 */ MCD_OPC_Decode, 207, 6, 169, 1, // Opcode: INS >+/* 10655 */ MCD_OPC_FilterValue, 10, 42, 0, // Skip to: 10701 >+/* 10659 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 10662 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10675 >+/* 10666 */ MCD_OPC_CheckPredicate, 11, 125, 10, // Skip to: 13355 >+/* 10670 */ MCD_OPC_Decode, 199, 7, 170, 1, // Opcode: LWX >+/* 10675 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 10688 >+/* 10679 */ MCD_OPC_CheckPredicate, 11, 112, 10, // Skip to: 13355 >+/* 10683 */ MCD_OPC_Decode, 158, 7, 170, 1, // Opcode: LHX >+/* 10688 */ MCD_OPC_FilterValue, 6, 103, 10, // Skip to: 13355 >+/* 10692 */ MCD_OPC_CheckPredicate, 11, 99, 10, // Skip to: 13355 >+/* 10696 */ MCD_OPC_Decode, 128, 7, 170, 1, // Opcode: LBUX >+/* 10701 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 10720 >+/* 10705 */ MCD_OPC_CheckPredicate, 11, 86, 10, // Skip to: 13355 >+/* 10709 */ MCD_OPC_CheckField, 6, 10, 0, 80, 10, // Skip to: 13355 >+/* 10715 */ MCD_OPC_Decode, 220, 6, 171, 1, // Opcode: INSV >+/* 10720 */ MCD_OPC_FilterValue, 16, 51, 1, // Skip to: 11031 >+/* 10724 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 10727 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10739 >+/* 10731 */ MCD_OPC_CheckPredicate, 11, 60, 10, // Skip to: 13355 >+/* 10735 */ MCD_OPC_Decode, 48, 172, 1, // Opcode: ADDU_QB >+/* 10739 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 10752 >+/* 10743 */ MCD_OPC_CheckPredicate, 11, 48, 10, // Skip to: 13355 >+/* 10747 */ MCD_OPC_Decode, 151, 12, 172, 1, // Opcode: SUBU_QB >+/* 10752 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 10764 >+/* 10756 */ MCD_OPC_CheckPredicate, 11, 35, 10, // Skip to: 13355 >+/* 10760 */ MCD_OPC_Decode, 50, 172, 1, // Opcode: ADDU_S_QB >+/* 10764 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 10777 >+/* 10768 */ MCD_OPC_CheckPredicate, 11, 23, 10, // Skip to: 13355 >+/* 10772 */ MCD_OPC_Decode, 153, 12, 172, 1, // Opcode: SUBU_S_QB >+/* 10777 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 10790 >+/* 10781 */ MCD_OPC_CheckPredicate, 11, 10, 10, // Skip to: 13355 >+/* 10785 */ MCD_OPC_Decode, 157, 9, 172, 1, // Opcode: MULEU_S_PH_QBL >+/* 10790 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 10803 >+/* 10794 */ MCD_OPC_CheckPredicate, 11, 253, 9, // Skip to: 13355 >+/* 10798 */ MCD_OPC_Decode, 158, 9, 172, 1, // Opcode: MULEU_S_PH_QBR >+/* 10803 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 10815 >+/* 10807 */ MCD_OPC_CheckPredicate, 29, 240, 9, // Skip to: 13355 >+/* 10811 */ MCD_OPC_Decode, 47, 172, 1, // Opcode: ADDU_PH >+/* 10815 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 10828 >+/* 10819 */ MCD_OPC_CheckPredicate, 29, 228, 9, // Skip to: 13355 >+/* 10823 */ MCD_OPC_Decode, 150, 12, 172, 1, // Opcode: SUBU_PH >+/* 10828 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 10840 >+/* 10832 */ MCD_OPC_CheckPredicate, 11, 215, 9, // Skip to: 13355 >+/* 10836 */ MCD_OPC_Decode, 29, 172, 1, // Opcode: ADDQ_PH >+/* 10840 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 10853 >+/* 10844 */ MCD_OPC_CheckPredicate, 11, 203, 9, // Skip to: 13355 >+/* 10848 */ MCD_OPC_Decode, 129, 12, 172, 1, // Opcode: SUBQ_PH >+/* 10853 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 10865 >+/* 10857 */ MCD_OPC_CheckPredicate, 29, 190, 9, // Skip to: 13355 >+/* 10861 */ MCD_OPC_Decode, 49, 172, 1, // Opcode: ADDU_S_PH >+/* 10865 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 10878 >+/* 10869 */ MCD_OPC_CheckPredicate, 29, 178, 9, // Skip to: 13355 >+/* 10873 */ MCD_OPC_Decode, 152, 12, 172, 1, // Opcode: SUBU_S_PH >+/* 10878 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 10890 >+/* 10882 */ MCD_OPC_CheckPredicate, 11, 165, 9, // Skip to: 13355 >+/* 10886 */ MCD_OPC_Decode, 30, 172, 1, // Opcode: ADDQ_S_PH >+/* 10890 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 10903 >+/* 10894 */ MCD_OPC_CheckPredicate, 11, 153, 9, // Skip to: 13355 >+/* 10898 */ MCD_OPC_Decode, 130, 12, 172, 1, // Opcode: SUBQ_S_PH >+/* 10903 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 10914 >+/* 10907 */ MCD_OPC_CheckPredicate, 11, 140, 9, // Skip to: 13355 >+/* 10911 */ MCD_OPC_Decode, 32, 17, // Opcode: ADDSC >+/* 10914 */ MCD_OPC_FilterValue, 17, 7, 0, // Skip to: 10925 >+/* 10918 */ MCD_OPC_CheckPredicate, 11, 129, 9, // Skip to: 13355 >+/* 10922 */ MCD_OPC_Decode, 59, 17, // Opcode: ADDWC >+/* 10925 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 10937 >+/* 10929 */ MCD_OPC_CheckPredicate, 11, 118, 9, // Skip to: 13355 >+/* 10933 */ MCD_OPC_Decode, 185, 8, 17, // Opcode: MODSUB >+/* 10937 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 10956 >+/* 10941 */ MCD_OPC_CheckPredicate, 11, 106, 9, // Skip to: 13355 >+/* 10945 */ MCD_OPC_CheckField, 16, 5, 0, 100, 9, // Skip to: 13355 >+/* 10951 */ MCD_OPC_Decode, 178, 10, 173, 1, // Opcode: RADDU_W_QB >+/* 10956 */ MCD_OPC_FilterValue, 22, 7, 0, // Skip to: 10967 >+/* 10960 */ MCD_OPC_CheckPredicate, 11, 87, 9, // Skip to: 13355 >+/* 10964 */ MCD_OPC_Decode, 31, 17, // Opcode: ADDQ_S_W >+/* 10967 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 10979 >+/* 10971 */ MCD_OPC_CheckPredicate, 11, 76, 9, // Skip to: 13355 >+/* 10975 */ MCD_OPC_Decode, 131, 12, 17, // Opcode: SUBQ_S_W >+/* 10979 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 10992 >+/* 10983 */ MCD_OPC_CheckPredicate, 11, 64, 9, // Skip to: 13355 >+/* 10987 */ MCD_OPC_Decode, 155, 9, 174, 1, // Opcode: MULEQ_S_W_PHL >+/* 10992 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 11005 >+/* 10996 */ MCD_OPC_CheckPredicate, 11, 51, 9, // Skip to: 13355 >+/* 11000 */ MCD_OPC_Decode, 156, 9, 174, 1, // Opcode: MULEQ_S_W_PHR >+/* 11005 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11018 >+/* 11009 */ MCD_OPC_CheckPredicate, 29, 38, 9, // Skip to: 13355 >+/* 11013 */ MCD_OPC_Decode, 161, 9, 172, 1, // Opcode: MULQ_S_PH >+/* 11018 */ MCD_OPC_FilterValue, 31, 29, 9, // Skip to: 13355 >+/* 11022 */ MCD_OPC_CheckPredicate, 11, 25, 9, // Skip to: 13355 >+/* 11026 */ MCD_OPC_Decode, 159, 9, 172, 1, // Opcode: MULQ_RS_PH >+/* 11031 */ MCD_OPC_FilterValue, 17, 69, 1, // Skip to: 11360 >+/* 11035 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11038 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 11057 >+/* 11042 */ MCD_OPC_CheckPredicate, 11, 5, 9, // Skip to: 13355 >+/* 11046 */ MCD_OPC_CheckField, 11, 5, 0, 255, 8, // Skip to: 13355 >+/* 11052 */ MCD_OPC_Decode, 141, 3, 175, 1, // Opcode: CMPU_EQ_QB >+/* 11057 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 11076 >+/* 11061 */ MCD_OPC_CheckPredicate, 11, 242, 8, // Skip to: 13355 >+/* 11065 */ MCD_OPC_CheckField, 11, 5, 0, 236, 8, // Skip to: 13355 >+/* 11071 */ MCD_OPC_Decode, 143, 3, 175, 1, // Opcode: CMPU_LT_QB >+/* 11076 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 11095 >+/* 11080 */ MCD_OPC_CheckPredicate, 11, 223, 8, // Skip to: 13355 >+/* 11084 */ MCD_OPC_CheckField, 11, 5, 0, 217, 8, // Skip to: 13355 >+/* 11090 */ MCD_OPC_Decode, 142, 3, 175, 1, // Opcode: CMPU_LE_QB >+/* 11095 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11108 >+/* 11099 */ MCD_OPC_CheckPredicate, 11, 204, 8, // Skip to: 13355 >+/* 11103 */ MCD_OPC_Decode, 248, 9, 172, 1, // Opcode: PICK_QB >+/* 11108 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11121 >+/* 11112 */ MCD_OPC_CheckPredicate, 11, 191, 8, // Skip to: 13355 >+/* 11116 */ MCD_OPC_Decode, 138, 3, 174, 1, // Opcode: CMPGU_EQ_QB >+/* 11121 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11134 >+/* 11125 */ MCD_OPC_CheckPredicate, 11, 178, 8, // Skip to: 13355 >+/* 11129 */ MCD_OPC_Decode, 140, 3, 174, 1, // Opcode: CMPGU_LT_QB >+/* 11134 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11147 >+/* 11138 */ MCD_OPC_CheckPredicate, 11, 165, 8, // Skip to: 13355 >+/* 11142 */ MCD_OPC_Decode, 139, 3, 174, 1, // Opcode: CMPGU_LE_QB >+/* 11147 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 11166 >+/* 11151 */ MCD_OPC_CheckPredicate, 11, 152, 8, // Skip to: 13355 >+/* 11155 */ MCD_OPC_CheckField, 11, 5, 0, 146, 8, // Skip to: 13355 >+/* 11161 */ MCD_OPC_Decode, 145, 3, 175, 1, // Opcode: CMP_EQ_PH >+/* 11166 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 11185 >+/* 11170 */ MCD_OPC_CheckPredicate, 11, 133, 8, // Skip to: 13355 >+/* 11174 */ MCD_OPC_CheckField, 11, 5, 0, 127, 8, // Skip to: 13355 >+/* 11180 */ MCD_OPC_Decode, 153, 3, 175, 1, // Opcode: CMP_LT_PH >+/* 11185 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 11204 >+/* 11189 */ MCD_OPC_CheckPredicate, 11, 114, 8, // Skip to: 13355 >+/* 11193 */ MCD_OPC_CheckField, 11, 5, 0, 108, 8, // Skip to: 13355 >+/* 11199 */ MCD_OPC_Decode, 150, 3, 175, 1, // Opcode: CMP_LE_PH >+/* 11204 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11217 >+/* 11208 */ MCD_OPC_CheckPredicate, 11, 95, 8, // Skip to: 13355 >+/* 11212 */ MCD_OPC_Decode, 247, 9, 172, 1, // Opcode: PICK_PH >+/* 11217 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11230 >+/* 11221 */ MCD_OPC_CheckPredicate, 11, 82, 8, // Skip to: 13355 >+/* 11225 */ MCD_OPC_Decode, 134, 10, 172, 1, // Opcode: PRECRQ_QB_PH >+/* 11230 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11243 >+/* 11234 */ MCD_OPC_CheckPredicate, 29, 69, 8, // Skip to: 13355 >+/* 11238 */ MCD_OPC_Decode, 136, 10, 172, 1, // Opcode: PRECR_QB_PH >+/* 11243 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11256 >+/* 11247 */ MCD_OPC_CheckPredicate, 11, 56, 8, // Skip to: 13355 >+/* 11251 */ MCD_OPC_Decode, 233, 9, 172, 1, // Opcode: PACKRL_PH >+/* 11256 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11269 >+/* 11260 */ MCD_OPC_CheckPredicate, 11, 43, 8, // Skip to: 13355 >+/* 11264 */ MCD_OPC_Decode, 132, 10, 172, 1, // Opcode: PRECRQU_S_QB_PH >+/* 11269 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11282 >+/* 11273 */ MCD_OPC_CheckPredicate, 11, 30, 8, // Skip to: 13355 >+/* 11277 */ MCD_OPC_Decode, 133, 10, 176, 1, // Opcode: PRECRQ_PH_W >+/* 11282 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11295 >+/* 11286 */ MCD_OPC_CheckPredicate, 11, 17, 8, // Skip to: 13355 >+/* 11290 */ MCD_OPC_Decode, 135, 10, 176, 1, // Opcode: PRECRQ_RS_PH_W >+/* 11295 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 11308 >+/* 11299 */ MCD_OPC_CheckPredicate, 29, 4, 8, // Skip to: 13355 >+/* 11303 */ MCD_OPC_Decode, 135, 3, 174, 1, // Opcode: CMPGDU_EQ_QB >+/* 11308 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11321 >+/* 11312 */ MCD_OPC_CheckPredicate, 29, 247, 7, // Skip to: 13355 >+/* 11316 */ MCD_OPC_Decode, 137, 3, 174, 1, // Opcode: CMPGDU_LT_QB >+/* 11321 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 11334 >+/* 11325 */ MCD_OPC_CheckPredicate, 29, 234, 7, // Skip to: 13355 >+/* 11329 */ MCD_OPC_Decode, 136, 3, 174, 1, // Opcode: CMPGDU_LE_QB >+/* 11334 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 11347 >+/* 11338 */ MCD_OPC_CheckPredicate, 29, 221, 7, // Skip to: 13355 >+/* 11342 */ MCD_OPC_Decode, 137, 10, 177, 1, // Opcode: PRECR_SRA_PH_W >+/* 11347 */ MCD_OPC_FilterValue, 31, 212, 7, // Skip to: 13355 >+/* 11351 */ MCD_OPC_CheckPredicate, 29, 208, 7, // Skip to: 13355 >+/* 11355 */ MCD_OPC_Decode, 138, 10, 177, 1, // Opcode: PRECR_SRA_R_PH_W >+/* 11360 */ MCD_OPC_FilterValue, 18, 74, 1, // Skip to: 11694 >+/* 11364 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11367 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11385 >+/* 11371 */ MCD_OPC_CheckPredicate, 29, 188, 7, // Skip to: 13355 >+/* 11375 */ MCD_OPC_CheckField, 21, 5, 0, 182, 7, // Skip to: 13355 >+/* 11381 */ MCD_OPC_Decode, 21, 178, 1, // Opcode: ABSQ_S_QB >+/* 11385 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11398 >+/* 11389 */ MCD_OPC_CheckPredicate, 11, 170, 7, // Skip to: 13355 >+/* 11393 */ MCD_OPC_Decode, 185, 10, 179, 1, // Opcode: REPL_QB >+/* 11398 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 11417 >+/* 11402 */ MCD_OPC_CheckPredicate, 11, 157, 7, // Skip to: 13355 >+/* 11406 */ MCD_OPC_CheckField, 21, 5, 0, 151, 7, // Skip to: 13355 >+/* 11412 */ MCD_OPC_Decode, 183, 10, 180, 1, // Opcode: REPLV_QB >+/* 11417 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 11436 >+/* 11421 */ MCD_OPC_CheckPredicate, 11, 138, 7, // Skip to: 13355 >+/* 11425 */ MCD_OPC_CheckField, 21, 5, 0, 132, 7, // Skip to: 13355 >+/* 11431 */ MCD_OPC_Decode, 250, 9, 178, 1, // Opcode: PRECEQU_PH_QBL >+/* 11436 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 11455 >+/* 11440 */ MCD_OPC_CheckPredicate, 11, 119, 7, // Skip to: 13355 >+/* 11444 */ MCD_OPC_CheckField, 21, 5, 0, 113, 7, // Skip to: 13355 >+/* 11450 */ MCD_OPC_Decode, 252, 9, 178, 1, // Opcode: PRECEQU_PH_QBR >+/* 11455 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 11474 >+/* 11459 */ MCD_OPC_CheckPredicate, 11, 100, 7, // Skip to: 13355 >+/* 11463 */ MCD_OPC_CheckField, 21, 5, 0, 94, 7, // Skip to: 13355 >+/* 11469 */ MCD_OPC_Decode, 251, 9, 178, 1, // Opcode: PRECEQU_PH_QBLA >+/* 11474 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 11493 >+/* 11478 */ MCD_OPC_CheckPredicate, 11, 81, 7, // Skip to: 13355 >+/* 11482 */ MCD_OPC_CheckField, 21, 5, 0, 75, 7, // Skip to: 13355 >+/* 11488 */ MCD_OPC_Decode, 253, 9, 178, 1, // Opcode: PRECEQU_PH_QBRA >+/* 11493 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 11511 >+/* 11497 */ MCD_OPC_CheckPredicate, 11, 62, 7, // Skip to: 13355 >+/* 11501 */ MCD_OPC_CheckField, 21, 5, 0, 56, 7, // Skip to: 13355 >+/* 11507 */ MCD_OPC_Decode, 20, 178, 1, // Opcode: ABSQ_S_PH >+/* 11511 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11524 >+/* 11515 */ MCD_OPC_CheckPredicate, 11, 44, 7, // Skip to: 13355 >+/* 11519 */ MCD_OPC_Decode, 184, 10, 179, 1, // Opcode: REPL_PH >+/* 11524 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 11543 >+/* 11528 */ MCD_OPC_CheckPredicate, 11, 31, 7, // Skip to: 13355 >+/* 11532 */ MCD_OPC_CheckField, 21, 5, 0, 25, 7, // Skip to: 13355 >+/* 11538 */ MCD_OPC_Decode, 182, 10, 180, 1, // Opcode: REPLV_PH >+/* 11543 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 11562 >+/* 11547 */ MCD_OPC_CheckPredicate, 11, 12, 7, // Skip to: 13355 >+/* 11551 */ MCD_OPC_CheckField, 21, 5, 0, 6, 7, // Skip to: 13355 >+/* 11557 */ MCD_OPC_Decode, 254, 9, 181, 1, // Opcode: PRECEQ_W_PHL >+/* 11562 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 11581 >+/* 11566 */ MCD_OPC_CheckPredicate, 11, 249, 6, // Skip to: 13355 >+/* 11570 */ MCD_OPC_CheckField, 21, 5, 0, 243, 6, // Skip to: 13355 >+/* 11576 */ MCD_OPC_Decode, 255, 9, 181, 1, // Opcode: PRECEQ_W_PHR >+/* 11581 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 11599 >+/* 11585 */ MCD_OPC_CheckPredicate, 11, 230, 6, // Skip to: 13355 >+/* 11589 */ MCD_OPC_CheckField, 21, 5, 0, 224, 6, // Skip to: 13355 >+/* 11595 */ MCD_OPC_Decode, 22, 182, 1, // Opcode: ABSQ_S_W >+/* 11599 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 11618 >+/* 11603 */ MCD_OPC_CheckPredicate, 11, 212, 6, // Skip to: 13355 >+/* 11607 */ MCD_OPC_CheckField, 21, 5, 0, 206, 6, // Skip to: 13355 >+/* 11613 */ MCD_OPC_Decode, 233, 1, 182, 1, // Opcode: BITREV >+/* 11618 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 11637 >+/* 11622 */ MCD_OPC_CheckPredicate, 11, 193, 6, // Skip to: 13355 >+/* 11626 */ MCD_OPC_CheckField, 21, 5, 0, 187, 6, // Skip to: 13355 >+/* 11632 */ MCD_OPC_Decode, 128, 10, 178, 1, // Opcode: PRECEU_PH_QBL >+/* 11637 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 11656 >+/* 11641 */ MCD_OPC_CheckPredicate, 11, 174, 6, // Skip to: 13355 >+/* 11645 */ MCD_OPC_CheckField, 21, 5, 0, 168, 6, // Skip to: 13355 >+/* 11651 */ MCD_OPC_Decode, 130, 10, 178, 1, // Opcode: PRECEU_PH_QBR >+/* 11656 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 11675 >+/* 11660 */ MCD_OPC_CheckPredicate, 11, 155, 6, // Skip to: 13355 >+/* 11664 */ MCD_OPC_CheckField, 21, 5, 0, 149, 6, // Skip to: 13355 >+/* 11670 */ MCD_OPC_Decode, 129, 10, 178, 1, // Opcode: PRECEU_PH_QBLA >+/* 11675 */ MCD_OPC_FilterValue, 31, 140, 6, // Skip to: 13355 >+/* 11679 */ MCD_OPC_CheckPredicate, 11, 136, 6, // Skip to: 13355 >+/* 11683 */ MCD_OPC_CheckField, 21, 5, 0, 130, 6, // Skip to: 13355 >+/* 11689 */ MCD_OPC_Decode, 131, 10, 178, 1, // Opcode: PRECEU_PH_QBRA >+/* 11694 */ MCD_OPC_FilterValue, 19, 31, 1, // Skip to: 11985 >+/* 11698 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11701 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11714 >+/* 11705 */ MCD_OPC_CheckPredicate, 11, 110, 6, // Skip to: 13355 >+/* 11709 */ MCD_OPC_Decode, 136, 11, 183, 1, // Opcode: SHLL_QB >+/* 11714 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 11727 >+/* 11718 */ MCD_OPC_CheckPredicate, 11, 97, 6, // Skip to: 13355 >+/* 11722 */ MCD_OPC_Decode, 152, 11, 183, 1, // Opcode: SHRL_QB >+/* 11727 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 11740 >+/* 11731 */ MCD_OPC_CheckPredicate, 11, 84, 6, // Skip to: 13355 >+/* 11735 */ MCD_OPC_Decode, 132, 11, 184, 1, // Opcode: SHLLV_QB >+/* 11740 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 11753 >+/* 11744 */ MCD_OPC_CheckPredicate, 11, 71, 6, // Skip to: 13355 >+/* 11748 */ MCD_OPC_Decode, 150, 11, 184, 1, // Opcode: SHRLV_QB >+/* 11753 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 11766 >+/* 11757 */ MCD_OPC_CheckPredicate, 29, 58, 6, // Skip to: 13355 >+/* 11761 */ MCD_OPC_Decode, 145, 11, 183, 1, // Opcode: SHRA_QB >+/* 11766 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 11779 >+/* 11770 */ MCD_OPC_CheckPredicate, 29, 45, 6, // Skip to: 13355 >+/* 11774 */ MCD_OPC_Decode, 147, 11, 183, 1, // Opcode: SHRA_R_QB >+/* 11779 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 11792 >+/* 11783 */ MCD_OPC_CheckPredicate, 29, 32, 6, // Skip to: 13355 >+/* 11787 */ MCD_OPC_Decode, 140, 11, 184, 1, // Opcode: SHRAV_QB >+/* 11792 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 11805 >+/* 11796 */ MCD_OPC_CheckPredicate, 29, 19, 6, // Skip to: 13355 >+/* 11800 */ MCD_OPC_Decode, 142, 11, 184, 1, // Opcode: SHRAV_R_QB >+/* 11805 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 11818 >+/* 11809 */ MCD_OPC_CheckPredicate, 11, 6, 6, // Skip to: 13355 >+/* 11813 */ MCD_OPC_Decode, 135, 11, 183, 1, // Opcode: SHLL_PH >+/* 11818 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 11831 >+/* 11822 */ MCD_OPC_CheckPredicate, 11, 249, 5, // Skip to: 13355 >+/* 11826 */ MCD_OPC_Decode, 144, 11, 183, 1, // Opcode: SHRA_PH >+/* 11831 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 11844 >+/* 11835 */ MCD_OPC_CheckPredicate, 11, 236, 5, // Skip to: 13355 >+/* 11839 */ MCD_OPC_Decode, 131, 11, 184, 1, // Opcode: SHLLV_PH >+/* 11844 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 11857 >+/* 11848 */ MCD_OPC_CheckPredicate, 11, 223, 5, // Skip to: 13355 >+/* 11852 */ MCD_OPC_Decode, 139, 11, 184, 1, // Opcode: SHRAV_PH >+/* 11857 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 11870 >+/* 11861 */ MCD_OPC_CheckPredicate, 11, 210, 5, // Skip to: 13355 >+/* 11865 */ MCD_OPC_Decode, 137, 11, 183, 1, // Opcode: SHLL_S_PH >+/* 11870 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 11883 >+/* 11874 */ MCD_OPC_CheckPredicate, 11, 197, 5, // Skip to: 13355 >+/* 11878 */ MCD_OPC_Decode, 146, 11, 183, 1, // Opcode: SHRA_R_PH >+/* 11883 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 11896 >+/* 11887 */ MCD_OPC_CheckPredicate, 11, 184, 5, // Skip to: 13355 >+/* 11891 */ MCD_OPC_Decode, 133, 11, 184, 1, // Opcode: SHLLV_S_PH >+/* 11896 */ MCD_OPC_FilterValue, 15, 9, 0, // Skip to: 11909 >+/* 11900 */ MCD_OPC_CheckPredicate, 11, 171, 5, // Skip to: 13355 >+/* 11904 */ MCD_OPC_Decode, 141, 11, 184, 1, // Opcode: SHRAV_R_PH >+/* 11909 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 11922 >+/* 11913 */ MCD_OPC_CheckPredicate, 11, 158, 5, // Skip to: 13355 >+/* 11917 */ MCD_OPC_Decode, 138, 11, 185, 1, // Opcode: SHLL_S_W >+/* 11922 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 11935 >+/* 11926 */ MCD_OPC_CheckPredicate, 11, 145, 5, // Skip to: 13355 >+/* 11930 */ MCD_OPC_Decode, 148, 11, 185, 1, // Opcode: SHRA_R_W >+/* 11935 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 11947 >+/* 11939 */ MCD_OPC_CheckPredicate, 11, 132, 5, // Skip to: 13355 >+/* 11943 */ MCD_OPC_Decode, 134, 11, 18, // Opcode: SHLLV_S_W >+/* 11947 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 11959 >+/* 11951 */ MCD_OPC_CheckPredicate, 11, 120, 5, // Skip to: 13355 >+/* 11955 */ MCD_OPC_Decode, 143, 11, 18, // Opcode: SHRAV_R_W >+/* 11959 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 11972 >+/* 11963 */ MCD_OPC_CheckPredicate, 29, 108, 5, // Skip to: 13355 >+/* 11967 */ MCD_OPC_Decode, 151, 11, 183, 1, // Opcode: SHRL_PH >+/* 11972 */ MCD_OPC_FilterValue, 27, 99, 5, // Skip to: 13355 >+/* 11976 */ MCD_OPC_CheckPredicate, 29, 95, 5, // Skip to: 13355 >+/* 11980 */ MCD_OPC_Decode, 149, 11, 184, 1, // Opcode: SHRLV_PH >+/* 11985 */ MCD_OPC_FilterValue, 24, 199, 0, // Skip to: 12188 >+/* 11989 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 11992 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12004 >+/* 11996 */ MCD_OPC_CheckPredicate, 29, 75, 5, // Skip to: 13355 >+/* 12000 */ MCD_OPC_Decode, 45, 172, 1, // Opcode: ADDUH_QB >+/* 12004 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12017 >+/* 12008 */ MCD_OPC_CheckPredicate, 29, 63, 5, // Skip to: 13355 >+/* 12012 */ MCD_OPC_Decode, 148, 12, 172, 1, // Opcode: SUBUH_QB >+/* 12017 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12029 >+/* 12021 */ MCD_OPC_CheckPredicate, 29, 50, 5, // Skip to: 13355 >+/* 12025 */ MCD_OPC_Decode, 46, 172, 1, // Opcode: ADDUH_R_QB >+/* 12029 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 12042 >+/* 12033 */ MCD_OPC_CheckPredicate, 29, 38, 5, // Skip to: 13355 >+/* 12037 */ MCD_OPC_Decode, 149, 12, 172, 1, // Opcode: SUBUH_R_QB >+/* 12042 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12054 >+/* 12046 */ MCD_OPC_CheckPredicate, 29, 25, 5, // Skip to: 13355 >+/* 12050 */ MCD_OPC_Decode, 25, 172, 1, // Opcode: ADDQH_PH >+/* 12054 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 12067 >+/* 12058 */ MCD_OPC_CheckPredicate, 29, 13, 5, // Skip to: 13355 >+/* 12062 */ MCD_OPC_Decode, 253, 11, 172, 1, // Opcode: SUBQH_PH >+/* 12067 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12079 >+/* 12071 */ MCD_OPC_CheckPredicate, 29, 0, 5, // Skip to: 13355 >+/* 12075 */ MCD_OPC_Decode, 26, 172, 1, // Opcode: ADDQH_R_PH >+/* 12079 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 12092 >+/* 12083 */ MCD_OPC_CheckPredicate, 29, 244, 4, // Skip to: 13355 >+/* 12087 */ MCD_OPC_Decode, 254, 11, 172, 1, // Opcode: SUBQH_R_PH >+/* 12092 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 12105 >+/* 12096 */ MCD_OPC_CheckPredicate, 29, 231, 4, // Skip to: 13355 >+/* 12100 */ MCD_OPC_Decode, 179, 9, 172, 1, // Opcode: MUL_PH >+/* 12105 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 12118 >+/* 12109 */ MCD_OPC_CheckPredicate, 29, 218, 4, // Skip to: 13355 >+/* 12113 */ MCD_OPC_Decode, 183, 9, 172, 1, // Opcode: MUL_S_PH >+/* 12118 */ MCD_OPC_FilterValue, 16, 7, 0, // Skip to: 12129 >+/* 12122 */ MCD_OPC_CheckPredicate, 29, 205, 4, // Skip to: 13355 >+/* 12126 */ MCD_OPC_Decode, 28, 17, // Opcode: ADDQH_W >+/* 12129 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 12141 >+/* 12133 */ MCD_OPC_CheckPredicate, 29, 194, 4, // Skip to: 13355 >+/* 12137 */ MCD_OPC_Decode, 128, 12, 17, // Opcode: SUBQH_W >+/* 12141 */ MCD_OPC_FilterValue, 18, 7, 0, // Skip to: 12152 >+/* 12145 */ MCD_OPC_CheckPredicate, 29, 182, 4, // Skip to: 13355 >+/* 12149 */ MCD_OPC_Decode, 27, 17, // Opcode: ADDQH_R_W >+/* 12152 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 12164 >+/* 12156 */ MCD_OPC_CheckPredicate, 29, 171, 4, // Skip to: 13355 >+/* 12160 */ MCD_OPC_Decode, 255, 11, 17, // Opcode: SUBQH_R_W >+/* 12164 */ MCD_OPC_FilterValue, 22, 8, 0, // Skip to: 12176 >+/* 12168 */ MCD_OPC_CheckPredicate, 29, 159, 4, // Skip to: 13355 >+/* 12172 */ MCD_OPC_Decode, 162, 9, 17, // Opcode: MULQ_S_W >+/* 12176 */ MCD_OPC_FilterValue, 23, 151, 4, // Skip to: 13355 >+/* 12180 */ MCD_OPC_CheckPredicate, 29, 147, 4, // Skip to: 13355 >+/* 12184 */ MCD_OPC_Decode, 160, 9, 17, // Opcode: MULQ_RS_W >+/* 12188 */ MCD_OPC_FilterValue, 32, 60, 0, // Skip to: 12252 >+/* 12192 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12195 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12214 >+/* 12199 */ MCD_OPC_CheckPredicate, 4, 128, 4, // Skip to: 13355 >+/* 12203 */ MCD_OPC_CheckField, 21, 5, 0, 122, 4, // Skip to: 13355 >+/* 12209 */ MCD_OPC_Decode, 160, 13, 182, 1, // Opcode: WSBH >+/* 12214 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 12233 >+/* 12218 */ MCD_OPC_CheckPredicate, 4, 109, 4, // Skip to: 13355 >+/* 12222 */ MCD_OPC_CheckField, 21, 5, 0, 103, 4, // Skip to: 13355 >+/* 12228 */ MCD_OPC_Decode, 234, 10, 182, 1, // Opcode: SEB >+/* 12233 */ MCD_OPC_FilterValue, 24, 94, 4, // Skip to: 13355 >+/* 12237 */ MCD_OPC_CheckPredicate, 4, 90, 4, // Skip to: 13355 >+/* 12241 */ MCD_OPC_CheckField, 21, 5, 0, 84, 4, // Skip to: 13355 >+/* 12247 */ MCD_OPC_Decode, 237, 10, 182, 1, // Opcode: SEH >+/* 12252 */ MCD_OPC_FilterValue, 48, 143, 1, // Skip to: 12655 >+/* 12256 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12259 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12277 >+/* 12263 */ MCD_OPC_CheckPredicate, 29, 64, 4, // Skip to: 13355 >+/* 12267 */ MCD_OPC_CheckField, 13, 3, 0, 58, 4, // Skip to: 13355 >+/* 12273 */ MCD_OPC_Decode, 210, 4, 93, // Opcode: DPA_W_PH >+/* 12277 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12295 >+/* 12281 */ MCD_OPC_CheckPredicate, 29, 46, 4, // Skip to: 13355 >+/* 12285 */ MCD_OPC_CheckField, 13, 3, 0, 40, 4, // Skip to: 13355 >+/* 12291 */ MCD_OPC_Decode, 225, 4, 93, // Opcode: DPS_W_PH >+/* 12295 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12313 >+/* 12299 */ MCD_OPC_CheckPredicate, 29, 28, 4, // Skip to: 13355 >+/* 12303 */ MCD_OPC_CheckField, 13, 3, 0, 22, 4, // Skip to: 13355 >+/* 12309 */ MCD_OPC_Decode, 166, 9, 93, // Opcode: MULSA_W_PH >+/* 12313 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12331 >+/* 12317 */ MCD_OPC_CheckPredicate, 11, 10, 4, // Skip to: 13355 >+/* 12321 */ MCD_OPC_CheckField, 13, 3, 0, 4, 4, // Skip to: 13355 >+/* 12327 */ MCD_OPC_Decode, 207, 4, 93, // Opcode: DPAU_H_QBL >+/* 12331 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12349 >+/* 12335 */ MCD_OPC_CheckPredicate, 11, 248, 3, // Skip to: 13355 >+/* 12339 */ MCD_OPC_CheckField, 13, 3, 0, 242, 3, // Skip to: 13355 >+/* 12345 */ MCD_OPC_Decode, 206, 4, 93, // Opcode: DPAQ_S_W_PH >+/* 12349 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12367 >+/* 12353 */ MCD_OPC_CheckPredicate, 11, 230, 3, // Skip to: 13355 >+/* 12357 */ MCD_OPC_CheckField, 13, 3, 0, 224, 3, // Skip to: 13355 >+/* 12363 */ MCD_OPC_Decode, 215, 4, 93, // Opcode: DPSQ_S_W_PH >+/* 12367 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 12385 >+/* 12371 */ MCD_OPC_CheckPredicate, 11, 212, 3, // Skip to: 13355 >+/* 12375 */ MCD_OPC_CheckField, 13, 3, 0, 206, 3, // Skip to: 13355 >+/* 12381 */ MCD_OPC_Decode, 165, 9, 93, // Opcode: MULSAQ_S_W_PH >+/* 12385 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 12403 >+/* 12389 */ MCD_OPC_CheckPredicate, 11, 194, 3, // Skip to: 13355 >+/* 12393 */ MCD_OPC_CheckField, 13, 3, 0, 188, 3, // Skip to: 13355 >+/* 12399 */ MCD_OPC_Decode, 208, 4, 93, // Opcode: DPAU_H_QBR >+/* 12403 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12421 >+/* 12407 */ MCD_OPC_CheckPredicate, 29, 176, 3, // Skip to: 13355 >+/* 12411 */ MCD_OPC_CheckField, 13, 3, 0, 170, 3, // Skip to: 13355 >+/* 12417 */ MCD_OPC_Decode, 209, 4, 93, // Opcode: DPAX_W_PH >+/* 12421 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 12439 >+/* 12425 */ MCD_OPC_CheckPredicate, 29, 158, 3, // Skip to: 13355 >+/* 12429 */ MCD_OPC_CheckField, 13, 3, 0, 152, 3, // Skip to: 13355 >+/* 12435 */ MCD_OPC_Decode, 224, 4, 93, // Opcode: DPSX_W_PH >+/* 12439 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12457 >+/* 12443 */ MCD_OPC_CheckPredicate, 11, 140, 3, // Skip to: 13355 >+/* 12447 */ MCD_OPC_CheckField, 13, 3, 0, 134, 3, // Skip to: 13355 >+/* 12453 */ MCD_OPC_Decode, 222, 4, 93, // Opcode: DPSU_H_QBL >+/* 12457 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12475 >+/* 12461 */ MCD_OPC_CheckPredicate, 11, 122, 3, // Skip to: 13355 >+/* 12465 */ MCD_OPC_CheckField, 13, 3, 0, 116, 3, // Skip to: 13355 >+/* 12471 */ MCD_OPC_Decode, 205, 4, 93, // Opcode: DPAQ_SA_L_W >+/* 12475 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12493 >+/* 12479 */ MCD_OPC_CheckPredicate, 11, 104, 3, // Skip to: 13355 >+/* 12483 */ MCD_OPC_CheckField, 13, 3, 0, 98, 3, // Skip to: 13355 >+/* 12489 */ MCD_OPC_Decode, 214, 4, 93, // Opcode: DPSQ_SA_L_W >+/* 12493 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 12511 >+/* 12497 */ MCD_OPC_CheckPredicate, 11, 86, 3, // Skip to: 13355 >+/* 12501 */ MCD_OPC_CheckField, 13, 3, 0, 80, 3, // Skip to: 13355 >+/* 12507 */ MCD_OPC_Decode, 223, 4, 93, // Opcode: DPSU_H_QBR >+/* 12511 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 12529 >+/* 12515 */ MCD_OPC_CheckPredicate, 11, 68, 3, // Skip to: 13355 >+/* 12519 */ MCD_OPC_CheckField, 13, 3, 0, 62, 3, // Skip to: 13355 >+/* 12525 */ MCD_OPC_Decode, 241, 7, 93, // Opcode: MAQ_SA_W_PHL >+/* 12529 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 12547 >+/* 12533 */ MCD_OPC_CheckPredicate, 11, 50, 3, // Skip to: 13355 >+/* 12537 */ MCD_OPC_CheckField, 13, 3, 0, 44, 3, // Skip to: 13355 >+/* 12543 */ MCD_OPC_Decode, 242, 7, 93, // Opcode: MAQ_SA_W_PHR >+/* 12547 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 12565 >+/* 12551 */ MCD_OPC_CheckPredicate, 11, 32, 3, // Skip to: 13355 >+/* 12555 */ MCD_OPC_CheckField, 13, 3, 0, 26, 3, // Skip to: 13355 >+/* 12561 */ MCD_OPC_Decode, 243, 7, 93, // Opcode: MAQ_S_W_PHL >+/* 12565 */ MCD_OPC_FilterValue, 22, 14, 0, // Skip to: 12583 >+/* 12569 */ MCD_OPC_CheckPredicate, 11, 14, 3, // Skip to: 13355 >+/* 12573 */ MCD_OPC_CheckField, 13, 3, 0, 8, 3, // Skip to: 13355 >+/* 12579 */ MCD_OPC_Decode, 244, 7, 93, // Opcode: MAQ_S_W_PHR >+/* 12583 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 12601 >+/* 12587 */ MCD_OPC_CheckPredicate, 29, 252, 2, // Skip to: 13355 >+/* 12591 */ MCD_OPC_CheckField, 13, 3, 0, 246, 2, // Skip to: 13355 >+/* 12597 */ MCD_OPC_Decode, 204, 4, 93, // Opcode: DPAQX_S_W_PH >+/* 12601 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 12619 >+/* 12605 */ MCD_OPC_CheckPredicate, 29, 234, 2, // Skip to: 13355 >+/* 12609 */ MCD_OPC_CheckField, 13, 3, 0, 228, 2, // Skip to: 13355 >+/* 12615 */ MCD_OPC_Decode, 213, 4, 93, // Opcode: DPSQX_S_W_PH >+/* 12619 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 12637 >+/* 12623 */ MCD_OPC_CheckPredicate, 29, 216, 2, // Skip to: 13355 >+/* 12627 */ MCD_OPC_CheckField, 13, 3, 0, 210, 2, // Skip to: 13355 >+/* 12633 */ MCD_OPC_Decode, 203, 4, 93, // Opcode: DPAQX_SA_W_PH >+/* 12637 */ MCD_OPC_FilterValue, 27, 202, 2, // Skip to: 13355 >+/* 12641 */ MCD_OPC_CheckPredicate, 29, 198, 2, // Skip to: 13355 >+/* 12645 */ MCD_OPC_CheckField, 13, 3, 0, 192, 2, // Skip to: 13355 >+/* 12651 */ MCD_OPC_Decode, 212, 4, 93, // Opcode: DPSQX_SA_W_PH >+/* 12655 */ MCD_OPC_FilterValue, 49, 41, 0, // Skip to: 12700 >+/* 12659 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12662 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12674 >+/* 12666 */ MCD_OPC_CheckPredicate, 29, 173, 2, // Skip to: 13355 >+/* 12670 */ MCD_OPC_Decode, 86, 186, 1, // Opcode: APPEND >+/* 12674 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 12687 >+/* 12678 */ MCD_OPC_CheckPredicate, 29, 161, 2, // Skip to: 13355 >+/* 12682 */ MCD_OPC_Decode, 141, 10, 186, 1, // Opcode: PREPEND >+/* 12687 */ MCD_OPC_FilterValue, 16, 152, 2, // Skip to: 13355 >+/* 12691 */ MCD_OPC_CheckPredicate, 29, 148, 2, // Skip to: 13355 >+/* 12695 */ MCD_OPC_Decode, 158, 1, 186, 1, // Opcode: BALIGN >+/* 12700 */ MCD_OPC_FilterValue, 56, 58, 1, // Skip to: 13018 >+/* 12704 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 12707 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 12726 >+/* 12711 */ MCD_OPC_CheckPredicate, 11, 128, 2, // Skip to: 13355 >+/* 12715 */ MCD_OPC_CheckField, 13, 3, 0, 122, 2, // Skip to: 13355 >+/* 12721 */ MCD_OPC_Decode, 136, 5, 187, 1, // Opcode: EXTR_W >+/* 12726 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 12745 >+/* 12730 */ MCD_OPC_CheckPredicate, 11, 109, 2, // Skip to: 13355 >+/* 12734 */ MCD_OPC_CheckField, 13, 3, 0, 103, 2, // Skip to: 13355 >+/* 12740 */ MCD_OPC_Decode, 132, 5, 188, 1, // Opcode: EXTRV_W >+/* 12745 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 12764 >+/* 12749 */ MCD_OPC_CheckPredicate, 11, 90, 2, // Skip to: 13355 >+/* 12753 */ MCD_OPC_CheckField, 13, 3, 0, 84, 2, // Skip to: 13355 >+/* 12759 */ MCD_OPC_Decode, 253, 4, 187, 1, // Opcode: EXTP >+/* 12764 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 12783 >+/* 12768 */ MCD_OPC_CheckPredicate, 11, 71, 2, // Skip to: 13355 >+/* 12772 */ MCD_OPC_CheckField, 13, 3, 0, 65, 2, // Skip to: 13355 >+/* 12778 */ MCD_OPC_Decode, 128, 5, 188, 1, // Opcode: EXTPV >+/* 12783 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 12802 >+/* 12787 */ MCD_OPC_CheckPredicate, 11, 52, 2, // Skip to: 13355 >+/* 12791 */ MCD_OPC_CheckField, 13, 3, 0, 46, 2, // Skip to: 13355 >+/* 12797 */ MCD_OPC_Decode, 134, 5, 187, 1, // Opcode: EXTR_R_W >+/* 12802 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 12821 >+/* 12806 */ MCD_OPC_CheckPredicate, 11, 33, 2, // Skip to: 13355 >+/* 12810 */ MCD_OPC_CheckField, 13, 3, 0, 27, 2, // Skip to: 13355 >+/* 12816 */ MCD_OPC_Decode, 130, 5, 188, 1, // Opcode: EXTRV_R_W >+/* 12821 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 12840 >+/* 12825 */ MCD_OPC_CheckPredicate, 11, 14, 2, // Skip to: 13355 >+/* 12829 */ MCD_OPC_CheckField, 13, 3, 0, 8, 2, // Skip to: 13355 >+/* 12835 */ MCD_OPC_Decode, 133, 5, 187, 1, // Opcode: EXTR_RS_W >+/* 12840 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 12859 >+/* 12844 */ MCD_OPC_CheckPredicate, 11, 251, 1, // Skip to: 13355 >+/* 12848 */ MCD_OPC_CheckField, 13, 3, 0, 245, 1, // Skip to: 13355 >+/* 12854 */ MCD_OPC_Decode, 129, 5, 188, 1, // Opcode: EXTRV_RS_W >+/* 12859 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 12878 >+/* 12863 */ MCD_OPC_CheckPredicate, 11, 232, 1, // Skip to: 13355 >+/* 12867 */ MCD_OPC_CheckField, 13, 3, 0, 226, 1, // Skip to: 13355 >+/* 12873 */ MCD_OPC_Decode, 254, 4, 187, 1, // Opcode: EXTPDP >+/* 12878 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 12897 >+/* 12882 */ MCD_OPC_CheckPredicate, 11, 213, 1, // Skip to: 13355 >+/* 12886 */ MCD_OPC_CheckField, 13, 3, 0, 207, 1, // Skip to: 13355 >+/* 12892 */ MCD_OPC_Decode, 255, 4, 188, 1, // Opcode: EXTPDPV >+/* 12897 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 12916 >+/* 12901 */ MCD_OPC_CheckPredicate, 11, 194, 1, // Skip to: 13355 >+/* 12905 */ MCD_OPC_CheckField, 13, 3, 0, 188, 1, // Skip to: 13355 >+/* 12911 */ MCD_OPC_Decode, 135, 5, 187, 1, // Opcode: EXTR_S_H >+/* 12916 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 12935 >+/* 12920 */ MCD_OPC_CheckPredicate, 11, 175, 1, // Skip to: 13355 >+/* 12924 */ MCD_OPC_CheckField, 13, 3, 0, 169, 1, // Skip to: 13355 >+/* 12930 */ MCD_OPC_Decode, 131, 5, 188, 1, // Opcode: EXTRV_S_H >+/* 12935 */ MCD_OPC_FilterValue, 18, 9, 0, // Skip to: 12948 >+/* 12939 */ MCD_OPC_CheckPredicate, 11, 156, 1, // Skip to: 13355 >+/* 12943 */ MCD_OPC_Decode, 179, 10, 189, 1, // Opcode: RDDSP >+/* 12948 */ MCD_OPC_FilterValue, 19, 9, 0, // Skip to: 12961 >+/* 12952 */ MCD_OPC_CheckPredicate, 11, 143, 1, // Skip to: 13355 >+/* 12956 */ MCD_OPC_Decode, 159, 13, 190, 1, // Opcode: WRDSP >+/* 12961 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 12980 >+/* 12965 */ MCD_OPC_CheckPredicate, 11, 130, 1, // Skip to: 13355 >+/* 12969 */ MCD_OPC_CheckField, 13, 7, 0, 124, 1, // Skip to: 13355 >+/* 12975 */ MCD_OPC_Decode, 129, 11, 191, 1, // Opcode: SHILO >+/* 12980 */ MCD_OPC_FilterValue, 27, 15, 0, // Skip to: 12999 >+/* 12984 */ MCD_OPC_CheckPredicate, 11, 111, 1, // Skip to: 13355 >+/* 12988 */ MCD_OPC_CheckField, 13, 8, 0, 105, 1, // Skip to: 13355 >+/* 12994 */ MCD_OPC_Decode, 130, 11, 192, 1, // Opcode: SHILOV >+/* 12999 */ MCD_OPC_FilterValue, 31, 96, 1, // Skip to: 13355 >+/* 13003 */ MCD_OPC_CheckPredicate, 11, 92, 1, // Skip to: 13355 >+/* 13007 */ MCD_OPC_CheckField, 13, 8, 0, 86, 1, // Skip to: 13355 >+/* 13013 */ MCD_OPC_Decode, 141, 9, 192, 1, // Opcode: MTHLIP >+/* 13018 */ MCD_OPC_FilterValue, 59, 77, 1, // Skip to: 13355 >+/* 13022 */ MCD_OPC_CheckPredicate, 1, 73, 1, // Skip to: 13355 >+/* 13026 */ MCD_OPC_CheckField, 21, 5, 0, 67, 1, // Skip to: 13355 >+/* 13032 */ MCD_OPC_CheckField, 6, 5, 0, 61, 1, // Skip to: 13355 >+/* 13038 */ MCD_OPC_Decode, 180, 10, 193, 1, // Opcode: RDHWR >+/* 13043 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 13056 >+/* 13047 */ MCD_OPC_CheckPredicate, 1, 48, 1, // Skip to: 13355 >+/* 13051 */ MCD_OPC_Decode, 254, 6, 194, 1, // Opcode: LB >+/* 13056 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 13069 >+/* 13060 */ MCD_OPC_CheckPredicate, 1, 35, 1, // Skip to: 13355 >+/* 13064 */ MCD_OPC_Decode, 156, 7, 194, 1, // Opcode: LH >+/* 13069 */ MCD_OPC_FilterValue, 34, 9, 0, // Skip to: 13082 >+/* 13073 */ MCD_OPC_CheckPredicate, 10, 22, 1, // Skip to: 13355 >+/* 13077 */ MCD_OPC_Decode, 190, 7, 194, 1, // Opcode: LWL >+/* 13082 */ MCD_OPC_FilterValue, 35, 9, 0, // Skip to: 13095 >+/* 13086 */ MCD_OPC_CheckPredicate, 1, 9, 1, // Skip to: 13355 >+/* 13090 */ MCD_OPC_Decode, 183, 7, 194, 1, // Opcode: LW >+/* 13095 */ MCD_OPC_FilterValue, 36, 9, 0, // Skip to: 13108 >+/* 13099 */ MCD_OPC_CheckPredicate, 1, 252, 0, // Skip to: 13355 >+/* 13103 */ MCD_OPC_Decode, 130, 7, 194, 1, // Opcode: LBu >+/* 13108 */ MCD_OPC_FilterValue, 37, 9, 0, // Skip to: 13121 >+/* 13112 */ MCD_OPC_CheckPredicate, 1, 239, 0, // Skip to: 13355 >+/* 13116 */ MCD_OPC_Decode, 160, 7, 194, 1, // Opcode: LHu >+/* 13121 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 13134 >+/* 13125 */ MCD_OPC_CheckPredicate, 10, 226, 0, // Skip to: 13355 >+/* 13129 */ MCD_OPC_Decode, 194, 7, 194, 1, // Opcode: LWR >+/* 13134 */ MCD_OPC_FilterValue, 40, 9, 0, // Skip to: 13147 >+/* 13138 */ MCD_OPC_CheckPredicate, 1, 213, 0, // Skip to: 13355 >+/* 13142 */ MCD_OPC_Decode, 211, 10, 194, 1, // Opcode: SB >+/* 13147 */ MCD_OPC_FilterValue, 41, 9, 0, // Skip to: 13160 >+/* 13151 */ MCD_OPC_CheckPredicate, 1, 200, 0, // Skip to: 13355 >+/* 13155 */ MCD_OPC_Decode, 252, 10, 194, 1, // Opcode: SH >+/* 13160 */ MCD_OPC_FilterValue, 42, 9, 0, // Skip to: 13173 >+/* 13164 */ MCD_OPC_CheckPredicate, 10, 187, 0, // Skip to: 13355 >+/* 13168 */ MCD_OPC_Decode, 175, 12, 194, 1, // Opcode: SWL >+/* 13173 */ MCD_OPC_FilterValue, 43, 9, 0, // Skip to: 13186 >+/* 13177 */ MCD_OPC_CheckPredicate, 1, 174, 0, // Skip to: 13355 >+/* 13181 */ MCD_OPC_Decode, 168, 12, 194, 1, // Opcode: SW >+/* 13186 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 13199 >+/* 13190 */ MCD_OPC_CheckPredicate, 10, 161, 0, // Skip to: 13355 >+/* 13194 */ MCD_OPC_Decode, 178, 12, 194, 1, // Opcode: SWR >+/* 13199 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 13212 >+/* 13203 */ MCD_OPC_CheckPredicate, 30, 148, 0, // Skip to: 13355 >+/* 13207 */ MCD_OPC_Decode, 201, 2, 195, 1, // Opcode: CACHE >+/* 13212 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 13225 >+/* 13216 */ MCD_OPC_CheckPredicate, 31, 135, 0, // Skip to: 13355 >+/* 13220 */ MCD_OPC_Decode, 163, 7, 194, 1, // Opcode: LL >+/* 13225 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 13238 >+/* 13229 */ MCD_OPC_CheckPredicate, 1, 122, 0, // Skip to: 13355 >+/* 13233 */ MCD_OPC_Decode, 185, 7, 196, 1, // Opcode: LWC1 >+/* 13238 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 13251 >+/* 13242 */ MCD_OPC_CheckPredicate, 12, 109, 0, // Skip to: 13355 >+/* 13246 */ MCD_OPC_Decode, 187, 7, 197, 1, // Opcode: LWC2 >+/* 13251 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 13264 >+/* 13255 */ MCD_OPC_CheckPredicate, 30, 96, 0, // Skip to: 13355 >+/* 13259 */ MCD_OPC_Decode, 139, 10, 195, 1, // Opcode: PREF >+/* 13264 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 13277 >+/* 13268 */ MCD_OPC_CheckPredicate, 32, 83, 0, // Skip to: 13355 >+/* 13272 */ MCD_OPC_Decode, 134, 7, 196, 1, // Opcode: LDC1 >+/* 13277 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 13290 >+/* 13281 */ MCD_OPC_CheckPredicate, 14, 70, 0, // Skip to: 13355 >+/* 13285 */ MCD_OPC_Decode, 137, 7, 197, 1, // Opcode: LDC2 >+/* 13290 */ MCD_OPC_FilterValue, 56, 9, 0, // Skip to: 13303 >+/* 13294 */ MCD_OPC_CheckPredicate, 31, 57, 0, // Skip to: 13355 >+/* 13298 */ MCD_OPC_Decode, 214, 10, 194, 1, // Opcode: SC >+/* 13303 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 13316 >+/* 13307 */ MCD_OPC_CheckPredicate, 1, 44, 0, // Skip to: 13355 >+/* 13311 */ MCD_OPC_Decode, 170, 12, 196, 1, // Opcode: SWC1 >+/* 13316 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 13329 >+/* 13320 */ MCD_OPC_CheckPredicate, 12, 31, 0, // Skip to: 13355 >+/* 13324 */ MCD_OPC_Decode, 172, 12, 197, 1, // Opcode: SWC2 >+/* 13329 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 13342 >+/* 13333 */ MCD_OPC_CheckPredicate, 32, 18, 0, // Skip to: 13355 >+/* 13337 */ MCD_OPC_Decode, 222, 10, 196, 1, // Opcode: SDC1 >+/* 13342 */ MCD_OPC_FilterValue, 62, 9, 0, // Skip to: 13355 >+/* 13346 */ MCD_OPC_CheckPredicate, 14, 5, 0, // Skip to: 13355 >+/* 13350 */ MCD_OPC_Decode, 225, 10, 197, 1, // Opcode: SDC2 >+/* 13355 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableMips32r6_64r632[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 29 >+/* 14 */ MCD_OPC_CheckPredicate, 33, 38, 7, // Skip to: 1848 >+/* 18 */ MCD_OPC_CheckField, 8, 3, 0, 32, 7, // Skip to: 1848 >+/* 24 */ MCD_OPC_Decode, 176, 7, 198, 1, // Opcode: LSA_R6 >+/* 29 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 47 >+/* 33 */ MCD_OPC_CheckPredicate, 33, 19, 7, // Skip to: 1848 >+/* 37 */ MCD_OPC_CheckField, 6, 15, 16, 13, 7, // Skip to: 1848 >+/* 43 */ MCD_OPC_Decode, 245, 6, 39, // Opcode: JR_HB_R6 >+/* 47 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 59 >+/* 51 */ MCD_OPC_CheckPredicate, 33, 1, 7, // Skip to: 1848 >+/* 55 */ MCD_OPC_Decode, 221, 10, 42, // Opcode: SDBBP_R6 >+/* 59 */ MCD_OPC_FilterValue, 16, 20, 0, // Skip to: 83 >+/* 63 */ MCD_OPC_CheckPredicate, 33, 245, 6, // Skip to: 1848 >+/* 67 */ MCD_OPC_CheckField, 16, 5, 0, 239, 6, // Skip to: 1848 >+/* 73 */ MCD_OPC_CheckField, 6, 5, 1, 233, 6, // Skip to: 1848 >+/* 79 */ MCD_OPC_Decode, 134, 3, 40, // Opcode: CLZ_R6 >+/* 83 */ MCD_OPC_FilterValue, 17, 20, 0, // Skip to: 107 >+/* 87 */ MCD_OPC_CheckPredicate, 33, 221, 6, // Skip to: 1848 >+/* 91 */ MCD_OPC_CheckField, 16, 5, 0, 215, 6, // Skip to: 1848 >+/* 97 */ MCD_OPC_CheckField, 6, 5, 1, 209, 6, // Skip to: 1848 >+/* 103 */ MCD_OPC_Decode, 243, 2, 40, // Opcode: CLO_R6 >+/* 107 */ MCD_OPC_FilterValue, 18, 21, 0, // Skip to: 132 >+/* 111 */ MCD_OPC_CheckPredicate, 34, 197, 6, // Skip to: 1848 >+/* 115 */ MCD_OPC_CheckField, 16, 5, 0, 191, 6, // Skip to: 1848 >+/* 121 */ MCD_OPC_CheckField, 6, 5, 1, 185, 6, // Skip to: 1848 >+/* 127 */ MCD_OPC_Decode, 151, 4, 199, 1, // Opcode: DCLZ_R6 >+/* 132 */ MCD_OPC_FilterValue, 19, 21, 0, // Skip to: 157 >+/* 136 */ MCD_OPC_CheckPredicate, 34, 172, 6, // Skip to: 1848 >+/* 140 */ MCD_OPC_CheckField, 16, 5, 0, 166, 6, // Skip to: 1848 >+/* 146 */ MCD_OPC_CheckField, 6, 5, 1, 160, 6, // Skip to: 1848 >+/* 152 */ MCD_OPC_Decode, 149, 4, 199, 1, // Opcode: DCLO_R6 >+/* 157 */ MCD_OPC_FilterValue, 21, 15, 0, // Skip to: 176 >+/* 161 */ MCD_OPC_CheckPredicate, 34, 147, 6, // Skip to: 1848 >+/* 165 */ MCD_OPC_CheckField, 8, 3, 0, 141, 6, // Skip to: 1848 >+/* 171 */ MCD_OPC_Decode, 175, 4, 200, 1, // Opcode: DLSA_R6 >+/* 176 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 207 >+/* 180 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 183 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 195 >+/* 187 */ MCD_OPC_CheckPredicate, 33, 121, 6, // Skip to: 1848 >+/* 191 */ MCD_OPC_Decode, 182, 9, 17, // Opcode: MUL_R6 >+/* 195 */ MCD_OPC_FilterValue, 3, 113, 6, // Skip to: 1848 >+/* 199 */ MCD_OPC_CheckPredicate, 33, 109, 6, // Skip to: 1848 >+/* 203 */ MCD_OPC_Decode, 152, 9, 17, // Opcode: MUH >+/* 207 */ MCD_OPC_FilterValue, 25, 27, 0, // Skip to: 238 >+/* 211 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 214 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 226 >+/* 218 */ MCD_OPC_CheckPredicate, 33, 90, 6, // Skip to: 1848 >+/* 222 */ MCD_OPC_Decode, 173, 9, 17, // Opcode: MULU >+/* 226 */ MCD_OPC_FilterValue, 3, 82, 6, // Skip to: 1848 >+/* 230 */ MCD_OPC_CheckPredicate, 33, 78, 6, // Skip to: 1848 >+/* 234 */ MCD_OPC_Decode, 153, 9, 17, // Opcode: MUHU >+/* 238 */ MCD_OPC_FilterValue, 26, 27, 0, // Skip to: 269 >+/* 242 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 245 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 257 >+/* 249 */ MCD_OPC_CheckPredicate, 33, 59, 6, // Skip to: 1848 >+/* 253 */ MCD_OPC_Decode, 163, 4, 17, // Opcode: DIV >+/* 257 */ MCD_OPC_FilterValue, 3, 51, 6, // Skip to: 1848 >+/* 261 */ MCD_OPC_CheckPredicate, 33, 47, 6, // Skip to: 1848 >+/* 265 */ MCD_OPC_Decode, 184, 8, 17, // Opcode: MOD >+/* 269 */ MCD_OPC_FilterValue, 27, 27, 0, // Skip to: 300 >+/* 273 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 276 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 288 >+/* 280 */ MCD_OPC_CheckPredicate, 33, 28, 6, // Skip to: 1848 >+/* 284 */ MCD_OPC_Decode, 164, 4, 17, // Opcode: DIVU >+/* 288 */ MCD_OPC_FilterValue, 3, 20, 6, // Skip to: 1848 >+/* 292 */ MCD_OPC_CheckPredicate, 33, 16, 6, // Skip to: 1848 >+/* 296 */ MCD_OPC_Decode, 186, 8, 17, // Opcode: MODU >+/* 300 */ MCD_OPC_FilterValue, 28, 29, 0, // Skip to: 333 >+/* 304 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 307 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 320 >+/* 311 */ MCD_OPC_CheckPredicate, 34, 253, 5, // Skip to: 1848 >+/* 315 */ MCD_OPC_Decode, 190, 4, 201, 1, // Opcode: DMUL_R6 >+/* 320 */ MCD_OPC_FilterValue, 3, 244, 5, // Skip to: 1848 >+/* 324 */ MCD_OPC_CheckPredicate, 34, 240, 5, // Skip to: 1848 >+/* 328 */ MCD_OPC_Decode, 184, 4, 201, 1, // Opcode: DMUH >+/* 333 */ MCD_OPC_FilterValue, 29, 29, 0, // Skip to: 366 >+/* 337 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 353 >+/* 344 */ MCD_OPC_CheckPredicate, 34, 220, 5, // Skip to: 1848 >+/* 348 */ MCD_OPC_Decode, 189, 4, 201, 1, // Opcode: DMULU >+/* 353 */ MCD_OPC_FilterValue, 3, 211, 5, // Skip to: 1848 >+/* 357 */ MCD_OPC_CheckPredicate, 34, 207, 5, // Skip to: 1848 >+/* 361 */ MCD_OPC_Decode, 185, 4, 201, 1, // Opcode: DMUHU >+/* 366 */ MCD_OPC_FilterValue, 30, 29, 0, // Skip to: 399 >+/* 370 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 386 >+/* 377 */ MCD_OPC_CheckPredicate, 34, 187, 5, // Skip to: 1848 >+/* 381 */ MCD_OPC_Decode, 152, 4, 201, 1, // Opcode: DDIV >+/* 386 */ MCD_OPC_FilterValue, 3, 178, 5, // Skip to: 1848 >+/* 390 */ MCD_OPC_CheckPredicate, 34, 174, 5, // Skip to: 1848 >+/* 394 */ MCD_OPC_Decode, 179, 4, 201, 1, // Opcode: DMOD >+/* 399 */ MCD_OPC_FilterValue, 31, 29, 0, // Skip to: 432 >+/* 403 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 406 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 419 >+/* 410 */ MCD_OPC_CheckPredicate, 34, 154, 5, // Skip to: 1848 >+/* 414 */ MCD_OPC_Decode, 153, 4, 201, 1, // Opcode: DDIVU >+/* 419 */ MCD_OPC_FilterValue, 3, 145, 5, // Skip to: 1848 >+/* 423 */ MCD_OPC_CheckPredicate, 34, 141, 5, // Skip to: 1848 >+/* 427 */ MCD_OPC_Decode, 180, 4, 201, 1, // Opcode: DMODU >+/* 432 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 450 >+/* 436 */ MCD_OPC_CheckPredicate, 35, 128, 5, // Skip to: 1848 >+/* 440 */ MCD_OPC_CheckField, 6, 5, 0, 122, 5, // Skip to: 1848 >+/* 446 */ MCD_OPC_Decode, 240, 10, 17, // Opcode: SELEQZ >+/* 450 */ MCD_OPC_FilterValue, 55, 114, 5, // Skip to: 1848 >+/* 454 */ MCD_OPC_CheckPredicate, 35, 110, 5, // Skip to: 1848 >+/* 458 */ MCD_OPC_CheckField, 6, 5, 0, 104, 5, // Skip to: 1848 >+/* 464 */ MCD_OPC_Decode, 244, 10, 17, // Opcode: SELNEZ >+/* 468 */ MCD_OPC_FilterValue, 1, 47, 0, // Skip to: 519 >+/* 472 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... >+/* 475 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 488 >+/* 479 */ MCD_OPC_CheckPredicate, 34, 85, 5, // Skip to: 1848 >+/* 483 */ MCD_OPC_Decode, 143, 4, 202, 1, // Opcode: DAHI >+/* 488 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 506 >+/* 492 */ MCD_OPC_CheckPredicate, 33, 72, 5, // Skip to: 1848 >+/* 496 */ MCD_OPC_CheckField, 21, 5, 0, 66, 5, // Skip to: 1848 >+/* 502 */ MCD_OPC_Decode, 156, 1, 53, // Opcode: BAL >+/* 506 */ MCD_OPC_FilterValue, 30, 58, 5, // Skip to: 1848 >+/* 510 */ MCD_OPC_CheckPredicate, 34, 54, 5, // Skip to: 1848 >+/* 514 */ MCD_OPC_Decode, 145, 4, 202, 1, // Opcode: DATI >+/* 519 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 532 >+/* 523 */ MCD_OPC_CheckPredicate, 33, 41, 5, // Skip to: 1848 >+/* 527 */ MCD_OPC_Decode, 204, 1, 203, 1, // Opcode: BGEZALC >+/* 532 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 545 >+/* 536 */ MCD_OPC_CheckPredicate, 33, 28, 5, // Skip to: 1848 >+/* 540 */ MCD_OPC_Decode, 246, 1, 204, 1, // Opcode: BLTZALC >+/* 545 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 558 >+/* 549 */ MCD_OPC_CheckPredicate, 33, 15, 5, // Skip to: 1848 >+/* 553 */ MCD_OPC_Decode, 193, 1, 205, 1, // Opcode: BEQC >+/* 558 */ MCD_OPC_FilterValue, 15, 7, 0, // Skip to: 569 >+/* 562 */ MCD_OPC_CheckPredicate, 33, 2, 5, // Skip to: 1848 >+/* 566 */ MCD_OPC_Decode, 127, 27, // Opcode: AUI >+/* 569 */ MCD_OPC_FilterValue, 17, 5, 3, // Skip to: 1346 >+/* 573 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 576 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 589 >+/* 580 */ MCD_OPC_CheckPredicate, 33, 240, 4, // Skip to: 1848 >+/* 584 */ MCD_OPC_Decode, 165, 1, 206, 1, // Opcode: BC1EQZ >+/* 589 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 602 >+/* 593 */ MCD_OPC_CheckPredicate, 33, 227, 4, // Skip to: 1848 >+/* 597 */ MCD_OPC_Decode, 169, 1, 206, 1, // Opcode: BC1NEZ >+/* 602 */ MCD_OPC_FilterValue, 16, 150, 0, // Skip to: 756 >+/* 606 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 609 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 622 >+/* 613 */ MCD_OPC_CheckPredicate, 33, 207, 4, // Skip to: 1848 >+/* 617 */ MCD_OPC_Decode, 249, 10, 207, 1, // Opcode: SEL_S >+/* 622 */ MCD_OPC_FilterValue, 20, 8, 0, // Skip to: 634 >+/* 626 */ MCD_OPC_CheckPredicate, 33, 194, 4, // Skip to: 1848 >+/* 630 */ MCD_OPC_Decode, 243, 10, 70, // Opcode: SELEQZ_S >+/* 634 */ MCD_OPC_FilterValue, 23, 8, 0, // Skip to: 646 >+/* 638 */ MCD_OPC_CheckPredicate, 33, 182, 4, // Skip to: 1848 >+/* 642 */ MCD_OPC_Decode, 247, 10, 70, // Opcode: SELNEZ_S >+/* 646 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 659 >+/* 650 */ MCD_OPC_CheckPredicate, 33, 170, 4, // Skip to: 1848 >+/* 654 */ MCD_OPC_Decode, 222, 7, 208, 1, // Opcode: MADDF_S >+/* 659 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 672 >+/* 663 */ MCD_OPC_CheckPredicate, 33, 157, 4, // Skip to: 1848 >+/* 667 */ MCD_OPC_Decode, 239, 8, 208, 1, // Opcode: MSUBF_S >+/* 672 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 690 >+/* 676 */ MCD_OPC_CheckPredicate, 33, 144, 4, // Skip to: 1848 >+/* 680 */ MCD_OPC_CheckField, 16, 5, 0, 138, 4, // Skip to: 1848 >+/* 686 */ MCD_OPC_Decode, 187, 10, 71, // Opcode: RINT_S >+/* 690 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 708 >+/* 694 */ MCD_OPC_CheckPredicate, 33, 126, 4, // Skip to: 1848 >+/* 698 */ MCD_OPC_CheckField, 16, 5, 0, 120, 4, // Skip to: 1848 >+/* 704 */ MCD_OPC_Decode, 224, 2, 71, // Opcode: CLASS_S >+/* 708 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 720 >+/* 712 */ MCD_OPC_CheckPredicate, 33, 108, 4, // Skip to: 1848 >+/* 716 */ MCD_OPC_Decode, 173, 8, 70, // Opcode: MIN_S >+/* 720 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 732 >+/* 724 */ MCD_OPC_CheckPredicate, 33, 96, 4, // Skip to: 1848 >+/* 728 */ MCD_OPC_Decode, 132, 8, 70, // Opcode: MAX_S >+/* 732 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 744 >+/* 736 */ MCD_OPC_CheckPredicate, 33, 84, 4, // Skip to: 1848 >+/* 740 */ MCD_OPC_Decode, 159, 8, 70, // Opcode: MINA_S >+/* 744 */ MCD_OPC_FilterValue, 31, 76, 4, // Skip to: 1848 >+/* 748 */ MCD_OPC_CheckPredicate, 33, 72, 4, // Skip to: 1848 >+/* 752 */ MCD_OPC_Decode, 246, 7, 70, // Opcode: MAXA_S >+/* 756 */ MCD_OPC_FilterValue, 17, 156, 0, // Skip to: 916 >+/* 760 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 763 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 776 >+/* 767 */ MCD_OPC_CheckPredicate, 33, 53, 4, // Skip to: 1848 >+/* 771 */ MCD_OPC_Decode, 248, 10, 209, 1, // Opcode: SEL_D >+/* 776 */ MCD_OPC_FilterValue, 20, 9, 0, // Skip to: 789 >+/* 780 */ MCD_OPC_CheckPredicate, 33, 40, 4, // Skip to: 1848 >+/* 784 */ MCD_OPC_Decode, 242, 10, 210, 1, // Opcode: SELEQZ_D >+/* 789 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 802 >+/* 793 */ MCD_OPC_CheckPredicate, 33, 27, 4, // Skip to: 1848 >+/* 797 */ MCD_OPC_Decode, 246, 10, 210, 1, // Opcode: SELNEZ_D >+/* 802 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 815 >+/* 806 */ MCD_OPC_CheckPredicate, 33, 14, 4, // Skip to: 1848 >+/* 810 */ MCD_OPC_Decode, 221, 7, 211, 1, // Opcode: MADDF_D >+/* 815 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 828 >+/* 819 */ MCD_OPC_CheckPredicate, 33, 1, 4, // Skip to: 1848 >+/* 823 */ MCD_OPC_Decode, 238, 8, 211, 1, // Opcode: MSUBF_D >+/* 828 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 846 >+/* 832 */ MCD_OPC_CheckPredicate, 33, 244, 3, // Skip to: 1848 >+/* 836 */ MCD_OPC_CheckField, 16, 5, 0, 238, 3, // Skip to: 1848 >+/* 842 */ MCD_OPC_Decode, 186, 10, 82, // Opcode: RINT_D >+/* 846 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 864 >+/* 850 */ MCD_OPC_CheckPredicate, 33, 226, 3, // Skip to: 1848 >+/* 854 */ MCD_OPC_CheckField, 16, 5, 0, 220, 3, // Skip to: 1848 >+/* 860 */ MCD_OPC_Decode, 223, 2, 82, // Opcode: CLASS_D >+/* 864 */ MCD_OPC_FilterValue, 28, 9, 0, // Skip to: 877 >+/* 868 */ MCD_OPC_CheckPredicate, 33, 208, 3, // Skip to: 1848 >+/* 872 */ MCD_OPC_Decode, 172, 8, 210, 1, // Opcode: MIN_D >+/* 877 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 890 >+/* 881 */ MCD_OPC_CheckPredicate, 33, 195, 3, // Skip to: 1848 >+/* 885 */ MCD_OPC_Decode, 131, 8, 210, 1, // Opcode: MAX_D >+/* 890 */ MCD_OPC_FilterValue, 30, 9, 0, // Skip to: 903 >+/* 894 */ MCD_OPC_CheckPredicate, 33, 182, 3, // Skip to: 1848 >+/* 898 */ MCD_OPC_Decode, 158, 8, 210, 1, // Opcode: MINA_D >+/* 903 */ MCD_OPC_FilterValue, 31, 173, 3, // Skip to: 1848 >+/* 907 */ MCD_OPC_CheckPredicate, 33, 169, 3, // Skip to: 1848 >+/* 911 */ MCD_OPC_Decode, 245, 7, 210, 1, // Opcode: MAXA_D >+/* 916 */ MCD_OPC_FilterValue, 20, 211, 0, // Skip to: 1131 >+/* 920 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 923 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 936 >+/* 927 */ MCD_OPC_CheckPredicate, 33, 149, 3, // Skip to: 1848 >+/* 931 */ MCD_OPC_Decode, 148, 3, 212, 1, // Opcode: CMP_F_S >+/* 936 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 949 >+/* 940 */ MCD_OPC_CheckPredicate, 33, 136, 3, // Skip to: 1848 >+/* 944 */ MCD_OPC_Decode, 178, 3, 212, 1, // Opcode: CMP_UN_S >+/* 949 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 962 >+/* 953 */ MCD_OPC_CheckPredicate, 33, 123, 3, // Skip to: 1848 >+/* 957 */ MCD_OPC_Decode, 146, 3, 212, 1, // Opcode: CMP_EQ_S >+/* 962 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 975 >+/* 966 */ MCD_OPC_CheckPredicate, 33, 110, 3, // Skip to: 1848 >+/* 970 */ MCD_OPC_Decode, 172, 3, 212, 1, // Opcode: CMP_UEQ_S >+/* 975 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 988 >+/* 979 */ MCD_OPC_CheckPredicate, 33, 97, 3, // Skip to: 1848 >+/* 983 */ MCD_OPC_Decode, 154, 3, 212, 1, // Opcode: CMP_LT_S >+/* 988 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1001 >+/* 992 */ MCD_OPC_CheckPredicate, 33, 84, 3, // Skip to: 1848 >+/* 996 */ MCD_OPC_Decode, 176, 3, 212, 1, // Opcode: CMP_ULT_S >+/* 1001 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1014 >+/* 1005 */ MCD_OPC_CheckPredicate, 33, 71, 3, // Skip to: 1848 >+/* 1009 */ MCD_OPC_Decode, 151, 3, 212, 1, // Opcode: CMP_LE_S >+/* 1014 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1027 >+/* 1018 */ MCD_OPC_CheckPredicate, 33, 58, 3, // Skip to: 1848 >+/* 1022 */ MCD_OPC_Decode, 174, 3, 212, 1, // Opcode: CMP_ULE_S >+/* 1027 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1040 >+/* 1031 */ MCD_OPC_CheckPredicate, 33, 45, 3, // Skip to: 1848 >+/* 1035 */ MCD_OPC_Decode, 156, 3, 212, 1, // Opcode: CMP_SAF_S >+/* 1040 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1053 >+/* 1044 */ MCD_OPC_CheckPredicate, 33, 32, 3, // Skip to: 1848 >+/* 1048 */ MCD_OPC_Decode, 170, 3, 212, 1, // Opcode: CMP_SUN_S >+/* 1053 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1066 >+/* 1057 */ MCD_OPC_CheckPredicate, 33, 19, 3, // Skip to: 1848 >+/* 1061 */ MCD_OPC_Decode, 158, 3, 212, 1, // Opcode: CMP_SEQ_S >+/* 1066 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1079 >+/* 1070 */ MCD_OPC_CheckPredicate, 33, 6, 3, // Skip to: 1848 >+/* 1074 */ MCD_OPC_Decode, 164, 3, 212, 1, // Opcode: CMP_SUEQ_S >+/* 1079 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1092 >+/* 1083 */ MCD_OPC_CheckPredicate, 33, 249, 2, // Skip to: 1848 >+/* 1087 */ MCD_OPC_Decode, 162, 3, 212, 1, // Opcode: CMP_SLT_S >+/* 1092 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1105 >+/* 1096 */ MCD_OPC_CheckPredicate, 33, 236, 2, // Skip to: 1848 >+/* 1100 */ MCD_OPC_Decode, 168, 3, 212, 1, // Opcode: CMP_SULT_S >+/* 1105 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1118 >+/* 1109 */ MCD_OPC_CheckPredicate, 33, 223, 2, // Skip to: 1848 >+/* 1113 */ MCD_OPC_Decode, 160, 3, 212, 1, // Opcode: CMP_SLE_S >+/* 1118 */ MCD_OPC_FilterValue, 15, 214, 2, // Skip to: 1848 >+/* 1122 */ MCD_OPC_CheckPredicate, 33, 210, 2, // Skip to: 1848 >+/* 1126 */ MCD_OPC_Decode, 166, 3, 212, 1, // Opcode: CMP_SULE_S >+/* 1131 */ MCD_OPC_FilterValue, 21, 201, 2, // Skip to: 1848 >+/* 1135 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1138 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1151 >+/* 1142 */ MCD_OPC_CheckPredicate, 33, 190, 2, // Skip to: 1848 >+/* 1146 */ MCD_OPC_Decode, 147, 3, 213, 1, // Opcode: CMP_F_D >+/* 1151 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1164 >+/* 1155 */ MCD_OPC_CheckPredicate, 33, 177, 2, // Skip to: 1848 >+/* 1159 */ MCD_OPC_Decode, 177, 3, 213, 1, // Opcode: CMP_UN_D >+/* 1164 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1177 >+/* 1168 */ MCD_OPC_CheckPredicate, 33, 164, 2, // Skip to: 1848 >+/* 1172 */ MCD_OPC_Decode, 144, 3, 213, 1, // Opcode: CMP_EQ_D >+/* 1177 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 1190 >+/* 1181 */ MCD_OPC_CheckPredicate, 33, 151, 2, // Skip to: 1848 >+/* 1185 */ MCD_OPC_Decode, 171, 3, 213, 1, // Opcode: CMP_UEQ_D >+/* 1190 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 1203 >+/* 1194 */ MCD_OPC_CheckPredicate, 33, 138, 2, // Skip to: 1848 >+/* 1198 */ MCD_OPC_Decode, 152, 3, 213, 1, // Opcode: CMP_LT_D >+/* 1203 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 1216 >+/* 1207 */ MCD_OPC_CheckPredicate, 33, 125, 2, // Skip to: 1848 >+/* 1211 */ MCD_OPC_Decode, 175, 3, 213, 1, // Opcode: CMP_ULT_D >+/* 1216 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 1229 >+/* 1220 */ MCD_OPC_CheckPredicate, 33, 112, 2, // Skip to: 1848 >+/* 1224 */ MCD_OPC_Decode, 149, 3, 213, 1, // Opcode: CMP_LE_D >+/* 1229 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 1242 >+/* 1233 */ MCD_OPC_CheckPredicate, 33, 99, 2, // Skip to: 1848 >+/* 1237 */ MCD_OPC_Decode, 173, 3, 213, 1, // Opcode: CMP_ULE_D >+/* 1242 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 1255 >+/* 1246 */ MCD_OPC_CheckPredicate, 33, 86, 2, // Skip to: 1848 >+/* 1250 */ MCD_OPC_Decode, 155, 3, 213, 1, // Opcode: CMP_SAF_D >+/* 1255 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1268 >+/* 1259 */ MCD_OPC_CheckPredicate, 33, 73, 2, // Skip to: 1848 >+/* 1263 */ MCD_OPC_Decode, 169, 3, 213, 1, // Opcode: CMP_SUN_D >+/* 1268 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1281 >+/* 1272 */ MCD_OPC_CheckPredicate, 33, 60, 2, // Skip to: 1848 >+/* 1276 */ MCD_OPC_Decode, 157, 3, 213, 1, // Opcode: CMP_SEQ_D >+/* 1281 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1294 >+/* 1285 */ MCD_OPC_CheckPredicate, 33, 47, 2, // Skip to: 1848 >+/* 1289 */ MCD_OPC_Decode, 163, 3, 213, 1, // Opcode: CMP_SUEQ_D >+/* 1294 */ MCD_OPC_FilterValue, 12, 9, 0, // Skip to: 1307 >+/* 1298 */ MCD_OPC_CheckPredicate, 33, 34, 2, // Skip to: 1848 >+/* 1302 */ MCD_OPC_Decode, 161, 3, 213, 1, // Opcode: CMP_SLT_D >+/* 1307 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1320 >+/* 1311 */ MCD_OPC_CheckPredicate, 33, 21, 2, // Skip to: 1848 >+/* 1315 */ MCD_OPC_Decode, 167, 3, 213, 1, // Opcode: CMP_SULT_D >+/* 1320 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1333 >+/* 1324 */ MCD_OPC_CheckPredicate, 33, 8, 2, // Skip to: 1848 >+/* 1328 */ MCD_OPC_Decode, 159, 3, 213, 1, // Opcode: CMP_SLE_D >+/* 1333 */ MCD_OPC_FilterValue, 15, 255, 1, // Skip to: 1848 >+/* 1337 */ MCD_OPC_CheckPredicate, 33, 251, 1, // Skip to: 1848 >+/* 1341 */ MCD_OPC_Decode, 165, 3, 213, 1, // Opcode: CMP_SULE_D >+/* 1346 */ MCD_OPC_FilterValue, 18, 81, 0, // Skip to: 1431 >+/* 1350 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1353 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 1366 >+/* 1357 */ MCD_OPC_CheckPredicate, 33, 231, 1, // Skip to: 1848 >+/* 1361 */ MCD_OPC_Decode, 173, 1, 214, 1, // Opcode: BC2EQZ >+/* 1366 */ MCD_OPC_FilterValue, 10, 9, 0, // Skip to: 1379 >+/* 1370 */ MCD_OPC_CheckPredicate, 33, 218, 1, // Skip to: 1848 >+/* 1374 */ MCD_OPC_Decode, 188, 7, 215, 1, // Opcode: LWC2_R6 >+/* 1379 */ MCD_OPC_FilterValue, 11, 9, 0, // Skip to: 1392 >+/* 1383 */ MCD_OPC_CheckPredicate, 33, 205, 1, // Skip to: 1848 >+/* 1387 */ MCD_OPC_Decode, 173, 12, 215, 1, // Opcode: SWC2_R6 >+/* 1392 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 1405 >+/* 1396 */ MCD_OPC_CheckPredicate, 33, 192, 1, // Skip to: 1848 >+/* 1400 */ MCD_OPC_Decode, 176, 1, 214, 1, // Opcode: BC2NEZ >+/* 1405 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 1418 >+/* 1409 */ MCD_OPC_CheckPredicate, 33, 179, 1, // Skip to: 1848 >+/* 1413 */ MCD_OPC_Decode, 138, 7, 215, 1, // Opcode: LDC2_R6 >+/* 1418 */ MCD_OPC_FilterValue, 15, 170, 1, // Skip to: 1848 >+/* 1422 */ MCD_OPC_CheckPredicate, 33, 166, 1, // Skip to: 1848 >+/* 1426 */ MCD_OPC_Decode, 226, 10, 215, 1, // Opcode: SDC2_R6 >+/* 1431 */ MCD_OPC_FilterValue, 22, 9, 0, // Skip to: 1444 >+/* 1435 */ MCD_OPC_CheckPredicate, 33, 153, 1, // Skip to: 1848 >+/* 1439 */ MCD_OPC_Decode, 208, 1, 216, 1, // Opcode: BGEZC >+/* 1444 */ MCD_OPC_FilterValue, 23, 9, 0, // Skip to: 1457 >+/* 1448 */ MCD_OPC_CheckPredicate, 33, 140, 1, // Skip to: 1848 >+/* 1452 */ MCD_OPC_Decode, 250, 1, 217, 1, // Opcode: BLTZC >+/* 1457 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1470 >+/* 1461 */ MCD_OPC_CheckPredicate, 33, 127, 1, // Skip to: 1848 >+/* 1465 */ MCD_OPC_Decode, 131, 2, 218, 1, // Opcode: BNEC >+/* 1470 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 1483 >+/* 1474 */ MCD_OPC_CheckPredicate, 34, 114, 1, // Skip to: 1848 >+/* 1478 */ MCD_OPC_Decode, 146, 4, 219, 1, // Opcode: DAUI >+/* 1483 */ MCD_OPC_FilterValue, 31, 182, 0, // Skip to: 1669 >+/* 1487 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1490 */ MCD_OPC_FilterValue, 32, 40, 0, // Skip to: 1534 >+/* 1494 */ MCD_OPC_ExtractField, 8, 3, // Inst{10-8} ... >+/* 1497 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1522 >+/* 1501 */ MCD_OPC_CheckPredicate, 33, 87, 1, // Skip to: 1848 >+/* 1505 */ MCD_OPC_CheckField, 21, 5, 0, 81, 1, // Skip to: 1848 >+/* 1511 */ MCD_OPC_CheckField, 6, 2, 0, 75, 1, // Skip to: 1848 >+/* 1517 */ MCD_OPC_Decode, 234, 1, 182, 1, // Opcode: BITSWAP >+/* 1522 */ MCD_OPC_FilterValue, 2, 66, 1, // Skip to: 1848 >+/* 1526 */ MCD_OPC_CheckPredicate, 33, 62, 1, // Skip to: 1848 >+/* 1530 */ MCD_OPC_Decode, 73, 198, 1, // Opcode: ALIGN >+/* 1534 */ MCD_OPC_FilterValue, 36, 41, 0, // Skip to: 1579 >+/* 1538 */ MCD_OPC_ExtractField, 9, 2, // Inst{10-9} ... >+/* 1541 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 1566 >+/* 1545 */ MCD_OPC_CheckPredicate, 34, 43, 1, // Skip to: 1848 >+/* 1549 */ MCD_OPC_CheckField, 21, 5, 0, 37, 1, // Skip to: 1848 >+/* 1555 */ MCD_OPC_CheckField, 6, 3, 0, 31, 1, // Skip to: 1848 >+/* 1561 */ MCD_OPC_Decode, 147, 4, 220, 1, // Opcode: DBITSWAP >+/* 1566 */ MCD_OPC_FilterValue, 1, 22, 1, // Skip to: 1848 >+/* 1570 */ MCD_OPC_CheckPredicate, 34, 18, 1, // Skip to: 1848 >+/* 1574 */ MCD_OPC_Decode, 144, 4, 221, 1, // Opcode: DALIGN >+/* 1579 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1598 >+/* 1583 */ MCD_OPC_CheckPredicate, 33, 5, 1, // Skip to: 1848 >+/* 1587 */ MCD_OPC_CheckField, 6, 1, 0, 255, 0, // Skip to: 1848 >+/* 1593 */ MCD_OPC_Decode, 202, 2, 222, 1, // Opcode: CACHE_R6 >+/* 1598 */ MCD_OPC_FilterValue, 38, 9, 0, // Skip to: 1611 >+/* 1602 */ MCD_OPC_CheckPredicate, 33, 242, 0, // Skip to: 1848 >+/* 1606 */ MCD_OPC_Decode, 218, 10, 223, 1, // Opcode: SC_R6 >+/* 1611 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 1624 >+/* 1615 */ MCD_OPC_CheckPredicate, 33, 229, 0, // Skip to: 1848 >+/* 1619 */ MCD_OPC_Decode, 216, 10, 223, 1, // Opcode: SCD_R6 >+/* 1624 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 1643 >+/* 1628 */ MCD_OPC_CheckPredicate, 33, 216, 0, // Skip to: 1848 >+/* 1632 */ MCD_OPC_CheckField, 6, 1, 0, 210, 0, // Skip to: 1848 >+/* 1638 */ MCD_OPC_Decode, 140, 10, 222, 1, // Opcode: PREF_R6 >+/* 1643 */ MCD_OPC_FilterValue, 54, 9, 0, // Skip to: 1656 >+/* 1647 */ MCD_OPC_CheckPredicate, 33, 197, 0, // Skip to: 1848 >+/* 1651 */ MCD_OPC_Decode, 167, 7, 223, 1, // Opcode: LL_R6 >+/* 1656 */ MCD_OPC_FilterValue, 55, 188, 0, // Skip to: 1848 >+/* 1660 */ MCD_OPC_CheckPredicate, 33, 184, 0, // Skip to: 1848 >+/* 1664 */ MCD_OPC_Decode, 165, 7, 223, 1, // Opcode: LLD_R6 >+/* 1669 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1682 >+/* 1673 */ MCD_OPC_CheckPredicate, 33, 171, 0, // Skip to: 1848 >+/* 1677 */ MCD_OPC_Decode, 160, 1, 224, 1, // Opcode: BC >+/* 1682 */ MCD_OPC_FilterValue, 54, 24, 0, // Skip to: 1710 >+/* 1686 */ MCD_OPC_CheckPredicate, 33, 11, 0, // Skip to: 1701 >+/* 1690 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, // Skip to: 1701 >+/* 1696 */ MCD_OPC_Decode, 240, 6, 225, 1, // Opcode: JIC >+/* 1701 */ MCD_OPC_CheckPredicate, 33, 143, 0, // Skip to: 1848 >+/* 1705 */ MCD_OPC_Decode, 196, 1, 226, 1, // Opcode: BEQZC >+/* 1710 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 1723 >+/* 1714 */ MCD_OPC_CheckPredicate, 33, 130, 0, // Skip to: 1848 >+/* 1718 */ MCD_OPC_Decode, 157, 1, 224, 1, // Opcode: BALC >+/* 1723 */ MCD_OPC_FilterValue, 59, 93, 0, // Skip to: 1820 >+/* 1727 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... >+/* 1730 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1742 >+/* 1734 */ MCD_OPC_CheckPredicate, 33, 110, 0, // Skip to: 1848 >+/* 1738 */ MCD_OPC_Decode, 24, 227, 1, // Opcode: ADDIUPC >+/* 1742 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 1755 >+/* 1746 */ MCD_OPC_CheckPredicate, 33, 98, 0, // Skip to: 1848 >+/* 1750 */ MCD_OPC_Decode, 193, 7, 227, 1, // Opcode: LWPC >+/* 1755 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1768 >+/* 1759 */ MCD_OPC_CheckPredicate, 33, 85, 0, // Skip to: 1848 >+/* 1763 */ MCD_OPC_Decode, 197, 7, 227, 1, // Opcode: LWUPC >+/* 1768 */ MCD_OPC_FilterValue, 3, 76, 0, // Skip to: 1848 >+/* 1772 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... >+/* 1775 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1788 >+/* 1779 */ MCD_OPC_CheckPredicate, 34, 65, 0, // Skip to: 1848 >+/* 1783 */ MCD_OPC_Decode, 145, 7, 228, 1, // Opcode: LDPC >+/* 1788 */ MCD_OPC_FilterValue, 1, 56, 0, // Skip to: 1848 >+/* 1792 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 1795 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1808 >+/* 1799 */ MCD_OPC_CheckPredicate, 33, 45, 0, // Skip to: 1848 >+/* 1803 */ MCD_OPC_Decode, 128, 1, 229, 1, // Opcode: AUIPC >+/* 1808 */ MCD_OPC_FilterValue, 3, 36, 0, // Skip to: 1848 >+/* 1812 */ MCD_OPC_CheckPredicate, 33, 32, 0, // Skip to: 1848 >+/* 1816 */ MCD_OPC_Decode, 74, 229, 1, // Opcode: ALUIPC >+/* 1820 */ MCD_OPC_FilterValue, 62, 24, 0, // Skip to: 1848 >+/* 1824 */ MCD_OPC_CheckPredicate, 33, 11, 0, // Skip to: 1839 >+/* 1828 */ MCD_OPC_CheckField, 21, 5, 0, 5, 0, // Skip to: 1839 >+/* 1834 */ MCD_OPC_Decode, 239, 6, 225, 1, // Opcode: JIALC >+/* 1839 */ MCD_OPC_CheckPredicate, 33, 5, 0, // Skip to: 1848 >+/* 1843 */ MCD_OPC_Decode, 142, 2, 226, 1, // Opcode: BNEZC >+/* 1848 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = { >+/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ... >+/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22 >+/* 7 */ MCD_OPC_CheckPredicate, 36, 30, 0, // Skip to: 41 >+/* 11 */ MCD_OPC_CheckField, 26, 6, 0, 24, 0, // Skip to: 41 >+/* 17 */ MCD_OPC_Decode, 241, 10, 201, 1, // Opcode: SELEQZ64 >+/* 22 */ MCD_OPC_FilterValue, 55, 15, 0, // Skip to: 41 >+/* 26 */ MCD_OPC_CheckPredicate, 36, 11, 0, // Skip to: 41 >+/* 30 */ MCD_OPC_CheckField, 26, 6, 0, 5, 0, // Skip to: 41 >+/* 36 */ MCD_OPC_Decode, 245, 10, 201, 1, // Opcode: SELNEZ64 >+/* 41 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static const uint8_t DecoderTableMips6432[] = { >+/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... >+/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375 >+/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 10 */ MCD_OPC_FilterValue, 20, 15, 0, // Skip to: 29 >+/* 14 */ MCD_OPC_CheckPredicate, 17, 194, 8, // Skip to: 2260 >+/* 18 */ MCD_OPC_CheckField, 6, 5, 0, 188, 8, // Skip to: 2260 >+/* 24 */ MCD_OPC_Decode, 235, 4, 230, 1, // Opcode: DSLLV >+/* 29 */ MCD_OPC_FilterValue, 22, 29, 0, // Skip to: 62 >+/* 33 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 36 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 49 >+/* 40 */ MCD_OPC_CheckPredicate, 17, 168, 8, // Skip to: 2260 >+/* 44 */ MCD_OPC_Decode, 241, 4, 230, 1, // Opcode: DSRLV >+/* 49 */ MCD_OPC_FilterValue, 1, 159, 8, // Skip to: 2260 >+/* 53 */ MCD_OPC_CheckPredicate, 37, 155, 8, // Skip to: 2260 >+/* 57 */ MCD_OPC_Decode, 228, 4, 230, 1, // Opcode: DROTRV >+/* 62 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 81 >+/* 66 */ MCD_OPC_CheckPredicate, 17, 142, 8, // Skip to: 2260 >+/* 70 */ MCD_OPC_CheckField, 6, 5, 0, 136, 8, // Skip to: 2260 >+/* 76 */ MCD_OPC_Decode, 238, 4, 230, 1, // Opcode: DSRAV >+/* 81 */ MCD_OPC_FilterValue, 28, 15, 0, // Skip to: 100 >+/* 85 */ MCD_OPC_CheckPredicate, 38, 123, 8, // Skip to: 2260 >+/* 89 */ MCD_OPC_CheckField, 6, 10, 0, 117, 8, // Skip to: 2260 >+/* 95 */ MCD_OPC_Decode, 187, 4, 231, 1, // Opcode: DMULT >+/* 100 */ MCD_OPC_FilterValue, 29, 15, 0, // Skip to: 119 >+/* 104 */ MCD_OPC_CheckPredicate, 38, 104, 8, // Skip to: 2260 >+/* 108 */ MCD_OPC_CheckField, 6, 10, 0, 98, 8, // Skip to: 2260 >+/* 114 */ MCD_OPC_Decode, 188, 4, 231, 1, // Opcode: DMULTu >+/* 119 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 138 >+/* 123 */ MCD_OPC_CheckPredicate, 38, 85, 8, // Skip to: 2260 >+/* 127 */ MCD_OPC_CheckField, 6, 10, 0, 79, 8, // Skip to: 2260 >+/* 133 */ MCD_OPC_Decode, 230, 4, 231, 1, // Opcode: DSDIV >+/* 138 */ MCD_OPC_FilterValue, 31, 15, 0, // Skip to: 157 >+/* 142 */ MCD_OPC_CheckPredicate, 38, 66, 8, // Skip to: 2260 >+/* 146 */ MCD_OPC_CheckField, 6, 10, 0, 60, 8, // Skip to: 2260 >+/* 152 */ MCD_OPC_Decode, 244, 4, 231, 1, // Opcode: DUDIV >+/* 157 */ MCD_OPC_FilterValue, 44, 15, 0, // Skip to: 176 >+/* 161 */ MCD_OPC_CheckPredicate, 17, 47, 8, // Skip to: 2260 >+/* 165 */ MCD_OPC_CheckField, 6, 5, 0, 41, 8, // Skip to: 2260 >+/* 171 */ MCD_OPC_Decode, 139, 4, 201, 1, // Opcode: DADD >+/* 176 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 195 >+/* 180 */ MCD_OPC_CheckPredicate, 17, 28, 8, // Skip to: 2260 >+/* 184 */ MCD_OPC_CheckField, 6, 5, 0, 22, 8, // Skip to: 2260 >+/* 190 */ MCD_OPC_Decode, 142, 4, 201, 1, // Opcode: DADDu >+/* 195 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 214 >+/* 199 */ MCD_OPC_CheckPredicate, 17, 9, 8, // Skip to: 2260 >+/* 203 */ MCD_OPC_CheckField, 6, 5, 0, 3, 8, // Skip to: 2260 >+/* 209 */ MCD_OPC_Decode, 242, 4, 201, 1, // Opcode: DSUB >+/* 214 */ MCD_OPC_FilterValue, 47, 15, 0, // Skip to: 233 >+/* 218 */ MCD_OPC_CheckPredicate, 17, 246, 7, // Skip to: 2260 >+/* 222 */ MCD_OPC_CheckField, 6, 5, 0, 240, 7, // Skip to: 2260 >+/* 228 */ MCD_OPC_Decode, 243, 4, 201, 1, // Opcode: DSUBu >+/* 233 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 252 >+/* 237 */ MCD_OPC_CheckPredicate, 17, 227, 7, // Skip to: 2260 >+/* 241 */ MCD_OPC_CheckField, 21, 5, 0, 221, 7, // Skip to: 2260 >+/* 247 */ MCD_OPC_Decode, 232, 4, 232, 1, // Opcode: DSLL >+/* 252 */ MCD_OPC_FilterValue, 58, 29, 0, // Skip to: 285 >+/* 256 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 259 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 272 >+/* 263 */ MCD_OPC_CheckPredicate, 17, 201, 7, // Skip to: 2260 >+/* 267 */ MCD_OPC_Decode, 239, 4, 232, 1, // Opcode: DSRL >+/* 272 */ MCD_OPC_FilterValue, 1, 192, 7, // Skip to: 2260 >+/* 276 */ MCD_OPC_CheckPredicate, 37, 188, 7, // Skip to: 2260 >+/* 280 */ MCD_OPC_Decode, 226, 4, 232, 1, // Opcode: DROTR >+/* 285 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 304 >+/* 289 */ MCD_OPC_CheckPredicate, 17, 175, 7, // Skip to: 2260 >+/* 293 */ MCD_OPC_CheckField, 21, 5, 0, 169, 7, // Skip to: 2260 >+/* 299 */ MCD_OPC_Decode, 236, 4, 232, 1, // Opcode: DSRA >+/* 304 */ MCD_OPC_FilterValue, 60, 15, 0, // Skip to: 323 >+/* 308 */ MCD_OPC_CheckPredicate, 17, 156, 7, // Skip to: 2260 >+/* 312 */ MCD_OPC_CheckField, 21, 5, 0, 150, 7, // Skip to: 2260 >+/* 318 */ MCD_OPC_Decode, 233, 4, 232, 1, // Opcode: DSLL32 >+/* 323 */ MCD_OPC_FilterValue, 62, 29, 0, // Skip to: 356 >+/* 327 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 330 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 343 >+/* 334 */ MCD_OPC_CheckPredicate, 17, 130, 7, // Skip to: 2260 >+/* 338 */ MCD_OPC_Decode, 240, 4, 232, 1, // Opcode: DSRL32 >+/* 343 */ MCD_OPC_FilterValue, 1, 121, 7, // Skip to: 2260 >+/* 347 */ MCD_OPC_CheckPredicate, 37, 117, 7, // Skip to: 2260 >+/* 351 */ MCD_OPC_Decode, 227, 4, 232, 1, // Opcode: DROTR32 >+/* 356 */ MCD_OPC_FilterValue, 63, 108, 7, // Skip to: 2260 >+/* 360 */ MCD_OPC_CheckPredicate, 17, 104, 7, // Skip to: 2260 >+/* 364 */ MCD_OPC_CheckField, 21, 5, 0, 98, 7, // Skip to: 2260 >+/* 370 */ MCD_OPC_Decode, 237, 4, 232, 1, // Opcode: DSRA32 >+/* 375 */ MCD_OPC_FilterValue, 16, 41, 0, // Skip to: 420 >+/* 379 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 382 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 401 >+/* 386 */ MCD_OPC_CheckPredicate, 39, 78, 7, // Skip to: 2260 >+/* 390 */ MCD_OPC_CheckField, 3, 8, 0, 72, 7, // Skip to: 2260 >+/* 396 */ MCD_OPC_Decode, 176, 4, 233, 1, // Opcode: DMFC0 >+/* 401 */ MCD_OPC_FilterValue, 5, 63, 7, // Skip to: 2260 >+/* 405 */ MCD_OPC_CheckPredicate, 39, 59, 7, // Skip to: 2260 >+/* 409 */ MCD_OPC_CheckField, 3, 8, 0, 53, 7, // Skip to: 2260 >+/* 415 */ MCD_OPC_Decode, 181, 4, 233, 1, // Opcode: DMTC0 >+/* 420 */ MCD_OPC_FilterValue, 17, 222, 3, // Skip to: 1414 >+/* 424 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 427 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 485 >+/* 431 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 434 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 453 >+/* 438 */ MCD_OPC_CheckPredicate, 40, 26, 7, // Skip to: 2260 >+/* 442 */ MCD_OPC_CheckField, 6, 5, 0, 20, 7, // Skip to: 2260 >+/* 448 */ MCD_OPC_Decode, 146, 8, 234, 1, // Opcode: MFHC1_D64 >+/* 453 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 472 >+/* 457 */ MCD_OPC_CheckPredicate, 40, 7, 7, // Skip to: 2260 >+/* 461 */ MCD_OPC_CheckField, 6, 5, 0, 1, 7, // Skip to: 2260 >+/* 467 */ MCD_OPC_Decode, 135, 9, 235, 1, // Opcode: MTHC1_D64 >+/* 472 */ MCD_OPC_FilterValue, 17, 248, 6, // Skip to: 2260 >+/* 476 */ MCD_OPC_CheckPredicate, 41, 244, 6, // Skip to: 2260 >+/* 480 */ MCD_OPC_Decode, 151, 5, 210, 1, // Opcode: FADD_D64 >+/* 485 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 504 >+/* 489 */ MCD_OPC_CheckPredicate, 41, 231, 6, // Skip to: 2260 >+/* 493 */ MCD_OPC_CheckField, 21, 5, 17, 225, 6, // Skip to: 2260 >+/* 499 */ MCD_OPC_Decode, 153, 6, 210, 1, // Opcode: FSUB_D64 >+/* 504 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 523 >+/* 508 */ MCD_OPC_CheckPredicate, 41, 212, 6, // Skip to: 2260 >+/* 512 */ MCD_OPC_CheckField, 21, 5, 17, 206, 6, // Skip to: 2260 >+/* 518 */ MCD_OPC_Decode, 244, 5, 210, 1, // Opcode: FMUL_D64 >+/* 523 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 542 >+/* 527 */ MCD_OPC_CheckPredicate, 41, 193, 6, // Skip to: 2260 >+/* 531 */ MCD_OPC_CheckField, 21, 5, 17, 187, 6, // Skip to: 2260 >+/* 537 */ MCD_OPC_Decode, 187, 5, 210, 1, // Opcode: FDIV_D64 >+/* 542 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 561 >+/* 546 */ MCD_OPC_CheckPredicate, 42, 174, 6, // Skip to: 2260 >+/* 550 */ MCD_OPC_CheckField, 16, 10, 160, 4, 167, 6, // Skip to: 2260 >+/* 557 */ MCD_OPC_Decode, 146, 6, 82, // Opcode: FSQRT_D64 >+/* 561 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 580 >+/* 565 */ MCD_OPC_CheckPredicate, 41, 155, 6, // Skip to: 2260 >+/* 569 */ MCD_OPC_CheckField, 16, 10, 160, 4, 148, 6, // Skip to: 2260 >+/* 576 */ MCD_OPC_Decode, 144, 5, 82, // Opcode: FABS_D64 >+/* 580 */ MCD_OPC_FilterValue, 6, 15, 0, // Skip to: 599 >+/* 584 */ MCD_OPC_CheckPredicate, 41, 136, 6, // Skip to: 2260 >+/* 588 */ MCD_OPC_CheckField, 16, 10, 160, 4, 129, 6, // Skip to: 2260 >+/* 595 */ MCD_OPC_Decode, 237, 5, 82, // Opcode: FMOV_D64 >+/* 599 */ MCD_OPC_FilterValue, 7, 15, 0, // Skip to: 618 >+/* 603 */ MCD_OPC_CheckPredicate, 41, 117, 6, // Skip to: 2260 >+/* 607 */ MCD_OPC_CheckField, 16, 10, 160, 4, 110, 6, // Skip to: 2260 >+/* 614 */ MCD_OPC_Decode, 250, 5, 82, // Opcode: FNEG_D64 >+/* 618 */ MCD_OPC_FilterValue, 8, 29, 0, // Skip to: 651 >+/* 622 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 625 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 638 >+/* 630 */ MCD_OPC_CheckPredicate, 41, 90, 6, // Skip to: 2260 >+/* 634 */ MCD_OPC_Decode, 193, 10, 75, // Opcode: ROUND_L_S >+/* 638 */ MCD_OPC_FilterValue, 160, 4, 81, 6, // Skip to: 2260 >+/* 643 */ MCD_OPC_CheckPredicate, 41, 77, 6, // Skip to: 2260 >+/* 647 */ MCD_OPC_Decode, 192, 10, 82, // Opcode: ROUND_L_D64 >+/* 651 */ MCD_OPC_FilterValue, 9, 29, 0, // Skip to: 684 >+/* 655 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 658 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 671 >+/* 663 */ MCD_OPC_CheckPredicate, 41, 57, 6, // Skip to: 2260 >+/* 667 */ MCD_OPC_Decode, 141, 13, 75, // Opcode: TRUNC_L_S >+/* 671 */ MCD_OPC_FilterValue, 160, 4, 48, 6, // Skip to: 2260 >+/* 676 */ MCD_OPC_CheckPredicate, 41, 44, 6, // Skip to: 2260 >+/* 680 */ MCD_OPC_Decode, 140, 13, 82, // Opcode: TRUNC_L_D64 >+/* 684 */ MCD_OPC_FilterValue, 10, 29, 0, // Skip to: 717 >+/* 688 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 691 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 704 >+/* 696 */ MCD_OPC_CheckPredicate, 41, 24, 6, // Skip to: 2260 >+/* 700 */ MCD_OPC_Decode, 204, 2, 75, // Opcode: CEIL_L_S >+/* 704 */ MCD_OPC_FilterValue, 160, 4, 15, 6, // Skip to: 2260 >+/* 709 */ MCD_OPC_CheckPredicate, 41, 11, 6, // Skip to: 2260 >+/* 713 */ MCD_OPC_Decode, 203, 2, 82, // Opcode: CEIL_L_D64 >+/* 717 */ MCD_OPC_FilterValue, 11, 29, 0, // Skip to: 750 >+/* 721 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 724 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 737 >+/* 729 */ MCD_OPC_CheckPredicate, 41, 247, 5, // Skip to: 2260 >+/* 733 */ MCD_OPC_Decode, 219, 5, 75, // Opcode: FLOOR_L_S >+/* 737 */ MCD_OPC_FilterValue, 160, 4, 238, 5, // Skip to: 2260 >+/* 742 */ MCD_OPC_CheckPredicate, 41, 234, 5, // Skip to: 2260 >+/* 746 */ MCD_OPC_Decode, 218, 5, 82, // Opcode: FLOOR_L_D64 >+/* 750 */ MCD_OPC_FilterValue, 12, 16, 0, // Skip to: 770 >+/* 754 */ MCD_OPC_CheckPredicate, 42, 222, 5, // Skip to: 2260 >+/* 758 */ MCD_OPC_CheckField, 16, 10, 160, 4, 215, 5, // Skip to: 2260 >+/* 765 */ MCD_OPC_Decode, 195, 10, 236, 1, // Opcode: ROUND_W_D64 >+/* 770 */ MCD_OPC_FilterValue, 13, 16, 0, // Skip to: 790 >+/* 774 */ MCD_OPC_CheckPredicate, 42, 202, 5, // Skip to: 2260 >+/* 778 */ MCD_OPC_CheckField, 16, 10, 160, 4, 195, 5, // Skip to: 2260 >+/* 785 */ MCD_OPC_Decode, 143, 13, 236, 1, // Opcode: TRUNC_W_D64 >+/* 790 */ MCD_OPC_FilterValue, 14, 16, 0, // Skip to: 810 >+/* 794 */ MCD_OPC_CheckPredicate, 42, 182, 5, // Skip to: 2260 >+/* 798 */ MCD_OPC_CheckField, 16, 10, 160, 4, 175, 5, // Skip to: 2260 >+/* 805 */ MCD_OPC_Decode, 206, 2, 236, 1, // Opcode: CEIL_W_D64 >+/* 810 */ MCD_OPC_FilterValue, 15, 16, 0, // Skip to: 830 >+/* 814 */ MCD_OPC_CheckPredicate, 42, 162, 5, // Skip to: 2260 >+/* 818 */ MCD_OPC_CheckField, 16, 10, 160, 4, 155, 5, // Skip to: 2260 >+/* 825 */ MCD_OPC_Decode, 221, 5, 236, 1, // Opcode: FLOOR_W_D64 >+/* 830 */ MCD_OPC_FilterValue, 17, 41, 0, // Skip to: 875 >+/* 834 */ MCD_OPC_ExtractField, 16, 2, // Inst{17-16} ... >+/* 837 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 856 >+/* 841 */ MCD_OPC_CheckPredicate, 43, 135, 5, // Skip to: 2260 >+/* 845 */ MCD_OPC_CheckField, 21, 5, 17, 129, 5, // Skip to: 2260 >+/* 851 */ MCD_OPC_Decode, 199, 8, 237, 1, // Opcode: MOVF_D64 >+/* 856 */ MCD_OPC_FilterValue, 1, 120, 5, // Skip to: 2260 >+/* 860 */ MCD_OPC_CheckPredicate, 43, 116, 5, // Skip to: 2260 >+/* 864 */ MCD_OPC_CheckField, 21, 5, 17, 110, 5, // Skip to: 2260 >+/* 870 */ MCD_OPC_Decode, 219, 8, 237, 1, // Opcode: MOVT_D64 >+/* 875 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 894 >+/* 879 */ MCD_OPC_CheckPredicate, 43, 97, 5, // Skip to: 2260 >+/* 883 */ MCD_OPC_CheckField, 21, 5, 17, 91, 5, // Skip to: 2260 >+/* 889 */ MCD_OPC_Decode, 231, 8, 238, 1, // Opcode: MOVZ_I_D64 >+/* 894 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 913 >+/* 898 */ MCD_OPC_CheckPredicate, 43, 78, 5, // Skip to: 2260 >+/* 902 */ MCD_OPC_CheckField, 21, 5, 17, 72, 5, // Skip to: 2260 >+/* 908 */ MCD_OPC_Decode, 211, 8, 238, 1, // Opcode: MOVN_I_D64 >+/* 913 */ MCD_OPC_FilterValue, 32, 31, 0, // Skip to: 948 >+/* 917 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 920 */ MCD_OPC_FilterValue, 160, 4, 9, 0, // Skip to: 934 >+/* 925 */ MCD_OPC_CheckPredicate, 41, 51, 5, // Skip to: 2260 >+/* 929 */ MCD_OPC_Decode, 206, 3, 236, 1, // Opcode: CVT_S_D64 >+/* 934 */ MCD_OPC_FilterValue, 160, 5, 41, 5, // Skip to: 2260 >+/* 939 */ MCD_OPC_CheckPredicate, 41, 37, 5, // Skip to: 2260 >+/* 943 */ MCD_OPC_Decode, 207, 3, 236, 1, // Opcode: CVT_S_L >+/* 948 */ MCD_OPC_FilterValue, 33, 42, 0, // Skip to: 994 >+/* 952 */ MCD_OPC_ExtractField, 16, 10, // Inst{25-16} ... >+/* 955 */ MCD_OPC_FilterValue, 128, 4, 8, 0, // Skip to: 968 >+/* 960 */ MCD_OPC_CheckPredicate, 41, 16, 5, // Skip to: 2260 >+/* 964 */ MCD_OPC_Decode, 197, 3, 75, // Opcode: CVT_D64_S >+/* 968 */ MCD_OPC_FilterValue, 128, 5, 8, 0, // Skip to: 981 >+/* 973 */ MCD_OPC_CheckPredicate, 41, 3, 5, // Skip to: 2260 >+/* 977 */ MCD_OPC_Decode, 198, 3, 75, // Opcode: CVT_D64_W >+/* 981 */ MCD_OPC_FilterValue, 160, 5, 250, 4, // Skip to: 2260 >+/* 986 */ MCD_OPC_CheckPredicate, 41, 246, 4, // Skip to: 2260 >+/* 990 */ MCD_OPC_Decode, 196, 3, 82, // Opcode: CVT_D64_L >+/* 994 */ MCD_OPC_FilterValue, 36, 16, 0, // Skip to: 1014 >+/* 998 */ MCD_OPC_CheckPredicate, 41, 234, 4, // Skip to: 2260 >+/* 1002 */ MCD_OPC_CheckField, 16, 10, 160, 4, 227, 4, // Skip to: 2260 >+/* 1009 */ MCD_OPC_Decode, 211, 3, 236, 1, // Opcode: CVT_W_D64 >+/* 1014 */ MCD_OPC_FilterValue, 48, 21, 0, // Skip to: 1039 >+/* 1018 */ MCD_OPC_CheckPredicate, 44, 214, 4, // Skip to: 2260 >+/* 1022 */ MCD_OPC_CheckField, 21, 5, 17, 208, 4, // Skip to: 2260 >+/* 1028 */ MCD_OPC_CheckField, 6, 5, 0, 202, 4, // Skip to: 2260 >+/* 1034 */ MCD_OPC_Decode, 219, 3, 239, 1, // Opcode: C_F_D64 >+/* 1039 */ MCD_OPC_FilterValue, 49, 21, 0, // Skip to: 1064 >+/* 1043 */ MCD_OPC_CheckPredicate, 44, 189, 4, // Skip to: 2260 >+/* 1047 */ MCD_OPC_CheckField, 21, 5, 17, 183, 4, // Skip to: 2260 >+/* 1053 */ MCD_OPC_CheckField, 6, 5, 0, 177, 4, // Skip to: 2260 >+/* 1059 */ MCD_OPC_Decode, 133, 4, 239, 1, // Opcode: C_UN_D64 >+/* 1064 */ MCD_OPC_FilterValue, 50, 21, 0, // Skip to: 1089 >+/* 1068 */ MCD_OPC_CheckPredicate, 44, 164, 4, // Skip to: 2260 >+/* 1072 */ MCD_OPC_CheckField, 21, 5, 17, 158, 4, // Skip to: 2260 >+/* 1078 */ MCD_OPC_CheckField, 6, 5, 0, 152, 4, // Skip to: 2260 >+/* 1084 */ MCD_OPC_Decode, 216, 3, 239, 1, // Opcode: C_EQ_D64 >+/* 1089 */ MCD_OPC_FilterValue, 51, 21, 0, // Skip to: 1114 >+/* 1093 */ MCD_OPC_CheckPredicate, 44, 139, 4, // Skip to: 2260 >+/* 1097 */ MCD_OPC_CheckField, 21, 5, 17, 133, 4, // Skip to: 2260 >+/* 1103 */ MCD_OPC_CheckField, 6, 5, 0, 127, 4, // Skip to: 2260 >+/* 1109 */ MCD_OPC_Decode, 252, 3, 239, 1, // Opcode: C_UEQ_D64 >+/* 1114 */ MCD_OPC_FilterValue, 52, 21, 0, // Skip to: 1139 >+/* 1118 */ MCD_OPC_CheckPredicate, 44, 114, 4, // Skip to: 2260 >+/* 1122 */ MCD_OPC_CheckField, 21, 5, 17, 108, 4, // Skip to: 2260 >+/* 1128 */ MCD_OPC_CheckField, 6, 5, 0, 102, 4, // Skip to: 2260 >+/* 1134 */ MCD_OPC_Decode, 243, 3, 239, 1, // Opcode: C_OLT_D64 >+/* 1139 */ MCD_OPC_FilterValue, 53, 21, 0, // Skip to: 1164 >+/* 1143 */ MCD_OPC_CheckPredicate, 44, 89, 4, // Skip to: 2260 >+/* 1147 */ MCD_OPC_CheckField, 21, 5, 17, 83, 4, // Skip to: 2260 >+/* 1153 */ MCD_OPC_CheckField, 6, 5, 0, 77, 4, // Skip to: 2260 >+/* 1159 */ MCD_OPC_Decode, 130, 4, 239, 1, // Opcode: C_ULT_D64 >+/* 1164 */ MCD_OPC_FilterValue, 54, 21, 0, // Skip to: 1189 >+/* 1168 */ MCD_OPC_CheckPredicate, 44, 64, 4, // Skip to: 2260 >+/* 1172 */ MCD_OPC_CheckField, 21, 5, 17, 58, 4, // Skip to: 2260 >+/* 1178 */ MCD_OPC_CheckField, 6, 5, 0, 52, 4, // Skip to: 2260 >+/* 1184 */ MCD_OPC_Decode, 240, 3, 239, 1, // Opcode: C_OLE_D64 >+/* 1189 */ MCD_OPC_FilterValue, 55, 21, 0, // Skip to: 1214 >+/* 1193 */ MCD_OPC_CheckPredicate, 44, 39, 4, // Skip to: 2260 >+/* 1197 */ MCD_OPC_CheckField, 21, 5, 17, 33, 4, // Skip to: 2260 >+/* 1203 */ MCD_OPC_CheckField, 6, 5, 0, 27, 4, // Skip to: 2260 >+/* 1209 */ MCD_OPC_Decode, 255, 3, 239, 1, // Opcode: C_ULE_D64 >+/* 1214 */ MCD_OPC_FilterValue, 56, 21, 0, // Skip to: 1239 >+/* 1218 */ MCD_OPC_CheckPredicate, 44, 14, 4, // Skip to: 2260 >+/* 1222 */ MCD_OPC_CheckField, 21, 5, 17, 8, 4, // Skip to: 2260 >+/* 1228 */ MCD_OPC_CheckField, 6, 5, 0, 2, 4, // Skip to: 2260 >+/* 1234 */ MCD_OPC_Decode, 249, 3, 239, 1, // Opcode: C_SF_D64 >+/* 1239 */ MCD_OPC_FilterValue, 57, 21, 0, // Skip to: 1264 >+/* 1243 */ MCD_OPC_CheckPredicate, 44, 245, 3, // Skip to: 2260 >+/* 1247 */ MCD_OPC_CheckField, 21, 5, 17, 239, 3, // Skip to: 2260 >+/* 1253 */ MCD_OPC_CheckField, 6, 5, 0, 233, 3, // Skip to: 2260 >+/* 1259 */ MCD_OPC_Decode, 231, 3, 239, 1, // Opcode: C_NGLE_D64 >+/* 1264 */ MCD_OPC_FilterValue, 58, 21, 0, // Skip to: 1289 >+/* 1268 */ MCD_OPC_CheckPredicate, 44, 220, 3, // Skip to: 2260 >+/* 1272 */ MCD_OPC_CheckField, 21, 5, 17, 214, 3, // Skip to: 2260 >+/* 1278 */ MCD_OPC_CheckField, 6, 5, 0, 208, 3, // Skip to: 2260 >+/* 1284 */ MCD_OPC_Decode, 246, 3, 239, 1, // Opcode: C_SEQ_D64 >+/* 1289 */ MCD_OPC_FilterValue, 59, 21, 0, // Skip to: 1314 >+/* 1293 */ MCD_OPC_CheckPredicate, 44, 195, 3, // Skip to: 2260 >+/* 1297 */ MCD_OPC_CheckField, 21, 5, 17, 189, 3, // Skip to: 2260 >+/* 1303 */ MCD_OPC_CheckField, 6, 5, 0, 183, 3, // Skip to: 2260 >+/* 1309 */ MCD_OPC_Decode, 234, 3, 239, 1, // Opcode: C_NGL_D64 >+/* 1314 */ MCD_OPC_FilterValue, 60, 21, 0, // Skip to: 1339 >+/* 1318 */ MCD_OPC_CheckPredicate, 44, 170, 3, // Skip to: 2260 >+/* 1322 */ MCD_OPC_CheckField, 21, 5, 17, 164, 3, // Skip to: 2260 >+/* 1328 */ MCD_OPC_CheckField, 6, 5, 0, 158, 3, // Skip to: 2260 >+/* 1334 */ MCD_OPC_Decode, 225, 3, 239, 1, // Opcode: C_LT_D64 >+/* 1339 */ MCD_OPC_FilterValue, 61, 21, 0, // Skip to: 1364 >+/* 1343 */ MCD_OPC_CheckPredicate, 44, 145, 3, // Skip to: 2260 >+/* 1347 */ MCD_OPC_CheckField, 21, 5, 17, 139, 3, // Skip to: 2260 >+/* 1353 */ MCD_OPC_CheckField, 6, 5, 0, 133, 3, // Skip to: 2260 >+/* 1359 */ MCD_OPC_Decode, 228, 3, 239, 1, // Opcode: C_NGE_D64 >+/* 1364 */ MCD_OPC_FilterValue, 62, 21, 0, // Skip to: 1389 >+/* 1368 */ MCD_OPC_CheckPredicate, 44, 120, 3, // Skip to: 2260 >+/* 1372 */ MCD_OPC_CheckField, 21, 5, 17, 114, 3, // Skip to: 2260 >+/* 1378 */ MCD_OPC_CheckField, 6, 5, 0, 108, 3, // Skip to: 2260 >+/* 1384 */ MCD_OPC_Decode, 222, 3, 239, 1, // Opcode: C_LE_D64 >+/* 1389 */ MCD_OPC_FilterValue, 63, 99, 3, // Skip to: 2260 >+/* 1393 */ MCD_OPC_CheckPredicate, 44, 95, 3, // Skip to: 2260 >+/* 1397 */ MCD_OPC_CheckField, 21, 5, 17, 89, 3, // Skip to: 2260 >+/* 1403 */ MCD_OPC_CheckField, 6, 5, 0, 83, 3, // Skip to: 2260 >+/* 1409 */ MCD_OPC_Decode, 237, 3, 239, 1, // Opcode: C_NGT_D64 >+/* 1414 */ MCD_OPC_FilterValue, 18, 41, 0, // Skip to: 1459 >+/* 1418 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... >+/* 1421 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1440 >+/* 1425 */ MCD_OPC_CheckPredicate, 39, 63, 3, // Skip to: 2260 >+/* 1429 */ MCD_OPC_CheckField, 3, 8, 0, 57, 3, // Skip to: 2260 >+/* 1435 */ MCD_OPC_Decode, 178, 4, 233, 1, // Opcode: DMFC2 >+/* 1440 */ MCD_OPC_FilterValue, 5, 48, 3, // Skip to: 2260 >+/* 1444 */ MCD_OPC_CheckPredicate, 39, 44, 3, // Skip to: 2260 >+/* 1448 */ MCD_OPC_CheckField, 3, 8, 0, 38, 3, // Skip to: 2260 >+/* 1454 */ MCD_OPC_Decode, 183, 4, 233, 1, // Opcode: DMTC2 >+/* 1459 */ MCD_OPC_FilterValue, 19, 79, 0, // Skip to: 1542 >+/* 1463 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1466 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 1485 >+/* 1470 */ MCD_OPC_CheckPredicate, 45, 18, 3, // Skip to: 2260 >+/* 1474 */ MCD_OPC_CheckField, 11, 5, 0, 12, 3, // Skip to: 2260 >+/* 1480 */ MCD_OPC_Decode, 148, 7, 240, 1, // Opcode: LDXC164 >+/* 1485 */ MCD_OPC_FilterValue, 5, 15, 0, // Skip to: 1504 >+/* 1489 */ MCD_OPC_CheckPredicate, 46, 255, 2, // Skip to: 2260 >+/* 1493 */ MCD_OPC_CheckField, 11, 5, 0, 249, 2, // Skip to: 2260 >+/* 1499 */ MCD_OPC_Decode, 178, 7, 240, 1, // Opcode: LUXC164 >+/* 1504 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1523 >+/* 1508 */ MCD_OPC_CheckPredicate, 45, 236, 2, // Skip to: 2260 >+/* 1512 */ MCD_OPC_CheckField, 6, 5, 0, 230, 2, // Skip to: 2260 >+/* 1518 */ MCD_OPC_Decode, 233, 10, 241, 1, // Opcode: SDXC164 >+/* 1523 */ MCD_OPC_FilterValue, 13, 221, 2, // Skip to: 2260 >+/* 1527 */ MCD_OPC_CheckPredicate, 46, 217, 2, // Skip to: 2260 >+/* 1531 */ MCD_OPC_CheckField, 6, 5, 0, 211, 2, // Skip to: 2260 >+/* 1537 */ MCD_OPC_Decode, 166, 12, 241, 1, // Opcode: SUXC164 >+/* 1542 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 1555 >+/* 1546 */ MCD_OPC_CheckPredicate, 38, 198, 2, // Skip to: 2260 >+/* 1550 */ MCD_OPC_Decode, 140, 4, 242, 1, // Opcode: DADDi >+/* 1555 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 1568 >+/* 1559 */ MCD_OPC_CheckPredicate, 17, 185, 2, // Skip to: 2260 >+/* 1563 */ MCD_OPC_Decode, 141, 4, 242, 1, // Opcode: DADDiu >+/* 1568 */ MCD_OPC_FilterValue, 26, 9, 0, // Skip to: 1581 >+/* 1572 */ MCD_OPC_CheckPredicate, 38, 172, 2, // Skip to: 2260 >+/* 1576 */ MCD_OPC_Decode, 144, 7, 194, 1, // Opcode: LDL >+/* 1581 */ MCD_OPC_FilterValue, 27, 9, 0, // Skip to: 1594 >+/* 1585 */ MCD_OPC_CheckPredicate, 38, 159, 2, // Skip to: 2260 >+/* 1589 */ MCD_OPC_Decode, 146, 7, 194, 1, // Opcode: LDR >+/* 1594 */ MCD_OPC_FilterValue, 28, 159, 1, // Skip to: 2013 >+/* 1598 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 1601 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 1620 >+/* 1605 */ MCD_OPC_CheckPredicate, 47, 139, 2, // Skip to: 2260 >+/* 1609 */ MCD_OPC_CheckField, 6, 5, 0, 133, 2, // Skip to: 2260 >+/* 1615 */ MCD_OPC_Decode, 186, 4, 201, 1, // Opcode: DMUL >+/* 1620 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 1639 >+/* 1624 */ MCD_OPC_CheckPredicate, 47, 120, 2, // Skip to: 2260 >+/* 1628 */ MCD_OPC_CheckField, 6, 15, 0, 114, 2, // Skip to: 2260 >+/* 1634 */ MCD_OPC_Decode, 146, 9, 243, 1, // Opcode: MTM0 >+/* 1639 */ MCD_OPC_FilterValue, 9, 15, 0, // Skip to: 1658 >+/* 1643 */ MCD_OPC_CheckPredicate, 47, 101, 2, // Skip to: 2260 >+/* 1647 */ MCD_OPC_CheckField, 6, 15, 0, 95, 2, // Skip to: 2260 >+/* 1653 */ MCD_OPC_Decode, 149, 9, 243, 1, // Opcode: MTP0 >+/* 1658 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 1677 >+/* 1662 */ MCD_OPC_CheckPredicate, 47, 82, 2, // Skip to: 2260 >+/* 1666 */ MCD_OPC_CheckField, 6, 15, 0, 76, 2, // Skip to: 2260 >+/* 1672 */ MCD_OPC_Decode, 150, 9, 243, 1, // Opcode: MTP1 >+/* 1677 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 1696 >+/* 1681 */ MCD_OPC_CheckPredicate, 47, 63, 2, // Skip to: 2260 >+/* 1685 */ MCD_OPC_CheckField, 6, 15, 0, 57, 2, // Skip to: 2260 >+/* 1691 */ MCD_OPC_Decode, 151, 9, 243, 1, // Opcode: MTP2 >+/* 1696 */ MCD_OPC_FilterValue, 12, 15, 0, // Skip to: 1715 >+/* 1700 */ MCD_OPC_CheckPredicate, 47, 44, 2, // Skip to: 2260 >+/* 1704 */ MCD_OPC_CheckField, 6, 15, 0, 38, 2, // Skip to: 2260 >+/* 1710 */ MCD_OPC_Decode, 147, 9, 243, 1, // Opcode: MTM1 >+/* 1715 */ MCD_OPC_FilterValue, 13, 15, 0, // Skip to: 1734 >+/* 1719 */ MCD_OPC_CheckPredicate, 47, 25, 2, // Skip to: 2260 >+/* 1723 */ MCD_OPC_CheckField, 6, 15, 0, 19, 2, // Skip to: 2260 >+/* 1729 */ MCD_OPC_Decode, 148, 9, 243, 1, // Opcode: MTM2 >+/* 1734 */ MCD_OPC_FilterValue, 15, 15, 0, // Skip to: 1753 >+/* 1738 */ MCD_OPC_CheckPredicate, 47, 6, 2, // Skip to: 2260 >+/* 1742 */ MCD_OPC_CheckField, 6, 5, 0, 0, 2, // Skip to: 2260 >+/* 1748 */ MCD_OPC_Decode, 152, 13, 201, 1, // Opcode: VMULU >+/* 1753 */ MCD_OPC_FilterValue, 16, 15, 0, // Skip to: 1772 >+/* 1757 */ MCD_OPC_CheckPredicate, 47, 243, 1, // Skip to: 2260 >+/* 1761 */ MCD_OPC_CheckField, 6, 5, 0, 237, 1, // Skip to: 2260 >+/* 1767 */ MCD_OPC_Decode, 151, 13, 201, 1, // Opcode: VMM0 >+/* 1772 */ MCD_OPC_FilterValue, 17, 15, 0, // Skip to: 1791 >+/* 1776 */ MCD_OPC_CheckPredicate, 47, 224, 1, // Skip to: 2260 >+/* 1780 */ MCD_OPC_CheckField, 6, 5, 0, 218, 1, // Skip to: 2260 >+/* 1786 */ MCD_OPC_Decode, 150, 13, 201, 1, // Opcode: V3MULU >+/* 1791 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 1810 >+/* 1795 */ MCD_OPC_CheckPredicate, 48, 205, 1, // Skip to: 2260 >+/* 1799 */ MCD_OPC_CheckField, 6, 5, 0, 199, 1, // Skip to: 2260 >+/* 1805 */ MCD_OPC_Decode, 150, 4, 244, 1, // Opcode: DCLZ >+/* 1810 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 1829 >+/* 1814 */ MCD_OPC_CheckPredicate, 48, 186, 1, // Skip to: 2260 >+/* 1818 */ MCD_OPC_CheckField, 6, 5, 0, 180, 1, // Skip to: 2260 >+/* 1824 */ MCD_OPC_Decode, 148, 4, 244, 1, // Opcode: DCLO >+/* 1829 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 1848 >+/* 1833 */ MCD_OPC_CheckPredicate, 47, 167, 1, // Skip to: 2260 >+/* 1837 */ MCD_OPC_CheckField, 6, 5, 0, 161, 1, // Skip to: 2260 >+/* 1843 */ MCD_OPC_Decode, 155, 1, 201, 1, // Opcode: BADDu >+/* 1848 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 1867 >+/* 1852 */ MCD_OPC_CheckPredicate, 47, 148, 1, // Skip to: 2260 >+/* 1856 */ MCD_OPC_CheckField, 6, 5, 0, 142, 1, // Skip to: 2260 >+/* 1862 */ MCD_OPC_Decode, 250, 10, 201, 1, // Opcode: SEQ >+/* 1867 */ MCD_OPC_FilterValue, 43, 15, 0, // Skip to: 1886 >+/* 1871 */ MCD_OPC_CheckPredicate, 47, 129, 1, // Skip to: 2260 >+/* 1875 */ MCD_OPC_CheckField, 6, 5, 0, 123, 1, // Skip to: 2260 >+/* 1881 */ MCD_OPC_Decode, 188, 11, 201, 1, // Opcode: SNE >+/* 1886 */ MCD_OPC_FilterValue, 44, 20, 0, // Skip to: 1910 >+/* 1890 */ MCD_OPC_CheckPredicate, 47, 110, 1, // Skip to: 2260 >+/* 1894 */ MCD_OPC_CheckField, 16, 5, 0, 104, 1, // Skip to: 2260 >+/* 1900 */ MCD_OPC_CheckField, 6, 5, 0, 98, 1, // Skip to: 2260 >+/* 1906 */ MCD_OPC_Decode, 249, 9, 40, // Opcode: POP >+/* 1910 */ MCD_OPC_FilterValue, 45, 21, 0, // Skip to: 1935 >+/* 1914 */ MCD_OPC_CheckPredicate, 47, 86, 1, // Skip to: 2260 >+/* 1918 */ MCD_OPC_CheckField, 16, 5, 0, 80, 1, // Skip to: 2260 >+/* 1924 */ MCD_OPC_CheckField, 6, 5, 0, 74, 1, // Skip to: 2260 >+/* 1930 */ MCD_OPC_Decode, 211, 4, 199, 1, // Opcode: DPOP >+/* 1935 */ MCD_OPC_FilterValue, 46, 9, 0, // Skip to: 1948 >+/* 1939 */ MCD_OPC_CheckPredicate, 47, 61, 1, // Skip to: 2260 >+/* 1943 */ MCD_OPC_Decode, 251, 10, 245, 1, // Opcode: SEQi >+/* 1948 */ MCD_OPC_FilterValue, 47, 9, 0, // Skip to: 1961 >+/* 1952 */ MCD_OPC_CheckPredicate, 47, 48, 1, // Skip to: 2260 >+/* 1956 */ MCD_OPC_Decode, 189, 11, 245, 1, // Opcode: SNEi >+/* 1961 */ MCD_OPC_FilterValue, 50, 9, 0, // Skip to: 1974 >+/* 1965 */ MCD_OPC_CheckPredicate, 47, 35, 1, // Skip to: 2260 >+/* 1969 */ MCD_OPC_Decode, 221, 2, 246, 1, // Opcode: CINS >+/* 1974 */ MCD_OPC_FilterValue, 51, 9, 0, // Skip to: 1987 >+/* 1978 */ MCD_OPC_CheckPredicate, 47, 22, 1, // Skip to: 2260 >+/* 1982 */ MCD_OPC_Decode, 222, 2, 246, 1, // Opcode: CINS32 >+/* 1987 */ MCD_OPC_FilterValue, 58, 9, 0, // Skip to: 2000 >+/* 1991 */ MCD_OPC_CheckPredicate, 47, 9, 1, // Skip to: 2260 >+/* 1995 */ MCD_OPC_Decode, 137, 5, 246, 1, // Opcode: EXTS >+/* 2000 */ MCD_OPC_FilterValue, 59, 0, 1, // Skip to: 2260 >+/* 2004 */ MCD_OPC_CheckPredicate, 47, 252, 0, // Skip to: 2260 >+/* 2008 */ MCD_OPC_Decode, 138, 5, 246, 1, // Opcode: EXTS32 >+/* 2013 */ MCD_OPC_FilterValue, 31, 126, 0, // Skip to: 2143 >+/* 2017 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ... >+/* 2020 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 2033 >+/* 2024 */ MCD_OPC_CheckPredicate, 4, 232, 0, // Skip to: 2260 >+/* 2028 */ MCD_OPC_Decode, 157, 4, 247, 1, // Opcode: DEXTM >+/* 2033 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 2046 >+/* 2037 */ MCD_OPC_CheckPredicate, 4, 219, 0, // Skip to: 2260 >+/* 2041 */ MCD_OPC_Decode, 158, 4, 247, 1, // Opcode: DEXTU >+/* 2046 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 2059 >+/* 2050 */ MCD_OPC_CheckPredicate, 4, 206, 0, // Skip to: 2260 >+/* 2054 */ MCD_OPC_Decode, 156, 4, 247, 1, // Opcode: DEXT >+/* 2059 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 2072 >+/* 2063 */ MCD_OPC_CheckPredicate, 4, 193, 0, // Skip to: 2260 >+/* 2067 */ MCD_OPC_Decode, 161, 4, 248, 1, // Opcode: DINSM >+/* 2072 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 2085 >+/* 2076 */ MCD_OPC_CheckPredicate, 4, 180, 0, // Skip to: 2260 >+/* 2080 */ MCD_OPC_Decode, 162, 4, 248, 1, // Opcode: DINSU >+/* 2085 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 2098 >+/* 2089 */ MCD_OPC_CheckPredicate, 4, 167, 0, // Skip to: 2260 >+/* 2093 */ MCD_OPC_Decode, 160, 4, 248, 1, // Opcode: DINS >+/* 2098 */ MCD_OPC_FilterValue, 36, 158, 0, // Skip to: 2260 >+/* 2102 */ MCD_OPC_ExtractField, 6, 5, // Inst{10-6} ... >+/* 2105 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 2124 >+/* 2109 */ MCD_OPC_CheckPredicate, 37, 147, 0, // Skip to: 2260 >+/* 2113 */ MCD_OPC_CheckField, 21, 5, 0, 141, 0, // Skip to: 2260 >+/* 2119 */ MCD_OPC_Decode, 229, 4, 220, 1, // Opcode: DSBH >+/* 2124 */ MCD_OPC_FilterValue, 5, 132, 0, // Skip to: 2260 >+/* 2128 */ MCD_OPC_CheckPredicate, 37, 128, 0, // Skip to: 2260 >+/* 2132 */ MCD_OPC_CheckField, 21, 5, 0, 122, 0, // Skip to: 2260 >+/* 2138 */ MCD_OPC_Decode, 231, 4, 220, 1, // Opcode: DSHD >+/* 2143 */ MCD_OPC_FilterValue, 39, 9, 0, // Skip to: 2156 >+/* 2147 */ MCD_OPC_CheckPredicate, 17, 109, 0, // Skip to: 2260 >+/* 2151 */ MCD_OPC_Decode, 203, 7, 194, 1, // Opcode: LWu >+/* 2156 */ MCD_OPC_FilterValue, 44, 9, 0, // Skip to: 2169 >+/* 2160 */ MCD_OPC_CheckPredicate, 38, 96, 0, // Skip to: 2260 >+/* 2164 */ MCD_OPC_Decode, 230, 10, 194, 1, // Opcode: SDL >+/* 2169 */ MCD_OPC_FilterValue, 45, 9, 0, // Skip to: 2182 >+/* 2173 */ MCD_OPC_CheckPredicate, 38, 83, 0, // Skip to: 2260 >+/* 2177 */ MCD_OPC_Decode, 231, 10, 194, 1, // Opcode: SDR >+/* 2182 */ MCD_OPC_FilterValue, 52, 9, 0, // Skip to: 2195 >+/* 2186 */ MCD_OPC_CheckPredicate, 38, 70, 0, // Skip to: 2260 >+/* 2190 */ MCD_OPC_Decode, 164, 7, 194, 1, // Opcode: LLD >+/* 2195 */ MCD_OPC_FilterValue, 53, 9, 0, // Skip to: 2208 >+/* 2199 */ MCD_OPC_CheckPredicate, 49, 57, 0, // Skip to: 2260 >+/* 2203 */ MCD_OPC_Decode, 135, 7, 196, 1, // Opcode: LDC164 >+/* 2208 */ MCD_OPC_FilterValue, 55, 9, 0, // Skip to: 2221 >+/* 2212 */ MCD_OPC_CheckPredicate, 17, 44, 0, // Skip to: 2260 >+/* 2216 */ MCD_OPC_Decode, 133, 7, 194, 1, // Opcode: LD >+/* 2221 */ MCD_OPC_FilterValue, 60, 9, 0, // Skip to: 2234 >+/* 2225 */ MCD_OPC_CheckPredicate, 38, 31, 0, // Skip to: 2260 >+/* 2229 */ MCD_OPC_Decode, 215, 10, 194, 1, // Opcode: SCD >+/* 2234 */ MCD_OPC_FilterValue, 61, 9, 0, // Skip to: 2247 >+/* 2238 */ MCD_OPC_CheckPredicate, 49, 18, 0, // Skip to: 2260 >+/* 2242 */ MCD_OPC_Decode, 223, 10, 196, 1, // Opcode: SDC164 >+/* 2247 */ MCD_OPC_FilterValue, 63, 9, 0, // Skip to: 2260 >+/* 2251 */ MCD_OPC_CheckPredicate, 17, 5, 0, // Skip to: 2260 >+/* 2255 */ MCD_OPC_Decode, 219, 10, 194, 1, // Opcode: SD >+/* 2260 */ MCD_OPC_Fail, >+ 0 >+}; >+ >+static bool getbool(uint64_t b) >+{ >+ return b != 0; >+} >+ >+static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) >+{ >+ switch (Idx) { >+ default: // llvm_unreachable("Invalid index!"); >+ case 0: >+ return getbool((Bits & Mips_FeatureMips16)); >+ case 1: >+ return getbool(!(Bits & Mips_FeatureMips16)); >+ case 2: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2)); >+ case 3: >+ return getbool((Bits & Mips_FeatureMicroMips)); >+ case 4: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2)); >+ case 5: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 6: >+ return getbool((Bits & Mips_FeatureMSA)); >+ case 7: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 8: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMicroMips)); >+ case 9: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32)); >+ case 10: >+ return getbool(!(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 11: >+ return getbool((Bits & Mips_FeatureDSP)); >+ case 12: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 13: >+ return getbool((Bits & Mips_FeatureMSA) && (Bits & Mips_FeatureMips64)); >+ case 14: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 15: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32)); >+ case 16: >+ return getbool(!(Bits & Mips_FeatureMicroMips)); >+ case 17: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3)); >+ case 18: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureFP64Bit)); >+ case 19: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit)); >+ case 20: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32r2)); >+ case 21: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureFP64Bit)); >+ case 22: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 23: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureFP64Bit)); >+ case 24: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 25: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 26: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 27: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 28: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 29: >+ return getbool((Bits & Mips_FeatureDSPR2)); >+ case 30: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 31: >+ return getbool((Bits & Mips_FeatureMips2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && !(Bits & Mips_FeatureMicroMips)); >+ case 32: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); >+ case 33: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r6)); >+ case 34: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r6)); >+ case 35: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); >+ case 36: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureGP64Bit) && (Bits & Mips_FeatureMips32r6)); >+ case 37: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64r2)); >+ case 38: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips3) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 39: >+ return getbool((Bits & Mips_FeatureMips64)); >+ case 40: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips32r2) && (Bits & Mips_FeatureFP64Bit)); >+ case 41: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit)); >+ case 42: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips2) && (Bits & Mips_FeatureFP64Bit)); >+ case 43: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 44: >+ return getbool(!(Bits & Mips_FeatureMips16) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6) && (Bits & Mips_FeatureFP64Bit)); >+ case 45: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips4_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 46: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips5_32r2) && !(Bits & Mips_FeatureMips32r6) && !(Bits & Mips_FeatureMips64r6)); >+ case 47: >+ return getbool((Bits & Mips_FeatureCnMips)); >+ case 48: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureMips64) && !(Bits & Mips_FeatureMips64r6)); >+ case 49: >+ return getbool(!(Bits & Mips_FeatureMips16) && (Bits & Mips_FeatureFP64Bit) && (Bits & Mips_FeatureMips2)); >+ } >+} >+ >+#define DecodeToMCInst(fname,fieldname, InsnType) \ >+static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ >+ uint64_t Address, const void *Decoder) \ >+{ \ >+ InsnType tmp; \ >+ switch (Idx) { \ >+ default: \ >+ case 0: \ >+ return S; \ >+ case 1: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 2: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 3: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 3, 2) << 3); \ >+ tmp |= (fieldname(insn, 5, 3) << 0); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 4: \ >+ tmp = fieldname(insn, 0, 4); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 5: \ >+ tmp = fieldname(insn, 2, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 6: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 7: \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 8, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 8: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 5) << 0); \ >+ tmp |= (fieldname(insn, 16, 5) << 11); \ >+ tmp |= (fieldname(insn, 21, 6) << 5); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 9: \ >+ tmp = fieldname(insn, 5, 3); \ >+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 10: \ >+ if (DecodeCOP3Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 11: \ >+ tmp = fieldname(insn, 5, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 12: \ >+ tmp = fieldname(insn, 0, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 13: \ >+ tmp = fieldname(insn, 0, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 14: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 15: \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 16: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 17: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 18: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 19: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 20: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 21: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 12, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 22: \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 23: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 24: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 25: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 26: \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 27: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 28: \ >+ if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 29: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 30: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 31: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 32: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 13, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 33: \ >+ if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 34: \ >+ if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 35: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 36: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 37: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 38: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 39: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 40: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 41: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 42: \ >+ tmp = fieldname(insn, 6, 20); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 43: \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 44: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 45: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 46: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 47: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 48: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ if (DecodeLSAImm(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 49: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 50: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 51: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 52: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 53: \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 54: \ >+ if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 55: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 56: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 57: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 58: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 59: \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 60: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 61: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 62: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 63: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 64: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 65: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 66: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 67: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 68: \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 69: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 70: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 71: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 72: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 73: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 74: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 75: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 76: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 77: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 78: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 79: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 80: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 81: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 82: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 83: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 84: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 85: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 86: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 87: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 88: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 89: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 90: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 91: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 92: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 93: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 94: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 5) << 0); \ >+ tmp |= (fieldname(insn, 16, 5) << 0); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 95: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 96: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 97: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 98: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 8); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 99: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 100: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 101: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 102: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 103: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 104: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 105: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 106: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 107: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 108: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 109: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 110: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 6); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 111: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 112: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 113: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 114: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 115: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 116: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 117: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 118: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 119: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 120: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 121: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 122: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 123: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 124: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 125: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 126: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 127: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 128: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 129: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 130: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 131: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 132: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 133: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 134: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 135: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 136: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 137: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 138: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 139: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 140: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 141: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 142: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 143: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 144: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 145: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 146: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 147: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 148: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 149: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 150: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 151: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 4); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 152: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 153: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 154: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 1); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 155: \ >+ if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 156: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 157: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 158: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 159: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 160: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 161: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 162: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 163: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 164: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 165: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 166: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 167: \ >+ if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 168: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 169: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 170: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 171: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 172: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 173: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 174: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 175: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 176: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 177: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 178: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 179: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 180: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 181: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 182: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 183: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 184: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 185: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 186: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 187: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 188: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 189: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 190: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 191: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 20, 6); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 192: \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 2); \ >+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 193: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 194: \ >+ if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 195: \ >+ if (DecodeCachePref(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 196: \ >+ if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 197: \ >+ if (DecodeCOP2Mem(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 198: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 199: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 200: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 2); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 201: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 202: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 203: \ >+ if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 204: \ >+ if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 205: \ >+ if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 206: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 207: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 208: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 209: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 210: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 211: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 212: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 213: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 214: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 215: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 0, 11) << 0); \ >+ tmp |= (fieldname(insn, 11, 5) << 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 216: \ >+ if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 217: \ >+ if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 218: \ >+ if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 219: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 220: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 221: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 222: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 7, 9) << 0); \ >+ tmp |= (fieldname(insn, 21, 5) << 16); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 16, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 223: \ >+ if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 224: \ >+ tmp = fieldname(insn, 0, 26); \ >+ if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 225: \ >+ if (DecodeSimm16(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 226: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 21); \ >+ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 227: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 19); \ >+ if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 228: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 18); \ >+ if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 229: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 230: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 231: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 232: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 233: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 3); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 234: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 235: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 236: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 237: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 18, 3); \ >+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 238: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 239: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 240: \ >+ tmp = fieldname(insn, 6, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 241: \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 242: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 0, 16); \ >+ if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 243: \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 244: \ >+ tmp = 0; \ >+ tmp |= (fieldname(insn, 11, 5) << 0); \ >+ tmp |= (fieldname(insn, 16, 5) << 0); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 245: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 10); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 246: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ return S; \ >+ case 247: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeExtSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ case 248: \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 21, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 6, 5); \ >+ MCOperand_CreateImm0(MI, tmp); \ >+ tmp = fieldname(insn, 11, 5); \ >+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ tmp = fieldname(insn, 16, 5); \ >+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ >+ return S; \ >+ } \ >+} >+ >+#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ >+static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ >+ InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ >+{ \ >+ uint64_t Bits = getFeatureBits(feature); \ >+ const uint8_t *Ptr = DecodeTable; \ >+ uint32_t CurFieldValue = 0, ExpectedValue; \ >+ DecodeStatus S = MCDisassembler_Success; \ >+ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ >+ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ >+ bool Pred, Fail; \ >+ for (;;) { \ >+ switch (*Ptr) { \ >+ default: \ >+ return MCDisassembler_Fail; \ >+ case MCD_OPC_ExtractField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ ++Ptr; \ >+ CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ >+ break; \ >+ } \ >+ case MCD_OPC_FilterValue: { \ >+ Val = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (Val != CurFieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckField: { \ >+ Start = *++Ptr; \ >+ Len = *++Ptr; \ >+ FieldValue = fieldname(insn, Start, Len); \ >+ ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ if (ExpectedValue != FieldValue) \ >+ Ptr += NumToSkip; \ >+ break; \ >+ } \ >+ case MCD_OPC_CheckPredicate: { \ >+ PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NumToSkip = *Ptr++; \ >+ NumToSkip |= (*Ptr++) << 8; \ >+ Pred = checkDecoderPredicate(PIdx, Bits); \ >+ if (!Pred) \ >+ Ptr += NumToSkip; \ >+ (void)Pred; \ >+ break; \ >+ } \ >+ case MCD_OPC_Decode: { \ >+ Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ MCInst_setOpcode(MI, Opc); \ >+ return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ >+ } \ >+ case MCD_OPC_SoftFail: { \ >+ PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ >+ Ptr += Len; \ >+ NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ >+ Ptr += Len; \ >+ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ >+ if (Fail) \ >+ S = MCDisassembler_SoftFail; \ >+ break; \ >+ } \ >+ case MCD_OPC_Fail: { \ >+ return MCDisassembler_Fail; \ >+ } \ >+ } \ >+ } \ >+} >+ >+FieldFromInstruction(fieldFromInstruction, uint32_t) >+DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) >+DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..947f360cc92865d2c24e0f1e2920327c4a575c57 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenInstrInfo.inc >@@ -0,0 +1,1730 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Instruction Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_INSTRINFO_ENUM >+#undef GET_INSTRINFO_ENUM >+ >+enum { >+ Mips_PHI = 0, >+ Mips_INLINEASM = 1, >+ Mips_CFI_INSTRUCTION = 2, >+ Mips_EH_LABEL = 3, >+ Mips_GC_LABEL = 4, >+ Mips_KILL = 5, >+ Mips_EXTRACT_SUBREG = 6, >+ Mips_INSERT_SUBREG = 7, >+ Mips_IMPLICIT_DEF = 8, >+ Mips_SUBREG_TO_REG = 9, >+ Mips_COPY_TO_REGCLASS = 10, >+ Mips_DBG_VALUE = 11, >+ Mips_REG_SEQUENCE = 12, >+ Mips_COPY = 13, >+ Mips_BUNDLE = 14, >+ Mips_LIFETIME_START = 15, >+ Mips_LIFETIME_END = 16, >+ Mips_STACKMAP = 17, >+ Mips_PATCHPOINT = 18, >+ Mips_LOAD_STACK_GUARD = 19, >+ Mips_ABSQ_S_PH = 20, >+ Mips_ABSQ_S_QB = 21, >+ Mips_ABSQ_S_W = 22, >+ Mips_ADD = 23, >+ Mips_ADDIUPC = 24, >+ Mips_ADDQH_PH = 25, >+ Mips_ADDQH_R_PH = 26, >+ Mips_ADDQH_R_W = 27, >+ Mips_ADDQH_W = 28, >+ Mips_ADDQ_PH = 29, >+ Mips_ADDQ_S_PH = 30, >+ Mips_ADDQ_S_W = 31, >+ Mips_ADDSC = 32, >+ Mips_ADDS_A_B = 33, >+ Mips_ADDS_A_D = 34, >+ Mips_ADDS_A_H = 35, >+ Mips_ADDS_A_W = 36, >+ Mips_ADDS_S_B = 37, >+ Mips_ADDS_S_D = 38, >+ Mips_ADDS_S_H = 39, >+ Mips_ADDS_S_W = 40, >+ Mips_ADDS_U_B = 41, >+ Mips_ADDS_U_D = 42, >+ Mips_ADDS_U_H = 43, >+ Mips_ADDS_U_W = 44, >+ Mips_ADDUH_QB = 45, >+ Mips_ADDUH_R_QB = 46, >+ Mips_ADDU_PH = 47, >+ Mips_ADDU_QB = 48, >+ Mips_ADDU_S_PH = 49, >+ Mips_ADDU_S_QB = 50, >+ Mips_ADDVI_B = 51, >+ Mips_ADDVI_D = 52, >+ Mips_ADDVI_H = 53, >+ Mips_ADDVI_W = 54, >+ Mips_ADDV_B = 55, >+ Mips_ADDV_D = 56, >+ Mips_ADDV_H = 57, >+ Mips_ADDV_W = 58, >+ Mips_ADDWC = 59, >+ Mips_ADD_A_B = 60, >+ Mips_ADD_A_D = 61, >+ Mips_ADD_A_H = 62, >+ Mips_ADD_A_W = 63, >+ Mips_ADD_MM = 64, >+ Mips_ADDi = 65, >+ Mips_ADDi_MM = 66, >+ Mips_ADDiu = 67, >+ Mips_ADDiu_MM = 68, >+ Mips_ADDu = 69, >+ Mips_ADDu_MM = 70, >+ Mips_ADJCALLSTACKDOWN = 71, >+ Mips_ADJCALLSTACKUP = 72, >+ Mips_ALIGN = 73, >+ Mips_ALUIPC = 74, >+ Mips_AND = 75, >+ Mips_AND64 = 76, >+ Mips_ANDI_B = 77, >+ Mips_AND_MM = 78, >+ Mips_AND_V = 79, >+ Mips_AND_V_D_PSEUDO = 80, >+ Mips_AND_V_H_PSEUDO = 81, >+ Mips_AND_V_W_PSEUDO = 82, >+ Mips_ANDi = 83, >+ Mips_ANDi64 = 84, >+ Mips_ANDi_MM = 85, >+ Mips_APPEND = 86, >+ Mips_ASUB_S_B = 87, >+ Mips_ASUB_S_D = 88, >+ Mips_ASUB_S_H = 89, >+ Mips_ASUB_S_W = 90, >+ Mips_ASUB_U_B = 91, >+ Mips_ASUB_U_D = 92, >+ Mips_ASUB_U_H = 93, >+ Mips_ASUB_U_W = 94, >+ Mips_ATOMIC_CMP_SWAP_I16 = 95, >+ Mips_ATOMIC_CMP_SWAP_I32 = 96, >+ Mips_ATOMIC_CMP_SWAP_I64 = 97, >+ Mips_ATOMIC_CMP_SWAP_I8 = 98, >+ Mips_ATOMIC_LOAD_ADD_I16 = 99, >+ Mips_ATOMIC_LOAD_ADD_I32 = 100, >+ Mips_ATOMIC_LOAD_ADD_I64 = 101, >+ Mips_ATOMIC_LOAD_ADD_I8 = 102, >+ Mips_ATOMIC_LOAD_AND_I16 = 103, >+ Mips_ATOMIC_LOAD_AND_I32 = 104, >+ Mips_ATOMIC_LOAD_AND_I64 = 105, >+ Mips_ATOMIC_LOAD_AND_I8 = 106, >+ Mips_ATOMIC_LOAD_NAND_I16 = 107, >+ Mips_ATOMIC_LOAD_NAND_I32 = 108, >+ Mips_ATOMIC_LOAD_NAND_I64 = 109, >+ Mips_ATOMIC_LOAD_NAND_I8 = 110, >+ Mips_ATOMIC_LOAD_OR_I16 = 111, >+ Mips_ATOMIC_LOAD_OR_I32 = 112, >+ Mips_ATOMIC_LOAD_OR_I64 = 113, >+ Mips_ATOMIC_LOAD_OR_I8 = 114, >+ Mips_ATOMIC_LOAD_SUB_I16 = 115, >+ Mips_ATOMIC_LOAD_SUB_I32 = 116, >+ Mips_ATOMIC_LOAD_SUB_I64 = 117, >+ Mips_ATOMIC_LOAD_SUB_I8 = 118, >+ Mips_ATOMIC_LOAD_XOR_I16 = 119, >+ Mips_ATOMIC_LOAD_XOR_I32 = 120, >+ Mips_ATOMIC_LOAD_XOR_I64 = 121, >+ Mips_ATOMIC_LOAD_XOR_I8 = 122, >+ Mips_ATOMIC_SWAP_I16 = 123, >+ Mips_ATOMIC_SWAP_I32 = 124, >+ Mips_ATOMIC_SWAP_I64 = 125, >+ Mips_ATOMIC_SWAP_I8 = 126, >+ Mips_AUI = 127, >+ Mips_AUIPC = 128, >+ Mips_AVER_S_B = 129, >+ Mips_AVER_S_D = 130, >+ Mips_AVER_S_H = 131, >+ Mips_AVER_S_W = 132, >+ Mips_AVER_U_B = 133, >+ Mips_AVER_U_D = 134, >+ Mips_AVER_U_H = 135, >+ Mips_AVER_U_W = 136, >+ Mips_AVE_S_B = 137, >+ Mips_AVE_S_D = 138, >+ Mips_AVE_S_H = 139, >+ Mips_AVE_S_W = 140, >+ Mips_AVE_U_B = 141, >+ Mips_AVE_U_D = 142, >+ Mips_AVE_U_H = 143, >+ Mips_AVE_U_W = 144, >+ Mips_AddiuRxImmX16 = 145, >+ Mips_AddiuRxPcImmX16 = 146, >+ Mips_AddiuRxRxImm16 = 147, >+ Mips_AddiuRxRxImmX16 = 148, >+ Mips_AddiuRxRyOffMemX16 = 149, >+ Mips_AddiuSpImm16 = 150, >+ Mips_AddiuSpImmX16 = 151, >+ Mips_AdduRxRyRz16 = 152, >+ Mips_AndRxRxRy16 = 153, >+ Mips_B = 154, >+ Mips_BADDu = 155, >+ Mips_BAL = 156, >+ Mips_BALC = 157, >+ Mips_BALIGN = 158, >+ Mips_BAL_BR = 159, >+ Mips_BC = 160, >+ Mips_BC0F = 161, >+ Mips_BC0FL = 162, >+ Mips_BC0T = 163, >+ Mips_BC0TL = 164, >+ Mips_BC1EQZ = 165, >+ Mips_BC1F = 166, >+ Mips_BC1FL = 167, >+ Mips_BC1F_MM = 168, >+ Mips_BC1NEZ = 169, >+ Mips_BC1T = 170, >+ Mips_BC1TL = 171, >+ Mips_BC1T_MM = 172, >+ Mips_BC2EQZ = 173, >+ Mips_BC2F = 174, >+ Mips_BC2FL = 175, >+ Mips_BC2NEZ = 176, >+ Mips_BC2T = 177, >+ Mips_BC2TL = 178, >+ Mips_BC3F = 179, >+ Mips_BC3FL = 180, >+ Mips_BC3T = 181, >+ Mips_BC3TL = 182, >+ Mips_BCLRI_B = 183, >+ Mips_BCLRI_D = 184, >+ Mips_BCLRI_H = 185, >+ Mips_BCLRI_W = 186, >+ Mips_BCLR_B = 187, >+ Mips_BCLR_D = 188, >+ Mips_BCLR_H = 189, >+ Mips_BCLR_W = 190, >+ Mips_BEQ = 191, >+ Mips_BEQ64 = 192, >+ Mips_BEQC = 193, >+ Mips_BEQL = 194, >+ Mips_BEQZALC = 195, >+ Mips_BEQZC = 196, >+ Mips_BEQZC_MM = 197, >+ Mips_BEQ_MM = 198, >+ Mips_BGEC = 199, >+ Mips_BGEUC = 200, >+ Mips_BGEZ = 201, >+ Mips_BGEZ64 = 202, >+ Mips_BGEZAL = 203, >+ Mips_BGEZALC = 204, >+ Mips_BGEZALL = 205, >+ Mips_BGEZALS_MM = 206, >+ Mips_BGEZAL_MM = 207, >+ Mips_BGEZC = 208, >+ Mips_BGEZL = 209, >+ Mips_BGEZ_MM = 210, >+ Mips_BGTZ = 211, >+ Mips_BGTZ64 = 212, >+ Mips_BGTZALC = 213, >+ Mips_BGTZC = 214, >+ Mips_BGTZL = 215, >+ Mips_BGTZ_MM = 216, >+ Mips_BINSLI_B = 217, >+ Mips_BINSLI_D = 218, >+ Mips_BINSLI_H = 219, >+ Mips_BINSLI_W = 220, >+ Mips_BINSL_B = 221, >+ Mips_BINSL_D = 222, >+ Mips_BINSL_H = 223, >+ Mips_BINSL_W = 224, >+ Mips_BINSRI_B = 225, >+ Mips_BINSRI_D = 226, >+ Mips_BINSRI_H = 227, >+ Mips_BINSRI_W = 228, >+ Mips_BINSR_B = 229, >+ Mips_BINSR_D = 230, >+ Mips_BINSR_H = 231, >+ Mips_BINSR_W = 232, >+ Mips_BITREV = 233, >+ Mips_BITSWAP = 234, >+ Mips_BLEZ = 235, >+ Mips_BLEZ64 = 236, >+ Mips_BLEZALC = 237, >+ Mips_BLEZC = 238, >+ Mips_BLEZL = 239, >+ Mips_BLEZ_MM = 240, >+ Mips_BLTC = 241, >+ Mips_BLTUC = 242, >+ Mips_BLTZ = 243, >+ Mips_BLTZ64 = 244, >+ Mips_BLTZAL = 245, >+ Mips_BLTZALC = 246, >+ Mips_BLTZALL = 247, >+ Mips_BLTZALS_MM = 248, >+ Mips_BLTZAL_MM = 249, >+ Mips_BLTZC = 250, >+ Mips_BLTZL = 251, >+ Mips_BLTZ_MM = 252, >+ Mips_BMNZI_B = 253, >+ Mips_BMNZ_V = 254, >+ Mips_BMZI_B = 255, >+ Mips_BMZ_V = 256, >+ Mips_BNE = 257, >+ Mips_BNE64 = 258, >+ Mips_BNEC = 259, >+ Mips_BNEGI_B = 260, >+ Mips_BNEGI_D = 261, >+ Mips_BNEGI_H = 262, >+ Mips_BNEGI_W = 263, >+ Mips_BNEG_B = 264, >+ Mips_BNEG_D = 265, >+ Mips_BNEG_H = 266, >+ Mips_BNEG_W = 267, >+ Mips_BNEL = 268, >+ Mips_BNEZALC = 269, >+ Mips_BNEZC = 270, >+ Mips_BNEZC_MM = 271, >+ Mips_BNE_MM = 272, >+ Mips_BNVC = 273, >+ Mips_BNZ_B = 274, >+ Mips_BNZ_D = 275, >+ Mips_BNZ_H = 276, >+ Mips_BNZ_V = 277, >+ Mips_BNZ_W = 278, >+ Mips_BOVC = 279, >+ Mips_BPOSGE32 = 280, >+ Mips_BPOSGE32_PSEUDO = 281, >+ Mips_BREAK = 282, >+ Mips_BREAK_MM = 283, >+ Mips_BSELI_B = 284, >+ Mips_BSEL_D_PSEUDO = 285, >+ Mips_BSEL_FD_PSEUDO = 286, >+ Mips_BSEL_FW_PSEUDO = 287, >+ Mips_BSEL_H_PSEUDO = 288, >+ Mips_BSEL_V = 289, >+ Mips_BSEL_W_PSEUDO = 290, >+ Mips_BSETI_B = 291, >+ Mips_BSETI_D = 292, >+ Mips_BSETI_H = 293, >+ Mips_BSETI_W = 294, >+ Mips_BSET_B = 295, >+ Mips_BSET_D = 296, >+ Mips_BSET_H = 297, >+ Mips_BSET_W = 298, >+ Mips_BZ_B = 299, >+ Mips_BZ_D = 300, >+ Mips_BZ_H = 301, >+ Mips_BZ_V = 302, >+ Mips_BZ_W = 303, >+ Mips_BeqzRxImm16 = 304, >+ Mips_BeqzRxImmX16 = 305, >+ Mips_Bimm16 = 306, >+ Mips_BimmX16 = 307, >+ Mips_BnezRxImm16 = 308, >+ Mips_BnezRxImmX16 = 309, >+ Mips_Break16 = 310, >+ Mips_Bteqz16 = 311, >+ Mips_BteqzT8CmpX16 = 312, >+ Mips_BteqzT8CmpiX16 = 313, >+ Mips_BteqzT8SltX16 = 314, >+ Mips_BteqzT8SltiX16 = 315, >+ Mips_BteqzT8SltiuX16 = 316, >+ Mips_BteqzT8SltuX16 = 317, >+ Mips_BteqzX16 = 318, >+ Mips_Btnez16 = 319, >+ Mips_BtnezT8CmpX16 = 320, >+ Mips_BtnezT8CmpiX16 = 321, >+ Mips_BtnezT8SltX16 = 322, >+ Mips_BtnezT8SltiX16 = 323, >+ Mips_BtnezT8SltiuX16 = 324, >+ Mips_BtnezT8SltuX16 = 325, >+ Mips_BtnezX16 = 326, >+ Mips_BuildPairF64 = 327, >+ Mips_BuildPairF64_64 = 328, >+ Mips_CACHE = 329, >+ Mips_CACHE_R6 = 330, >+ Mips_CEIL_L_D64 = 331, >+ Mips_CEIL_L_S = 332, >+ Mips_CEIL_W_D32 = 333, >+ Mips_CEIL_W_D64 = 334, >+ Mips_CEIL_W_MM = 335, >+ Mips_CEIL_W_S = 336, >+ Mips_CEIL_W_S_MM = 337, >+ Mips_CEQI_B = 338, >+ Mips_CEQI_D = 339, >+ Mips_CEQI_H = 340, >+ Mips_CEQI_W = 341, >+ Mips_CEQ_B = 342, >+ Mips_CEQ_D = 343, >+ Mips_CEQ_H = 344, >+ Mips_CEQ_W = 345, >+ Mips_CFC1 = 346, >+ Mips_CFC1_MM = 347, >+ Mips_CFCMSA = 348, >+ Mips_CINS = 349, >+ Mips_CINS32 = 350, >+ Mips_CLASS_D = 351, >+ Mips_CLASS_S = 352, >+ Mips_CLEI_S_B = 353, >+ Mips_CLEI_S_D = 354, >+ Mips_CLEI_S_H = 355, >+ Mips_CLEI_S_W = 356, >+ Mips_CLEI_U_B = 357, >+ Mips_CLEI_U_D = 358, >+ Mips_CLEI_U_H = 359, >+ Mips_CLEI_U_W = 360, >+ Mips_CLE_S_B = 361, >+ Mips_CLE_S_D = 362, >+ Mips_CLE_S_H = 363, >+ Mips_CLE_S_W = 364, >+ Mips_CLE_U_B = 365, >+ Mips_CLE_U_D = 366, >+ Mips_CLE_U_H = 367, >+ Mips_CLE_U_W = 368, >+ Mips_CLO = 369, >+ Mips_CLO_MM = 370, >+ Mips_CLO_R6 = 371, >+ Mips_CLTI_S_B = 372, >+ Mips_CLTI_S_D = 373, >+ Mips_CLTI_S_H = 374, >+ Mips_CLTI_S_W = 375, >+ Mips_CLTI_U_B = 376, >+ Mips_CLTI_U_D = 377, >+ Mips_CLTI_U_H = 378, >+ Mips_CLTI_U_W = 379, >+ Mips_CLT_S_B = 380, >+ Mips_CLT_S_D = 381, >+ Mips_CLT_S_H = 382, >+ Mips_CLT_S_W = 383, >+ Mips_CLT_U_B = 384, >+ Mips_CLT_U_D = 385, >+ Mips_CLT_U_H = 386, >+ Mips_CLT_U_W = 387, >+ Mips_CLZ = 388, >+ Mips_CLZ_MM = 389, >+ Mips_CLZ_R6 = 390, >+ Mips_CMPGDU_EQ_QB = 391, >+ Mips_CMPGDU_LE_QB = 392, >+ Mips_CMPGDU_LT_QB = 393, >+ Mips_CMPGU_EQ_QB = 394, >+ Mips_CMPGU_LE_QB = 395, >+ Mips_CMPGU_LT_QB = 396, >+ Mips_CMPU_EQ_QB = 397, >+ Mips_CMPU_LE_QB = 398, >+ Mips_CMPU_LT_QB = 399, >+ Mips_CMP_EQ_D = 400, >+ Mips_CMP_EQ_PH = 401, >+ Mips_CMP_EQ_S = 402, >+ Mips_CMP_F_D = 403, >+ Mips_CMP_F_S = 404, >+ Mips_CMP_LE_D = 405, >+ Mips_CMP_LE_PH = 406, >+ Mips_CMP_LE_S = 407, >+ Mips_CMP_LT_D = 408, >+ Mips_CMP_LT_PH = 409, >+ Mips_CMP_LT_S = 410, >+ Mips_CMP_SAF_D = 411, >+ Mips_CMP_SAF_S = 412, >+ Mips_CMP_SEQ_D = 413, >+ Mips_CMP_SEQ_S = 414, >+ Mips_CMP_SLE_D = 415, >+ Mips_CMP_SLE_S = 416, >+ Mips_CMP_SLT_D = 417, >+ Mips_CMP_SLT_S = 418, >+ Mips_CMP_SUEQ_D = 419, >+ Mips_CMP_SUEQ_S = 420, >+ Mips_CMP_SULE_D = 421, >+ Mips_CMP_SULE_S = 422, >+ Mips_CMP_SULT_D = 423, >+ Mips_CMP_SULT_S = 424, >+ Mips_CMP_SUN_D = 425, >+ Mips_CMP_SUN_S = 426, >+ Mips_CMP_UEQ_D = 427, >+ Mips_CMP_UEQ_S = 428, >+ Mips_CMP_ULE_D = 429, >+ Mips_CMP_ULE_S = 430, >+ Mips_CMP_ULT_D = 431, >+ Mips_CMP_ULT_S = 432, >+ Mips_CMP_UN_D = 433, >+ Mips_CMP_UN_S = 434, >+ Mips_CONSTPOOL_ENTRY = 435, >+ Mips_COPY_FD_PSEUDO = 436, >+ Mips_COPY_FW_PSEUDO = 437, >+ Mips_COPY_S_B = 438, >+ Mips_COPY_S_D = 439, >+ Mips_COPY_S_H = 440, >+ Mips_COPY_S_W = 441, >+ Mips_COPY_U_B = 442, >+ Mips_COPY_U_D = 443, >+ Mips_COPY_U_H = 444, >+ Mips_COPY_U_W = 445, >+ Mips_CTC1 = 446, >+ Mips_CTC1_MM = 447, >+ Mips_CTCMSA = 448, >+ Mips_CVT_D32_S = 449, >+ Mips_CVT_D32_W = 450, >+ Mips_CVT_D32_W_MM = 451, >+ Mips_CVT_D64_L = 452, >+ Mips_CVT_D64_S = 453, >+ Mips_CVT_D64_W = 454, >+ Mips_CVT_D_S_MM = 455, >+ Mips_CVT_L_D64 = 456, >+ Mips_CVT_L_D64_MM = 457, >+ Mips_CVT_L_S = 458, >+ Mips_CVT_L_S_MM = 459, >+ Mips_CVT_S_D32 = 460, >+ Mips_CVT_S_D32_MM = 461, >+ Mips_CVT_S_D64 = 462, >+ Mips_CVT_S_L = 463, >+ Mips_CVT_S_W = 464, >+ Mips_CVT_S_W_MM = 465, >+ Mips_CVT_W_D32 = 466, >+ Mips_CVT_W_D64 = 467, >+ Mips_CVT_W_MM = 468, >+ Mips_CVT_W_S = 469, >+ Mips_CVT_W_S_MM = 470, >+ Mips_C_EQ_D32 = 471, >+ Mips_C_EQ_D64 = 472, >+ Mips_C_EQ_S = 473, >+ Mips_C_F_D32 = 474, >+ Mips_C_F_D64 = 475, >+ Mips_C_F_S = 476, >+ Mips_C_LE_D32 = 477, >+ Mips_C_LE_D64 = 478, >+ Mips_C_LE_S = 479, >+ Mips_C_LT_D32 = 480, >+ Mips_C_LT_D64 = 481, >+ Mips_C_LT_S = 482, >+ Mips_C_NGE_D32 = 483, >+ Mips_C_NGE_D64 = 484, >+ Mips_C_NGE_S = 485, >+ Mips_C_NGLE_D32 = 486, >+ Mips_C_NGLE_D64 = 487, >+ Mips_C_NGLE_S = 488, >+ Mips_C_NGL_D32 = 489, >+ Mips_C_NGL_D64 = 490, >+ Mips_C_NGL_S = 491, >+ Mips_C_NGT_D32 = 492, >+ Mips_C_NGT_D64 = 493, >+ Mips_C_NGT_S = 494, >+ Mips_C_OLE_D32 = 495, >+ Mips_C_OLE_D64 = 496, >+ Mips_C_OLE_S = 497, >+ Mips_C_OLT_D32 = 498, >+ Mips_C_OLT_D64 = 499, >+ Mips_C_OLT_S = 500, >+ Mips_C_SEQ_D32 = 501, >+ Mips_C_SEQ_D64 = 502, >+ Mips_C_SEQ_S = 503, >+ Mips_C_SF_D32 = 504, >+ Mips_C_SF_D64 = 505, >+ Mips_C_SF_S = 506, >+ Mips_C_UEQ_D32 = 507, >+ Mips_C_UEQ_D64 = 508, >+ Mips_C_UEQ_S = 509, >+ Mips_C_ULE_D32 = 510, >+ Mips_C_ULE_D64 = 511, >+ Mips_C_ULE_S = 512, >+ Mips_C_ULT_D32 = 513, >+ Mips_C_ULT_D64 = 514, >+ Mips_C_ULT_S = 515, >+ Mips_C_UN_D32 = 516, >+ Mips_C_UN_D64 = 517, >+ Mips_C_UN_S = 518, >+ Mips_CmpRxRy16 = 519, >+ Mips_CmpiRxImm16 = 520, >+ Mips_CmpiRxImmX16 = 521, >+ Mips_Constant32 = 522, >+ Mips_DADD = 523, >+ Mips_DADDi = 524, >+ Mips_DADDiu = 525, >+ Mips_DADDu = 526, >+ Mips_DAHI = 527, >+ Mips_DALIGN = 528, >+ Mips_DATI = 529, >+ Mips_DAUI = 530, >+ Mips_DBITSWAP = 531, >+ Mips_DCLO = 532, >+ Mips_DCLO_R6 = 533, >+ Mips_DCLZ = 534, >+ Mips_DCLZ_R6 = 535, >+ Mips_DDIV = 536, >+ Mips_DDIVU = 537, >+ Mips_DERET = 538, >+ Mips_DERET_MM = 539, >+ Mips_DEXT = 540, >+ Mips_DEXTM = 541, >+ Mips_DEXTU = 542, >+ Mips_DI = 543, >+ Mips_DINS = 544, >+ Mips_DINSM = 545, >+ Mips_DINSU = 546, >+ Mips_DIV = 547, >+ Mips_DIVU = 548, >+ Mips_DIV_S_B = 549, >+ Mips_DIV_S_D = 550, >+ Mips_DIV_S_H = 551, >+ Mips_DIV_S_W = 552, >+ Mips_DIV_U_B = 553, >+ Mips_DIV_U_D = 554, >+ Mips_DIV_U_H = 555, >+ Mips_DIV_U_W = 556, >+ Mips_DI_MM = 557, >+ Mips_DLSA = 558, >+ Mips_DLSA_R6 = 559, >+ Mips_DMFC0 = 560, >+ Mips_DMFC1 = 561, >+ Mips_DMFC2 = 562, >+ Mips_DMOD = 563, >+ Mips_DMODU = 564, >+ Mips_DMTC0 = 565, >+ Mips_DMTC1 = 566, >+ Mips_DMTC2 = 567, >+ Mips_DMUH = 568, >+ Mips_DMUHU = 569, >+ Mips_DMUL = 570, >+ Mips_DMULT = 571, >+ Mips_DMULTu = 572, >+ Mips_DMULU = 573, >+ Mips_DMUL_R6 = 574, >+ Mips_DOTP_S_D = 575, >+ Mips_DOTP_S_H = 576, >+ Mips_DOTP_S_W = 577, >+ Mips_DOTP_U_D = 578, >+ Mips_DOTP_U_H = 579, >+ Mips_DOTP_U_W = 580, >+ Mips_DPADD_S_D = 581, >+ Mips_DPADD_S_H = 582, >+ Mips_DPADD_S_W = 583, >+ Mips_DPADD_U_D = 584, >+ Mips_DPADD_U_H = 585, >+ Mips_DPADD_U_W = 586, >+ Mips_DPAQX_SA_W_PH = 587, >+ Mips_DPAQX_S_W_PH = 588, >+ Mips_DPAQ_SA_L_W = 589, >+ Mips_DPAQ_S_W_PH = 590, >+ Mips_DPAU_H_QBL = 591, >+ Mips_DPAU_H_QBR = 592, >+ Mips_DPAX_W_PH = 593, >+ Mips_DPA_W_PH = 594, >+ Mips_DPOP = 595, >+ Mips_DPSQX_SA_W_PH = 596, >+ Mips_DPSQX_S_W_PH = 597, >+ Mips_DPSQ_SA_L_W = 598, >+ Mips_DPSQ_S_W_PH = 599, >+ Mips_DPSUB_S_D = 600, >+ Mips_DPSUB_S_H = 601, >+ Mips_DPSUB_S_W = 602, >+ Mips_DPSUB_U_D = 603, >+ Mips_DPSUB_U_H = 604, >+ Mips_DPSUB_U_W = 605, >+ Mips_DPSU_H_QBL = 606, >+ Mips_DPSU_H_QBR = 607, >+ Mips_DPSX_W_PH = 608, >+ Mips_DPS_W_PH = 609, >+ Mips_DROTR = 610, >+ Mips_DROTR32 = 611, >+ Mips_DROTRV = 612, >+ Mips_DSBH = 613, >+ Mips_DSDIV = 614, >+ Mips_DSHD = 615, >+ Mips_DSLL = 616, >+ Mips_DSLL32 = 617, >+ Mips_DSLL64_32 = 618, >+ Mips_DSLLV = 619, >+ Mips_DSRA = 620, >+ Mips_DSRA32 = 621, >+ Mips_DSRAV = 622, >+ Mips_DSRL = 623, >+ Mips_DSRL32 = 624, >+ Mips_DSRLV = 625, >+ Mips_DSUB = 626, >+ Mips_DSUBu = 627, >+ Mips_DUDIV = 628, >+ Mips_DivRxRy16 = 629, >+ Mips_DivuRxRy16 = 630, >+ Mips_EHB = 631, >+ Mips_EI = 632, >+ Mips_EI_MM = 633, >+ Mips_ERET = 634, >+ Mips_ERET_MM = 635, >+ Mips_EXT = 636, >+ Mips_EXTP = 637, >+ Mips_EXTPDP = 638, >+ Mips_EXTPDPV = 639, >+ Mips_EXTPV = 640, >+ Mips_EXTRV_RS_W = 641, >+ Mips_EXTRV_R_W = 642, >+ Mips_EXTRV_S_H = 643, >+ Mips_EXTRV_W = 644, >+ Mips_EXTR_RS_W = 645, >+ Mips_EXTR_R_W = 646, >+ Mips_EXTR_S_H = 647, >+ Mips_EXTR_W = 648, >+ Mips_EXTS = 649, >+ Mips_EXTS32 = 650, >+ Mips_EXT_MM = 651, >+ Mips_ExtractElementF64 = 652, >+ Mips_ExtractElementF64_64 = 653, >+ Mips_FABS_D = 654, >+ Mips_FABS_D32 = 655, >+ Mips_FABS_D64 = 656, >+ Mips_FABS_MM = 657, >+ Mips_FABS_S = 658, >+ Mips_FABS_S_MM = 659, >+ Mips_FABS_W = 660, >+ Mips_FADD_D = 661, >+ Mips_FADD_D32 = 662, >+ Mips_FADD_D64 = 663, >+ Mips_FADD_MM = 664, >+ Mips_FADD_S = 665, >+ Mips_FADD_S_MM = 666, >+ Mips_FADD_W = 667, >+ Mips_FCAF_D = 668, >+ Mips_FCAF_W = 669, >+ Mips_FCEQ_D = 670, >+ Mips_FCEQ_W = 671, >+ Mips_FCLASS_D = 672, >+ Mips_FCLASS_W = 673, >+ Mips_FCLE_D = 674, >+ Mips_FCLE_W = 675, >+ Mips_FCLT_D = 676, >+ Mips_FCLT_W = 677, >+ Mips_FCMP_D32 = 678, >+ Mips_FCMP_D32_MM = 679, >+ Mips_FCMP_D64 = 680, >+ Mips_FCMP_S32 = 681, >+ Mips_FCMP_S32_MM = 682, >+ Mips_FCNE_D = 683, >+ Mips_FCNE_W = 684, >+ Mips_FCOR_D = 685, >+ Mips_FCOR_W = 686, >+ Mips_FCUEQ_D = 687, >+ Mips_FCUEQ_W = 688, >+ Mips_FCULE_D = 689, >+ Mips_FCULE_W = 690, >+ Mips_FCULT_D = 691, >+ Mips_FCULT_W = 692, >+ Mips_FCUNE_D = 693, >+ Mips_FCUNE_W = 694, >+ Mips_FCUN_D = 695, >+ Mips_FCUN_W = 696, >+ Mips_FDIV_D = 697, >+ Mips_FDIV_D32 = 698, >+ Mips_FDIV_D64 = 699, >+ Mips_FDIV_MM = 700, >+ Mips_FDIV_S = 701, >+ Mips_FDIV_S_MM = 702, >+ Mips_FDIV_W = 703, >+ Mips_FEXDO_H = 704, >+ Mips_FEXDO_W = 705, >+ Mips_FEXP2_D = 706, >+ Mips_FEXP2_D_1_PSEUDO = 707, >+ Mips_FEXP2_W = 708, >+ Mips_FEXP2_W_1_PSEUDO = 709, >+ Mips_FEXUPL_D = 710, >+ Mips_FEXUPL_W = 711, >+ Mips_FEXUPR_D = 712, >+ Mips_FEXUPR_W = 713, >+ Mips_FFINT_S_D = 714, >+ Mips_FFINT_S_W = 715, >+ Mips_FFINT_U_D = 716, >+ Mips_FFINT_U_W = 717, >+ Mips_FFQL_D = 718, >+ Mips_FFQL_W = 719, >+ Mips_FFQR_D = 720, >+ Mips_FFQR_W = 721, >+ Mips_FILL_B = 722, >+ Mips_FILL_D = 723, >+ Mips_FILL_FD_PSEUDO = 724, >+ Mips_FILL_FW_PSEUDO = 725, >+ Mips_FILL_H = 726, >+ Mips_FILL_W = 727, >+ Mips_FLOG2_D = 728, >+ Mips_FLOG2_W = 729, >+ Mips_FLOOR_L_D64 = 730, >+ Mips_FLOOR_L_S = 731, >+ Mips_FLOOR_W_D32 = 732, >+ Mips_FLOOR_W_D64 = 733, >+ Mips_FLOOR_W_MM = 734, >+ Mips_FLOOR_W_S = 735, >+ Mips_FLOOR_W_S_MM = 736, >+ Mips_FMADD_D = 737, >+ Mips_FMADD_W = 738, >+ Mips_FMAX_A_D = 739, >+ Mips_FMAX_A_W = 740, >+ Mips_FMAX_D = 741, >+ Mips_FMAX_W = 742, >+ Mips_FMIN_A_D = 743, >+ Mips_FMIN_A_W = 744, >+ Mips_FMIN_D = 745, >+ Mips_FMIN_W = 746, >+ Mips_FMOV_D32 = 747, >+ Mips_FMOV_D32_MM = 748, >+ Mips_FMOV_D64 = 749, >+ Mips_FMOV_S = 750, >+ Mips_FMOV_S_MM = 751, >+ Mips_FMSUB_D = 752, >+ Mips_FMSUB_W = 753, >+ Mips_FMUL_D = 754, >+ Mips_FMUL_D32 = 755, >+ Mips_FMUL_D64 = 756, >+ Mips_FMUL_MM = 757, >+ Mips_FMUL_S = 758, >+ Mips_FMUL_S_MM = 759, >+ Mips_FMUL_W = 760, >+ Mips_FNEG_D32 = 761, >+ Mips_FNEG_D64 = 762, >+ Mips_FNEG_MM = 763, >+ Mips_FNEG_S = 764, >+ Mips_FNEG_S_MM = 765, >+ Mips_FRCP_D = 766, >+ Mips_FRCP_W = 767, >+ Mips_FRINT_D = 768, >+ Mips_FRINT_W = 769, >+ Mips_FRSQRT_D = 770, >+ Mips_FRSQRT_W = 771, >+ Mips_FSAF_D = 772, >+ Mips_FSAF_W = 773, >+ Mips_FSEQ_D = 774, >+ Mips_FSEQ_W = 775, >+ Mips_FSLE_D = 776, >+ Mips_FSLE_W = 777, >+ Mips_FSLT_D = 778, >+ Mips_FSLT_W = 779, >+ Mips_FSNE_D = 780, >+ Mips_FSNE_W = 781, >+ Mips_FSOR_D = 782, >+ Mips_FSOR_W = 783, >+ Mips_FSQRT_D = 784, >+ Mips_FSQRT_D32 = 785, >+ Mips_FSQRT_D64 = 786, >+ Mips_FSQRT_MM = 787, >+ Mips_FSQRT_S = 788, >+ Mips_FSQRT_S_MM = 789, >+ Mips_FSQRT_W = 790, >+ Mips_FSUB_D = 791, >+ Mips_FSUB_D32 = 792, >+ Mips_FSUB_D64 = 793, >+ Mips_FSUB_MM = 794, >+ Mips_FSUB_S = 795, >+ Mips_FSUB_S_MM = 796, >+ Mips_FSUB_W = 797, >+ Mips_FSUEQ_D = 798, >+ Mips_FSUEQ_W = 799, >+ Mips_FSULE_D = 800, >+ Mips_FSULE_W = 801, >+ Mips_FSULT_D = 802, >+ Mips_FSULT_W = 803, >+ Mips_FSUNE_D = 804, >+ Mips_FSUNE_W = 805, >+ Mips_FSUN_D = 806, >+ Mips_FSUN_W = 807, >+ Mips_FTINT_S_D = 808, >+ Mips_FTINT_S_W = 809, >+ Mips_FTINT_U_D = 810, >+ Mips_FTINT_U_W = 811, >+ Mips_FTQ_H = 812, >+ Mips_FTQ_W = 813, >+ Mips_FTRUNC_S_D = 814, >+ Mips_FTRUNC_S_W = 815, >+ Mips_FTRUNC_U_D = 816, >+ Mips_FTRUNC_U_W = 817, >+ Mips_GotPrologue16 = 818, >+ Mips_HADD_S_D = 819, >+ Mips_HADD_S_H = 820, >+ Mips_HADD_S_W = 821, >+ Mips_HADD_U_D = 822, >+ Mips_HADD_U_H = 823, >+ Mips_HADD_U_W = 824, >+ Mips_HSUB_S_D = 825, >+ Mips_HSUB_S_H = 826, >+ Mips_HSUB_S_W = 827, >+ Mips_HSUB_U_D = 828, >+ Mips_HSUB_U_H = 829, >+ Mips_HSUB_U_W = 830, >+ Mips_ILVEV_B = 831, >+ Mips_ILVEV_D = 832, >+ Mips_ILVEV_H = 833, >+ Mips_ILVEV_W = 834, >+ Mips_ILVL_B = 835, >+ Mips_ILVL_D = 836, >+ Mips_ILVL_H = 837, >+ Mips_ILVL_W = 838, >+ Mips_ILVOD_B = 839, >+ Mips_ILVOD_D = 840, >+ Mips_ILVOD_H = 841, >+ Mips_ILVOD_W = 842, >+ Mips_ILVR_B = 843, >+ Mips_ILVR_D = 844, >+ Mips_ILVR_H = 845, >+ Mips_ILVR_W = 846, >+ Mips_INS = 847, >+ Mips_INSERT_B = 848, >+ Mips_INSERT_B_VIDX_PSEUDO = 849, >+ Mips_INSERT_D = 850, >+ Mips_INSERT_D_VIDX_PSEUDO = 851, >+ Mips_INSERT_FD_PSEUDO = 852, >+ Mips_INSERT_FD_VIDX_PSEUDO = 853, >+ Mips_INSERT_FW_PSEUDO = 854, >+ Mips_INSERT_FW_VIDX_PSEUDO = 855, >+ Mips_INSERT_H = 856, >+ Mips_INSERT_H_VIDX_PSEUDO = 857, >+ Mips_INSERT_W = 858, >+ Mips_INSERT_W_VIDX_PSEUDO = 859, >+ Mips_INSV = 860, >+ Mips_INSVE_B = 861, >+ Mips_INSVE_D = 862, >+ Mips_INSVE_H = 863, >+ Mips_INSVE_W = 864, >+ Mips_INS_MM = 865, >+ Mips_J = 866, >+ Mips_JAL = 867, >+ Mips_JALR = 868, >+ Mips_JALR16_MM = 869, >+ Mips_JALR64 = 870, >+ Mips_JALR64Pseudo = 871, >+ Mips_JALRPseudo = 872, >+ Mips_JALRS_MM = 873, >+ Mips_JALR_HB = 874, >+ Mips_JALR_MM = 875, >+ Mips_JALS_MM = 876, >+ Mips_JALX = 877, >+ Mips_JAL_MM = 878, >+ Mips_JIALC = 879, >+ Mips_JIC = 880, >+ Mips_JR = 881, >+ Mips_JR64 = 882, >+ Mips_JRADDIUSP = 883, >+ Mips_JR_HB = 884, >+ Mips_JR_HB_R6 = 885, >+ Mips_JR_MM = 886, >+ Mips_J_MM = 887, >+ Mips_Jal16 = 888, >+ Mips_JalB16 = 889, >+ Mips_JrRa16 = 890, >+ Mips_JrcRa16 = 891, >+ Mips_JrcRx16 = 892, >+ Mips_JumpLinkReg16 = 893, >+ Mips_LB = 894, >+ Mips_LB64 = 895, >+ Mips_LBUX = 896, >+ Mips_LB_MM = 897, >+ Mips_LBu = 898, >+ Mips_LBu64 = 899, >+ Mips_LBu_MM = 900, >+ Mips_LD = 901, >+ Mips_LDC1 = 902, >+ Mips_LDC164 = 903, >+ Mips_LDC1_MM = 904, >+ Mips_LDC2 = 905, >+ Mips_LDC2_R6 = 906, >+ Mips_LDC3 = 907, >+ Mips_LDI_B = 908, >+ Mips_LDI_D = 909, >+ Mips_LDI_H = 910, >+ Mips_LDI_W = 911, >+ Mips_LDL = 912, >+ Mips_LDPC = 913, >+ Mips_LDR = 914, >+ Mips_LDXC1 = 915, >+ Mips_LDXC164 = 916, >+ Mips_LD_B = 917, >+ Mips_LD_D = 918, >+ Mips_LD_H = 919, >+ Mips_LD_W = 920, >+ Mips_LEA_ADDiu = 921, >+ Mips_LEA_ADDiu64 = 922, >+ Mips_LEA_ADDiu_MM = 923, >+ Mips_LH = 924, >+ Mips_LH64 = 925, >+ Mips_LHX = 926, >+ Mips_LH_MM = 927, >+ Mips_LHu = 928, >+ Mips_LHu64 = 929, >+ Mips_LHu_MM = 930, >+ Mips_LL = 931, >+ Mips_LLD = 932, >+ Mips_LLD_R6 = 933, >+ Mips_LL_MM = 934, >+ Mips_LL_R6 = 935, >+ Mips_LOAD_ACC128 = 936, >+ Mips_LOAD_ACC64 = 937, >+ Mips_LOAD_ACC64DSP = 938, >+ Mips_LOAD_CCOND_DSP = 939, >+ Mips_LONG_BRANCH_ADDiu = 940, >+ Mips_LONG_BRANCH_DADDiu = 941, >+ Mips_LONG_BRANCH_LUi = 942, >+ Mips_LSA = 943, >+ Mips_LSA_R6 = 944, >+ Mips_LUXC1 = 945, >+ Mips_LUXC164 = 946, >+ Mips_LUXC1_MM = 947, >+ Mips_LUi = 948, >+ Mips_LUi64 = 949, >+ Mips_LUi_MM = 950, >+ Mips_LW = 951, >+ Mips_LW64 = 952, >+ Mips_LWC1 = 953, >+ Mips_LWC1_MM = 954, >+ Mips_LWC2 = 955, >+ Mips_LWC2_R6 = 956, >+ Mips_LWC3 = 957, >+ Mips_LWL = 958, >+ Mips_LWL64 = 959, >+ Mips_LWL_MM = 960, >+ Mips_LWPC = 961, >+ Mips_LWR = 962, >+ Mips_LWR64 = 963, >+ Mips_LWR_MM = 964, >+ Mips_LWUPC = 965, >+ Mips_LWU_MM = 966, >+ Mips_LWX = 967, >+ Mips_LWXC1 = 968, >+ Mips_LWXC1_MM = 969, >+ Mips_LW_MM = 970, >+ Mips_LWu = 971, >+ Mips_LbRxRyOffMemX16 = 972, >+ Mips_LbuRxRyOffMemX16 = 973, >+ Mips_LhRxRyOffMemX16 = 974, >+ Mips_LhuRxRyOffMemX16 = 975, >+ Mips_LiRxImm16 = 976, >+ Mips_LiRxImmAlignX16 = 977, >+ Mips_LiRxImmX16 = 978, >+ Mips_LoadAddr32Imm = 979, >+ Mips_LoadAddr32Reg = 980, >+ Mips_LoadImm32Reg = 981, >+ Mips_LoadImm64Reg = 982, >+ Mips_LwConstant32 = 983, >+ Mips_LwRxPcTcp16 = 984, >+ Mips_LwRxPcTcpX16 = 985, >+ Mips_LwRxRyOffMemX16 = 986, >+ Mips_LwRxSpImmX16 = 987, >+ Mips_MADD = 988, >+ Mips_MADDF_D = 989, >+ Mips_MADDF_S = 990, >+ Mips_MADDR_Q_H = 991, >+ Mips_MADDR_Q_W = 992, >+ Mips_MADDU = 993, >+ Mips_MADDU_DSP = 994, >+ Mips_MADDU_MM = 995, >+ Mips_MADDV_B = 996, >+ Mips_MADDV_D = 997, >+ Mips_MADDV_H = 998, >+ Mips_MADDV_W = 999, >+ Mips_MADD_D32 = 1000, >+ Mips_MADD_D32_MM = 1001, >+ Mips_MADD_D64 = 1002, >+ Mips_MADD_DSP = 1003, >+ Mips_MADD_MM = 1004, >+ Mips_MADD_Q_H = 1005, >+ Mips_MADD_Q_W = 1006, >+ Mips_MADD_S = 1007, >+ Mips_MADD_S_MM = 1008, >+ Mips_MAQ_SA_W_PHL = 1009, >+ Mips_MAQ_SA_W_PHR = 1010, >+ Mips_MAQ_S_W_PHL = 1011, >+ Mips_MAQ_S_W_PHR = 1012, >+ Mips_MAXA_D = 1013, >+ Mips_MAXA_S = 1014, >+ Mips_MAXI_S_B = 1015, >+ Mips_MAXI_S_D = 1016, >+ Mips_MAXI_S_H = 1017, >+ Mips_MAXI_S_W = 1018, >+ Mips_MAXI_U_B = 1019, >+ Mips_MAXI_U_D = 1020, >+ Mips_MAXI_U_H = 1021, >+ Mips_MAXI_U_W = 1022, >+ Mips_MAX_A_B = 1023, >+ Mips_MAX_A_D = 1024, >+ Mips_MAX_A_H = 1025, >+ Mips_MAX_A_W = 1026, >+ Mips_MAX_D = 1027, >+ Mips_MAX_S = 1028, >+ Mips_MAX_S_B = 1029, >+ Mips_MAX_S_D = 1030, >+ Mips_MAX_S_H = 1031, >+ Mips_MAX_S_W = 1032, >+ Mips_MAX_U_B = 1033, >+ Mips_MAX_U_D = 1034, >+ Mips_MAX_U_H = 1035, >+ Mips_MAX_U_W = 1036, >+ Mips_MFC0 = 1037, >+ Mips_MFC1 = 1038, >+ Mips_MFC1_MM = 1039, >+ Mips_MFC2 = 1040, >+ Mips_MFHC1_D32 = 1041, >+ Mips_MFHC1_D64 = 1042, >+ Mips_MFHC1_MM = 1043, >+ Mips_MFHI = 1044, >+ Mips_MFHI16_MM = 1045, >+ Mips_MFHI64 = 1046, >+ Mips_MFHI_DSP = 1047, >+ Mips_MFHI_MM = 1048, >+ Mips_MFLO = 1049, >+ Mips_MFLO16_MM = 1050, >+ Mips_MFLO64 = 1051, >+ Mips_MFLO_DSP = 1052, >+ Mips_MFLO_MM = 1053, >+ Mips_MINA_D = 1054, >+ Mips_MINA_S = 1055, >+ Mips_MINI_S_B = 1056, >+ Mips_MINI_S_D = 1057, >+ Mips_MINI_S_H = 1058, >+ Mips_MINI_S_W = 1059, >+ Mips_MINI_U_B = 1060, >+ Mips_MINI_U_D = 1061, >+ Mips_MINI_U_H = 1062, >+ Mips_MINI_U_W = 1063, >+ Mips_MIN_A_B = 1064, >+ Mips_MIN_A_D = 1065, >+ Mips_MIN_A_H = 1066, >+ Mips_MIN_A_W = 1067, >+ Mips_MIN_D = 1068, >+ Mips_MIN_S = 1069, >+ Mips_MIN_S_B = 1070, >+ Mips_MIN_S_D = 1071, >+ Mips_MIN_S_H = 1072, >+ Mips_MIN_S_W = 1073, >+ Mips_MIN_U_B = 1074, >+ Mips_MIN_U_D = 1075, >+ Mips_MIN_U_H = 1076, >+ Mips_MIN_U_W = 1077, >+ Mips_MIPSeh_return32 = 1078, >+ Mips_MIPSeh_return64 = 1079, >+ Mips_MOD = 1080, >+ Mips_MODSUB = 1081, >+ Mips_MODU = 1082, >+ Mips_MOD_S_B = 1083, >+ Mips_MOD_S_D = 1084, >+ Mips_MOD_S_H = 1085, >+ Mips_MOD_S_W = 1086, >+ Mips_MOD_U_B = 1087, >+ Mips_MOD_U_D = 1088, >+ Mips_MOD_U_H = 1089, >+ Mips_MOD_U_W = 1090, >+ Mips_MOVE16_MM = 1091, >+ Mips_MOVE_V = 1092, >+ Mips_MOVF_D32 = 1093, >+ Mips_MOVF_D32_MM = 1094, >+ Mips_MOVF_D64 = 1095, >+ Mips_MOVF_I = 1096, >+ Mips_MOVF_I64 = 1097, >+ Mips_MOVF_I_MM = 1098, >+ Mips_MOVF_S = 1099, >+ Mips_MOVF_S_MM = 1100, >+ Mips_MOVN_I64_D64 = 1101, >+ Mips_MOVN_I64_I = 1102, >+ Mips_MOVN_I64_I64 = 1103, >+ Mips_MOVN_I64_S = 1104, >+ Mips_MOVN_I_D32 = 1105, >+ Mips_MOVN_I_D32_MM = 1106, >+ Mips_MOVN_I_D64 = 1107, >+ Mips_MOVN_I_I = 1108, >+ Mips_MOVN_I_I64 = 1109, >+ Mips_MOVN_I_MM = 1110, >+ Mips_MOVN_I_S = 1111, >+ Mips_MOVN_I_S_MM = 1112, >+ Mips_MOVT_D32 = 1113, >+ Mips_MOVT_D32_MM = 1114, >+ Mips_MOVT_D64 = 1115, >+ Mips_MOVT_I = 1116, >+ Mips_MOVT_I64 = 1117, >+ Mips_MOVT_I_MM = 1118, >+ Mips_MOVT_S = 1119, >+ Mips_MOVT_S_MM = 1120, >+ Mips_MOVZ_I64_D64 = 1121, >+ Mips_MOVZ_I64_I = 1122, >+ Mips_MOVZ_I64_I64 = 1123, >+ Mips_MOVZ_I64_S = 1124, >+ Mips_MOVZ_I_D32 = 1125, >+ Mips_MOVZ_I_D32_MM = 1126, >+ Mips_MOVZ_I_D64 = 1127, >+ Mips_MOVZ_I_I = 1128, >+ Mips_MOVZ_I_I64 = 1129, >+ Mips_MOVZ_I_MM = 1130, >+ Mips_MOVZ_I_S = 1131, >+ Mips_MOVZ_I_S_MM = 1132, >+ Mips_MSUB = 1133, >+ Mips_MSUBF_D = 1134, >+ Mips_MSUBF_S = 1135, >+ Mips_MSUBR_Q_H = 1136, >+ Mips_MSUBR_Q_W = 1137, >+ Mips_MSUBU = 1138, >+ Mips_MSUBU_DSP = 1139, >+ Mips_MSUBU_MM = 1140, >+ Mips_MSUBV_B = 1141, >+ Mips_MSUBV_D = 1142, >+ Mips_MSUBV_H = 1143, >+ Mips_MSUBV_W = 1144, >+ Mips_MSUB_D32 = 1145, >+ Mips_MSUB_D32_MM = 1146, >+ Mips_MSUB_D64 = 1147, >+ Mips_MSUB_DSP = 1148, >+ Mips_MSUB_MM = 1149, >+ Mips_MSUB_Q_H = 1150, >+ Mips_MSUB_Q_W = 1151, >+ Mips_MSUB_S = 1152, >+ Mips_MSUB_S_MM = 1153, >+ Mips_MTC0 = 1154, >+ Mips_MTC1 = 1155, >+ Mips_MTC1_MM = 1156, >+ Mips_MTC2 = 1157, >+ Mips_MTHC1_D32 = 1158, >+ Mips_MTHC1_D64 = 1159, >+ Mips_MTHC1_MM = 1160, >+ Mips_MTHI = 1161, >+ Mips_MTHI64 = 1162, >+ Mips_MTHI_DSP = 1163, >+ Mips_MTHI_MM = 1164, >+ Mips_MTHLIP = 1165, >+ Mips_MTLO = 1166, >+ Mips_MTLO64 = 1167, >+ Mips_MTLO_DSP = 1168, >+ Mips_MTLO_MM = 1169, >+ Mips_MTM0 = 1170, >+ Mips_MTM1 = 1171, >+ Mips_MTM2 = 1172, >+ Mips_MTP0 = 1173, >+ Mips_MTP1 = 1174, >+ Mips_MTP2 = 1175, >+ Mips_MUH = 1176, >+ Mips_MUHU = 1177, >+ Mips_MUL = 1178, >+ Mips_MULEQ_S_W_PHL = 1179, >+ Mips_MULEQ_S_W_PHR = 1180, >+ Mips_MULEU_S_PH_QBL = 1181, >+ Mips_MULEU_S_PH_QBR = 1182, >+ Mips_MULQ_RS_PH = 1183, >+ Mips_MULQ_RS_W = 1184, >+ Mips_MULQ_S_PH = 1185, >+ Mips_MULQ_S_W = 1186, >+ Mips_MULR_Q_H = 1187, >+ Mips_MULR_Q_W = 1188, >+ Mips_MULSAQ_S_W_PH = 1189, >+ Mips_MULSA_W_PH = 1190, >+ Mips_MULT = 1191, >+ Mips_MULTU_DSP = 1192, >+ Mips_MULT_DSP = 1193, >+ Mips_MULT_MM = 1194, >+ Mips_MULTu = 1195, >+ Mips_MULTu_MM = 1196, >+ Mips_MULU = 1197, >+ Mips_MULV_B = 1198, >+ Mips_MULV_D = 1199, >+ Mips_MULV_H = 1200, >+ Mips_MULV_W = 1201, >+ Mips_MUL_MM = 1202, >+ Mips_MUL_PH = 1203, >+ Mips_MUL_Q_H = 1204, >+ Mips_MUL_Q_W = 1205, >+ Mips_MUL_R6 = 1206, >+ Mips_MUL_S_PH = 1207, >+ Mips_Mfhi16 = 1208, >+ Mips_Mflo16 = 1209, >+ Mips_Move32R16 = 1210, >+ Mips_MoveR3216 = 1211, >+ Mips_MultRxRy16 = 1212, >+ Mips_MultRxRyRz16 = 1213, >+ Mips_MultuRxRy16 = 1214, >+ Mips_MultuRxRyRz16 = 1215, >+ Mips_NLOC_B = 1216, >+ Mips_NLOC_D = 1217, >+ Mips_NLOC_H = 1218, >+ Mips_NLOC_W = 1219, >+ Mips_NLZC_B = 1220, >+ Mips_NLZC_D = 1221, >+ Mips_NLZC_H = 1222, >+ Mips_NLZC_W = 1223, >+ Mips_NMADD_D32 = 1224, >+ Mips_NMADD_D32_MM = 1225, >+ Mips_NMADD_D64 = 1226, >+ Mips_NMADD_S = 1227, >+ Mips_NMADD_S_MM = 1228, >+ Mips_NMSUB_D32 = 1229, >+ Mips_NMSUB_D32_MM = 1230, >+ Mips_NMSUB_D64 = 1231, >+ Mips_NMSUB_S = 1232, >+ Mips_NMSUB_S_MM = 1233, >+ Mips_NOP = 1234, >+ Mips_NOR = 1235, >+ Mips_NOR64 = 1236, >+ Mips_NORI_B = 1237, >+ Mips_NOR_MM = 1238, >+ Mips_NOR_V = 1239, >+ Mips_NOR_V_D_PSEUDO = 1240, >+ Mips_NOR_V_H_PSEUDO = 1241, >+ Mips_NOR_V_W_PSEUDO = 1242, >+ Mips_NegRxRy16 = 1243, >+ Mips_NotRxRy16 = 1244, >+ Mips_OR = 1245, >+ Mips_OR64 = 1246, >+ Mips_ORI_B = 1247, >+ Mips_OR_MM = 1248, >+ Mips_OR_V = 1249, >+ Mips_OR_V_D_PSEUDO = 1250, >+ Mips_OR_V_H_PSEUDO = 1251, >+ Mips_OR_V_W_PSEUDO = 1252, >+ Mips_ORi = 1253, >+ Mips_ORi64 = 1254, >+ Mips_ORi_MM = 1255, >+ Mips_OrRxRxRy16 = 1256, >+ Mips_PACKRL_PH = 1257, >+ Mips_PAUSE = 1258, >+ Mips_PCKEV_B = 1259, >+ Mips_PCKEV_D = 1260, >+ Mips_PCKEV_H = 1261, >+ Mips_PCKEV_W = 1262, >+ Mips_PCKOD_B = 1263, >+ Mips_PCKOD_D = 1264, >+ Mips_PCKOD_H = 1265, >+ Mips_PCKOD_W = 1266, >+ Mips_PCNT_B = 1267, >+ Mips_PCNT_D = 1268, >+ Mips_PCNT_H = 1269, >+ Mips_PCNT_W = 1270, >+ Mips_PICK_PH = 1271, >+ Mips_PICK_QB = 1272, >+ Mips_POP = 1273, >+ Mips_PRECEQU_PH_QBL = 1274, >+ Mips_PRECEQU_PH_QBLA = 1275, >+ Mips_PRECEQU_PH_QBR = 1276, >+ Mips_PRECEQU_PH_QBRA = 1277, >+ Mips_PRECEQ_W_PHL = 1278, >+ Mips_PRECEQ_W_PHR = 1279, >+ Mips_PRECEU_PH_QBL = 1280, >+ Mips_PRECEU_PH_QBLA = 1281, >+ Mips_PRECEU_PH_QBR = 1282, >+ Mips_PRECEU_PH_QBRA = 1283, >+ Mips_PRECRQU_S_QB_PH = 1284, >+ Mips_PRECRQ_PH_W = 1285, >+ Mips_PRECRQ_QB_PH = 1286, >+ Mips_PRECRQ_RS_PH_W = 1287, >+ Mips_PRECR_QB_PH = 1288, >+ Mips_PRECR_SRA_PH_W = 1289, >+ Mips_PRECR_SRA_R_PH_W = 1290, >+ Mips_PREF = 1291, >+ Mips_PREF_R6 = 1292, >+ Mips_PREPEND = 1293, >+ Mips_PseudoCMPU_EQ_QB = 1294, >+ Mips_PseudoCMPU_LE_QB = 1295, >+ Mips_PseudoCMPU_LT_QB = 1296, >+ Mips_PseudoCMP_EQ_PH = 1297, >+ Mips_PseudoCMP_LE_PH = 1298, >+ Mips_PseudoCMP_LT_PH = 1299, >+ Mips_PseudoCVT_D32_W = 1300, >+ Mips_PseudoCVT_D64_L = 1301, >+ Mips_PseudoCVT_D64_W = 1302, >+ Mips_PseudoCVT_S_L = 1303, >+ Mips_PseudoCVT_S_W = 1304, >+ Mips_PseudoDMULT = 1305, >+ Mips_PseudoDMULTu = 1306, >+ Mips_PseudoDSDIV = 1307, >+ Mips_PseudoDUDIV = 1308, >+ Mips_PseudoIndirectBranch = 1309, >+ Mips_PseudoIndirectBranch64 = 1310, >+ Mips_PseudoMADD = 1311, >+ Mips_PseudoMADDU = 1312, >+ Mips_PseudoMFHI = 1313, >+ Mips_PseudoMFHI64 = 1314, >+ Mips_PseudoMFLO = 1315, >+ Mips_PseudoMFLO64 = 1316, >+ Mips_PseudoMSUB = 1317, >+ Mips_PseudoMSUBU = 1318, >+ Mips_PseudoMTLOHI = 1319, >+ Mips_PseudoMTLOHI64 = 1320, >+ Mips_PseudoMTLOHI_DSP = 1321, >+ Mips_PseudoMULT = 1322, >+ Mips_PseudoMULTu = 1323, >+ Mips_PseudoPICK_PH = 1324, >+ Mips_PseudoPICK_QB = 1325, >+ Mips_PseudoReturn = 1326, >+ Mips_PseudoReturn64 = 1327, >+ Mips_PseudoSDIV = 1328, >+ Mips_PseudoUDIV = 1329, >+ Mips_RADDU_W_QB = 1330, >+ Mips_RDDSP = 1331, >+ Mips_RDHWR = 1332, >+ Mips_RDHWR64 = 1333, >+ Mips_REPLV_PH = 1334, >+ Mips_REPLV_QB = 1335, >+ Mips_REPL_PH = 1336, >+ Mips_REPL_QB = 1337, >+ Mips_RINT_D = 1338, >+ Mips_RINT_S = 1339, >+ Mips_ROTR = 1340, >+ Mips_ROTRV = 1341, >+ Mips_ROTRV_MM = 1342, >+ Mips_ROTR_MM = 1343, >+ Mips_ROUND_L_D64 = 1344, >+ Mips_ROUND_L_S = 1345, >+ Mips_ROUND_W_D32 = 1346, >+ Mips_ROUND_W_D64 = 1347, >+ Mips_ROUND_W_MM = 1348, >+ Mips_ROUND_W_S = 1349, >+ Mips_ROUND_W_S_MM = 1350, >+ Mips_Restore16 = 1351, >+ Mips_RestoreX16 = 1352, >+ Mips_RetRA = 1353, >+ Mips_RetRA16 = 1354, >+ Mips_SAT_S_B = 1355, >+ Mips_SAT_S_D = 1356, >+ Mips_SAT_S_H = 1357, >+ Mips_SAT_S_W = 1358, >+ Mips_SAT_U_B = 1359, >+ Mips_SAT_U_D = 1360, >+ Mips_SAT_U_H = 1361, >+ Mips_SAT_U_W = 1362, >+ Mips_SB = 1363, >+ Mips_SB64 = 1364, >+ Mips_SB_MM = 1365, >+ Mips_SC = 1366, >+ Mips_SCD = 1367, >+ Mips_SCD_R6 = 1368, >+ Mips_SC_MM = 1369, >+ Mips_SC_R6 = 1370, >+ Mips_SD = 1371, >+ Mips_SDBBP = 1372, >+ Mips_SDBBP_R6 = 1373, >+ Mips_SDC1 = 1374, >+ Mips_SDC164 = 1375, >+ Mips_SDC1_MM = 1376, >+ Mips_SDC2 = 1377, >+ Mips_SDC2_R6 = 1378, >+ Mips_SDC3 = 1379, >+ Mips_SDIV = 1380, >+ Mips_SDIV_MM = 1381, >+ Mips_SDL = 1382, >+ Mips_SDR = 1383, >+ Mips_SDXC1 = 1384, >+ Mips_SDXC164 = 1385, >+ Mips_SEB = 1386, >+ Mips_SEB64 = 1387, >+ Mips_SEB_MM = 1388, >+ Mips_SEH = 1389, >+ Mips_SEH64 = 1390, >+ Mips_SEH_MM = 1391, >+ Mips_SELEQZ = 1392, >+ Mips_SELEQZ64 = 1393, >+ Mips_SELEQZ_D = 1394, >+ Mips_SELEQZ_S = 1395, >+ Mips_SELNEZ = 1396, >+ Mips_SELNEZ64 = 1397, >+ Mips_SELNEZ_D = 1398, >+ Mips_SELNEZ_S = 1399, >+ Mips_SEL_D = 1400, >+ Mips_SEL_S = 1401, >+ Mips_SEQ = 1402, >+ Mips_SEQi = 1403, >+ Mips_SH = 1404, >+ Mips_SH64 = 1405, >+ Mips_SHF_B = 1406, >+ Mips_SHF_H = 1407, >+ Mips_SHF_W = 1408, >+ Mips_SHILO = 1409, >+ Mips_SHILOV = 1410, >+ Mips_SHLLV_PH = 1411, >+ Mips_SHLLV_QB = 1412, >+ Mips_SHLLV_S_PH = 1413, >+ Mips_SHLLV_S_W = 1414, >+ Mips_SHLL_PH = 1415, >+ Mips_SHLL_QB = 1416, >+ Mips_SHLL_S_PH = 1417, >+ Mips_SHLL_S_W = 1418, >+ Mips_SHRAV_PH = 1419, >+ Mips_SHRAV_QB = 1420, >+ Mips_SHRAV_R_PH = 1421, >+ Mips_SHRAV_R_QB = 1422, >+ Mips_SHRAV_R_W = 1423, >+ Mips_SHRA_PH = 1424, >+ Mips_SHRA_QB = 1425, >+ Mips_SHRA_R_PH = 1426, >+ Mips_SHRA_R_QB = 1427, >+ Mips_SHRA_R_W = 1428, >+ Mips_SHRLV_PH = 1429, >+ Mips_SHRLV_QB = 1430, >+ Mips_SHRL_PH = 1431, >+ Mips_SHRL_QB = 1432, >+ Mips_SH_MM = 1433, >+ Mips_SLDI_B = 1434, >+ Mips_SLDI_D = 1435, >+ Mips_SLDI_H = 1436, >+ Mips_SLDI_W = 1437, >+ Mips_SLD_B = 1438, >+ Mips_SLD_D = 1439, >+ Mips_SLD_H = 1440, >+ Mips_SLD_W = 1441, >+ Mips_SLL = 1442, >+ Mips_SLL64_32 = 1443, >+ Mips_SLL64_64 = 1444, >+ Mips_SLLI_B = 1445, >+ Mips_SLLI_D = 1446, >+ Mips_SLLI_H = 1447, >+ Mips_SLLI_W = 1448, >+ Mips_SLLV = 1449, >+ Mips_SLLV_MM = 1450, >+ Mips_SLL_B = 1451, >+ Mips_SLL_D = 1452, >+ Mips_SLL_H = 1453, >+ Mips_SLL_MM = 1454, >+ Mips_SLL_W = 1455, >+ Mips_SLT = 1456, >+ Mips_SLT64 = 1457, >+ Mips_SLT_MM = 1458, >+ Mips_SLTi = 1459, >+ Mips_SLTi64 = 1460, >+ Mips_SLTi_MM = 1461, >+ Mips_SLTiu = 1462, >+ Mips_SLTiu64 = 1463, >+ Mips_SLTiu_MM = 1464, >+ Mips_SLTu = 1465, >+ Mips_SLTu64 = 1466, >+ Mips_SLTu_MM = 1467, >+ Mips_SNE = 1468, >+ Mips_SNEi = 1469, >+ Mips_SNZ_B_PSEUDO = 1470, >+ Mips_SNZ_D_PSEUDO = 1471, >+ Mips_SNZ_H_PSEUDO = 1472, >+ Mips_SNZ_V_PSEUDO = 1473, >+ Mips_SNZ_W_PSEUDO = 1474, >+ Mips_SPLATI_B = 1475, >+ Mips_SPLATI_D = 1476, >+ Mips_SPLATI_H = 1477, >+ Mips_SPLATI_W = 1478, >+ Mips_SPLAT_B = 1479, >+ Mips_SPLAT_D = 1480, >+ Mips_SPLAT_H = 1481, >+ Mips_SPLAT_W = 1482, >+ Mips_SRA = 1483, >+ Mips_SRAI_B = 1484, >+ Mips_SRAI_D = 1485, >+ Mips_SRAI_H = 1486, >+ Mips_SRAI_W = 1487, >+ Mips_SRARI_B = 1488, >+ Mips_SRARI_D = 1489, >+ Mips_SRARI_H = 1490, >+ Mips_SRARI_W = 1491, >+ Mips_SRAR_B = 1492, >+ Mips_SRAR_D = 1493, >+ Mips_SRAR_H = 1494, >+ Mips_SRAR_W = 1495, >+ Mips_SRAV = 1496, >+ Mips_SRAV_MM = 1497, >+ Mips_SRA_B = 1498, >+ Mips_SRA_D = 1499, >+ Mips_SRA_H = 1500, >+ Mips_SRA_MM = 1501, >+ Mips_SRA_W = 1502, >+ Mips_SRL = 1503, >+ Mips_SRLI_B = 1504, >+ Mips_SRLI_D = 1505, >+ Mips_SRLI_H = 1506, >+ Mips_SRLI_W = 1507, >+ Mips_SRLRI_B = 1508, >+ Mips_SRLRI_D = 1509, >+ Mips_SRLRI_H = 1510, >+ Mips_SRLRI_W = 1511, >+ Mips_SRLR_B = 1512, >+ Mips_SRLR_D = 1513, >+ Mips_SRLR_H = 1514, >+ Mips_SRLR_W = 1515, >+ Mips_SRLV = 1516, >+ Mips_SRLV_MM = 1517, >+ Mips_SRL_B = 1518, >+ Mips_SRL_D = 1519, >+ Mips_SRL_H = 1520, >+ Mips_SRL_MM = 1521, >+ Mips_SRL_W = 1522, >+ Mips_SSNOP = 1523, >+ Mips_STORE_ACC128 = 1524, >+ Mips_STORE_ACC64 = 1525, >+ Mips_STORE_ACC64DSP = 1526, >+ Mips_STORE_CCOND_DSP = 1527, >+ Mips_ST_B = 1528, >+ Mips_ST_D = 1529, >+ Mips_ST_H = 1530, >+ Mips_ST_W = 1531, >+ Mips_SUB = 1532, >+ Mips_SUBQH_PH = 1533, >+ Mips_SUBQH_R_PH = 1534, >+ Mips_SUBQH_R_W = 1535, >+ Mips_SUBQH_W = 1536, >+ Mips_SUBQ_PH = 1537, >+ Mips_SUBQ_S_PH = 1538, >+ Mips_SUBQ_S_W = 1539, >+ Mips_SUBSUS_U_B = 1540, >+ Mips_SUBSUS_U_D = 1541, >+ Mips_SUBSUS_U_H = 1542, >+ Mips_SUBSUS_U_W = 1543, >+ Mips_SUBSUU_S_B = 1544, >+ Mips_SUBSUU_S_D = 1545, >+ Mips_SUBSUU_S_H = 1546, >+ Mips_SUBSUU_S_W = 1547, >+ Mips_SUBS_S_B = 1548, >+ Mips_SUBS_S_D = 1549, >+ Mips_SUBS_S_H = 1550, >+ Mips_SUBS_S_W = 1551, >+ Mips_SUBS_U_B = 1552, >+ Mips_SUBS_U_D = 1553, >+ Mips_SUBS_U_H = 1554, >+ Mips_SUBS_U_W = 1555, >+ Mips_SUBUH_QB = 1556, >+ Mips_SUBUH_R_QB = 1557, >+ Mips_SUBU_PH = 1558, >+ Mips_SUBU_QB = 1559, >+ Mips_SUBU_S_PH = 1560, >+ Mips_SUBU_S_QB = 1561, >+ Mips_SUBVI_B = 1562, >+ Mips_SUBVI_D = 1563, >+ Mips_SUBVI_H = 1564, >+ Mips_SUBVI_W = 1565, >+ Mips_SUBV_B = 1566, >+ Mips_SUBV_D = 1567, >+ Mips_SUBV_H = 1568, >+ Mips_SUBV_W = 1569, >+ Mips_SUB_MM = 1570, >+ Mips_SUBu = 1571, >+ Mips_SUBu_MM = 1572, >+ Mips_SUXC1 = 1573, >+ Mips_SUXC164 = 1574, >+ Mips_SUXC1_MM = 1575, >+ Mips_SW = 1576, >+ Mips_SW64 = 1577, >+ Mips_SWC1 = 1578, >+ Mips_SWC1_MM = 1579, >+ Mips_SWC2 = 1580, >+ Mips_SWC2_R6 = 1581, >+ Mips_SWC3 = 1582, >+ Mips_SWL = 1583, >+ Mips_SWL64 = 1584, >+ Mips_SWL_MM = 1585, >+ Mips_SWR = 1586, >+ Mips_SWR64 = 1587, >+ Mips_SWR_MM = 1588, >+ Mips_SWXC1 = 1589, >+ Mips_SWXC1_MM = 1590, >+ Mips_SW_MM = 1591, >+ Mips_SYNC = 1592, >+ Mips_SYNC_MM = 1593, >+ Mips_SYSCALL = 1594, >+ Mips_SYSCALL_MM = 1595, >+ Mips_SZ_B_PSEUDO = 1596, >+ Mips_SZ_D_PSEUDO = 1597, >+ Mips_SZ_H_PSEUDO = 1598, >+ Mips_SZ_V_PSEUDO = 1599, >+ Mips_SZ_W_PSEUDO = 1600, >+ Mips_Save16 = 1601, >+ Mips_SaveX16 = 1602, >+ Mips_SbRxRyOffMemX16 = 1603, >+ Mips_SebRx16 = 1604, >+ Mips_SehRx16 = 1605, >+ Mips_SelBeqZ = 1606, >+ Mips_SelBneZ = 1607, >+ Mips_SelTBteqZCmp = 1608, >+ Mips_SelTBteqZCmpi = 1609, >+ Mips_SelTBteqZSlt = 1610, >+ Mips_SelTBteqZSlti = 1611, >+ Mips_SelTBteqZSltiu = 1612, >+ Mips_SelTBteqZSltu = 1613, >+ Mips_SelTBtneZCmp = 1614, >+ Mips_SelTBtneZCmpi = 1615, >+ Mips_SelTBtneZSlt = 1616, >+ Mips_SelTBtneZSlti = 1617, >+ Mips_SelTBtneZSltiu = 1618, >+ Mips_SelTBtneZSltu = 1619, >+ Mips_ShRxRyOffMemX16 = 1620, >+ Mips_SllX16 = 1621, >+ Mips_SllvRxRy16 = 1622, >+ Mips_SltCCRxRy16 = 1623, >+ Mips_SltRxRy16 = 1624, >+ Mips_SltiCCRxImmX16 = 1625, >+ Mips_SltiRxImm16 = 1626, >+ Mips_SltiRxImmX16 = 1627, >+ Mips_SltiuCCRxImmX16 = 1628, >+ Mips_SltiuRxImm16 = 1629, >+ Mips_SltiuRxImmX16 = 1630, >+ Mips_SltuCCRxRy16 = 1631, >+ Mips_SltuRxRy16 = 1632, >+ Mips_SltuRxRyRz16 = 1633, >+ Mips_SraX16 = 1634, >+ Mips_SravRxRy16 = 1635, >+ Mips_SrlX16 = 1636, >+ Mips_SrlvRxRy16 = 1637, >+ Mips_SubuRxRyRz16 = 1638, >+ Mips_SwRxRyOffMemX16 = 1639, >+ Mips_SwRxSpImmX16 = 1640, >+ Mips_TAILCALL = 1641, >+ Mips_TAILCALL64_R = 1642, >+ Mips_TAILCALL_R = 1643, >+ Mips_TEQ = 1644, >+ Mips_TEQI = 1645, >+ Mips_TEQI_MM = 1646, >+ Mips_TEQ_MM = 1647, >+ Mips_TGE = 1648, >+ Mips_TGEI = 1649, >+ Mips_TGEIU = 1650, >+ Mips_TGEIU_MM = 1651, >+ Mips_TGEI_MM = 1652, >+ Mips_TGEU = 1653, >+ Mips_TGEU_MM = 1654, >+ Mips_TGE_MM = 1655, >+ Mips_TLBP = 1656, >+ Mips_TLBP_MM = 1657, >+ Mips_TLBR = 1658, >+ Mips_TLBR_MM = 1659, >+ Mips_TLBWI = 1660, >+ Mips_TLBWI_MM = 1661, >+ Mips_TLBWR = 1662, >+ Mips_TLBWR_MM = 1663, >+ Mips_TLT = 1664, >+ Mips_TLTI = 1665, >+ Mips_TLTIU_MM = 1666, >+ Mips_TLTI_MM = 1667, >+ Mips_TLTU = 1668, >+ Mips_TLTU_MM = 1669, >+ Mips_TLT_MM = 1670, >+ Mips_TNE = 1671, >+ Mips_TNEI = 1672, >+ Mips_TNEI_MM = 1673, >+ Mips_TNE_MM = 1674, >+ Mips_TRAP = 1675, >+ Mips_TRUNC_L_D64 = 1676, >+ Mips_TRUNC_L_S = 1677, >+ Mips_TRUNC_W_D32 = 1678, >+ Mips_TRUNC_W_D64 = 1679, >+ Mips_TRUNC_W_MM = 1680, >+ Mips_TRUNC_W_S = 1681, >+ Mips_TRUNC_W_S_MM = 1682, >+ Mips_TTLTIU = 1683, >+ Mips_UDIV = 1684, >+ Mips_UDIV_MM = 1685, >+ Mips_V3MULU = 1686, >+ Mips_VMM0 = 1687, >+ Mips_VMULU = 1688, >+ Mips_VSHF_B = 1689, >+ Mips_VSHF_D = 1690, >+ Mips_VSHF_H = 1691, >+ Mips_VSHF_W = 1692, >+ Mips_WAIT = 1693, >+ Mips_WAIT_MM = 1694, >+ Mips_WRDSP = 1695, >+ Mips_WSBH = 1696, >+ Mips_WSBH_MM = 1697, >+ Mips_XOR = 1698, >+ Mips_XOR64 = 1699, >+ Mips_XORI_B = 1700, >+ Mips_XOR_MM = 1701, >+ Mips_XOR_V = 1702, >+ Mips_XOR_V_D_PSEUDO = 1703, >+ Mips_XOR_V_H_PSEUDO = 1704, >+ Mips_XOR_V_W_PSEUDO = 1705, >+ Mips_XORi = 1706, >+ Mips_XORi64 = 1707, >+ Mips_XORi_MM = 1708, >+ Mips_XorRxRxRy16 = 1709, >+ Mips_INSTRUCTION_LIST_END = 1710 >+}; >+ >+#endif // GET_INSTRINFO_ENUM >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..d87ef67a96d9dfa41b69f6d8b323275d0af81c65 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenRegisterInfo.inc >@@ -0,0 +1,1527 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Target Register Enum Values *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_ENUM >+#undef GET_REGINFO_ENUM >+ >+enum { >+ Mips_NoRegister, >+ Mips_AT = 1, >+ Mips_DSPCCond = 2, >+ Mips_DSPCarry = 3, >+ Mips_DSPEFI = 4, >+ Mips_DSPOutFlag = 5, >+ Mips_DSPPos = 6, >+ Mips_DSPSCount = 7, >+ Mips_FP = 8, >+ Mips_GP = 9, >+ Mips_MSAAccess = 10, >+ Mips_MSACSR = 11, >+ Mips_MSAIR = 12, >+ Mips_MSAMap = 13, >+ Mips_MSAModify = 14, >+ Mips_MSARequest = 15, >+ Mips_MSASave = 16, >+ Mips_MSAUnmap = 17, >+ Mips_PC = 18, >+ Mips_RA = 19, >+ Mips_SP = 20, >+ Mips_ZERO = 21, >+ Mips_A0 = 22, >+ Mips_A1 = 23, >+ Mips_A2 = 24, >+ Mips_A3 = 25, >+ Mips_AC0 = 26, >+ Mips_AC1 = 27, >+ Mips_AC2 = 28, >+ Mips_AC3 = 29, >+ Mips_AT_64 = 30, >+ Mips_CC0 = 31, >+ Mips_CC1 = 32, >+ Mips_CC2 = 33, >+ Mips_CC3 = 34, >+ Mips_CC4 = 35, >+ Mips_CC5 = 36, >+ Mips_CC6 = 37, >+ Mips_CC7 = 38, >+ Mips_COP20 = 39, >+ Mips_COP21 = 40, >+ Mips_COP22 = 41, >+ Mips_COP23 = 42, >+ Mips_COP24 = 43, >+ Mips_COP25 = 44, >+ Mips_COP26 = 45, >+ Mips_COP27 = 46, >+ Mips_COP28 = 47, >+ Mips_COP29 = 48, >+ Mips_COP30 = 49, >+ Mips_COP31 = 50, >+ Mips_COP32 = 51, >+ Mips_COP33 = 52, >+ Mips_COP34 = 53, >+ Mips_COP35 = 54, >+ Mips_COP36 = 55, >+ Mips_COP37 = 56, >+ Mips_COP38 = 57, >+ Mips_COP39 = 58, >+ Mips_COP210 = 59, >+ Mips_COP211 = 60, >+ Mips_COP212 = 61, >+ Mips_COP213 = 62, >+ Mips_COP214 = 63, >+ Mips_COP215 = 64, >+ Mips_COP216 = 65, >+ Mips_COP217 = 66, >+ Mips_COP218 = 67, >+ Mips_COP219 = 68, >+ Mips_COP220 = 69, >+ Mips_COP221 = 70, >+ Mips_COP222 = 71, >+ Mips_COP223 = 72, >+ Mips_COP224 = 73, >+ Mips_COP225 = 74, >+ Mips_COP226 = 75, >+ Mips_COP227 = 76, >+ Mips_COP228 = 77, >+ Mips_COP229 = 78, >+ Mips_COP230 = 79, >+ Mips_COP231 = 80, >+ Mips_COP310 = 81, >+ Mips_COP311 = 82, >+ Mips_COP312 = 83, >+ Mips_COP313 = 84, >+ Mips_COP314 = 85, >+ Mips_COP315 = 86, >+ Mips_COP316 = 87, >+ Mips_COP317 = 88, >+ Mips_COP318 = 89, >+ Mips_COP319 = 90, >+ Mips_COP320 = 91, >+ Mips_COP321 = 92, >+ Mips_COP322 = 93, >+ Mips_COP323 = 94, >+ Mips_COP324 = 95, >+ Mips_COP325 = 96, >+ Mips_COP326 = 97, >+ Mips_COP327 = 98, >+ Mips_COP328 = 99, >+ Mips_COP329 = 100, >+ Mips_COP330 = 101, >+ Mips_COP331 = 102, >+ Mips_D0 = 103, >+ Mips_D1 = 104, >+ Mips_D2 = 105, >+ Mips_D3 = 106, >+ Mips_D4 = 107, >+ Mips_D5 = 108, >+ Mips_D6 = 109, >+ Mips_D7 = 110, >+ Mips_D8 = 111, >+ Mips_D9 = 112, >+ Mips_D10 = 113, >+ Mips_D11 = 114, >+ Mips_D12 = 115, >+ Mips_D13 = 116, >+ Mips_D14 = 117, >+ Mips_D15 = 118, >+ Mips_DSPOutFlag20 = 119, >+ Mips_DSPOutFlag21 = 120, >+ Mips_DSPOutFlag22 = 121, >+ Mips_DSPOutFlag23 = 122, >+ Mips_F0 = 123, >+ Mips_F1 = 124, >+ Mips_F2 = 125, >+ Mips_F3 = 126, >+ Mips_F4 = 127, >+ Mips_F5 = 128, >+ Mips_F6 = 129, >+ Mips_F7 = 130, >+ Mips_F8 = 131, >+ Mips_F9 = 132, >+ Mips_F10 = 133, >+ Mips_F11 = 134, >+ Mips_F12 = 135, >+ Mips_F13 = 136, >+ Mips_F14 = 137, >+ Mips_F15 = 138, >+ Mips_F16 = 139, >+ Mips_F17 = 140, >+ Mips_F18 = 141, >+ Mips_F19 = 142, >+ Mips_F20 = 143, >+ Mips_F21 = 144, >+ Mips_F22 = 145, >+ Mips_F23 = 146, >+ Mips_F24 = 147, >+ Mips_F25 = 148, >+ Mips_F26 = 149, >+ Mips_F27 = 150, >+ Mips_F28 = 151, >+ Mips_F29 = 152, >+ Mips_F30 = 153, >+ Mips_F31 = 154, >+ Mips_FCC0 = 155, >+ Mips_FCC1 = 156, >+ Mips_FCC2 = 157, >+ Mips_FCC3 = 158, >+ Mips_FCC4 = 159, >+ Mips_FCC5 = 160, >+ Mips_FCC6 = 161, >+ Mips_FCC7 = 162, >+ Mips_FCR0 = 163, >+ Mips_FCR1 = 164, >+ Mips_FCR2 = 165, >+ Mips_FCR3 = 166, >+ Mips_FCR4 = 167, >+ Mips_FCR5 = 168, >+ Mips_FCR6 = 169, >+ Mips_FCR7 = 170, >+ Mips_FCR8 = 171, >+ Mips_FCR9 = 172, >+ Mips_FCR10 = 173, >+ Mips_FCR11 = 174, >+ Mips_FCR12 = 175, >+ Mips_FCR13 = 176, >+ Mips_FCR14 = 177, >+ Mips_FCR15 = 178, >+ Mips_FCR16 = 179, >+ Mips_FCR17 = 180, >+ Mips_FCR18 = 181, >+ Mips_FCR19 = 182, >+ Mips_FCR20 = 183, >+ Mips_FCR21 = 184, >+ Mips_FCR22 = 185, >+ Mips_FCR23 = 186, >+ Mips_FCR24 = 187, >+ Mips_FCR25 = 188, >+ Mips_FCR26 = 189, >+ Mips_FCR27 = 190, >+ Mips_FCR28 = 191, >+ Mips_FCR29 = 192, >+ Mips_FCR30 = 193, >+ Mips_FCR31 = 194, >+ Mips_FP_64 = 195, >+ Mips_F_HI0 = 196, >+ Mips_F_HI1 = 197, >+ Mips_F_HI2 = 198, >+ Mips_F_HI3 = 199, >+ Mips_F_HI4 = 200, >+ Mips_F_HI5 = 201, >+ Mips_F_HI6 = 202, >+ Mips_F_HI7 = 203, >+ Mips_F_HI8 = 204, >+ Mips_F_HI9 = 205, >+ Mips_F_HI10 = 206, >+ Mips_F_HI11 = 207, >+ Mips_F_HI12 = 208, >+ Mips_F_HI13 = 209, >+ Mips_F_HI14 = 210, >+ Mips_F_HI15 = 211, >+ Mips_F_HI16 = 212, >+ Mips_F_HI17 = 213, >+ Mips_F_HI18 = 214, >+ Mips_F_HI19 = 215, >+ Mips_F_HI20 = 216, >+ Mips_F_HI21 = 217, >+ Mips_F_HI22 = 218, >+ Mips_F_HI23 = 219, >+ Mips_F_HI24 = 220, >+ Mips_F_HI25 = 221, >+ Mips_F_HI26 = 222, >+ Mips_F_HI27 = 223, >+ Mips_F_HI28 = 224, >+ Mips_F_HI29 = 225, >+ Mips_F_HI30 = 226, >+ Mips_F_HI31 = 227, >+ Mips_GP_64 = 228, >+ Mips_HI0 = 229, >+ Mips_HI1 = 230, >+ Mips_HI2 = 231, >+ Mips_HI3 = 232, >+ Mips_HWR0 = 233, >+ Mips_HWR1 = 234, >+ Mips_HWR2 = 235, >+ Mips_HWR3 = 236, >+ Mips_HWR4 = 237, >+ Mips_HWR5 = 238, >+ Mips_HWR6 = 239, >+ Mips_HWR7 = 240, >+ Mips_HWR8 = 241, >+ Mips_HWR9 = 242, >+ Mips_HWR10 = 243, >+ Mips_HWR11 = 244, >+ Mips_HWR12 = 245, >+ Mips_HWR13 = 246, >+ Mips_HWR14 = 247, >+ Mips_HWR15 = 248, >+ Mips_HWR16 = 249, >+ Mips_HWR17 = 250, >+ Mips_HWR18 = 251, >+ Mips_HWR19 = 252, >+ Mips_HWR20 = 253, >+ Mips_HWR21 = 254, >+ Mips_HWR22 = 255, >+ Mips_HWR23 = 256, >+ Mips_HWR24 = 257, >+ Mips_HWR25 = 258, >+ Mips_HWR26 = 259, >+ Mips_HWR27 = 260, >+ Mips_HWR28 = 261, >+ Mips_HWR29 = 262, >+ Mips_HWR30 = 263, >+ Mips_HWR31 = 264, >+ Mips_K0 = 265, >+ Mips_K1 = 266, >+ Mips_LO0 = 267, >+ Mips_LO1 = 268, >+ Mips_LO2 = 269, >+ Mips_LO3 = 270, >+ Mips_MPL0 = 271, >+ Mips_MPL1 = 272, >+ Mips_MPL2 = 273, >+ Mips_P0 = 274, >+ Mips_P1 = 275, >+ Mips_P2 = 276, >+ Mips_RA_64 = 277, >+ Mips_S0 = 278, >+ Mips_S1 = 279, >+ Mips_S2 = 280, >+ Mips_S3 = 281, >+ Mips_S4 = 282, >+ Mips_S5 = 283, >+ Mips_S6 = 284, >+ Mips_S7 = 285, >+ Mips_SP_64 = 286, >+ Mips_T0 = 287, >+ Mips_T1 = 288, >+ Mips_T2 = 289, >+ Mips_T3 = 290, >+ Mips_T4 = 291, >+ Mips_T5 = 292, >+ Mips_T6 = 293, >+ Mips_T7 = 294, >+ Mips_T8 = 295, >+ Mips_T9 = 296, >+ Mips_V0 = 297, >+ Mips_V1 = 298, >+ Mips_W0 = 299, >+ Mips_W1 = 300, >+ Mips_W2 = 301, >+ Mips_W3 = 302, >+ Mips_W4 = 303, >+ Mips_W5 = 304, >+ Mips_W6 = 305, >+ Mips_W7 = 306, >+ Mips_W8 = 307, >+ Mips_W9 = 308, >+ Mips_W10 = 309, >+ Mips_W11 = 310, >+ Mips_W12 = 311, >+ Mips_W13 = 312, >+ Mips_W14 = 313, >+ Mips_W15 = 314, >+ Mips_W16 = 315, >+ Mips_W17 = 316, >+ Mips_W18 = 317, >+ Mips_W19 = 318, >+ Mips_W20 = 319, >+ Mips_W21 = 320, >+ Mips_W22 = 321, >+ Mips_W23 = 322, >+ Mips_W24 = 323, >+ Mips_W25 = 324, >+ Mips_W26 = 325, >+ Mips_W27 = 326, >+ Mips_W28 = 327, >+ Mips_W29 = 328, >+ Mips_W30 = 329, >+ Mips_W31 = 330, >+ Mips_ZERO_64 = 331, >+ Mips_A0_64 = 332, >+ Mips_A1_64 = 333, >+ Mips_A2_64 = 334, >+ Mips_A3_64 = 335, >+ Mips_AC0_64 = 336, >+ Mips_D0_64 = 337, >+ Mips_D1_64 = 338, >+ Mips_D2_64 = 339, >+ Mips_D3_64 = 340, >+ Mips_D4_64 = 341, >+ Mips_D5_64 = 342, >+ Mips_D6_64 = 343, >+ Mips_D7_64 = 344, >+ Mips_D8_64 = 345, >+ Mips_D9_64 = 346, >+ Mips_D10_64 = 347, >+ Mips_D11_64 = 348, >+ Mips_D12_64 = 349, >+ Mips_D13_64 = 350, >+ Mips_D14_64 = 351, >+ Mips_D15_64 = 352, >+ Mips_D16_64 = 353, >+ Mips_D17_64 = 354, >+ Mips_D18_64 = 355, >+ Mips_D19_64 = 356, >+ Mips_D20_64 = 357, >+ Mips_D21_64 = 358, >+ Mips_D22_64 = 359, >+ Mips_D23_64 = 360, >+ Mips_D24_64 = 361, >+ Mips_D25_64 = 362, >+ Mips_D26_64 = 363, >+ Mips_D27_64 = 364, >+ Mips_D28_64 = 365, >+ Mips_D29_64 = 366, >+ Mips_D30_64 = 367, >+ Mips_D31_64 = 368, >+ Mips_DSPOutFlag16_19 = 369, >+ Mips_HI0_64 = 370, >+ Mips_K0_64 = 371, >+ Mips_K1_64 = 372, >+ Mips_LO0_64 = 373, >+ Mips_S0_64 = 374, >+ Mips_S1_64 = 375, >+ Mips_S2_64 = 376, >+ Mips_S3_64 = 377, >+ Mips_S4_64 = 378, >+ Mips_S5_64 = 379, >+ Mips_S6_64 = 380, >+ Mips_S7_64 = 381, >+ Mips_T0_64 = 382, >+ Mips_T1_64 = 383, >+ Mips_T2_64 = 384, >+ Mips_T3_64 = 385, >+ Mips_T4_64 = 386, >+ Mips_T5_64 = 387, >+ Mips_T6_64 = 388, >+ Mips_T7_64 = 389, >+ Mips_T8_64 = 390, >+ Mips_T9_64 = 391, >+ Mips_V0_64 = 392, >+ Mips_V1_64 = 393, >+ Mips_NUM_TARGET_REGS // 394 >+}; >+ >+// Register classes >+enum { >+ Mips_OddSPRegClassID = 0, >+ Mips_CCRRegClassID = 1, >+ Mips_COP2RegClassID = 2, >+ Mips_COP3RegClassID = 3, >+ Mips_DSPRRegClassID = 4, >+ Mips_FGR32RegClassID = 5, >+ Mips_FGRCCRegClassID = 6, >+ Mips_FGRH32RegClassID = 7, >+ Mips_GPR32RegClassID = 8, >+ Mips_HWRegsRegClassID = 9, >+ Mips_OddSP_with_sub_hiRegClassID = 10, >+ Mips_FGR32_and_OddSPRegClassID = 11, >+ Mips_FGRH32_and_OddSPRegClassID = 12, >+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13, >+ Mips_CPU16RegsPlusSPRegClassID = 14, >+ Mips_CCRegClassID = 15, >+ Mips_CPU16RegsRegClassID = 16, >+ Mips_FCCRegClassID = 17, >+ Mips_MSACtrlRegClassID = 18, >+ Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 19, >+ Mips_HI32DSPRegClassID = 20, >+ Mips_LO32DSPRegClassID = 21, >+ Mips_CPURARegRegClassID = 22, >+ Mips_CPUSPRegRegClassID = 23, >+ Mips_DSPCCRegClassID = 24, >+ Mips_HI32RegClassID = 25, >+ Mips_LO32RegClassID = 26, >+ Mips_FGR64RegClassID = 27, >+ Mips_GPR64RegClassID = 28, >+ Mips_AFGR64RegClassID = 29, >+ Mips_FGR64_and_OddSPRegClassID = 30, >+ Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 31, >+ Mips_AFGR64_and_OddSPRegClassID = 32, >+ Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 33, >+ Mips_ACC64DSPRegClassID = 34, >+ Mips_OCTEON_MPLRegClassID = 35, >+ Mips_OCTEON_PRegClassID = 36, >+ Mips_ACC64RegClassID = 37, >+ Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 38, >+ Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 39, >+ Mips_HI64RegClassID = 40, >+ Mips_LO64RegClassID = 41, >+ Mips_MSA128BRegClassID = 42, >+ Mips_MSA128DRegClassID = 43, >+ Mips_MSA128HRegClassID = 44, >+ Mips_MSA128WRegClassID = 45, >+ Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 46, >+ Mips_ACC128RegClassID = 47 >+}; >+ >+// Subregister indices >+enum { >+ Mips_NoSubRegister, >+ Mips_sub_32, // 1 >+ Mips_sub_64, // 2 >+ Mips_sub_dsp16_19, // 3 >+ Mips_sub_dsp20, // 4 >+ Mips_sub_dsp21, // 5 >+ Mips_sub_dsp22, // 6 >+ Mips_sub_dsp23, // 7 >+ Mips_sub_hi, // 8 >+ Mips_sub_lo, // 9 >+ Mips_sub_hi_then_sub_32, // 10 >+ Mips_sub_32_sub_hi_then_sub_32, // 11 >+ Mips_NUM_TARGET_SUBREGS >+}; >+ >+#endif // GET_REGINFO_ENUM >+ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*MC Register Information *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_REGINFO_MC_DESC >+#undef GET_REGINFO_MC_DESC >+ >+static const MCPhysReg MipsRegDiffLists[] = { >+ /* 0 */ 0, 0, >+ /* 2 */ 4, 1, 1, 1, 1, 0, >+ /* 8 */ 364, 65286, 1, 1, 1, 0, >+ /* 14 */ 20, 1, 0, >+ /* 17 */ 21, 1, 0, >+ /* 20 */ 22, 1, 0, >+ /* 23 */ 23, 1, 0, >+ /* 26 */ 24, 1, 0, >+ /* 29 */ 25, 1, 0, >+ /* 32 */ 26, 1, 0, >+ /* 35 */ 27, 1, 0, >+ /* 38 */ 28, 1, 0, >+ /* 41 */ 29, 1, 0, >+ /* 44 */ 30, 1, 0, >+ /* 47 */ 31, 1, 0, >+ /* 50 */ 32, 1, 0, >+ /* 53 */ 33, 1, 0, >+ /* 56 */ 34, 1, 0, >+ /* 59 */ 35, 1, 0, >+ /* 62 */ 65439, 1, 0, >+ /* 65 */ 65513, 1, 0, >+ /* 68 */ 3, 0, >+ /* 70 */ 4, 0, >+ /* 72 */ 6, 0, >+ /* 74 */ 11, 0, >+ /* 76 */ 12, 0, >+ /* 78 */ 22, 0, >+ /* 80 */ 23, 0, >+ /* 82 */ 29, 0, >+ /* 84 */ 30, 0, >+ /* 86 */ 65308, 72, 0, >+ /* 89 */ 65346, 72, 0, >+ /* 92 */ 38, 65322, 73, 0, >+ /* 96 */ 95, 0, >+ /* 98 */ 96, 0, >+ /* 100 */ 106, 0, >+ /* 102 */ 187, 0, >+ /* 104 */ 219, 0, >+ /* 106 */ 258, 0, >+ /* 108 */ 266, 0, >+ /* 110 */ 310, 0, >+ /* 112 */ 65031, 0, >+ /* 114 */ 65108, 0, >+ /* 116 */ 65172, 0, >+ /* 118 */ 65226, 0, >+ /* 120 */ 65229, 0, >+ /* 122 */ 65270, 0, >+ /* 124 */ 65278, 0, >+ /* 126 */ 65295, 0, >+ /* 128 */ 65317, 0, >+ /* 130 */ 37, 65430, 103, 65395, 65333, 0, >+ /* 136 */ 65349, 0, >+ /* 138 */ 65395, 0, >+ /* 140 */ 65410, 0, >+ /* 142 */ 65415, 0, >+ /* 144 */ 65419, 0, >+ /* 146 */ 65420, 0, >+ /* 148 */ 65421, 0, >+ /* 150 */ 65422, 0, >+ /* 152 */ 65430, 0, >+ /* 154 */ 65440, 0, >+ /* 156 */ 65441, 0, >+ /* 158 */ 141, 65498, 0, >+ /* 161 */ 65516, 234, 65498, 0, >+ /* 165 */ 65515, 235, 65498, 0, >+ /* 169 */ 65514, 236, 65498, 0, >+ /* 173 */ 65513, 237, 65498, 0, >+ /* 177 */ 65512, 238, 65498, 0, >+ /* 181 */ 65511, 239, 65498, 0, >+ /* 185 */ 65510, 240, 65498, 0, >+ /* 189 */ 65509, 241, 65498, 0, >+ /* 193 */ 65508, 242, 65498, 0, >+ /* 197 */ 65507, 243, 65498, 0, >+ /* 201 */ 65506, 244, 65498, 0, >+ /* 205 */ 65505, 245, 65498, 0, >+ /* 209 */ 65504, 246, 65498, 0, >+ /* 213 */ 65503, 247, 65498, 0, >+ /* 217 */ 65502, 248, 65498, 0, >+ /* 221 */ 65501, 249, 65498, 0, >+ /* 225 */ 65500, 250, 65498, 0, >+ /* 229 */ 65295, 347, 65499, 0, >+ /* 233 */ 65333, 344, 65502, 0, >+ /* 237 */ 65507, 0, >+ /* 239 */ 65510, 0, >+ /* 241 */ 65511, 0, >+ /* 243 */ 65512, 0, >+ /* 245 */ 65516, 0, >+ /* 247 */ 65521, 0, >+ /* 249 */ 65522, 0, >+ /* 251 */ 65535, 0, >+}; >+ >+static const uint16_t MipsSubRegIdxLists[] = { >+ /* 0 */ 1, 0, >+ /* 2 */ 3, 4, 5, 6, 7, 0, >+ /* 8 */ 2, 9, 8, 0, >+ /* 12 */ 9, 1, 8, 10, 11, 0, >+}; >+ >+static const MCRegisterDesc MipsRegDesc[] = { // Descriptors >+ { 6, 0, 0, 0, 0 }, >+ { 2007, 1, 82, 1, 4017 }, >+ { 2010, 1, 1, 1, 4017 }, >+ { 2102, 1, 1, 1, 4017 }, >+ { 1973, 1, 1, 1, 4017 }, >+ { 2027, 8, 1, 2, 32 }, >+ { 2054, 1, 1, 1, 1089 }, >+ { 2071, 1, 1, 1, 1089 }, >+ { 1985, 1, 102, 1, 1089 }, >+ { 1988, 1, 104, 1, 1089 }, >+ { 2061, 1, 1, 1, 1089 }, >+ { 2000, 1, 1, 1, 1089 }, >+ { 1994, 1, 1, 1, 1089 }, >+ { 2038, 1, 1, 1, 1089 }, >+ { 2092, 1, 1, 1, 1089 }, >+ { 2081, 1, 1, 1, 1089 }, >+ { 2019, 1, 1, 1, 1089 }, >+ { 2045, 1, 1, 1, 1089 }, >+ { 1970, 1, 1, 1, 1089 }, >+ { 1967, 1, 106, 1, 1089 }, >+ { 1991, 1, 108, 1, 1089 }, >+ { 1980, 1, 110, 1, 1089 }, >+ { 152, 1, 110, 1, 1089 }, >+ { 365, 1, 110, 1, 1089 }, >+ { 537, 1, 110, 1, 1089 }, >+ { 703, 1, 110, 1, 1089 }, >+ { 155, 190, 110, 9, 1042 }, >+ { 368, 190, 1, 9, 1042 }, >+ { 540, 190, 1, 9, 1042 }, >+ { 706, 190, 1, 9, 1042 }, >+ { 1271, 237, 1, 0, 0 }, >+ { 160, 1, 1, 1, 1153 }, >+ { 373, 1, 1, 1, 1153 }, >+ { 545, 1, 1, 1, 1153 }, >+ { 711, 1, 1, 1, 1153 }, >+ { 1278, 1, 1, 1, 1153 }, >+ { 1412, 1, 1, 1, 1153 }, >+ { 1542, 1, 1, 1, 1153 }, >+ { 1672, 1, 1, 1, 1153 }, >+ { 70, 1, 1, 1, 1153 }, >+ { 283, 1, 1, 1, 1153 }, >+ { 496, 1, 1, 1, 1153 }, >+ { 662, 1, 1, 1, 1153 }, >+ { 820, 1, 1, 1, 1153 }, >+ { 1383, 1, 1, 1, 1153 }, >+ { 1513, 1, 1, 1, 1153 }, >+ { 1643, 1, 1, 1, 1153 }, >+ { 1773, 1, 1, 1, 1153 }, >+ { 1911, 1, 1, 1, 1153 }, >+ { 130, 1, 1, 1, 1153 }, >+ { 343, 1, 1, 1, 1153 }, >+ { 531, 1, 1, 1, 1153 }, >+ { 697, 1, 1, 1, 1153 }, >+ { 842, 1, 1, 1, 1153 }, >+ { 1405, 1, 1, 1, 1153 }, >+ { 1535, 1, 1, 1, 1153 }, >+ { 1665, 1, 1, 1, 1153 }, >+ { 1795, 1, 1, 1, 1153 }, >+ { 1933, 1, 1, 1, 1153 }, >+ { 0, 1, 1, 1, 1153 }, >+ { 213, 1, 1, 1, 1153 }, >+ { 426, 1, 1, 1, 1153 }, >+ { 592, 1, 1, 1, 1153 }, >+ { 750, 1, 1, 1, 1153 }, >+ { 1313, 1, 1, 1, 1153 }, >+ { 1447, 1, 1, 1, 1153 }, >+ { 1577, 1, 1, 1, 1153 }, >+ { 1707, 1, 1, 1, 1153 }, >+ { 1829, 1, 1, 1, 1153 }, >+ { 45, 1, 1, 1, 1153 }, >+ { 258, 1, 1, 1, 1153 }, >+ { 471, 1, 1, 1, 1153 }, >+ { 637, 1, 1, 1, 1153 }, >+ { 795, 1, 1, 1, 1153 }, >+ { 1358, 1, 1, 1, 1153 }, >+ { 1488, 1, 1, 1, 1153 }, >+ { 1618, 1, 1, 1, 1153 }, >+ { 1748, 1, 1, 1, 1153 }, >+ { 1886, 1, 1, 1, 1153 }, >+ { 105, 1, 1, 1, 1153 }, >+ { 318, 1, 1, 1, 1153 }, >+ { 7, 1, 1, 1, 1153 }, >+ { 220, 1, 1, 1, 1153 }, >+ { 433, 1, 1, 1, 1153 }, >+ { 599, 1, 1, 1, 1153 }, >+ { 757, 1, 1, 1, 1153 }, >+ { 1320, 1, 1, 1, 1153 }, >+ { 1454, 1, 1, 1, 1153 }, >+ { 1584, 1, 1, 1, 1153 }, >+ { 1714, 1, 1, 1, 1153 }, >+ { 1836, 1, 1, 1, 1153 }, >+ { 52, 1, 1, 1, 1153 }, >+ { 265, 1, 1, 1, 1153 }, >+ { 478, 1, 1, 1, 1153 }, >+ { 644, 1, 1, 1, 1153 }, >+ { 802, 1, 1, 1, 1153 }, >+ { 1365, 1, 1, 1, 1153 }, >+ { 1495, 1, 1, 1, 1153 }, >+ { 1625, 1, 1, 1, 1153 }, >+ { 1755, 1, 1, 1, 1153 }, >+ { 1893, 1, 1, 1, 1153 }, >+ { 112, 1, 1, 1, 1153 }, >+ { 325, 1, 1, 1, 1153 }, >+ { 164, 14, 1, 9, 994 }, >+ { 377, 17, 1, 9, 994 }, >+ { 549, 20, 1, 9, 994 }, >+ { 715, 23, 1, 9, 994 }, >+ { 1282, 26, 1, 9, 994 }, >+ { 1416, 29, 1, 9, 994 }, >+ { 1546, 32, 1, 9, 994 }, >+ { 1676, 35, 1, 9, 994 }, >+ { 1801, 38, 1, 9, 994 }, >+ { 1939, 41, 1, 9, 994 }, >+ { 14, 44, 1, 9, 994 }, >+ { 227, 47, 1, 9, 994 }, >+ { 440, 50, 1, 9, 994 }, >+ { 606, 53, 1, 9, 994 }, >+ { 764, 56, 1, 9, 994 }, >+ { 1327, 59, 1, 9, 994 }, >+ { 92, 1, 150, 1, 2401 }, >+ { 305, 1, 148, 1, 2401 }, >+ { 518, 1, 146, 1, 2401 }, >+ { 684, 1, 144, 1, 2401 }, >+ { 167, 1, 161, 1, 3985 }, >+ { 380, 1, 165, 1, 3985 }, >+ { 552, 1, 165, 1, 3985 }, >+ { 718, 1, 169, 1, 3985 }, >+ { 1285, 1, 169, 1, 3985 }, >+ { 1419, 1, 173, 1, 3985 }, >+ { 1549, 1, 173, 1, 3985 }, >+ { 1679, 1, 177, 1, 3985 }, >+ { 1804, 1, 177, 1, 3985 }, >+ { 1942, 1, 181, 1, 3985 }, >+ { 18, 1, 181, 1, 3985 }, >+ { 231, 1, 185, 1, 3985 }, >+ { 444, 1, 185, 1, 3985 }, >+ { 610, 1, 189, 1, 3985 }, >+ { 768, 1, 189, 1, 3985 }, >+ { 1331, 1, 193, 1, 3985 }, >+ { 1461, 1, 193, 1, 3985 }, >+ { 1591, 1, 197, 1, 3985 }, >+ { 1721, 1, 197, 1, 3985 }, >+ { 1843, 1, 201, 1, 3985 }, >+ { 59, 1, 201, 1, 3985 }, >+ { 272, 1, 205, 1, 3985 }, >+ { 485, 1, 205, 1, 3985 }, >+ { 651, 1, 209, 1, 3985 }, >+ { 809, 1, 209, 1, 3985 }, >+ { 1372, 1, 213, 1, 3985 }, >+ { 1502, 1, 213, 1, 3985 }, >+ { 1632, 1, 217, 1, 3985 }, >+ { 1762, 1, 217, 1, 3985 }, >+ { 1900, 1, 221, 1, 3985 }, >+ { 119, 1, 221, 1, 3985 }, >+ { 332, 1, 225, 1, 3985 }, >+ { 159, 1, 1, 1, 3985 }, >+ { 372, 1, 1, 1, 3985 }, >+ { 544, 1, 1, 1, 3985 }, >+ { 710, 1, 1, 1, 3985 }, >+ { 1277, 1, 1, 1, 3985 }, >+ { 1411, 1, 1, 1, 3985 }, >+ { 1541, 1, 1, 1, 3985 }, >+ { 1671, 1, 1, 1, 3985 }, >+ { 191, 1, 1, 1, 3985 }, >+ { 404, 1, 1, 1, 3985 }, >+ { 573, 1, 1, 1, 3985 }, >+ { 731, 1, 1, 1, 3985 }, >+ { 1294, 1, 1, 1, 3985 }, >+ { 1428, 1, 1, 1, 3985 }, >+ { 1558, 1, 1, 1, 3985 }, >+ { 1688, 1, 1, 1, 3985 }, >+ { 1813, 1, 1, 1, 3985 }, >+ { 1951, 1, 1, 1, 3985 }, >+ { 29, 1, 1, 1, 3985 }, >+ { 242, 1, 1, 1, 3985 }, >+ { 455, 1, 1, 1, 3985 }, >+ { 621, 1, 1, 1, 3985 }, >+ { 779, 1, 1, 1, 3985 }, >+ { 1342, 1, 1, 1, 3985 }, >+ { 1472, 1, 1, 1, 3985 }, >+ { 1602, 1, 1, 1, 3985 }, >+ { 1732, 1, 1, 1, 3985 }, >+ { 1854, 1, 1, 1, 3985 }, >+ { 76, 1, 1, 1, 3985 }, >+ { 289, 1, 1, 1, 3985 }, >+ { 502, 1, 1, 1, 3985 }, >+ { 668, 1, 1, 1, 3985 }, >+ { 826, 1, 1, 1, 3985 }, >+ { 1389, 1, 1, 1, 3985 }, >+ { 1519, 1, 1, 1, 3985 }, >+ { 1649, 1, 1, 1, 3985 }, >+ { 1779, 1, 1, 1, 3985 }, >+ { 1917, 1, 1, 1, 3985 }, >+ { 136, 1, 1, 1, 3985 }, >+ { 349, 1, 1, 1, 3985 }, >+ { 1253, 136, 1, 0, 1184 }, >+ { 170, 1, 158, 1, 3953 }, >+ { 383, 1, 158, 1, 3953 }, >+ { 555, 1, 158, 1, 3953 }, >+ { 721, 1, 158, 1, 3953 }, >+ { 1288, 1, 158, 1, 3953 }, >+ { 1422, 1, 158, 1, 3953 }, >+ { 1552, 1, 158, 1, 3953 }, >+ { 1682, 1, 158, 1, 3953 }, >+ { 1807, 1, 158, 1, 3953 }, >+ { 1945, 1, 158, 1, 3953 }, >+ { 22, 1, 158, 1, 3953 }, >+ { 235, 1, 158, 1, 3953 }, >+ { 448, 1, 158, 1, 3953 }, >+ { 614, 1, 158, 1, 3953 }, >+ { 772, 1, 158, 1, 3953 }, >+ { 1335, 1, 158, 1, 3953 }, >+ { 1465, 1, 158, 1, 3953 }, >+ { 1595, 1, 158, 1, 3953 }, >+ { 1725, 1, 158, 1, 3953 }, >+ { 1847, 1, 158, 1, 3953 }, >+ { 63, 1, 158, 1, 3953 }, >+ { 276, 1, 158, 1, 3953 }, >+ { 489, 1, 158, 1, 3953 }, >+ { 655, 1, 158, 1, 3953 }, >+ { 813, 1, 158, 1, 3953 }, >+ { 1376, 1, 158, 1, 3953 }, >+ { 1506, 1, 158, 1, 3953 }, >+ { 1636, 1, 158, 1, 3953 }, >+ { 1766, 1, 158, 1, 3953 }, >+ { 1904, 1, 158, 1, 3953 }, >+ { 123, 1, 158, 1, 3953 }, >+ { 336, 1, 158, 1, 3953 }, >+ { 1259, 128, 1, 0, 1216 }, >+ { 172, 1, 233, 1, 1826 }, >+ { 385, 1, 134, 1, 1826 }, >+ { 557, 1, 134, 1, 1826 }, >+ { 723, 1, 134, 1, 1826 }, >+ { 196, 1, 1, 1, 3921 }, >+ { 409, 1, 1, 1, 3921 }, >+ { 578, 1, 1, 1, 3921 }, >+ { 736, 1, 1, 1, 3921 }, >+ { 1299, 1, 1, 1, 3921 }, >+ { 1433, 1, 1, 1, 3921 }, >+ { 1563, 1, 1, 1, 3921 }, >+ { 1693, 1, 1, 1, 3921 }, >+ { 1818, 1, 1, 1, 3921 }, >+ { 1956, 1, 1, 1, 3921 }, >+ { 35, 1, 1, 1, 3921 }, >+ { 248, 1, 1, 1, 3921 }, >+ { 461, 1, 1, 1, 3921 }, >+ { 627, 1, 1, 1, 3921 }, >+ { 785, 1, 1, 1, 3921 }, >+ { 1348, 1, 1, 1, 3921 }, >+ { 1478, 1, 1, 1, 3921 }, >+ { 1608, 1, 1, 1, 3921 }, >+ { 1738, 1, 1, 1, 3921 }, >+ { 1860, 1, 1, 1, 3921 }, >+ { 82, 1, 1, 1, 3921 }, >+ { 295, 1, 1, 1, 3921 }, >+ { 508, 1, 1, 1, 3921 }, >+ { 674, 1, 1, 1, 3921 }, >+ { 832, 1, 1, 1, 3921 }, >+ { 1395, 1, 1, 1, 3921 }, >+ { 1525, 1, 1, 1, 3921 }, >+ { 1655, 1, 1, 1, 3921 }, >+ { 1785, 1, 1, 1, 3921 }, >+ { 1923, 1, 1, 1, 3921 }, >+ { 142, 1, 1, 1, 3921 }, >+ { 355, 1, 1, 1, 3921 }, >+ { 176, 1, 100, 1, 3921 }, >+ { 389, 1, 100, 1, 3921 }, >+ { 184, 1, 229, 1, 1794 }, >+ { 397, 1, 126, 1, 1794 }, >+ { 566, 1, 126, 1, 1794 }, >+ { 727, 1, 126, 1, 1794 }, >+ { 179, 1, 1, 1, 3889 }, >+ { 392, 1, 1, 1, 3889 }, >+ { 561, 1, 1, 1, 3889 }, >+ { 188, 1, 1, 1, 3889 }, >+ { 401, 1, 1, 1, 3889 }, >+ { 570, 1, 1, 1, 3889 }, >+ { 1239, 124, 1, 0, 1248 }, >+ { 201, 1, 98, 1, 3857 }, >+ { 414, 1, 98, 1, 3857 }, >+ { 583, 1, 98, 1, 3857 }, >+ { 741, 1, 98, 1, 3857 }, >+ { 1304, 1, 98, 1, 3857 }, >+ { 1438, 1, 98, 1, 3857 }, >+ { 1568, 1, 98, 1, 3857 }, >+ { 1698, 1, 98, 1, 3857 }, >+ { 1265, 122, 1, 0, 1280 }, >+ { 204, 1, 96, 1, 3825 }, >+ { 417, 1, 96, 1, 3825 }, >+ { 586, 1, 96, 1, 3825 }, >+ { 744, 1, 96, 1, 3825 }, >+ { 1307, 1, 96, 1, 3825 }, >+ { 1441, 1, 96, 1, 3825 }, >+ { 1571, 1, 96, 1, 3825 }, >+ { 1701, 1, 96, 1, 3825 }, >+ { 1823, 1, 96, 1, 3825 }, >+ { 1961, 1, 96, 1, 3825 }, >+ { 207, 1, 96, 1, 3825 }, >+ { 420, 1, 96, 1, 3825 }, >+ { 210, 92, 1, 8, 1425 }, >+ { 423, 92, 1, 8, 1425 }, >+ { 589, 92, 1, 8, 1425 }, >+ { 747, 92, 1, 8, 1425 }, >+ { 1310, 92, 1, 8, 1425 }, >+ { 1444, 92, 1, 8, 1425 }, >+ { 1574, 92, 1, 8, 1425 }, >+ { 1704, 92, 1, 8, 1425 }, >+ { 1826, 92, 1, 8, 1425 }, >+ { 1964, 92, 1, 8, 1425 }, >+ { 41, 92, 1, 8, 1425 }, >+ { 254, 92, 1, 8, 1425 }, >+ { 467, 92, 1, 8, 1425 }, >+ { 633, 92, 1, 8, 1425 }, >+ { 791, 92, 1, 8, 1425 }, >+ { 1354, 92, 1, 8, 1425 }, >+ { 1484, 92, 1, 8, 1425 }, >+ { 1614, 92, 1, 8, 1425 }, >+ { 1744, 92, 1, 8, 1425 }, >+ { 1866, 92, 1, 8, 1425 }, >+ { 88, 92, 1, 8, 1425 }, >+ { 301, 92, 1, 8, 1425 }, >+ { 514, 92, 1, 8, 1425 }, >+ { 680, 92, 1, 8, 1425 }, >+ { 838, 92, 1, 8, 1425 }, >+ { 1401, 92, 1, 8, 1425 }, >+ { 1531, 92, 1, 8, 1425 }, >+ { 1661, 92, 1, 8, 1425 }, >+ { 1791, 92, 1, 8, 1425 }, >+ { 1929, 92, 1, 8, 1425 }, >+ { 148, 92, 1, 8, 1425 }, >+ { 361, 92, 1, 8, 1425 }, >+ { 1245, 118, 1, 0, 1921 }, >+ { 869, 118, 1, 0, 1921 }, >+ { 947, 118, 1, 0, 1921 }, >+ { 997, 118, 1, 0, 1921 }, >+ { 1035, 118, 1, 0, 1921 }, >+ { 875, 130, 1, 12, 656 }, >+ { 882, 93, 159, 9, 1377 }, >+ { 953, 93, 159, 9, 1377 }, >+ { 1003, 93, 159, 9, 1377 }, >+ { 1041, 93, 159, 9, 1377 }, >+ { 1073, 93, 159, 9, 1377 }, >+ { 1105, 93, 159, 9, 1377 }, >+ { 1137, 93, 159, 9, 1377 }, >+ { 1169, 93, 159, 9, 1377 }, >+ { 1201, 93, 159, 9, 1377 }, >+ { 1227, 93, 159, 9, 1377 }, >+ { 848, 93, 159, 9, 1377 }, >+ { 926, 93, 159, 9, 1377 }, >+ { 983, 93, 159, 9, 1377 }, >+ { 1021, 93, 159, 9, 1377 }, >+ { 1059, 93, 159, 9, 1377 }, >+ { 1091, 93, 159, 9, 1377 }, >+ { 1123, 93, 159, 9, 1377 }, >+ { 1155, 93, 159, 9, 1377 }, >+ { 1187, 93, 159, 9, 1377 }, >+ { 1213, 93, 159, 9, 1377 }, >+ { 855, 93, 159, 9, 1377 }, >+ { 933, 93, 159, 9, 1377 }, >+ { 990, 93, 159, 9, 1377 }, >+ { 1028, 93, 159, 9, 1377 }, >+ { 1066, 93, 159, 9, 1377 }, >+ { 1098, 93, 159, 9, 1377 }, >+ { 1130, 93, 159, 9, 1377 }, >+ { 1162, 93, 159, 9, 1377 }, >+ { 1194, 93, 159, 9, 1377 }, >+ { 1220, 93, 159, 9, 1377 }, >+ { 862, 93, 159, 9, 1377 }, >+ { 940, 93, 159, 9, 1377 }, >+ { 1870, 1, 116, 1, 1120 }, >+ { 888, 138, 235, 0, 1344 }, >+ { 895, 152, 1, 0, 2241 }, >+ { 959, 152, 1, 0, 2241 }, >+ { 901, 152, 231, 0, 1312 }, >+ { 908, 154, 1, 0, 2273 }, >+ { 965, 154, 1, 0, 2273 }, >+ { 1009, 154, 1, 0, 2273 }, >+ { 1047, 154, 1, 0, 2273 }, >+ { 1079, 154, 1, 0, 2273 }, >+ { 1111, 154, 1, 0, 2273 }, >+ { 1143, 154, 1, 0, 2273 }, >+ { 1175, 154, 1, 0, 2273 }, >+ { 914, 156, 1, 0, 2273 }, >+ { 971, 156, 1, 0, 2273 }, >+ { 1015, 156, 1, 0, 2273 }, >+ { 1053, 156, 1, 0, 2273 }, >+ { 1085, 156, 1, 0, 2273 }, >+ { 1117, 156, 1, 0, 2273 }, >+ { 1149, 156, 1, 0, 2273 }, >+ { 1181, 156, 1, 0, 2273 }, >+ { 1207, 156, 1, 0, 2273 }, >+ { 1233, 156, 1, 0, 2273 }, >+ { 920, 156, 1, 0, 2273 }, >+ { 977, 156, 1, 0, 2273 }, >+}; >+ >+ static const MCPhysReg OddSP[] = { >+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP Bit set. >+ static const uint8_t OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // CCR Register Class... >+ static const MCPhysReg CCR[] = { >+ Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31, >+ }; >+ >+ // CCR Bit set. >+ static const uint8_t CCRBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // COP2 Register Class... >+ static const MCPhysReg COP2[] = { >+ Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231, >+ }; >+ >+ // COP2 Bit set. >+ static const uint8_t COP2Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01, >+ }; >+ >+ // COP3 Register Class... >+ static const MCPhysReg COP3[] = { >+ Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331, >+ }; >+ >+ // COP3 Bit set. >+ static const uint8_t COP3Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f, >+ }; >+ >+ // DSPR Register Class... >+ static const MCPhysReg DSPR[] = { >+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, >+ }; >+ >+ // DSPR Bit set. >+ static const uint8_t DSPRBits[] = { >+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, >+ }; >+ >+ // FGR32 Register Class... >+ static const MCPhysReg FGR32[] = { >+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, >+ }; >+ >+ // FGR32 Bit set. >+ static const uint8_t FGR32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // FGRCC Register Class... >+ static const MCPhysReg FGRCC[] = { >+ Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31, >+ }; >+ >+ // FGRCC Bit set. >+ static const uint8_t FGRCCBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // FGRH32 Register Class... >+ static const MCPhysReg FGRH32[] = { >+ Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31, >+ }; >+ >+ // FGRH32 Bit set. >+ static const uint8_t FGRH32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, >+ }; >+ >+ // GPR32 Register Class... >+ static const MCPhysReg GPR32[] = { >+ Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA, >+ }; >+ >+ // GPR32 Bit set. >+ static const uint8_t GPR32Bits[] = { >+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, >+ }; >+ >+ // HWRegs Register Class... >+ static const MCPhysReg HWRegs[] = { >+ Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31, >+ }; >+ >+ // HWRegs Bit set. >+ static const uint8_t HWRegsBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, >+ }; >+ >+ // OddSP_with_sub_hi Register Class... >+ static const MCPhysReg OddSP_with_sub_hi[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP_with_sub_hi Bit set. >+ static const uint8_t OddSP_with_sub_hiBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // FGR32_and_OddSP Register Class... >+ static const MCPhysReg FGR32_and_OddSP[] = { >+ Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, >+ }; >+ >+ // FGR32_and_OddSP Bit set. >+ static const uint8_t FGR32_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, >+ }; >+ >+ // FGRH32_and_OddSP Register Class... >+ static const MCPhysReg FGRH32_and_OddSP[] = { >+ Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, >+ }; >+ >+ // FGRH32_and_OddSP Bit set. >+ static const uint8_t FGRH32_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... >+ static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { >+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. >+ static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // CPU16RegsPlusSP Register Class... >+ static const MCPhysReg CPU16RegsPlusSP[] = { >+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP, >+ }; >+ >+ // CPU16RegsPlusSP Bit set. >+ static const uint8_t CPU16RegsPlusSPBits[] = { >+ 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // CC Register Class... >+ static const MCPhysReg CC[] = { >+ Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7, >+ }; >+ >+ // CC Bit set. >+ static const uint8_t CCBits[] = { >+ 0x00, 0x00, 0x00, 0x80, 0x7f, >+ }; >+ >+ // CPU16Regs Register Class... >+ static const MCPhysReg CPU16Regs[] = { >+ Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, >+ }; >+ >+ // CPU16Regs Bit set. >+ static const uint8_t CPU16RegsBits[] = { >+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, >+ }; >+ >+ // FCC Register Class... >+ static const MCPhysReg FCC[] = { >+ Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7, >+ }; >+ >+ // FCC Bit set. >+ static const uint8_t FCCBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, >+ }; >+ >+ // MSACtrl Register Class... >+ static const MCPhysReg MSACtrl[] = { >+ Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap, >+ }; >+ >+ // MSACtrl Bit set. >+ static const uint8_t MSACtrlBits[] = { >+ 0x00, 0xfc, 0x03, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... >+ static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, >+ }; >+ >+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. >+ static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // HI32DSP Register Class... >+ static const MCPhysReg HI32DSP[] = { >+ Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3, >+ }; >+ >+ // HI32DSP Bit set. >+ static const uint8_t HI32DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, >+ }; >+ >+ // LO32DSP Register Class... >+ static const MCPhysReg LO32DSP[] = { >+ Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3, >+ }; >+ >+ // LO32DSP Bit set. >+ static const uint8_t LO32DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, >+ }; >+ >+ // CPURAReg Register Class... >+ static const MCPhysReg CPURAReg[] = { >+ Mips_RA, >+ }; >+ >+ // CPURAReg Bit set. >+ static const uint8_t CPURARegBits[] = { >+ 0x00, 0x00, 0x08, >+ }; >+ >+ // CPUSPReg Register Class... >+ static const MCPhysReg CPUSPReg[] = { >+ Mips_SP, >+ }; >+ >+ // CPUSPReg Bit set. >+ static const uint8_t CPUSPRegBits[] = { >+ 0x00, 0x00, 0x10, >+ }; >+ >+ // DSPCC Register Class... >+ static const MCPhysReg DSPCC[] = { >+ Mips_DSPCCond, >+ }; >+ >+ // DSPCC Bit set. >+ static const uint8_t DSPCCBits[] = { >+ 0x04, >+ }; >+ >+ // HI32 Register Class... >+ static const MCPhysReg HI32[] = { >+ Mips_HI0, >+ }; >+ >+ // HI32 Bit set. >+ static const uint8_t HI32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // LO32 Register Class... >+ static const MCPhysReg LO32[] = { >+ Mips_LO0, >+ }; >+ >+ // LO32 Bit set. >+ static const uint8_t LO32Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, >+ }; >+ >+ // FGR64 Register Class... >+ static const MCPhysReg FGR64[] = { >+ Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64, >+ }; >+ >+ // FGR64 Bit set. >+ static const uint8_t FGR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, >+ }; >+ >+ // GPR64 Register Class... >+ static const MCPhysReg GPR64[] = { >+ Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64, >+ }; >+ >+ // GPR64 Bit set. >+ static const uint8_t GPR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, >+ }; >+ >+ // AFGR64 Register Class... >+ static const MCPhysReg AFGR64[] = { >+ Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15, >+ }; >+ >+ // AFGR64 Bit set. >+ static const uint8_t AFGR64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, >+ }; >+ >+ // FGR64_and_OddSP Register Class... >+ static const MCPhysReg FGR64_and_OddSP[] = { >+ Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64, >+ }; >+ >+ // FGR64_and_OddSP Bit set. >+ static const uint8_t FGR64_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... >+ static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { >+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. >+ static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, >+ }; >+ >+ // AFGR64_and_OddSP Register Class... >+ static const MCPhysReg AFGR64_and_OddSP[] = { >+ Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, >+ }; >+ >+ // AFGR64_and_OddSP Bit set. >+ static const uint8_t AFGR64_and_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs Register Class... >+ static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { >+ Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPU16Regs Bit set. >+ static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, >+ }; >+ >+ // ACC64DSP Register Class... >+ static const MCPhysReg ACC64DSP[] = { >+ Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3, >+ }; >+ >+ // ACC64DSP Bit set. >+ static const uint8_t ACC64DSPBits[] = { >+ 0x00, 0x00, 0x00, 0x3c, >+ }; >+ >+ // OCTEON_MPL Register Class... >+ static const MCPhysReg OCTEON_MPL[] = { >+ Mips_MPL0, Mips_MPL1, Mips_MPL2, >+ }; >+ >+ // OCTEON_MPL Bit set. >+ static const uint8_t OCTEON_MPLBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, >+ }; >+ >+ // OCTEON_P Register Class... >+ static const MCPhysReg OCTEON_P[] = { >+ Mips_P0, Mips_P1, Mips_P2, >+ }; >+ >+ // OCTEON_P Bit set. >+ static const uint8_t OCTEON_PBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, >+ }; >+ >+ // ACC64 Register Class... >+ static const MCPhysReg ACC64[] = { >+ Mips_AC0, >+ }; >+ >+ // ACC64 Bit set. >+ static const uint8_t ACC64Bits[] = { >+ 0x00, 0x00, 0x00, 0x04, >+ }; >+ >+ // GPR64_with_sub_32_in_CPURAReg Register Class... >+ static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { >+ Mips_RA_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPURAReg Bit set. >+ static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // GPR64_with_sub_32_in_CPUSPReg Register Class... >+ static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { >+ Mips_SP_64, >+ }; >+ >+ // GPR64_with_sub_32_in_CPUSPReg Bit set. >+ static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, >+ }; >+ >+ // HI64 Register Class... >+ static const MCPhysReg HI64[] = { >+ Mips_HI0_64, >+ }; >+ >+ // HI64 Bit set. >+ static const uint8_t HI64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, >+ }; >+ >+ // LO64 Register Class... >+ static const MCPhysReg LO64[] = { >+ Mips_LO0_64, >+ }; >+ >+ // LO64 Bit set. >+ static const uint8_t LO64Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, >+ }; >+ >+ // MSA128B Register Class... >+ static const MCPhysReg MSA128B[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128B Bit set. >+ static const uint8_t MSA128BBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128D Register Class... >+ static const MCPhysReg MSA128D[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128D Bit set. >+ static const uint8_t MSA128DBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128H Register Class... >+ static const MCPhysReg MSA128H[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128H Bit set. >+ static const uint8_t MSA128HBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128W Register Class... >+ static const MCPhysReg MSA128W[] = { >+ Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31, >+ }; >+ >+ // MSA128W Bit set. >+ static const uint8_t MSA128WBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, >+ }; >+ >+ // MSA128B_with_sub_64_in_OddSP Register Class... >+ static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { >+ Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31, >+ }; >+ >+ // MSA128B_with_sub_64_in_OddSP Bit set. >+ static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, >+ }; >+ >+ // ACC128 Register Class... >+ static const MCPhysReg ACC128[] = { >+ Mips_AC0_64, >+ }; >+ >+ // ACC128 Bit set. >+ static const uint8_t ACC128Bits[] = { >+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, >+ }; >+ >+static const MCRegisterClass MipsMCRegisterClasses[] = { >+ { "OddSP", OddSP, OddSPBits, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 }, >+ { "CCR", CCR, CCRBits, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 }, >+ { "COP2", COP2, COP2Bits, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 }, >+ { "COP3", COP3, COP3Bits, 32, sizeof(COP3Bits), Mips_COP3RegClassID, 4, 4, 1, 0 }, >+ { "DSPR", DSPR, DSPRBits, 32, sizeof(DSPRBits), Mips_DSPRRegClassID, 4, 4, 1, 1 }, >+ { "FGR32", FGR32, FGR32Bits, 32, sizeof(FGR32Bits), Mips_FGR32RegClassID, 4, 4, 1, 1 }, >+ { "FGRCC", FGRCC, FGRCCBits, 32, sizeof(FGRCCBits), Mips_FGRCCRegClassID, 4, 4, 1, 1 }, >+ { "FGRH32", FGRH32, FGRH32Bits, 32, sizeof(FGRH32Bits), Mips_FGRH32RegClassID, 4, 4, 1, 0 }, >+ { "GPR32", GPR32, GPR32Bits, 32, sizeof(GPR32Bits), Mips_GPR32RegClassID, 4, 4, 1, 1 }, >+ { "HWRegs", HWRegs, HWRegsBits, 32, sizeof(HWRegsBits), Mips_HWRegsRegClassID, 4, 4, 1, 0 }, >+ { "OddSP_with_sub_hi", OddSP_with_sub_hi, OddSP_with_sub_hiBits, 24, sizeof(OddSP_with_sub_hiBits), Mips_OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 }, >+ { "FGR32_and_OddSP", FGR32_and_OddSP, FGR32_and_OddSPBits, 16, sizeof(FGR32_and_OddSPBits), Mips_FGR32_and_OddSPRegClassID, 4, 4, 1, 1 }, >+ { "FGRH32_and_OddSP", FGRH32_and_OddSP, FGRH32_and_OddSPBits, 16, sizeof(FGRH32_and_OddSPBits), Mips_FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 }, >+ { "OddSP_with_sub_hi_with_sub_hi_in_FGRH32", OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 }, >+ { "CPU16RegsPlusSP", CPU16RegsPlusSP, CPU16RegsPlusSPBits, 9, sizeof(CPU16RegsPlusSPBits), Mips_CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 }, >+ { "CC", CC, CCBits, 8, sizeof(CCBits), Mips_CCRegClassID, 4, 4, 1, 0 }, >+ { "CPU16Regs", CPU16Regs, CPU16RegsBits, 8, sizeof(CPU16RegsBits), Mips_CPU16RegsRegClassID, 4, 4, 1, 1 }, >+ { "FCC", FCC, FCCBits, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 }, >+ { "MSACtrl", MSACtrl, MSACtrlBits, 8, sizeof(MSACtrlBits), Mips_MSACtrlRegClassID, 4, 4, 1, 1 }, >+ { "OddSP_with_sub_hi_with_sub_hi_in_FGR32", OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 }, >+ { "HI32DSP", HI32DSP, HI32DSPBits, 4, sizeof(HI32DSPBits), Mips_HI32DSPRegClassID, 4, 4, 1, 1 }, >+ { "LO32DSP", LO32DSP, LO32DSPBits, 4, sizeof(LO32DSPBits), Mips_LO32DSPRegClassID, 4, 4, 1, 1 }, >+ { "CPURAReg", CPURAReg, CPURARegBits, 1, sizeof(CPURARegBits), Mips_CPURARegRegClassID, 4, 4, 1, 0 }, >+ { "CPUSPReg", CPUSPReg, CPUSPRegBits, 1, sizeof(CPUSPRegBits), Mips_CPUSPRegRegClassID, 4, 4, 1, 0 }, >+ { "DSPCC", DSPCC, DSPCCBits, 1, sizeof(DSPCCBits), Mips_DSPCCRegClassID, 4, 4, 1, 1 }, >+ { "HI32", HI32, HI32Bits, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 }, >+ { "LO32", LO32, LO32Bits, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 }, >+ { "FGR64", FGR64, FGR64Bits, 32, sizeof(FGR64Bits), Mips_FGR64RegClassID, 8, 8, 1, 1 }, >+ { "GPR64", GPR64, GPR64Bits, 32, sizeof(GPR64Bits), Mips_GPR64RegClassID, 8, 8, 1, 1 }, >+ { "AFGR64", AFGR64, AFGR64Bits, 16, sizeof(AFGR64Bits), Mips_AFGR64RegClassID, 8, 8, 1, 1 }, >+ { "FGR64_and_OddSP", FGR64_and_OddSP, FGR64_and_OddSPBits, 16, sizeof(FGR64_and_OddSPBits), Mips_FGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, >+ { "GPR64_with_sub_32_in_CPU16RegsPlusSP", GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 }, >+ { "AFGR64_and_OddSP", AFGR64_and_OddSP, AFGR64_and_OddSPBits, 8, sizeof(AFGR64_and_OddSPBits), Mips_AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, >+ { "GPR64_with_sub_32_in_CPU16Regs", GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 }, >+ { "ACC64DSP", ACC64DSP, ACC64DSPBits, 4, sizeof(ACC64DSPBits), Mips_ACC64DSPRegClassID, 8, 8, 1, 1 }, >+ { "OCTEON_MPL", OCTEON_MPL, OCTEON_MPLBits, 3, sizeof(OCTEON_MPLBits), Mips_OCTEON_MPLRegClassID, 8, 8, 1, 0 }, >+ { "OCTEON_P", OCTEON_P, OCTEON_PBits, 3, sizeof(OCTEON_PBits), Mips_OCTEON_PRegClassID, 8, 8, 1, 0 }, >+ { "ACC64", ACC64, ACC64Bits, 1, sizeof(ACC64Bits), Mips_ACC64RegClassID, 8, 8, 1, 1 }, >+ { "GPR64_with_sub_32_in_CPURAReg", GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips_GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 }, >+ { "GPR64_with_sub_32_in_CPUSPReg", GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 }, >+ { "HI64", HI64, HI64Bits, 1, sizeof(HI64Bits), Mips_HI64RegClassID, 8, 8, 1, 1 }, >+ { "LO64", LO64, LO64Bits, 1, sizeof(LO64Bits), Mips_LO64RegClassID, 8, 8, 1, 1 }, >+ { "MSA128B", MSA128B, MSA128BBits, 32, sizeof(MSA128BBits), Mips_MSA128BRegClassID, 16, 16, 1, 1 }, >+ { "MSA128D", MSA128D, MSA128DBits, 32, sizeof(MSA128DBits), Mips_MSA128DRegClassID, 16, 16, 1, 1 }, >+ { "MSA128H", MSA128H, MSA128HBits, 32, sizeof(MSA128HBits), Mips_MSA128HRegClassID, 16, 16, 1, 1 }, >+ { "MSA128W", MSA128W, MSA128WBits, 32, sizeof(MSA128WBits), Mips_MSA128WRegClassID, 16, 16, 1, 1 }, >+ { "MSA128B_with_sub_64_in_OddSP", MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips_MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 }, >+ { "ACC128", ACC128, ACC128Bits, 1, sizeof(ACC128Bits), Mips_ACC128RegClassID, 16, 16, 1, 1 }, >+}; >+ >+#endif // GET_REGINFO_MC_DESC >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..0cba4db9cb689c6b3753efc8f1b4bdedd857f94a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsGenSubtargetInfo.inc >@@ -0,0 +1,52 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Subtarget Enumeration Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+ >+#ifdef GET_SUBTARGETINFO_ENUM >+#undef GET_SUBTARGETINFO_ENUM >+ >+#define Mips_FeatureCnMips (1ULL << 0) >+#define Mips_FeatureDSP (1ULL << 1) >+#define Mips_FeatureDSPR2 (1ULL << 2) >+#define Mips_FeatureEABI (1ULL << 3) >+#define Mips_FeatureFP64Bit (1ULL << 4) >+#define Mips_FeatureFPXX (1ULL << 5) >+#define Mips_FeatureGP64Bit (1ULL << 6) >+#define Mips_FeatureMSA (1ULL << 7) >+#define Mips_FeatureMicroMips (1ULL << 8) >+#define Mips_FeatureMips1 (1ULL << 9) >+#define Mips_FeatureMips2 (1ULL << 10) >+#define Mips_FeatureMips3 (1ULL << 11) >+#define Mips_FeatureMips3_32 (1ULL << 12) >+#define Mips_FeatureMips3_32r2 (1ULL << 13) >+#define Mips_FeatureMips4 (1ULL << 14) >+#define Mips_FeatureMips4_32 (1ULL << 15) >+#define Mips_FeatureMips4_32r2 (1ULL << 16) >+#define Mips_FeatureMips5 (1ULL << 17) >+#define Mips_FeatureMips5_32r2 (1ULL << 18) >+#define Mips_FeatureMips16 (1ULL << 19) >+#define Mips_FeatureMips32 (1ULL << 20) >+#define Mips_FeatureMips32r2 (1ULL << 21) >+#define Mips_FeatureMips32r6 (1ULL << 22) >+#define Mips_FeatureMips64 (1ULL << 23) >+#define Mips_FeatureMips64r2 (1ULL << 24) >+#define Mips_FeatureMips64r6 (1ULL << 25) >+#define Mips_FeatureN32 (1ULL << 26) >+#define Mips_FeatureN64 (1ULL << 27) >+#define Mips_FeatureNaN2008 (1ULL << 28) >+#define Mips_FeatureNoABICalls (1ULL << 29) >+#define Mips_FeatureNoOddSPReg (1ULL << 30) >+#define Mips_FeatureO32 (1ULL << 31) >+#define Mips_FeatureSingleFloat (1ULL << 32) >+#define Mips_FeatureVFPU (1ULL << 33) >+ >+#endif // GET_SUBTARGETINFO_ENUM >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c b/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c >new file mode 100644 >index 0000000000000000000000000000000000000000..f57588f04e8793c657afddd949c3daa0a62a6709 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.c >@@ -0,0 +1,424 @@ >+//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints an Mips MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <platform.h> >+#include <stdlib.h> >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "MipsInstPrinter.h" >+#include "../../MCInst.h" >+#include "../../utils.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "MipsMapping.h" >+ >+#include "MipsInstPrinter.h" >+ >+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O); >+static char *printAliasInstr(MCInst *MI, SStream *O, void *info); >+static char *printAlias(MCInst *MI, SStream *OS); >+ >+// These enumeration declarations were originally in MipsInstrInfo.h but >+// had to be moved here to avoid circular dependencies between >+// LLVMMipsCodeGen and LLVMMipsAsmPrinter. >+ >+// Mips Condition Codes >+typedef enum Mips_CondCode { >+ // To be used with float branch True >+ Mips_FCOND_F, >+ Mips_FCOND_UN, >+ Mips_FCOND_OEQ, >+ Mips_FCOND_UEQ, >+ Mips_FCOND_OLT, >+ Mips_FCOND_ULT, >+ Mips_FCOND_OLE, >+ Mips_FCOND_ULE, >+ Mips_FCOND_SF, >+ Mips_FCOND_NGLE, >+ Mips_FCOND_SEQ, >+ Mips_FCOND_NGL, >+ Mips_FCOND_LT, >+ Mips_FCOND_NGE, >+ Mips_FCOND_LE, >+ Mips_FCOND_NGT, >+ >+ // To be used with float branch False >+ // This conditions have the same mnemonic as the >+ // above ones, but are used with a branch False; >+ Mips_FCOND_T, >+ Mips_FCOND_OR, >+ Mips_FCOND_UNE, >+ Mips_FCOND_ONE, >+ Mips_FCOND_UGE, >+ Mips_FCOND_OGE, >+ Mips_FCOND_UGT, >+ Mips_FCOND_OGT, >+ Mips_FCOND_ST, >+ Mips_FCOND_GLE, >+ Mips_FCOND_SNE, >+ Mips_FCOND_GL, >+ Mips_FCOND_NLT, >+ Mips_FCOND_GE, >+ Mips_FCOND_NLE, >+ Mips_FCOND_GT >+} Mips_CondCode; >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+static const char *getRegisterName(unsigned RegNo); >+static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI); >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ MI->csh->doing_mem = status; >+ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ if (status) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; >+ } else { >+ // done, create the next operand slot >+ MI->flat_insn->detail->mips.op_count++; >+ } >+} >+ >+static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) >+{ >+ return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) && >+ MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R); >+} >+ >+static const char* MipsFCCToString(Mips_CondCode CC) >+{ >+ switch (CC) { >+ default: return 0; // never reach >+ case Mips_FCOND_F: >+ case Mips_FCOND_T: return "f"; >+ case Mips_FCOND_UN: >+ case Mips_FCOND_OR: return "un"; >+ case Mips_FCOND_OEQ: >+ case Mips_FCOND_UNE: return "eq"; >+ case Mips_FCOND_UEQ: >+ case Mips_FCOND_ONE: return "ueq"; >+ case Mips_FCOND_OLT: >+ case Mips_FCOND_UGE: return "olt"; >+ case Mips_FCOND_ULT: >+ case Mips_FCOND_OGE: return "ult"; >+ case Mips_FCOND_OLE: >+ case Mips_FCOND_UGT: return "ole"; >+ case Mips_FCOND_ULE: >+ case Mips_FCOND_OGT: return "ule"; >+ case Mips_FCOND_SF: >+ case Mips_FCOND_ST: return "sf"; >+ case Mips_FCOND_NGLE: >+ case Mips_FCOND_GLE: return "ngle"; >+ case Mips_FCOND_SEQ: >+ case Mips_FCOND_SNE: return "seq"; >+ case Mips_FCOND_NGL: >+ case Mips_FCOND_GL: return "ngl"; >+ case Mips_FCOND_LT: >+ case Mips_FCOND_NLT: return "lt"; >+ case Mips_FCOND_NGE: >+ case Mips_FCOND_GE: return "nge"; >+ case Mips_FCOND_LE: >+ case Mips_FCOND_NLE: return "le"; >+ case Mips_FCOND_NGT: >+ case Mips_FCOND_GT: return "ngt"; >+ } >+} >+ >+static void printRegName(SStream *OS, unsigned RegNo) >+{ >+ SStream_concat(OS, "$%s", getRegisterName(RegNo)); >+} >+ >+void Mips_printInst(MCInst *MI, SStream *O, void *info) >+{ >+ char *mnem; >+ >+ switch (MCInst_getOpcode(MI)) { >+ default: break; >+ case Mips_Save16: >+ case Mips_SaveX16: >+ case Mips_Restore16: >+ case Mips_RestoreX16: >+ return; >+ } >+ >+ // Try to print any aliases first. >+ mnem = printAliasInstr(MI, O, info); >+ if (!mnem) { >+ mnem = printAlias(MI, O); >+ if (!mnem) { >+ printInstruction(MI, O, NULL); >+ } >+ } >+ >+ if (mnem) { >+ // fixup instruction id due to the change in alias instruction >+ MCInst_setOpcodePub(MI, Mips_map_insn(mnem)); >+ cs_mem_free(mnem); >+ } >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op; >+ >+ if (OpNo >= MI->size) >+ return; >+ >+ Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ unsigned int reg = MCOperand_getReg(Op); >+ printRegName(O, reg); >+ reg = Mips_map_register(reg); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg; >+ } else { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ int64_t imm = MCOperand_getImm(Op); >+ if (MI->csh->doing_mem) { >+ if (imm) { // only print Imm offset if it is not 0 >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "-%"PRIu64, -imm); >+ } >+ } >+ if (MI->csh->detail) >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; >+ } else { >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "-%"PRIu64, -imm); >+ } >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } >+ } >+} >+ >+static void printUnsignedImm(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ if (MCOperand_isImm(MO)) { >+ int64_t imm = MCOperand_getImm(MO); >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", (unsigned short int)imm); >+ else >+ SStream_concat(O, "%u", (unsigned short int)imm); >+ } else { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%x", (short int)-imm); >+ else >+ SStream_concat(O, "-%u", (short int)-imm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } else >+ printOperand(MI, opNum, O); >+} >+ >+static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ if (MCOperand_isImm(MO)) { >+ uint8_t imm = (uint8_t)MCOperand_getImm(MO); >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%x", imm); >+ else >+ SStream_concat(O, "%u", imm); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM; >+ MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm; >+ MI->flat_insn->detail->mips.op_count++; >+ } >+ } else >+ printOperand(MI, opNum, O); >+} >+ >+static void printMemOperand(MCInst *MI, int opNum, SStream *O) >+{ >+ // Load/Store memory operands -- imm($reg) >+ // If PIC target the target is loaded as the >+ // pattern lw $25,%call16($28) >+ set_mem_access(MI, true); >+ printOperand(MI, opNum + 1, O); >+ SStream_concat0(O, "("); >+ printOperand(MI, opNum, O); >+ SStream_concat0(O, ")"); >+ set_mem_access(MI, false); >+} >+ >+// TODO??? >+static void printMemOperandEA(MCInst *MI, int opNum, SStream *O) >+{ >+ // when using stack locations for not load/store instructions >+ // print the same way as all normal 3 operand instructions. >+ printOperand(MI, opNum, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, opNum + 1, O); >+ return; >+} >+ >+static void printFCCOperand(MCInst *MI, int opNum, SStream *O) >+{ >+ MCOperand *MO = MCInst_getOperand(MI, opNum); >+ SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO))); >+} >+ >+static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS) >+{ >+ SStream_concat(OS, "%s\t", Str); >+ printOperand(MI, OpNo, OS); >+ return cs_strdup(Str); >+} >+ >+static char *printAlias2(const char *Str, MCInst *MI, >+ unsigned OpNo0, unsigned OpNo1, SStream *OS) >+{ >+ char *tmp; >+ >+ tmp = printAlias1(Str, MI, OpNo0, OS); >+ SStream_concat0(OS, ", "); >+ printOperand(MI, OpNo1, OS); >+ >+ return tmp; >+} >+ >+#define GET_REGINFO_ENUM >+#include "MipsGenRegisterInfo.inc" >+ >+static char *printAlias(MCInst *MI, SStream *OS) >+{ >+ switch (MCInst_getOpcode(MI)) { >+ case Mips_BEQ: >+ // beq $zero, $zero, $L2 => b $L2 >+ // beq $r0, $zero, $L2 => beqz $r0, $L2 >+ if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) >+ return printAlias1("b", MI, 2, OS); >+ if (isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("beqz", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BEQL: >+ // beql $r0, $zero, $L2 => beqzl $r0, $L2 >+ if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("beqzl", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BEQ64: >+ // beq $r0, $zero, $L2 => beqz $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO_64)) >+ return printAlias2("beqz", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BNE: >+ // bne $r0, $zero, $L2 => bnez $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("bnez", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BNEL: >+ // bnel $r0, $zero, $L2 => bnezl $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO)) >+ return printAlias2("bnezl", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BNE64: >+ // bne $r0, $zero, $L2 => bnez $r0, $L2 >+ if (isReg(MI, 1, Mips_ZERO_64)) >+ return printAlias2("bnez", MI, 0, 2, OS); >+ return NULL; >+ case Mips_BGEZAL: >+ // bgezal $zero, $L1 => bal $L1 >+ if (isReg(MI, 0, Mips_ZERO)) >+ return printAlias1("bal", MI, 1, OS); >+ return NULL; >+ case Mips_BC1T: >+ // bc1t $fcc0, $L1 => bc1t $L1 >+ if (isReg(MI, 0, Mips_FCC0)) >+ return printAlias1("bc1t", MI, 1, OS); >+ return NULL; >+ case Mips_BC1F: >+ // bc1f $fcc0, $L1 => bc1f $L1 >+ if (isReg(MI, 0, Mips_FCC0)) >+ return printAlias1("bc1f", MI, 1, OS); >+ return NULL; >+ case Mips_JALR: >+ // jalr $ra, $r1 => jalr $r1 >+ if (isReg(MI, 0, Mips_RA)) >+ return printAlias1("jalr", MI, 1, OS); >+ return NULL; >+ case Mips_JALR64: >+ // jalr $ra, $r1 => jalr $r1 >+ if (isReg(MI, 0, Mips_RA_64)) >+ return printAlias1("jalr", MI, 1, OS); >+ return NULL; >+ case Mips_NOR: >+ case Mips_NOR_MM: >+ // nor $r0, $r1, $zero => not $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO)) >+ return printAlias2("not", MI, 0, 1, OS); >+ return NULL; >+ case Mips_NOR64: >+ // nor $r0, $r1, $zero => not $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO_64)) >+ return printAlias2("not", MI, 0, 1, OS); >+ return NULL; >+ case Mips_OR: >+ // or $r0, $r1, $zero => move $r0, $r1 >+ if (isReg(MI, 2, Mips_ZERO)) >+ return printAlias2("move", MI, 0, 1, OS); >+ return NULL; >+ default: return NULL; >+ } >+} >+ >+#define PRINT_ALIAS_INSTR >+#include "MipsGenAsmWriter.inc" >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h b/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h >new file mode 100644 >index 0000000000000000000000000000000000000000..7c2c6e131fb3aac6b55b79f4ccca4f9061d72eb4 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsInstPrinter.h >@@ -0,0 +1,25 @@ >+//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This class prints a Mips MCInst to a .s file. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_MIPSINSTPRINTER_H >+#define CS_MIPSINSTPRINTER_H >+ >+#include "../../MCInst.h" >+#include "../../SStream.h" >+ >+void Mips_printInst(MCInst *MI, SStream *O, void *info); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c b/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c >new file mode 100644 >index 0000000000000000000000000000000000000000..0e5c8489a7be4557fe91384668c1779cf3281238 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.c >@@ -0,0 +1,10023 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include <stdio.h> // debug >+#include <string.h> >+ >+#include "../../utils.h" >+ >+#include "MipsMapping.h" >+ >+#define GET_INSTRINFO_ENUM >+#include "MipsGenInstrInfo.inc" >+ >+#ifndef CAPSTONE_DIET >+static const name_map reg_name_maps[] = { >+ { MIPS_REG_INVALID, NULL }, >+ >+ //{ MIPS_REG_0, "0"}, >+ { MIPS_REG_0, "zero"}, >+ { MIPS_REG_1, "at"}, >+ //{ MIPS_REG_1, "1"}, >+ { MIPS_REG_2, "v0"}, >+ //{ MIPS_REG_2, "2"}, >+ { MIPS_REG_3, "v1"}, >+ //{ MIPS_REG_3, "3"}, >+ { MIPS_REG_4, "a0"}, >+ //{ MIPS_REG_4, "4"}, >+ { MIPS_REG_5, "a1"}, >+ //{ MIPS_REG_5, "5"}, >+ { MIPS_REG_6, "a2"}, >+ //{ MIPS_REG_6, "6"}, >+ { MIPS_REG_7, "a3"}, >+ //{ MIPS_REG_7, "7"}, >+ { MIPS_REG_8, "t0"}, >+ //{ MIPS_REG_8, "8"}, >+ { MIPS_REG_9, "t1"}, >+ //{ MIPS_REG_9, "9"}, >+ { MIPS_REG_10, "t2"}, >+ //{ MIPS_REG_10, "10"}, >+ { MIPS_REG_11, "t3"}, >+ //{ MIPS_REG_11, "11"}, >+ { MIPS_REG_12, "t4"}, >+ //{ MIPS_REG_12, "12"}, >+ { MIPS_REG_13, "t5"}, >+ //{ MIPS_REG_13, "13"}, >+ { MIPS_REG_14, "t6"}, >+ //{ MIPS_REG_14, "14"}, >+ { MIPS_REG_15, "t7"}, >+ //{ MIPS_REG_15, "15"}, >+ { MIPS_REG_16, "s0"}, >+ //{ MIPS_REG_16, "16"}, >+ { MIPS_REG_17, "s1"}, >+ //{ MIPS_REG_17, "17"}, >+ { MIPS_REG_18, "s2"}, >+ //{ MIPS_REG_18, "18"}, >+ { MIPS_REG_19, "s3"}, >+ //{ MIPS_REG_19, "19"}, >+ { MIPS_REG_20, "s4"}, >+ //{ MIPS_REG_20, "20"}, >+ { MIPS_REG_21, "s5"}, >+ //{ MIPS_REG_21, "21"}, >+ { MIPS_REG_22, "s6"}, >+ //{ MIPS_REG_22, "22"}, >+ { MIPS_REG_23, "s7"}, >+ //{ MIPS_REG_23, "23"}, >+ { MIPS_REG_24, "t8"}, >+ //{ MIPS_REG_24, "24"}, >+ { MIPS_REG_25, "t9"}, >+ //{ MIPS_REG_25, "25"}, >+ { MIPS_REG_26, "k0"}, >+ //{ MIPS_REG_26, "26"}, >+ { MIPS_REG_27, "k1"}, >+ //{ MIPS_REG_27, "27"}, >+ { MIPS_REG_28, "gp"}, >+ //{ MIPS_REG_28, "28"}, >+ { MIPS_REG_29, "sp"}, >+ //{ MIPS_REG_29, "29"}, >+ { MIPS_REG_30, "fp"}, >+ //{ MIPS_REG_30, "30"}, >+ { MIPS_REG_31, "ra"}, >+ //{ MIPS_REG_31, "31"}, >+ >+ { MIPS_REG_DSPCCOND, "dspccond"}, >+ { MIPS_REG_DSPCARRY, "dspcarry"}, >+ { MIPS_REG_DSPEFI, "dspefi"}, >+ { MIPS_REG_DSPOUTFLAG, "dspoutflag"}, >+ { MIPS_REG_DSPOUTFLAG16_19, "dspoutflag16_19"}, >+ { MIPS_REG_DSPOUTFLAG20, "dspoutflag20"}, >+ { MIPS_REG_DSPOUTFLAG21, "dspoutflag21"}, >+ { MIPS_REG_DSPOUTFLAG22, "dspoutflag22"}, >+ { MIPS_REG_DSPOUTFLAG23, "dspoutflag23"}, >+ { MIPS_REG_DSPPOS, "dsppos"}, >+ { MIPS_REG_DSPSCOUNT, "dspscount"}, >+ >+ { MIPS_REG_AC0, "ac0"}, >+ { MIPS_REG_AC1, "ac1"}, >+ { MIPS_REG_AC2, "ac2"}, >+ { MIPS_REG_AC3, "ac3"}, >+ >+ { MIPS_REG_CC0, "cc0"}, >+ { MIPS_REG_CC1, "cc1"}, >+ { MIPS_REG_CC2, "cc2"}, >+ { MIPS_REG_CC3, "cc3"}, >+ { MIPS_REG_CC4, "cc4"}, >+ { MIPS_REG_CC5, "cc5"}, >+ { MIPS_REG_CC6, "cc6"}, >+ { MIPS_REG_CC7, "cc7"}, >+ >+ { MIPS_REG_F0, "f0"}, >+ { MIPS_REG_F1, "f1"}, >+ { MIPS_REG_F2, "f2"}, >+ { MIPS_REG_F3, "f3"}, >+ { MIPS_REG_F4, "f4"}, >+ { MIPS_REG_F5, "f5"}, >+ { MIPS_REG_F6, "f6"}, >+ { MIPS_REG_F7, "f7"}, >+ { MIPS_REG_F8, "f8"}, >+ { MIPS_REG_F9, "f9"}, >+ { MIPS_REG_F10, "f10"}, >+ { MIPS_REG_F11, "f11"}, >+ { MIPS_REG_F12, "f12"}, >+ { MIPS_REG_F13, "f13"}, >+ { MIPS_REG_F14, "f14"}, >+ { MIPS_REG_F15, "f15"}, >+ { MIPS_REG_F16, "f16"}, >+ { MIPS_REG_F17, "f17"}, >+ { MIPS_REG_F18, "f18"}, >+ { MIPS_REG_F19, "f19"}, >+ { MIPS_REG_F20, "f20"}, >+ { MIPS_REG_F21, "f21"}, >+ { MIPS_REG_F22, "f22"}, >+ { MIPS_REG_F23, "f23"}, >+ { MIPS_REG_F24, "f24"}, >+ { MIPS_REG_F25, "f25"}, >+ { MIPS_REG_F26, "f26"}, >+ { MIPS_REG_F27, "f27"}, >+ { MIPS_REG_F28, "f28"}, >+ { MIPS_REG_F29, "f29"}, >+ { MIPS_REG_F30, "f30"}, >+ { MIPS_REG_F31, "f31"}, >+ >+ { MIPS_REG_FCC0, "fcc0"}, >+ { MIPS_REG_FCC1, "fcc1"}, >+ { MIPS_REG_FCC2, "fcc2"}, >+ { MIPS_REG_FCC3, "fcc3"}, >+ { MIPS_REG_FCC4, "fcc4"}, >+ { MIPS_REG_FCC5, "fcc5"}, >+ { MIPS_REG_FCC6, "fcc6"}, >+ { MIPS_REG_FCC7, "fcc7"}, >+ >+ { MIPS_REG_W0, "w0"}, >+ { MIPS_REG_W1, "w1"}, >+ { MIPS_REG_W2, "w2"}, >+ { MIPS_REG_W3, "w3"}, >+ { MIPS_REG_W4, "w4"}, >+ { MIPS_REG_W5, "w5"}, >+ { MIPS_REG_W6, "w6"}, >+ { MIPS_REG_W7, "w7"}, >+ { MIPS_REG_W8, "w8"}, >+ { MIPS_REG_W9, "w9"}, >+ { MIPS_REG_W10, "w10"}, >+ { MIPS_REG_W11, "w11"}, >+ { MIPS_REG_W12, "w12"}, >+ { MIPS_REG_W13, "w13"}, >+ { MIPS_REG_W14, "w14"}, >+ { MIPS_REG_W15, "w15"}, >+ { MIPS_REG_W16, "w16"}, >+ { MIPS_REG_W17, "w17"}, >+ { MIPS_REG_W18, "w18"}, >+ { MIPS_REG_W19, "w19"}, >+ { MIPS_REG_W20, "w20"}, >+ { MIPS_REG_W21, "w21"}, >+ { MIPS_REG_W22, "w22"}, >+ { MIPS_REG_W23, "w23"}, >+ { MIPS_REG_W24, "w24"}, >+ { MIPS_REG_W25, "w25"}, >+ { MIPS_REG_W26, "w26"}, >+ { MIPS_REG_W27, "w27"}, >+ { MIPS_REG_W28, "w28"}, >+ { MIPS_REG_W29, "w29"}, >+ { MIPS_REG_W30, "w30"}, >+ { MIPS_REG_W31, "w31"}, >+ >+ { MIPS_REG_HI, "hi"}, >+ { MIPS_REG_LO, "lo"}, >+ >+ { MIPS_REG_P0, "p0"}, >+ { MIPS_REG_P1, "p1"}, >+ { MIPS_REG_P2, "p2"}, >+ >+ { MIPS_REG_MPL0, "mpl0"}, >+ { MIPS_REG_MPL1, "mpl1"}, >+ { MIPS_REG_MPL2, "mpl2"}, >+}; >+#endif >+ >+const char *Mips_reg_name(csh handle, unsigned int reg) >+{ >+#ifndef CAPSTONE_DIET >+ if (reg >= MIPS_REG_ENDING) >+ return NULL; >+ >+ return reg_name_maps[reg].name; >+#else >+ return NULL; >+#endif >+} >+ >+static const insn_map insns[] = { >+ // dummy item >+ { >+ 0, 0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { 0 }, 0, 0 >+#endif >+ }, >+ >+ { >+ Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ABSQ_S_W, MIPS_INS_ABSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDIUPC, MIPS_INS_ADDIUPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQH_PH, MIPS_INS_ADDQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQH_R_W, MIPS_INS_ADDQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQH_W, MIPS_INS_ADDQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQ_PH, MIPS_INS_ADDQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDQ_S_W, MIPS_INS_ADDQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDSC, MIPS_INS_ADDSC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_A_B, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_A_D, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_A_H, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_A_W, MIPS_INS_ADDS_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_S_B, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_S_D, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_S_H, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_S_W, MIPS_INS_ADDS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_U_B, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_U_D, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_U_H, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDS_U_W, MIPS_INS_ADDS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDUH_QB, MIPS_INS_ADDUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDU_PH, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDU_QB, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDU_S_PH, MIPS_INS_ADDU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDU_S_QB, MIPS_INS_ADDU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDVI_B, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDVI_D, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDVI_H, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDVI_W, MIPS_INS_ADDVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDV_B, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDV_D, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDV_H, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDV_W, MIPS_INS_ADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDWC, MIPS_INS_ADDWC, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD_A_B, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD_A_D, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD_A_H, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD_A_W, MIPS_INS_ADD_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADD_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDi, MIPS_INS_ADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDi_MM, MIPS_INS_ADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDiu, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDiu_MM, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDu, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ADDu_MM, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ALIGN, MIPS_INS_ALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ALUIPC, MIPS_INS_ALUIPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AND, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AND64, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ANDI_B, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AND_MM, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AND_V, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ANDi, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ANDi64, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ANDi_MM, MIPS_INS_ANDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_APPEND, MIPS_INS_APPEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_S_B, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_S_D, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_S_H, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_S_W, MIPS_INS_ASUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_U_B, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_U_D, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_U_H, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ASUB_U_W, MIPS_INS_ASUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AUI, MIPS_INS_AUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AUIPC, MIPS_INS_AUIPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_S_B, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_S_D, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_S_H, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_S_W, MIPS_INS_AVER_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_U_B, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_U_D, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_U_H, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVER_U_W, MIPS_INS_AVER_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_S_B, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_S_D, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_S_H, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_S_W, MIPS_INS_AVE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_U_B, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_U_D, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_U_H, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AVE_U_W, MIPS_INS_AVE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuRxImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuRxRxImm16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuSpImm16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AddiuSpImmX16, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AdduRxRyRz16, MIPS_INS_ADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_AndRxRxRy16, MIPS_INS_AND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BADDu, MIPS_INS_BADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BAL, MIPS_INS_BAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BALC, MIPS_INS_BALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BALIGN, MIPS_INS_BALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BC, MIPS_INS_BC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC0F, MIPS_INS_BC0F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC0FL, MIPS_INS_BC0FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC0T, MIPS_INS_BC0T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC0TL, MIPS_INS_BC0TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1EQZ, MIPS_INS_BC1EQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1F, MIPS_INS_BC1F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1FL, MIPS_INS_BC1FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1F_MM, MIPS_INS_BC1F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1NEZ, MIPS_INS_BC1NEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1T, MIPS_INS_BC1T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1TL, MIPS_INS_BC1TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC1T_MM, MIPS_INS_BC1T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2EQZ, MIPS_INS_BC2EQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2F, MIPS_INS_BC2F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2FL, MIPS_INS_BC2FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2NEZ, MIPS_INS_BC2NEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2T, MIPS_INS_BC2T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC2TL, MIPS_INS_BC2TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC3F, MIPS_INS_BC3F, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC3FL, MIPS_INS_BC3FL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC3T, MIPS_INS_BC3T, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BC3TL, MIPS_INS_BC3TL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BCLRI_B, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLRI_D, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLRI_H, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLRI_W, MIPS_INS_BCLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLR_B, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLR_D, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLR_H, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BCLR_W, MIPS_INS_BCLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BEQ, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQ64, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQC, MIPS_INS_BEQC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQL, MIPS_INS_BEQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQZALC, MIPS_INS_BEQZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQZC, MIPS_INS_BEQZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQZC_MM, MIPS_INS_BEQZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BEQ_MM, MIPS_INS_BEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEC, MIPS_INS_BGEC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEUC, MIPS_INS_BGEUC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZ, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZ64, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZAL, MIPS_INS_BGEZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BGEZALC, MIPS_INS_BGEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZALL, MIPS_INS_BGEZALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZALS_MM, MIPS_INS_BGEZALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BGEZAL_MM, MIPS_INS_BGEZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BGEZC, MIPS_INS_BGEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZL, MIPS_INS_BGEZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGEZ_MM, MIPS_INS_BGEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZ, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZ64, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZALC, MIPS_INS_BGTZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZC, MIPS_INS_BGTZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZL, MIPS_INS_BGTZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BGTZ_MM, MIPS_INS_BGTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BINSLI_B, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSLI_D, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSLI_H, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSLI_W, MIPS_INS_BINSLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSL_B, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSL_D, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSL_H, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSL_W, MIPS_INS_BINSL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSRI_B, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSRI_D, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSRI_H, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSRI_W, MIPS_INS_BINSRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSR_B, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSR_D, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSR_H, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BINSR_W, MIPS_INS_BINSR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BITREV, MIPS_INS_BITREV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BITSWAP, MIPS_INS_BITSWAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BLEZ, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLEZ64, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLEZALC, MIPS_INS_BLEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLEZC, MIPS_INS_BLEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLEZL, MIPS_INS_BLEZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLEZ_MM, MIPS_INS_BLEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTC, MIPS_INS_BLTC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTUC, MIPS_INS_BLTUC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZ, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZ64, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZAL, MIPS_INS_BLTZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BLTZALC, MIPS_INS_BLTZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZALL, MIPS_INS_BLTZALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZALS_MM, MIPS_INS_BLTZALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BLTZAL_MM, MIPS_INS_BLTZAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BLTZC, MIPS_INS_BLTZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZL, MIPS_INS_BLTZL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BLTZ_MM, MIPS_INS_BLTZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BMNZI_B, MIPS_INS_BMNZI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BMNZ_V, MIPS_INS_BMNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BMZI_B, MIPS_INS_BMZI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BMZ_V, MIPS_INS_BMZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNE, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNE64, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNEC, MIPS_INS_BNEC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNEGI_B, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEGI_D, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEGI_H, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEGI_W, MIPS_INS_BNEGI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEG_B, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEG_D, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEG_H, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEG_W, MIPS_INS_BNEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BNEL, MIPS_INS_BNEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNEZALC, MIPS_INS_BNEZALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNEZC, MIPS_INS_BNEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNEZC_MM, MIPS_INS_BNEZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNE_MM, MIPS_INS_BNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNVC, MIPS_INS_BNVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNZ_B, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNZ_D, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNZ_H, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNZ_V, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BNZ_W, MIPS_INS_BNZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BOVC, MIPS_INS_BOVC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BPOSGE32, MIPS_INS_BPOSGE32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BREAK, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BREAK_MM, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSELI_B, MIPS_INS_BSELI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSEL_V, MIPS_INS_BSEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSETI_B, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSETI_D, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSETI_H, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSETI_W, MIPS_INS_BSETI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSET_B, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSET_D, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSET_H, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BSET_W, MIPS_INS_BSET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_BZ_B, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BZ_D, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BZ_H, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BZ_V, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BZ_W, MIPS_INS_BZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BeqzRxImm16, MIPS_INS_BEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BeqzRxImmX16, MIPS_INS_BEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_Bimm16, MIPS_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BimmX16, MIPS_INS_B, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BnezRxImm16, MIPS_INS_BNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BnezRxImmX16, MIPS_INS_BNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_Break16, MIPS_INS_BREAK, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_Bteqz16, MIPS_INS_BTEQZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BteqzX16, MIPS_INS_BTEQZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_Btnez16, MIPS_INS_BTNEZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_BtnezX16, MIPS_INS_BTNEZ, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_CACHE, MIPS_INS_CACHE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CACHE_R6, MIPS_INS_CACHE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_L_D64, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_L_S, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_W_D32, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_W_D64, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_W_MM, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_W_S, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEIL_W_S_MM, MIPS_INS_CEIL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQI_B, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQI_D, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQI_H, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQI_W, MIPS_INS_CEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQ_B, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQ_D, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQ_H, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CEQ_W, MIPS_INS_CEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CFC1, MIPS_INS_CFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CFC1_MM, MIPS_INS_CFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CFCMSA, MIPS_INS_CFCMSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CINS, MIPS_INS_CINS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CINS32, MIPS_INS_CINS32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLASS_D, MIPS_INS_CLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLASS_S, MIPS_INS_CLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_S_B, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_S_D, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_S_H, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_S_W, MIPS_INS_CLEI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_U_B, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_U_D, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_U_H, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLEI_U_W, MIPS_INS_CLEI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_S_B, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_S_D, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_S_H, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_S_W, MIPS_INS_CLE_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_U_B, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_U_D, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_U_H, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLE_U_W, MIPS_INS_CLE_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLO, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLO_MM, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLO_R6, MIPS_INS_CLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_S_B, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_S_D, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_S_H, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_S_W, MIPS_INS_CLTI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_U_B, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_U_D, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_U_H, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLTI_U_W, MIPS_INS_CLTI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_S_B, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_S_D, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_S_H, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_S_W, MIPS_INS_CLT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_U_B, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_U_D, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_U_H, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLT_U_W, MIPS_INS_CLT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLZ, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLZ_MM, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CLZ_R6, MIPS_INS_CLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGU_LE_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPGU_LT_QB, MIPS_INS_CMPGU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPU_EQ_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPU_LE_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMPU_LT_QB, MIPS_INS_CMPU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_EQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_EQ_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_EQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_F_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_F_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LE_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LT_PH, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_LT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SAF_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SAF_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SLE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SLE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SLT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SLT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SUEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SUEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SULE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SULE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SULT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SULT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SUN_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_SUN_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_UEQ_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_UEQ_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_ULE_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_ULE_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_ULT_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_ULT_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_UN_D, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CMP_UN_S, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_S_B, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_S_D, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_S_H, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_S_W, MIPS_INS_COPY_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_U_B, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_U_D, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_U_H, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_COPY_U_W, MIPS_INS_COPY_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CTC1, MIPS_INS_CTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CTC1_MM, MIPS_INS_CTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CTCMSA, MIPS_INS_CTCMSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D32_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D32_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D32_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D64_L, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D64_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D64_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_D_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_L_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_L_D64_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_L_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_L_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_D32, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_D32_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_L, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_W, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_S_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_W_D32, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_W_D64, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_W_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_W_S, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CVT_W_S_MM, MIPS_INS_CVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_EQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_EQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_EQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_F_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_F_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_F_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_LT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGLE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGLE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGLE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGL_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGL_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGL_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_NGT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_OLT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SEQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SEQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SEQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SF_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SF_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_SF_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UEQ_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UEQ_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UEQ_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULE_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULE_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULE_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULT_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULT_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_ULT_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UN_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UN_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_C_UN_S, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CmpRxRy16, MIPS_INS_CMP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CmpiRxImm16, MIPS_INS_CMPI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_CmpiRxImmX16, MIPS_INS_CMPI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DADD, MIPS_INS_DADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DADDi, MIPS_INS_DADDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DADDiu, MIPS_INS_DADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DADDu, MIPS_INS_DADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DAHI, MIPS_INS_DAHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DALIGN, MIPS_INS_DALIGN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DATI, MIPS_INS_DATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DAUI, MIPS_INS_DAUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DBITSWAP, MIPS_INS_DBITSWAP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DCLO, MIPS_INS_DCLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DCLO_R6, MIPS_INS_DCLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DCLZ, MIPS_INS_DCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DCLZ_R6, MIPS_INS_DCLZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DDIV, MIPS_INS_DDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DDIVU, MIPS_INS_DDIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DERET, MIPS_INS_DERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DERET_MM, MIPS_INS_DERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DEXT, MIPS_INS_DEXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DEXTM, MIPS_INS_DEXTM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DEXTU, MIPS_INS_DEXTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DI, MIPS_INS_DI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DINS, MIPS_INS_DINS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DINSM, MIPS_INS_DINSM, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DINSU, MIPS_INS_DINSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIVU, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_S_B, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_S_D, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_S_H, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_S_W, MIPS_INS_DIV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_U_B, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_U_D, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_U_H, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DIV_U_W, MIPS_INS_DIV_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DI_MM, MIPS_INS_DI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DLSA, MIPS_INS_DLSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DLSA_R6, MIPS_INS_DLSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMFC0, MIPS_INS_DMFC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMFC1, MIPS_INS_DMFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMFC2, MIPS_INS_DMFC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMOD, MIPS_INS_DMOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMODU, MIPS_INS_DMODU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMTC0, MIPS_INS_DMTC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMTC1, MIPS_INS_DMTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMTC2, MIPS_INS_DMTC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMUH, MIPS_INS_DMUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMUHU, MIPS_INS_DMUHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMUL, MIPS_INS_DMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMULT, MIPS_INS_DMULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMULTu, MIPS_INS_DMULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMULU, MIPS_INS_DMULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DMUL_R6, MIPS_INS_DMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_S_D, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_S_H, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_S_W, MIPS_INS_DOTP_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_U_D, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_U_H, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DOTP_U_W, MIPS_INS_DOTP_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_S_D, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_S_H, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_S_W, MIPS_INS_DPADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_U_D, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_U_H, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPADD_U_W, MIPS_INS_DPADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAU_H_QBL, MIPS_INS_DPAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAU_H_QBR, MIPS_INS_DPAU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPAX_W_PH, MIPS_INS_DPAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPA_W_PH, MIPS_INS_DPA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPOP, MIPS_INS_DPOP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_S_D, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_S_H, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_S_W, MIPS_INS_DPSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_U_D, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_U_H, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSUB_U_W, MIPS_INS_DPSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSU_H_QBL, MIPS_INS_DPSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSU_H_QBR, MIPS_INS_DPSU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPSX_W_PH, MIPS_INS_DPSX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DPS_W_PH, MIPS_INS_DPS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DROTR, MIPS_INS_DROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DROTR32, MIPS_INS_DROTR32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DROTRV, MIPS_INS_DROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSBH, MIPS_INS_DSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSDIV, MIPS_INS_DDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSHD, MIPS_INS_DSHD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSLL, MIPS_INS_DSLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSLL32, MIPS_INS_DSLL32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSLL64_32, MIPS_INS_DSLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSLLV, MIPS_INS_DSLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRA, MIPS_INS_DSRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRA32, MIPS_INS_DSRA32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRAV, MIPS_INS_DSRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRL, MIPS_INS_DSRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRL32, MIPS_INS_DSRL32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSRLV, MIPS_INS_DSRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSUB, MIPS_INS_DSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DSUBu, MIPS_INS_DSUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DUDIV, MIPS_INS_DDIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DivRxRy16, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_DivuRxRy16, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EHB, MIPS_INS_EHB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EI, MIPS_INS_EI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EI_MM, MIPS_INS_EI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ERET, MIPS_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ERET_MM, MIPS_INS_ERET, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXT, MIPS_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTP, MIPS_INS_EXTP, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTPDP, MIPS_INS_EXTPDP, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTPDPV, MIPS_INS_EXTPDPV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTPV, MIPS_INS_EXTPV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTRV_R_W, MIPS_INS_EXTRV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTRV_S_H, MIPS_INS_EXTRV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTRV_W, MIPS_INS_EXTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTR_RS_W, MIPS_INS_EXTR_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTR_R_W, MIPS_INS_EXTR_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTR_S_H, MIPS_INS_EXTR_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTR_W, MIPS_INS_EXTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTS, MIPS_INS_EXTS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXTS32, MIPS_INS_EXTS32, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_EXT_MM, MIPS_INS_EXT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FABS_D32, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FABS_D64, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FABS_MM, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FABS_S, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FABS_S_MM, MIPS_INS_ABS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_D, MIPS_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_D32, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_D64, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_S, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_S_MM, MIPS_INS_ADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FADD_W, MIPS_INS_FADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCAF_D, MIPS_INS_FCAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCAF_W, MIPS_INS_FCAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCEQ_D, MIPS_INS_FCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCEQ_W, MIPS_INS_FCEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLASS_D, MIPS_INS_FCLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLASS_W, MIPS_INS_FCLASS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLE_D, MIPS_INS_FCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLE_W, MIPS_INS_FCLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLT_D, MIPS_INS_FCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCLT_W, MIPS_INS_FCLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCMP_D32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCMP_D32_MM, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCMP_D64, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCMP_S32, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCMP_S32_MM, MIPS_INS_C, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCNE_D, MIPS_INS_FCNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCNE_W, MIPS_INS_FCNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCOR_D, MIPS_INS_FCOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCOR_W, MIPS_INS_FCOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUEQ_D, MIPS_INS_FCUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUEQ_W, MIPS_INS_FCUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCULE_D, MIPS_INS_FCULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCULE_W, MIPS_INS_FCULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCULT_D, MIPS_INS_FCULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCULT_W, MIPS_INS_FCULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUNE_D, MIPS_INS_FCUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUNE_W, MIPS_INS_FCUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUN_D, MIPS_INS_FCUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FCUN_W, MIPS_INS_FCUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_D, MIPS_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_D32, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_D64, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_S, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_S_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FDIV_W, MIPS_INS_FDIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXDO_H, MIPS_INS_FEXDO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXDO_W, MIPS_INS_FEXDO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXP2_D, MIPS_INS_FEXP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXP2_W, MIPS_INS_FEXP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXUPL_D, MIPS_INS_FEXUPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXUPL_W, MIPS_INS_FEXUPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXUPR_D, MIPS_INS_FEXUPR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FEXUPR_W, MIPS_INS_FEXUPR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFINT_S_D, MIPS_INS_FFINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFINT_S_W, MIPS_INS_FFINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFINT_U_D, MIPS_INS_FFINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFINT_U_W, MIPS_INS_FFINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFQL_D, MIPS_INS_FFQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFQL_W, MIPS_INS_FFQL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFQR_D, MIPS_INS_FFQR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FFQR_W, MIPS_INS_FFQR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FILL_B, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FILL_D, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FILL_H, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FILL_W, MIPS_INS_FILL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOG2_D, MIPS_INS_FLOG2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOG2_W, MIPS_INS_FLOG2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_L_D64, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_L_S, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_W_D32, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_W_D64, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_W_MM, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_W_S, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMADD_D, MIPS_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMADD_W, MIPS_INS_FMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMAX_A_D, MIPS_INS_FMAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMAX_A_W, MIPS_INS_FMAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMAX_D, MIPS_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMAX_W, MIPS_INS_FMAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMIN_A_D, MIPS_INS_FMIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMIN_A_W, MIPS_INS_FMIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMIN_D, MIPS_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMIN_W, MIPS_INS_FMIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMOV_D32, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMOV_D32_MM, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMOV_D64, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMOV_S, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMOV_S_MM, MIPS_INS_MOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMSUB_D, MIPS_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMSUB_W, MIPS_INS_FMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_D, MIPS_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_D32, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_D64, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_S, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_S_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FMUL_W, MIPS_INS_FMUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FNEG_D32, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FNEG_D64, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FNEG_MM, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FNEG_S, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FNEG_S_MM, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRCP_D, MIPS_INS_FRCP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRCP_W, MIPS_INS_FRCP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRINT_D, MIPS_INS_FRINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRINT_W, MIPS_INS_FRINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRSQRT_D, MIPS_INS_FRSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FRSQRT_W, MIPS_INS_FRSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSAF_D, MIPS_INS_FSAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSAF_W, MIPS_INS_FSAF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSEQ_D, MIPS_INS_FSEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSEQ_W, MIPS_INS_FSEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSLE_D, MIPS_INS_FSLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSLE_W, MIPS_INS_FSLE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSLT_D, MIPS_INS_FSLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSLT_W, MIPS_INS_FSLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSNE_D, MIPS_INS_FSNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSNE_W, MIPS_INS_FSNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSOR_D, MIPS_INS_FSOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSOR_W, MIPS_INS_FSOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_D, MIPS_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_D32, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_D64, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_MM, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_S, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_S_MM, MIPS_INS_SQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSQRT_W, MIPS_INS_FSQRT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_D, MIPS_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_D32, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_D64, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_S, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_S_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUB_W, MIPS_INS_FSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUEQ_D, MIPS_INS_FSUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUEQ_W, MIPS_INS_FSUEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSULE_D, MIPS_INS_FSULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSULE_W, MIPS_INS_FSULE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSULT_D, MIPS_INS_FSULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSULT_W, MIPS_INS_FSULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUNE_D, MIPS_INS_FSUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUNE_W, MIPS_INS_FSUNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUN_D, MIPS_INS_FSUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FSUN_W, MIPS_INS_FSUN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTINT_S_D, MIPS_INS_FTINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTINT_S_W, MIPS_INS_FTINT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTINT_U_D, MIPS_INS_FTINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTINT_U_W, MIPS_INS_FTINT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTQ_H, MIPS_INS_FTQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTQ_W, MIPS_INS_FTQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_S_D, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_S_H, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_S_W, MIPS_INS_HADD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_U_D, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_U_H, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HADD_U_W, MIPS_INS_HADD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_S_D, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_S_H, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_S_W, MIPS_INS_HSUB_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_U_D, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_U_H, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_HSUB_U_W, MIPS_INS_HSUB_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVEV_B, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVEV_D, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVEV_H, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVEV_W, MIPS_INS_ILVEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVL_B, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVL_D, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVL_H, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVL_W, MIPS_INS_ILVL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVOD_B, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVOD_D, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVOD_H, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVOD_W, MIPS_INS_ILVOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVR_B, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVR_D, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVR_H, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ILVR_W, MIPS_INS_ILVR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INS, MIPS_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSERT_B, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSERT_D, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSERT_H, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSERT_W, MIPS_INS_INSERT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSV, MIPS_INS_INSV, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSVE_B, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSVE_D, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSVE_H, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INSVE_W, MIPS_INS_INSVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_INS_MM, MIPS_INS_INS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_J, MIPS_INS_J, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0 >+#endif >+ }, >+ { >+ Mips_JAL, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALR, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALR16_MM, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALR64, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALRS_MM, MIPS_INS_JALRS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALR_HB, MIPS_INS_JALR_HB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 1 >+#endif >+ }, >+ { >+ Mips_JALR_MM, MIPS_INS_JALR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALS_MM, MIPS_INS_JALS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JALX, MIPS_INS_JALX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JAL_MM, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JIALC, MIPS_INS_JIALC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JIC, MIPS_INS_JIC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JR, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JR64, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JRADDIUSP, MIPS_INS_JRADDIUSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JR_HB, MIPS_INS_JR_HB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JR_HB_R6, MIPS_INS_JR_HB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JR_MM, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_J_MM, MIPS_INS_J, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_Jal16, MIPS_INS_JAL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_JrRa16, MIPS_INS_JR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JrcRa16, MIPS_INS_JRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JrcRx16, MIPS_INS_JRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1 >+#endif >+ }, >+ { >+ Mips_JumpLinkReg16, MIPS_INS_JALRC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LB, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LB64, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LBUX, MIPS_INS_LBUX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LB_MM, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LBu, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LBu64, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LBu_MM, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LD, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC1, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC164, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC1_MM, MIPS_INS_LDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC2, MIPS_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC2_R6, MIPS_INS_LDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDC3, MIPS_INS_LDC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDI_B, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDI_D, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDI_H, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDI_W, MIPS_INS_LDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDL, MIPS_INS_LDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDPC, MIPS_INS_LDPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDR, MIPS_INS_LDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDXC1, MIPS_INS_LDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LDXC164, MIPS_INS_LDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LD_B, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LD_D, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LD_H, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LD_W, MIPS_INS_LD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LEA_ADDiu, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LEA_ADDiu64, MIPS_INS_DADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LH, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LH64, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LHX, MIPS_INS_LHX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LH_MM, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LHu, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LHu64, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LHu_MM, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LL, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LLD, MIPS_INS_LLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LLD_R6, MIPS_INS_LLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LL_MM, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LL_R6, MIPS_INS_LL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LSA, MIPS_INS_LSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LSA_R6, MIPS_INS_LSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUXC1, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUXC164, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUXC1_MM, MIPS_INS_LUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUi, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUi64, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LUi_MM, MIPS_INS_LUI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LW, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LW64, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWC1, MIPS_INS_LWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWC1_MM, MIPS_INS_LWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWC2, MIPS_INS_LWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWC2_R6, MIPS_INS_LWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWC3, MIPS_INS_LWC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWL, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWL64, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWL_MM, MIPS_INS_LWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWPC, MIPS_INS_LWPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWR, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWR64, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWR_MM, MIPS_INS_LWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWUPC, MIPS_INS_LWUPC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWU_MM, MIPS_INS_LWU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWX, MIPS_INS_LWX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWXC1, MIPS_INS_LWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWXC1_MM, MIPS_INS_LWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LW_MM, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LWu, MIPS_INS_LWU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LbRxRyOffMemX16, MIPS_INS_LB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LbuRxRyOffMemX16, MIPS_INS_LBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LhRxRyOffMemX16, MIPS_INS_LH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LhuRxRyOffMemX16, MIPS_INS_LHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LiRxImm16, MIPS_INS_LI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LiRxImmX16, MIPS_INS_LI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LwRxPcTcp16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LwRxPcTcpX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LwRxRyOffMemX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_LwRxSpImmX16, MIPS_INS_LW, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDF_D, MIPS_INS_MADDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDF_S, MIPS_INS_MADDF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDR_Q_H, MIPS_INS_MADDR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDR_Q_W, MIPS_INS_MADDR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDU, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDU_DSP, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDU_MM, MIPS_INS_MADDU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDV_B, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDV_D, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDV_H, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADDV_W, MIPS_INS_MADDV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_D32, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_D32_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_D64, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_DSP, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_Q_H, MIPS_INS_MADD_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_Q_W, MIPS_INS_MADD_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_S, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MADD_S_MM, MIPS_INS_MADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXA_D, MIPS_INS_MAXA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXA_S, MIPS_INS_MAXA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_S_B, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_S_D, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_S_H, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_S_W, MIPS_INS_MAXI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_U_B, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_U_D, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_U_H, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAXI_U_W, MIPS_INS_MAXI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_A_B, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_A_D, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_A_H, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_A_W, MIPS_INS_MAX_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_D, MIPS_INS_MAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_S, MIPS_INS_MAX, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_S_B, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_S_D, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_S_H, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_S_W, MIPS_INS_MAX_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_U_B, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_U_D, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_U_H, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MAX_U_W, MIPS_INS_MAX_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFC0, MIPS_INS_MFC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFC1, MIPS_INS_MFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFC1_MM, MIPS_INS_MFC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFC2, MIPS_INS_MFC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHC1_D32, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHC1_D64, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHC1_MM, MIPS_INS_MFHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHI, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHI16_MM, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHI64, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHI_DSP, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFHI_MM, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFLO, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFLO16_MM, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFLO64, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFLO_DSP, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MFLO_MM, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINA_D, MIPS_INS_MINA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINA_S, MIPS_INS_MINA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_S_B, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_S_D, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_S_H, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_S_W, MIPS_INS_MINI_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_U_B, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_U_D, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_U_H, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MINI_U_W, MIPS_INS_MINI_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_A_B, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_A_D, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_A_H, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_A_W, MIPS_INS_MIN_A, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_D, MIPS_INS_MIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_S, MIPS_INS_MIN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_S_B, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_S_D, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_S_H, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_S_W, MIPS_INS_MIN_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_U_B, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_U_D, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_U_H, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MIN_U_W, MIPS_INS_MIN_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD, MIPS_INS_MOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MODSUB, MIPS_INS_MODSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MODU, MIPS_INS_MODU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_S_B, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_S_D, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_S_H, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_S_W, MIPS_INS_MOD_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_U_B, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_U_D, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_U_H, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOD_U_W, MIPS_INS_MOD_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVE16_MM, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVE_V, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_D32, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_D32_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_D64, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_I, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_I64, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_I_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_S, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVF_S_MM, MIPS_INS_MOVF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I64_D64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I64_I, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I64_I64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I64_S, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_D32, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_D32_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_D64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_I, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_I64, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_S, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVN_I_S_MM, MIPS_INS_MOVN, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_D32, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_D32_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_D64, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_I, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_I64, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_I_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_S, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVT_S_MM, MIPS_INS_MOVT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I64_D64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I64_I, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I64_I64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I64_S, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_D32, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_D64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_I, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_I64, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_S, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBF_D, MIPS_INS_MSUBF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBF_S, MIPS_INS_MSUBF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBU, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBU_DSP, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBU_MM, MIPS_INS_MSUBU, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBV_B, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBV_D, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBV_H, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUBV_W, MIPS_INS_MSUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_D32, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_D32_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_D64, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_DSP, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_Q_H, MIPS_INS_MSUB_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_Q_W, MIPS_INS_MSUB_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_S, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MSUB_S_MM, MIPS_INS_MSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTC0, MIPS_INS_MTC0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTC1, MIPS_INS_MTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTC1_MM, MIPS_INS_MTC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTC2, MIPS_INS_MTC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHC1_D32, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHC1_D64, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHC1_MM, MIPS_INS_MTHC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHI, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHI64, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHI_DSP, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHI_MM, MIPS_INS_MTHI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTHLIP, MIPS_INS_MTHLIP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTLO, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTLO64, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTLO_DSP, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTLO_MM, MIPS_INS_MTLO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTM0, MIPS_INS_MTM0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTM1, MIPS_INS_MTM1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTM2, MIPS_INS_MTM2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTP0, MIPS_INS_MTP0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTP1, MIPS_INS_MTP1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MTP2, MIPS_INS_MTP2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUH, MIPS_INS_MUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUHU, MIPS_INS_MUHU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULQ_RS_W, MIPS_INS_MULQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULQ_S_PH, MIPS_INS_MULQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULQ_S_W, MIPS_INS_MULQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULR_Q_H, MIPS_INS_MULR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULR_Q_W, MIPS_INS_MULR_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULSA_W_PH, MIPS_INS_MULSA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULT, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULTU_DSP, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULT_DSP, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULT_MM, MIPS_INS_MULT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULTu, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULTu_MM, MIPS_INS_MULTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULU, MIPS_INS_MULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULV_B, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULV_D, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULV_H, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MULV_W, MIPS_INS_MULV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_MM, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_PH, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_Q_H, MIPS_INS_MUL_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_Q_W, MIPS_INS_MUL_Q, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_R6, MIPS_INS_MUL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MUL_S_PH, MIPS_INS_MUL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_Mfhi16, MIPS_INS_MFHI, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_Mflo16, MIPS_INS_MFLO, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_Move32R16, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_MoveR3216, MIPS_INS_MOVE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLOC_B, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLOC_D, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLOC_H, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLOC_W, MIPS_INS_NLOC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLZC_B, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLZC_D, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLZC_H, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NLZC_W, MIPS_INS_NLZC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMADD_D32, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMADD_D32_MM, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMADD_D64, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMADD_S, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMADD_S_MM, MIPS_INS_NMADD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMSUB_D32, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMSUB_D32_MM, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMSUB_D64, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMSUB_S, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NMSUB_S_MM, MIPS_INS_NMSUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NOR, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NOR64, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NORI_B, MIPS_INS_NORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NOR_MM, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NOR_V, MIPS_INS_NOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NegRxRy16, MIPS_INS_NEG, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_NotRxRy16, MIPS_INS_NOT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_OR, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_OR64, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ORI_B, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_OR_MM, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_OR_V, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ORi, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ORi64, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ORi_MM, MIPS_INS_ORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_OrRxRxRy16, MIPS_INS_OR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PACKRL_PH, MIPS_INS_PACKRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PAUSE, MIPS_INS_PAUSE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKEV_B, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKEV_D, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKEV_H, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKEV_W, MIPS_INS_PCKEV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKOD_B, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKOD_D, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKOD_H, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCKOD_W, MIPS_INS_PCKOD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCNT_B, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCNT_D, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCNT_H, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PCNT_W, MIPS_INS_PCNT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PICK_PH, MIPS_INS_PICK, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PICK_QB, MIPS_INS_PICK, >+#ifndef CAPSTONE_DIET >+ { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_POP, MIPS_INS_POP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECR_QB_PH, MIPS_INS_PRECR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PREF, MIPS_INS_PREF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PREF_R6, MIPS_INS_PREF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_PREPEND, MIPS_INS_PREPEND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RADDU_W_QB, MIPS_INS_RADDU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RDDSP, MIPS_INS_RDDSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RDHWR, MIPS_INS_RDHWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RDHWR64, MIPS_INS_RDHWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_REPLV_PH, MIPS_INS_REPLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_REPLV_QB, MIPS_INS_REPLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_REPL_PH, MIPS_INS_REPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_REPL_QB, MIPS_INS_REPL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RINT_D, MIPS_INS_RINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_RINT_S, MIPS_INS_RINT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROTR, MIPS_INS_ROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROTRV, MIPS_INS_ROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROTRV_MM, MIPS_INS_ROTRV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROTR_MM, MIPS_INS_ROTR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_L_D64, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_L_S, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_W_D32, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_W_D64, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_W_MM, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_W_S, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ROUND_W_S_MM, MIPS_INS_ROUND, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_S_B, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_S_D, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_S_H, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_S_W, MIPS_INS_SAT_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_U_B, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_U_D, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_U_H, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SAT_U_W, MIPS_INS_SAT_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SB, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SB64, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SB_MM, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SC, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SCD, MIPS_INS_SCD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SCD_R6, MIPS_INS_SCD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SC_MM, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SC_R6, MIPS_INS_SC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SD, MIPS_INS_SD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDBBP, MIPS_INS_SDBBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDBBP_R6, MIPS_INS_SDBBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC1, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC164, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC1_MM, MIPS_INS_SDC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC2, MIPS_INS_SDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC2_R6, MIPS_INS_SDC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDC3, MIPS_INS_SDC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDIV, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDIV_MM, MIPS_INS_DIV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDL, MIPS_INS_SDL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDR, MIPS_INS_SDR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDXC1, MIPS_INS_SDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SDXC164, MIPS_INS_SDXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEB, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEB64, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEB_MM, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEH, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEH64, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEH_MM, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELEQZ, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELEQZ64, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELEQZ_D, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELEQZ_S, MIPS_INS_SELEQZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELNEZ, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELNEZ64, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELNEZ_D, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SELNEZ_S, MIPS_INS_SELNEZ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEL_D, MIPS_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEL_S, MIPS_INS_SEL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEQ, MIPS_INS_SEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SEQi, MIPS_INS_SEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SH, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SH64, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHF_B, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHF_H, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHF_W, MIPS_INS_SHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHILO, MIPS_INS_SHILO, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHILOV, MIPS_INS_SHILOV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLLV_PH, MIPS_INS_SHLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLLV_QB, MIPS_INS_SHLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLLV_S_W, MIPS_INS_SHLLV_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLL_PH, MIPS_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLL_QB, MIPS_INS_SHLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLL_S_PH, MIPS_INS_SHLL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHLL_S_W, MIPS_INS_SHLL_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRAV_PH, MIPS_INS_SHRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRAV_QB, MIPS_INS_SHRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRAV_R_W, MIPS_INS_SHRAV_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRA_PH, MIPS_INS_SHRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRA_QB, MIPS_INS_SHRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRA_R_PH, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRA_R_QB, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRA_R_W, MIPS_INS_SHRA_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRLV_PH, MIPS_INS_SHRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRLV_QB, MIPS_INS_SHRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRL_PH, MIPS_INS_SHRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SHRL_QB, MIPS_INS_SHRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SH_MM, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLDI_B, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLDI_D, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLDI_H, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLDI_W, MIPS_INS_SLDI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLD_B, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLD_D, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLD_H, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLD_W, MIPS_INS_SLD, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL64_32, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL64_64, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLI_B, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLI_D, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLI_H, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLI_W, MIPS_INS_SLLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLV, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLLV_MM, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL_B, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL_D, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL_H, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL_MM, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLL_W, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLT, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLT64, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLT_MM, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTi, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTi64, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTi_MM, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTiu, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTiu64, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTiu_MM, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTu, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTu64, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SLTu_MM, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SNE, MIPS_INS_SNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SNEi, MIPS_INS_SNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLATI_B, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLATI_D, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLATI_H, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLATI_W, MIPS_INS_SPLATI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLAT_B, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLAT_D, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLAT_H, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SPLAT_W, MIPS_INS_SPLAT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAI_B, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAI_D, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAI_H, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAI_W, MIPS_INS_SRAI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRARI_B, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRARI_D, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRARI_H, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRARI_W, MIPS_INS_SRARI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAR_B, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAR_D, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAR_H, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAR_W, MIPS_INS_SRAR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAV, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRAV_MM, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA_B, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA_D, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA_H, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA_MM, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRA_W, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLI_B, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLI_D, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLI_H, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLI_W, MIPS_INS_SRLI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLRI_B, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLRI_D, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLRI_H, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLRI_W, MIPS_INS_SRLRI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLR_B, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLR_D, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLR_H, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLR_W, MIPS_INS_SRLR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLV, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRLV_MM, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL_B, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL_D, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL_H, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL_MM, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SRL_W, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SSNOP, MIPS_INS_SSNOP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ST_B, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ST_D, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ST_H, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ST_W, MIPS_INS_ST, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUB, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQH_PH, MIPS_INS_SUBQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQH_R_W, MIPS_INS_SUBQH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQH_W, MIPS_INS_SUBQH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQ_PH, MIPS_INS_SUBQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBQ_S_W, MIPS_INS_SUBQ_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_S_B, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_S_D, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_S_H, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_S_W, MIPS_INS_SUBS_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_U_B, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_U_D, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_U_H, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBS_U_W, MIPS_INS_SUBS_U, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBUH_QB, MIPS_INS_SUBUH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBU_PH, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBU_QB, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBU_S_PH, MIPS_INS_SUBU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBU_S_QB, MIPS_INS_SUBU_S, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBVI_B, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBVI_D, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBVI_H, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBVI_W, MIPS_INS_SUBVI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBV_B, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBV_D, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBV_H, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBV_W, MIPS_INS_SUBV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUB_MM, MIPS_INS_SUB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBu, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUBu_MM, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUXC1, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUXC164, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SUXC1_MM, MIPS_INS_SUXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SW, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SW64, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWC1, MIPS_INS_SWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWC1_MM, MIPS_INS_SWC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWC2, MIPS_INS_SWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWC2_R6, MIPS_INS_SWC2, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWC3, MIPS_INS_SWC3, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWL, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWL64, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWL_MM, MIPS_INS_SWL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWR, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWR64, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWR_MM, MIPS_INS_SWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWXC1, MIPS_INS_SWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SWXC1_MM, MIPS_INS_SWXC1, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SW_MM, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SYNC, MIPS_INS_SYNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SYNC_MM, MIPS_INS_SYNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SYSCALL, MIPS_INS_SYSCALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SYSCALL_MM, MIPS_INS_SYSCALL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SbRxRyOffMemX16, MIPS_INS_SB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SebRx16, MIPS_INS_SEB, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SehRx16, MIPS_INS_SEH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_ShRxRyOffMemX16, MIPS_INS_SH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SllX16, MIPS_INS_SLL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SllvRxRy16, MIPS_INS_SLLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltRxRy16, MIPS_INS_SLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltiRxImm16, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltiRxImmX16, MIPS_INS_SLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltiuRxImm16, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltiuRxImmX16, MIPS_INS_SLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SltuRxRy16, MIPS_INS_SLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SraX16, MIPS_INS_SRA, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SravRxRy16, MIPS_INS_SRAV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SrlX16, MIPS_INS_SRL, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SrlvRxRy16, MIPS_INS_SRLV, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SubuRxRyRz16, MIPS_INS_SUBU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SwRxRyOffMemX16, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_SwRxSpImmX16, MIPS_INS_SW, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TEQ, MIPS_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TEQI, MIPS_INS_TEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TEQI_MM, MIPS_INS_TEQI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TEQ_MM, MIPS_INS_TEQ, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGE, MIPS_INS_TGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEI, MIPS_INS_TGEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEIU, MIPS_INS_TGEIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEIU_MM, MIPS_INS_TGEIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEI_MM, MIPS_INS_TGEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEU, MIPS_INS_TGEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGEU_MM, MIPS_INS_TGEU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TGE_MM, MIPS_INS_TGE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBP, MIPS_INS_TLBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBP_MM, MIPS_INS_TLBP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBR, MIPS_INS_TLBR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBR_MM, MIPS_INS_TLBR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBWI, MIPS_INS_TLBWI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBWI_MM, MIPS_INS_TLBWI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBWR, MIPS_INS_TLBWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLBWR_MM, MIPS_INS_TLBWR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLT, MIPS_INS_TLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLTI, MIPS_INS_TLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLTIU_MM, MIPS_INS_TLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLTI_MM, MIPS_INS_TLTI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLTU, MIPS_INS_TLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLTU_MM, MIPS_INS_TLTU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TLT_MM, MIPS_INS_TLT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TNE, MIPS_INS_TNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TNEI, MIPS_INS_TNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TNEI_MM, MIPS_INS_TNEI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TNE_MM, MIPS_INS_TNE, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_L_D64, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_L_S, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_W_D32, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_W_D64, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_W_MM, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_W_S, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_TTLTIU, MIPS_INS_TLTIU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_UDIV, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_UDIV_MM, MIPS_INS_DIVU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_V3MULU, MIPS_INS_V3MULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VMM0, MIPS_INS_VMM0, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VMULU, MIPS_INS_VMULU, >+#ifndef CAPSTONE_DIET >+ { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VSHF_B, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VSHF_D, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VSHF_H, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_VSHF_W, MIPS_INS_VSHF, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_WAIT, MIPS_INS_WAIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_WAIT_MM, MIPS_INS_WAIT, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_WRDSP, MIPS_INS_WRDSP, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_WSBH, MIPS_INS_WSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_WSBH_MM, MIPS_INS_WSBH, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XOR, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XOR64, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XORI_B, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XOR_MM, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XOR_V, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XORi, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XORi64, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XORi_MM, MIPS_INS_XORI, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0 >+#endif >+ }, >+ { >+ Mips_XorRxRxRy16, MIPS_INS_XOR, >+#ifndef CAPSTONE_DIET >+ { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0 >+#endif >+ }, >+}; >+ >+// given internal insn id, return public instruction info >+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) >+{ >+ unsigned int i; >+ >+ i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); >+ if (i != 0) { >+ insn->id = insns[i].mapid; >+ >+ if (h->detail) { >+#ifndef CAPSTONE_DIET >+ memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); >+ insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); >+ >+ memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); >+ insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); >+ >+ memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); >+ insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups); >+ >+ if (insns[i].branch || insns[i].indirect_branch) { >+ // this insn also belongs to JUMP group. add JUMP group >+ insn->detail->groups[insn->detail->groups_count] = MIPS_GRP_JUMP; >+ insn->detail->groups_count++; >+ } >+#endif >+ } >+ } >+} >+ >+static const name_map insn_name_maps[] = { >+ { MIPS_INS_INVALID, NULL }, >+ >+ { MIPS_INS_ABSQ_S, "absq_s" }, >+ { MIPS_INS_ADD, "add" }, >+ { MIPS_INS_ADDIUPC, "addiupc" }, >+ { MIPS_INS_ADDQH, "addqh" }, >+ { MIPS_INS_ADDQH_R, "addqh_r" }, >+ { MIPS_INS_ADDQ, "addq" }, >+ { MIPS_INS_ADDQ_S, "addq_s" }, >+ { MIPS_INS_ADDSC, "addsc" }, >+ { MIPS_INS_ADDS_A, "adds_a" }, >+ { MIPS_INS_ADDS_S, "adds_s" }, >+ { MIPS_INS_ADDS_U, "adds_u" }, >+ { MIPS_INS_ADDUH, "adduh" }, >+ { MIPS_INS_ADDUH_R, "adduh_r" }, >+ { MIPS_INS_ADDU, "addu" }, >+ { MIPS_INS_ADDU_S, "addu_s" }, >+ { MIPS_INS_ADDVI, "addvi" }, >+ { MIPS_INS_ADDV, "addv" }, >+ { MIPS_INS_ADDWC, "addwc" }, >+ { MIPS_INS_ADD_A, "add_a" }, >+ { MIPS_INS_ADDI, "addi" }, >+ { MIPS_INS_ADDIU, "addiu" }, >+ { MIPS_INS_ALIGN, "align" }, >+ { MIPS_INS_ALUIPC, "aluipc" }, >+ { MIPS_INS_AND, "and" }, >+ { MIPS_INS_ANDI, "andi" }, >+ { MIPS_INS_APPEND, "append" }, >+ { MIPS_INS_ASUB_S, "asub_s" }, >+ { MIPS_INS_ASUB_U, "asub_u" }, >+ { MIPS_INS_AUI, "aui" }, >+ { MIPS_INS_AUIPC, "auipc" }, >+ { MIPS_INS_AVER_S, "aver_s" }, >+ { MIPS_INS_AVER_U, "aver_u" }, >+ { MIPS_INS_AVE_S, "ave_s" }, >+ { MIPS_INS_AVE_U, "ave_u" }, >+ { MIPS_INS_BADDU, "baddu" }, >+ { MIPS_INS_BAL, "bal" }, >+ { MIPS_INS_BALC, "balc" }, >+ { MIPS_INS_BALIGN, "balign" }, >+ { MIPS_INS_BC, "bc" }, >+ { MIPS_INS_BC0F, "bc0f" }, >+ { MIPS_INS_BC0FL, "bc0fl" }, >+ { MIPS_INS_BC0T, "bc0t" }, >+ { MIPS_INS_BC0TL, "bc0tl" }, >+ { MIPS_INS_BC1EQZ, "bc1eqz" }, >+ { MIPS_INS_BC1F, "bc1f" }, >+ { MIPS_INS_BC1FL, "bc1fl" }, >+ { MIPS_INS_BC1NEZ, "bc1nez" }, >+ { MIPS_INS_BC1T, "bc1t" }, >+ { MIPS_INS_BC1TL, "bc1tl" }, >+ { MIPS_INS_BC2EQZ, "bc2eqz" }, >+ { MIPS_INS_BC2F, "bc2f" }, >+ { MIPS_INS_BC2FL, "bc2fl" }, >+ { MIPS_INS_BC2NEZ, "bc2nez" }, >+ { MIPS_INS_BC2T, "bc2t" }, >+ { MIPS_INS_BC2TL, "bc2tl" }, >+ { MIPS_INS_BC3F, "bc3f" }, >+ { MIPS_INS_BC3FL, "bc3fl" }, >+ { MIPS_INS_BC3T, "bc3t" }, >+ { MIPS_INS_BC3TL, "bc3tl" }, >+ { MIPS_INS_BCLRI, "bclri" }, >+ { MIPS_INS_BCLR, "bclr" }, >+ { MIPS_INS_BEQ, "beq" }, >+ { MIPS_INS_BEQC, "beqc" }, >+ { MIPS_INS_BEQL, "beql" }, >+ { MIPS_INS_BEQZALC, "beqzalc" }, >+ { MIPS_INS_BEQZC, "beqzc" }, >+ { MIPS_INS_BGEC, "bgec" }, >+ { MIPS_INS_BGEUC, "bgeuc" }, >+ { MIPS_INS_BGEZ, "bgez" }, >+ { MIPS_INS_BGEZAL, "bgezal" }, >+ { MIPS_INS_BGEZALC, "bgezalc" }, >+ { MIPS_INS_BGEZALL, "bgezall" }, >+ { MIPS_INS_BGEZALS, "bgezals" }, >+ { MIPS_INS_BGEZC, "bgezc" }, >+ { MIPS_INS_BGEZL, "bgezl" }, >+ { MIPS_INS_BGTZ, "bgtz" }, >+ { MIPS_INS_BGTZALC, "bgtzalc" }, >+ { MIPS_INS_BGTZC, "bgtzc" }, >+ { MIPS_INS_BGTZL, "bgtzl" }, >+ { MIPS_INS_BINSLI, "binsli" }, >+ { MIPS_INS_BINSL, "binsl" }, >+ { MIPS_INS_BINSRI, "binsri" }, >+ { MIPS_INS_BINSR, "binsr" }, >+ { MIPS_INS_BITREV, "bitrev" }, >+ { MIPS_INS_BITSWAP, "bitswap" }, >+ { MIPS_INS_BLEZ, "blez" }, >+ { MIPS_INS_BLEZALC, "blezalc" }, >+ { MIPS_INS_BLEZC, "blezc" }, >+ { MIPS_INS_BLEZL, "blezl" }, >+ { MIPS_INS_BLTC, "bltc" }, >+ { MIPS_INS_BLTUC, "bltuc" }, >+ { MIPS_INS_BLTZ, "bltz" }, >+ { MIPS_INS_BLTZAL, "bltzal" }, >+ { MIPS_INS_BLTZALC, "bltzalc" }, >+ { MIPS_INS_BLTZALL, "bltzall" }, >+ { MIPS_INS_BLTZALS, "bltzals" }, >+ { MIPS_INS_BLTZC, "bltzc" }, >+ { MIPS_INS_BLTZL, "bltzl" }, >+ { MIPS_INS_BMNZI, "bmnzi" }, >+ { MIPS_INS_BMNZ, "bmnz" }, >+ { MIPS_INS_BMZI, "bmzi" }, >+ { MIPS_INS_BMZ, "bmz" }, >+ { MIPS_INS_BNE, "bne" }, >+ { MIPS_INS_BNEC, "bnec" }, >+ { MIPS_INS_BNEGI, "bnegi" }, >+ { MIPS_INS_BNEG, "bneg" }, >+ { MIPS_INS_BNEL, "bnel" }, >+ { MIPS_INS_BNEZALC, "bnezalc" }, >+ { MIPS_INS_BNEZC, "bnezc" }, >+ { MIPS_INS_BNVC, "bnvc" }, >+ { MIPS_INS_BNZ, "bnz" }, >+ { MIPS_INS_BOVC, "bovc" }, >+ { MIPS_INS_BPOSGE32, "bposge32" }, >+ { MIPS_INS_BREAK, "break" }, >+ { MIPS_INS_BSELI, "bseli" }, >+ { MIPS_INS_BSEL, "bsel" }, >+ { MIPS_INS_BSETI, "bseti" }, >+ { MIPS_INS_BSET, "bset" }, >+ { MIPS_INS_BZ, "bz" }, >+ { MIPS_INS_BEQZ, "beqz" }, >+ { MIPS_INS_B, "b" }, >+ { MIPS_INS_BNEZ, "bnez" }, >+ { MIPS_INS_BTEQZ, "bteqz" }, >+ { MIPS_INS_BTNEZ, "btnez" }, >+ { MIPS_INS_CACHE, "cache" }, >+ { MIPS_INS_CEIL, "ceil" }, >+ { MIPS_INS_CEQI, "ceqi" }, >+ { MIPS_INS_CEQ, "ceq" }, >+ { MIPS_INS_CFC1, "cfc1" }, >+ { MIPS_INS_CFCMSA, "cfcmsa" }, >+ { MIPS_INS_CINS, "cins" }, >+ { MIPS_INS_CINS32, "cins32" }, >+ { MIPS_INS_CLASS, "class" }, >+ { MIPS_INS_CLEI_S, "clei_s" }, >+ { MIPS_INS_CLEI_U, "clei_u" }, >+ { MIPS_INS_CLE_S, "cle_s" }, >+ { MIPS_INS_CLE_U, "cle_u" }, >+ { MIPS_INS_CLO, "clo" }, >+ { MIPS_INS_CLTI_S, "clti_s" }, >+ { MIPS_INS_CLTI_U, "clti_u" }, >+ { MIPS_INS_CLT_S, "clt_s" }, >+ { MIPS_INS_CLT_U, "clt_u" }, >+ { MIPS_INS_CLZ, "clz" }, >+ { MIPS_INS_CMPGDU, "cmpgdu" }, >+ { MIPS_INS_CMPGU, "cmpgu" }, >+ { MIPS_INS_CMPU, "cmpu" }, >+ { MIPS_INS_CMP, "cmp" }, >+ { MIPS_INS_COPY_S, "copy_s" }, >+ { MIPS_INS_COPY_U, "copy_u" }, >+ { MIPS_INS_CTC1, "ctc1" }, >+ { MIPS_INS_CTCMSA, "ctcmsa" }, >+ { MIPS_INS_CVT, "cvt" }, >+ { MIPS_INS_C, "c" }, >+ { MIPS_INS_CMPI, "cmpi" }, >+ { MIPS_INS_DADD, "dadd" }, >+ { MIPS_INS_DADDI, "daddi" }, >+ { MIPS_INS_DADDIU, "daddiu" }, >+ { MIPS_INS_DADDU, "daddu" }, >+ { MIPS_INS_DAHI, "dahi" }, >+ { MIPS_INS_DALIGN, "dalign" }, >+ { MIPS_INS_DATI, "dati" }, >+ { MIPS_INS_DAUI, "daui" }, >+ { MIPS_INS_DBITSWAP, "dbitswap" }, >+ { MIPS_INS_DCLO, "dclo" }, >+ { MIPS_INS_DCLZ, "dclz" }, >+ { MIPS_INS_DDIV, "ddiv" }, >+ { MIPS_INS_DDIVU, "ddivu" }, >+ { MIPS_INS_DERET, "deret" }, >+ { MIPS_INS_DEXT, "dext" }, >+ { MIPS_INS_DEXTM, "dextm" }, >+ { MIPS_INS_DEXTU, "dextu" }, >+ { MIPS_INS_DI, "di" }, >+ { MIPS_INS_DINS, "dins" }, >+ { MIPS_INS_DINSM, "dinsm" }, >+ { MIPS_INS_DINSU, "dinsu" }, >+ { MIPS_INS_DIV, "div" }, >+ { MIPS_INS_DIVU, "divu" }, >+ { MIPS_INS_DIV_S, "div_s" }, >+ { MIPS_INS_DIV_U, "div_u" }, >+ { MIPS_INS_DLSA, "dlsa" }, >+ { MIPS_INS_DMFC0, "dmfc0" }, >+ { MIPS_INS_DMFC1, "dmfc1" }, >+ { MIPS_INS_DMFC2, "dmfc2" }, >+ { MIPS_INS_DMOD, "dmod" }, >+ { MIPS_INS_DMODU, "dmodu" }, >+ { MIPS_INS_DMTC0, "dmtc0" }, >+ { MIPS_INS_DMTC1, "dmtc1" }, >+ { MIPS_INS_DMTC2, "dmtc2" }, >+ { MIPS_INS_DMUH, "dmuh" }, >+ { MIPS_INS_DMUHU, "dmuhu" }, >+ { MIPS_INS_DMUL, "dmul" }, >+ { MIPS_INS_DMULT, "dmult" }, >+ { MIPS_INS_DMULTU, "dmultu" }, >+ { MIPS_INS_DMULU, "dmulu" }, >+ { MIPS_INS_DOTP_S, "dotp_s" }, >+ { MIPS_INS_DOTP_U, "dotp_u" }, >+ { MIPS_INS_DPADD_S, "dpadd_s" }, >+ { MIPS_INS_DPADD_U, "dpadd_u" }, >+ { MIPS_INS_DPAQX_SA, "dpaqx_sa" }, >+ { MIPS_INS_DPAQX_S, "dpaqx_s" }, >+ { MIPS_INS_DPAQ_SA, "dpaq_sa" }, >+ { MIPS_INS_DPAQ_S, "dpaq_s" }, >+ { MIPS_INS_DPAU, "dpau" }, >+ { MIPS_INS_DPAX, "dpax" }, >+ { MIPS_INS_DPA, "dpa" }, >+ { MIPS_INS_DPOP, "dpop" }, >+ { MIPS_INS_DPSQX_SA, "dpsqx_sa" }, >+ { MIPS_INS_DPSQX_S, "dpsqx_s" }, >+ { MIPS_INS_DPSQ_SA, "dpsq_sa" }, >+ { MIPS_INS_DPSQ_S, "dpsq_s" }, >+ { MIPS_INS_DPSUB_S, "dpsub_s" }, >+ { MIPS_INS_DPSUB_U, "dpsub_u" }, >+ { MIPS_INS_DPSU, "dpsu" }, >+ { MIPS_INS_DPSX, "dpsx" }, >+ { MIPS_INS_DPS, "dps" }, >+ { MIPS_INS_DROTR, "drotr" }, >+ { MIPS_INS_DROTR32, "drotr32" }, >+ { MIPS_INS_DROTRV, "drotrv" }, >+ { MIPS_INS_DSBH, "dsbh" }, >+ { MIPS_INS_DSHD, "dshd" }, >+ { MIPS_INS_DSLL, "dsll" }, >+ { MIPS_INS_DSLL32, "dsll32" }, >+ { MIPS_INS_DSLLV, "dsllv" }, >+ { MIPS_INS_DSRA, "dsra" }, >+ { MIPS_INS_DSRA32, "dsra32" }, >+ { MIPS_INS_DSRAV, "dsrav" }, >+ { MIPS_INS_DSRL, "dsrl" }, >+ { MIPS_INS_DSRL32, "dsrl32" }, >+ { MIPS_INS_DSRLV, "dsrlv" }, >+ { MIPS_INS_DSUB, "dsub" }, >+ { MIPS_INS_DSUBU, "dsubu" }, >+ { MIPS_INS_EHB, "ehb" }, >+ { MIPS_INS_EI, "ei" }, >+ { MIPS_INS_ERET, "eret" }, >+ { MIPS_INS_EXT, "ext" }, >+ { MIPS_INS_EXTP, "extp" }, >+ { MIPS_INS_EXTPDP, "extpdp" }, >+ { MIPS_INS_EXTPDPV, "extpdpv" }, >+ { MIPS_INS_EXTPV, "extpv" }, >+ { MIPS_INS_EXTRV_RS, "extrv_rs" }, >+ { MIPS_INS_EXTRV_R, "extrv_r" }, >+ { MIPS_INS_EXTRV_S, "extrv_s" }, >+ { MIPS_INS_EXTRV, "extrv" }, >+ { MIPS_INS_EXTR_RS, "extr_rs" }, >+ { MIPS_INS_EXTR_R, "extr_r" }, >+ { MIPS_INS_EXTR_S, "extr_s" }, >+ { MIPS_INS_EXTR, "extr" }, >+ { MIPS_INS_EXTS, "exts" }, >+ { MIPS_INS_EXTS32, "exts32" }, >+ { MIPS_INS_ABS, "abs" }, >+ { MIPS_INS_FADD, "fadd" }, >+ { MIPS_INS_FCAF, "fcaf" }, >+ { MIPS_INS_FCEQ, "fceq" }, >+ { MIPS_INS_FCLASS, "fclass" }, >+ { MIPS_INS_FCLE, "fcle" }, >+ { MIPS_INS_FCLT, "fclt" }, >+ { MIPS_INS_FCNE, "fcne" }, >+ { MIPS_INS_FCOR, "fcor" }, >+ { MIPS_INS_FCUEQ, "fcueq" }, >+ { MIPS_INS_FCULE, "fcule" }, >+ { MIPS_INS_FCULT, "fcult" }, >+ { MIPS_INS_FCUNE, "fcune" }, >+ { MIPS_INS_FCUN, "fcun" }, >+ { MIPS_INS_FDIV, "fdiv" }, >+ { MIPS_INS_FEXDO, "fexdo" }, >+ { MIPS_INS_FEXP2, "fexp2" }, >+ { MIPS_INS_FEXUPL, "fexupl" }, >+ { MIPS_INS_FEXUPR, "fexupr" }, >+ { MIPS_INS_FFINT_S, "ffint_s" }, >+ { MIPS_INS_FFINT_U, "ffint_u" }, >+ { MIPS_INS_FFQL, "ffql" }, >+ { MIPS_INS_FFQR, "ffqr" }, >+ { MIPS_INS_FILL, "fill" }, >+ { MIPS_INS_FLOG2, "flog2" }, >+ { MIPS_INS_FLOOR, "floor" }, >+ { MIPS_INS_FMADD, "fmadd" }, >+ { MIPS_INS_FMAX_A, "fmax_a" }, >+ { MIPS_INS_FMAX, "fmax" }, >+ { MIPS_INS_FMIN_A, "fmin_a" }, >+ { MIPS_INS_FMIN, "fmin" }, >+ { MIPS_INS_MOV, "mov" }, >+ { MIPS_INS_FMSUB, "fmsub" }, >+ { MIPS_INS_FMUL, "fmul" }, >+ { MIPS_INS_MUL, "mul" }, >+ { MIPS_INS_NEG, "neg" }, >+ { MIPS_INS_FRCP, "frcp" }, >+ { MIPS_INS_FRINT, "frint" }, >+ { MIPS_INS_FRSQRT, "frsqrt" }, >+ { MIPS_INS_FSAF, "fsaf" }, >+ { MIPS_INS_FSEQ, "fseq" }, >+ { MIPS_INS_FSLE, "fsle" }, >+ { MIPS_INS_FSLT, "fslt" }, >+ { MIPS_INS_FSNE, "fsne" }, >+ { MIPS_INS_FSOR, "fsor" }, >+ { MIPS_INS_FSQRT, "fsqrt" }, >+ { MIPS_INS_SQRT, "sqrt" }, >+ { MIPS_INS_FSUB, "fsub" }, >+ { MIPS_INS_SUB, "sub" }, >+ { MIPS_INS_FSUEQ, "fsueq" }, >+ { MIPS_INS_FSULE, "fsule" }, >+ { MIPS_INS_FSULT, "fsult" }, >+ { MIPS_INS_FSUNE, "fsune" }, >+ { MIPS_INS_FSUN, "fsun" }, >+ { MIPS_INS_FTINT_S, "ftint_s" }, >+ { MIPS_INS_FTINT_U, "ftint_u" }, >+ { MIPS_INS_FTQ, "ftq" }, >+ { MIPS_INS_FTRUNC_S, "ftrunc_s" }, >+ { MIPS_INS_FTRUNC_U, "ftrunc_u" }, >+ { MIPS_INS_HADD_S, "hadd_s" }, >+ { MIPS_INS_HADD_U, "hadd_u" }, >+ { MIPS_INS_HSUB_S, "hsub_s" }, >+ { MIPS_INS_HSUB_U, "hsub_u" }, >+ { MIPS_INS_ILVEV, "ilvev" }, >+ { MIPS_INS_ILVL, "ilvl" }, >+ { MIPS_INS_ILVOD, "ilvod" }, >+ { MIPS_INS_ILVR, "ilvr" }, >+ { MIPS_INS_INS, "ins" }, >+ { MIPS_INS_INSERT, "insert" }, >+ { MIPS_INS_INSV, "insv" }, >+ { MIPS_INS_INSVE, "insve" }, >+ { MIPS_INS_J, "j" }, >+ { MIPS_INS_JAL, "jal" }, >+ { MIPS_INS_JALR, "jalr" }, >+ { MIPS_INS_JALRS, "jalrs" }, >+ { MIPS_INS_JALS, "jals" }, >+ { MIPS_INS_JALX, "jalx" }, >+ { MIPS_INS_JIALC, "jialc" }, >+ { MIPS_INS_JIC, "jic" }, >+ { MIPS_INS_JR, "jr" }, >+ { MIPS_INS_JRADDIUSP, "jraddiusp" }, >+ { MIPS_INS_JRC, "jrc" }, >+ { MIPS_INS_JALRC, "jalrc" }, >+ { MIPS_INS_LB, "lb" }, >+ { MIPS_INS_LBUX, "lbux" }, >+ { MIPS_INS_LBU, "lbu" }, >+ { MIPS_INS_LD, "ld" }, >+ { MIPS_INS_LDC1, "ldc1" }, >+ { MIPS_INS_LDC2, "ldc2" }, >+ { MIPS_INS_LDC3, "ldc3" }, >+ { MIPS_INS_LDI, "ldi" }, >+ { MIPS_INS_LDL, "ldl" }, >+ { MIPS_INS_LDPC, "ldpc" }, >+ { MIPS_INS_LDR, "ldr" }, >+ { MIPS_INS_LDXC1, "ldxc1" }, >+ { MIPS_INS_LH, "lh" }, >+ { MIPS_INS_LHX, "lhx" }, >+ { MIPS_INS_LHU, "lhu" }, >+ { MIPS_INS_LL, "ll" }, >+ { MIPS_INS_LLD, "lld" }, >+ { MIPS_INS_LSA, "lsa" }, >+ { MIPS_INS_LUXC1, "luxc1" }, >+ { MIPS_INS_LUI, "lui" }, >+ { MIPS_INS_LW, "lw" }, >+ { MIPS_INS_LWC1, "lwc1" }, >+ { MIPS_INS_LWC2, "lwc2" }, >+ { MIPS_INS_LWC3, "lwc3" }, >+ { MIPS_INS_LWL, "lwl" }, >+ { MIPS_INS_LWPC, "lwpc" }, >+ { MIPS_INS_LWR, "lwr" }, >+ { MIPS_INS_LWUPC, "lwupc" }, >+ { MIPS_INS_LWU, "lwu" }, >+ { MIPS_INS_LWX, "lwx" }, >+ { MIPS_INS_LWXC1, "lwxc1" }, >+ { MIPS_INS_LI, "li" }, >+ { MIPS_INS_MADD, "madd" }, >+ { MIPS_INS_MADDF, "maddf" }, >+ { MIPS_INS_MADDR_Q, "maddr_q" }, >+ { MIPS_INS_MADDU, "maddu" }, >+ { MIPS_INS_MADDV, "maddv" }, >+ { MIPS_INS_MADD_Q, "madd_q" }, >+ { MIPS_INS_MAQ_SA, "maq_sa" }, >+ { MIPS_INS_MAQ_S, "maq_s" }, >+ { MIPS_INS_MAXA, "maxa" }, >+ { MIPS_INS_MAXI_S, "maxi_s" }, >+ { MIPS_INS_MAXI_U, "maxi_u" }, >+ { MIPS_INS_MAX_A, "max_a" }, >+ { MIPS_INS_MAX, "max" }, >+ { MIPS_INS_MAX_S, "max_s" }, >+ { MIPS_INS_MAX_U, "max_u" }, >+ { MIPS_INS_MFC0, "mfc0" }, >+ { MIPS_INS_MFC1, "mfc1" }, >+ { MIPS_INS_MFC2, "mfc2" }, >+ { MIPS_INS_MFHC1, "mfhc1" }, >+ { MIPS_INS_MFHI, "mfhi" }, >+ { MIPS_INS_MFLO, "mflo" }, >+ { MIPS_INS_MINA, "mina" }, >+ { MIPS_INS_MINI_S, "mini_s" }, >+ { MIPS_INS_MINI_U, "mini_u" }, >+ { MIPS_INS_MIN_A, "min_a" }, >+ { MIPS_INS_MIN, "min" }, >+ { MIPS_INS_MIN_S, "min_s" }, >+ { MIPS_INS_MIN_U, "min_u" }, >+ { MIPS_INS_MOD, "mod" }, >+ { MIPS_INS_MODSUB, "modsub" }, >+ { MIPS_INS_MODU, "modu" }, >+ { MIPS_INS_MOD_S, "mod_s" }, >+ { MIPS_INS_MOD_U, "mod_u" }, >+ { MIPS_INS_MOVE, "move" }, >+ { MIPS_INS_MOVF, "movf" }, >+ { MIPS_INS_MOVN, "movn" }, >+ { MIPS_INS_MOVT, "movt" }, >+ { MIPS_INS_MOVZ, "movz" }, >+ { MIPS_INS_MSUB, "msub" }, >+ { MIPS_INS_MSUBF, "msubf" }, >+ { MIPS_INS_MSUBR_Q, "msubr_q" }, >+ { MIPS_INS_MSUBU, "msubu" }, >+ { MIPS_INS_MSUBV, "msubv" }, >+ { MIPS_INS_MSUB_Q, "msub_q" }, >+ { MIPS_INS_MTC0, "mtc0" }, >+ { MIPS_INS_MTC1, "mtc1" }, >+ { MIPS_INS_MTC2, "mtc2" }, >+ { MIPS_INS_MTHC1, "mthc1" }, >+ { MIPS_INS_MTHI, "mthi" }, >+ { MIPS_INS_MTHLIP, "mthlip" }, >+ { MIPS_INS_MTLO, "mtlo" }, >+ { MIPS_INS_MTM0, "mtm0" }, >+ { MIPS_INS_MTM1, "mtm1" }, >+ { MIPS_INS_MTM2, "mtm2" }, >+ { MIPS_INS_MTP0, "mtp0" }, >+ { MIPS_INS_MTP1, "mtp1" }, >+ { MIPS_INS_MTP2, "mtp2" }, >+ { MIPS_INS_MUH, "muh" }, >+ { MIPS_INS_MUHU, "muhu" }, >+ { MIPS_INS_MULEQ_S, "muleq_s" }, >+ { MIPS_INS_MULEU_S, "muleu_s" }, >+ { MIPS_INS_MULQ_RS, "mulq_rs" }, >+ { MIPS_INS_MULQ_S, "mulq_s" }, >+ { MIPS_INS_MULR_Q, "mulr_q" }, >+ { MIPS_INS_MULSAQ_S, "mulsaq_s" }, >+ { MIPS_INS_MULSA, "mulsa" }, >+ { MIPS_INS_MULT, "mult" }, >+ { MIPS_INS_MULTU, "multu" }, >+ { MIPS_INS_MULU, "mulu" }, >+ { MIPS_INS_MULV, "mulv" }, >+ { MIPS_INS_MUL_Q, "mul_q" }, >+ { MIPS_INS_MUL_S, "mul_s" }, >+ { MIPS_INS_NLOC, "nloc" }, >+ { MIPS_INS_NLZC, "nlzc" }, >+ { MIPS_INS_NMADD, "nmadd" }, >+ { MIPS_INS_NMSUB, "nmsub" }, >+ { MIPS_INS_NOR, "nor" }, >+ { MIPS_INS_NORI, "nori" }, >+ { MIPS_INS_NOT, "not" }, >+ { MIPS_INS_OR, "or" }, >+ { MIPS_INS_ORI, "ori" }, >+ { MIPS_INS_PACKRL, "packrl" }, >+ { MIPS_INS_PAUSE, "pause" }, >+ { MIPS_INS_PCKEV, "pckev" }, >+ { MIPS_INS_PCKOD, "pckod" }, >+ { MIPS_INS_PCNT, "pcnt" }, >+ { MIPS_INS_PICK, "pick" }, >+ { MIPS_INS_POP, "pop" }, >+ { MIPS_INS_PRECEQU, "precequ" }, >+ { MIPS_INS_PRECEQ, "preceq" }, >+ { MIPS_INS_PRECEU, "preceu" }, >+ { MIPS_INS_PRECRQU_S, "precrqu_s" }, >+ { MIPS_INS_PRECRQ, "precrq" }, >+ { MIPS_INS_PRECRQ_RS, "precrq_rs" }, >+ { MIPS_INS_PRECR, "precr" }, >+ { MIPS_INS_PRECR_SRA, "precr_sra" }, >+ { MIPS_INS_PRECR_SRA_R, "precr_sra_r" }, >+ { MIPS_INS_PREF, "pref" }, >+ { MIPS_INS_PREPEND, "prepend" }, >+ { MIPS_INS_RADDU, "raddu" }, >+ { MIPS_INS_RDDSP, "rddsp" }, >+ { MIPS_INS_RDHWR, "rdhwr" }, >+ { MIPS_INS_REPLV, "replv" }, >+ { MIPS_INS_REPL, "repl" }, >+ { MIPS_INS_RINT, "rint" }, >+ { MIPS_INS_ROTR, "rotr" }, >+ { MIPS_INS_ROTRV, "rotrv" }, >+ { MIPS_INS_ROUND, "round" }, >+ { MIPS_INS_SAT_S, "sat_s" }, >+ { MIPS_INS_SAT_U, "sat_u" }, >+ { MIPS_INS_SB, "sb" }, >+ { MIPS_INS_SC, "sc" }, >+ { MIPS_INS_SCD, "scd" }, >+ { MIPS_INS_SD, "sd" }, >+ { MIPS_INS_SDBBP, "sdbbp" }, >+ { MIPS_INS_SDC1, "sdc1" }, >+ { MIPS_INS_SDC2, "sdc2" }, >+ { MIPS_INS_SDC3, "sdc3" }, >+ { MIPS_INS_SDL, "sdl" }, >+ { MIPS_INS_SDR, "sdr" }, >+ { MIPS_INS_SDXC1, "sdxc1" }, >+ { MIPS_INS_SEB, "seb" }, >+ { MIPS_INS_SEH, "seh" }, >+ { MIPS_INS_SELEQZ, "seleqz" }, >+ { MIPS_INS_SELNEZ, "selnez" }, >+ { MIPS_INS_SEL, "sel" }, >+ { MIPS_INS_SEQ, "seq" }, >+ { MIPS_INS_SEQI, "seqi" }, >+ { MIPS_INS_SH, "sh" }, >+ { MIPS_INS_SHF, "shf" }, >+ { MIPS_INS_SHILO, "shilo" }, >+ { MIPS_INS_SHILOV, "shilov" }, >+ { MIPS_INS_SHLLV, "shllv" }, >+ { MIPS_INS_SHLLV_S, "shllv_s" }, >+ { MIPS_INS_SHLL, "shll" }, >+ { MIPS_INS_SHLL_S, "shll_s" }, >+ { MIPS_INS_SHRAV, "shrav" }, >+ { MIPS_INS_SHRAV_R, "shrav_r" }, >+ { MIPS_INS_SHRA, "shra" }, >+ { MIPS_INS_SHRA_R, "shra_r" }, >+ { MIPS_INS_SHRLV, "shrlv" }, >+ { MIPS_INS_SHRL, "shrl" }, >+ { MIPS_INS_SLDI, "sldi" }, >+ { MIPS_INS_SLD, "sld" }, >+ { MIPS_INS_SLL, "sll" }, >+ { MIPS_INS_SLLI, "slli" }, >+ { MIPS_INS_SLLV, "sllv" }, >+ { MIPS_INS_SLT, "slt" }, >+ { MIPS_INS_SLTI, "slti" }, >+ { MIPS_INS_SLTIU, "sltiu" }, >+ { MIPS_INS_SLTU, "sltu" }, >+ { MIPS_INS_SNE, "sne" }, >+ { MIPS_INS_SNEI, "snei" }, >+ { MIPS_INS_SPLATI, "splati" }, >+ { MIPS_INS_SPLAT, "splat" }, >+ { MIPS_INS_SRA, "sra" }, >+ { MIPS_INS_SRAI, "srai" }, >+ { MIPS_INS_SRARI, "srari" }, >+ { MIPS_INS_SRAR, "srar" }, >+ { MIPS_INS_SRAV, "srav" }, >+ { MIPS_INS_SRL, "srl" }, >+ { MIPS_INS_SRLI, "srli" }, >+ { MIPS_INS_SRLRI, "srlri" }, >+ { MIPS_INS_SRLR, "srlr" }, >+ { MIPS_INS_SRLV, "srlv" }, >+ { MIPS_INS_SSNOP, "ssnop" }, >+ { MIPS_INS_ST, "st" }, >+ { MIPS_INS_SUBQH, "subqh" }, >+ { MIPS_INS_SUBQH_R, "subqh_r" }, >+ { MIPS_INS_SUBQ, "subq" }, >+ { MIPS_INS_SUBQ_S, "subq_s" }, >+ { MIPS_INS_SUBSUS_U, "subsus_u" }, >+ { MIPS_INS_SUBSUU_S, "subsuu_s" }, >+ { MIPS_INS_SUBS_S, "subs_s" }, >+ { MIPS_INS_SUBS_U, "subs_u" }, >+ { MIPS_INS_SUBUH, "subuh" }, >+ { MIPS_INS_SUBUH_R, "subuh_r" }, >+ { MIPS_INS_SUBU, "subu" }, >+ { MIPS_INS_SUBU_S, "subu_s" }, >+ { MIPS_INS_SUBVI, "subvi" }, >+ { MIPS_INS_SUBV, "subv" }, >+ { MIPS_INS_SUXC1, "suxc1" }, >+ { MIPS_INS_SW, "sw" }, >+ { MIPS_INS_SWC1, "swc1" }, >+ { MIPS_INS_SWC2, "swc2" }, >+ { MIPS_INS_SWC3, "swc3" }, >+ { MIPS_INS_SWL, "swl" }, >+ { MIPS_INS_SWR, "swr" }, >+ { MIPS_INS_SWXC1, "swxc1" }, >+ { MIPS_INS_SYNC, "sync" }, >+ { MIPS_INS_SYSCALL, "syscall" }, >+ { MIPS_INS_TEQ, "teq" }, >+ { MIPS_INS_TEQI, "teqi" }, >+ { MIPS_INS_TGE, "tge" }, >+ { MIPS_INS_TGEI, "tgei" }, >+ { MIPS_INS_TGEIU, "tgeiu" }, >+ { MIPS_INS_TGEU, "tgeu" }, >+ { MIPS_INS_TLBP, "tlbp" }, >+ { MIPS_INS_TLBR, "tlbr" }, >+ { MIPS_INS_TLBWI, "tlbwi" }, >+ { MIPS_INS_TLBWR, "tlbwr" }, >+ { MIPS_INS_TLT, "tlt" }, >+ { MIPS_INS_TLTI, "tlti" }, >+ { MIPS_INS_TLTIU, "tltiu" }, >+ { MIPS_INS_TLTU, "tltu" }, >+ { MIPS_INS_TNE, "tne" }, >+ { MIPS_INS_TNEI, "tnei" }, >+ { MIPS_INS_TRUNC, "trunc" }, >+ { MIPS_INS_V3MULU, "v3mulu" }, >+ { MIPS_INS_VMM0, "vmm0" }, >+ { MIPS_INS_VMULU, "vmulu" }, >+ { MIPS_INS_VSHF, "vshf" }, >+ { MIPS_INS_WAIT, "wait" }, >+ { MIPS_INS_WRDSP, "wrdsp" }, >+ { MIPS_INS_WSBH, "wsbh" }, >+ { MIPS_INS_XOR, "xor" }, >+ { MIPS_INS_XORI, "xori" }, >+ >+ // alias instructions >+ { MIPS_INS_NOP, "nop" }, >+ { MIPS_INS_NEGU, "negu" }, >+ >+ { MIPS_INS_JALR_HB, "jalr.hb" }, >+ { MIPS_INS_JR_HB, "jr.hb" }, >+}; >+ >+const char *Mips_insn_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ if (id >= MIPS_INS_ENDING) >+ return NULL; >+ >+ return insn_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+#ifndef CAPSTONE_DIET >+static const name_map group_name_maps[] = { >+ // generic groups >+ { MIPS_GRP_INVALID, NULL }, >+ { MIPS_GRP_JUMP, "jump" }, >+ >+ // architecture-specific groups >+ { MIPS_GRP_BITCOUNT, "bitcount" }, >+ { MIPS_GRP_DSP, "dsp" }, >+ { MIPS_GRP_DSPR2, "dspr2" }, >+ { MIPS_GRP_FPIDX, "fpidx" }, >+ { MIPS_GRP_MSA, "msa" }, >+ { MIPS_GRP_MIPS32R2, "mips32r2" }, >+ { MIPS_GRP_MIPS64, "mips64" }, >+ { MIPS_GRP_MIPS64R2, "mips64r2" }, >+ { MIPS_GRP_SEINREG, "seinreg" }, >+ { MIPS_GRP_STDENC, "stdenc" }, >+ { MIPS_GRP_SWAP, "swap" }, >+ { MIPS_GRP_MICROMIPS, "micromips" }, >+ { MIPS_GRP_MIPS16MODE, "mips16mode" }, >+ { MIPS_GRP_FP64BIT, "fp64bit" }, >+ { MIPS_GRP_NONANSFPMATH, "nonansfpmath" }, >+ { MIPS_GRP_NOTFP64BIT, "notfp64bit" }, >+ { MIPS_GRP_NOTINMICROMIPS, "notinmicromips" }, >+ { MIPS_GRP_NOTNACL, "notnacl" }, >+ >+ { MIPS_GRP_NOTMIPS32R6, "notmips32r6" }, >+ { MIPS_GRP_NOTMIPS64R6, "notmips64r6" }, >+ { MIPS_GRP_CNMIPS, "cnmips" }, >+ >+ { MIPS_GRP_MIPS32, "mips32" }, >+ { MIPS_GRP_MIPS32R6, "mips32r6" }, >+ { MIPS_GRP_MIPS64R6, "mips64r6" }, >+ >+ { MIPS_GRP_MIPS2, "mips2" }, >+ { MIPS_GRP_MIPS3, "mips3" }, >+ { MIPS_GRP_MIPS3_32, "mips3_32"}, >+ { MIPS_GRP_MIPS3_32R2, "mips3_32r2" }, >+ >+ { MIPS_GRP_MIPS4_32, "mips4_32" }, >+ { MIPS_GRP_MIPS4_32R2, "mips4_32r2" }, >+ { MIPS_GRP_MIPS5_32R2, "mips5_32r2" }, >+ >+ { MIPS_GRP_GP32BIT, "gp32bit" }, >+ { MIPS_GRP_GP64BIT, "gp64bit" }, >+}; >+#endif >+ >+const char *Mips_group_name(csh handle, unsigned int id) >+{ >+#ifndef CAPSTONE_DIET >+ // verify group id >+ if (id >= MIPS_GRP_ENDING || (id > MIPS_GRP_JUMP && id < MIPS_GRP_BITCOUNT)) >+ return NULL; >+ >+ // NOTE: when new generic groups are added, 2 must be changed accordingly >+ if (id >= 128) >+ return group_name_maps[id - 128 + 2].name; >+ else >+ return group_name_maps[id].name; >+#else >+ return NULL; >+#endif >+} >+ >+// map instruction name to public instruction ID >+mips_reg Mips_map_insn(const char *name) >+{ >+ // handle special alias first >+ unsigned int i; >+ >+ // NOTE: skip first NULL name in insn_name_maps >+ i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); >+ >+ return (i != -1)? i : MIPS_REG_INVALID; >+} >+ >+// map internal raw register to 'public' register >+mips_reg Mips_map_register(unsigned int r) >+{ >+ // for some reasons different Mips modes can map different register number to >+ // the same Mips register. this function handles the issue for exposing Mips >+ // operands by mapping internal registers to 'public' register. >+ static const unsigned int map[] = { 0, >+ MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG, >+ MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2, >+ MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5, >+ MIPS_REG_3, MIPS_REG_7, 0, MIPS_REG_RA, MIPS_REG_SP, >+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, >+ MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT, >+ MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4, >+ MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1, >+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, >+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1, >+ MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, >+ MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, >+ MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, >+ MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, >+ MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, >+ MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, >+ MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, >+ MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, >+ MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, >+ MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, >+ MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4, >+ MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14, >+ MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24, >+ MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21, >+ MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, >+ MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, >+ MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, >+ MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, >+ MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, >+ MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, >+ MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0, >+ MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5, >+ MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, >+ MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, >+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, >+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, >+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, >+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, >+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP, >+ MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4, >+ MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9, >+ MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14, >+ MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19, >+ MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24, >+ MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29, >+ MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1, >+ MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2, >+ MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7, >+ MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, >+ MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, >+ MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, >+ MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, >+ MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0, >+ MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, >+ MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, >+ MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2, >+ MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7, >+ MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, >+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, >+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1, >+ MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6, >+ MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11, >+ MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16, >+ MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21, >+ MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26, >+ MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31, >+ MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3, >+ MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, >+ MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, >+ MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, >+ MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, >+ MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, >+ MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, >+ MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI, >+ MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1, >+ MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, >+ MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3, >+ MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8, >+ MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, >+ }; >+ >+ if (r < ARR_SIZE(map)) >+ return map[r]; >+ >+ // cannot find this register >+ return 0; >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h b/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h >new file mode 100644 >index 0000000000000000000000000000000000000000..f6d4b4fda766631b6222047dd4cb955fc5e0812f >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsMapping.h >@@ -0,0 +1,25 @@ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_MIPS_MAP_H >+#define CS_MIPS_MAP_H >+ >+#include "../../include/capstone.h" >+ >+// return name of regiser in friendly string >+const char *Mips_reg_name(csh handle, unsigned int reg); >+ >+// given internal insn id, return public instruction info >+void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); >+ >+const char *Mips_insn_name(csh handle, unsigned int id); >+ >+const char *Mips_group_name(csh handle, unsigned int id); >+ >+// map instruction name to instruction ID >+mips_reg Mips_map_insn(const char *name); >+ >+// map internal raw register to 'public' register >+mips_reg Mips_map_register(unsigned int r); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c b/Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c >new file mode 100644 >index 0000000000000000000000000000000000000000..59361214ad08751cea17913779775c897964e7ea >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/Mips/MipsModule.c >@@ -0,0 +1,76 @@ >+/* Capstone Disassembly Engine */ >+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */ >+ >+#ifdef CAPSTONE_HAS_MIPS >+ >+#include "../../utils.h" >+#include "../../MCRegisterInfo.h" >+#include "MipsDisassembler.h" >+#include "MipsInstPrinter.h" >+#include "MipsMapping.h" >+ >+// Returns mode value with implied bits set >+static inline cs_mode updated_mode(cs_mode mode) >+{ >+ if (mode & CS_MODE_MIPS32R6) { >+ mode |= CS_MODE_32; >+ } >+ >+ return mode; >+} >+ >+static cs_err init(cs_struct *ud) >+{ >+ MCRegisterInfo *mri; >+ mri = cs_mem_malloc(sizeof(*mri)); >+ >+ Mips_init(mri); >+ ud->printer = Mips_printInst; >+ ud->printer_info = mri; >+ ud->getinsn_info = mri; >+ ud->reg_name = Mips_reg_name; >+ ud->insn_id = Mips_get_insn_id; >+ ud->insn_name = Mips_insn_name; >+ ud->group_name = Mips_group_name; >+ >+ ud->mode = updated_mode(ud->mode); >+ if (ud->mode & CS_MODE_32) >+ ud->disasm = Mips_getInstruction; >+ else >+ ud->disasm = Mips64_getInstruction; >+ >+ return CS_ERR_OK; >+} >+ >+static cs_err option(cs_struct *handle, cs_opt_type type, size_t value) >+{ >+ if (type == CS_OPT_MODE) { >+ value = updated_mode((cs_mode)value); >+ if (value & CS_MODE_32) >+ handle->disasm = Mips_getInstruction; >+ else >+ handle->disasm = Mips64_getInstruction; >+ >+ handle->mode = (cs_mode)value; >+ } >+ return CS_ERR_OK; >+} >+ >+static void destroy(cs_struct *handle) >+{ >+} >+ >+void Mips_enable(void) >+{ >+ cs_arch_init[CS_ARCH_MIPS] = init; >+ cs_arch_option[CS_ARCH_MIPS] = option; >+ cs_arch_destroy[CS_ARCH_MIPS] = destroy; >+ cs_arch_disallowed_mode_mask[CS_ARCH_MIPS] = ~(CS_MODE_LITTLE_ENDIAN | >+ CS_MODE_32 | CS_MODE_64 | CS_MODE_MICRO | CS_MODE_MIPS32R6 | >+ CS_MODE_MIPSGP64 | CS_MODE_BIG_ENDIAN); >+ >+ // support this arch >+ all_arch |= (1 << CS_ARCH_MIPS); >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86ATTInstPrinter.c b/Source/ThirdParty/capstone/Source/arch/X86/X86ATTInstPrinter.c >new file mode 100644 >index 0000000000000000000000000000000000000000..358deeb62b38b84032d15af0b54045c054430ff0 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86ATTInstPrinter.c >@@ -0,0 +1,864 @@ >+//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file includes code for rendering MCInst instances as AT&T-style >+// assembly. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+// this code is only relevant when DIET mode is disable >+#if defined(CAPSTONE_HAS_X86) && !defined(CAPSTONE_DIET) && !defined(CAPSTONE_X86_ATT_DISABLE) >+ >+#if !defined(CAPSTONE_HAS_OSXKERNEL) >+#include <ctype.h> >+#endif >+#include <platform.h> >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#include <stdlib.h> >+#endif >+ >+#include <string.h> >+ >+#include "../../utils.h" >+#include "../../MCInst.h" >+#include "../../SStream.h" >+#include "../../MCRegisterInfo.h" >+#include "X86Mapping.h" >+#include "X86BaseInfo.h" >+ >+ >+#define GET_INSTRINFO_ENUM >+#ifdef CAPSTONE_X86_REDUCE >+#include "X86GenInstrInfo_reduce.inc" >+#else >+#include "X86GenInstrInfo.inc" >+#endif >+ >+static void printMemReference(MCInst *MI, unsigned Op, SStream *O); >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); >+ >+ >+static void set_mem_access(MCInst *MI, bool status) >+{ >+ if (MI->csh->detail != CS_OPT_ON) >+ return; >+ >+ MI->csh->doing_mem = status; >+ if (!status) >+ // done, create the next operand slot >+ MI->flat_insn->detail->x86.op_count++; >+} >+ >+static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ switch(MI->csh->mode) { >+ case CS_MODE_16: >+ MI->x86opsize = 2; >+ break; >+ case CS_MODE_32: >+ MI->x86opsize = 4; >+ break; >+ case CS_MODE_64: >+ MI->x86opsize = 8; >+ break; >+ default: // never reach >+ break; >+ } >+ >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 1; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 2; >+ >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 4; >+ >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 8; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 16; >+ printMemReference(MI, OpNo, O); >+} >+ >+#ifndef CAPSTONE_X86_REDUCE >+static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 32; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 64; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 4; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 8; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 10; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 16; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 32; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 64; >+ printMemReference(MI, OpNo, O); >+} >+ >+static void printSSECC(MCInst *MI, unsigned Op, SStream *OS) >+{ >+ int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7; >+ switch (Imm) { >+ default: break; // never reach >+ case 0: SStream_concat0(OS, "eq"); op_addSseCC(MI, X86_SSE_CC_EQ); break; >+ case 1: SStream_concat0(OS, "lt"); op_addSseCC(MI, X86_SSE_CC_LT); break; >+ case 2: SStream_concat0(OS, "le"); op_addSseCC(MI, X86_SSE_CC_LE); break; >+ case 3: SStream_concat0(OS, "unord"); op_addSseCC(MI, X86_SSE_CC_UNORD); break; >+ case 4: SStream_concat0(OS, "neq"); op_addSseCC(MI, X86_SSE_CC_NEQ); break; >+ case 5: SStream_concat0(OS, "nlt"); op_addSseCC(MI, X86_SSE_CC_NLT); break; >+ case 6: SStream_concat0(OS, "nle"); op_addSseCC(MI, X86_SSE_CC_NLE); break; >+ case 7: SStream_concat0(OS, "ord"); op_addSseCC(MI, X86_SSE_CC_ORD); break; >+ case 8: SStream_concat0(OS, "eq_uq"); op_addSseCC(MI, X86_SSE_CC_EQ_UQ); break; >+ case 9: SStream_concat0(OS, "nge"); op_addSseCC(MI, X86_SSE_CC_NGE); break; >+ case 0xa: SStream_concat0(OS, "ngt"); op_addSseCC(MI, X86_SSE_CC_NGT); break; >+ case 0xb: SStream_concat0(OS, "false"); op_addSseCC(MI, X86_SSE_CC_FALSE); break; >+ case 0xc: SStream_concat0(OS, "neq_oq"); op_addSseCC(MI, X86_SSE_CC_NEQ_OQ); break; >+ case 0xd: SStream_concat0(OS, "ge"); op_addSseCC(MI, X86_SSE_CC_GE); break; >+ case 0xe: SStream_concat0(OS, "gt"); op_addSseCC(MI, X86_SSE_CC_GT); break; >+ case 0xf: SStream_concat0(OS, "true"); op_addSseCC(MI, X86_SSE_CC_TRUE); break; >+ } >+} >+ >+static void printAVXCC(MCInst *MI, unsigned Op, SStream *O) >+{ >+ int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f; >+ switch (Imm) { >+ default: break;//printf("Invalid avxcc argument!\n"); break; >+ case 0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break; >+ case 1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break; >+ case 2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break; >+ case 3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break; >+ case 4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break; >+ case 5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break; >+ case 6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break; >+ case 7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break; >+ case 8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break; >+ case 9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break; >+ case 0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break; >+ case 0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break; >+ case 0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break; >+ case 0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break; >+ case 0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break; >+ case 0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break; >+ case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break; >+ case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break; >+ case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break; >+ case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break; >+ case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break; >+ case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break; >+ case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break; >+ case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break; >+ case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break; >+ case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break; >+ case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break; >+ case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break; >+ case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break; >+ case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break; >+ case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break; >+ case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break; >+ } >+} >+ >+static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O) >+{ >+ int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3; >+ switch (Imm) { >+ case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break; >+ case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break; >+ case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break; >+ case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break; >+ default: break; // nev0er reach >+ } >+} >+ >+#endif >+ >+static void printRegName(SStream *OS, unsigned RegNo); >+ >+// local printOperand, without updating public operands >+static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ printRegName(O, MCOperand_getReg(Op)); >+ } else if (MCOperand_isImm(Op)) { >+ // Print X86 immediates as signed values. >+ int64_t imm = MCOperand_getImm(Op); >+ if (imm < 0) { >+ if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "$-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "$-%"PRIu64, -imm); >+ } else { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "$0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "$%"PRIu64, imm); >+ } >+ } >+} >+ >+static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *SegReg; >+ int reg; >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; >+ } >+ >+ SegReg = MCInst_getOperand(MI, Op+1); >+ reg = MCOperand_getReg(SegReg); >+ >+ // If this has a segment register, print it. >+ if (reg) { >+ _printOperand(MI, Op+1, O); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg; >+ } >+ >+ SStream_concat0(O, ":"); >+ } >+ >+ SStream_concat0(O, "("); >+ set_mem_access(MI, true); >+ >+ printOperand(MI, Op, O); >+ >+ SStream_concat0(O, ")"); >+ set_mem_access(MI, false); >+} >+ >+static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) >+{ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; >+ } >+ >+ // DI accesses are always ES-based on non-64bit mode >+ if (MI->csh->mode != CS_MODE_64) { >+ SStream_concat0(O, "%es:("); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES; >+ } >+ } else >+ SStream_concat0(O, "("); >+ >+ set_mem_access(MI, true); >+ >+ printOperand(MI, Op, O); >+ >+ SStream_concat0(O, ")"); >+ set_mem_access(MI, false); >+} >+ >+static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 1; >+ printSrcIdx(MI, OpNo, O); >+} >+ >+static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 2; >+ printSrcIdx(MI, OpNo, O); >+} >+ >+static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 4; >+ printSrcIdx(MI, OpNo, O); >+} >+ >+static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 8; >+ printSrcIdx(MI, OpNo, O); >+} >+ >+static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 1; >+ printDstIdx(MI, OpNo, O); >+} >+ >+static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 2; >+ printDstIdx(MI, OpNo, O); >+} >+ >+static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 4; >+ printDstIdx(MI, OpNo, O); >+} >+ >+static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 8; >+ printDstIdx(MI, OpNo, O); >+} >+ >+static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *DispSpec = MCInst_getOperand(MI, Op); >+ MCOperand *SegReg = MCInst_getOperand(MI, Op+1); >+ int reg; >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; >+ } >+ >+ // If this has a segment register, print it. >+ reg = MCOperand_getReg(SegReg); >+ if (reg) { >+ _printOperand(MI, Op + 1, O); >+ SStream_concat0(O, ":"); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg; >+ } >+ } >+ >+ if (MCOperand_isImm(DispSpec)) { >+ int64_t imm = MCOperand_getImm(DispSpec); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; >+ if (imm < 0) { >+ SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); >+ } else { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } >+ } >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->x86.op_count++; >+} >+ >+static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 1; >+ printMemOffset(MI, OpNo, O); >+} >+ >+static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 2; >+ printMemOffset(MI, OpNo, O); >+} >+ >+static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 4; >+ printMemOffset(MI, OpNo, O); >+} >+ >+static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MI->x86opsize = 8; >+ printMemOffset(MI, OpNo, O); >+} >+ >+/// printPCRelImm - This is used to print an immediate value that ends up >+/// being encoded as a pc-relative value (e.g. for jumps and calls). These >+/// print slightly differently than normal immediates. For example, a $ is not >+/// emitted. >+static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isImm(Op)) { >+ int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; >+ >+ // truncat imm for non-64bit >+ if (MI->csh->mode != CS_MODE_64) { >+ imm = imm & 0xffffffff; >+ } >+ >+ if (MI->csh->mode == CS_MODE_16 && >+ (MI->Opcode != X86_JMP_4 && MI->Opcode != X86_CALLpcrel32)) >+ imm = imm & 0xffff; >+ >+ // Hack: X86 16bit with opcode X86_JMP_4 >+ if (MI->csh->mode == CS_MODE_16 && >+ (MI->Opcode == X86_JMP_4 && MI->x86_prefix[2] != 0x66)) >+ imm = imm & 0xffff; >+ >+ // CALL/JMP rel16 is special >+ if (MI->Opcode == X86_CALLpcrel16 || MI->Opcode == X86_JMP_2) >+ imm = imm & 0xffff; >+ >+ if (imm < 0) { >+ SStream_concat(O, "0x%"PRIx64, imm); >+ } else { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "%"PRIu64, imm); >+ } >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; >+ MI->has_imm = true; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; >+ MI->flat_insn->detail->x86.op_count++; >+ } >+ } >+} >+ >+static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) >+{ >+ MCOperand *Op = MCInst_getOperand(MI, OpNo); >+ if (MCOperand_isReg(Op)) { >+ unsigned int reg = MCOperand_getReg(Op); >+ printRegName(O, reg); >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg; >+ } else { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg]; >+ >+ MI->flat_insn->detail->x86.op_count++; >+ } >+ } >+ } else if (MCOperand_isImm(Op)) { >+ // Print X86 immediates as signed values. >+ int64_t imm = MCOperand_getImm(Op); >+ int opsize = X86_immediate_size(MCInst_getOpcode(MI)); >+ if (opsize == 1) // print 1 byte immediate in positive form >+ imm = imm & 0xff; >+ >+ switch(MI->flat_insn->id) { >+ default: >+ if (imm >= 0) { >+ if (imm > HEX_THRESHOLD) >+ SStream_concat(O, "$0x%"PRIx64, imm); >+ else >+ SStream_concat(O, "$%"PRIu64, imm); >+ } else { >+ if (imm == 0x8000000000000000LL) // imm == -imm >+ SStream_concat0(O, "$0x8000000000000000"); >+ else if (imm < -HEX_THRESHOLD) >+ SStream_concat(O, "$-0x%"PRIx64, -imm); >+ else >+ SStream_concat(O, "$-%"PRIu64, -imm); >+ } >+ break; >+ >+ case X86_INS_MOVABS: >+ // do not print number in negative form >+ SStream_concat(O, "$0x%"PRIx64, imm); >+ break; >+ >+ case X86_INS_IN: >+ case X86_INS_OUT: >+ case X86_INS_INT: >+ // do not print number in negative form >+ imm = imm & 0xff; >+ if (imm >= 0 && imm <= HEX_THRESHOLD) >+ SStream_concat(O, "$%u", imm); >+ else { >+ SStream_concat(O, "$0x%x", imm); >+ } >+ break; >+ >+ case X86_INS_LCALL: >+ case X86_INS_LJMP: >+ // always print address in positive form >+ if (OpNo == 1) { // selector is ptr16 >+ imm = imm & 0xffff; >+ opsize = 2; >+ } >+ SStream_concat(O, "$0x%"PRIx64, imm); >+ break; >+ >+ case X86_INS_AND: >+ case X86_INS_OR: >+ case X86_INS_XOR: >+ // do not print number in negative form >+ if (imm >= 0 && imm <= HEX_THRESHOLD) >+ SStream_concat(O, "$%u", imm); >+ else { >+ imm = arch_masks[opsize? opsize : MI->imm_size] & imm; >+ SStream_concat(O, "$0x%"PRIx64, imm); >+ } >+ break; >+ >+ case X86_INS_RET: >+ // RET imm16 >+ if (imm >= 0 && imm <= HEX_THRESHOLD) >+ SStream_concat(O, "$%u", imm); >+ else { >+ imm = 0xffff & imm; >+ SStream_concat(O, "$0x%x", imm); >+ } >+ break; >+ } >+ >+ if (MI->csh->detail) { >+ if (MI->csh->doing_mem) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; >+ } else { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; >+ MI->has_imm = true; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm; >+ >+ if (opsize > 0) >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = (uint8_t)opsize; >+ else if (MI->op1_size > 0) >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size; >+ else >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size; >+ >+ MI->flat_insn->detail->x86.op_count++; >+ } >+ } >+ } >+} >+ >+static void printMemReference(MCInst *MI, unsigned Op, SStream *O) >+{ >+ MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg); >+ MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg); >+ MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp); >+ MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg); >+ uint64_t ScaleVal; >+ int segreg; >+ >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = MCOperand_getReg(BaseReg); >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = MCOperand_getReg(IndexReg); >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1; >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0; >+ } >+ >+ // If this has a segment register, print it. >+ segreg = MCOperand_getReg(SegReg); >+ if (segreg) { >+ _printOperand(MI, Op + X86_AddrSegmentReg, O); >+ if (MI->csh->detail) { >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = segreg; >+ } >+ >+ SStream_concat0(O, ":"); >+ } >+ >+ if (MCOperand_isImm(DispSpec)) { >+ int64_t DispVal = MCOperand_getImm(DispSpec); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal; >+ if (DispVal) { >+ if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { >+ if (DispVal < 0) { >+ if (DispVal < -HEX_THRESHOLD) >+ SStream_concat(O, "-0x%"PRIx64, -DispVal); >+ else >+ SStream_concat(O, "-%"PRIu64, -DispVal); >+ } else { >+ if (DispVal > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, DispVal); >+ else >+ SStream_concat(O, "%"PRIu64, DispVal); >+ } >+ } else { >+ // only immediate as address of memory >+ if (DispVal < 0) { >+ SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); >+ } else { >+ if (DispVal > HEX_THRESHOLD) >+ SStream_concat(O, "0x%"PRIx64, DispVal); >+ else >+ SStream_concat(O, "%"PRIu64, DispVal); >+ } >+ } >+ } else { >+ SStream_concat0(O, "0"); >+ } >+ } >+ >+ if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { >+ SStream_concat0(O, "("); >+ >+ if (MCOperand_getReg(BaseReg)) >+ _printOperand(MI, Op + X86_AddrBaseReg, O); >+ >+ if (MCOperand_getReg(IndexReg)) { >+ SStream_concat0(O, ", "); >+ _printOperand(MI, Op + X86_AddrIndexReg, O); >+ ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt)); >+ if (MI->csh->detail) >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal; >+ if (ScaleVal != 1) { >+ SStream_concat(O, ", %u", ScaleVal); >+ } >+ } >+ SStream_concat0(O, ")"); >+ } >+ >+ if (MI->csh->detail) >+ MI->flat_insn->detail->x86.op_count++; >+} >+ >+#include "X86InstPrinter.h" >+ >+#define GET_REGINFO_ENUM >+#include "X86GenRegisterInfo.inc" >+ >+// Include the auto-generated portion of the assembly writer. >+#define PRINT_ALIAS_INSTR >+#ifdef CAPSTONE_X86_REDUCE >+#include "X86GenAsmWriter_reduce.inc" >+#else >+#include "X86GenAsmWriter.inc" >+#endif >+ >+static void printRegName(SStream *OS, unsigned RegNo) >+{ >+ SStream_concat(OS, "%%%s", getRegisterName(RegNo)); >+} >+ >+void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) >+{ >+ char *mnem; >+ x86_reg reg, reg2; >+ int i; >+ >+ // Output CALLpcrel32 as "callq" in 64-bit mode. >+ // In Intel annotation it's always emitted as "call". >+ // >+ // TODO: Probably this hack should be redesigned via InstAlias in >+ // InstrInfo.td as soon as Requires clause is supported properly >+ // for InstAlias. >+ if (MI->csh->mode == CS_MODE_64 && MCInst_getOpcode(MI) == X86_CALLpcrel32) { >+ SStream_concat0(OS, "callq\t"); >+ MCInst_setOpcodePub(MI, X86_INS_CALL); >+ printPCRelImm(MI, 0, OS); >+ return; >+ } >+ >+ // Try to print any aliases first. >+ mnem = printAliasInstr(MI, OS, info); >+ if (mnem) >+ cs_mem_free(mnem); >+ else >+ printInstruction(MI, OS, info); >+ >+ // HACK TODO: fix this in machine description >+ switch(MI->flat_insn->id) { >+ default: break; >+ case X86_INS_SYSEXIT: >+ SStream_Init(OS); >+ SStream_concat0(OS, "sysexit"); >+ break; >+ } >+ >+ if (MI->has_imm) { >+ // if op_count > 1, then this operand's size is taken from the destination op >+ if (MI->flat_insn->detail->x86.op_count > 1) { >+ if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) { >+ for (i = 0; i < MI->flat_insn->detail->x86.op_count; i++) { >+ if (MI->flat_insn->detail->x86.operands[i].type == X86_OP_IMM) >+ MI->flat_insn->detail->x86.operands[i].size = >+ MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count - 1].size; >+ } >+ } >+ } else >+ MI->flat_insn->detail->x86.operands[0].size = MI->imm_size; >+ } >+ >+ if (MI->csh->detail) { >+ // some instructions need to supply immediate 1 in the first op >+ switch(MCInst_getOpcode(MI)) { >+ default: >+ break; >+ case X86_SHL8r1: >+ case X86_SHL16r1: >+ case X86_SHL32r1: >+ case X86_SHL64r1: >+ case X86_SAL8r1: >+ case X86_SAL16r1: >+ case X86_SAL32r1: >+ case X86_SAL64r1: >+ case X86_SHR8r1: >+ case X86_SHR16r1: >+ case X86_SHR32r1: >+ case X86_SHR64r1: >+ case X86_SAR8r1: >+ case X86_SAR16r1: >+ case X86_SAR32r1: >+ case X86_SAR64r1: >+ case X86_RCL8r1: >+ case X86_RCL16r1: >+ case X86_RCL32r1: >+ case X86_RCL64r1: >+ case X86_RCR8r1: >+ case X86_RCR16r1: >+ case X86_RCR32r1: >+ case X86_RCR64r1: >+ case X86_ROL8r1: >+ case X86_ROL16r1: >+ case X86_ROL32r1: >+ case X86_ROL64r1: >+ case X86_ROR8r1: >+ case X86_ROR16r1: >+ case X86_ROR32r1: >+ case X86_ROR64r1: >+ case X86_SHL8m1: >+ case X86_SHL16m1: >+ case X86_SHL32m1: >+ case X86_SHL64m1: >+ case X86_SAL8m1: >+ case X86_SAL16m1: >+ case X86_SAL32m1: >+ case X86_SAL64m1: >+ case X86_SHR8m1: >+ case X86_SHR16m1: >+ case X86_SHR32m1: >+ case X86_SHR64m1: >+ case X86_SAR8m1: >+ case X86_SAR16m1: >+ case X86_SAR32m1: >+ case X86_SAR64m1: >+ case X86_RCL8m1: >+ case X86_RCL16m1: >+ case X86_RCL32m1: >+ case X86_RCL64m1: >+ case X86_RCR8m1: >+ case X86_RCR16m1: >+ case X86_RCR32m1: >+ case X86_RCR64m1: >+ case X86_ROL8m1: >+ case X86_ROL16m1: >+ case X86_ROL32m1: >+ case X86_ROL64m1: >+ case X86_ROR8m1: >+ case X86_ROR16m1: >+ case X86_ROR32m1: >+ case X86_ROR64m1: >+ // shift all the ops right to leave 1st slot for this new register op >+ memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), >+ sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); >+ MI->flat_insn->detail->x86.operands[0].type = X86_OP_IMM; >+ MI->flat_insn->detail->x86.operands[0].imm = 1; >+ MI->flat_insn->detail->x86.operands[0].size = 1; >+ MI->flat_insn->detail->x86.op_count++; >+ } >+ >+ // special instruction needs to supply register op >+ // first op can be embedded in the asm by llvm. >+ // so we have to add the missing register as the first operand >+ reg = X86_insn_reg_att(MCInst_getOpcode(MI)); >+ if (reg) { >+ // shift all the ops right to leave 1st slot for this new register op >+ memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]), >+ sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1)); >+ MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; >+ MI->flat_insn->detail->x86.operands[0].reg = reg; >+ MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; >+ MI->flat_insn->detail->x86.op_count++; >+ } else { >+ if (X86_insn_reg_att2(MCInst_getOpcode(MI), ®, ®2)) { >+ MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG; >+ MI->flat_insn->detail->x86.operands[0].reg = reg; >+ MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg]; >+ MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; >+ MI->flat_insn->detail->x86.operands[1].reg = reg2; >+ MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; >+ MI->flat_insn->detail->x86.op_count = 2; >+ } >+ } >+ } >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86BaseInfo.h b/Source/ThirdParty/capstone/Source/arch/X86/X86BaseInfo.h >new file mode 100644 >index 0000000000000000000000000000000000000000..7708b06a6233d6af668940ce4691131690f0e149 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86BaseInfo.h >@@ -0,0 +1,40 @@ >+//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file contains small standalone helper functions and enum definitions for >+// the X86 target useful for the compiler back-end and the MC libraries. >+// As such, it deliberately does not include references to LLVM core >+// code gen types, passes, etc.. >+// >+//===----------------------------------------------------------------------===// >+ >+#ifndef CS_X86_BASEINFO_H >+#define CS_X86_BASEINFO_H >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+// Enums for memory operand decoding. Each memory operand is represented with >+// a 5 operand sequence in the form: >+// [BaseReg, ScaleAmt, IndexReg, Disp, Segment] >+// These enums help decode this. >+enum { >+ X86_AddrBaseReg = 0, >+ X86_AddrScaleAmt = 1, >+ X86_AddrIndexReg = 2, >+ X86_AddrDisp = 3, >+ >+ /// AddrSegmentReg - The operand # of the segment in the memory operand. >+ X86_AddrSegmentReg = 4, >+ >+ /// AddrNumOperands - Total number of operands in a memory reference. >+ X86_AddrNumOperands = 5 >+}; >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.c b/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.c >new file mode 100644 >index 0000000000000000000000000000000000000000..c99a371983fbb6efbb2dee7a192fa1ea2df8aa8b >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.c >@@ -0,0 +1,864 @@ >+//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// This file is part of the X86 Disassembler. >+// It contains code to translate the data produced by the decoder into >+// MCInsts. >+// Documentation for the disassembler can be found in X86Disassembler.h. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_X86 >+ >+#include <string.h> >+ >+#include "../../cs_priv.h" >+ >+#include "X86Disassembler.h" >+#include "X86DisassemblerDecoderCommon.h" >+#include "X86DisassemblerDecoder.h" >+#include "../../MCInst.h" >+#include "../../utils.h" >+#include "X86Mapping.h" >+ >+#define GET_REGINFO_ENUM >+#define GET_REGINFO_MC_DESC >+#include "X86GenRegisterInfo.inc" >+ >+#define GET_INSTRINFO_ENUM >+#ifdef CAPSTONE_X86_REDUCE >+#include "X86GenInstrInfo_reduce.inc" >+#else >+#include "X86GenInstrInfo.inc" >+#endif >+ >+// Fill-ins to make the compiler happy. These constants are never actually >+// assigned; they are just filler to make an automatically-generated switch >+// statement work. >+enum { >+ X86_BX_SI = 500, >+ X86_BX_DI = 501, >+ X86_BP_SI = 502, >+ X86_BP_DI = 503, >+ X86_sib = 504, >+ X86_sib64 = 505 >+}; >+ >+// >+// Private code that translates from struct InternalInstructions to MCInsts. >+// >+ >+/// translateRegister - Translates an internal register to the appropriate LLVM >+/// register, and appends it as an operand to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param reg - The Reg to append. >+static void translateRegister(MCInst *mcInst, Reg reg) >+{ >+#define ENTRY(x) X86_##x, >+ static const uint8_t llvmRegnums[] = { >+ ALL_REGS >+ 0 >+ }; >+#undef ENTRY >+ >+ uint8_t llvmRegnum = llvmRegnums[reg]; >+ MCOperand_CreateReg0(mcInst, llvmRegnum); >+} >+ >+static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = { >+ 0, // SEG_OVERRIDE_NONE >+ X86_CS, >+ X86_SS, >+ X86_DS, >+ X86_ES, >+ X86_FS, >+ X86_GS >+}; >+ >+/// translateSrcIndex - Appends a source index operand to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param insn - The internal instruction. >+static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn) >+{ >+ unsigned baseRegNo; >+ >+ if (insn->mode == MODE_64BIT) >+ baseRegNo = insn->isPrefix67 ? X86_ESI : X86_RSI; >+ else if (insn->mode == MODE_32BIT) >+ baseRegNo = insn->isPrefix67 ? X86_SI : X86_ESI; >+ else { >+ // assert(insn->mode == MODE_16BIT); >+ baseRegNo = insn->isPrefix67 ? X86_ESI : X86_SI; >+ } >+ >+ MCOperand_CreateReg0(mcInst, baseRegNo); >+ >+ MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); >+ >+ return false; >+} >+ >+/// translateDstIndex - Appends a destination index operand to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param insn - The internal instruction. >+static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn) >+{ >+ unsigned baseRegNo; >+ >+ if (insn->mode == MODE_64BIT) >+ baseRegNo = insn->isPrefix67 ? X86_EDI : X86_RDI; >+ else if (insn->mode == MODE_32BIT) >+ baseRegNo = insn->isPrefix67 ? X86_DI : X86_EDI; >+ else { >+ // assert(insn->mode == MODE_16BIT); >+ baseRegNo = insn->isPrefix67 ? X86_EDI : X86_DI; >+ } >+ >+ MCOperand_CreateReg0(mcInst, baseRegNo); >+ >+ return false; >+} >+ >+/// translateImmediate - Appends an immediate operand to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param immediate - The immediate value to append. >+/// @param operand - The operand, as stored in the descriptor table. >+/// @param insn - The internal instruction. >+static void translateImmediate(MCInst *mcInst, uint64_t immediate, >+ const OperandSpecifier *operand, InternalInstruction *insn) >+{ >+ OperandType type; >+ >+ type = (OperandType)operand->type; >+ if (type == TYPE_RELv) { >+ //isBranch = true; >+ //pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize; >+ switch (insn->displacementSize) { >+ case 1: >+ if (immediate & 0x80) >+ immediate |= ~(0xffull); >+ break; >+ case 2: >+ if (immediate & 0x8000) >+ immediate |= ~(0xffffull); >+ break; >+ case 4: >+ if (immediate & 0x80000000) >+ immediate |= ~(0xffffffffull); >+ break; >+ case 8: >+ break; >+ default: >+ break; >+ } >+ } // By default sign-extend all X86 immediates based on their encoding. >+ else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || >+ type == TYPE_IMM64 || type == TYPE_IMMv) { >+ >+ uint32_t Opcode = MCInst_getOpcode(mcInst); >+ bool check_opcode; >+ >+ switch (operand->encoding) { >+ default: >+ break; >+ case ENCODING_IB: >+ // Special case those X86 instructions that use the imm8 as a set of >+ // bits, bit count, etc. and are not sign-extend. >+ check_opcode = (Opcode != X86_INT); >+#ifndef CAPSTONE_X86_REDUCE >+ check_opcode = ((Opcode != X86_BLENDPSrri && >+ Opcode != X86_BLENDPDrri && >+ Opcode != X86_PBLENDWrri && >+ Opcode != X86_MPSADBWrri && >+ Opcode != X86_DPPSrri && >+ Opcode != X86_DPPDrri && >+ Opcode != X86_INSERTPSrr && >+ Opcode != X86_VBLENDPSYrri && >+ Opcode != X86_VBLENDPSYrmi && >+ Opcode != X86_VBLENDPDYrri && >+ Opcode != X86_VBLENDPDYrmi && >+ Opcode != X86_VPBLENDWrri && >+ Opcode != X86_VMPSADBWrri && >+ Opcode != X86_VDPPSYrri && >+ Opcode != X86_VDPPSYrmi && >+ Opcode != X86_VDPPDrri && >+ Opcode != X86_VINSERTPSrr) && check_opcode); >+#endif >+ if (check_opcode) >+ if(immediate & 0x80) >+ immediate |= ~(0xffull); >+ break; >+ case ENCODING_IW: >+ if(immediate & 0x8000) >+ immediate |= ~(0xffffull); >+ break; >+ case ENCODING_ID: >+ if(immediate & 0x80000000) >+ immediate |= ~(0xffffffffull); >+ break; >+ case ENCODING_IO: >+ break; >+ } >+ } else if (type == TYPE_IMM3) { >+#ifndef CAPSTONE_X86_REDUCE >+ // Check for immediates that printSSECC can't handle. >+ if (immediate >= 8) { >+ unsigned NewOpc = 0; >+ >+ switch (MCInst_getOpcode(mcInst)) { >+ default: break; // never reach >+ case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; >+ case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; >+ case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; >+ case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; >+ case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; >+ case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; >+ case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; >+ case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; >+ } >+ // Switch opcode to the one that doesn't get special printing. >+ if (NewOpc != 0) { >+ MCInst_setOpcode(mcInst, NewOpc); >+ } >+ } >+#endif >+ } else if (type == TYPE_IMM5) { >+#ifndef CAPSTONE_X86_REDUCE >+ // Check for immediates that printAVXCC can't handle. >+ if (immediate >= 32) { >+ unsigned NewOpc = 0; >+ >+ switch (MCInst_getOpcode(mcInst)) { >+ default: break; // unexpected opcode >+ case X86_VCMPPDrmi: NewOpc = X86_VCMPPDrmi_alt; break; >+ case X86_VCMPPDrri: NewOpc = X86_VCMPPDrri_alt; break; >+ case X86_VCMPPSrmi: NewOpc = X86_VCMPPSrmi_alt; break; >+ case X86_VCMPPSrri: NewOpc = X86_VCMPPSrri_alt; break; >+ case X86_VCMPSDrm: NewOpc = X86_VCMPSDrm_alt; break; >+ case X86_VCMPSDrr: NewOpc = X86_VCMPSDrr_alt; break; >+ case X86_VCMPSSrm: NewOpc = X86_VCMPSSrm_alt; break; >+ case X86_VCMPSSrr: NewOpc = X86_VCMPSSrr_alt; break; >+ case X86_VCMPPDYrmi: NewOpc = X86_VCMPPDYrmi_alt; break; >+ case X86_VCMPPDYrri: NewOpc = X86_VCMPPDYrri_alt; break; >+ case X86_VCMPPSYrmi: NewOpc = X86_VCMPPSYrmi_alt; break; >+ case X86_VCMPPSYrri: NewOpc = X86_VCMPPSYrri_alt; break; >+ case X86_VCMPPDZrmi: NewOpc = X86_VCMPPDZrmi_alt; break; >+ case X86_VCMPPDZrri: NewOpc = X86_VCMPPDZrri_alt; break; >+ case X86_VCMPPSZrmi: NewOpc = X86_VCMPPSZrmi_alt; break; >+ case X86_VCMPPSZrri: NewOpc = X86_VCMPPSZrri_alt; break; >+ case X86_VCMPSDZrm: NewOpc = X86_VCMPSDZrmi_alt; break; >+ case X86_VCMPSDZrr: NewOpc = X86_VCMPSDZrri_alt; break; >+ case X86_VCMPSSZrm: NewOpc = X86_VCMPSSZrmi_alt; break; >+ case X86_VCMPSSZrr: NewOpc = X86_VCMPSSZrri_alt; break; >+ } >+ // Switch opcode to the one that doesn't get special printing. >+ if (NewOpc != 0) { >+ MCInst_setOpcode(mcInst, NewOpc); >+ } >+ } >+#endif >+ } >+ >+ switch (type) { >+ case TYPE_XMM32: >+ case TYPE_XMM64: >+ case TYPE_XMM128: >+ MCOperand_CreateReg0(mcInst, X86_XMM0 + ((uint32_t)immediate >> 4)); >+ return; >+ case TYPE_XMM256: >+ MCOperand_CreateReg0(mcInst, X86_YMM0 + ((uint32_t)immediate >> 4)); >+ return; >+ case TYPE_XMM512: >+ MCOperand_CreateReg0(mcInst, X86_ZMM0 + ((uint32_t)immediate >> 4)); >+ return; >+ case TYPE_REL8: >+ if(immediate & 0x80) >+ immediate |= ~(0xffull); >+ break; >+ case TYPE_REL32: >+ case TYPE_REL64: >+ if(immediate & 0x80000000) >+ immediate |= ~(0xffffffffull); >+ break; >+ default: >+ // operand is 64 bits wide. Do nothing. >+ break; >+ } >+ >+ MCOperand_CreateImm0(mcInst, immediate); >+ >+ if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || >+ type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { >+ MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); >+ } >+} >+ >+/// translateRMRegister - Translates a register stored in the R/M field of the >+/// ModR/M byte to its LLVM equivalent and appends it to an MCInst. >+/// @param mcInst - The MCInst to append to. >+/// @param insn - The internal instruction to extract the R/M field >+/// from. >+/// @return - 0 on success; -1 otherwise >+static bool translateRMRegister(MCInst *mcInst, InternalInstruction *insn) >+{ >+ if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { >+ //debug("A R/M register operand may not have a SIB byte"); >+ return true; >+ } >+ >+ switch (insn->eaBase) { >+ case EA_BASE_NONE: >+ //debug("EA_BASE_NONE for ModR/M base"); >+ return true; >+#define ENTRY(x) case EA_BASE_##x: >+ ALL_EA_BASES >+#undef ENTRY >+ //debug("A R/M register operand may not have a base; " >+ // "the operand must be a register."); >+ return true; >+#define ENTRY(x) \ >+ case EA_REG_##x: \ >+ MCOperand_CreateReg0(mcInst, X86_##x); break; >+ ALL_REGS >+#undef ENTRY >+ default: >+ //debug("Unexpected EA base register"); >+ return true; >+ } >+ >+ return false; >+} >+ >+/// translateRMMemory - Translates a memory operand stored in the Mod and R/M >+/// fields of an internal instruction (and possibly its SIB byte) to a memory >+/// operand in LLVM's format, and appends it to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param insn - The instruction to extract Mod, R/M, and SIB fields >+/// from. >+/// @return - 0 on success; nonzero otherwise >+static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn) >+{ >+ // Addresses in an MCInst are represented as five operands: >+ // 1. basereg (register) The R/M base, or (if there is a SIB) the >+ // SIB base >+ // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified >+ // scale amount >+ // 3. indexreg (register) x86_registerNONE, or (if there is a SIB) >+ // the index (which is multiplied by the >+ // scale amount) >+ // 4. displacement (immediate) 0, or the displacement if there is one >+ // 5. segmentreg (register) x86_registerNONE for now, but could be set >+ // if we have segment overrides >+ >+ bool IndexIs512, IndexIs128, IndexIs256; >+ int scaleAmount, indexReg; >+#ifndef CAPSTONE_X86_REDUCE >+ uint32_t Opcode; >+#endif >+ >+ if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) { >+ if (insn->sibBase != SIB_BASE_NONE) { >+ switch (insn->sibBase) { >+#define ENTRY(x) \ >+ case SIB_BASE_##x: \ >+ MCOperand_CreateReg0(mcInst, X86_##x); break; >+ ALL_SIB_BASES >+#undef ENTRY >+ default: >+ //debug("Unexpected sibBase"); >+ return true; >+ } >+ } else { >+ MCOperand_CreateReg0(mcInst, 0); >+ } >+ >+ // Check whether we are handling VSIB addressing mode for GATHER. >+ // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and >+ // we should use SIB_INDEX_XMM4|YMM4 for VSIB. >+ // I don't see a way to get the correct IndexReg in readSIB: >+ // We can tell whether it is VSIB or SIB after instruction ID is decoded, >+ // but instruction ID may not be decoded yet when calling readSIB. >+#ifndef CAPSTONE_X86_REDUCE >+ Opcode = MCInst_getOpcode(mcInst); >+#endif >+ IndexIs128 = ( >+#ifndef CAPSTONE_X86_REDUCE >+ Opcode == X86_VGATHERDPDrm || >+ Opcode == X86_VGATHERDPDYrm || >+ Opcode == X86_VGATHERQPDrm || >+ Opcode == X86_VGATHERDPSrm || >+ Opcode == X86_VGATHERQPSrm || >+ Opcode == X86_VPGATHERDQrm || >+ Opcode == X86_VPGATHERDQYrm || >+ Opcode == X86_VPGATHERQQrm || >+ Opcode == X86_VPGATHERDDrm || >+ Opcode == X86_VPGATHERQDrm || >+#endif >+ false >+ ); >+ IndexIs256 = ( >+#ifndef CAPSTONE_X86_REDUCE >+ Opcode == X86_VGATHERQPDYrm || >+ Opcode == X86_VGATHERDPSYrm || >+ Opcode == X86_VGATHERQPSYrm || >+ Opcode == X86_VGATHERDPDZrm || >+ Opcode == X86_VPGATHERDQZrm || >+ Opcode == X86_VPGATHERQQYrm || >+ Opcode == X86_VPGATHERDDYrm || >+ Opcode == X86_VPGATHERQDYrm || >+#endif >+ false >+ ); >+ IndexIs512 = ( >+#ifndef CAPSTONE_X86_REDUCE >+ Opcode == X86_VGATHERQPDZrm || >+ Opcode == X86_VGATHERDPSZrm || >+ Opcode == X86_VGATHERQPSZrm || >+ Opcode == X86_VPGATHERQQZrm || >+ Opcode == X86_VPGATHERDDZrm || >+ Opcode == X86_VPGATHERQDZrm || >+#endif >+ false >+ ); >+ >+ if (IndexIs128 || IndexIs256 || IndexIs512) { >+ unsigned IndexOffset = insn->sibIndex - >+ (insn->addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); >+ SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 : >+ IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0; >+ >+ insn->sibIndex = (SIBIndex)(IndexBase + (insn->sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset)); >+ } >+ >+ if (insn->sibIndex != SIB_INDEX_NONE) { >+ switch (insn->sibIndex) { >+ default: >+ //debug("Unexpected sibIndex"); >+ return true; >+#define ENTRY(x) \ >+ case SIB_INDEX_##x: \ >+ indexReg = X86_##x; break; >+ EA_BASES_32BIT >+ EA_BASES_64BIT >+ REGS_XMM >+ REGS_YMM >+ REGS_ZMM >+#undef ENTRY >+ } >+ } else { >+ indexReg = 0; >+ } >+ >+ scaleAmount = insn->sibScale; >+ } else { >+ switch (insn->eaBase) { >+ case EA_BASE_NONE: >+ if (insn->eaDisplacement == EA_DISP_NONE) { >+ //debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base"); >+ return true; >+ } >+ if (insn->mode == MODE_64BIT) { >+ if (insn->prefix3 == 0x67) // address-size prefix overrides RIP relative addressing >+ MCOperand_CreateReg0(mcInst, X86_EIP); >+ else >+ MCOperand_CreateReg0(mcInst, X86_RIP); // Section 2.2.1.6 >+ } else { >+ MCOperand_CreateReg0(mcInst, 0); >+ } >+ >+ indexReg = 0; >+ break; >+ case EA_BASE_BX_SI: >+ MCOperand_CreateReg0(mcInst, X86_BX); >+ indexReg = X86_SI; >+ break; >+ case EA_BASE_BX_DI: >+ MCOperand_CreateReg0(mcInst, X86_BX); >+ indexReg = X86_DI; >+ break; >+ case EA_BASE_BP_SI: >+ MCOperand_CreateReg0(mcInst, X86_BP); >+ indexReg = X86_SI; >+ break; >+ case EA_BASE_BP_DI: >+ MCOperand_CreateReg0(mcInst, X86_BP); >+ indexReg = X86_DI; >+ break; >+ default: >+ indexReg = 0; >+ switch (insn->eaBase) { >+ default: >+ //debug("Unexpected eaBase"); >+ return true; >+ // Here, we will use the fill-ins defined above. However, >+ // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and >+ // sib and sib64 were handled in the top-level if, so they're only >+ // placeholders to keep the compiler happy. >+#define ENTRY(x) \ >+ case EA_BASE_##x: \ >+ MCOperand_CreateReg0(mcInst, X86_##x); break; >+ ALL_EA_BASES >+#undef ENTRY >+#define ENTRY(x) case EA_REG_##x: >+ ALL_REGS >+#undef ENTRY >+ //debug("A R/M memory operand may not be a register; " >+ // "the base field must be a base."); >+ return true; >+ } >+ } >+ >+ scaleAmount = 1; >+ } >+ >+ MCOperand_CreateImm0(mcInst, scaleAmount); >+ MCOperand_CreateReg0(mcInst, indexReg); >+ MCOperand_CreateImm0(mcInst, insn->displacement); >+ >+ MCOperand_CreateReg0(mcInst, segmentRegnums[insn->segmentOverride]); >+ >+ return false; >+} >+ >+/// translateRM - Translates an operand stored in the R/M (and possibly SIB) >+/// byte of an instruction to LLVM form, and appends it to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param operand - The operand, as stored in the descriptor table. >+/// @param insn - The instruction to extract Mod, R/M, and SIB fields >+/// from. >+/// @return - 0 on success; nonzero otherwise >+static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand, >+ InternalInstruction *insn) >+{ >+ switch (operand->type) { >+ case TYPE_R8: >+ case TYPE_R16: >+ case TYPE_R32: >+ case TYPE_R64: >+ case TYPE_Rv: >+ case TYPE_MM: >+ case TYPE_MM32: >+ case TYPE_MM64: >+ case TYPE_XMM: >+ case TYPE_XMM32: >+ case TYPE_XMM64: >+ case TYPE_XMM128: >+ case TYPE_XMM256: >+ case TYPE_XMM512: >+ case TYPE_VK1: >+ case TYPE_VK8: >+ case TYPE_VK16: >+ case TYPE_DEBUGREG: >+ case TYPE_CONTROLREG: >+ return translateRMRegister(mcInst, insn); >+ case TYPE_M: >+ case TYPE_M8: >+ case TYPE_M16: >+ case TYPE_M32: >+ case TYPE_M64: >+ case TYPE_M128: >+ case TYPE_M256: >+ case TYPE_M512: >+ case TYPE_Mv: >+ case TYPE_M32FP: >+ case TYPE_M64FP: >+ case TYPE_M80FP: >+ case TYPE_M16INT: >+ case TYPE_M32INT: >+ case TYPE_M64INT: >+ case TYPE_M1616: >+ case TYPE_M1632: >+ case TYPE_M1664: >+ case TYPE_LEA: >+ return translateRMMemory(mcInst, insn); >+ default: >+ //debug("Unexpected type for a R/M operand"); >+ return true; >+ } >+} >+ >+/// translateFPRegister - Translates a stack position on the FPU stack to its >+/// LLVM form, and appends it to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param stackPos - The stack position to translate. >+static void translateFPRegister(MCInst *mcInst, uint8_t stackPos) >+{ >+ MCOperand_CreateReg0(mcInst, X86_ST0 + stackPos); >+} >+ >+/// translateMaskRegister - Translates a 3-bit mask register number to >+/// LLVM form, and appends it to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param maskRegNum - Number of mask register from 0 to 7. >+/// @return - false on success; true otherwise. >+static bool translateMaskRegister(MCInst *mcInst, uint8_t maskRegNum) >+{ >+ if (maskRegNum >= 8) { >+ // debug("Invalid mask register number"); >+ return true; >+ } >+ >+ MCOperand_CreateReg0(mcInst, X86_K0 + maskRegNum); >+ >+ return false; >+} >+ >+/// translateOperand - Translates an operand stored in an internal instruction >+/// to LLVM's format and appends it to an MCInst. >+/// >+/// @param mcInst - The MCInst to append to. >+/// @param operand - The operand, as stored in the descriptor table. >+/// @param insn - The internal instruction. >+/// @return - false on success; true otherwise. >+static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, InternalInstruction *insn) >+{ >+ switch (operand->encoding) { >+ case ENCODING_REG: >+ translateRegister(mcInst, insn->reg); >+ return false; >+ case ENCODING_WRITEMASK: >+ return translateMaskRegister(mcInst, insn->writemask); >+ CASE_ENCODING_RM: >+ return translateRM(mcInst, operand, insn); >+ case ENCODING_CB: >+ case ENCODING_CW: >+ case ENCODING_CD: >+ case ENCODING_CP: >+ case ENCODING_CO: >+ case ENCODING_CT: >+ //debug("Translation of code offsets isn't supported."); >+ return true; >+ case ENCODING_IB: >+ case ENCODING_IW: >+ case ENCODING_ID: >+ case ENCODING_IO: >+ case ENCODING_Iv: >+ case ENCODING_Ia: >+ translateImmediate(mcInst, insn->immediates[insn->numImmediatesTranslated++], operand, insn); >+ return false; >+ case ENCODING_SI: >+ return translateSrcIndex(mcInst, insn); >+ case ENCODING_DI: >+ return translateDstIndex(mcInst, insn); >+ case ENCODING_RB: >+ case ENCODING_RW: >+ case ENCODING_RD: >+ case ENCODING_RO: >+ case ENCODING_Rv: >+ translateRegister(mcInst, insn->opcodeRegister); >+ return false; >+ case ENCODING_FP: >+ translateFPRegister(mcInst, insn->modRM & 7); >+ return false; >+ case ENCODING_VVVV: >+ translateRegister(mcInst, insn->vvvv); >+ return false; >+ case ENCODING_DUP: >+ return translateOperand(mcInst, &insn->operands[operand->type - TYPE_DUP0], insn); >+ default: >+ //debug("Unhandled operand encoding during translation"); >+ return true; >+ } >+} >+ >+static bool translateInstruction(MCInst *mcInst, InternalInstruction *insn) >+{ >+ int index; >+ >+ if (!insn->spec) { >+ //debug("Instruction has no specification"); >+ return true; >+ } >+ >+ MCInst_setOpcode(mcInst, insn->instructionID); >+ >+ // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3 >+ // prefix bytes should be disassembled as xrelease and xacquire then set the >+ // opcode to those instead of the rep and repne opcodes. >+#ifndef CAPSTONE_X86_REDUCE >+ if (insn->xAcquireRelease) { >+ if (MCInst_getOpcode(mcInst) == X86_REP_PREFIX) >+ MCInst_setOpcode(mcInst, X86_XRELEASE_PREFIX); >+ else if (MCInst_getOpcode(mcInst) == X86_REPNE_PREFIX) >+ MCInst_setOpcode(mcInst, X86_XACQUIRE_PREFIX); >+ } >+#endif >+ >+ insn->numImmediatesTranslated = 0; >+ >+ for (index = 0; index < X86_MAX_OPERANDS; ++index) { >+ if (insn->operands[index].encoding != ENCODING_NONE) { >+ if (translateOperand(mcInst, &insn->operands[index], insn)) { >+ return true; >+ } >+ } >+ } >+ >+ return false; >+} >+ >+static int reader(const struct reader_info *info, uint8_t *byte, uint64_t address) >+{ >+ if (address - info->offset >= info->size) >+ // out of buffer range >+ return -1; >+ >+ *byte = info->code[address - info->offset]; >+ >+ return 0; >+} >+ >+// copy x86 detail information from internal structure to public structure >+static void update_pub_insn(cs_insn *pub, InternalInstruction *inter, uint8_t *prefixes) >+{ >+ prefixes[0] = inter->prefix0; >+ prefixes[1] = inter->prefix1; >+ prefixes[2] = inter->prefix2; >+ prefixes[3] = inter->prefix3; >+ >+ if (inter->vectorExtensionType != 0) >+ memcpy(pub->detail->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->detail->x86.opcode)); >+ else { >+ if (inter->twoByteEscape) { >+ if (inter->threeByteEscape) { >+ pub->detail->x86.opcode[0] = inter->twoByteEscape; >+ pub->detail->x86.opcode[1] = inter->threeByteEscape; >+ pub->detail->x86.opcode[2] = inter->opcode; >+ } else { >+ pub->detail->x86.opcode[0] = inter->twoByteEscape; >+ pub->detail->x86.opcode[1] = inter->opcode; >+ } >+ } else { >+ pub->detail->x86.opcode[0] = inter->opcode; >+ } >+ } >+ >+ pub->detail->x86.rex = inter->rexPrefix; >+ >+ pub->detail->x86.addr_size = inter->addressSize; >+ >+ pub->detail->x86.modrm = inter->orgModRM; >+ pub->detail->x86.sib = inter->sib; >+ pub->detail->x86.disp = inter->displacement; >+ >+ pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex); >+ pub->detail->x86.sib_scale = inter->sibScale; >+ pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase); >+} >+ >+void X86_init(MCRegisterInfo *MRI) >+{ >+ /* >+ InitMCRegisterInfo(X86RegDesc, 234, >+ RA, PC, >+ X86MCRegisterClasses, 79, >+ X86RegUnitRoots, 119, X86RegDiffLists, X86RegStrings, >+ X86SubRegIdxLists, 7, >+ X86SubRegIdxRanges, X86RegEncodingTable); >+ */ >+ >+ MCRegisterInfo_InitMCRegisterInfo(MRI, X86RegDesc, 234, >+ 0, 0, >+ X86MCRegisterClasses, 79, >+ 0, 0, X86RegDiffLists, 0, >+ X86SubRegIdxLists, 7, >+ 0); >+} >+ >+// Public interface for the disassembler >+bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *_info) >+{ >+ cs_struct *handle = (cs_struct *)(uintptr_t)ud; >+ InternalInstruction insn; >+ struct reader_info info; >+ int ret; >+ bool result; >+ >+ info.code = code; >+ info.size = code_len; >+ info.offset = address; >+ >+ memset(&insn, 0, offsetof(InternalInstruction, reader)); >+ >+ if (instr->flat_insn->detail) { >+ instr->flat_insn->detail->x86.op_count = 0; >+ instr->flat_insn->detail->x86.sse_cc = X86_SSE_CC_INVALID; >+ instr->flat_insn->detail->x86.avx_cc = X86_AVX_CC_INVALID; >+ instr->flat_insn->detail->x86.avx_sae = false; >+ instr->flat_insn->detail->x86.avx_rm = X86_AVX_RM_INVALID; >+ >+ memset(instr->flat_insn->detail->x86.prefix, 0, sizeof(instr->flat_insn->detail->x86.prefix)); >+ memset(instr->flat_insn->detail->x86.opcode, 0, sizeof(instr->flat_insn->detail->x86.opcode)); >+ memset(instr->flat_insn->detail->x86.operands, 0, sizeof(instr->flat_insn->detail->x86.operands)); >+ } >+ >+ if (handle->mode & CS_MODE_16) >+ ret = decodeInstruction(&insn, >+ reader, &info, >+ address, >+ MODE_16BIT); >+ else if (handle->mode & CS_MODE_32) >+ ret = decodeInstruction(&insn, >+ reader, &info, >+ address, >+ MODE_32BIT); >+ else >+ ret = decodeInstruction(&insn, >+ reader, &info, >+ address, >+ MODE_64BIT); >+ >+ if (ret) { >+ *size = (uint16_t)(insn.readerCursor - address); >+ >+ return false; >+ } else { >+ *size = (uint16_t)insn.length; >+ >+ result = (!translateInstruction(instr, &insn)) ? true : false; >+ if (result) { >+ // quick fix for #904. TODO: fix this properly in the next update >+ if (handle->mode & CS_MODE_64) { >+ if (instr->Opcode == X86_LES16rm || instr->Opcode == X86_LES32rm) >+ // LES is invalid in x64 >+ return false; >+ if (instr->Opcode == X86_LDS16rm || instr->Opcode == X86_LDS32rm) >+ // LDS is invalid in x64 >+ return false; >+ } >+ >+ instr->imm_size = insn.immSize; >+ if (handle->detail) { >+ update_pub_insn(instr->flat_insn, &insn, instr->x86_prefix); >+ } else { >+ // still copy all prefixes >+ instr->x86_prefix[0] = insn.prefix0; >+ instr->x86_prefix[1] = insn.prefix1; >+ instr->x86_prefix[2] = insn.prefix2; >+ instr->x86_prefix[3] = insn.prefix3; >+ } >+ } >+ >+ return result; >+ } >+} >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.h b/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.h >new file mode 100644 >index 0000000000000000000000000000000000000000..eb2dbe591f3431eba26da897dadffe37abce6ee7 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86Disassembler.h >@@ -0,0 +1,96 @@ >+//===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===// >+// >+// The LLVM Compiler Infrastructure >+// >+// This file is distributed under the University of Illinois Open Source >+// License. See LICENSE.TXT for details. >+// >+//===----------------------------------------------------------------------===// >+// >+// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and >+// 64-bit X86 instruction sets. The main decode sequence for an assembly >+// instruction in this disassembler is: >+// >+// 1. Read the prefix bytes and determine the attributes of the instruction. >+// These attributes, recorded in enum attributeBits >+// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM >+// provides a mapping from bitmasks to contexts, which are represented by >+// enum InstructionContext (ibid.). >+// >+// 2. Read the opcode, and determine what kind of opcode it is. The >+// disassembler distinguishes four kinds of opcodes, which are enumerated in >+// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte >+// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a >+// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. >+// >+// 3. Depending on the opcode type, look in one of four ClassDecision structures >+// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which >+// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get >+// a ModRMDecision (ibid.). >+// >+// 4. Some instructions, such as escape opcodes or extended opcodes, or even >+// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the >+// ModR/M byte to complete decode. The ModRMDecision's type is an entry from >+// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the >+// ModR/M byte is required and how to interpret it. >+// >+// 5. After resolving the ModRMDecision, the disassembler has a unique ID >+// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in >+// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and >+// meanings of its operands. >+// >+// 6. For each operand, its encoding is an entry from OperandEncoding >+// (X86DisassemblerDecoderCommon.h) and its type is an entry from >+// OperandType (ibid.). The encoding indicates how to read it from the >+// instruction; the type indicates how to interpret the value once it has >+// been read. For example, a register operand could be stored in the R/M >+// field of the ModR/M byte, the REG field of the ModR/M byte, or added to >+// the main opcode. This is orthogonal from its meaning (an GPR or an XMM >+// register, for instance). Given this information, the operands can be >+// extracted and interpreted. >+// >+// 7. As the last step, the disassembler translates the instruction information >+// and operands into a format understandable by the client - in this case, an >+// MCInst for use by the MC infrastructure. >+// >+// The disassembler is broken broadly into two parts: the table emitter that >+// emits the instruction decode tables discussed above during compilation, and >+// the disassembler itself. The table emitter is documented in more detail in >+// utils/TableGen/X86DisassemblerEmitter.h. >+// >+// X86Disassembler.h contains the public interface for the disassembler, >+// adhering to the MCDisassembler interface. >+// X86Disassembler.cpp contains the code responsible for step 7, and for >+// invoking the decoder to execute steps 1-6. >+// X86DisassemblerDecoderCommon.h contains the definitions needed by both the >+// table emitter and the disassembler. >+// X86DisassemblerDecoder.h contains the public interface of the decoder, >+// factored out into C for possible use by other projects. >+// X86DisassemblerDecoder.c contains the source code of the decoder, which is >+// responsible for steps 1-6. >+// >+//===----------------------------------------------------------------------===// >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_X86_DISASSEMBLER_H >+#define CS_X86_DISASSEMBLER_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+#include "../../include/capstone.h" >+ >+#include "../../MCInst.h" >+ >+#include "../../MCRegisterInfo.h" >+#include "X86DisassemblerDecoderCommon.h" >+ >+bool X86_getInstruction(csh handle, const uint8_t *code, size_t code_len, >+ MCInst *instr, uint16_t *size, uint64_t address, void *info); >+ >+void X86_init(MCRegisterInfo *MRI); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.c b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.c >new file mode 100644 >index 0000000000000000000000000000000000000000..5c60aac1fe3d9c5f2ee5baa0f84c9e256a1d89d9 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.c >@@ -0,0 +1,2406 @@ >+/*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===* >+ * >+ * The LLVM Compiler Infrastructure >+ * >+ * This file is distributed under the University of Illinois Open Source >+ * License. See LICENSE.TXT for details. >+ * >+ *===----------------------------------------------------------------------===* >+ * >+ * This file is part of the X86 Disassembler. >+ * It contains the implementation of the instruction decoder. >+ * Documentation for the disassembler can be found in X86Disassembler.h. >+ * >+ *===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifdef CAPSTONE_HAS_X86 >+ >+#include <stdarg.h> /* for va_*() */ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdlib.h> /* for exit() */ >+#endif >+ >+#include "../../cs_priv.h" >+#include "../../utils.h" >+ >+#include "X86DisassemblerDecoder.h" >+ >+/// Specifies whether a ModR/M byte is needed and (if so) which >+/// instruction each possible value of the ModR/M byte corresponds to. Once >+/// this information is known, we have narrowed down to a single instruction. >+struct ModRMDecision { >+ uint8_t modrm_type; >+ uint16_t instructionIDs; >+}; >+ >+/// Specifies which set of ModR/M->instruction tables to look at >+/// given a particular opcode. >+struct OpcodeDecision { >+ struct ModRMDecision modRMDecisions[256]; >+}; >+ >+/// Specifies which opcode->instruction tables to look at given >+/// a particular context (set of attributes). Since there are many possible >+/// contexts, the decoder first uses CONTEXTS_SYM to determine which context >+/// applies given a specific set of attributes. Hence there are only IC_max >+/// entries in this table, rather than 2^(ATTR_max). >+struct ContextDecision { >+ struct OpcodeDecision opcodeDecisions[IC_max]; >+}; >+ >+#ifdef CAPSTONE_X86_REDUCE >+#include "X86GenDisassemblerTables_reduce.inc" >+#else >+#include "X86GenDisassemblerTables.inc" >+#endif >+ >+//#define GET_INSTRINFO_ENUM >+#define GET_INSTRINFO_MC_DESC >+#ifdef CAPSTONE_X86_REDUCE >+#include "X86GenInstrInfo_reduce.inc" >+#else >+#include "X86GenInstrInfo.inc" >+#endif >+ >+/* >+ * contextForAttrs - Client for the instruction context table. Takes a set of >+ * attributes and returns the appropriate decode context. >+ * >+ * @param attrMask - Attributes, from the enumeration attributeBits. >+ * @return - The InstructionContext to use when looking up an >+ * an instruction with these attributes. >+ */ >+static InstructionContext contextForAttrs(uint16_t attrMask) >+{ >+ return CONTEXTS_SYM[attrMask]; >+} >+ >+/* >+ * modRMRequired - Reads the appropriate instruction table to determine whether >+ * the ModR/M byte is required to decode a particular instruction. >+ * >+ * @param type - The opcode type (i.e., how many bytes it has). >+ * @param insnContext - The context for the instruction, as returned by >+ * contextForAttrs. >+ * @param opcode - The last byte of the instruction's opcode, not counting >+ * ModR/M extensions and escapes. >+ * @return - true if the ModR/M byte is required, false otherwise. >+ */ >+static int modRMRequired(OpcodeType type, >+ InstructionContext insnContext, >+ uint16_t opcode) >+{ >+ const struct OpcodeDecision *decision = NULL; >+ const uint8_t *indextable = NULL; >+ uint8_t index; >+ >+ switch (type) { >+ default: >+ case ONEBYTE: >+ decision = ONEBYTE_SYM; >+ indextable = index_x86DisassemblerOneByteOpcodes; >+ break; >+ case TWOBYTE: >+ decision = TWOBYTE_SYM; >+ indextable = index_x86DisassemblerTwoByteOpcodes; >+ break; >+ case THREEBYTE_38: >+ decision = THREEBYTE38_SYM; >+ indextable = index_x86DisassemblerThreeByte38Opcodes; >+ break; >+ case THREEBYTE_3A: >+ decision = THREEBYTE3A_SYM; >+ indextable = index_x86DisassemblerThreeByte3AOpcodes; >+ break; >+#ifndef CAPSTONE_X86_REDUCE >+ case XOP8_MAP: >+ decision = XOP8_MAP_SYM; >+ indextable = index_x86DisassemblerXOP8Opcodes; >+ break; >+ case XOP9_MAP: >+ decision = XOP9_MAP_SYM; >+ indextable = index_x86DisassemblerXOP9Opcodes; >+ break; >+ case XOPA_MAP: >+ decision = XOPA_MAP_SYM; >+ indextable = index_x86DisassemblerXOPAOpcodes; >+ break; >+ case T3DNOW_MAP: >+ // 3DNow instructions always have ModRM byte >+ return true; >+#endif >+ } >+ >+ index = indextable[insnContext]; >+ if (index) >+ return decision[index - 1].modRMDecisions[opcode].modrm_type != MODRM_ONEENTRY; >+ else >+ return false; >+} >+ >+/* >+ * decode - Reads the appropriate instruction table to obtain the unique ID of >+ * an instruction. >+ * >+ * @param type - See modRMRequired(). >+ * @param insnContext - See modRMRequired(). >+ * @param opcode - See modRMRequired(). >+ * @param modRM - The ModR/M byte if required, or any value if not. >+ * @return - The UID of the instruction, or 0 on failure. >+ */ >+static InstrUID decode(OpcodeType type, >+ InstructionContext insnContext, >+ uint8_t opcode, >+ uint8_t modRM) >+{ >+ const struct ModRMDecision *dec = NULL; >+ const uint8_t *indextable = NULL; >+ uint8_t index; >+ >+ switch (type) { >+ default: >+ case ONEBYTE: >+ indextable = index_x86DisassemblerOneByteOpcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &ONEBYTE_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case TWOBYTE: >+ indextable = index_x86DisassemblerTwoByteOpcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &TWOBYTE_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case THREEBYTE_38: >+ indextable = index_x86DisassemblerThreeByte38Opcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &THREEBYTE38_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case THREEBYTE_3A: >+ indextable = index_x86DisassemblerThreeByte3AOpcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &THREEBYTE3A_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+#ifndef CAPSTONE_X86_REDUCE >+ case XOP8_MAP: >+ indextable = index_x86DisassemblerXOP8Opcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &XOP8_MAP_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case XOP9_MAP: >+ indextable = index_x86DisassemblerXOP9Opcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &XOP9_MAP_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case XOPA_MAP: >+ indextable = index_x86DisassemblerXOPAOpcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &XOPA_MAP_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+ case T3DNOW_MAP: >+ indextable = index_x86DisassemblerT3DNOWOpcodes; >+ index = indextable[insnContext]; >+ if (index) >+ dec = &T3DNOW_MAP_SYM[index - 1].modRMDecisions[opcode]; >+ else >+ dec = &emptyTable.modRMDecisions[opcode]; >+ break; >+#endif >+ } >+ >+ switch (dec->modrm_type) { >+ default: >+ //debug("Corrupt table! Unknown modrm_type"); >+ return 0; >+ case MODRM_ONEENTRY: >+ return modRMTable[dec->instructionIDs]; >+ case MODRM_SPLITRM: >+ if (modFromModRM(modRM) == 0x3) >+ return modRMTable[dec->instructionIDs+1]; >+ return modRMTable[dec->instructionIDs]; >+ case MODRM_SPLITREG: >+ if (modFromModRM(modRM) == 0x3) >+ return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)+8]; >+ return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; >+ case MODRM_SPLITMISC: >+ if (modFromModRM(modRM) == 0x3) >+ return modRMTable[dec->instructionIDs+(modRM & 0x3f)+8]; >+ return modRMTable[dec->instructionIDs+((modRM & 0x38) >> 3)]; >+ case MODRM_FULL: >+ return modRMTable[dec->instructionIDs+modRM]; >+ } >+} >+ >+/* >+ * specifierForUID - Given a UID, returns the name and operand specification for >+ * that instruction. >+ * >+ * @param uid - The unique ID for the instruction. This should be returned by >+ * decode(); specifierForUID will not check bounds. >+ * @return - A pointer to the specification for that instruction. >+ */ >+static const struct InstructionSpecifier *specifierForUID(InstrUID uid) >+{ >+ return &INSTRUCTIONS_SYM[uid]; >+} >+ >+/* >+ * consumeByte - Uses the reader function provided by the user to consume one >+ * byte from the instruction's memory and advance the cursor. >+ * >+ * @param insn - The instruction with the reader function to use. The cursor >+ * for this instruction is advanced. >+ * @param byte - A pointer to a pre-allocated memory buffer to be populated >+ * with the data read. >+ * @return - 0 if the read was successful; nonzero otherwise. >+ */ >+static int consumeByte(struct InternalInstruction *insn, uint8_t *byte) >+{ >+ int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); >+ >+ if (!ret) >+ ++(insn->readerCursor); >+ >+ return ret; >+} >+ >+/* >+ * lookAtByte - Like consumeByte, but does not advance the cursor. >+ * >+ * @param insn - See consumeByte(). >+ * @param byte - See consumeByte(). >+ * @return - See consumeByte(). >+ */ >+static int lookAtByte(struct InternalInstruction *insn, uint8_t *byte) >+{ >+ return insn->reader(insn->readerArg, byte, insn->readerCursor); >+} >+ >+static void unconsumeByte(struct InternalInstruction *insn) >+{ >+ insn->readerCursor--; >+} >+ >+#define CONSUME_FUNC(name, type) \ >+ static int name(struct InternalInstruction *insn, type *ptr) { \ >+ type combined = 0; \ >+ unsigned offset; \ >+ for (offset = 0; offset < sizeof(type); ++offset) { \ >+ uint8_t byte; \ >+ int ret = insn->reader(insn->readerArg, \ >+ &byte, \ >+ insn->readerCursor + offset); \ >+ if (ret) \ >+ return ret; \ >+ combined = combined | (type)((uint64_t)byte << (offset * 8)); \ >+ } \ >+ *ptr = combined; \ >+ insn->readerCursor += sizeof(type); \ >+ return 0; \ >+ } >+ >+/* >+ * consume* - Use the reader function provided by the user to consume data >+ * values of various sizes from the instruction's memory and advance the >+ * cursor appropriately. These readers perform endian conversion. >+ * >+ * @param insn - See consumeByte(). >+ * @param ptr - A pointer to a pre-allocated memory of appropriate size to >+ * be populated with the data read. >+ * @return - See consumeByte(). >+ */ >+CONSUME_FUNC(consumeInt8, int8_t) >+CONSUME_FUNC(consumeInt16, int16_t) >+CONSUME_FUNC(consumeInt32, int32_t) >+CONSUME_FUNC(consumeUInt16, uint16_t) >+CONSUME_FUNC(consumeUInt32, uint32_t) >+CONSUME_FUNC(consumeUInt64, uint64_t) >+ >+/* >+ * setPrefixPresent - Marks that a particular prefix is present at a particular >+ * location. >+ * >+ * @param insn - The instruction to be marked as having the prefix. >+ * @param prefix - The prefix that is present. >+ * @param location - The location where the prefix is located (in the address >+ * space of the instruction's reader). >+ */ >+static void setPrefixPresent(struct InternalInstruction *insn, >+ uint8_t prefix, uint64_t location) >+{ >+ switch (prefix) { >+ case 0x26: >+ insn->isPrefix26 = true; >+ insn->prefix26 = location; >+ break; >+ case 0x2e: >+ insn->isPrefix2e = true; >+ insn->prefix2e = location; >+ break; >+ case 0x36: >+ insn->isPrefix36 = true; >+ insn->prefix36 = location; >+ break; >+ case 0x3e: >+ insn->isPrefix3e = true; >+ insn->prefix3e = location; >+ break; >+ case 0x64: >+ insn->isPrefix64 = true; >+ insn->prefix64 = location; >+ break; >+ case 0x65: >+ insn->isPrefix65 = true; >+ insn->prefix65 = location; >+ break; >+ case 0x66: >+ insn->isPrefix66 = true; >+ insn->prefix66 = location; >+ break; >+ case 0x67: >+ insn->isPrefix67 = true; >+ insn->prefix67 = location; >+ break; >+ case 0xf0: >+ insn->isPrefixf0 = true; >+ insn->prefixf0 = location; >+ break; >+ case 0xf2: >+ insn->isPrefixf2 = true; >+ insn->prefixf2 = location; >+ break; >+ case 0xf3: >+ insn->isPrefixf3 = true; >+ insn->prefixf3 = location; >+ break; >+ default: >+ break; >+ } >+} >+ >+/* >+ * isPrefixAtLocation - Queries an instruction to determine whether a prefix is >+ * present at a given location. >+ * >+ * @param insn - The instruction to be queried. >+ * @param prefix - The prefix. >+ * @param location - The location to query. >+ * @return - Whether the prefix is at that location. >+ */ >+static bool isPrefixAtLocation(struct InternalInstruction *insn, uint8_t prefix, >+ uint64_t location) >+{ >+ switch (prefix) { >+ case 0x26: >+ if (insn->isPrefix26 && insn->prefix26 == location) >+ return true; >+ break; >+ case 0x2e: >+ if (insn->isPrefix2e && insn->prefix2e == location) >+ return true; >+ break; >+ case 0x36: >+ if (insn->isPrefix36 && insn->prefix36 == location) >+ return true; >+ break; >+ case 0x3e: >+ if (insn->isPrefix3e && insn->prefix3e == location) >+ return true; >+ break; >+ case 0x64: >+ if (insn->isPrefix64 && insn->prefix64 == location) >+ return true; >+ break; >+ case 0x65: >+ if (insn->isPrefix65 && insn->prefix65 == location) >+ return true; >+ break; >+ case 0x66: >+ if (insn->isPrefix66 && insn->prefix66 == location) >+ return true; >+ break; >+ case 0x67: >+ if (insn->isPrefix67 && insn->prefix67 == location) >+ return true; >+ break; >+ case 0xf0: >+ if (insn->isPrefixf0 && insn->prefixf0 == location) >+ return true; >+ break; >+ case 0xf2: >+ if (insn->isPrefixf2 && insn->prefixf2 == location) >+ return true; >+ break; >+ case 0xf3: >+ if (insn->isPrefixf3 && insn->prefixf3 == location) >+ return true; >+ break; >+ default: >+ break; >+ } >+ return false; >+} >+ >+/* >+ * readPrefixes - Consumes all of an instruction's prefix bytes, and marks the >+ * instruction as having them. Also sets the instruction's default operand, >+ * address, and other relevant data sizes to report operands correctly. >+ * >+ * @param insn - The instruction whose prefixes are to be read. >+ * @return - 0 if the instruction could be read until the end of the prefix >+ * bytes, and no prefixes conflicted; nonzero otherwise. >+ */ >+static int readPrefixes(struct InternalInstruction *insn) >+{ >+ bool isPrefix = true; >+ uint64_t prefixLocation; >+ uint8_t byte = 0, nextByte; >+ >+ bool hasAdSize = false; >+ bool hasOpSize = false; >+ >+ while (isPrefix) { >+ if (insn->mode == MODE_64BIT) { >+ // eliminate consecutive redundant REX bytes in front >+ if (consumeByte(insn, &byte)) >+ return -1; >+ >+ if ((byte & 0xf0) == 0x40) { >+ while(true) { >+ if (lookAtByte(insn, &byte)) // out of input code >+ return -1; >+ if ((byte & 0xf0) == 0x40) { >+ // another REX prefix, but we only remember the last one >+ if (consumeByte(insn, &byte)) >+ return -1; >+ } else >+ break; >+ } >+ >+ // recover the last REX byte if next byte is not a legacy prefix >+ switch (byte) { >+ case 0xf2: /* REPNE/REPNZ */ >+ case 0xf3: /* REP or REPE/REPZ */ >+ case 0xf0: /* LOCK */ >+ case 0x2e: /* CS segment override -OR- Branch not taken */ >+ case 0x36: /* SS segment override -OR- Branch taken */ >+ case 0x3e: /* DS segment override */ >+ case 0x26: /* ES segment override */ >+ case 0x64: /* FS segment override */ >+ case 0x65: /* GS segment override */ >+ case 0x66: /* Operand-size override */ >+ case 0x67: /* Address-size override */ >+ break; >+ default: /* Not a prefix byte */ >+ unconsumeByte(insn); >+ break; >+ } >+ } else { >+ unconsumeByte(insn); >+ } >+ } >+ >+ prefixLocation = insn->readerCursor; >+ >+ /* If we fail reading prefixes, just stop here and let the opcode reader deal with it */ >+ if (consumeByte(insn, &byte)) >+ return -1; >+ >+ if (insn->readerCursor - 1 == insn->startLocation >+ && (byte == 0xf2 || byte == 0xf3)) { >+ >+ if (lookAtByte(insn, &nextByte)) >+ return -1; >+ >+ /* >+ * If the byte is 0xf2 or 0xf3, and any of the following conditions are >+ * met: >+ * - it is followed by a LOCK (0xf0) prefix >+ * - it is followed by an xchg instruction >+ * then it should be disassembled as a xacquire/xrelease not repne/rep. >+ */ >+ if ((byte == 0xf2 || byte == 0xf3) && >+ ((nextByte == 0xf0) | >+ ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) >+ insn->xAcquireRelease = true; >+ /* >+ * Also if the byte is 0xf3, and the following condition is met: >+ * - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or >+ * "mov mem, imm" (opcode 0xc6/0xc7) instructions. >+ * then it should be disassembled as an xrelease not rep. >+ */ >+ if (byte == 0xf3 && >+ (nextByte == 0x88 || nextByte == 0x89 || >+ nextByte == 0xc6 || nextByte == 0xc7)) >+ insn->xAcquireRelease = true; >+ >+ if (insn->mode == MODE_64BIT && (nextByte & 0xf0) == 0x40) { >+ if (consumeByte(insn, &nextByte)) >+ return -1; >+ if (lookAtByte(insn, &nextByte)) >+ return -1; >+ unconsumeByte(insn); >+ } >+ } >+ >+ switch (byte) { >+ case 0xf2: /* REPNE/REPNZ */ >+ case 0xf3: /* REP or REPE/REPZ */ >+ case 0xf0: /* LOCK */ >+ // only accept the last prefix >+ insn->isPrefixf2 = false; >+ insn->isPrefixf3 = false; >+ insn->isPrefixf0 = false; >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix0 = byte; >+ break; >+ case 0x2e: /* CS segment override -OR- Branch not taken */ >+ insn->segmentOverride = SEG_OVERRIDE_CS; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x36: /* SS segment override -OR- Branch taken */ >+ insn->segmentOverride = SEG_OVERRIDE_SS; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x3e: /* DS segment override */ >+ insn->segmentOverride = SEG_OVERRIDE_DS; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x26: /* ES segment override */ >+ insn->segmentOverride = SEG_OVERRIDE_ES; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x64: /* FS segment override */ >+ insn->segmentOverride = SEG_OVERRIDE_FS; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x65: /* GS segment override */ >+ insn->segmentOverride = SEG_OVERRIDE_GS; >+ // only accept the last prefix >+ insn->isPrefix2e = false; >+ insn->isPrefix36 = false; >+ insn->isPrefix3e = false; >+ insn->isPrefix26 = false; >+ insn->isPrefix64 = false; >+ insn->isPrefix65 = false; >+ >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix1 = byte; >+ break; >+ case 0x66: /* Operand-size override */ >+ hasOpSize = true; >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix2 = byte; >+ break; >+ case 0x67: /* Address-size override */ >+ hasAdSize = true; >+ setPrefixPresent(insn, byte, prefixLocation); >+ insn->prefix3 = byte; >+ break; >+ default: /* Not a prefix byte */ >+ isPrefix = false; >+ break; >+ } >+ >+ //if (isPrefix) >+ // dbgprintf(insn, "Found prefix 0x%hhx", byte); >+ } >+ >+ insn->vectorExtensionType = TYPE_NO_VEX_XOP; >+ >+ >+ if (byte == 0x62) { >+ uint8_t byte1, byte2; >+ >+ if (consumeByte(insn, &byte1)) { >+ //dbgprintf(insn, "Couldn't read second byte of EVEX prefix"); >+ return -1; >+ } >+ >+ if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && >+ ((~byte1 & 0xc) == 0xc)) { >+ if (lookAtByte(insn, &byte2)) { >+ //dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); >+ return -1; >+ } >+ >+ if ((byte2 & 0x4) == 0x4) { >+ insn->vectorExtensionType = TYPE_EVEX; >+ } else { >+ unconsumeByte(insn); /* unconsume byte1 */ >+ unconsumeByte(insn); /* unconsume byte */ >+ insn->necessaryPrefixLocation = insn->readerCursor - 2; >+ } >+ >+ if (insn->vectorExtensionType == TYPE_EVEX) { >+ insn->vectorExtensionPrefix[0] = byte; >+ insn->vectorExtensionPrefix[1] = byte1; >+ >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) { >+ //dbgprintf(insn, "Couldn't read third byte of EVEX prefix"); >+ return -1; >+ } >+ >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[3])) { >+ //dbgprintf(insn, "Couldn't read fourth byte of EVEX prefix"); >+ return -1; >+ } >+ >+ /* We simulate the REX prefix for simplicity's sake */ >+ if (insn->mode == MODE_64BIT) { >+ insn->rexPrefix = 0x40 >+ | (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) >+ | (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) >+ | (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) >+ | (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); >+ } >+ switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { >+ default: >+ break; >+ case VEX_PREFIX_66: >+ hasOpSize = true; >+ break; >+ } >+ //dbgprintf(insn, "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx", >+ // insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], >+ // insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]); >+ } >+ } else { >+ // BOUND instruction >+ unconsumeByte(insn); /* unconsume byte1 */ >+ unconsumeByte(insn); /* unconsume byte */ >+ } >+ } else if (byte == 0xc4) { >+ uint8_t byte1; >+ >+ if (lookAtByte(insn, &byte1)) { >+ //dbgprintf(insn, "Couldn't read second byte of VEX"); >+ return -1; >+ } >+ >+ if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { >+ insn->vectorExtensionType = TYPE_VEX_3B; >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } else { >+ unconsumeByte(insn); >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } >+ >+ if (insn->vectorExtensionType == TYPE_VEX_3B) { >+ insn->vectorExtensionPrefix[0] = byte; >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[1])) >+ return -1; >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) >+ return -1; >+ >+ /* We simulate the REX prefix for simplicity's sake */ >+ if (insn->mode == MODE_64BIT) { >+ insn->rexPrefix = 0x40 >+ | (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) >+ | (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) >+ | (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) >+ | (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); >+ >+ } >+ switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { >+ default: >+ break; >+ case VEX_PREFIX_66: >+ hasOpSize = true; >+ break; >+ } >+ } >+ } else if (byte == 0xc5) { >+ uint8_t byte1; >+ >+ if (lookAtByte(insn, &byte1)) { >+ //dbgprintf(insn, "Couldn't read second byte of VEX"); >+ return -1; >+ } >+ >+ if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) { >+ insn->vectorExtensionType = TYPE_VEX_2B; >+ } else { >+ unconsumeByte(insn); >+ } >+ >+ if (insn->vectorExtensionType == TYPE_VEX_2B) { >+ insn->vectorExtensionPrefix[0] = byte; >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[1])) >+ return -1; >+ >+ if (insn->mode == MODE_64BIT) { >+ insn->rexPrefix = 0x40 >+ | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); >+ } >+ >+ switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { >+ default: >+ break; >+ case VEX_PREFIX_66: >+ hasOpSize = true; >+ break; >+ } >+ } >+ } else if (byte == 0x8f) { >+ uint8_t byte1; >+ >+ if (lookAtByte(insn, &byte1)) { >+ // dbgprintf(insn, "Couldn't read second byte of XOP"); >+ return -1; >+ } >+ >+ if ((byte1 & 0x38) != 0x0) { /* 0 in these 3 bits is a POP instruction. */ >+ insn->vectorExtensionType = TYPE_XOP; >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } else { >+ unconsumeByte(insn); >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } >+ >+ if (insn->vectorExtensionType == TYPE_XOP) { >+ insn->vectorExtensionPrefix[0] = byte; >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[1])) >+ return -1; >+ if (consumeByte(insn, &insn->vectorExtensionPrefix[2])) >+ return -1; >+ >+ /* We simulate the REX prefix for simplicity's sake */ >+ if (insn->mode == MODE_64BIT) { >+ insn->rexPrefix = 0x40 >+ | (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) >+ | (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) >+ | (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) >+ | (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); >+ } >+ >+ switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { >+ default: >+ break; >+ case VEX_PREFIX_66: >+ hasOpSize = true; >+ break; >+ } >+ } >+ } else { >+ if (insn->mode == MODE_64BIT) { >+ if ((byte & 0xf0) == 0x40) { >+ uint8_t opcodeByte; >+ >+ while(true) { >+ if (lookAtByte(insn, &opcodeByte)) // out of input code >+ return -1; >+ if ((opcodeByte & 0xf0) == 0x40) { >+ // another REX prefix, but we only remember the last one >+ if (consumeByte(insn, &byte)) >+ return -1; >+ } else >+ break; >+ } >+ >+ insn->rexPrefix = byte; >+ insn->necessaryPrefixLocation = insn->readerCursor - 2; >+ // dbgprintf(insn, "Found REX prefix 0x%hhx", byte); >+ } else { >+ unconsumeByte(insn); >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } >+ } else { >+ unconsumeByte(insn); >+ insn->necessaryPrefixLocation = insn->readerCursor - 1; >+ } >+ } >+ >+ if (insn->mode == MODE_16BIT) { >+ insn->registerSize = (hasOpSize ? 4 : 2); >+ insn->addressSize = (hasAdSize ? 4 : 2); >+ insn->displacementSize = (hasAdSize ? 4 : 2); >+ insn->immediateSize = (hasOpSize ? 4 : 2); >+ insn->immSize = (hasOpSize ? 4 : 2); >+ } else if (insn->mode == MODE_32BIT) { >+ insn->registerSize = (hasOpSize ? 2 : 4); >+ insn->addressSize = (hasAdSize ? 2 : 4); >+ insn->displacementSize = (hasAdSize ? 2 : 4); >+ insn->immediateSize = (hasOpSize ? 2 : 4); >+ insn->immSize = (hasOpSize ? 2 : 4); >+ } else if (insn->mode == MODE_64BIT) { >+ if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { >+ insn->registerSize = 8; >+ insn->addressSize = (hasAdSize ? 4 : 8); >+ insn->displacementSize = 4; >+ insn->immediateSize = 4; >+ insn->immSize = 4; >+ } else if (insn->rexPrefix) { >+ insn->registerSize = (hasOpSize ? 2 : 4); >+ insn->addressSize = (hasAdSize ? 4 : 8); >+ insn->displacementSize = (hasOpSize ? 2 : 4); >+ insn->immediateSize = (hasOpSize ? 2 : 4); >+ insn->immSize = (hasOpSize ? 2 : 4); >+ } else { >+ insn->registerSize = (hasOpSize ? 2 : 4); >+ insn->addressSize = (hasAdSize ? 4 : 8); >+ insn->displacementSize = (hasOpSize ? 2 : 4); >+ insn->immediateSize = (hasOpSize ? 2 : 4); >+ insn->immSize = (hasOpSize ? 4 : 8); >+ } >+ } >+ >+ return 0; >+} >+ >+static int readModRM(struct InternalInstruction *insn); >+ >+/* >+ * readOpcode - Reads the opcode (excepting the ModR/M byte in the case of >+ * extended or escape opcodes). >+ * >+ * @param insn - The instruction whose opcode is to be read. >+ * @return - 0 if the opcode could be read successfully; nonzero otherwise. >+ */ >+static int readOpcode(struct InternalInstruction *insn) >+{ >+ /* Determine the length of the primary opcode */ >+ uint8_t current; >+ >+ // printf(">>> readOpcode() = %x\n", insn->readerCursor); >+ >+ insn->opcodeType = ONEBYTE; >+ insn->firstByte = 0x00; >+ >+ if (insn->vectorExtensionType == TYPE_EVEX) { >+ switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { >+ default: >+ // dbgprintf(insn, "Unhandled mm field for instruction (0x%hhx)", >+ // mmFromEVEX2of4(insn->vectorExtensionPrefix[1])); >+ return -1; >+ case VEX_LOB_0F: >+ insn->opcodeType = TWOBYTE; >+ return consumeByte(insn, &insn->opcode); >+ case VEX_LOB_0F38: >+ insn->opcodeType = THREEBYTE_38; >+ return consumeByte(insn, &insn->opcode); >+ case VEX_LOB_0F3A: >+ insn->opcodeType = THREEBYTE_3A; >+ return consumeByte(insn, &insn->opcode); >+ } >+ } else if (insn->vectorExtensionType == TYPE_VEX_3B) { >+ switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { >+ default: >+ // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", >+ // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); >+ return -1; >+ case VEX_LOB_0F: >+ insn->twoByteEscape = 0x0f; >+ insn->opcodeType = TWOBYTE; >+ return consumeByte(insn, &insn->opcode); >+ case VEX_LOB_0F38: >+ insn->twoByteEscape = 0x0f; >+ insn->threeByteEscape = 0x38; >+ insn->opcodeType = THREEBYTE_38; >+ return consumeByte(insn, &insn->opcode); >+ case VEX_LOB_0F3A: >+ insn->twoByteEscape = 0x0f; >+ insn->threeByteEscape = 0x3a; >+ insn->opcodeType = THREEBYTE_3A; >+ return consumeByte(insn, &insn->opcode); >+ } >+ } else if (insn->vectorExtensionType == TYPE_VEX_2B) { >+ insn->twoByteEscape = 0x0f; >+ insn->opcodeType = TWOBYTE; >+ return consumeByte(insn, &insn->opcode); >+ } else if (insn->vectorExtensionType == TYPE_XOP) { >+ switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { >+ default: >+ // dbgprintf(insn, "Unhandled m-mmmm field for instruction (0x%hhx)", >+ // mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])); >+ return -1; >+ case XOP_MAP_SELECT_8: >+ // FIXME: twoByteEscape? >+ insn->opcodeType = XOP8_MAP; >+ return consumeByte(insn, &insn->opcode); >+ case XOP_MAP_SELECT_9: >+ // FIXME: twoByteEscape? >+ insn->opcodeType = XOP9_MAP; >+ return consumeByte(insn, &insn->opcode); >+ case XOP_MAP_SELECT_A: >+ // FIXME: twoByteEscape? >+ insn->opcodeType = XOPA_MAP; >+ return consumeByte(insn, &insn->opcode); >+ } >+ } >+ >+ if (consumeByte(insn, ¤t)) >+ return -1; >+ >+ // save this first byte for MOVcr, MOVdr, MOVrc, MOVrd >+ insn->firstByte = current; >+ >+ if (current == 0x0f) { >+ // dbgprintf(insn, "Found a two-byte escape prefix (0x%hhx)", current); >+ >+ insn->twoByteEscape = current; >+ >+ if (consumeByte(insn, ¤t)) >+ return -1; >+ >+ if (current == 0x38) { >+ // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); >+ >+ insn->threeByteEscape = current; >+ >+ if (consumeByte(insn, ¤t)) >+ return -1; >+ >+ insn->opcodeType = THREEBYTE_38; >+ } else if (current == 0x3a) { >+ // dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current); >+ >+ insn->threeByteEscape = current; >+ >+ if (consumeByte(insn, ¤t)) >+ return -1; >+ >+ insn->opcodeType = THREEBYTE_3A; >+ } else { >+#ifndef CAPSTONE_X86_REDUCE >+ switch(current) { >+ default: >+ // dbgprintf(insn, "Didn't find a three-byte escape prefix"); >+ insn->opcodeType = TWOBYTE; >+ break; >+ case 0x0e: // HACK for femms. to be handled properly in next version 3.x >+ insn->opcodeType = T3DNOW_MAP; >+ // this encode does not have ModRM >+ insn->consumedModRM = true; >+ break; >+ case 0x0f: >+ // 3DNow instruction has weird format: ModRM/SIB/displacement + opcode >+ if (readModRM(insn)) >+ return -1; >+ // next is 3DNow opcode >+ if (consumeByte(insn, ¤t)) >+ return -1; >+ insn->opcodeType = T3DNOW_MAP; >+ break; >+ } >+#endif >+ } >+ } >+ >+ /* >+ * At this point we have consumed the full opcode. >+ * Anything we consume from here on must be unconsumed. >+ */ >+ >+ insn->opcode = current; >+ >+ return 0; >+} >+ >+// Hacky for FEMMS >+#define GET_INSTRINFO_ENUM >+#ifndef CAPSTONE_X86_REDUCE >+#include "X86GenInstrInfo.inc" >+#else >+#include "X86GenInstrInfo_reduce.inc" >+#endif >+ >+/* >+ * getIDWithAttrMask - Determines the ID of an instruction, consuming >+ * the ModR/M byte as appropriate for extended and escape opcodes, >+ * and using a supplied attribute mask. >+ * >+ * @param instructionID - A pointer whose target is filled in with the ID of the >+ * instruction. >+ * @param insn - The instruction whose ID is to be determined. >+ * @param attrMask - The attribute mask to search. >+ * @return - 0 if the ModR/M could be read when needed or was not >+ * needed; nonzero otherwise. >+ */ >+static int getIDWithAttrMask(uint16_t *instructionID, >+ struct InternalInstruction *insn, >+ uint16_t attrMask) >+{ >+ bool hasModRMExtension; >+ >+ InstructionContext instructionClass; >+ >+#ifndef CAPSTONE_X86_REDUCE >+ // HACK for femms. to be handled properly in next version 3.x >+ if (insn->opcode == 0x0e && insn->opcodeType == T3DNOW_MAP) { >+ *instructionID = X86_FEMMS; >+ return 0; >+ } >+#endif >+ >+ if (insn->opcodeType == T3DNOW_MAP) >+ instructionClass = IC_OF; >+ else >+ instructionClass = contextForAttrs(attrMask); >+ >+ hasModRMExtension = modRMRequired(insn->opcodeType, >+ instructionClass, >+ insn->opcode) != 0; >+ >+ if (hasModRMExtension) { >+ if (readModRM(insn)) >+ return -1; >+ >+ *instructionID = decode(insn->opcodeType, >+ instructionClass, >+ insn->opcode, >+ insn->modRM); >+ } else { >+ *instructionID = decode(insn->opcodeType, >+ instructionClass, >+ insn->opcode, >+ 0); >+ } >+ >+ return 0; >+} >+ >+/* >+ * is16BitEquivalent - Determines whether two instruction names refer to >+ * equivalent instructions but one is 16-bit whereas the other is not. >+ * >+ * @param orig - The instruction ID that is not 16-bit >+ * @param equiv - The instruction ID that is 16-bit >+ */ >+static bool is16BitEquivalent(unsigned orig, unsigned equiv) >+{ >+ size_t i; >+ uint16_t idx; >+ >+ if ((idx = x86_16_bit_eq_lookup[orig]) != 0) { >+ for (i = idx - 1; i < ARR_SIZE(x86_16_bit_eq_tbl) && x86_16_bit_eq_tbl[i].first == orig; i++) { >+ if (x86_16_bit_eq_tbl[i].second == equiv) >+ return true; >+ } >+ } >+ >+ return false; >+} >+ >+/* >+ * getID - Determines the ID of an instruction, consuming the ModR/M byte as >+ * appropriate for extended and escape opcodes. Determines the attributes and >+ * context for the instruction before doing so. >+ * >+ * @param insn - The instruction whose ID is to be determined. >+ * @return - 0 if the ModR/M could be read when needed or was not needed; >+ * nonzero otherwise. >+ */ >+static int getID(struct InternalInstruction *insn) >+{ >+ uint16_t attrMask; >+ uint16_t instructionID; >+ const struct InstructionSpecifier *spec; >+ >+ // printf(">>> getID()\n"); >+ attrMask = ATTR_NONE; >+ >+ if (insn->mode == MODE_64BIT) >+ attrMask |= ATTR_64BIT; >+ >+ if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { >+ attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX; >+ >+ if (insn->vectorExtensionType == TYPE_EVEX) { >+ switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { >+ case VEX_PREFIX_66: >+ attrMask |= ATTR_OPSIZE; >+ break; >+ case VEX_PREFIX_F3: >+ attrMask |= ATTR_XS; >+ break; >+ case VEX_PREFIX_F2: >+ attrMask |= ATTR_XD; >+ break; >+ } >+ >+ if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) >+ attrMask |= ATTR_EVEXKZ; >+ if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) >+ attrMask |= ATTR_EVEXB; >+ if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])) >+ attrMask |= ATTR_EVEXK; >+ if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) >+ attrMask |= ATTR_EVEXL; >+ if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) >+ attrMask |= ATTR_EVEXL2; >+ } else if (insn->vectorExtensionType == TYPE_VEX_3B) { >+ switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { >+ case VEX_PREFIX_66: >+ attrMask |= ATTR_OPSIZE; >+ break; >+ case VEX_PREFIX_F3: >+ attrMask |= ATTR_XS; >+ break; >+ case VEX_PREFIX_F2: >+ attrMask |= ATTR_XD; >+ break; >+ } >+ >+ if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) >+ attrMask |= ATTR_VEXL; >+ } else if (insn->vectorExtensionType == TYPE_VEX_2B) { >+ switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { >+ case VEX_PREFIX_66: >+ attrMask |= ATTR_OPSIZE; >+ break; >+ case VEX_PREFIX_F3: >+ attrMask |= ATTR_XS; >+ break; >+ case VEX_PREFIX_F2: >+ attrMask |= ATTR_XD; >+ break; >+ } >+ >+ if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) >+ attrMask |= ATTR_VEXL; >+ } else if (insn->vectorExtensionType == TYPE_XOP) { >+ switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { >+ case VEX_PREFIX_66: >+ attrMask |= ATTR_OPSIZE; >+ break; >+ case VEX_PREFIX_F3: >+ attrMask |= ATTR_XS; >+ break; >+ case VEX_PREFIX_F2: >+ attrMask |= ATTR_XD; >+ break; >+ } >+ >+ if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) >+ attrMask |= ATTR_VEXL; >+ } else { >+ return -1; >+ } >+ } else { >+ if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0x66, insn->necessaryPrefixLocation)) { >+ attrMask |= ATTR_OPSIZE; >+ } else if (isPrefixAtLocation(insn, 0x67, insn->necessaryPrefixLocation)) { >+ attrMask |= ATTR_ADSIZE; >+ } else if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0xf3, insn->necessaryPrefixLocation)) { >+ attrMask |= ATTR_XS; >+ } else if (insn->mode != MODE_16BIT && isPrefixAtLocation(insn, 0xf2, insn->necessaryPrefixLocation)) { >+ attrMask |= ATTR_XD; >+ } >+ } >+ >+ if (insn->rexPrefix & 0x08) >+ attrMask |= ATTR_REXW; >+ >+ if (getIDWithAttrMask(&instructionID, insn, attrMask)) >+ return -1; >+ >+ /* Fixing CALL and JMP instruction when in 64bit mode and x66 prefix is used */ >+ if (insn->mode == MODE_64BIT && insn->isPrefix66 && >+ (insn->opcode == 0xE8 || insn->opcode == 0xE9)) >+ { >+ attrMask ^= ATTR_OPSIZE; >+ if (getIDWithAttrMask(&instructionID, insn, attrMask)) >+ return -1; >+ } >+ >+ >+ /* >+ * JCXZ/JECXZ need special handling for 16-bit mode because the meaning >+ * of the AdSize prefix is inverted w.r.t. 32-bit mode. >+ */ >+ if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) { >+ spec = specifierForUID(instructionID); >+ >+ /* >+ * Check for Ii8PCRel instructions. We could alternatively do a >+ * string-compare on the names, but this is probably cheaper. >+ */ >+ if (x86OperandSets[spec->operands][0].type == TYPE_REL8) { >+ attrMask ^= ATTR_ADSIZE; >+ if (getIDWithAttrMask(&instructionID, insn, attrMask)) >+ return -1; >+ } >+ } >+ >+ /* The following clauses compensate for limitations of the tables. */ >+ if ((insn->mode == MODE_16BIT || insn->isPrefix66) && >+ !(attrMask & ATTR_OPSIZE)) { >+ /* >+ * The instruction tables make no distinction between instructions that >+ * allow OpSize anywhere (i.e., 16-bit operations) and that need it in a >+ * particular spot (i.e., many MMX operations). In general we're >+ * conservative, but in the specific case where OpSize is present but not >+ * in the right place we check if there's a 16-bit operation. >+ */ >+ >+ const struct InstructionSpecifier *spec; >+ uint16_t instructionIDWithOpsize; >+ >+ spec = specifierForUID(instructionID); >+ >+ if (getIDWithAttrMask(&instructionIDWithOpsize, >+ insn, attrMask | ATTR_OPSIZE)) { >+ /* >+ * ModRM required with OpSize but not present; give up and return version >+ * without OpSize set >+ */ >+ >+ insn->instructionID = instructionID; >+ insn->spec = spec; >+ return 0; >+ } >+ >+ if (is16BitEquivalent(instructionID, instructionIDWithOpsize) && >+ (insn->mode == MODE_16BIT) ^ insn->isPrefix66) { >+ insn->instructionID = instructionIDWithOpsize; >+ insn->spec = specifierForUID(instructionIDWithOpsize); >+ } else { >+ insn->instructionID = instructionID; >+ insn->spec = spec; >+ } >+ return 0; >+ } >+ >+ if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && >+ insn->rexPrefix & 0x01) { >+ /* >+ * NOOP shouldn't decode as NOOP if REX.b is set. Instead >+ * it should decode as XCHG %r8, %eax. >+ */ >+ >+ const struct InstructionSpecifier *spec; >+ uint16_t instructionIDWithNewOpcode; >+ const struct InstructionSpecifier *specWithNewOpcode; >+ >+ spec = specifierForUID(instructionID); >+ >+ /* Borrow opcode from one of the other XCHGar opcodes */ >+ insn->opcode = 0x91; >+ >+ if (getIDWithAttrMask(&instructionIDWithNewOpcode, >+ insn, >+ attrMask)) { >+ insn->opcode = 0x90; >+ >+ insn->instructionID = instructionID; >+ insn->spec = spec; >+ return 0; >+ } >+ >+ specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode); >+ >+ /* Change back */ >+ insn->opcode = 0x90; >+ >+ insn->instructionID = instructionIDWithNewOpcode; >+ insn->spec = specWithNewOpcode; >+ >+ return 0; >+ } >+ >+ insn->instructionID = instructionID; >+ insn->spec = specifierForUID(insn->instructionID); >+ >+ return 0; >+} >+ >+/* >+ * readSIB - Consumes the SIB byte to determine addressing information for an >+ * instruction. >+ * >+ * @param insn - The instruction whose SIB byte is to be read. >+ * @return - 0 if the SIB byte was successfully read; nonzero otherwise. >+ */ >+static int readSIB(struct InternalInstruction *insn) >+{ >+ SIBIndex sibIndexBase = SIB_INDEX_NONE; >+ SIBBase sibBaseBase = SIB_BASE_NONE; >+ uint8_t index, base; >+ >+ // dbgprintf(insn, "readSIB()"); >+ >+ if (insn->consumedSIB) >+ return 0; >+ >+ insn->consumedSIB = true; >+ >+ switch (insn->addressSize) { >+ case 2: >+ // dbgprintf(insn, "SIB-based addressing doesn't work in 16-bit mode"); >+ return -1; >+ case 4: >+ sibIndexBase = SIB_INDEX_EAX; >+ sibBaseBase = SIB_BASE_EAX; >+ break; >+ case 8: >+ sibIndexBase = SIB_INDEX_RAX; >+ sibBaseBase = SIB_BASE_RAX; >+ break; >+ } >+ >+ if (consumeByte(insn, &insn->sib)) >+ return -1; >+ >+ index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3); >+ if (insn->vectorExtensionType == TYPE_EVEX) >+ index |= v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4; >+ >+ switch (index) { >+ case 0x4: >+ insn->sibIndex = SIB_INDEX_NONE; >+ break; >+ default: >+ insn->sibIndex = (SIBIndex)(sibIndexBase + index); >+ if (insn->sibIndex == SIB_INDEX_sib || >+ insn->sibIndex == SIB_INDEX_sib64) >+ insn->sibIndex = SIB_INDEX_NONE; >+ break; >+ } >+ >+ switch (scaleFromSIB(insn->sib)) { >+ case 0: >+ insn->sibScale = 1; >+ break; >+ case 1: >+ insn->sibScale = 2; >+ break; >+ case 2: >+ insn->sibScale = 4; >+ break; >+ case 3: >+ insn->sibScale = 8; >+ break; >+ } >+ >+ base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3); >+ >+ switch (base) { >+ case 0x5: >+ case 0xd: >+ switch (modFromModRM(insn->modRM)) { >+ case 0x0: >+ insn->eaDisplacement = EA_DISP_32; >+ insn->sibBase = SIB_BASE_NONE; >+ break; >+ case 0x1: >+ insn->eaDisplacement = EA_DISP_8; >+ insn->sibBase = (SIBBase)(sibBaseBase + base); >+ break; >+ case 0x2: >+ insn->eaDisplacement = EA_DISP_32; >+ insn->sibBase = (SIBBase)(sibBaseBase + base); >+ break; >+ case 0x3: >+ //debug("Cannot have Mod = 0b11 and a SIB byte"); >+ return -1; >+ } >+ break; >+ default: >+ insn->sibBase = (SIBBase)(sibBaseBase + base); >+ break; >+ } >+ >+ return 0; >+} >+ >+/* >+ * readDisplacement - Consumes the displacement of an instruction. >+ * >+ * @param insn - The instruction whose displacement is to be read. >+ * @return - 0 if the displacement byte was successfully read; nonzero >+ * otherwise. >+ */ >+static int readDisplacement(struct InternalInstruction *insn) >+{ >+ int8_t d8; >+ int16_t d16; >+ int32_t d32; >+ >+ // dbgprintf(insn, "readDisplacement()"); >+ >+ if (insn->consumedDisplacement) >+ return 0; >+ >+ insn->consumedDisplacement = true; >+ insn->displacementOffset = (uint8_t)(insn->readerCursor - insn->startLocation); >+ >+ switch (insn->eaDisplacement) { >+ case EA_DISP_NONE: >+ insn->consumedDisplacement = false; >+ break; >+ case EA_DISP_8: >+ if (consumeInt8(insn, &d8)) >+ return -1; >+ insn->displacement = d8; >+ break; >+ case EA_DISP_16: >+ if (consumeInt16(insn, &d16)) >+ return -1; >+ insn->displacement = d16; >+ break; >+ case EA_DISP_32: >+ if (consumeInt32(insn, &d32)) >+ return -1; >+ insn->displacement = d32; >+ break; >+ } >+ >+ insn->consumedDisplacement = true; >+ return 0; >+} >+ >+/* >+ * readModRM - Consumes all addressing information (ModR/M byte, SIB byte, and >+ * displacement) for an instruction and interprets it. >+ * >+ * @param insn - The instruction whose addressing information is to be read. >+ * @return - 0 if the information was successfully read; nonzero otherwise. >+ */ >+static int readModRM(struct InternalInstruction *insn) >+{ >+ uint8_t mod, rm, reg; >+ >+ // dbgprintf(insn, "readModRM()"); >+ >+ // already got ModRM byte? >+ if (insn->consumedModRM) >+ return 0; >+ >+ if (consumeByte(insn, &insn->modRM)) >+ return -1; >+ >+ // mark that we already got ModRM >+ insn->consumedModRM = true; >+ >+ // save original ModRM for later reference >+ insn->orgModRM = insn->modRM; >+ >+ // handle MOVcr, MOVdr, MOVrc, MOVrd by pretending they have MRM.mod = 3 >+ if ((insn->firstByte == 0x0f && insn->opcodeType == TWOBYTE) && >+ (insn->opcode >= 0x20 && insn->opcode <= 0x23 )) >+ insn->modRM |= 0xC0; >+ >+ mod = modFromModRM(insn->modRM); >+ rm = rmFromModRM(insn->modRM); >+ reg = regFromModRM(insn->modRM); >+ >+ /* >+ * This goes by insn->registerSize to pick the correct register, which messes >+ * up if we're using (say) XMM or 8-bit register operands. That gets fixed in >+ * fixupReg(). >+ */ >+ switch (insn->registerSize) { >+ case 2: >+ insn->regBase = MODRM_REG_AX; >+ insn->eaRegBase = EA_REG_AX; >+ break; >+ case 4: >+ insn->regBase = MODRM_REG_EAX; >+ insn->eaRegBase = EA_REG_EAX; >+ break; >+ case 8: >+ insn->regBase = MODRM_REG_RAX; >+ insn->eaRegBase = EA_REG_RAX; >+ break; >+ } >+ >+ reg |= rFromREX(insn->rexPrefix) << 3; >+ rm |= bFromREX(insn->rexPrefix) << 3; >+ if (insn->vectorExtensionType == TYPE_EVEX) { >+ reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; >+ rm |= xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; >+ } >+ >+ insn->reg = (Reg)(insn->regBase + reg); >+ >+ switch (insn->addressSize) { >+ case 2: >+ insn->eaBaseBase = EA_BASE_BX_SI; >+ >+ switch (mod) { >+ case 0x0: >+ if (rm == 0x6) { >+ insn->eaBase = EA_BASE_NONE; >+ insn->eaDisplacement = EA_DISP_16; >+ if (readDisplacement(insn)) >+ return -1; >+ } else { >+ insn->eaBase = (EABase)(insn->eaBaseBase + rm); >+ insn->eaDisplacement = EA_DISP_NONE; >+ } >+ break; >+ case 0x1: >+ insn->eaBase = (EABase)(insn->eaBaseBase + rm); >+ insn->eaDisplacement = EA_DISP_8; >+ insn->displacementSize = 1; >+ if (readDisplacement(insn)) >+ return -1; >+ break; >+ case 0x2: >+ insn->eaBase = (EABase)(insn->eaBaseBase + rm); >+ insn->eaDisplacement = EA_DISP_16; >+ if (readDisplacement(insn)) >+ return -1; >+ break; >+ case 0x3: >+ insn->eaBase = (EABase)(insn->eaRegBase + rm); >+ insn->eaDisplacement = EA_DISP_NONE; >+ if (readDisplacement(insn)) >+ return -1; >+ break; >+ } >+ break; >+ case 4: >+ case 8: >+ insn->eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); >+ >+ switch (mod) { >+ case 0x0: >+ insn->eaDisplacement = EA_DISP_NONE; /* readSIB may override this */ >+ switch (rm) { >+ case 0x14: >+ case 0x4: >+ case 0xc: /* in case REXW.b is set */ >+ insn->eaBase = (insn->addressSize == 4 ? >+ EA_BASE_sib : EA_BASE_sib64); >+ if (readSIB(insn) || readDisplacement(insn)) >+ return -1; >+ break; >+ case 0x5: >+ case 0xd: >+ insn->eaBase = EA_BASE_NONE; >+ insn->eaDisplacement = EA_DISP_32; >+ if (readDisplacement(insn)) >+ return -1; >+ break; >+ default: >+ insn->eaBase = (EABase)(insn->eaBaseBase + rm); >+ break; >+ } >+ >+ break; >+ case 0x1: >+ insn->displacementSize = 1; >+ /* FALLTHROUGH */ >+ case 0x2: >+ insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); >+ switch (rm) { >+ case 0x14: >+ case 0x4: >+ case 0xc: /* in case REXW.b is set */ >+ insn->eaBase = EA_BASE_sib; >+ if (readSIB(insn) || readDisplacement(insn)) >+ return -1; >+ break; >+ default: >+ insn->eaBase = (EABase)(insn->eaBaseBase + rm); >+ if (readDisplacement(insn)) >+ return -1; >+ break; >+ } >+ break; >+ case 0x3: >+ insn->eaDisplacement = EA_DISP_NONE; >+ insn->eaBase = (EABase)(insn->eaRegBase + rm); >+ break; >+ } >+ break; >+ } /* switch (insn->addressSize) */ >+ >+ return 0; >+} >+ >+#define GENERIC_FIXUP_FUNC(name, base, prefix) \ >+ static uint8_t name(struct InternalInstruction *insn, \ >+ OperandType type, \ >+ uint8_t index, \ >+ uint8_t *valid) { \ >+ *valid = 1; \ >+ switch (type) { \ >+ case TYPE_R8: \ >+ insn->operandSize = 1; \ >+ break; \ >+ case TYPE_R16: \ >+ insn->operandSize = 2; \ >+ break; \ >+ case TYPE_R32: \ >+ insn->operandSize = 4; \ >+ break; \ >+ case TYPE_R64: \ >+ insn->operandSize = 8; \ >+ break; \ >+ case TYPE_XMM512: \ >+ insn->operandSize = 64; \ >+ break; \ >+ case TYPE_XMM256: \ >+ insn->operandSize = 32; \ >+ break; \ >+ case TYPE_XMM128: \ >+ insn->operandSize = 16; \ >+ break; \ >+ case TYPE_XMM64: \ >+ insn->operandSize = 8; \ >+ break; \ >+ case TYPE_XMM32: \ >+ insn->operandSize = 4; \ >+ break; \ >+ case TYPE_XMM: \ >+ insn->operandSize = 2; \ >+ break; \ >+ case TYPE_MM64: \ >+ insn->operandSize = 8; \ >+ break; \ >+ case TYPE_MM32: \ >+ insn->operandSize = 4; \ >+ break; \ >+ case TYPE_MM: \ >+ insn->operandSize = 2; \ >+ break; \ >+ case TYPE_CONTROLREG: \ >+ insn->operandSize = 4; \ >+ break; \ >+ default: break; \ >+ } \ >+ switch (type) { \ >+ default: \ >+ *valid = 0; \ >+ return 0; \ >+ case TYPE_Rv: \ >+ return (uint8_t)(base + index); \ >+ case TYPE_R8: \ >+ if (insn->rexPrefix && \ >+ index >= 4 && index <= 7) { \ >+ return prefix##_SPL + (index - 4); \ >+ } else { \ >+ return prefix##_AL + index; \ >+ } \ >+ case TYPE_R16: \ >+ return prefix##_AX + index; \ >+ case TYPE_R32: \ >+ return prefix##_EAX + index; \ >+ case TYPE_R64: \ >+ return prefix##_RAX + index; \ >+ case TYPE_XMM512: \ >+ return prefix##_ZMM0 + index; \ >+ case TYPE_XMM256: \ >+ return prefix##_YMM0 + index; \ >+ case TYPE_XMM128: \ >+ case TYPE_XMM64: \ >+ case TYPE_XMM32: \ >+ case TYPE_XMM: \ >+ return prefix##_XMM0 + index; \ >+ case TYPE_VK1: \ >+ case TYPE_VK8: \ >+ case TYPE_VK16: \ >+ if (index > 7) \ >+ *valid = 0; \ >+ return prefix##_K0 + index; \ >+ case TYPE_MM64: \ >+ case TYPE_MM32: \ >+ case TYPE_MM: \ >+ return prefix##_MM0 + (index & 7); \ >+ case TYPE_SEGMENTREG: \ >+ if (index > 5) \ >+ *valid = 0; \ >+ return prefix##_ES + index; \ >+ case TYPE_DEBUGREG: \ >+ if (index > 7) \ >+ *valid = 0; \ >+ return prefix##_DR0 + index; \ >+ case TYPE_CONTROLREG: \ >+ return prefix##_CR0 + index; \ >+ } \ >+ } >+ >+/* >+ * fixup*Value - Consults an operand type to determine the meaning of the >+ * reg or R/M field. If the operand is an XMM operand, for example, an >+ * operand would be XMM0 instead of AX, which readModRM() would otherwise >+ * misinterpret it as. >+ * >+ * @param insn - The instruction containing the operand. >+ * @param type - The operand type. >+ * @param index - The existing value of the field as reported by readModRM(). >+ * @param valid - The address of a uint8_t. The target is set to 1 if the >+ * field is valid for the register class; 0 if not. >+ * @return - The proper value. >+ */ >+GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG) >+GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) >+ >+/* >+ * fixupReg - Consults an operand specifier to determine which of the >+ * fixup*Value functions to use in correcting readModRM()'ss interpretation. >+ * >+ * @param insn - See fixup*Value(). >+ * @param op - The operand specifier. >+ * @return - 0 if fixup was successful; -1 if the register returned was >+ * invalid for its class. >+ */ >+static int fixupReg(struct InternalInstruction *insn, >+ const struct OperandSpecifier *op) >+{ >+ uint8_t valid; >+ >+ // dbgprintf(insn, "fixupReg()"); >+ >+ switch ((OperandEncoding)op->encoding) { >+ default: >+ //debug("Expected a REG or R/M encoding in fixupReg"); >+ return -1; >+ case ENCODING_VVVV: >+ insn->vvvv = (Reg)fixupRegValue(insn, >+ (OperandType)op->type, >+ insn->vvvv, >+ &valid); >+ if (!valid) >+ return -1; >+ break; >+ case ENCODING_REG: >+ insn->reg = (Reg)fixupRegValue(insn, >+ (OperandType)op->type, >+ (uint8_t)(insn->reg - insn->regBase), >+ &valid); >+ if (!valid) >+ return -1; >+ break; >+ CASE_ENCODING_RM: >+ if (insn->eaBase >= insn->eaRegBase) { >+ insn->eaBase = (EABase)fixupRMValue(insn, >+ (OperandType)op->type, >+ (uint8_t)(insn->eaBase - insn->eaRegBase), >+ &valid); >+ if (!valid) >+ return -1; >+ } >+ break; >+ } >+ >+ return 0; >+} >+ >+/* >+ * readOpcodeRegister - Reads an operand from the opcode field of an >+ * instruction and interprets it appropriately given the operand width. >+ * Handles AddRegFrm instructions. >+ * >+ * @param insn - the instruction whose opcode field is to be read. >+ * @param size - The width (in bytes) of the register being specified. >+ * 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means >+ * RAX. >+ * @return - 0 on success; nonzero otherwise. >+ */ >+static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) >+{ >+ // dbgprintf(insn, "readOpcodeRegister()"); >+ >+ if (size == 0) >+ size = insn->registerSize; >+ >+ insn->operandSize = size; >+ >+ switch (size) { >+ case 1: >+ insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) >+ | (insn->opcode & 7))); >+ if (insn->rexPrefix && >+ insn->opcodeRegister >= MODRM_REG_AL + 0x4 && >+ insn->opcodeRegister < MODRM_REG_AL + 0x8) { >+ insn->opcodeRegister = (Reg)(MODRM_REG_SPL >+ + (insn->opcodeRegister - MODRM_REG_AL - 4)); >+ } >+ >+ break; >+ case 2: >+ insn->opcodeRegister = (Reg)(MODRM_REG_AX >+ + ((bFromREX(insn->rexPrefix) << 3) >+ | (insn->opcode & 7))); >+ break; >+ case 4: >+ insn->opcodeRegister = (Reg)(MODRM_REG_EAX >+ + ((bFromREX(insn->rexPrefix) << 3) >+ | (insn->opcode & 7))); >+ break; >+ case 8: >+ insn->opcodeRegister = (Reg)(MODRM_REG_RAX >+ + ((bFromREX(insn->rexPrefix) << 3) >+ | (insn->opcode & 7))); >+ break; >+ } >+ >+ return 0; >+} >+ >+/* >+ * readImmediate - Consumes an immediate operand from an instruction, given the >+ * desired operand size. >+ * >+ * @param insn - The instruction whose operand is to be read. >+ * @param size - The width (in bytes) of the operand. >+ * @return - 0 if the immediate was successfully consumed; nonzero >+ * otherwise. >+ */ >+static int readImmediate(struct InternalInstruction *insn, uint8_t size) >+{ >+ uint8_t imm8; >+ uint16_t imm16; >+ uint32_t imm32; >+ uint64_t imm64; >+ >+ // dbgprintf(insn, "readImmediate()"); >+ >+ if (insn->numImmediatesConsumed == 2) { >+ //debug("Already consumed two immediates"); >+ return -1; >+ } >+ >+ if (size == 0) >+ size = insn->immediateSize; >+ else >+ insn->immediateSize = size; >+ insn->immediateOffset = (uint8_t)(insn->readerCursor - insn->startLocation); >+ >+ switch (size) { >+ case 1: >+ if (consumeByte(insn, &imm8)) >+ return -1; >+ insn->immediates[insn->numImmediatesConsumed] = imm8; >+ break; >+ case 2: >+ if (consumeUInt16(insn, &imm16)) >+ return -1; >+ insn->immediates[insn->numImmediatesConsumed] = imm16; >+ break; >+ case 4: >+ if (consumeUInt32(insn, &imm32)) >+ return -1; >+ insn->immediates[insn->numImmediatesConsumed] = imm32; >+ break; >+ case 8: >+ if (consumeUInt64(insn, &imm64)) >+ return -1; >+ insn->immediates[insn->numImmediatesConsumed] = imm64; >+ break; >+ } >+ >+ insn->numImmediatesConsumed++; >+ >+ return 0; >+} >+ >+/* >+ * readVVVV - Consumes vvvv from an instruction if it has a VEX prefix. >+ * >+ * @param insn - The instruction whose operand is to be read. >+ * @return - 0 if the vvvv was successfully consumed; nonzero >+ * otherwise. >+ */ >+static int readVVVV(struct InternalInstruction *insn) >+{ >+ int vvvv; >+ // dbgprintf(insn, "readVVVV()"); >+ >+ if (insn->vectorExtensionType == TYPE_EVEX) >+ vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | >+ vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); >+ else if (insn->vectorExtensionType == TYPE_VEX_3B) >+ vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); >+ else if (insn->vectorExtensionType == TYPE_VEX_2B) >+ vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); >+ else if (insn->vectorExtensionType == TYPE_XOP) >+ vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); >+ else >+ return -1; >+ >+ if (insn->mode != MODE_64BIT) >+ vvvv &= 0x7; >+ >+ insn->vvvv = vvvv; >+ >+ return 0; >+} >+ >+/* >+ * readMaskRegister - Reads an mask register from the opcode field of an >+ * instruction. >+ * >+ * @param insn - The instruction whose opcode field is to be read. >+ * @return - 0 on success; nonzero otherwise. >+ */ >+static int readMaskRegister(struct InternalInstruction *insn) >+{ >+ // dbgprintf(insn, "readMaskRegister()"); >+ >+ if (insn->vectorExtensionType != TYPE_EVEX) >+ return -1; >+ >+ insn->writemask = aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]); >+ >+ return 0; >+} >+ >+/* >+ * readOperands - Consults the specifier for an instruction and consumes all >+ * operands for that instruction, interpreting them as it goes. >+ * >+ * @param insn - The instruction whose operands are to be read and interpreted. >+ * @return - 0 if all operands could be read; nonzero otherwise. >+ */ >+static int readOperands(struct InternalInstruction *insn) >+{ >+ int index; >+ int hasVVVV, needVVVV; >+ int sawRegImm = 0; >+ >+ // printf(">>> readOperands()\n"); >+ /* If non-zero vvvv specified, need to make sure one of the operands >+ uses it. */ >+ hasVVVV = !readVVVV(insn); >+ needVVVV = hasVVVV && (insn->vvvv != 0); >+ >+ for (index = 0; index < X86_MAX_OPERANDS; ++index) { >+ //printf(">>> encoding[%u] = %u\n", index, x86OperandSets[insn->spec->operands][index].encoding); >+ switch (x86OperandSets[insn->spec->operands][index].encoding) { >+ case ENCODING_NONE: >+ case ENCODING_SI: >+ case ENCODING_DI: >+ break; >+ case ENCODING_REG: >+ CASE_ENCODING_RM: >+ if (readModRM(insn)) >+ return -1; >+ if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index])) >+ return -1; >+ // Apply the AVX512 compressed displacement scaling factor. >+ if (x86OperandSets[insn->spec->operands][index].encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) >+ insn->displacement *= 1 << (x86OperandSets[insn->spec->operands][index].encoding - ENCODING_RM); >+ break; >+ case ENCODING_CB: >+ case ENCODING_CW: >+ case ENCODING_CD: >+ case ENCODING_CP: >+ case ENCODING_CO: >+ case ENCODING_CT: >+ // dbgprintf(insn, "We currently don't hande code-offset encodings"); >+ return -1; >+ case ENCODING_IB: >+ if (sawRegImm) { >+ /* Saw a register immediate so don't read again and instead split the >+ previous immediate. FIXME: This is a hack. */ >+ insn->immediates[insn->numImmediatesConsumed] = >+ insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; >+ ++insn->numImmediatesConsumed; >+ break; >+ } >+ if (readImmediate(insn, 1)) >+ return -1; >+ if (x86OperandSets[insn->spec->operands][index].type == TYPE_XMM128 || >+ x86OperandSets[insn->spec->operands][index].type == TYPE_XMM256) >+ sawRegImm = 1; >+ break; >+ case ENCODING_IW: >+ if (readImmediate(insn, 2)) >+ return -1; >+ break; >+ case ENCODING_ID: >+ if (readImmediate(insn, 4)) >+ return -1; >+ break; >+ case ENCODING_IO: >+ if (readImmediate(insn, 8)) >+ return -1; >+ break; >+ case ENCODING_Iv: >+ if (readImmediate(insn, insn->immediateSize)) >+ return -1; >+ break; >+ case ENCODING_Ia: >+ if (readImmediate(insn, insn->addressSize)) >+ return -1; >+ break; >+ case ENCODING_RB: >+ if (readOpcodeRegister(insn, 1)) >+ return -1; >+ break; >+ case ENCODING_RW: >+ if (readOpcodeRegister(insn, 2)) >+ return -1; >+ break; >+ case ENCODING_RD: >+ if (readOpcodeRegister(insn, 4)) >+ return -1; >+ break; >+ case ENCODING_RO: >+ if (readOpcodeRegister(insn, 8)) >+ return -1; >+ break; >+ case ENCODING_Rv: >+ if (readOpcodeRegister(insn, 0)) >+ return -1; >+ break; >+ case ENCODING_FP: >+ break; >+ case ENCODING_VVVV: >+ needVVVV = 0; /* Mark that we have found a VVVV operand. */ >+ if (!hasVVVV) >+ return -1; >+ if (fixupReg(insn, &x86OperandSets[insn->spec->operands][index])) >+ return -1; >+ break; >+ case ENCODING_WRITEMASK: >+ if (readMaskRegister(insn)) >+ return -1; >+ break; >+ case ENCODING_DUP: >+ break; >+ default: >+ // dbgprintf(insn, "Encountered an operand with an unknown encoding."); >+ return -1; >+ } >+ } >+ >+ /* If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail */ >+ if (needVVVV) return -1; >+ >+ return 0; >+} >+ >+// return True if instruction is illegal to use with prefixes >+// This also check & fix the prefixPresent[] when a prefix is irrelevant. >+static bool checkPrefix(struct InternalInstruction *insn) >+{ >+ // LOCK prefix >+ if (insn->isPrefixf0) { >+ switch(insn->instructionID) { >+ default: >+ // invalid LOCK >+ return true; >+ >+ // nop dword [rax] >+ case X86_NOOPL: >+ >+ // DEC >+ case X86_DEC16m: >+ case X86_DEC32m: >+ case X86_DEC64_16m: >+ case X86_DEC64_32m: >+ case X86_DEC64m: >+ case X86_DEC8m: >+ >+ // ADC >+ case X86_ADC16mi: >+ case X86_ADC16mi8: >+ case X86_ADC16mr: >+ case X86_ADC32mi: >+ case X86_ADC32mi8: >+ case X86_ADC32mr: >+ case X86_ADC64mi32: >+ case X86_ADC64mi8: >+ case X86_ADC64mr: >+ case X86_ADC8mi: >+ case X86_ADC8mr: >+ >+ // ADD >+ case X86_ADD16mi: >+ case X86_ADD16mi8: >+ case X86_ADD16mr: >+ case X86_ADD32mi: >+ case X86_ADD32mi8: >+ case X86_ADD32mr: >+ case X86_ADD64mi32: >+ case X86_ADD64mi8: >+ case X86_ADD64mr: >+ case X86_ADD8mi: >+ case X86_ADD8mr: >+ >+ // AND >+ case X86_AND16mi: >+ case X86_AND16mi8: >+ case X86_AND16mr: >+ case X86_AND32mi: >+ case X86_AND32mi8: >+ case X86_AND32mr: >+ case X86_AND64mi32: >+ case X86_AND64mi8: >+ case X86_AND64mr: >+ case X86_AND8mi: >+ case X86_AND8mr: >+ >+ // BTC >+ case X86_BTC16mi8: >+ case X86_BTC16mr: >+ case X86_BTC32mi8: >+ case X86_BTC32mr: >+ case X86_BTC64mi8: >+ case X86_BTC64mr: >+ >+ // BTR >+ case X86_BTR16mi8: >+ case X86_BTR16mr: >+ case X86_BTR32mi8: >+ case X86_BTR32mr: >+ case X86_BTR64mi8: >+ case X86_BTR64mr: >+ >+ // BTS >+ case X86_BTS16mi8: >+ case X86_BTS16mr: >+ case X86_BTS32mi8: >+ case X86_BTS32mr: >+ case X86_BTS64mi8: >+ case X86_BTS64mr: >+ >+ // CMPXCHG >+ case X86_CMPXCHG16B: >+ case X86_CMPXCHG16rm: >+ case X86_CMPXCHG32rm: >+ case X86_CMPXCHG64rm: >+ case X86_CMPXCHG8rm: >+ case X86_CMPXCHG8B: >+ >+ // INC >+ case X86_INC16m: >+ case X86_INC32m: >+ case X86_INC64_16m: >+ case X86_INC64_32m: >+ case X86_INC64m: >+ case X86_INC8m: >+ >+ // NEG >+ case X86_NEG16m: >+ case X86_NEG32m: >+ case X86_NEG64m: >+ case X86_NEG8m: >+ >+ // NOT >+ case X86_NOT16m: >+ case X86_NOT32m: >+ case X86_NOT64m: >+ case X86_NOT8m: >+ >+ // OR >+ case X86_OR16mi: >+ case X86_OR16mi8: >+ case X86_OR16mr: >+ case X86_OR32mi: >+ case X86_OR32mi8: >+ case X86_OR32mr: >+ case X86_OR32mrLocked: >+ case X86_OR64mi32: >+ case X86_OR64mi8: >+ case X86_OR64mr: >+ case X86_OR8mi: >+ case X86_OR8mr: >+ >+ // SBB >+ case X86_SBB16mi: >+ case X86_SBB16mi8: >+ case X86_SBB16mr: >+ case X86_SBB32mi: >+ case X86_SBB32mi8: >+ case X86_SBB32mr: >+ case X86_SBB64mi32: >+ case X86_SBB64mi8: >+ case X86_SBB64mr: >+ case X86_SBB8mi: >+ case X86_SBB8mr: >+ >+ // SUB >+ case X86_SUB16mi: >+ case X86_SUB16mi8: >+ case X86_SUB16mr: >+ case X86_SUB32mi: >+ case X86_SUB32mi8: >+ case X86_SUB32mr: >+ case X86_SUB64mi32: >+ case X86_SUB64mi8: >+ case X86_SUB64mr: >+ case X86_SUB8mi: >+ case X86_SUB8mr: >+ >+ // XADD >+ case X86_XADD16rm: >+ case X86_XADD32rm: >+ case X86_XADD64rm: >+ case X86_XADD8rm: >+ >+ // XCHG >+ case X86_XCHG16rm: >+ case X86_XCHG32rm: >+ case X86_XCHG64rm: >+ case X86_XCHG8rm: >+ >+ // XOR >+ case X86_XOR16mi: >+ case X86_XOR16mi8: >+ case X86_XOR16mr: >+ case X86_XOR32mi: >+ case X86_XOR32mi8: >+ case X86_XOR32mr: >+ case X86_XOR64mi32: >+ case X86_XOR64mi8: >+ case X86_XOR64mr: >+ case X86_XOR8mi: >+ case X86_XOR8mr: >+ >+ // this instruction can be used with LOCK prefix >+ return false; >+ } >+ } >+ >+ // REPNE prefix >+ if (insn->isPrefixf2) { >+ // 0xf2 can be a part of instruction encoding, but not really a prefix. >+ // In such a case, clear it. >+ if (insn->twoByteEscape == 0x0f) { >+ insn->prefix0 = 0; >+ } >+ } >+ >+ // no invalid prefixes >+ return false; >+} >+ >+/* >+ * decodeInstruction - Reads and interprets a full instruction provided by the >+ * user. >+ * >+ * @param insn - A pointer to the instruction to be populated. Must be >+ * pre-allocated. >+ * @param reader - The function to be used to read the instruction's bytes. >+ * @param readerArg - A generic argument to be passed to the reader to store >+ * any internal state. >+ * @param startLoc - The address (in the reader's address space) of the first >+ * byte in the instruction. >+ * @param mode - The mode (real mode, IA-32e, or IA-32e in 64-bit mode) to >+ * decode the instruction in. >+ * @return - 0 if instruction is valid; nonzero if not. >+ */ >+int decodeInstruction(struct InternalInstruction *insn, >+ byteReader_t reader, >+ const void *readerArg, >+ uint64_t startLoc, >+ DisassemblerMode mode) >+{ >+ insn->reader = reader; >+ insn->readerArg = readerArg; >+ insn->startLocation = startLoc; >+ insn->readerCursor = startLoc; >+ insn->mode = mode; >+ >+ if (readPrefixes(insn) || >+ readOpcode(insn) || >+ getID(insn) || >+ insn->instructionID == 0 || >+ checkPrefix(insn) || >+ readOperands(insn)) >+ return -1; >+ >+ insn->length = (size_t)(insn->readerCursor - insn->startLocation); >+ >+ // instruction length must be <= 15 to be valid >+ if (insn->length > 15) >+ return -1; >+ >+ if (insn->operandSize == 0) >+ insn->operandSize = insn->registerSize; >+ >+ insn->operands = &x86OperandSets[insn->spec->operands][0]; >+ >+ // dbgprintf(insn, "Read from 0x%llx to 0x%llx: length %zu", >+ // startLoc, insn->readerCursor, insn->length); >+ >+ //if (insn->length > 15) >+ // dbgprintf(insn, "Instruction exceeds 15-byte limit"); >+ >+#if 0 >+ printf("\n>>> x86OperandSets = %lu\n", sizeof(x86OperandSets)); >+ printf(">>> x86DisassemblerInstrSpecifiers = %lu\n", sizeof(x86DisassemblerInstrSpecifiers)); >+ printf(">>> x86DisassemblerContexts = %lu\n", sizeof(x86DisassemblerContexts)); >+ printf(">>> modRMTable = %lu\n", sizeof(modRMTable)); >+ printf(">>> x86DisassemblerOneByteOpcodes = %lu\n", sizeof(x86DisassemblerOneByteOpcodes)); >+ printf(">>> x86DisassemblerTwoByteOpcodes = %lu\n", sizeof(x86DisassemblerTwoByteOpcodes)); >+ printf(">>> x86DisassemblerThreeByte38Opcodes = %lu\n", sizeof(x86DisassemblerThreeByte38Opcodes)); >+ printf(">>> x86DisassemblerThreeByte3AOpcodes = %lu\n", sizeof(x86DisassemblerThreeByte3AOpcodes)); >+ printf(">>> x86DisassemblerThreeByteA6Opcodes = %lu\n", sizeof(x86DisassemblerThreeByteA6Opcodes)); >+ printf(">>> x86DisassemblerThreeByteA7Opcodes= %lu\n", sizeof(x86DisassemblerThreeByteA7Opcodes)); >+ printf(">>> x86DisassemblerXOP8Opcodes = %lu\n", sizeof(x86DisassemblerXOP8Opcodes)); >+ printf(">>> x86DisassemblerXOP9Opcodes = %lu\n", sizeof(x86DisassemblerXOP9Opcodes)); >+ printf(">>> x86DisassemblerXOPAOpcodes = %lu\n\n", sizeof(x86DisassemblerXOPAOpcodes)); >+#endif >+ >+ return 0; >+} >+ >+#endif >+ >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.h b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.h >new file mode 100644 >index 0000000000000000000000000000000000000000..a022be5b8473ecb1b3cfffc78e3de599f84227f7 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoder.h >@@ -0,0 +1,735 @@ >+/*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===* >+ * >+ * The LLVM Compiler Infrastructure >+ * >+ * This file is distributed under the University of Illinois Open Source >+ * License. See LICENSE.TXT for details. >+ * >+ *===----------------------------------------------------------------------===* >+ * >+ * This file is part of the X86 Disassembler. >+ * It contains the public interface of the instruction decoder. >+ * Documentation for the disassembler can be found in X86Disassembler.h. >+ * >+ *===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+#ifndef CS_X86_DISASSEMBLERDECODER_H >+#define CS_X86_DISASSEMBLERDECODER_H >+ >+#if defined(CAPSTONE_HAS_OSXKERNEL) >+#include <libkern/libkern.h> >+#else >+#include <stdio.h> >+#endif >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+#include "X86DisassemblerDecoderCommon.h" >+ >+/* >+ * Accessor functions for various fields of an Intel instruction >+ */ >+#define modFromModRM(modRM) (((modRM) & 0xc0) >> 6) >+#define regFromModRM(modRM) (((modRM) & 0x38) >> 3) >+#define rmFromModRM(modRM) ((modRM) & 0x7) >+#define scaleFromSIB(sib) (((sib) & 0xc0) >> 6) >+#define indexFromSIB(sib) (((sib) & 0x38) >> 3) >+#define baseFromSIB(sib) ((sib) & 0x7) >+#define wFromREX(rex) (((rex) & 0x8) >> 3) >+#define rFromREX(rex) (((rex) & 0x4) >> 2) >+#define xFromREX(rex) (((rex) & 0x2) >> 1) >+#define bFromREX(rex) ((rex) & 0x1) >+ >+#define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7) >+#define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6) >+#define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5) >+#define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4) >+#define mmFromEVEX2of4(evex) ((evex) & 0x3) >+#define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7) >+#define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3) >+#define ppFromEVEX3of4(evex) ((evex) & 0x3) >+#define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7) >+#define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6) >+#define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5) >+#define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4) >+#define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3) >+#define aaaFromEVEX4of4(evex) ((evex) & 0x7) >+ >+#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7) >+#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6) >+#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5) >+#define mmmmmFromVEX2of3(vex) ((vex) & 0x1f) >+#define wFromVEX3of3(vex) (((vex) & 0x80) >> 7) >+#define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3) >+#define lFromVEX3of3(vex) (((vex) & 0x4) >> 2) >+#define ppFromVEX3of3(vex) ((vex) & 0x3) >+ >+#define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7) >+#define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3) >+#define lFromVEX2of2(vex) (((vex) & 0x4) >> 2) >+#define ppFromVEX2of2(vex) ((vex) & 0x3) >+ >+#define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) >+#define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) >+#define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) >+#define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) >+#define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) >+#define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3) >+#define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) >+#define ppFromXOP3of3(xop) ((xop) & 0x3) >+ >+/* >+ * These enums represent Intel registers for use by the decoder. >+ */ >+ >+#define REGS_8BIT \ >+ ENTRY(AL) \ >+ ENTRY(CL) \ >+ ENTRY(DL) \ >+ ENTRY(BL) \ >+ ENTRY(AH) \ >+ ENTRY(CH) \ >+ ENTRY(DH) \ >+ ENTRY(BH) \ >+ ENTRY(R8B) \ >+ ENTRY(R9B) \ >+ ENTRY(R10B) \ >+ ENTRY(R11B) \ >+ ENTRY(R12B) \ >+ ENTRY(R13B) \ >+ ENTRY(R14B) \ >+ ENTRY(R15B) \ >+ ENTRY(SPL) \ >+ ENTRY(BPL) \ >+ ENTRY(SIL) \ >+ ENTRY(DIL) >+ >+#define EA_BASES_16BIT \ >+ ENTRY(BX_SI) \ >+ ENTRY(BX_DI) \ >+ ENTRY(BP_SI) \ >+ ENTRY(BP_DI) \ >+ ENTRY(SI) \ >+ ENTRY(DI) \ >+ ENTRY(BP) \ >+ ENTRY(BX) \ >+ ENTRY(R8W) \ >+ ENTRY(R9W) \ >+ ENTRY(R10W) \ >+ ENTRY(R11W) \ >+ ENTRY(R12W) \ >+ ENTRY(R13W) \ >+ ENTRY(R14W) \ >+ ENTRY(R15W) >+ >+#define REGS_16BIT \ >+ ENTRY(AX) \ >+ ENTRY(CX) \ >+ ENTRY(DX) \ >+ ENTRY(BX) \ >+ ENTRY(SP) \ >+ ENTRY(BP) \ >+ ENTRY(SI) \ >+ ENTRY(DI) \ >+ ENTRY(R8W) \ >+ ENTRY(R9W) \ >+ ENTRY(R10W) \ >+ ENTRY(R11W) \ >+ ENTRY(R12W) \ >+ ENTRY(R13W) \ >+ ENTRY(R14W) \ >+ ENTRY(R15W) >+ >+#define EA_BASES_32BIT \ >+ ENTRY(EAX) \ >+ ENTRY(ECX) \ >+ ENTRY(EDX) \ >+ ENTRY(EBX) \ >+ ENTRY(sib) \ >+ ENTRY(EBP) \ >+ ENTRY(ESI) \ >+ ENTRY(EDI) \ >+ ENTRY(R8D) \ >+ ENTRY(R9D) \ >+ ENTRY(R10D) \ >+ ENTRY(R11D) \ >+ ENTRY(R12D) \ >+ ENTRY(R13D) \ >+ ENTRY(R14D) \ >+ ENTRY(R15D) >+ >+#define REGS_32BIT \ >+ ENTRY(EAX) \ >+ ENTRY(ECX) \ >+ ENTRY(EDX) \ >+ ENTRY(EBX) \ >+ ENTRY(ESP) \ >+ ENTRY(EBP) \ >+ ENTRY(ESI) \ >+ ENTRY(EDI) \ >+ ENTRY(R8D) \ >+ ENTRY(R9D) \ >+ ENTRY(R10D) \ >+ ENTRY(R11D) \ >+ ENTRY(R12D) \ >+ ENTRY(R13D) \ >+ ENTRY(R14D) \ >+ ENTRY(R15D) >+ >+#define EA_BASES_64BIT \ >+ ENTRY(RAX) \ >+ ENTRY(RCX) \ >+ ENTRY(RDX) \ >+ ENTRY(RBX) \ >+ ENTRY(sib64) \ >+ ENTRY(RBP) \ >+ ENTRY(RSI) \ >+ ENTRY(RDI) \ >+ ENTRY(R8) \ >+ ENTRY(R9) \ >+ ENTRY(R10) \ >+ ENTRY(R11) \ >+ ENTRY(R12) \ >+ ENTRY(R13) \ >+ ENTRY(R14) \ >+ ENTRY(R15) >+ >+#define REGS_64BIT \ >+ ENTRY(RAX) \ >+ ENTRY(RCX) \ >+ ENTRY(RDX) \ >+ ENTRY(RBX) \ >+ ENTRY(RSP) \ >+ ENTRY(RBP) \ >+ ENTRY(RSI) \ >+ ENTRY(RDI) \ >+ ENTRY(R8) \ >+ ENTRY(R9) \ >+ ENTRY(R10) \ >+ ENTRY(R11) \ >+ ENTRY(R12) \ >+ ENTRY(R13) \ >+ ENTRY(R14) \ >+ ENTRY(R15) >+ >+#define REGS_MMX \ >+ ENTRY(MM0) \ >+ ENTRY(MM1) \ >+ ENTRY(MM2) \ >+ ENTRY(MM3) \ >+ ENTRY(MM4) \ >+ ENTRY(MM5) \ >+ ENTRY(MM6) \ >+ ENTRY(MM7) >+ >+#define REGS_XMM \ >+ ENTRY(XMM0) \ >+ ENTRY(XMM1) \ >+ ENTRY(XMM2) \ >+ ENTRY(XMM3) \ >+ ENTRY(XMM4) \ >+ ENTRY(XMM5) \ >+ ENTRY(XMM6) \ >+ ENTRY(XMM7) \ >+ ENTRY(XMM8) \ >+ ENTRY(XMM9) \ >+ ENTRY(XMM10) \ >+ ENTRY(XMM11) \ >+ ENTRY(XMM12) \ >+ ENTRY(XMM13) \ >+ ENTRY(XMM14) \ >+ ENTRY(XMM15) \ >+ ENTRY(XMM16) \ >+ ENTRY(XMM17) \ >+ ENTRY(XMM18) \ >+ ENTRY(XMM19) \ >+ ENTRY(XMM20) \ >+ ENTRY(XMM21) \ >+ ENTRY(XMM22) \ >+ ENTRY(XMM23) \ >+ ENTRY(XMM24) \ >+ ENTRY(XMM25) \ >+ ENTRY(XMM26) \ >+ ENTRY(XMM27) \ >+ ENTRY(XMM28) \ >+ ENTRY(XMM29) \ >+ ENTRY(XMM30) \ >+ ENTRY(XMM31) >+ >+ >+#define REGS_YMM \ >+ ENTRY(YMM0) \ >+ ENTRY(YMM1) \ >+ ENTRY(YMM2) \ >+ ENTRY(YMM3) \ >+ ENTRY(YMM4) \ >+ ENTRY(YMM5) \ >+ ENTRY(YMM6) \ >+ ENTRY(YMM7) \ >+ ENTRY(YMM8) \ >+ ENTRY(YMM9) \ >+ ENTRY(YMM10) \ >+ ENTRY(YMM11) \ >+ ENTRY(YMM12) \ >+ ENTRY(YMM13) \ >+ ENTRY(YMM14) \ >+ ENTRY(YMM15) \ >+ ENTRY(YMM16) \ >+ ENTRY(YMM17) \ >+ ENTRY(YMM18) \ >+ ENTRY(YMM19) \ >+ ENTRY(YMM20) \ >+ ENTRY(YMM21) \ >+ ENTRY(YMM22) \ >+ ENTRY(YMM23) \ >+ ENTRY(YMM24) \ >+ ENTRY(YMM25) \ >+ ENTRY(YMM26) \ >+ ENTRY(YMM27) \ >+ ENTRY(YMM28) \ >+ ENTRY(YMM29) \ >+ ENTRY(YMM30) \ >+ ENTRY(YMM31) >+ >+#define REGS_ZMM \ >+ ENTRY(ZMM0) \ >+ ENTRY(ZMM1) \ >+ ENTRY(ZMM2) \ >+ ENTRY(ZMM3) \ >+ ENTRY(ZMM4) \ >+ ENTRY(ZMM5) \ >+ ENTRY(ZMM6) \ >+ ENTRY(ZMM7) \ >+ ENTRY(ZMM8) \ >+ ENTRY(ZMM9) \ >+ ENTRY(ZMM10) \ >+ ENTRY(ZMM11) \ >+ ENTRY(ZMM12) \ >+ ENTRY(ZMM13) \ >+ ENTRY(ZMM14) \ >+ ENTRY(ZMM15) \ >+ ENTRY(ZMM16) \ >+ ENTRY(ZMM17) \ >+ ENTRY(ZMM18) \ >+ ENTRY(ZMM19) \ >+ ENTRY(ZMM20) \ >+ ENTRY(ZMM21) \ >+ ENTRY(ZMM22) \ >+ ENTRY(ZMM23) \ >+ ENTRY(ZMM24) \ >+ ENTRY(ZMM25) \ >+ ENTRY(ZMM26) \ >+ ENTRY(ZMM27) \ >+ ENTRY(ZMM28) \ >+ ENTRY(ZMM29) \ >+ ENTRY(ZMM30) \ >+ ENTRY(ZMM31) >+ >+#define REGS_MASKS \ >+ ENTRY(K0) \ >+ ENTRY(K1) \ >+ ENTRY(K2) \ >+ ENTRY(K3) \ >+ ENTRY(K4) \ >+ ENTRY(K5) \ >+ ENTRY(K6) \ >+ ENTRY(K7) >+ >+#define REGS_SEGMENT \ >+ ENTRY(ES) \ >+ ENTRY(CS) \ >+ ENTRY(SS) \ >+ ENTRY(DS) \ >+ ENTRY(FS) \ >+ ENTRY(GS) >+ >+#define REGS_DEBUG \ >+ ENTRY(DR0) \ >+ ENTRY(DR1) \ >+ ENTRY(DR2) \ >+ ENTRY(DR3) \ >+ ENTRY(DR4) \ >+ ENTRY(DR5) \ >+ ENTRY(DR6) \ >+ ENTRY(DR7) >+ >+#define REGS_CONTROL \ >+ ENTRY(CR0) \ >+ ENTRY(CR1) \ >+ ENTRY(CR2) \ >+ ENTRY(CR3) \ >+ ENTRY(CR4) \ >+ ENTRY(CR5) \ >+ ENTRY(CR6) \ >+ ENTRY(CR7) \ >+ ENTRY(CR8) \ >+ ENTRY(CR9) \ >+ ENTRY(CR10) \ >+ ENTRY(CR11) \ >+ ENTRY(CR12) \ >+ ENTRY(CR13) \ >+ ENTRY(CR14) \ >+ ENTRY(CR15) >+ >+#define ALL_EA_BASES \ >+ EA_BASES_16BIT \ >+ EA_BASES_32BIT \ >+ EA_BASES_64BIT >+ >+#define ALL_SIB_BASES \ >+ REGS_32BIT \ >+ REGS_64BIT >+ >+#define ALL_REGS \ >+ REGS_8BIT \ >+ REGS_16BIT \ >+ REGS_32BIT \ >+ REGS_64BIT \ >+ REGS_MMX \ >+ REGS_XMM \ >+ REGS_YMM \ >+ REGS_ZMM \ >+ REGS_MASKS \ >+ REGS_SEGMENT \ >+ REGS_DEBUG \ >+ REGS_CONTROL \ >+ ENTRY(RIP) >+ >+/* >+ * EABase - All possible values of the base field for effective-address >+ * computations, a.k.a. the Mod and R/M fields of the ModR/M byte. We >+ * distinguish between bases (EA_BASE_*) and registers that just happen to be >+ * referred to when Mod == 0b11 (EA_REG_*). >+ */ >+typedef enum { >+ EA_BASE_NONE, >+#define ENTRY(x) EA_BASE_##x, >+ ALL_EA_BASES >+#undef ENTRY >+#define ENTRY(x) EA_REG_##x, >+ ALL_REGS >+#undef ENTRY >+ EA_max >+} EABase; >+ >+/* >+ * SIBIndex - All possible values of the SIB index field. >+ * Borrows entries from ALL_EA_BASES with the special case that >+ * sib is synonymous with NONE. >+ * Vector SIB: index can be XMM or YMM. >+ */ >+typedef enum { >+ SIB_INDEX_NONE, >+#define ENTRY(x) SIB_INDEX_##x, >+ ALL_EA_BASES >+ REGS_XMM >+ REGS_YMM >+ REGS_ZMM >+#undef ENTRY >+ SIB_INDEX_max >+} SIBIndex; >+ >+/* >+ * SIBBase - All possible values of the SIB base field. >+ */ >+typedef enum { >+ SIB_BASE_NONE, >+#define ENTRY(x) SIB_BASE_##x, >+ ALL_SIB_BASES >+#undef ENTRY >+ SIB_BASE_max >+} SIBBase; >+ >+/* >+ * EADisplacement - Possible displacement types for effective-address >+ * computations. >+ */ >+typedef enum { >+ EA_DISP_NONE, >+ EA_DISP_8, >+ EA_DISP_16, >+ EA_DISP_32 >+} EADisplacement; >+ >+/* >+ * Reg - All possible values of the reg field in the ModR/M byte. >+ */ >+typedef enum { >+#define ENTRY(x) MODRM_REG_##x, >+ ALL_REGS >+#undef ENTRY >+ MODRM_REG_max >+} Reg; >+ >+/* >+ * SegmentOverride - All possible segment overrides. >+ */ >+typedef enum { >+ SEG_OVERRIDE_NONE, >+ SEG_OVERRIDE_CS, >+ SEG_OVERRIDE_SS, >+ SEG_OVERRIDE_DS, >+ SEG_OVERRIDE_ES, >+ SEG_OVERRIDE_FS, >+ SEG_OVERRIDE_GS, >+ SEG_OVERRIDE_max >+} SegmentOverride; >+ >+/* >+ * VEXLeadingOpcodeByte - Possible values for the VEX.m-mmmm field >+ */ >+typedef enum { >+ VEX_LOB_0F = 0x1, >+ VEX_LOB_0F38 = 0x2, >+ VEX_LOB_0F3A = 0x3 >+} VEXLeadingOpcodeByte; >+ >+typedef enum { >+ XOP_MAP_SELECT_8 = 0x8, >+ XOP_MAP_SELECT_9 = 0x9, >+ XOP_MAP_SELECT_A = 0xA >+} XOPMapSelect; >+ >+/* >+ * VEXPrefixCode - Possible values for the VEX.pp/EVEX.pp field >+ */ >+typedef enum { >+ VEX_PREFIX_NONE = 0x0, >+ VEX_PREFIX_66 = 0x1, >+ VEX_PREFIX_F3 = 0x2, >+ VEX_PREFIX_F2 = 0x3 >+} VEXPrefixCode; >+ >+typedef enum { >+ TYPE_NO_VEX_XOP = 0x0, >+ TYPE_VEX_2B = 0x1, >+ TYPE_VEX_3B = 0x2, >+ TYPE_EVEX = 0x3, >+ TYPE_XOP = 0x4 >+} VectorExtensionType; >+ >+struct reader_info { >+ const uint8_t *code; >+ uint64_t size; >+ uint64_t offset; >+}; >+ >+/* >+ * byteReader_t - Type for the byte reader that the consumer must provide to >+ * the decoder. Reads a single byte from the instruction's address space. >+ * @param arg - A baton that the consumer can associate with any internal >+ * state that it needs. >+ * @param byte - A pointer to a single byte in memory that should be set to >+ * contain the value at address. >+ * @param address - The address in the instruction's address space that should >+ * be read from. >+ * @return - -1 if the byte cannot be read for any reason; 0 otherwise. >+ */ >+typedef int (*byteReader_t)(const struct reader_info *arg, uint8_t* byte, uint64_t address); >+ >+/* >+ * dlog_t - Type for the logging function that the consumer can provide to >+ * get debugging output from the decoder. >+ * @param arg - A baton that the consumer can associate with any internal >+ * state that it needs. >+ * @param log - A string that contains the message. Will be reused after >+ * the logger returns. >+ */ >+typedef void (*dlog_t)(void* arg, const char *log); >+ >+/// The specification for how to extract and interpret a full instruction and >+/// its operands. >+struct InstructionSpecifier { >+ uint16_t operands; >+}; >+ >+/* >+ * The x86 internal instruction, which is produced by the decoder. >+ */ >+typedef struct InternalInstruction { >+ // from here, all members must be initialized to ZERO to work properly >+ uint8_t operandSize; >+ uint8_t prefix0, prefix1, prefix2, prefix3; >+ /* true if the prefix byte corresponding to the entry is present; false if not */ >+ bool isPrefix26; >+ bool isPrefix2e; >+ bool isPrefix36; >+ bool isPrefix3e; >+ bool isPrefix64; >+ bool isPrefix65; >+ bool isPrefix66; >+ bool isPrefix67; >+ bool isPrefixf0; >+ bool isPrefixf2; >+ bool isPrefixf3; >+ /* contains the location (for use with the reader) of the prefix byte */ >+ uint64_t prefix26; >+ uint64_t prefix2e; >+ uint64_t prefix36; >+ uint64_t prefix3e; >+ uint64_t prefix64; >+ uint64_t prefix65; >+ uint64_t prefix66; >+ uint64_t prefix67; >+ uint64_t prefixf0; >+ uint64_t prefixf2; >+ uint64_t prefixf3; >+ /* The value of the REX prefix, if present */ >+ uint8_t rexPrefix; >+ /* The segment override type */ >+ SegmentOverride segmentOverride; >+ bool consumedModRM; >+ uint8_t orgModRM; // save original modRM because we will modify modRM >+ /* The SIB byte, used for more complex 32- or 64-bit memory operands */ >+ bool consumedSIB; >+ uint8_t sib; >+ /* The displacement, used for memory operands */ >+ bool consumedDisplacement; >+ int32_t displacement; >+ /* The value of the two-byte escape prefix (usually 0x0f) */ >+ uint8_t twoByteEscape; >+ /* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */ >+ uint8_t threeByteEscape; >+ /* SIB state */ >+ SIBIndex sibIndex; >+ uint8_t sibScale; >+ SIBBase sibBase; >+ uint8_t numImmediatesConsumed; >+ /* true if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease */ >+ bool xAcquireRelease; >+ >+ /* The value of the vector extension prefix(EVEX/VEX/XOP), if present */ >+ uint8_t vectorExtensionPrefix[4]; >+ >+ // end-of-zero-members >+ >+ /* Reader interface (C) */ >+ byteReader_t reader; >+ >+ /* Opaque value passed to the reader */ >+ const void* readerArg; >+ /* The address of the next byte to read via the reader */ >+ uint64_t readerCursor; >+ >+ /* Logger interface (C) */ >+ dlog_t dlog; >+ /* Opaque value passed to the logger */ >+ void* dlogArg; >+ >+ /* General instruction information */ >+ >+ /* The mode to disassemble for (64-bit, protected, real) */ >+ DisassemblerMode mode; >+ /* The start of the instruction, usable with the reader */ >+ uint64_t startLocation; >+ /* The length of the instruction, in bytes */ >+ size_t length; >+ >+ /* Prefix state */ >+ >+ /* The type of the vector extension prefix */ >+ VectorExtensionType vectorExtensionType; >+ >+ /* The location where a mandatory prefix would have to be (i.e., right before >+ the opcode, or right before the REX prefix if one is present) */ >+ uint64_t necessaryPrefixLocation; >+ >+ /* Sizes of various critical pieces of data, in bytes */ >+ uint8_t registerSize; >+ uint8_t addressSize; >+ uint8_t displacementSize; >+ uint8_t immediateSize; >+ >+ uint8_t immSize; // immediate size for X86_OP_IMM operand >+ >+ /* Offsets from the start of the instruction to the pieces of data, which is >+ needed to find relocation entries for adding symbolic operands */ >+ uint8_t displacementOffset; >+ uint8_t immediateOffset; >+ >+ /* opcode state */ >+ >+ /* The last byte of the opcode, not counting any ModR/M extension */ >+ uint8_t opcode; >+ >+ /* decode state */ >+ >+ /* The type of opcode, used for indexing into the array of decode tables */ >+ OpcodeType opcodeType; >+ /* The instruction ID, extracted from the decode table */ >+ uint16_t instructionID; >+ /* The specifier for the instruction, from the instruction info table */ >+ const struct InstructionSpecifier *spec; >+ >+ /* state for additional bytes, consumed during operand decode. Pattern: >+ consumed___ indicates that the byte was already consumed and does not >+ need to be consumed again */ >+ >+ /* The VEX.vvvv field, which contains a third register operand for some AVX >+ instructions */ >+ Reg vvvv; >+ >+ /* The writemask for AVX-512 instructions which is contained in EVEX.aaa */ >+ Reg writemask; >+ >+ /* The ModR/M byte, which contains most register operands and some portion of >+ all memory operands */ >+ uint8_t modRM; >+ >+ // special data to handle MOVcr, MOVdr, MOVrc, MOVrd >+ uint8_t firstByte; // save the first byte in stream >+ >+ /* Immediates. There can be two in some cases */ >+ uint8_t numImmediatesTranslated; >+ uint64_t immediates[2]; >+ >+ /* A register or immediate operand encoded into the opcode */ >+ Reg opcodeRegister; >+ >+ /* Portions of the ModR/M byte */ >+ >+ /* These fields determine the allowable values for the ModR/M fields, which >+ depend on operand and address widths */ >+ EABase eaBaseBase; >+ EABase eaRegBase; >+ Reg regBase; >+ >+ /* The Mod and R/M fields can encode a base for an effective address, or a >+ register. These are separated into two fields here */ >+ EABase eaBase; >+ EADisplacement eaDisplacement; >+ /* The reg field always encodes a register */ >+ Reg reg; >+ >+ const struct OperandSpecifier *operands; >+} InternalInstruction; >+ >+/* decodeInstruction - Decode one instruction and store the decoding results in >+ * a buffer provided by the consumer. >+ * @param insn - The buffer to store the instruction in. Allocated by the >+ * consumer. >+ * @param reader - The byteReader_t for the bytes to be read. >+ * @param readerArg - An argument to pass to the reader for storing context >+ * specific to the consumer. May be NULL. >+ * @param logger - The dlog_t to be used in printing status messages from the >+ * disassembler. May be NULL. >+ * @param loggerArg - An argument to pass to the logger for storing context >+ * specific to the logger. May be NULL. >+ * @param startLoc - The address (in the reader's address space) of the first >+ * byte in the instruction. >+ * @param mode - The mode (16-bit, 32-bit, 64-bit) to decode in. >+ * @return - Nonzero if there was an error during decode, 0 otherwise. >+ */ >+int decodeInstruction(struct InternalInstruction* insn, >+ byteReader_t reader, >+ const void* readerArg, >+ uint64_t startLoc, >+ DisassemblerMode mode); >+ >+//const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii); >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoderCommon.h b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoderCommon.h >new file mode 100644 >index 0000000000000000000000000000000000000000..62effdc54da53992340103ae25f7dfa7f8a1674c >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86DisassemblerDecoderCommon.h >@@ -0,0 +1,538 @@ >+/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===* >+ * >+ * The LLVM Compiler Infrastructure >+ * >+ * This file is distributed under the University of Illinois Open Source >+ * License. See LICENSE.TXT for details. >+ * >+ *===----------------------------------------------------------------------===* >+ * >+ * This file is part of the X86 Disassembler. >+ * It contains common definitions used by both the disassembler and the table >+ * generator. >+ * Documentation for the disassembler can be found in X86Disassembler.h. >+ * >+ *===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+/* >+ * This header file provides those definitions that need to be shared between >+ * the decoder and the table generator in a C-friendly manner. >+ */ >+ >+#ifndef CS_X86_DISASSEMBLERDECODERCOMMON_H >+#define CS_X86_DISASSEMBLERDECODERCOMMON_H >+ >+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE) >+#include <stdint.h> >+#endif >+ >+#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers >+#define CONTEXTS_SYM x86DisassemblerContexts >+#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes >+#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes >+#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes >+#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes >+#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes >+#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes >+#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes >+#define T3DNOW_MAP_SYM x86DisassemblerT3DNOWOpcodes >+ >+ >+/* >+ * Attributes of an instruction that must be known before the opcode can be >+ * processed correctly. Most of these indicate the presence of particular >+ * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. >+ */ >+#define ATTRIBUTE_BITS \ >+ ENUM_ENTRY(ATTR_NONE, 0x00) \ >+ ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ >+ ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ >+ ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ >+ ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ >+ ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ >+ ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ >+ ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ >+ ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ >+ ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ >+ ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ >+ ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ >+ ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ >+ ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ >+ ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) >+ >+#define ENUM_ENTRY(n, v) n = v, >+enum attributeBits { >+ ATTRIBUTE_BITS >+ ATTR_max >+}; >+#undef ENUM_ENTRY >+ >+/* >+ * Combinations of the above attributes that are relevant to instruction >+ * decode. Although other combinations are possible, they can be reduced to >+ * these without affecting the ultimately decoded instruction. >+ */ >+ >+/* Class name Rank Rationale for rank assignment */ >+#define INSTRUCTION_CONTEXTS \ >+ ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ >+ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ >+ "64-bit mode but no more") \ >+ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ >+ "operands change width") \ >+ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ >+ "operands change width") \ >+ENUM_ENTRY(IC_OF, 2, "requires 0x0F prefix") \ >+ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ >+ "but not the operands") \ >+ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ >+ "but not the operands") \ >+ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ >+ "operands change width") \ >+ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ >+ "operands change width") \ >+ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\ >+ "change width; overrides IC_OPSIZE") \ >+ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ >+ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ >+ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \ >+ "secondary") \ >+ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \ >+ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ >+ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ >+ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \ >+ "opcode") \ >+ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \ >+ "IC_64BIT_REXW_XS") \ >+ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \ >+ "else because this changes most " \ >+ "operands' meaning") \ >+ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ >+ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ >+ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ >+ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ >+ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ >+ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ >+ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ >+ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ >+ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ >+ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ >+ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ >+ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ >+ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ >+ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ >+ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ >+ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ >+ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ >+ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ >+ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ >+ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ >+ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ >+ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ >+ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ >+ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ >+ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ >+ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ >+ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ >+ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ >+ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ >+ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") >+ >+#define ENUM_ENTRY(n, r, d) n, >+typedef enum { >+ INSTRUCTION_CONTEXTS >+ IC_max >+} InstructionContext; >+#undef ENUM_ENTRY >+ >+/* >+ * Opcode types, which determine which decode table to use, both in the Intel >+ * manual and also for the decoder. >+ */ >+typedef enum { >+ ONEBYTE = 0, >+ TWOBYTE = 1, >+ THREEBYTE_38 = 2, >+ THREEBYTE_3A = 3, >+ XOP8_MAP = 4, >+ XOP9_MAP = 5, >+ XOPA_MAP = 6, >+ T3DNOW_MAP = 7 >+} OpcodeType; >+ >+/* >+ * The following structs are used for the hierarchical decode table. After >+ * determining the instruction's class (i.e., which IC_* constant applies to >+ * it), the decoder reads the opcode. Some instructions require specific >+ * values of the ModR/M byte, so the ModR/M byte indexes into the final table. >+ * >+ * If a ModR/M byte is not required, "required" is left unset, and the values >+ * for each instructionID are identical. >+ */ >+ >+typedef uint16_t InstrUID; >+ >+/* >+ * ModRMDecisionType - describes the type of ModR/M decision, allowing the >+ * consumer to determine the number of entries in it. >+ * >+ * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded >+ * instruction is the same. >+ * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode >+ * corresponds to one instruction; otherwise, it corresponds to >+ * a different instruction. >+ * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte >+ * divided by 8 is used to select instruction; otherwise, each >+ * value of the ModR/M byte could correspond to a different >+ * instruction. >+ * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This >+ corresponds to instructions that use reg field as opcode >+ * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond >+ * to a different instruction. >+ */ >+ >+#define MODRMTYPES \ >+ ENUM_ENTRY(MODRM_ONEENTRY) \ >+ENUM_ENTRY(MODRM_SPLITRM) \ >+ENUM_ENTRY(MODRM_SPLITMISC) \ >+ENUM_ENTRY(MODRM_SPLITREG) \ >+ENUM_ENTRY(MODRM_FULL) >+ >+#define ENUM_ENTRY(n) n, >+typedef enum { >+ MODRMTYPES >+ MODRM_max >+} ModRMDecisionType; >+#undef ENUM_ENTRY >+ >+#define CASE_ENCODING_RM \ >+ case ENCODING_RM: \ >+ case ENCODING_RM_CD2: \ >+ case ENCODING_RM_CD4: \ >+ case ENCODING_RM_CD8: \ >+ case ENCODING_RM_CD16: \ >+ case ENCODING_RM_CD32: \ >+ case ENCODING_RM_CD64 >+ >+// Physical encodings of instruction operands. >+ >+#define ENCODINGS \ >+ENUM_ENTRY(ENCODING_NONE, "") \ >+ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ >+ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ >+ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ >+ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ >+ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ >+ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ >+ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ >+ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ >+ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ >+ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ >+ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \ >+ENUM_ENTRY(ENCODING_CW, "2-byte") \ >+ENUM_ENTRY(ENCODING_CD, "4-byte") \ >+ENUM_ENTRY(ENCODING_CP, "6-byte") \ >+ENUM_ENTRY(ENCODING_CO, "8-byte") \ >+ENUM_ENTRY(ENCODING_CT, "10-byte") \ >+ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ >+ENUM_ENTRY(ENCODING_IW, "2-byte") \ >+ENUM_ENTRY(ENCODING_ID, "4-byte") \ >+ENUM_ENTRY(ENCODING_IO, "8-byte") \ >+ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ >+ "the opcode byte") \ >+ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ >+ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ >+ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ >+ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ >+ "byte.") \ >+ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ >+ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ >+ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ >+ "opcode byte") \ >+ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ >+ "in type") \ >+ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ >+ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") >+ >+#define ENUM_ENTRY(n, d) n, >+typedef enum { >+ ENCODINGS >+ ENCODING_max >+} OperandEncoding; >+#undef ENUM_ENTRY >+ >+/* >+ * Semantic interpretations of instruction operands. >+ */ >+ >+#define TYPES \ >+ENUM_ENTRY(TYPE_NONE, "") \ >+ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \ >+ENUM_ENTRY(TYPE_REL16, "2-byte") \ >+ENUM_ENTRY(TYPE_REL32, "4-byte") \ >+ENUM_ENTRY(TYPE_REL64, "8-byte") \ >+ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ >+ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ >+ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ >+ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ >+ENUM_ENTRY(TYPE_R16, "2-byte") \ >+ENUM_ENTRY(TYPE_R32, "4-byte") \ >+ENUM_ENTRY(TYPE_R64, "8-byte") \ >+ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ >+ENUM_ENTRY(TYPE_IMM16, "2-byte") \ >+ENUM_ENTRY(TYPE_IMM32, "4-byte") \ >+ENUM_ENTRY(TYPE_IMM64, "8-byte") \ >+ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ >+ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ >+ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ >+ENUM_ENTRY(TYPE_RM16, "2-byte") \ >+ENUM_ENTRY(TYPE_RM32, "4-byte") \ >+ENUM_ENTRY(TYPE_RM64, "8-byte") \ >+ENUM_ENTRY(TYPE_M, "Memory operand") \ >+ENUM_ENTRY(TYPE_M8, "1-byte") \ >+ENUM_ENTRY(TYPE_M16, "2-byte") \ >+ENUM_ENTRY(TYPE_M32, "4-byte") \ >+ENUM_ENTRY(TYPE_M64, "8-byte") \ >+ENUM_ENTRY(TYPE_LEA, "Effective address") \ >+ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ >+ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ >+ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ >+ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ >+ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ >+ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \ >+ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \ >+ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \ >+ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \ >+ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \ >+ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \ >+ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \ >+ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \ >+ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \ >+ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \ >+ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \ >+ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \ >+ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ >+ "base)") \ >+ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ >+ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ >+ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ >+ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \ >+ "2 = SS, 3 = DS, 4 = FS, 5 = GS") \ >+ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ >+ENUM_ENTRY(TYPE_M64FP, "64-bit") \ >+ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ >+ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \ >+ "floating-point instructions") \ >+ENUM_ENTRY(TYPE_M32INT, "4-byte") \ >+ENUM_ENTRY(TYPE_M64INT, "8-byte") \ >+ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ >+ENUM_ENTRY(TYPE_MM, "MMX register operand") \ >+ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \ >+ENUM_ENTRY(TYPE_MM64, "8-byte") \ >+ENUM_ENTRY(TYPE_XMM, "XMM register operand") \ >+ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ >+ENUM_ENTRY(TYPE_XMM64, "8-byte") \ >+ENUM_ENTRY(TYPE_XMM128, "16-byte") \ >+ENUM_ENTRY(TYPE_XMM256, "32-byte") \ >+ENUM_ENTRY(TYPE_XMM512, "64-byte") \ >+ENUM_ENTRY(TYPE_VK1, "1-bit") \ >+ENUM_ENTRY(TYPE_VK2, "2-bit") \ >+ENUM_ENTRY(TYPE_VK4, "4-bit") \ >+ENUM_ENTRY(TYPE_VK8, "8-bit") \ >+ENUM_ENTRY(TYPE_VK16, "16-bit") \ >+ENUM_ENTRY(TYPE_VK32, "32-bit") \ >+ENUM_ENTRY(TYPE_VK64, "64-bit") \ >+ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \ >+ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ >+ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ >+ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ >+\ >+ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ >+ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ >+ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ >+ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ >+ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ >+ENUM_ENTRY(TYPE_DUP1, "operand 1") \ >+ENUM_ENTRY(TYPE_DUP2, "operand 2") \ >+ENUM_ENTRY(TYPE_DUP3, "operand 3") \ >+ENUM_ENTRY(TYPE_DUP4, "operand 4") \ >+ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") >+ >+#define ENUM_ENTRY(n, d) n, >+typedef enum { >+ TYPES >+ TYPE_max >+} OperandType; >+#undef ENUM_ENTRY >+ >+/* >+ * OperandSpecifier - The specification for how to extract and interpret one >+ * operand. >+ */ >+typedef struct OperandSpecifier { >+ uint8_t encoding; >+ uint8_t type; >+} OperandSpecifier; >+ >+/* >+ * Indicates where the opcode modifier (if any) is to be found. Extended >+ * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte. >+ */ >+ >+#define MODIFIER_TYPES \ >+ ENUM_ENTRY(MODIFIER_NONE) >+ >+#define ENUM_ENTRY(n) n, >+typedef enum { >+ MODIFIER_TYPES >+ MODIFIER_max >+} ModifierType; >+#undef ENUM_ENTRY >+ >+#define X86_MAX_OPERANDS 5 >+ >+/* >+ * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode >+ * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, >+ * respectively. >+ */ >+typedef enum { >+ MODE_16BIT, >+ MODE_32BIT, >+ MODE_64BIT >+} DisassemblerMode; >+ >+#endif >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter.inc b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..cc3661612c62c34bc9ab963a638a3763328ee879 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter.inc >@@ -0,0 +1,15727 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 14036U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 14029U, // BUNDLE >+ 14101U, // LIFETIME_START >+ 14016U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 14116U, // AAA >+ 20679U, // AAD8i8 >+ 23816U, // AAM8i8 >+ 14857U, // AAS >+ 14865U, // ABS_F >+ 0U, // ABS_Fp32 >+ 0U, // ABS_Fp64 >+ 0U, // ABS_Fp80 >+ 13680U, // ACQUIRE_MOV16rm >+ 13680U, // ACQUIRE_MOV32rm >+ 13680U, // ACQUIRE_MOV64rm >+ 13680U, // ACQUIRE_MOV8rm >+ 2124421U, // ADC16i16 >+ 4237957U, // ADC16mi >+ 4237957U, // ADC16mi8 >+ 4237957U, // ADC16mr >+ 6351493U, // ADC16ri >+ 6351493U, // ADC16ri8 >+ 6367877U, // ADC16rm >+ 6351493U, // ADC16rr >+ 8448645U, // ADC16rr_REV >+ 10508565U, // ADC32i32 >+ 12622101U, // ADC32mi >+ 12622101U, // ADC32mi8 >+ 12622101U, // ADC32mr >+ 6347029U, // ADC32ri >+ 6347029U, // ADC32ri8 >+ 283203861U, // ADC32rm >+ 6347029U, // ADC32rr >+ 8444181U, // ADC32rr_REV >+ 16801419U, // ADC64i32 >+ 18914955U, // ADC64mi32 >+ 18914955U, // ADC64mi8 >+ 18914955U, // ADC64mr >+ 6348427U, // ADC64ri32 >+ 6348427U, // ADC64ri8 >+ 283221643U, // ADC64rm >+ 6348427U, // ADC64rr >+ 8445579U, // ADC64rr_REV >+ 20991661U, // ADC8i8 >+ 23105197U, // ADC8mi >+ 23105197U, // ADC8mr >+ 6344365U, // ADC8ri >+ 118445U, // ADC8rm >+ 6344365U, // ADC8rr >+ 8441517U, // ADC8rr_REV >+ 551640279U, // ADCX32rm >+ 8445143U, // ADCX32rr >+ 551658286U, // ADCX64rm >+ 8446766U, // ADCX64rr >+ 2124463U, // ADD16i16 >+ 4237999U, // ADD16mi >+ 4237999U, // ADD16mi8 >+ 4237999U, // ADD16mr >+ 6351535U, // ADD16ri >+ 6351535U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 6367919U, // ADD16rm >+ 6351535U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 8448687U, // ADD16rr_REV >+ 10508599U, // ADD32i32 >+ 12622135U, // ADD32mi >+ 12622135U, // ADD32mi8 >+ 12622135U, // ADD32mr >+ 6347063U, // ADD32ri >+ 6347063U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 283203895U, // ADD32rm >+ 6347063U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 8444215U, // ADD32rr_REV >+ 16801519U, // ADD64i32 >+ 18915055U, // ADD64mi32 >+ 18915055U, // ADD64mi8 >+ 18915055U, // ADD64mr >+ 6348527U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 6348527U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 283221743U, // ADD64rm >+ 6348527U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 8445679U, // ADD64rr_REV >+ 20991681U, // ADD8i8 >+ 23105217U, // ADD8mi >+ 23105217U, // ADD8mr >+ 6344385U, // ADD8ri >+ 6344385U, // ADD8ri8 >+ 118465U, // ADD8rm >+ 6344385U, // ADD8rr >+ 8441537U, // ADD8rr_REV >+ 8524643U, // ADDPDrm >+ 8442723U, // ADDPDrr >+ 8529324U, // ADDPSrm >+ 8447404U, // ADDPSrr >+ 551703973U, // ADDSDrm >+ 551703973U, // ADDSDrm_Int >+ 8443301U, // ADDSDrr >+ 8443301U, // ADDSDrr_Int >+ 551725118U, // ADDSSrm >+ 551725118U, // ADDSSrm_Int >+ 8448062U, // ADDSSrr >+ 8448062U, // ADDSSrr_Int >+ 8524578U, // ADDSUBPDrm >+ 8442658U, // ADDSUBPDrr >+ 8529259U, // ADDSUBPSrm >+ 8447339U, // ADDSUBPSrr >+ 189404U, // ADD_F32m >+ 203062U, // ADD_F64m >+ 222179U, // ADD_FI16m >+ 235837U, // ADD_FI32m >+ 23932U, // ADD_FPrST0 >+ 20761U, // ADD_FST0r >+ 0U, // ADD_Fp32 >+ 0U, // ADD_Fp32m >+ 0U, // ADD_Fp64 >+ 0U, // ADD_Fp64m >+ 0U, // ADD_Fp64m32 >+ 0U, // ADD_Fp80 >+ 0U, // ADD_Fp80m32 >+ 0U, // ADD_Fp80m64 >+ 0U, // ADD_FpI16m32 >+ 0U, // ADD_FpI16m64 >+ 0U, // ADD_FpI16m80 >+ 0U, // ADD_FpI32m32 >+ 0U, // ADD_FpI32m64 >+ 0U, // ADD_FpI32m80 >+ 28362U, // ADD_FrST0 >+ 14055U, // ADJCALLSTACKDOWN32 >+ 14055U, // ADJCALLSTACKDOWN64 >+ 14073U, // ADJCALLSTACKUP32 >+ 14073U, // ADJCALLSTACKUP64 >+ 551804140U, // ADOX32rm >+ 551820524U, // ADOX32rr >+ 551838531U, // ADOX64rm >+ 551822147U, // ADOX64rr >+ 8694081U, // AESDECLASTrm >+ 8448321U, // AESDECLASTrr >+ 8687767U, // AESDECrm >+ 8442007U, // AESDECrr >+ 8694094U, // AESENCLASTrm >+ 8448334U, // AESENCLASTrr >+ 8687807U, // AESENCrm >+ 8442047U, // AESENCrr >+ 315574U, // AESIMCrm >+ 551817398U, // AESIMCrr >+ 25504104U, // AESKEYGENASSIST128rm >+ 811657576U, // AESKEYGENASSIST128rr >+ 2124503U, // AND16i16 >+ 4238039U, // AND16mi >+ 4238039U, // AND16mi8 >+ 4238039U, // AND16mr >+ 6351575U, // AND16ri >+ 6351575U, // AND16ri8 >+ 6367959U, // AND16rm >+ 6351575U, // AND16rr >+ 8448727U, // AND16rr_REV >+ 10508652U, // AND32i32 >+ 12622188U, // AND32mi >+ 12622188U, // AND32mi8 >+ 12622188U, // AND32mr >+ 6347116U, // AND32ri >+ 6347116U, // AND32ri8 >+ 283203948U, // AND32rm >+ 6347116U, // AND32rr >+ 8444268U, // AND32rr_REV >+ 16801612U, // AND64i32 >+ 18915148U, // AND64mi32 >+ 18915148U, // AND64mi8 >+ 18915148U, // AND64mr >+ 6348620U, // AND64ri32 >+ 6348620U, // AND64ri8 >+ 283221836U, // AND64rm >+ 6348620U, // AND64rr >+ 8445772U, // AND64rr_REV >+ 20991694U, // AND8i8 >+ 23105230U, // AND8mi >+ 23105230U, // AND8mr >+ 6344398U, // AND8ri >+ 6344398U, // AND8ri8 >+ 118478U, // AND8rm >+ 6344398U, // AND8rr >+ 8441550U, // AND8rr_REV >+ 283204287U, // ANDN32rm >+ 811653823U, // ANDN32rr >+ 283222265U, // ANDN64rm >+ 811655417U, // ANDN64rr >+ 8524825U, // ANDNPDrm >+ 8442905U, // ANDNPDrr >+ 8529535U, // ANDNPSrm >+ 8447615U, // ANDNPSrr >+ 8524689U, // ANDPDrm >+ 8442769U, // ANDPDrr >+ 8529370U, // ANDPSrm >+ 8447450U, // ANDPSrr >+ 4234014U, // ARPL16mr >+ 551820062U, // ARPL16rr >+ 0U, // AVX2_SETALLONES >+ 0U, // AVX512_512_SET0 >+ 0U, // AVX_SET0 >+ 832904105U, // BEXTR32rm >+ 811654057U, // BEXTR32rr >+ 835002789U, // BEXTR64rm >+ 811655589U, // BEXTR64rr >+ 832906169U, // BEXTRI32mi >+ 811656121U, // BEXTRI32ri >+ 835003321U, // BEXTRI64mi >+ 811656121U, // BEXTRI64ri >+ 551803488U, // BLCFILL32rm >+ 551819872U, // BLCFILL32rr >+ 551836256U, // BLCFILL64rm >+ 551819872U, // BLCFILL64rr >+ 551802925U, // BLCI32rm >+ 551819309U, // BLCI32rr >+ 551835693U, // BLCI64rm >+ 551819309U, // BLCI64rr >+ 551800991U, // BLCIC32rm >+ 551817375U, // BLCIC32rr >+ 551833759U, // BLCIC64rm >+ 551817375U, // BLCIC64rr >+ 551803075U, // BLCMSK32rm >+ 551819459U, // BLCMSK32rr >+ 551835843U, // BLCMSK64rm >+ 551819459U, // BLCMSK64rr >+ 551805910U, // BLCS32rm >+ 551822294U, // BLCS32rr >+ 551838678U, // BLCS64rm >+ 551822294U, // BLCS64rr >+ 568677273U, // BLENDPDrmi >+ 570790809U, // BLENDPDrri >+ 568681954U, // BLENDPSrmi >+ 570795490U, // BLENDPSrri >+ 8524921U, // BLENDVPDrm0 >+ 8443001U, // BLENDVPDrr0 >+ 8529696U, // BLENDVPSrm0 >+ 8447776U, // BLENDVPSrr0 >+ 551803497U, // BLSFILL32rm >+ 551819881U, // BLSFILL32rr >+ 551836265U, // BLSFILL64rm >+ 551819881U, // BLSFILL64rr >+ 551803433U, // BLSI32rm >+ 551819817U, // BLSI32rr >+ 551837826U, // BLSI64rm >+ 551821442U, // BLSI64rr >+ 551800998U, // BLSIC32rm >+ 551817382U, // BLSIC32rr >+ 551833766U, // BLSIC64rm >+ 551817382U, // BLSIC64rr >+ 551803453U, // BLSMSK32rm >+ 551819837U, // BLSMSK32rr >+ 551837842U, // BLSMSK64rm >+ 551821458U, // BLSMSK64rr >+ 551803798U, // BLSR32rm >+ 551820182U, // BLSR32rr >+ 551838089U, // BLSR64rm >+ 551821705U, // BLSR64rr >+ 551801305U, // BOUNDS16rm >+ 551834073U, // BOUNDS32rm >+ 387904U, // BSF16rm >+ 551824192U, // BSF16rr >+ 551803389U, // BSF32rm >+ 551819773U, // BSF32rr >+ 551837782U, // BSF64rm >+ 551821398U, // BSF64rr >+ 388226U, // BSR16rm >+ 551824514U, // BSR16rr >+ 551803792U, // BSR32rm >+ 551820176U, // BSR32rr >+ 551838083U, // BSR64rm >+ 551821699U, // BSR64rr >+ 23260U, // BSWAP32r >+ 24849U, // BSWAP64r >+ 4238713U, // BT16mi8 >+ 4238713U, // BT16mr >+ 551824761U, // BT16ri8 >+ 551824761U, // BT16rr >+ 12622901U, // BT32mi8 >+ 12622901U, // BT32mr >+ 551820341U, // BT32ri8 >+ 551820341U, // BT32rr >+ 18915862U, // BT64mi8 >+ 18915862U, // BT64mr >+ 551821846U, // BT64ri8 >+ 551821846U, // BT64rr >+ 4237982U, // BTC16mi8 >+ 4237982U, // BTC16mr >+ 551824030U, // BTC16ri8 >+ 551824030U, // BTC16rr >+ 12622119U, // BTC32mi8 >+ 12622119U, // BTC32mr >+ 551819559U, // BTC32ri8 >+ 551819559U, // BTC32rr >+ 18914973U, // BTC64mi8 >+ 18914973U, // BTC64mr >+ 551820957U, // BTC64ri8 >+ 551820957U, // BTC64rr >+ 4238481U, // BTR16mi8 >+ 4238481U, // BTR16mr >+ 551824529U, // BTR16ri8 >+ 551824529U, // BTR16rr >+ 12622749U, // BTR32mi8 >+ 12622749U, // BTR32mr >+ 551820189U, // BTR32ri8 >+ 551820189U, // BTR32rr >+ 18915737U, // BTR64mi8 >+ 18915737U, // BTR64mr >+ 551821721U, // BTR64ri8 >+ 551821721U, // BTR64rr >+ 4238655U, // BTS16mi8 >+ 4238655U, // BTS16mr >+ 551824703U, // BTS16ri8 >+ 551824703U, // BTS16rr >+ 12622880U, // BTS32mi8 >+ 12622880U, // BTS32mr >+ 551820320U, // BTS32ri8 >+ 551820320U, // BTS32rr >+ 18915848U, // BTS64mi8 >+ 18915848U, // BTS64mr >+ 551821832U, // BTS64ri8 >+ 551821832U, // BTS64rr >+ 832903714U, // BZHI32rm >+ 811653666U, // BZHI32rr >+ 835002491U, // BZHI64rm >+ 811655291U, // BZHI64rr >+ 226749U, // CALL16m >+ 30141U, // CALL16r >+ 243099U, // CALL32m >+ 30107U, // CALL32r >+ 406956U, // CALL64m >+ 417967U, // CALL64pcrel32 >+ 30124U, // CALL64r >+ 420793U, // CALLpcrel16 >+ 416371U, // CALLpcrel32 >+ 15328U, // CBW >+ 14263U, // CDQ >+ 14802U, // CDQE >+ 15087U, // CHS_F >+ 0U, // CHS_Fp32 >+ 0U, // CHS_Fp64 >+ 0U, // CHS_Fp80 >+ 14185U, // CLAC >+ 14217U, // CLC >+ 14254U, // CLD >+ 432164U, // CLFLUSH >+ 14428U, // CLGI >+ 14438U, // CLI >+ 15200U, // CLTS >+ 14221U, // CMC >+ 8464878U, // CMOVA16rm >+ 8448494U, // CMOVA16rr >+ 551639264U, // CMOVA32rm >+ 8444128U, // CMOVA32rr >+ 551657010U, // CMOVA64rm >+ 8445490U, // CMOVA64rr >+ 8465156U, // CMOVAE16rm >+ 8448772U, // CMOVAE16rr >+ 551639442U, // CMOVAE32rm >+ 8444306U, // CMOVAE32rr >+ 551657433U, // CMOVAE64rm >+ 8445913U, // CMOVAE64rr >+ 8464991U, // CMOVB16rm >+ 8448607U, // CMOVB16rr >+ 551639301U, // CMOVB32rm >+ 8444165U, // CMOVB32rr >+ 551657061U, // CMOVB64rm >+ 8445541U, // CMOVB64rr >+ 8465165U, // CMOVBE16rm >+ 8448781U, // CMOVBE16rr >+ 551639451U, // CMOVBE32rm >+ 8444315U, // CMOVBE32rr >+ 551657442U, // CMOVBE64rm >+ 8445922U, // CMOVBE64rr >+ 35673950U, // CMOVBE_F >+ 0U, // CMOVBE_Fp32 >+ 0U, // CMOVBE_Fp64 >+ 0U, // CMOVBE_Fp80 >+ 35672160U, // CMOVB_F >+ 0U, // CMOVB_Fp32 >+ 0U, // CMOVB_Fp64 >+ 0U, // CMOVB_Fp80 >+ 8465201U, // CMOVE16rm >+ 8448817U, // CMOVE16rr >+ 551639541U, // CMOVE32rm >+ 8444405U, // CMOVE32rr >+ 551657550U, // CMOVE64rm >+ 8446030U, // CMOVE64rr >+ 35674072U, // CMOVE_F >+ 0U, // CMOVE_Fp32 >+ 0U, // CMOVE_Fp64 >+ 0U, // CMOVE_Fp80 >+ 8465254U, // CMOVG16rm >+ 8448870U, // CMOVG16rr >+ 551639571U, // CMOVG32rm >+ 8444435U, // CMOVG32rr >+ 551657580U, // CMOVG64rm >+ 8446060U, // CMOVG64rr >+ 8465174U, // CMOVGE16rm >+ 8448790U, // CMOVGE16rr >+ 551639460U, // CMOVGE32rm >+ 8444324U, // CMOVGE32rr >+ 551657451U, // CMOVGE64rm >+ 8445931U, // CMOVGE64rr >+ 8465388U, // CMOVL16rm >+ 8449004U, // CMOVL16rr >+ 551639720U, // CMOVL32rm >+ 8444584U, // CMOVL32rr >+ 551657697U, // CMOVL64rm >+ 8446177U, // CMOVL64rr >+ 8465183U, // CMOVLE16rm >+ 8448799U, // CMOVLE16rr >+ 551639469U, // CMOVLE32rm >+ 8444333U, // CMOVLE32rr >+ 551657460U, // CMOVLE64rm >+ 8445940U, // CMOVLE64rr >+ 35673933U, // CMOVNBE_F >+ 0U, // CMOVNBE_Fp32 >+ 0U, // CMOVNBE_Fp64 >+ 0U, // CMOVNBE_Fp80 >+ 35671867U, // CMOVNB_F >+ 0U, // CMOVNB_Fp32 >+ 0U, // CMOVNB_Fp64 >+ 0U, // CMOVNB_Fp80 >+ 8465192U, // CMOVNE16rm >+ 8448808U, // CMOVNE16rr >+ 551639478U, // CMOVNE32rm >+ 8444342U, // CMOVNE32rr >+ 551657469U, // CMOVNE64rm >+ 8445949U, // CMOVNE64rr >+ 35674023U, // CMOVNE_F >+ 0U, // CMOVNE_Fp32 >+ 0U, // CMOVNE_Fp64 >+ 0U, // CMOVNE_Fp80 >+ 8465418U, // CMOVNO16rm >+ 8449034U, // CMOVNO16rr >+ 551639755U, // CMOVNO32rm >+ 8444619U, // CMOVNO32rr >+ 551657728U, // CMOVNO64rm >+ 8446208U, // CMOVNO64rr >+ 8465448U, // CMOVNP16rm >+ 8449064U, // CMOVNP16rr >+ 551639817U, // CMOVNP32rm >+ 8444681U, // CMOVNP32rr >+ 551657768U, // CMOVNP64rm >+ 8446248U, // CMOVNP64rr >+ 35678594U, // CMOVNP_F >+ 0U, // CMOVNP_Fp32 >+ 0U, // CMOVNP_Fp64 >+ 0U, // CMOVNP_Fp80 >+ 8465694U, // CMOVNS16rm >+ 8449310U, // CMOVNS16rr >+ 551640049U, // CMOVNS32rm >+ 8444913U, // CMOVNS32rr >+ 551657945U, // CMOVNS64rm >+ 8446425U, // CMOVNS64rr >+ 8465427U, // CMOVO16rm >+ 8449043U, // CMOVO16rr >+ 551639764U, // CMOVO32rm >+ 8444628U, // CMOVO32rr >+ 551657737U, // CMOVO64rm >+ 8446217U, // CMOVO64rr >+ 8465469U, // CMOVP16rm >+ 8449085U, // CMOVP16rr >+ 551639868U, // CMOVP32rm >+ 8444732U, // CMOVP32rr >+ 551657783U, // CMOVP64rm >+ 8446263U, // CMOVP64rr >+ 35678633U, // CMOVP_F >+ 0U, // CMOVP_Fp32 >+ 0U, // CMOVP_Fp64 >+ 0U, // CMOVP_Fp80 >+ 8465768U, // CMOVS16rm >+ 8449384U, // CMOVS16rr >+ 551640109U, // CMOVS32rm >+ 8444973U, // CMOVS32rr >+ 551657998U, // CMOVS64rm >+ 8446478U, // CMOVS64rr >+ 13484U, // CMOV_FR32 >+ 13643U, // CMOV_FR64 >+ 13363U, // CMOV_GR16 >+ 13343U, // CMOV_GR32 >+ 13662U, // CMOV_GR8 >+ 13464U, // CMOV_RFP32 >+ 13623U, // CMOV_RFP64 >+ 13383U, // CMOV_RFP80 >+ 13423U, // CMOV_V16F32 >+ 13503U, // CMOV_V2F64 >+ 13563U, // CMOV_V2I64 >+ 13403U, // CMOV_V4F32 >+ 13523U, // CMOV_V4F64 >+ 13583U, // CMOV_V4I64 >+ 13444U, // CMOV_V8F32 >+ 13543U, // CMOV_V8F64 >+ 13603U, // CMOV_V8I64 >+ 2124827U, // CMP16i16 >+ 4238363U, // CMP16mi >+ 4238363U, // CMP16mi8 >+ 4238363U, // CMP16mr >+ 551824411U, // CMP16ri >+ 551824411U, // CMP16ri8 >+ 388123U, // CMP16rm >+ 551824411U, // CMP16rr >+ 551824411U, // CMP16rr_REV >+ 10509035U, // CMP32i32 >+ 12622571U, // CMP32mi >+ 12622571U, // CMP32mi8 >+ 12622571U, // CMP32mr >+ 551820011U, // CMP32ri >+ 551820011U, // CMP32ri8 >+ 551803627U, // CMP32rm >+ 551820011U, // CMP32rr >+ 551820011U, // CMP32rr_REV >+ 16802082U, // CMP64i32 >+ 18915618U, // CMP64mi32 >+ 18915618U, // CMP64mi8 >+ 18915618U, // CMP64mr >+ 551821602U, // CMP64ri32 >+ 551821602U, // CMP64ri8 >+ 551837986U, // CMP64rm >+ 551821602U, // CMP64rr >+ 551821602U, // CMP64rr_REV >+ 20991812U, // CMP8i8 >+ 23105348U, // CMP8mi >+ 23105348U, // CMP8mr >+ 551817028U, // CMP8ri >+ 446276U, // CMP8rm >+ 551817028U, // CMP8rr >+ 551817028U, // CMP8rr_REV >+ 1111964007U, // CMPPDrmi >+ 568677425U, // CMPPDrmi_alt >+ 1380415847U, // CMPPDrri >+ 570790961U, // CMPPDrri_alt >+ 1114061159U, // CMPPSrmi >+ 568682143U, // CMPPSrmi_alt >+ 1382512999U, // CMPPSrri >+ 570795679U, // CMPPSrri_alt >+ 1625788350U, // CMPSB >+ 1921464679U, // CMPSDrm >+ 581260790U, // CMPSDrm_alt >+ 1384610151U, // CMPSDrr >+ 570791414U, // CMPSDrr_alt >+ 2162678778U, // CMPSL >+ 2431132130U, // CMPSQ >+ 2730965351U, // CMPSSrm >+ 585459854U, // CMPSSrm_alt >+ 1388804455U, // CMPSSrr >+ 570796174U, // CMPSSrr_alt >+ 2968022311U, // CMPSW >+ 560768U, // CMPXCHG16B >+ 4238164U, // CMPXCHG16rm >+ 551824212U, // CMPXCHG16rr >+ 12622345U, // CMPXCHG32rm >+ 551819785U, // CMPXCHG32rr >+ 18915426U, // CMPXCHG64rm >+ 551821410U, // CMPXCHG64rr >+ 396940U, // CMPXCHG8B >+ 23105251U, // CMPXCHG8rm >+ 551816931U, // CMPXCHG8rr >+ 579019U, // COMISDrm >+ 551818699U, // COMISDrr >+ 583780U, // COMISSrm >+ 551823460U, // COMISSrr >+ 23955U, // COMP_FST0r >+ 22636U, // COM_FIPr >+ 22579U, // COM_FIr >+ 23821U, // COM_FST0r >+ 15149U, // COS_F >+ 0U, // COS_Fp32 >+ 0U, // COS_Fp64 >+ 0U, // COS_Fp80 >+ 14248U, // CPUID32 >+ 14248U, // CPUID64 >+ 14677U, // CQO >+ 6367696U, // CRC32r32m16 >+ 283203794U, // CRC32r32m32 >+ 118392U, // CRC32r32m8 >+ 6351312U, // CRC32r32r16 >+ 6346962U, // CRC32r32r32 >+ 6344312U, // CRC32r32r8 >+ 283221523U, // CRC32r64m64 >+ 118392U, // CRC32r64m8 >+ 6348307U, // CRC32r64r64 >+ 6344312U, // CRC32r64r8 >+ 551834275U, // CVTDQ2PDrm >+ 551817891U, // CVTDQ2PDrr >+ 320767U, // CVTDQ2PSrm >+ 551822591U, // CVTDQ2PSrr >+ 581296U, // CVTPD2DQrm >+ 551820976U, // CVTPD2DQrr >+ 582867U, // CVTPD2PSrm >+ 551822547U, // CVTPD2PSrr >+ 581328U, // CVTPS2DQrm >+ 551821008U, // CVTPS2DQrr >+ 594606U, // CVTPS2PDrm >+ 551817902U, // CVTPS2PDrr >+ 596130U, // CVTSD2SI64rm >+ 551819426U, // CVTSD2SI64rr >+ 596130U, // CVTSD2SIrm >+ 551819426U, // CVTSD2SIrr >+ 600030U, // CVTSD2SSrm >+ 551823326U, // CVTSD2SSrr >+ 551837580U, // CVTSI2SD64rm >+ 551821196U, // CVTSI2SD64rr >+ 551803258U, // CVTSI2SDrm >+ 551819642U, // CVTSI2SDrr >+ 551838186U, // CVTSI2SS64rm >+ 551821802U, // CVTSI2SS64rr >+ 551803906U, // CVTSI2SSrm >+ 551820290U, // CVTSI2SSrr >+ 611645U, // CVTSS2SDrm >+ 551818557U, // CVTSS2SDrr >+ 612537U, // CVTSS2SI64rm >+ 551819449U, // CVTSS2SI64rr >+ 612537U, // CVTSS2SIrm >+ 551819449U, // CVTSS2SIrr >+ 581284U, // CVTTPD2DQrm >+ 551820964U, // CVTTPD2DQrr >+ 581316U, // CVTTPS2DQrm >+ 551820996U, // CVTTPS2DQrr >+ 596118U, // CVTTSD2SI64rm >+ 551819414U, // CVTTSD2SI64rr >+ 596118U, // CVTTSD2SIrm >+ 551819414U, // CVTTSD2SIrr >+ 612525U, // CVTTSS2SI64rm >+ 551819437U, // CVTTSS2SI64rr >+ 612525U, // CVTTSS2SIrm >+ 551819437U, // CVTTSS2SIrr >+ 14272U, // CWD >+ 14592U, // CWDE >+ 14120U, // DAA >+ 14861U, // DAS >+ 14001U, // DATA16_PREFIX >+ 223890U, // DEC16m >+ 27282U, // DEC16r >+ 27282U, // DEC32_16r >+ 22811U, // DEC32_32r >+ 235803U, // DEC32m >+ 22811U, // DEC32r >+ 223890U, // DEC64_16m >+ 27282U, // DEC64_16r >+ 235803U, // DEC64_32m >+ 22811U, // DEC64_32r >+ 401041U, // DEC64m >+ 24209U, // DEC64r >+ 429747U, // DEC8m >+ 20147U, // DEC8r >+ 224808U, // DIV16m >+ 28200U, // DIV16r >+ 236716U, // DIV32m >+ 23724U, // DIV32r >+ 402113U, // DIV64m >+ 25281U, // DIV64r >+ 430170U, // DIV8m >+ 20570U, // DIV8r >+ 8524932U, // DIVPDrm >+ 8443012U, // DIVPDrr >+ 8529707U, // DIVPSrm >+ 8447787U, // DIVPSrr >+ 190304U, // DIVR_F32m >+ 203697U, // DIVR_F64m >+ 223080U, // DIVR_FI16m >+ 236473U, // DIVR_FI32m >+ 24076U, // DIVR_FPrST0 >+ 25536U, // DIVR_FST0r >+ 0U, // DIVR_Fp32m >+ 0U, // DIVR_Fp64m >+ 0U, // DIVR_Fp64m32 >+ 0U, // DIVR_Fp80m32 >+ 0U, // DIVR_Fp80m64 >+ 0U, // DIVR_FpI16m32 >+ 0U, // DIVR_FpI16m64 >+ 0U, // DIVR_FpI16m80 >+ 0U, // DIVR_FpI32m32 >+ 0U, // DIVR_FpI32m64 >+ 0U, // DIVR_FpI32m80 >+ 28451U, // DIVR_FrST0 >+ 551704094U, // DIVSDrm >+ 551704094U, // DIVSDrm_Int >+ 8443422U, // DIVSDrr >+ 8443422U, // DIVSDrr_Int >+ 551725248U, // DIVSSrm >+ 551725248U, // DIVSSrm_Int >+ 8448192U, // DIVSSrr >+ 8448192U, // DIVSSrr_Int >+ 190707U, // DIV_F32m >+ 203947U, // DIV_F64m >+ 223482U, // DIV_FI16m >+ 236722U, // DIV_FI32m >+ 24001U, // DIV_FPrST0 >+ 27057U, // DIV_FST0r >+ 0U, // DIV_Fp32 >+ 0U, // DIV_Fp32m >+ 0U, // DIV_Fp64 >+ 0U, // DIV_Fp64m >+ 0U, // DIV_Fp64m32 >+ 0U, // DIV_Fp80 >+ 0U, // DIV_Fp80m32 >+ 0U, // DIV_Fp80m64 >+ 0U, // DIV_FpI16m32 >+ 0U, // DIV_FpI16m64 >+ 0U, // DIV_FpI16m80 >+ 0U, // DIV_FpI32m32 >+ 0U, // DIV_FpI32m64 >+ 0U, // DIV_FpI32m80 >+ 28436U, // DIV_FrST0 >+ 568677418U, // DPPDrmi >+ 570790954U, // DPPDrri >+ 568682136U, // DPPSrmi >+ 570795672U, // DPPSrri >+ 29590U, // EH_RETURN >+ 29590U, // EH_RETURN64 >+ 13810U, // EH_SjLj_LongJmp32 >+ 13914U, // EH_SjLj_LongJmp64 >+ 13829U, // EH_SjLj_SetJmp32 >+ 13933U, // EH_SjLj_SetJmp64 >+ 417276U, // EH_SjLj_Setup >+ 15137U, // ENCLS >+ 15262U, // ENCLU >+ 283140976U, // ENTER >+ 3271894722U, // EXTRACTPSmr >+ 811656898U, // EXTRACTPSrr >+ 6349222U, // EXTRQ >+ 302358950U, // EXTRQI >+ 13791U, // F2XM1 >+ 52702136U, // FARCALL16i >+ 636348U, // FARCALL16m >+ 52697714U, // FARCALL32i >+ 636314U, // FARCALL32m >+ 636331U, // FARCALL64 >+ 52702241U, // FARJMP16i >+ 636357U, // FARJMP16m >+ 52697841U, // FARJMP32i >+ 636323U, // FARJMP32m >+ 636340U, // FARJMP64 >+ 184708U, // FBLDm >+ 187855U, // FBSTPm >+ 189451U, // FCOM32m >+ 203440U, // FCOM64m >+ 190052U, // FCOMP32m >+ 203512U, // FCOMP64m >+ 14709U, // FCOMPP >+ 14724U, // FDECSTP >+ 15143U, // FEMMS >+ 22375U, // FFREE >+ 222226U, // FICOM16m >+ 236215U, // FICOM32m >+ 222828U, // FICOMP16m >+ 236288U, // FICOMP32m >+ 14732U, // FINCSTP >+ 223883U, // FLDCW16m >+ 190903U, // FLDENVm >+ 14284U, // FLDL2E >+ 15205U, // FLDL2T >+ 13895U, // FLDLG2 >+ 13902U, // FLDLN2 >+ 14442U, // FLDPI >+ 15552U, // FNCLEX >+ 15226U, // FNINIT >+ 14704U, // FNOP >+ 223908U, // FNSTCW16m >+ 15351U, // FNSTSW16r >+ 191813U, // FNSTSWm >+ 0U, // FP32_TO_INT16_IN_MEM >+ 0U, // FP32_TO_INT32_IN_MEM >+ 0U, // FP32_TO_INT64_IN_MEM >+ 0U, // FP64_TO_INT16_IN_MEM >+ 0U, // FP64_TO_INT32_IN_MEM >+ 0U, // FP64_TO_INT64_IN_MEM >+ 0U, // FP80_TO_INT16_IN_MEM >+ 0U, // FP80_TO_INT32_IN_MEM >+ 0U, // FP80_TO_INT64_IN_MEM >+ 14627U, // FPATAN >+ 14610U, // FPREM >+ 13784U, // FPREM1 >+ 14634U, // FPTAN >+ 15237U, // FRNDINT >+ 189319U, // FRSTORm >+ 186312U, // FSAVEm >+ 14312U, // FSCALE >+ 14616U, // FSETPM >+ 15154U, // FSINCOS >+ 190911U, // FSTENVm >+ 14605U, // FXAM >+ 631695U, // FXRSTOR >+ 631155U, // FXRSTOR64 >+ 628688U, // FXSAVE >+ 630853U, // FXSAVE64 >+ 15212U, // FXTRACT >+ 15345U, // FYL2X >+ 13797U, // FYL2XP1 >+ 8524825U, // FsANDNPDrm >+ 8442905U, // FsANDNPDrr >+ 8529535U, // FsANDNPSrm >+ 8447615U, // FsANDNPSrr >+ 8524689U, // FsANDPDrm >+ 8442769U, // FsANDPDrr >+ 8529370U, // FsANDPSrm >+ 8447450U, // FsANDPSrr >+ 0U, // FsFLD0SD >+ 0U, // FsFLD0SS >+ 578319U, // FsMOVAPDrm >+ 583008U, // FsMOVAPSrm >+ 8524869U, // FsORPDrm >+ 8442949U, // FsORPDrr >+ 8529587U, // FsORPSrm >+ 8447667U, // FsORPSrr >+ 578318U, // FsVMOVAPDrm >+ 583007U, // FsVMOVAPSrm >+ 8524876U, // FsXORPDrm >+ 8442956U, // FsXORPDrr >+ 8529594U, // FsXORPSrm >+ 8447674U, // FsXORPSrr >+ 14205U, // GETSEC >+ 8524651U, // HADDPDrm >+ 8442731U, // HADDPDrr >+ 8529332U, // HADDPSrm >+ 8447412U, // HADDPSrr >+ 15233U, // HLT >+ 8524600U, // HSUBPDrm >+ 8442680U, // HSUBPDrr >+ 8529281U, // HSUBPSrm >+ 8447361U, // HSUBPSrr >+ 224807U, // IDIV16m >+ 28199U, // IDIV16r >+ 236723U, // IDIV32m >+ 23731U, // IDIV32r >+ 402112U, // IDIV64m >+ 25280U, // IDIV64r >+ 430169U, // IDIV8m >+ 20569U, // IDIV8r >+ 222193U, // ILD_F16m >+ 235874U, // ILD_F32m >+ 399954U, // ILD_F64m >+ 0U, // ILD_Fp16m32 >+ 0U, // ILD_Fp16m64 >+ 0U, // ILD_Fp16m80 >+ 0U, // ILD_Fp32m32 >+ 0U, // ILD_Fp32m64 >+ 0U, // ILD_Fp32m80 >+ 0U, // ILD_Fp64m32 >+ 0U, // ILD_Fp64m64 >+ 0U, // ILD_Fp64m80 >+ 224229U, // IMUL16m >+ 27621U, // IMUL16r >+ 8465381U, // IMUL16rm >+ 54864869U, // IMUL16rmi >+ 54864869U, // IMUL16rmi8 >+ 8448997U, // IMUL16rr >+ 811658213U, // IMUL16rri >+ 811658213U, // IMUL16rri8 >+ 236193U, // IMUL32m >+ 23201U, // IMUL32r >+ 551639713U, // IMUL32rm >+ 832903841U, // IMUL32rmi >+ 832903841U, // IMUL32rmi8 >+ 8444577U, // IMUL32rr >+ 811653793U, // IMUL32rri >+ 811653793U, // IMUL32rri8 >+ 401626U, // IMUL64m >+ 24794U, // IMUL64r >+ 551657690U, // IMUL64rm >+ 835002586U, // IMUL64rmi32 >+ 835002586U, // IMUL64rmi8 >+ 8446170U, // IMUL64rr >+ 811655386U, // IMUL64rri32 >+ 811655386U, // IMUL64rri8 >+ 429854U, // IMUL8m >+ 20254U, // IMUL8r >+ 2124805U, // IN16ri >+ 15362U, // IN16rr >+ 10508998U, // IN32ri >+ 15441U, // IN32rr >+ 20991798U, // IN8ri >+ 14472U, // IN8rr >+ 223896U, // INC16m >+ 27288U, // INC16r >+ 27288U, // INC32_16r >+ 22817U, // INC32_32r >+ 235809U, // INC32m >+ 22817U, // INC32r >+ 223896U, // INC64_16m >+ 27288U, // INC64_16r >+ 235809U, // INC64_32m >+ 22817U, // INC64_32r >+ 401047U, // INC64m >+ 24215U, // INC64r >+ 429753U, // INC8m >+ 20153U, // INC8r >+ 504521U, // INSB >+ 585459416U, // INSERTPSrm >+ 570795736U, // INSERTPSrr >+ 6349449U, // INSERTQ >+ 302637705U, // INSERTQI >+ 520916U, // INSL >+ 553695U, // INSW >+ 26897U, // INT >+ 13805U, // INT1 >+ 13909U, // INT3 >+ 14672U, // INTO >+ 14279U, // INVD >+ 321814U, // INVEPT32 >+ 321814U, // INVEPT64 >+ 432100U, // INVLPG >+ 15422U, // INVLPGA32 >+ 15490U, // INVLPGA64 >+ 315762U, // INVPCID32 >+ 315762U, // INVPCID64 >+ 315771U, // INVVPID32 >+ 315771U, // INVVPID64 >+ 15333U, // IRET16 >+ 14563U, // IRET32 >+ 14773U, // IRET64 >+ 222989U, // ISTT_FP16m >+ 236339U, // ISTT_FP32m >+ 400009U, // ISTT_FP64m >+ 0U, // ISTT_Fp16m32 >+ 0U, // ISTT_Fp16m64 >+ 0U, // ISTT_Fp16m80 >+ 0U, // ISTT_Fp32m32 >+ 0U, // ISTT_Fp32m64 >+ 0U, // ISTT_Fp32m80 >+ 0U, // ISTT_Fp64m32 >+ 0U, // ISTT_Fp64m64 >+ 0U, // ISTT_Fp64m80 >+ 223468U, // IST_F16m >+ 236694U, // IST_F32m >+ 222981U, // IST_FP16m >+ 236331U, // IST_FP32m >+ 400000U, // IST_FP64m >+ 0U, // IST_Fp16m32 >+ 0U, // IST_Fp16m64 >+ 0U, // IST_Fp16m80 >+ 0U, // IST_Fp32m32 >+ 0U, // IST_Fp32m64 >+ 0U, // IST_Fp32m80 >+ 0U, // IST_Fp64m32 >+ 0U, // IST_Fp64m64 >+ 0U, // IST_Fp64m80 >+ 1921464679U, // Int_CMPSDrm >+ 1384610151U, // Int_CMPSDrr >+ 2730965351U, // Int_CMPSSrm >+ 1388804455U, // Int_CMPSSrr >+ 579019U, // Int_COMISDrm >+ 551818699U, // Int_COMISDrr >+ 583780U, // Int_COMISSrm >+ 551823460U, // Int_COMISSrr >+ 551708638U, // Int_CVTSD2SSrm >+ 8447966U, // Int_CVTSD2SSrr >+ 551657356U, // Int_CVTSI2SD64rm >+ 8445836U, // Int_CVTSI2SD64rr >+ 551639418U, // Int_CVTSI2SDrm >+ 8444282U, // Int_CVTSI2SDrr >+ 551657962U, // Int_CVTSI2SS64rm >+ 8446442U, // Int_CVTSI2SS64rr >+ 551640066U, // Int_CVTSI2SSrm >+ 8444930U, // Int_CVTSI2SSrr >+ 551720253U, // Int_CVTSS2SDrm >+ 8443197U, // Int_CVTSS2SDrr >+ 596118U, // Int_CVTTSD2SI64rm >+ 551819414U, // Int_CVTTSD2SI64rr >+ 596118U, // Int_CVTTSD2SIrm >+ 551819414U, // Int_CVTTSD2SIrr >+ 612525U, // Int_CVTTSS2SI64rm >+ 551819437U, // Int_CVTTSS2SI64rr >+ 612525U, // Int_CVTTSS2SIrm >+ 551819437U, // Int_CVTTSS2SIrr >+ 14089U, // Int_MemBarrier >+ 579018U, // Int_UCOMISDrm >+ 551818698U, // Int_UCOMISDrr >+ 583779U, // Int_UCOMISSrm >+ 551823459U, // Int_UCOMISSrr >+ 1921661291U, // Int_VCMPSDrm >+ 1384806763U, // Int_VCMPSDrr >+ 2731161963U, // Int_VCMPSSrm >+ 1389001067U, // Int_VCMPSSrr >+ 579027U, // Int_VCOMISDZrm >+ 551818707U, // Int_VCOMISDZrr >+ 579027U, // Int_VCOMISDrm >+ 551818707U, // Int_VCOMISDrr >+ 583788U, // Int_VCOMISSZrm >+ 551823468U, // Int_VCOMISSZrr >+ 583788U, // Int_VCOMISSrm >+ 551823468U, // Int_VCOMISSrr >+ 283273181U, // Int_VCVTSD2SSrm >+ 811657181U, // Int_VCVTSD2SSrr >+ 283221899U, // Int_VCVTSI2SD64Zrm >+ 811655051U, // Int_VCVTSI2SD64Zrr >+ 283221899U, // Int_VCVTSI2SD64rm >+ 811655051U, // Int_VCVTSI2SD64rr >+ 283203961U, // Int_VCVTSI2SDZrm >+ 811653497U, // Int_VCVTSI2SDZrr >+ 283203961U, // Int_VCVTSI2SDrm >+ 811653497U, // Int_VCVTSI2SDrr >+ 283222505U, // Int_VCVTSI2SS64Zrm >+ 811655657U, // Int_VCVTSI2SS64Zrr >+ 283222505U, // Int_VCVTSI2SS64rm >+ 811655657U, // Int_VCVTSI2SS64rr >+ 283204609U, // Int_VCVTSI2SSZrm >+ 811654145U, // Int_VCVTSI2SSZrr >+ 283204609U, // Int_VCVTSI2SSrm >+ 811654145U, // Int_VCVTSI2SSrr >+ 283284796U, // Int_VCVTSS2SDrm >+ 811652412U, // Int_VCVTSS2SDrr >+ 591246U, // Int_VCVTTSD2SI64Zrm >+ 551814542U, // Int_VCVTTSD2SI64Zrr >+ 596117U, // Int_VCVTTSD2SI64rm >+ 551819413U, // Int_VCVTTSD2SI64rr >+ 591246U, // Int_VCVTTSD2SIZrm >+ 551814542U, // Int_VCVTTSD2SIZrr >+ 596117U, // Int_VCVTTSD2SIrm >+ 551819413U, // Int_VCVTTSD2SIrr >+ 591296U, // Int_VCVTTSD2USI64Zrm >+ 551814592U, // Int_VCVTTSD2USI64Zrr >+ 591296U, // Int_VCVTTSD2USIZrm >+ 551814592U, // Int_VCVTTSD2USIZrr >+ 607655U, // Int_VCVTTSS2SI64Zrm >+ 551814567U, // Int_VCVTTSS2SI64Zrr >+ 612524U, // Int_VCVTTSS2SI64rm >+ 551819436U, // Int_VCVTTSS2SI64rr >+ 607655U, // Int_VCVTTSS2SIZrm >+ 551814567U, // Int_VCVTTSS2SIZrr >+ 612524U, // Int_VCVTTSS2SIrm >+ 551819436U, // Int_VCVTTSS2SIrr >+ 607707U, // Int_VCVTTSS2USI64Zrm >+ 551814619U, // Int_VCVTTSS2USI64Zrr >+ 607707U, // Int_VCVTTSS2USIZrm >+ 551814619U, // Int_VCVTTSS2USIZrr >+ 283221911U, // Int_VCVTUSI2SD64Zrm >+ 811655063U, // Int_VCVTUSI2SD64Zrr >+ 283203973U, // Int_VCVTUSI2SDZrm >+ 811653509U, // Int_VCVTUSI2SDZrr >+ 283222517U, // Int_VCVTUSI2SS64Zrm >+ 811655669U, // Int_VCVTUSI2SS64Zrr >+ 283204621U, // Int_VCVTUSI2SSZrm >+ 811654157U, // Int_VCVTUSI2SSZrr >+ 579017U, // Int_VUCOMISDZrm >+ 551818697U, // Int_VUCOMISDZrr >+ 579017U, // Int_VUCOMISDrm >+ 551818697U, // Int_VUCOMISDrr >+ 583778U, // Int_VUCOMISSZrm >+ 551823458U, // Int_VUCOMISSZrr >+ 583778U, // Int_VUCOMISSrm >+ 551823458U, // Int_VUCOMISSrr >+ 415548U, // JAE_1 >+ 415548U, // JAE_2 >+ 415548U, // JAE_4 >+ 413261U, // JA_1 >+ 413261U, // JA_2 >+ 413261U, // JA_4 >+ 415560U, // JBE_1 >+ 415560U, // JBE_2 >+ 415560U, // JBE_4 >+ 413429U, // JB_1 >+ 413429U, // JB_2 >+ 413429U, // JB_4 >+ 421551U, // JCXZ >+ 421544U, // JECXZ_32 >+ 421544U, // JECXZ_64 >+ 415619U, // JE_1 >+ 415619U, // JE_2 >+ 415619U, // JE_4 >+ 415598U, // JGE_1 >+ 415598U, // JGE_2 >+ 415598U, // JGE_4 >+ 415712U, // JG_1 >+ 415712U, // JG_2 >+ 415712U, // JG_4 >+ 415623U, // JLE_1 >+ 415623U, // JLE_2 >+ 415623U, // JLE_4 >+ 416313U, // JL_1 >+ 416313U, // JL_2 >+ 416313U, // JL_4 >+ 226758U, // JMP16m >+ 30150U, // JMP16r >+ 243108U, // JMP32m >+ 30116U, // JMP32r >+ 406965U, // JMP64m >+ 30133U, // JMP64r >+ 417166U, // JMP_1 >+ 417166U, // JMP_2 >+ 417166U, // JMP_4 >+ 415635U, // JNE_1 >+ 415635U, // JNE_2 >+ 415635U, // JNE_4 >+ 417116U, // JNO_1 >+ 417116U, // JNO_2 >+ 417116U, // JNO_4 >+ 417186U, // JNP_1 >+ 417186U, // JNP_2 >+ 417186U, // JNP_4 >+ 418842U, // JNS_1 >+ 418842U, // JNS_2 >+ 418842U, // JNS_4 >+ 417112U, // JO_1 >+ 417112U, // JO_2 >+ 417112U, // JO_4 >+ 417155U, // JP_1 >+ 417155U, // JP_2 >+ 417155U, // JP_4 >+ 421557U, // JRCXZ >+ 418808U, // JS_1 >+ 418808U, // JS_2 >+ 418808U, // JS_4 >+ 811647013U, // KANDBrr >+ 811647227U, // KANDDrr >+ 811647054U, // KANDNBrr >+ 811647353U, // KANDNDrr >+ 811649018U, // KANDNQrr >+ 811650108U, // KANDNWrr >+ 811648768U, // KANDQrr >+ 811650056U, // KANDWrr >+ 551813272U, // KMOVBkk >+ 442520U, // KMOVBkm >+ 551813272U, // KMOVBkr >+ 23101592U, // KMOVBmk >+ 551813272U, // KMOVBrk >+ 551814498U, // KMOVDkk >+ 551798114U, // KMOVDkm >+ 551814498U, // KMOVDkr >+ 12617058U, // KMOVDmk >+ 551814498U, // KMOVDrk >+ 551815413U, // KMOVQkk >+ 551831797U, // KMOVQkm >+ 551815413U, // KMOVQkr >+ 18909429U, // KMOVQmk >+ 551815413U, // KMOVQrk >+ 551816348U, // KMOVWkk >+ 380060U, // KMOVWkm >+ 551816348U, // KMOVWkr >+ 4230300U, // KMOVWmk >+ 551816348U, // KMOVWrk >+ 551813264U, // KNOTBrr >+ 551814425U, // KNOTDrr >+ 551815340U, // KNOTQrr >+ 551816329U, // KNOTWrr >+ 811647096U, // KORBrr >+ 811648042U, // KORDrr >+ 811649074U, // KORQrr >+ 551816337U, // KORTESTWrr >+ 811650150U, // KORWrr >+ 0U, // KSET0B >+ 0U, // KSET0W >+ 0U, // KSET1B >+ 0U, // KSET1W >+ 811650097U, // KSHIFTLWri >+ 811650174U, // KSHIFTRWri >+ 811650045U, // KUNPCKBWrr >+ 811647103U, // KXNORBrr >+ 811648049U, // KXNORDrr >+ 811649081U, // KXNORQrr >+ 811650157U, // KXNORWrr >+ 811647112U, // KXORBrr >+ 811648066U, // KXORDrr >+ 811649098U, // KXORQrr >+ 811650166U, // KXORWrr >+ 14409U, // LAHF >+ 388175U, // LAR16rm >+ 551824463U, // LAR16rr >+ 383835U, // LAR32rm >+ 551820123U, // LAR32rr >+ 385365U, // LAR64rm >+ 551821653U, // LAR64rr >+ 4238164U, // LCMPXCHG16 >+ 560768U, // LCMPXCHG16B >+ 12622345U, // LCMPXCHG32 >+ 18915426U, // LCMPXCHG64 >+ 23105251U, // LCMPXCHG8 >+ 396940U, // LCMPXCHG8B >+ 321932U, // LDDQUrm >+ 238502U, // LDMXCSR >+ 699638U, // LDS16rm >+ 695250U, // LDS32rm >+ 15559U, // LD_F0 >+ 13779U, // LD_F1 >+ 189419U, // LD_F32m >+ 203093U, // LD_F64m >+ 715010U, // LD_F80m >+ 0U, // LD_Fp032 >+ 0U, // LD_Fp064 >+ 0U, // LD_Fp080 >+ 0U, // LD_Fp132 >+ 0U, // LD_Fp164 >+ 0U, // LD_Fp180 >+ 0U, // LD_Fp32m >+ 0U, // LD_Fp32m64 >+ 0U, // LD_Fp32m80 >+ 0U, // LD_Fp64m >+ 0U, // LD_Fp64m80 >+ 0U, // LD_Fp80m >+ 20874U, // LD_Frr >+ 387544U, // LEA16r >+ 551803098U, // LEA32r >+ 551803098U, // LEA64_32r >+ 551837220U, // LEA64r >+ 14396U, // LEAVE >+ 14396U, // LEAVE64 >+ 699651U, // LES16rm >+ 695263U, // LES32rm >+ 14291U, // LFENCE >+ 699657U, // LFS16rm >+ 695269U, // LFS32rm >+ 696781U, // LFS64rm >+ 634238U, // LGDT16m >+ 629818U, // LGDT32m >+ 631323U, // LGDT64m >+ 699663U, // LGS16rm >+ 695275U, // LGS32rm >+ 696787U, // LGS64rm >+ 634252U, // LIDT16m >+ 629832U, // LIDT32m >+ 631337U, // LIDT64m >+ 224666U, // LLDT16m >+ 28058U, // LLDT16r >+ 224830U, // LMSW16m >+ 28222U, // LMSW16r >+ 4237999U, // LOCK_ADD16mi >+ 4237999U, // LOCK_ADD16mi8 >+ 4237999U, // LOCK_ADD16mr >+ 12622135U, // LOCK_ADD32mi >+ 12622135U, // LOCK_ADD32mi8 >+ 12622135U, // LOCK_ADD32mr >+ 18915055U, // LOCK_ADD64mi32 >+ 18915055U, // LOCK_ADD64mi8 >+ 18915055U, // LOCK_ADD64mr >+ 23105217U, // LOCK_ADD8mi >+ 23105217U, // LOCK_ADD8mr >+ 4238039U, // LOCK_AND16mi >+ 4238039U, // LOCK_AND16mi8 >+ 4238039U, // LOCK_AND16mr >+ 12622188U, // LOCK_AND32mi >+ 12622188U, // LOCK_AND32mi8 >+ 12622188U, // LOCK_AND32mr >+ 18915148U, // LOCK_AND64mi32 >+ 18915148U, // LOCK_AND64mi8 >+ 18915148U, // LOCK_AND64mr >+ 23105230U, // LOCK_AND8mi >+ 23105230U, // LOCK_AND8mr >+ 223890U, // LOCK_DEC16m >+ 235803U, // LOCK_DEC32m >+ 401041U, // LOCK_DEC64m >+ 429747U, // LOCK_DEC8m >+ 223896U, // LOCK_INC16m >+ 235809U, // LOCK_INC32m >+ 401047U, // LOCK_INC64m >+ 429753U, // LOCK_INC8m >+ 4238455U, // LOCK_OR16mi >+ 4238455U, // LOCK_OR16mi8 >+ 4238455U, // LOCK_OR16mr >+ 12622725U, // LOCK_OR32mi >+ 12622725U, // LOCK_OR32mi8 >+ 12622725U, // LOCK_OR32mr >+ 18915694U, // LOCK_OR64mi32 >+ 18915694U, // LOCK_OR64mi8 >+ 18915694U, // LOCK_OR64mr >+ 23105383U, // LOCK_OR8mi >+ 23105383U, // LOCK_OR8mr >+ 14467U, // LOCK_PREFIX >+ 4237905U, // LOCK_SUB16mi >+ 4237905U, // LOCK_SUB16mi8 >+ 4237905U, // LOCK_SUB16mr >+ 12622071U, // LOCK_SUB32mi >+ 12622071U, // LOCK_SUB32mi8 >+ 12622071U, // LOCK_SUB32mr >+ 18914911U, // LOCK_SUB64mi32 >+ 18914911U, // LOCK_SUB64mi8 >+ 18914911U, // LOCK_SUB64mr >+ 23105191U, // LOCK_SUB8mi >+ 23105191U, // LOCK_SUB8mr >+ 4238460U, // LOCK_XOR16mi >+ 4238460U, // LOCK_XOR16mi8 >+ 4238460U, // LOCK_XOR16mr >+ 12622730U, // LOCK_XOR32mi >+ 12622730U, // LOCK_XOR32mi8 >+ 12622730U, // LOCK_XOR32mr >+ 18915709U, // LOCK_XOR64mi32 >+ 18915709U, // LOCK_XOR64mi8 >+ 18915709U, // LOCK_XOR64mr >+ 23105388U, // LOCK_XOR8mi >+ 23105388U, // LOCK_XOR8mr >+ 21696430U, // LODSB >+ 11230168U, // LODSL >+ 762310U, // LODSQ >+ 2878716U, // LODSW >+ 417203U, // LOOP >+ 415664U, // LOOPE >+ 415640U, // LOOPNE >+ 23645U, // LRETIL >+ 25150U, // LRETIQ >+ 28072U, // LRETIW >+ 14569U, // LRETL >+ 14779U, // LRETQ >+ 15339U, // LRETW >+ 388063U, // LSL16rm >+ 551824351U, // LSL16rr >+ 551803539U, // LSL32rm >+ 551819923U, // LSL32rr >+ 551837900U, // LSL64rm >+ 551821516U, // LSL64rr >+ 699705U, // LSS16rm >+ 695322U, // LSS32rm >+ 696834U, // LSS64rm >+ 224407U, // LTRm >+ 27799U, // LTRr >+ 3504614077U, // LXADD16 >+ 3773045061U, // LXADD32 >+ 4041481973U, // LXADD64 >+ 14945991U, // LXADD8 >+ 388546U, // LZCNT16rm >+ 551824834U, // LZCNT16rr >+ 551804019U, // LZCNT32rm >+ 551820403U, // LZCNT32rr >+ 551838296U, // LZCNT64rm >+ 551821912U, // LZCNT64rr >+ 551823764U, // MASKMOVDQU >+ 551823764U, // MASKMOVDQU64 >+ 8524952U, // MAXCPDrm >+ 8443032U, // MAXCPDrr >+ 8529727U, // MAXCPSrm >+ 8447807U, // MAXCPSrr >+ 551704111U, // MAXCSDrm >+ 8443439U, // MAXCSDrr >+ 551725264U, // MAXCSSrm >+ 8448208U, // MAXCSSrr >+ 8524952U, // MAXPDrm >+ 8443032U, // MAXPDrr >+ 8529727U, // MAXPSrm >+ 8447807U, // MAXPSrr >+ 551704111U, // MAXSDrm >+ 551704111U, // MAXSDrm_Int >+ 8443439U, // MAXSDrr >+ 8443439U, // MAXSDrr_Int >+ 551725264U, // MAXSSrm >+ 551725264U, // MAXSSrm_Int >+ 8448208U, // MAXSSrr >+ 8448208U, // MAXSSrr_Int >+ 14298U, // MFENCE >+ 8524834U, // MINCPDrm >+ 8442914U, // MINCPDrr >+ 8529544U, // MINCPSrm >+ 8447624U, // MINCPSrr >+ 551704038U, // MINCSDrm >+ 8443366U, // MINCSDrr >+ 551725182U, // MINCSSrm >+ 8448126U, // MINCSSrr >+ 8524834U, // MINPDrm >+ 8442914U, // MINPDrr >+ 8529544U, // MINPSrm >+ 8447624U, // MINPSrr >+ 551704038U, // MINSDrm >+ 551704038U, // MINSDrm_Int >+ 8443366U, // MINSDrr >+ 8443366U, // MINSDrr_Int >+ 551725182U, // MINSSrm >+ 551725182U, // MINSSrm_Int >+ 8448126U, // MINSSrr >+ 8448126U, // MINSSrr_Int >+ 579661U, // MMX_CVTPD2PIirm >+ 551819341U, // MMX_CVTPD2PIirr >+ 551834252U, // MMX_CVTPI2PDirm >+ 551817868U, // MMX_CVTPI2PDirr >+ 551658728U, // MMX_CVTPI2PSirm >+ 8447208U, // MMX_CVTPI2PSirr >+ 596066U, // MMX_CVTPS2PIirm >+ 551819362U, // MMX_CVTPS2PIirr >+ 579650U, // MMX_CVTTPD2PIirm >+ 551819330U, // MMX_CVTTPD2PIirr >+ 596055U, // MMX_CVTTPS2PIirm >+ 551819351U, // MMX_CVTTPS2PIirr >+ 15144U, // MMX_EMMS >+ 551822043U, // MMX_MASKMOVQ >+ 551822043U, // MMX_MASKMOVQ64 >+ 551818924U, // MMX_MOVD64from64rr >+ 551818924U, // MMX_MOVD64grr >+ 12621484U, // MMX_MOVD64mr >+ 551802540U, // MMX_MOVD64rm >+ 551818924U, // MMX_MOVD64rr >+ 551818924U, // MMX_MOVD64to64rr >+ 551820827U, // MMX_MOVDQ2Qrr >+ 551820827U, // MMX_MOVFR642Qrr >+ 18915944U, // MMX_MOVNTQmr >+ 551820986U, // MMX_MOVQ2DQrr >+ 551820986U, // MMX_MOVQ2FR64rr >+ 18916063U, // MMX_MOVQ64mr >+ 551838431U, // MMX_MOVQ64rm >+ 551822047U, // MMX_MOVQ64rr >+ 551822047U, // MMX_MOVQ64rr_REV >+ 551833484U, // MMX_PABSBrm64 >+ 551817100U, // MMX_PABSBrr64 >+ 551835006U, // MMX_PABSDrm64 >+ 551818622U, // MMX_PABSDrr64 >+ 551840948U, // MMX_PABSWrm64 >+ 551824564U, // MMX_PABSWrr64 >+ 551660271U, // MMX_PACKSSDWirm >+ 8448751U, // MMX_PACKSSDWirr >+ 551653481U, // MMX_PACKSSWBirm >+ 8441961U, // MMX_PACKSSWBirr >+ 551653492U, // MMX_PACKUSWBirm >+ 8441972U, // MMX_PACKUSWBirr >+ 551653056U, // MMX_PADDBirm >+ 8441536U, // MMX_PADDBirr >+ 551653673U, // MMX_PADDDirm >+ 8442153U, // MMX_PADDDirr >+ 551657198U, // MMX_PADDQirm >+ 8445678U, // MMX_PADDQirr >+ 551653286U, // MMX_PADDSBirm >+ 8441766U, // MMX_PADDSBirr >+ 551660782U, // MMX_PADDSWirm >+ 8449262U, // MMX_PADDSWirr >+ 551653335U, // MMX_PADDUSBirm >+ 8441815U, // MMX_PADDUSBirr >+ 551660895U, // MMX_PADDUSWirm >+ 8449375U, // MMX_PADDUSWirr >+ 551660214U, // MMX_PADDWirm >+ 8448694U, // MMX_PADDWirr >+ 593847160U, // MMX_PALIGNR64irm >+ 570794872U, // MMX_PALIGNR64irr >+ 551656763U, // MMX_PANDNirm >+ 8445243U, // MMX_PANDNirr >+ 551653834U, // MMX_PANDirm >+ 8442314U, // MMX_PANDirr >+ 551653102U, // MMX_PAVGBirm >+ 8441582U, // MMX_PAVGBirr >+ 551660383U, // MMX_PAVGWirm >+ 8448863U, // MMX_PAVGWirr >+ 551653195U, // MMX_PCMPEQBirm >+ 8441675U, // MMX_PCMPEQBirr >+ 551654569U, // MMX_PCMPEQDirm >+ 8443049U, // MMX_PCMPEQDirr >+ 551660614U, // MMX_PCMPEQWirm >+ 8449094U, // MMX_PCMPEQWirr >+ 551653376U, // MMX_PCMPGTBirm >+ 8441856U, // MMX_PCMPGTBirr >+ 551654984U, // MMX_PCMPGTDirm >+ 8443464U, // MMX_PCMPGTDirr >+ 551660976U, // MMX_PCMPGTWirm >+ 8449456U, // MMX_PCMPGTWirr >+ 811658404U, // MMX_PEXTRWirri >+ 551660772U, // MMX_PHADDSWrm64 >+ 8449252U, // MMX_PHADDSWrr64 >+ 551660205U, // MMX_PHADDWrm64 >+ 8448685U, // MMX_PHADDWrr64 >+ 551653664U, // MMX_PHADDrm64 >+ 8442144U, // MMX_PHADDrr64 >+ 551653618U, // MMX_PHSUBDrm64 >+ 8442098U, // MMX_PHSUBDrr64 >+ 551660753U, // MMX_PHSUBSWrm64 >+ 8449233U, // MMX_PHSUBSWrr64 >+ 551660111U, // MMX_PHSUBWrm64 >+ 8448591U, // MMX_PHSUBWrr64 >+ 595946633U, // MMX_PINSRWirmi >+ 570797193U, // MMX_PINSRWirri >+ 551660741U, // MMX_PMADDUBSWrm64 >+ 8449221U, // MMX_PMADDUBSWrr64 >+ 551655118U, // MMX_PMADDWDirm >+ 8443598U, // MMX_PMADDWDirr >+ 551660913U, // MMX_PMAXSWirm >+ 8449393U, // MMX_PMAXSWirr >+ 551653446U, // MMX_PMAXUBirm >+ 8441926U, // MMX_PMAXUBirr >+ 551660822U, // MMX_PMINSWirm >+ 8449302U, // MMX_PMINSWirr >+ 551653430U, // MMX_PMINUBirm >+ 8441910U, // MMX_PMINUBirr >+ 551816954U, // MMX_PMOVMSKBrr >+ 551660847U, // MMX_PMULHRSWrm64 >+ 8449327U, // MMX_PMULHRSWrr64 >+ 551661046U, // MMX_PMULHUWirm >+ 8449526U, // MMX_PMULHUWirr >+ 551660420U, // MMX_PMULHWirm >+ 8448900U, // MMX_PMULHWirr >+ 551660489U, // MMX_PMULLWirm >+ 8448969U, // MMX_PMULLWirr >+ 551657402U, // MMX_PMULUDQirm >+ 8445882U, // MMX_PMULUDQirr >+ 551658370U, // MMX_PORirm >+ 8446850U, // MMX_PORirr >+ 551660040U, // MMX_PSADBWirm >+ 8448520U, // MMX_PSADBWirr >+ 551653077U, // MMX_PSHUFBrm64 >+ 8441557U, // MMX_PSHUFBrr64 >+ 835005254U, // MMX_PSHUFWmi >+ 811658054U, // MMX_PSHUFWri >+ 551653166U, // MMX_PSIGNBrm64 >+ 8441646U, // MMX_PSIGNBrr64 >+ 551653841U, // MMX_PSIGNDrm64 >+ 8442321U, // MMX_PSIGNDrr64 >+ 551660541U, // MMX_PSIGNWrm64 >+ 8449021U, // MMX_PSIGNWrr64 >+ 8442264U, // MMX_PSLLDri >+ 551653784U, // MMX_PSLLDrm >+ 8442264U, // MMX_PSLLDrr >+ 8446135U, // MMX_PSLLQri >+ 551657655U, // MMX_PSLLQrm >+ 8446135U, // MMX_PSLLQrr >+ 8448961U, // MMX_PSLLWri >+ 551660481U, // MMX_PSLLWrm >+ 8448961U, // MMX_PSLLWrr >+ 8442069U, // MMX_PSRADri >+ 551653589U, // MMX_PSRADrm >+ 8442069U, // MMX_PSRADrr >+ 8448487U, // MMX_PSRAWri >+ 551660007U, // MMX_PSRAWrm >+ 8448487U, // MMX_PSRAWrr >+ 8442281U, // MMX_PSRLDri >+ 551653801U, // MMX_PSRLDrm >+ 8442281U, // MMX_PSRLDrr >+ 8446149U, // MMX_PSRLQri >+ 551657669U, // MMX_PSRLQrm >+ 8446149U, // MMX_PSRLQrr >+ 8448984U, // MMX_PSRLWri >+ 551660504U, // MMX_PSRLWrm >+ 8448984U, // MMX_PSRLWrr >+ 551653030U, // MMX_PSUBBirm >+ 8441510U, // MMX_PSUBBirr >+ 551653627U, // MMX_PSUBDirm >+ 8442107U, // MMX_PSUBDirr >+ 551657054U, // MMX_PSUBQirm >+ 8445534U, // MMX_PSUBQirr >+ 551653277U, // MMX_PSUBSBirm >+ 8441757U, // MMX_PSUBSBirr >+ 551660763U, // MMX_PSUBSWirm >+ 8449243U, // MMX_PSUBSWirr >+ 551653325U, // MMX_PSUBUSBirm >+ 8441805U, // MMX_PSUBUSBirr >+ 551660885U, // MMX_PSUBUSWirm >+ 8449365U, // MMX_PSUBUSWirr >+ 551660120U, // MMX_PSUBWirm >+ 8448600U, // MMX_PSUBWirr >+ 551660068U, // MMX_PUNPCKHBWirm >+ 8448548U, // MMX_PUNPCKHBWirr >+ 551657232U, // MMX_PUNPCKHDQirm >+ 8445712U, // MMX_PUNPCKHDQirr >+ 551655128U, // MMX_PUNPCKHWDirm >+ 8443608U, // MMX_PUNPCKHWDirr >+ 551660080U, // MMX_PUNPCKLBWirm >+ 8448560U, // MMX_PUNPCKLBWirr >+ 551657251U, // MMX_PUNPCKLDQirm >+ 8445731U, // MMX_PUNPCKLDQirr >+ 551655140U, // MMX_PUNPCKLWDirm >+ 8443620U, // MMX_PUNPCKLWDirr >+ 551658393U, // MMX_PXORirm >+ 8446873U, // MMX_PXORirr >+ 0U, // MONITOR >+ 14827U, // MONITORrrr >+ 14597U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 799342U, // MOV16ao16 >+ 799342U, // MOV16ao16_16 >+ 4238894U, // MOV16mi >+ 4238894U, // MOV16mr >+ 4238894U, // MOV16ms >+ 2895406U, // MOV16o16a >+ 2895406U, // MOV16o16a_16 >+ 551824942U, // MOV16ri >+ 551824942U, // MOV16ri_alt >+ 388654U, // MOV16rm >+ 551824942U, // MOV16rr >+ 551824942U, // MOV16rr_REV >+ 551824942U, // MOV16rs >+ 388654U, // MOV16sm >+ 551824942U, // MOV16sr >+ 815777U, // MOV32ao32 >+ 815777U, // MOV32ao32_16 >+ 551820474U, // MOV32cr >+ 551820474U, // MOV32dr >+ 12623034U, // MOV32mi >+ 12623034U, // MOV32mr >+ 4234426U, // MOV32ms >+ 11295930U, // MOV32o32a >+ 11295930U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 551820474U, // MOV32rc >+ 551820474U, // MOV32rd >+ 551820474U, // MOV32ri >+ 0U, // MOV32ri64 >+ 551820474U, // MOV32ri_alt >+ 551804090U, // MOV32rm >+ 551820474U, // MOV32rr >+ 551820474U, // MOV32rr_REV >+ 551820474U, // MOV32rs >+ 384186U, // MOV32sm >+ 551820474U, // MOV32sr >+ 799305U, // MOV64ao16 >+ 815737U, // MOV64ao32 >+ 832173U, // MOV64ao64 >+ 847985U, // MOV64ao8 >+ 551822047U, // MOV64cr >+ 551822047U, // MOV64dr >+ 18916063U, // MOV64mi32 >+ 18916063U, // MOV64mr >+ 4235999U, // MOV64ms >+ 2895035U, // MOV64o16a >+ 11295689U, // MOV64o32a >+ 17605053U, // MOV64o64a >+ 21811091U, // MOV64o8a >+ 551822047U, // MOV64rc >+ 551822047U, // MOV64rd >+ 551821757U, // MOV64ri >+ 551822047U, // MOV64ri32 >+ 551838431U, // MOV64rm >+ 551822047U, // MOV64rr >+ 551822047U, // MOV64rr_REV >+ 551822047U, // MOV64rs >+ 385759U, // MOV64sm >+ 551822047U, // MOV64sr >+ 551818924U, // MOV64toPQIrr >+ 551838431U, // MOV64toSDrm >+ 551818924U, // MOV64toSDrr >+ 848022U, // MOV8ao8 >+ 848022U, // MOV8ao8_16 >+ 23105634U, // MOV8mi >+ 23105634U, // MOV8mr >+ 291541090U, // MOV8mr_NOREX >+ 21811298U, // MOV8o8a >+ 21811298U, // MOV8o8a_16 >+ 551817314U, // MOV8ri >+ 551817314U, // MOV8ri_alt >+ 446562U, // MOV8rm >+ 61263970U, // MOV8rm_NOREX >+ 551817314U, // MOV8rr >+ 551817314U, // MOV8rr_NOREX >+ 551817314U, // MOV8rr_REV >+ 62952207U, // MOVAPDmr >+ 578319U, // MOVAPDrm >+ 551817999U, // MOVAPDrr >+ 551817999U, // MOVAPDrr_REV >+ 62956896U, // MOVAPSmr >+ 583008U, // MOVAPSrm >+ 551822688U, // MOVAPSrr >+ 551822688U, // MOVAPSrr_REV >+ 4238094U, // MOVBE16mr >+ 387854U, // MOVBE16rm >+ 12622236U, // MOVBE32mr >+ 551803292U, // MOVBE32rm >+ 18915299U, // MOVBE64mr >+ 551837667U, // MOVBE64rm >+ 597469U, // MOVDDUPrm >+ 551820765U, // MOVDDUPrr >+ 551802540U, // MOVDI2PDIrm >+ 551818924U, // MOVDI2PDIrr >+ 551802540U, // MOVDI2SSrm >+ 551818924U, // MOVDI2SSrr >+ 65048157U, // MOVDQAmr >+ 314973U, // MOVDQArm >+ 551816797U, // MOVDQArr >+ 551816797U, // MOVDQArr_REV >+ 65055128U, // MOVDQUmr >+ 321944U, // MOVDQUrm >+ 551823768U, // MOVDQUrr >+ 551823768U, // MOVDQUrr_REV >+ 8447540U, // MOVHLPSrr >+ 67146701U, // MOVHPDmr >+ 551703501U, // MOVHPDrm >+ 67151392U, // MOVHPSmr >+ 551708192U, // MOVHPSrm >+ 8447510U, // MOVLHPSrr >+ 67146751U, // MOVLPDmr >+ 551703551U, // MOVLPDrm >+ 67151452U, // MOVLPSmr >+ 551708252U, // MOVLPSrm >+ 551818198U, // MOVMSKPDrr >+ 551822889U, // MOVMSKPSrr >+ 314962U, // MOVNTDQArm >+ 62955429U, // MOVNTDQmr >+ 18915465U, // MOVNTI_64mr >+ 12622384U, // MOVNTImr >+ 62952532U, // MOVNTPDmr >+ 62957262U, // MOVNTPSmr >+ 67147261U, // MOVNTSD >+ 69249173U, // MOVNTSS >+ 0U, // MOVPC32r >+ 12621484U, // MOVPDI2DImr >+ 551818924U, // MOVPDI2DIrr >+ 18916063U, // MOVPQI2QImr >+ 551822047U, // MOVPQI2QIrr >+ 551818924U, // MOVPQIto64rr >+ 551838431U, // MOVQI2PQIrm >+ 856041U, // MOVSB >+ 67147302U, // MOVSDmr >+ 595494U, // MOVSDrm >+ 8443430U, // MOVSDrr >+ 8443430U, // MOVSDrr_REV >+ 18916063U, // MOVSDto64mr >+ 551818924U, // MOVSDto64rr >+ 581095U, // MOVSHDUPrm >+ 551820775U, // MOVSHDUPrr >+ 875566U, // MOVSL >+ 581106U, // MOVSLDUPrm >+ 551820786U, // MOVSLDUPrr >+ 893455U, // MOVSQ >+ 12621484U, // MOVSS2DImr >+ 551818924U, // MOVSS2DIrr >+ 69249224U, // MOVSSmr >+ 616648U, // MOVSSrm >+ 8448200U, // MOVSSrr >+ 8448200U, // MOVSSrr_REV >+ 912745U, // MOVSW >+ 453179U, // MOVSX16rm8 >+ 551823931U, // MOVSX16rr8 >+ 384199U, // MOVSX32rm16 >+ 448750U, // MOVSX32rm8 >+ 551820487U, // MOVSX32rr16 >+ 551819502U, // MOVSX32rr8 >+ 551821522U, // MOVSX64_NOREXrr32 >+ 385789U, // MOVSX64rm16 >+ 551805138U, // MOVSX64rm32 >+ 450122U, // MOVSX64rm8 >+ 551822077U, // MOVSX64rr16 >+ 551821522U, // MOVSX64rr32 >+ 551820874U, // MOVSX64rr8 >+ 62952560U, // MOVUPDmr >+ 578672U, // MOVUPDrm >+ 551818352U, // MOVUPDrr >+ 551818352U, // MOVUPDrr_REV >+ 62957335U, // MOVUPSmr >+ 583447U, // MOVUPSrm >+ 551823127U, // MOVUPSrr >+ 551823127U, // MOVUPSrr_REV >+ 320223U, // MOVZPQILo2PQIrm >+ 551822047U, // MOVZPQILo2PQIrr >+ 551838431U, // MOVZQI2PQIrm >+ 551818924U, // MOVZQI2PQIrr >+ 453245U, // MOVZX16rm8 >+ 551823997U, // MOVZX16rr8 >+ 448781U, // MOVZX32_NOREXrm8 >+ 551819533U, // MOVZX32_NOREXrr8 >+ 384207U, // MOVZX32rm16 >+ 448781U, // MOVZX32rm8 >+ 551820495U, // MOVZX32rr16 >+ 551819533U, // MOVZX32rr8 >+ 385830U, // MOVZX64rm16_Q >+ 450179U, // MOVZX64rm8_Q >+ 551822118U, // MOVZX64rr16_Q >+ 551820931U, // MOVZX64rr8_Q >+ 608528903U, // MPSADBWrmi >+ 570796551U, // MPSADBWrri >+ 224230U, // MUL16m >+ 27622U, // MUL16r >+ 236186U, // MUL32m >+ 23194U, // MUL32r >+ 401627U, // MUL64m >+ 24795U, // MUL64r >+ 429855U, // MUL8m >+ 20255U, // MUL8r >+ 8524791U, // MULPDrm >+ 8442871U, // MULPDrr >+ 8529492U, // MULPSrm >+ 8447572U, // MULPSrr >+ 551704029U, // MULSDrm >+ 551704029U, // MULSDrm_Int >+ 8443357U, // MULSDrr >+ 8443357U, // MULSDrr_Int >+ 551725174U, // MULSSrm >+ 551725174U, // MULSSrm_Int >+ 8448118U, // MULSSrr >+ 8448118U, // MULSSrr_Int >+ 283204837U, // MULX32rm >+ 811654373U, // MULX32rr >+ 283222844U, // MULX64rm >+ 811655996U, // MULX64rr >+ 189436U, // MUL_F32m >+ 203417U, // MUL_F64m >+ 222211U, // MUL_FI16m >+ 236192U, // MUL_FI32m >+ 23943U, // MUL_FPrST0 >+ 23717U, // MUL_FST0r >+ 0U, // MUL_Fp32 >+ 0U, // MUL_Fp32m >+ 0U, // MUL_Fp64 >+ 0U, // MUL_Fp64m >+ 0U, // MUL_Fp64m32 >+ 0U, // MUL_Fp80 >+ 0U, // MUL_Fp80m32 >+ 0U, // MUL_Fp80m64 >+ 0U, // MUL_FpI16m32 >+ 0U, // MUL_FpI16m64 >+ 0U, // MUL_FpI16m80 >+ 0U, // MUL_FpI32m32 >+ 0U, // MUL_FpI32m64 >+ 0U, // MUL_FpI32m80 >+ 28393U, // MUL_FrST0 >+ 15220U, // MWAITrr >+ 224078U, // NEG16m >+ 27470U, // NEG16r >+ 236035U, // NEG32m >+ 23043U, // NEG32r >+ 401500U, // NEG64m >+ 24668U, // NEG64r >+ 429789U, // NEG8m >+ 20189U, // NEG8r >+ 14705U, // NOOP >+ 224305U, // NOOP18_16m4 >+ 224305U, // NOOP18_16m5 >+ 224305U, // NOOP18_16m6 >+ 224305U, // NOOP18_16m7 >+ 27697U, // NOOP18_16r4 >+ 27697U, // NOOP18_16r5 >+ 27697U, // NOOP18_16r6 >+ 27697U, // NOOP18_16r7 >+ 236306U, // NOOP18_m4 >+ 236306U, // NOOP18_m5 >+ 236306U, // NOOP18_m6 >+ 236306U, // NOOP18_m7 >+ 23314U, // NOOP18_r4 >+ 23314U, // NOOP18_r5 >+ 23314U, // NOOP18_r6 >+ 23314U, // NOOP18_r7 >+ 283139502U, // NOOP19rr >+ 236306U, // NOOPL >+ 236306U, // NOOPL_19 >+ 236306U, // NOOPL_1a >+ 236306U, // NOOPL_1b >+ 236306U, // NOOPL_1c >+ 236306U, // NOOPL_1d >+ 236306U, // NOOPL_1e >+ 224305U, // NOOPW >+ 224305U, // NOOPW_19 >+ 224305U, // NOOPW_1a >+ 224305U, // NOOPW_1b >+ 224305U, // NOOPW_1c >+ 224305U, // NOOPW_1d >+ 224305U, // NOOPW_1e >+ 224722U, // NOT16m >+ 28114U, // NOT16r >+ 236675U, // NOT32m >+ 23683U, // NOT32r >+ 402032U, // NOT64m >+ 25200U, // NOT64r >+ 430089U, // NOT8m >+ 20489U, // NOT8r >+ 2124919U, // OR16i16 >+ 4238455U, // OR16mi >+ 4238455U, // OR16mi8 >+ 4238455U, // OR16mr >+ 6351991U, // OR16ri >+ 6351991U, // OR16ri8 >+ 6368375U, // OR16rm >+ 6351991U, // OR16rr >+ 8449143U, // OR16rr_REV >+ 10509189U, // OR32i32 >+ 12622725U, // OR32mi >+ 12622725U, // OR32mi8 >+ 12622725U, // OR32mr >+ 12622725U, // OR32mrLocked >+ 6347653U, // OR32ri >+ 6347653U, // OR32ri8 >+ 283204485U, // OR32rm >+ 6347653U, // OR32rr >+ 8444805U, // OR32rr_REV >+ 16802158U, // OR64i32 >+ 18915694U, // OR64mi32 >+ 18915694U, // OR64mi8 >+ 18915694U, // OR64mr >+ 6349166U, // OR64ri32 >+ 6349166U, // OR64ri8 >+ 283222382U, // OR64rm >+ 6349166U, // OR64rr >+ 8446318U, // OR64rr_REV >+ 20991847U, // OR8i8 >+ 23105383U, // OR8mi >+ 23105383U, // OR8mr >+ 6344551U, // OR8ri >+ 6344551U, // OR8ri8 >+ 118631U, // OR8rm >+ 6344551U, // OR8rr >+ 8441703U, // OR8rr_REV >+ 8524869U, // ORPDrm >+ 8442949U, // ORPDrr >+ 8529587U, // ORPSrm >+ 8447667U, // ORPSrr >+ 29283U, // OUT16ir >+ 15523U, // OUT16rr >+ 29333U, // OUT32ir >+ 15537U, // OUT32rr >+ 28811U, // OUT8ir >+ 15509U, // OUT8rr >+ 74125253U, // OUTSB >+ 74144806U, // OUTSL >+ 74181965U, // OUTSW >+ 315276U, // PABSBrm128 >+ 551817100U, // PABSBrr128 >+ 316798U, // PABSDrm128 >+ 551818622U, // PABSDrr128 >+ 322740U, // PABSWrm128 >+ 551824564U, // PABSWrr128 >+ 8694511U, // PACKSSDWrm >+ 8448751U, // PACKSSDWrr >+ 8687721U, // PACKSSWBrm >+ 8441961U, // PACKSSWBrr >+ 8694522U, // PACKUSDWrm >+ 8448762U, // PACKUSDWrr >+ 8687732U, // PACKUSWBrm >+ 8441972U, // PACKUSWBrr >+ 8687296U, // PADDBrm >+ 8441536U, // PADDBrr >+ 8687913U, // PADDDrm >+ 8442153U, // PADDDrr >+ 8691438U, // PADDQrm >+ 8445678U, // PADDQrr >+ 8687526U, // PADDSBrm >+ 8441766U, // PADDSBrr >+ 8695022U, // PADDSWrm >+ 8449262U, // PADDSWrr >+ 8687575U, // PADDUSBrm >+ 8441815U, // PADDUSBrr >+ 8695135U, // PADDUSWrm >+ 8449375U, // PADDUSWrr >+ 8694454U, // PADDWrm >+ 8448694U, // PADDWrr >+ 608527224U, // PALIGNR128rm >+ 570794872U, // PALIGNR128rr >+ 8691003U, // PANDNrm >+ 8445243U, // PANDNrr >+ 8688074U, // PANDrm >+ 8442314U, // PANDrr >+ 14359U, // PAUSE >+ 8687342U, // PAVGBrm >+ 8441582U, // PAVGBrr >+ 551653344U, // PAVGUSBrm >+ 8441824U, // PAVGUSBrr >+ 8694623U, // PAVGWrm >+ 8448863U, // PAVGWrr >+ 8687695U, // PBLENDVBrm0 >+ 8441935U, // PBLENDVBrr0 >+ 608529118U, // PBLENDWrmi >+ 570796766U, // PBLENDWrri >+ 608526189U, // PCLMULQDQrm >+ 570793837U, // PCLMULQDQrr >+ 8687435U, // PCMPEQBrm >+ 8441675U, // PCMPEQBrr >+ 8688809U, // PCMPEQDrm >+ 8443049U, // PCMPEQDrr >+ 8692032U, // PCMPEQQrm >+ 8446272U, // PCMPEQQrr >+ 8694854U, // PCMPEQWrm >+ 8449094U, // PCMPEQWrr >+ 0U, // PCMPESTRIMEM >+ 0U, // PCMPESTRIREG >+ 25499774U, // PCMPESTRIrm >+ 811653246U, // PCMPESTRIrr >+ 0U, // PCMPESTRM128MEM >+ 0U, // PCMPESTRM128REG >+ 25500963U, // PCMPESTRM128rm >+ 811654435U, // PCMPESTRM128rr >+ 8687616U, // PCMPGTBrm >+ 8441856U, // PCMPGTBrr >+ 8689224U, // PCMPGTDrm >+ 8443464U, // PCMPGTDrr >+ 8692294U, // PCMPGTQrm >+ 8446534U, // PCMPGTQrr >+ 8695216U, // PCMPGTWrm >+ 8449456U, // PCMPGTWrr >+ 0U, // PCMPISTRIMEM >+ 0U, // PCMPISTRIREG >+ 25499786U, // PCMPISTRIrm >+ 811653258U, // PCMPISTRIrr >+ 0U, // PCMPISTRM128MEM >+ 0U, // PCMPISTRM128REG >+ 25500975U, // PCMPISTRM128rm >+ 811654447U, // PCMPISTRM128rr >+ 283204324U, // PDEP32rm >+ 811653860U, // PDEP32rr >+ 283222297U, // PDEP64rm >+ 811655449U, // PDEP64rr >+ 283204765U, // PEXT32rm >+ 811654301U, // PEXT32rr >+ 283222695U, // PEXT64rm >+ 811655847U, // PEXT64rr >+ 587534204U, // PEXTRBmr >+ 811650940U, // PEXTRBrr >+ 855971016U, // PEXTRDmr >+ 811652296U, // PEXTRDrr >+ 1124409774U, // PEXTRQmr >+ 811655598U, // PEXTRQrr >+ 1392848036U, // PEXTRWmr >+ 811658404U, // PEXTRWri >+ 811658404U, // PEXTRWrr_REV >+ 551833963U, // PF2IDrm >+ 551817579U, // PF2IDrr >+ 551840659U, // PF2IWrm >+ 551824275U, // PF2IWrr >+ 551653502U, // PFACCrm >+ 8441982U, // PFACCrr >+ 551653656U, // PFADDrm >+ 8442136U, // PFADDrr >+ 551657478U, // PFCMPEQrm >+ 8445958U, // PFCMPEQrr >+ 551655283U, // PFCMPGErm >+ 8443763U, // PFCMPGErr >+ 551659784U, // PFCMPGTrm >+ 8448264U, // PFCMPGTrr >+ 551661143U, // PFMAXrm >+ 8449623U, // PFMAXrr >+ 551656778U, // PFMINrm >+ 8445258U, // PFMINrr >+ 551656612U, // PFMULrm >+ 8445092U, // PFMULrr >+ 551653509U, // PFNACCrm >+ 8441989U, // PFNACCrr >+ 551653517U, // PFPNACCrm >+ 8441997U, // PFPNACCrr >+ 551652562U, // PFRCPIT1rm >+ 8441042U, // PFRCPIT1rr >+ 551652651U, // PFRCPIT2rm >+ 8441131U, // PFRCPIT2rr >+ 551837045U, // PFRCPrm >+ 551820661U, // PFRCPrr >+ 551652572U, // PFRSQIT1rm >+ 8441052U, // PFRSQIT1rr >+ 551840055U, // PFRSQRTrm >+ 551823671U, // PFRSQRTrr >+ 551658344U, // PFSUBRrm >+ 8446824U, // PFSUBRrr >+ 551653438U, // PFSUBrm >+ 8441918U, // PFSUBrr >+ 8687904U, // PHADDDrm >+ 8442144U, // PHADDDrr >+ 8695012U, // PHADDSWrm128 >+ 8449252U, // PHADDSWrr128 >+ 8694445U, // PHADDWrm >+ 8448685U, // PHADDWrr >+ 323090U, // PHMINPOSUWrm128 >+ 551824914U, // PHMINPOSUWrr128 >+ 8687858U, // PHSUBDrm >+ 8442098U, // PHSUBDrr >+ 8694993U, // PHSUBSWrm128 >+ 8449233U, // PHSUBSWrr128 >+ 8694351U, // PHSUBWrm >+ 8448591U, // PHSUBWrr >+ 551833947U, // PI2FDrm >+ 551817563U, // PI2FDrr >+ 551840569U, // PI2FWrm >+ 551824185U, // PI2FWrr >+ 612716403U, // PINSRBrm >+ 570789747U, // PINSRBrr >+ 614814911U, // PINSRDrm >+ 570791103U, // PINSRDrr >+ 593846673U, // PINSRQrm >+ 570794385U, // PINSRQrr >+ 595946633U, // PINSRWrmi >+ 570797193U, // PINSRWrri >+ 8694981U, // PMADDUBSWrm128 >+ 8449221U, // PMADDUBSWrr128 >+ 8689358U, // PMADDWDrm >+ 8443598U, // PMADDWDrr >+ 8687601U, // PMAXSBrm >+ 8441841U, // PMAXSBrr >+ 8689198U, // PMAXSDrm >+ 8443438U, // PMAXSDrr >+ 8695153U, // PMAXSWrm >+ 8449393U, // PMAXSWrr >+ 8687686U, // PMAXUBrm >+ 8441926U, // PMAXUBrr >+ 8689283U, // PMAXUDrm >+ 8443523U, // PMAXUDrr >+ 8695327U, // PMAXUWrm >+ 8449567U, // PMAXUWrr >+ 8687542U, // PMINSBrm >+ 8441782U, // PMINSBrr >+ 8689125U, // PMINSDrm >+ 8443365U, // PMINSDrr >+ 8695062U, // PMINSWrm >+ 8449302U, // PMINSWrr >+ 8687670U, // PMINUBrm >+ 8441910U, // PMINUBrr >+ 8689265U, // PMINUDrm >+ 8443505U, // PMINUDrr >+ 8695305U, // PMINUWrm >+ 8449545U, // PMINUWrr >+ 551816954U, // PMOVMSKBrr >+ 551801091U, // PMOVSXBDrm >+ 551817475U, // PMOVSXBDrr >+ 384622U, // PMOVSXBQrm >+ 551820910U, // PMOVSXBQrr >+ 551840360U, // PMOVSXBWrm >+ 551823976U, // PMOVSXBWrr >+ 551837636U, // PMOVSXDQrm >+ 551821252U, // PMOVSXDQrr >+ 551835431U, // PMOVSXWDrm >+ 551819047U, // PMOVSXWDrr >+ 551805713U, // PMOVSXWQrm >+ 551822097U, // PMOVSXWQrr >+ 551801102U, // PMOVZXBDrm >+ 551817486U, // PMOVZXBDrr >+ 384633U, // PMOVZXBQrm >+ 551820921U, // PMOVZXBQrr >+ 551840371U, // PMOVZXBWrm >+ 551823987U, // PMOVZXBWrr >+ 551837647U, // PMOVZXDQrm >+ 551821263U, // PMOVZXDQrr >+ 551835442U, // PMOVZXWDrm >+ 551819058U, // PMOVZXWDrr >+ 551805724U, // PMOVZXWQrm >+ 551822108U, // PMOVZXWQrr >+ 8691521U, // PMULDQrm >+ 8445761U, // PMULDQrr >+ 8695087U, // PMULHRSWrm128 >+ 8449327U, // PMULHRSWrr128 >+ 551660647U, // PMULHRWrm >+ 8449127U, // PMULHRWrr >+ 8695286U, // PMULHUWrm >+ 8449526U, // PMULHUWrr >+ 8694660U, // PMULHWrm >+ 8448900U, // PMULHWrr >+ 8688032U, // PMULLDrm >+ 8442272U, // PMULLDrr >+ 8694729U, // PMULLWrm >+ 8448969U, // PMULLWrr >+ 8691642U, // PMULUDQrm >+ 8445882U, // PMULUDQrr >+ 27703U, // POP16r >+ 224311U, // POP16rmm >+ 27703U, // POP16rmr >+ 23320U, // POP32r >+ 236312U, // POP32rmm >+ 23320U, // POP32rmr >+ 24881U, // POP64r >+ 401713U, // POP64rmm >+ 24881U, // POP64rmr >+ 15289U, // POPA16 >+ 14492U, // POPA32 >+ 388537U, // POPCNT16rm >+ 551824825U, // POPCNT16rr >+ 551804010U, // POPCNT32rm >+ 551820394U, // POPCNT32rr >+ 551838287U, // POPCNT64rm >+ 551821903U, // POPCNT64rr >+ 14919U, // POPDS16 >+ 14900U, // POPDS32 >+ 14957U, // POPES16 >+ 14938U, // POPES32 >+ 15302U, // POPF16 >+ 14505U, // POPF32 >+ 14747U, // POPF64 >+ 15014U, // POPFS16 >+ 14976U, // POPFS32 >+ 14995U, // POPFS64 >+ 15071U, // POPGS16 >+ 15033U, // POPGS32 >+ 15052U, // POPGS64 >+ 15191U, // POPSS16 >+ 15172U, // POPSS32 >+ 8692610U, // PORrm >+ 8446850U, // PORrr >+ 432114U, // PREFETCH >+ 429675U, // PREFETCHNTA >+ 429220U, // PREFETCHT0 >+ 429254U, // PREFETCHT1 >+ 429343U, // PREFETCHT2 >+ 437102U, // PREFETCHW >+ 8694280U, // PSADBWrm >+ 8448520U, // PSADBWrr >+ 8687317U, // PSHUFBrm >+ 8441557U, // PSHUFBrr >+ 25497955U, // PSHUFDmi >+ 811651427U, // PSHUFDri >+ 25504634U, // PSHUFHWmi >+ 811658106U, // PSHUFHWri >+ 25504679U, // PSHUFLWmi >+ 811658151U, // PSHUFLWri >+ 8687406U, // PSIGNBrm >+ 8441646U, // PSIGNBrr >+ 8688081U, // PSIGNDrm >+ 8442321U, // PSIGNDrr >+ 8694781U, // PSIGNWrm >+ 8449021U, // PSIGNWrr >+ 8445743U, // PSLLDQri >+ 8442264U, // PSLLDri >+ 8688024U, // PSLLDrm >+ 8442264U, // PSLLDrr >+ 8446135U, // PSLLQri >+ 8691895U, // PSLLQrm >+ 8446135U, // PSLLQrr >+ 8448961U, // PSLLWri >+ 8694721U, // PSLLWrm >+ 8448961U, // PSLLWrr >+ 8442069U, // PSRADri >+ 8687829U, // PSRADrm >+ 8442069U, // PSRADrr >+ 8448487U, // PSRAWri >+ 8694247U, // PSRAWrm >+ 8448487U, // PSRAWrr >+ 8445752U, // PSRLDQri >+ 8442281U, // PSRLDri >+ 8688041U, // PSRLDrm >+ 8442281U, // PSRLDrr >+ 8446149U, // PSRLQri >+ 8691909U, // PSRLQrm >+ 8446149U, // PSRLQrr >+ 8448984U, // PSRLWri >+ 8694744U, // PSRLWrm >+ 8448984U, // PSRLWrr >+ 8687270U, // PSUBBrm >+ 8441510U, // PSUBBrr >+ 8687867U, // PSUBDrm >+ 8442107U, // PSUBDrr >+ 8691294U, // PSUBQrm >+ 8445534U, // PSUBQrr >+ 8687517U, // PSUBSBrm >+ 8441757U, // PSUBSBrr >+ 8695003U, // PSUBSWrm >+ 8449243U, // PSUBSWrr >+ 8687565U, // PSUBUSBrm >+ 8441805U, // PSUBUSBrr >+ 8695125U, // PSUBUSWrm >+ 8449365U, // PSUBUSWrr >+ 8694360U, // PSUBWrm >+ 8448600U, // PSUBWrr >+ 551834391U, // PSWAPDrm >+ 551818007U, // PSWAPDrr >+ 584027U, // PTESTrm >+ 551823707U, // PTESTrr >+ 8694308U, // PUNPCKHBWrm >+ 8448548U, // PUNPCKHBWrr >+ 8691472U, // PUNPCKHDQrm >+ 8445712U, // PUNPCKHDQrr >+ 8691539U, // PUNPCKHQDQrm >+ 8445779U, // PUNPCKHQDQrr >+ 8689368U, // PUNPCKHWDrm >+ 8443608U, // PUNPCKHWDrr >+ 8694320U, // PUNPCKLBWrm >+ 8448560U, // PUNPCKLBWrr >+ 8691491U, // PUNPCKLDQrm >+ 8445731U, // PUNPCKLDQrr >+ 8691552U, // PUNPCKLQDQrm >+ 8445792U, // PUNPCKLQDQrr >+ 8689380U, // PUNPCKLWDrm >+ 8443620U, // PUNPCKLWDrr >+ 27532U, // PUSH16i8 >+ 27532U, // PUSH16r >+ 224140U, // PUSH16rmm >+ 27532U, // PUSH16rmr >+ 23067U, // PUSH32i8 >+ 23067U, // PUSH32r >+ 236059U, // PUSH32rmm >+ 23067U, // PUSH32rmr >+ 27532U, // PUSH64i16 >+ 24692U, // PUSH64i32 >+ 24692U, // PUSH64i8 >+ 24692U, // PUSH64r >+ 401524U, // PUSH64rmm >+ 24692U, // PUSH64rmr >+ 15282U, // PUSHA16 >+ 14485U, // PUSHA32 >+ 14880U, // PUSHCS16 >+ 14870U, // PUSHCS32 >+ 14909U, // PUSHDS16 >+ 14890U, // PUSHDS32 >+ 14947U, // PUSHES16 >+ 14928U, // PUSHES32 >+ 15295U, // PUSHF16 >+ 14498U, // PUSHF32 >+ 14740U, // PUSHF64 >+ 15004U, // PUSHFS16 >+ 14966U, // PUSHFS32 >+ 14985U, // PUSHFS64 >+ 15061U, // PUSHGS16 >+ 15023U, // PUSHGS32 >+ 15042U, // PUSHGS64 >+ 15181U, // PUSHSS16 >+ 15162U, // PUSHSS32 >+ 27532U, // PUSHi16 >+ 23067U, // PUSHi32 >+ 8692633U, // PXORrm >+ 8446873U, // PXORrr >+ 225323U, // RCL16m1 >+ 225788U, // RCL16mCL >+ 4238240U, // RCL16mi >+ 28715U, // RCL16r1 >+ 29180U, // RCL16rCL >+ 8448928U, // RCL16ri >+ 242562U, // RCL32m1 >+ 241948U, // RCL32mCL >+ 12622412U, // RCL32mi >+ 28555U, // RCL32r1 >+ 28956U, // RCL32rCL >+ 8444492U, // RCL32ri >+ 405467U, // RCL64m1 >+ 405900U, // RCL64mCL >+ 18915489U, // RCL64mi >+ 28635U, // RCL64r1 >+ 29068U, // RCL64rCL >+ 8446113U, // RCL64ri >+ 438075U, // RCL8m1 >+ 438444U, // RCL8mCL >+ 23105290U, // RCL8mi >+ 28475U, // RCL8r1 >+ 28844U, // RCL8rCL >+ 8441610U, // RCL8ri >+ 583312U, // RCPPSm >+ 583312U, // RCPPSm_Int >+ 551822992U, // RCPPSr >+ 551822992U, // RCPPSr_Int >+ 616582U, // RCPSSm >+ 551725190U, // RCPSSm_Int >+ 551823494U, // RCPSSr >+ 8448134U, // RCPSSr_Int >+ 225363U, // RCR16m1 >+ 225832U, // RCR16mCL >+ 4238427U, // RCR16mi >+ 28755U, // RCR16r1 >+ 29224U, // RCR16rCL >+ 8449115U, // RCR16ri >+ 241587U, // RCR32m1 >+ 241992U, // RCR32mCL >+ 12622712U, // RCR32mi >+ 28595U, // RCR32r1 >+ 29000U, // RCR32rCL >+ 8444792U, // RCR32ri >+ 405507U, // RCR64m1 >+ 405944U, // RCR64mCL >+ 18915681U, // RCR64mi >+ 28675U, // RCR64r1 >+ 29112U, // RCR64rCL >+ 8446305U, // RCR64ri >+ 438115U, // RCR8m1 >+ 438488U, // RCR8mCL >+ 23105370U, // RCR8mi >+ 28515U, // RCR8r1 >+ 28888U, // RCR8rCL >+ 8441690U, // RCR8ri >+ 22975U, // RDFSBASE >+ 24591U, // RDFSBASE64 >+ 22997U, // RDGSBASE >+ 24613U, // RDGSBASE64 >+ 14835U, // RDMSR >+ 14225U, // RDPMC >+ 27348U, // RDRAND16r >+ 22889U, // RDRAND32r >+ 24393U, // RDRAND64r >+ 27332U, // RDSEED16r >+ 22860U, // RDSEED32r >+ 24326U, // RDSEED64r >+ 14238U, // RDTSC >+ 14682U, // RDTSCP >+ 13701U, // RELEASE_MOV16mr >+ 13701U, // RELEASE_MOV32mr >+ 13701U, // RELEASE_MOV64mr >+ 13701U, // RELEASE_MOV8mr >+ 14328U, // REPNE_PREFIX >+ 14169U, // REP_MOVSB_32 >+ 14169U, // REP_MOVSB_64 >+ 14553U, // REP_MOVSD_32 >+ 14553U, // REP_MOVSD_64 >+ 14763U, // REP_MOVSQ_64 >+ 15318U, // REP_MOVSW_32 >+ 15318U, // REP_MOVSW_64 >+ 14689U, // REP_PREFIX >+ 14159U, // REP_STOSB_32 >+ 14159U, // REP_STOSB_64 >+ 14543U, // REP_STOSD_32 >+ 14543U, // REP_STOSD_64 >+ 14753U, // REP_STOSQ_64 >+ 15308U, // REP_STOSW_32 >+ 15308U, // REP_STOSW_64 >+ 23646U, // RETIL >+ 25151U, // RETIQ >+ 28073U, // RETIW >+ 14564U, // RETL >+ 14774U, // RETQ >+ 15334U, // RETW >+ 13995U, // REX64_PREFIX >+ 225343U, // ROL16m1 >+ 225810U, // ROL16mCL >+ 4238289U, // ROL16mi >+ 28735U, // ROL16r1 >+ 29202U, // ROL16rCL >+ 8448977U, // ROL16ri >+ 241567U, // ROL32m1 >+ 241970U, // ROL32mCL >+ 12622458U, // ROL32mi >+ 28575U, // ROL32r1 >+ 28978U, // ROL32rCL >+ 8444538U, // ROL32ri >+ 405487U, // ROL64m1 >+ 405922U, // ROL64mCL >+ 18915518U, // ROL64mi >+ 28655U, // ROL64r1 >+ 29090U, // ROL64rCL >+ 8446142U, // ROL64ri >+ 438095U, // ROL8m1 >+ 438466U, // ROL8mCL >+ 23105304U, // ROL8mi >+ 28495U, // ROL8r1 >+ 28866U, // ROL8rCL >+ 8441624U, // ROL8ri >+ 225383U, // ROR16m1 >+ 225854U, // ROR16mCL >+ 4238454U, // ROR16mi >+ 28775U, // ROR16r1 >+ 29246U, // ROR16rCL >+ 8449142U, // ROR16ri >+ 241607U, // ROR32m1 >+ 242014U, // ROR32mCL >+ 12622724U, // ROR32mi >+ 28615U, // ROR32r1 >+ 29022U, // ROR32rCL >+ 8444804U, // ROR32ri >+ 405527U, // ROR64m1 >+ 405966U, // ROR64mCL >+ 18915693U, // ROR64mi >+ 28695U, // ROR64r1 >+ 29134U, // ROR64rCL >+ 8446317U, // ROR64ri >+ 438135U, // ROR8m1 >+ 438510U, // ROR8mCL >+ 23105382U, // ROR8mi >+ 28535U, // ROR8r1 >+ 28910U, // ROR8rCL >+ 8441702U, // ROR8ri >+ 832904449U, // RORX32mi >+ 811654401U, // RORX32ri >+ 835003224U, // RORX64mi >+ 811656024U, // RORX64ri >+ 80024483U, // ROUNDPDm >+ 811652003U, // ROUNDPDr >+ 80029164U, // ROUNDPSm >+ 811656684U, // ROUNDPSr >+ 581260736U, // ROUNDSDm >+ 570791360U, // ROUNDSDr >+ 570791360U, // ROUNDSDr_Int >+ 585459801U, // ROUNDSSm >+ 570796121U, // ROUNDSSr >+ 570796121U, // ROUNDSSr_Int >+ 14623U, // RSM >+ 583395U, // RSQRTPSm >+ 583395U, // RSQRTPSm_Int >+ 551823075U, // RSQRTPSr >+ 551823075U, // RSQRTPSr_Int >+ 616607U, // RSQRTSSm >+ 551725215U, // RSQRTSSm_Int >+ 551823519U, // RSQRTSSr >+ 8448159U, // RSQRTSSr_Int >+ 14414U, // SAHF >+ 225313U, // SAL16m1 >+ 225777U, // SAL16mCL >+ 4238234U, // SAL16mi >+ 28705U, // SAL16r1 >+ 29169U, // SAL16rCL >+ 8448922U, // SAL16ri >+ 241537U, // SAL32m1 >+ 241937U, // SAL32mCL >+ 12622406U, // SAL32mi >+ 28545U, // SAL32r1 >+ 28945U, // SAL32rCL >+ 8444486U, // SAL32ri >+ 405457U, // SAL64m1 >+ 405889U, // SAL64mCL >+ 18915483U, // SAL64mi >+ 28625U, // SAL64r1 >+ 29057U, // SAL64rCL >+ 8446107U, // SAL64ri >+ 438065U, // SAL8m1 >+ 438433U, // SAL8mCL >+ 23105284U, // SAL8mi >+ 28465U, // SAL8r1 >+ 28833U, // SAL8rCL >+ 8441604U, // SAL8ri >+ 14212U, // SALC >+ 225353U, // SAR16m1 >+ 225821U, // SAR16mCL >+ 4238421U, // SAR16mi >+ 28745U, // SAR16r1 >+ 29213U, // SAR16rCL >+ 8449109U, // SAR16ri >+ 241577U, // SAR32m1 >+ 241981U, // SAR32mCL >+ 12622689U, // SAR32mi >+ 28585U, // SAR32r1 >+ 28989U, // SAR32rCL >+ 8444769U, // SAR32ri >+ 405497U, // SAR64m1 >+ 405933U, // SAR64mCL >+ 18915675U, // SAR64mi >+ 28665U, // SAR64r1 >+ 29101U, // SAR64rCL >+ 8446299U, // SAR64ri >+ 438105U, // SAR8m1 >+ 438477U, // SAR8mCL >+ 23105364U, // SAR8mi >+ 28505U, // SAR8r1 >+ 28877U, // SAR8rCL >+ 8441684U, // SAR8ri >+ 832904435U, // SARX32rm >+ 811654387U, // SARX32rr >+ 835003210U, // SARX64rm >+ 811656010U, // SARX64rr >+ 2124278U, // SBB16i16 >+ 4237814U, // SBB16mi >+ 4237814U, // SBB16mi8 >+ 4237814U, // SBB16mr >+ 6351350U, // SBB16ri >+ 6351350U, // SBB16ri8 >+ 6367734U, // SBB16rm >+ 6351350U, // SBB16rr >+ 8448502U, // SBB16rr_REV >+ 10508520U, // SBB32i32 >+ 12622056U, // SBB32mi >+ 12622056U, // SBB32mi8 >+ 12622056U, // SBB32mr >+ 6346984U, // SBB32ri >+ 6346984U, // SBB32ri8 >+ 283203816U, // SBB32rm >+ 6346984U, // SBB32rr >+ 8444136U, // SBB32rr_REV >+ 16801338U, // SBB64i32 >+ 18914874U, // SBB64mi32 >+ 18914874U, // SBB64mi8 >+ 18914874U, // SBB64mr >+ 6348346U, // SBB64ri32 >+ 6348346U, // SBB64ri8 >+ 283221562U, // SBB64rm >+ 6348346U, // SBB64rr >+ 8445498U, // SBB64rr_REV >+ 20991647U, // SBB8i8 >+ 23105183U, // SBB8mi >+ 23105183U, // SBB8mr >+ 6344351U, // SBB8ri >+ 118431U, // SBB8rm >+ 6344351U, // SBB8rr >+ 8441503U, // SBB8rr_REV >+ 21467012U, // SCASB >+ 11000770U, // SCASL >+ 17310134U, // SCASQ >+ 2649260U, // SCASW >+ 15092U, // SEG_ALLOCA_32 >+ 15092U, // SEG_ALLOCA_64 >+ 14379U, // SEH_EndPrologue >+ 14365U, // SEH_Epilogue >+ 29668U, // SEH_PushFrame >+ 29713U, // SEH_PushReg >+ 283145219U, // SEH_SaveReg >+ 283145133U, // SEH_SaveXMM >+ 283145204U, // SEH_SetFrame >+ 29651U, // SEH_StackAlloc >+ 431937U, // SETAEm >+ 22337U, // SETAEr >+ 429669U, // SETAm >+ 20069U, // SETAr >+ 431959U, // SETBEm >+ 22359U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 430073U, // SETBm >+ 20473U, // SETBr >+ 432055U, // SETEm >+ 22455U, // SETEr >+ 431996U, // SETGEm >+ 22396U, // SETGEr >+ 432108U, // SETGm >+ 22508U, // SETGr >+ 432012U, // SETLEm >+ 22412U, // SETLEr >+ 433252U, // SETLm >+ 23652U, // SETLr >+ 432032U, // SETNEm >+ 22432U, // SETNEr >+ 433505U, // SETNOm >+ 23905U, // SETNOr >+ 433575U, // SETNPm >+ 23975U, // SETNPr >+ 435231U, // SETNSm >+ 25631U, // SETNSr >+ 433512U, // SETOm >+ 23912U, // SETOr >+ 433609U, // SETPm >+ 24009U, // SETPr >+ 436448U, // SETSm >+ 26848U, // SETSr >+ 14305U, // SFENCE >+ 634245U, // SGDT16m >+ 629825U, // SGDT32m >+ 631330U, // SGDT64m >+ 8686768U, // SHA1MSG1rm >+ 8441008U, // SHA1MSG1rr >+ 8686844U, // SHA1MSG2rm >+ 8441084U, // SHA1MSG2rr >+ 8689597U, // SHA1NEXTErm >+ 8443837U, // SHA1NEXTErr >+ 608521547U, // SHA1RNDS4rmi >+ 570789195U, // SHA1RNDS4rri >+ 8686778U, // SHA256MSG1rm >+ 8441018U, // SHA256MSG1rr >+ 8686854U, // SHA256MSG2rm >+ 8441094U, // SHA256MSG2rr >+ 8686866U, // SHA256RNDS2rm >+ 8441106U, // SHA256RNDS2rr >+ 225333U, // SHL16m1 >+ 225799U, // SHL16mCL >+ 4238258U, // SHL16mi >+ 28725U, // SHL16r1 >+ 29191U, // SHL16rCL >+ 8448946U, // SHL16ri >+ 241557U, // SHL32m1 >+ 241959U, // SHL32mCL >+ 12622426U, // SHL32mi >+ 28565U, // SHL32r1 >+ 28967U, // SHL32rCL >+ 8444506U, // SHL32ri >+ 405477U, // SHL64m1 >+ 405911U, // SHL64mCL >+ 18915497U, // SHL64mi >+ 28645U, // SHL64r1 >+ 29079U, // SHL64rCL >+ 8446121U, // SHL64ri >+ 438085U, // SHL8m1 >+ 438455U, // SHL8mCL >+ 23105298U, // SHL8mi >+ 28485U, // SHL8r1 >+ 28855U, // SHL8rCL >+ 8441618U, // SHL8ri >+ 4239833U, // SHLD16mrCL >+ 1392847565U, // SHLD16mri8 >+ 8450521U, // SHLD16rrCL >+ 570796749U, // SHLD16rri8 >+ 12628217U, // SHLD32mrCL >+ 855972187U, // SHLD32mri8 >+ 8450297U, // SHLD32rrCL >+ 570792283U, // SHLD32rri8 >+ 18919785U, // SHLD64mrCL >+ 1124409115U, // SHLD64mri8 >+ 8450409U, // SHLD64rrCL >+ 570793755U, // SHLD64rri8 >+ 832904414U, // SHLX32rm >+ 811654366U, // SHLX32rr >+ 835003189U, // SHLX64rm >+ 811655989U, // SHLX64rr >+ 225373U, // SHR16m1 >+ 225843U, // SHR16mCL >+ 4238448U, // SHR16mi >+ 28765U, // SHR16r1 >+ 29235U, // SHR16rCL >+ 8449136U, // SHR16ri >+ 241597U, // SHR32m1 >+ 242003U, // SHR32mCL >+ 12622718U, // SHR32mi >+ 28605U, // SHR32r1 >+ 29011U, // SHR32rCL >+ 8444798U, // SHR32ri >+ 405517U, // SHR64m1 >+ 405955U, // SHR64mCL >+ 18915687U, // SHR64mi >+ 28685U, // SHR64r1 >+ 29123U, // SHR64rCL >+ 8446311U, // SHR64ri >+ 438125U, // SHR8m1 >+ 438499U, // SHR8mCL >+ 23105376U, // SHR8mi >+ 28525U, // SHR8r1 >+ 28899U, // SHR8rCL >+ 8441696U, // SHR8ri >+ 4239845U, // SHRD16mrCL >+ 1392847591U, // SHRD16mri8 >+ 8450533U, // SHRD16rrCL >+ 570796775U, // SHRD16rri8 >+ 12628229U, // SHRD32mrCL >+ 855972210U, // SHRD32mri8 >+ 8450309U, // SHRD32rrCL >+ 570792306U, // SHRD32rri8 >+ 18919797U, // SHRD64mrCL >+ 1124409220U, // SHRD64mri8 >+ 8450421U, // SHRD64rrCL >+ 570793860U, // SHRD64rri8 >+ 832904442U, // SHRX32rm >+ 811654394U, // SHRX32rr >+ 835003217U, // SHRX64rm >+ 811656017U, // SHRX64rr >+ 568677305U, // SHUFPDrmi >+ 570790841U, // SHUFPDrri >+ 568681986U, // SHUFPSrmi >+ 570795522U, // SHUFPSrri >+ 634259U, // SIDT16m >+ 629839U, // SIDT32m >+ 631344U, // SIDT64m >+ 14640U, // SIN_F >+ 0U, // SIN_Fp32 >+ 0U, // SIN_Fp64 >+ 0U, // SIN_Fp80 >+ 15410U, // SKINIT >+ 224673U, // SLDT16m >+ 28065U, // SLDT16r >+ 23638U, // SLDT32r >+ 221751U, // SLDT64m >+ 25143U, // SLDT64r >+ 224837U, // SMSW16m >+ 28229U, // SMSW16r >+ 23744U, // SMSW32r >+ 25334U, // SMSW64r >+ 578654U, // SQRTPDm >+ 551818334U, // SQRTPDr >+ 583396U, // SQRTPSm >+ 551823076U, // SQRTPSr >+ 595463U, // SQRTSDm >+ 595463U, // SQRTSDm_Int >+ 551818759U, // SQRTSDr >+ 551818759U, // SQRTSDr_Int >+ 616608U, // SQRTSSm >+ 616608U, // SQRTSSm_Int >+ 551823520U, // SQRTSSr >+ 551823520U, // SQRTSSr_Int >+ 15245U, // SQRT_F >+ 0U, // SQRT_Fp32 >+ 0U, // SQRT_Fp64 >+ 0U, // SQRT_Fp80 >+ 14190U, // STAC >+ 14244U, // STC >+ 14268U, // STD >+ 14433U, // STGI >+ 14448U, // STI >+ 238512U, // STMXCSR >+ 503935U, // STOSB >+ 520840U, // STOSL >+ 537276U, // STOSQ >+ 553559U, // STOSW >+ 27805U, // STR16r >+ 23459U, // STR32r >+ 24991U, // STR64r >+ 224413U, // STRm >+ 190694U, // ST_F32m >+ 203920U, // ST_F64m >+ 35675539U, // ST_FCOMPST0r >+ 35675539U, // ST_FCOMPST0r_alt >+ 35675405U, // ST_FCOMST0r >+ 190206U, // ST_FP32m >+ 203556U, // ST_FP64m >+ 715048U, // ST_FP80m >+ 28376U, // ST_FPNCEST0r >+ 28407U, // ST_FPST0r >+ 28407U, // ST_FPST0r_alt >+ 24022U, // ST_FPrr >+ 35674108U, // ST_FXCHST0r >+ 35674108U, // ST_FXCHST0r_alt >+ 0U, // ST_Fp32m >+ 0U, // ST_Fp64m >+ 0U, // ST_Fp64m32 >+ 0U, // ST_Fp80m32 >+ 0U, // ST_Fp80m64 >+ 0U, // ST_FpP32m >+ 0U, // ST_FpP64m >+ 0U, // ST_FpP64m32 >+ 0U, // ST_FpP80m >+ 0U, // ST_FpP80m32 >+ 0U, // ST_FpP80m64 >+ 26978U, // ST_Frr >+ 2124369U, // SUB16i16 >+ 4237905U, // SUB16mi >+ 4237905U, // SUB16mi8 >+ 4237905U, // SUB16mr >+ 6351441U, // SUB16ri >+ 6351441U, // SUB16ri8 >+ 6367825U, // SUB16rm >+ 6351441U, // SUB16rr >+ 8448593U, // SUB16rr_REV >+ 10508535U, // SUB32i32 >+ 12622071U, // SUB32mi >+ 12622071U, // SUB32mi8 >+ 12622071U, // SUB32mr >+ 6346999U, // SUB32ri >+ 6346999U, // SUB32ri8 >+ 283203831U, // SUB32rm >+ 6346999U, // SUB32rr >+ 8444151U, // SUB32rr_REV >+ 16801375U, // SUB64i32 >+ 18914911U, // SUB64mi32 >+ 18914911U, // SUB64mi8 >+ 18914911U, // SUB64mr >+ 6348383U, // SUB64ri32 >+ 6348383U, // SUB64ri8 >+ 283221599U, // SUB64rm >+ 6348383U, // SUB64rr >+ 8445535U, // SUB64rr_REV >+ 20991655U, // SUB8i8 >+ 23105191U, // SUB8mi >+ 23105191U, // SUB8mr >+ 6344359U, // SUB8ri >+ 6344359U, // SUB8ri8 >+ 118439U, // SUB8rm >+ 6344359U, // SUB8rr >+ 8441511U, // SUB8rr_REV >+ 8524581U, // SUBPDrm >+ 8442661U, // SUBPDrr >+ 8529262U, // SUBPSrm >+ 8447342U, // SUBPSrr >+ 190287U, // SUBR_F32m >+ 203623U, // SUBR_F64m >+ 223063U, // SUBR_FI16m >+ 236399U, // SUBR_FI32m >+ 23918U, // SUBR_FPrST0 >+ 25449U, // SUBR_FST0r >+ 0U, // SUBR_Fp32m >+ 0U, // SUBR_Fp64m >+ 0U, // SUBR_Fp64m32 >+ 0U, // SUBR_Fp80m32 >+ 0U, // SUBR_Fp80m64 >+ 0U, // SUBR_FpI16m32 >+ 0U, // SUBR_FpI16m64 >+ 0U, // SUBR_FpI16m80 >+ 0U, // SUBR_FpI32m32 >+ 0U, // SUBR_FpI32m64 >+ 0U, // SUBR_FpI32m80 >+ 28348U, // SUBR_FrST0 >+ 551703944U, // SUBSDrm >+ 551703944U, // SUBSDrm_Int >+ 8443272U, // SUBSDrr >+ 8443272U, // SUBSDrr_Int >+ 551725089U, // SUBSSrm >+ 551725089U, // SUBSSrm_Int >+ 8448033U, // SUBSSrr >+ 8448033U, // SUBSSrr_Int >+ 189383U, // SUB_F32m >+ 202998U, // SUB_F64m >+ 222158U, // SUB_FI16m >+ 235773U, // SUB_FI32m >+ 23993U, // SUB_FPrST0 >+ 20543U, // SUB_FST0r >+ 0U, // SUB_Fp32 >+ 0U, // SUB_Fp32m >+ 0U, // SUB_Fp64 >+ 0U, // SUB_Fp64m >+ 0U, // SUB_Fp64m32 >+ 0U, // SUB_Fp80 >+ 0U, // SUB_Fp80m32 >+ 0U, // SUB_Fp80m64 >+ 0U, // SUB_FpI16m32 >+ 0U, // SUB_FpI16m64 >+ 0U, // SUB_FpI16m80 >+ 0U, // SUB_FpI32m32 >+ 0U, // SUB_FpI32m64 >+ 0U, // SUB_FpI32m80 >+ 28421U, // SUB_FrST0 >+ 15080U, // SWAPGS >+ 14526U, // SYSCALL >+ 14818U, // SYSENTER >+ 14583U, // SYSEXIT >+ 14793U, // SYSEXIT64 >+ 14575U, // SYSRET >+ 14785U, // SYSRET64 >+ 551801005U, // T1MSKC32rm >+ 551817389U, // T1MSKC32rr >+ 551833773U, // T1MSKC64rm >+ 551817389U, // T1MSKC64rr >+ 82206094U, // TAILJMPd >+ 82206094U, // TAILJMPd64 >+ 82032036U, // TAILJMPm >+ 82195893U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 81819061U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 2125294U, // TEST16i16 >+ 4238830U, // TEST16mi >+ 4238830U, // TEST16mi_alt >+ 551824878U, // TEST16ri >+ 551824878U, // TEST16ri_alt >+ 4238830U, // TEST16rm >+ 551824878U, // TEST16rr >+ 10509449U, // TEST32i32 >+ 12622985U, // TEST32mi >+ 12622985U, // TEST32mi_alt >+ 551820425U, // TEST32ri >+ 551820425U, // TEST32ri_alt >+ 12622985U, // TEST32rm >+ 551820425U, // TEST32rr >+ 16802464U, // TEST64i32 >+ 18916000U, // TEST64mi32 >+ 18916000U, // TEST64mi32_alt >+ 551821984U, // TEST64ri32 >+ 551821984U, // TEST64ri32_alt >+ 18916000U, // TEST64rm >+ 551821984U, // TEST64rr >+ 20992037U, // TEST8i8 >+ 23105573U, // TEST8mi >+ 23105573U, // TEST8mi_alt >+ 551817253U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 551817253U, // TEST8ri_alt >+ 23105573U, // TEST8rm >+ 551817253U, // TEST8rr >+ 13847U, // TLSCall_32 >+ 13951U, // TLSCall_64 >+ 13860U, // TLS_addr32 >+ 13964U, // TLS_addr64 >+ 13873U, // TLS_base_addr32 >+ 13977U, // TLS_base_addr64 >+ 13891U, // TRAP >+ 15257U, // TST_F >+ 0U, // TST_Fp32 >+ 0U, // TST_Fp64 >+ 0U, // TST_Fp80 >+ 388554U, // TZCNT16rm >+ 551824842U, // TZCNT16rr >+ 551804027U, // TZCNT32rm >+ 551820411U, // TZCNT32rr >+ 551838304U, // TZCNT64rm >+ 551821920U, // TZCNT64rr >+ 551803083U, // TZMSK32rm >+ 551819467U, // TZMSK32rr >+ 551835851U, // TZMSK64rm >+ 551819467U, // TZMSK64rr >+ 595402U, // UCOMISDrm >+ 551818698U, // UCOMISDrr >+ 616547U, // UCOMISSrm >+ 551823459U, // UCOMISSrr >+ 22644U, // UCOM_FIPr >+ 22586U, // UCOM_FIr >+ 14716U, // UCOM_FPPr >+ 23962U, // UCOM_FPr >+ 0U, // UCOM_FpIr32 >+ 0U, // UCOM_FpIr64 >+ 0U, // UCOM_FpIr80 >+ 0U, // UCOM_Fpr32 >+ 0U, // UCOM_Fpr64 >+ 0U, // UCOM_Fpr80 >+ 23827U, // UCOM_Fr >+ 14124U, // UD2B >+ 8524738U, // UNPCKHPDrm >+ 8442818U, // UNPCKHPDrr >+ 8529419U, // UNPCKHPSrm >+ 8447499U, // UNPCKHPSrr >+ 8524780U, // UNPCKLPDrm >+ 8442860U, // UNPCKLPDrr >+ 8529481U, // UNPCKLPSrm >+ 8447561U, // UNPCKLPSrr >+ 1625322379U, // VAARG_64 >+ 812520328U, // VADDPDYrm >+ 811651976U, // VADDPDYrr >+ 812532486U, // VADDPDZrm >+ 352469766U, // VADDPDZrmb >+ 1427014406U, // VADDPDZrmbk >+ 1427014406U, // VADDPDZrmbkz >+ 571397000U, // VADDPDZrmk >+ 571397000U, // VADDPDZrmkz >+ 811647750U, // VADDPDZrr >+ 570786566U, // VADDPDZrrk >+ 570786566U, // VADDPDZrrkz >+ 811733896U, // VADDPDrm >+ 811651976U, // VADDPDrr >+ 812525009U, // VADDPSYrm >+ 811656657U, // VADDPSYrr >+ 812534405U, // VADDPSZrm >+ 354585221U, // VADDPSZrmb >+ 1429146245U, // VADDPSZrmbk >+ 1429146245U, // VADDPSZrmbkz >+ 571401681U, // VADDPSZrmk >+ 571401681U, // VADDPSZrmkz >+ 811649669U, // VADDPSZrr >+ 570788485U, // VADDPSZrrk >+ 570788485U, // VADDPSZrrkz >+ 811738577U, // VADDPSrm >+ 811656657U, // VADDPSrr >+ 283268535U, // VADDSDZrm >+ 811652535U, // VADDSDZrr >+ 283268535U, // VADDSDrm >+ 283268535U, // VADDSDrm_Int >+ 811652535U, // VADDSDrr >+ 811652535U, // VADDSDrr_Int >+ 283289680U, // VADDSSZrm >+ 811657296U, // VADDSSZrr >+ 283289680U, // VADDSSrm >+ 283289680U, // VADDSSrm_Int >+ 811657296U, // VADDSSrr >+ 811657296U, // VADDSSrr_Int >+ 812520236U, // VADDSUBPDYrm >+ 811651884U, // VADDSUBPDYrr >+ 811733804U, // VADDSUBPDrm >+ 811651884U, // VADDSUBPDrr >+ 812524917U, // VADDSUBPSYrm >+ 811656565U, // VADDSUBPSYrr >+ 811738485U, // VADDSUBPSrm >+ 811656565U, // VADDSUBPSrr >+ 811903296U, // VAESDECLASTrm >+ 811657536U, // VAESDECLASTrr >+ 811896982U, // VAESDECrm >+ 811651222U, // VAESDECrr >+ 811903309U, // VAESENCLASTrm >+ 811657549U, // VAESENCLASTrr >+ 811897022U, // VAESENCrm >+ 811651262U, // VAESENCrr >+ 315573U, // VAESIMCrm >+ 551817397U, // VAESIMCrr >+ 25504103U, // VAESKEYGENASSIST128rm >+ 811657575U, // VAESKEYGENASSIST128rr >+ 356860300U, // VALIGNDrmi >+ 302350732U, // VALIGNDrri >+ 90210700U, // VALIGNDrrik >+ 571064716U, // VALIGNDrrikz >+ 356861965U, // VALIGNQrmi >+ 302352397U, // VALIGNQrri >+ 90212365U, // VALIGNQrrik >+ 571066381U, // VALIGNQrrikz >+ 812520472U, // VANDNPDYrm >+ 811652120U, // VANDNPDYrr >+ 811734040U, // VANDNPDrm >+ 811652120U, // VANDNPDrr >+ 812525182U, // VANDNPSYrm >+ 811656830U, // VANDNPSYrr >+ 811738750U, // VANDNPSrm >+ 811656830U, // VANDNPSrr >+ 812520336U, // VANDPDYrm >+ 811651984U, // VANDPDYrr >+ 811733904U, // VANDPDrm >+ 811651984U, // VANDPDrr >+ 812525017U, // VANDPSYrm >+ 811656665U, // VANDPSYrr >+ 811738585U, // VANDPSrm >+ 811656665U, // VANDPSrr >+ 283145147U, // VASTART_SAVE_XMM_REGS >+ 571392855U, // VBLENDMPDZrm >+ 570786647U, // VBLENDMPDZrr >+ 571394774U, // VBLENDMPSZrm >+ 570788566U, // VBLENDMPSZrr >+ 92623768U, // VBLENDPDYrmi >+ 302355352U, // VBLENDPDYrri >+ 300241816U, // VBLENDPDrmi >+ 302355352U, // VBLENDPDrri >+ 92628449U, // VBLENDPSYrmi >+ 302360033U, // VBLENDPSYrri >+ 300246497U, // VBLENDPSrmi >+ 302360033U, // VBLENDPSrri >+ 92623992U, // VBLENDVPDYrm >+ 302355576U, // VBLENDVPDYrr >+ 300242040U, // VBLENDVPDrm >+ 302355576U, // VBLENDVPDrr >+ 92628767U, // VBLENDVPSYrm >+ 302360351U, // VBLENDVPSYrr >+ 300246815U, // VBLENDVPSrm >+ 302360351U, // VBLENDVPSrr >+ 577020U, // VBROADCASTF128 >+ 314931U, // VBROADCASTI128 >+ 1887731713U, // VBROADCASTI32X4krm >+ 311297U, // VBROADCASTI32X4rm >+ 1888436243U, // VBROADCASTI64X4krm >+ 1015827U, // VBROADCASTI64X4rm >+ 595471U, // VBROADCASTSDYrm >+ 551818767U, // VBROADCASTSDYrr >+ 591070U, // VBROADCASTSDZrm >+ 551814366U, // VBROADCASTSDZrr >+ 616625U, // VBROADCASTSSYrm >+ 551823537U, // VBROADCASTSSYrr >+ 609253U, // VBROADCASTSSZrm >+ 551816165U, // VBROADCASTSSZrr >+ 616625U, // VBROADCASTSSrm >+ 551823537U, // VBROADCASTSSrr >+ 2185902443U, // VCMPPDYrmi >+ 92623920U, // VCMPPDYrmi_alt >+ 1380612459U, // VCMPPDYrri >+ 302355504U, // VCMPPDYrri_alt >+ 2510961003U, // VCMPPDZrmi >+ 96813942U, // VCMPPDZrmi_alt >+ 1437235563U, // VCMPPDZrri >+ 302351222U, // VCMPPDZrri_alt >+ 99252587U, // VCMPPDZrrib >+ 1112160619U, // VCMPPDrmi >+ 300241968U, // VCMPPDrmi_alt >+ 1380612459U, // VCMPPDrri >+ 302355504U, // VCMPPDrri_alt >+ 2187999595U, // VCMPPSYrmi >+ 92628638U, // VCMPPSYrmi_alt >+ 1382709611U, // VCMPPSYrri >+ 302360222U, // VCMPPSYrri_alt >+ 2517252459U, // VCMPPSZrmi >+ 96815861U, // VCMPPSZrmi_alt >+ 1443527019U, // VCMPPSZrri >+ 302353141U, // VCMPPSZrri_alt >+ 103446891U, // VCMPPSZrrib >+ 1114257771U, // VCMPPSrmi >+ 300246686U, // VCMPPSrmi_alt >+ 1382709611U, // VCMPPSrri >+ 302360222U, // VCMPPSrri_alt >+ 1921661291U, // VCMPSDZrm >+ 312825333U, // VCMPSDZrmi_alt >+ 1384806763U, // VCMPSDZrr >+ 302355957U, // VCMPSDZrri_alt >+ 1921661291U, // VCMPSDrm >+ 312825333U, // VCMPSDrm_alt >+ 1384806763U, // VCMPSDrr >+ 302355957U, // VCMPSDrr_alt >+ 2731161963U, // VCMPSSZrm >+ 317024397U, // VCMPSSZrmi_alt >+ 1389001067U, // VCMPSSZrr >+ 302360717U, // VCMPSSZrri_alt >+ 2731161963U, // VCMPSSrm >+ 317024397U, // VCMPSSrm_alt >+ 1389001067U, // VCMPSSrr >+ 302360717U, // VCMPSSrr_alt >+ 579027U, // VCOMISDZrm >+ 551818707U, // VCOMISDZrr >+ 579027U, // VCOMISDrm >+ 551818707U, // VCOMISDrr >+ 583788U, // VCOMISSZrm >+ 551823468U, // VCOMISSZrr >+ 583788U, // VCOMISSrm >+ 551823468U, // VCOMISSrr >+ 316066U, // VCVTDQ2PDYrm >+ 551817890U, // VCVTDQ2PDYrr >+ 1016318U, // VCVTDQ2PDZrm >+ 551813630U, // VCVTDQ2PDZrr >+ 551834274U, // VCVTDQ2PDrm >+ 551817890U, // VCVTDQ2PDrr >+ 1025278U, // VCVTDQ2PSYrm >+ 551822590U, // VCVTDQ2PSYrr >+ 1034633U, // VCVTDQ2PSZrm >+ 551815561U, // VCVTDQ2PSZrr >+ 1051017U, // VCVTDQ2PSZrrb >+ 320766U, // VCVTDQ2PSrm >+ 551822590U, // VCVTDQ2PSrr >+ 585323U, // VCVTPD2DQXrm >+ 1076880U, // VCVTPD2DQYrm >+ 551825040U, // VCVTPD2DQYrr >+ 1083054U, // VCVTPD2DQZrm >+ 551814830U, // VCVTPD2DQZrr >+ 1050286U, // VCVTPD2DQZrrb >+ 551820975U, // VCVTPD2DQrr >+ 585335U, // VCVTPD2PSXrm >+ 1076892U, // VCVTPD2PSYrm >+ 551825052U, // VCVTPD2PSYrr >+ 1083761U, // VCVTPD2PSZrm >+ 551815537U, // VCVTPD2PSZrr >+ 1050993U, // VCVTPD2PSZrrb >+ 551822546U, // VCVTPD2PSrr >+ 1083249U, // VCVTPD2UDQZrm >+ 551815025U, // VCVTPD2UDQZrr >+ 1050481U, // VCVTPD2UDQZrrb >+ 582877U, // VCVTPH2PSYrm >+ 551822557U, // VCVTPH2PSYrr >+ 1074397U, // VCVTPH2PSZrm >+ 551822557U, // VCVTPH2PSZrr >+ 599261U, // VCVTPH2PSrm >+ 551822557U, // VCVTPH2PSrr >+ 1072847U, // VCVTPS2DQYrm >+ 551821007U, // VCVTPS2DQYrr >+ 1083079U, // VCVTPS2DQZrm >+ 551814855U, // VCVTPS2DQZrr >+ 1050311U, // VCVTPS2DQZrrb >+ 581327U, // VCVTPS2DQrm >+ 551821007U, // VCVTPS2DQrr >+ 578221U, // VCVTPS2PDYrm >+ 551817901U, // VCVTPS2PDYrr >+ 1065495U, // VCVTPS2PDZrm >+ 551813655U, // VCVTPS2PDZrr >+ 594605U, // VCVTPS2PDrm >+ 551817901U, // VCVTPS2PDrr >+ 2735020034U, // VCVTPS2PHYmr >+ 811653122U, // VCVTPS2PHYrr >+ 3003450754U, // VCVTPS2PHZmr >+ 811648386U, // VCVTPS2PHZrr >+ 3271890946U, // VCVTPS2PHmr >+ 811653122U, // VCVTPS2PHrr >+ 1083276U, // VCVTPS2UDQZrm >+ 551815052U, // VCVTPS2UDQZrr >+ 1050508U, // VCVTPS2UDQZrrb >+ 591259U, // VCVTSD2SI64Zrm >+ 551814555U, // VCVTSD2SI64Zrr >+ 596129U, // VCVTSD2SI64rm >+ 551819425U, // VCVTSD2SI64rr >+ 591259U, // VCVTSD2SIZrm >+ 551814555U, // VCVTSD2SIZrr >+ 596129U, // VCVTSD2SIrm >+ 551819425U, // VCVTSD2SIrr >+ 283273181U, // VCVTSD2SSZrm >+ 811657181U, // VCVTSD2SSZrr >+ 283273181U, // VCVTSD2SSrm >+ 811657181U, // VCVTSD2SSrr >+ 591310U, // VCVTSD2USI64Zrm >+ 551814606U, // VCVTSD2USI64Zrr >+ 591310U, // VCVTSD2USIZrm >+ 551814606U, // VCVTSD2USIZrr >+ 283221899U, // VCVTSI2SD64rm >+ 811655051U, // VCVTSI2SD64rr >+ 283198966U, // VCVTSI2SDZrm >+ 811648502U, // VCVTSI2SDZrr >+ 283203961U, // VCVTSI2SDrm >+ 811653497U, // VCVTSI2SDrr >+ 283222505U, // VCVTSI2SS64rm >+ 811655657U, // VCVTSI2SS64rr >+ 283198993U, // VCVTSI2SSZrm >+ 811648529U, // VCVTSI2SSZrr >+ 283204609U, // VCVTSI2SSrm >+ 811654145U, // VCVTSI2SSrr >+ 283215688U, // VCVTSI642SDZrm >+ 811648840U, // VCVTSI642SDZrr >+ 283215982U, // VCVTSI642SSZrm >+ 811649134U, // VCVTSI642SSZrr >+ 283284796U, // VCVTSS2SDZrm >+ 811652412U, // VCVTSS2SDZrr >+ 283284796U, // VCVTSS2SDrm >+ 811652412U, // VCVTSS2SDrr >+ 607668U, // VCVTSS2SI64Zrm >+ 551814580U, // VCVTSS2SI64Zrr >+ 612536U, // VCVTSS2SI64rm >+ 551819448U, // VCVTSS2SI64rr >+ 607668U, // VCVTSS2SIZrm >+ 551814580U, // VCVTSS2SIZrr >+ 612536U, // VCVTSS2SIrm >+ 551819448U, // VCVTSS2SIrr >+ 607721U, // VCVTSS2USI64Zrm >+ 551814633U, // VCVTSS2USI64Zrr >+ 607721U, // VCVTSS2USIZrm >+ 551814633U, // VCVTSS2USIZrr >+ 585310U, // VCVTTPD2DQXrm >+ 1076867U, // VCVTTPD2DQYrm >+ 551825027U, // VCVTTPD2DQYrr >+ 1083041U, // VCVTTPD2DQZrm >+ 551814817U, // VCVTTPD2DQZrr >+ 551820963U, // VCVTTPD2DQrr >+ 1083235U, // VCVTTPD2UDQZrm >+ 551815011U, // VCVTTPD2UDQZrr >+ 1072835U, // VCVTTPS2DQYrm >+ 551820995U, // VCVTTPS2DQYrr >+ 1083066U, // VCVTTPS2DQZrm >+ 551814842U, // VCVTTPS2DQZrr >+ 581315U, // VCVTTPS2DQrm >+ 551820995U, // VCVTTPS2DQrr >+ 1083262U, // VCVTTPS2UDQZrm >+ 551815038U, // VCVTTPS2UDQZrr >+ 591246U, // VCVTTSD2SI64Zrm >+ 551814542U, // VCVTTSD2SI64Zrr >+ 596117U, // VCVTTSD2SI64rm >+ 551819413U, // VCVTTSD2SI64rr >+ 591246U, // VCVTTSD2SIZrm >+ 551814542U, // VCVTTSD2SIZrr >+ 596117U, // VCVTTSD2SIrm >+ 551819413U, // VCVTTSD2SIrr >+ 591296U, // VCVTTSD2USI64Zrm >+ 551814592U, // VCVTTSD2USI64Zrr >+ 591296U, // VCVTTSD2USIZrm >+ 551814592U, // VCVTTSD2USIZrr >+ 607655U, // VCVTTSS2SI64Zrm >+ 551814567U, // VCVTTSS2SI64Zrr >+ 612524U, // VCVTTSS2SI64rm >+ 551819436U, // VCVTTSS2SI64rr >+ 607655U, // VCVTTSS2SIZrm >+ 551814567U, // VCVTTSS2SIZrr >+ 612524U, // VCVTTSS2SIrm >+ 551819436U, // VCVTTSS2SIrr >+ 607707U, // VCVTTSS2USI64Zrm >+ 551814619U, // VCVTTSS2USI64Zrr >+ 607707U, // VCVTTSS2USIZrm >+ 551814619U, // VCVTTSS2USIZrr >+ 1065482U, // VCVTUDQ2PDZrm >+ 551813642U, // VCVTUDQ2PDZrr >+ 1083797U, // VCVTUDQ2PSZrm >+ 551815573U, // VCVTUDQ2PSZrr >+ 1051029U, // VCVTUDQ2PSZrrb >+ 283198979U, // VCVTUSI2SDZrm >+ 811648515U, // VCVTUSI2SDZrr >+ 283199006U, // VCVTUSI2SSZrm >+ 811648542U, // VCVTUSI2SSZrr >+ 283215701U, // VCVTUSI642SDZrm >+ 811648853U, // VCVTUSI642SDZrr >+ 283215995U, // VCVTUSI642SSZrm >+ 811649147U, // VCVTUSI642SSZrr >+ 812520579U, // VDIVPDYrm >+ 811652227U, // VDIVPDYrr >+ 812532700U, // VDIVPDZrm >+ 352469980U, // VDIVPDZrmb >+ 1427014620U, // VDIVPDZrmbk >+ 1427014620U, // VDIVPDZrmbkz >+ 571397251U, // VDIVPDZrmk >+ 571397251U, // VDIVPDZrmkz >+ 811647964U, // VDIVPDZrr >+ 570786780U, // VDIVPDZrrk >+ 570786780U, // VDIVPDZrrkz >+ 811734147U, // VDIVPDrm >+ 811652227U, // VDIVPDrr >+ 812525354U, // VDIVPSYrm >+ 811657002U, // VDIVPSYrr >+ 812534619U, // VDIVPSZrm >+ 354585435U, // VDIVPSZrmb >+ 1429146459U, // VDIVPSZrmbk >+ 1429146459U, // VDIVPSZrmbkz >+ 571402026U, // VDIVPSZrmk >+ 571402026U, // VDIVPSZrmkz >+ 811649883U, // VDIVPSZrr >+ 570788699U, // VDIVPSZrrk >+ 570788699U, // VDIVPSZrrkz >+ 811738922U, // VDIVPSrm >+ 811657002U, // VDIVPSrr >+ 283268637U, // VDIVSDZrm >+ 811652637U, // VDIVSDZrr >+ 283268637U, // VDIVSDrm >+ 283268637U, // VDIVSDrm_Int >+ 811652637U, // VDIVSDrr >+ 811652637U, // VDIVSDrr_Int >+ 283289791U, // VDIVSSZrm >+ 811657407U, // VDIVSSZrr >+ 283289791U, // VDIVSSrm >+ 283289791U, // VDIVSSrm_Int >+ 811657407U, // VDIVSSrr >+ 811657407U, // VDIVSSrr_Int >+ 300241961U, // VDPPDrmi >+ 302355497U, // VDPPDrri >+ 105211543U, // VDPPSYrmi >+ 302360215U, // VDPPSYrri >+ 300246679U, // VDPPSrmi >+ 302360215U, // VDPPSrri >+ 222111U, // VERRm >+ 25503U, // VERRr >+ 224353U, // VERWm >+ 27745U, // VERWr >+ 2735017441U, // VEXTRACTF128mr >+ 811650529U, // VEXTRACTF128rr >+ 2735017302U, // VEXTRACTF32x4mr >+ 811650390U, // VEXTRACTF32x4rr >+ 3003452816U, // VEXTRACTF64x4mr >+ 811650448U, // VEXTRACTF64x4rr >+ 3540323864U, // VEXTRACTI128mr >+ 811650584U, // VEXTRACTI128rr >+ 3540323699U, // VEXTRACTI32x4mr >+ 811650419U, // VEXTRACTI32x4rr >+ 3808759213U, // VEXTRACTI64x4mr >+ 811650477U, // VEXTRACTI64x4rr >+ 3271894721U, // VEXTRACTPSmr >+ 811656897U, // VEXTRACTPSrr >+ 3271894721U, // VEXTRACTPSzmr >+ 811656897U, // VEXTRACTPSzrr >+ 571392469U, // VFMADD132PDZm >+ 1427014101U, // VFMADD132PDZmb >+ 571394388U, // VFMADD132PSZm >+ 1429145940U, // VFMADD132PSZmb >+ 571392622U, // VFMADD213PDZm >+ 1427014254U, // VFMADD213PDZmb >+ 570786414U, // VFMADD213PDZr >+ 1888076398U, // VFMADD213PDZrk >+ 1888076398U, // VFMADD213PDZrkz >+ 571394541U, // VFMADD213PSZm >+ 1429146093U, // VFMADD213PSZmb >+ 570788333U, // VFMADD213PSZr >+ 1888078317U, // VFMADD213PSZrk >+ 1888078317U, // VFMADD213PSZrkz >+ 300241779U, // VFMADDPD4mr >+ 92623731U, // VFMADDPD4mrY >+ 303092595U, // VFMADDPD4rm >+ 303108979U, // VFMADDPD4rmY >+ 302355315U, // VFMADDPD4rr >+ 302355315U, // VFMADDPD4rrY >+ 302355315U, // VFMADDPD4rrY_REV >+ 302355315U, // VFMADDPD4rr_REV >+ 571527793U, // VFMADDPDr132m >+ 571544177U, // VFMADDPDr132mY >+ 570790513U, // VFMADDPDr132r >+ 570790513U, // VFMADDPDr132rY >+ 571527923U, // VFMADDPDr213m >+ 571544307U, // VFMADDPDr213mY >+ 570790643U, // VFMADDPDr213r >+ 570790643U, // VFMADDPDr213rY >+ 571527707U, // VFMADDPDr231m >+ 571544091U, // VFMADDPDr231mY >+ 570790427U, // VFMADDPDr231r >+ 570790427U, // VFMADDPDr231rY >+ 300246460U, // VFMADDPS4mr >+ 92628412U, // VFMADDPS4mrY >+ 303097276U, // VFMADDPS4rm >+ 303113660U, // VFMADDPS4rmY >+ 302359996U, // VFMADDPS4rr >+ 302359996U, // VFMADDPS4rrY >+ 302359996U, // VFMADDPS4rrY_REV >+ 302359996U, // VFMADDPS4rr_REV >+ 571532471U, // VFMADDPSr132m >+ 571548855U, // VFMADDPSr132mY >+ 570795191U, // VFMADDPSr132r >+ 570795191U, // VFMADDPSr132rY >+ 571532612U, // VFMADDPSr213m >+ 571548996U, // VFMADDPSr213mY >+ 570795332U, // VFMADDPSr213r >+ 570795332U, // VFMADDPSr213rY >+ 571532385U, // VFMADDPSr231m >+ 571548769U, // VFMADDPSr231mY >+ 570795105U, // VFMADDPSr231r >+ 570795105U, // VFMADDPSr231rY >+ 312825250U, // VFMADDSD4mr >+ 312825250U, // VFMADDSD4mr_Int >+ 1357813154U, // VFMADDSD4rm >+ 1357813154U, // VFMADDSD4rm_Int >+ 302355874U, // VFMADDSD4rr >+ 302355874U, // VFMADDSD4rr_Int >+ 302355874U, // VFMADDSD4rr_REV >+ 571524208U, // VFMADDSDZm >+ 570786928U, // VFMADDSDZr >+ 1357813025U, // VFMADDSDr132m >+ 570791201U, // VFMADDSDr132r >+ 1357813090U, // VFMADDSDr213m >+ 570791266U, // VFMADDSDr213r >+ 1357812971U, // VFMADDSDr231m >+ 570791147U, // VFMADDSDr231r >+ 317024315U, // VFMADDSS4mr >+ 317024315U, // VFMADDSS4mr_Int >+ 1357850683U, // VFMADDSS4rm >+ 1357850683U, // VFMADDSS4rm_Int >+ 302360635U, // VFMADDSS4rr >+ 302360635U, // VFMADDSS4rr_Int >+ 302360635U, // VFMADDSS4rr_REV >+ 571526026U, // VFMADDSSZm >+ 570788746U, // VFMADDSSZr >+ 1357850562U, // VFMADDSSr132m >+ 570795970U, // VFMADDSSr132r >+ 1357850627U, // VFMADDSSr213m >+ 570796035U, // VFMADDSSr213r >+ 1357850508U, // VFMADDSSr231m >+ 570795916U, // VFMADDSSr231r >+ 571392406U, // VFMADDSUB132PDZm >+ 1427014038U, // VFMADDSUB132PDZmb >+ 571394325U, // VFMADDSUB132PSZm >+ 1429145877U, // VFMADDSUB132PSZmb >+ 571392559U, // VFMADDSUB213PDZm >+ 1427014191U, // VFMADDSUB213PDZmb >+ 570786351U, // VFMADDSUB213PDZr >+ 1888076335U, // VFMADDSUB213PDZrk >+ 1888076335U, // VFMADDSUB213PDZrkz >+ 571394478U, // VFMADDSUB213PSZm >+ 1429146030U, // VFMADDSUB213PSZmb >+ 570788270U, // VFMADDSUB213PSZr >+ 1888078254U, // VFMADDSUB213PSZrk >+ 1888078254U, // VFMADDSUB213PSZrkz >+ 300241695U, // VFMADDSUBPD4mr >+ 92623647U, // VFMADDSUBPD4mrY >+ 303092511U, // VFMADDSUBPD4rm >+ 303108895U, // VFMADDSUBPD4rmY >+ 302355231U, // VFMADDSUBPD4rr >+ 302355231U, // VFMADDSUBPD4rrY >+ 302355231U, // VFMADDSUBPD4rrY_REV >+ 302355231U, // VFMADDSUBPD4rr_REV >+ 571527734U, // VFMADDSUBPDr132m >+ 571544118U, // VFMADDSUBPDr132mY >+ 570790454U, // VFMADDSUBPDr132r >+ 570790454U, // VFMADDSUBPDr132rY >+ 571527864U, // VFMADDSUBPDr213m >+ 571544248U, // VFMADDSUBPDr213mY >+ 570790584U, // VFMADDSUBPDr213r >+ 570790584U, // VFMADDSUBPDr213rY >+ 571527648U, // VFMADDSUBPDr231m >+ 571544032U, // VFMADDSUBPDr231mY >+ 570790368U, // VFMADDSUBPDr231r >+ 570790368U, // VFMADDSUBPDr231rY >+ 300246376U, // VFMADDSUBPS4mr >+ 92628328U, // VFMADDSUBPS4mrY >+ 303097192U, // VFMADDSUBPS4rm >+ 303113576U, // VFMADDSUBPS4rmY >+ 302359912U, // VFMADDSUBPS4rr >+ 302359912U, // VFMADDSUBPS4rrY >+ 302359912U, // VFMADDSUBPS4rrY_REV >+ 302359912U, // VFMADDSUBPS4rr_REV >+ 571532412U, // VFMADDSUBPSr132m >+ 571548796U, // VFMADDSUBPSr132mY >+ 570795132U, // VFMADDSUBPSr132r >+ 570795132U, // VFMADDSUBPSr132rY >+ 571532553U, // VFMADDSUBPSr213m >+ 571548937U, // VFMADDSUBPSr213mY >+ 570795273U, // VFMADDSUBPSr213r >+ 570795273U, // VFMADDSUBPSr213rY >+ 571532326U, // VFMADDSUBPSr231m >+ 571548710U, // VFMADDSUBPSr231mY >+ 570795046U, // VFMADDSUBPSr231r >+ 570795046U, // VFMADDSUBPSr231rY >+ 571392423U, // VFMSUB132PDZm >+ 1427014055U, // VFMSUB132PDZmb >+ 571394342U, // VFMSUB132PSZm >+ 1429145894U, // VFMSUB132PSZmb >+ 571392576U, // VFMSUB213PDZm >+ 1427014208U, // VFMSUB213PDZmb >+ 570786368U, // VFMSUB213PDZr >+ 1888076352U, // VFMSUB213PDZrk >+ 1888076352U, // VFMSUB213PDZrkz >+ 571394495U, // VFMSUB213PSZm >+ 1429146047U, // VFMSUB213PSZmb >+ 570788287U, // VFMSUB213PSZr >+ 1888078271U, // VFMSUB213PSZrk >+ 1888078271U, // VFMSUB213PSZrkz >+ 571392452U, // VFMSUBADD132PDZm >+ 1427014084U, // VFMSUBADD132PDZmb >+ 571394371U, // VFMSUBADD132PSZm >+ 1429145923U, // VFMSUBADD132PSZmb >+ 571392605U, // VFMSUBADD213PDZm >+ 1427014237U, // VFMSUBADD213PDZmb >+ 570786397U, // VFMSUBADD213PDZr >+ 1888076381U, // VFMSUBADD213PDZrk >+ 1888076381U, // VFMSUBADD213PDZrkz >+ 571394524U, // VFMSUBADD213PSZm >+ 1429146076U, // VFMSUBADD213PSZmb >+ 570788316U, // VFMSUBADD213PSZr >+ 1888078300U, // VFMSUBADD213PSZrk >+ 1888078300U, // VFMSUBADD213PSZrkz >+ 300241757U, // VFMSUBADDPD4mr >+ 92623709U, // VFMSUBADDPD4mrY >+ 303092573U, // VFMSUBADDPD4rm >+ 303108957U, // VFMSUBADDPD4rmY >+ 302355293U, // VFMSUBADDPD4rr >+ 302355293U, // VFMSUBADDPD4rrY >+ 302355293U, // VFMSUBADDPD4rrY_REV >+ 302355293U, // VFMSUBADDPD4rr_REV >+ 571527777U, // VFMSUBADDPDr132m >+ 571544161U, // VFMSUBADDPDr132mY >+ 570790497U, // VFMSUBADDPDr132r >+ 570790497U, // VFMSUBADDPDr132rY >+ 571527907U, // VFMSUBADDPDr213m >+ 571544291U, // VFMSUBADDPDr213mY >+ 570790627U, // VFMSUBADDPDr213r >+ 570790627U, // VFMSUBADDPDr213rY >+ 571527691U, // VFMSUBADDPDr231m >+ 571544075U, // VFMSUBADDPDr231mY >+ 570790411U, // VFMSUBADDPDr231r >+ 570790411U, // VFMSUBADDPDr231rY >+ 300246438U, // VFMSUBADDPS4mr >+ 92628390U, // VFMSUBADDPS4mrY >+ 303097254U, // VFMSUBADDPS4rm >+ 303113638U, // VFMSUBADDPS4rmY >+ 302359974U, // VFMSUBADDPS4rr >+ 302359974U, // VFMSUBADDPS4rrY >+ 302359974U, // VFMSUBADDPS4rrY_REV >+ 302359974U, // VFMSUBADDPS4rr_REV >+ 571532455U, // VFMSUBADDPSr132m >+ 571548839U, // VFMSUBADDPSr132mY >+ 570795175U, // VFMSUBADDPSr132r >+ 570795175U, // VFMSUBADDPSr132rY >+ 571532596U, // VFMSUBADDPSr213m >+ 571548980U, // VFMSUBADDPSr213mY >+ 570795316U, // VFMSUBADDPSr213r >+ 570795316U, // VFMSUBADDPSr213rY >+ 571532369U, // VFMSUBADDPSr231m >+ 571548753U, // VFMSUBADDPSr231mY >+ 570795089U, // VFMSUBADDPSr231r >+ 570795089U, // VFMSUBADDPSr231rY >+ 300241728U, // VFMSUBPD4mr >+ 92623680U, // VFMSUBPD4mrY >+ 303092544U, // VFMSUBPD4rm >+ 303108928U, // VFMSUBPD4rmY >+ 302355264U, // VFMSUBPD4rr >+ 302355264U, // VFMSUBPD4rrY >+ 302355264U, // VFMSUBPD4rrY_REV >+ 302355264U, // VFMSUBPD4rr_REV >+ 571527750U, // VFMSUBPDr132m >+ 571544134U, // VFMSUBPDr132mY >+ 570790470U, // VFMSUBPDr132r >+ 570790470U, // VFMSUBPDr132rY >+ 571527880U, // VFMSUBPDr213m >+ 571544264U, // VFMSUBPDr213mY >+ 570790600U, // VFMSUBPDr213r >+ 570790600U, // VFMSUBPDr213rY >+ 571527664U, // VFMSUBPDr231m >+ 571544048U, // VFMSUBPDr231mY >+ 570790384U, // VFMSUBPDr231r >+ 570790384U, // VFMSUBPDr231rY >+ 300246409U, // VFMSUBPS4mr >+ 92628361U, // VFMSUBPS4mrY >+ 303097225U, // VFMSUBPS4rm >+ 303113609U, // VFMSUBPS4rmY >+ 302359945U, // VFMSUBPS4rr >+ 302359945U, // VFMSUBPS4rrY >+ 302359945U, // VFMSUBPS4rrY_REV >+ 302359945U, // VFMSUBPS4rr_REV >+ 571532428U, // VFMSUBPSr132m >+ 571548812U, // VFMSUBPSr132mY >+ 570795148U, // VFMSUBPSr132r >+ 570795148U, // VFMSUBPSr132rY >+ 571532569U, // VFMSUBPSr213m >+ 571548953U, // VFMSUBPSr213mY >+ 570795289U, // VFMSUBPSr213r >+ 570795289U, // VFMSUBPSr213rY >+ 571532342U, // VFMSUBPSr231m >+ 571548726U, // VFMSUBPSr231mY >+ 570795062U, // VFMSUBPSr231r >+ 570795062U, // VFMSUBPSr231rY >+ 312825221U, // VFMSUBSD4mr >+ 312825221U, // VFMSUBSD4mr_Int >+ 1357813125U, // VFMSUBSD4rm >+ 1357813125U, // VFMSUBSD4rm_Int >+ 302355845U, // VFMSUBSD4rr >+ 302355845U, // VFMSUBSD4rr_Int >+ 302355845U, // VFMSUBSD4rr_REV >+ 571524179U, // VFMSUBSDZm >+ 570786899U, // VFMSUBSDZr >+ 1357812998U, // VFMSUBSDr132m >+ 570791174U, // VFMSUBSDr132r >+ 1357813063U, // VFMSUBSDr213m >+ 570791239U, // VFMSUBSDr213r >+ 1357812944U, // VFMSUBSDr231m >+ 570791120U, // VFMSUBSDr231r >+ 317024286U, // VFMSUBSS4mr >+ 317024286U, // VFMSUBSS4mr_Int >+ 1357850654U, // VFMSUBSS4rm >+ 1357850654U, // VFMSUBSS4rm_Int >+ 302360606U, // VFMSUBSS4rr >+ 302360606U, // VFMSUBSS4rr_Int >+ 302360606U, // VFMSUBSS4rr_REV >+ 571525997U, // VFMSUBSSZm >+ 570788717U, // VFMSUBSSZr >+ 1357850535U, // VFMSUBSSr132m >+ 570795943U, // VFMSUBSSr132r >+ 1357850600U, // VFMSUBSSr213m >+ 570796008U, // VFMSUBSSr213r >+ 1357850481U, // VFMSUBSSr231m >+ 570795889U, // VFMSUBSSr231r >+ 571392483U, // VFNMADD132PDZm >+ 1427014115U, // VFNMADD132PDZmb >+ 571394402U, // VFNMADD132PSZm >+ 1429145954U, // VFNMADD132PSZmb >+ 571392636U, // VFNMADD213PDZm >+ 1427014268U, // VFNMADD213PDZmb >+ 570786428U, // VFNMADD213PDZr >+ 1888076412U, // VFNMADD213PDZrk >+ 1888076412U, // VFNMADD213PDZrkz >+ 571394555U, // VFNMADD213PSZm >+ 1429146107U, // VFNMADD213PSZmb >+ 570788347U, // VFNMADD213PSZr >+ 1888078331U, // VFNMADD213PSZrk >+ 1888078331U, // VFNMADD213PSZrkz >+ 300241789U, // VFNMADDPD4mr >+ 92623741U, // VFNMADDPD4mrY >+ 303092605U, // VFNMADDPD4rm >+ 303108989U, // VFNMADDPD4rmY >+ 302355325U, // VFNMADDPD4rr >+ 302355325U, // VFNMADDPD4rrY >+ 302355325U, // VFNMADDPD4rrY_REV >+ 302355325U, // VFNMADDPD4rr_REV >+ 571527806U, // VFNMADDPDr132m >+ 571544190U, // VFNMADDPDr132mY >+ 570790526U, // VFNMADDPDr132r >+ 570790526U, // VFNMADDPDr132rY >+ 571527936U, // VFNMADDPDr213m >+ 571544320U, // VFNMADDPDr213mY >+ 570790656U, // VFNMADDPDr213r >+ 570790656U, // VFNMADDPDr213rY >+ 571527720U, // VFNMADDPDr231m >+ 571544104U, // VFNMADDPDr231mY >+ 570790440U, // VFNMADDPDr231r >+ 570790440U, // VFNMADDPDr231rY >+ 300246470U, // VFNMADDPS4mr >+ 92628422U, // VFNMADDPS4mrY >+ 303097286U, // VFNMADDPS4rm >+ 303113670U, // VFNMADDPS4rmY >+ 302360006U, // VFNMADDPS4rr >+ 302360006U, // VFNMADDPS4rrY >+ 302360006U, // VFNMADDPS4rrY_REV >+ 302360006U, // VFNMADDPS4rr_REV >+ 571532484U, // VFNMADDPSr132m >+ 571548868U, // VFNMADDPSr132mY >+ 570795204U, // VFNMADDPSr132r >+ 570795204U, // VFNMADDPSr132rY >+ 571532625U, // VFNMADDPSr213m >+ 571549009U, // VFNMADDPSr213mY >+ 570795345U, // VFNMADDPSr213r >+ 570795345U, // VFNMADDPSr213rY >+ 571532398U, // VFNMADDPSr231m >+ 571548782U, // VFNMADDPSr231mY >+ 570795118U, // VFNMADDPSr231r >+ 570795118U, // VFNMADDPSr231rY >+ 312825260U, // VFNMADDSD4mr >+ 312825260U, // VFNMADDSD4mr_Int >+ 1357813164U, // VFNMADDSD4rm >+ 1357813164U, // VFNMADDSD4rm_Int >+ 302355884U, // VFNMADDSD4rr >+ 302355884U, // VFNMADDSD4rr_Int >+ 302355884U, // VFNMADDSD4rr_REV >+ 571524222U, // VFNMADDSDZm >+ 570786942U, // VFNMADDSDZr >+ 1357813038U, // VFNMADDSDr132m >+ 570791214U, // VFNMADDSDr132r >+ 1357813103U, // VFNMADDSDr213m >+ 570791279U, // VFNMADDSDr213r >+ 1357812984U, // VFNMADDSDr231m >+ 570791160U, // VFNMADDSDr231r >+ 317024325U, // VFNMADDSS4mr >+ 317024325U, // VFNMADDSS4mr_Int >+ 1357850693U, // VFNMADDSS4rm >+ 1357850693U, // VFNMADDSS4rm_Int >+ 302360645U, // VFNMADDSS4rr >+ 302360645U, // VFNMADDSS4rr_Int >+ 302360645U, // VFNMADDSS4rr_REV >+ 571526040U, // VFNMADDSSZm >+ 570788760U, // VFNMADDSSZr >+ 1357850575U, // VFNMADDSSr132m >+ 570795983U, // VFNMADDSSr132r >+ 1357850640U, // VFNMADDSSr213m >+ 570796048U, // VFNMADDSSr213r >+ 1357850521U, // VFNMADDSSr231m >+ 570795929U, // VFNMADDSSr231r >+ 571392437U, // VFNMSUB132PDZm >+ 1427014069U, // VFNMSUB132PDZmb >+ 571394356U, // VFNMSUB132PSZm >+ 1429145908U, // VFNMSUB132PSZmb >+ 571392590U, // VFNMSUB213PDZm >+ 1427014222U, // VFNMSUB213PDZmb >+ 570786382U, // VFNMSUB213PDZr >+ 1888076366U, // VFNMSUB213PDZrk >+ 1888076366U, // VFNMSUB213PDZrkz >+ 571394509U, // VFNMSUB213PSZm >+ 1429146061U, // VFNMSUB213PSZmb >+ 570788301U, // VFNMSUB213PSZr >+ 1888078285U, // VFNMSUB213PSZrk >+ 1888078285U, // VFNMSUB213PSZrkz >+ 300241738U, // VFNMSUBPD4mr >+ 92623690U, // VFNMSUBPD4mrY >+ 303092554U, // VFNMSUBPD4rm >+ 303108938U, // VFNMSUBPD4rmY >+ 302355274U, // VFNMSUBPD4rr >+ 302355274U, // VFNMSUBPD4rrY >+ 302355274U, // VFNMSUBPD4rrY_REV >+ 302355274U, // VFNMSUBPD4rr_REV >+ 571527763U, // VFNMSUBPDr132m >+ 571544147U, // VFNMSUBPDr132mY >+ 570790483U, // VFNMSUBPDr132r >+ 570790483U, // VFNMSUBPDr132rY >+ 571527893U, // VFNMSUBPDr213m >+ 571544277U, // VFNMSUBPDr213mY >+ 570790613U, // VFNMSUBPDr213r >+ 570790613U, // VFNMSUBPDr213rY >+ 571527677U, // VFNMSUBPDr231m >+ 571544061U, // VFNMSUBPDr231mY >+ 570790397U, // VFNMSUBPDr231r >+ 570790397U, // VFNMSUBPDr231rY >+ 300246419U, // VFNMSUBPS4mr >+ 92628371U, // VFNMSUBPS4mrY >+ 303097235U, // VFNMSUBPS4rm >+ 303113619U, // VFNMSUBPS4rmY >+ 302359955U, // VFNMSUBPS4rr >+ 302359955U, // VFNMSUBPS4rrY >+ 302359955U, // VFNMSUBPS4rrY_REV >+ 302359955U, // VFNMSUBPS4rr_REV >+ 571532441U, // VFNMSUBPSr132m >+ 571548825U, // VFNMSUBPSr132mY >+ 570795161U, // VFNMSUBPSr132r >+ 570795161U, // VFNMSUBPSr132rY >+ 571532582U, // VFNMSUBPSr213m >+ 571548966U, // VFNMSUBPSr213mY >+ 570795302U, // VFNMSUBPSr213r >+ 570795302U, // VFNMSUBPSr213rY >+ 571532355U, // VFNMSUBPSr231m >+ 571548739U, // VFNMSUBPSr231mY >+ 570795075U, // VFNMSUBPSr231r >+ 570795075U, // VFNMSUBPSr231rY >+ 312825231U, // VFNMSUBSD4mr >+ 312825231U, // VFNMSUBSD4mr_Int >+ 1357813135U, // VFNMSUBSD4rm >+ 1357813135U, // VFNMSUBSD4rm_Int >+ 302355855U, // VFNMSUBSD4rr >+ 302355855U, // VFNMSUBSD4rr_Int >+ 302355855U, // VFNMSUBSD4rr_REV >+ 571524193U, // VFNMSUBSDZm >+ 570786913U, // VFNMSUBSDZr >+ 1357813011U, // VFNMSUBSDr132m >+ 570791187U, // VFNMSUBSDr132r >+ 1357813076U, // VFNMSUBSDr213m >+ 570791252U, // VFNMSUBSDr213r >+ 1357812957U, // VFNMSUBSDr231m >+ 570791133U, // VFNMSUBSDr231r >+ 317024296U, // VFNMSUBSS4mr >+ 317024296U, // VFNMSUBSS4mr_Int >+ 1357850664U, // VFNMSUBSS4rm >+ 1357850664U, // VFNMSUBSS4rm_Int >+ 302360616U, // VFNMSUBSS4rr >+ 302360616U, // VFNMSUBSS4rr_Int >+ 302360616U, // VFNMSUBSS4rr_REV >+ 571526011U, // VFNMSUBSSZm >+ 570788731U, // VFNMSUBSSZr >+ 1357850548U, // VFNMSUBSSr132m >+ 570795956U, // VFNMSUBSSr132r >+ 1357850613U, // VFNMSUBSSr213m >+ 570796021U, // VFNMSUBSSr213r >+ 1357850494U, // VFNMSUBSSr231m >+ 570795902U, // VFNMSUBSSr231r >+ 578719U, // VFRCZPDrm >+ 1070239U, // VFRCZPDrmY >+ 551818399U, // VFRCZPDrr >+ 551818399U, // VFRCZPDrrY >+ 583494U, // VFRCZPSrm >+ 1075014U, // VFRCZPSrmY >+ 551823174U, // VFRCZPSrr >+ 551823174U, // VFRCZPSrrY >+ 595518U, // VFRCZSDrm >+ 551818814U, // VFRCZSDrr >+ 616663U, // VFRCZSSrm >+ 551823575U, // VFRCZSSrr >+ 811734040U, // VFsANDNPDrm >+ 811652120U, // VFsANDNPDrr >+ 811738750U, // VFsANDNPSrm >+ 811656830U, // VFsANDNPSrr >+ 811733904U, // VFsANDPDrm >+ 811651984U, // VFsANDPDrr >+ 811738585U, // VFsANDPSrm >+ 811656665U, // VFsANDPSrr >+ 811734084U, // VFsORPDrm >+ 811652164U, // VFsORPDrr >+ 811738802U, // VFsORPSrm >+ 811656882U, // VFsORPSrr >+ 811734091U, // VFsXORPDrm >+ 811652171U, // VFsXORPDrr >+ 811738809U, // VFsXORPSrm >+ 811656889U, // VFsXORPSrr >+ 108090284U, // VGATHERDPDYrm >+ 552698639U, // VGATHERDPDZrm >+ 108090284U, // VGATHERDPDrm >+ 110192117U, // VGATHERDPSYrm >+ 552716942U, // VGATHERDPSZrm >+ 110192117U, // VGATHERDPSrm >+ 111395524U, // VGATHERPF0DPDm >+ 111397443U, // VGATHERPF0DPSm >+ 111428479U, // VGATHERPF0QPDm >+ 111430398U, // VGATHERPF0QPSm >+ 111395557U, // VGATHERPF1DPDm >+ 111397476U, // VGATHERPF1DPSm >+ 111428512U, // VGATHERPF1QPDm >+ 111430431U, // VGATHERPF1QPSm >+ 108090424U, // VGATHERQPDYrm >+ 552698817U, // VGATHERQPDZrm >+ 108090424U, // VGATHERQPDrm >+ 110192294U, // VGATHERQPSYrm >+ 552700736U, // VGATHERQPSZrm >+ 110192294U, // VGATHERQPSrm >+ 812520298U, // VHADDPDYrm >+ 811651946U, // VHADDPDYrr >+ 811733866U, // VHADDPDrm >+ 811651946U, // VHADDPDrr >+ 812524979U, // VHADDPSYrm >+ 811656627U, // VHADDPSYrr >+ 811738547U, // VHADDPSrm >+ 811656627U, // VHADDPSrr >+ 812520247U, // VHSUBPDYrm >+ 811651895U, // VHSUBPDYrr >+ 811733815U, // VHSUBPDrm >+ 811651895U, // VHSUBPDrr >+ 812524928U, // VHSUBPSYrm >+ 811656576U, // VHSUBPSYrr >+ 811738496U, // VHSUBPSrm >+ 811656576U, // VHSUBPSrr >+ 300240367U, // VINSERTF128rm >+ 302353903U, // VINSERTF128rr >+ 300240229U, // VINSERTF32x4rm >+ 302353765U, // VINSERTF32x4rr >+ 105205151U, // VINSERTF64x4rm >+ 302353823U, // VINSERTF64x4rr >+ 340086310U, // VINSERTI128rm >+ 302353958U, // VINSERTI128rr >+ 340086146U, // VINSERTI32x4rm >+ 302353794U, // VINSERTI32x4rr >+ 105205180U, // VINSERTI64x4rm >+ 302353852U, // VINSERTI64x4rr >+ 317023959U, // VINSERTPSrm >+ 302360279U, // VINSERTPSrr >+ 317023959U, // VINSERTPSzrm >+ 302360279U, // VINSERTPSzrr >+ 1026443U, // VLDDQUYrm >+ 321931U, // VLDDQUrm >+ 238501U, // VLDMXCSR >+ 551823763U, // VMASKMOVDQU >+ 551823763U, // VMASKMOVDQU64 >+ 3003454603U, // VMASKMOVPDYmr >+ 812520587U, // VMASKMOVPDYrm >+ 2735019147U, // VMASKMOVPDmr >+ 811734155U, // VMASKMOVPDrm >+ 3003459378U, // VMASKMOVPSYmr >+ 812525362U, // VMASKMOVPSYrm >+ 2735023922U, // VMASKMOVPSmr >+ 811738930U, // VMASKMOVPSrm >+ 812520599U, // VMAXCPDYrm >+ 811652247U, // VMAXCPDYrr >+ 811734167U, // VMAXCPDrm >+ 811652247U, // VMAXCPDrr >+ 812525374U, // VMAXCPSYrm >+ 811657022U, // VMAXCPSYrr >+ 811738942U, // VMAXCPSrm >+ 811657022U, // VMAXCPSrr >+ 283268662U, // VMAXCSDrm >+ 811652662U, // VMAXCSDrr >+ 283289807U, // VMAXCSSrm >+ 811657423U, // VMAXCSSrr >+ 812520599U, // VMAXPDYrm >+ 811652247U, // VMAXPDYrr >+ 812532709U, // VMAXPDZrm >+ 352469989U, // VMAXPDZrmb >+ 1427014629U, // VMAXPDZrmbk >+ 1427014629U, // VMAXPDZrmbkz >+ 571397271U, // VMAXPDZrmk >+ 571397271U, // VMAXPDZrmkz >+ 811647973U, // VMAXPDZrr >+ 570786789U, // VMAXPDZrrk >+ 570786789U, // VMAXPDZrrkz >+ 811734167U, // VMAXPDrm >+ 811652247U, // VMAXPDrr >+ 812525374U, // VMAXPSYrm >+ 811657022U, // VMAXPSYrr >+ 812534628U, // VMAXPSZrm >+ 354585444U, // VMAXPSZrmb >+ 1429146468U, // VMAXPSZrmbk >+ 1429146468U, // VMAXPSZrmbkz >+ 571402046U, // VMAXPSZrmk >+ 571402046U, // VMAXPSZrmkz >+ 811649892U, // VMAXPSZrr >+ 570788708U, // VMAXPSZrrk >+ 570788708U, // VMAXPSZrrkz >+ 811738942U, // VMAXPSrm >+ 811657022U, // VMAXPSrr >+ 283268662U, // VMAXSDZrm >+ 811652662U, // VMAXSDZrr >+ 283268662U, // VMAXSDrm >+ 283268662U, // VMAXSDrm_Int >+ 811652662U, // VMAXSDrr >+ 811652662U, // VMAXSDrr_Int >+ 283289807U, // VMAXSSZrm >+ 811657423U, // VMAXSSZrr >+ 283289807U, // VMAXSSrm >+ 283289807U, // VMAXSSrm_Int >+ 811657423U, // VMAXSSrr >+ 811657423U, // VMAXSSrr_Int >+ 14519U, // VMCALL >+ 402271U, // VMCLEARm >+ 14231U, // VMFUNC >+ 812520481U, // VMINCPDYrm >+ 811652129U, // VMINCPDYrr >+ 811734049U, // VMINCPDrm >+ 811652129U, // VMINCPDrr >+ 812525191U, // VMINCPSYrm >+ 811656839U, // VMINCPSYrr >+ 811738759U, // VMINCPSrm >+ 811656839U, // VMINCPSrr >+ 283268589U, // VMINCSDrm >+ 811652589U, // VMINCSDrr >+ 283289725U, // VMINCSSrm >+ 811657341U, // VMINCSSrr >+ 812520481U, // VMINPDYrm >+ 811652129U, // VMINPDYrr >+ 812532589U, // VMINPDZrm >+ 352469869U, // VMINPDZrmb >+ 1427014509U, // VMINPDZrmbk >+ 1427014509U, // VMINPDZrmbkz >+ 571397153U, // VMINPDZrmk >+ 571397153U, // VMINPDZrmkz >+ 811647853U, // VMINPDZrr >+ 570786669U, // VMINPDZrrk >+ 570786669U, // VMINPDZrrkz >+ 811734049U, // VMINPDrm >+ 811652129U, // VMINPDrr >+ 812525191U, // VMINPSYrm >+ 811656839U, // VMINPSYrr >+ 812534508U, // VMINPSZrm >+ 354585324U, // VMINPSZrmb >+ 1429146348U, // VMINPSZrmbk >+ 1429146348U, // VMINPSZrmbkz >+ 571401863U, // VMINPSZrmk >+ 571401863U, // VMINPSZrmkz >+ 811649772U, // VMINPSZrr >+ 570788588U, // VMINPSZrrk >+ 570788588U, // VMINPSZrrkz >+ 811738759U, // VMINPSrm >+ 811656839U, // VMINPSrr >+ 283268589U, // VMINSDZrm >+ 811652589U, // VMINSDZrr >+ 283268589U, // VMINSDrm >+ 283268589U, // VMINSDrm_Int >+ 811652589U, // VMINSDrr >+ 811652589U, // VMINSDrr_Int >+ 283289725U, // VMINSSZrm >+ 811657341U, // VMINSSZrr >+ 283289725U, // VMINSSrm >+ 283289725U, // VMINSSrm_Int >+ 811657341U, // VMINSSrr >+ 811657341U, // VMINSSrr_Int >+ 14419U, // VMLAUNCH >+ 15375U, // VMLOAD32 >+ 15455U, // VMLOAD64 >+ 14511U, // VMMCALL >+ 551822053U, // VMOV64toPQIZrr >+ 551822053U, // VMOV64toPQIrr >+ 551822053U, // VMOV64toSDZrr >+ 551838437U, // VMOV64toSDrm >+ 551822053U, // VMOV64toSDrr >+ 113283854U, // VMOVAPDYmr >+ 1069838U, // VMOVAPDYrm >+ 551817998U, // VMOVAPDYrr >+ 551817998U, // VMOVAPDYrr_REV >+ 62952206U, // VMOVAPDZ128mr >+ 1942295310U, // VMOVAPDZ128mrk >+ 578318U, // VMOVAPDZ128rm >+ 1888539406U, // VMOVAPDZ128rmk >+ 1887572750U, // VMOVAPDZ128rmkz >+ 551817998U, // VMOVAPDZ128rr >+ 551817998U, // VMOVAPDZ128rr_alt >+ 1887802126U, // VMOVAPDZ128rrk >+ 1887802126U, // VMOVAPDZ128rrk_alt >+ 1887490830U, // VMOVAPDZ128rrkz >+ 1887490830U, // VMOVAPDZ128rrkz_alt >+ 113283854U, // VMOVAPDZ256mr >+ 1992626958U, // VMOVAPDZ256mrk >+ 1069838U, // VMOVAPDZ256rm >+ 1888555790U, // VMOVAPDZ256rmk >+ 1888359182U, // VMOVAPDZ256rmkz >+ 551817998U, // VMOVAPDZ256rr >+ 551817998U, // VMOVAPDZ256rr_alt >+ 1887802126U, // VMOVAPDZ256rrk >+ 1887802126U, // VMOVAPDZ256rrk_alt >+ 1887490830U, // VMOVAPDZ256rrkz >+ 1887490830U, // VMOVAPDZ256rrkz_alt >+ 115381006U, // VMOVAPDZmr >+ 1994724110U, // VMOVAPDZmrk >+ 1086222U, // VMOVAPDZrm >+ 1888408334U, // VMOVAPDZrmk >+ 1888375566U, // VMOVAPDZrmkz >+ 551817998U, // VMOVAPDZrr >+ 551817998U, // VMOVAPDZrr_alt >+ 1887802126U, // VMOVAPDZrrk >+ 1887802126U, // VMOVAPDZrrk_alt >+ 1887490830U, // VMOVAPDZrrkz >+ 1887490830U, // VMOVAPDZrrkz_alt >+ 62952206U, // VMOVAPDmr >+ 578318U, // VMOVAPDrm >+ 551817998U, // VMOVAPDrr >+ 551817998U, // VMOVAPDrr_REV >+ 113288543U, // VMOVAPSYmr >+ 1074527U, // VMOVAPSYrm >+ 551822687U, // VMOVAPSYrr >+ 551822687U, // VMOVAPSYrr_REV >+ 62956895U, // VMOVAPSZ128mr >+ 1942299999U, // VMOVAPSZ128mrk >+ 583007U, // VMOVAPSZ128rm >+ 1888544095U, // VMOVAPSZ128rmk >+ 1887577439U, // VMOVAPSZ128rmkz >+ 551822687U, // VMOVAPSZ128rr >+ 551822687U, // VMOVAPSZ128rr_alt >+ 1887806815U, // VMOVAPSZ128rrk >+ 1887806815U, // VMOVAPSZ128rrk_alt >+ 1887495519U, // VMOVAPSZ128rrkz >+ 1887495519U, // VMOVAPSZ128rrkz_alt >+ 113288543U, // VMOVAPSZ256mr >+ 1992631647U, // VMOVAPSZ256mrk >+ 1074527U, // VMOVAPSZ256rm >+ 1888560479U, // VMOVAPSZ256rmk >+ 1888363871U, // VMOVAPSZ256rmkz >+ 551822687U, // VMOVAPSZ256rr >+ 551822687U, // VMOVAPSZ256rr_alt >+ 1887806815U, // VMOVAPSZ256rrk >+ 1887806815U, // VMOVAPSZ256rrk_alt >+ 1887495519U, // VMOVAPSZ256rrkz >+ 1887495519U, // VMOVAPSZ256rrkz_alt >+ 115385695U, // VMOVAPSZmr >+ 1994728799U, // VMOVAPSZmrk >+ 1090911U, // VMOVAPSZrm >+ 1888413023U, // VMOVAPSZrmk >+ 1888380255U, // VMOVAPSZrmkz >+ 551822687U, // VMOVAPSZrr >+ 551822687U, // VMOVAPSZrr_alt >+ 1887806815U, // VMOVAPSZrrk >+ 1887806815U, // VMOVAPSZrrk_alt >+ 1887495519U, // VMOVAPSZrrkz >+ 1887495519U, // VMOVAPSZrrkz_alt >+ 62956895U, // VMOVAPSmr >+ 583007U, // VMOVAPSrm >+ 551822687U, // VMOVAPSrr >+ 551822687U, // VMOVAPSrr_REV >+ 1072604U, // VMOVDDUPYrm >+ 551820764U, // VMOVDDUPYrr >+ 1082924U, // VMOVDDUPZrm >+ 551814700U, // VMOVDDUPZrr >+ 597468U, // VMOVDDUPrm >+ 551820764U, // VMOVDDUPrr >+ 551802546U, // VMOVDI2PDIZrm >+ 551818930U, // VMOVDI2PDIZrr >+ 551802546U, // VMOVDI2PDIrm >+ 551818930U, // VMOVDI2PDIrr >+ 551802546U, // VMOVDI2SSZrm >+ 551818930U, // VMOVDI2SSZrr >+ 551802546U, // VMOVDI2SSrm >+ 551818930U, // VMOVDI2SSrr >+ 65047782U, // VMOVDQA32Z128mr >+ 1944390886U, // VMOVDQA32Z128mrk >+ 314598U, // VMOVDQA32Z128rm >+ 1888619750U, // VMOVDQA32Z128rmk >+ 1887735014U, // VMOVDQA32Z128rmkz >+ 551816422U, // VMOVDQA32Z128rr >+ 551816422U, // VMOVDQA32Z128rr_alt >+ 1887800550U, // VMOVDQA32Z128rrk >+ 1887800550U, // VMOVDQA32Z128rrk_alt >+ 1887489254U, // VMOVDQA32Z128rrkz >+ 1887489254U, // VMOVDQA32Z128rrkz_alt >+ 117476582U, // VMOVDQA32Z256mr >+ 1996819686U, // VMOVDQA32Z256mrk >+ 1019110U, // VMOVDQA32Z256rm >+ 1888636134U, // VMOVDQA32Z256rmk >+ 1888439526U, // VMOVDQA32Z256rmkz >+ 551816422U, // VMOVDQA32Z256rr >+ 551816422U, // VMOVDQA32Z256rr_alt >+ 1887800550U, // VMOVDQA32Z256rrk >+ 1887800550U, // VMOVDQA32Z256rrk_alt >+ 1887489254U, // VMOVDQA32Z256rrkz >+ 1887489254U, // VMOVDQA32Z256rrkz_alt >+ 119573734U, // VMOVDQA32Zmr >+ 1998916838U, // VMOVDQA32Zmrk >+ 1035494U, // VMOVDQA32Zrm >+ 1888652518U, // VMOVDQA32Zrmk >+ 1888668902U, // VMOVDQA32Zrmkz >+ 551816422U, // VMOVDQA32Zrr >+ 551816422U, // VMOVDQA32Zrr_alt >+ 1887800550U, // VMOVDQA32Zrrk >+ 1887800550U, // VMOVDQA32Zrrk_alt >+ 1887489254U, // VMOVDQA32Zrrkz >+ 1887489254U, // VMOVDQA32Zrrkz_alt >+ 65047861U, // VMOVDQA64Z128mr >+ 1944390965U, // VMOVDQA64Z128mrk >+ 314677U, // VMOVDQA64Z128rm >+ 1888619829U, // VMOVDQA64Z128rmk >+ 1887735093U, // VMOVDQA64Z128rmkz >+ 551816501U, // VMOVDQA64Z128rr >+ 551816501U, // VMOVDQA64Z128rr_alt >+ 1887800629U, // VMOVDQA64Z128rrk >+ 1887800629U, // VMOVDQA64Z128rrk_alt >+ 1887489333U, // VMOVDQA64Z128rrkz >+ 1887489333U, // VMOVDQA64Z128rrkz_alt >+ 117476661U, // VMOVDQA64Z256mr >+ 1996819765U, // VMOVDQA64Z256mrk >+ 1019189U, // VMOVDQA64Z256rm >+ 1888636213U, // VMOVDQA64Z256rmk >+ 1888439605U, // VMOVDQA64Z256rmkz >+ 551816501U, // VMOVDQA64Z256rr >+ 551816501U, // VMOVDQA64Z256rr_alt >+ 1887800629U, // VMOVDQA64Z256rrk >+ 1887800629U, // VMOVDQA64Z256rrk_alt >+ 1887489333U, // VMOVDQA64Z256rrkz >+ 1887489333U, // VMOVDQA64Z256rrkz_alt >+ 119573813U, // VMOVDQA64Zmr >+ 1998916917U, // VMOVDQA64Zmrk >+ 1035573U, // VMOVDQA64Zrm >+ 1888652597U, // VMOVDQA64Zrmk >+ 1888668981U, // VMOVDQA64Zrmkz >+ 551816501U, // VMOVDQA64Zrr >+ 551816501U, // VMOVDQA64Zrr_alt >+ 1887800629U, // VMOVDQA64Zrrk >+ 1887800629U, // VMOVDQA64Zrrk_alt >+ 1887489333U, // VMOVDQA64Zrrkz >+ 1887489333U, // VMOVDQA64Zrrkz_alt >+ 117476956U, // VMOVDQAYmr >+ 1019484U, // VMOVDQAYrm >+ 551816796U, // VMOVDQAYrr >+ 551816796U, // VMOVDQAYrr_REV >+ 65048156U, // VMOVDQAmr >+ 314972U, // VMOVDQArm >+ 551816796U, // VMOVDQArr >+ 551816796U, // VMOVDQArr_REV >+ 65048010U, // VMOVDQU16Z128mr >+ 1944391114U, // VMOVDQU16Z128mrk >+ 314826U, // VMOVDQU16Z128rm >+ 1888619978U, // VMOVDQU16Z128rmk >+ 1887735242U, // VMOVDQU16Z128rmkz >+ 551816650U, // VMOVDQU16Z128rr >+ 551816650U, // VMOVDQU16Z128rr_alt >+ 1887800778U, // VMOVDQU16Z128rrk >+ 1887800778U, // VMOVDQU16Z128rrk_alt >+ 1887489482U, // VMOVDQU16Z128rrkz >+ 1887489482U, // VMOVDQU16Z128rrkz_alt >+ 117476810U, // VMOVDQU16Z256mr >+ 1996819914U, // VMOVDQU16Z256mrk >+ 1019338U, // VMOVDQU16Z256rm >+ 1888636362U, // VMOVDQU16Z256rmk >+ 1888439754U, // VMOVDQU16Z256rmkz >+ 551816650U, // VMOVDQU16Z256rr >+ 551816650U, // VMOVDQU16Z256rr_alt >+ 1887800778U, // VMOVDQU16Z256rrk >+ 1887800778U, // VMOVDQU16Z256rrk_alt >+ 1887489482U, // VMOVDQU16Z256rrkz >+ 1887489482U, // VMOVDQU16Z256rrkz_alt >+ 119573962U, // VMOVDQU16Zmr >+ 1998917066U, // VMOVDQU16Zmrk >+ 1035722U, // VMOVDQU16Zrm >+ 1888652746U, // VMOVDQU16Zrmk >+ 1888669130U, // VMOVDQU16Zrmkz >+ 551816650U, // VMOVDQU16Zrr >+ 551816650U, // VMOVDQU16Zrr_alt >+ 1887800778U, // VMOVDQU16Zrrk >+ 1887800778U, // VMOVDQU16Zrrk_alt >+ 1887489482U, // VMOVDQU16Zrrkz >+ 1887489482U, // VMOVDQU16Zrrkz_alt >+ 65047793U, // VMOVDQU32Z128mr >+ 1944390897U, // VMOVDQU32Z128mrk >+ 314609U, // VMOVDQU32Z128rm >+ 1888619761U, // VMOVDQU32Z128rmk >+ 1887735025U, // VMOVDQU32Z128rmkz >+ 551816433U, // VMOVDQU32Z128rr >+ 551816433U, // VMOVDQU32Z128rr_alt >+ 1887800561U, // VMOVDQU32Z128rrk >+ 1887800561U, // VMOVDQU32Z128rrk_alt >+ 1887489265U, // VMOVDQU32Z128rrkz >+ 1887489265U, // VMOVDQU32Z128rrkz_alt >+ 117476593U, // VMOVDQU32Z256mr >+ 1996819697U, // VMOVDQU32Z256mrk >+ 1019121U, // VMOVDQU32Z256rm >+ 1888636145U, // VMOVDQU32Z256rmk >+ 1888439537U, // VMOVDQU32Z256rmkz >+ 551816433U, // VMOVDQU32Z256rr >+ 551816433U, // VMOVDQU32Z256rr_alt >+ 1887800561U, // VMOVDQU32Z256rrk >+ 1887800561U, // VMOVDQU32Z256rrk_alt >+ 1887489265U, // VMOVDQU32Z256rrkz >+ 1887489265U, // VMOVDQU32Z256rrkz_alt >+ 119573745U, // VMOVDQU32Zmr >+ 1998916849U, // VMOVDQU32Zmrk >+ 1035505U, // VMOVDQU32Zrm >+ 1888652529U, // VMOVDQU32Zrmk >+ 1888668913U, // VMOVDQU32Zrmkz >+ 551816433U, // VMOVDQU32Zrr >+ 551816433U, // VMOVDQU32Zrr_alt >+ 1887800561U, // VMOVDQU32Zrrk >+ 1887800561U, // VMOVDQU32Zrrk_alt >+ 1887489265U, // VMOVDQU32Zrrkz >+ 1887489265U, // VMOVDQU32Zrrkz_alt >+ 65047872U, // VMOVDQU64Z128mr >+ 1944390976U, // VMOVDQU64Z128mrk >+ 314688U, // VMOVDQU64Z128rm >+ 1888619840U, // VMOVDQU64Z128rmk >+ 1887735104U, // VMOVDQU64Z128rmkz >+ 551816512U, // VMOVDQU64Z128rr >+ 551816512U, // VMOVDQU64Z128rr_alt >+ 1887800640U, // VMOVDQU64Z128rrk >+ 1887800640U, // VMOVDQU64Z128rrk_alt >+ 1887489344U, // VMOVDQU64Z128rrkz >+ 1887489344U, // VMOVDQU64Z128rrkz_alt >+ 117476672U, // VMOVDQU64Z256mr >+ 1996819776U, // VMOVDQU64Z256mrk >+ 1019200U, // VMOVDQU64Z256rm >+ 1888636224U, // VMOVDQU64Z256rmk >+ 1888439616U, // VMOVDQU64Z256rmkz >+ 551816512U, // VMOVDQU64Z256rr >+ 551816512U, // VMOVDQU64Z256rr_alt >+ 1887800640U, // VMOVDQU64Z256rrk >+ 1887800640U, // VMOVDQU64Z256rrk_alt >+ 1887489344U, // VMOVDQU64Z256rrkz >+ 1887489344U, // VMOVDQU64Z256rrkz_alt >+ 119573824U, // VMOVDQU64Zmr >+ 1998916928U, // VMOVDQU64Zmrk >+ 1035584U, // VMOVDQU64Zrm >+ 1888652608U, // VMOVDQU64Zrmk >+ 1888668992U, // VMOVDQU64Zrmkz >+ 551816512U, // VMOVDQU64Zrr >+ 551816512U, // VMOVDQU64Zrr_alt >+ 1887800640U, // VMOVDQU64Zrrk >+ 1887800640U, // VMOVDQU64Zrrk_alt >+ 1887489344U, // VMOVDQU64Zrrkz >+ 1887489344U, // VMOVDQU64Zrrkz_alt >+ 65048131U, // VMOVDQU8Z128mr >+ 1944391235U, // VMOVDQU8Z128mrk >+ 314947U, // VMOVDQU8Z128rm >+ 1888620099U, // VMOVDQU8Z128rmk >+ 1887735363U, // VMOVDQU8Z128rmkz >+ 551816771U, // VMOVDQU8Z128rr >+ 551816771U, // VMOVDQU8Z128rr_alt >+ 1887800899U, // VMOVDQU8Z128rrk >+ 1887800899U, // VMOVDQU8Z128rrk_alt >+ 1887489603U, // VMOVDQU8Z128rrkz >+ 1887489603U, // VMOVDQU8Z128rrkz_alt >+ 117476931U, // VMOVDQU8Z256mr >+ 1996820035U, // VMOVDQU8Z256mrk >+ 1019459U, // VMOVDQU8Z256rm >+ 1888636483U, // VMOVDQU8Z256rmk >+ 1888439875U, // VMOVDQU8Z256rmkz >+ 551816771U, // VMOVDQU8Z256rr >+ 551816771U, // VMOVDQU8Z256rr_alt >+ 1887800899U, // VMOVDQU8Z256rrk >+ 1887800899U, // VMOVDQU8Z256rrk_alt >+ 1887489603U, // VMOVDQU8Z256rrkz >+ 1887489603U, // VMOVDQU8Z256rrkz_alt >+ 119574083U, // VMOVDQU8Zmr >+ 1998917187U, // VMOVDQU8Zmrk >+ 1035843U, // VMOVDQU8Zrm >+ 1888652867U, // VMOVDQU8Zrmk >+ 1888669251U, // VMOVDQU8Zrmkz >+ 551816771U, // VMOVDQU8Zrr >+ 551816771U, // VMOVDQU8Zrr_alt >+ 1887800899U, // VMOVDQU8Zrrk >+ 1887800899U, // VMOVDQU8Zrrk_alt >+ 1887489603U, // VMOVDQU8Zrrkz >+ 1887489603U, // VMOVDQU8Zrrkz_alt >+ 117483936U, // VMOVDQUYmr >+ 1026464U, // VMOVDQUYrm >+ 551823776U, // VMOVDQUYrr >+ 551823776U, // VMOVDQUYrr_REV >+ 65055136U, // VMOVDQUmr >+ 321952U, // VMOVDQUrm >+ 551823776U, // VMOVDQUrr >+ 551823776U, // VMOVDQUrr_REV >+ 811656755U, // VMOVHLPSZrr >+ 811656755U, // VMOVHLPSrr >+ 67146700U, // VMOVHPDmr >+ 283268044U, // VMOVHPDrm >+ 67151391U, // VMOVHPSmr >+ 283272735U, // VMOVHPSrm >+ 811656725U, // VMOVLHPSZrr >+ 811656725U, // VMOVLHPSrr >+ 67146750U, // VMOVLPDmr >+ 283268094U, // VMOVLPDrm >+ 67151451U, // VMOVLPSmr >+ 283272795U, // VMOVLPSrm >+ 551818197U, // VMOVMSKPDYrr >+ 551818197U, // VMOVMSKPDrr >+ 551822888U, // VMOVMSKPSYrr >+ 551822888U, // VMOVMSKPSrr >+ 1019473U, // VMOVNTDQAYrm >+ 314961U, // VMOVNTDQAZ128rm >+ 1019473U, // VMOVNTDQAZ256rm >+ 1035857U, // VMOVNTDQAZrm >+ 314961U, // VMOVNTDQArm >+ 113287076U, // VMOVNTDQYmr >+ 65052580U, // VMOVNTDQZ128mr >+ 117481380U, // VMOVNTDQZ256mr >+ 119578532U, // VMOVNTDQZmr >+ 62955428U, // VMOVNTDQmr >+ 113284179U, // VMOVNTPDYmr >+ 62952531U, // VMOVNTPDZ128mr >+ 113284179U, // VMOVNTPDZ256mr >+ 115381331U, // VMOVNTPDZmr >+ 62952531U, // VMOVNTPDmr >+ 113288909U, // VMOVNTPSYmr >+ 62957261U, // VMOVNTPSZ128mr >+ 113288909U, // VMOVNTPSZ256mr >+ 115386061U, // VMOVNTPSZmr >+ 62957261U, // VMOVNTPSmr >+ 12621490U, // VMOVPDI2DIZmr >+ 551818930U, // VMOVPDI2DIZrr >+ 12621490U, // VMOVPDI2DImr >+ 551818930U, // VMOVPDI2DIrr >+ 18916069U, // VMOVPQI2QImr >+ 551822053U, // VMOVPQI2QIrr >+ 18916069U, // VMOVPQIto64Zmr >+ 551822053U, // VMOVPQIto64Zrr >+ 551822053U, // VMOVPQIto64rr >+ 551838437U, // VMOVQI2PQIZrm >+ 551838437U, // VMOVQI2PQIrm >+ 67142893U, // VMOVSDZmr >+ 591085U, // VMOVSDZrm >+ 811648237U, // VMOVSDZrr >+ 811652645U, // VMOVSDZrr_REV >+ 1888077037U, // VMOVSDZrrk >+ 67147301U, // VMOVSDmr >+ 595493U, // VMOVSDrm >+ 811652645U, // VMOVSDrr >+ 811652645U, // VMOVSDrr_REV >+ 18916069U, // VMOVSDto64Zmr >+ 551822053U, // VMOVSDto64Zrr >+ 18916069U, // VMOVSDto64mr >+ 551822053U, // VMOVSDto64rr >+ 1072614U, // VMOVSHDUPYrm >+ 551820774U, // VMOVSHDUPYrr >+ 1082935U, // VMOVSHDUPZrm >+ 551814711U, // VMOVSHDUPZrr >+ 581094U, // VMOVSHDUPrm >+ 551820774U, // VMOVSHDUPrr >+ 1072625U, // VMOVSLDUPYrm >+ 551820785U, // VMOVSLDUPYrr >+ 1082947U, // VMOVSLDUPZrm >+ 551814723U, // VMOVSLDUPZrr >+ 581105U, // VMOVSLDUPrm >+ 551820785U, // VMOVSLDUPrr >+ 12621490U, // VMOVSS2DIZmr >+ 551818930U, // VMOVSS2DIZrr >+ 12621490U, // VMOVSS2DImr >+ 551818930U, // VMOVSS2DIrr >+ 69241844U, // VMOVSSZmr >+ 609268U, // VMOVSSZrm >+ 811650036U, // VMOVSSZrr >+ 811657415U, // VMOVSSZrr_REV >+ 1888078836U, // VMOVSSZrrk >+ 69249223U, // VMOVSSmr >+ 616647U, // VMOVSSrm >+ 811657415U, // VMOVSSrr >+ 811657415U, // VMOVSSrr_REV >+ 113284207U, // VMOVUPDYmr >+ 1070191U, // VMOVUPDYrm >+ 551818351U, // VMOVUPDYrr >+ 551818351U, // VMOVUPDYrr_REV >+ 62952559U, // VMOVUPDZ128mr >+ 1942295663U, // VMOVUPDZ128mrk >+ 578671U, // VMOVUPDZ128rm >+ 1888539759U, // VMOVUPDZ128rmk >+ 1887573103U, // VMOVUPDZ128rmkz >+ 551818351U, // VMOVUPDZ128rr >+ 551818351U, // VMOVUPDZ128rr_alt >+ 1887802479U, // VMOVUPDZ128rrk >+ 1887802479U, // VMOVUPDZ128rrk_alt >+ 1887491183U, // VMOVUPDZ128rrkz >+ 1887491183U, // VMOVUPDZ128rrkz_alt >+ 113284207U, // VMOVUPDZ256mr >+ 1992627311U, // VMOVUPDZ256mrk >+ 1070191U, // VMOVUPDZ256rm >+ 1888556143U, // VMOVUPDZ256rmk >+ 1888359535U, // VMOVUPDZ256rmkz >+ 551818351U, // VMOVUPDZ256rr >+ 551818351U, // VMOVUPDZ256rr_alt >+ 1887802479U, // VMOVUPDZ256rrk >+ 1887802479U, // VMOVUPDZ256rrk_alt >+ 1887491183U, // VMOVUPDZ256rrkz >+ 1887491183U, // VMOVUPDZ256rrkz_alt >+ 115381359U, // VMOVUPDZmr >+ 1994724463U, // VMOVUPDZmrk >+ 1086575U, // VMOVUPDZrm >+ 1888408687U, // VMOVUPDZrmk >+ 1888375919U, // VMOVUPDZrmkz >+ 551818351U, // VMOVUPDZrr >+ 551818351U, // VMOVUPDZrr_alt >+ 1887802479U, // VMOVUPDZrrk >+ 1887802479U, // VMOVUPDZrrk_alt >+ 1887491183U, // VMOVUPDZrrkz >+ 1887491183U, // VMOVUPDZrrkz_alt >+ 62952559U, // VMOVUPDmr >+ 578671U, // VMOVUPDrm >+ 551818351U, // VMOVUPDrr >+ 551818351U, // VMOVUPDrr_REV >+ 113288982U, // VMOVUPSYmr >+ 1074966U, // VMOVUPSYrm >+ 551823126U, // VMOVUPSYrr >+ 551823126U, // VMOVUPSYrr_REV >+ 62957334U, // VMOVUPSZ128mr >+ 1942300438U, // VMOVUPSZ128mrk >+ 583446U, // VMOVUPSZ128rm >+ 1888544534U, // VMOVUPSZ128rmk >+ 1887577878U, // VMOVUPSZ128rmkz >+ 551823126U, // VMOVUPSZ128rr >+ 551823126U, // VMOVUPSZ128rr_alt >+ 1887807254U, // VMOVUPSZ128rrk >+ 1887807254U, // VMOVUPSZ128rrk_alt >+ 1887495958U, // VMOVUPSZ128rrkz >+ 1887495958U, // VMOVUPSZ128rrkz_alt >+ 113288982U, // VMOVUPSZ256mr >+ 1992632086U, // VMOVUPSZ256mrk >+ 1074966U, // VMOVUPSZ256rm >+ 1888560918U, // VMOVUPSZ256rmk >+ 1888364310U, // VMOVUPSZ256rmkz >+ 551823126U, // VMOVUPSZ256rr >+ 551823126U, // VMOVUPSZ256rr_alt >+ 1887807254U, // VMOVUPSZ256rrk >+ 1887807254U, // VMOVUPSZ256rrk_alt >+ 1887495958U, // VMOVUPSZ256rrkz >+ 1887495958U, // VMOVUPSZ256rrkz_alt >+ 115386134U, // VMOVUPSZmr >+ 1994729238U, // VMOVUPSZmrk >+ 1091350U, // VMOVUPSZrm >+ 1888413462U, // VMOVUPSZrmk >+ 1888380694U, // VMOVUPSZrmkz >+ 551823126U, // VMOVUPSZrr >+ 551823126U, // VMOVUPSZrr_alt >+ 1887807254U, // VMOVUPSZrrk >+ 1887807254U, // VMOVUPSZrrk_alt >+ 1887495958U, // VMOVUPSZrrkz >+ 1887495958U, // VMOVUPSZrrkz_alt >+ 62957334U, // VMOVUPSmr >+ 583446U, // VMOVUPSrm >+ 551823126U, // VMOVUPSrr >+ 551823126U, // VMOVUPSrr_REV >+ 320229U, // VMOVZPQILo2PQIZrm >+ 551822053U, // VMOVZPQILo2PQIZrr >+ 320229U, // VMOVZPQILo2PQIrm >+ 551822053U, // VMOVZPQILo2PQIrr >+ 551838437U, // VMOVZQI2PQIrm >+ 551822053U, // VMOVZQI2PQIrr >+ 105212422U, // VMPSADBWYrmi >+ 302361094U, // VMPSADBWYrri >+ 340093446U, // VMPSADBWrmi >+ 302361094U, // VMPSADBWrri >+ 397744U, // VMPTRLDm >+ 403833U, // VMPTRSTm >+ 12622125U, // VMREAD32rm >+ 551819565U, // VMREAD32rr >+ 18915034U, // VMREAD64rm >+ 551821018U, // VMREAD64rr >+ 14319U, // VMRESUME >+ 15399U, // VMRUN32 >+ 15479U, // VMRUN64 >+ 15387U, // VMSAVE32 >+ 15467U, // VMSAVE64 >+ 812520438U, // VMULPDYrm >+ 811652086U, // VMULPDYrr >+ 812532558U, // VMULPDZrm >+ 352469838U, // VMULPDZrmb >+ 1427014478U, // VMULPDZrmbk >+ 1427014478U, // VMULPDZrmbkz >+ 571397110U, // VMULPDZrmk >+ 571397110U, // VMULPDZrmkz >+ 811647822U, // VMULPDZrr >+ 570786638U, // VMULPDZrrk >+ 570786638U, // VMULPDZrrkz >+ 811734006U, // VMULPDrm >+ 811652086U, // VMULPDrr >+ 812525139U, // VMULPSYrm >+ 811656787U, // VMULPSYrr >+ 812534477U, // VMULPSZrm >+ 354585293U, // VMULPSZrmb >+ 1429146317U, // VMULPSZrmbk >+ 1429146317U, // VMULPSZrmbkz >+ 571401811U, // VMULPSZrmk >+ 571401811U, // VMULPSZrmkz >+ 811649741U, // VMULPSZrr >+ 570788557U, // VMULPSZrrk >+ 570788557U, // VMULPSZrrkz >+ 811738707U, // VMULPSrm >+ 811656787U, // VMULPSrr >+ 283268572U, // VMULSDZrm >+ 811652572U, // VMULSDZrr >+ 283268572U, // VMULSDrm >+ 283268572U, // VMULSDrm_Int >+ 811652572U, // VMULSDrr >+ 811652572U, // VMULSDrr_Int >+ 283289717U, // VMULSSZrm >+ 811657333U, // VMULSSZrr >+ 283289717U, // VMULSSrm >+ 283289717U, // VMULSSrm_Int >+ 811657333U, // VMULSSrr >+ 811657333U, // VMULSSrr_Int >+ 551803371U, // VMWRITE32rm >+ 551819755U, // VMWRITE32rr >+ 551837755U, // VMWRITE64rm >+ 551821371U, // VMWRITE64rr >+ 14402U, // VMXOFF >+ 400721U, // VMXON >+ 812520516U, // VORPDYrm >+ 811652164U, // VORPDYrr >+ 811734084U, // VORPDrm >+ 811652164U, // VORPDrr >+ 812525234U, // VORPSYrm >+ 811656882U, // VORPSYrr >+ 811738802U, // VORPSrm >+ 811656882U, // VORPSrr >+ 315275U, // VPABSBrm128 >+ 1019787U, // VPABSBrm256 >+ 551817099U, // VPABSBrr128 >+ 551817099U, // VPABSBrr256 >+ 1033405U, // VPABSDZrm >+ 623101117U, // VPABSDZrmb >+ 622937277U, // VPABSDZrmbk >+ 622937277U, // VPABSDZrmbkz >+ 1888666813U, // VPABSDZrmk >+ 1888666813U, // VPABSDZrmkz >+ 551814333U, // VPABSDZrr >+ 1887487165U, // VPABSDZrrk >+ 1887487165U, // VPABSDZrrkz >+ 316797U, // VPABSDrm128 >+ 1021309U, // VPABSDrm256 >+ 551818621U, // VPABSDrr128 >+ 551818621U, // VPABSDrr256 >+ 1034331U, // VPABSQZrm >+ 621037659U, // VPABSQZrmb >+ 620857435U, // VPABSQZrmbk >+ 620857435U, // VPABSQZrmbkz >+ 1888667739U, // VPABSQZrmk >+ 1888667739U, // VPABSQZrmkz >+ 551815259U, // VPABSQZrr >+ 1887488091U, // VPABSQZrrk >+ 1887488091U, // VPABSQZrrkz >+ 322739U, // VPABSWrm128 >+ 1027251U, // VPABSWrm256 >+ 551824563U, // VPABSWrr128 >+ 551824563U, // VPABSWrr256 >+ 812608238U, // VPACKSSDWYrm >+ 811657966U, // VPACKSSDWYrr >+ 811903726U, // VPACKSSDWrm >+ 811657966U, // VPACKSSDWrr >+ 812601448U, // VPACKSSWBYrm >+ 811651176U, // VPACKSSWBYrr >+ 811896936U, // VPACKSSWBrm >+ 811651176U, // VPACKSSWBrr >+ 812608249U, // VPACKUSDWYrm >+ 811657977U, // VPACKUSDWYrr >+ 811903737U, // VPACKUSDWrm >+ 811657977U, // VPACKUSDWrr >+ 812601459U, // VPACKUSWBYrm >+ 811651187U, // VPACKUSWBYrr >+ 811896947U, // VPACKUSWBrm >+ 811651187U, // VPACKUSWBrr >+ 812601023U, // VPADDBYrm >+ 811650751U, // VPADDBYrr >+ 811896511U, // VPADDBrm >+ 811650751U, // VPADDBrr >+ 812601640U, // VPADDDYrm >+ 811651368U, // VPADDDYrr >+ 812826866U, // VPADDDZrm >+ 354500850U, // VPADDDZrmb >+ 4113678578U, // VPADDDZrmbk >+ 1429405938U, // VPADDDZrmbkz >+ 122896626U, // VPADDDZrmk >+ 571638002U, // VPADDDZrmkz >+ 811647218U, // VPADDDZrr >+ 1888076018U, // VPADDDZrrk >+ 570786034U, // VPADDDZrrkz >+ 811897128U, // VPADDDrm >+ 811651368U, // VPADDDrr >+ 812605165U, // VPADDQYrm >+ 811654893U, // VPADDQYrr >+ 812828371U, // VPADDQZrm >+ 352421587U, // VPADDQZrmb >+ 4111566547U, // VPADDQZrmbk >+ 1427343059U, // VPADDQZrmbkz >+ 122898131U, // VPADDQZrmk >+ 571639507U, // VPADDQZrmkz >+ 811648723U, // VPADDQZrr >+ 1888077523U, // VPADDQZrrk >+ 570787539U, // VPADDQZrrkz >+ 811900653U, // VPADDQrm >+ 811654893U, // VPADDQrr >+ 812601253U, // VPADDSBYrm >+ 811650981U, // VPADDSBYrr >+ 811896741U, // VPADDSBrm >+ 811650981U, // VPADDSBrr >+ 812608749U, // VPADDSWYrm >+ 811658477U, // VPADDSWYrr >+ 811904237U, // VPADDSWrm >+ 811658477U, // VPADDSWrr >+ 812601302U, // VPADDUSBYrm >+ 811651030U, // VPADDUSBYrr >+ 811896790U, // VPADDUSBrm >+ 811651030U, // VPADDUSBrr >+ 812608862U, // VPADDUSWYrm >+ 811658590U, // VPADDUSWYrr >+ 811904350U, // VPADDUSWrm >+ 811658590U, // VPADDUSWrr >+ 812608181U, // VPADDWYrm >+ 811657909U, // VPADDWYrr >+ 811903669U, // VPADDWrm >+ 811657909U, // VPADDWrr >+ 340091767U, // VPALIGNR128rm >+ 302359415U, // VPALIGNR128rr >+ 105210743U, // VPALIGNR256rm >+ 302359415U, // VPALIGNR256rr >+ 812826883U, // VPANDDZrm >+ 354500867U, // VPANDDZrmb >+ 4113678595U, // VPANDDZrmbk >+ 1429405955U, // VPANDDZrmbkz >+ 122896643U, // VPANDDZrmk >+ 571638019U, // VPANDDZrmkz >+ 811647235U, // VPANDDZrr >+ 1888076035U, // VPANDDZrrk >+ 570786051U, // VPANDDZrrkz >+ 812827010U, // VPANDNDZrm >+ 354500994U, // VPANDNDZrmb >+ 4113678722U, // VPANDNDZrmbk >+ 1429406082U, // VPANDNDZrmbkz >+ 122896770U, // VPANDNDZrmk >+ 571638146U, // VPANDNDZrmkz >+ 811647362U, // VPANDNDZrr >+ 1888076162U, // VPANDNDZrrk >+ 570786178U, // VPANDNDZrrkz >+ 812828675U, // VPANDNQZrm >+ 352421891U, // VPANDNQZrmb >+ 4111566851U, // VPANDNQZrmbk >+ 1427343363U, // VPANDNQZrmbkz >+ 122898435U, // VPANDNQZrmk >+ 571639811U, // VPANDNQZrmkz >+ 811649027U, // VPANDNQZrr >+ 1888077827U, // VPANDNQZrrk >+ 570787843U, // VPANDNQZrrkz >+ 812604730U, // VPANDNYrm >+ 811654458U, // VPANDNYrr >+ 811900218U, // VPANDNrm >+ 811654458U, // VPANDNrr >+ 812828424U, // VPANDQZrm >+ 352421640U, // VPANDQZrmb >+ 4111566600U, // VPANDQZrmbk >+ 1427343112U, // VPANDQZrmbkz >+ 122898184U, // VPANDQZrmk >+ 571639560U, // VPANDQZrmkz >+ 811648776U, // VPANDQZrr >+ 1888077576U, // VPANDQZrrk >+ 570787592U, // VPANDQZrrkz >+ 812601801U, // VPANDYrm >+ 811651529U, // VPANDYrr >+ 811897289U, // VPANDrm >+ 811651529U, // VPANDrr >+ 812601069U, // VPAVGBYrm >+ 811650797U, // VPAVGBYrr >+ 811896557U, // VPAVGBrm >+ 811650797U, // VPAVGBrr >+ 812608350U, // VPAVGWYrm >+ 811658078U, // VPAVGWYrr >+ 811903838U, // VPAVGWrm >+ 811658078U, // VPAVGWrr >+ 105206064U, // VPBLENDDYrmi >+ 302354736U, // VPBLENDDYrri >+ 340087088U, // VPBLENDDrmi >+ 302354736U, // VPBLENDDrri >+ 571392333U, // VPBLENDMDZrm >+ 570786125U, // VPBLENDMDZrr >+ 571393998U, // VPBLENDMQZrm >+ 570787790U, // VPBLENDMQZrr >+ 105205838U, // VPBLENDVBYrm >+ 302354510U, // VPBLENDVBYrr >+ 340086862U, // VPBLENDVBrm >+ 302354510U, // VPBLENDVBrr >+ 105212637U, // VPBLENDWYrmi >+ 302361309U, // VPBLENDWYrri >+ 340093661U, // VPBLENDWrmi >+ 302361309U, // VPBLENDWrri >+ 446487U, // VPBROADCASTBYrm >+ 551817239U, // VPBROADCASTBYrr >+ 446487U, // VPBROADCASTBrm >+ 551817239U, // VPBROADCASTBrr >+ 551802457U, // VPBROADCASTDYrm >+ 551818841U, // VPBROADCASTDYrr >+ 551634209U, // VPBROADCASTDZkrm >+ 1887487265U, // VPBROADCASTDZkrr >+ 551798049U, // VPBROADCASTDZrm >+ 551814433U, // VPBROADCASTDZrr >+ 1887487265U, // VPBROADCASTDrZkrr >+ 551814433U, // VPBROADCASTDrZrr >+ 551802457U, // VPBROADCASTDrm >+ 551818841U, // VPBROADCASTDrr >+ 551814735U, // VPBROADCASTMB2Qrr >+ 551813302U, // VPBROADCASTMW2Drr >+ 551838354U, // VPBROADCASTQYrm >+ 551821970U, // VPBROADCASTQYrr >+ 551651508U, // VPBROADCASTQZkrm >+ 1887488180U, // VPBROADCASTQZkrr >+ 551831732U, // VPBROADCASTQZrm >+ 551815348U, // VPBROADCASTQZrr >+ 1887488180U, // VPBROADCASTQrZkrr >+ 551815348U, // VPBROADCASTQrZrr >+ 551838354U, // VPBROADCASTQrm >+ 551821970U, // VPBROADCASTQrr >+ 388576U, // VPBROADCASTWYrm >+ 551824864U, // VPBROADCASTWYrr >+ 388576U, // VPBROADCASTWrm >+ 551824864U, // VPBROADCASTWrr >+ 340090732U, // VPCLMULQDQrm >+ 302358380U, // VPCLMULQDQrr >+ 340093384U, // VPCMOVmr >+ 92629448U, // VPCMOVmrY >+ 303180232U, // VPCMOVrm >+ 303196616U, // VPCMOVrmY >+ 302361032U, // VPCMOVrr >+ 302361032U, // VPCMOVrrY >+ 124402021U, // VPCMPDZrmi >+ 356865031U, // VPCMPDZrmi_alt >+ 126964743U, // VPCMPDZrmik_alt >+ 1466595685U, // VPCMPDZrri >+ 302355463U, // VPCMPDZrri_alt >+ 571069447U, // VPCMPDZrrik_alt >+ 812601162U, // VPCMPEQBYrm >+ 811650890U, // VPCMPEQBYrr >+ 811896650U, // VPCMPEQBZ128rm >+ 571608906U, // VPCMPEQBZ128rmk >+ 811650890U, // VPCMPEQBZ128rr >+ 570789706U, // VPCMPEQBZ128rrk >+ 812601162U, // VPCMPEQBZ256rm >+ 571625290U, // VPCMPEQBZ256rmk >+ 811650890U, // VPCMPEQBZ256rr >+ 570789706U, // VPCMPEQBZ256rrk >+ 812830538U, // VPCMPEQBZrm >+ 571641674U, // VPCMPEQBZrmk >+ 811650890U, // VPCMPEQBZrr >+ 570789706U, // VPCMPEQBZrrk >+ 811896650U, // VPCMPEQBrm >+ 811650890U, // VPCMPEQBrr >+ 812602536U, // VPCMPEQDYrm >+ 811652264U, // VPCMPEQDYrr >+ 811898024U, // VPCMPEQDZ128rm >+ 396448936U, // VPCMPEQDZ128rmb >+ 1471354024U, // VPCMPEQDZ128rmbk >+ 571610280U, // VPCMPEQDZ128rmk >+ 811652264U, // VPCMPEQDZ128rr >+ 570791080U, // VPCMPEQDZ128rrk >+ 812602536U, // VPCMPEQDZ256rm >+ 352408744U, // VPCMPEQDZ256rmb >+ 1427313832U, // VPCMPEQDZ256rmbk >+ 571626664U, // VPCMPEQDZ256rmk >+ 811652264U, // VPCMPEQDZ256rr >+ 570791080U, // VPCMPEQDZ256rrk >+ 812831912U, // VPCMPEQDZrm >+ 354505896U, // VPCMPEQDZrmb >+ 1429410984U, // VPCMPEQDZrmbk >+ 571643048U, // VPCMPEQDZrmk >+ 811652264U, // VPCMPEQDZrr >+ 570791080U, // VPCMPEQDZrrk >+ 811898024U, // VPCMPEQDrm >+ 811652264U, // VPCMPEQDrr >+ 812605759U, // VPCMPEQQYrm >+ 811655487U, // VPCMPEQQYrr >+ 811901247U, // VPCMPEQQZ128rm >+ 398565695U, // VPCMPEQQZ128rmb >+ 1473487167U, // VPCMPEQQZ128rmbk >+ 571613503U, // VPCMPEQQZ128rmk >+ 811655487U, // VPCMPEQQZ128rr >+ 570794303U, // VPCMPEQQZ128rrk >+ 812605759U, // VPCMPEQQZ256rm >+ 396468543U, // VPCMPEQQZ256rmb >+ 1471390015U, // VPCMPEQQZ256rmbk >+ 571629887U, // VPCMPEQQZ256rmk >+ 811655487U, // VPCMPEQQZ256rr >+ 570794303U, // VPCMPEQQZ256rrk >+ 812835135U, // VPCMPEQQZrm >+ 352428351U, // VPCMPEQQZrmb >+ 1427349823U, // VPCMPEQQZrmbk >+ 571646271U, // VPCMPEQQZrmk >+ 811655487U, // VPCMPEQQZrr >+ 570794303U, // VPCMPEQQZrrk >+ 811901247U, // VPCMPEQQrm >+ 811655487U, // VPCMPEQQrr >+ 812608581U, // VPCMPEQWYrm >+ 811658309U, // VPCMPEQWYrr >+ 811904069U, // VPCMPEQWZ128rm >+ 571616325U, // VPCMPEQWZ128rmk >+ 811658309U, // VPCMPEQWZ128rr >+ 570797125U, // VPCMPEQWZ128rrk >+ 812608581U, // VPCMPEQWZ256rm >+ 571632709U, // VPCMPEQWZ256rmk >+ 811658309U, // VPCMPEQWZ256rr >+ 570797125U, // VPCMPEQWZ256rrk >+ 812837957U, // VPCMPEQWZrm >+ 571649093U, // VPCMPEQWZrmk >+ 811658309U, // VPCMPEQWZrr >+ 570797125U, // VPCMPEQWZrrk >+ 811904069U, // VPCMPEQWrm >+ 811658309U, // VPCMPEQWrr >+ 0U, // VPCMPESTRIMEM >+ 0U, // VPCMPESTRIREG >+ 25499773U, // VPCMPESTRIrm >+ 811653245U, // VPCMPESTRIrr >+ 0U, // VPCMPESTRM128MEM >+ 0U, // VPCMPESTRM128REG >+ 25500962U, // VPCMPESTRM128rm >+ 811654434U, // VPCMPESTRM128rr >+ 812601343U, // VPCMPGTBYrm >+ 811651071U, // VPCMPGTBYrr >+ 811896831U, // VPCMPGTBZ128rm >+ 571609087U, // VPCMPGTBZ128rmk >+ 811651071U, // VPCMPGTBZ128rr >+ 570789887U, // VPCMPGTBZ128rrk >+ 812601343U, // VPCMPGTBZ256rm >+ 571625471U, // VPCMPGTBZ256rmk >+ 811651071U, // VPCMPGTBZ256rr >+ 570789887U, // VPCMPGTBZ256rrk >+ 812830719U, // VPCMPGTBZrm >+ 571641855U, // VPCMPGTBZrmk >+ 811651071U, // VPCMPGTBZrr >+ 570789887U, // VPCMPGTBZrrk >+ 811896831U, // VPCMPGTBrm >+ 811651071U, // VPCMPGTBrr >+ 812602951U, // VPCMPGTDYrm >+ 811652679U, // VPCMPGTDYrr >+ 811898439U, // VPCMPGTDZ128rm >+ 396449351U, // VPCMPGTDZ128rmb >+ 1471354439U, // VPCMPGTDZ128rmbk >+ 571610695U, // VPCMPGTDZ128rmk >+ 811652679U, // VPCMPGTDZ128rr >+ 570791495U, // VPCMPGTDZ128rrk >+ 812602951U, // VPCMPGTDZ256rm >+ 352409159U, // VPCMPGTDZ256rmb >+ 1427314247U, // VPCMPGTDZ256rmbk >+ 571627079U, // VPCMPGTDZ256rmk >+ 811652679U, // VPCMPGTDZ256rr >+ 570791495U, // VPCMPGTDZ256rrk >+ 812832327U, // VPCMPGTDZrm >+ 354506311U, // VPCMPGTDZrmb >+ 1429411399U, // VPCMPGTDZrmbk >+ 571643463U, // VPCMPGTDZrmk >+ 811652679U, // VPCMPGTDZrr >+ 570791495U, // VPCMPGTDZrrk >+ 811898439U, // VPCMPGTDrm >+ 811652679U, // VPCMPGTDrr >+ 812606021U, // VPCMPGTQYrm >+ 811655749U, // VPCMPGTQYrr >+ 811901509U, // VPCMPGTQZ128rm >+ 398565957U, // VPCMPGTQZ128rmb >+ 1473487429U, // VPCMPGTQZ128rmbk >+ 571613765U, // VPCMPGTQZ128rmk >+ 811655749U, // VPCMPGTQZ128rr >+ 570794565U, // VPCMPGTQZ128rrk >+ 812606021U, // VPCMPGTQZ256rm >+ 396468805U, // VPCMPGTQZ256rmb >+ 1471390277U, // VPCMPGTQZ256rmbk >+ 571630149U, // VPCMPGTQZ256rmk >+ 811655749U, // VPCMPGTQZ256rr >+ 570794565U, // VPCMPGTQZ256rrk >+ 812835397U, // VPCMPGTQZrm >+ 352428613U, // VPCMPGTQZrmb >+ 1427350085U, // VPCMPGTQZrmbk >+ 571646533U, // VPCMPGTQZrmk >+ 811655749U, // VPCMPGTQZrr >+ 570794565U, // VPCMPGTQZrrk >+ 811901509U, // VPCMPGTQrm >+ 811655749U, // VPCMPGTQrr >+ 812608943U, // VPCMPGTWYrm >+ 811658671U, // VPCMPGTWYrr >+ 811904431U, // VPCMPGTWZ128rm >+ 571616687U, // VPCMPGTWZ128rmk >+ 811658671U, // VPCMPGTWZ128rr >+ 570797487U, // VPCMPGTWZ128rrk >+ 812608943U, // VPCMPGTWZ256rm >+ 571633071U, // VPCMPGTWZ256rmk >+ 811658671U, // VPCMPGTWZ256rr >+ 570797487U, // VPCMPGTWZ256rrk >+ 812838319U, // VPCMPGTWZrm >+ 571649455U, // VPCMPGTWZrmk >+ 811658671U, // VPCMPGTWZrr >+ 570797487U, // VPCMPGTWZrrk >+ 811904431U, // VPCMPGTWrm >+ 811658671U, // VPCMPGTWrr >+ 0U, // VPCMPISTRIMEM >+ 0U, // VPCMPISTRIREG >+ 25499785U, // VPCMPISTRIrm >+ 811653257U, // VPCMPISTRIrr >+ 0U, // VPCMPISTRM128MEM >+ 0U, // VPCMPISTRM128REG >+ 25500974U, // VPCMPISTRM128rm >+ 811654446U, // VPCMPISTRM128rr >+ 132790629U, // VPCMPQZrmi >+ 356868384U, // VPCMPQZrmi_alt >+ 126968096U, // VPCMPQZrmik_alt >+ 1474984293U, // VPCMPQZrri >+ 302358816U, // VPCMPQZrri_alt >+ 571072800U, // VPCMPQZrrik_alt >+ 134887781U, // VPCMPUDZrmi >+ 356865657U, // VPCMPUDZrmi_alt >+ 126965369U, // VPCMPUDZrmik_alt >+ 1477081445U, // VPCMPUDZrri >+ 302356089U, // VPCMPUDZrri_alt >+ 571070073U, // VPCMPUDZrrik_alt >+ 136984933U, // VPCMPUQZrmi >+ 356868791U, // VPCMPUQZrmi_alt >+ 126968503U, // VPCMPUQZrmik_alt >+ 1479178597U, // VPCMPUQZrri >+ 302359223U, // VPCMPUQZrri_alt >+ 571073207U, // VPCMPUQZrrik_alt >+ 340086565U, // VPCOMBmi >+ 302354213U, // VPCOMBri >+ 340087225U, // VPCOMDmi >+ 302354873U, // VPCOMDri >+ 340091113U, // VPCOMQmi >+ 302358761U, // VPCOMQri >+ 340086828U, // VPCOMUBmi >+ 302354476U, // VPCOMUBri >+ 340088423U, // VPCOMUDmi >+ 302356071U, // VPCOMUDri >+ 340091566U, // VPCOMUQmi >+ 302359214U, // VPCOMUQri >+ 340094463U, // VPCOMUWmi >+ 302362111U, // VPCOMUWri >+ 340093940U, // VPCOMWmi >+ 302361588U, // VPCOMWri >+ 1033472U, // VPCONFLICTDrm >+ 623101184U, // VPCONFLICTDrmb >+ 624100608U, // VPCONFLICTDrmbk >+ 622937344U, // VPCONFLICTDrmbkz >+ 1888650496U, // VPCONFLICTDrmk >+ 1888666880U, // VPCONFLICTDrmkz >+ 551814400U, // VPCONFLICTDrr >+ 1887798528U, // VPCONFLICTDrrk >+ 1887487232U, // VPCONFLICTDrrkz >+ 1034387U, // VPCONFLICTQrm >+ 621037715U, // VPCONFLICTQrmb >+ 622037139U, // VPCONFLICTQrmbk >+ 620857491U, // VPCONFLICTQrmbkz >+ 1888651411U, // VPCONFLICTQrmk >+ 1888667795U, // VPCONFLICTQrmkz >+ 551815315U, // VPCONFLICTQrr >+ 1887799443U, // VPCONFLICTQrrk >+ 1887488147U, // VPCONFLICTQrrkz >+ 92622293U, // VPERM2F128rm >+ 302353877U, // VPERM2F128rr >+ 92622348U, // VPERM2I128rm >+ 302353932U, // VPERM2I128rr >+ 812601793U, // VPERMDYrm >+ 811651521U, // VPERMDYrr >+ 812826981U, // VPERMDZrm >+ 811647333U, // VPERMDZrr >+ 571637920U, // VPERMI2Drm >+ 122896544U, // VPERMI2Drmk >+ 139673760U, // VPERMI2Drmkz >+ 570785952U, // VPERMI2Drr >+ 1888075936U, // VPERMI2Drrk >+ 1888075936U, // VPERMI2Drrkz >+ 571638258U, // VPERMI2PDrm >+ 122896882U, // VPERMI2PDrmk >+ 139674098U, // VPERMI2PDrmkz >+ 570786290U, // VPERMI2PDrr >+ 1888076274U, // VPERMI2PDrrk >+ 1888076274U, // VPERMI2PDrrkz >+ 571640189U, // VPERMI2PSrm >+ 122898813U, // VPERMI2PSrmk >+ 139676029U, // VPERMI2PSrmkz >+ 570788221U, // VPERMI2PSrr >+ 1888078205U, // VPERMI2PSrrk >+ 1888078205U, // VPERMI2PSrrkz >+ 571639393U, // VPERMI2Qrm >+ 122898017U, // VPERMI2Qrmk >+ 139675233U, // VPERMI2Qrmkz >+ 570787425U, // VPERMI2Qrr >+ 1888077409U, // VPERMI2Qrrk >+ 1888077409U, // VPERMI2Qrrkz >+ 1215386262U, // VPERMIL2PDmr >+ 2289128086U, // VPERMIL2PDmrY >+ 143741590U, // VPERMIL2PDrm >+ 145838742U, // VPERMIL2PDrmY >+ 302633622U, // VPERMIL2PDrr >+ 302633622U, // VPERMIL2PDrrY >+ 1215390962U, // VPERMIL2PSmr >+ 2289132786U, // VPERMIL2PSmrY >+ 143746290U, // VPERMIL2PSrm >+ 145843442U, // VPERMIL2PSrmY >+ 302638322U, // VPERMIL2PSrr >+ 302638322U, // VPERMIL2PSrrY >+ 147133408U, // VPERMILPDYmi >+ 811652064U, // VPERMILPDYri >+ 812602336U, // VPERMILPDYrm >+ 811652064U, // VPERMILPDYrr >+ 149226306U, // VPERMILPDZmi >+ 811647810U, // VPERMILPDZri >+ 80024544U, // VPERMILPDmi >+ 811652064U, // VPERMILPDri >+ 811897824U, // VPERMILPDrm >+ 811652064U, // VPERMILPDrr >+ 147138109U, // VPERMILPSYmi >+ 811656765U, // VPERMILPSYri >+ 812607037U, // VPERMILPSYrm >+ 811656765U, // VPERMILPSYrr >+ 149228225U, // VPERMILPSZmi >+ 811649729U, // VPERMILPSZri >+ 80029245U, // VPERMILPSmi >+ 811656765U, // VPERMILPSri >+ 811902525U, // VPERMILPSrm >+ 811656765U, // VPERMILPSrr >+ 151327759U, // VPERMPDYmi >+ 811652111U, // VPERMPDYri >+ 153420643U, // VPERMPDZmi >+ 811647843U, // VPERMPDZri >+ 812532579U, // VPERMPDZrm >+ 811647843U, // VPERMPDZrr >+ 812607093U, // VPERMPSYrm >+ 811656821U, // VPERMPSYrr >+ 812534498U, // VPERMPSZrm >+ 811649762U, // VPERMPSZrr >+ 151331057U, // VPERMQYmi >+ 811655409U, // VPERMQYri >+ 149227494U, // VPERMQZmi >+ 811648998U, // VPERMQZri >+ 812828646U, // VPERMQZrm >+ 811648998U, // VPERMQZrr >+ 571637931U, // VPERMT2Drm >+ 122896555U, // VPERMT2Drmk >+ 139673771U, // VPERMT2Drmkz >+ 570785963U, // VPERMT2Drr >+ 1888075947U, // VPERMT2Drrk >+ 1888075947U, // VPERMT2Drrkz >+ 571638307U, // VPERMT2PDrm >+ 122896931U, // VPERMT2PDrmk >+ 139674147U, // VPERMT2PDrmkz >+ 570786339U, // VPERMT2PDrr >+ 1888076323U, // VPERMT2PDrrk >+ 1888076323U, // VPERMT2PDrrkz >+ 571640226U, // VPERMT2PSrm >+ 122898850U, // VPERMT2PSrmk >+ 139676066U, // VPERMT2PSrmkz >+ 570788258U, // VPERMT2PSrr >+ 1888078242U, // VPERMT2PSrrk >+ 1888078242U, // VPERMT2PSrrkz >+ 571639404U, // VPERMT2Qrm >+ 122898028U, // VPERMT2Qrmk >+ 139675244U, // VPERMT2Qrmkz >+ 570787436U, // VPERMT2Qrr >+ 1888077420U, // VPERMT2Qrrk >+ 1888077420U, // VPERMT2Qrrkz >+ 587534203U, // VPEXTRBmr >+ 811650939U, // VPEXTRBrr >+ 855971015U, // VPEXTRDmr >+ 811652295U, // VPEXTRDrr >+ 1124409773U, // VPEXTRQmr >+ 811655597U, // VPEXTRQrr >+ 1392848035U, // VPEXTRWmr >+ 811658403U, // VPEXTRWri >+ 811658403U, // VPEXTRWrr_REV >+ 110186810U, // VPGATHERDDYrm >+ 552714508U, // VPGATHERDDZrm >+ 110186810U, // VPGATHERDDrm >+ 108093304U, // VPGATHERDQYrm >+ 552699693U, // VPGATHERDQZrm >+ 108093304U, // VPGATHERDQrm >+ 110187698U, // VPGATHERQDYrm >+ 552698862U, // VPGATHERQDZrm >+ 110187698U, // VPGATHERQDrm >+ 108093769U, // VPGATHERQQYrm >+ 552699927U, // VPGATHERQQZrm >+ 108093769U, // VPGATHERQQrm >+ 315612U, // VPHADDBDrm >+ 551817436U, // VPHADDBDrr >+ 319040U, // VPHADDBQrm >+ 551820864U, // VPHADDBQrr >+ 322073U, // VPHADDBWrm >+ 551823897U, // VPHADDBWrr >+ 319228U, // VPHADDDQrm >+ 551821052U, // VPHADDDQrr >+ 812601631U, // VPHADDDYrm >+ 811651359U, // VPHADDDYrr >+ 811897119U, // VPHADDDrm >+ 811651359U, // VPHADDDrr >+ 811904227U, // VPHADDSWrm128 >+ 812608739U, // VPHADDSWrm256 >+ 811658467U, // VPHADDSWrr128 >+ 811658467U, // VPHADDSWrr256 >+ 315622U, // VPHADDUBDrm >+ 551817446U, // VPHADDUBDrr >+ 319058U, // VPHADDUBQrm >+ 551820882U, // VPHADDUBQrr >+ 322115U, // VPHADDUBWrm >+ 551823939U, // VPHADDUBWrr >+ 319406U, // VPHADDUDQrm >+ 551821230U, // VPHADDUDQrr >+ 317211U, // VPHADDUWDrm >+ 551819035U, // VPHADDUWDrr >+ 320261U, // VPHADDUWQrm >+ 551822085U, // VPHADDUWQrr >+ 317123U, // VPHADDWDrm >+ 551818947U, // VPHADDWDrr >+ 320236U, // VPHADDWQrm >+ 551822060U, // VPHADDWQrr >+ 812608172U, // VPHADDWYrm >+ 811657900U, // VPHADDWYrr >+ 811903660U, // VPHADDWrm >+ 811657900U, // VPHADDWrr >+ 323089U, // VPHMINPOSUWrm128 >+ 551824913U, // VPHMINPOSUWrr128 >+ 322044U, // VPHSUBBWrm >+ 551823868U, // VPHSUBBWrr >+ 319203U, // VPHSUBDQrm >+ 551821027U, // VPHSUBDQrr >+ 812601585U, // VPHSUBDYrm >+ 811651313U, // VPHSUBDYrr >+ 811897073U, // VPHSUBDrm >+ 811651313U, // VPHSUBDrr >+ 811904208U, // VPHSUBSWrm128 >+ 812608720U, // VPHSUBSWrm256 >+ 811658448U, // VPHSUBSWrr128 >+ 811658448U, // VPHSUBSWrr256 >+ 317113U, // VPHSUBWDrm >+ 551818937U, // VPHSUBWDrr >+ 812608078U, // VPHSUBWYrm >+ 811657806U, // VPHSUBWYrr >+ 811903566U, // VPHSUBWrm >+ 811657806U, // VPHSUBWrr >+ 344280946U, // VPINSRBrm >+ 302354290U, // VPINSRBrr >+ 346379454U, // VPINSRDrm >+ 302355646U, // VPINSRDrr >+ 325411216U, // VPINSRQrm >+ 302358928U, // VPINSRQrr >+ 327511176U, // VPINSRWrmi >+ 302361736U, // VPINSRWrri >+ 1033486U, // VPLZCNTDrm >+ 623101198U, // VPLZCNTDrmb >+ 624100622U, // VPLZCNTDrmbk >+ 622937358U, // VPLZCNTDrmbkz >+ 1888650510U, // VPLZCNTDrmk >+ 1888666894U, // VPLZCNTDrmkz >+ 551814414U, // VPLZCNTDrr >+ 1887798542U, // VPLZCNTDrrk >+ 1887487246U, // VPLZCNTDrrkz >+ 1034401U, // VPLZCNTQrm >+ 621037729U, // VPLZCNTQrmb >+ 622037153U, // VPLZCNTQrmbk >+ 620857505U, // VPLZCNTQrmbkz >+ 1888651425U, // VPLZCNTQrmk >+ 1888667809U, // VPLZCNTQrmkz >+ 551815329U, // VPLZCNTQrr >+ 1887799457U, // VPLZCNTQrrk >+ 1887488161U, // VPLZCNTQrrkz >+ 340087110U, // VPMACSDDrm >+ 302354758U, // VPMACSDDrr >+ 340088845U, // VPMACSDQHrm >+ 302356493U, // VPMACSDQHrr >+ 340089668U, // VPMACSDQLrm >+ 302357316U, // VPMACSDQLrr >+ 340087120U, // VPMACSSDDrm >+ 302354768U, // VPMACSSDDrr >+ 340088856U, // VPMACSSDQHrm >+ 302356504U, // VPMACSSDQHrr >+ 340089679U, // VPMACSSDQLrm >+ 302357327U, // VPMACSSDQLrr >+ 340088580U, // VPMACSSWDrm >+ 302356228U, // VPMACSSWDrr >+ 340094540U, // VPMACSSWWrm >+ 302362188U, // VPMACSSWWrr >+ 340088559U, // VPMACSWDrm >+ 302356207U, // VPMACSWDrr >+ 340094516U, // VPMACSWWrm >+ 302362164U, // VPMACSWWrr >+ 340088591U, // VPMADCSSWDrm >+ 302356239U, // VPMADCSSWDrr >+ 340088569U, // VPMADCSWDrm >+ 302356217U, // VPMADCSWDrr >+ 811904196U, // VPMADDUBSWrm128 >+ 812608708U, // VPMADDUBSWrm256 >+ 811658436U, // VPMADDUBSWrr128 >+ 811658436U, // VPMADDUBSWrr256 >+ 812603085U, // VPMADDWDYrm >+ 811652813U, // VPMADDWDYrr >+ 811898573U, // VPMADDWDrm >+ 811652813U, // VPMADDWDrr >+ 3808761510U, // VPMASKMOVDYmr >+ 812603046U, // VPMASKMOVDYrm >+ 3540326054U, // VPMASKMOVDmr >+ 811898534U, // VPMASKMOVDrm >+ 3808764633U, // VPMASKMOVQYmr >+ 812606169U, // VPMASKMOVQYrm >+ 3540329177U, // VPMASKMOVQmr >+ 811901657U, // VPMASKMOVQrm >+ 812601328U, // VPMAXSBYrm >+ 811651056U, // VPMAXSBYrr >+ 811896816U, // VPMAXSBrm >+ 811651056U, // VPMAXSBrr >+ 812602925U, // VPMAXSDYrm >+ 811652653U, // VPMAXSDYrr >+ 812827894U, // VPMAXSDZrm >+ 354501878U, // VPMAXSDZrmb >+ 4113679606U, // VPMAXSDZrmbk >+ 1429406966U, // VPMAXSDZrmbkz >+ 122897654U, // VPMAXSDZrmk >+ 571639030U, // VPMAXSDZrmkz >+ 811648246U, // VPMAXSDZrr >+ 1888077046U, // VPMAXSDZrrk >+ 570787062U, // VPMAXSDZrrkz >+ 811898413U, // VPMAXSDrm >+ 811652653U, // VPMAXSDrr >+ 812828809U, // VPMAXSQZrm >+ 352422025U, // VPMAXSQZrmb >+ 4111566985U, // VPMAXSQZrmbk >+ 1427343497U, // VPMAXSQZrmbkz >+ 122898569U, // VPMAXSQZrmk >+ 571639945U, // VPMAXSQZrmkz >+ 811649161U, // VPMAXSQZrr >+ 1888077961U, // VPMAXSQZrrk >+ 570787977U, // VPMAXSQZrrkz >+ 812608880U, // VPMAXSWYrm >+ 811658608U, // VPMAXSWYrr >+ 811904368U, // VPMAXSWrm >+ 811658608U, // VPMAXSWrr >+ 812601413U, // VPMAXUBYrm >+ 811651141U, // VPMAXUBYrr >+ 811896901U, // VPMAXUBrm >+ 811651141U, // VPMAXUBrr >+ 812603010U, // VPMAXUDYrm >+ 811652738U, // VPMAXUDYrr >+ 812827962U, // VPMAXUDZrm >+ 354501946U, // VPMAXUDZrmb >+ 4113679674U, // VPMAXUDZrmbk >+ 1429407034U, // VPMAXUDZrmbkz >+ 122897722U, // VPMAXUDZrmk >+ 571639098U, // VPMAXUDZrmkz >+ 811648314U, // VPMAXUDZrr >+ 1888077114U, // VPMAXUDZrrk >+ 570787130U, // VPMAXUDZrrkz >+ 811898498U, // VPMAXUDrm >+ 811652738U, // VPMAXUDrr >+ 812828877U, // VPMAXUQZrm >+ 352422093U, // VPMAXUQZrmb >+ 4111567053U, // VPMAXUQZrmbk >+ 1427343565U, // VPMAXUQZrmbkz >+ 122898637U, // VPMAXUQZrmk >+ 571640013U, // VPMAXUQZrmkz >+ 811649229U, // VPMAXUQZrr >+ 1888078029U, // VPMAXUQZrrk >+ 570788045U, // VPMAXUQZrrkz >+ 812609054U, // VPMAXUWYrm >+ 811658782U, // VPMAXUWYrr >+ 811904542U, // VPMAXUWrm >+ 811658782U, // VPMAXUWrr >+ 812601269U, // VPMINSBYrm >+ 811650997U, // VPMINSBYrr >+ 811896757U, // VPMINSBrm >+ 811650997U, // VPMINSBrr >+ 812602852U, // VPMINSDYrm >+ 811652580U, // VPMINSDYrr >+ 812827860U, // VPMINSDZrm >+ 354501844U, // VPMINSDZrmb >+ 4113679572U, // VPMINSDZrmbk >+ 1429406932U, // VPMINSDZrmbkz >+ 122897620U, // VPMINSDZrmk >+ 571638996U, // VPMINSDZrmkz >+ 811648212U, // VPMINSDZrr >+ 1888077012U, // VPMINSDZrrk >+ 570787028U, // VPMINSDZrrkz >+ 811898340U, // VPMINSDrm >+ 811652580U, // VPMINSDrr >+ 812828772U, // VPMINSQZrm >+ 352421988U, // VPMINSQZrmb >+ 4111566948U, // VPMINSQZrmbk >+ 1427343460U, // VPMINSQZrmbkz >+ 122898532U, // VPMINSQZrmk >+ 571639908U, // VPMINSQZrmkz >+ 811649124U, // VPMINSQZrr >+ 1888077924U, // VPMINSQZrrk >+ 570787940U, // VPMINSQZrrkz >+ 812608789U, // VPMINSWYrm >+ 811658517U, // VPMINSWYrr >+ 811904277U, // VPMINSWrm >+ 811658517U, // VPMINSWrr >+ 812601397U, // VPMINUBYrm >+ 811651125U, // VPMINUBYrr >+ 811896885U, // VPMINUBrm >+ 811651125U, // VPMINUBrr >+ 812602992U, // VPMINUDYrm >+ 811652720U, // VPMINUDYrr >+ 812827952U, // VPMINUDZrm >+ 354501936U, // VPMINUDZrmb >+ 4113679664U, // VPMINUDZrmbk >+ 1429407024U, // VPMINUDZrmbkz >+ 122897712U, // VPMINUDZrmk >+ 571639088U, // VPMINUDZrmkz >+ 811648304U, // VPMINUDZrr >+ 1888077104U, // VPMINUDZrrk >+ 570787120U, // VPMINUDZrrkz >+ 811898480U, // VPMINUDrm >+ 811652720U, // VPMINUDrr >+ 812828867U, // VPMINUQZrm >+ 352422083U, // VPMINUQZrmb >+ 4111567043U, // VPMINUQZrmbk >+ 1427343555U, // VPMINUQZrmbkz >+ 122898627U, // VPMINUQZrmk >+ 571640003U, // VPMINUQZrmkz >+ 811649219U, // VPMINUQZrr >+ 1888078019U, // VPMINUQZrrk >+ 570788035U, // VPMINUQZrrkz >+ 812609032U, // VPMINUWYrm >+ 811658760U, // VPMINUWYrr >+ 811904520U, // VPMINUWrm >+ 811658760U, // VPMINUWrr >+ 65044548U, // VPMOVDBmr >+ 1944387652U, // VPMOVDBmrk >+ 551813188U, // VPMOVDBrr >+ 1887486020U, // VPMOVDBrrk >+ 1887486020U, // VPMOVDBrrkz >+ 117476391U, // VPMOVDWmr >+ 1996819495U, // VPMOVDWmrk >+ 551816231U, // VPMOVDWrr >+ 1887489063U, // VPMOVDWrrk >+ 1887489063U, // VPMOVDWrrkz >+ 551816953U, // VPMOVMSKBYrr >+ 551816953U, // VPMOVMSKBrr >+ 65044590U, // VPMOVQBmr >+ 1944387694U, // VPMOVQBmrk >+ 551813230U, // VPMOVQBrr >+ 1887486062U, // VPMOVQBrrk >+ 1887486062U, // VPMOVQBrrkz >+ 117474336U, // VPMOVQDmr >+ 1996817440U, // VPMOVQDmrk >+ 551814176U, // VPMOVQDrr >+ 1887487008U, // VPMOVQDrrk >+ 1887487008U, // VPMOVQDrrkz >+ 65047644U, // VPMOVQWmr >+ 1944390748U, // VPMOVQWmrk >+ 551816284U, // VPMOVQWrr >+ 1887489116U, // VPMOVQWrrk >+ 1887489116U, // VPMOVQWrrkz >+ 65044537U, // VPMOVSDBmr >+ 1944387641U, // VPMOVSDBmrk >+ 551813177U, // VPMOVSDBrr >+ 1887486009U, // VPMOVSDBrrk >+ 1887486009U, // VPMOVSDBrrkz >+ 117476380U, // VPMOVSDWmr >+ 1996819484U, // VPMOVSDWmrk >+ 551816220U, // VPMOVSDWrr >+ 1887489052U, // VPMOVSDWrrk >+ 1887489052U, // VPMOVSDWrrkz >+ 65044579U, // VPMOVSQBmr >+ 1944387683U, // VPMOVSQBmrk >+ 551813219U, // VPMOVSQBrr >+ 1887486051U, // VPMOVSQBrrk >+ 1887486051U, // VPMOVSQBrrkz >+ 117474325U, // VPMOVSQDmr >+ 1996817429U, // VPMOVSQDmrk >+ 551814165U, // VPMOVSQDrr >+ 1887486997U, // VPMOVSQDrrk >+ 1887486997U, // VPMOVSQDrrkz >+ 65047633U, // VPMOVSQWmr >+ 1944390737U, // VPMOVSQWmrk >+ 551816273U, // VPMOVSQWrr >+ 1887489105U, // VPMOVSQWrrk >+ 1887489105U, // VPMOVSQWrrkz >+ 551801090U, // VPMOVSXBDYrm >+ 551817474U, // VPMOVSXBDYrr >+ 311514U, // VPMOVSXBDZrm >+ 1887731930U, // VPMOVSXBDZrmk >+ 1887731930U, // VPMOVSXBDZrmkz >+ 551813338U, // VPMOVSXBDZrr >+ 1887486170U, // VPMOVSXBDZrrk >+ 1887486170U, // VPMOVSXBDZrrkz >+ 551801090U, // VPMOVSXBDrm >+ 551817474U, // VPMOVSXBDrr >+ 384621U, // VPMOVSXBQYrm >+ 551820909U, // VPMOVSXBQYrr >+ 312969U, // VPMOVSXBQZrm >+ 1887733385U, // VPMOVSXBQZrmk >+ 1887733385U, // VPMOVSXBQZrmkz >+ 551814793U, // VPMOVSXBQZrr >+ 1887487625U, // VPMOVSXBQZrrk >+ 1887487625U, // VPMOVSXBQZrrkz >+ 384621U, // VPMOVSXBQrm >+ 551820909U, // VPMOVSXBQrr >+ 322151U, // VPMOVSXBWYrm >+ 551823975U, // VPMOVSXBWYrr >+ 551840359U, // VPMOVSXBWrm >+ 551823975U, // VPMOVSXBWrr >+ 319427U, // VPMOVSXDQYrm >+ 551821251U, // VPMOVSXDQYrr >+ 1017764U, // VPMOVSXDQZrm >+ 1888438180U, // VPMOVSXDQZrmk >+ 1888438180U, // VPMOVSXDQZrmkz >+ 551815076U, // VPMOVSXDQZrr >+ 1887487908U, // VPMOVSXDQZrrk >+ 1887487908U, // VPMOVSXDQZrrkz >+ 551837635U, // VPMOVSXDQrm >+ 551821251U, // VPMOVSXDQrr >+ 317222U, // VPMOVSXWDYrm >+ 551819046U, // VPMOVSXWDYrr >+ 1017194U, // VPMOVSXWDZrm >+ 1888437610U, // VPMOVSXWDZrmk >+ 1888437610U, // VPMOVSXWDZrmkz >+ 551814506U, // VPMOVSXWDZrr >+ 1887487338U, // VPMOVSXWDZrrk >+ 1887487338U, // VPMOVSXWDZrrkz >+ 551835430U, // VPMOVSXWDrm >+ 551819046U, // VPMOVSXWDrr >+ 551805712U, // VPMOVSXWQYrm >+ 551822096U, // VPMOVSXWQYrr >+ 313597U, // VPMOVSXWQZrm >+ 1887734013U, // VPMOVSXWQZrmk >+ 1887734013U, // VPMOVSXWQZrmkz >+ 551815421U, // VPMOVSXWQZrr >+ 1887488253U, // VPMOVSXWQZrrk >+ 1887488253U, // VPMOVSXWQZrrkz >+ 551805712U, // VPMOVSXWQrm >+ 551822096U, // VPMOVSXWQrr >+ 65044525U, // VPMOVUSDBmr >+ 1944387629U, // VPMOVUSDBmrk >+ 551813165U, // VPMOVUSDBrr >+ 1887485997U, // VPMOVUSDBrrk >+ 1887485997U, // VPMOVUSDBrrkz >+ 117476368U, // VPMOVUSDWmr >+ 1996819472U, // VPMOVUSDWmrk >+ 551816208U, // VPMOVUSDWrr >+ 1887489040U, // VPMOVUSDWrrk >+ 1887489040U, // VPMOVUSDWrrkz >+ 65044567U, // VPMOVUSQBmr >+ 1944387671U, // VPMOVUSQBmrk >+ 551813207U, // VPMOVUSQBrr >+ 1887486039U, // VPMOVUSQBrrk >+ 1887486039U, // VPMOVUSQBrrkz >+ 117474313U, // VPMOVUSQDmr >+ 1996817417U, // VPMOVUSQDmrk >+ 551814153U, // VPMOVUSQDrr >+ 1887486985U, // VPMOVUSQDrrk >+ 1887486985U, // VPMOVUSQDrrkz >+ 65047621U, // VPMOVUSQWmr >+ 1944390725U, // VPMOVUSQWmrk >+ 551816261U, // VPMOVUSQWrr >+ 1887489093U, // VPMOVUSQWrrk >+ 1887489093U, // VPMOVUSQWrrkz >+ 551801101U, // VPMOVZXBDYrm >+ 551817485U, // VPMOVZXBDYrr >+ 311526U, // VPMOVZXBDZrm >+ 1887731942U, // VPMOVZXBDZrmk >+ 1887731942U, // VPMOVZXBDZrmkz >+ 551813350U, // VPMOVZXBDZrr >+ 1887486182U, // VPMOVZXBDZrrk >+ 1887486182U, // VPMOVZXBDZrrkz >+ 551801101U, // VPMOVZXBDrm >+ 551817485U, // VPMOVZXBDrr >+ 384632U, // VPMOVZXBQYrm >+ 551820920U, // VPMOVZXBQYrr >+ 312981U, // VPMOVZXBQZrm >+ 1887733397U, // VPMOVZXBQZrmk >+ 1887733397U, // VPMOVZXBQZrmkz >+ 551814805U, // VPMOVZXBQZrr >+ 1887487637U, // VPMOVZXBQZrrk >+ 1887487637U, // VPMOVZXBQZrrkz >+ 384632U, // VPMOVZXBQrm >+ 551820920U, // VPMOVZXBQrr >+ 322162U, // VPMOVZXBWYrm >+ 551823986U, // VPMOVZXBWYrr >+ 551840370U, // VPMOVZXBWrm >+ 551823986U, // VPMOVZXBWrr >+ 319438U, // VPMOVZXDQYrm >+ 551821262U, // VPMOVZXDQYrr >+ 1017776U, // VPMOVZXDQZrm >+ 1888438192U, // VPMOVZXDQZrmk >+ 1888438192U, // VPMOVZXDQZrmkz >+ 551815088U, // VPMOVZXDQZrr >+ 1887487920U, // VPMOVZXDQZrrk >+ 1887487920U, // VPMOVZXDQZrrkz >+ 551837646U, // VPMOVZXDQrm >+ 551821262U, // VPMOVZXDQrr >+ 317233U, // VPMOVZXWDYrm >+ 551819057U, // VPMOVZXWDYrr >+ 1017206U, // VPMOVZXWDZrm >+ 1888437622U, // VPMOVZXWDZrmk >+ 1888437622U, // VPMOVZXWDZrmkz >+ 551814518U, // VPMOVZXWDZrr >+ 1887487350U, // VPMOVZXWDZrrk >+ 1887487350U, // VPMOVZXWDZrrkz >+ 551835441U, // VPMOVZXWDrm >+ 551819057U, // VPMOVZXWDrr >+ 551805723U, // VPMOVZXWQYrm >+ 551822107U, // VPMOVZXWQYrr >+ 313609U, // VPMOVZXWQZrm >+ 1887734025U, // VPMOVZXWQZrmk >+ 1887734025U, // VPMOVZXWQZrmkz >+ 551815433U, // VPMOVZXWQZrr >+ 1887488265U, // VPMOVZXWQZrrk >+ 1887488265U, // VPMOVZXWQZrrkz >+ 551805723U, // VPMOVZXWQrm >+ 551822107U, // VPMOVZXWQrr >+ 812605248U, // VPMULDQYrm >+ 811654976U, // VPMULDQYrr >+ 812828406U, // VPMULDQZrm >+ 352421622U, // VPMULDQZrmb >+ 1427343094U, // VPMULDQZrmbk >+ 1427343094U, // VPMULDQZrmbkz >+ 571639542U, // VPMULDQZrmk >+ 571639542U, // VPMULDQZrmkz >+ 811648758U, // VPMULDQZrr >+ 570787574U, // VPMULDQZrrk >+ 570787574U, // VPMULDQZrrkz >+ 811900736U, // VPMULDQrm >+ 811654976U, // VPMULDQrr >+ 811904302U, // VPMULHRSWrm128 >+ 812608814U, // VPMULHRSWrm256 >+ 811658542U, // VPMULHRSWrr128 >+ 811658542U, // VPMULHRSWrr256 >+ 812609013U, // VPMULHUWYrm >+ 811658741U, // VPMULHUWYrr >+ 811904501U, // VPMULHUWrm >+ 811658741U, // VPMULHUWrr >+ 812608387U, // VPMULHWYrm >+ 811658115U, // VPMULHWYrr >+ 811903875U, // VPMULHWrm >+ 811658115U, // VPMULHWrr >+ 812601759U, // VPMULLDYrm >+ 811651487U, // VPMULLDYrr >+ 812826938U, // VPMULLDZrm >+ 354500922U, // VPMULLDZrmb >+ 4113678650U, // VPMULLDZrmbk >+ 1429406010U, // VPMULLDZrmbkz >+ 122896698U, // VPMULLDZrmk >+ 571638074U, // VPMULLDZrmkz >+ 811647290U, // VPMULLDZrr >+ 1888076090U, // VPMULLDZrrk >+ 570786106U, // VPMULLDZrrkz >+ 811897247U, // VPMULLDrm >+ 811651487U, // VPMULLDrr >+ 812608456U, // VPMULLWYrm >+ 811658184U, // VPMULLWYrr >+ 811903944U, // VPMULLWrm >+ 811658184U, // VPMULLWrr >+ 812605369U, // VPMULUDQYrm >+ 811655097U, // VPMULUDQYrr >+ 812828569U, // VPMULUDQZrm >+ 352421785U, // VPMULUDQZrmb >+ 1427343257U, // VPMULUDQZrmbk >+ 1427343257U, // VPMULUDQZrmbkz >+ 571639705U, // VPMULUDQZrmk >+ 571639705U, // VPMULUDQZrmkz >+ 811648921U, // VPMULUDQZrr >+ 570787737U, // VPMULUDQZrrk >+ 570787737U, // VPMULUDQZrrkz >+ 811900857U, // VPMULUDQrm >+ 811655097U, // VPMULUDQrr >+ 812827706U, // VPORDZrm >+ 354501690U, // VPORDZrmb >+ 4113679418U, // VPORDZrmbk >+ 1429406778U, // VPORDZrmbkz >+ 122897466U, // VPORDZrmk >+ 571638842U, // VPORDZrmkz >+ 811648058U, // VPORDZrr >+ 1888076858U, // VPORDZrrk >+ 570786874U, // VPORDZrrkz >+ 812828738U, // VPORQZrm >+ 352421954U, // VPORQZrmb >+ 4111566914U, // VPORQZrmbk >+ 1427343426U, // VPORQZrmbkz >+ 122898498U, // VPORQZrmk >+ 571639874U, // VPORQZrmkz >+ 811649090U, // VPORQZrr >+ 1888077890U, // VPORQZrrk >+ 570787906U, // VPORQZrrkz >+ 812606337U, // VPORYrm >+ 811656065U, // VPORYrr >+ 811901825U, // VPORrm >+ 811656065U, // VPORrr >+ 340090138U, // VPPERMmr >+ 303176986U, // VPPERMrm >+ 302357786U, // VPPERMrr >+ 25497615U, // VPROTBmi >+ 25497615U, // VPROTBmr >+ 811651087U, // VPROTBri >+ 811896847U, // VPROTBrm >+ 811651087U, // VPROTBrr >+ 25499217U, // VPROTDmi >+ 25499217U, // VPROTDmr >+ 811652689U, // VPROTDri >+ 811898449U, // VPROTDrm >+ 811652689U, // VPROTDrr >+ 25502326U, // VPROTQmi >+ 25502326U, // VPROTQmr >+ 811655798U, // VPROTQri >+ 811901558U, // VPROTQrm >+ 811655798U, // VPROTQrr >+ 25505240U, // VPROTWmi >+ 25505240U, // VPROTWmr >+ 811658712U, // VPROTWri >+ 811904472U, // VPROTWrm >+ 811658712U, // VPROTWrr >+ 812608016U, // VPSADBWYrm >+ 811657744U, // VPSADBWYrr >+ 811903504U, // VPSADBWrm >+ 811657744U, // VPSADBWrr >+ 1906655513U, // VPSCATTERDDZmr >+ 1908754234U, // VPSCATTERDQZmr >+ 1908753403U, // VPSCATTERQDZmr >+ 1908754468U, // VPSCATTERQQZmr >+ 25497239U, // VPSHABmr >+ 811896471U, // VPSHABrm >+ 811650711U, // VPSHABrr >+ 25497804U, // VPSHADmr >+ 811897036U, // VPSHADrm >+ 811651276U, // VPSHADrr >+ 25501226U, // VPSHAQmr >+ 811900458U, // VPSHAQrm >+ 811654698U, // VPSHAQrr >+ 25504222U, // VPSHAWmr >+ 811903454U, // VPSHAWrm >+ 811657694U, // VPSHAWrr >+ 25497360U, // VPSHLBmr >+ 811896592U, // VPSHLBrm >+ 811650832U, // VPSHLBrr >+ 25497999U, // VPSHLDmr >+ 811897231U, // VPSHLDrm >+ 811651471U, // VPSHLDrr >+ 25501863U, // VPSHLQmr >+ 811901095U, // VPSHLQrm >+ 811655335U, // VPSHLQrr >+ 25504688U, // VPSHLWmr >+ 811903920U, // VPSHLWrm >+ 811658160U, // VPSHLWrr >+ 812601044U, // VPSHUFBYrm >+ 811650772U, // VPSHUFBYrr >+ 811896532U, // VPSHUFBrm >+ 811650772U, // VPSHUFBrr >+ 151327074U, // VPSHUFDYmi >+ 811651426U, // VPSHUFDYri >+ 149225767U, // VPSHUFDZmi >+ 811647271U, // VPSHUFDZri >+ 25497954U, // VPSHUFDmi >+ 811651426U, // VPSHUFDri >+ 151333753U, // VPSHUFHWYmi >+ 811658105U, // VPSHUFHWYri >+ 25504633U, // VPSHUFHWmi >+ 811658105U, // VPSHUFHWri >+ 151333798U, // VPSHUFLWYmi >+ 811658150U, // VPSHUFLWYri >+ 25504678U, // VPSHUFLWmi >+ 811658150U, // VPSHUFLWri >+ 812601133U, // VPSIGNBYrm >+ 811650861U, // VPSIGNBYrr >+ 811896621U, // VPSIGNBrm >+ 811650861U, // VPSIGNBrr >+ 812601808U, // VPSIGNDYrm >+ 811651536U, // VPSIGNDYrr >+ 811897296U, // VPSIGNDrm >+ 811651536U, // VPSIGNDrr >+ 812608508U, // VPSIGNWYrm >+ 811658236U, // VPSIGNWYrr >+ 811903996U, // VPSIGNWrm >+ 811658236U, // VPSIGNWrr >+ 811654958U, // VPSLLDQYri >+ 811654958U, // VPSLLDQri >+ 811651479U, // VPSLLDYri >+ 811897239U, // VPSLLDYrm >+ 811651479U, // VPSLLDYrr >+ 149225777U, // VPSLLDZmi >+ 625295665U, // VPSLLDZmik >+ 811647281U, // VPSLLDZri >+ 570786097U, // VPSLLDZrik >+ 811893041U, // VPSLLDZrm >+ 571605297U, // VPSLLDZrmk >+ 811647281U, // VPSLLDZrr >+ 570786097U, // VPSLLDZrrk >+ 811651479U, // VPSLLDri >+ 811897239U, // VPSLLDrm >+ 811651479U, // VPSLLDrr >+ 811655350U, // VPSLLQYri >+ 811901110U, // VPSLLQYrm >+ 811655350U, // VPSLLQYrr >+ 149227452U, // VPSLLQZmi >+ 625297340U, // VPSLLQZmik >+ 811648956U, // VPSLLQZri >+ 570787772U, // VPSLLQZrik >+ 811894716U, // VPSLLQZrm >+ 571606972U, // VPSLLQZrmk >+ 811648956U, // VPSLLQZrr >+ 570787772U, // VPSLLQZrrk >+ 811655350U, // VPSLLQri >+ 811901110U, // VPSLLQrm >+ 811655350U, // VPSLLQrr >+ 812603028U, // VPSLLVDYrm >+ 811652756U, // VPSLLVDYrr >+ 812827982U, // VPSLLVDZrm >+ 811648334U, // VPSLLVDZrr >+ 811898516U, // VPSLLVDrm >+ 811652756U, // VPSLLVDrr >+ 812606151U, // VPSLLVQYrm >+ 811655879U, // VPSLLVQYrr >+ 812828897U, // VPSLLVQZrm >+ 811649249U, // VPSLLVQZrr >+ 811901639U, // VPSLLVQrm >+ 811655879U, // VPSLLVQrr >+ 811658176U, // VPSLLWYri >+ 811903936U, // VPSLLWYrm >+ 811658176U, // VPSLLWYrr >+ 811658176U, // VPSLLWri >+ 811903936U, // VPSLLWrm >+ 811658176U, // VPSLLWrr >+ 811651284U, // VPSRADYri >+ 811897044U, // VPSRADYrm >+ 811651284U, // VPSRADYrr >+ 149225672U, // VPSRADZmi >+ 625295560U, // VPSRADZmik >+ 811647176U, // VPSRADZri >+ 570785992U, // VPSRADZrik >+ 811892936U, // VPSRADZrm >+ 571605192U, // VPSRADZrmk >+ 811647176U, // VPSRADZrr >+ 570785992U, // VPSRADZrrk >+ 811651284U, // VPSRADri >+ 811897044U, // VPSRADrm >+ 811651284U, // VPSRADrr >+ 149227127U, // VPSRAQZmi >+ 625297015U, // VPSRAQZmik >+ 811648631U, // VPSRAQZri >+ 570787447U, // VPSRAQZrik >+ 811894391U, // VPSRAQZrm >+ 571606647U, // VPSRAQZrmk >+ 811648631U, // VPSRAQZrr >+ 570787447U, // VPSRAQZrrk >+ 812603019U, // VPSRAVDYrm >+ 811652747U, // VPSRAVDYrr >+ 812827972U, // VPSRAVDZrm >+ 811648324U, // VPSRAVDZrr >+ 811898507U, // VPSRAVDrm >+ 811652747U, // VPSRAVDrr >+ 812828887U, // VPSRAVQZrm >+ 811649239U, // VPSRAVQZrr >+ 811657702U, // VPSRAWYri >+ 811903462U, // VPSRAWYrm >+ 811657702U, // VPSRAWYrr >+ 811657702U, // VPSRAWri >+ 811903462U, // VPSRAWrm >+ 811657702U, // VPSRAWrr >+ 811654967U, // VPSRLDQYri >+ 811654967U, // VPSRLDQri >+ 811651496U, // VPSRLDYri >+ 811897256U, // VPSRLDYrm >+ 811651496U, // VPSRLDYrr >+ 149225796U, // VPSRLDZmi >+ 625295684U, // VPSRLDZmik >+ 811647300U, // VPSRLDZri >+ 570786116U, // VPSRLDZrik >+ 811893060U, // VPSRLDZrm >+ 571605316U, // VPSRLDZrmk >+ 811647300U, // VPSRLDZrr >+ 570786116U, // VPSRLDZrrk >+ 811651496U, // VPSRLDri >+ 811897256U, // VPSRLDrm >+ 811651496U, // VPSRLDrr >+ 811655364U, // VPSRLQYri >+ 811901124U, // VPSRLQYrm >+ 811655364U, // VPSRLQYrr >+ 149227461U, // VPSRLQZmi >+ 625297349U, // VPSRLQZmik >+ 811648965U, // VPSRLQZri >+ 570787781U, // VPSRLQZrik >+ 811894725U, // VPSRLQZrm >+ 571606981U, // VPSRLQZrmk >+ 811648965U, // VPSRLQZrr >+ 570787781U, // VPSRLQZrrk >+ 811655364U, // VPSRLQri >+ 811901124U, // VPSRLQrm >+ 811655364U, // VPSRLQrr >+ 812603037U, // VPSRLVDYrm >+ 811652765U, // VPSRLVDYrr >+ 812827992U, // VPSRLVDZrm >+ 811648344U, // VPSRLVDZrr >+ 811898525U, // VPSRLVDrm >+ 811652765U, // VPSRLVDrr >+ 812606160U, // VPSRLVQYrm >+ 811655888U, // VPSRLVQYrr >+ 812828907U, // VPSRLVQZrm >+ 811649259U, // VPSRLVQZrr >+ 811901648U, // VPSRLVQrm >+ 811655888U, // VPSRLVQrr >+ 811658199U, // VPSRLWYri >+ 811903959U, // VPSRLWYrm >+ 811658199U, // VPSRLWYrr >+ 811658199U, // VPSRLWri >+ 811903959U, // VPSRLWrm >+ 811658199U, // VPSRLWrr >+ 812600997U, // VPSUBBYrm >+ 811650725U, // VPSUBBYrr >+ 811896485U, // VPSUBBrm >+ 811650725U, // VPSUBBrr >+ 812601594U, // VPSUBDYrm >+ 811651322U, // VPSUBDYrr >+ 812826833U, // VPSUBDZrm >+ 354500817U, // VPSUBDZrmb >+ 4113678545U, // VPSUBDZrmbk >+ 1429405905U, // VPSUBDZrmbkz >+ 122896593U, // VPSUBDZrmk >+ 571637969U, // VPSUBDZrmkz >+ 811647185U, // VPSUBDZrr >+ 1888075985U, // VPSUBDZrrk >+ 570786001U, // VPSUBDZrrkz >+ 811897082U, // VPSUBDrm >+ 811651322U, // VPSUBDrr >+ 812605021U, // VPSUBQYrm >+ 811654749U, // VPSUBQYrr >+ 812828288U, // VPSUBQZrm >+ 352421504U, // VPSUBQZrmb >+ 4111566464U, // VPSUBQZrmbk >+ 1427342976U, // VPSUBQZrmbkz >+ 122898048U, // VPSUBQZrmk >+ 571639424U, // VPSUBQZrmkz >+ 811648640U, // VPSUBQZrr >+ 1888077440U, // VPSUBQZrrk >+ 570787456U, // VPSUBQZrrkz >+ 811900509U, // VPSUBQrm >+ 811654749U, // VPSUBQrr >+ 812601244U, // VPSUBSBYrm >+ 811650972U, // VPSUBSBYrr >+ 811896732U, // VPSUBSBrm >+ 811650972U, // VPSUBSBrr >+ 812608730U, // VPSUBSWYrm >+ 811658458U, // VPSUBSWYrr >+ 811904218U, // VPSUBSWrm >+ 811658458U, // VPSUBSWrr >+ 812601292U, // VPSUBUSBYrm >+ 811651020U, // VPSUBUSBYrr >+ 811896780U, // VPSUBUSBrm >+ 811651020U, // VPSUBUSBrr >+ 812608852U, // VPSUBUSWYrm >+ 811658580U, // VPSUBUSWYrr >+ 811904340U, // VPSUBUSWrm >+ 811658580U, // VPSUBUSWrr >+ 812608087U, // VPSUBWYrm >+ 811657815U, // VPSUBWYrr >+ 811903575U, // VPSUBWrm >+ 811657815U, // VPSUBWrr >+ 812532078U, // VPTESTMDZrm >+ 811647342U, // VPTESTMDZrr >+ 812533743U, // VPTESTMQZrm >+ 811649007U, // VPTESTMQZrr >+ 812532057U, // VPTESTNMDZrm >+ 811647321U, // VPTESTNMDZrr >+ 812533722U, // VPTESTNMQZrm >+ 811648986U, // VPTESTNMQZrr >+ 1026394U, // VPTESTYrm >+ 551823706U, // VPTESTYrr >+ 584026U, // VPTESTrm >+ 551823706U, // VPTESTrr >+ 812608035U, // VPUNPCKHBWYrm >+ 811657763U, // VPUNPCKHBWYrr >+ 811903523U, // VPUNPCKHBWrm >+ 811657763U, // VPUNPCKHBWrr >+ 812605199U, // VPUNPCKHDQYrm >+ 811654927U, // VPUNPCKHDQYrr >+ 812828380U, // VPUNPCKHDQZrm >+ 811648732U, // VPUNPCKHDQZrr >+ 811900687U, // VPUNPCKHDQrm >+ 811654927U, // VPUNPCKHDQrr >+ 812605266U, // VPUNPCKHQDQYrm >+ 811654994U, // VPUNPCKHQDQYrr >+ 812828433U, // VPUNPCKHQDQZrm >+ 811648785U, // VPUNPCKHQDQZrr >+ 811900754U, // VPUNPCKHQDQrm >+ 811654994U, // VPUNPCKHQDQrr >+ 812603095U, // VPUNPCKHWDYrm >+ 811652823U, // VPUNPCKHWDYrr >+ 811898583U, // VPUNPCKHWDrm >+ 811652823U, // VPUNPCKHWDrr >+ 812608047U, // VPUNPCKLBWYrm >+ 811657775U, // VPUNPCKLBWYrr >+ 811903535U, // VPUNPCKLBWrm >+ 811657775U, // VPUNPCKLBWrr >+ 812605218U, // VPUNPCKLDQYrm >+ 811654946U, // VPUNPCKLDQYrr >+ 812828393U, // VPUNPCKLDQZrm >+ 811648745U, // VPUNPCKLDQZrr >+ 811900706U, // VPUNPCKLDQrm >+ 811654946U, // VPUNPCKLDQrr >+ 812605279U, // VPUNPCKLQDQYrm >+ 811655007U, // VPUNPCKLQDQYrr >+ 812828447U, // VPUNPCKLQDQZrm >+ 811648799U, // VPUNPCKLQDQZrr >+ 811900767U, // VPUNPCKLQDQrm >+ 811655007U, // VPUNPCKLQDQrr >+ 812603107U, // VPUNPCKLWDYrm >+ 811652835U, // VPUNPCKLWDYrr >+ 811898595U, // VPUNPCKLWDrm >+ 811652835U, // VPUNPCKLWDrr >+ 812827722U, // VPXORDZrm >+ 354501706U, // VPXORDZrmb >+ 4113679434U, // VPXORDZrmbk >+ 1429406794U, // VPXORDZrmbkz >+ 122897482U, // VPXORDZrmk >+ 571638858U, // VPXORDZrmkz >+ 811648074U, // VPXORDZrr >+ 1888076874U, // VPXORDZrrk >+ 570786890U, // VPXORDZrrkz >+ 812828754U, // VPXORQZrm >+ 352421970U, // VPXORQZrmb >+ 4111566930U, // VPXORQZrmbk >+ 1427343442U, // VPXORQZrmbkz >+ 122898514U, // VPXORQZrmk >+ 571639890U, // VPXORQZrmkz >+ 811649106U, // VPXORQZrr >+ 1888077906U, // VPXORQZrrk >+ 570787922U, // VPXORQZrrkz >+ 812606360U, // VPXORYrm >+ 811656088U, // VPXORYrr >+ 811901848U, // VPXORrm >+ 811656088U, // VPXORrr >+ 1081995U, // VRCP14PDZm >+ 551813771U, // VRCP14PDZr >+ 1083914U, // VRCP14PSZm >+ 551815690U, // VRCP14PSZr >+ 283264141U, // VRCP14SDrm >+ 811648141U, // VRCP14SDrr >+ 283282343U, // VRCP14SSrm >+ 811649959U, // VRCP14SSrr >+ 1082019U, // VRCP28PDZm >+ 551813795U, // VRCP28PDZr >+ 551826154U, // VRCP28PDZrb >+ 1083938U, // VRCP28PSZm >+ 551815714U, // VRCP28PSZr >+ 551826230U, // VRCP28PSZrb >+ 283264165U, // VRCP28SDrm >+ 811648165U, // VRCP28SDrr >+ 811660048U, // VRCP28SDrrb >+ 283282367U, // VRCP28SSrm >+ 811649983U, // VRCP28SSrr >+ 811660124U, // VRCP28SSrrb >+ 1074831U, // VRCPPSYm >+ 1074831U, // VRCPPSYm_Int >+ 551822991U, // VRCPPSYr >+ 551822991U, // VRCPPSYr_Int >+ 583311U, // VRCPPSm >+ 583311U, // VRCPPSm_Int >+ 551822991U, // VRCPPSr >+ 551822991U, // VRCPPSr_Int >+ 283289733U, // VRCPSSm >+ 283289733U, // VRCPSSm_Int >+ 811657349U, // VRCPSSr >+ 153420586U, // VRNDSCALEPDZm >+ 811647786U, // VRNDSCALEPDZr >+ 153422505U, // VRNDSCALEPSZm >+ 811649705U, // VRNDSCALEPSZr >+ 283264198U, // VRNDSCALESDm >+ 811648198U, // VRNDSCALESDr >+ 283282391U, // VRNDSCALESSm >+ 811650007U, // VRNDSCALESSr >+ 80024482U, // VROUNDPDm >+ 811652002U, // VROUNDPDr >+ 80029163U, // VROUNDPSm >+ 811656683U, // VROUNDPSr >+ 312825279U, // VROUNDSDm >+ 302355903U, // VROUNDSDr >+ 302355903U, // VROUNDSDr_Int >+ 317024344U, // VROUNDSSm >+ 302360664U, // VROUNDSSr >+ 302360664U, // VROUNDSSr_Int >+ 147133346U, // VROUNDYPDm >+ 811652002U, // VROUNDYPDr >+ 147138027U, // VROUNDYPSm >+ 811656683U, // VROUNDYPSr >+ 1082006U, // VRSQRT14PDZm >+ 551813782U, // VRSQRT14PDZr >+ 1083925U, // VRSQRT14PSZm >+ 551815701U, // VRSQRT14PSZr >+ 283264152U, // VRSQRT14SDrm >+ 811648152U, // VRSQRT14SDrr >+ 283282354U, // VRSQRT14SSrm >+ 811649970U, // VRSQRT14SSrr >+ 1082030U, // VRSQRT28PDZm >+ 551813806U, // VRSQRT28PDZr >+ 551826172U, // VRSQRT28PDZrb >+ 1083949U, // VRSQRT28PSZm >+ 551815725U, // VRSQRT28PSZr >+ 551826248U, // VRSQRT28PSZrb >+ 283264176U, // VRSQRT28SDrm >+ 811648176U, // VRSQRT28SDrr >+ 811660066U, // VRSQRT28SDrrb >+ 283282378U, // VRSQRT28SSrm >+ 811649994U, // VRSQRT28SSrr >+ 811660142U, // VRSQRT28SSrrb >+ 1074914U, // VRSQRTPSYm >+ 1074914U, // VRSQRTPSYm_Int >+ 551823074U, // VRSQRTPSYr >+ 551823074U, // VRSQRTPSYr_Int >+ 583394U, // VRSQRTPSm >+ 583394U, // VRSQRTPSm_Int >+ 551823074U, // VRSQRTPSr >+ 551823074U, // VRSQRTPSr_Int >+ 283289758U, // VRSQRTSSm >+ 283289758U, // VRSQRTSSm_Int >+ 811657374U, // VRSQRTSSr >+ 1908753180U, // VSCATTERDPDZmr >+ 1906657947U, // VSCATTERDPSZmr >+ 111395540U, // VSCATTERPF0DPDm >+ 111397459U, // VSCATTERPF0DPSm >+ 111428495U, // VSCATTERPF0QPDm >+ 111430414U, // VSCATTERPF0QPSm >+ 111395573U, // VSCATTERPF1DPDm >+ 111397492U, // VSCATTERPF1DPSm >+ 111428528U, // VSCATTERPF1QPDm >+ 111430447U, // VSCATTERPF1QPSm >+ 1908753358U, // VSCATTERQPDZmr >+ 1908755277U, // VSCATTERQPSZmr >+ 92623800U, // VSHUFPDYrmi >+ 302355384U, // VSHUFPDYrri >+ 96813880U, // VSHUFPDZrmi >+ 302351160U, // VSHUFPDZrri >+ 300241848U, // VSHUFPDrmi >+ 302355384U, // VSHUFPDrri >+ 92628481U, // VSHUFPSYrmi >+ 302360065U, // VSHUFPSYrri >+ 96815799U, // VSHUFPSZrmi >+ 302353079U, // VSHUFPSZrri >+ 300246529U, // VSHUFPSrmi >+ 302360065U, // VSHUFPSrri >+ 1070173U, // VSQRTPDYm >+ 551818333U, // VSQRTPDYr >+ 1086557U, // VSQRTPDZrm >+ 551818333U, // VSQRTPDZrr >+ 578653U, // VSQRTPDm >+ 551818333U, // VSQRTPDr >+ 1074924U, // VSQRTPSYm >+ 551823084U, // VSQRTPSYr >+ 1091308U, // VSQRTPSZrm >+ 551823084U, // VSQRTPSZrr >+ 583404U, // VSQRTPSm >+ 551823084U, // VSQRTPSr >+ 283268614U, // VSQRTSDZm >+ 283268614U, // VSQRTSDZm_Int >+ 811652614U, // VSQRTSDZr >+ 811652614U, // VSQRTSDZr_Int >+ 283268614U, // VSQRTSDm >+ 283268614U, // VSQRTSDm_Int >+ 811652614U, // VSQRTSDr >+ 283289768U, // VSQRTSSZm >+ 283289768U, // VSQRTSSZm_Int >+ 811657384U, // VSQRTSSZr >+ 811657384U, // VSQRTSSZr_Int >+ 283289768U, // VSQRTSSm >+ 283289768U, // VSQRTSSm_Int >+ 811657384U, // VSQRTSSr >+ 238511U, // VSTMXCSR >+ 812520277U, // VSUBPDYrm >+ 811651925U, // VSUBPDYrr >+ 812532411U, // VSUBPDZrm >+ 352469691U, // VSUBPDZrmb >+ 1427014331U, // VSUBPDZrmbk >+ 1427014331U, // VSUBPDZrmbkz >+ 571396949U, // VSUBPDZrmk >+ 571396949U, // VSUBPDZrmkz >+ 811647675U, // VSUBPDZrr >+ 570786491U, // VSUBPDZrrk >+ 570786491U, // VSUBPDZrrkz >+ 811733845U, // VSUBPDrm >+ 811651925U, // VSUBPDrr >+ 812524958U, // VSUBPSYrm >+ 811656606U, // VSUBPSYrr >+ 812534330U, // VSUBPSZrm >+ 354585146U, // VSUBPSZrmb >+ 1429146170U, // VSUBPSZrmbk >+ 1429146170U, // VSUBPSZrmbkz >+ 571401630U, // VSUBPSZrmk >+ 571401630U, // VSUBPSZrmkz >+ 811649594U, // VSUBPSZrr >+ 570788410U, // VSUBPSZrrk >+ 570788410U, // VSUBPSZrrkz >+ 811738526U, // VSUBPSrm >+ 811656606U, // VSUBPSrr >+ 283268506U, // VSUBSDZrm >+ 811652506U, // VSUBSDZrr >+ 283268506U, // VSUBSDrm >+ 283268506U, // VSUBSDrm_Int >+ 811652506U, // VSUBSDrr >+ 811652506U, // VSUBSDrr_Int >+ 283289651U, // VSUBSSZrm >+ 811657267U, // VSUBSSZrr >+ 283289651U, // VSUBSSrm >+ 283289651U, // VSUBSSrm_Int >+ 811657267U, // VSUBSSrr >+ 811657267U, // VSUBSSrr_Int >+ 1070182U, // VTESTPDYrm >+ 551818342U, // VTESTPDYrr >+ 578662U, // VTESTPDrm >+ 551818342U, // VTESTPDrr >+ 1074933U, // VTESTPSYrm >+ 551823093U, // VTESTPSYrr >+ 583413U, // VTESTPSrm >+ 551823093U, // VTESTPSrr >+ 595401U, // VUCOMISDZrm >+ 551818697U, // VUCOMISDZrr >+ 595401U, // VUCOMISDrm >+ 551818697U, // VUCOMISDrr >+ 616546U, // VUCOMISSZrm >+ 551823458U, // VUCOMISSZrr >+ 616546U, // VUCOMISSrm >+ 551823458U, // VUCOMISSrr >+ 812520385U, // VUNPCKHPDYrm >+ 811652033U, // VUNPCKHPDYrr >+ 812536769U, // VUNPCKHPDZrm >+ 811652033U, // VUNPCKHPDZrr >+ 811733953U, // VUNPCKHPDrm >+ 811652033U, // VUNPCKHPDrr >+ 812525066U, // VUNPCKHPSYrm >+ 811656714U, // VUNPCKHPSYrr >+ 812541450U, // VUNPCKHPSZrm >+ 811656714U, // VUNPCKHPSZrr >+ 811738634U, // VUNPCKHPSrm >+ 811656714U, // VUNPCKHPSrr >+ 812520427U, // VUNPCKLPDYrm >+ 811652075U, // VUNPCKLPDYrr >+ 812536811U, // VUNPCKLPDZrm >+ 811652075U, // VUNPCKLPDZrr >+ 811733995U, // VUNPCKLPDrm >+ 811652075U, // VUNPCKLPDrr >+ 812525128U, // VUNPCKLPSYrm >+ 811656776U, // VUNPCKLPSYrr >+ 812541512U, // VUNPCKLPSZrm >+ 811656776U, // VUNPCKLPSZrr >+ 811738696U, // VUNPCKLPSrm >+ 811656776U, // VUNPCKLPSrr >+ 812520523U, // VXORPDYrm >+ 811652171U, // VXORPDYrr >+ 811734091U, // VXORPDrm >+ 811652171U, // VXORPDrr >+ 812525241U, // VXORPSYrm >+ 811656889U, // VXORPSYrr >+ 811738809U, // VXORPSrm >+ 811656889U, // VXORPSrr >+ 14534U, // VZEROALL >+ 14807U, // VZEROUPPER >+ 0U, // V_SET0 >+ 0U, // V_SETALLONES >+ 417967U, // W64ALLOCA >+ 15221U, // WAIT >+ 14277U, // WBINVD >+ 14645U, // WIN_ALLOCA >+ 14452U, // WIN_FTOL_32 >+ 14452U, // WIN_FTOL_64 >+ 22986U, // WRFSBASE >+ 24602U, // WRFSBASE64 >+ 23008U, // WRGSBASE >+ 24624U, // WRGSBASE64 >+ 14841U, // WRMSR >+ 26927U, // XABORT >+ 14334U, // XACQUIRE_PREFIX >+ 4238013U, // XADD16rm >+ 551824061U, // XADD16rr >+ 12622149U, // XADD32rm >+ 551819589U, // XADD32rr >+ 18915061U, // XADD64rm >+ 551821045U, // XADD64rr >+ 23105223U, // XADD8rm >+ 551816903U, // XADD8rr >+ 14046U, // XBEGIN >+ 417090U, // XBEGIN_4 >+ 2124631U, // XCHG16ar >+ 3504614231U, // XCHG16rm >+ 1357130583U, // XCHG16rr >+ 10508812U, // XCHG32ar >+ 10508812U, // XCHG32ar64 >+ 3773045260U, // XCHG32rm >+ 1357126156U, // XCHG32rr >+ 16801893U, // XCHG64ar >+ 4041482341U, // XCHG64rm >+ 1357127781U, // XCHG64rr >+ 14946022U, // XCHG8rm >+ 1357123302U, // XCHG8rr >+ 22524U, // XCH_F >+ 14195U, // XCRYPTCBC >+ 14139U, // XCRYPTCFB >+ 14847U, // XCRYPTCTR >+ 14129U, // XCRYPTECB >+ 14149U, // XCRYPTOFB >+ 14258U, // XEND >+ 15268U, // XGETBV >+ 14179U, // XLAT >+ 2124924U, // XOR16i16 >+ 4238460U, // XOR16mi >+ 4238460U, // XOR16mi8 >+ 4238460U, // XOR16mr >+ 6351996U, // XOR16ri >+ 6351996U, // XOR16ri8 >+ 6368380U, // XOR16rm >+ 6351996U, // XOR16rr >+ 8449148U, // XOR16rr_REV >+ 10509194U, // XOR32i32 >+ 12622730U, // XOR32mi >+ 12622730U, // XOR32mi8 >+ 12622730U, // XOR32mr >+ 6347658U, // XOR32ri >+ 6347658U, // XOR32ri8 >+ 283204490U, // XOR32rm >+ 6347658U, // XOR32rr >+ 8444810U, // XOR32rr_REV >+ 16802173U, // XOR64i32 >+ 18915709U, // XOR64mi32 >+ 18915709U, // XOR64mi8 >+ 18915709U, // XOR64mr >+ 6349181U, // XOR64ri32 >+ 6349181U, // XOR64ri8 >+ 283222397U, // XOR64rm >+ 6349181U, // XOR64rr >+ 8446333U, // XOR64rr_REV >+ 20991852U, // XOR8i8 >+ 23105388U, // XOR8mi >+ 23105388U, // XOR8mr >+ 6344556U, // XOR8ri >+ 6344556U, // XOR8ri8 >+ 118636U, // XOR8rm >+ 6344556U, // XOR8rr >+ 8441708U, // XOR8rr_REV >+ 8524876U, // XORPDrm >+ 8442956U, // XORPDrr >+ 8529594U, // XORPSrm >+ 8447674U, // XORPSrr >+ 14350U, // XRELEASE_PREFIX >+ 631696U, // XRSTOR >+ 631156U, // XRSTOR64 >+ 628689U, // XSAVE >+ 630854U, // XSAVE64 >+ 633118U, // XSAVEOPT >+ 631422U, // XSAVEOPT64 >+ 15275U, // XSETBV >+ 13773U, // XSHA1 >+ 14008U, // XSHA256 >+ 14343U, // XSTORE >+ 15251U, // XTEST >+ 0U >+ }; >+ >+ static const uint16_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // AAA >+ 0U, // AAD8i8 >+ 0U, // AAM8i8 >+ 0U, // AAS >+ 0U, // ABS_F >+ 0U, // ABS_Fp32 >+ 0U, // ABS_Fp64 >+ 0U, // ABS_Fp80 >+ 0U, // ACQUIRE_MOV16rm >+ 0U, // ACQUIRE_MOV32rm >+ 0U, // ACQUIRE_MOV64rm >+ 0U, // ACQUIRE_MOV8rm >+ 0U, // ADC16i16 >+ 0U, // ADC16mi >+ 0U, // ADC16mi8 >+ 0U, // ADC16mr >+ 0U, // ADC16ri >+ 0U, // ADC16ri8 >+ 0U, // ADC16rm >+ 0U, // ADC16rr >+ 0U, // ADC16rr_REV >+ 0U, // ADC32i32 >+ 0U, // ADC32mi >+ 0U, // ADC32mi8 >+ 0U, // ADC32mr >+ 0U, // ADC32ri >+ 0U, // ADC32ri8 >+ 0U, // ADC32rm >+ 0U, // ADC32rr >+ 0U, // ADC32rr_REV >+ 0U, // ADC64i32 >+ 0U, // ADC64mi32 >+ 0U, // ADC64mi8 >+ 0U, // ADC64mr >+ 0U, // ADC64ri32 >+ 0U, // ADC64ri8 >+ 0U, // ADC64rm >+ 0U, // ADC64rr >+ 0U, // ADC64rr_REV >+ 0U, // ADC8i8 >+ 0U, // ADC8mi >+ 0U, // ADC8mr >+ 0U, // ADC8ri >+ 0U, // ADC8rm >+ 0U, // ADC8rr >+ 0U, // ADC8rr_REV >+ 0U, // ADCX32rm >+ 0U, // ADCX32rr >+ 0U, // ADCX64rm >+ 0U, // ADCX64rr >+ 0U, // ADD16i16 >+ 0U, // ADD16mi >+ 0U, // ADD16mi8 >+ 0U, // ADD16mr >+ 0U, // ADD16ri >+ 0U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 0U, // ADD16rm >+ 0U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 0U, // ADD16rr_REV >+ 0U, // ADD32i32 >+ 0U, // ADD32mi >+ 0U, // ADD32mi8 >+ 0U, // ADD32mr >+ 0U, // ADD32ri >+ 0U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 0U, // ADD32rm >+ 0U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 0U, // ADD32rr_REV >+ 0U, // ADD64i32 >+ 0U, // ADD64mi32 >+ 0U, // ADD64mi8 >+ 0U, // ADD64mr >+ 0U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 0U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 0U, // ADD64rm >+ 0U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 0U, // ADD64rr_REV >+ 0U, // ADD8i8 >+ 0U, // ADD8mi >+ 0U, // ADD8mr >+ 0U, // ADD8ri >+ 0U, // ADD8ri8 >+ 0U, // ADD8rm >+ 0U, // ADD8rr >+ 0U, // ADD8rr_REV >+ 0U, // ADDPDrm >+ 0U, // ADDPDrr >+ 0U, // ADDPSrm >+ 0U, // ADDPSrr >+ 0U, // ADDSDrm >+ 0U, // ADDSDrm_Int >+ 0U, // ADDSDrr >+ 0U, // ADDSDrr_Int >+ 0U, // ADDSSrm >+ 0U, // ADDSSrm_Int >+ 0U, // ADDSSrr >+ 0U, // ADDSSrr_Int >+ 0U, // ADDSUBPDrm >+ 0U, // ADDSUBPDrr >+ 0U, // ADDSUBPSrm >+ 0U, // ADDSUBPSrr >+ 0U, // ADD_F32m >+ 0U, // ADD_F64m >+ 0U, // ADD_FI16m >+ 0U, // ADD_FI32m >+ 0U, // ADD_FPrST0 >+ 0U, // ADD_FST0r >+ 0U, // ADD_Fp32 >+ 0U, // ADD_Fp32m >+ 0U, // ADD_Fp64 >+ 0U, // ADD_Fp64m >+ 0U, // ADD_Fp64m32 >+ 0U, // ADD_Fp80 >+ 0U, // ADD_Fp80m32 >+ 0U, // ADD_Fp80m64 >+ 0U, // ADD_FpI16m32 >+ 0U, // ADD_FpI16m64 >+ 0U, // ADD_FpI16m80 >+ 0U, // ADD_FpI32m32 >+ 0U, // ADD_FpI32m64 >+ 0U, // ADD_FpI32m80 >+ 0U, // ADD_FrST0 >+ 0U, // ADJCALLSTACKDOWN32 >+ 0U, // ADJCALLSTACKDOWN64 >+ 0U, // ADJCALLSTACKUP32 >+ 0U, // ADJCALLSTACKUP64 >+ 0U, // ADOX32rm >+ 0U, // ADOX32rr >+ 0U, // ADOX64rm >+ 0U, // ADOX64rr >+ 0U, // AESDECLASTrm >+ 0U, // AESDECLASTrr >+ 0U, // AESDECrm >+ 0U, // AESDECrr >+ 0U, // AESENCLASTrm >+ 0U, // AESENCLASTrr >+ 0U, // AESENCrm >+ 0U, // AESENCrr >+ 0U, // AESIMCrm >+ 0U, // AESIMCrr >+ 0U, // AESKEYGENASSIST128rm >+ 0U, // AESKEYGENASSIST128rr >+ 0U, // AND16i16 >+ 0U, // AND16mi >+ 0U, // AND16mi8 >+ 0U, // AND16mr >+ 0U, // AND16ri >+ 0U, // AND16ri8 >+ 0U, // AND16rm >+ 0U, // AND16rr >+ 0U, // AND16rr_REV >+ 0U, // AND32i32 >+ 0U, // AND32mi >+ 0U, // AND32mi8 >+ 0U, // AND32mr >+ 0U, // AND32ri >+ 0U, // AND32ri8 >+ 0U, // AND32rm >+ 0U, // AND32rr >+ 0U, // AND32rr_REV >+ 0U, // AND64i32 >+ 0U, // AND64mi32 >+ 0U, // AND64mi8 >+ 0U, // AND64mr >+ 0U, // AND64ri32 >+ 0U, // AND64ri8 >+ 0U, // AND64rm >+ 0U, // AND64rr >+ 0U, // AND64rr_REV >+ 0U, // AND8i8 >+ 0U, // AND8mi >+ 0U, // AND8mr >+ 0U, // AND8ri >+ 0U, // AND8ri8 >+ 0U, // AND8rm >+ 0U, // AND8rr >+ 0U, // AND8rr_REV >+ 4U, // ANDN32rm >+ 0U, // ANDN32rr >+ 4U, // ANDN64rm >+ 0U, // ANDN64rr >+ 0U, // ANDNPDrm >+ 0U, // ANDNPDrr >+ 0U, // ANDNPSrm >+ 0U, // ANDNPSrr >+ 0U, // ANDPDrm >+ 0U, // ANDPDrr >+ 0U, // ANDPSrm >+ 0U, // ANDPSrr >+ 0U, // ARPL16mr >+ 0U, // ARPL16rr >+ 0U, // AVX2_SETALLONES >+ 0U, // AVX512_512_SET0 >+ 0U, // AVX_SET0 >+ 0U, // BEXTR32rm >+ 0U, // BEXTR32rr >+ 0U, // BEXTR64rm >+ 0U, // BEXTR64rr >+ 0U, // BEXTRI32mi >+ 0U, // BEXTRI32ri >+ 0U, // BEXTRI64mi >+ 0U, // BEXTRI64ri >+ 0U, // BLCFILL32rm >+ 0U, // BLCFILL32rr >+ 0U, // BLCFILL64rm >+ 0U, // BLCFILL64rr >+ 0U, // BLCI32rm >+ 0U, // BLCI32rr >+ 0U, // BLCI64rm >+ 0U, // BLCI64rr >+ 0U, // BLCIC32rm >+ 0U, // BLCIC32rr >+ 0U, // BLCIC64rm >+ 0U, // BLCIC64rr >+ 0U, // BLCMSK32rm >+ 0U, // BLCMSK32rr >+ 0U, // BLCMSK64rm >+ 0U, // BLCMSK64rr >+ 0U, // BLCS32rm >+ 0U, // BLCS32rr >+ 0U, // BLCS64rm >+ 0U, // BLCS64rr >+ 0U, // BLENDPDrmi >+ 0U, // BLENDPDrri >+ 0U, // BLENDPSrmi >+ 0U, // BLENDPSrri >+ 0U, // BLENDVPDrm0 >+ 0U, // BLENDVPDrr0 >+ 0U, // BLENDVPSrm0 >+ 0U, // BLENDVPSrr0 >+ 0U, // BLSFILL32rm >+ 0U, // BLSFILL32rr >+ 0U, // BLSFILL64rm >+ 0U, // BLSFILL64rr >+ 0U, // BLSI32rm >+ 0U, // BLSI32rr >+ 0U, // BLSI64rm >+ 0U, // BLSI64rr >+ 0U, // BLSIC32rm >+ 0U, // BLSIC32rr >+ 0U, // BLSIC64rm >+ 0U, // BLSIC64rr >+ 0U, // BLSMSK32rm >+ 0U, // BLSMSK32rr >+ 0U, // BLSMSK64rm >+ 0U, // BLSMSK64rr >+ 0U, // BLSR32rm >+ 0U, // BLSR32rr >+ 0U, // BLSR64rm >+ 0U, // BLSR64rr >+ 0U, // BOUNDS16rm >+ 0U, // BOUNDS32rm >+ 0U, // BSF16rm >+ 0U, // BSF16rr >+ 0U, // BSF32rm >+ 0U, // BSF32rr >+ 0U, // BSF64rm >+ 0U, // BSF64rr >+ 0U, // BSR16rm >+ 0U, // BSR16rr >+ 0U, // BSR32rm >+ 0U, // BSR32rr >+ 0U, // BSR64rm >+ 0U, // BSR64rr >+ 0U, // BSWAP32r >+ 0U, // BSWAP64r >+ 0U, // BT16mi8 >+ 0U, // BT16mr >+ 0U, // BT16ri8 >+ 0U, // BT16rr >+ 0U, // BT32mi8 >+ 0U, // BT32mr >+ 0U, // BT32ri8 >+ 0U, // BT32rr >+ 0U, // BT64mi8 >+ 0U, // BT64mr >+ 0U, // BT64ri8 >+ 0U, // BT64rr >+ 0U, // BTC16mi8 >+ 0U, // BTC16mr >+ 0U, // BTC16ri8 >+ 0U, // BTC16rr >+ 0U, // BTC32mi8 >+ 0U, // BTC32mr >+ 0U, // BTC32ri8 >+ 0U, // BTC32rr >+ 0U, // BTC64mi8 >+ 0U, // BTC64mr >+ 0U, // BTC64ri8 >+ 0U, // BTC64rr >+ 0U, // BTR16mi8 >+ 0U, // BTR16mr >+ 0U, // BTR16ri8 >+ 0U, // BTR16rr >+ 0U, // BTR32mi8 >+ 0U, // BTR32mr >+ 0U, // BTR32ri8 >+ 0U, // BTR32rr >+ 0U, // BTR64mi8 >+ 0U, // BTR64mr >+ 0U, // BTR64ri8 >+ 0U, // BTR64rr >+ 0U, // BTS16mi8 >+ 0U, // BTS16mr >+ 0U, // BTS16ri8 >+ 0U, // BTS16rr >+ 0U, // BTS32mi8 >+ 0U, // BTS32mr >+ 0U, // BTS32ri8 >+ 0U, // BTS32rr >+ 0U, // BTS64mi8 >+ 0U, // BTS64mr >+ 0U, // BTS64ri8 >+ 0U, // BTS64rr >+ 0U, // BZHI32rm >+ 0U, // BZHI32rr >+ 0U, // BZHI64rm >+ 0U, // BZHI64rr >+ 0U, // CALL16m >+ 0U, // CALL16r >+ 0U, // CALL32m >+ 0U, // CALL32r >+ 0U, // CALL64m >+ 0U, // CALL64pcrel32 >+ 0U, // CALL64r >+ 0U, // CALLpcrel16 >+ 0U, // CALLpcrel32 >+ 0U, // CBW >+ 0U, // CDQ >+ 0U, // CDQE >+ 0U, // CHS_F >+ 0U, // CHS_Fp32 >+ 0U, // CHS_Fp64 >+ 0U, // CHS_Fp80 >+ 0U, // CLAC >+ 0U, // CLC >+ 0U, // CLD >+ 0U, // CLFLUSH >+ 0U, // CLGI >+ 0U, // CLI >+ 0U, // CLTS >+ 0U, // CMC >+ 0U, // CMOVA16rm >+ 0U, // CMOVA16rr >+ 0U, // CMOVA32rm >+ 0U, // CMOVA32rr >+ 0U, // CMOVA64rm >+ 0U, // CMOVA64rr >+ 0U, // CMOVAE16rm >+ 0U, // CMOVAE16rr >+ 0U, // CMOVAE32rm >+ 0U, // CMOVAE32rr >+ 0U, // CMOVAE64rm >+ 0U, // CMOVAE64rr >+ 0U, // CMOVB16rm >+ 0U, // CMOVB16rr >+ 0U, // CMOVB32rm >+ 0U, // CMOVB32rr >+ 0U, // CMOVB64rm >+ 0U, // CMOVB64rr >+ 0U, // CMOVBE16rm >+ 0U, // CMOVBE16rr >+ 0U, // CMOVBE32rm >+ 0U, // CMOVBE32rr >+ 0U, // CMOVBE64rm >+ 0U, // CMOVBE64rr >+ 0U, // CMOVBE_F >+ 0U, // CMOVBE_Fp32 >+ 0U, // CMOVBE_Fp64 >+ 0U, // CMOVBE_Fp80 >+ 0U, // CMOVB_F >+ 0U, // CMOVB_Fp32 >+ 0U, // CMOVB_Fp64 >+ 0U, // CMOVB_Fp80 >+ 0U, // CMOVE16rm >+ 0U, // CMOVE16rr >+ 0U, // CMOVE32rm >+ 0U, // CMOVE32rr >+ 0U, // CMOVE64rm >+ 0U, // CMOVE64rr >+ 0U, // CMOVE_F >+ 0U, // CMOVE_Fp32 >+ 0U, // CMOVE_Fp64 >+ 0U, // CMOVE_Fp80 >+ 0U, // CMOVG16rm >+ 0U, // CMOVG16rr >+ 0U, // CMOVG32rm >+ 0U, // CMOVG32rr >+ 0U, // CMOVG64rm >+ 0U, // CMOVG64rr >+ 0U, // CMOVGE16rm >+ 0U, // CMOVGE16rr >+ 0U, // CMOVGE32rm >+ 0U, // CMOVGE32rr >+ 0U, // CMOVGE64rm >+ 0U, // CMOVGE64rr >+ 0U, // CMOVL16rm >+ 0U, // CMOVL16rr >+ 0U, // CMOVL32rm >+ 0U, // CMOVL32rr >+ 0U, // CMOVL64rm >+ 0U, // CMOVL64rr >+ 0U, // CMOVLE16rm >+ 0U, // CMOVLE16rr >+ 0U, // CMOVLE32rm >+ 0U, // CMOVLE32rr >+ 0U, // CMOVLE64rm >+ 0U, // CMOVLE64rr >+ 0U, // CMOVNBE_F >+ 0U, // CMOVNBE_Fp32 >+ 0U, // CMOVNBE_Fp64 >+ 0U, // CMOVNBE_Fp80 >+ 0U, // CMOVNB_F >+ 0U, // CMOVNB_Fp32 >+ 0U, // CMOVNB_Fp64 >+ 0U, // CMOVNB_Fp80 >+ 0U, // CMOVNE16rm >+ 0U, // CMOVNE16rr >+ 0U, // CMOVNE32rm >+ 0U, // CMOVNE32rr >+ 0U, // CMOVNE64rm >+ 0U, // CMOVNE64rr >+ 0U, // CMOVNE_F >+ 0U, // CMOVNE_Fp32 >+ 0U, // CMOVNE_Fp64 >+ 0U, // CMOVNE_Fp80 >+ 0U, // CMOVNO16rm >+ 0U, // CMOVNO16rr >+ 0U, // CMOVNO32rm >+ 0U, // CMOVNO32rr >+ 0U, // CMOVNO64rm >+ 0U, // CMOVNO64rr >+ 0U, // CMOVNP16rm >+ 0U, // CMOVNP16rr >+ 0U, // CMOVNP32rm >+ 0U, // CMOVNP32rr >+ 0U, // CMOVNP64rm >+ 0U, // CMOVNP64rr >+ 0U, // CMOVNP_F >+ 0U, // CMOVNP_Fp32 >+ 0U, // CMOVNP_Fp64 >+ 0U, // CMOVNP_Fp80 >+ 0U, // CMOVNS16rm >+ 0U, // CMOVNS16rr >+ 0U, // CMOVNS32rm >+ 0U, // CMOVNS32rr >+ 0U, // CMOVNS64rm >+ 0U, // CMOVNS64rr >+ 0U, // CMOVO16rm >+ 0U, // CMOVO16rr >+ 0U, // CMOVO32rm >+ 0U, // CMOVO32rr >+ 0U, // CMOVO64rm >+ 0U, // CMOVO64rr >+ 0U, // CMOVP16rm >+ 0U, // CMOVP16rr >+ 0U, // CMOVP32rm >+ 0U, // CMOVP32rr >+ 0U, // CMOVP64rm >+ 0U, // CMOVP64rr >+ 0U, // CMOVP_F >+ 0U, // CMOVP_Fp32 >+ 0U, // CMOVP_Fp64 >+ 0U, // CMOVP_Fp80 >+ 0U, // CMOVS16rm >+ 0U, // CMOVS16rr >+ 0U, // CMOVS32rm >+ 0U, // CMOVS32rr >+ 0U, // CMOVS64rm >+ 0U, // CMOVS64rr >+ 0U, // CMOV_FR32 >+ 0U, // CMOV_FR64 >+ 0U, // CMOV_GR16 >+ 0U, // CMOV_GR32 >+ 0U, // CMOV_GR8 >+ 0U, // CMOV_RFP32 >+ 0U, // CMOV_RFP64 >+ 0U, // CMOV_RFP80 >+ 0U, // CMOV_V16F32 >+ 0U, // CMOV_V2F64 >+ 0U, // CMOV_V2I64 >+ 0U, // CMOV_V4F32 >+ 0U, // CMOV_V4F64 >+ 0U, // CMOV_V4I64 >+ 0U, // CMOV_V8F32 >+ 0U, // CMOV_V8F64 >+ 0U, // CMOV_V8I64 >+ 0U, // CMP16i16 >+ 0U, // CMP16mi >+ 0U, // CMP16mi8 >+ 0U, // CMP16mr >+ 0U, // CMP16ri >+ 0U, // CMP16ri8 >+ 0U, // CMP16rm >+ 0U, // CMP16rr >+ 0U, // CMP16rr_REV >+ 0U, // CMP32i32 >+ 0U, // CMP32mi >+ 0U, // CMP32mi8 >+ 0U, // CMP32mr >+ 0U, // CMP32ri >+ 0U, // CMP32ri8 >+ 0U, // CMP32rm >+ 0U, // CMP32rr >+ 0U, // CMP32rr_REV >+ 0U, // CMP64i32 >+ 0U, // CMP64mi32 >+ 0U, // CMP64mi8 >+ 0U, // CMP64mr >+ 0U, // CMP64ri32 >+ 0U, // CMP64ri8 >+ 0U, // CMP64rm >+ 0U, // CMP64rr >+ 0U, // CMP64rr_REV >+ 0U, // CMP8i8 >+ 0U, // CMP8mi >+ 0U, // CMP8mr >+ 0U, // CMP8ri >+ 0U, // CMP8rm >+ 0U, // CMP8rr >+ 0U, // CMP8rr_REV >+ 8U, // CMPPDrmi >+ 0U, // CMPPDrmi_alt >+ 4U, // CMPPDrri >+ 0U, // CMPPDrri_alt >+ 8U, // CMPPSrmi >+ 0U, // CMPPSrmi_alt >+ 4U, // CMPPSrri >+ 0U, // CMPPSrri_alt >+ 0U, // CMPSB >+ 8U, // CMPSDrm >+ 0U, // CMPSDrm_alt >+ 4U, // CMPSDrr >+ 0U, // CMPSDrr_alt >+ 0U, // CMPSL >+ 0U, // CMPSQ >+ 8U, // CMPSSrm >+ 0U, // CMPSSrm_alt >+ 4U, // CMPSSrr >+ 0U, // CMPSSrr_alt >+ 0U, // CMPSW >+ 0U, // CMPXCHG16B >+ 0U, // CMPXCHG16rm >+ 0U, // CMPXCHG16rr >+ 0U, // CMPXCHG32rm >+ 0U, // CMPXCHG32rr >+ 0U, // CMPXCHG64rm >+ 0U, // CMPXCHG64rr >+ 0U, // CMPXCHG8B >+ 0U, // CMPXCHG8rm >+ 0U, // CMPXCHG8rr >+ 0U, // COMISDrm >+ 0U, // COMISDrr >+ 0U, // COMISSrm >+ 0U, // COMISSrr >+ 0U, // COMP_FST0r >+ 0U, // COM_FIPr >+ 0U, // COM_FIr >+ 0U, // COM_FST0r >+ 0U, // COS_F >+ 0U, // COS_Fp32 >+ 0U, // COS_Fp64 >+ 0U, // COS_Fp80 >+ 0U, // CPUID32 >+ 0U, // CPUID64 >+ 0U, // CQO >+ 0U, // CRC32r32m16 >+ 0U, // CRC32r32m32 >+ 0U, // CRC32r32m8 >+ 0U, // CRC32r32r16 >+ 0U, // CRC32r32r32 >+ 0U, // CRC32r32r8 >+ 0U, // CRC32r64m64 >+ 0U, // CRC32r64m8 >+ 0U, // CRC32r64r64 >+ 0U, // CRC32r64r8 >+ 0U, // CVTDQ2PDrm >+ 0U, // CVTDQ2PDrr >+ 0U, // CVTDQ2PSrm >+ 0U, // CVTDQ2PSrr >+ 0U, // CVTPD2DQrm >+ 0U, // CVTPD2DQrr >+ 0U, // CVTPD2PSrm >+ 0U, // CVTPD2PSrr >+ 0U, // CVTPS2DQrm >+ 0U, // CVTPS2DQrr >+ 0U, // CVTPS2PDrm >+ 0U, // CVTPS2PDrr >+ 0U, // CVTSD2SI64rm >+ 0U, // CVTSD2SI64rr >+ 0U, // CVTSD2SIrm >+ 0U, // CVTSD2SIrr >+ 0U, // CVTSD2SSrm >+ 0U, // CVTSD2SSrr >+ 0U, // CVTSI2SD64rm >+ 0U, // CVTSI2SD64rr >+ 0U, // CVTSI2SDrm >+ 0U, // CVTSI2SDrr >+ 0U, // CVTSI2SS64rm >+ 0U, // CVTSI2SS64rr >+ 0U, // CVTSI2SSrm >+ 0U, // CVTSI2SSrr >+ 0U, // CVTSS2SDrm >+ 0U, // CVTSS2SDrr >+ 0U, // CVTSS2SI64rm >+ 0U, // CVTSS2SI64rr >+ 0U, // CVTSS2SIrm >+ 0U, // CVTSS2SIrr >+ 0U, // CVTTPD2DQrm >+ 0U, // CVTTPD2DQrr >+ 0U, // CVTTPS2DQrm >+ 0U, // CVTTPS2DQrr >+ 0U, // CVTTSD2SI64rm >+ 0U, // CVTTSD2SI64rr >+ 0U, // CVTTSD2SIrm >+ 0U, // CVTTSD2SIrr >+ 0U, // CVTTSS2SI64rm >+ 0U, // CVTTSS2SI64rr >+ 0U, // CVTTSS2SIrm >+ 0U, // CVTTSS2SIrr >+ 0U, // CWD >+ 0U, // CWDE >+ 0U, // DAA >+ 0U, // DAS >+ 0U, // DATA16_PREFIX >+ 0U, // DEC16m >+ 0U, // DEC16r >+ 0U, // DEC32_16r >+ 0U, // DEC32_32r >+ 0U, // DEC32m >+ 0U, // DEC32r >+ 0U, // DEC64_16m >+ 0U, // DEC64_16r >+ 0U, // DEC64_32m >+ 0U, // DEC64_32r >+ 0U, // DEC64m >+ 0U, // DEC64r >+ 0U, // DEC8m >+ 0U, // DEC8r >+ 0U, // DIV16m >+ 0U, // DIV16r >+ 0U, // DIV32m >+ 0U, // DIV32r >+ 0U, // DIV64m >+ 0U, // DIV64r >+ 0U, // DIV8m >+ 0U, // DIV8r >+ 0U, // DIVPDrm >+ 0U, // DIVPDrr >+ 0U, // DIVPSrm >+ 0U, // DIVPSrr >+ 0U, // DIVR_F32m >+ 0U, // DIVR_F64m >+ 0U, // DIVR_FI16m >+ 0U, // DIVR_FI32m >+ 0U, // DIVR_FPrST0 >+ 0U, // DIVR_FST0r >+ 0U, // DIVR_Fp32m >+ 0U, // DIVR_Fp64m >+ 0U, // DIVR_Fp64m32 >+ 0U, // DIVR_Fp80m32 >+ 0U, // DIVR_Fp80m64 >+ 0U, // DIVR_FpI16m32 >+ 0U, // DIVR_FpI16m64 >+ 0U, // DIVR_FpI16m80 >+ 0U, // DIVR_FpI32m32 >+ 0U, // DIVR_FpI32m64 >+ 0U, // DIVR_FpI32m80 >+ 0U, // DIVR_FrST0 >+ 0U, // DIVSDrm >+ 0U, // DIVSDrm_Int >+ 0U, // DIVSDrr >+ 0U, // DIVSDrr_Int >+ 0U, // DIVSSrm >+ 0U, // DIVSSrm_Int >+ 0U, // DIVSSrr >+ 0U, // DIVSSrr_Int >+ 0U, // DIV_F32m >+ 0U, // DIV_F64m >+ 0U, // DIV_FI16m >+ 0U, // DIV_FI32m >+ 0U, // DIV_FPrST0 >+ 0U, // DIV_FST0r >+ 0U, // DIV_Fp32 >+ 0U, // DIV_Fp32m >+ 0U, // DIV_Fp64 >+ 0U, // DIV_Fp64m >+ 0U, // DIV_Fp64m32 >+ 0U, // DIV_Fp80 >+ 0U, // DIV_Fp80m32 >+ 0U, // DIV_Fp80m64 >+ 0U, // DIV_FpI16m32 >+ 0U, // DIV_FpI16m64 >+ 0U, // DIV_FpI16m80 >+ 0U, // DIV_FpI32m32 >+ 0U, // DIV_FpI32m64 >+ 0U, // DIV_FpI32m80 >+ 0U, // DIV_FrST0 >+ 0U, // DPPDrmi >+ 0U, // DPPDrri >+ 0U, // DPPSrmi >+ 0U, // DPPSrri >+ 0U, // EH_RETURN >+ 0U, // EH_RETURN64 >+ 0U, // EH_SjLj_LongJmp32 >+ 0U, // EH_SjLj_LongJmp64 >+ 0U, // EH_SjLj_SetJmp32 >+ 0U, // EH_SjLj_SetJmp64 >+ 0U, // EH_SjLj_Setup >+ 0U, // ENCLS >+ 0U, // ENCLU >+ 0U, // ENTER >+ 0U, // EXTRACTPSmr >+ 0U, // EXTRACTPSrr >+ 0U, // EXTRQ >+ 0U, // EXTRQI >+ 0U, // F2XM1 >+ 0U, // FARCALL16i >+ 0U, // FARCALL16m >+ 0U, // FARCALL32i >+ 0U, // FARCALL32m >+ 0U, // FARCALL64 >+ 0U, // FARJMP16i >+ 0U, // FARJMP16m >+ 0U, // FARJMP32i >+ 0U, // FARJMP32m >+ 0U, // FARJMP64 >+ 0U, // FBLDm >+ 0U, // FBSTPm >+ 0U, // FCOM32m >+ 0U, // FCOM64m >+ 0U, // FCOMP32m >+ 0U, // FCOMP64m >+ 0U, // FCOMPP >+ 0U, // FDECSTP >+ 0U, // FEMMS >+ 0U, // FFREE >+ 0U, // FICOM16m >+ 0U, // FICOM32m >+ 0U, // FICOMP16m >+ 0U, // FICOMP32m >+ 0U, // FINCSTP >+ 0U, // FLDCW16m >+ 0U, // FLDENVm >+ 0U, // FLDL2E >+ 0U, // FLDL2T >+ 0U, // FLDLG2 >+ 0U, // FLDLN2 >+ 0U, // FLDPI >+ 0U, // FNCLEX >+ 0U, // FNINIT >+ 0U, // FNOP >+ 0U, // FNSTCW16m >+ 0U, // FNSTSW16r >+ 0U, // FNSTSWm >+ 0U, // FP32_TO_INT16_IN_MEM >+ 0U, // FP32_TO_INT32_IN_MEM >+ 0U, // FP32_TO_INT64_IN_MEM >+ 0U, // FP64_TO_INT16_IN_MEM >+ 0U, // FP64_TO_INT32_IN_MEM >+ 0U, // FP64_TO_INT64_IN_MEM >+ 0U, // FP80_TO_INT16_IN_MEM >+ 0U, // FP80_TO_INT32_IN_MEM >+ 0U, // FP80_TO_INT64_IN_MEM >+ 0U, // FPATAN >+ 0U, // FPREM >+ 0U, // FPREM1 >+ 0U, // FPTAN >+ 0U, // FRNDINT >+ 0U, // FRSTORm >+ 0U, // FSAVEm >+ 0U, // FSCALE >+ 0U, // FSETPM >+ 0U, // FSINCOS >+ 0U, // FSTENVm >+ 0U, // FXAM >+ 0U, // FXRSTOR >+ 0U, // FXRSTOR64 >+ 0U, // FXSAVE >+ 0U, // FXSAVE64 >+ 0U, // FXTRACT >+ 0U, // FYL2X >+ 0U, // FYL2XP1 >+ 0U, // FsANDNPDrm >+ 0U, // FsANDNPDrr >+ 0U, // FsANDNPSrm >+ 0U, // FsANDNPSrr >+ 0U, // FsANDPDrm >+ 0U, // FsANDPDrr >+ 0U, // FsANDPSrm >+ 0U, // FsANDPSrr >+ 0U, // FsFLD0SD >+ 0U, // FsFLD0SS >+ 0U, // FsMOVAPDrm >+ 0U, // FsMOVAPSrm >+ 0U, // FsORPDrm >+ 0U, // FsORPDrr >+ 0U, // FsORPSrm >+ 0U, // FsORPSrr >+ 0U, // FsVMOVAPDrm >+ 0U, // FsVMOVAPSrm >+ 0U, // FsXORPDrm >+ 0U, // FsXORPDrr >+ 0U, // FsXORPSrm >+ 0U, // FsXORPSrr >+ 0U, // GETSEC >+ 0U, // HADDPDrm >+ 0U, // HADDPDrr >+ 0U, // HADDPSrm >+ 0U, // HADDPSrr >+ 0U, // HLT >+ 0U, // HSUBPDrm >+ 0U, // HSUBPDrr >+ 0U, // HSUBPSrm >+ 0U, // HSUBPSrr >+ 0U, // IDIV16m >+ 0U, // IDIV16r >+ 0U, // IDIV32m >+ 0U, // IDIV32r >+ 0U, // IDIV64m >+ 0U, // IDIV64r >+ 0U, // IDIV8m >+ 0U, // IDIV8r >+ 0U, // ILD_F16m >+ 0U, // ILD_F32m >+ 0U, // ILD_F64m >+ 0U, // ILD_Fp16m32 >+ 0U, // ILD_Fp16m64 >+ 0U, // ILD_Fp16m80 >+ 0U, // ILD_Fp32m32 >+ 0U, // ILD_Fp32m64 >+ 0U, // ILD_Fp32m80 >+ 0U, // ILD_Fp64m32 >+ 0U, // ILD_Fp64m64 >+ 0U, // ILD_Fp64m80 >+ 0U, // IMUL16m >+ 0U, // IMUL16r >+ 0U, // IMUL16rm >+ 0U, // IMUL16rmi >+ 0U, // IMUL16rmi8 >+ 0U, // IMUL16rr >+ 0U, // IMUL16rri >+ 0U, // IMUL16rri8 >+ 0U, // IMUL32m >+ 0U, // IMUL32r >+ 0U, // IMUL32rm >+ 0U, // IMUL32rmi >+ 0U, // IMUL32rmi8 >+ 0U, // IMUL32rr >+ 0U, // IMUL32rri >+ 0U, // IMUL32rri8 >+ 0U, // IMUL64m >+ 0U, // IMUL64r >+ 0U, // IMUL64rm >+ 0U, // IMUL64rmi32 >+ 0U, // IMUL64rmi8 >+ 0U, // IMUL64rr >+ 0U, // IMUL64rri32 >+ 0U, // IMUL64rri8 >+ 0U, // IMUL8m >+ 0U, // IMUL8r >+ 0U, // IN16ri >+ 0U, // IN16rr >+ 0U, // IN32ri >+ 0U, // IN32rr >+ 0U, // IN8ri >+ 0U, // IN8rr >+ 0U, // INC16m >+ 0U, // INC16r >+ 0U, // INC32_16r >+ 0U, // INC32_32r >+ 0U, // INC32m >+ 0U, // INC32r >+ 0U, // INC64_16m >+ 0U, // INC64_16r >+ 0U, // INC64_32m >+ 0U, // INC64_32r >+ 0U, // INC64m >+ 0U, // INC64r >+ 0U, // INC8m >+ 0U, // INC8r >+ 0U, // INSB >+ 0U, // INSERTPSrm >+ 0U, // INSERTPSrr >+ 0U, // INSERTQ >+ 0U, // INSERTQI >+ 0U, // INSL >+ 0U, // INSW >+ 0U, // INT >+ 0U, // INT1 >+ 0U, // INT3 >+ 0U, // INTO >+ 0U, // INVD >+ 0U, // INVEPT32 >+ 0U, // INVEPT64 >+ 0U, // INVLPG >+ 0U, // INVLPGA32 >+ 0U, // INVLPGA64 >+ 0U, // INVPCID32 >+ 0U, // INVPCID64 >+ 0U, // INVVPID32 >+ 0U, // INVVPID64 >+ 0U, // IRET16 >+ 0U, // IRET32 >+ 0U, // IRET64 >+ 0U, // ISTT_FP16m >+ 0U, // ISTT_FP32m >+ 0U, // ISTT_FP64m >+ 0U, // ISTT_Fp16m32 >+ 0U, // ISTT_Fp16m64 >+ 0U, // ISTT_Fp16m80 >+ 0U, // ISTT_Fp32m32 >+ 0U, // ISTT_Fp32m64 >+ 0U, // ISTT_Fp32m80 >+ 0U, // ISTT_Fp64m32 >+ 0U, // ISTT_Fp64m64 >+ 0U, // ISTT_Fp64m80 >+ 0U, // IST_F16m >+ 0U, // IST_F32m >+ 0U, // IST_FP16m >+ 0U, // IST_FP32m >+ 0U, // IST_FP64m >+ 0U, // IST_Fp16m32 >+ 0U, // IST_Fp16m64 >+ 0U, // IST_Fp16m80 >+ 0U, // IST_Fp32m32 >+ 0U, // IST_Fp32m64 >+ 0U, // IST_Fp32m80 >+ 0U, // IST_Fp64m32 >+ 0U, // IST_Fp64m64 >+ 0U, // IST_Fp64m80 >+ 8U, // Int_CMPSDrm >+ 4U, // Int_CMPSDrr >+ 8U, // Int_CMPSSrm >+ 4U, // Int_CMPSSrr >+ 0U, // Int_COMISDrm >+ 0U, // Int_COMISDrr >+ 0U, // Int_COMISSrm >+ 0U, // Int_COMISSrr >+ 0U, // Int_CVTSD2SSrm >+ 0U, // Int_CVTSD2SSrr >+ 0U, // Int_CVTSI2SD64rm >+ 0U, // Int_CVTSI2SD64rr >+ 0U, // Int_CVTSI2SDrm >+ 0U, // Int_CVTSI2SDrr >+ 0U, // Int_CVTSI2SS64rm >+ 0U, // Int_CVTSI2SS64rr >+ 0U, // Int_CVTSI2SSrm >+ 0U, // Int_CVTSI2SSrr >+ 0U, // Int_CVTSS2SDrm >+ 0U, // Int_CVTSS2SDrr >+ 0U, // Int_CVTTSD2SI64rm >+ 0U, // Int_CVTTSD2SI64rr >+ 0U, // Int_CVTTSD2SIrm >+ 0U, // Int_CVTTSD2SIrr >+ 0U, // Int_CVTTSS2SI64rm >+ 0U, // Int_CVTTSS2SI64rr >+ 0U, // Int_CVTTSS2SIrm >+ 0U, // Int_CVTTSS2SIrr >+ 0U, // Int_MemBarrier >+ 0U, // Int_UCOMISDrm >+ 0U, // Int_UCOMISDrr >+ 0U, // Int_UCOMISSrm >+ 0U, // Int_UCOMISSrr >+ 76U, // Int_VCMPSDrm >+ 1156U, // Int_VCMPSDrr >+ 76U, // Int_VCMPSSrm >+ 1156U, // Int_VCMPSSrr >+ 0U, // Int_VCOMISDZrm >+ 0U, // Int_VCOMISDZrr >+ 0U, // Int_VCOMISDrm >+ 0U, // Int_VCOMISDrr >+ 0U, // Int_VCOMISSZrm >+ 0U, // Int_VCOMISSZrr >+ 0U, // Int_VCOMISSrm >+ 0U, // Int_VCOMISSrr >+ 4U, // Int_VCVTSD2SSrm >+ 0U, // Int_VCVTSD2SSrr >+ 4U, // Int_VCVTSI2SD64Zrm >+ 0U, // Int_VCVTSI2SD64Zrr >+ 4U, // Int_VCVTSI2SD64rm >+ 0U, // Int_VCVTSI2SD64rr >+ 4U, // Int_VCVTSI2SDZrm >+ 0U, // Int_VCVTSI2SDZrr >+ 4U, // Int_VCVTSI2SDrm >+ 0U, // Int_VCVTSI2SDrr >+ 4U, // Int_VCVTSI2SS64Zrm >+ 0U, // Int_VCVTSI2SS64Zrr >+ 4U, // Int_VCVTSI2SS64rm >+ 0U, // Int_VCVTSI2SS64rr >+ 4U, // Int_VCVTSI2SSZrm >+ 0U, // Int_VCVTSI2SSZrr >+ 4U, // Int_VCVTSI2SSrm >+ 0U, // Int_VCVTSI2SSrr >+ 4U, // Int_VCVTSS2SDrm >+ 0U, // Int_VCVTSS2SDrr >+ 0U, // Int_VCVTTSD2SI64Zrm >+ 0U, // Int_VCVTTSD2SI64Zrr >+ 0U, // Int_VCVTTSD2SI64rm >+ 0U, // Int_VCVTTSD2SI64rr >+ 0U, // Int_VCVTTSD2SIZrm >+ 0U, // Int_VCVTTSD2SIZrr >+ 0U, // Int_VCVTTSD2SIrm >+ 0U, // Int_VCVTTSD2SIrr >+ 0U, // Int_VCVTTSD2USI64Zrm >+ 0U, // Int_VCVTTSD2USI64Zrr >+ 0U, // Int_VCVTTSD2USIZrm >+ 0U, // Int_VCVTTSD2USIZrr >+ 0U, // Int_VCVTTSS2SI64Zrm >+ 0U, // Int_VCVTTSS2SI64Zrr >+ 0U, // Int_VCVTTSS2SI64rm >+ 0U, // Int_VCVTTSS2SI64rr >+ 0U, // Int_VCVTTSS2SIZrm >+ 0U, // Int_VCVTTSS2SIZrr >+ 0U, // Int_VCVTTSS2SIrm >+ 0U, // Int_VCVTTSS2SIrr >+ 0U, // Int_VCVTTSS2USI64Zrm >+ 0U, // Int_VCVTTSS2USI64Zrr >+ 0U, // Int_VCVTTSS2USIZrm >+ 0U, // Int_VCVTTSS2USIZrr >+ 4U, // Int_VCVTUSI2SD64Zrm >+ 0U, // Int_VCVTUSI2SD64Zrr >+ 4U, // Int_VCVTUSI2SDZrm >+ 0U, // Int_VCVTUSI2SDZrr >+ 4U, // Int_VCVTUSI2SS64Zrm >+ 0U, // Int_VCVTUSI2SS64Zrr >+ 4U, // Int_VCVTUSI2SSZrm >+ 0U, // Int_VCVTUSI2SSZrr >+ 0U, // Int_VUCOMISDZrm >+ 0U, // Int_VUCOMISDZrr >+ 0U, // Int_VUCOMISDrm >+ 0U, // Int_VUCOMISDrr >+ 0U, // Int_VUCOMISSZrm >+ 0U, // Int_VUCOMISSZrr >+ 0U, // Int_VUCOMISSrm >+ 0U, // Int_VUCOMISSrr >+ 0U, // JAE_1 >+ 0U, // JAE_2 >+ 0U, // JAE_4 >+ 0U, // JA_1 >+ 0U, // JA_2 >+ 0U, // JA_4 >+ 0U, // JBE_1 >+ 0U, // JBE_2 >+ 0U, // JBE_4 >+ 0U, // JB_1 >+ 0U, // JB_2 >+ 0U, // JB_4 >+ 0U, // JCXZ >+ 0U, // JECXZ_32 >+ 0U, // JECXZ_64 >+ 0U, // JE_1 >+ 0U, // JE_2 >+ 0U, // JE_4 >+ 0U, // JGE_1 >+ 0U, // JGE_2 >+ 0U, // JGE_4 >+ 0U, // JG_1 >+ 0U, // JG_2 >+ 0U, // JG_4 >+ 0U, // JLE_1 >+ 0U, // JLE_2 >+ 0U, // JLE_4 >+ 0U, // JL_1 >+ 0U, // JL_2 >+ 0U, // JL_4 >+ 0U, // JMP16m >+ 0U, // JMP16r >+ 0U, // JMP32m >+ 0U, // JMP32r >+ 0U, // JMP64m >+ 0U, // JMP64r >+ 0U, // JMP_1 >+ 0U, // JMP_2 >+ 0U, // JMP_4 >+ 0U, // JNE_1 >+ 0U, // JNE_2 >+ 0U, // JNE_4 >+ 0U, // JNO_1 >+ 0U, // JNO_2 >+ 0U, // JNO_4 >+ 0U, // JNP_1 >+ 0U, // JNP_2 >+ 0U, // JNP_4 >+ 0U, // JNS_1 >+ 0U, // JNS_2 >+ 0U, // JNS_4 >+ 0U, // JO_1 >+ 0U, // JO_2 >+ 0U, // JO_4 >+ 0U, // JP_1 >+ 0U, // JP_2 >+ 0U, // JP_4 >+ 0U, // JRCXZ >+ 0U, // JS_1 >+ 0U, // JS_2 >+ 0U, // JS_4 >+ 0U, // KANDBrr >+ 0U, // KANDDrr >+ 0U, // KANDNBrr >+ 0U, // KANDNDrr >+ 0U, // KANDNQrr >+ 0U, // KANDNWrr >+ 0U, // KANDQrr >+ 0U, // KANDWrr >+ 0U, // KMOVBkk >+ 0U, // KMOVBkm >+ 0U, // KMOVBkr >+ 0U, // KMOVBmk >+ 0U, // KMOVBrk >+ 0U, // KMOVDkk >+ 0U, // KMOVDkm >+ 0U, // KMOVDkr >+ 0U, // KMOVDmk >+ 0U, // KMOVDrk >+ 0U, // KMOVQkk >+ 0U, // KMOVQkm >+ 0U, // KMOVQkr >+ 0U, // KMOVQmk >+ 0U, // KMOVQrk >+ 0U, // KMOVWkk >+ 0U, // KMOVWkm >+ 0U, // KMOVWkr >+ 0U, // KMOVWmk >+ 0U, // KMOVWrk >+ 0U, // KNOTBrr >+ 0U, // KNOTDrr >+ 0U, // KNOTQrr >+ 0U, // KNOTWrr >+ 0U, // KORBrr >+ 0U, // KORDrr >+ 0U, // KORQrr >+ 0U, // KORTESTWrr >+ 0U, // KORWrr >+ 0U, // KSET0B >+ 0U, // KSET0W >+ 0U, // KSET1B >+ 0U, // KSET1W >+ 0U, // KSHIFTLWri >+ 0U, // KSHIFTRWri >+ 0U, // KUNPCKBWrr >+ 0U, // KXNORBrr >+ 0U, // KXNORDrr >+ 0U, // KXNORQrr >+ 0U, // KXNORWrr >+ 0U, // KXORBrr >+ 0U, // KXORDrr >+ 0U, // KXORQrr >+ 0U, // KXORWrr >+ 0U, // LAHF >+ 0U, // LAR16rm >+ 0U, // LAR16rr >+ 0U, // LAR32rm >+ 0U, // LAR32rr >+ 0U, // LAR64rm >+ 0U, // LAR64rr >+ 0U, // LCMPXCHG16 >+ 0U, // LCMPXCHG16B >+ 0U, // LCMPXCHG32 >+ 0U, // LCMPXCHG64 >+ 0U, // LCMPXCHG8 >+ 0U, // LCMPXCHG8B >+ 0U, // LDDQUrm >+ 0U, // LDMXCSR >+ 0U, // LDS16rm >+ 0U, // LDS32rm >+ 0U, // LD_F0 >+ 0U, // LD_F1 >+ 0U, // LD_F32m >+ 0U, // LD_F64m >+ 0U, // LD_F80m >+ 0U, // LD_Fp032 >+ 0U, // LD_Fp064 >+ 0U, // LD_Fp080 >+ 0U, // LD_Fp132 >+ 0U, // LD_Fp164 >+ 0U, // LD_Fp180 >+ 0U, // LD_Fp32m >+ 0U, // LD_Fp32m64 >+ 0U, // LD_Fp32m80 >+ 0U, // LD_Fp64m >+ 0U, // LD_Fp64m80 >+ 0U, // LD_Fp80m >+ 0U, // LD_Frr >+ 0U, // LEA16r >+ 0U, // LEA32r >+ 0U, // LEA64_32r >+ 0U, // LEA64r >+ 0U, // LEAVE >+ 0U, // LEAVE64 >+ 0U, // LES16rm >+ 0U, // LES32rm >+ 0U, // LFENCE >+ 0U, // LFS16rm >+ 0U, // LFS32rm >+ 0U, // LFS64rm >+ 0U, // LGDT16m >+ 0U, // LGDT32m >+ 0U, // LGDT64m >+ 0U, // LGS16rm >+ 0U, // LGS32rm >+ 0U, // LGS64rm >+ 0U, // LIDT16m >+ 0U, // LIDT32m >+ 0U, // LIDT64m >+ 0U, // LLDT16m >+ 0U, // LLDT16r >+ 0U, // LMSW16m >+ 0U, // LMSW16r >+ 0U, // LOCK_ADD16mi >+ 0U, // LOCK_ADD16mi8 >+ 0U, // LOCK_ADD16mr >+ 0U, // LOCK_ADD32mi >+ 0U, // LOCK_ADD32mi8 >+ 0U, // LOCK_ADD32mr >+ 0U, // LOCK_ADD64mi32 >+ 0U, // LOCK_ADD64mi8 >+ 0U, // LOCK_ADD64mr >+ 0U, // LOCK_ADD8mi >+ 0U, // LOCK_ADD8mr >+ 0U, // LOCK_AND16mi >+ 0U, // LOCK_AND16mi8 >+ 0U, // LOCK_AND16mr >+ 0U, // LOCK_AND32mi >+ 0U, // LOCK_AND32mi8 >+ 0U, // LOCK_AND32mr >+ 0U, // LOCK_AND64mi32 >+ 0U, // LOCK_AND64mi8 >+ 0U, // LOCK_AND64mr >+ 0U, // LOCK_AND8mi >+ 0U, // LOCK_AND8mr >+ 0U, // LOCK_DEC16m >+ 0U, // LOCK_DEC32m >+ 0U, // LOCK_DEC64m >+ 0U, // LOCK_DEC8m >+ 0U, // LOCK_INC16m >+ 0U, // LOCK_INC32m >+ 0U, // LOCK_INC64m >+ 0U, // LOCK_INC8m >+ 0U, // LOCK_OR16mi >+ 0U, // LOCK_OR16mi8 >+ 0U, // LOCK_OR16mr >+ 0U, // LOCK_OR32mi >+ 0U, // LOCK_OR32mi8 >+ 0U, // LOCK_OR32mr >+ 0U, // LOCK_OR64mi32 >+ 0U, // LOCK_OR64mi8 >+ 0U, // LOCK_OR64mr >+ 0U, // LOCK_OR8mi >+ 0U, // LOCK_OR8mr >+ 0U, // LOCK_PREFIX >+ 0U, // LOCK_SUB16mi >+ 0U, // LOCK_SUB16mi8 >+ 0U, // LOCK_SUB16mr >+ 0U, // LOCK_SUB32mi >+ 0U, // LOCK_SUB32mi8 >+ 0U, // LOCK_SUB32mr >+ 0U, // LOCK_SUB64mi32 >+ 0U, // LOCK_SUB64mi8 >+ 0U, // LOCK_SUB64mr >+ 0U, // LOCK_SUB8mi >+ 0U, // LOCK_SUB8mr >+ 0U, // LOCK_XOR16mi >+ 0U, // LOCK_XOR16mi8 >+ 0U, // LOCK_XOR16mr >+ 0U, // LOCK_XOR32mi >+ 0U, // LOCK_XOR32mi8 >+ 0U, // LOCK_XOR32mr >+ 0U, // LOCK_XOR64mi32 >+ 0U, // LOCK_XOR64mi8 >+ 0U, // LOCK_XOR64mr >+ 0U, // LOCK_XOR8mi >+ 0U, // LOCK_XOR8mr >+ 0U, // LODSB >+ 0U, // LODSL >+ 0U, // LODSQ >+ 0U, // LODSW >+ 0U, // LOOP >+ 0U, // LOOPE >+ 0U, // LOOPNE >+ 0U, // LRETIL >+ 0U, // LRETIQ >+ 0U, // LRETIW >+ 0U, // LRETL >+ 0U, // LRETQ >+ 0U, // LRETW >+ 0U, // LSL16rm >+ 0U, // LSL16rr >+ 0U, // LSL32rm >+ 0U, // LSL32rr >+ 0U, // LSL64rm >+ 0U, // LSL64rr >+ 0U, // LSS16rm >+ 0U, // LSS32rm >+ 0U, // LSS64rm >+ 0U, // LTRm >+ 0U, // LTRr >+ 0U, // LXADD16 >+ 0U, // LXADD32 >+ 0U, // LXADD64 >+ 1U, // LXADD8 >+ 0U, // LZCNT16rm >+ 0U, // LZCNT16rr >+ 0U, // LZCNT32rm >+ 0U, // LZCNT32rr >+ 0U, // LZCNT64rm >+ 0U, // LZCNT64rr >+ 0U, // MASKMOVDQU >+ 0U, // MASKMOVDQU64 >+ 0U, // MAXCPDrm >+ 0U, // MAXCPDrr >+ 0U, // MAXCPSrm >+ 0U, // MAXCPSrr >+ 0U, // MAXCSDrm >+ 0U, // MAXCSDrr >+ 0U, // MAXCSSrm >+ 0U, // MAXCSSrr >+ 0U, // MAXPDrm >+ 0U, // MAXPDrr >+ 0U, // MAXPSrm >+ 0U, // MAXPSrr >+ 0U, // MAXSDrm >+ 0U, // MAXSDrm_Int >+ 0U, // MAXSDrr >+ 0U, // MAXSDrr_Int >+ 0U, // MAXSSrm >+ 0U, // MAXSSrm_Int >+ 0U, // MAXSSrr >+ 0U, // MAXSSrr_Int >+ 0U, // MFENCE >+ 0U, // MINCPDrm >+ 0U, // MINCPDrr >+ 0U, // MINCPSrm >+ 0U, // MINCPSrr >+ 0U, // MINCSDrm >+ 0U, // MINCSDrr >+ 0U, // MINCSSrm >+ 0U, // MINCSSrr >+ 0U, // MINPDrm >+ 0U, // MINPDrr >+ 0U, // MINPSrm >+ 0U, // MINPSrr >+ 0U, // MINSDrm >+ 0U, // MINSDrm_Int >+ 0U, // MINSDrr >+ 0U, // MINSDrr_Int >+ 0U, // MINSSrm >+ 0U, // MINSSrm_Int >+ 0U, // MINSSrr >+ 0U, // MINSSrr_Int >+ 0U, // MMX_CVTPD2PIirm >+ 0U, // MMX_CVTPD2PIirr >+ 0U, // MMX_CVTPI2PDirm >+ 0U, // MMX_CVTPI2PDirr >+ 0U, // MMX_CVTPI2PSirm >+ 0U, // MMX_CVTPI2PSirr >+ 0U, // MMX_CVTPS2PIirm >+ 0U, // MMX_CVTPS2PIirr >+ 0U, // MMX_CVTTPD2PIirm >+ 0U, // MMX_CVTTPD2PIirr >+ 0U, // MMX_CVTTPS2PIirm >+ 0U, // MMX_CVTTPS2PIirr >+ 0U, // MMX_EMMS >+ 0U, // MMX_MASKMOVQ >+ 0U, // MMX_MASKMOVQ64 >+ 0U, // MMX_MOVD64from64rr >+ 0U, // MMX_MOVD64grr >+ 0U, // MMX_MOVD64mr >+ 0U, // MMX_MOVD64rm >+ 0U, // MMX_MOVD64rr >+ 0U, // MMX_MOVD64to64rr >+ 0U, // MMX_MOVDQ2Qrr >+ 0U, // MMX_MOVFR642Qrr >+ 0U, // MMX_MOVNTQmr >+ 0U, // MMX_MOVQ2DQrr >+ 0U, // MMX_MOVQ2FR64rr >+ 0U, // MMX_MOVQ64mr >+ 0U, // MMX_MOVQ64rm >+ 0U, // MMX_MOVQ64rr >+ 0U, // MMX_MOVQ64rr_REV >+ 0U, // MMX_PABSBrm64 >+ 0U, // MMX_PABSBrr64 >+ 0U, // MMX_PABSDrm64 >+ 0U, // MMX_PABSDrr64 >+ 0U, // MMX_PABSWrm64 >+ 0U, // MMX_PABSWrr64 >+ 0U, // MMX_PACKSSDWirm >+ 0U, // MMX_PACKSSDWirr >+ 0U, // MMX_PACKSSWBirm >+ 0U, // MMX_PACKSSWBirr >+ 0U, // MMX_PACKUSWBirm >+ 0U, // MMX_PACKUSWBirr >+ 0U, // MMX_PADDBirm >+ 0U, // MMX_PADDBirr >+ 0U, // MMX_PADDDirm >+ 0U, // MMX_PADDDirr >+ 0U, // MMX_PADDQirm >+ 0U, // MMX_PADDQirr >+ 0U, // MMX_PADDSBirm >+ 0U, // MMX_PADDSBirr >+ 0U, // MMX_PADDSWirm >+ 0U, // MMX_PADDSWirr >+ 0U, // MMX_PADDUSBirm >+ 0U, // MMX_PADDUSBirr >+ 0U, // MMX_PADDUSWirm >+ 0U, // MMX_PADDUSWirr >+ 0U, // MMX_PADDWirm >+ 0U, // MMX_PADDWirr >+ 0U, // MMX_PALIGNR64irm >+ 0U, // MMX_PALIGNR64irr >+ 0U, // MMX_PANDNirm >+ 0U, // MMX_PANDNirr >+ 0U, // MMX_PANDirm >+ 0U, // MMX_PANDirr >+ 0U, // MMX_PAVGBirm >+ 0U, // MMX_PAVGBirr >+ 0U, // MMX_PAVGWirm >+ 0U, // MMX_PAVGWirr >+ 0U, // MMX_PCMPEQBirm >+ 0U, // MMX_PCMPEQBirr >+ 0U, // MMX_PCMPEQDirm >+ 0U, // MMX_PCMPEQDirr >+ 0U, // MMX_PCMPEQWirm >+ 0U, // MMX_PCMPEQWirr >+ 0U, // MMX_PCMPGTBirm >+ 0U, // MMX_PCMPGTBirr >+ 0U, // MMX_PCMPGTDirm >+ 0U, // MMX_PCMPGTDirr >+ 0U, // MMX_PCMPGTWirm >+ 0U, // MMX_PCMPGTWirr >+ 0U, // MMX_PEXTRWirri >+ 0U, // MMX_PHADDSWrm64 >+ 0U, // MMX_PHADDSWrr64 >+ 0U, // MMX_PHADDWrm64 >+ 0U, // MMX_PHADDWrr64 >+ 0U, // MMX_PHADDrm64 >+ 0U, // MMX_PHADDrr64 >+ 0U, // MMX_PHSUBDrm64 >+ 0U, // MMX_PHSUBDrr64 >+ 0U, // MMX_PHSUBSWrm64 >+ 0U, // MMX_PHSUBSWrr64 >+ 0U, // MMX_PHSUBWrm64 >+ 0U, // MMX_PHSUBWrr64 >+ 0U, // MMX_PINSRWirmi >+ 0U, // MMX_PINSRWirri >+ 0U, // MMX_PMADDUBSWrm64 >+ 0U, // MMX_PMADDUBSWrr64 >+ 0U, // MMX_PMADDWDirm >+ 0U, // MMX_PMADDWDirr >+ 0U, // MMX_PMAXSWirm >+ 0U, // MMX_PMAXSWirr >+ 0U, // MMX_PMAXUBirm >+ 0U, // MMX_PMAXUBirr >+ 0U, // MMX_PMINSWirm >+ 0U, // MMX_PMINSWirr >+ 0U, // MMX_PMINUBirm >+ 0U, // MMX_PMINUBirr >+ 0U, // MMX_PMOVMSKBrr >+ 0U, // MMX_PMULHRSWrm64 >+ 0U, // MMX_PMULHRSWrr64 >+ 0U, // MMX_PMULHUWirm >+ 0U, // MMX_PMULHUWirr >+ 0U, // MMX_PMULHWirm >+ 0U, // MMX_PMULHWirr >+ 0U, // MMX_PMULLWirm >+ 0U, // MMX_PMULLWirr >+ 0U, // MMX_PMULUDQirm >+ 0U, // MMX_PMULUDQirr >+ 0U, // MMX_PORirm >+ 0U, // MMX_PORirr >+ 0U, // MMX_PSADBWirm >+ 0U, // MMX_PSADBWirr >+ 0U, // MMX_PSHUFBrm64 >+ 0U, // MMX_PSHUFBrr64 >+ 0U, // MMX_PSHUFWmi >+ 0U, // MMX_PSHUFWri >+ 0U, // MMX_PSIGNBrm64 >+ 0U, // MMX_PSIGNBrr64 >+ 0U, // MMX_PSIGNDrm64 >+ 0U, // MMX_PSIGNDrr64 >+ 0U, // MMX_PSIGNWrm64 >+ 0U, // MMX_PSIGNWrr64 >+ 0U, // MMX_PSLLDri >+ 0U, // MMX_PSLLDrm >+ 0U, // MMX_PSLLDrr >+ 0U, // MMX_PSLLQri >+ 0U, // MMX_PSLLQrm >+ 0U, // MMX_PSLLQrr >+ 0U, // MMX_PSLLWri >+ 0U, // MMX_PSLLWrm >+ 0U, // MMX_PSLLWrr >+ 0U, // MMX_PSRADri >+ 0U, // MMX_PSRADrm >+ 0U, // MMX_PSRADrr >+ 0U, // MMX_PSRAWri >+ 0U, // MMX_PSRAWrm >+ 0U, // MMX_PSRAWrr >+ 0U, // MMX_PSRLDri >+ 0U, // MMX_PSRLDrm >+ 0U, // MMX_PSRLDrr >+ 0U, // MMX_PSRLQri >+ 0U, // MMX_PSRLQrm >+ 0U, // MMX_PSRLQrr >+ 0U, // MMX_PSRLWri >+ 0U, // MMX_PSRLWrm >+ 0U, // MMX_PSRLWrr >+ 0U, // MMX_PSUBBirm >+ 0U, // MMX_PSUBBirr >+ 0U, // MMX_PSUBDirm >+ 0U, // MMX_PSUBDirr >+ 0U, // MMX_PSUBQirm >+ 0U, // MMX_PSUBQirr >+ 0U, // MMX_PSUBSBirm >+ 0U, // MMX_PSUBSBirr >+ 0U, // MMX_PSUBSWirm >+ 0U, // MMX_PSUBSWirr >+ 0U, // MMX_PSUBUSBirm >+ 0U, // MMX_PSUBUSBirr >+ 0U, // MMX_PSUBUSWirm >+ 0U, // MMX_PSUBUSWirr >+ 0U, // MMX_PSUBWirm >+ 0U, // MMX_PSUBWirr >+ 0U, // MMX_PUNPCKHBWirm >+ 0U, // MMX_PUNPCKHBWirr >+ 0U, // MMX_PUNPCKHDQirm >+ 0U, // MMX_PUNPCKHDQirr >+ 0U, // MMX_PUNPCKHWDirm >+ 0U, // MMX_PUNPCKHWDirr >+ 0U, // MMX_PUNPCKLBWirm >+ 0U, // MMX_PUNPCKLBWirr >+ 0U, // MMX_PUNPCKLDQirm >+ 0U, // MMX_PUNPCKLDQirr >+ 0U, // MMX_PUNPCKLWDirm >+ 0U, // MMX_PUNPCKLWDirr >+ 0U, // MMX_PXORirm >+ 0U, // MMX_PXORirr >+ 0U, // MONITOR >+ 0U, // MONITORrrr >+ 0U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 0U, // MOV16ao16 >+ 0U, // MOV16ao16_16 >+ 0U, // MOV16mi >+ 0U, // MOV16mr >+ 0U, // MOV16ms >+ 0U, // MOV16o16a >+ 0U, // MOV16o16a_16 >+ 0U, // MOV16ri >+ 0U, // MOV16ri_alt >+ 0U, // MOV16rm >+ 0U, // MOV16rr >+ 0U, // MOV16rr_REV >+ 0U, // MOV16rs >+ 0U, // MOV16sm >+ 0U, // MOV16sr >+ 0U, // MOV32ao32 >+ 0U, // MOV32ao32_16 >+ 0U, // MOV32cr >+ 0U, // MOV32dr >+ 0U, // MOV32mi >+ 0U, // MOV32mr >+ 0U, // MOV32ms >+ 0U, // MOV32o32a >+ 0U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 0U, // MOV32rc >+ 0U, // MOV32rd >+ 0U, // MOV32ri >+ 0U, // MOV32ri64 >+ 0U, // MOV32ri_alt >+ 0U, // MOV32rm >+ 0U, // MOV32rr >+ 0U, // MOV32rr_REV >+ 0U, // MOV32rs >+ 0U, // MOV32sm >+ 0U, // MOV32sr >+ 0U, // MOV64ao16 >+ 0U, // MOV64ao32 >+ 0U, // MOV64ao64 >+ 0U, // MOV64ao8 >+ 0U, // MOV64cr >+ 0U, // MOV64dr >+ 0U, // MOV64mi32 >+ 0U, // MOV64mr >+ 0U, // MOV64ms >+ 0U, // MOV64o16a >+ 0U, // MOV64o32a >+ 0U, // MOV64o64a >+ 0U, // MOV64o8a >+ 0U, // MOV64rc >+ 0U, // MOV64rd >+ 0U, // MOV64ri >+ 0U, // MOV64ri32 >+ 0U, // MOV64rm >+ 0U, // MOV64rr >+ 0U, // MOV64rr_REV >+ 0U, // MOV64rs >+ 0U, // MOV64sm >+ 0U, // MOV64sr >+ 0U, // MOV64toPQIrr >+ 0U, // MOV64toSDrm >+ 0U, // MOV64toSDrr >+ 0U, // MOV8ao8 >+ 0U, // MOV8ao8_16 >+ 0U, // MOV8mi >+ 0U, // MOV8mr >+ 1U, // MOV8mr_NOREX >+ 0U, // MOV8o8a >+ 0U, // MOV8o8a_16 >+ 0U, // MOV8ri >+ 0U, // MOV8ri_alt >+ 0U, // MOV8rm >+ 0U, // MOV8rm_NOREX >+ 0U, // MOV8rr >+ 16U, // MOV8rr_NOREX >+ 0U, // MOV8rr_REV >+ 0U, // MOVAPDmr >+ 0U, // MOVAPDrm >+ 0U, // MOVAPDrr >+ 0U, // MOVAPDrr_REV >+ 0U, // MOVAPSmr >+ 0U, // MOVAPSrm >+ 0U, // MOVAPSrr >+ 0U, // MOVAPSrr_REV >+ 0U, // MOVBE16mr >+ 0U, // MOVBE16rm >+ 0U, // MOVBE32mr >+ 0U, // MOVBE32rm >+ 0U, // MOVBE64mr >+ 0U, // MOVBE64rm >+ 0U, // MOVDDUPrm >+ 0U, // MOVDDUPrr >+ 0U, // MOVDI2PDIrm >+ 0U, // MOVDI2PDIrr >+ 0U, // MOVDI2SSrm >+ 0U, // MOVDI2SSrr >+ 0U, // MOVDQAmr >+ 0U, // MOVDQArm >+ 0U, // MOVDQArr >+ 0U, // MOVDQArr_REV >+ 0U, // MOVDQUmr >+ 0U, // MOVDQUrm >+ 0U, // MOVDQUrr >+ 0U, // MOVDQUrr_REV >+ 0U, // MOVHLPSrr >+ 0U, // MOVHPDmr >+ 0U, // MOVHPDrm >+ 0U, // MOVHPSmr >+ 0U, // MOVHPSrm >+ 0U, // MOVLHPSrr >+ 0U, // MOVLPDmr >+ 0U, // MOVLPDrm >+ 0U, // MOVLPSmr >+ 0U, // MOVLPSrm >+ 0U, // MOVMSKPDrr >+ 0U, // MOVMSKPSrr >+ 0U, // MOVNTDQArm >+ 0U, // MOVNTDQmr >+ 0U, // MOVNTI_64mr >+ 0U, // MOVNTImr >+ 0U, // MOVNTPDmr >+ 0U, // MOVNTPSmr >+ 0U, // MOVNTSD >+ 0U, // MOVNTSS >+ 0U, // MOVPC32r >+ 0U, // MOVPDI2DImr >+ 0U, // MOVPDI2DIrr >+ 0U, // MOVPQI2QImr >+ 0U, // MOVPQI2QIrr >+ 0U, // MOVPQIto64rr >+ 0U, // MOVQI2PQIrm >+ 0U, // MOVSB >+ 0U, // MOVSDmr >+ 0U, // MOVSDrm >+ 0U, // MOVSDrr >+ 0U, // MOVSDrr_REV >+ 0U, // MOVSDto64mr >+ 0U, // MOVSDto64rr >+ 0U, // MOVSHDUPrm >+ 0U, // MOVSHDUPrr >+ 0U, // MOVSL >+ 0U, // MOVSLDUPrm >+ 0U, // MOVSLDUPrr >+ 0U, // MOVSQ >+ 0U, // MOVSS2DImr >+ 0U, // MOVSS2DIrr >+ 0U, // MOVSSmr >+ 0U, // MOVSSrm >+ 0U, // MOVSSrr >+ 0U, // MOVSSrr_REV >+ 0U, // MOVSW >+ 0U, // MOVSX16rm8 >+ 0U, // MOVSX16rr8 >+ 0U, // MOVSX32rm16 >+ 0U, // MOVSX32rm8 >+ 0U, // MOVSX32rr16 >+ 0U, // MOVSX32rr8 >+ 0U, // MOVSX64_NOREXrr32 >+ 0U, // MOVSX64rm16 >+ 0U, // MOVSX64rm32 >+ 0U, // MOVSX64rm8 >+ 0U, // MOVSX64rr16 >+ 0U, // MOVSX64rr32 >+ 0U, // MOVSX64rr8 >+ 0U, // MOVUPDmr >+ 0U, // MOVUPDrm >+ 0U, // MOVUPDrr >+ 0U, // MOVUPDrr_REV >+ 0U, // MOVUPSmr >+ 0U, // MOVUPSrm >+ 0U, // MOVUPSrr >+ 0U, // MOVUPSrr_REV >+ 0U, // MOVZPQILo2PQIrm >+ 0U, // MOVZPQILo2PQIrr >+ 0U, // MOVZQI2PQIrm >+ 0U, // MOVZQI2PQIrr >+ 0U, // MOVZX16rm8 >+ 0U, // MOVZX16rr8 >+ 0U, // MOVZX32_NOREXrm8 >+ 0U, // MOVZX32_NOREXrr8 >+ 0U, // MOVZX32rm16 >+ 0U, // MOVZX32rm8 >+ 0U, // MOVZX32rr16 >+ 0U, // MOVZX32rr8 >+ 0U, // MOVZX64rm16_Q >+ 0U, // MOVZX64rm8_Q >+ 0U, // MOVZX64rr16_Q >+ 0U, // MOVZX64rr8_Q >+ 0U, // MPSADBWrmi >+ 0U, // MPSADBWrri >+ 0U, // MUL16m >+ 0U, // MUL16r >+ 0U, // MUL32m >+ 0U, // MUL32r >+ 0U, // MUL64m >+ 0U, // MUL64r >+ 0U, // MUL8m >+ 0U, // MUL8r >+ 0U, // MULPDrm >+ 0U, // MULPDrr >+ 0U, // MULPSrm >+ 0U, // MULPSrr >+ 0U, // MULSDrm >+ 0U, // MULSDrm_Int >+ 0U, // MULSDrr >+ 0U, // MULSDrr_Int >+ 0U, // MULSSrm >+ 0U, // MULSSrm_Int >+ 0U, // MULSSrr >+ 0U, // MULSSrr_Int >+ 4U, // MULX32rm >+ 0U, // MULX32rr >+ 4U, // MULX64rm >+ 0U, // MULX64rr >+ 0U, // MUL_F32m >+ 0U, // MUL_F64m >+ 0U, // MUL_FI16m >+ 0U, // MUL_FI32m >+ 0U, // MUL_FPrST0 >+ 0U, // MUL_FST0r >+ 0U, // MUL_Fp32 >+ 0U, // MUL_Fp32m >+ 0U, // MUL_Fp64 >+ 0U, // MUL_Fp64m >+ 0U, // MUL_Fp64m32 >+ 0U, // MUL_Fp80 >+ 0U, // MUL_Fp80m32 >+ 0U, // MUL_Fp80m64 >+ 0U, // MUL_FpI16m32 >+ 0U, // MUL_FpI16m64 >+ 0U, // MUL_FpI16m80 >+ 0U, // MUL_FpI32m32 >+ 0U, // MUL_FpI32m64 >+ 0U, // MUL_FpI32m80 >+ 0U, // MUL_FrST0 >+ 0U, // MWAITrr >+ 0U, // NEG16m >+ 0U, // NEG16r >+ 0U, // NEG32m >+ 0U, // NEG32r >+ 0U, // NEG64m >+ 0U, // NEG64r >+ 0U, // NEG8m >+ 0U, // NEG8r >+ 0U, // NOOP >+ 0U, // NOOP18_16m4 >+ 0U, // NOOP18_16m5 >+ 0U, // NOOP18_16m6 >+ 0U, // NOOP18_16m7 >+ 0U, // NOOP18_16r4 >+ 0U, // NOOP18_16r5 >+ 0U, // NOOP18_16r6 >+ 0U, // NOOP18_16r7 >+ 0U, // NOOP18_m4 >+ 0U, // NOOP18_m5 >+ 0U, // NOOP18_m6 >+ 0U, // NOOP18_m7 >+ 0U, // NOOP18_r4 >+ 0U, // NOOP18_r5 >+ 0U, // NOOP18_r6 >+ 0U, // NOOP18_r7 >+ 0U, // NOOP19rr >+ 0U, // NOOPL >+ 0U, // NOOPL_19 >+ 0U, // NOOPL_1a >+ 0U, // NOOPL_1b >+ 0U, // NOOPL_1c >+ 0U, // NOOPL_1d >+ 0U, // NOOPL_1e >+ 0U, // NOOPW >+ 0U, // NOOPW_19 >+ 0U, // NOOPW_1a >+ 0U, // NOOPW_1b >+ 0U, // NOOPW_1c >+ 0U, // NOOPW_1d >+ 0U, // NOOPW_1e >+ 0U, // NOT16m >+ 0U, // NOT16r >+ 0U, // NOT32m >+ 0U, // NOT32r >+ 0U, // NOT64m >+ 0U, // NOT64r >+ 0U, // NOT8m >+ 0U, // NOT8r >+ 0U, // OR16i16 >+ 0U, // OR16mi >+ 0U, // OR16mi8 >+ 0U, // OR16mr >+ 0U, // OR16ri >+ 0U, // OR16ri8 >+ 0U, // OR16rm >+ 0U, // OR16rr >+ 0U, // OR16rr_REV >+ 0U, // OR32i32 >+ 0U, // OR32mi >+ 0U, // OR32mi8 >+ 0U, // OR32mr >+ 0U, // OR32mrLocked >+ 0U, // OR32ri >+ 0U, // OR32ri8 >+ 0U, // OR32rm >+ 0U, // OR32rr >+ 0U, // OR32rr_REV >+ 0U, // OR64i32 >+ 0U, // OR64mi32 >+ 0U, // OR64mi8 >+ 0U, // OR64mr >+ 0U, // OR64ri32 >+ 0U, // OR64ri8 >+ 0U, // OR64rm >+ 0U, // OR64rr >+ 0U, // OR64rr_REV >+ 0U, // OR8i8 >+ 0U, // OR8mi >+ 0U, // OR8mr >+ 0U, // OR8ri >+ 0U, // OR8ri8 >+ 0U, // OR8rm >+ 0U, // OR8rr >+ 0U, // OR8rr_REV >+ 0U, // ORPDrm >+ 0U, // ORPDrr >+ 0U, // ORPSrm >+ 0U, // ORPSrr >+ 0U, // OUT16ir >+ 0U, // OUT16rr >+ 0U, // OUT32ir >+ 0U, // OUT32rr >+ 0U, // OUT8ir >+ 0U, // OUT8rr >+ 0U, // OUTSB >+ 0U, // OUTSL >+ 0U, // OUTSW >+ 0U, // PABSBrm128 >+ 0U, // PABSBrr128 >+ 0U, // PABSDrm128 >+ 0U, // PABSDrr128 >+ 0U, // PABSWrm128 >+ 0U, // PABSWrr128 >+ 0U, // PACKSSDWrm >+ 0U, // PACKSSDWrr >+ 0U, // PACKSSWBrm >+ 0U, // PACKSSWBrr >+ 0U, // PACKUSDWrm >+ 0U, // PACKUSDWrr >+ 0U, // PACKUSWBrm >+ 0U, // PACKUSWBrr >+ 0U, // PADDBrm >+ 0U, // PADDBrr >+ 0U, // PADDDrm >+ 0U, // PADDDrr >+ 0U, // PADDQrm >+ 0U, // PADDQrr >+ 0U, // PADDSBrm >+ 0U, // PADDSBrr >+ 0U, // PADDSWrm >+ 0U, // PADDSWrr >+ 0U, // PADDUSBrm >+ 0U, // PADDUSBrr >+ 0U, // PADDUSWrm >+ 0U, // PADDUSWrr >+ 0U, // PADDWrm >+ 0U, // PADDWrr >+ 0U, // PALIGNR128rm >+ 0U, // PALIGNR128rr >+ 0U, // PANDNrm >+ 0U, // PANDNrr >+ 0U, // PANDrm >+ 0U, // PANDrr >+ 0U, // PAUSE >+ 0U, // PAVGBrm >+ 0U, // PAVGBrr >+ 0U, // PAVGUSBrm >+ 0U, // PAVGUSBrr >+ 0U, // PAVGWrm >+ 0U, // PAVGWrr >+ 0U, // PBLENDVBrm0 >+ 0U, // PBLENDVBrr0 >+ 0U, // PBLENDWrmi >+ 0U, // PBLENDWrri >+ 0U, // PCLMULQDQrm >+ 0U, // PCLMULQDQrr >+ 0U, // PCMPEQBrm >+ 0U, // PCMPEQBrr >+ 0U, // PCMPEQDrm >+ 0U, // PCMPEQDrr >+ 0U, // PCMPEQQrm >+ 0U, // PCMPEQQrr >+ 0U, // PCMPEQWrm >+ 0U, // PCMPEQWrr >+ 0U, // PCMPESTRIMEM >+ 0U, // PCMPESTRIREG >+ 0U, // PCMPESTRIrm >+ 0U, // PCMPESTRIrr >+ 0U, // PCMPESTRM128MEM >+ 0U, // PCMPESTRM128REG >+ 0U, // PCMPESTRM128rm >+ 0U, // PCMPESTRM128rr >+ 0U, // PCMPGTBrm >+ 0U, // PCMPGTBrr >+ 0U, // PCMPGTDrm >+ 0U, // PCMPGTDrr >+ 0U, // PCMPGTQrm >+ 0U, // PCMPGTQrr >+ 0U, // PCMPGTWrm >+ 0U, // PCMPGTWrr >+ 0U, // PCMPISTRIMEM >+ 0U, // PCMPISTRIREG >+ 0U, // PCMPISTRIrm >+ 0U, // PCMPISTRIrr >+ 0U, // PCMPISTRM128MEM >+ 0U, // PCMPISTRM128REG >+ 0U, // PCMPISTRM128rm >+ 0U, // PCMPISTRM128rr >+ 4U, // PDEP32rm >+ 0U, // PDEP32rr >+ 4U, // PDEP64rm >+ 0U, // PDEP64rr >+ 4U, // PEXT32rm >+ 0U, // PEXT32rr >+ 4U, // PEXT64rm >+ 0U, // PEXT64rr >+ 1U, // PEXTRBmr >+ 0U, // PEXTRBrr >+ 1U, // PEXTRDmr >+ 0U, // PEXTRDrr >+ 1U, // PEXTRQmr >+ 0U, // PEXTRQrr >+ 1U, // PEXTRWmr >+ 0U, // PEXTRWri >+ 0U, // PEXTRWrr_REV >+ 0U, // PF2IDrm >+ 0U, // PF2IDrr >+ 0U, // PF2IWrm >+ 0U, // PF2IWrr >+ 0U, // PFACCrm >+ 0U, // PFACCrr >+ 0U, // PFADDrm >+ 0U, // PFADDrr >+ 0U, // PFCMPEQrm >+ 0U, // PFCMPEQrr >+ 0U, // PFCMPGErm >+ 0U, // PFCMPGErr >+ 0U, // PFCMPGTrm >+ 0U, // PFCMPGTrr >+ 0U, // PFMAXrm >+ 0U, // PFMAXrr >+ 0U, // PFMINrm >+ 0U, // PFMINrr >+ 0U, // PFMULrm >+ 0U, // PFMULrr >+ 0U, // PFNACCrm >+ 0U, // PFNACCrr >+ 0U, // PFPNACCrm >+ 0U, // PFPNACCrr >+ 0U, // PFRCPIT1rm >+ 0U, // PFRCPIT1rr >+ 0U, // PFRCPIT2rm >+ 0U, // PFRCPIT2rr >+ 0U, // PFRCPrm >+ 0U, // PFRCPrr >+ 0U, // PFRSQIT1rm >+ 0U, // PFRSQIT1rr >+ 0U, // PFRSQRTrm >+ 0U, // PFRSQRTrr >+ 0U, // PFSUBRrm >+ 0U, // PFSUBRrr >+ 0U, // PFSUBrm >+ 0U, // PFSUBrr >+ 0U, // PHADDDrm >+ 0U, // PHADDDrr >+ 0U, // PHADDSWrm128 >+ 0U, // PHADDSWrr128 >+ 0U, // PHADDWrm >+ 0U, // PHADDWrr >+ 0U, // PHMINPOSUWrm128 >+ 0U, // PHMINPOSUWrr128 >+ 0U, // PHSUBDrm >+ 0U, // PHSUBDrr >+ 0U, // PHSUBSWrm128 >+ 0U, // PHSUBSWrr128 >+ 0U, // PHSUBWrm >+ 0U, // PHSUBWrr >+ 0U, // PI2FDrm >+ 0U, // PI2FDrr >+ 0U, // PI2FWrm >+ 0U, // PI2FWrr >+ 0U, // PINSRBrm >+ 0U, // PINSRBrr >+ 0U, // PINSRDrm >+ 0U, // PINSRDrr >+ 0U, // PINSRQrm >+ 0U, // PINSRQrr >+ 0U, // PINSRWrmi >+ 0U, // PINSRWrri >+ 0U, // PMADDUBSWrm128 >+ 0U, // PMADDUBSWrr128 >+ 0U, // PMADDWDrm >+ 0U, // PMADDWDrr >+ 0U, // PMAXSBrm >+ 0U, // PMAXSBrr >+ 0U, // PMAXSDrm >+ 0U, // PMAXSDrr >+ 0U, // PMAXSWrm >+ 0U, // PMAXSWrr >+ 0U, // PMAXUBrm >+ 0U, // PMAXUBrr >+ 0U, // PMAXUDrm >+ 0U, // PMAXUDrr >+ 0U, // PMAXUWrm >+ 0U, // PMAXUWrr >+ 0U, // PMINSBrm >+ 0U, // PMINSBrr >+ 0U, // PMINSDrm >+ 0U, // PMINSDrr >+ 0U, // PMINSWrm >+ 0U, // PMINSWrr >+ 0U, // PMINUBrm >+ 0U, // PMINUBrr >+ 0U, // PMINUDrm >+ 0U, // PMINUDrr >+ 0U, // PMINUWrm >+ 0U, // PMINUWrr >+ 0U, // PMOVMSKBrr >+ 0U, // PMOVSXBDrm >+ 0U, // PMOVSXBDrr >+ 0U, // PMOVSXBQrm >+ 0U, // PMOVSXBQrr >+ 0U, // PMOVSXBWrm >+ 0U, // PMOVSXBWrr >+ 0U, // PMOVSXDQrm >+ 0U, // PMOVSXDQrr >+ 0U, // PMOVSXWDrm >+ 0U, // PMOVSXWDrr >+ 0U, // PMOVSXWQrm >+ 0U, // PMOVSXWQrr >+ 0U, // PMOVZXBDrm >+ 0U, // PMOVZXBDrr >+ 0U, // PMOVZXBQrm >+ 0U, // PMOVZXBQrr >+ 0U, // PMOVZXBWrm >+ 0U, // PMOVZXBWrr >+ 0U, // PMOVZXDQrm >+ 0U, // PMOVZXDQrr >+ 0U, // PMOVZXWDrm >+ 0U, // PMOVZXWDrr >+ 0U, // PMOVZXWQrm >+ 0U, // PMOVZXWQrr >+ 0U, // PMULDQrm >+ 0U, // PMULDQrr >+ 0U, // PMULHRSWrm128 >+ 0U, // PMULHRSWrr128 >+ 0U, // PMULHRWrm >+ 0U, // PMULHRWrr >+ 0U, // PMULHUWrm >+ 0U, // PMULHUWrr >+ 0U, // PMULHWrm >+ 0U, // PMULHWrr >+ 0U, // PMULLDrm >+ 0U, // PMULLDrr >+ 0U, // PMULLWrm >+ 0U, // PMULLWrr >+ 0U, // PMULUDQrm >+ 0U, // PMULUDQrr >+ 0U, // POP16r >+ 0U, // POP16rmm >+ 0U, // POP16rmr >+ 0U, // POP32r >+ 0U, // POP32rmm >+ 0U, // POP32rmr >+ 0U, // POP64r >+ 0U, // POP64rmm >+ 0U, // POP64rmr >+ 0U, // POPA16 >+ 0U, // POPA32 >+ 0U, // POPCNT16rm >+ 0U, // POPCNT16rr >+ 0U, // POPCNT32rm >+ 0U, // POPCNT32rr >+ 0U, // POPCNT64rm >+ 0U, // POPCNT64rr >+ 0U, // POPDS16 >+ 0U, // POPDS32 >+ 0U, // POPES16 >+ 0U, // POPES32 >+ 0U, // POPF16 >+ 0U, // POPF32 >+ 0U, // POPF64 >+ 0U, // POPFS16 >+ 0U, // POPFS32 >+ 0U, // POPFS64 >+ 0U, // POPGS16 >+ 0U, // POPGS32 >+ 0U, // POPGS64 >+ 0U, // POPSS16 >+ 0U, // POPSS32 >+ 0U, // PORrm >+ 0U, // PORrr >+ 0U, // PREFETCH >+ 0U, // PREFETCHNTA >+ 0U, // PREFETCHT0 >+ 0U, // PREFETCHT1 >+ 0U, // PREFETCHT2 >+ 0U, // PREFETCHW >+ 0U, // PSADBWrm >+ 0U, // PSADBWrr >+ 0U, // PSHUFBrm >+ 0U, // PSHUFBrr >+ 0U, // PSHUFDmi >+ 0U, // PSHUFDri >+ 0U, // PSHUFHWmi >+ 0U, // PSHUFHWri >+ 0U, // PSHUFLWmi >+ 0U, // PSHUFLWri >+ 0U, // PSIGNBrm >+ 0U, // PSIGNBrr >+ 0U, // PSIGNDrm >+ 0U, // PSIGNDrr >+ 0U, // PSIGNWrm >+ 0U, // PSIGNWrr >+ 0U, // PSLLDQri >+ 0U, // PSLLDri >+ 0U, // PSLLDrm >+ 0U, // PSLLDrr >+ 0U, // PSLLQri >+ 0U, // PSLLQrm >+ 0U, // PSLLQrr >+ 0U, // PSLLWri >+ 0U, // PSLLWrm >+ 0U, // PSLLWrr >+ 0U, // PSRADri >+ 0U, // PSRADrm >+ 0U, // PSRADrr >+ 0U, // PSRAWri >+ 0U, // PSRAWrm >+ 0U, // PSRAWrr >+ 0U, // PSRLDQri >+ 0U, // PSRLDri >+ 0U, // PSRLDrm >+ 0U, // PSRLDrr >+ 0U, // PSRLQri >+ 0U, // PSRLQrm >+ 0U, // PSRLQrr >+ 0U, // PSRLWri >+ 0U, // PSRLWrm >+ 0U, // PSRLWrr >+ 0U, // PSUBBrm >+ 0U, // PSUBBrr >+ 0U, // PSUBDrm >+ 0U, // PSUBDrr >+ 0U, // PSUBQrm >+ 0U, // PSUBQrr >+ 0U, // PSUBSBrm >+ 0U, // PSUBSBrr >+ 0U, // PSUBSWrm >+ 0U, // PSUBSWrr >+ 0U, // PSUBUSBrm >+ 0U, // PSUBUSBrr >+ 0U, // PSUBUSWrm >+ 0U, // PSUBUSWrr >+ 0U, // PSUBWrm >+ 0U, // PSUBWrr >+ 0U, // PSWAPDrm >+ 0U, // PSWAPDrr >+ 0U, // PTESTrm >+ 0U, // PTESTrr >+ 0U, // PUNPCKHBWrm >+ 0U, // PUNPCKHBWrr >+ 0U, // PUNPCKHDQrm >+ 0U, // PUNPCKHDQrr >+ 0U, // PUNPCKHQDQrm >+ 0U, // PUNPCKHQDQrr >+ 0U, // PUNPCKHWDrm >+ 0U, // PUNPCKHWDrr >+ 0U, // PUNPCKLBWrm >+ 0U, // PUNPCKLBWrr >+ 0U, // PUNPCKLDQrm >+ 0U, // PUNPCKLDQrr >+ 0U, // PUNPCKLQDQrm >+ 0U, // PUNPCKLQDQrr >+ 0U, // PUNPCKLWDrm >+ 0U, // PUNPCKLWDrr >+ 0U, // PUSH16i8 >+ 0U, // PUSH16r >+ 0U, // PUSH16rmm >+ 0U, // PUSH16rmr >+ 0U, // PUSH32i8 >+ 0U, // PUSH32r >+ 0U, // PUSH32rmm >+ 0U, // PUSH32rmr >+ 0U, // PUSH64i16 >+ 0U, // PUSH64i32 >+ 0U, // PUSH64i8 >+ 0U, // PUSH64r >+ 0U, // PUSH64rmm >+ 0U, // PUSH64rmr >+ 0U, // PUSHA16 >+ 0U, // PUSHA32 >+ 0U, // PUSHCS16 >+ 0U, // PUSHCS32 >+ 0U, // PUSHDS16 >+ 0U, // PUSHDS32 >+ 0U, // PUSHES16 >+ 0U, // PUSHES32 >+ 0U, // PUSHF16 >+ 0U, // PUSHF32 >+ 0U, // PUSHF64 >+ 0U, // PUSHFS16 >+ 0U, // PUSHFS32 >+ 0U, // PUSHFS64 >+ 0U, // PUSHGS16 >+ 0U, // PUSHGS32 >+ 0U, // PUSHGS64 >+ 0U, // PUSHSS16 >+ 0U, // PUSHSS32 >+ 0U, // PUSHi16 >+ 0U, // PUSHi32 >+ 0U, // PXORrm >+ 0U, // PXORrr >+ 0U, // RCL16m1 >+ 0U, // RCL16mCL >+ 0U, // RCL16mi >+ 0U, // RCL16r1 >+ 0U, // RCL16rCL >+ 0U, // RCL16ri >+ 0U, // RCL32m1 >+ 0U, // RCL32mCL >+ 0U, // RCL32mi >+ 0U, // RCL32r1 >+ 0U, // RCL32rCL >+ 0U, // RCL32ri >+ 0U, // RCL64m1 >+ 0U, // RCL64mCL >+ 0U, // RCL64mi >+ 0U, // RCL64r1 >+ 0U, // RCL64rCL >+ 0U, // RCL64ri >+ 0U, // RCL8m1 >+ 0U, // RCL8mCL >+ 0U, // RCL8mi >+ 0U, // RCL8r1 >+ 0U, // RCL8rCL >+ 0U, // RCL8ri >+ 0U, // RCPPSm >+ 0U, // RCPPSm_Int >+ 0U, // RCPPSr >+ 0U, // RCPPSr_Int >+ 0U, // RCPSSm >+ 0U, // RCPSSm_Int >+ 0U, // RCPSSr >+ 0U, // RCPSSr_Int >+ 0U, // RCR16m1 >+ 0U, // RCR16mCL >+ 0U, // RCR16mi >+ 0U, // RCR16r1 >+ 0U, // RCR16rCL >+ 0U, // RCR16ri >+ 0U, // RCR32m1 >+ 0U, // RCR32mCL >+ 0U, // RCR32mi >+ 0U, // RCR32r1 >+ 0U, // RCR32rCL >+ 0U, // RCR32ri >+ 0U, // RCR64m1 >+ 0U, // RCR64mCL >+ 0U, // RCR64mi >+ 0U, // RCR64r1 >+ 0U, // RCR64rCL >+ 0U, // RCR64ri >+ 0U, // RCR8m1 >+ 0U, // RCR8mCL >+ 0U, // RCR8mi >+ 0U, // RCR8r1 >+ 0U, // RCR8rCL >+ 0U, // RCR8ri >+ 0U, // RDFSBASE >+ 0U, // RDFSBASE64 >+ 0U, // RDGSBASE >+ 0U, // RDGSBASE64 >+ 0U, // RDMSR >+ 0U, // RDPMC >+ 0U, // RDRAND16r >+ 0U, // RDRAND32r >+ 0U, // RDRAND64r >+ 0U, // RDSEED16r >+ 0U, // RDSEED32r >+ 0U, // RDSEED64r >+ 0U, // RDTSC >+ 0U, // RDTSCP >+ 0U, // RELEASE_MOV16mr >+ 0U, // RELEASE_MOV32mr >+ 0U, // RELEASE_MOV64mr >+ 0U, // RELEASE_MOV8mr >+ 0U, // REPNE_PREFIX >+ 0U, // REP_MOVSB_32 >+ 0U, // REP_MOVSB_64 >+ 0U, // REP_MOVSD_32 >+ 0U, // REP_MOVSD_64 >+ 0U, // REP_MOVSQ_64 >+ 0U, // REP_MOVSW_32 >+ 0U, // REP_MOVSW_64 >+ 0U, // REP_PREFIX >+ 0U, // REP_STOSB_32 >+ 0U, // REP_STOSB_64 >+ 0U, // REP_STOSD_32 >+ 0U, // REP_STOSD_64 >+ 0U, // REP_STOSQ_64 >+ 0U, // REP_STOSW_32 >+ 0U, // REP_STOSW_64 >+ 0U, // RETIL >+ 0U, // RETIQ >+ 0U, // RETIW >+ 0U, // RETL >+ 0U, // RETQ >+ 0U, // RETW >+ 0U, // REX64_PREFIX >+ 0U, // ROL16m1 >+ 0U, // ROL16mCL >+ 0U, // ROL16mi >+ 0U, // ROL16r1 >+ 0U, // ROL16rCL >+ 0U, // ROL16ri >+ 0U, // ROL32m1 >+ 0U, // ROL32mCL >+ 0U, // ROL32mi >+ 0U, // ROL32r1 >+ 0U, // ROL32rCL >+ 0U, // ROL32ri >+ 0U, // ROL64m1 >+ 0U, // ROL64mCL >+ 0U, // ROL64mi >+ 0U, // ROL64r1 >+ 0U, // ROL64rCL >+ 0U, // ROL64ri >+ 0U, // ROL8m1 >+ 0U, // ROL8mCL >+ 0U, // ROL8mi >+ 0U, // ROL8r1 >+ 0U, // ROL8rCL >+ 0U, // ROL8ri >+ 0U, // ROR16m1 >+ 0U, // ROR16mCL >+ 0U, // ROR16mi >+ 0U, // ROR16r1 >+ 0U, // ROR16rCL >+ 0U, // ROR16ri >+ 0U, // ROR32m1 >+ 0U, // ROR32mCL >+ 0U, // ROR32mi >+ 0U, // ROR32r1 >+ 0U, // ROR32rCL >+ 0U, // ROR32ri >+ 0U, // ROR64m1 >+ 0U, // ROR64mCL >+ 0U, // ROR64mi >+ 0U, // ROR64r1 >+ 0U, // ROR64rCL >+ 0U, // ROR64ri >+ 0U, // ROR8m1 >+ 0U, // ROR8mCL >+ 0U, // ROR8mi >+ 0U, // ROR8r1 >+ 0U, // ROR8rCL >+ 0U, // ROR8ri >+ 0U, // RORX32mi >+ 0U, // RORX32ri >+ 0U, // RORX64mi >+ 0U, // RORX64ri >+ 0U, // ROUNDPDm >+ 0U, // ROUNDPDr >+ 0U, // ROUNDPSm >+ 0U, // ROUNDPSr >+ 0U, // ROUNDSDm >+ 0U, // ROUNDSDr >+ 0U, // ROUNDSDr_Int >+ 0U, // ROUNDSSm >+ 0U, // ROUNDSSr >+ 0U, // ROUNDSSr_Int >+ 0U, // RSM >+ 0U, // RSQRTPSm >+ 0U, // RSQRTPSm_Int >+ 0U, // RSQRTPSr >+ 0U, // RSQRTPSr_Int >+ 0U, // RSQRTSSm >+ 0U, // RSQRTSSm_Int >+ 0U, // RSQRTSSr >+ 0U, // RSQRTSSr_Int >+ 0U, // SAHF >+ 0U, // SAL16m1 >+ 0U, // SAL16mCL >+ 0U, // SAL16mi >+ 0U, // SAL16r1 >+ 0U, // SAL16rCL >+ 0U, // SAL16ri >+ 0U, // SAL32m1 >+ 0U, // SAL32mCL >+ 0U, // SAL32mi >+ 0U, // SAL32r1 >+ 0U, // SAL32rCL >+ 0U, // SAL32ri >+ 0U, // SAL64m1 >+ 0U, // SAL64mCL >+ 0U, // SAL64mi >+ 0U, // SAL64r1 >+ 0U, // SAL64rCL >+ 0U, // SAL64ri >+ 0U, // SAL8m1 >+ 0U, // SAL8mCL >+ 0U, // SAL8mi >+ 0U, // SAL8r1 >+ 0U, // SAL8rCL >+ 0U, // SAL8ri >+ 0U, // SALC >+ 0U, // SAR16m1 >+ 0U, // SAR16mCL >+ 0U, // SAR16mi >+ 0U, // SAR16r1 >+ 0U, // SAR16rCL >+ 0U, // SAR16ri >+ 0U, // SAR32m1 >+ 0U, // SAR32mCL >+ 0U, // SAR32mi >+ 0U, // SAR32r1 >+ 0U, // SAR32rCL >+ 0U, // SAR32ri >+ 0U, // SAR64m1 >+ 0U, // SAR64mCL >+ 0U, // SAR64mi >+ 0U, // SAR64r1 >+ 0U, // SAR64rCL >+ 0U, // SAR64ri >+ 0U, // SAR8m1 >+ 0U, // SAR8mCL >+ 0U, // SAR8mi >+ 0U, // SAR8r1 >+ 0U, // SAR8rCL >+ 0U, // SAR8ri >+ 0U, // SARX32rm >+ 0U, // SARX32rr >+ 0U, // SARX64rm >+ 0U, // SARX64rr >+ 0U, // SBB16i16 >+ 0U, // SBB16mi >+ 0U, // SBB16mi8 >+ 0U, // SBB16mr >+ 0U, // SBB16ri >+ 0U, // SBB16ri8 >+ 0U, // SBB16rm >+ 0U, // SBB16rr >+ 0U, // SBB16rr_REV >+ 0U, // SBB32i32 >+ 0U, // SBB32mi >+ 0U, // SBB32mi8 >+ 0U, // SBB32mr >+ 0U, // SBB32ri >+ 0U, // SBB32ri8 >+ 0U, // SBB32rm >+ 0U, // SBB32rr >+ 0U, // SBB32rr_REV >+ 0U, // SBB64i32 >+ 0U, // SBB64mi32 >+ 0U, // SBB64mi8 >+ 0U, // SBB64mr >+ 0U, // SBB64ri32 >+ 0U, // SBB64ri8 >+ 0U, // SBB64rm >+ 0U, // SBB64rr >+ 0U, // SBB64rr_REV >+ 0U, // SBB8i8 >+ 0U, // SBB8mi >+ 0U, // SBB8mr >+ 0U, // SBB8ri >+ 0U, // SBB8rm >+ 0U, // SBB8rr >+ 0U, // SBB8rr_REV >+ 0U, // SCASB >+ 0U, // SCASL >+ 0U, // SCASQ >+ 0U, // SCASW >+ 0U, // SEG_ALLOCA_32 >+ 0U, // SEG_ALLOCA_64 >+ 0U, // SEH_EndPrologue >+ 0U, // SEH_Epilogue >+ 0U, // SEH_PushFrame >+ 0U, // SEH_PushReg >+ 0U, // SEH_SaveReg >+ 0U, // SEH_SaveXMM >+ 0U, // SEH_SetFrame >+ 0U, // SEH_StackAlloc >+ 0U, // SETAEm >+ 0U, // SETAEr >+ 0U, // SETAm >+ 0U, // SETAr >+ 0U, // SETBEm >+ 0U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 0U, // SETBm >+ 0U, // SETBr >+ 0U, // SETEm >+ 0U, // SETEr >+ 0U, // SETGEm >+ 0U, // SETGEr >+ 0U, // SETGm >+ 0U, // SETGr >+ 0U, // SETLEm >+ 0U, // SETLEr >+ 0U, // SETLm >+ 0U, // SETLr >+ 0U, // SETNEm >+ 0U, // SETNEr >+ 0U, // SETNOm >+ 0U, // SETNOr >+ 0U, // SETNPm >+ 0U, // SETNPr >+ 0U, // SETNSm >+ 0U, // SETNSr >+ 0U, // SETOm >+ 0U, // SETOr >+ 0U, // SETPm >+ 0U, // SETPr >+ 0U, // SETSm >+ 0U, // SETSr >+ 0U, // SFENCE >+ 0U, // SGDT16m >+ 0U, // SGDT32m >+ 0U, // SGDT64m >+ 0U, // SHA1MSG1rm >+ 0U, // SHA1MSG1rr >+ 0U, // SHA1MSG2rm >+ 0U, // SHA1MSG2rr >+ 0U, // SHA1NEXTErm >+ 0U, // SHA1NEXTErr >+ 0U, // SHA1RNDS4rmi >+ 0U, // SHA1RNDS4rri >+ 0U, // SHA256MSG1rm >+ 0U, // SHA256MSG1rr >+ 0U, // SHA256MSG2rm >+ 0U, // SHA256MSG2rr >+ 0U, // SHA256RNDS2rm >+ 0U, // SHA256RNDS2rr >+ 0U, // SHL16m1 >+ 0U, // SHL16mCL >+ 0U, // SHL16mi >+ 0U, // SHL16r1 >+ 0U, // SHL16rCL >+ 0U, // SHL16ri >+ 0U, // SHL32m1 >+ 0U, // SHL32mCL >+ 0U, // SHL32mi >+ 0U, // SHL32r1 >+ 0U, // SHL32rCL >+ 0U, // SHL32ri >+ 0U, // SHL64m1 >+ 0U, // SHL64mCL >+ 0U, // SHL64mi >+ 0U, // SHL64r1 >+ 0U, // SHL64rCL >+ 0U, // SHL64ri >+ 0U, // SHL8m1 >+ 0U, // SHL8mCL >+ 0U, // SHL8mi >+ 0U, // SHL8r1 >+ 0U, // SHL8rCL >+ 0U, // SHL8ri >+ 0U, // SHLD16mrCL >+ 1U, // SHLD16mri8 >+ 0U, // SHLD16rrCL >+ 0U, // SHLD16rri8 >+ 0U, // SHLD32mrCL >+ 1U, // SHLD32mri8 >+ 0U, // SHLD32rrCL >+ 0U, // SHLD32rri8 >+ 0U, // SHLD64mrCL >+ 1U, // SHLD64mri8 >+ 0U, // SHLD64rrCL >+ 0U, // SHLD64rri8 >+ 0U, // SHLX32rm >+ 0U, // SHLX32rr >+ 0U, // SHLX64rm >+ 0U, // SHLX64rr >+ 0U, // SHR16m1 >+ 0U, // SHR16mCL >+ 0U, // SHR16mi >+ 0U, // SHR16r1 >+ 0U, // SHR16rCL >+ 0U, // SHR16ri >+ 0U, // SHR32m1 >+ 0U, // SHR32mCL >+ 0U, // SHR32mi >+ 0U, // SHR32r1 >+ 0U, // SHR32rCL >+ 0U, // SHR32ri >+ 0U, // SHR64m1 >+ 0U, // SHR64mCL >+ 0U, // SHR64mi >+ 0U, // SHR64r1 >+ 0U, // SHR64rCL >+ 0U, // SHR64ri >+ 0U, // SHR8m1 >+ 0U, // SHR8mCL >+ 0U, // SHR8mi >+ 0U, // SHR8r1 >+ 0U, // SHR8rCL >+ 0U, // SHR8ri >+ 0U, // SHRD16mrCL >+ 1U, // SHRD16mri8 >+ 0U, // SHRD16rrCL >+ 0U, // SHRD16rri8 >+ 0U, // SHRD32mrCL >+ 1U, // SHRD32mri8 >+ 0U, // SHRD32rrCL >+ 0U, // SHRD32rri8 >+ 0U, // SHRD64mrCL >+ 1U, // SHRD64mri8 >+ 0U, // SHRD64rrCL >+ 0U, // SHRD64rri8 >+ 0U, // SHRX32rm >+ 0U, // SHRX32rr >+ 0U, // SHRX64rm >+ 0U, // SHRX64rr >+ 0U, // SHUFPDrmi >+ 0U, // SHUFPDrri >+ 0U, // SHUFPSrmi >+ 0U, // SHUFPSrri >+ 0U, // SIDT16m >+ 0U, // SIDT32m >+ 0U, // SIDT64m >+ 0U, // SIN_F >+ 0U, // SIN_Fp32 >+ 0U, // SIN_Fp64 >+ 0U, // SIN_Fp80 >+ 0U, // SKINIT >+ 0U, // SLDT16m >+ 0U, // SLDT16r >+ 0U, // SLDT32r >+ 0U, // SLDT64m >+ 0U, // SLDT64r >+ 0U, // SMSW16m >+ 0U, // SMSW16r >+ 0U, // SMSW32r >+ 0U, // SMSW64r >+ 0U, // SQRTPDm >+ 0U, // SQRTPDr >+ 0U, // SQRTPSm >+ 0U, // SQRTPSr >+ 0U, // SQRTSDm >+ 0U, // SQRTSDm_Int >+ 0U, // SQRTSDr >+ 0U, // SQRTSDr_Int >+ 0U, // SQRTSSm >+ 0U, // SQRTSSm_Int >+ 0U, // SQRTSSr >+ 0U, // SQRTSSr_Int >+ 0U, // SQRT_F >+ 0U, // SQRT_Fp32 >+ 0U, // SQRT_Fp64 >+ 0U, // SQRT_Fp80 >+ 0U, // STAC >+ 0U, // STC >+ 0U, // STD >+ 0U, // STGI >+ 0U, // STI >+ 0U, // STMXCSR >+ 0U, // STOSB >+ 0U, // STOSL >+ 0U, // STOSQ >+ 0U, // STOSW >+ 0U, // STR16r >+ 0U, // STR32r >+ 0U, // STR64r >+ 0U, // STRm >+ 0U, // ST_F32m >+ 0U, // ST_F64m >+ 0U, // ST_FCOMPST0r >+ 0U, // ST_FCOMPST0r_alt >+ 0U, // ST_FCOMST0r >+ 0U, // ST_FP32m >+ 0U, // ST_FP64m >+ 0U, // ST_FP80m >+ 0U, // ST_FPNCEST0r >+ 0U, // ST_FPST0r >+ 0U, // ST_FPST0r_alt >+ 0U, // ST_FPrr >+ 0U, // ST_FXCHST0r >+ 0U, // ST_FXCHST0r_alt >+ 0U, // ST_Fp32m >+ 0U, // ST_Fp64m >+ 0U, // ST_Fp64m32 >+ 0U, // ST_Fp80m32 >+ 0U, // ST_Fp80m64 >+ 0U, // ST_FpP32m >+ 0U, // ST_FpP64m >+ 0U, // ST_FpP64m32 >+ 0U, // ST_FpP80m >+ 0U, // ST_FpP80m32 >+ 0U, // ST_FpP80m64 >+ 0U, // ST_Frr >+ 0U, // SUB16i16 >+ 0U, // SUB16mi >+ 0U, // SUB16mi8 >+ 0U, // SUB16mr >+ 0U, // SUB16ri >+ 0U, // SUB16ri8 >+ 0U, // SUB16rm >+ 0U, // SUB16rr >+ 0U, // SUB16rr_REV >+ 0U, // SUB32i32 >+ 0U, // SUB32mi >+ 0U, // SUB32mi8 >+ 0U, // SUB32mr >+ 0U, // SUB32ri >+ 0U, // SUB32ri8 >+ 0U, // SUB32rm >+ 0U, // SUB32rr >+ 0U, // SUB32rr_REV >+ 0U, // SUB64i32 >+ 0U, // SUB64mi32 >+ 0U, // SUB64mi8 >+ 0U, // SUB64mr >+ 0U, // SUB64ri32 >+ 0U, // SUB64ri8 >+ 0U, // SUB64rm >+ 0U, // SUB64rr >+ 0U, // SUB64rr_REV >+ 0U, // SUB8i8 >+ 0U, // SUB8mi >+ 0U, // SUB8mr >+ 0U, // SUB8ri >+ 0U, // SUB8ri8 >+ 0U, // SUB8rm >+ 0U, // SUB8rr >+ 0U, // SUB8rr_REV >+ 0U, // SUBPDrm >+ 0U, // SUBPDrr >+ 0U, // SUBPSrm >+ 0U, // SUBPSrr >+ 0U, // SUBR_F32m >+ 0U, // SUBR_F64m >+ 0U, // SUBR_FI16m >+ 0U, // SUBR_FI32m >+ 0U, // SUBR_FPrST0 >+ 0U, // SUBR_FST0r >+ 0U, // SUBR_Fp32m >+ 0U, // SUBR_Fp64m >+ 0U, // SUBR_Fp64m32 >+ 0U, // SUBR_Fp80m32 >+ 0U, // SUBR_Fp80m64 >+ 0U, // SUBR_FpI16m32 >+ 0U, // SUBR_FpI16m64 >+ 0U, // SUBR_FpI16m80 >+ 0U, // SUBR_FpI32m32 >+ 0U, // SUBR_FpI32m64 >+ 0U, // SUBR_FpI32m80 >+ 0U, // SUBR_FrST0 >+ 0U, // SUBSDrm >+ 0U, // SUBSDrm_Int >+ 0U, // SUBSDrr >+ 0U, // SUBSDrr_Int >+ 0U, // SUBSSrm >+ 0U, // SUBSSrm_Int >+ 0U, // SUBSSrr >+ 0U, // SUBSSrr_Int >+ 0U, // SUB_F32m >+ 0U, // SUB_F64m >+ 0U, // SUB_FI16m >+ 0U, // SUB_FI32m >+ 0U, // SUB_FPrST0 >+ 0U, // SUB_FST0r >+ 0U, // SUB_Fp32 >+ 0U, // SUB_Fp32m >+ 0U, // SUB_Fp64 >+ 0U, // SUB_Fp64m >+ 0U, // SUB_Fp64m32 >+ 0U, // SUB_Fp80 >+ 0U, // SUB_Fp80m32 >+ 0U, // SUB_Fp80m64 >+ 0U, // SUB_FpI16m32 >+ 0U, // SUB_FpI16m64 >+ 0U, // SUB_FpI16m80 >+ 0U, // SUB_FpI32m32 >+ 0U, // SUB_FpI32m64 >+ 0U, // SUB_FpI32m80 >+ 0U, // SUB_FrST0 >+ 0U, // SWAPGS >+ 0U, // SYSCALL >+ 0U, // SYSENTER >+ 0U, // SYSEXIT >+ 0U, // SYSEXIT64 >+ 0U, // SYSRET >+ 0U, // SYSRET64 >+ 0U, // T1MSKC32rm >+ 0U, // T1MSKC32rr >+ 0U, // T1MSKC64rm >+ 0U, // T1MSKC64rr >+ 0U, // TAILJMPd >+ 0U, // TAILJMPd64 >+ 0U, // TAILJMPm >+ 0U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 0U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 0U, // TEST16i16 >+ 0U, // TEST16mi >+ 0U, // TEST16mi_alt >+ 0U, // TEST16ri >+ 0U, // TEST16ri_alt >+ 0U, // TEST16rm >+ 0U, // TEST16rr >+ 0U, // TEST32i32 >+ 0U, // TEST32mi >+ 0U, // TEST32mi_alt >+ 0U, // TEST32ri >+ 0U, // TEST32ri_alt >+ 0U, // TEST32rm >+ 0U, // TEST32rr >+ 0U, // TEST64i32 >+ 0U, // TEST64mi32 >+ 0U, // TEST64mi32_alt >+ 0U, // TEST64ri32 >+ 0U, // TEST64ri32_alt >+ 0U, // TEST64rm >+ 0U, // TEST64rr >+ 0U, // TEST8i8 >+ 0U, // TEST8mi >+ 0U, // TEST8mi_alt >+ 0U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 0U, // TEST8ri_alt >+ 0U, // TEST8rm >+ 0U, // TEST8rr >+ 0U, // TLSCall_32 >+ 0U, // TLSCall_64 >+ 0U, // TLS_addr32 >+ 0U, // TLS_addr64 >+ 0U, // TLS_base_addr32 >+ 0U, // TLS_base_addr64 >+ 0U, // TRAP >+ 0U, // TST_F >+ 0U, // TST_Fp32 >+ 0U, // TST_Fp64 >+ 0U, // TST_Fp80 >+ 0U, // TZCNT16rm >+ 0U, // TZCNT16rr >+ 0U, // TZCNT32rm >+ 0U, // TZCNT32rr >+ 0U, // TZCNT64rm >+ 0U, // TZCNT64rr >+ 0U, // TZMSK32rm >+ 0U, // TZMSK32rr >+ 0U, // TZMSK64rm >+ 0U, // TZMSK64rr >+ 0U, // UCOMISDrm >+ 0U, // UCOMISDrr >+ 0U, // UCOMISSrm >+ 0U, // UCOMISSrr >+ 0U, // UCOM_FIPr >+ 0U, // UCOM_FIr >+ 0U, // UCOM_FPPr >+ 0U, // UCOM_FPr >+ 0U, // UCOM_FpIr32 >+ 0U, // UCOM_FpIr64 >+ 0U, // UCOM_FpIr80 >+ 0U, // UCOM_Fpr32 >+ 0U, // UCOM_Fpr64 >+ 0U, // UCOM_Fpr80 >+ 0U, // UCOM_Fr >+ 0U, // UD2B >+ 0U, // UNPCKHPDrm >+ 0U, // UNPCKHPDrr >+ 0U, // UNPCKHPSrm >+ 0U, // UNPCKHPSrr >+ 0U, // UNPCKLPDrm >+ 0U, // UNPCKLPDrr >+ 0U, // UNPCKLPSrm >+ 0U, // UNPCKLPSrr >+ 1U, // VAARG_64 >+ 0U, // VADDPDYrm >+ 0U, // VADDPDYrr >+ 0U, // VADDPDZrm >+ 4U, // VADDPDZrmb >+ 2052U, // VADDPDZrmbk >+ 10244U, // VADDPDZrmbkz >+ 3220U, // VADDPDZrmk >+ 4244U, // VADDPDZrmkz >+ 0U, // VADDPDZrr >+ 5268U, // VADDPDZrrk >+ 4244U, // VADDPDZrrkz >+ 0U, // VADDPDrm >+ 0U, // VADDPDrr >+ 0U, // VADDPSYrm >+ 0U, // VADDPSYrr >+ 0U, // VADDPSZrm >+ 4U, // VADDPSZrmb >+ 2052U, // VADDPSZrmbk >+ 10244U, // VADDPSZrmbkz >+ 3220U, // VADDPSZrmk >+ 4244U, // VADDPSZrmkz >+ 0U, // VADDPSZrr >+ 5268U, // VADDPSZrrk >+ 4244U, // VADDPSZrrkz >+ 0U, // VADDPSrm >+ 0U, // VADDPSrr >+ 4U, // VADDSDZrm >+ 0U, // VADDSDZrr >+ 4U, // VADDSDrm >+ 4U, // VADDSDrm_Int >+ 0U, // VADDSDrr >+ 0U, // VADDSDrr_Int >+ 4U, // VADDSSZrm >+ 0U, // VADDSSZrr >+ 4U, // VADDSSrm >+ 4U, // VADDSSrm_Int >+ 0U, // VADDSSrr >+ 0U, // VADDSSrr_Int >+ 0U, // VADDSUBPDYrm >+ 0U, // VADDSUBPDYrr >+ 0U, // VADDSUBPDrm >+ 0U, // VADDSUBPDrr >+ 0U, // VADDSUBPSYrm >+ 0U, // VADDSUBPSYrr >+ 0U, // VADDSUBPSrm >+ 0U, // VADDSUBPSrr >+ 0U, // VAESDECLASTrm >+ 0U, // VAESDECLASTrr >+ 0U, // VAESDECrm >+ 0U, // VAESDECrr >+ 0U, // VAESENCLASTrm >+ 0U, // VAESENCLASTrr >+ 0U, // VAESENCrm >+ 0U, // VAESENCrr >+ 0U, // VAESIMCrm >+ 0U, // VAESIMCrr >+ 0U, // VAESKEYGENASSIST128rm >+ 0U, // VAESKEYGENASSIST128rr >+ 4U, // VALIGNDrmi >+ 4U, // VALIGNDrri >+ 0U, // VALIGNDrrik >+ 4244U, // VALIGNDrrikz >+ 4U, // VALIGNQrmi >+ 4U, // VALIGNQrri >+ 0U, // VALIGNQrrik >+ 4244U, // VALIGNQrrikz >+ 0U, // VANDNPDYrm >+ 0U, // VANDNPDYrr >+ 0U, // VANDNPDrm >+ 0U, // VANDNPDrr >+ 0U, // VANDNPSYrm >+ 0U, // VANDNPSYrr >+ 0U, // VANDNPSrm >+ 0U, // VANDNPSrr >+ 0U, // VANDPDYrm >+ 0U, // VANDPDYrr >+ 0U, // VANDPDrm >+ 0U, // VANDPDrr >+ 0U, // VANDPSYrm >+ 0U, // VANDPSYrr >+ 0U, // VANDPSrm >+ 0U, // VANDPSrr >+ 196U, // VASTART_SAVE_XMM_REGS >+ 3220U, // VBLENDMPDZrm >+ 3220U, // VBLENDMPDZrr >+ 3220U, // VBLENDMPSZrm >+ 3220U, // VBLENDMPSZrr >+ 0U, // VBLENDPDYrmi >+ 4U, // VBLENDPDYrri >+ 4U, // VBLENDPDrmi >+ 4U, // VBLENDPDrri >+ 0U, // VBLENDPSYrmi >+ 4U, // VBLENDPSYrri >+ 4U, // VBLENDPSrmi >+ 4U, // VBLENDPSrri >+ 0U, // VBLENDVPDYrm >+ 4U, // VBLENDVPDYrr >+ 4U, // VBLENDVPDrm >+ 4U, // VBLENDVPDrr >+ 0U, // VBLENDVPSYrm >+ 4U, // VBLENDVPSYrr >+ 4U, // VBLENDVPSrm >+ 4U, // VBLENDVPSrr >+ 0U, // VBROADCASTF128 >+ 0U, // VBROADCASTI128 >+ 269U, // VBROADCASTI32X4krm >+ 0U, // VBROADCASTI32X4rm >+ 269U, // VBROADCASTI64X4krm >+ 0U, // VBROADCASTI64X4rm >+ 0U, // VBROADCASTSDYrm >+ 0U, // VBROADCASTSDYrr >+ 0U, // VBROADCASTSDZrm >+ 0U, // VBROADCASTSDZrr >+ 0U, // VBROADCASTSSYrm >+ 0U, // VBROADCASTSSYrr >+ 0U, // VBROADCASTSSZrm >+ 0U, // VBROADCASTSSZrr >+ 0U, // VBROADCASTSSrm >+ 0U, // VBROADCASTSSrr >+ 1U, // VCMPPDYrmi >+ 0U, // VCMPPDYrmi_alt >+ 1156U, // VCMPPDYrri >+ 4U, // VCMPPDYrri_alt >+ 1U, // VCMPPDZrmi >+ 0U, // VCMPPDZrmi_alt >+ 1156U, // VCMPPDZrri >+ 4U, // VCMPPDZrri_alt >+ 0U, // VCMPPDZrrib >+ 76U, // VCMPPDrmi >+ 4U, // VCMPPDrmi_alt >+ 1156U, // VCMPPDrri >+ 4U, // VCMPPDrri_alt >+ 1U, // VCMPPSYrmi >+ 0U, // VCMPPSYrmi_alt >+ 1156U, // VCMPPSYrri >+ 4U, // VCMPPSYrri_alt >+ 1U, // VCMPPSZrmi >+ 0U, // VCMPPSZrmi_alt >+ 1156U, // VCMPPSZrri >+ 4U, // VCMPPSZrri_alt >+ 0U, // VCMPPSZrrib >+ 76U, // VCMPPSrmi >+ 4U, // VCMPPSrmi_alt >+ 1156U, // VCMPPSrri >+ 4U, // VCMPPSrri_alt >+ 76U, // VCMPSDZrm >+ 4U, // VCMPSDZrmi_alt >+ 1156U, // VCMPSDZrr >+ 4U, // VCMPSDZrri_alt >+ 76U, // VCMPSDrm >+ 4U, // VCMPSDrm_alt >+ 1156U, // VCMPSDrr >+ 4U, // VCMPSDrr_alt >+ 76U, // VCMPSSZrm >+ 4U, // VCMPSSZrmi_alt >+ 1156U, // VCMPSSZrr >+ 4U, // VCMPSSZrri_alt >+ 76U, // VCMPSSrm >+ 4U, // VCMPSSrm_alt >+ 1156U, // VCMPSSrr >+ 4U, // VCMPSSrr_alt >+ 0U, // VCOMISDZrm >+ 0U, // VCOMISDZrr >+ 0U, // VCOMISDrm >+ 0U, // VCOMISDrr >+ 0U, // VCOMISSZrm >+ 0U, // VCOMISSZrr >+ 0U, // VCOMISSrm >+ 0U, // VCOMISSrr >+ 0U, // VCVTDQ2PDYrm >+ 0U, // VCVTDQ2PDYrr >+ 0U, // VCVTDQ2PDZrm >+ 0U, // VCVTDQ2PDZrr >+ 0U, // VCVTDQ2PDrm >+ 0U, // VCVTDQ2PDrr >+ 0U, // VCVTDQ2PSYrm >+ 0U, // VCVTDQ2PSYrr >+ 0U, // VCVTDQ2PSZrm >+ 0U, // VCVTDQ2PSZrr >+ 0U, // VCVTDQ2PSZrrb >+ 0U, // VCVTDQ2PSrm >+ 0U, // VCVTDQ2PSrr >+ 0U, // VCVTPD2DQXrm >+ 0U, // VCVTPD2DQYrm >+ 0U, // VCVTPD2DQYrr >+ 0U, // VCVTPD2DQZrm >+ 0U, // VCVTPD2DQZrr >+ 0U, // VCVTPD2DQZrrb >+ 0U, // VCVTPD2DQrr >+ 0U, // VCVTPD2PSXrm >+ 0U, // VCVTPD2PSYrm >+ 0U, // VCVTPD2PSYrr >+ 0U, // VCVTPD2PSZrm >+ 0U, // VCVTPD2PSZrr >+ 0U, // VCVTPD2PSZrrb >+ 0U, // VCVTPD2PSrr >+ 0U, // VCVTPD2UDQZrm >+ 0U, // VCVTPD2UDQZrr >+ 0U, // VCVTPD2UDQZrrb >+ 0U, // VCVTPH2PSYrm >+ 0U, // VCVTPH2PSYrr >+ 0U, // VCVTPH2PSZrm >+ 0U, // VCVTPH2PSZrr >+ 0U, // VCVTPH2PSrm >+ 0U, // VCVTPH2PSrr >+ 0U, // VCVTPS2DQYrm >+ 0U, // VCVTPS2DQYrr >+ 0U, // VCVTPS2DQZrm >+ 0U, // VCVTPS2DQZrr >+ 0U, // VCVTPS2DQZrrb >+ 0U, // VCVTPS2DQrm >+ 0U, // VCVTPS2DQrr >+ 0U, // VCVTPS2PDYrm >+ 0U, // VCVTPS2PDYrr >+ 0U, // VCVTPS2PDZrm >+ 0U, // VCVTPS2PDZrr >+ 0U, // VCVTPS2PDrm >+ 0U, // VCVTPS2PDrr >+ 1U, // VCVTPS2PHYmr >+ 0U, // VCVTPS2PHYrr >+ 1U, // VCVTPS2PHZmr >+ 0U, // VCVTPS2PHZrr >+ 1U, // VCVTPS2PHmr >+ 0U, // VCVTPS2PHrr >+ 0U, // VCVTPS2UDQZrm >+ 0U, // VCVTPS2UDQZrr >+ 0U, // VCVTPS2UDQZrrb >+ 0U, // VCVTSD2SI64Zrm >+ 0U, // VCVTSD2SI64Zrr >+ 0U, // VCVTSD2SI64rm >+ 0U, // VCVTSD2SI64rr >+ 0U, // VCVTSD2SIZrm >+ 0U, // VCVTSD2SIZrr >+ 0U, // VCVTSD2SIrm >+ 0U, // VCVTSD2SIrr >+ 4U, // VCVTSD2SSZrm >+ 0U, // VCVTSD2SSZrr >+ 4U, // VCVTSD2SSrm >+ 0U, // VCVTSD2SSrr >+ 0U, // VCVTSD2USI64Zrm >+ 0U, // VCVTSD2USI64Zrr >+ 0U, // VCVTSD2USIZrm >+ 0U, // VCVTSD2USIZrr >+ 4U, // VCVTSI2SD64rm >+ 0U, // VCVTSI2SD64rr >+ 4U, // VCVTSI2SDZrm >+ 0U, // VCVTSI2SDZrr >+ 4U, // VCVTSI2SDrm >+ 0U, // VCVTSI2SDrr >+ 4U, // VCVTSI2SS64rm >+ 0U, // VCVTSI2SS64rr >+ 4U, // VCVTSI2SSZrm >+ 0U, // VCVTSI2SSZrr >+ 4U, // VCVTSI2SSrm >+ 0U, // VCVTSI2SSrr >+ 4U, // VCVTSI642SDZrm >+ 0U, // VCVTSI642SDZrr >+ 4U, // VCVTSI642SSZrm >+ 0U, // VCVTSI642SSZrr >+ 4U, // VCVTSS2SDZrm >+ 0U, // VCVTSS2SDZrr >+ 4U, // VCVTSS2SDrm >+ 0U, // VCVTSS2SDrr >+ 0U, // VCVTSS2SI64Zrm >+ 0U, // VCVTSS2SI64Zrr >+ 0U, // VCVTSS2SI64rm >+ 0U, // VCVTSS2SI64rr >+ 0U, // VCVTSS2SIZrm >+ 0U, // VCVTSS2SIZrr >+ 0U, // VCVTSS2SIrm >+ 0U, // VCVTSS2SIrr >+ 0U, // VCVTSS2USI64Zrm >+ 0U, // VCVTSS2USI64Zrr >+ 0U, // VCVTSS2USIZrm >+ 0U, // VCVTSS2USIZrr >+ 0U, // VCVTTPD2DQXrm >+ 0U, // VCVTTPD2DQYrm >+ 0U, // VCVTTPD2DQYrr >+ 0U, // VCVTTPD2DQZrm >+ 0U, // VCVTTPD2DQZrr >+ 0U, // VCVTTPD2DQrr >+ 0U, // VCVTTPD2UDQZrm >+ 0U, // VCVTTPD2UDQZrr >+ 0U, // VCVTTPS2DQYrm >+ 0U, // VCVTTPS2DQYrr >+ 0U, // VCVTTPS2DQZrm >+ 0U, // VCVTTPS2DQZrr >+ 0U, // VCVTTPS2DQrm >+ 0U, // VCVTTPS2DQrr >+ 0U, // VCVTTPS2UDQZrm >+ 0U, // VCVTTPS2UDQZrr >+ 0U, // VCVTTSD2SI64Zrm >+ 0U, // VCVTTSD2SI64Zrr >+ 0U, // VCVTTSD2SI64rm >+ 0U, // VCVTTSD2SI64rr >+ 0U, // VCVTTSD2SIZrm >+ 0U, // VCVTTSD2SIZrr >+ 0U, // VCVTTSD2SIrm >+ 0U, // VCVTTSD2SIrr >+ 0U, // VCVTTSD2USI64Zrm >+ 0U, // VCVTTSD2USI64Zrr >+ 0U, // VCVTTSD2USIZrm >+ 0U, // VCVTTSD2USIZrr >+ 0U, // VCVTTSS2SI64Zrm >+ 0U, // VCVTTSS2SI64Zrr >+ 0U, // VCVTTSS2SI64rm >+ 0U, // VCVTTSS2SI64rr >+ 0U, // VCVTTSS2SIZrm >+ 0U, // VCVTTSS2SIZrr >+ 0U, // VCVTTSS2SIrm >+ 0U, // VCVTTSS2SIrr >+ 0U, // VCVTTSS2USI64Zrm >+ 0U, // VCVTTSS2USI64Zrr >+ 0U, // VCVTTSS2USIZrm >+ 0U, // VCVTTSS2USIZrr >+ 0U, // VCVTUDQ2PDZrm >+ 0U, // VCVTUDQ2PDZrr >+ 0U, // VCVTUDQ2PSZrm >+ 0U, // VCVTUDQ2PSZrr >+ 0U, // VCVTUDQ2PSZrrb >+ 4U, // VCVTUSI2SDZrm >+ 0U, // VCVTUSI2SDZrr >+ 4U, // VCVTUSI2SSZrm >+ 0U, // VCVTUSI2SSZrr >+ 4U, // VCVTUSI642SDZrm >+ 0U, // VCVTUSI642SDZrr >+ 4U, // VCVTUSI642SSZrm >+ 0U, // VCVTUSI642SSZrr >+ 0U, // VDIVPDYrm >+ 0U, // VDIVPDYrr >+ 0U, // VDIVPDZrm >+ 4U, // VDIVPDZrmb >+ 2052U, // VDIVPDZrmbk >+ 10244U, // VDIVPDZrmbkz >+ 3220U, // VDIVPDZrmk >+ 4244U, // VDIVPDZrmkz >+ 0U, // VDIVPDZrr >+ 5268U, // VDIVPDZrrk >+ 4244U, // VDIVPDZrrkz >+ 0U, // VDIVPDrm >+ 0U, // VDIVPDrr >+ 0U, // VDIVPSYrm >+ 0U, // VDIVPSYrr >+ 0U, // VDIVPSZrm >+ 4U, // VDIVPSZrmb >+ 2052U, // VDIVPSZrmbk >+ 10244U, // VDIVPSZrmbkz >+ 3220U, // VDIVPSZrmk >+ 4244U, // VDIVPSZrmkz >+ 0U, // VDIVPSZrr >+ 5268U, // VDIVPSZrrk >+ 4244U, // VDIVPSZrrkz >+ 0U, // VDIVPSrm >+ 0U, // VDIVPSrr >+ 4U, // VDIVSDZrm >+ 0U, // VDIVSDZrr >+ 4U, // VDIVSDrm >+ 4U, // VDIVSDrm_Int >+ 0U, // VDIVSDrr >+ 0U, // VDIVSDrr_Int >+ 4U, // VDIVSSZrm >+ 0U, // VDIVSSZrr >+ 4U, // VDIVSSrm >+ 4U, // VDIVSSrm_Int >+ 0U, // VDIVSSrr >+ 0U, // VDIVSSrr_Int >+ 4U, // VDPPDrmi >+ 4U, // VDPPDrri >+ 0U, // VDPPSYrmi >+ 4U, // VDPPSYrri >+ 4U, // VDPPSrmi >+ 4U, // VDPPSrri >+ 0U, // VERRm >+ 0U, // VERRr >+ 0U, // VERWm >+ 0U, // VERWr >+ 1U, // VEXTRACTF128mr >+ 0U, // VEXTRACTF128rr >+ 1U, // VEXTRACTF32x4mr >+ 0U, // VEXTRACTF32x4rr >+ 1U, // VEXTRACTF64x4mr >+ 0U, // VEXTRACTF64x4rr >+ 1U, // VEXTRACTI128mr >+ 0U, // VEXTRACTI128rr >+ 1U, // VEXTRACTI32x4mr >+ 0U, // VEXTRACTI32x4rr >+ 1U, // VEXTRACTI64x4mr >+ 0U, // VEXTRACTI64x4rr >+ 0U, // VEXTRACTPSmr >+ 0U, // VEXTRACTPSrr >+ 0U, // VEXTRACTPSzmr >+ 0U, // VEXTRACTPSzrr >+ 0U, // VFMADD132PDZm >+ 4U, // VFMADD132PDZmb >+ 0U, // VFMADD132PSZm >+ 4U, // VFMADD132PSZmb >+ 0U, // VFMADD213PDZm >+ 4U, // VFMADD213PDZmb >+ 0U, // VFMADD213PDZr >+ 345U, // VFMADD213PDZrk >+ 281U, // VFMADD213PDZrkz >+ 0U, // VFMADD213PSZm >+ 4U, // VFMADD213PSZmb >+ 0U, // VFMADD213PSZr >+ 345U, // VFMADD213PSZrk >+ 281U, // VFMADD213PSZrkz >+ 4U, // VFMADDPD4mr >+ 0U, // VFMADDPD4mrY >+ 4U, // VFMADDPD4rm >+ 4U, // VFMADDPD4rmY >+ 4U, // VFMADDPD4rr >+ 4U, // VFMADDPD4rrY >+ 4U, // VFMADDPD4rrY_REV >+ 4U, // VFMADDPD4rr_REV >+ 0U, // VFMADDPDr132m >+ 0U, // VFMADDPDr132mY >+ 0U, // VFMADDPDr132r >+ 0U, // VFMADDPDr132rY >+ 0U, // VFMADDPDr213m >+ 0U, // VFMADDPDr213mY >+ 0U, // VFMADDPDr213r >+ 0U, // VFMADDPDr213rY >+ 0U, // VFMADDPDr231m >+ 0U, // VFMADDPDr231mY >+ 0U, // VFMADDPDr231r >+ 0U, // VFMADDPDr231rY >+ 4U, // VFMADDPS4mr >+ 0U, // VFMADDPS4mrY >+ 4U, // VFMADDPS4rm >+ 4U, // VFMADDPS4rmY >+ 4U, // VFMADDPS4rr >+ 4U, // VFMADDPS4rrY >+ 4U, // VFMADDPS4rrY_REV >+ 4U, // VFMADDPS4rr_REV >+ 0U, // VFMADDPSr132m >+ 0U, // VFMADDPSr132mY >+ 0U, // VFMADDPSr132r >+ 0U, // VFMADDPSr132rY >+ 0U, // VFMADDPSr213m >+ 0U, // VFMADDPSr213mY >+ 0U, // VFMADDPSr213r >+ 0U, // VFMADDPSr213rY >+ 0U, // VFMADDPSr231m >+ 0U, // VFMADDPSr231mY >+ 0U, // VFMADDPSr231r >+ 0U, // VFMADDPSr231rY >+ 4U, // VFMADDSD4mr >+ 4U, // VFMADDSD4mr_Int >+ 1156U, // VFMADDSD4rm >+ 1156U, // VFMADDSD4rm_Int >+ 4U, // VFMADDSD4rr >+ 4U, // VFMADDSD4rr_Int >+ 4U, // VFMADDSD4rr_REV >+ 0U, // VFMADDSDZm >+ 0U, // VFMADDSDZr >+ 4U, // VFMADDSDr132m >+ 0U, // VFMADDSDr132r >+ 4U, // VFMADDSDr213m >+ 0U, // VFMADDSDr213r >+ 4U, // VFMADDSDr231m >+ 0U, // VFMADDSDr231r >+ 4U, // VFMADDSS4mr >+ 4U, // VFMADDSS4mr_Int >+ 1156U, // VFMADDSS4rm >+ 1156U, // VFMADDSS4rm_Int >+ 4U, // VFMADDSS4rr >+ 4U, // VFMADDSS4rr_Int >+ 4U, // VFMADDSS4rr_REV >+ 0U, // VFMADDSSZm >+ 0U, // VFMADDSSZr >+ 4U, // VFMADDSSr132m >+ 0U, // VFMADDSSr132r >+ 4U, // VFMADDSSr213m >+ 0U, // VFMADDSSr213r >+ 4U, // VFMADDSSr231m >+ 0U, // VFMADDSSr231r >+ 0U, // VFMADDSUB132PDZm >+ 4U, // VFMADDSUB132PDZmb >+ 0U, // VFMADDSUB132PSZm >+ 4U, // VFMADDSUB132PSZmb >+ 0U, // VFMADDSUB213PDZm >+ 4U, // VFMADDSUB213PDZmb >+ 0U, // VFMADDSUB213PDZr >+ 345U, // VFMADDSUB213PDZrk >+ 281U, // VFMADDSUB213PDZrkz >+ 0U, // VFMADDSUB213PSZm >+ 4U, // VFMADDSUB213PSZmb >+ 0U, // VFMADDSUB213PSZr >+ 345U, // VFMADDSUB213PSZrk >+ 281U, // VFMADDSUB213PSZrkz >+ 4U, // VFMADDSUBPD4mr >+ 0U, // VFMADDSUBPD4mrY >+ 4U, // VFMADDSUBPD4rm >+ 4U, // VFMADDSUBPD4rmY >+ 4U, // VFMADDSUBPD4rr >+ 4U, // VFMADDSUBPD4rrY >+ 4U, // VFMADDSUBPD4rrY_REV >+ 4U, // VFMADDSUBPD4rr_REV >+ 0U, // VFMADDSUBPDr132m >+ 0U, // VFMADDSUBPDr132mY >+ 0U, // VFMADDSUBPDr132r >+ 0U, // VFMADDSUBPDr132rY >+ 0U, // VFMADDSUBPDr213m >+ 0U, // VFMADDSUBPDr213mY >+ 0U, // VFMADDSUBPDr213r >+ 0U, // VFMADDSUBPDr213rY >+ 0U, // VFMADDSUBPDr231m >+ 0U, // VFMADDSUBPDr231mY >+ 0U, // VFMADDSUBPDr231r >+ 0U, // VFMADDSUBPDr231rY >+ 4U, // VFMADDSUBPS4mr >+ 0U, // VFMADDSUBPS4mrY >+ 4U, // VFMADDSUBPS4rm >+ 4U, // VFMADDSUBPS4rmY >+ 4U, // VFMADDSUBPS4rr >+ 4U, // VFMADDSUBPS4rrY >+ 4U, // VFMADDSUBPS4rrY_REV >+ 4U, // VFMADDSUBPS4rr_REV >+ 0U, // VFMADDSUBPSr132m >+ 0U, // VFMADDSUBPSr132mY >+ 0U, // VFMADDSUBPSr132r >+ 0U, // VFMADDSUBPSr132rY >+ 0U, // VFMADDSUBPSr213m >+ 0U, // VFMADDSUBPSr213mY >+ 0U, // VFMADDSUBPSr213r >+ 0U, // VFMADDSUBPSr213rY >+ 0U, // VFMADDSUBPSr231m >+ 0U, // VFMADDSUBPSr231mY >+ 0U, // VFMADDSUBPSr231r >+ 0U, // VFMADDSUBPSr231rY >+ 0U, // VFMSUB132PDZm >+ 4U, // VFMSUB132PDZmb >+ 0U, // VFMSUB132PSZm >+ 4U, // VFMSUB132PSZmb >+ 0U, // VFMSUB213PDZm >+ 4U, // VFMSUB213PDZmb >+ 0U, // VFMSUB213PDZr >+ 345U, // VFMSUB213PDZrk >+ 281U, // VFMSUB213PDZrkz >+ 0U, // VFMSUB213PSZm >+ 4U, // VFMSUB213PSZmb >+ 0U, // VFMSUB213PSZr >+ 345U, // VFMSUB213PSZrk >+ 281U, // VFMSUB213PSZrkz >+ 0U, // VFMSUBADD132PDZm >+ 4U, // VFMSUBADD132PDZmb >+ 0U, // VFMSUBADD132PSZm >+ 4U, // VFMSUBADD132PSZmb >+ 0U, // VFMSUBADD213PDZm >+ 4U, // VFMSUBADD213PDZmb >+ 0U, // VFMSUBADD213PDZr >+ 345U, // VFMSUBADD213PDZrk >+ 281U, // VFMSUBADD213PDZrkz >+ 0U, // VFMSUBADD213PSZm >+ 4U, // VFMSUBADD213PSZmb >+ 0U, // VFMSUBADD213PSZr >+ 345U, // VFMSUBADD213PSZrk >+ 281U, // VFMSUBADD213PSZrkz >+ 4U, // VFMSUBADDPD4mr >+ 0U, // VFMSUBADDPD4mrY >+ 4U, // VFMSUBADDPD4rm >+ 4U, // VFMSUBADDPD4rmY >+ 4U, // VFMSUBADDPD4rr >+ 4U, // VFMSUBADDPD4rrY >+ 4U, // VFMSUBADDPD4rrY_REV >+ 4U, // VFMSUBADDPD4rr_REV >+ 0U, // VFMSUBADDPDr132m >+ 0U, // VFMSUBADDPDr132mY >+ 0U, // VFMSUBADDPDr132r >+ 0U, // VFMSUBADDPDr132rY >+ 0U, // VFMSUBADDPDr213m >+ 0U, // VFMSUBADDPDr213mY >+ 0U, // VFMSUBADDPDr213r >+ 0U, // VFMSUBADDPDr213rY >+ 0U, // VFMSUBADDPDr231m >+ 0U, // VFMSUBADDPDr231mY >+ 0U, // VFMSUBADDPDr231r >+ 0U, // VFMSUBADDPDr231rY >+ 4U, // VFMSUBADDPS4mr >+ 0U, // VFMSUBADDPS4mrY >+ 4U, // VFMSUBADDPS4rm >+ 4U, // VFMSUBADDPS4rmY >+ 4U, // VFMSUBADDPS4rr >+ 4U, // VFMSUBADDPS4rrY >+ 4U, // VFMSUBADDPS4rrY_REV >+ 4U, // VFMSUBADDPS4rr_REV >+ 0U, // VFMSUBADDPSr132m >+ 0U, // VFMSUBADDPSr132mY >+ 0U, // VFMSUBADDPSr132r >+ 0U, // VFMSUBADDPSr132rY >+ 0U, // VFMSUBADDPSr213m >+ 0U, // VFMSUBADDPSr213mY >+ 0U, // VFMSUBADDPSr213r >+ 0U, // VFMSUBADDPSr213rY >+ 0U, // VFMSUBADDPSr231m >+ 0U, // VFMSUBADDPSr231mY >+ 0U, // VFMSUBADDPSr231r >+ 0U, // VFMSUBADDPSr231rY >+ 4U, // VFMSUBPD4mr >+ 0U, // VFMSUBPD4mrY >+ 4U, // VFMSUBPD4rm >+ 4U, // VFMSUBPD4rmY >+ 4U, // VFMSUBPD4rr >+ 4U, // VFMSUBPD4rrY >+ 4U, // VFMSUBPD4rrY_REV >+ 4U, // VFMSUBPD4rr_REV >+ 0U, // VFMSUBPDr132m >+ 0U, // VFMSUBPDr132mY >+ 0U, // VFMSUBPDr132r >+ 0U, // VFMSUBPDr132rY >+ 0U, // VFMSUBPDr213m >+ 0U, // VFMSUBPDr213mY >+ 0U, // VFMSUBPDr213r >+ 0U, // VFMSUBPDr213rY >+ 0U, // VFMSUBPDr231m >+ 0U, // VFMSUBPDr231mY >+ 0U, // VFMSUBPDr231r >+ 0U, // VFMSUBPDr231rY >+ 4U, // VFMSUBPS4mr >+ 0U, // VFMSUBPS4mrY >+ 4U, // VFMSUBPS4rm >+ 4U, // VFMSUBPS4rmY >+ 4U, // VFMSUBPS4rr >+ 4U, // VFMSUBPS4rrY >+ 4U, // VFMSUBPS4rrY_REV >+ 4U, // VFMSUBPS4rr_REV >+ 0U, // VFMSUBPSr132m >+ 0U, // VFMSUBPSr132mY >+ 0U, // VFMSUBPSr132r >+ 0U, // VFMSUBPSr132rY >+ 0U, // VFMSUBPSr213m >+ 0U, // VFMSUBPSr213mY >+ 0U, // VFMSUBPSr213r >+ 0U, // VFMSUBPSr213rY >+ 0U, // VFMSUBPSr231m >+ 0U, // VFMSUBPSr231mY >+ 0U, // VFMSUBPSr231r >+ 0U, // VFMSUBPSr231rY >+ 4U, // VFMSUBSD4mr >+ 4U, // VFMSUBSD4mr_Int >+ 1156U, // VFMSUBSD4rm >+ 1156U, // VFMSUBSD4rm_Int >+ 4U, // VFMSUBSD4rr >+ 4U, // VFMSUBSD4rr_Int >+ 4U, // VFMSUBSD4rr_REV >+ 0U, // VFMSUBSDZm >+ 0U, // VFMSUBSDZr >+ 4U, // VFMSUBSDr132m >+ 0U, // VFMSUBSDr132r >+ 4U, // VFMSUBSDr213m >+ 0U, // VFMSUBSDr213r >+ 4U, // VFMSUBSDr231m >+ 0U, // VFMSUBSDr231r >+ 4U, // VFMSUBSS4mr >+ 4U, // VFMSUBSS4mr_Int >+ 1156U, // VFMSUBSS4rm >+ 1156U, // VFMSUBSS4rm_Int >+ 4U, // VFMSUBSS4rr >+ 4U, // VFMSUBSS4rr_Int >+ 4U, // VFMSUBSS4rr_REV >+ 0U, // VFMSUBSSZm >+ 0U, // VFMSUBSSZr >+ 4U, // VFMSUBSSr132m >+ 0U, // VFMSUBSSr132r >+ 4U, // VFMSUBSSr213m >+ 0U, // VFMSUBSSr213r >+ 4U, // VFMSUBSSr231m >+ 0U, // VFMSUBSSr231r >+ 0U, // VFNMADD132PDZm >+ 4U, // VFNMADD132PDZmb >+ 0U, // VFNMADD132PSZm >+ 4U, // VFNMADD132PSZmb >+ 0U, // VFNMADD213PDZm >+ 4U, // VFNMADD213PDZmb >+ 0U, // VFNMADD213PDZr >+ 345U, // VFNMADD213PDZrk >+ 281U, // VFNMADD213PDZrkz >+ 0U, // VFNMADD213PSZm >+ 4U, // VFNMADD213PSZmb >+ 0U, // VFNMADD213PSZr >+ 345U, // VFNMADD213PSZrk >+ 281U, // VFNMADD213PSZrkz >+ 4U, // VFNMADDPD4mr >+ 0U, // VFNMADDPD4mrY >+ 4U, // VFNMADDPD4rm >+ 4U, // VFNMADDPD4rmY >+ 4U, // VFNMADDPD4rr >+ 4U, // VFNMADDPD4rrY >+ 4U, // VFNMADDPD4rrY_REV >+ 4U, // VFNMADDPD4rr_REV >+ 0U, // VFNMADDPDr132m >+ 0U, // VFNMADDPDr132mY >+ 0U, // VFNMADDPDr132r >+ 0U, // VFNMADDPDr132rY >+ 0U, // VFNMADDPDr213m >+ 0U, // VFNMADDPDr213mY >+ 0U, // VFNMADDPDr213r >+ 0U, // VFNMADDPDr213rY >+ 0U, // VFNMADDPDr231m >+ 0U, // VFNMADDPDr231mY >+ 0U, // VFNMADDPDr231r >+ 0U, // VFNMADDPDr231rY >+ 4U, // VFNMADDPS4mr >+ 0U, // VFNMADDPS4mrY >+ 4U, // VFNMADDPS4rm >+ 4U, // VFNMADDPS4rmY >+ 4U, // VFNMADDPS4rr >+ 4U, // VFNMADDPS4rrY >+ 4U, // VFNMADDPS4rrY_REV >+ 4U, // VFNMADDPS4rr_REV >+ 0U, // VFNMADDPSr132m >+ 0U, // VFNMADDPSr132mY >+ 0U, // VFNMADDPSr132r >+ 0U, // VFNMADDPSr132rY >+ 0U, // VFNMADDPSr213m >+ 0U, // VFNMADDPSr213mY >+ 0U, // VFNMADDPSr213r >+ 0U, // VFNMADDPSr213rY >+ 0U, // VFNMADDPSr231m >+ 0U, // VFNMADDPSr231mY >+ 0U, // VFNMADDPSr231r >+ 0U, // VFNMADDPSr231rY >+ 4U, // VFNMADDSD4mr >+ 4U, // VFNMADDSD4mr_Int >+ 1156U, // VFNMADDSD4rm >+ 1156U, // VFNMADDSD4rm_Int >+ 4U, // VFNMADDSD4rr >+ 4U, // VFNMADDSD4rr_Int >+ 4U, // VFNMADDSD4rr_REV >+ 0U, // VFNMADDSDZm >+ 0U, // VFNMADDSDZr >+ 4U, // VFNMADDSDr132m >+ 0U, // VFNMADDSDr132r >+ 4U, // VFNMADDSDr213m >+ 0U, // VFNMADDSDr213r >+ 4U, // VFNMADDSDr231m >+ 0U, // VFNMADDSDr231r >+ 4U, // VFNMADDSS4mr >+ 4U, // VFNMADDSS4mr_Int >+ 1156U, // VFNMADDSS4rm >+ 1156U, // VFNMADDSS4rm_Int >+ 4U, // VFNMADDSS4rr >+ 4U, // VFNMADDSS4rr_Int >+ 4U, // VFNMADDSS4rr_REV >+ 0U, // VFNMADDSSZm >+ 0U, // VFNMADDSSZr >+ 4U, // VFNMADDSSr132m >+ 0U, // VFNMADDSSr132r >+ 4U, // VFNMADDSSr213m >+ 0U, // VFNMADDSSr213r >+ 4U, // VFNMADDSSr231m >+ 0U, // VFNMADDSSr231r >+ 0U, // VFNMSUB132PDZm >+ 4U, // VFNMSUB132PDZmb >+ 0U, // VFNMSUB132PSZm >+ 4U, // VFNMSUB132PSZmb >+ 0U, // VFNMSUB213PDZm >+ 4U, // VFNMSUB213PDZmb >+ 0U, // VFNMSUB213PDZr >+ 345U, // VFNMSUB213PDZrk >+ 281U, // VFNMSUB213PDZrkz >+ 0U, // VFNMSUB213PSZm >+ 4U, // VFNMSUB213PSZmb >+ 0U, // VFNMSUB213PSZr >+ 345U, // VFNMSUB213PSZrk >+ 281U, // VFNMSUB213PSZrkz >+ 4U, // VFNMSUBPD4mr >+ 0U, // VFNMSUBPD4mrY >+ 4U, // VFNMSUBPD4rm >+ 4U, // VFNMSUBPD4rmY >+ 4U, // VFNMSUBPD4rr >+ 4U, // VFNMSUBPD4rrY >+ 4U, // VFNMSUBPD4rrY_REV >+ 4U, // VFNMSUBPD4rr_REV >+ 0U, // VFNMSUBPDr132m >+ 0U, // VFNMSUBPDr132mY >+ 0U, // VFNMSUBPDr132r >+ 0U, // VFNMSUBPDr132rY >+ 0U, // VFNMSUBPDr213m >+ 0U, // VFNMSUBPDr213mY >+ 0U, // VFNMSUBPDr213r >+ 0U, // VFNMSUBPDr213rY >+ 0U, // VFNMSUBPDr231m >+ 0U, // VFNMSUBPDr231mY >+ 0U, // VFNMSUBPDr231r >+ 0U, // VFNMSUBPDr231rY >+ 4U, // VFNMSUBPS4mr >+ 0U, // VFNMSUBPS4mrY >+ 4U, // VFNMSUBPS4rm >+ 4U, // VFNMSUBPS4rmY >+ 4U, // VFNMSUBPS4rr >+ 4U, // VFNMSUBPS4rrY >+ 4U, // VFNMSUBPS4rrY_REV >+ 4U, // VFNMSUBPS4rr_REV >+ 0U, // VFNMSUBPSr132m >+ 0U, // VFNMSUBPSr132mY >+ 0U, // VFNMSUBPSr132r >+ 0U, // VFNMSUBPSr132rY >+ 0U, // VFNMSUBPSr213m >+ 0U, // VFNMSUBPSr213mY >+ 0U, // VFNMSUBPSr213r >+ 0U, // VFNMSUBPSr213rY >+ 0U, // VFNMSUBPSr231m >+ 0U, // VFNMSUBPSr231mY >+ 0U, // VFNMSUBPSr231r >+ 0U, // VFNMSUBPSr231rY >+ 4U, // VFNMSUBSD4mr >+ 4U, // VFNMSUBSD4mr_Int >+ 1156U, // VFNMSUBSD4rm >+ 1156U, // VFNMSUBSD4rm_Int >+ 4U, // VFNMSUBSD4rr >+ 4U, // VFNMSUBSD4rr_Int >+ 4U, // VFNMSUBSD4rr_REV >+ 0U, // VFNMSUBSDZm >+ 0U, // VFNMSUBSDZr >+ 4U, // VFNMSUBSDr132m >+ 0U, // VFNMSUBSDr132r >+ 4U, // VFNMSUBSDr213m >+ 0U, // VFNMSUBSDr213r >+ 4U, // VFNMSUBSDr231m >+ 0U, // VFNMSUBSDr231r >+ 4U, // VFNMSUBSS4mr >+ 4U, // VFNMSUBSS4mr_Int >+ 1156U, // VFNMSUBSS4rm >+ 1156U, // VFNMSUBSS4rm_Int >+ 4U, // VFNMSUBSS4rr >+ 4U, // VFNMSUBSS4rr_Int >+ 4U, // VFNMSUBSS4rr_REV >+ 0U, // VFNMSUBSSZm >+ 0U, // VFNMSUBSSZr >+ 4U, // VFNMSUBSSr132m >+ 0U, // VFNMSUBSSr132r >+ 4U, // VFNMSUBSSr213m >+ 0U, // VFNMSUBSSr213r >+ 4U, // VFNMSUBSSr231m >+ 0U, // VFNMSUBSSr231r >+ 0U, // VFRCZPDrm >+ 0U, // VFRCZPDrmY >+ 0U, // VFRCZPDrr >+ 0U, // VFRCZPDrrY >+ 0U, // VFRCZPSrm >+ 0U, // VFRCZPSrmY >+ 0U, // VFRCZPSrr >+ 0U, // VFRCZPSrrY >+ 0U, // VFRCZSDrm >+ 0U, // VFRCZSDrr >+ 0U, // VFRCZSSrm >+ 0U, // VFRCZSSrr >+ 0U, // VFsANDNPDrm >+ 0U, // VFsANDNPDrr >+ 0U, // VFsANDNPSrm >+ 0U, // VFsANDNPSrr >+ 0U, // VFsANDPDrm >+ 0U, // VFsANDPDrr >+ 0U, // VFsANDPSrm >+ 0U, // VFsANDPSrr >+ 0U, // VFsORPDrm >+ 0U, // VFsORPDrr >+ 0U, // VFsORPSrm >+ 0U, // VFsORPSrr >+ 0U, // VFsXORPDrm >+ 0U, // VFsXORPDrr >+ 0U, // VFsXORPSrm >+ 0U, // VFsXORPSrr >+ 0U, // VGATHERDPDYrm >+ 404U, // VGATHERDPDZrm >+ 0U, // VGATHERDPDrm >+ 0U, // VGATHERDPSYrm >+ 404U, // VGATHERDPSZrm >+ 0U, // VGATHERDPSrm >+ 0U, // VGATHERPF0DPDm >+ 0U, // VGATHERPF0DPSm >+ 0U, // VGATHERPF0QPDm >+ 0U, // VGATHERPF0QPSm >+ 0U, // VGATHERPF1DPDm >+ 0U, // VGATHERPF1DPSm >+ 0U, // VGATHERPF1QPDm >+ 0U, // VGATHERPF1QPSm >+ 0U, // VGATHERQPDYrm >+ 404U, // VGATHERQPDZrm >+ 0U, // VGATHERQPDrm >+ 0U, // VGATHERQPSYrm >+ 404U, // VGATHERQPSZrm >+ 0U, // VGATHERQPSrm >+ 0U, // VHADDPDYrm >+ 0U, // VHADDPDYrr >+ 0U, // VHADDPDrm >+ 0U, // VHADDPDrr >+ 0U, // VHADDPSYrm >+ 0U, // VHADDPSYrr >+ 0U, // VHADDPSrm >+ 0U, // VHADDPSrr >+ 0U, // VHSUBPDYrm >+ 0U, // VHSUBPDYrr >+ 0U, // VHSUBPDrm >+ 0U, // VHSUBPDrr >+ 0U, // VHSUBPSYrm >+ 0U, // VHSUBPSYrr >+ 0U, // VHSUBPSrm >+ 0U, // VHSUBPSrr >+ 4U, // VINSERTF128rm >+ 4U, // VINSERTF128rr >+ 4U, // VINSERTF32x4rm >+ 4U, // VINSERTF32x4rr >+ 0U, // VINSERTF64x4rm >+ 4U, // VINSERTF64x4rr >+ 4U, // VINSERTI128rm >+ 4U, // VINSERTI128rr >+ 4U, // VINSERTI32x4rm >+ 4U, // VINSERTI32x4rr >+ 0U, // VINSERTI64x4rm >+ 4U, // VINSERTI64x4rr >+ 4U, // VINSERTPSrm >+ 4U, // VINSERTPSrr >+ 4U, // VINSERTPSzrm >+ 4U, // VINSERTPSzrr >+ 0U, // VLDDQUYrm >+ 0U, // VLDDQUrm >+ 0U, // VLDMXCSR >+ 0U, // VMASKMOVDQU >+ 0U, // VMASKMOVDQU64 >+ 1U, // VMASKMOVPDYmr >+ 0U, // VMASKMOVPDYrm >+ 1U, // VMASKMOVPDmr >+ 0U, // VMASKMOVPDrm >+ 1U, // VMASKMOVPSYmr >+ 0U, // VMASKMOVPSYrm >+ 1U, // VMASKMOVPSmr >+ 0U, // VMASKMOVPSrm >+ 0U, // VMAXCPDYrm >+ 0U, // VMAXCPDYrr >+ 0U, // VMAXCPDrm >+ 0U, // VMAXCPDrr >+ 0U, // VMAXCPSYrm >+ 0U, // VMAXCPSYrr >+ 0U, // VMAXCPSrm >+ 0U, // VMAXCPSrr >+ 4U, // VMAXCSDrm >+ 0U, // VMAXCSDrr >+ 4U, // VMAXCSSrm >+ 0U, // VMAXCSSrr >+ 0U, // VMAXPDYrm >+ 0U, // VMAXPDYrr >+ 0U, // VMAXPDZrm >+ 4U, // VMAXPDZrmb >+ 2052U, // VMAXPDZrmbk >+ 10244U, // VMAXPDZrmbkz >+ 3220U, // VMAXPDZrmk >+ 4244U, // VMAXPDZrmkz >+ 0U, // VMAXPDZrr >+ 5268U, // VMAXPDZrrk >+ 4244U, // VMAXPDZrrkz >+ 0U, // VMAXPDrm >+ 0U, // VMAXPDrr >+ 0U, // VMAXPSYrm >+ 0U, // VMAXPSYrr >+ 0U, // VMAXPSZrm >+ 4U, // VMAXPSZrmb >+ 2052U, // VMAXPSZrmbk >+ 10244U, // VMAXPSZrmbkz >+ 3220U, // VMAXPSZrmk >+ 4244U, // VMAXPSZrmkz >+ 0U, // VMAXPSZrr >+ 5268U, // VMAXPSZrrk >+ 4244U, // VMAXPSZrrkz >+ 0U, // VMAXPSrm >+ 0U, // VMAXPSrr >+ 4U, // VMAXSDZrm >+ 0U, // VMAXSDZrr >+ 4U, // VMAXSDrm >+ 4U, // VMAXSDrm_Int >+ 0U, // VMAXSDrr >+ 0U, // VMAXSDrr_Int >+ 4U, // VMAXSSZrm >+ 0U, // VMAXSSZrr >+ 4U, // VMAXSSrm >+ 4U, // VMAXSSrm_Int >+ 0U, // VMAXSSrr >+ 0U, // VMAXSSrr_Int >+ 0U, // VMCALL >+ 0U, // VMCLEARm >+ 0U, // VMFUNC >+ 0U, // VMINCPDYrm >+ 0U, // VMINCPDYrr >+ 0U, // VMINCPDrm >+ 0U, // VMINCPDrr >+ 0U, // VMINCPSYrm >+ 0U, // VMINCPSYrr >+ 0U, // VMINCPSrm >+ 0U, // VMINCPSrr >+ 4U, // VMINCSDrm >+ 0U, // VMINCSDrr >+ 4U, // VMINCSSrm >+ 0U, // VMINCSSrr >+ 0U, // VMINPDYrm >+ 0U, // VMINPDYrr >+ 0U, // VMINPDZrm >+ 4U, // VMINPDZrmb >+ 2052U, // VMINPDZrmbk >+ 10244U, // VMINPDZrmbkz >+ 3220U, // VMINPDZrmk >+ 4244U, // VMINPDZrmkz >+ 0U, // VMINPDZrr >+ 5268U, // VMINPDZrrk >+ 4244U, // VMINPDZrrkz >+ 0U, // VMINPDrm >+ 0U, // VMINPDrr >+ 0U, // VMINPSYrm >+ 0U, // VMINPSYrr >+ 0U, // VMINPSZrm >+ 4U, // VMINPSZrmb >+ 2052U, // VMINPSZrmbk >+ 10244U, // VMINPSZrmbkz >+ 3220U, // VMINPSZrmk >+ 4244U, // VMINPSZrmkz >+ 0U, // VMINPSZrr >+ 5268U, // VMINPSZrrk >+ 4244U, // VMINPSZrrkz >+ 0U, // VMINPSrm >+ 0U, // VMINPSrr >+ 4U, // VMINSDZrm >+ 0U, // VMINSDZrr >+ 4U, // VMINSDrm >+ 4U, // VMINSDrm_Int >+ 0U, // VMINSDrr >+ 0U, // VMINSDrr_Int >+ 4U, // VMINSSZrm >+ 0U, // VMINSSZrr >+ 4U, // VMINSSrm >+ 4U, // VMINSSrm_Int >+ 0U, // VMINSSrr >+ 0U, // VMINSSrr_Int >+ 0U, // VMLAUNCH >+ 0U, // VMLOAD32 >+ 0U, // VMLOAD64 >+ 0U, // VMMCALL >+ 0U, // VMOV64toPQIZrr >+ 0U, // VMOV64toPQIrr >+ 0U, // VMOV64toSDZrr >+ 0U, // VMOV64toSDrm >+ 0U, // VMOV64toSDrr >+ 0U, // VMOVAPDYmr >+ 0U, // VMOVAPDYrm >+ 0U, // VMOVAPDYrr >+ 0U, // VMOVAPDYrr_REV >+ 0U, // VMOVAPDZ128mr >+ 29U, // VMOVAPDZ128mrk >+ 0U, // VMOVAPDZ128rm >+ 345U, // VMOVAPDZ128rmk >+ 269U, // VMOVAPDZ128rmkz >+ 0U, // VMOVAPDZ128rr >+ 0U, // VMOVAPDZ128rr_alt >+ 345U, // VMOVAPDZ128rrk >+ 345U, // VMOVAPDZ128rrk_alt >+ 269U, // VMOVAPDZ128rrkz >+ 269U, // VMOVAPDZ128rrkz_alt >+ 0U, // VMOVAPDZ256mr >+ 29U, // VMOVAPDZ256mrk >+ 0U, // VMOVAPDZ256rm >+ 345U, // VMOVAPDZ256rmk >+ 269U, // VMOVAPDZ256rmkz >+ 0U, // VMOVAPDZ256rr >+ 0U, // VMOVAPDZ256rr_alt >+ 345U, // VMOVAPDZ256rrk >+ 345U, // VMOVAPDZ256rrk_alt >+ 269U, // VMOVAPDZ256rrkz >+ 269U, // VMOVAPDZ256rrkz_alt >+ 0U, // VMOVAPDZmr >+ 29U, // VMOVAPDZmrk >+ 0U, // VMOVAPDZrm >+ 345U, // VMOVAPDZrmk >+ 269U, // VMOVAPDZrmkz >+ 0U, // VMOVAPDZrr >+ 0U, // VMOVAPDZrr_alt >+ 345U, // VMOVAPDZrrk >+ 345U, // VMOVAPDZrrk_alt >+ 269U, // VMOVAPDZrrkz >+ 269U, // VMOVAPDZrrkz_alt >+ 0U, // VMOVAPDmr >+ 0U, // VMOVAPDrm >+ 0U, // VMOVAPDrr >+ 0U, // VMOVAPDrr_REV >+ 0U, // VMOVAPSYmr >+ 0U, // VMOVAPSYrm >+ 0U, // VMOVAPSYrr >+ 0U, // VMOVAPSYrr_REV >+ 0U, // VMOVAPSZ128mr >+ 29U, // VMOVAPSZ128mrk >+ 0U, // VMOVAPSZ128rm >+ 345U, // VMOVAPSZ128rmk >+ 269U, // VMOVAPSZ128rmkz >+ 0U, // VMOVAPSZ128rr >+ 0U, // VMOVAPSZ128rr_alt >+ 345U, // VMOVAPSZ128rrk >+ 345U, // VMOVAPSZ128rrk_alt >+ 269U, // VMOVAPSZ128rrkz >+ 269U, // VMOVAPSZ128rrkz_alt >+ 0U, // VMOVAPSZ256mr >+ 29U, // VMOVAPSZ256mrk >+ 0U, // VMOVAPSZ256rm >+ 345U, // VMOVAPSZ256rmk >+ 269U, // VMOVAPSZ256rmkz >+ 0U, // VMOVAPSZ256rr >+ 0U, // VMOVAPSZ256rr_alt >+ 345U, // VMOVAPSZ256rrk >+ 345U, // VMOVAPSZ256rrk_alt >+ 269U, // VMOVAPSZ256rrkz >+ 269U, // VMOVAPSZ256rrkz_alt >+ 0U, // VMOVAPSZmr >+ 29U, // VMOVAPSZmrk >+ 0U, // VMOVAPSZrm >+ 345U, // VMOVAPSZrmk >+ 269U, // VMOVAPSZrmkz >+ 0U, // VMOVAPSZrr >+ 0U, // VMOVAPSZrr_alt >+ 345U, // VMOVAPSZrrk >+ 345U, // VMOVAPSZrrk_alt >+ 269U, // VMOVAPSZrrkz >+ 269U, // VMOVAPSZrrkz_alt >+ 0U, // VMOVAPSmr >+ 0U, // VMOVAPSrm >+ 0U, // VMOVAPSrr >+ 0U, // VMOVAPSrr_REV >+ 0U, // VMOVDDUPYrm >+ 0U, // VMOVDDUPYrr >+ 0U, // VMOVDDUPZrm >+ 0U, // VMOVDDUPZrr >+ 0U, // VMOVDDUPrm >+ 0U, // VMOVDDUPrr >+ 0U, // VMOVDI2PDIZrm >+ 0U, // VMOVDI2PDIZrr >+ 0U, // VMOVDI2PDIrm >+ 0U, // VMOVDI2PDIrr >+ 0U, // VMOVDI2SSZrm >+ 0U, // VMOVDI2SSZrr >+ 0U, // VMOVDI2SSrm >+ 0U, // VMOVDI2SSrr >+ 0U, // VMOVDQA32Z128mr >+ 29U, // VMOVDQA32Z128mrk >+ 0U, // VMOVDQA32Z128rm >+ 345U, // VMOVDQA32Z128rmk >+ 269U, // VMOVDQA32Z128rmkz >+ 0U, // VMOVDQA32Z128rr >+ 0U, // VMOVDQA32Z128rr_alt >+ 345U, // VMOVDQA32Z128rrk >+ 345U, // VMOVDQA32Z128rrk_alt >+ 269U, // VMOVDQA32Z128rrkz >+ 269U, // VMOVDQA32Z128rrkz_alt >+ 0U, // VMOVDQA32Z256mr >+ 29U, // VMOVDQA32Z256mrk >+ 0U, // VMOVDQA32Z256rm >+ 345U, // VMOVDQA32Z256rmk >+ 269U, // VMOVDQA32Z256rmkz >+ 0U, // VMOVDQA32Z256rr >+ 0U, // VMOVDQA32Z256rr_alt >+ 345U, // VMOVDQA32Z256rrk >+ 345U, // VMOVDQA32Z256rrk_alt >+ 269U, // VMOVDQA32Z256rrkz >+ 269U, // VMOVDQA32Z256rrkz_alt >+ 0U, // VMOVDQA32Zmr >+ 29U, // VMOVDQA32Zmrk >+ 0U, // VMOVDQA32Zrm >+ 345U, // VMOVDQA32Zrmk >+ 269U, // VMOVDQA32Zrmkz >+ 0U, // VMOVDQA32Zrr >+ 0U, // VMOVDQA32Zrr_alt >+ 345U, // VMOVDQA32Zrrk >+ 345U, // VMOVDQA32Zrrk_alt >+ 269U, // VMOVDQA32Zrrkz >+ 269U, // VMOVDQA32Zrrkz_alt >+ 0U, // VMOVDQA64Z128mr >+ 29U, // VMOVDQA64Z128mrk >+ 0U, // VMOVDQA64Z128rm >+ 345U, // VMOVDQA64Z128rmk >+ 269U, // VMOVDQA64Z128rmkz >+ 0U, // VMOVDQA64Z128rr >+ 0U, // VMOVDQA64Z128rr_alt >+ 345U, // VMOVDQA64Z128rrk >+ 345U, // VMOVDQA64Z128rrk_alt >+ 269U, // VMOVDQA64Z128rrkz >+ 269U, // VMOVDQA64Z128rrkz_alt >+ 0U, // VMOVDQA64Z256mr >+ 29U, // VMOVDQA64Z256mrk >+ 0U, // VMOVDQA64Z256rm >+ 345U, // VMOVDQA64Z256rmk >+ 269U, // VMOVDQA64Z256rmkz >+ 0U, // VMOVDQA64Z256rr >+ 0U, // VMOVDQA64Z256rr_alt >+ 345U, // VMOVDQA64Z256rrk >+ 345U, // VMOVDQA64Z256rrk_alt >+ 269U, // VMOVDQA64Z256rrkz >+ 269U, // VMOVDQA64Z256rrkz_alt >+ 0U, // VMOVDQA64Zmr >+ 29U, // VMOVDQA64Zmrk >+ 0U, // VMOVDQA64Zrm >+ 345U, // VMOVDQA64Zrmk >+ 269U, // VMOVDQA64Zrmkz >+ 0U, // VMOVDQA64Zrr >+ 0U, // VMOVDQA64Zrr_alt >+ 345U, // VMOVDQA64Zrrk >+ 345U, // VMOVDQA64Zrrk_alt >+ 269U, // VMOVDQA64Zrrkz >+ 269U, // VMOVDQA64Zrrkz_alt >+ 0U, // VMOVDQAYmr >+ 0U, // VMOVDQAYrm >+ 0U, // VMOVDQAYrr >+ 0U, // VMOVDQAYrr_REV >+ 0U, // VMOVDQAmr >+ 0U, // VMOVDQArm >+ 0U, // VMOVDQArr >+ 0U, // VMOVDQArr_REV >+ 0U, // VMOVDQU16Z128mr >+ 29U, // VMOVDQU16Z128mrk >+ 0U, // VMOVDQU16Z128rm >+ 345U, // VMOVDQU16Z128rmk >+ 269U, // VMOVDQU16Z128rmkz >+ 0U, // VMOVDQU16Z128rr >+ 0U, // VMOVDQU16Z128rr_alt >+ 345U, // VMOVDQU16Z128rrk >+ 345U, // VMOVDQU16Z128rrk_alt >+ 269U, // VMOVDQU16Z128rrkz >+ 269U, // VMOVDQU16Z128rrkz_alt >+ 0U, // VMOVDQU16Z256mr >+ 29U, // VMOVDQU16Z256mrk >+ 0U, // VMOVDQU16Z256rm >+ 345U, // VMOVDQU16Z256rmk >+ 269U, // VMOVDQU16Z256rmkz >+ 0U, // VMOVDQU16Z256rr >+ 0U, // VMOVDQU16Z256rr_alt >+ 345U, // VMOVDQU16Z256rrk >+ 345U, // VMOVDQU16Z256rrk_alt >+ 269U, // VMOVDQU16Z256rrkz >+ 269U, // VMOVDQU16Z256rrkz_alt >+ 0U, // VMOVDQU16Zmr >+ 29U, // VMOVDQU16Zmrk >+ 0U, // VMOVDQU16Zrm >+ 345U, // VMOVDQU16Zrmk >+ 269U, // VMOVDQU16Zrmkz >+ 0U, // VMOVDQU16Zrr >+ 0U, // VMOVDQU16Zrr_alt >+ 345U, // VMOVDQU16Zrrk >+ 345U, // VMOVDQU16Zrrk_alt >+ 269U, // VMOVDQU16Zrrkz >+ 269U, // VMOVDQU16Zrrkz_alt >+ 0U, // VMOVDQU32Z128mr >+ 29U, // VMOVDQU32Z128mrk >+ 0U, // VMOVDQU32Z128rm >+ 345U, // VMOVDQU32Z128rmk >+ 269U, // VMOVDQU32Z128rmkz >+ 0U, // VMOVDQU32Z128rr >+ 0U, // VMOVDQU32Z128rr_alt >+ 345U, // VMOVDQU32Z128rrk >+ 345U, // VMOVDQU32Z128rrk_alt >+ 269U, // VMOVDQU32Z128rrkz >+ 269U, // VMOVDQU32Z128rrkz_alt >+ 0U, // VMOVDQU32Z256mr >+ 29U, // VMOVDQU32Z256mrk >+ 0U, // VMOVDQU32Z256rm >+ 345U, // VMOVDQU32Z256rmk >+ 269U, // VMOVDQU32Z256rmkz >+ 0U, // VMOVDQU32Z256rr >+ 0U, // VMOVDQU32Z256rr_alt >+ 345U, // VMOVDQU32Z256rrk >+ 345U, // VMOVDQU32Z256rrk_alt >+ 269U, // VMOVDQU32Z256rrkz >+ 269U, // VMOVDQU32Z256rrkz_alt >+ 0U, // VMOVDQU32Zmr >+ 29U, // VMOVDQU32Zmrk >+ 0U, // VMOVDQU32Zrm >+ 345U, // VMOVDQU32Zrmk >+ 269U, // VMOVDQU32Zrmkz >+ 0U, // VMOVDQU32Zrr >+ 0U, // VMOVDQU32Zrr_alt >+ 345U, // VMOVDQU32Zrrk >+ 345U, // VMOVDQU32Zrrk_alt >+ 269U, // VMOVDQU32Zrrkz >+ 269U, // VMOVDQU32Zrrkz_alt >+ 0U, // VMOVDQU64Z128mr >+ 29U, // VMOVDQU64Z128mrk >+ 0U, // VMOVDQU64Z128rm >+ 345U, // VMOVDQU64Z128rmk >+ 269U, // VMOVDQU64Z128rmkz >+ 0U, // VMOVDQU64Z128rr >+ 0U, // VMOVDQU64Z128rr_alt >+ 345U, // VMOVDQU64Z128rrk >+ 345U, // VMOVDQU64Z128rrk_alt >+ 269U, // VMOVDQU64Z128rrkz >+ 269U, // VMOVDQU64Z128rrkz_alt >+ 0U, // VMOVDQU64Z256mr >+ 29U, // VMOVDQU64Z256mrk >+ 0U, // VMOVDQU64Z256rm >+ 345U, // VMOVDQU64Z256rmk >+ 269U, // VMOVDQU64Z256rmkz >+ 0U, // VMOVDQU64Z256rr >+ 0U, // VMOVDQU64Z256rr_alt >+ 345U, // VMOVDQU64Z256rrk >+ 345U, // VMOVDQU64Z256rrk_alt >+ 269U, // VMOVDQU64Z256rrkz >+ 269U, // VMOVDQU64Z256rrkz_alt >+ 0U, // VMOVDQU64Zmr >+ 29U, // VMOVDQU64Zmrk >+ 0U, // VMOVDQU64Zrm >+ 345U, // VMOVDQU64Zrmk >+ 269U, // VMOVDQU64Zrmkz >+ 0U, // VMOVDQU64Zrr >+ 0U, // VMOVDQU64Zrr_alt >+ 345U, // VMOVDQU64Zrrk >+ 345U, // VMOVDQU64Zrrk_alt >+ 269U, // VMOVDQU64Zrrkz >+ 269U, // VMOVDQU64Zrrkz_alt >+ 0U, // VMOVDQU8Z128mr >+ 29U, // VMOVDQU8Z128mrk >+ 0U, // VMOVDQU8Z128rm >+ 345U, // VMOVDQU8Z128rmk >+ 269U, // VMOVDQU8Z128rmkz >+ 0U, // VMOVDQU8Z128rr >+ 0U, // VMOVDQU8Z128rr_alt >+ 345U, // VMOVDQU8Z128rrk >+ 345U, // VMOVDQU8Z128rrk_alt >+ 269U, // VMOVDQU8Z128rrkz >+ 269U, // VMOVDQU8Z128rrkz_alt >+ 0U, // VMOVDQU8Z256mr >+ 29U, // VMOVDQU8Z256mrk >+ 0U, // VMOVDQU8Z256rm >+ 345U, // VMOVDQU8Z256rmk >+ 269U, // VMOVDQU8Z256rmkz >+ 0U, // VMOVDQU8Z256rr >+ 0U, // VMOVDQU8Z256rr_alt >+ 345U, // VMOVDQU8Z256rrk >+ 345U, // VMOVDQU8Z256rrk_alt >+ 269U, // VMOVDQU8Z256rrkz >+ 269U, // VMOVDQU8Z256rrkz_alt >+ 0U, // VMOVDQU8Zmr >+ 29U, // VMOVDQU8Zmrk >+ 0U, // VMOVDQU8Zrm >+ 345U, // VMOVDQU8Zrmk >+ 269U, // VMOVDQU8Zrmkz >+ 0U, // VMOVDQU8Zrr >+ 0U, // VMOVDQU8Zrr_alt >+ 345U, // VMOVDQU8Zrrk >+ 345U, // VMOVDQU8Zrrk_alt >+ 269U, // VMOVDQU8Zrrkz >+ 269U, // VMOVDQU8Zrrkz_alt >+ 0U, // VMOVDQUYmr >+ 0U, // VMOVDQUYrm >+ 0U, // VMOVDQUYrr >+ 0U, // VMOVDQUYrr_REV >+ 0U, // VMOVDQUmr >+ 0U, // VMOVDQUrm >+ 0U, // VMOVDQUrr >+ 0U, // VMOVDQUrr_REV >+ 0U, // VMOVHLPSZrr >+ 0U, // VMOVHLPSrr >+ 0U, // VMOVHPDmr >+ 4U, // VMOVHPDrm >+ 0U, // VMOVHPSmr >+ 4U, // VMOVHPSrm >+ 0U, // VMOVLHPSZrr >+ 0U, // VMOVLHPSrr >+ 0U, // VMOVLPDmr >+ 4U, // VMOVLPDrm >+ 0U, // VMOVLPSmr >+ 4U, // VMOVLPSrm >+ 0U, // VMOVMSKPDYrr >+ 0U, // VMOVMSKPDrr >+ 0U, // VMOVMSKPSYrr >+ 0U, // VMOVMSKPSrr >+ 0U, // VMOVNTDQAYrm >+ 0U, // VMOVNTDQAZ128rm >+ 0U, // VMOVNTDQAZ256rm >+ 0U, // VMOVNTDQAZrm >+ 0U, // VMOVNTDQArm >+ 0U, // VMOVNTDQYmr >+ 0U, // VMOVNTDQZ128mr >+ 0U, // VMOVNTDQZ256mr >+ 0U, // VMOVNTDQZmr >+ 0U, // VMOVNTDQmr >+ 0U, // VMOVNTPDYmr >+ 0U, // VMOVNTPDZ128mr >+ 0U, // VMOVNTPDZ256mr >+ 0U, // VMOVNTPDZmr >+ 0U, // VMOVNTPDmr >+ 0U, // VMOVNTPSYmr >+ 0U, // VMOVNTPSZ128mr >+ 0U, // VMOVNTPSZ256mr >+ 0U, // VMOVNTPSZmr >+ 0U, // VMOVNTPSmr >+ 0U, // VMOVPDI2DIZmr >+ 0U, // VMOVPDI2DIZrr >+ 0U, // VMOVPDI2DImr >+ 0U, // VMOVPDI2DIrr >+ 0U, // VMOVPQI2QImr >+ 0U, // VMOVPQI2QIrr >+ 0U, // VMOVPQIto64Zmr >+ 0U, // VMOVPQIto64Zrr >+ 0U, // VMOVPQIto64rr >+ 0U, // VMOVQI2PQIZrm >+ 0U, // VMOVQI2PQIrm >+ 0U, // VMOVSDZmr >+ 0U, // VMOVSDZrm >+ 0U, // VMOVSDZrr >+ 0U, // VMOVSDZrr_REV >+ 345U, // VMOVSDZrrk >+ 0U, // VMOVSDmr >+ 0U, // VMOVSDrm >+ 0U, // VMOVSDrr >+ 0U, // VMOVSDrr_REV >+ 0U, // VMOVSDto64Zmr >+ 0U, // VMOVSDto64Zrr >+ 0U, // VMOVSDto64mr >+ 0U, // VMOVSDto64rr >+ 0U, // VMOVSHDUPYrm >+ 0U, // VMOVSHDUPYrr >+ 0U, // VMOVSHDUPZrm >+ 0U, // VMOVSHDUPZrr >+ 0U, // VMOVSHDUPrm >+ 0U, // VMOVSHDUPrr >+ 0U, // VMOVSLDUPYrm >+ 0U, // VMOVSLDUPYrr >+ 0U, // VMOVSLDUPZrm >+ 0U, // VMOVSLDUPZrr >+ 0U, // VMOVSLDUPrm >+ 0U, // VMOVSLDUPrr >+ 0U, // VMOVSS2DIZmr >+ 0U, // VMOVSS2DIZrr >+ 0U, // VMOVSS2DImr >+ 0U, // VMOVSS2DIrr >+ 0U, // VMOVSSZmr >+ 0U, // VMOVSSZrm >+ 0U, // VMOVSSZrr >+ 0U, // VMOVSSZrr_REV >+ 345U, // VMOVSSZrrk >+ 0U, // VMOVSSmr >+ 0U, // VMOVSSrm >+ 0U, // VMOVSSrr >+ 0U, // VMOVSSrr_REV >+ 0U, // VMOVUPDYmr >+ 0U, // VMOVUPDYrm >+ 0U, // VMOVUPDYrr >+ 0U, // VMOVUPDYrr_REV >+ 0U, // VMOVUPDZ128mr >+ 29U, // VMOVUPDZ128mrk >+ 0U, // VMOVUPDZ128rm >+ 345U, // VMOVUPDZ128rmk >+ 269U, // VMOVUPDZ128rmkz >+ 0U, // VMOVUPDZ128rr >+ 0U, // VMOVUPDZ128rr_alt >+ 345U, // VMOVUPDZ128rrk >+ 345U, // VMOVUPDZ128rrk_alt >+ 269U, // VMOVUPDZ128rrkz >+ 269U, // VMOVUPDZ128rrkz_alt >+ 0U, // VMOVUPDZ256mr >+ 29U, // VMOVUPDZ256mrk >+ 0U, // VMOVUPDZ256rm >+ 345U, // VMOVUPDZ256rmk >+ 269U, // VMOVUPDZ256rmkz >+ 0U, // VMOVUPDZ256rr >+ 0U, // VMOVUPDZ256rr_alt >+ 345U, // VMOVUPDZ256rrk >+ 345U, // VMOVUPDZ256rrk_alt >+ 269U, // VMOVUPDZ256rrkz >+ 269U, // VMOVUPDZ256rrkz_alt >+ 0U, // VMOVUPDZmr >+ 29U, // VMOVUPDZmrk >+ 0U, // VMOVUPDZrm >+ 345U, // VMOVUPDZrmk >+ 269U, // VMOVUPDZrmkz >+ 0U, // VMOVUPDZrr >+ 0U, // VMOVUPDZrr_alt >+ 345U, // VMOVUPDZrrk >+ 345U, // VMOVUPDZrrk_alt >+ 269U, // VMOVUPDZrrkz >+ 269U, // VMOVUPDZrrkz_alt >+ 0U, // VMOVUPDmr >+ 0U, // VMOVUPDrm >+ 0U, // VMOVUPDrr >+ 0U, // VMOVUPDrr_REV >+ 0U, // VMOVUPSYmr >+ 0U, // VMOVUPSYrm >+ 0U, // VMOVUPSYrr >+ 0U, // VMOVUPSYrr_REV >+ 0U, // VMOVUPSZ128mr >+ 29U, // VMOVUPSZ128mrk >+ 0U, // VMOVUPSZ128rm >+ 345U, // VMOVUPSZ128rmk >+ 269U, // VMOVUPSZ128rmkz >+ 0U, // VMOVUPSZ128rr >+ 0U, // VMOVUPSZ128rr_alt >+ 345U, // VMOVUPSZ128rrk >+ 345U, // VMOVUPSZ128rrk_alt >+ 269U, // VMOVUPSZ128rrkz >+ 269U, // VMOVUPSZ128rrkz_alt >+ 0U, // VMOVUPSZ256mr >+ 29U, // VMOVUPSZ256mrk >+ 0U, // VMOVUPSZ256rm >+ 345U, // VMOVUPSZ256rmk >+ 269U, // VMOVUPSZ256rmkz >+ 0U, // VMOVUPSZ256rr >+ 0U, // VMOVUPSZ256rr_alt >+ 345U, // VMOVUPSZ256rrk >+ 345U, // VMOVUPSZ256rrk_alt >+ 269U, // VMOVUPSZ256rrkz >+ 269U, // VMOVUPSZ256rrkz_alt >+ 0U, // VMOVUPSZmr >+ 29U, // VMOVUPSZmrk >+ 0U, // VMOVUPSZrm >+ 345U, // VMOVUPSZrmk >+ 269U, // VMOVUPSZrmkz >+ 0U, // VMOVUPSZrr >+ 0U, // VMOVUPSZrr_alt >+ 345U, // VMOVUPSZrrk >+ 345U, // VMOVUPSZrrk_alt >+ 269U, // VMOVUPSZrrkz >+ 269U, // VMOVUPSZrrkz_alt >+ 0U, // VMOVUPSmr >+ 0U, // VMOVUPSrm >+ 0U, // VMOVUPSrr >+ 0U, // VMOVUPSrr_REV >+ 0U, // VMOVZPQILo2PQIZrm >+ 0U, // VMOVZPQILo2PQIZrr >+ 0U, // VMOVZPQILo2PQIrm >+ 0U, // VMOVZPQILo2PQIrr >+ 0U, // VMOVZQI2PQIrm >+ 0U, // VMOVZQI2PQIrr >+ 0U, // VMPSADBWYrmi >+ 4U, // VMPSADBWYrri >+ 4U, // VMPSADBWrmi >+ 4U, // VMPSADBWrri >+ 0U, // VMPTRLDm >+ 0U, // VMPTRSTm >+ 0U, // VMREAD32rm >+ 0U, // VMREAD32rr >+ 0U, // VMREAD64rm >+ 0U, // VMREAD64rr >+ 0U, // VMRESUME >+ 0U, // VMRUN32 >+ 0U, // VMRUN64 >+ 0U, // VMSAVE32 >+ 0U, // VMSAVE64 >+ 0U, // VMULPDYrm >+ 0U, // VMULPDYrr >+ 0U, // VMULPDZrm >+ 4U, // VMULPDZrmb >+ 2052U, // VMULPDZrmbk >+ 10244U, // VMULPDZrmbkz >+ 3220U, // VMULPDZrmk >+ 4244U, // VMULPDZrmkz >+ 0U, // VMULPDZrr >+ 5268U, // VMULPDZrrk >+ 4244U, // VMULPDZrrkz >+ 0U, // VMULPDrm >+ 0U, // VMULPDrr >+ 0U, // VMULPSYrm >+ 0U, // VMULPSYrr >+ 0U, // VMULPSZrm >+ 4U, // VMULPSZrmb >+ 2052U, // VMULPSZrmbk >+ 10244U, // VMULPSZrmbkz >+ 3220U, // VMULPSZrmk >+ 4244U, // VMULPSZrmkz >+ 0U, // VMULPSZrr >+ 5268U, // VMULPSZrrk >+ 4244U, // VMULPSZrrkz >+ 0U, // VMULPSrm >+ 0U, // VMULPSrr >+ 4U, // VMULSDZrm >+ 0U, // VMULSDZrr >+ 4U, // VMULSDrm >+ 4U, // VMULSDrm_Int >+ 0U, // VMULSDrr >+ 0U, // VMULSDrr_Int >+ 4U, // VMULSSZrm >+ 0U, // VMULSSZrr >+ 4U, // VMULSSrm >+ 4U, // VMULSSrm_Int >+ 0U, // VMULSSrr >+ 0U, // VMULSSrr_Int >+ 0U, // VMWRITE32rm >+ 0U, // VMWRITE32rr >+ 0U, // VMWRITE64rm >+ 0U, // VMWRITE64rr >+ 0U, // VMXOFF >+ 0U, // VMXON >+ 0U, // VORPDYrm >+ 0U, // VORPDYrr >+ 0U, // VORPDrm >+ 0U, // VORPDrr >+ 0U, // VORPSYrm >+ 0U, // VORPSYrr >+ 0U, // VORPSrm >+ 0U, // VORPSrr >+ 0U, // VPABSBrm128 >+ 0U, // VPABSBrm256 >+ 0U, // VPABSBrr128 >+ 0U, // VPABSBrr256 >+ 0U, // VPABSDZrm >+ 0U, // VPABSDZrmb >+ 3220U, // VPABSDZrmbk >+ 4244U, // VPABSDZrmbkz >+ 333U, // VPABSDZrmk >+ 269U, // VPABSDZrmkz >+ 0U, // VPABSDZrr >+ 333U, // VPABSDZrrk >+ 269U, // VPABSDZrrkz >+ 0U, // VPABSDrm128 >+ 0U, // VPABSDrm256 >+ 0U, // VPABSDrr128 >+ 0U, // VPABSDrr256 >+ 0U, // VPABSQZrm >+ 0U, // VPABSQZrmb >+ 3220U, // VPABSQZrmbk >+ 4244U, // VPABSQZrmbkz >+ 333U, // VPABSQZrmk >+ 269U, // VPABSQZrmkz >+ 0U, // VPABSQZrr >+ 333U, // VPABSQZrrk >+ 269U, // VPABSQZrrkz >+ 0U, // VPABSWrm128 >+ 0U, // VPABSWrm256 >+ 0U, // VPABSWrr128 >+ 0U, // VPABSWrr256 >+ 0U, // VPACKSSDWYrm >+ 0U, // VPACKSSDWYrr >+ 0U, // VPACKSSDWrm >+ 0U, // VPACKSSDWrr >+ 0U, // VPACKSSWBYrm >+ 0U, // VPACKSSWBYrr >+ 0U, // VPACKSSWBrm >+ 0U, // VPACKSSWBrr >+ 0U, // VPACKUSDWYrm >+ 0U, // VPACKUSDWYrr >+ 0U, // VPACKUSDWrm >+ 0U, // VPACKUSDWrr >+ 0U, // VPACKUSWBYrm >+ 0U, // VPACKUSWBYrr >+ 0U, // VPACKUSWBrm >+ 0U, // VPACKUSWBrr >+ 0U, // VPADDBYrm >+ 0U, // VPADDBYrr >+ 0U, // VPADDBrm >+ 0U, // VPADDBrr >+ 0U, // VPADDDYrm >+ 0U, // VPADDDYrr >+ 0U, // VPADDDZrm >+ 4U, // VPADDDZrmb >+ 1U, // VPADDDZrmbk >+ 10244U, // VPADDDZrmbkz >+ 0U, // VPADDDZrmk >+ 4244U, // VPADDDZrmkz >+ 0U, // VPADDDZrr >+ 345U, // VPADDDZrrk >+ 4244U, // VPADDDZrrkz >+ 0U, // VPADDDrm >+ 0U, // VPADDDrr >+ 0U, // VPADDQYrm >+ 0U, // VPADDQYrr >+ 0U, // VPADDQZrm >+ 4U, // VPADDQZrmb >+ 1U, // VPADDQZrmbk >+ 10244U, // VPADDQZrmbkz >+ 0U, // VPADDQZrmk >+ 4244U, // VPADDQZrmkz >+ 0U, // VPADDQZrr >+ 345U, // VPADDQZrrk >+ 4244U, // VPADDQZrrkz >+ 0U, // VPADDQrm >+ 0U, // VPADDQrr >+ 0U, // VPADDSBYrm >+ 0U, // VPADDSBYrr >+ 0U, // VPADDSBrm >+ 0U, // VPADDSBrr >+ 0U, // VPADDSWYrm >+ 0U, // VPADDSWYrr >+ 0U, // VPADDSWrm >+ 0U, // VPADDSWrr >+ 0U, // VPADDUSBYrm >+ 0U, // VPADDUSBYrr >+ 0U, // VPADDUSBrm >+ 0U, // VPADDUSBrr >+ 0U, // VPADDUSWYrm >+ 0U, // VPADDUSWYrr >+ 0U, // VPADDUSWrm >+ 0U, // VPADDUSWrr >+ 0U, // VPADDWYrm >+ 0U, // VPADDWYrr >+ 0U, // VPADDWrm >+ 0U, // VPADDWrr >+ 4U, // VPALIGNR128rm >+ 4U, // VPALIGNR128rr >+ 0U, // VPALIGNR256rm >+ 4U, // VPALIGNR256rr >+ 0U, // VPANDDZrm >+ 4U, // VPANDDZrmb >+ 1U, // VPANDDZrmbk >+ 10244U, // VPANDDZrmbkz >+ 0U, // VPANDDZrmk >+ 4244U, // VPANDDZrmkz >+ 0U, // VPANDDZrr >+ 345U, // VPANDDZrrk >+ 4244U, // VPANDDZrrkz >+ 0U, // VPANDNDZrm >+ 4U, // VPANDNDZrmb >+ 1U, // VPANDNDZrmbk >+ 10244U, // VPANDNDZrmbkz >+ 0U, // VPANDNDZrmk >+ 4244U, // VPANDNDZrmkz >+ 0U, // VPANDNDZrr >+ 345U, // VPANDNDZrrk >+ 4244U, // VPANDNDZrrkz >+ 0U, // VPANDNQZrm >+ 4U, // VPANDNQZrmb >+ 1U, // VPANDNQZrmbk >+ 10244U, // VPANDNQZrmbkz >+ 0U, // VPANDNQZrmk >+ 4244U, // VPANDNQZrmkz >+ 0U, // VPANDNQZrr >+ 345U, // VPANDNQZrrk >+ 4244U, // VPANDNQZrrkz >+ 0U, // VPANDNYrm >+ 0U, // VPANDNYrr >+ 0U, // VPANDNrm >+ 0U, // VPANDNrr >+ 0U, // VPANDQZrm >+ 4U, // VPANDQZrmb >+ 1U, // VPANDQZrmbk >+ 10244U, // VPANDQZrmbkz >+ 0U, // VPANDQZrmk >+ 4244U, // VPANDQZrmkz >+ 0U, // VPANDQZrr >+ 345U, // VPANDQZrrk >+ 4244U, // VPANDQZrrkz >+ 0U, // VPANDYrm >+ 0U, // VPANDYrr >+ 0U, // VPANDrm >+ 0U, // VPANDrr >+ 0U, // VPAVGBYrm >+ 0U, // VPAVGBYrr >+ 0U, // VPAVGBrm >+ 0U, // VPAVGBrr >+ 0U, // VPAVGWYrm >+ 0U, // VPAVGWYrr >+ 0U, // VPAVGWrm >+ 0U, // VPAVGWrr >+ 0U, // VPBLENDDYrmi >+ 4U, // VPBLENDDYrri >+ 4U, // VPBLENDDrmi >+ 4U, // VPBLENDDrri >+ 3220U, // VPBLENDMDZrm >+ 3220U, // VPBLENDMDZrr >+ 3220U, // VPBLENDMQZrm >+ 3220U, // VPBLENDMQZrr >+ 0U, // VPBLENDVBYrm >+ 4U, // VPBLENDVBYrr >+ 4U, // VPBLENDVBrm >+ 4U, // VPBLENDVBrr >+ 0U, // VPBLENDWYrmi >+ 4U, // VPBLENDWYrri >+ 4U, // VPBLENDWrmi >+ 4U, // VPBLENDWrri >+ 0U, // VPBROADCASTBYrm >+ 0U, // VPBROADCASTBYrr >+ 0U, // VPBROADCASTBrm >+ 0U, // VPBROADCASTBrr >+ 0U, // VPBROADCASTDYrm >+ 0U, // VPBROADCASTDYrr >+ 4244U, // VPBROADCASTDZkrm >+ 269U, // VPBROADCASTDZkrr >+ 0U, // VPBROADCASTDZrm >+ 0U, // VPBROADCASTDZrr >+ 269U, // VPBROADCASTDrZkrr >+ 0U, // VPBROADCASTDrZrr >+ 0U, // VPBROADCASTDrm >+ 0U, // VPBROADCASTDrr >+ 0U, // VPBROADCASTMB2Qrr >+ 0U, // VPBROADCASTMW2Drr >+ 0U, // VPBROADCASTQYrm >+ 0U, // VPBROADCASTQYrr >+ 4244U, // VPBROADCASTQZkrm >+ 269U, // VPBROADCASTQZkrr >+ 0U, // VPBROADCASTQZrm >+ 0U, // VPBROADCASTQZrr >+ 269U, // VPBROADCASTQrZkrr >+ 0U, // VPBROADCASTQrZrr >+ 0U, // VPBROADCASTQrm >+ 0U, // VPBROADCASTQrr >+ 0U, // VPBROADCASTWYrm >+ 0U, // VPBROADCASTWYrr >+ 0U, // VPBROADCASTWrm >+ 0U, // VPBROADCASTWrr >+ 4U, // VPCLMULQDQrm >+ 4U, // VPCLMULQDQrr >+ 4U, // VPCMOVmr >+ 0U, // VPCMOVmrY >+ 4U, // VPCMOVrm >+ 4U, // VPCMOVrmY >+ 4U, // VPCMOVrr >+ 4U, // VPCMOVrrY >+ 2U, // VPCMPDZrmi >+ 4U, // VPCMPDZrmi_alt >+ 0U, // VPCMPDZrmik_alt >+ 1156U, // VPCMPDZrri >+ 4U, // VPCMPDZrri_alt >+ 3220U, // VPCMPDZrrik_alt >+ 0U, // VPCMPEQBYrm >+ 0U, // VPCMPEQBYrr >+ 0U, // VPCMPEQBZ128rm >+ 3220U, // VPCMPEQBZ128rmk >+ 0U, // VPCMPEQBZ128rr >+ 3220U, // VPCMPEQBZ128rrk >+ 0U, // VPCMPEQBZ256rm >+ 3220U, // VPCMPEQBZ256rmk >+ 0U, // VPCMPEQBZ256rr >+ 3220U, // VPCMPEQBZ256rrk >+ 0U, // VPCMPEQBZrm >+ 3220U, // VPCMPEQBZrmk >+ 0U, // VPCMPEQBZrr >+ 3220U, // VPCMPEQBZrrk >+ 0U, // VPCMPEQBrm >+ 0U, // VPCMPEQBrr >+ 0U, // VPCMPEQDYrm >+ 0U, // VPCMPEQDYrr >+ 0U, // VPCMPEQDZ128rm >+ 4U, // VPCMPEQDZ128rmb >+ 2052U, // VPCMPEQDZ128rmbk >+ 3220U, // VPCMPEQDZ128rmk >+ 0U, // VPCMPEQDZ128rr >+ 3220U, // VPCMPEQDZ128rrk >+ 0U, // VPCMPEQDZ256rm >+ 4U, // VPCMPEQDZ256rmb >+ 2052U, // VPCMPEQDZ256rmbk >+ 3220U, // VPCMPEQDZ256rmk >+ 0U, // VPCMPEQDZ256rr >+ 3220U, // VPCMPEQDZ256rrk >+ 0U, // VPCMPEQDZrm >+ 4U, // VPCMPEQDZrmb >+ 2052U, // VPCMPEQDZrmbk >+ 3220U, // VPCMPEQDZrmk >+ 0U, // VPCMPEQDZrr >+ 3220U, // VPCMPEQDZrrk >+ 0U, // VPCMPEQDrm >+ 0U, // VPCMPEQDrr >+ 0U, // VPCMPEQQYrm >+ 0U, // VPCMPEQQYrr >+ 0U, // VPCMPEQQZ128rm >+ 4U, // VPCMPEQQZ128rmb >+ 2052U, // VPCMPEQQZ128rmbk >+ 3220U, // VPCMPEQQZ128rmk >+ 0U, // VPCMPEQQZ128rr >+ 3220U, // VPCMPEQQZ128rrk >+ 0U, // VPCMPEQQZ256rm >+ 4U, // VPCMPEQQZ256rmb >+ 2052U, // VPCMPEQQZ256rmbk >+ 3220U, // VPCMPEQQZ256rmk >+ 0U, // VPCMPEQQZ256rr >+ 3220U, // VPCMPEQQZ256rrk >+ 0U, // VPCMPEQQZrm >+ 4U, // VPCMPEQQZrmb >+ 2052U, // VPCMPEQQZrmbk >+ 3220U, // VPCMPEQQZrmk >+ 0U, // VPCMPEQQZrr >+ 3220U, // VPCMPEQQZrrk >+ 0U, // VPCMPEQQrm >+ 0U, // VPCMPEQQrr >+ 0U, // VPCMPEQWYrm >+ 0U, // VPCMPEQWYrr >+ 0U, // VPCMPEQWZ128rm >+ 3220U, // VPCMPEQWZ128rmk >+ 0U, // VPCMPEQWZ128rr >+ 3220U, // VPCMPEQWZ128rrk >+ 0U, // VPCMPEQWZ256rm >+ 3220U, // VPCMPEQWZ256rmk >+ 0U, // VPCMPEQWZ256rr >+ 3220U, // VPCMPEQWZ256rrk >+ 0U, // VPCMPEQWZrm >+ 3220U, // VPCMPEQWZrmk >+ 0U, // VPCMPEQWZrr >+ 3220U, // VPCMPEQWZrrk >+ 0U, // VPCMPEQWrm >+ 0U, // VPCMPEQWrr >+ 0U, // VPCMPESTRIMEM >+ 0U, // VPCMPESTRIREG >+ 0U, // VPCMPESTRIrm >+ 0U, // VPCMPESTRIrr >+ 0U, // VPCMPESTRM128MEM >+ 0U, // VPCMPESTRM128REG >+ 0U, // VPCMPESTRM128rm >+ 0U, // VPCMPESTRM128rr >+ 0U, // VPCMPGTBYrm >+ 0U, // VPCMPGTBYrr >+ 0U, // VPCMPGTBZ128rm >+ 3220U, // VPCMPGTBZ128rmk >+ 0U, // VPCMPGTBZ128rr >+ 3220U, // VPCMPGTBZ128rrk >+ 0U, // VPCMPGTBZ256rm >+ 3220U, // VPCMPGTBZ256rmk >+ 0U, // VPCMPGTBZ256rr >+ 3220U, // VPCMPGTBZ256rrk >+ 0U, // VPCMPGTBZrm >+ 3220U, // VPCMPGTBZrmk >+ 0U, // VPCMPGTBZrr >+ 3220U, // VPCMPGTBZrrk >+ 0U, // VPCMPGTBrm >+ 0U, // VPCMPGTBrr >+ 0U, // VPCMPGTDYrm >+ 0U, // VPCMPGTDYrr >+ 0U, // VPCMPGTDZ128rm >+ 4U, // VPCMPGTDZ128rmb >+ 2052U, // VPCMPGTDZ128rmbk >+ 3220U, // VPCMPGTDZ128rmk >+ 0U, // VPCMPGTDZ128rr >+ 3220U, // VPCMPGTDZ128rrk >+ 0U, // VPCMPGTDZ256rm >+ 4U, // VPCMPGTDZ256rmb >+ 2052U, // VPCMPGTDZ256rmbk >+ 3220U, // VPCMPGTDZ256rmk >+ 0U, // VPCMPGTDZ256rr >+ 3220U, // VPCMPGTDZ256rrk >+ 0U, // VPCMPGTDZrm >+ 4U, // VPCMPGTDZrmb >+ 2052U, // VPCMPGTDZrmbk >+ 3220U, // VPCMPGTDZrmk >+ 0U, // VPCMPGTDZrr >+ 3220U, // VPCMPGTDZrrk >+ 0U, // VPCMPGTDrm >+ 0U, // VPCMPGTDrr >+ 0U, // VPCMPGTQYrm >+ 0U, // VPCMPGTQYrr >+ 0U, // VPCMPGTQZ128rm >+ 4U, // VPCMPGTQZ128rmb >+ 2052U, // VPCMPGTQZ128rmbk >+ 3220U, // VPCMPGTQZ128rmk >+ 0U, // VPCMPGTQZ128rr >+ 3220U, // VPCMPGTQZ128rrk >+ 0U, // VPCMPGTQZ256rm >+ 4U, // VPCMPGTQZ256rmb >+ 2052U, // VPCMPGTQZ256rmbk >+ 3220U, // VPCMPGTQZ256rmk >+ 0U, // VPCMPGTQZ256rr >+ 3220U, // VPCMPGTQZ256rrk >+ 0U, // VPCMPGTQZrm >+ 4U, // VPCMPGTQZrmb >+ 2052U, // VPCMPGTQZrmbk >+ 3220U, // VPCMPGTQZrmk >+ 0U, // VPCMPGTQZrr >+ 3220U, // VPCMPGTQZrrk >+ 0U, // VPCMPGTQrm >+ 0U, // VPCMPGTQrr >+ 0U, // VPCMPGTWYrm >+ 0U, // VPCMPGTWYrr >+ 0U, // VPCMPGTWZ128rm >+ 3220U, // VPCMPGTWZ128rmk >+ 0U, // VPCMPGTWZ128rr >+ 3220U, // VPCMPGTWZ128rrk >+ 0U, // VPCMPGTWZ256rm >+ 3220U, // VPCMPGTWZ256rmk >+ 0U, // VPCMPGTWZ256rr >+ 3220U, // VPCMPGTWZ256rrk >+ 0U, // VPCMPGTWZrm >+ 3220U, // VPCMPGTWZrmk >+ 0U, // VPCMPGTWZrr >+ 3220U, // VPCMPGTWZrrk >+ 0U, // VPCMPGTWrm >+ 0U, // VPCMPGTWrr >+ 0U, // VPCMPISTRIMEM >+ 0U, // VPCMPISTRIREG >+ 0U, // VPCMPISTRIrm >+ 0U, // VPCMPISTRIrr >+ 0U, // VPCMPISTRM128MEM >+ 0U, // VPCMPISTRM128REG >+ 0U, // VPCMPISTRM128rm >+ 0U, // VPCMPISTRM128rr >+ 2U, // VPCMPQZrmi >+ 4U, // VPCMPQZrmi_alt >+ 0U, // VPCMPQZrmik_alt >+ 1156U, // VPCMPQZrri >+ 4U, // VPCMPQZrri_alt >+ 3220U, // VPCMPQZrrik_alt >+ 2U, // VPCMPUDZrmi >+ 4U, // VPCMPUDZrmi_alt >+ 0U, // VPCMPUDZrmik_alt >+ 1156U, // VPCMPUDZrri >+ 4U, // VPCMPUDZrri_alt >+ 3220U, // VPCMPUDZrrik_alt >+ 2U, // VPCMPUQZrmi >+ 4U, // VPCMPUQZrmi_alt >+ 0U, // VPCMPUQZrmik_alt >+ 1156U, // VPCMPUQZrri >+ 4U, // VPCMPUQZrri_alt >+ 3220U, // VPCMPUQZrrik_alt >+ 4U, // VPCOMBmi >+ 4U, // VPCOMBri >+ 4U, // VPCOMDmi >+ 4U, // VPCOMDri >+ 4U, // VPCOMQmi >+ 4U, // VPCOMQri >+ 4U, // VPCOMUBmi >+ 4U, // VPCOMUBri >+ 4U, // VPCOMUDmi >+ 4U, // VPCOMUDri >+ 4U, // VPCOMUQmi >+ 4U, // VPCOMUQri >+ 4U, // VPCOMUWmi >+ 4U, // VPCOMUWri >+ 4U, // VPCOMWmi >+ 4U, // VPCOMWri >+ 0U, // VPCONFLICTDrm >+ 0U, // VPCONFLICTDrmb >+ 3284U, // VPCONFLICTDrmbk >+ 4244U, // VPCONFLICTDrmbkz >+ 345U, // VPCONFLICTDrmk >+ 269U, // VPCONFLICTDrmkz >+ 32U, // VPCONFLICTDrr >+ 345U, // VPCONFLICTDrrk >+ 269U, // VPCONFLICTDrrkz >+ 0U, // VPCONFLICTQrm >+ 0U, // VPCONFLICTQrmb >+ 3284U, // VPCONFLICTQrmbk >+ 4244U, // VPCONFLICTQrmbkz >+ 345U, // VPCONFLICTQrmk >+ 269U, // VPCONFLICTQrmkz >+ 32U, // VPCONFLICTQrr >+ 345U, // VPCONFLICTQrrk >+ 269U, // VPCONFLICTQrrkz >+ 0U, // VPERM2F128rm >+ 4U, // VPERM2F128rr >+ 0U, // VPERM2I128rm >+ 4U, // VPERM2I128rr >+ 0U, // VPERMDYrm >+ 0U, // VPERMDYrr >+ 0U, // VPERMDZrm >+ 0U, // VPERMDZrr >+ 0U, // VPERMI2Drm >+ 0U, // VPERMI2Drmk >+ 0U, // VPERMI2Drmkz >+ 0U, // VPERMI2Drr >+ 345U, // VPERMI2Drrk >+ 473U, // VPERMI2Drrkz >+ 0U, // VPERMI2PDrm >+ 0U, // VPERMI2PDrmk >+ 0U, // VPERMI2PDrmkz >+ 0U, // VPERMI2PDrr >+ 345U, // VPERMI2PDrrk >+ 473U, // VPERMI2PDrrkz >+ 0U, // VPERMI2PSrm >+ 0U, // VPERMI2PSrmk >+ 0U, // VPERMI2PSrmkz >+ 0U, // VPERMI2PSrr >+ 345U, // VPERMI2PSrrk >+ 473U, // VPERMI2PSrrkz >+ 0U, // VPERMI2Qrm >+ 0U, // VPERMI2Qrmk >+ 0U, // VPERMI2Qrmkz >+ 0U, // VPERMI2Qrr >+ 345U, // VPERMI2Qrrk >+ 473U, // VPERMI2Qrrkz >+ 76U, // VPERMIL2PDmr >+ 1U, // VPERMIL2PDmrY >+ 0U, // VPERMIL2PDrm >+ 0U, // VPERMIL2PDrmY >+ 4U, // VPERMIL2PDrr >+ 4U, // VPERMIL2PDrrY >+ 76U, // VPERMIL2PSmr >+ 1U, // VPERMIL2PSmrY >+ 0U, // VPERMIL2PSrm >+ 0U, // VPERMIL2PSrmY >+ 4U, // VPERMIL2PSrr >+ 4U, // VPERMIL2PSrrY >+ 0U, // VPERMILPDYmi >+ 0U, // VPERMILPDYri >+ 0U, // VPERMILPDYrm >+ 0U, // VPERMILPDYrr >+ 0U, // VPERMILPDZmi >+ 0U, // VPERMILPDZri >+ 0U, // VPERMILPDmi >+ 0U, // VPERMILPDri >+ 0U, // VPERMILPDrm >+ 0U, // VPERMILPDrr >+ 0U, // VPERMILPSYmi >+ 0U, // VPERMILPSYri >+ 0U, // VPERMILPSYrm >+ 0U, // VPERMILPSYrr >+ 0U, // VPERMILPSZmi >+ 0U, // VPERMILPSZri >+ 0U, // VPERMILPSmi >+ 0U, // VPERMILPSri >+ 0U, // VPERMILPSrm >+ 0U, // VPERMILPSrr >+ 0U, // VPERMPDYmi >+ 0U, // VPERMPDYri >+ 0U, // VPERMPDZmi >+ 0U, // VPERMPDZri >+ 0U, // VPERMPDZrm >+ 0U, // VPERMPDZrr >+ 0U, // VPERMPSYrm >+ 0U, // VPERMPSYrr >+ 0U, // VPERMPSZrm >+ 0U, // VPERMPSZrr >+ 0U, // VPERMQYmi >+ 0U, // VPERMQYri >+ 0U, // VPERMQZmi >+ 0U, // VPERMQZri >+ 0U, // VPERMQZrm >+ 0U, // VPERMQZrr >+ 0U, // VPERMT2Drm >+ 0U, // VPERMT2Drmk >+ 0U, // VPERMT2Drmkz >+ 0U, // VPERMT2Drr >+ 345U, // VPERMT2Drrk >+ 473U, // VPERMT2Drrkz >+ 0U, // VPERMT2PDrm >+ 0U, // VPERMT2PDrmk >+ 0U, // VPERMT2PDrmkz >+ 0U, // VPERMT2PDrr >+ 345U, // VPERMT2PDrrk >+ 473U, // VPERMT2PDrrkz >+ 0U, // VPERMT2PSrm >+ 0U, // VPERMT2PSrmk >+ 0U, // VPERMT2PSrmkz >+ 0U, // VPERMT2PSrr >+ 345U, // VPERMT2PSrrk >+ 473U, // VPERMT2PSrrkz >+ 0U, // VPERMT2Qrm >+ 0U, // VPERMT2Qrmk >+ 0U, // VPERMT2Qrmkz >+ 0U, // VPERMT2Qrr >+ 345U, // VPERMT2Qrrk >+ 473U, // VPERMT2Qrrkz >+ 1U, // VPEXTRBmr >+ 0U, // VPEXTRBrr >+ 1U, // VPEXTRDmr >+ 0U, // VPEXTRDrr >+ 1U, // VPEXTRQmr >+ 0U, // VPEXTRQrr >+ 1U, // VPEXTRWmr >+ 0U, // VPEXTRWri >+ 0U, // VPEXTRWrr_REV >+ 0U, // VPGATHERDDYrm >+ 404U, // VPGATHERDDZrm >+ 0U, // VPGATHERDDrm >+ 0U, // VPGATHERDQYrm >+ 404U, // VPGATHERDQZrm >+ 0U, // VPGATHERDQrm >+ 0U, // VPGATHERQDYrm >+ 404U, // VPGATHERQDZrm >+ 0U, // VPGATHERQDrm >+ 0U, // VPGATHERQQYrm >+ 404U, // VPGATHERQQZrm >+ 0U, // VPGATHERQQrm >+ 0U, // VPHADDBDrm >+ 0U, // VPHADDBDrr >+ 0U, // VPHADDBQrm >+ 0U, // VPHADDBQrr >+ 0U, // VPHADDBWrm >+ 0U, // VPHADDBWrr >+ 0U, // VPHADDDQrm >+ 0U, // VPHADDDQrr >+ 0U, // VPHADDDYrm >+ 0U, // VPHADDDYrr >+ 0U, // VPHADDDrm >+ 0U, // VPHADDDrr >+ 0U, // VPHADDSWrm128 >+ 0U, // VPHADDSWrm256 >+ 0U, // VPHADDSWrr128 >+ 0U, // VPHADDSWrr256 >+ 0U, // VPHADDUBDrm >+ 0U, // VPHADDUBDrr >+ 0U, // VPHADDUBQrm >+ 0U, // VPHADDUBQrr >+ 0U, // VPHADDUBWrm >+ 0U, // VPHADDUBWrr >+ 0U, // VPHADDUDQrm >+ 0U, // VPHADDUDQrr >+ 0U, // VPHADDUWDrm >+ 0U, // VPHADDUWDrr >+ 0U, // VPHADDUWQrm >+ 0U, // VPHADDUWQrr >+ 0U, // VPHADDWDrm >+ 0U, // VPHADDWDrr >+ 0U, // VPHADDWQrm >+ 0U, // VPHADDWQrr >+ 0U, // VPHADDWYrm >+ 0U, // VPHADDWYrr >+ 0U, // VPHADDWrm >+ 0U, // VPHADDWrr >+ 0U, // VPHMINPOSUWrm128 >+ 0U, // VPHMINPOSUWrr128 >+ 0U, // VPHSUBBWrm >+ 0U, // VPHSUBBWrr >+ 0U, // VPHSUBDQrm >+ 0U, // VPHSUBDQrr >+ 0U, // VPHSUBDYrm >+ 0U, // VPHSUBDYrr >+ 0U, // VPHSUBDrm >+ 0U, // VPHSUBDrr >+ 0U, // VPHSUBSWrm128 >+ 0U, // VPHSUBSWrm256 >+ 0U, // VPHSUBSWrr128 >+ 0U, // VPHSUBSWrr256 >+ 0U, // VPHSUBWDrm >+ 0U, // VPHSUBWDrr >+ 0U, // VPHSUBWYrm >+ 0U, // VPHSUBWYrr >+ 0U, // VPHSUBWrm >+ 0U, // VPHSUBWrr >+ 4U, // VPINSRBrm >+ 4U, // VPINSRBrr >+ 4U, // VPINSRDrm >+ 4U, // VPINSRDrr >+ 4U, // VPINSRQrm >+ 4U, // VPINSRQrr >+ 4U, // VPINSRWrmi >+ 4U, // VPINSRWrri >+ 0U, // VPLZCNTDrm >+ 0U, // VPLZCNTDrmb >+ 3284U, // VPLZCNTDrmbk >+ 4244U, // VPLZCNTDrmbkz >+ 345U, // VPLZCNTDrmk >+ 269U, // VPLZCNTDrmkz >+ 32U, // VPLZCNTDrr >+ 345U, // VPLZCNTDrrk >+ 269U, // VPLZCNTDrrkz >+ 0U, // VPLZCNTQrm >+ 0U, // VPLZCNTQrmb >+ 3284U, // VPLZCNTQrmbk >+ 4244U, // VPLZCNTQrmbkz >+ 345U, // VPLZCNTQrmk >+ 269U, // VPLZCNTQrmkz >+ 32U, // VPLZCNTQrr >+ 345U, // VPLZCNTQrrk >+ 269U, // VPLZCNTQrrkz >+ 4U, // VPMACSDDrm >+ 4U, // VPMACSDDrr >+ 4U, // VPMACSDQHrm >+ 4U, // VPMACSDQHrr >+ 4U, // VPMACSDQLrm >+ 4U, // VPMACSDQLrr >+ 4U, // VPMACSSDDrm >+ 4U, // VPMACSSDDrr >+ 4U, // VPMACSSDQHrm >+ 4U, // VPMACSSDQHrr >+ 4U, // VPMACSSDQLrm >+ 4U, // VPMACSSDQLrr >+ 4U, // VPMACSSWDrm >+ 4U, // VPMACSSWDrr >+ 4U, // VPMACSSWWrm >+ 4U, // VPMACSSWWrr >+ 4U, // VPMACSWDrm >+ 4U, // VPMACSWDrr >+ 4U, // VPMACSWWrm >+ 4U, // VPMACSWWrr >+ 4U, // VPMADCSSWDrm >+ 4U, // VPMADCSSWDrr >+ 4U, // VPMADCSWDrm >+ 4U, // VPMADCSWDrr >+ 0U, // VPMADDUBSWrm128 >+ 0U, // VPMADDUBSWrm256 >+ 0U, // VPMADDUBSWrr128 >+ 0U, // VPMADDUBSWrr256 >+ 0U, // VPMADDWDYrm >+ 0U, // VPMADDWDYrr >+ 0U, // VPMADDWDrm >+ 0U, // VPMADDWDrr >+ 1U, // VPMASKMOVDYmr >+ 0U, // VPMASKMOVDYrm >+ 1U, // VPMASKMOVDmr >+ 0U, // VPMASKMOVDrm >+ 1U, // VPMASKMOVQYmr >+ 0U, // VPMASKMOVQYrm >+ 1U, // VPMASKMOVQmr >+ 0U, // VPMASKMOVQrm >+ 0U, // VPMAXSBYrm >+ 0U, // VPMAXSBYrr >+ 0U, // VPMAXSBrm >+ 0U, // VPMAXSBrr >+ 0U, // VPMAXSDYrm >+ 0U, // VPMAXSDYrr >+ 0U, // VPMAXSDZrm >+ 4U, // VPMAXSDZrmb >+ 1U, // VPMAXSDZrmbk >+ 10244U, // VPMAXSDZrmbkz >+ 0U, // VPMAXSDZrmk >+ 4244U, // VPMAXSDZrmkz >+ 0U, // VPMAXSDZrr >+ 345U, // VPMAXSDZrrk >+ 4244U, // VPMAXSDZrrkz >+ 0U, // VPMAXSDrm >+ 0U, // VPMAXSDrr >+ 0U, // VPMAXSQZrm >+ 4U, // VPMAXSQZrmb >+ 1U, // VPMAXSQZrmbk >+ 10244U, // VPMAXSQZrmbkz >+ 0U, // VPMAXSQZrmk >+ 4244U, // VPMAXSQZrmkz >+ 0U, // VPMAXSQZrr >+ 345U, // VPMAXSQZrrk >+ 4244U, // VPMAXSQZrrkz >+ 0U, // VPMAXSWYrm >+ 0U, // VPMAXSWYrr >+ 0U, // VPMAXSWrm >+ 0U, // VPMAXSWrr >+ 0U, // VPMAXUBYrm >+ 0U, // VPMAXUBYrr >+ 0U, // VPMAXUBrm >+ 0U, // VPMAXUBrr >+ 0U, // VPMAXUDYrm >+ 0U, // VPMAXUDYrr >+ 0U, // VPMAXUDZrm >+ 4U, // VPMAXUDZrmb >+ 1U, // VPMAXUDZrmbk >+ 10244U, // VPMAXUDZrmbkz >+ 0U, // VPMAXUDZrmk >+ 4244U, // VPMAXUDZrmkz >+ 0U, // VPMAXUDZrr >+ 345U, // VPMAXUDZrrk >+ 4244U, // VPMAXUDZrrkz >+ 0U, // VPMAXUDrm >+ 0U, // VPMAXUDrr >+ 0U, // VPMAXUQZrm >+ 4U, // VPMAXUQZrmb >+ 1U, // VPMAXUQZrmbk >+ 10244U, // VPMAXUQZrmbkz >+ 0U, // VPMAXUQZrmk >+ 4244U, // VPMAXUQZrmkz >+ 0U, // VPMAXUQZrr >+ 345U, // VPMAXUQZrrk >+ 4244U, // VPMAXUQZrrkz >+ 0U, // VPMAXUWYrm >+ 0U, // VPMAXUWYrr >+ 0U, // VPMAXUWrm >+ 0U, // VPMAXUWrr >+ 0U, // VPMINSBYrm >+ 0U, // VPMINSBYrr >+ 0U, // VPMINSBrm >+ 0U, // VPMINSBrr >+ 0U, // VPMINSDYrm >+ 0U, // VPMINSDYrr >+ 0U, // VPMINSDZrm >+ 4U, // VPMINSDZrmb >+ 1U, // VPMINSDZrmbk >+ 10244U, // VPMINSDZrmbkz >+ 0U, // VPMINSDZrmk >+ 4244U, // VPMINSDZrmkz >+ 0U, // VPMINSDZrr >+ 345U, // VPMINSDZrrk >+ 4244U, // VPMINSDZrrkz >+ 0U, // VPMINSDrm >+ 0U, // VPMINSDrr >+ 0U, // VPMINSQZrm >+ 4U, // VPMINSQZrmb >+ 1U, // VPMINSQZrmbk >+ 10244U, // VPMINSQZrmbkz >+ 0U, // VPMINSQZrmk >+ 4244U, // VPMINSQZrmkz >+ 0U, // VPMINSQZrr >+ 345U, // VPMINSQZrrk >+ 4244U, // VPMINSQZrrkz >+ 0U, // VPMINSWYrm >+ 0U, // VPMINSWYrr >+ 0U, // VPMINSWrm >+ 0U, // VPMINSWrr >+ 0U, // VPMINUBYrm >+ 0U, // VPMINUBYrr >+ 0U, // VPMINUBrm >+ 0U, // VPMINUBrr >+ 0U, // VPMINUDYrm >+ 0U, // VPMINUDYrr >+ 0U, // VPMINUDZrm >+ 4U, // VPMINUDZrmb >+ 1U, // VPMINUDZrmbk >+ 10244U, // VPMINUDZrmbkz >+ 0U, // VPMINUDZrmk >+ 4244U, // VPMINUDZrmkz >+ 0U, // VPMINUDZrr >+ 345U, // VPMINUDZrrk >+ 4244U, // VPMINUDZrrkz >+ 0U, // VPMINUDrm >+ 0U, // VPMINUDrr >+ 0U, // VPMINUQZrm >+ 4U, // VPMINUQZrmb >+ 1U, // VPMINUQZrmbk >+ 10244U, // VPMINUQZrmbkz >+ 0U, // VPMINUQZrmk >+ 4244U, // VPMINUQZrmkz >+ 0U, // VPMINUQZrr >+ 345U, // VPMINUQZrrk >+ 4244U, // VPMINUQZrrkz >+ 0U, // VPMINUWYrm >+ 0U, // VPMINUWYrr >+ 0U, // VPMINUWrm >+ 0U, // VPMINUWrr >+ 0U, // VPMOVDBmr >+ 29U, // VPMOVDBmrk >+ 0U, // VPMOVDBrr >+ 333U, // VPMOVDBrrk >+ 269U, // VPMOVDBrrkz >+ 0U, // VPMOVDWmr >+ 29U, // VPMOVDWmrk >+ 0U, // VPMOVDWrr >+ 333U, // VPMOVDWrrk >+ 269U, // VPMOVDWrrkz >+ 0U, // VPMOVMSKBYrr >+ 0U, // VPMOVMSKBrr >+ 0U, // VPMOVQBmr >+ 29U, // VPMOVQBmrk >+ 0U, // VPMOVQBrr >+ 333U, // VPMOVQBrrk >+ 269U, // VPMOVQBrrkz >+ 0U, // VPMOVQDmr >+ 29U, // VPMOVQDmrk >+ 0U, // VPMOVQDrr >+ 333U, // VPMOVQDrrk >+ 269U, // VPMOVQDrrkz >+ 0U, // VPMOVQWmr >+ 29U, // VPMOVQWmrk >+ 0U, // VPMOVQWrr >+ 333U, // VPMOVQWrrk >+ 269U, // VPMOVQWrrkz >+ 0U, // VPMOVSDBmr >+ 29U, // VPMOVSDBmrk >+ 0U, // VPMOVSDBrr >+ 333U, // VPMOVSDBrrk >+ 269U, // VPMOVSDBrrkz >+ 0U, // VPMOVSDWmr >+ 29U, // VPMOVSDWmrk >+ 0U, // VPMOVSDWrr >+ 333U, // VPMOVSDWrrk >+ 269U, // VPMOVSDWrrkz >+ 0U, // VPMOVSQBmr >+ 29U, // VPMOVSQBmrk >+ 0U, // VPMOVSQBrr >+ 333U, // VPMOVSQBrrk >+ 269U, // VPMOVSQBrrkz >+ 0U, // VPMOVSQDmr >+ 29U, // VPMOVSQDmrk >+ 0U, // VPMOVSQDrr >+ 333U, // VPMOVSQDrrk >+ 269U, // VPMOVSQDrrkz >+ 0U, // VPMOVSQWmr >+ 29U, // VPMOVSQWmrk >+ 0U, // VPMOVSQWrr >+ 333U, // VPMOVSQWrrk >+ 269U, // VPMOVSQWrrkz >+ 0U, // VPMOVSXBDYrm >+ 0U, // VPMOVSXBDYrr >+ 0U, // VPMOVSXBDZrm >+ 525U, // VPMOVSXBDZrmk >+ 269U, // VPMOVSXBDZrmkz >+ 0U, // VPMOVSXBDZrr >+ 525U, // VPMOVSXBDZrrk >+ 269U, // VPMOVSXBDZrrkz >+ 0U, // VPMOVSXBDrm >+ 0U, // VPMOVSXBDrr >+ 0U, // VPMOVSXBQYrm >+ 0U, // VPMOVSXBQYrr >+ 0U, // VPMOVSXBQZrm >+ 525U, // VPMOVSXBQZrmk >+ 269U, // VPMOVSXBQZrmkz >+ 0U, // VPMOVSXBQZrr >+ 525U, // VPMOVSXBQZrrk >+ 269U, // VPMOVSXBQZrrkz >+ 0U, // VPMOVSXBQrm >+ 0U, // VPMOVSXBQrr >+ 0U, // VPMOVSXBWYrm >+ 0U, // VPMOVSXBWYrr >+ 0U, // VPMOVSXBWrm >+ 0U, // VPMOVSXBWrr >+ 0U, // VPMOVSXDQYrm >+ 0U, // VPMOVSXDQYrr >+ 0U, // VPMOVSXDQZrm >+ 525U, // VPMOVSXDQZrmk >+ 269U, // VPMOVSXDQZrmkz >+ 0U, // VPMOVSXDQZrr >+ 525U, // VPMOVSXDQZrrk >+ 269U, // VPMOVSXDQZrrkz >+ 0U, // VPMOVSXDQrm >+ 0U, // VPMOVSXDQrr >+ 0U, // VPMOVSXWDYrm >+ 0U, // VPMOVSXWDYrr >+ 0U, // VPMOVSXWDZrm >+ 525U, // VPMOVSXWDZrmk >+ 269U, // VPMOVSXWDZrmkz >+ 0U, // VPMOVSXWDZrr >+ 525U, // VPMOVSXWDZrrk >+ 269U, // VPMOVSXWDZrrkz >+ 0U, // VPMOVSXWDrm >+ 0U, // VPMOVSXWDrr >+ 0U, // VPMOVSXWQYrm >+ 0U, // VPMOVSXWQYrr >+ 0U, // VPMOVSXWQZrm >+ 525U, // VPMOVSXWQZrmk >+ 269U, // VPMOVSXWQZrmkz >+ 0U, // VPMOVSXWQZrr >+ 525U, // VPMOVSXWQZrrk >+ 269U, // VPMOVSXWQZrrkz >+ 0U, // VPMOVSXWQrm >+ 0U, // VPMOVSXWQrr >+ 0U, // VPMOVUSDBmr >+ 29U, // VPMOVUSDBmrk >+ 0U, // VPMOVUSDBrr >+ 333U, // VPMOVUSDBrrk >+ 269U, // VPMOVUSDBrrkz >+ 0U, // VPMOVUSDWmr >+ 29U, // VPMOVUSDWmrk >+ 0U, // VPMOVUSDWrr >+ 333U, // VPMOVUSDWrrk >+ 269U, // VPMOVUSDWrrkz >+ 0U, // VPMOVUSQBmr >+ 29U, // VPMOVUSQBmrk >+ 0U, // VPMOVUSQBrr >+ 333U, // VPMOVUSQBrrk >+ 269U, // VPMOVUSQBrrkz >+ 0U, // VPMOVUSQDmr >+ 29U, // VPMOVUSQDmrk >+ 0U, // VPMOVUSQDrr >+ 333U, // VPMOVUSQDrrk >+ 269U, // VPMOVUSQDrrkz >+ 0U, // VPMOVUSQWmr >+ 29U, // VPMOVUSQWmrk >+ 0U, // VPMOVUSQWrr >+ 333U, // VPMOVUSQWrrk >+ 269U, // VPMOVUSQWrrkz >+ 0U, // VPMOVZXBDYrm >+ 0U, // VPMOVZXBDYrr >+ 0U, // VPMOVZXBDZrm >+ 525U, // VPMOVZXBDZrmk >+ 269U, // VPMOVZXBDZrmkz >+ 0U, // VPMOVZXBDZrr >+ 525U, // VPMOVZXBDZrrk >+ 269U, // VPMOVZXBDZrrkz >+ 0U, // VPMOVZXBDrm >+ 0U, // VPMOVZXBDrr >+ 0U, // VPMOVZXBQYrm >+ 0U, // VPMOVZXBQYrr >+ 0U, // VPMOVZXBQZrm >+ 525U, // VPMOVZXBQZrmk >+ 269U, // VPMOVZXBQZrmkz >+ 0U, // VPMOVZXBQZrr >+ 525U, // VPMOVZXBQZrrk >+ 269U, // VPMOVZXBQZrrkz >+ 0U, // VPMOVZXBQrm >+ 0U, // VPMOVZXBQrr >+ 0U, // VPMOVZXBWYrm >+ 0U, // VPMOVZXBWYrr >+ 0U, // VPMOVZXBWrm >+ 0U, // VPMOVZXBWrr >+ 0U, // VPMOVZXDQYrm >+ 0U, // VPMOVZXDQYrr >+ 0U, // VPMOVZXDQZrm >+ 525U, // VPMOVZXDQZrmk >+ 269U, // VPMOVZXDQZrmkz >+ 0U, // VPMOVZXDQZrr >+ 525U, // VPMOVZXDQZrrk >+ 269U, // VPMOVZXDQZrrkz >+ 0U, // VPMOVZXDQrm >+ 0U, // VPMOVZXDQrr >+ 0U, // VPMOVZXWDYrm >+ 0U, // VPMOVZXWDYrr >+ 0U, // VPMOVZXWDZrm >+ 525U, // VPMOVZXWDZrmk >+ 269U, // VPMOVZXWDZrmkz >+ 0U, // VPMOVZXWDZrr >+ 525U, // VPMOVZXWDZrrk >+ 269U, // VPMOVZXWDZrrkz >+ 0U, // VPMOVZXWDrm >+ 0U, // VPMOVZXWDrr >+ 0U, // VPMOVZXWQYrm >+ 0U, // VPMOVZXWQYrr >+ 0U, // VPMOVZXWQZrm >+ 525U, // VPMOVZXWQZrmk >+ 269U, // VPMOVZXWQZrmkz >+ 0U, // VPMOVZXWQZrr >+ 525U, // VPMOVZXWQZrrk >+ 269U, // VPMOVZXWQZrrkz >+ 0U, // VPMOVZXWQrm >+ 0U, // VPMOVZXWQrr >+ 0U, // VPMULDQYrm >+ 0U, // VPMULDQYrr >+ 0U, // VPMULDQZrm >+ 4U, // VPMULDQZrmb >+ 2052U, // VPMULDQZrmbk >+ 10244U, // VPMULDQZrmbkz >+ 3220U, // VPMULDQZrmk >+ 4244U, // VPMULDQZrmkz >+ 0U, // VPMULDQZrr >+ 3220U, // VPMULDQZrrk >+ 4244U, // VPMULDQZrrkz >+ 0U, // VPMULDQrm >+ 0U, // VPMULDQrr >+ 0U, // VPMULHRSWrm128 >+ 0U, // VPMULHRSWrm256 >+ 0U, // VPMULHRSWrr128 >+ 0U, // VPMULHRSWrr256 >+ 0U, // VPMULHUWYrm >+ 0U, // VPMULHUWYrr >+ 0U, // VPMULHUWrm >+ 0U, // VPMULHUWrr >+ 0U, // VPMULHWYrm >+ 0U, // VPMULHWYrr >+ 0U, // VPMULHWrm >+ 0U, // VPMULHWrr >+ 0U, // VPMULLDYrm >+ 0U, // VPMULLDYrr >+ 0U, // VPMULLDZrm >+ 4U, // VPMULLDZrmb >+ 1U, // VPMULLDZrmbk >+ 10244U, // VPMULLDZrmbkz >+ 0U, // VPMULLDZrmk >+ 4244U, // VPMULLDZrmkz >+ 0U, // VPMULLDZrr >+ 345U, // VPMULLDZrrk >+ 4244U, // VPMULLDZrrkz >+ 0U, // VPMULLDrm >+ 0U, // VPMULLDrr >+ 0U, // VPMULLWYrm >+ 0U, // VPMULLWYrr >+ 0U, // VPMULLWrm >+ 0U, // VPMULLWrr >+ 0U, // VPMULUDQYrm >+ 0U, // VPMULUDQYrr >+ 0U, // VPMULUDQZrm >+ 4U, // VPMULUDQZrmb >+ 2052U, // VPMULUDQZrmbk >+ 10244U, // VPMULUDQZrmbkz >+ 3220U, // VPMULUDQZrmk >+ 4244U, // VPMULUDQZrmkz >+ 0U, // VPMULUDQZrr >+ 3220U, // VPMULUDQZrrk >+ 4244U, // VPMULUDQZrrkz >+ 0U, // VPMULUDQrm >+ 0U, // VPMULUDQrr >+ 0U, // VPORDZrm >+ 4U, // VPORDZrmb >+ 1U, // VPORDZrmbk >+ 10244U, // VPORDZrmbkz >+ 0U, // VPORDZrmk >+ 4244U, // VPORDZrmkz >+ 0U, // VPORDZrr >+ 345U, // VPORDZrrk >+ 4244U, // VPORDZrrkz >+ 0U, // VPORQZrm >+ 4U, // VPORQZrmb >+ 1U, // VPORQZrmbk >+ 10244U, // VPORQZrmbkz >+ 0U, // VPORQZrmk >+ 4244U, // VPORQZrmkz >+ 0U, // VPORQZrr >+ 345U, // VPORQZrrk >+ 4244U, // VPORQZrrkz >+ 0U, // VPORYrm >+ 0U, // VPORYrr >+ 0U, // VPORrm >+ 0U, // VPORrr >+ 4U, // VPPERMmr >+ 4U, // VPPERMrm >+ 4U, // VPPERMrr >+ 0U, // VPROTBmi >+ 0U, // VPROTBmr >+ 0U, // VPROTBri >+ 0U, // VPROTBrm >+ 0U, // VPROTBrr >+ 0U, // VPROTDmi >+ 0U, // VPROTDmr >+ 0U, // VPROTDri >+ 0U, // VPROTDrm >+ 0U, // VPROTDrr >+ 0U, // VPROTQmi >+ 0U, // VPROTQmr >+ 0U, // VPROTQri >+ 0U, // VPROTQrm >+ 0U, // VPROTQrr >+ 0U, // VPROTWmi >+ 0U, // VPROTWmr >+ 0U, // VPROTWri >+ 0U, // VPROTWrm >+ 0U, // VPROTWrr >+ 0U, // VPSADBWYrm >+ 0U, // VPSADBWYrr >+ 0U, // VPSADBWrm >+ 0U, // VPSADBWrr >+ 37U, // VPSCATTERDDZmr >+ 37U, // VPSCATTERDQZmr >+ 37U, // VPSCATTERQDZmr >+ 37U, // VPSCATTERQQZmr >+ 0U, // VPSHABmr >+ 0U, // VPSHABrm >+ 0U, // VPSHABrr >+ 0U, // VPSHADmr >+ 0U, // VPSHADrm >+ 0U, // VPSHADrr >+ 0U, // VPSHAQmr >+ 0U, // VPSHAQrm >+ 0U, // VPSHAQrr >+ 0U, // VPSHAWmr >+ 0U, // VPSHAWrm >+ 0U, // VPSHAWrr >+ 0U, // VPSHLBmr >+ 0U, // VPSHLBrm >+ 0U, // VPSHLBrr >+ 0U, // VPSHLDmr >+ 0U, // VPSHLDrm >+ 0U, // VPSHLDrr >+ 0U, // VPSHLQmr >+ 0U, // VPSHLQrm >+ 0U, // VPSHLQrr >+ 0U, // VPSHLWmr >+ 0U, // VPSHLWrm >+ 0U, // VPSHLWrr >+ 0U, // VPSHUFBYrm >+ 0U, // VPSHUFBYrr >+ 0U, // VPSHUFBrm >+ 0U, // VPSHUFBrr >+ 0U, // VPSHUFDYmi >+ 0U, // VPSHUFDYri >+ 0U, // VPSHUFDZmi >+ 0U, // VPSHUFDZri >+ 0U, // VPSHUFDmi >+ 0U, // VPSHUFDri >+ 0U, // VPSHUFHWYmi >+ 0U, // VPSHUFHWYri >+ 0U, // VPSHUFHWmi >+ 0U, // VPSHUFHWri >+ 0U, // VPSHUFLWYmi >+ 0U, // VPSHUFLWYri >+ 0U, // VPSHUFLWmi >+ 0U, // VPSHUFLWri >+ 0U, // VPSIGNBYrm >+ 0U, // VPSIGNBYrr >+ 0U, // VPSIGNBrm >+ 0U, // VPSIGNBrr >+ 0U, // VPSIGNDYrm >+ 0U, // VPSIGNDYrr >+ 0U, // VPSIGNDrm >+ 0U, // VPSIGNDrr >+ 0U, // VPSIGNWYrm >+ 0U, // VPSIGNWYrr >+ 0U, // VPSIGNWrm >+ 0U, // VPSIGNWrr >+ 0U, // VPSLLDQYri >+ 0U, // VPSLLDQri >+ 0U, // VPSLLDYri >+ 0U, // VPSLLDYrm >+ 0U, // VPSLLDYrr >+ 0U, // VPSLLDZmi >+ 3220U, // VPSLLDZmik >+ 0U, // VPSLLDZri >+ 3220U, // VPSLLDZrik >+ 0U, // VPSLLDZrm >+ 3220U, // VPSLLDZrmk >+ 0U, // VPSLLDZrr >+ 3220U, // VPSLLDZrrk >+ 0U, // VPSLLDri >+ 0U, // VPSLLDrm >+ 0U, // VPSLLDrr >+ 0U, // VPSLLQYri >+ 0U, // VPSLLQYrm >+ 0U, // VPSLLQYrr >+ 0U, // VPSLLQZmi >+ 3220U, // VPSLLQZmik >+ 0U, // VPSLLQZri >+ 3220U, // VPSLLQZrik >+ 0U, // VPSLLQZrm >+ 3220U, // VPSLLQZrmk >+ 0U, // VPSLLQZrr >+ 3220U, // VPSLLQZrrk >+ 0U, // VPSLLQri >+ 0U, // VPSLLQrm >+ 0U, // VPSLLQrr >+ 0U, // VPSLLVDYrm >+ 0U, // VPSLLVDYrr >+ 0U, // VPSLLVDZrm >+ 0U, // VPSLLVDZrr >+ 0U, // VPSLLVDrm >+ 0U, // VPSLLVDrr >+ 0U, // VPSLLVQYrm >+ 0U, // VPSLLVQYrr >+ 0U, // VPSLLVQZrm >+ 0U, // VPSLLVQZrr >+ 0U, // VPSLLVQrm >+ 0U, // VPSLLVQrr >+ 0U, // VPSLLWYri >+ 0U, // VPSLLWYrm >+ 0U, // VPSLLWYrr >+ 0U, // VPSLLWri >+ 0U, // VPSLLWrm >+ 0U, // VPSLLWrr >+ 0U, // VPSRADYri >+ 0U, // VPSRADYrm >+ 0U, // VPSRADYrr >+ 0U, // VPSRADZmi >+ 3220U, // VPSRADZmik >+ 0U, // VPSRADZri >+ 3220U, // VPSRADZrik >+ 0U, // VPSRADZrm >+ 3220U, // VPSRADZrmk >+ 0U, // VPSRADZrr >+ 3220U, // VPSRADZrrk >+ 0U, // VPSRADri >+ 0U, // VPSRADrm >+ 0U, // VPSRADrr >+ 0U, // VPSRAQZmi >+ 3220U, // VPSRAQZmik >+ 0U, // VPSRAQZri >+ 3220U, // VPSRAQZrik >+ 0U, // VPSRAQZrm >+ 3220U, // VPSRAQZrmk >+ 0U, // VPSRAQZrr >+ 3220U, // VPSRAQZrrk >+ 0U, // VPSRAVDYrm >+ 0U, // VPSRAVDYrr >+ 0U, // VPSRAVDZrm >+ 0U, // VPSRAVDZrr >+ 0U, // VPSRAVDrm >+ 0U, // VPSRAVDrr >+ 0U, // VPSRAVQZrm >+ 0U, // VPSRAVQZrr >+ 0U, // VPSRAWYri >+ 0U, // VPSRAWYrm >+ 0U, // VPSRAWYrr >+ 0U, // VPSRAWri >+ 0U, // VPSRAWrm >+ 0U, // VPSRAWrr >+ 0U, // VPSRLDQYri >+ 0U, // VPSRLDQri >+ 0U, // VPSRLDYri >+ 0U, // VPSRLDYrm >+ 0U, // VPSRLDYrr >+ 0U, // VPSRLDZmi >+ 3220U, // VPSRLDZmik >+ 0U, // VPSRLDZri >+ 3220U, // VPSRLDZrik >+ 0U, // VPSRLDZrm >+ 3220U, // VPSRLDZrmk >+ 0U, // VPSRLDZrr >+ 3220U, // VPSRLDZrrk >+ 0U, // VPSRLDri >+ 0U, // VPSRLDrm >+ 0U, // VPSRLDrr >+ 0U, // VPSRLQYri >+ 0U, // VPSRLQYrm >+ 0U, // VPSRLQYrr >+ 0U, // VPSRLQZmi >+ 3220U, // VPSRLQZmik >+ 0U, // VPSRLQZri >+ 3220U, // VPSRLQZrik >+ 0U, // VPSRLQZrm >+ 3220U, // VPSRLQZrmk >+ 0U, // VPSRLQZrr >+ 3220U, // VPSRLQZrrk >+ 0U, // VPSRLQri >+ 0U, // VPSRLQrm >+ 0U, // VPSRLQrr >+ 0U, // VPSRLVDYrm >+ 0U, // VPSRLVDYrr >+ 0U, // VPSRLVDZrm >+ 0U, // VPSRLVDZrr >+ 0U, // VPSRLVDrm >+ 0U, // VPSRLVDrr >+ 0U, // VPSRLVQYrm >+ 0U, // VPSRLVQYrr >+ 0U, // VPSRLVQZrm >+ 0U, // VPSRLVQZrr >+ 0U, // VPSRLVQrm >+ 0U, // VPSRLVQrr >+ 0U, // VPSRLWYri >+ 0U, // VPSRLWYrm >+ 0U, // VPSRLWYrr >+ 0U, // VPSRLWri >+ 0U, // VPSRLWrm >+ 0U, // VPSRLWrr >+ 0U, // VPSUBBYrm >+ 0U, // VPSUBBYrr >+ 0U, // VPSUBBrm >+ 0U, // VPSUBBrr >+ 0U, // VPSUBDYrm >+ 0U, // VPSUBDYrr >+ 0U, // VPSUBDZrm >+ 4U, // VPSUBDZrmb >+ 1U, // VPSUBDZrmbk >+ 10244U, // VPSUBDZrmbkz >+ 0U, // VPSUBDZrmk >+ 4244U, // VPSUBDZrmkz >+ 0U, // VPSUBDZrr >+ 345U, // VPSUBDZrrk >+ 4244U, // VPSUBDZrrkz >+ 0U, // VPSUBDrm >+ 0U, // VPSUBDrr >+ 0U, // VPSUBQYrm >+ 0U, // VPSUBQYrr >+ 0U, // VPSUBQZrm >+ 4U, // VPSUBQZrmb >+ 1U, // VPSUBQZrmbk >+ 10244U, // VPSUBQZrmbkz >+ 0U, // VPSUBQZrmk >+ 4244U, // VPSUBQZrmkz >+ 0U, // VPSUBQZrr >+ 345U, // VPSUBQZrrk >+ 4244U, // VPSUBQZrrkz >+ 0U, // VPSUBQrm >+ 0U, // VPSUBQrr >+ 0U, // VPSUBSBYrm >+ 0U, // VPSUBSBYrr >+ 0U, // VPSUBSBrm >+ 0U, // VPSUBSBrr >+ 0U, // VPSUBSWYrm >+ 0U, // VPSUBSWYrr >+ 0U, // VPSUBSWrm >+ 0U, // VPSUBSWrr >+ 0U, // VPSUBUSBYrm >+ 0U, // VPSUBUSBYrr >+ 0U, // VPSUBUSBrm >+ 0U, // VPSUBUSBrr >+ 0U, // VPSUBUSWYrm >+ 0U, // VPSUBUSWYrr >+ 0U, // VPSUBUSWrm >+ 0U, // VPSUBUSWrr >+ 0U, // VPSUBWYrm >+ 0U, // VPSUBWYrr >+ 0U, // VPSUBWrm >+ 0U, // VPSUBWrr >+ 0U, // VPTESTMDZrm >+ 0U, // VPTESTMDZrr >+ 0U, // VPTESTMQZrm >+ 0U, // VPTESTMQZrr >+ 0U, // VPTESTNMDZrm >+ 0U, // VPTESTNMDZrr >+ 0U, // VPTESTNMQZrm >+ 0U, // VPTESTNMQZrr >+ 0U, // VPTESTYrm >+ 0U, // VPTESTYrr >+ 0U, // VPTESTrm >+ 0U, // VPTESTrr >+ 0U, // VPUNPCKHBWYrm >+ 0U, // VPUNPCKHBWYrr >+ 0U, // VPUNPCKHBWrm >+ 0U, // VPUNPCKHBWrr >+ 0U, // VPUNPCKHDQYrm >+ 0U, // VPUNPCKHDQYrr >+ 0U, // VPUNPCKHDQZrm >+ 0U, // VPUNPCKHDQZrr >+ 0U, // VPUNPCKHDQrm >+ 0U, // VPUNPCKHDQrr >+ 0U, // VPUNPCKHQDQYrm >+ 0U, // VPUNPCKHQDQYrr >+ 0U, // VPUNPCKHQDQZrm >+ 0U, // VPUNPCKHQDQZrr >+ 0U, // VPUNPCKHQDQrm >+ 0U, // VPUNPCKHQDQrr >+ 0U, // VPUNPCKHWDYrm >+ 0U, // VPUNPCKHWDYrr >+ 0U, // VPUNPCKHWDrm >+ 0U, // VPUNPCKHWDrr >+ 0U, // VPUNPCKLBWYrm >+ 0U, // VPUNPCKLBWYrr >+ 0U, // VPUNPCKLBWrm >+ 0U, // VPUNPCKLBWrr >+ 0U, // VPUNPCKLDQYrm >+ 0U, // VPUNPCKLDQYrr >+ 0U, // VPUNPCKLDQZrm >+ 0U, // VPUNPCKLDQZrr >+ 0U, // VPUNPCKLDQrm >+ 0U, // VPUNPCKLDQrr >+ 0U, // VPUNPCKLQDQYrm >+ 0U, // VPUNPCKLQDQYrr >+ 0U, // VPUNPCKLQDQZrm >+ 0U, // VPUNPCKLQDQZrr >+ 0U, // VPUNPCKLQDQrm >+ 0U, // VPUNPCKLQDQrr >+ 0U, // VPUNPCKLWDYrm >+ 0U, // VPUNPCKLWDYrr >+ 0U, // VPUNPCKLWDrm >+ 0U, // VPUNPCKLWDrr >+ 0U, // VPXORDZrm >+ 4U, // VPXORDZrmb >+ 1U, // VPXORDZrmbk >+ 10244U, // VPXORDZrmbkz >+ 0U, // VPXORDZrmk >+ 4244U, // VPXORDZrmkz >+ 0U, // VPXORDZrr >+ 345U, // VPXORDZrrk >+ 4244U, // VPXORDZrrkz >+ 0U, // VPXORQZrm >+ 4U, // VPXORQZrmb >+ 1U, // VPXORQZrmbk >+ 10244U, // VPXORQZrmbkz >+ 0U, // VPXORQZrmk >+ 4244U, // VPXORQZrmkz >+ 0U, // VPXORQZrr >+ 345U, // VPXORQZrrk >+ 4244U, // VPXORQZrrkz >+ 0U, // VPXORYrm >+ 0U, // VPXORYrr >+ 0U, // VPXORrm >+ 0U, // VPXORrr >+ 0U, // VRCP14PDZm >+ 0U, // VRCP14PDZr >+ 0U, // VRCP14PSZm >+ 0U, // VRCP14PSZr >+ 4U, // VRCP14SDrm >+ 0U, // VRCP14SDrr >+ 4U, // VRCP14SSrm >+ 0U, // VRCP14SSrr >+ 0U, // VRCP28PDZm >+ 0U, // VRCP28PDZr >+ 0U, // VRCP28PDZrb >+ 0U, // VRCP28PSZm >+ 0U, // VRCP28PSZr >+ 0U, // VRCP28PSZrb >+ 4U, // VRCP28SDrm >+ 0U, // VRCP28SDrr >+ 0U, // VRCP28SDrrb >+ 4U, // VRCP28SSrm >+ 0U, // VRCP28SSrr >+ 0U, // VRCP28SSrrb >+ 0U, // VRCPPSYm >+ 0U, // VRCPPSYm_Int >+ 0U, // VRCPPSYr >+ 0U, // VRCPPSYr_Int >+ 0U, // VRCPPSm >+ 0U, // VRCPPSm_Int >+ 0U, // VRCPPSr >+ 0U, // VRCPPSr_Int >+ 4U, // VRCPSSm >+ 4U, // VRCPSSm_Int >+ 0U, // VRCPSSr >+ 0U, // VRNDSCALEPDZm >+ 0U, // VRNDSCALEPDZr >+ 0U, // VRNDSCALEPSZm >+ 0U, // VRNDSCALEPSZr >+ 4U, // VRNDSCALESDm >+ 0U, // VRNDSCALESDr >+ 4U, // VRNDSCALESSm >+ 0U, // VRNDSCALESSr >+ 0U, // VROUNDPDm >+ 0U, // VROUNDPDr >+ 0U, // VROUNDPSm >+ 0U, // VROUNDPSr >+ 4U, // VROUNDSDm >+ 4U, // VROUNDSDr >+ 4U, // VROUNDSDr_Int >+ 4U, // VROUNDSSm >+ 4U, // VROUNDSSr >+ 4U, // VROUNDSSr_Int >+ 0U, // VROUNDYPDm >+ 0U, // VROUNDYPDr >+ 0U, // VROUNDYPSm >+ 0U, // VROUNDYPSr >+ 0U, // VRSQRT14PDZm >+ 0U, // VRSQRT14PDZr >+ 0U, // VRSQRT14PSZm >+ 0U, // VRSQRT14PSZr >+ 4U, // VRSQRT14SDrm >+ 0U, // VRSQRT14SDrr >+ 4U, // VRSQRT14SSrm >+ 0U, // VRSQRT14SSrr >+ 0U, // VRSQRT28PDZm >+ 0U, // VRSQRT28PDZr >+ 0U, // VRSQRT28PDZrb >+ 0U, // VRSQRT28PSZm >+ 0U, // VRSQRT28PSZr >+ 0U, // VRSQRT28PSZrb >+ 4U, // VRSQRT28SDrm >+ 0U, // VRSQRT28SDrr >+ 0U, // VRSQRT28SDrrb >+ 4U, // VRSQRT28SSrm >+ 0U, // VRSQRT28SSrr >+ 0U, // VRSQRT28SSrrb >+ 0U, // VRSQRTPSYm >+ 0U, // VRSQRTPSYm_Int >+ 0U, // VRSQRTPSYr >+ 0U, // VRSQRTPSYr_Int >+ 0U, // VRSQRTPSm >+ 0U, // VRSQRTPSm_Int >+ 0U, // VRSQRTPSr >+ 0U, // VRSQRTPSr_Int >+ 4U, // VRSQRTSSm >+ 4U, // VRSQRTSSm_Int >+ 0U, // VRSQRTSSr >+ 37U, // VSCATTERDPDZmr >+ 37U, // VSCATTERDPSZmr >+ 0U, // VSCATTERPF0DPDm >+ 0U, // VSCATTERPF0DPSm >+ 0U, // VSCATTERPF0QPDm >+ 0U, // VSCATTERPF0QPSm >+ 0U, // VSCATTERPF1DPDm >+ 0U, // VSCATTERPF1DPSm >+ 0U, // VSCATTERPF1QPDm >+ 0U, // VSCATTERPF1QPSm >+ 37U, // VSCATTERQPDZmr >+ 37U, // VSCATTERQPSZmr >+ 0U, // VSHUFPDYrmi >+ 4U, // VSHUFPDYrri >+ 0U, // VSHUFPDZrmi >+ 4U, // VSHUFPDZrri >+ 4U, // VSHUFPDrmi >+ 4U, // VSHUFPDrri >+ 0U, // VSHUFPSYrmi >+ 4U, // VSHUFPSYrri >+ 0U, // VSHUFPSZrmi >+ 4U, // VSHUFPSZrri >+ 4U, // VSHUFPSrmi >+ 4U, // VSHUFPSrri >+ 0U, // VSQRTPDYm >+ 0U, // VSQRTPDYr >+ 0U, // VSQRTPDZrm >+ 0U, // VSQRTPDZrr >+ 0U, // VSQRTPDm >+ 0U, // VSQRTPDr >+ 0U, // VSQRTPSYm >+ 0U, // VSQRTPSYr >+ 0U, // VSQRTPSZrm >+ 0U, // VSQRTPSZrr >+ 0U, // VSQRTPSm >+ 0U, // VSQRTPSr >+ 4U, // VSQRTSDZm >+ 4U, // VSQRTSDZm_Int >+ 0U, // VSQRTSDZr >+ 0U, // VSQRTSDZr_Int >+ 4U, // VSQRTSDm >+ 4U, // VSQRTSDm_Int >+ 0U, // VSQRTSDr >+ 4U, // VSQRTSSZm >+ 4U, // VSQRTSSZm_Int >+ 0U, // VSQRTSSZr >+ 0U, // VSQRTSSZr_Int >+ 4U, // VSQRTSSm >+ 4U, // VSQRTSSm_Int >+ 0U, // VSQRTSSr >+ 0U, // VSTMXCSR >+ 0U, // VSUBPDYrm >+ 0U, // VSUBPDYrr >+ 0U, // VSUBPDZrm >+ 4U, // VSUBPDZrmb >+ 2052U, // VSUBPDZrmbk >+ 10244U, // VSUBPDZrmbkz >+ 3220U, // VSUBPDZrmk >+ 4244U, // VSUBPDZrmkz >+ 0U, // VSUBPDZrr >+ 5268U, // VSUBPDZrrk >+ 4244U, // VSUBPDZrrkz >+ 0U, // VSUBPDrm >+ 0U, // VSUBPDrr >+ 0U, // VSUBPSYrm >+ 0U, // VSUBPSYrr >+ 0U, // VSUBPSZrm >+ 4U, // VSUBPSZrmb >+ 2052U, // VSUBPSZrmbk >+ 10244U, // VSUBPSZrmbkz >+ 3220U, // VSUBPSZrmk >+ 4244U, // VSUBPSZrmkz >+ 0U, // VSUBPSZrr >+ 5268U, // VSUBPSZrrk >+ 4244U, // VSUBPSZrrkz >+ 0U, // VSUBPSrm >+ 0U, // VSUBPSrr >+ 4U, // VSUBSDZrm >+ 0U, // VSUBSDZrr >+ 4U, // VSUBSDrm >+ 4U, // VSUBSDrm_Int >+ 0U, // VSUBSDrr >+ 0U, // VSUBSDrr_Int >+ 4U, // VSUBSSZrm >+ 0U, // VSUBSSZrr >+ 4U, // VSUBSSrm >+ 4U, // VSUBSSrm_Int >+ 0U, // VSUBSSrr >+ 0U, // VSUBSSrr_Int >+ 0U, // VTESTPDYrm >+ 0U, // VTESTPDYrr >+ 0U, // VTESTPDrm >+ 0U, // VTESTPDrr >+ 0U, // VTESTPSYrm >+ 0U, // VTESTPSYrr >+ 0U, // VTESTPSrm >+ 0U, // VTESTPSrr >+ 0U, // VUCOMISDZrm >+ 0U, // VUCOMISDZrr >+ 0U, // VUCOMISDrm >+ 0U, // VUCOMISDrr >+ 0U, // VUCOMISSZrm >+ 0U, // VUCOMISSZrr >+ 0U, // VUCOMISSrm >+ 0U, // VUCOMISSrr >+ 0U, // VUNPCKHPDYrm >+ 0U, // VUNPCKHPDYrr >+ 0U, // VUNPCKHPDZrm >+ 0U, // VUNPCKHPDZrr >+ 0U, // VUNPCKHPDrm >+ 0U, // VUNPCKHPDrr >+ 0U, // VUNPCKHPSYrm >+ 0U, // VUNPCKHPSYrr >+ 0U, // VUNPCKHPSZrm >+ 0U, // VUNPCKHPSZrr >+ 0U, // VUNPCKHPSrm >+ 0U, // VUNPCKHPSrr >+ 0U, // VUNPCKLPDYrm >+ 0U, // VUNPCKLPDYrr >+ 0U, // VUNPCKLPDZrm >+ 0U, // VUNPCKLPDZrr >+ 0U, // VUNPCKLPDrm >+ 0U, // VUNPCKLPDrr >+ 0U, // VUNPCKLPSYrm >+ 0U, // VUNPCKLPSYrr >+ 0U, // VUNPCKLPSZrm >+ 0U, // VUNPCKLPSZrr >+ 0U, // VUNPCKLPSrm >+ 0U, // VUNPCKLPSrr >+ 0U, // VXORPDYrm >+ 0U, // VXORPDYrr >+ 0U, // VXORPDrm >+ 0U, // VXORPDrr >+ 0U, // VXORPSYrm >+ 0U, // VXORPSYrr >+ 0U, // VXORPSrm >+ 0U, // VXORPSrr >+ 0U, // VZEROALL >+ 0U, // VZEROUPPER >+ 0U, // V_SET0 >+ 0U, // V_SETALLONES >+ 0U, // W64ALLOCA >+ 0U, // WAIT >+ 0U, // WBINVD >+ 0U, // WIN_ALLOCA >+ 0U, // WIN_FTOL_32 >+ 0U, // WIN_FTOL_64 >+ 0U, // WRFSBASE >+ 0U, // WRFSBASE64 >+ 0U, // WRGSBASE >+ 0U, // WRGSBASE64 >+ 0U, // WRMSR >+ 0U, // XABORT >+ 0U, // XACQUIRE_PREFIX >+ 0U, // XADD16rm >+ 0U, // XADD16rr >+ 0U, // XADD32rm >+ 0U, // XADD32rr >+ 0U, // XADD64rm >+ 0U, // XADD64rr >+ 0U, // XADD8rm >+ 0U, // XADD8rr >+ 0U, // XBEGIN >+ 0U, // XBEGIN_4 >+ 0U, // XCHG16ar >+ 0U, // XCHG16rm >+ 0U, // XCHG16rr >+ 0U, // XCHG32ar >+ 0U, // XCHG32ar64 >+ 0U, // XCHG32rm >+ 0U, // XCHG32rr >+ 0U, // XCHG64ar >+ 0U, // XCHG64rm >+ 0U, // XCHG64rr >+ 1U, // XCHG8rm >+ 0U, // XCHG8rr >+ 0U, // XCH_F >+ 0U, // XCRYPTCBC >+ 0U, // XCRYPTCFB >+ 0U, // XCRYPTCTR >+ 0U, // XCRYPTECB >+ 0U, // XCRYPTOFB >+ 0U, // XEND >+ 0U, // XGETBV >+ 0U, // XLAT >+ 0U, // XOR16i16 >+ 0U, // XOR16mi >+ 0U, // XOR16mi8 >+ 0U, // XOR16mr >+ 0U, // XOR16ri >+ 0U, // XOR16ri8 >+ 0U, // XOR16rm >+ 0U, // XOR16rr >+ 0U, // XOR16rr_REV >+ 0U, // XOR32i32 >+ 0U, // XOR32mi >+ 0U, // XOR32mi8 >+ 0U, // XOR32mr >+ 0U, // XOR32ri >+ 0U, // XOR32ri8 >+ 0U, // XOR32rm >+ 0U, // XOR32rr >+ 0U, // XOR32rr_REV >+ 0U, // XOR64i32 >+ 0U, // XOR64mi32 >+ 0U, // XOR64mi8 >+ 0U, // XOR64mr >+ 0U, // XOR64ri32 >+ 0U, // XOR64ri8 >+ 0U, // XOR64rm >+ 0U, // XOR64rr >+ 0U, // XOR64rr_REV >+ 0U, // XOR8i8 >+ 0U, // XOR8mi >+ 0U, // XOR8mr >+ 0U, // XOR8ri >+ 0U, // XOR8ri8 >+ 0U, // XOR8rm >+ 0U, // XOR8rr >+ 0U, // XOR8rr_REV >+ 0U, // XORPDrm >+ 0U, // XORPDrr >+ 0U, // XORPSrm >+ 0U, // XORPSrr >+ 0U, // XRELEASE_PREFIX >+ 0U, // XRSTOR >+ 0U, // XRSTOR64 >+ 0U, // XSAVE >+ 0U, // XSAVE64 >+ 0U, // XSAVEOPT >+ 0U, // XSAVEOPT64 >+ 0U, // XSETBV >+ 0U, // XSHA1 >+ 0U, // XSHA256 >+ 0U, // XSTORE >+ 0U, // XTEST >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 32, 9, 0, >+ /* 18 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 32, 9, 0, >+ /* 36 */ 'k', 'a', 'n', 'd', 'b', 32, 9, 0, >+ /* 44 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'b', 32, 9, 0, >+ /* 56 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'b', 32, 9, 0, >+ /* 67 */ 'v', 'p', 'm', 'o', 'v', 'd', 'b', 32, 9, 0, >+ /* 77 */ 'k', 'a', 'n', 'd', 'n', 'b', 32, 9, 0, >+ /* 86 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 32, 9, 0, >+ /* 98 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 32, 9, 0, >+ /* 109 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 32, 9, 0, >+ /* 119 */ 'k', 'o', 'r', 'b', 32, 9, 0, >+ /* 126 */ 'k', 'x', 'n', 'o', 'r', 'b', 32, 9, 0, >+ /* 135 */ 'k', 'x', 'o', 'r', 'b', 32, 9, 0, >+ /* 143 */ 'k', 'n', 'o', 't', 'b', 32, 9, 0, >+ /* 151 */ 'k', 'm', 'o', 'v', 'b', 32, 9, 0, >+ /* 159 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 32, 9, 0, >+ /* 170 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 32, 9, 0, >+ /* 181 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 32, 9, 0, >+ /* 199 */ 'v', 'p', 's', 'r', 'a', 'd', 32, 9, 0, >+ /* 208 */ 'v', 'p', 's', 'u', 'b', 'd', 32, 9, 0, >+ /* 217 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 32, 9, 0, >+ /* 229 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 32, 9, 0, >+ /* 241 */ 'v', 'p', 'a', 'd', 'd', 'd', 32, 9, 0, >+ /* 250 */ 'k', 'a', 'n', 'd', 'd', 32, 9, 0, >+ /* 258 */ 'v', 'p', 'a', 'n', 'd', 'd', 32, 9, 0, >+ /* 267 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 32, 9, 0, >+ /* 280 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 32, 9, 0, >+ /* 294 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 32, 9, 0, >+ /* 304 */ 'v', 'p', 's', 'l', 'l', 'd', 32, 9, 0, >+ /* 313 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 32, 9, 0, >+ /* 323 */ 'v', 'p', 's', 'r', 'l', 'd', 32, 9, 0, >+ /* 332 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'd', 32, 9, 0, >+ /* 344 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'd', 32, 9, 0, >+ /* 356 */ 'v', 'p', 'e', 'r', 'm', 'd', 32, 9, 0, >+ /* 365 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 32, 9, 0, >+ /* 376 */ 'k', 'a', 'n', 'd', 'n', 'd', 32, 9, 0, >+ /* 385 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 32, 9, 0, >+ /* 395 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 32, 9, 0, >+ /* 405 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 422 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 436 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 451 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 468 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 482 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 497 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 32, 9, 0, >+ /* 509 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 32, 9, 0, >+ /* 521 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 32, 9, 0, >+ /* 534 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 32, 9, 0, >+ /* 546 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 32, 9, 0, >+ /* 558 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 575 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 589 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 604 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 621 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 635 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 650 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 32, 9, 0, >+ /* 661 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 32, 9, 0, >+ /* 674 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 32, 9, 0, >+ /* 685 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 32, 9, 0, >+ /* 698 */ 'v', 's', 'u', 'b', 'p', 'd', 32, 9, 0, >+ /* 707 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 32, 9, 0, >+ /* 723 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 32, 9, 0, >+ /* 740 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 32, 9, 0, >+ /* 756 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 32, 9, 0, >+ /* 773 */ 'v', 'a', 'd', 'd', 'p', 'd', 32, 9, 0, >+ /* 782 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 32, 9, 0, >+ /* 795 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 32, 9, 0, >+ /* 809 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 32, 9, 0, >+ /* 823 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 32, 9, 0, >+ /* 833 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 32, 9, 0, >+ /* 845 */ 'v', 'm', 'u', 'l', 'p', 'd', 32, 9, 0, >+ /* 854 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 32, 9, 0, >+ /* 866 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 32, 9, 0, >+ /* 876 */ 'v', 'm', 'i', 'n', 'p', 'd', 32, 9, 0, >+ /* 885 */ 'v', 'c', 'm', 'p', 'p', 'd', 32, 9, 0, >+ /* 894 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 32, 9, 0, >+ /* 910 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 32, 9, 0, >+ /* 927 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 32, 9, 0, >+ /* 943 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 32, 9, 0, >+ /* 960 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 32, 9, 0, >+ /* 973 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 32, 9, 0, >+ /* 987 */ 'v', 'd', 'i', 'v', 'p', 'd', 32, 9, 0, >+ /* 996 */ 'v', 'm', 'a', 'x', 'p', 'd', 32, 9, 0, >+ /* 1005 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 32, 9, 0, >+ /* 1018 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 32, 9, 0, >+ /* 1032 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 32, 9, 0, >+ /* 1044 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 32, 9, 0, >+ /* 1055 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 32, 9, 0, >+ /* 1065 */ 'k', 'o', 'r', 'd', 32, 9, 0, >+ /* 1072 */ 'k', 'x', 'n', 'o', 'r', 'd', 32, 9, 0, >+ /* 1081 */ 'v', 'p', 'o', 'r', 'd', 32, 9, 0, >+ /* 1089 */ 'k', 'x', 'o', 'r', 'd', 32, 9, 0, >+ /* 1097 */ 'v', 'p', 'x', 'o', 'r', 'd', 32, 9, 0, >+ /* 1106 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1120 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1135 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1149 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1164 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 32, 9, 0, >+ /* 1175 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 32, 9, 0, >+ /* 1188 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 32, 9, 0, >+ /* 1199 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 32, 9, 0, >+ /* 1212 */ 'v', 'p', 'a', 'b', 's', 'd', 32, 9, 0, >+ /* 1221 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 32, 9, 0, >+ /* 1235 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 32, 9, 0, >+ /* 1245 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 32, 9, 0, >+ /* 1260 */ 'v', 'm', 'o', 'v', 's', 'd', 32, 9, 0, >+ /* 1269 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 32, 9, 0, >+ /* 1279 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 32, 9, 0, >+ /* 1293 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 32, 9, 0, >+ /* 1304 */ 'k', 'n', 'o', 't', 'd', 32, 9, 0, >+ /* 1312 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 32, 9, 0, >+ /* 1327 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 32, 9, 0, >+ /* 1337 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 32, 9, 0, >+ /* 1347 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 32, 9, 0, >+ /* 1357 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 32, 9, 0, >+ /* 1367 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 32, 9, 0, >+ /* 1377 */ 'k', 'm', 'o', 'v', 'd', 32, 9, 0, >+ /* 1385 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 32, 9, 0, >+ /* 1397 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 32, 9, 0, >+ /* 1409 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 32, 9, 0, >+ /* 1421 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 32, 9, 0, >+ /* 1434 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 32, 9, 0, >+ /* 1446 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 32, 9, 0, >+ /* 1459 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 32, 9, 0, >+ /* 1471 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1485 */ 'v', 'c', 'v', 't', 's', 'd', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1498 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1512 */ 'v', 'c', 'v', 't', 's', 's', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1525 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'l', 32, 9, 0, >+ /* 1538 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'l', 32, 9, 0, >+ /* 1552 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'l', 32, 9, 0, >+ /* 1565 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'l', 32, 9, 0, >+ /* 1579 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 32, 9, 0, >+ /* 1590 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 32, 9, 0, >+ /* 1602 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 32, 9, 0, >+ /* 1614 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'b', '2', 'q', 32, 9, 0, >+ /* 1632 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'q', 32, 9, 0, >+ /* 1643 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'q', 32, 9, 0, >+ /* 1654 */ 'v', 'p', 's', 'r', 'a', 'q', 32, 9, 0, >+ /* 1663 */ 'v', 'p', 's', 'u', 'b', 'q', 32, 9, 0, >+ /* 1672 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 32, 9, 0, >+ /* 1684 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 32, 9, 0, >+ /* 1696 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 32, 9, 0, >+ /* 1709 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 32, 9, 0, >+ /* 1721 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 32, 9, 0, >+ /* 1734 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 32, 9, 0, >+ /* 1746 */ 'v', 'p', 'a', 'd', 'd', 'q', 32, 9, 0, >+ /* 1755 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 32, 9, 0, >+ /* 1768 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 32, 9, 0, >+ /* 1781 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 32, 9, 0, >+ /* 1791 */ 'k', 'a', 'n', 'd', 'q', 32, 9, 0, >+ /* 1799 */ 'v', 'p', 'a', 'n', 'd', 'q', 32, 9, 0, >+ /* 1808 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 32, 9, 0, >+ /* 1822 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 32, 9, 0, >+ /* 1836 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 32, 9, 0, >+ /* 1849 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'q', 32, 9, 0, >+ /* 1863 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'q', 32, 9, 0, >+ /* 1876 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'q', 32, 9, 0, >+ /* 1890 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1904 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1917 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1931 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1944 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 32, 9, 0, >+ /* 1955 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 32, 9, 0, >+ /* 1967 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 32, 9, 0, >+ /* 1979 */ 'v', 'p', 's', 'l', 'l', 'q', 32, 9, 0, >+ /* 1988 */ 'v', 'p', 's', 'r', 'l', 'q', 32, 9, 0, >+ /* 1997 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'q', 32, 9, 0, >+ /* 2009 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'q', 32, 9, 0, >+ /* 2021 */ 'v', 'p', 'e', 'r', 'm', 'q', 32, 9, 0, >+ /* 2030 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'q', 32, 9, 0, >+ /* 2041 */ 'k', 'a', 'n', 'd', 'n', 'q', 32, 9, 0, >+ /* 2050 */ 'v', 'p', 'a', 'n', 'd', 'n', 'q', 32, 9, 0, >+ /* 2060 */ 'v', 'a', 'l', 'i', 'g', 'n', 'q', 32, 9, 0, >+ /* 2070 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 32, 9, 0, >+ /* 2083 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'q', 32, 9, 0, >+ /* 2097 */ 'k', 'o', 'r', 'q', 32, 9, 0, >+ /* 2104 */ 'k', 'x', 'n', 'o', 'r', 'q', 32, 9, 0, >+ /* 2113 */ 'v', 'p', 'o', 'r', 'q', 32, 9, 0, >+ /* 2121 */ 'k', 'x', 'o', 'r', 'q', 32, 9, 0, >+ /* 2129 */ 'v', 'p', 'x', 'o', 'r', 'q', 32, 9, 0, >+ /* 2138 */ 'v', 'p', 'a', 'b', 's', 'q', 32, 9, 0, >+ /* 2147 */ 'v', 'p', 'm', 'i', 'n', 's', 'q', 32, 9, 0, >+ /* 2157 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'q', 32, 9, 0, >+ /* 2170 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'q', 32, 9, 0, >+ /* 2184 */ 'v', 'p', 'm', 'a', 'x', 's', 'q', 32, 9, 0, >+ /* 2194 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'q', 32, 9, 0, >+ /* 2208 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'q', 32, 9, 0, >+ /* 2219 */ 'k', 'n', 'o', 't', 'q', 32, 9, 0, >+ /* 2227 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 32, 9, 0, >+ /* 2242 */ 'v', 'p', 'm', 'i', 'n', 'u', 'q', 32, 9, 0, >+ /* 2252 */ 'v', 'p', 'm', 'a', 'x', 'u', 'q', 32, 9, 0, >+ /* 2262 */ 'v', 'p', 's', 'r', 'a', 'v', 'q', 32, 9, 0, >+ /* 2272 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 32, 9, 0, >+ /* 2282 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 32, 9, 0, >+ /* 2292 */ 'k', 'm', 'o', 'v', 'q', 32, 9, 0, >+ /* 2300 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 32, 9, 0, >+ /* 2312 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 32, 9, 0, >+ /* 2324 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2341 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2355 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2370 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2387 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2401 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2416 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 32, 9, 0, >+ /* 2428 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 32, 9, 0, >+ /* 2440 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 32, 9, 0, >+ /* 2452 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 32, 9, 0, >+ /* 2465 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 32, 9, 0, >+ /* 2477 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2494 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2508 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2523 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2540 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2554 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2569 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 32, 9, 0, >+ /* 2580 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 32, 9, 0, >+ /* 2593 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 32, 9, 0, >+ /* 2604 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 32, 9, 0, >+ /* 2617 */ 'v', 's', 'u', 'b', 'p', 's', 32, 9, 0, >+ /* 2626 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 32, 9, 0, >+ /* 2642 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 32, 9, 0, >+ /* 2659 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 32, 9, 0, >+ /* 2675 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 32, 9, 0, >+ /* 2692 */ 'v', 'a', 'd', 'd', 'p', 's', 32, 9, 0, >+ /* 2701 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 32, 9, 0, >+ /* 2714 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 's', 32, 9, 0, >+ /* 2728 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 's', 32, 9, 0, >+ /* 2742 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 32, 9, 0, >+ /* 2752 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 32, 9, 0, >+ /* 2764 */ 'v', 'm', 'u', 'l', 'p', 's', 32, 9, 0, >+ /* 2773 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 32, 9, 0, >+ /* 2785 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 32, 9, 0, >+ /* 2795 */ 'v', 'm', 'i', 'n', 'p', 's', 32, 9, 0, >+ /* 2804 */ 'v', 'c', 'm', 'p', 'p', 's', 32, 9, 0, >+ /* 2813 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 32, 9, 0, >+ /* 2829 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 32, 9, 0, >+ /* 2846 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 32, 9, 0, >+ /* 2862 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 32, 9, 0, >+ /* 2879 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 32, 9, 0, >+ /* 2892 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 32, 9, 0, >+ /* 2906 */ 'v', 'd', 'i', 'v', 'p', 's', 32, 9, 0, >+ /* 2915 */ 'v', 'm', 'a', 'x', 'p', 's', 32, 9, 0, >+ /* 2924 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2938 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2953 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2967 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2982 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 32, 9, 0, >+ /* 2993 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 32, 9, 0, >+ /* 3006 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 32, 9, 0, >+ /* 3017 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 32, 9, 0, >+ /* 3030 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 32, 9, 0, >+ /* 3044 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 32, 9, 0, >+ /* 3059 */ 'v', 'm', 'o', 'v', 's', 's', 32, 9, 0, >+ /* 3068 */ 'k', 'u', 'n', 'p', 'c', 'k', 'b', 'w', 32, 9, 0, >+ /* 3079 */ 'k', 'a', 'n', 'd', 'w', 32, 9, 0, >+ /* 3087 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'w', 32, 9, 0, >+ /* 3099 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'w', 32, 9, 0, >+ /* 3110 */ 'v', 'p', 'm', 'o', 'v', 'd', 'w', 32, 9, 0, >+ /* 3120 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'w', 32, 9, 0, >+ /* 3131 */ 'k', 'a', 'n', 'd', 'n', 'w', 32, 9, 0, >+ /* 3140 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'w', 32, 9, 0, >+ /* 3152 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'w', 32, 9, 0, >+ /* 3163 */ 'v', 'p', 'm', 'o', 'v', 'q', 'w', 32, 9, 0, >+ /* 3173 */ 'k', 'o', 'r', 'w', 32, 9, 0, >+ /* 3180 */ 'k', 'x', 'n', 'o', 'r', 'w', 32, 9, 0, >+ /* 3189 */ 'k', 'x', 'o', 'r', 'w', 32, 9, 0, >+ /* 3197 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'w', 32, 9, 0, >+ /* 3208 */ 'k', 'n', 'o', 't', 'w', 32, 9, 0, >+ /* 3216 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'w', 32, 9, 0, >+ /* 3227 */ 'k', 'm', 'o', 'v', 'w', 32, 9, 0, >+ /* 3235 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, >+ /* 3247 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, >+ /* 3257 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, >+ /* 3269 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, >+ /* 3281 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, >+ /* 3291 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, >+ /* 3301 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, >+ /* 3312 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, >+ /* 3323 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, >+ /* 3333 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, >+ /* 3345 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, 0, >+ /* 3358 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, >+ /* 3370 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, >+ /* 3380 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, >+ /* 3391 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, >+ /* 3402 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, >+ /* 3413 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, >+ /* 3428 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, >+ /* 3442 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, >+ /* 3457 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, >+ /* 3471 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, >+ /* 3486 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, >+ /* 3500 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, >+ /* 3515 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, >+ /* 3529 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, >+ /* 3540 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, >+ /* 3552 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3566 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3579 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3595 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, >+ /* 3607 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3621 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3634 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3650 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, >+ /* 3660 */ 'j', 'a', 9, 0, >+ /* 3664 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, >+ /* 3675 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, >+ /* 3684 */ 's', 'e', 't', 'a', 9, 0, >+ /* 3690 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, >+ /* 3703 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, >+ /* 3711 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, >+ /* 3723 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, >+ /* 3734 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, >+ /* 3742 */ 's', 'b', 'b', 'b', 9, 0, >+ /* 3748 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, >+ /* 3756 */ 'a', 'd', 'c', 'b', 9, 0, >+ /* 3762 */ 'd', 'e', 'c', 'b', 9, 0, >+ /* 3768 */ 'i', 'n', 'c', 'b', 9, 0, >+ /* 3774 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, >+ /* 3782 */ 'x', 'a', 'd', 'd', 'b', 9, 0, >+ /* 3789 */ 'a', 'n', 'd', 'b', 9, 0, >+ /* 3795 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 9, 0, >+ /* 3804 */ 'n', 'e', 'g', 'b', 9, 0, >+ /* 3810 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'b', 9, 0, >+ /* 3820 */ 'v', 'p', 'a', 'v', 'g', 'b', 9, 0, >+ /* 3828 */ 'j', 'b', 9, 0, >+ /* 3832 */ 'v', 'p', 'm', 'o', 'v', 'm', 's', 'k', 'b', 9, 0, >+ /* 3843 */ 's', 'a', 'l', 'b', 9, 0, >+ /* 3849 */ 'r', 'c', 'l', 'b', 9, 0, >+ /* 3855 */ 'v', 'p', 's', 'h', 'l', 'b', 9, 0, >+ /* 3863 */ 'r', 'o', 'l', 'b', 9, 0, >+ /* 3869 */ 'i', 'm', 'u', 'l', 'b', 9, 0, >+ /* 3876 */ 'v', 'p', 'c', 'o', 'm', 'b', 9, 0, >+ /* 3884 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, >+ /* 3893 */ 'i', 'n', 'b', 9, 0, >+ /* 3898 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 9, 0, >+ /* 3907 */ 'c', 'm', 'p', 'b', 9, 0, >+ /* 3913 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, >+ /* 3923 */ 's', 'a', 'r', 'b', 9, 0, >+ /* 3929 */ 'r', 'c', 'r', 'b', 9, 0, >+ /* 3935 */ 's', 'h', 'r', 'b', 9, 0, >+ /* 3941 */ 'r', 'o', 'r', 'b', 9, 0, >+ /* 3947 */ 'x', 'o', 'r', 'b', 9, 0, >+ /* 3953 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, >+ /* 3962 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, >+ /* 3971 */ 's', 'c', 'a', 's', 'b', 9, 0, >+ /* 3978 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, >+ /* 3986 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, >+ /* 3995 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, >+ /* 4004 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, >+ /* 4013 */ 'l', 'o', 'd', 's', 'b', 9, 0, >+ /* 4020 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, >+ /* 4029 */ 'c', 'm', 'p', 's', 'b', 9, 0, >+ /* 4036 */ 'o', 'u', 't', 's', 'b', 9, 0, >+ /* 4043 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, >+ /* 4053 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, >+ /* 4063 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, >+ /* 4072 */ 'm', 'o', 'v', 's', 'b', 9, 0, >+ /* 4079 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, >+ /* 4088 */ 's', 'e', 't', 'b', 9, 0, >+ /* 4094 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, >+ /* 4104 */ 'n', 'o', 't', 'b', 9, 0, >+ /* 4110 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, >+ /* 4118 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, >+ /* 4132 */ 't', 'e', 's', 't', 'b', 9, 0, >+ /* 4139 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, >+ /* 4148 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, >+ /* 4157 */ 'p', 'f', 's', 'u', 'b', 9, 0, >+ /* 4164 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, >+ /* 4173 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, >+ /* 4184 */ 'i', 'd', 'i', 'v', 'b', 9, 0, >+ /* 4191 */ 'f', 'c', 'm', 'o', 'v', 'b', 9, 0, >+ /* 4199 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, >+ /* 4210 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, >+ /* 4221 */ 'p', 'f', 'a', 'c', 'c', 9, 0, >+ /* 4228 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, >+ /* 4236 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, >+ /* 4245 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, >+ /* 4254 */ 'b', 'l', 'c', 'i', 'c', 9, 0, >+ /* 4261 */ 'b', 'l', 's', 'i', 'c', 9, 0, >+ /* 4268 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, >+ /* 4276 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, >+ /* 4285 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, >+ /* 4294 */ 'a', 'a', 'd', 9, 0, >+ /* 4299 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, >+ /* 4307 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, >+ /* 4315 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, >+ /* 4325 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, >+ /* 4336 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, >+ /* 4345 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, >+ /* 4353 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, >+ /* 4364 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, >+ /* 4375 */ 'p', 'f', 'a', 'd', 'd', 9, 0, >+ /* 4382 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, >+ /* 4391 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, >+ /* 4399 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, >+ /* 4409 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, >+ /* 4421 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'd', 9, 0, >+ /* 4431 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'd', 9, 0, >+ /* 4442 */ 'p', 'i', '2', 'f', 'd', 9, 0, >+ /* 4449 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 9, 0, >+ /* 4458 */ 'p', 'f', '2', 'i', 'd', 9, 0, >+ /* 4465 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, >+ /* 4474 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, >+ /* 4483 */ 'f', 'b', 'l', 'd', 9, 0, >+ /* 4489 */ 'f', 'l', 'd', 9, 0, >+ /* 4494 */ 'v', 'p', 's', 'h', 'l', 'd', 9, 0, >+ /* 4502 */ 'v', 'p', 's', 'l', 'l', 'd', 9, 0, >+ /* 4510 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 9, 0, >+ /* 4519 */ 'v', 'p', 's', 'r', 'l', 'd', 9, 0, >+ /* 4527 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, >+ /* 4536 */ 'v', 'p', 'c', 'o', 'm', 'd', 9, 0, >+ /* 4544 */ 'v', 'p', 'e', 'r', 'm', 'd', 9, 0, >+ /* 4552 */ 'v', 'p', 'a', 'n', 'd', 9, 0, >+ /* 4559 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, >+ /* 4568 */ 'b', 'o', 'u', 'n', 'd', 9, 0, >+ /* 4575 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4591 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4604 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4618 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4634 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4647 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4661 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4677 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4690 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4704 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4720 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4733 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4747 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, >+ /* 4757 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, >+ /* 4769 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, >+ /* 4780 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, >+ /* 4791 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4807 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4820 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4834 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4850 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4863 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4877 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, >+ /* 4886 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, >+ /* 4894 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4907 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4918 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4927 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4937 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4948 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4956 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4969 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4978 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4988 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4999 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 5007 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, >+ /* 5015 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, >+ /* 5025 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, >+ /* 5035 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, >+ /* 5047 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, >+ /* 5056 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, >+ /* 5067 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, >+ /* 5076 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, >+ /* 5087 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, >+ /* 5098 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, >+ /* 5109 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, >+ /* 5117 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, >+ /* 5126 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, >+ /* 5134 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, >+ /* 5143 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, >+ /* 5152 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, >+ /* 5160 */ 'v', 'd', 'p', 'p', 'd', 9, 0, >+ /* 5167 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, >+ /* 5175 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, >+ /* 5187 */ 'v', 'o', 'r', 'p', 'd', 9, 0, >+ /* 5194 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, >+ /* 5202 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, >+ /* 5212 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, >+ /* 5221 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, >+ /* 5230 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, >+ /* 5239 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, >+ /* 5250 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, >+ /* 5258 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, >+ /* 5270 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, >+ /* 5278 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, >+ /* 5287 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, >+ /* 5297 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, >+ /* 5309 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, >+ /* 5318 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, >+ /* 5327 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, >+ /* 5340 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, >+ /* 5354 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, >+ /* 5367 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, >+ /* 5381 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5394 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5408 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5421 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5435 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, >+ /* 5446 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5459 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5473 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5486 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5500 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, >+ /* 5508 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5518 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5529 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5537 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5547 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5558 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5566 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, >+ /* 5576 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, >+ /* 5586 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, >+ /* 5595 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, >+ /* 5603 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, >+ /* 5612 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, >+ /* 5620 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, >+ /* 5628 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, >+ /* 5637 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, >+ /* 5646 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, >+ /* 5660 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, >+ /* 5668 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, >+ /* 5676 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, >+ /* 5685 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, >+ /* 5693 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, >+ /* 5702 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, >+ /* 5712 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, >+ /* 5720 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, >+ /* 5734 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, >+ /* 5743 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, >+ /* 5752 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, >+ /* 5761 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, >+ /* 5770 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, >+ /* 5779 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, >+ /* 5788 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, >+ /* 5797 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, >+ /* 5809 */ 'v', 'm', 'o', 'v', 'd', 9, 0, >+ /* 5816 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, >+ /* 5826 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, >+ /* 5836 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, >+ /* 5846 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, >+ /* 5858 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, >+ /* 5870 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, >+ /* 5880 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, >+ /* 5891 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, >+ /* 5902 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, >+ /* 5914 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, >+ /* 5925 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, >+ /* 5936 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, >+ /* 5947 */ 'j', 'a', 'e', 9, 0, >+ /* 5952 */ 's', 'e', 't', 'a', 'e', 9, 0, >+ /* 5959 */ 'j', 'b', 'e', 9, 0, >+ /* 5964 */ 'f', 'c', 'm', 'o', 'v', 'n', 'b', 'e', 9, 0, >+ /* 5974 */ 's', 'e', 't', 'b', 'e', 9, 0, >+ /* 5981 */ 'f', 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, >+ /* 5990 */ 'f', 'f', 'r', 'e', 'e', 9, 0, >+ /* 5997 */ 'j', 'g', 'e', 9, 0, >+ /* 6002 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, >+ /* 6011 */ 's', 'e', 't', 'g', 'e', 9, 0, >+ /* 6018 */ 'j', 'e', 9, 0, >+ /* 6022 */ 'j', 'l', 'e', 9, 0, >+ /* 6027 */ 's', 'e', 't', 'l', 'e', 9, 0, >+ /* 6034 */ 'j', 'n', 'e', 9, 0, >+ /* 6039 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, >+ /* 6047 */ 's', 'e', 't', 'n', 'e', 9, 0, >+ /* 6054 */ 'f', 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, >+ /* 6063 */ 'l', 'o', 'o', 'p', 'e', 9, 0, >+ /* 6070 */ 's', 'e', 't', 'e', 9, 0, >+ /* 6076 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, >+ /* 6087 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, >+ /* 6095 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, >+ /* 6103 */ 'f', 'c', 'm', 'o', 'v', 'e', 9, 0, >+ /* 6111 */ 'j', 'g', 9, 0, >+ /* 6115 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, >+ /* 6123 */ 's', 'e', 't', 'g', 9, 0, >+ /* 6129 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, >+ /* 6139 */ 'f', 'x', 'c', 'h', 9, 0, >+ /* 6145 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, >+ /* 6156 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, >+ /* 6167 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, >+ /* 6179 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, >+ /* 6188 */ 'b', 'l', 'c', 'i', 9, 0, >+ /* 6194 */ 'f', 'c', 'o', 'm', 'i', 9, 0, >+ /* 6201 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, >+ /* 6209 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, >+ /* 6220 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, >+ /* 6230 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, >+ /* 6241 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, >+ /* 6251 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, >+ /* 6259 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, >+ /* 6268 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, >+ /* 6280 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, >+ /* 6292 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, >+ /* 6304 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, >+ /* 6315 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, 0, >+ /* 6327 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 9, 0, >+ /* 6338 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, >+ /* 6346 */ 't', 'z', 'm', 's', 'k', 9, 0, >+ /* 6353 */ 'c', 'r', 'c', '3', '2', 'l', 9, 0, >+ /* 6361 */ 'l', 'e', 'a', 'l', 9, 0, >+ /* 6367 */ 'c', 'm', 'o', 'v', 'a', 'l', 9, 0, >+ /* 6375 */ 's', 'b', 'b', 'l', 9, 0, >+ /* 6381 */ 'm', 'o', 'v', 's', 'b', 'l', 9, 0, >+ /* 6389 */ 'f', 's', 'u', 'b', 'l', 9, 0, >+ /* 6396 */ 'f', 'i', 's', 'u', 'b', 'l', 9, 0, >+ /* 6404 */ 'c', 'm', 'o', 'v', 'b', 'l', 9, 0, >+ /* 6412 */ 'm', 'o', 'v', 'z', 'b', 'l', 9, 0, >+ /* 6420 */ 'a', 'd', 'c', 'l', 9, 0, >+ /* 6426 */ 'd', 'e', 'c', 'l', 9, 0, >+ /* 6432 */ 'i', 'n', 'c', 'l', 9, 0, >+ /* 6438 */ 'b', 't', 'c', 'l', 9, 0, >+ /* 6444 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, >+ /* 6453 */ 'f', 'a', 'd', 'd', 'l', 9, 0, >+ /* 6460 */ 'f', 'i', 'a', 'd', 'd', 'l', 9, 0, >+ /* 6468 */ 'x', 'a', 'd', 'd', 'l', 9, 0, >+ /* 6475 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, >+ /* 6484 */ 'f', 'l', 'd', 'l', 9, 0, >+ /* 6490 */ 's', 'h', 'l', 'd', 'l', 9, 0, >+ /* 6497 */ 'f', 'i', 'l', 'd', 'l', 9, 0, >+ /* 6504 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, >+ /* 6513 */ 's', 'h', 'r', 'd', 'l', 9, 0, >+ /* 6520 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'l', 9, 0, >+ /* 6532 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'l', 9, 0, >+ /* 6545 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, >+ /* 6554 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, >+ /* 6563 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, >+ /* 6572 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, >+ /* 6581 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, >+ /* 6590 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 6601 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 6612 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 6623 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 6634 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, >+ /* 6644 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, >+ /* 6652 */ 'b', 's', 'f', 'l', 9, 0, >+ /* 6658 */ 'n', 'e', 'g', 'l', 9, 0, >+ /* 6664 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, >+ /* 6674 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, >+ /* 6682 */ 'p', 'u', 's', 'h', 'l', 9, 0, >+ /* 6689 */ 'b', 'z', 'h', 'i', 'l', 9, 0, >+ /* 6696 */ 'b', 'l', 's', 'i', 'l', 9, 0, >+ /* 6703 */ 'm', 'o', 'v', 'n', 't', 'i', 'l', 9, 0, >+ /* 6712 */ 'j', 'l', 9, 0, >+ /* 6716 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, >+ /* 6725 */ 's', 'a', 'l', 'l', 9, 0, >+ /* 6731 */ 'r', 'c', 'l', 'l', 9, 0, >+ /* 6737 */ 'f', 'i', 'l', 'd', 'l', 'l', 9, 0, >+ /* 6745 */ 's', 'h', 'l', 'l', 9, 0, >+ /* 6751 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, >+ /* 6760 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, >+ /* 6769 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, >+ /* 6777 */ 'r', 'o', 'l', 'l', 9, 0, >+ /* 6783 */ 'f', 'i', 's', 't', 'p', 'l', 'l', 9, 0, >+ /* 6792 */ 'f', 'i', 's', 't', 't', 'p', 'l', 'l', 9, 0, >+ /* 6802 */ 'l', 's', 'l', 'l', 9, 0, >+ /* 6808 */ 'f', 'm', 'u', 'l', 'l', 9, 0, >+ /* 6815 */ 'f', 'i', 'm', 'u', 'l', 'l', 9, 0, >+ /* 6823 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, >+ /* 6831 */ 'f', 'c', 'o', 'm', 'l', 9, 0, >+ /* 6838 */ 'f', 'i', 'c', 'o', 'm', 'l', 9, 0, >+ /* 6846 */ 'a', 'n', 'd', 'n', 'l', 9, 0, >+ /* 6853 */ 'i', 'n', 'l', 9, 0, >+ /* 6858 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, >+ /* 6867 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, >+ /* 6875 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, >+ /* 6883 */ 'p', 'd', 'e', 'p', 'l', 9, 0, >+ /* 6890 */ 'c', 'm', 'p', 'l', 9, 0, >+ /* 6896 */ 'l', 'j', 'm', 'p', 'l', 9, 0, >+ /* 6903 */ 'f', 'c', 'o', 'm', 'p', 'l', 9, 0, >+ /* 6911 */ 'f', 'i', 'c', 'o', 'm', 'p', 'l', 9, 0, >+ /* 6920 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, >+ /* 6929 */ 'n', 'o', 'p', 'l', 9, 0, >+ /* 6935 */ 'p', 'o', 'p', 'l', 9, 0, >+ /* 6941 */ 'a', 'r', 'p', 'l', 9, 0, >+ /* 6947 */ 'f', 's', 't', 'p', 'l', 9, 0, >+ /* 6954 */ 'f', 'i', 's', 't', 'p', 'l', 9, 0, >+ /* 6962 */ 'f', 'i', 's', 't', 't', 'p', 'l', 9, 0, >+ /* 6971 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, >+ /* 6979 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'l', 9, 0, >+ /* 6990 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'l', 9, 0, >+ /* 7002 */ 'l', 'a', 'r', 'l', 9, 0, >+ /* 7008 */ 's', 'a', 'r', 'l', 9, 0, >+ /* 7014 */ 'f', 's', 'u', 'b', 'r', 'l', 9, 0, >+ /* 7022 */ 'f', 'i', 's', 'u', 'b', 'r', 'l', 9, 0, >+ /* 7031 */ 'r', 'c', 'r', 'l', 9, 0, >+ /* 7037 */ 's', 'h', 'r', 'l', 9, 0, >+ /* 7043 */ 'r', 'o', 'r', 'l', 9, 0, >+ /* 7049 */ 'x', 'o', 'r', 'l', 9, 0, >+ /* 7055 */ 'b', 's', 'r', 'l', 9, 0, >+ /* 7061 */ 'b', 'l', 's', 'r', 'l', 9, 0, >+ /* 7068 */ 'b', 't', 'r', 'l', 9, 0, >+ /* 7074 */ 's', 't', 'r', 'l', 9, 0, >+ /* 7080 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, >+ /* 7088 */ 'f', 'd', 'i', 'v', 'r', 'l', 9, 0, >+ /* 7096 */ 'f', 'i', 'd', 'i', 'v', 'r', 'l', 9, 0, >+ /* 7105 */ 's', 'c', 'a', 's', 'l', 9, 0, >+ /* 7112 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, >+ /* 7121 */ 'l', 'd', 's', 'l', 9, 0, >+ /* 7127 */ 'l', 'o', 'd', 's', 'l', 9, 0, >+ /* 7134 */ 'l', 'e', 's', 'l', 9, 0, >+ /* 7140 */ 'l', 'f', 's', 'l', 9, 0, >+ /* 7146 */ 'l', 'g', 's', 'l', 9, 0, >+ /* 7152 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, >+ /* 7161 */ 'c', 'm', 'p', 's', 'l', 9, 0, >+ /* 7168 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'l', 9, 0, >+ /* 7180 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'l', 9, 0, >+ /* 7193 */ 'l', 's', 's', 'l', 9, 0, >+ /* 7199 */ 'b', 't', 's', 'l', 9, 0, >+ /* 7205 */ 'o', 'u', 't', 's', 'l', 9, 0, >+ /* 7212 */ 'c', 'm', 'o', 'v', 's', 'l', 9, 0, >+ /* 7220 */ 'b', 't', 'l', 9, 0, >+ /* 7225 */ 'l', 'g', 'd', 't', 'l', 9, 0, >+ /* 7232 */ 's', 'g', 'd', 't', 'l', 9, 0, >+ /* 7239 */ 'l', 'i', 'd', 't', 'l', 9, 0, >+ /* 7246 */ 's', 'i', 'd', 't', 'l', 9, 0, >+ /* 7253 */ 's', 'l', 'd', 't', 'l', 9, 0, >+ /* 7260 */ 'l', 'r', 'e', 't', 'l', 9, 0, >+ /* 7267 */ 's', 'e', 't', 'l', 9, 0, >+ /* 7273 */ 'p', 'o', 'p', 'c', 'n', 't', 'l', 9, 0, >+ /* 7282 */ 'l', 'z', 'c', 'n', 't', 'l', 9, 0, >+ /* 7290 */ 't', 'z', 'c', 'n', 't', 'l', 9, 0, >+ /* 7298 */ 'n', 'o', 't', 'l', 9, 0, >+ /* 7304 */ 't', 'e', 's', 't', 'l', 9, 0, >+ /* 7311 */ 'f', 's', 't', 'l', 9, 0, >+ /* 7317 */ 'f', 'i', 's', 't', 'l', 9, 0, >+ /* 7324 */ 'p', 'e', 'x', 't', 'l', 9, 0, >+ /* 7331 */ 'p', 'f', 'm', 'u', 'l', 9, 0, >+ /* 7338 */ 'f', 'd', 'i', 'v', 'l', 9, 0, >+ /* 7345 */ 'f', 'i', 'd', 'i', 'v', 'l', 9, 0, >+ /* 7353 */ 'm', 'o', 'v', 'l', 9, 0, >+ /* 7359 */ 's', 'm', 's', 'w', 'l', 9, 0, >+ /* 7366 */ 'm', 'o', 'v', 's', 'w', 'l', 9, 0, >+ /* 7374 */ 'm', 'o', 'v', 'z', 'w', 'l', 9, 0, >+ /* 7382 */ 'a', 'd', 'c', 'x', 'l', 9, 0, >+ /* 7389 */ 's', 'h', 'l', 'x', 'l', 9, 0, >+ /* 7396 */ 'm', 'u', 'l', 'x', 'l', 9, 0, >+ /* 7403 */ 'a', 'd', 'o', 'x', 'l', 9, 0, >+ /* 7410 */ 's', 'a', 'r', 'x', 'l', 9, 0, >+ /* 7417 */ 's', 'h', 'r', 'x', 'l', 9, 0, >+ /* 7424 */ 'r', 'o', 'r', 'x', 'l', 9, 0, >+ /* 7431 */ 'a', 'a', 'm', 9, 0, >+ /* 7436 */ 'f', 'c', 'o', 'm', 9, 0, >+ /* 7442 */ 'f', 'u', 'c', 'o', 'm', 9, 0, >+ /* 7449 */ 'v', 'p', 'p', 'e', 'r', 'm', 9, 0, >+ /* 7457 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'm', 9, 0, >+ /* 7469 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'm', 9, 0, >+ /* 7481 */ 'v', 'p', 'a', 'n', 'd', 'n', 9, 0, >+ /* 7489 */ 'x', 'b', 'e', 'g', 'i', 'n', 9, 0, >+ /* 7497 */ 'p', 'f', 'm', 'i', 'n', 9, 0, >+ /* 7504 */ 'v', 'm', 'x', 'o', 'n', 9, 0, >+ /* 7511 */ 'j', 'o', 9, 0, >+ /* 7515 */ 'j', 'n', 'o', 9, 0, >+ /* 7520 */ 's', 'e', 't', 'n', 'o', 9, 0, >+ /* 7527 */ 's', 'e', 't', 'o', 9, 0, >+ /* 7533 */ 'f', 's', 'u', 'b', 'p', 9, 0, >+ /* 7540 */ 'p', 'f', 'r', 'c', 'p', 9, 0, >+ /* 7547 */ 'f', 'a', 'd', 'd', 'p', 9, 0, >+ /* 7554 */ 'j', 'p', 9, 0, >+ /* 7558 */ 'f', 'm', 'u', 'l', 'p', 9, 0, >+ /* 7565 */ 'j', 'm', 'p', 9, 0, >+ /* 7570 */ 'f', 'c', 'o', 'm', 'p', 9, 0, >+ /* 7577 */ 'f', 'u', 'c', 'o', 'm', 'p', 9, 0, >+ /* 7585 */ 'j', 'n', 'p', 9, 0, >+ /* 7590 */ 's', 'e', 't', 'n', 'p', 9, 0, >+ /* 7597 */ 'n', 'o', 'p', 9, 0, >+ /* 7602 */ 'l', 'o', 'o', 'p', 9, 0, >+ /* 7608 */ 'f', 's', 'u', 'b', 'r', 'p', 9, 0, >+ /* 7616 */ 'f', 'd', 'i', 'v', 'r', 'p', 9, 0, >+ /* 7624 */ 's', 'e', 't', 'p', 9, 0, >+ /* 7630 */ 'f', 'b', 's', 't', 'p', 9, 0, >+ /* 7637 */ 'f', 's', 't', 'p', 9, 0, >+ /* 7643 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 9, 0, >+ /* 7653 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 9, 0, >+ /* 7664 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 9, 0, >+ /* 7675 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, >+ /* 7691 */ 'f', 'd', 'i', 'v', 'p', 9, 0, >+ /* 7698 */ 'c', 'r', 'c', '3', '2', 'q', 9, 0, >+ /* 7706 */ 'm', 'o', 'v', 'd', 'q', '2', 'q', 9, 0, >+ /* 7715 */ 'l', 'e', 'a', 'q', 9, 0, >+ /* 7721 */ 'v', 'p', 's', 'h', 'a', 'q', 9, 0, >+ /* 7729 */ 'c', 'm', 'o', 'v', 'a', 'q', 9, 0, >+ /* 7737 */ 's', 'b', 'b', 'q', 9, 0, >+ /* 7743 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'q', 9, 0, >+ /* 7753 */ 'm', 'o', 'v', 's', 'b', 'q', 9, 0, >+ /* 7761 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'q', 9, 0, >+ /* 7772 */ 'v', 'p', 's', 'u', 'b', 'q', 9, 0, >+ /* 7780 */ 'c', 'm', 'o', 'v', 'b', 'q', 9, 0, >+ /* 7788 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 9, 0, >+ /* 7799 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 9, 0, >+ /* 7810 */ 'm', 'o', 'v', 'z', 'b', 'q', 9, 0, >+ /* 7818 */ 'a', 'd', 'c', 'q', 9, 0, >+ /* 7824 */ 'd', 'e', 'c', 'q', 9, 0, >+ /* 7830 */ 'i', 'n', 'c', 'q', 9, 0, >+ /* 7836 */ 'b', 't', 'c', 'q', 9, 0, >+ /* 7842 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, 0, >+ /* 7854 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 9, 0, >+ /* 7865 */ 'm', 'o', 'v', 'q', '2', 'd', 'q', 9, 0, >+ /* 7874 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, 0, >+ /* 7886 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 9, 0, >+ /* 7897 */ 'v', 'm', 'r', 'e', 'a', 'd', 'q', 9, 0, >+ /* 7906 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 'q', 9, 0, >+ /* 7916 */ 'v', 'p', 'a', 'd', 'd', 'q', 9, 0, >+ /* 7924 */ 'x', 'a', 'd', 'd', 'q', 9, 0, >+ /* 7931 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 'q', 9, 0, >+ /* 7941 */ 'r', 'd', 's', 'e', 'e', 'd', 'q', 9, 0, >+ /* 7950 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 9, 0, >+ /* 7962 */ 's', 'h', 'l', 'd', 'q', 9, 0, >+ /* 7969 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 9, 0, >+ /* 7981 */ 'v', 'p', 's', 'l', 'l', 'd', 'q', 9, 0, >+ /* 7990 */ 'v', 'p', 's', 'r', 'l', 'd', 'q', 9, 0, >+ /* 7999 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 9, 0, >+ /* 8008 */ 'r', 'd', 'r', 'a', 'n', 'd', 'q', 9, 0, >+ /* 8017 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, >+ /* 8030 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, >+ /* 8043 */ 'v', 'p', 'c', 'l', 'm', 'u', 'l', 'q', 'd', 'q', 9, 0, >+ /* 8055 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 9, 0, >+ /* 8067 */ 's', 'h', 'r', 'd', 'q', 9, 0, >+ /* 8074 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 'q', 9, 0, >+ /* 8086 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 'q', 9, 0, >+ /* 8099 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 9, 0, >+ /* 8109 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'd', 'q', 9, 0, >+ /* 8120 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 9, 0, >+ /* 8130 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 9, 0, >+ /* 8141 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 9, 0, >+ /* 8152 */ 'c', 'm', 'o', 'v', 'a', 'e', 'q', 9, 0, >+ /* 8161 */ 'c', 'm', 'o', 'v', 'b', 'e', 'q', 9, 0, >+ /* 8170 */ 'c', 'm', 'o', 'v', 'g', 'e', 'q', 9, 0, >+ /* 8179 */ 'c', 'm', 'o', 'v', 'l', 'e', 'q', 9, 0, >+ /* 8188 */ 'c', 'm', 'o', 'v', 'n', 'e', 'q', 9, 0, >+ /* 8197 */ 'p', 'f', 'c', 'm', 'p', 'e', 'q', 9, 0, >+ /* 8206 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 8217 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 8228 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 8239 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 8250 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, >+ /* 8260 */ 'f', 'x', 's', 'a', 'v', 'e', 'q', 9, 0, >+ /* 8269 */ 'c', 'm', 'o', 'v', 'e', 'q', 9, 0, >+ /* 8277 */ 'b', 's', 'f', 'q', 9, 0, >+ /* 8283 */ 'n', 'e', 'g', 'q', 9, 0, >+ /* 8289 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'q', 9, 0, >+ /* 8299 */ 'c', 'm', 'o', 'v', 'g', 'q', 9, 0, >+ /* 8307 */ 'p', 'u', 's', 'h', 'q', 9, 0, >+ /* 8314 */ 'b', 'z', 'h', 'i', 'q', 9, 0, >+ /* 8321 */ 'b', 'l', 's', 'i', 'q', 9, 0, >+ /* 8328 */ 'm', 'o', 'v', 'n', 't', 'i', 'q', 9, 0, >+ /* 8337 */ 'b', 'l', 's', 'm', 's', 'k', 'q', 9, 0, >+ /* 8346 */ 's', 'a', 'l', 'q', 9, 0, >+ /* 8352 */ 'r', 'c', 'l', 'q', 9, 0, >+ /* 8358 */ 'v', 'p', 's', 'h', 'l', 'q', 9, 0, >+ /* 8366 */ 'c', 'a', 'l', 'l', 'q', 9, 0, >+ /* 8373 */ 'v', 'p', 's', 'l', 'l', 'q', 9, 0, >+ /* 8381 */ 'r', 'o', 'l', 'q', 9, 0, >+ /* 8387 */ 'v', 'p', 's', 'r', 'l', 'q', 9, 0, >+ /* 8395 */ 'l', 's', 'l', 'q', 9, 0, >+ /* 8401 */ 'm', 'o', 'v', 's', 'l', 'q', 9, 0, >+ /* 8409 */ 'i', 'm', 'u', 'l', 'q', 9, 0, >+ /* 8416 */ 'c', 'm', 'o', 'v', 'l', 'q', 9, 0, >+ /* 8424 */ 'v', 'p', 'c', 'o', 'm', 'q', 9, 0, >+ /* 8432 */ 'v', 'p', 'e', 'r', 'm', 'q', 9, 0, >+ /* 8440 */ 'a', 'n', 'd', 'n', 'q', 9, 0, >+ /* 8447 */ 'c', 'm', 'o', 'v', 'n', 'o', 'q', 9, 0, >+ /* 8456 */ 'c', 'm', 'o', 'v', 'o', 'q', 9, 0, >+ /* 8464 */ 'b', 's', 'w', 'a', 'p', 'q', 9, 0, >+ /* 8472 */ 'p', 'd', 'e', 'p', 'q', 9, 0, >+ /* 8479 */ 'v', 'p', 'c', 'm', 'p', 'q', 9, 0, >+ /* 8487 */ 'c', 'm', 'o', 'v', 'n', 'p', 'q', 9, 0, >+ /* 8496 */ 'p', 'o', 'p', 'q', 9, 0, >+ /* 8502 */ 'c', 'm', 'o', 'v', 'p', 'q', 9, 0, >+ /* 8510 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'q', 9, 0, >+ /* 8520 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 9, 0, >+ /* 8532 */ 'l', 'a', 'r', 'q', 9, 0, >+ /* 8538 */ 's', 'a', 'r', 'q', 9, 0, >+ /* 8544 */ 'r', 'c', 'r', 'q', 9, 0, >+ /* 8550 */ 's', 'h', 'r', 'q', 9, 0, >+ /* 8556 */ 'r', 'o', 'r', 'q', 9, 0, >+ /* 8562 */ 'f', 'x', 'r', 's', 't', 'o', 'r', 'q', 9, 0, >+ /* 8572 */ 'x', 'o', 'r', 'q', 9, 0, >+ /* 8578 */ 'b', 's', 'r', 'q', 9, 0, >+ /* 8584 */ 'b', 'l', 's', 'r', 'q', 9, 0, >+ /* 8591 */ 'v', 'p', 'i', 'n', 's', 'r', 'q', 9, 0, >+ /* 8600 */ 'b', 't', 'r', 'q', 9, 0, >+ /* 8606 */ 's', 't', 'r', 'q', 9, 0, >+ /* 8612 */ 'b', 'e', 'x', 't', 'r', 'q', 9, 0, >+ /* 8620 */ 'v', 'p', 'e', 'x', 't', 'r', 'q', 9, 0, >+ /* 8629 */ 's', 'c', 'a', 's', 'q', 9, 0, >+ /* 8636 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, 0, >+ /* 8645 */ 'l', 'o', 'd', 's', 'q', 9, 0, >+ /* 8652 */ 'l', 'f', 's', 'q', 9, 0, >+ /* 8658 */ 'l', 'g', 's', 'q', 9, 0, >+ /* 8664 */ 'c', 'm', 'o', 'v', 'n', 's', 'q', 9, 0, >+ /* 8673 */ 'c', 'm', 'p', 's', 'q', 9, 0, >+ /* 8680 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 'q', 9, 0, >+ /* 8692 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 'q', 9, 0, >+ /* 8705 */ 'l', 's', 's', 'q', 9, 0, >+ /* 8711 */ 'b', 't', 's', 'q', 9, 0, >+ /* 8717 */ 'c', 'm', 'o', 'v', 's', 'q', 9, 0, >+ /* 8725 */ 'b', 't', 'q', 9, 0, >+ /* 8730 */ 'l', 'g', 'd', 't', 'q', 9, 0, >+ /* 8737 */ 's', 'g', 'd', 't', 'q', 9, 0, >+ /* 8744 */ 'l', 'i', 'd', 't', 'q', 9, 0, >+ /* 8751 */ 's', 'i', 'd', 't', 'q', 9, 0, >+ /* 8758 */ 's', 'l', 'd', 't', 'q', 9, 0, >+ /* 8765 */ 'l', 'r', 'e', 't', 'q', 9, 0, >+ /* 8772 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'q', 9, 0, >+ /* 8782 */ 'p', 'o', 'p', 'c', 'n', 't', 'q', 9, 0, >+ /* 8791 */ 'l', 'z', 'c', 'n', 't', 'q', 9, 0, >+ /* 8799 */ 't', 'z', 'c', 'n', 't', 'q', 9, 0, >+ /* 8807 */ 'm', 'o', 'v', 'n', 't', 'q', 9, 0, >+ /* 8815 */ 'n', 'o', 't', 'q', 9, 0, >+ /* 8821 */ 'v', 'p', 'r', 'o', 't', 'q', 9, 0, >+ /* 8829 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 'q', 9, 0, >+ /* 8840 */ 'i', 'n', 's', 'e', 'r', 't', 'q', 9, 0, >+ /* 8849 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 9, 0, >+ /* 8863 */ 't', 'e', 's', 't', 'q', 9, 0, >+ /* 8870 */ 'p', 'e', 'x', 't', 'q', 9, 0, >+ /* 8877 */ 'v', 'p', 'c', 'o', 'm', 'u', 'q', 9, 0, >+ /* 8886 */ 'v', 'p', 'c', 'm', 'p', 'u', 'q', 9, 0, >+ /* 8895 */ 'i', 'd', 'i', 'v', 'q', 9, 0, >+ /* 8902 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 9, 0, >+ /* 8911 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 9, 0, >+ /* 8920 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'q', 9, 0, >+ /* 8932 */ 'v', 'm', 'o', 'v', 'q', 9, 0, >+ /* 8939 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'q', 9, 0, >+ /* 8949 */ 's', 'm', 's', 'w', 'q', 9, 0, >+ /* 8956 */ 'm', 'o', 'v', 's', 'w', 'q', 9, 0, >+ /* 8964 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'q', 9, 0, >+ /* 8975 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 9, 0, >+ /* 8986 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 9, 0, >+ /* 8997 */ 'm', 'o', 'v', 'z', 'w', 'q', 9, 0, >+ /* 9005 */ 'a', 'd', 'c', 'x', 'q', 9, 0, >+ /* 9012 */ 's', 'h', 'l', 'x', 'q', 9, 0, >+ /* 9019 */ 'm', 'u', 'l', 'x', 'q', 9, 0, >+ /* 9026 */ 'a', 'd', 'o', 'x', 'q', 9, 0, >+ /* 9033 */ 's', 'a', 'r', 'x', 'q', 9, 0, >+ /* 9040 */ 's', 'h', 'r', 'x', 'q', 9, 0, >+ /* 9047 */ 'r', 'o', 'r', 'x', 'q', 9, 0, >+ /* 9054 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, >+ /* 9063 */ 'p', 'f', 's', 'u', 'b', 'r', 9, 0, >+ /* 9071 */ 'e', 'n', 't', 'e', 'r', 9, 0, >+ /* 9078 */ 'v', 'p', 'a', 'l', 'i', 'g', 'n', 'r', 9, 0, >+ /* 9088 */ 'v', 'p', 'o', 'r', 9, 0, >+ /* 9094 */ 'f', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 9102 */ 'f', 'x', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 9111 */ 'v', 'p', 'x', 'o', 'r', 9, 0, >+ /* 9118 */ 'v', 'e', 'r', 'r', 9, 0, >+ /* 9124 */ 'v', 'l', 'd', 'm', 'x', 'c', 's', 'r', 9, 0, >+ /* 9134 */ 'v', 's', 't', 'm', 'x', 'c', 's', 'r', 9, 0, >+ /* 9144 */ 'b', 'e', 'x', 't', 'r', 9, 0, >+ /* 9151 */ 'f', 'd', 'i', 'v', 'r', 9, 0, >+ /* 9158 */ 'f', 's', 'u', 'b', 's', 9, 0, >+ /* 9165 */ 'f', 'i', 's', 'u', 'b', 's', 9, 0, >+ /* 9173 */ 'b', 'l', 'c', 's', 9, 0, >+ /* 9179 */ 'f', 'a', 'd', 'd', 's', 9, 0, >+ /* 9186 */ 'f', 'i', 'a', 'd', 'd', 's', 9, 0, >+ /* 9194 */ 'f', 'l', 'd', 's', 9, 0, >+ /* 9200 */ 'f', 'i', 'l', 'd', 's', 9, 0, >+ /* 9207 */ 'j', 's', 9, 0, >+ /* 9211 */ 'f', 'm', 'u', 'l', 's', 9, 0, >+ /* 9218 */ 'f', 'i', 'm', 'u', 'l', 's', 9, 0, >+ /* 9226 */ 'f', 'c', 'o', 'm', 's', 9, 0, >+ /* 9233 */ 'f', 'i', 'c', 'o', 'm', 's', 9, 0, >+ /* 9241 */ 'j', 'n', 's', 9, 0, >+ /* 9246 */ 's', 'e', 't', 'n', 's', 9, 0, >+ /* 9253 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9269 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9282 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9296 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9312 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9325 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 9339 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9355 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9368 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9382 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9398 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9411 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 9425 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, >+ /* 9436 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, >+ /* 9447 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, >+ /* 9457 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, >+ /* 9469 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, >+ /* 9480 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9496 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9509 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9523 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9539 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9552 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 9566 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, >+ /* 9575 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9588 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9599 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9608 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9618 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9629 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 9637 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 9650 */ 'v', 'h', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 9659 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 9669 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 9680 */ 'v', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 9688 */ 'v', 'a', 'n', 'd', 'p', 's', 9, 0, >+ /* 9696 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 's', 9, 0, >+ /* 9706 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 's', 9, 0, >+ /* 9716 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 9, 0, >+ /* 9728 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 9, 0, >+ /* 9737 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 's', 9, 0, >+ /* 9748 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, >+ /* 9758 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, >+ /* 9767 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, >+ /* 9778 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, >+ /* 9788 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, >+ /* 9799 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, >+ /* 9810 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, >+ /* 9818 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, >+ /* 9827 */ 'f', 'c', 'o', 'm', 'p', 's', 9, 0, >+ /* 9835 */ 'f', 'i', 'c', 'o', 'm', 'p', 's', 9, 0, >+ /* 9844 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, >+ /* 9853 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, >+ /* 9862 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, >+ /* 9870 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, >+ /* 9878 */ 'v', 'd', 'p', 'p', 's', 9, 0, >+ /* 9885 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, >+ /* 9893 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, >+ /* 9905 */ 'v', 'o', 'r', 'p', 's', 9, 0, >+ /* 9912 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, >+ /* 9920 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, >+ /* 9932 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, >+ /* 9942 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, >+ /* 9953 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, >+ /* 9963 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, >+ /* 9972 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, >+ /* 9981 */ 'f', 's', 't', 'p', 's', 9, 0, >+ /* 9988 */ 'f', 'i', 's', 't', 'p', 's', 9, 0, >+ /* 9996 */ 'f', 'i', 's', 't', 't', 'p', 's', 9, 0, >+ /* 10005 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, >+ /* 10014 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, >+ /* 10025 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, >+ /* 10033 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, >+ /* 10045 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, >+ /* 10053 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, >+ /* 10062 */ 'f', 's', 'u', 'b', 'r', 's', 9, 0, >+ /* 10070 */ 'f', 'i', 's', 'u', 'b', 'r', 's', 9, 0, >+ /* 10079 */ 'f', 'd', 'i', 'v', 'r', 's', 9, 0, >+ /* 10087 */ 'f', 'i', 'd', 'i', 'v', 'r', 's', 9, 0, >+ /* 10096 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, >+ /* 10109 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, >+ /* 10123 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, >+ /* 10136 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, >+ /* 10150 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, >+ /* 10163 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, >+ /* 10177 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, >+ /* 10190 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, >+ /* 10204 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, >+ /* 10215 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, >+ /* 10228 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, >+ /* 10242 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, >+ /* 10255 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, >+ /* 10269 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 10279 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 10290 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 10298 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 10308 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 10319 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 10327 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, >+ /* 10337 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, >+ /* 10347 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, >+ /* 10356 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, >+ /* 10364 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, >+ /* 10372 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, >+ /* 10380 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, >+ /* 10388 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, >+ /* 10397 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, >+ /* 10407 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, >+ /* 10416 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, >+ /* 10430 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, >+ /* 10438 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, >+ /* 10446 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, >+ /* 10454 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, >+ /* 10463 */ 's', 'e', 't', 's', 9, 0, >+ /* 10469 */ 'f', 's', 't', 's', 9, 0, >+ /* 10475 */ 'f', 'i', 's', 't', 's', 9, 0, >+ /* 10482 */ 'f', 'd', 'i', 'v', 's', 9, 0, >+ /* 10489 */ 'f', 'i', 'd', 'i', 'v', 's', 9, 0, >+ /* 10497 */ 'f', 'l', 'd', 't', 9, 0, >+ /* 10503 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, >+ /* 10512 */ 'i', 'n', 't', 9, 0, >+ /* 10517 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, >+ /* 10525 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, >+ /* 10535 */ 'f', 's', 't', 'p', 't', 9, 0, >+ /* 10542 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, >+ /* 10550 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, >+ /* 10559 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, >+ /* 10572 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, >+ /* 10585 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, >+ /* 10593 */ 'f', 's', 't', 9, 0, >+ /* 10598 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, >+ /* 10616 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, >+ /* 10625 */ 'f', 'c', 'm', 'o', 'v', 'n', 'u', 9, 0, >+ /* 10634 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, >+ /* 10642 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, >+ /* 10655 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, >+ /* 10664 */ 'f', 'c', 'm', 'o', 'v', 'u', 9, 0, >+ /* 10672 */ 'f', 'd', 'i', 'v', 9, 0, >+ /* 10678 */ 'f', 'l', 'd', 'e', 'n', 'v', 9, 0, >+ /* 10686 */ 'f', 'n', 's', 't', 'e', 'n', 'v', 9, 0, >+ /* 10695 */ 'v', 'p', 'c', 'm', 'o', 'v', 9, 0, >+ /* 10703 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, >+ /* 10711 */ 'l', 'e', 'a', 'w', 9, 0, >+ /* 10717 */ 'v', 'p', 's', 'h', 'a', 'w', 9, 0, >+ /* 10725 */ 'v', 'p', 's', 'r', 'a', 'w', 9, 0, >+ /* 10733 */ 'c', 'm', 'o', 'v', 'a', 'w', 9, 0, >+ /* 10741 */ 's', 'b', 'b', 'w', 9, 0, >+ /* 10747 */ 'v', 'p', 'h', 's', 'u', 'b', 'b', 'w', 9, 0, >+ /* 10757 */ 'v', 'm', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, >+ /* 10767 */ 'v', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, >+ /* 10776 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'w', 9, 0, >+ /* 10786 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'b', 'w', 9, 0, >+ /* 10798 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'b', 'w', 9, 0, >+ /* 10810 */ 'm', 'o', 'v', 's', 'b', 'w', 9, 0, >+ /* 10818 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'w', 9, 0, >+ /* 10829 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 9, 0, >+ /* 10838 */ 'v', 'p', 's', 'u', 'b', 'w', 9, 0, >+ /* 10846 */ 'c', 'm', 'o', 'v', 'b', 'w', 9, 0, >+ /* 10854 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'w', 9, 0, >+ /* 10865 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'w', 9, 0, >+ /* 10876 */ 'm', 'o', 'v', 'z', 'b', 'w', 9, 0, >+ /* 10884 */ 'a', 'd', 'c', 'w', 9, 0, >+ /* 10890 */ 'f', 'l', 'd', 'c', 'w', 9, 0, >+ /* 10897 */ 'd', 'e', 'c', 'w', 9, 0, >+ /* 10903 */ 'i', 'n', 'c', 'w', 9, 0, >+ /* 10909 */ 'b', 't', 'c', 'w', 9, 0, >+ /* 10915 */ 'f', 'n', 's', 't', 'c', 'w', 9, 0, >+ /* 10923 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 9, 0, >+ /* 10932 */ 'v', 'p', 'a', 'd', 'd', 'w', 9, 0, >+ /* 10940 */ 'x', 'a', 'd', 'd', 'w', 9, 0, >+ /* 10947 */ 'r', 'd', 's', 'e', 'e', 'd', 'w', 9, 0, >+ /* 10956 */ 's', 'h', 'l', 'd', 'w', 9, 0, >+ /* 10963 */ 'r', 'd', 'r', 'a', 'n', 'd', 'w', 9, 0, >+ /* 10972 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'w', 9, 0, >+ /* 10982 */ 's', 'h', 'r', 'd', 'w', 9, 0, >+ /* 10989 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'd', 'w', 9, 0, >+ /* 11000 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'd', 'w', 9, 0, >+ /* 11011 */ 'c', 'm', 'o', 'v', 'a', 'e', 'w', 9, 0, >+ /* 11020 */ 'c', 'm', 'o', 'v', 'b', 'e', 'w', 9, 0, >+ /* 11029 */ 'c', 'm', 'o', 'v', 'g', 'e', 'w', 9, 0, >+ /* 11038 */ 'c', 'm', 'o', 'v', 'l', 'e', 'w', 9, 0, >+ /* 11047 */ 'c', 'm', 'o', 'v', 'n', 'e', 'w', 9, 0, >+ /* 11056 */ 'c', 'm', 'o', 'v', 'e', 'w', 9, 0, >+ /* 11064 */ 'p', 'i', '2', 'f', 'w', 9, 0, >+ /* 11071 */ 'b', 's', 'f', 'w', 9, 0, >+ /* 11077 */ 'p', 's', 'h', 'u', 'f', 'w', 9, 0, >+ /* 11085 */ 'n', 'e', 'g', 'w', 9, 0, >+ /* 11091 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'w', 9, 0, >+ /* 11101 */ 'v', 'p', 'a', 'v', 'g', 'w', 9, 0, >+ /* 11109 */ 'c', 'm', 'o', 'v', 'g', 'w', 9, 0, >+ /* 11117 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'w', 9, 0, >+ /* 11128 */ 'v', 'p', 's', 'h', 'u', 'f', 'h', 'w', 9, 0, >+ /* 11138 */ 'v', 'p', 'm', 'u', 'l', 'h', 'w', 9, 0, >+ /* 11147 */ 'p', 'u', 's', 'h', 'w', 9, 0, >+ /* 11154 */ 'p', 'f', '2', 'i', 'w', 9, 0, >+ /* 11161 */ 's', 'a', 'l', 'w', 9, 0, >+ /* 11167 */ 'r', 'c', 'l', 'w', 9, 0, >+ /* 11173 */ 'v', 'p', 's', 'h', 'u', 'f', 'l', 'w', 9, 0, >+ /* 11183 */ 'v', 'p', 's', 'h', 'l', 'w', 9, 0, >+ /* 11191 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, 0, >+ /* 11199 */ 'v', 'p', 's', 'l', 'l', 'w', 9, 0, >+ /* 11207 */ 'v', 'p', 'm', 'u', 'l', 'l', 'w', 9, 0, >+ /* 11216 */ 'r', 'o', 'l', 'w', 9, 0, >+ /* 11222 */ 'v', 'p', 's', 'r', 'l', 'w', 9, 0, >+ /* 11230 */ 'l', 's', 'l', 'w', 9, 0, >+ /* 11236 */ 'i', 'm', 'u', 'l', 'w', 9, 0, >+ /* 11243 */ 'c', 'm', 'o', 'v', 'l', 'w', 9, 0, >+ /* 11251 */ 'v', 'p', 'c', 'o', 'm', 'w', 9, 0, >+ /* 11259 */ 'v', 'p', 's', 'i', 'g', 'n', 'w', 9, 0, >+ /* 11268 */ 'i', 'n', 'w', 9, 0, >+ /* 11273 */ 'c', 'm', 'o', 'v', 'n', 'o', 'w', 9, 0, >+ /* 11282 */ 'c', 'm', 'o', 'v', 'o', 'w', 9, 0, >+ /* 11290 */ 'c', 'm', 'p', 'w', 9, 0, >+ /* 11296 */ 'l', 'j', 'm', 'p', 'w', 9, 0, >+ /* 11303 */ 'c', 'm', 'o', 'v', 'n', 'p', 'w', 9, 0, >+ /* 11312 */ 'n', 'o', 'p', 'w', 9, 0, >+ /* 11318 */ 'p', 'o', 'p', 'w', 9, 0, >+ /* 11324 */ 'c', 'm', 'o', 'v', 'p', 'w', 9, 0, >+ /* 11332 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'w', 9, 0, >+ /* 11342 */ 'l', 'a', 'r', 'w', 9, 0, >+ /* 11348 */ 's', 'a', 'r', 'w', 9, 0, >+ /* 11354 */ 'r', 'c', 'r', 'w', 9, 0, >+ /* 11360 */ 'v', 'e', 'r', 'w', 9, 0, >+ /* 11366 */ 'p', 'm', 'u', 'l', 'h', 'r', 'w', 9, 0, >+ /* 11375 */ 's', 'h', 'r', 'w', 9, 0, >+ /* 11381 */ 'r', 'o', 'r', 'w', 9, 0, >+ /* 11387 */ 'x', 'o', 'r', 'w', 9, 0, >+ /* 11393 */ 'b', 's', 'r', 'w', 9, 0, >+ /* 11399 */ 'v', 'p', 'i', 'n', 's', 'r', 'w', 9, 0, >+ /* 11408 */ 'b', 't', 'r', 'w', 9, 0, >+ /* 11414 */ 'l', 't', 'r', 'w', 9, 0, >+ /* 11420 */ 's', 't', 'r', 'w', 9, 0, >+ /* 11426 */ 'v', 'p', 'e', 'x', 't', 'r', 'w', 9, 0, >+ /* 11435 */ 's', 'c', 'a', 's', 'w', 9, 0, >+ /* 11442 */ 'v', 'p', 'a', 'b', 's', 'w', 9, 0, >+ /* 11450 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, 0, >+ /* 11459 */ 'v', 'p', 'm', 'a', 'd', 'd', 'u', 'b', 's', 'w', 9, 0, >+ /* 11471 */ 'v', 'p', 'h', 's', 'u', 'b', 's', 'w', 9, 0, >+ /* 11481 */ 'v', 'p', 's', 'u', 'b', 's', 'w', 9, 0, >+ /* 11490 */ 'v', 'p', 'h', 'a', 'd', 'd', 's', 'w', 9, 0, >+ /* 11500 */ 'v', 'p', 'a', 'd', 'd', 's', 'w', 9, 0, >+ /* 11509 */ 'l', 'd', 's', 'w', 9, 0, >+ /* 11515 */ 'l', 'o', 'd', 's', 'w', 9, 0, >+ /* 11522 */ 'l', 'e', 's', 'w', 9, 0, >+ /* 11528 */ 'l', 'f', 's', 'w', 9, 0, >+ /* 11534 */ 'l', 'g', 's', 'w', 9, 0, >+ /* 11540 */ 'v', 'p', 'm', 'i', 'n', 's', 'w', 9, 0, >+ /* 11549 */ 'c', 'm', 'o', 'v', 'n', 's', 'w', 9, 0, >+ /* 11558 */ 'c', 'm', 'p', 's', 'w', 9, 0, >+ /* 11565 */ 'v', 'p', 'm', 'u', 'l', 'h', 'r', 's', 'w', 9, 0, >+ /* 11576 */ 'l', 's', 's', 'w', 9, 0, >+ /* 11582 */ 'b', 't', 's', 'w', 9, 0, >+ /* 11588 */ 'f', 'n', 's', 't', 's', 'w', 9, 0, >+ /* 11596 */ 'o', 'u', 't', 's', 'w', 9, 0, >+ /* 11603 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'w', 9, 0, >+ /* 11613 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'w', 9, 0, >+ /* 11623 */ 'c', 'm', 'o', 'v', 's', 'w', 9, 0, >+ /* 11631 */ 'v', 'p', 'm', 'a', 'x', 's', 'w', 9, 0, >+ /* 11640 */ 'b', 't', 'w', 9, 0, >+ /* 11645 */ 'l', 'g', 'd', 't', 'w', 9, 0, >+ /* 11652 */ 's', 'g', 'd', 't', 'w', 9, 0, >+ /* 11659 */ 'l', 'i', 'd', 't', 'w', 9, 0, >+ /* 11666 */ 's', 'i', 'd', 't', 'w', 9, 0, >+ /* 11673 */ 'l', 'l', 'd', 't', 'w', 9, 0, >+ /* 11680 */ 's', 'l', 'd', 't', 'w', 9, 0, >+ /* 11687 */ 'l', 'r', 'e', 't', 'w', 9, 0, >+ /* 11694 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'w', 9, 0, >+ /* 11704 */ 'p', 'o', 'p', 'c', 'n', 't', 'w', 9, 0, >+ /* 11713 */ 'l', 'z', 'c', 'n', 't', 'w', 9, 0, >+ /* 11721 */ 't', 'z', 'c', 'n', 't', 'w', 9, 0, >+ /* 11729 */ 'n', 'o', 't', 'w', 9, 0, >+ /* 11735 */ 'v', 'p', 'r', 'o', 't', 'w', 9, 0, >+ /* 11743 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'w', 9, 0, >+ /* 11757 */ 't', 'e', 's', 't', 'w', 9, 0, >+ /* 11764 */ 'v', 'p', 'm', 'u', 'l', 'h', 'u', 'w', 9, 0, >+ /* 11774 */ 'v', 'p', 'c', 'o', 'm', 'u', 'w', 9, 0, >+ /* 11783 */ 'v', 'p', 'm', 'i', 'n', 'u', 'w', 9, 0, >+ /* 11792 */ 'v', 'p', 'h', 'm', 'i', 'n', 'p', 'o', 's', 'u', 'w', 9, 0, >+ /* 11805 */ 'v', 'p', 'm', 'a', 'x', 'u', 'w', 9, 0, >+ /* 11814 */ 'i', 'd', 'i', 'v', 'w', 9, 0, >+ /* 11821 */ 'm', 'o', 'v', 'w', 9, 0, >+ /* 11827 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'w', 9, 0, >+ /* 11837 */ 'l', 'm', 's', 'w', 'w', 9, 0, >+ /* 11844 */ 's', 'm', 's', 'w', 'w', 9, 0, >+ /* 11851 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'w', 9, 0, >+ /* 11862 */ 'p', 'f', 'm', 'a', 'x', 9, 0, >+ /* 11869 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, >+ /* 11882 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'x', 9, 0, >+ /* 11894 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'x', 9, 0, >+ /* 11906 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, >+ /* 11919 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 'y', 9, 0, >+ /* 11931 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 'y', 9, 0, >+ /* 11943 */ 'j', 'e', 'c', 'x', 'z', 9, 0, >+ /* 11950 */ 'j', 'c', 'x', 'z', 9, 0, >+ /* 11956 */ 'j', 'r', 'c', 'x', 'z', 9, 0, >+ /* 11963 */ 'f', 's', 'u', 'b', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 11977 */ 'f', 'a', 'd', 'd', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 11991 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12008 */ 'f', 'm', 'u', 'l', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12022 */ 'f', 's', 't', 'p', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12036 */ 'f', 's', 'u', 'b', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12051 */ 'f', 'd', 'i', 'v', 'r', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12066 */ 'f', 'd', 'i', 'v', 9, '%', 's', 't', '(', '0', ')', ',', 32, 0, >+ /* 12080 */ 's', 'a', 'l', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12090 */ 'r', 'c', 'l', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12100 */ 's', 'h', 'l', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12110 */ 'r', 'o', 'l', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12120 */ 's', 'a', 'r', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12130 */ 'r', 'c', 'r', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12140 */ 's', 'h', 'r', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12150 */ 'r', 'o', 'r', 'b', 9, '$', '1', ',', 32, 0, >+ /* 12160 */ 's', 'a', 'l', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12170 */ 'r', 'c', 'l', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12180 */ 's', 'h', 'l', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12190 */ 'r', 'o', 'l', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12200 */ 's', 'a', 'r', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12210 */ 'r', 'c', 'r', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12220 */ 's', 'h', 'r', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12230 */ 'r', 'o', 'r', 'l', 9, '$', '1', ',', 32, 0, >+ /* 12240 */ 's', 'a', 'l', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12250 */ 'r', 'c', 'l', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12260 */ 's', 'h', 'l', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12270 */ 'r', 'o', 'l', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12280 */ 's', 'a', 'r', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12290 */ 'r', 'c', 'r', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12300 */ 's', 'h', 'r', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12310 */ 'r', 'o', 'r', 'q', 9, '$', '1', ',', 32, 0, >+ /* 12320 */ 's', 'a', 'l', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12330 */ 'r', 'c', 'l', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12340 */ 's', 'h', 'l', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12350 */ 'r', 'o', 'l', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12360 */ 's', 'a', 'r', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12370 */ 'r', 'c', 'r', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12380 */ 's', 'h', 'r', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12390 */ 'r', 'o', 'r', 'w', 9, '$', '1', ',', 32, 0, >+ /* 12400 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 12414 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 12426 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 12437 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 12448 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12459 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12470 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12481 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12492 */ 's', 'a', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12503 */ 'r', 'c', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12514 */ 's', 'h', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12525 */ 'r', 'o', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12536 */ 's', 'h', 'l', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12548 */ 's', 'h', 'r', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12560 */ 's', 'a', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12571 */ 'r', 'c', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12582 */ 's', 'h', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12593 */ 'r', 'o', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12604 */ 's', 'a', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12615 */ 'r', 'c', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12626 */ 's', 'h', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12637 */ 'r', 'o', 'r', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12648 */ 's', 'h', 'l', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12660 */ 's', 'h', 'r', 'd', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12672 */ 's', 'a', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12683 */ 'r', 'c', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12694 */ 's', 'h', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12705 */ 'r', 'o', 'l', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12716 */ 's', 'a', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12727 */ 'r', 'c', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12738 */ 's', 'h', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12749 */ 'r', 'o', 'r', 'q', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12760 */ 's', 'h', 'l', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12772 */ 's', 'h', 'r', 'd', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12784 */ 's', 'a', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12795 */ 'r', 'c', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12806 */ 's', 'h', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12817 */ 'r', 'o', 'l', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12828 */ 's', 'a', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12839 */ 'r', 'c', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12850 */ 's', 'h', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12861 */ 'r', 'o', 'r', 'w', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 12872 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, >+ /* 12886 */ 's', 't', 'o', 's', 'w', 9, '%', 'a', 'x', ',', 32, 0, >+ /* 12898 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, 0, >+ /* 12909 */ 'm', 'o', 'v', 'w', 9, '%', 'a', 'x', ',', 32, 0, >+ /* 12920 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, >+ /* 12935 */ 's', 't', 'o', 's', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, >+ /* 12948 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, >+ /* 12960 */ 'm', 'o', 'v', 'l', 9, '%', 'e', 'a', 'x', ',', 32, 0, >+ /* 12972 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, >+ /* 12987 */ 's', 't', 'o', 's', 'q', 9, '%', 'r', 'a', 'x', ',', 32, 0, >+ /* 13000 */ 'i', 'n', 's', 'b', 9, '%', 'd', 'x', ',', 32, 0, >+ /* 13011 */ 'i', 'n', 's', 'l', 9, '%', 'd', 'x', ',', 32, 0, >+ /* 13022 */ 'i', 'n', 's', 'w', 9, '%', 'd', 'x', ',', 32, 0, >+ /* 13033 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13051 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13071 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13089 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13109 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13127 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13147 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13165 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 32, 9, '{', 's', 'a', 'e', '}', ',', 32, 0, >+ /* 13185 */ 'r', 'c', 'l', 'l', 9, '$', '1', 32, 0, >+ /* 13194 */ '#', 'V', 'A', 'A', 'R', 'G', '_', '6', '4', 32, 0, >+ /* 13205 */ 'r', 'e', 't', 9, '#', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', ',', 32, 'a', 'd', 'd', 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'h', 'l', 9, '%', 'f', 's', 0, >+ /* 14975 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, >+ /* 14984 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, >+ /* 14994 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, >+ /* 15003 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, >+ /* 15013 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, >+ /* 15022 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, >+ /* 15032 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, >+ /* 15041 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, >+ /* 15051 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, >+ /* 15060 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, >+ /* 15070 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, >+ /* 15079 */ 's', 'w', 'a', 'p', 'g', 's', 0, >+ /* 15086 */ 'f', 'c', 'h', 's', 0, >+ /* 15091 */ '#', 32, 'v', 'a', 'r', 'i', 'a', 'b', 'l', 'e', 32, 's', 'i', 'z', 'e', 'd', 32, 'a', 'l', 'l', 'o', 'c', 'a', 32, 'f', 'o', 'r', 32, 's', 'e', 'g', 'm', 'e', 'n', 't', 'e', 'd', 32, 's', 't', 'a', 'c', 'k', 's', 0, >+ /* 15136 */ 'e', 'n', 'c', 'l', 's', 0, >+ /* 15142 */ 'f', 'e', 'm', 'm', 's', 0, >+ /* 15148 */ 'f', 'c', 'o', 's', 0, >+ /* 15153 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, >+ /* 15161 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, >+ /* 15171 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, >+ /* 15180 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, >+ /* 15190 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, >+ /* 15199 */ 'c', 'l', 't', 's', 0, >+ /* 15204 */ 'f', 'l', 'd', 'l', '2', 't', 0, >+ /* 15211 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, >+ /* 15219 */ 'm', 'w', 'a', 'i', 't', 0, >+ /* 15225 */ 'f', 'n', 'i', 'n', 'i', 't', 0, >+ /* 15232 */ 'h', 'l', 't', 0, >+ /* 15236 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, >+ /* 15244 */ 'f', 's', 'q', 'r', 't', 0, >+ /* 15250 */ 'x', 't', 'e', 's', 't', 0, >+ /* 15256 */ 'f', 't', 's', 't', 0, >+ /* 15261 */ 'e', 'n', 'c', 'l', 'u', 0, >+ /* 15267 */ 'x', 'g', 'e', 't', 'b', 'v', 0, >+ /* 15274 */ 'x', 's', 'e', 't', 'b', 'v', 0, >+ /* 15281 */ 'p', 'u', 's', 'h', 'a', 'w', 0, >+ /* 15288 */ 'p', 'o', 'p', 'a', 'w', 0, >+ /* 15294 */ 'p', 'u', 's', 'h', 'f', 'w', 0, >+ /* 15301 */ 'p', 'o', 'p', 'f', 'w', 0, >+ /* 15307 */ 'r', 'e', 'p', ';', 's', 't', 'o', 's', 'w', 0, >+ /* 15317 */ 'r', 'e', 'p', ';', 'm', 'o', 'v', 's', 'w', 0, >+ /* 15327 */ 'c', 'b', 't', 'w', 0, >+ /* 15332 */ 'i', 'r', 'e', 't', 'w', 0, >+ /* 15338 */ 'l', 'r', 'e', 't', 'w', 0, >+ /* 15344 */ 'f', 'y', 'l', '2', 'x', 0, >+ /* 15350 */ 'f', 'n', 's', 't', 's', 'w', 9, '%', 'a', 'x', 0, >+ /* 15361 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, >+ /* 15374 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, >+ /* 15386 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, >+ /* 15398 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, >+ /* 15409 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, >+ /* 15421 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'c', 'x', ',', 32, '%', 'e', 'a', 'x', 0, >+ /* 15440 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, >+ /* 15454 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, >+ /* 15466 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, >+ /* 15478 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, >+ /* 15489 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'c', 'x', ',', 32, '%', 'r', 'a', 'x', 0, >+ /* 15508 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, >+ /* 15522 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, >+ /* 15536 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, >+ /* 15551 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, >+ /* 15558 */ 'f', 'l', 'd', 'z', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ unsigned int opcode = MCInst_getOpcode(MI); >+ //printf("> opcode = %u\n", opcode); >+ uint64_t Bits1 = OpInfo[opcode]; >+ uint64_t Bits2 = OpInfo2[opcode]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+ if (!X86_lockrep(MI, O)) { >+#ifndef CAPSTONE_DIET >+ // HACK TODO >+ switch(opcode) { >+ default: >+ SStream_concat0(O, AsmStrs+(Bits & 16383)-1); >+ break; >+ case X86_MOV32sm: >+ SStream_concat0(O, "movw\t"); >+ break; >+ case X86_ROL32r1: >+ SStream_concat0(O, "rol\t$1, "); >+ break; >+ case X86_LGS64rm: >+ SStream_concat0(O, "lgs\t"); >+ break; >+ case X86_SLDT64m: >+ SStream_concat0(O, "sldt\t"); >+ break; >+ } >+#endif >+ } >+ >+ >+ // Fragment 0 encoded into 7 bits for 79 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 127); >+ switch ((Bits >> 14) & 127) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, AAA, AAS, ABS_F, ACQU... >+ return; >+ break; >+ case 1: >+ // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // ADC32rm, ADCX32rm, ADD32rm, AND32rm, ANDN32rm, CMOVA32rm, CMOVAE32rm, ... >+ printi32mem(MI, 2, O); >+ break; >+ case 6: >+ // ADC64rm, ADCX64rm, ADD64rm, AND64rm, ANDN64rm, CMOVA64rm, CMOVAE64rm, ... >+ printi64mem(MI, 2, O); >+ break; >+ case 7: >+ // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, SBB8rm, SUB8rm,... >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... >+ printf128mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 9: >+ // ADDSDrm, ADDSDrm_Int, DIVSDrm, DIVSDrm_Int, Int_CVTSD2SSrm, Int_VCVTSD... >+ printf64mem(MI, 2, O); >+ break; >+ case 10: >+ // ADDSSrm, ADDSSrm_Int, DIVSSrm, DIVSSrm_Int, Int_CVTSS2SDrm, Int_VCVTSS... >+ printf32mem(MI, 2, O); >+ break; >+ case 11: >+ // ADD_F32m, DIVR_F32m, DIV_F32m, FBLDm, FBSTPm, FCOM32m, FCOMP32m, FLDEN... >+ printf32mem(MI, 0, O); >+ return; >+ break; >+ case 12: >+ // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MUL_F64m, S... >+ printf64mem(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // ADD_FI16m, CALL16m, DEC16m, DEC64_16m, DIV16m, DIVR_FI16m, DIV_FI16m, ... >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // ADD_FI32m, CALL32m, DEC32m, DEC64_32m, DIV32m, DIVR_FI32m, DIV_FI32m, ... >+ printi32mem(MI, 0, O); >+ break; >+ case 15: >+ // ADOX32rm, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSF... >+ printi32mem(MI, 1, O); >+ break; >+ case 16: >+ // ADOX32rr, ADOX64rr, AESIMCrr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI... >+ printOperand(MI, 1, O); >+ break; >+ case 17: >+ // ADOX64rm, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSF... >+ printi64mem(MI, 1, O); >+ break; >+ case 18: >+ // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, PACKSSDWrm, PACKSSWBrm... >+ printi128mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // AESIMCrm, CVTDQ2PSrm, INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPI... >+ printi128mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 20: >+ // AESKEYGENASSIST128rm, BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZ... >+ printOperand(MI, 6, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... >+ printOperand(MI, 7, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 23: >+ // BSF16rm, BSR16rm, CMP16rm, KMOVWkm, LAR16rm, LAR32rm, LAR64rm, LEA16r,... >+ printi16mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 24: >+ // CALL64m, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, ILD_F64m, IMUL64m, INC64m... >+ printi64mem(MI, 0, O); >+ break; >+ case 25: >+ // CALL64pcrel32, CALLpcrel16, CALLpcrel32, EH_SjLj_Setup, JAE_1, JAE_2, ... >+ printPCRelImm(MI, 0, O); >+ break; >+ case 26: >+ // CLFLUSH, DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, INVLPG, LOCK_DEC8m, LOCK... >+ printi8mem(MI, 0, O); >+ return; >+ break; >+ case 27: >+ // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64... >+ printi8mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ break; >+ case 28: >+ // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSSrm, Int_CMPSDrm, Int_CMPSSrm >+ printSSECC(MI, 7, O); >+ break; >+ case 29: >+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr >+ printSSECC(MI, 3, O); >+ break; >+ case 30: >+ // CMPSB, INSB, SCASB, STOSB >+ printDstIdx8(MI, 0, O); >+ break; >+ case 31: >+ // CMPSL, INSL, SCASL, STOSL >+ printDstIdx32(MI, 0, O); >+ break; >+ case 32: >+ // CMPSQ, SCASQ, STOSQ >+ printDstIdx64(MI, 0, O); >+ break; >+ case 33: >+ // CMPSW, INSW, SCASW, STOSW >+ printDstIdx16(MI, 0, O); >+ break; >+ case 34: >+ // CMPXCHG16B, LCMPXCHG16B >+ printi128mem(MI, 0, O); >+ return; >+ break; >+ case 35: >+ // COMISDrm, COMISSrm, CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, C... >+ printf128mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 36: >+ // CVTPS2PDrm, CVTSD2SI64rm, CVTSD2SIrm, CVTSD2SSrm, CVTTSD2SI64rm, CVTTS... >+ printf64mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 37: >+ // CVTSS2SDrm, CVTSS2SI64rm, CVTSS2SIrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_... >+ printf32mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 38: >+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... >+ printopaquemem(MI, 0, O); >+ return; >+ break; >+ case 39: >+ // INSERTQI, VALIGNDrrikz, VALIGNQrrikz, VFMADD213PDZrk, VFMADD213PDZrkz,... >+ printOperand(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 40: >+ // Int_VCMPSDrm, Int_VCMPSSrm, VCMPPDYrmi, VCMPPDZrmi, VCMPPDrmi, VCMPPSY... >+ printAVXCC(MI, 7, O); >+ break; >+ case 41: >+ // Int_VCMPSDrr, Int_VCMPSSrr, VCMPPDYrri, VCMPPDZrri, VCMPPDZrrib, VCMPP... >+ printAVXCC(MI, 3, O); >+ break; >+ case 42: >+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... >+ printopaquemem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 43: >+ // LD_F80m, ST_FP80m >+ printf80mem(MI, 0, O); >+ return; >+ break; >+ case 44: >+ // LODSB, OUTSB >+ printSrcIdx8(MI, 0, O); >+ break; >+ case 45: >+ // LODSL, OUTSL >+ printSrcIdx32(MI, 0, O); >+ break; >+ case 46: >+ // LODSQ >+ printSrcIdx64(MI, 0, O); >+ SStream_concat0(O, ", %rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 47: >+ // LODSW, OUTSW >+ printSrcIdx16(MI, 0, O); >+ break; >+ case 48: >+ // MOV16ao16, MOV16ao16_16, MOV16o16a, MOV16o16a_16, MOV64ao16, MOV64o16a >+ printMemOffs16(MI, 0, O); >+ break; >+ case 49: >+ // MOV32ao32, MOV32ao32_16, MOV32o32a, MOV32o32a_16, MOV64ao32, MOV64o32a >+ printMemOffs32(MI, 0, O); >+ break; >+ case 50: >+ // MOV64ao64, MOV64o64a >+ printMemOffs64(MI, 0, O); >+ break; >+ case 51: >+ // MOV64ao8, MOV64o8a, MOV8ao8, MOV8ao8_16, MOV8o8a, MOV8o8a_16 >+ printMemOffs8(MI, 0, O); >+ break; >+ case 52: >+ // MOVSB >+ printSrcIdx8(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx8(MI, 0, O); >+ return; >+ break; >+ case 53: >+ // MOVSL >+ printSrcIdx32(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx32(MI, 0, O); >+ return; >+ break; >+ case 54: >+ // MOVSQ >+ printSrcIdx64(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx64(MI, 0, O); >+ return; >+ break; >+ case 55: >+ // MOVSW >+ printSrcIdx16(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx16(MI, 0, O); >+ return; >+ break; >+ case 56: >+ // VADDPDYrm, VADDPSYrm, VADDSUBPDYrm, VADDSUBPSYrm, VANDNPDYrm, VANDNPSY... >+ printf256mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 57: >+ // VADDPDZrm, VADDPSZrm, VDIVPDZrm, VDIVPSZrm, VMAXPDZrm, VMAXPSZrm, VMIN... >+ printf512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 58: >+ // VADDPDZrmbk, VADDPDZrmbkz, VDIVPDZrmbk, VDIVPDZrmbkz, VFMADD132PDZmb, ... >+ printf64mem(MI, 3, O); >+ break; >+ case 59: >+ // VADDPDZrmk, VADDPDZrmkz, VADDPSZrmk, VADDPSZrmkz, VBLENDMPDZrm, VBLEND... >+ printf512mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 60: >+ // VADDPSZrmbk, VADDPSZrmbkz, VDIVPSZrmbk, VDIVPSZrmbkz, VFMADD132PSZmb, ... >+ printf32mem(MI, 3, O); >+ break; >+ case 61: >+ // VBROADCASTI64X4krm, VMOVDQA32Z256rmkz, VMOVDQA64Z256rmkz, VMOVDQU16Z25... >+ printi256mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 62: >+ // VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VLDDQUYrm, VMOVDQA32Z25... >+ printi256mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 63: >+ // VCVTDQ2PSZrm, VMOVDQA32Zrm, VMOVDQA64Zrm, VMOVDQU16Zrm, VMOVDQU32Zrm, ... >+ printi512mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 64: >+ // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2UDQZrrb, VCVTPS2DQ... >+ printRoundingControl(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 65: >+ // VCVTPD2DQYrm, VCVTPD2PSYrm, VCVTPH2PSZrm, VCVTPS2DQYrm, VCVTPS2PDZrm, ... >+ printf256mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 66: >+ // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2UDQZrm, VCVTPS2DQZrm, VCVTPS2UDQZrm... >+ printf512mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 67: >+ // VFMADDPD4rm, VFMADDPDr132m, VFMADDPDr213m, VFMADDPDr231m, VFMADDPS4rm,... >+ printf128mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 68: >+ // VFMADDPD4rmY, VFMADDPDr132mY, VFMADDPDr213mY, VFMADDPDr231mY, VFMADDPS... >+ printf256mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 69: >+ // VGATHERDPDYrm, VGATHERDPDrm, VGATHERDPSYrm, VGATHERDPSrm, VGATHERQPDYr... >+ printOperand(MI, 8, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 70: >+ // VGATHERDPDZrm, VGATHERQPDZrm, VGATHERQPSZrm, VPADDQZrmbk, VPANDNQZrmbk... >+ printi64mem(MI, 4, O); >+ break; >+ case 71: >+ // VGATHERDPSZrm, VPADDDZrmbk, VPANDDZrmbk, VPANDNDZrmbk, VPGATHERDDZrm, ... >+ printi32mem(MI, 4, O); >+ break; >+ case 72: >+ // VMOVDQA32Z128rmk, VMOVDQA64Z128rmk, VMOVDQU16Z128rmk, VMOVDQU32Z128rmk... >+ printi128mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 73: >+ // VMOVDQA32Z256rmk, VMOVDQA64Z256rmk, VMOVDQU16Z256rmk, VMOVDQU32Z256rmk... >+ printi256mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 74: >+ // VMOVDQA32Zrmk, VMOVDQA64Zrmk, VMOVDQU16Zrmk, VMOVDQU32Zrmk, VMOVDQU64Z... >+ printi512mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 75: >+ // VMOVDQA32Zrmkz, VMOVDQA64Zrmkz, VMOVDQU16Zrmkz, VMOVDQU32Zrmkz, VMOVDQ... >+ printi512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 76: >+ // VPADDDZrmbkz, VPANDDZrmbkz, VPANDNDZrmbkz, VPCMPEQDZ128rmbk, VPCMPEQDZ... >+ printi32mem(MI, 3, O); >+ break; >+ case 77: >+ // VPADDDZrmk, VPADDQZrmk, VPANDDZrmk, VPANDNDZrmk, VPANDNQZrmk, VPANDQZr... >+ printi512mem(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 2, O); >+ break; >+ case 78: >+ // VPADDQZrmbkz, VPANDNQZrmbkz, VPANDQZrmbkz, VPCMPEQQZ128rmbk, VPCMPEQQZ... >+ printi64mem(MI, 3, O); >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 7 bits for 74 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 21) & 127); >+ switch ((Bits >> 21) & 127) { >+ default: // unreachable. >+ case 0: >+ // AAD8i8, AAM8i8, ADD_FI32m, ADD_FPrST0, ADD_FST0r, ADD_FrST0, BSWAP32r,... >+ return; >+ break; >+ case 1: >+ // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16o16a, MOV1... >+ SStream_concat0(O, ", %ax"); >+ op_addReg(MI, X86_REG_AX); >+ return; >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rr, ADC64... >+ printOperand(MI, 1, O); >+ break; >+ case 4: >+ // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rr, ADCX64rr,... >+ printOperand(MI, 0, O); >+ break; >+ case 5: >+ // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32o32a, MOV3... >+ SStream_concat0(O, ", %eax"); >+ op_addReg(MI, X86_REG_EAX); >+ return; >+ break; >+ case 6: >+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... >+ printi32mem(MI, 0, O); >+ return; >+ break; >+ case 7: >+ // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... >+ SStream_concat0(O, ", "); >+ break; >+ case 8: >+ // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64o64a, OR64i32, SBB64i32, ... >+ SStream_concat0(O, ", %rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 9: >+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... >+ printi64mem(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV64o8a, MOV8o8a, MOV8o... >+ SStream_concat0(O, ", %al"); >+ op_addReg(MI, X86_REG_AL); >+ return; >+ break; >+ case 11: >+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH... >+ printi8mem(MI, 0, O); >+ break; >+ case 12: >+ // AESKEYGENASSIST128rm, PCMPESTRIrm, PCMPESTRM128rm, PCMPISTRIrm, PCMPIS... >+ printi128mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, RORX32mi, SARX... >+ printi32mem(MI, 1, O); >+ break; >+ case 14: >+ // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, MMX_PSHUFWmi... >+ printi64mem(MI, 1, O); >+ break; >+ case 15: >+ // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, DPPDrmi, DPPSrmi, ... >+ printf128mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 16: >+ // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 17: >+ // CMOVBE_F, CMOVB_F, CMOVE_F, CMOVNBE_F, CMOVNB_F, CMOVNE_F, CMOVNP_F, C... >+ SStream_concat0(O, ", %st(0)"); >+ op_addReg(MI, X86_REG_ST0); >+ return; >+ break; >+ case 18: >+ // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDrmi, VCMPPDrri >+ SStream_concat0(O, "pd\t"); >+ break; >+ case 19: >+ // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSrmi, VCMPPSrri >+ SStream_concat0(O, "ps\t"); >+ break; >+ case 20: >+ // CMPSDrm, CMPSDrr, Int_CMPSDrm, Int_CMPSDrr, Int_VCMPSDrm, Int_VCMPSDrr... >+ SStream_concat0(O, "sd\t"); >+ break; >+ case 21: >+ // CMPSDrm_alt, ROUNDSDm, VCMPSDZrmi_alt, VCMPSDrm_alt, VFMADDSD4mr, VFMA... >+ printf64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // CMPSSrm, CMPSSrr, Int_CMPSSrm, Int_CMPSSrr, Int_VCMPSSrm, Int_VCMPSSrr... >+ SStream_concat0(O, "ss\t"); >+ break; >+ case 23: >+ // CMPSSrm_alt, INSERTPSrm, ROUNDSSm, VCMPSSZrmi_alt, VCMPSSrm_alt, VFMAD... >+ printf32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 24: >+ // EXTRACTPSmr, PEXTRBmr, PEXTRDmr, PEXTRQmr, PEXTRWmr, SHLD16mri8, SHLD3... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 25: >+ // FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i >+ SStream_concat0(O, ":"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 26: >+ // IMUL16rmi, IMUL16rmi8 >+ printi16mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 27: >+ // MMX_PALIGNR64irm, PINSRQrm, VPINSRQrm >+ printi64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 28: >+ // MMX_PINSRWirmi, PINSRWrmi, VPINSRWrmi >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 29: >+ // MOV8rm_NOREX >+ return; >+ break; >+ case 30: >+ // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... >+ printf128mem(MI, 0, O); >+ break; >+ case 31: >+ // MOVDQAmr, MOVDQUmr, VMOVDQA32Z128mr, VMOVDQA32Z128mrk, VMOVDQA64Z128mr... >+ printi128mem(MI, 0, O); >+ break; >+ case 32: >+ // MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVNTSD, MOVSDmr, VMOVHPDmr, V... >+ printf64mem(MI, 0, O); >+ return; >+ break; >+ case 33: >+ // MOVNTSS, MOVSSmr, VMOVSSZmr, VMOVSSmr >+ printf32mem(MI, 0, O); >+ return; >+ break; >+ case 34: >+ // MPSADBWrmi, PALIGNR128rm, PBLENDWrmi, PCLMULQDQrm, SHA1RNDS4rmi, VINSE... >+ printi128mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 35: >+ // OUTSB, OUTSL, OUTSW >+ SStream_concat0(O, ", %dx"); >+ op_addReg(MI, X86_REG_DX); >+ return; >+ break; >+ case 36: >+ // PINSRBrm, VPINSRBrm >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 37: >+ // PINSRDrm, VPINSRDrm >+ printi32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 38: >+ // ROUNDPDm, ROUNDPSm, VPERMILPDmi, VPERMILPSmi, VROUNDPDm, VROUNDPSm >+ printf128mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 39: >+ // TAILJMPd, TAILJMPd64, TAILJMPm, TAILJMPm64, TAILJMPr64 >+ return; >+ break; >+ case 40: >+ // VADDPDZrmb, VADDPDZrmbk, VADDPDZrmbkz, VDIVPDZrmb, VDIVPDZrmbk, VDIVPD... >+ SStream_concat0(O, "{1to8}, "); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ break; >+ case 41: >+ // VADDPSZrmb, VADDPSZrmbk, VADDPSZrmbkz, VDIVPSZrmb, VDIVPSZrmbk, VDIVPS... >+ SStream_concat0(O, "{1to16}, "); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ break; >+ case 42: >+ // VALIGNDrmi, VALIGNQrmi, VPCMPDZrmi_alt, VPCMPQZrmi_alt, VPCMPUDZrmi_al... >+ printi512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 43: >+ // VALIGNDrrik, VALIGNQrrik >+ printOperand(MI, 4, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 44: >+ // VBLENDPDYrmi, VBLENDPSYrmi, VBLENDVPDYrm, VBLENDVPSYrm, VCMPPDYrmi_alt... >+ printf256mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 45: >+ // VCMPPDZrmi, VCMPPDZrri >+ SStream_concat0(O, "pd \t"); >+ break; >+ case 46: >+ // VCMPPDZrmi_alt, VCMPPSZrmi_alt, VSHUFPDZrmi, VSHUFPSZrmi >+ printf512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 47: >+ // VCMPPDZrrib >+ SStream_concat0(O, "pd \t{sae}, "); >+ op_addAvxSae(MI); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 48: >+ // VCMPPSZrmi, VCMPPSZrri >+ SStream_concat0(O, "ps \t"); >+ break; >+ case 49: >+ // VCMPPSZrrib >+ SStream_concat0(O, "ps \t{sae}, "); >+ op_addAvxSae(MI); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 50: >+ // VDPPSYrmi, VINSERTF64x4rm, VINSERTI64x4rm, VMPSADBWYrmi, VPALIGNR256rm... >+ printi256mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 51: >+ // VGATHERDPDYrm, VGATHERDPDrm, VGATHERQPDYrm, VGATHERQPDrm, VPGATHERDQYr... >+ printi64mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 52: >+ // VGATHERDPSYrm, VGATHERDPSrm, VGATHERQPSYrm, VGATHERQPSrm, VPGATHERDDYr... >+ printi32mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 53: >+ // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... >+ SStream_concat0(O, " {"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 54: >+ // VMOVAPDYmr, VMOVAPDZ256mr, VMOVAPDZ256mrk, VMOVAPSYmr, VMOVAPSZ256mr, ... >+ printf256mem(MI, 0, O); >+ break; >+ case 55: >+ // VMOVAPDZmr, VMOVAPDZmrk, VMOVAPSZmr, VMOVAPSZmrk, VMOVNTPDZmr, VMOVNTP... >+ printf512mem(MI, 0, O); >+ break; >+ case 56: >+ // VMOVDQA32Z256mr, VMOVDQA32Z256mrk, VMOVDQA64Z256mr, VMOVDQA64Z256mrk, ... >+ printi256mem(MI, 0, O); >+ break; >+ case 57: >+ // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... >+ printi512mem(MI, 0, O); >+ break; >+ case 58: >+ // VPADDDZrmk, VPADDQZrmk, VPANDDZrmk, VPANDNDZrmk, VPANDNQZrmk, VPANDQZr... >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 59: >+ // VPCMPDZrmi, VPCMPDZrri >+ SStream_concat0(O, "d\t"); >+ break; >+ case 60: >+ // VPCMPDZrmik_alt, VPCMPQZrmik_alt, VPCMPUDZrmik_alt, VPCMPUQZrmik_alt >+ printi512mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 61: >+ // VPCMPEQDZ128rmb, VPCMPEQDZ128rmbk, VPCMPEQQZ256rmb, VPCMPEQQZ256rmbk, ... >+ SStream_concat0(O, "{1to4}, "); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_4); >+ break; >+ case 62: >+ // VPCMPEQQZ128rmb, VPCMPEQQZ128rmbk, VPCMPGTQZ128rmb, VPCMPGTQZ128rmbk >+ SStream_concat0(O, "{1to2}, "); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_2); >+ break; >+ case 63: >+ // VPCMPQZrmi, VPCMPQZrri >+ SStream_concat0(O, "q\t"); >+ break; >+ case 64: >+ // VPCMPUDZrmi, VPCMPUDZrri >+ SStream_concat0(O, "ud\t"); >+ break; >+ case 65: >+ // VPCMPUQZrmi, VPCMPUQZrri >+ SStream_concat0(O, "uq\t"); >+ break; >+ case 66: >+ // VPERMI2Drmkz, VPERMI2PDrmkz, VPERMI2PSrmkz, VPERMI2Qrmkz, VPERMT2Drmkz... >+ SStream_concat0(O, "} {z}"); >+ op_addAvxZeroOpmask(MI); >+ return; >+ break; >+ case 67: >+ // VPERMIL2PDmr, VPERMIL2PDmrY, VPERMIL2PSmr, VPERMIL2PSmrY >+ printOperand(MI, 7, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 68: >+ // VPERMIL2PDrm, VPERMIL2PSrm >+ printf128mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 69: >+ // VPERMIL2PDrmY, VPERMIL2PSrmY >+ printf256mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 70: >+ // VPERMILPDYmi, VPERMILPSYmi, VROUNDYPDm, VROUNDYPSm >+ printf256mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 71: >+ // VPERMILPDZmi, VPERMILPSZmi, VPERMQZmi, VPSHUFDZmi, VPSLLDZmi, VPSLLQZm... >+ printi512mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 72: >+ // VPERMPDYmi, VPERMQYmi, VPSHUFDYmi, VPSHUFHWYmi, VPSHUFLWYmi >+ printi256mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 73: >+ // VPERMPDZmi, VRNDSCALEPDZm, VRNDSCALEPSZm >+ printf512mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 6 bits for 33 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 28) & 63); >+ switch ((Bits >> 28) & 63) { >+ default: // unreachable. >+ case 0: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, A... >+ return; >+ break; >+ case 1: >+ // ADC32rm, ADC64rm, ADD32rm, ADD64rm, AND32rm, AND64rm, ANDN32rm, ANDN64... >+ printOperand(MI, 1, O); >+ break; >+ case 2: >+ // ADCX32rm, ADCX64rm, ADDSDrm, ADDSDrm_Int, ADDSSrm, ADDSSrm_Int, ADOX32... >+ printOperand(MI, 0, O); >+ break; >+ case 3: >+ // AESKEYGENASSIST128rr, ANDN32rr, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR6... >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 4: >+ // CMPPDrmi, CMPPSrmi, VCMPPDrmi, VCMPPSrmi, VPERMIL2PDmr, VPERMIL2PSmr >+ printf128mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr, Int_VC... >+ printOperand(MI, 2, O); >+ break; >+ case 6: >+ // CMPSB >+ printSrcIdx8(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // CMPSDrm, Int_CMPSDrm, Int_VCMPSDrm, VCMPSDZrm, VCMPSDrm >+ printf64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 8: >+ // CMPSL >+ printSrcIdx32(MI, 1, O); >+ return; >+ break; >+ case 9: >+ // CMPSQ >+ printSrcIdx64(MI, 1, O); >+ return; >+ break; >+ case 10: >+ // CMPSSrm, Int_CMPSSrm, Int_VCMPSSrm, VCMPSSZrm, VCMPSSrm >+ printf32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 11: >+ // CMPSW >+ printSrcIdx16(MI, 1, O); >+ return; >+ break; >+ case 12: >+ // EXTRACTPSmr, VEXTRACTPSmr, VEXTRACTPSzmr >+ printf32mem(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // LXADD16, XCHG16rm >+ printi16mem(MI, 2, O); >+ return; >+ break; >+ case 14: >+ // LXADD32, XCHG32rm >+ printi32mem(MI, 2, O); >+ return; >+ break; >+ case 15: >+ // LXADD64, XCHG64rm >+ printi64mem(MI, 2, O); >+ return; >+ break; >+ case 16: >+ // LXADD8, XCHG8rm >+ printi8mem(MI, 2, O); >+ return; >+ break; >+ case 17: >+ // MOV8mr_NOREX >+ return; >+ break; >+ case 18: >+ // PEXTRBmr, VPEXTRBmr >+ printi8mem(MI, 0, O); >+ return; >+ break; >+ case 19: >+ // PEXTRDmr, SHLD32mri8, SHRD32mri8, VPEXTRDmr >+ printi32mem(MI, 0, O); >+ return; >+ break; >+ case 20: >+ // PEXTRQmr, SHLD64mri8, SHRD64mri8, VPEXTRQmr >+ printi64mem(MI, 0, O); >+ return; >+ break; >+ case 21: >+ // PEXTRWmr, SHLD16mri8, SHRD16mri8, VPEXTRWmr >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 22: >+ // VAARG_64 >+ printi8mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 7, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 8, O); >+ return; >+ break; >+ case 23: >+ // VBROADCASTI32X4krm, VBROADCASTI64X4krm, VFMADD213PDZrk, VFMADD213PDZrk... >+ SStream_concat0(O, " {"); >+ break; >+ case 24: >+ // VCMPPDYrmi, VCMPPSYrmi, VPERMIL2PDmrY, VPERMIL2PSmrY >+ printf256mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 25: >+ // VCMPPDZrmi, VCMPPSZrmi >+ printf512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 26: >+ // VCVTPS2PHYmr, VEXTRACTF128mr, VEXTRACTF32x4mr, VMASKMOVPDmr, VMASKMOVP... >+ printf128mem(MI, 0, O); >+ return; >+ break; >+ case 27: >+ // VCVTPS2PHZmr, VEXTRACTF64x4mr, VMASKMOVPDYmr, VMASKMOVPSYmr >+ printf256mem(MI, 0, O); >+ return; >+ break; >+ case 28: >+ // VCVTPS2PHmr >+ printf64mem(MI, 0, O); >+ return; >+ break; >+ case 29: >+ // VEXTRACTI128mr, VEXTRACTI32x4mr, VPMASKMOVDmr, VPMASKMOVQmr >+ printi128mem(MI, 0, O); >+ return; >+ break; >+ case 30: >+ // VEXTRACTI64x4mr, VPMASKMOVDYmr, VPMASKMOVQYmr >+ printi256mem(MI, 0, O); >+ return; >+ break; >+ case 31: >+ // VPADDDZrmbk, VPADDQZrmbk, VPANDDZrmbk, VPANDNDZrmbk, VPANDNQZrmbk, VPA... >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 32: >+ // VPCMPDZrmi, VPCMPQZrmi, VPCMPUDZrmi, VPCMPUQZrmi >+ printi512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 4 bits for 10 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 34) & 15); >+ switch ((Bits >> 34) & 15) { >+ default: // unreachable. >+ case 0: >+ // ADC32rm, ADC64rm, ADCX32rm, ADCX64rm, ADD32rm, ADD64rm, ADDSDrm, ADDSD... >+ return; >+ break; >+ case 1: >+ // ANDN32rm, ANDN64rm, CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr,... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSSrm, Int_CMPSDrm, Int_CMPSSrm >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // Int_VCMPSDrm, Int_VCMPSSrm, VBROADCASTI32X4krm, VBROADCASTI64X4krm, VC... >+ printOperand(MI, 1, O); >+ break; >+ case 4: >+ // MOV8rr_NOREX >+ return; >+ break; >+ case 5: >+ // VADDPDZrmk, VADDPDZrmkz, VADDPDZrrk, VADDPDZrrkz, VADDPSZrmk, VADDPSZr... >+ SStream_concat0(O, " {"); >+ break; >+ case 6: >+ // VFMADD213PDZrk, VFMADD213PDZrkz, VFMADD213PSZrk, VFMADD213PSZrkz, VFMA... >+ printOperand(MI, 2, O); >+ break; >+ case 7: >+ // VMOVAPDZ128mrk, VMOVAPDZ256mrk, VMOVAPDZmrk, VMOVAPSZ128mrk, VMOVAPSZ2... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 8: >+ // VPCONFLICTDrr, VPCONFLICTQrr, VPLZCNTDrr, VPLZCNTQrr >+ return; >+ break; >+ case 9: >+ // VPSCATTERDDZmr, VPSCATTERDQZmr, VPSCATTERQDZmr, VPSCATTERQQZmr, VSCATT... >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 4 bits for 9 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 38) & 15); >+ switch ((Bits >> 38) & 15) { >+ default: // unreachable. >+ case 0: >+ // ANDN32rm, ANDN64rm, CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr,... >+ printOperand(MI, 0, O); >+ break; >+ case 1: >+ // Int_VCMPSDrm, Int_VCMPSSrm, VCMPPDrmi, VCMPPSrmi, VCMPSDZrm, VCMPSDrm,... >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 2: >+ // Int_VCMPSDrr, Int_VCMPSSrr, VADDPDZrmk, VADDPDZrmkz, VADDPDZrrk, VADDP... >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // VASTART_SAVE_XMM_REGS, VPCONFLICTDrmbk, VPCONFLICTQrmbk, VPLZCNTDrmbk,... >+ printOperand(MI, 2, O); >+ break; >+ case 4: >+ // VBROADCASTI32X4krm, VBROADCASTI64X4krm, VFMADD213PDZrkz, VFMADD213PSZr... >+ SStream_concat0(O, "} {z}"); >+ op_addAvxZeroOpmask(MI); >+ return; >+ break; >+ case 5: >+ // VFMADD213PDZrk, VFMADD213PSZrk, VFMADDSUB213PDZrk, VFMADDSUB213PSZrk, ... >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 6: >+ // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VGATHERQPSZrm, VPGATHERDD... >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 7: >+ // VPERMI2Drrkz, VPERMI2PDrrkz, VPERMI2PSrrkz, VPERMI2Qrrkz, VPERMT2Drrkz... >+ SStream_concat0(O, "} {z} "); >+ op_addAvxZeroOpmask(MI); >+ return; >+ break; >+ case 8: >+ // VPMOVSXBDZrmk, VPMOVSXBDZrrk, VPMOVSXBQZrmk, VPMOVSXBQZrrk, VPMOVSXDQZ... >+ SStream_concat0(O, "} "); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 3 bits for 6 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 42) & 7); >+ switch ((Bits >> 42) & 7) { >+ default: // unreachable. >+ case 0: >+ // ANDN32rm, ANDN64rm, CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr,... >+ return; >+ break; >+ case 1: >+ // Int_VCMPSDrr, Int_VCMPSSrr, VCMPPDYrri, VCMPPDZrri, VCMPPDrri, VCMPPSY... >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 2: >+ // VADDPDZrmbk, VADDPDZrmbkz, VADDPSZrmbk, VADDPSZrmbkz, VDIVPDZrmbk, VDI... >+ SStream_concat0(O, " {"); >+ printOperand(MI, 1, O); >+ break; >+ case 3: >+ // VADDPDZrmk, VADDPSZrmk, VBLENDMPDZrm, VBLENDMPDZrr, VBLENDMPSZrm, VBLE... >+ SStream_concat0(O, "}"); >+ return; >+ break; >+ case 4: >+ // VADDPDZrmkz, VADDPDZrrkz, VADDPSZrmkz, VADDPSZrrkz, VALIGNDrrikz, VALI... >+ SStream_concat0(O, "} {z}"); >+ op_addAvxZeroOpmask(MI); >+ return; >+ break; >+ case 5: >+ // VADDPDZrrk, VADDPSZrrk, VDIVPDZrrk, VDIVPSZrrk, VMAXPDZrrk, VMAXPSZrrk... >+ SStream_concat0(O, "} "); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 1); >+ if ((Bits >> 45) & 1) { >+ // VADDPDZrmbkz, VADDPSZrmbkz, VDIVPDZrmbkz, VDIVPSZrmbkz, VMAXPDZrmbkz, ... >+ SStream_concat0(O, "} {z}"); >+ op_addAvxZeroOpmask(MI); >+ return; >+ } else { >+ // VADDPDZrmbk, VADDPSZrmbk, VDIVPDZrmbk, VDIVPSZrmbk, VMAXPDZrmbk, VMAXP... >+ SStream_concat0(O, "}"); >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 234 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 't', '(', '0', ')', 0, >+ /* 6 */ 's', 't', '(', '1', ')', 0, >+ /* 12 */ 's', 't', '(', '2', ')', 0, >+ /* 18 */ 's', 't', '(', '3', ')', 0, >+ /* 24 */ 's', 't', '(', '4', ')', 0, >+ /* 30 */ 's', 't', '(', '5', ')', 0, >+ /* 36 */ 's', 't', '(', '6', ')', 0, >+ /* 42 */ 's', 't', '(', '7', ')', 0, >+ /* 48 */ 'x', 'm', 'm', '1', '0', 0, >+ /* 54 */ 'y', 'm', 'm', '1', '0', 0, >+ /* 60 */ 'z', 'm', 'm', '1', '0', 0, >+ /* 66 */ 'c', 'r', '1', '0', 0, >+ /* 71 */ 'x', 'm', 'm', '2', '0', 0, >+ /* 77 */ 'y', 'm', 'm', '2', '0', 0, >+ /* 83 */ 'z', 'm', 'm', '2', '0', 0, >+ /* 89 */ 'x', 'm', 'm', '3', '0', 0, >+ /* 95 */ 'y', 'm', 'm', '3', '0', 0, >+ /* 101 */ 'z', 'm', 'm', '3', '0', 0, >+ /* 107 */ 'k', '0', 0, >+ /* 110 */ 'x', 'm', 'm', '0', 0, >+ /* 115 */ 'y', 'm', 'm', '0', 0, >+ /* 120 */ 'z', 'm', 'm', '0', 0, >+ /* 125 */ 'f', 'p', '0', 0, >+ /* 129 */ 'c', 'r', '0', 0, >+ /* 133 */ 'd', 'r', '0', 0, >+ /* 137 */ 'x', 'm', 'm', '1', '1', 0, >+ /* 143 */ 'y', 'm', 'm', '1', '1', 0, >+ /* 149 */ 'z', 'm', 'm', '1', '1', 0, >+ /* 155 */ 'c', 'r', '1', '1', 0, >+ /* 160 */ 'x', 'm', 'm', '2', '1', 0, >+ /* 166 */ 'y', 'm', 'm', '2', '1', 0, >+ /* 172 */ 'z', 'm', 'm', '2', '1', 0, >+ /* 178 */ 'x', 'm', 'm', '3', '1', 0, >+ /* 184 */ 'y', 'm', 'm', '3', '1', 0, >+ /* 190 */ 'z', 'm', 'm', '3', '1', 0, >+ /* 196 */ 'k', '1', 0, >+ /* 199 */ 'x', 'm', 'm', '1', 0, >+ /* 204 */ 'y', 'm', 'm', '1', 0, >+ /* 209 */ 'z', 'm', 'm', '1', 0, >+ /* 214 */ 'f', 'p', '1', 0, >+ /* 218 */ 'c', 'r', '1', 0, >+ /* 222 */ 'd', 'r', '1', 0, >+ /* 226 */ 'x', 'm', 'm', '1', '2', 0, >+ /* 232 */ 'y', 'm', 'm', '1', '2', 0, >+ /* 238 */ 'z', 'm', 'm', '1', '2', 0, >+ /* 244 */ 'c', 'r', '1', '2', 0, >+ /* 249 */ 'x', 'm', 'm', '2', '2', 0, >+ /* 255 */ 'y', 'm', 'm', '2', '2', 0, >+ /* 261 */ 'z', 'm', 'm', '2', '2', 0, >+ /* 267 */ 'k', '2', 0, >+ /* 270 */ 'x', 'm', 'm', '2', 0, >+ /* 275 */ 'y', 'm', 'm', '2', 0, >+ /* 280 */ 'z', 'm', 'm', '2', 0, >+ /* 285 */ 'f', 'p', '2', 0, >+ /* 289 */ 'c', 'r', '2', 0, >+ /* 293 */ 'd', 'r', '2', 0, >+ /* 297 */ 'x', 'm', 'm', '1', '3', 0, >+ /* 303 */ 'y', 'm', 'm', '1', '3', 0, >+ /* 309 */ 'z', 'm', 'm', '1', '3', 0, >+ /* 315 */ 'c', 'r', '1', '3', 0, >+ /* 320 */ 'x', 'm', 'm', '2', '3', 0, >+ /* 326 */ 'y', 'm', 'm', '2', '3', 0, >+ /* 332 */ 'z', 'm', 'm', '2', '3', 0, >+ /* 338 */ 'k', '3', 0, >+ /* 341 */ 'x', 'm', 'm', '3', 0, >+ /* 346 */ 'y', 'm', 'm', '3', 0, >+ /* 351 */ 'z', 'm', 'm', '3', 0, >+ /* 356 */ 'f', 'p', '3', 0, >+ /* 360 */ 'c', 'r', '3', 0, >+ /* 364 */ 'd', 'r', '3', 0, >+ /* 368 */ 'x', 'm', 'm', '1', '4', 0, >+ /* 374 */ 'y', 'm', 'm', '1', '4', 0, >+ /* 380 */ 'z', 'm', 'm', '1', '4', 0, >+ /* 386 */ 'c', 'r', '1', '4', 0, >+ /* 391 */ 'x', 'm', 'm', '2', '4', 0, >+ /* 397 */ 'y', 'm', 'm', '2', '4', 0, >+ /* 403 */ 'z', 'm', 'm', '2', '4', 0, >+ /* 409 */ 'k', '4', 0, >+ /* 412 */ 'x', 'm', 'm', '4', 0, >+ /* 417 */ 'y', 'm', 'm', '4', 0, >+ /* 422 */ 'z', 'm', 'm', '4', 0, >+ /* 427 */ 'f', 'p', '4', 0, >+ /* 431 */ 'c', 'r', '4', 0, >+ /* 435 */ 'd', 'r', '4', 0, >+ /* 439 */ 'x', 'm', 'm', '1', '5', 0, >+ /* 445 */ 'y', 'm', 'm', '1', '5', 0, >+ /* 451 */ 'z', 'm', 'm', '1', '5', 0, >+ /* 457 */ 'c', 'r', '1', '5', 0, >+ /* 462 */ 'x', 'm', 'm', '2', '5', 0, >+ /* 468 */ 'y', 'm', 'm', '2', '5', 0, >+ /* 474 */ 'z', 'm', 'm', '2', '5', 0, >+ /* 480 */ 'k', '5', 0, >+ /* 483 */ 'x', 'm', 'm', '5', 0, >+ /* 488 */ 'y', 'm', 'm', '5', 0, >+ /* 493 */ 'z', 'm', 'm', '5', 0, >+ /* 498 */ 'f', 'p', '5', 0, >+ /* 502 */ 'c', 'r', '5', 0, >+ /* 506 */ 'd', 'r', '5', 0, >+ /* 510 */ 'x', 'm', 'm', '1', '6', 0, >+ /* 516 */ 'y', 'm', 'm', '1', '6', 0, >+ /* 522 */ 'z', 'm', 'm', '1', '6', 0, >+ /* 528 */ 'x', 'm', 'm', '2', '6', 0, >+ /* 534 */ 'y', 'm', 'm', '2', '6', 0, >+ /* 540 */ 'z', 'm', 'm', '2', '6', 0, >+ /* 546 */ 'k', '6', 0, >+ /* 549 */ 'x', 'm', 'm', '6', 0, >+ /* 554 */ 'y', 'm', 'm', '6', 0, >+ /* 559 */ 'z', 'm', 'm', '6', 0, >+ /* 564 */ 'f', 'p', '6', 0, >+ /* 568 */ 'c', 'r', '6', 0, >+ /* 572 */ 'd', 'r', '6', 0, >+ /* 576 */ 'x', 'm', 'm', '1', '7', 0, >+ /* 582 */ 'y', 'm', 'm', '1', '7', 0, >+ /* 588 */ 'z', 'm', 'm', '1', '7', 0, >+ /* 594 */ 'x', 'm', 'm', '2', '7', 0, >+ /* 600 */ 'y', 'm', 'm', '2', '7', 0, >+ /* 606 */ 'z', 'm', 'm', '2', '7', 0, >+ /* 612 */ 'k', '7', 0, >+ /* 615 */ 'x', 'm', 'm', '7', 0, >+ /* 620 */ 'y', 'm', 'm', '7', 0, >+ /* 625 */ 'z', 'm', 'm', '7', 0, >+ /* 630 */ 'f', 'p', '7', 0, >+ /* 634 */ 'c', 'r', '7', 0, >+ /* 638 */ 'd', 'r', '7', 0, >+ /* 642 */ 'x', 'm', 'm', '1', '8', 0, >+ /* 648 */ 'y', 'm', 'm', '1', '8', 0, >+ /* 654 */ 'z', 'm', 'm', '1', '8', 0, >+ /* 660 */ 'x', 'm', 'm', '2', '8', 0, >+ /* 666 */ 'y', 'm', 'm', '2', '8', 0, >+ /* 672 */ 'z', 'm', 'm', '2', '8', 0, >+ /* 678 */ 'x', 'm', 'm', '8', 0, >+ /* 683 */ 'y', 'm', 'm', '8', 0, >+ /* 688 */ 'z', 'm', 'm', '8', 0, >+ /* 693 */ 'c', 'r', '8', 0, >+ /* 697 */ 'x', 'm', 'm', '1', '9', 0, >+ /* 703 */ 'y', 'm', 'm', '1', '9', 0, >+ /* 709 */ 'z', 'm', 'm', '1', '9', 0, >+ /* 715 */ 'x', 'm', 'm', '2', '9', 0, >+ /* 721 */ 'y', 'm', 'm', '2', '9', 0, >+ /* 727 */ 'z', 'm', 'm', '2', '9', 0, >+ /* 733 */ 'x', 'm', 'm', '9', 0, >+ /* 738 */ 'y', 'm', 'm', '9', 0, >+ /* 743 */ 'z', 'm', 'm', '9', 0, >+ /* 748 */ 'c', 'r', '9', 0, >+ /* 752 */ 'r', '1', '0', 'b', 0, >+ /* 757 */ 'r', '1', '1', 'b', 0, >+ /* 762 */ 'r', '1', '2', 'b', 0, >+ /* 767 */ 'r', '1', '3', 'b', 0, >+ /* 772 */ 'r', '1', '4', 'b', 0, >+ /* 777 */ 'r', '1', '5', 'b', 0, >+ /* 782 */ 'r', '8', 'b', 0, >+ /* 786 */ 'r', '9', 'b', 0, >+ /* 790 */ 'r', '1', '0', 'd', 0, >+ /* 795 */ 'r', '1', '1', 'd', 0, >+ /* 800 */ 'r', '1', '2', 'd', 0, >+ /* 805 */ 'r', '1', '3', 'd', 0, >+ /* 810 */ 'r', '1', '4', 'd', 0, >+ /* 815 */ 'r', '1', '5', 'd', 0, >+ /* 820 */ 'r', '8', 'd', 0, >+ /* 824 */ 'r', '9', 'd', 0, >+ /* 828 */ 'a', 'h', 0, >+ /* 831 */ 'b', 'h', 0, >+ /* 834 */ 'c', 'h', 0, >+ /* 837 */ 'd', 'h', 0, >+ /* 840 */ 'e', 'd', 'i', 0, >+ /* 844 */ 'r', 'd', 'i', 0, >+ /* 848 */ 'e', 's', 'i', 0, >+ /* 852 */ 'r', 's', 'i', 0, >+ /* 856 */ 'a', 'l', 0, >+ /* 859 */ 'b', 'l', 0, >+ /* 862 */ 'c', 'l', 0, >+ /* 865 */ 'd', 'l', 0, >+ /* 868 */ 'd', 'i', 'l', 0, >+ /* 872 */ 's', 'i', 'l', 0, >+ /* 876 */ 'b', 'p', 'l', 0, >+ /* 880 */ 's', 'p', 'l', 0, >+ /* 884 */ 'e', 'b', 'p', 0, >+ /* 888 */ 'r', 'b', 'p', 0, >+ /* 892 */ 'e', 'i', 'p', 0, >+ /* 896 */ 'r', 'i', 'p', 0, >+ /* 900 */ 'e', 's', 'p', 0, >+ /* 904 */ 'r', 's', 'p', 0, >+ /* 908 */ 'c', 's', 0, >+ /* 911 */ 'd', 's', 0, >+ /* 914 */ 'e', 's', 0, >+ /* 917 */ 'f', 's', 0, >+ /* 920 */ 'f', 'l', 'a', 'g', 's', 0, >+ /* 926 */ 's', 's', 0, >+ /* 929 */ 'r', '1', '0', 'w', 0, >+ /* 934 */ 'r', '1', '1', 'w', 0, >+ /* 939 */ 'r', '1', '2', 'w', 0, >+ /* 944 */ 'r', '1', '3', 'w', 0, >+ /* 949 */ 'r', '1', '4', 'w', 0, >+ /* 954 */ 'r', '1', '5', 'w', 0, >+ /* 959 */ 'r', '8', 'w', 0, >+ /* 963 */ 'r', '9', 'w', 0, >+ /* 967 */ 'f', 'p', 's', 'w', 0, >+ /* 972 */ 'e', 'a', 'x', 0, >+ /* 976 */ 'r', 'a', 'x', 0, >+ /* 980 */ 'e', 'b', 'x', 0, >+ /* 984 */ 'r', 'b', 'x', 0, >+ /* 988 */ 'e', 'c', 'x', 0, >+ /* 992 */ 'r', 'c', 'x', 0, >+ /* 996 */ 'e', 'd', 'x', 0, >+ /* 1000 */ 'r', 'd', 'x', 0, >+ /* 1004 */ 'e', 'i', 'z', 0, >+ /* 1008 */ 'r', 'i', 'z', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 828, 856, 973, 831, 859, 885, 876, 981, 834, 862, 908, 989, 837, 841, >+ 868, 865, 911, 997, 972, 884, 980, 988, 840, 996, 920, 892, 1004, 914, >+ 848, 900, 967, 917, 923, 893, 976, 888, 984, 992, 844, 1000, 896, 1008, >+ 852, 904, 849, 872, 901, 880, 926, 129, 218, 289, 360, 431, 502, 568, >+ 634, 693, 748, 66, 155, 244, 315, 386, 457, 133, 222, 293, 364, 435, >+ 506, 572, 638, 125, 214, 285, 356, 427, 498, 564, 630, 107, 196, 267, >+ 338, 409, 480, 546, 612, 111, 200, 271, 342, 413, 484, 550, 616, 694, >+ 749, 67, 156, 245, 316, 387, 458, 0, 6, 12, 18, 24, 30, 36, >+ 42, 110, 199, 270, 341, 412, 483, 549, 615, 678, 733, 48, 137, 226, >+ 297, 368, 439, 510, 576, 642, 697, 71, 160, 249, 320, 391, 462, 528, >+ 594, 660, 715, 89, 178, 115, 204, 275, 346, 417, 488, 554, 620, 683, >+ 738, 54, 143, 232, 303, 374, 445, 516, 582, 648, 703, 77, 166, 255, >+ 326, 397, 468, 534, 600, 666, 721, 95, 184, 120, 209, 280, 351, 422, >+ 493, 559, 625, 688, 743, 60, 149, 238, 309, 380, 451, 522, 588, 654, >+ 709, 83, 172, 261, 332, 403, 474, 540, 606, 672, 727, 101, 190, 782, >+ 786, 752, 757, 762, 767, 772, 777, 820, 824, 790, 795, 800, 805, 810, >+ 815, 959, 963, 929, 934, 939, 944, 949, 954, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+ switch (PrintMethodIdx) { >+ default: >+ // llvm_unreachable("Unknown PrintMethod kind"); >+ break; >+ case 0: >+ printf64mem(MI, OpIdx, OS); >+ break; >+ } >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case X86_AAD8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAD8i8 10) >+ AsmString = "aad"; >+ break; >+ } >+ return NULL; >+ case X86_AAM8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAM8i8 10) >+ AsmString = "aam"; >+ break; >+ } >+ return NULL; >+ case X86_CVTSD2SI64rm: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(X86_GR64RegClassID, 0)) { >+ // (CVTSD2SI64rm GR64:$dst, sdmem:$src) >+ AsmString = "cvtsd2siq $\xFF\x02\x01, $\x01"; >+ break; >+ } >+ return NULL; >+ case X86_XSTORE: >+ if (MCInst_getNumOperands(MI) == 0) { >+ // (XSTORE) >+ AsmString = "xstorerng"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1.inc b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..06eeadc8f8b9a8e280638dc19de3b92d2a4b953c >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1.inc >@@ -0,0 +1,15126 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 11119U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 11112U, // BUNDLE >+ 11184U, // LIFETIME_START >+ 11099U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 11199U, // AAA >+ 20256U, // AAD8i8 >+ 22647U, // AAM8i8 >+ 11911U, // AAS >+ 11919U, // ABS_F >+ 0U, // ABS_Fp32 >+ 0U, // ABS_Fp64 >+ 0U, // ABS_Fp80 >+ 10814U, // ACQUIRE_MOV16rm >+ 10814U, // ACQUIRE_MOV32rm >+ 10814U, // ACQUIRE_MOV64rm >+ 10814U, // ACQUIRE_MOV8rm >+ 26287U, // ADC16i16 >+ 1085152U, // ADC16mi >+ 1085152U, // ADC16mi8 >+ 1085152U, // ADC16mr >+ 34655968U, // ADC16ri >+ 34655968U, // ADC16ri8 >+ 68210400U, // ADC16rm >+ 34655968U, // ADC16rr >+ 34623200U, // ADC16rr_REV >+ 26423U, // ADC32i32 >+ 1117920U, // ADC32mi >+ 1117920U, // ADC32mi8 >+ 1117920U, // ADC32mr >+ 34655968U, // ADC32ri >+ 34655968U, // ADC32ri8 >+ 101764832U, // ADC32rm >+ 34655968U, // ADC32rr >+ 34623200U, // ADC32rr_REV >+ 26571U, // ADC64i32 >+ 1134304U, // ADC64mi32 >+ 1134304U, // ADC64mi8 >+ 1134304U, // ADC64mr >+ 34655968U, // ADC64ri32 >+ 34655968U, // ADC64ri8 >+ 135319264U, // ADC64rm >+ 34655968U, // ADC64rr >+ 34623200U, // ADC64rr_REV >+ 26185U, // ADC8i8 >+ 1150688U, // ADC8mi >+ 1150688U, // ADC8mr >+ 34655968U, // ADC8ri >+ 168873696U, // ADC8rm >+ 34655968U, // ADC8rr >+ 34623200U, // ADC8rr_REV >+ 101737738U, // ADCX32rm >+ 34628874U, // ADCX32rr >+ 135292170U, // ADCX64rm >+ 34628874U, // ADCX64rr >+ 26296U, // ADD16i16 >+ 1085307U, // ADD16mi >+ 1085307U, // ADD16mi8 >+ 1085307U, // ADD16mr >+ 34656123U, // ADD16ri >+ 34656123U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 68210555U, // ADD16rm >+ 34656123U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 34623355U, // ADD16rr_REV >+ 26433U, // ADD32i32 >+ 1118075U, // ADD32mi >+ 1118075U, // ADD32mi8 >+ 1118075U, // ADD32mr >+ 34656123U, // ADD32ri >+ 34656123U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 101764987U, // ADD32rm >+ 34656123U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 34623355U, // ADD32rr_REV >+ 26581U, // ADD64i32 >+ 1134459U, // ADD64mi32 >+ 1134459U, // ADD64mi8 >+ 1134459U, // ADD64mr >+ 34656123U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 34656123U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 135319419U, // ADD64rm >+ 34656123U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 34623355U, // ADD64rr_REV >+ 26194U, // ADD8i8 >+ 1150843U, // ADD8mi >+ 1150843U, // ADD8mr >+ 34656123U, // ADD8ri >+ 34656123U, // ADD8ri8 >+ 168873851U, // ADD8rm >+ 34656123U, // ADD8rr >+ 34623355U, // ADD8rr_REV >+ 202396135U, // ADDPDrm >+ 34623975U, // ADDPDrr >+ 202399362U, // ADDPSrm >+ 34627202U, // ADDPSrr >+ 235951174U, // ADDSDrm >+ 235951174U, // ADDSDrm_Int >+ 34624582U, // ADDSDrr >+ 34624582U, // ADDSDrr_Int >+ 269508832U, // ADDSSrm >+ 269508832U, // ADDSSrm_Int >+ 34627808U, // ADDSSrr >+ 34627808U, // ADDSSrr_Int >+ 202396070U, // ADDSUBPDrm >+ 34623910U, // ADDSUBPDrr >+ 202399297U, // ADDSUBPSrm >+ 34627137U, // ADDSUBPSrr >+ 118650U, // ADD_F32m >+ 135034U, // ADD_F64m >+ 36736U, // ADD_FI16m >+ 69504U, // ADD_FI32m >+ 22792U, // ADD_FPrST0 >+ 20346U, // ADD_FST0r >+ 0U, // ADD_Fp32 >+ 0U, // ADD_Fp32m >+ 0U, // ADD_Fp64 >+ 0U, // ADD_Fp64m >+ 0U, // ADD_Fp64m32 >+ 0U, // ADD_Fp80 >+ 0U, // ADD_Fp80m32 >+ 0U, // ADD_Fp80m64 >+ 0U, // ADD_FpI16m32 >+ 0U, // ADD_FpI16m64 >+ 0U, // ADD_FpI16m80 >+ 0U, // ADD_FpI32m32 >+ 0U, // ADD_FpI32m64 >+ 0U, // ADD_FpI32m80 >+ 2117498U, // ADD_FrST0 >+ 11138U, // ADJCALLSTACKDOWN32 >+ 11138U, // ADJCALLSTACKDOWN64 >+ 11156U, // ADJCALLSTACKUP32 >+ 11156U, // ADJCALLSTACKUP64 >+ 303064348U, // ADOX32rm >+ 336618780U, // ADOX32rr >+ 370173212U, // ADOX64rm >+ 336618780U, // ADOX64rr >+ 403726862U, // AESDECLASTrm >+ 34628110U, // AESDECLASTrr >+ 403721958U, // AESDECrm >+ 34623206U, // AESDECrr >+ 403726875U, // AESENCLASTrm >+ 34628123U, // AESENCLASTrr >+ 403721998U, // AESENCrm >+ 34623246U, // AESENCrr >+ 437276421U, // AESIMCrm >+ 336613125U, // AESIMCrr >+ 2584764987U, // AESKEYGENASSIST128rm >+ 2484101691U, // AESKEYGENASSIST128rr >+ 26305U, // AND16i16 >+ 1085511U, // AND16mi >+ 1085511U, // AND16mi8 >+ 1085511U, // AND16mr >+ 34656327U, // AND16ri >+ 34656327U, // AND16ri8 >+ 68210759U, // AND16rm >+ 34656327U, // AND16rr >+ 34623559U, // AND16rr_REV >+ 26443U, // AND32i32 >+ 1118279U, // AND32mi >+ 1118279U, // AND32mi8 >+ 1118279U, // AND32mr >+ 34656327U, // AND32ri >+ 34656327U, // AND32ri8 >+ 101765191U, // AND32rm >+ 34656327U, // AND32rr >+ 34623559U, // AND32rr_REV >+ 26591U, // AND64i32 >+ 1134663U, // AND64mi32 >+ 1134663U, // AND64mi8 >+ 1134663U, // AND64mr >+ 34656327U, // AND64ri32 >+ 34656327U, // AND64ri8 >+ 135319623U, // AND64rm >+ 34656327U, // AND64rr >+ 34623559U, // AND64rr_REV >+ 26203U, // AND8i8 >+ 1151047U, // AND8mi >+ 1151047U, // AND8mr >+ 34656327U, // AND8ri >+ 34656327U, // AND8ri8 >+ 168874055U, // AND8rm >+ 34656327U, // AND8rr >+ 34623559U, // AND8rr_REV >+ 2484099250U, // ANDN32rm >+ 2484099250U, // ANDN32rr >+ 2484099250U, // ANDN64rm >+ 2484099250U, // ANDN64rr >+ 202396317U, // ANDNPDrm >+ 34624157U, // ANDNPDrr >+ 202399556U, // ANDNPSrm >+ 34627396U, // ANDNPSrr >+ 202396181U, // ANDPDrm >+ 34624021U, // ANDPDrr >+ 202399408U, // ANDPSrm >+ 34627248U, // ANDPSrr >+ 1087546U, // ARPL16mr >+ 336615482U, // ARPL16rr >+ 0U, // AVX2_SETALLONES >+ 0U, // AVX512_512_SET0 >+ 0U, // AVX_SET0 >+ 2450545836U, // BEXTR32rm >+ 2484100268U, // BEXTR32rr >+ 2517654700U, // BEXTR64rm >+ 2484100268U, // BEXTR64rr >+ 2450545836U, // BEXTRI32mi >+ 2484100268U, // BEXTRI32ri >+ 2517654700U, // BEXTRI64mi >+ 2484100268U, // BEXTRI64ri >+ 303061027U, // BLCFILL32rm >+ 336615459U, // BLCFILL32rr >+ 370169891U, // BLCFILL64rm >+ 336615459U, // BLCFILL64rr >+ 303060808U, // BLCI32rm >+ 336615240U, // BLCI32rr >+ 370169672U, // BLCI64rm >+ 336615240U, // BLCI64rr >+ 303058670U, // BLCIC32rm >+ 336613102U, // BLCIC32rr >+ 370167534U, // BLCIC64rm >+ 336613102U, // BLCIC64rr >+ 303060978U, // BLCMSK32rm >+ 336615410U, // BLCMSK32rr >+ 370169842U, // BLCMSK64rm >+ 336615410U, // BLCMSK64rr >+ 303062218U, // BLCS32rm >+ 336616650U, // BLCS32rr >+ 370171082U, // BLCS64rm >+ 336616650U, // BLCS64rr >+ 2349879837U, // BLENDPDrmi >+ 2182107677U, // BLENDPDrri >+ 2349883064U, // BLENDPSrmi >+ 2182110904U, // BLENDPSrri >+ 202396413U, // BLENDVPDrm0 >+ 34624253U, // BLENDVPDrr0 >+ 202399693U, // BLENDVPSrm0 >+ 34627533U, // BLENDVPSrr0 >+ 303061036U, // BLSFILL32rm >+ 336615468U, // BLSFILL32rr >+ 370169900U, // BLSFILL64rm >+ 336615468U, // BLSFILL64rr >+ 303060964U, // BLSI32rm >+ 336615396U, // BLSI32rr >+ 370169828U, // BLSI64rm >+ 336615396U, // BLSI64rr >+ 303058677U, // BLSIC32rm >+ 336613109U, // BLSIC32rr >+ 370167541U, // BLSIC64rm >+ 336613109U, // BLSIC64rr >+ 303060986U, // BLSMSK32rm >+ 336615418U, // BLSMSK32rr >+ 370169850U, // BLSMSK64rm >+ 336615418U, // BLSMSK64rr >+ 303062167U, // BLSR32rm >+ 336616599U, // BLSR32rr >+ 370171031U, // BLSR64rm >+ 336616599U, // BLSR64rr >+ 303059037U, // BOUNDS16rm >+ 370167901U, // BOUNDS32rm >+ 470832853U, // BSF16rm >+ 336615125U, // BSF16rr >+ 303060693U, // BSF32rm >+ 336615125U, // BSF32rr >+ 370169557U, // BSF64rm >+ 336615125U, // BSF64rr >+ 470834302U, // BSR16rm >+ 336616574U, // BSR16rr >+ 303062142U, // BSR32rm >+ 336616574U, // BSR32rr >+ 370171006U, // BSR64rm >+ 336616574U, // BSR64rr >+ 22771U, // BSWAP32r >+ 22771U, // BSWAP64r >+ 1089940U, // BT16mi8 >+ 1089940U, // BT16mr >+ 336617876U, // BT16ri8 >+ 336617876U, // BT16rr >+ 1122708U, // BT32mi8 >+ 1122708U, // BT32mr >+ 336617876U, // BT32ri8 >+ 336617876U, // BT32rr >+ 1139092U, // BT64mi8 >+ 1139092U, // BT64mr >+ 336617876U, // BT64ri8 >+ 336617876U, // BT64rr >+ 1085211U, // BTC16mi8 >+ 1085211U, // BTC16mr >+ 336613147U, // BTC16ri8 >+ 336613147U, // BTC16rr >+ 1117979U, // BTC32mi8 >+ 1117979U, // BTC32mr >+ 336613147U, // BTC32ri8 >+ 336613147U, // BTC32rr >+ 1134363U, // BTC64mi8 >+ 1134363U, // BTC64mr >+ 336613147U, // BTC64ri8 >+ 336613147U, // BTC64rr >+ 1088669U, // BTR16mi8 >+ 1088669U, // BTR16mr >+ 336616605U, // BTR16ri8 >+ 336616605U, // BTR16rr >+ 1121437U, // BTR32mi8 >+ 1121437U, // BTR32mr >+ 336616605U, // BTR32ri8 >+ 336616605U, // BTR32rr >+ 1137821U, // BTR64mi8 >+ 1137821U, // BTR64mr >+ 336616605U, // BTR64ri8 >+ 336616605U, // BTR64rr >+ 1089922U, // BTS16mi8 >+ 1089922U, // BTS16mr >+ 336617858U, // BTS16ri8 >+ 336617858U, // BTS16rr >+ 1122690U, // BTS32mi8 >+ 1122690U, // BTS32mr >+ 336617858U, // BTS32ri8 >+ 336617858U, // BTS32rr >+ 1139074U, // BTS64mi8 >+ 1139074U, // BTS64mr >+ 336617858U, // BTS64ri8 >+ 336617858U, // BTS64rr >+ 2450544462U, // BZHI32rm >+ 2484098894U, // BZHI32rr >+ 2517653326U, // BZHI64rm >+ 2484098894U, // BZHI64rr >+ 38941U, // CALL16m >+ 22557U, // CALL16r >+ 71709U, // CALL32m >+ 22557U, // CALL32r >+ 88093U, // CALL64m >+ 153629U, // CALL64pcrel32 >+ 22557U, // CALL64r >+ 153629U, // CALLpcrel16 >+ 153629U, // CALLpcrel32 >+ 12204U, // CBW >+ 11812U, // CDQ >+ 11455U, // CDQE >+ 11999U, // CHS_F >+ 0U, // CHS_Fp32 >+ 0U, // CHS_Fp64 >+ 0U, // CHS_Fp80 >+ 11268U, // CLAC >+ 11300U, // CLC >+ 11350U, // CLD >+ 104249U, // CLFLUSH >+ 11570U, // CLGI >+ 11580U, // CLI >+ 12089U, // CLTS >+ 11304U, // CMC >+ 68177251U, // CMOVA16rm >+ 34622819U, // CMOVA16rr >+ 101731683U, // CMOVA32rm >+ 34622819U, // CMOVA32rr >+ 135286115U, // CMOVA64rm >+ 34622819U, // CMOVA64rr >+ 68179448U, // CMOVAE16rm >+ 34625016U, // CMOVAE16rr >+ 101733880U, // CMOVAE32rm >+ 34625016U, // CMOVAE32rr >+ 135288312U, // CMOVAE64rm >+ 34625016U, // CMOVAE64rr >+ 68177579U, // CMOVB16rm >+ 34623147U, // CMOVB16rr >+ 101732011U, // CMOVB32rm >+ 34623147U, // CMOVB32rr >+ 135286443U, // CMOVB64rm >+ 34623147U, // CMOVB64rr >+ 68179468U, // CMOVBE16rm >+ 34625036U, // CMOVBE16rr >+ 101733900U, // CMOVBE32rm >+ 34625036U, // CMOVBE32rr >+ 135288332U, // CMOVBE64rm >+ 34625036U, // CMOVBE64rr >+ 26027U, // CMOVBE_F >+ 0U, // CMOVBE_Fp32 >+ 0U, // CMOVBE_Fp64 >+ 0U, // CMOVBE_Fp80 >+ 25995U, // CMOVB_F >+ 0U, // CMOVB_Fp32 >+ 0U, // CMOVB_Fp64 >+ 0U, // CMOVB_Fp80 >+ 68179662U, // CMOVE16rm >+ 34625230U, // CMOVE16rr >+ 101734094U, // CMOVE32rm >+ 34625230U, // CMOVE32rr >+ 135288526U, // CMOVE64rm >+ 34625230U, // CMOVE64rr >+ 26059U, // CMOVE_F >+ 0U, // CMOVE_Fp32 >+ 0U, // CMOVE_Fp64 >+ 0U, // CMOVE_Fp80 >+ 68179712U, // CMOVG16rm >+ 34625280U, // CMOVG16rr >+ 101734144U, // CMOVG32rm >+ 34625280U, // CMOVG32rr >+ 135288576U, // CMOVG64rm >+ 34625280U, // CMOVG64rr >+ 68179513U, // CMOVGE16rm >+ 34625081U, // CMOVGE16rr >+ 101733945U, // CMOVGE32rm >+ 34625081U, // CMOVGE32rr >+ 135288377U, // CMOVGE64rm >+ 34625081U, // CMOVGE64rr >+ 68180080U, // CMOVL16rm >+ 34625648U, // CMOVL16rr >+ 101734512U, // CMOVL32rm >+ 34625648U, // CMOVL32rr >+ 135288944U, // CMOVL64rm >+ 34625648U, // CMOVL64rr >+ 68179537U, // CMOVLE16rm >+ 34625105U, // CMOVLE16rr >+ 101733969U, // CMOVLE32rm >+ 34625105U, // CMOVLE32rr >+ 135288401U, // CMOVLE64rm >+ 34625105U, // CMOVLE64rr >+ 26010U, // CMOVNBE_F >+ 0U, // CMOVNBE_Fp32 >+ 0U, // CMOVNBE_Fp64 >+ 0U, // CMOVNBE_Fp80 >+ 25979U, // CMOVNB_F >+ 0U, // CMOVNB_Fp32 >+ 0U, // CMOVNB_Fp64 >+ 0U, // CMOVNB_Fp80 >+ 68179565U, // CMOVNE16rm >+ 34625133U, // CMOVNE16rr >+ 101733997U, // CMOVNE32rm >+ 34625133U, // CMOVNE32rr >+ 135288429U, // CMOVNE64rm >+ 34625133U, // CMOVNE64rr >+ 26043U, // CMOVNE_F >+ 0U, // CMOVNE_Fp32 >+ 0U, // CMOVNE_Fp64 >+ 0U, // CMOVNE_Fp80 >+ 68180190U, // CMOVNO16rm >+ 34625758U, // CMOVNO16rr >+ 101734622U, // CMOVNO32rm >+ 34625758U, // CMOVNO32rr >+ 135289054U, // CMOVNO64rm >+ 34625758U, // CMOVNO64rr >+ 68180302U, // CMOVNP16rm >+ 34625870U, // CMOVNP16rr >+ 101734734U, // CMOVNP32rm >+ 34625870U, // CMOVNP32rr >+ 135289166U, // CMOVNP64rm >+ 34625870U, // CMOVNP64rr >+ 26114U, // CMOVNP_F >+ 0U, // CMOVNP_Fp32 >+ 0U, // CMOVNP_Fp64 >+ 0U, // CMOVNP_Fp80 >+ 68181236U, // CMOVNS16rm >+ 34626804U, // CMOVNS16rr >+ 101735668U, // CMOVNS32rm >+ 34626804U, // CMOVNS32rr >+ 135290100U, // CMOVNS64rm >+ 34626804U, // CMOVNS64rr >+ 68180204U, // CMOVO16rm >+ 34625772U, // CMOVO16rr >+ 101734636U, // CMOVO32rm >+ 34625772U, // CMOVO32rr >+ 135289068U, // CMOVO64rm >+ 34625772U, // CMOVO64rr >+ 68180431U, // CMOVP16rm >+ 34625999U, // CMOVP16rr >+ 101734863U, // CMOVP32rm >+ 34625999U, // CMOVP32rr >+ 135289295U, // CMOVP64rm >+ 34625999U, // CMOVP64rr >+ 26130U, // CMOVP_F >+ 0U, // CMOVP_Fp32 >+ 0U, // CMOVP_Fp64 >+ 0U, // CMOVP_Fp80 >+ 68182413U, // CMOVS16rm >+ 34627981U, // CMOVS16rr >+ 101736845U, // CMOVS32rm >+ 34627981U, // CMOVS32rr >+ 135291277U, // CMOVS64rm >+ 34627981U, // CMOVS64rr >+ 10618U, // CMOV_FR32 >+ 10777U, // CMOV_FR64 >+ 10497U, // CMOV_GR16 >+ 10477U, // CMOV_GR32 >+ 10796U, // CMOV_GR8 >+ 10598U, // CMOV_RFP32 >+ 10757U, // CMOV_RFP64 >+ 10517U, // CMOV_RFP80 >+ 10557U, // CMOV_V16F32 >+ 10637U, // CMOV_V2F64 >+ 10697U, // CMOV_V2I64 >+ 10537U, // CMOV_V4F32 >+ 10657U, // CMOV_V4F64 >+ 10717U, // CMOV_V4I64 >+ 10578U, // CMOV_V8F32 >+ 10677U, // CMOV_V8F64 >+ 10737U, // CMOV_V8I64 >+ 26332U, // CMP16i16 >+ 1087776U, // CMP16mi >+ 1087776U, // CMP16mi8 >+ 1087776U, // CMP16mr >+ 336615712U, // CMP16ri >+ 336615712U, // CMP16ri8 >+ 470833440U, // CMP16rm >+ 336615712U, // CMP16rr >+ 336615712U, // CMP16rr_REV >+ 26497U, // CMP32i32 >+ 1120544U, // CMP32mi >+ 1120544U, // CMP32mi8 >+ 1120544U, // CMP32mr >+ 336615712U, // CMP32ri >+ 336615712U, // CMP32ri8 >+ 303061280U, // CMP32rm >+ 336615712U, // CMP32rr >+ 336615712U, // CMP32rr_REV >+ 26612U, // CMP64i32 >+ 1136928U, // CMP64mi32 >+ 1136928U, // CMP64mi8 >+ 1136928U, // CMP64mr >+ 336615712U, // CMP64ri32 >+ 336615712U, // CMP64ri8 >+ 370170144U, // CMP64rm >+ 336615712U, // CMP64rr >+ 336615712U, // CMP64rr_REV >+ 26220U, // CMP8i8 >+ 1153312U, // CMP8mi >+ 1153312U, // CMP8mr >+ 336615712U, // CMP8ri >+ 504387872U, // CMP8rm >+ 336615712U, // CMP8rr >+ 336615712U, // CMP8rr_REV >+ 204647927U, // CMPPDrmi >+ 2349879989U, // CMPPDrmi_alt >+ 36892151U, // CMPPDrri >+ 2182107829U, // CMPPDrri_alt >+ 205696503U, // CMPPSrmi >+ 2349883236U, // CMPPSrmi_alt >+ 37940727U, // CMPPSrri >+ 2182111076U, // CMPPSrri_alt >+ 200221U, // CMPSB >+ 240299511U, // CMPSDrm >+ 2383434910U, // CMPSDrm_alt >+ 38989303U, // CMPSDrr >+ 2182108318U, // CMPSDrr_alt >+ 218270U, // CMPSL >+ 236406U, // CMPSQ >+ 274902519U, // CMPSSrm >+ 2416992560U, // CMPSSrm_alt >+ 40037879U, // CMPSSrr >+ 2182111536U, // CMPSSrr_alt >+ 255070U, // CMPSW >+ 265578U, // CMPXCHG16B >+ 1087205U, // CMPXCHG16rm >+ 336615141U, // CMPXCHG16rr >+ 1119973U, // CMPXCHG32rm >+ 336615141U, // CMPXCHG32rr >+ 1136357U, // CMPXCHG64rm >+ 336615141U, // CMPXCHG64rr >+ 85366U, // CMPXCHG8B >+ 1152741U, // CMPXCHG8rm >+ 336615141U, // CMPXCHG8rr >+ 537941100U, // COMISDrm >+ 336614508U, // COMISDrr >+ 537944326U, // COMISSrm >+ 336617734U, // COMISSrr >+ 22827U, // COMP_FST0r >+ 22413U, // COM_FIPr >+ 22356U, // COM_FIr >+ 22652U, // COM_FST0r >+ 12061U, // COS_F >+ 0U, // COS_Fp32 >+ 0U, // COS_Fp64 >+ 0U, // COS_Fp80 >+ 11344U, // CPUID32 >+ 11344U, // CPUID64 >+ 11745U, // CQO >+ 68209583U, // CRC32r32m16 >+ 101764015U, // CRC32r32m32 >+ 168872879U, // CRC32r32m8 >+ 34655151U, // CRC32r32r16 >+ 34655151U, // CRC32r32r32 >+ 34655151U, // CRC32r32r8 >+ 135318447U, // CRC32r64m64 >+ 168872879U, // CRC32r64m8 >+ 34655151U, // CRC32r64r64 >+ 34655151U, // CRC32r64r8 >+ 370168103U, // CVTDQ2PDrm >+ 336613671U, // CVTDQ2PDrr >+ 437280213U, // CVTDQ2PSrm >+ 336616917U, // CVTDQ2PSrr >+ 537942567U, // CVTPD2DQrm >+ 336615975U, // CVTPD2DQrr >+ 537943465U, // CVTPD2PSrm >+ 336616873U, // CVTPD2PSrr >+ 537942599U, // CVTPS2DQrm >+ 336616007U, // CVTPS2DQrr >+ 571494706U, // CVTPS2PDrm >+ 336613682U, // CVTPS2PDrr >+ 571496387U, // CVTSD2SI64rm >+ 336615363U, // CVTSD2SI64rr >+ 571496387U, // CVTSD2SIrm >+ 336615363U, // CVTSD2SIrr >+ 571498601U, // CVTSD2SSrm >+ 336617577U, // CVTSD2SSrr >+ 370168775U, // CVTSI2SD64rm >+ 336614343U, // CVTSI2SD64rr >+ 303059911U, // CVTSI2SDrm >+ 336614343U, // CVTSI2SDrr >+ 370172020U, // CVTSI2SS64rm >+ 336617588U, // CVTSI2SS64rr >+ 303063156U, // CVTSI2SSrm >+ 336617588U, // CVTSI2SSrr >+ 605049822U, // CVTSS2SDrm >+ 336614366U, // CVTSS2SDrr >+ 605050842U, // CVTSS2SI64rm >+ 336615386U, // CVTSS2SI64rr >+ 605050842U, // CVTSS2SIrm >+ 336615386U, // CVTSS2SIrr >+ 537942555U, // CVTTPD2DQrm >+ 336615963U, // CVTTPD2DQrr >+ 537942587U, // CVTTPS2DQrm >+ 336615995U, // CVTTPS2DQrr >+ 571496375U, // CVTTSD2SI64rm >+ 336615351U, // CVTTSD2SI64rr >+ 571496375U, // CVTTSD2SIrm >+ 336615351U, // CVTTSD2SIrr >+ 605050830U, // CVTTSS2SI64rm >+ 336615374U, // CVTTSS2SI64rr >+ 605050830U, // CVTTSS2SIrm >+ 336615374U, // CVTTSS2SIrr >+ 11396U, // CWD >+ 11428U, // CWDE >+ 11203U, // DAA >+ 11915U, // DAS >+ 11084U, // DATA16_PREFIX >+ 36585U, // DEC16m >+ 20201U, // DEC16r >+ 20201U, // DEC32_16r >+ 20201U, // DEC32_32r >+ 69353U, // DEC32m >+ 20201U, // DEC32r >+ 36585U, // DEC64_16m >+ 20201U, // DEC64_16r >+ 69353U, // DEC64_32m >+ 20201U, // DEC64_32r >+ 85737U, // DEC64m >+ 20201U, // DEC64r >+ 102121U, // DEC8m >+ 20201U, // DEC8r >+ 41599U, // DIV16m >+ 25215U, // DIV16r >+ 74367U, // DIV32m >+ 25215U, // DIV32r >+ 90751U, // DIV64m >+ 25215U, // DIV64r >+ 107135U, // DIV8m >+ 25215U, // DIV8r >+ 202396424U, // DIVPDrm >+ 34624264U, // DIVPDrr >+ 202399704U, // DIVPSrm >+ 34627544U, // DIVPSrr >+ 122035U, // DIVR_F32m >+ 138419U, // DIVR_F64m >+ 40122U, // DIVR_FI16m >+ 72890U, // DIVR_FI32m >+ 22894U, // DIVR_FPrST0 >+ 23731U, // DIVR_FST0r >+ 0U, // DIVR_Fp32m >+ 0U, // DIVR_Fp64m >+ 0U, // DIVR_Fp64m32 >+ 0U, // DIVR_Fp80m32 >+ 0U, // DIVR_Fp80m64 >+ 0U, // DIVR_FpI16m32 >+ 0U, // DIVR_FpI16m64 >+ 0U, // DIVR_FpI16m80 >+ 0U, // DIVR_FpI32m32 >+ 0U, // DIVR_FpI32m64 >+ 0U, // DIVR_FpI32m80 >+ 2120883U, // DIVR_FrST0 >+ 235951302U, // DIVSDrm >+ 235951302U, // DIVSDrm_Int >+ 34624710U, // DIVSDrr >+ 34624710U, // DIVSDrr_Int >+ 269508962U, // DIVSSrm >+ 269508962U, // DIVSSrm_Int >+ 34627938U, // DIVSSrr >+ 34627938U, // DIVSSrr_Int >+ 123518U, // DIV_F32m >+ 139902U, // DIV_F64m >+ 41604U, // DIV_FI16m >+ 74372U, // DIV_FI32m >+ 22984U, // DIV_FPrST0 >+ 25214U, // DIV_FST0r >+ 0U, // DIV_Fp32 >+ 0U, // DIV_Fp32m >+ 0U, // DIV_Fp64 >+ 0U, // DIV_Fp64m >+ 0U, // DIV_Fp64m32 >+ 0U, // DIV_Fp80 >+ 0U, // DIV_Fp80m32 >+ 0U, // DIV_Fp80m64 >+ 0U, // DIV_FpI16m32 >+ 0U, // DIV_FpI16m64 >+ 0U, // DIV_FpI16m80 >+ 0U, // DIV_FpI32m32 >+ 0U, // DIV_FpI32m64 >+ 0U, // DIV_FpI32m80 >+ 2122366U, // DIV_FrST0 >+ 2349879982U, // DPPDrmi >+ 2182107822U, // DPPDrri >+ 2349883229U, // DPPSrmi >+ 2182111069U, // DPPSrri >+ 26724U, // EH_RETURN >+ 26724U, // EH_RETURN64 >+ 10893U, // EH_SjLj_LongJmp32 >+ 10997U, // EH_SjLj_LongJmp64 >+ 10912U, // EH_SjLj_SetJmp32 >+ 11016U, // EH_SjLj_SetJmp64 >+ 154040U, // EH_SjLj_Setup >+ 12049U, // ENCLS >+ 12171U, // ENCLU >+ 336616511U, // ENTER >+ 2148654983U, // EXTRACTPSmr >+ 2484100999U, // EXTRACTPSrr >+ 34659176U, // EXTRQ >+ 2182142824U, // EXTRQI >+ 10874U, // F2XM1 >+ 7395356U, // FARCALL16i >+ 284700U, // FARCALL16m >+ 7395356U, // FARCALL32i >+ 284700U, // FARCALL32m >+ 284700U, // FARCALL64 >+ 7395621U, // FARJMP16i >+ 284965U, // FARJMP16m >+ 7395621U, // FARJMP32i >+ 284965U, // FARJMP32m >+ 284965U, // FARJMP64 >+ 118778U, // FBLDm >+ 121212U, // FBSTPm >+ 120956U, // FCOM32m >+ 137340U, // FCOM64m >+ 121131U, // FCOMP32m >+ 137515U, // FCOMP64m >+ 11781U, // FCOMPP >+ 11796U, // FDECSTP >+ 12055U, // FEMMS >+ 22045U, // FFREE >+ 39042U, // FICOM16m >+ 71810U, // FICOM32m >+ 39218U, // FICOMP16m >+ 71986U, // FICOMP32m >+ 11804U, // FINCSTP >+ 41765U, // FLDCW16m >+ 123531U, // FLDENVm >+ 11400U, // FLDL2E >+ 12094U, // FLDL2T >+ 10978U, // FLDLG2 >+ 10985U, // FLDLN2 >+ 11584U, // FLDPI >+ 12407U, // FNCLEX >+ 12127U, // FNINIT >+ 11776U, // FNOP >+ 41772U, // FNSTCW16m >+ 12234U, // FNSTSW16r >+ 124016U, // FNSTSWm >+ 0U, // FP32_TO_INT16_IN_MEM >+ 0U, // FP32_TO_INT32_IN_MEM >+ 0U, // FP32_TO_INT64_IN_MEM >+ 0U, // FP64_TO_INT16_IN_MEM >+ 0U, // FP64_TO_INT32_IN_MEM >+ 0U, // FP64_TO_INT64_IN_MEM >+ 0U, // FP80_TO_INT16_IN_MEM >+ 0U, // FP80_TO_INT32_IN_MEM >+ 0U, // FP80_TO_INT64_IN_MEM >+ 11700U, // FPATAN >+ 11683U, // FPREM >+ 10867U, // FPREM1 >+ 11707U, // FPTAN >+ 12146U, // FRNDINT >+ 121952U, // FRSTORm >+ 120510U, // FSAVEm >+ 11433U, // FSCALE >+ 11689U, // FSETPM >+ 12066U, // FSINCOS >+ 123539U, // FSTENVm >+ 11678U, // FXAM >+ 285800U, // FXRSTOR >+ 281615U, // FXRSTOR64 >+ 284358U, // FXSAVE >+ 281605U, // FXSAVE64 >+ 12101U, // FXTRACT >+ 12228U, // FYL2X >+ 10880U, // FYL2XP1 >+ 202396317U, // FsANDNPDrm >+ 34624157U, // FsANDNPDrr >+ 202399556U, // FsANDNPSrm >+ 34627396U, // FsANDNPSrr >+ 202396181U, // FsANDPDrm >+ 34624021U, // FsANDPDrr >+ 202399408U, // FsANDPSrm >+ 34627248U, // FsANDPSrr >+ 0U, // FsFLD0SD >+ 0U, // FsFLD0SS >+ 537940371U, // FsMOVAPDrm >+ 537943606U, // FsMOVAPSrm >+ 202396361U, // FsORPDrm >+ 34624201U, // FsORPDrr >+ 202399608U, // FsORPSrm >+ 34627448U, // FsORPSrr >+ 537940370U, // FsVMOVAPDrm >+ 537943605U, // FsVMOVAPSrm >+ 202396368U, // FsXORPDrm >+ 34624208U, // FsXORPDrr >+ 202399615U, // FsXORPSrm >+ 34627455U, // FsXORPSrr >+ 11288U, // GETSEC >+ 202396143U, // HADDPDrm >+ 34623983U, // HADDPDrr >+ 202399370U, // HADDPSrm >+ 34627210U, // HADDPSrr >+ 12142U, // HLT >+ 202396092U, // HSUBPDrm >+ 34623932U, // HSUBPDrr >+ 202399319U, // HSUBPSrm >+ 34627159U, // HSUBPSrr >+ 41605U, // IDIV16m >+ 25221U, // IDIV16r >+ 74373U, // IDIV32m >+ 25221U, // IDIV32r >+ 90757U, // IDIV64m >+ 25221U, // IDIV64r >+ 107141U, // IDIV8m >+ 25221U, // IDIV8r >+ 36877U, // ILD_F16m >+ 69645U, // ILD_F32m >+ 86029U, // ILD_F64m >+ 0U, // ILD_Fp16m32 >+ 0U, // ILD_Fp16m64 >+ 0U, // ILD_Fp16m80 >+ 0U, // ILD_Fp32m32 >+ 0U, // ILD_Fp32m64 >+ 0U, // ILD_Fp32m80 >+ 0U, // ILD_Fp64m32 >+ 0U, // ILD_Fp64m64 >+ 0U, // ILD_Fp64m80 >+ 39018U, // IMUL16m >+ 22634U, // IMUL16r >+ 68180074U, // IMUL16rm >+ 2618316906U, // IMUL16rmi >+ 2618316906U, // IMUL16rmi8 >+ 34625642U, // IMUL16rr >+ 2484099178U, // IMUL16rri >+ 2484099178U, // IMUL16rri8 >+ 71786U, // IMUL32m >+ 22634U, // IMUL32r >+ 101734506U, // IMUL32rm >+ 2450544746U, // IMUL32rmi >+ 2450544746U, // IMUL32rmi8 >+ 34625642U, // IMUL32rr >+ 2484099178U, // IMUL32rri >+ 2484099178U, // IMUL32rri8 >+ 88170U, // IMUL64m >+ 22634U, // IMUL64r >+ 135288938U, // IMUL64rm >+ 2517653610U, // IMUL64rmi32 >+ 2517653610U, // IMUL64rmi8 >+ 34625642U, // IMUL64rr >+ 2484099178U, // IMUL64rri32 >+ 2484099178U, // IMUL64rri8 >+ 104554U, // IMUL8m >+ 22634U, // IMUL8r >+ 26324U, // IN16ri >+ 12386U, // IN16rr >+ 26488U, // IN32ri >+ 12396U, // IN32rr >+ 26212U, // IN8ri >+ 12376U, // IN8rr >+ 36630U, // INC16m >+ 20246U, // INC16r >+ 20246U, // INC32_16r >+ 20246U, // INC32_32r >+ 69398U, // INC32m >+ 20246U, // INC32r >+ 36630U, // INC64_16m >+ 20246U, // INC64_16r >+ 69398U, // INC64_32m >+ 20246U, // INC64_32r >+ 85782U, // INC64m >+ 20246U, // INC64r >+ 102166U, // INC8m >+ 20246U, // INC8r >+ 8687120U, // INSB >+ 2416992157U, // INSERTPSrm >+ 2182111133U, // INSERTPSrr >+ 34659230U, // INSERTQ >+ 2182142878U, // INSERTQI >+ 8705160U, // INSL >+ 8725585U, // INSW >+ 25056U, // INT >+ 10888U, // INT1 >+ 10992U, // INT3 >+ 11749U, // INTO >+ 11391U, // INVD >+ 437281258U, // INVEPT32 >+ 437281258U, // INVEPT64 >+ 104178U, // INVLPG >+ 12342U, // INVLPGA32 >+ 12359U, // INVLPGA64 >+ 437276648U, // INVPCID32 >+ 437276648U, // INVPCID64 >+ 437276657U, // INVVPID32 >+ 437276657U, // INVVPID64 >+ 12109U, // IRET16 >+ 11379U, // IRET32 >+ 11855U, // IRET64 >+ 39312U, // ISTT_FP16m >+ 72080U, // ISTT_FP32m >+ 88464U, // ISTT_FP64m >+ 0U, // ISTT_Fp16m32 >+ 0U, // ISTT_Fp16m64 >+ 0U, // ISTT_Fp16m80 >+ 0U, // ISTT_Fp32m32 >+ 0U, // ISTT_Fp32m64 >+ 0U, // ISTT_Fp32m80 >+ 0U, // ISTT_Fp64m32 >+ 0U, // ISTT_Fp64m64 >+ 0U, // ISTT_Fp64m80 >+ 41524U, // IST_F16m >+ 74292U, // IST_F32m >+ 39305U, // IST_FP16m >+ 72073U, // IST_FP32m >+ 88457U, // IST_FP64m >+ 0U, // IST_Fp16m32 >+ 0U, // IST_Fp16m64 >+ 0U, // IST_Fp16m80 >+ 0U, // IST_Fp32m32 >+ 0U, // IST_Fp32m64 >+ 0U, // IST_Fp32m80 >+ 0U, // IST_Fp64m32 >+ 0U, // IST_Fp64m64 >+ 0U, // IST_Fp64m80 >+ 240299511U, // Int_CMPSDrm >+ 38989303U, // Int_CMPSDrr >+ 274902519U, // Int_CMPSSrm >+ 40037879U, // Int_CMPSSrr >+ 537941100U, // Int_COMISDrm >+ 336614508U, // Int_COMISDrr >+ 537944326U, // Int_COMISSrm >+ 336617734U, // Int_COMISSrr >+ 235954281U, // Int_CVTSD2SSrm >+ 34627689U, // Int_CVTSD2SSrr >+ 135287751U, // Int_CVTSI2SD64rm >+ 34624455U, // Int_CVTSI2SD64rr >+ 101733319U, // Int_CVTSI2SDrm >+ 34624455U, // Int_CVTSI2SDrr >+ 135290996U, // Int_CVTSI2SS64rm >+ 34627700U, // Int_CVTSI2SS64rr >+ 101736564U, // Int_CVTSI2SSrm >+ 34627700U, // Int_CVTSI2SSrr >+ 269505502U, // Int_CVTSS2SDrm >+ 34624478U, // Int_CVTSS2SDrr >+ 571496375U, // Int_CVTTSD2SI64rm >+ 336615351U, // Int_CVTTSD2SI64rr >+ 571496375U, // Int_CVTTSD2SIrm >+ 336615351U, // Int_CVTTSD2SIrr >+ 605050830U, // Int_CVTTSS2SI64rm >+ 336615374U, // Int_CVTTSS2SI64rr >+ 605050830U, // Int_CVTTSS2SIrm >+ 336615374U, // Int_CVTTSS2SIrr >+ 11172U, // Int_MemBarrier >+ 537941099U, // Int_UCOMISDrm >+ 336614507U, // Int_UCOMISDrr >+ 537944325U, // Int_UCOMISSrm >+ 336617733U, // Int_UCOMISSrr >+ 2488626683U, // Int_VCMPSDrm >+ 2488643067U, // Int_VCMPSDrr >+ 2489675259U, // Int_VCMPSSrm >+ 2489691643U, // Int_VCMPSSrr >+ 537941108U, // Int_VCOMISDZrm >+ 336614516U, // Int_VCOMISDZrr >+ 537941108U, // Int_VCOMISDrm >+ 336614516U, // Int_VCOMISDrr >+ 537944334U, // Int_VCOMISSZrm >+ 336617742U, // Int_VCOMISSZrr >+ 537944334U, // Int_VCOMISSrm >+ 336617742U, // Int_VCOMISSrr >+ 2484101224U, // Int_VCVTSD2SSrm >+ 2484101224U, // Int_VCVTSD2SSrr >+ 2484097990U, // Int_VCVTSI2SD64Zrm >+ 2484097990U, // Int_VCVTSI2SD64Zrr >+ 2484097990U, // Int_VCVTSI2SD64rm >+ 2484097990U, // Int_VCVTSI2SD64rr >+ 2484097990U, // Int_VCVTSI2SDZrm >+ 2484097990U, // Int_VCVTSI2SDZrr >+ 2484097990U, // Int_VCVTSI2SDrm >+ 2484097990U, // Int_VCVTSI2SDrr >+ 2484101235U, // Int_VCVTSI2SS64Zrm >+ 2484101235U, // Int_VCVTSI2SS64Zrr >+ 2484101235U, // Int_VCVTSI2SS64rm >+ 2484101235U, // Int_VCVTSI2SS64rr >+ 2484101235U, // Int_VCVTSI2SSZrm >+ 2484101235U, // Int_VCVTSI2SSZrr >+ 2484101235U, // Int_VCVTSI2SSrm >+ 2484101235U, // Int_VCVTSI2SSrr >+ 2484098013U, // Int_VCVTSS2SDrm >+ 2484098013U, // Int_VCVTSS2SDrr >+ 571491619U, // Int_VCVTTSD2SI64Zrm >+ 336610595U, // Int_VCVTTSD2SI64Zrr >+ 571496374U, // Int_VCVTTSD2SI64rm >+ 336615350U, // Int_VCVTTSD2SI64rr >+ 571491619U, // Int_VCVTTSD2SIZrm >+ 336610595U, // Int_VCVTTSD2SIZrr >+ 571496374U, // Int_VCVTTSD2SIrm >+ 336615350U, // Int_VCVTTSD2SIrr >+ 571491669U, // Int_VCVTTSD2USI64Zrm >+ 336610645U, // Int_VCVTTSD2USI64Zrr >+ 571491669U, // Int_VCVTTSD2USIZrm >+ 336610645U, // Int_VCVTTSD2USIZrr >+ 605046076U, // Int_VCVTTSS2SI64Zrm >+ 336610620U, // Int_VCVTTSS2SI64Zrr >+ 605050829U, // Int_VCVTTSS2SI64rm >+ 336615373U, // Int_VCVTTSS2SI64rr >+ 605046076U, // Int_VCVTTSS2SIZrm >+ 336610620U, // Int_VCVTTSS2SIZrr >+ 605050829U, // Int_VCVTTSS2SIrm >+ 336615373U, // Int_VCVTTSS2SIrr >+ 605046128U, // Int_VCVTTSS2USI64Zrm >+ 336610672U, // Int_VCVTTSS2USI64Zrr >+ 605046128U, // Int_VCVTTSS2USIZrm >+ 336610672U, // Int_VCVTTSS2USIZrr >+ 2484098001U, // Int_VCVTUSI2SD64Zrm >+ 2484098001U, // Int_VCVTUSI2SD64Zrr >+ 2484098001U, // Int_VCVTUSI2SDZrm >+ 2484098001U, // Int_VCVTUSI2SDZrr >+ 2484101246U, // Int_VCVTUSI2SS64Zrm >+ 2484101246U, // Int_VCVTUSI2SS64Zrr >+ 2484101246U, // Int_VCVTUSI2SSZrm >+ 2484101246U, // Int_VCVTUSI2SSZrr >+ 537941098U, // Int_VUCOMISDZrm >+ 336614506U, // Int_VUCOMISDZrr >+ 537941098U, // Int_VUCOMISDrm >+ 336614506U, // Int_VUCOMISDrr >+ 537944324U, // Int_VUCOMISSZrm >+ 336617732U, // Int_VUCOMISSZrr >+ 537944324U, // Int_VUCOMISSrm >+ 336617732U, // Int_VUCOMISSrr >+ 153068U, // JAE_1 >+ 153068U, // JAE_2 >+ 153068U, // JAE_4 >+ 150840U, // JA_1 >+ 150840U, // JA_2 >+ 150840U, // JA_4 >+ 153088U, // JBE_1 >+ 153088U, // JBE_2 >+ 153088U, // JBE_4 >+ 150959U, // JB_1 >+ 150959U, // JB_2 >+ 150959U, // JB_4 >+ 157038U, // JCXZ >+ 157031U, // JECXZ_32 >+ 157031U, // JECXZ_64 >+ 153153U, // JE_1 >+ 153153U, // JE_2 >+ 153153U, // JE_4 >+ 153124U, // JGE_1 >+ 153124U, // JGE_2 >+ 153124U, // JGE_4 >+ 153326U, // JG_1 >+ 153326U, // JG_2 >+ 153326U, // JG_4 >+ 153157U, // JLE_1 >+ 153157U, // JLE_2 >+ 153157U, // JLE_4 >+ 153624U, // JL_1 >+ 153624U, // JL_2 >+ 153624U, // JL_4 >+ 39206U, // JMP16m >+ 22822U, // JMP16r >+ 71974U, // JMP32m >+ 22822U, // JMP32r >+ 88358U, // JMP64m >+ 22822U, // JMP64r >+ 153894U, // JMP_1 >+ 153894U, // JMP_2 >+ 153894U, // JMP_4 >+ 153177U, // JNE_1 >+ 153177U, // JNE_2 >+ 153177U, // JNE_4 >+ 153810U, // JNO_1 >+ 153810U, // JNO_2 >+ 153810U, // JNO_4 >+ 153922U, // JNP_1 >+ 153922U, // JNP_2 >+ 153922U, // JNP_4 >+ 154856U, // JNS_1 >+ 154856U, // JNS_2 >+ 154856U, // JNS_4 >+ 153806U, // JO_1 >+ 153806U, // JO_2 >+ 153806U, // JO_4 >+ 153877U, // JP_1 >+ 153877U, // JP_2 >+ 153877U, // JP_4 >+ 157044U, // JRCXZ >+ 154852U, // JS_1 >+ 154852U, // JS_2 >+ 154852U, // JS_4 >+ 2484092965U, // KANDBrr >+ 2484093179U, // KANDDrr >+ 2484093006U, // KANDNBrr >+ 2484093305U, // KANDNDrr >+ 2484094782U, // KANDNQrr >+ 2484095738U, // KANDNWrr >+ 2484094559U, // KANDQrr >+ 2484095686U, // KANDWrr >+ 336609432U, // KMOVBkk >+ 504381592U, // KMOVBkm >+ 336609432U, // KMOVBkr >+ 1147032U, // KMOVBmk >+ 336609432U, // KMOVBrk >+ 336610551U, // KMOVDkk >+ 303056119U, // KMOVDkm >+ 336610551U, // KMOVDkr >+ 1115383U, // KMOVDmk >+ 336610551U, // KMOVDrk >+ 336611358U, // KMOVQkk >+ 370165790U, // KMOVQkm >+ 336611358U, // KMOVQkr >+ 1132574U, // KMOVQmk >+ 336611358U, // KMOVQrk >+ 336612186U, // KMOVWkk >+ 470829914U, // KMOVWkm >+ 336612186U, // KMOVWkr >+ 1084250U, // KMOVWmk >+ 336612186U, // KMOVWrk >+ 336609424U, // KNOTBrr >+ 336610478U, // KNOTDrr >+ 336611285U, // KNOTQrr >+ 336612167U, // KNOTWrr >+ 2484093048U, // KORBrr >+ 2484093862U, // KORDrr >+ 2484094838U, // KORQrr >+ 336612175U, // KORTESTWrr >+ 2484095780U, // KORWrr >+ 0U, // KSET0B >+ 0U, // KSET0W >+ 0U, // KSET1B >+ 0U, // KSET1W >+ 2484095727U, // KSHIFTLWri >+ 2484095804U, // KSHIFTRWri >+ 2484095675U, // KUNPCKBWrr >+ 2484093055U, // KXNORBrr >+ 2484093869U, // KXNORDrr >+ 2484094845U, // KXNORQrr >+ 2484095787U, // KXNORWrr >+ 2484093064U, // KXORBrr >+ 2484093886U, // KXORDrr >+ 2484094862U, // KXORQrr >+ 2484095796U, // KXORWrr >+ 11535U, // LAHF >+ 470834208U, // LAR16rm >+ 336616480U, // LAR16rr >+ 470834208U, // LAR32rm >+ 336616480U, // LAR32rr >+ 470834208U, // LAR64rm >+ 336616480U, // LAR64rr >+ 1087205U, // LCMPXCHG16 >+ 265578U, // LCMPXCHG16B >+ 1119973U, // LCMPXCHG32 >+ 1136357U, // LCMPXCHG64 >+ 1152741U, // LCMPXCHG8 >+ 85366U, // LCMPXCHG8B >+ 437281377U, // LDDQUrm >+ 72836U, // LDMXCSR >+ 638606544U, // LDS16rm >+ 638606544U, // LDS32rm >+ 12414U, // LD_F0 >+ 10862U, // LD_F1 >+ 118784U, // LD_F32m >+ 135168U, // LD_F64m >+ 380928U, // LD_F80m >+ 0U, // LD_Fp032 >+ 0U, // LD_Fp064 >+ 0U, // LD_Fp080 >+ 0U, // LD_Fp132 >+ 0U, // LD_Fp164 >+ 0U, // LD_Fp180 >+ 0U, // LD_Fp32m >+ 0U, // LD_Fp32m64 >+ 0U, // LD_Fp32m80 >+ 0U, // LD_Fp64m >+ 0U, // LD_Fp64m80 >+ 0U, // LD_Fp80m >+ 20480U, // LD_Frr >+ 470830387U, // LEA16r >+ 303058227U, // LEA32r >+ 303058227U, // LEA64_32r >+ 370167091U, // LEA64r >+ 11522U, // LEAVE >+ 11522U, // LEAVE64 >+ 638606549U, // LES16rm >+ 638606549U, // LES32rm >+ 11407U, // LFENCE >+ 638606554U, // LFS16rm >+ 638606554U, // LFS32rm >+ 638606554U, // LFS64rm >+ 287128U, // LGDT16m >+ 287128U, // LGDT32m >+ 287128U, // LGDT64m >+ 638606559U, // LGS16rm >+ 638606559U, // LGS32rm >+ 638606559U, // LGS64rm >+ 287140U, // LIDT16m >+ 287140U, // LIDT32m >+ 287140U, // LIDT64m >+ 41392U, // LLDT16m >+ 25008U, // LLDT16r >+ 42050U, // LMSW16m >+ 25666U, // LMSW16r >+ 1085307U, // LOCK_ADD16mi >+ 1085307U, // LOCK_ADD16mi8 >+ 1085307U, // LOCK_ADD16mr >+ 1118075U, // LOCK_ADD32mi >+ 1118075U, // LOCK_ADD32mi8 >+ 1118075U, // LOCK_ADD32mr >+ 1134459U, // LOCK_ADD64mi32 >+ 1134459U, // LOCK_ADD64mi8 >+ 1134459U, // LOCK_ADD64mr >+ 1150843U, // LOCK_ADD8mi >+ 1150843U, // LOCK_ADD8mr >+ 1085511U, // LOCK_AND16mi >+ 1085511U, // LOCK_AND16mi8 >+ 1085511U, // LOCK_AND16mr >+ 1118279U, // LOCK_AND32mi >+ 1118279U, // LOCK_AND32mi8 >+ 1118279U, // LOCK_AND32mr >+ 1134663U, // LOCK_AND64mi32 >+ 1134663U, // LOCK_AND64mi8 >+ 1134663U, // LOCK_AND64mr >+ 1151047U, // LOCK_AND8mi >+ 1151047U, // LOCK_AND8mr >+ 36585U, // LOCK_DEC16m >+ 69353U, // LOCK_DEC32m >+ 85737U, // LOCK_DEC64m >+ 102121U, // LOCK_DEC8m >+ 36630U, // LOCK_INC16m >+ 69398U, // LOCK_INC32m >+ 85782U, // LOCK_INC64m >+ 102166U, // LOCK_INC8m >+ 1088599U, // LOCK_OR16mi >+ 1088599U, // LOCK_OR16mi8 >+ 1088599U, // LOCK_OR16mr >+ 1121367U, // LOCK_OR32mi >+ 1121367U, // LOCK_OR32mi8 >+ 1121367U, // LOCK_OR32mr >+ 1137751U, // LOCK_OR64mi32 >+ 1137751U, // LOCK_OR64mi8 >+ 1137751U, // LOCK_OR64mr >+ 1154135U, // LOCK_OR8mi >+ 1154135U, // LOCK_OR8mr >+ 11609U, // LOCK_PREFIX >+ 1085067U, // LOCK_SUB16mi >+ 1085067U, // LOCK_SUB16mi8 >+ 1085067U, // LOCK_SUB16mr >+ 1117835U, // LOCK_SUB32mi >+ 1117835U, // LOCK_SUB32mi8 >+ 1117835U, // LOCK_SUB32mr >+ 1134219U, // LOCK_SUB64mi32 >+ 1134219U, // LOCK_SUB64mi8 >+ 1134219U, // LOCK_SUB64mr >+ 1150603U, // LOCK_SUB8mi >+ 1150603U, // LOCK_SUB8mr >+ 1088627U, // LOCK_XOR16mi >+ 1088627U, // LOCK_XOR16mi8 >+ 1088627U, // LOCK_XOR16mr >+ 1121395U, // LOCK_XOR32mi >+ 1121395U, // LOCK_XOR32mi8 >+ 1121395U, // LOCK_XOR32mr >+ 1137779U, // LOCK_XOR64mi32 >+ 1137779U, // LOCK_XOR64mi8 >+ 1137779U, // LOCK_XOR64mr >+ 1154163U, // LOCK_XOR8mi >+ 1154163U, // LOCK_XOR8mr >+ 402997U, // LODSB >+ 419681U, // LODSL >+ 436234U, // LODSQ >+ 452376U, // LODSW >+ 153947U, // LOOP >+ 153205U, // LOOPE >+ 153182U, // LOOPNE >+ 22234U, // LRETIL >+ 23312U, // LRETIQ >+ 22234U, // LRETIW >+ 11556U, // LRETL >+ 11829U, // LRETQ >+ 11556U, // LRETW >+ 470833239U, // LSL16rm >+ 336615511U, // LSL16rr >+ 303061079U, // LSL32rm >+ 336615511U, // LSL32rr >+ 370169943U, // LSL64rm >+ 336615511U, // LSL64rr >+ 638607642U, // LSS16rm >+ 638607642U, // LSS32rm >+ 638607642U, // LSS64rm >+ 40098U, // LTRm >+ 23714U, // LTRr >+ 462727U, // LXADD16 >+ 479111U, // LXADD32 >+ 495495U, // LXADD64 >+ 511879U, // LXADD8 >+ 470835666U, // LZCNT16rm >+ 336617938U, // LZCNT16rr >+ 303063506U, // LZCNT32rm >+ 336617938U, // LZCNT32rr >+ 370172370U, // LZCNT64rm >+ 336617938U, // LZCNT64rr >+ 336618089U, // MASKMOVDQU >+ 336618089U, // MASKMOVDQU64 >+ 202396444U, // MAXCPDrm >+ 34624284U, // MAXCPDrr >+ 202399724U, // MAXCPSrm >+ 34627564U, // MAXCPSrr >+ 235951319U, // MAXCSDrm >+ 34624727U, // MAXCSDrr >+ 269508978U, // MAXCSSrm >+ 34627954U, // MAXCSSrr >+ 202396444U, // MAXPDrm >+ 34624284U, // MAXPDrr >+ 202399724U, // MAXPSrm >+ 34627564U, // MAXPSrr >+ 235951319U, // MAXSDrm >+ 235951319U, // MAXSDrm_Int >+ 34624727U, // MAXSDrr >+ 34624727U, // MAXSDrr_Int >+ 269508978U, // MAXSSrm >+ 269508978U, // MAXSSrm_Int >+ 34627954U, // MAXSSrr >+ 34627954U, // MAXSSrr_Int >+ 11414U, // MFENCE >+ 202396326U, // MINCPDrm >+ 34624166U, // MINCPDrr >+ 202399565U, // MINCPSrm >+ 34627405U, // MINCPSrr >+ 235951239U, // MINCSDrm >+ 34624647U, // MINCSDrr >+ 269508896U, // MINCSSrm >+ 34627872U, // MINCSSrr >+ 202396326U, // MINPDrm >+ 34624166U, // MINPDrr >+ 202399565U, // MINPSrm >+ 34627405U, // MINPSrr >+ 235951239U, // MINSDrm >+ 235951239U, // MINSDrm_Int >+ 34624647U, // MINSDrr >+ 34624647U, // MINSDrr_Int >+ 269508896U, // MINSSrm >+ 269508896U, // MINSSrm_Int >+ 34627872U, // MINSSrr >+ 34627872U, // MINSSrr_Int >+ 537941870U, // MMX_CVTPD2PIirm >+ 336615278U, // MMX_CVTPD2PIirr >+ 370168080U, // MMX_CVTPI2PDirm >+ 336613648U, // MMX_CVTPI2PDirr >+ 135290302U, // MMX_CVTPI2PSirm >+ 34627006U, // MMX_CVTPI2PSirr >+ 571496323U, // MMX_CVTPS2PIirm >+ 336615299U, // MMX_CVTPS2PIirr >+ 537941859U, // MMX_CVTTPD2PIirm >+ 336615267U, // MMX_CVTTPD2PIirr >+ 571496312U, // MMX_CVTTPS2PIirm >+ 336615288U, // MMX_CVTTPS2PIirr >+ 12056U, // MMX_EMMS >+ 336616411U, // MMX_MASKMOVQ >+ 336616411U, // MMX_MASKMOVQ64 >+ 336614740U, // MMX_MOVD64from64rr >+ 336614740U, // MMX_MOVD64grr >+ 1119572U, // MMX_MOVD64mr >+ 303060308U, // MMX_MOVD64rm >+ 336614740U, // MMX_MOVD64rr >+ 336614740U, // MMX_MOVD64to64rr >+ 336615894U, // MMX_MOVDQ2Qrr >+ 336615894U, // MMX_MOVFR642Qrr >+ 1137550U, // MMX_MOVNTQmr >+ 336615985U, // MMX_MOVQ2DQrr >+ 336615985U, // MMX_MOVQ2FR64rr >+ 1137631U, // MMX_MOVQ64mr >+ 370170847U, // MMX_MOVQ64rm >+ 336616415U, // MMX_MOVQ64rr >+ 336616415U, // MMX_MOVQ64rr_REV >+ 370167284U, // MMX_PABSBrm64 >+ 336612852U, // MMX_PABSBrr64 >+ 370168863U, // MMX_PABSDrm64 >+ 336614431U, // MMX_PABSDrr64 >+ 370172937U, // MMX_PABSWrm64 >+ 336618505U, // MMX_PABSWrr64 >+ 135291728U, // MMX_PACKSSDWirm >+ 34628432U, // MMX_PACKSSDWirr >+ 135286451U, // MMX_PACKSSWBirm >+ 34623155U, // MMX_PACKSSWBirr >+ 135286462U, // MMX_PACKUSWBirm >+ 34623166U, // MMX_PACKUSWBirr >+ 135286167U, // MMX_PADDBirm >+ 34622871U, // MMX_PADDBirr >+ 135286679U, // MMX_PADDDirm >+ 34623383U, // MMX_PADDDirr >+ 135289436U, // MMX_PADDQirm >+ 34626140U, // MMX_PADDQirr >+ 135286277U, // MMX_PADDSBirm >+ 34622981U, // MMX_PADDSBirr >+ 135291962U, // MMX_PADDSWirm >+ 34628666U, // MMX_PADDSWirr >+ 135286319U, // MMX_PADDUSBirm >+ 34623023U, // MMX_PADDUSBirr >+ 135292035U, // MMX_PADDUSWirm >+ 34628739U, // MMX_PADDUSWirr >+ 135291710U, // MMX_PADDWirm >+ 34628414U, // MMX_PADDWirr >+ 2282773580U, // MMX_PALIGNR64irm >+ 2182110284U, // MMX_PALIGNR64irr >+ 135289009U, // MMX_PANDNirm >+ 34625713U, // MMX_PANDNirr >+ 135286854U, // MMX_PANDirm >+ 34623558U, // MMX_PANDirr >+ 135286184U, // MMX_PAVGBirm >+ 34622888U, // MMX_PAVGBirr >+ 135291765U, // MMX_PAVGWirm >+ 34628469U, // MMX_PAVGWirr >+ 135286232U, // MMX_PCMPEQBirm >+ 34622936U, // MMX_PCMPEQBirr >+ 135287597U, // MMX_PCMPEQDirm >+ 34624301U, // MMX_PCMPEQDirr >+ 135291870U, // MMX_PCMPEQWirm >+ 34628574U, // MMX_PCMPEQWirr >+ 135286360U, // MMX_PCMPGTBirm >+ 34623064U, // MMX_PCMPGTBirr >+ 135288048U, // MMX_PCMPGTDirm >+ 34624752U, // MMX_PCMPGTDirr >+ 135292061U, // MMX_PCMPGTWirm >+ 34628765U, // MMX_PCMPGTWirr >+ 2484102144U, // MMX_PEXTRWirri >+ 135291952U, // MMX_PHADDSWrm64 >+ 34628656U, // MMX_PHADDSWrr64 >+ 135291701U, // MMX_PHADDWrm64 >+ 34628405U, // MMX_PHADDWrr64 >+ 135286670U, // MMX_PHADDrm64 >+ 34623374U, // MMX_PHADDrr64 >+ 135286611U, // MMX_PHSUBDrm64 >+ 34623315U, // MMX_PHSUBDrr64 >+ 135291933U, // MMX_PHSUBSWrm64 >+ 34628637U, // MMX_PHSUBSWrr64 >+ 135291647U, // MMX_PHSUBWrm64 >+ 34628351U, // MMX_PHSUBWrr64 >+ 2215666679U, // MMX_PINSRWirmi >+ 2182112247U, // MMX_PINSRWirri >+ 135291921U, // MMX_PMADDUBSWrm64 >+ 34628625U, // MMX_PMADDUBSWrr64 >+ 135288182U, // MMX_PMADDWDirm >+ 34624886U, // MMX_PMADDWDirr >+ 135292052U, // MMX_PMAXSWirm >+ 34628756U, // MMX_PMAXSWirr >+ 135286424U, // MMX_PMAXUBirm >+ 34623128U, // MMX_PMAXUBirr >+ 135291983U, // MMX_PMINSWirm >+ 34628687U, // MMX_PMINSWirr >+ 135286401U, // MMX_PMINUBirm >+ 34623105U, // MMX_PMINUBirr >+ 336612788U, // MMX_PMOVMSKBrr >+ 135292006U, // MMX_PMULHRSWrm64 >+ 34628710U, // MMX_PMULHRSWrr64 >+ 135292093U, // MMX_PMULHUWirm >+ 34628797U, // MMX_PMULHUWirr >+ 135291794U, // MMX_PMULHWirm >+ 34628498U, // MMX_PMULHWirr >+ 135291836U, // MMX_PMULLWirm >+ 34628540U, // MMX_PMULLWirr >+ 135289576U, // MMX_PMULUDQirm >+ 34626280U, // MMX_PMULUDQirr >+ 135289942U, // MMX_PORirm >+ 34626646U, // MMX_PORirr >+ 135291584U, // MMX_PSADBWirm >+ 34628288U, // MMX_PSADBWirr >+ 135286175U, // MMX_PSHUFBrm64 >+ 34622879U, // MMX_PSHUFBrr64 >+ 2517656428U, // MMX_PSHUFWmi >+ 2484101996U, // MMX_PSHUFWri >+ 135286223U, // MMX_PSIGNBrm64 >+ 34622927U, // MMX_PSIGNBrr64 >+ 135286869U, // MMX_PSIGNDrm64 >+ 34623573U, // MMX_PSIGNDrr64 >+ 135291861U, // MMX_PSIGNWrm64 >+ 34628565U, // MMX_PSIGNWrr64 >+ 34623508U, // MMX_PSLLDri >+ 135286804U, // MMX_PSLLDrm >+ 34623508U, // MMX_PSLLDrr >+ 34626336U, // MMX_PSLLQri >+ 135289632U, // MMX_PSLLQrm >+ 34626336U, // MMX_PSLLQrr >+ 34628532U, // MMX_PSLLWri >+ 135291828U, // MMX_PSLLWrm >+ 34628532U, // MMX_PSLLWrr >+ 34623286U, // MMX_PSRADri >+ 135286582U, // MMX_PSRADrm >+ 34623286U, // MMX_PSRADrr >+ 34628269U, // MMX_PSRAWri >+ 135291565U, // MMX_PSRAWrm >+ 34628269U, // MMX_PSRAWrr >+ 34623525U, // MMX_PSRLDri >+ 135286821U, // MMX_PSRLDrm >+ 34623525U, // MMX_PSRLDrr >+ 34626344U, // MMX_PSRLQri >+ 135289640U, // MMX_PSRLQrm >+ 34626344U, // MMX_PSRLQrr >+ 34628549U, // MMX_PSRLWri >+ 135291845U, // MMX_PSRLWrm >+ 34628549U, // MMX_PSRLWrr >+ 135286159U, // MMX_PSUBBirm >+ 34622863U, // MMX_PSUBBirr >+ 135286620U, // MMX_PSUBDirm >+ 34623324U, // MMX_PSUBDirr >+ 135289341U, // MMX_PSUBQirm >+ 34626045U, // MMX_PSUBQirr >+ 135286268U, // MMX_PSUBSBirm >+ 34622972U, // MMX_PSUBSBirr >+ 135291943U, // MMX_PSUBSWirm >+ 34628647U, // MMX_PSUBSWirr >+ 135286309U, // MMX_PSUBUSBirm >+ 34623013U, // MMX_PSUBUSBirr >+ 135292025U, // MMX_PSUBUSWirm >+ 34628729U, // MMX_PSUBUSWirr >+ 135291656U, // MMX_PSUBWirm >+ 34628360U, // MMX_PSUBWirr >+ 135291612U, // MMX_PUNPCKHBWirm >+ 34628316U, // MMX_PUNPCKHBWirr >+ 135289454U, // MMX_PUNPCKHDQirm >+ 34626158U, // MMX_PUNPCKHDQirr >+ 135288192U, // MMX_PUNPCKHWDirm >+ 34624896U, // MMX_PUNPCKHWDirr >+ 135291624U, // MMX_PUNPCKLBWirm >+ 34628328U, // MMX_PUNPCKLBWirr >+ 135289466U, // MMX_PUNPCKLDQirm >+ 34626170U, // MMX_PUNPCKLDQirr >+ 135288204U, // MMX_PUNPCKLWDirm >+ 34624908U, // MMX_PUNPCKLWDirr >+ 135289970U, // MMX_PXORirm >+ 34626674U, // MMX_PXORirr >+ 0U, // MONITOR >+ 11881U, // MONITORrrr >+ 11670U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 9970335U, // MOV16ao16 >+ 9970335U, // MOV16ao16_16 >+ 1090207U, // MOV16mi >+ 1090207U, // MOV16mr >+ 1090207U, // MOV16ms >+ 534276U, // MOV16o16a >+ 534276U, // MOV16o16a_16 >+ 336618143U, // MOV16ri >+ 336618143U, // MOV16ri_alt >+ 470835871U, // MOV16rm >+ 336618143U, // MOV16rr >+ 336618143U, // MOV16rr_REV >+ 336618143U, // MOV16rs >+ 470835871U, // MOV16sm >+ 336618143U, // MOV16sr >+ 11035295U, // MOV32ao32 >+ 11035295U, // MOV32ao32_16 >+ 336618143U, // MOV32cr >+ 336618143U, // MOV32dr >+ 1122975U, // MOV32mi >+ 1122975U, // MOV32mr >+ 1090207U, // MOV32ms >+ 550829U, // MOV32o32a >+ 550829U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 336618143U, // MOV32rc >+ 336618143U, // MOV32rd >+ 336618143U, // MOV32ri >+ 0U, // MOV32ri64 >+ 336618143U, // MOV32ri_alt >+ 303063711U, // MOV32rm >+ 336618143U, // MOV32rr >+ 336618143U, // MOV32rr_REV >+ 336618143U, // MOV32rs >+ 470835871U, // MOV32sm >+ 336618143U, // MOV32sr >+ 9968834U, // MOV64ao16 >+ 11033794U, // MOV64ao32 >+ 12098754U, // MOV64ao64 >+ 13163714U, // MOV64ao8 >+ 336618143U, // MOV64cr >+ 336618143U, // MOV64dr >+ 1139359U, // MOV64mi32 >+ 1139359U, // MOV64mr >+ 1090207U, // MOV64ms >+ 534254U, // MOV64o16a >+ 550805U, // MOV64o32a >+ 567328U, // MOV64o64a >+ 583294U, // MOV64o8a >+ 336618143U, // MOV64rc >+ 336618143U, // MOV64rd >+ 336616642U, // MOV64ri >+ 336618143U, // MOV64ri32 >+ 370172575U, // MOV64rm >+ 336618143U, // MOV64rr >+ 336618143U, // MOV64rr_REV >+ 336618143U, // MOV64rs >+ 470835871U, // MOV64sm >+ 336618143U, // MOV64sr >+ 336616415U, // MOV64toPQIrr >+ 370170847U, // MOV64toSDrm >+ 336616415U, // MOV64toSDrr >+ 13165215U, // MOV8ao8 >+ 13165215U, // MOV8ao8_16 >+ 1155743U, // MOV8mi >+ 1155743U, // MOV8mr >+ 1155743U, // MOV8mr_NOREX >+ 583316U, // MOV8o8a >+ 583316U, // MOV8o8a_16 >+ 336618143U, // MOV8ri >+ 336618143U, // MOV8ri_alt >+ 504390303U, // MOV8rm >+ 504390303U, // MOV8rm_NOREX >+ 336618143U, // MOV8rr >+ 336618143U, // MOV8rr_NOREX >+ 336618143U, // MOV8rr_REV >+ 1642899U, // MOVAPDmr >+ 537940371U, // MOVAPDrm >+ 336613779U, // MOVAPDrr >+ 336613779U, // MOVAPDrr_REV >+ 1646134U, // MOVAPSmr >+ 537943606U, // MOVAPSrm >+ 336617014U, // MOVAPSrr >+ 336617014U, // MOVAPSrr_REV >+ 1086989U, // MOVBE16mr >+ 470832653U, // MOVBE16rm >+ 1119757U, // MOVBE32mr >+ 303060493U, // MOVBE32rm >+ 1136141U, // MOVBE64mr >+ 370169357U, // MOVBE64rm >+ 571496857U, // MOVDDUPrm >+ 336615833U, // MOVDDUPrr >+ 303060308U, // MOVDI2PDIrm >+ 336614740U, // MOVDI2PDIrr >+ 303060308U, // MOVDI2SSrm >+ 336614740U, // MOVDI2SSrr >+ 1314120U, // MOVDQAmr >+ 437275976U, // MOVDQArm >+ 336612680U, // MOVDQArr >+ 336612680U, // MOVDQArr_REV >+ 1319533U, // MOVDQUmr >+ 437281389U, // MOVDQUrm >+ 336618093U, // MOVDQUrr >+ 336618093U, // MOVDQUrr_REV >+ 34627338U, // MOVHLPSrr >+ 1184337U, // MOVHPDmr >+ 235950673U, // MOVHPDrm >+ 1187574U, // MOVHPSmr >+ 235953910U, // MOVHPSrm >+ 34627308U, // MOVLHPSrr >+ 1184387U, // MOVLPDmr >+ 235950723U, // MOVLPDrm >+ 1187634U, // MOVLPSmr >+ 235953970U, // MOVLPSrm >+ 336613978U, // MOVMSKPDrr >+ 336617215U, // MOVMSKPSrr >+ 437275965U, // MOVNTDQArm >+ 1645267U, // MOVNTDQmr >+ 1136618U, // MOVNTI_64mr >+ 1120234U, // MOVNTImr >+ 1643224U, // MOVNTPDmr >+ 1646483U, // MOVNTPSmr >+ 1184933U, // MOVNTSD >+ 1171767U, // MOVNTSS >+ 0U, // MOVPC32r >+ 1119572U, // MOVPDI2DImr >+ 336614740U, // MOVPDI2DIrr >+ 1137631U, // MOVPQI2QImr >+ 336616415U, // MOVPQI2QIrr >+ 336616415U, // MOVPQIto64rr >+ 370170847U, // MOVQI2PQIrm >+ 672435777U, // MOVSB >+ 1184974U, // MOVSDmr >+ 571495630U, // MOVSDrm >+ 34624718U, // MOVSDrr >+ 34624718U, // MOVSDrr_REV >+ 1137631U, // MOVSDto64mr >+ 336616415U, // MOVSDto64rr >+ 537942435U, // MOVSHDUPrm >+ 336615843U, // MOVSHDUPrr >+ 706008270U, // MOVSL >+ 537942446U, // MOVSLDUPrm >+ 336615854U, // MOVSLDUPrr >+ 739859325U, // MOVSQ >+ 1119572U, // MOVSS2DImr >+ 336614740U, // MOVSS2DIrr >+ 1171818U, // MOVSSmr >+ 605053290U, // MOVSSrm >+ 34627946U, // MOVSSrr >+ 34627946U, // MOVSSrr_REV >+ 773137548U, // MOVSW >+ 504391001U, // MOVSX16rm8 >+ 336618841U, // MOVSX16rr8 >+ 470836569U, // MOVSX32rm16 >+ 504391001U, // MOVSX32rm8 >+ 336618841U, // MOVSX32rr16 >+ 336618841U, // MOVSX32rr8 >+ 336614884U, // MOVSX64_NOREXrr32 >+ 470836569U, // MOVSX64rm16 >+ 303060452U, // MOVSX64rm32 >+ 504391001U, // MOVSX64rm8 >+ 336618841U, // MOVSX64rr16 >+ 336614884U, // MOVSX64rr32 >+ 336618841U, // MOVSX64rr8 >+ 1643252U, // MOVUPDmr >+ 537940724U, // MOVUPDrm >+ 336614132U, // MOVUPDrr >+ 336614132U, // MOVUPDrr_REV >+ 1646532U, // MOVUPSmr >+ 537944004U, // MOVUPSrm >+ 336617412U, // MOVUPSrr >+ 336617412U, // MOVUPSrr_REV >+ 437279711U, // MOVZPQILo2PQIrm >+ 336616415U, // MOVZPQILo2PQIrr >+ 370170847U, // MOVZQI2PQIrm >+ 336616415U, // MOVZQI2PQIrr >+ 504391008U, // MOVZX16rm8 >+ 336618848U, // MOVZX16rr8 >+ 504391008U, // MOVZX32_NOREXrm8 >+ 336618848U, // MOVZX32_NOREXrr8 >+ 470836576U, // MOVZX32rm16 >+ 504391008U, // MOVZX32rm8 >+ 336618848U, // MOVZX32rr16 >+ 336618848U, // MOVZX32rr8 >+ 470836576U, // MOVZX64rm16_Q >+ 504391008U, // MOVZX64rm8_Q >+ 336618848U, // MOVZX64rr16_Q >+ 336618848U, // MOVZX64rr8_Q >+ 2551210687U, // MPSADBWrmi >+ 2182111935U, // MPSADBWrri >+ 39012U, // MUL16m >+ 22628U, // MUL16r >+ 71780U, // MUL32m >+ 22628U, // MUL32r >+ 88164U, // MUL64m >+ 22628U, // MUL64r >+ 104548U, // MUL8m >+ 22628U, // MUL8r >+ 202396283U, // MULPDrm >+ 34624123U, // MULPDrr >+ 202399530U, // MULPSrm >+ 34627370U, // MULPSrr >+ 235951230U, // MULSDrm >+ 235951230U, // MULSDrm_Int >+ 34624638U, // MULSDrr >+ 34624638U, // MULSDrr_Int >+ 269508888U, // MULSSrm >+ 269508888U, // MULSSrm_Int >+ 34627864U, // MULSSrr >+ 34627864U, // MULSSrr_Int >+ 2484102422U, // MULX32rm >+ 2484102422U, // MULX32rr >+ 2484102422U, // MULX64rm >+ 2484102422U, // MULX64rr >+ 120931U, // MUL_F32m >+ 137315U, // MUL_F64m >+ 39017U, // MUL_FI16m >+ 71785U, // MUL_FI32m >+ 22809U, // MUL_FPrST0 >+ 22627U, // MUL_FST0r >+ 0U, // MUL_Fp32 >+ 0U, // MUL_Fp32m >+ 0U, // MUL_Fp64 >+ 0U, // MUL_Fp64m >+ 0U, // MUL_Fp64m32 >+ 0U, // MUL_Fp80 >+ 0U, // MUL_Fp80m32 >+ 0U, // MUL_Fp80m64 >+ 0U, // MUL_FpI16m32 >+ 0U, // MUL_FpI16m64 >+ 0U, // MUL_FpI16m80 >+ 0U, // MUL_FpI32m32 >+ 0U, // MUL_FpI32m64 >+ 0U, // MUL_FpI32m80 >+ 2119779U, // MUL_FrST0 >+ 12121U, // MWAITrr >+ 38624U, // NEG16m >+ 22240U, // NEG16r >+ 71392U, // NEG32m >+ 22240U, // NEG32r >+ 87776U, // NEG64m >+ 22240U, // NEG64r >+ 104160U, // NEG8m >+ 22240U, // NEG8r >+ 11777U, // NOOP >+ 39254U, // NOOP18_16m4 >+ 39254U, // NOOP18_16m5 >+ 39254U, // NOOP18_16m6 >+ 39254U, // NOOP18_16m7 >+ 22870U, // NOOP18_16r4 >+ 22870U, // NOOP18_16r5 >+ 22870U, // NOOP18_16r6 >+ 22870U, // NOOP18_16r7 >+ 72022U, // NOOP18_m4 >+ 72022U, // NOOP18_m5 >+ 72022U, // NOOP18_m6 >+ 72022U, // NOOP18_m7 >+ 22870U, // NOOP18_r4 >+ 22870U, // NOOP18_r5 >+ 22870U, // NOOP18_r6 >+ 22870U, // NOOP18_r7 >+ 806410582U, // NOOP19rr >+ 72022U, // NOOPL >+ 72022U, // NOOPL_19 >+ 72022U, // NOOPL_1a >+ 72022U, // NOOPL_1b >+ 72022U, // NOOPL_1c >+ 72022U, // NOOPL_1d >+ 72022U, // NOOPL_1e >+ 39254U, // NOOPW >+ 39254U, // NOOPW_19 >+ 39254U, // NOOPW_1a >+ 39254U, // NOOPW_1b >+ 39254U, // NOOPW_1c >+ 39254U, // NOOPW_1d >+ 39254U, // NOOPW_1e >+ 41445U, // NOT16m >+ 25061U, // NOT16r >+ 74213U, // NOT32m >+ 25061U, // NOT32r >+ 90597U, // NOT64m >+ 25061U, // NOT64r >+ 106981U, // NOT8m >+ 25061U, // NOT8r >+ 26342U, // OR16i16 >+ 1088599U, // OR16mi >+ 1088599U, // OR16mi8 >+ 1088599U, // OR16mr >+ 34659415U, // OR16ri >+ 34659415U, // OR16ri8 >+ 68213847U, // OR16rm >+ 34659415U, // OR16rr >+ 34626647U, // OR16rr_REV >+ 26508U, // OR32i32 >+ 1121367U, // OR32mi >+ 1121367U, // OR32mi8 >+ 1121367U, // OR32mr >+ 1121367U, // OR32mrLocked >+ 34659415U, // OR32ri >+ 34659415U, // OR32ri8 >+ 101768279U, // OR32rm >+ 34659415U, // OR32rr >+ 34626647U, // OR32rr_REV >+ 26647U, // OR64i32 >+ 1137751U, // OR64mi32 >+ 1137751U, // OR64mi8 >+ 1137751U, // OR64mr >+ 34659415U, // OR64ri32 >+ 34659415U, // OR64ri8 >+ 135322711U, // OR64rm >+ 34659415U, // OR64rr >+ 34626647U, // OR64rr_REV >+ 26230U, // OR8i8 >+ 1154135U, // OR8mi >+ 1154135U, // OR8mr >+ 34659415U, // OR8ri >+ 34659415U, // OR8ri8 >+ 168877143U, // OR8rm >+ 34659415U, // OR8rr >+ 34626647U, // OR8rr_REV >+ 202396361U, // ORPDrm >+ 34624201U, // ORPDrr >+ 202399608U, // ORPSrm >+ 34627448U, // ORPSrr >+ 9462357U, // OUT16ir >+ 12244U, // OUT16rr >+ 10510933U, // OUT32ir >+ 12298U, // OUT32rr >+ 12608085U, // OUT8ir >+ 11614U, // OUT8rr >+ 403512U, // OUTSB >+ 419907U, // OUTSL >+ 452686U, // OUTSW >+ 437276148U, // PABSBrm128 >+ 336612852U, // PABSBrr128 >+ 437277727U, // PABSDrm128 >+ 336614431U, // PABSDrr128 >+ 437281801U, // PABSWrm128 >+ 336618505U, // PABSWrr128 >+ 403727184U, // PACKSSDWrm >+ 34628432U, // PACKSSDWrr >+ 403721907U, // PACKSSWBrm >+ 34623155U, // PACKSSWBrr >+ 403727195U, // PACKUSDWrm >+ 34628443U, // PACKUSDWrr >+ 403721918U, // PACKUSWBrm >+ 34623166U, // PACKUSWBrr >+ 403721623U, // PADDBrm >+ 34622871U, // PADDBrr >+ 403722135U, // PADDDrm >+ 34623383U, // PADDDrr >+ 403724892U, // PADDQrm >+ 34626140U, // PADDQrr >+ 403721733U, // PADDSBrm >+ 34622981U, // PADDSBrr >+ 403727418U, // PADDSWrm >+ 34628666U, // PADDSWrr >+ 403721775U, // PADDUSBrm >+ 34623023U, // PADDUSBrr >+ 403727491U, // PADDUSWrm >+ 34628739U, // PADDUSWrr >+ 403727166U, // PADDWrm >+ 34628414U, // PADDWrr >+ 2551209036U, // PALIGNR128rm >+ 2182110284U, // PALIGNR128rr >+ 403724465U, // PANDNrm >+ 34625713U, // PANDNrr >+ 403722310U, // PANDrm >+ 34623558U, // PANDrr >+ 11485U, // PAUSE >+ 403721640U, // PAVGBrm >+ 34622888U, // PAVGBrr >+ 135286328U, // PAVGUSBrm >+ 34623032U, // PAVGUSBrr >+ 403727221U, // PAVGWrm >+ 34628469U, // PAVGWrr >+ 403721889U, // PBLENDVBrm0 >+ 34623137U, // PBLENDVBrr0 >+ 2551210822U, // PBLENDWrmi >+ 2182112070U, // PBLENDWrri >+ 2551208635U, // PCLMULQDQrm >+ 2182109883U, // PCLMULQDQrr >+ 403721688U, // PCMPEQBrm >+ 34622936U, // PCMPEQBrr >+ 403723053U, // PCMPEQDrm >+ 34624301U, // PCMPEQDrr >+ 403725128U, // PCMPEQQrm >+ 34626376U, // PCMPEQQrr >+ 403727326U, // PCMPEQWrm >+ 34628574U, // PCMPEQWrr >+ 0U, // PCMPESTRIMEM >+ 0U, // PCMPESTRIREG >+ 2584762271U, // PCMPESTRIrm >+ 2484098975U, // PCMPESTRIrr >+ 0U, // PCMPESTRM128MEM >+ 0U, // PCMPESTRM128REG >+ 2584762521U, // PCMPESTRM128rm >+ 2484099225U, // PCMPESTRM128rr >+ 403721816U, // PCMPGTBrm >+ 34623064U, // PCMPGTBrr >+ 403723504U, // PCMPGTDrm >+ 34624752U, // PCMPGTDrr >+ 403725189U, // PCMPGTQrm >+ 34626437U, // PCMPGTQrr >+ 403727517U, // PCMPGTWrm >+ 34628765U, // PCMPGTWrr >+ 0U, // PCMPISTRIMEM >+ 0U, // PCMPISTRIREG >+ 2584762283U, // PCMPISTRIrm >+ 2484098987U, // PCMPISTRIrr >+ 0U, // PCMPISTRM128MEM >+ 0U, // PCMPISTRM128REG >+ 2584762533U, // PCMPISTRM128rm >+ 2484099237U, // PCMPISTRM128rr >+ 2484099343U, // PDEP32rm >+ 2484099343U, // PDEP32rr >+ 2484099343U, // PDEP64rm >+ 2484099343U, // PDEP64rr >+ 2484101722U, // PEXT32rm >+ 2484101722U, // PEXT32rr >+ 2484101722U, // PEXT64rm >+ 2484101722U, // PEXT64rr >+ 2148634091U, // PEXTRBmr >+ 2484096491U, // PEXTRBrr >+ 2148602706U, // PEXTRDmr >+ 2484097874U, // PEXTRDrr >+ 2148621159U, // PEXTRQmr >+ 2484099943U, // PEXTRQrr >+ 2148574208U, // PEXTRWmr >+ 2484102144U, // PEXTRWri >+ 2484102144U, // PEXTRWrr_REV >+ 370167777U, // PF2IDrm >+ 336613345U, // PF2IDrr >+ 370172826U, // PF2IWrm >+ 336618394U, // PF2IWrr >+ 135286472U, // PFACCrm >+ 34623176U, // PFACCrr >+ 135286649U, // PFADDrm >+ 34623353U, // PFADDrr >+ 135289607U, // PFCMPEQrm >+ 34626311U, // PFCMPEQrr >+ 135288361U, // PFCMPGErm >+ 34625065U, // PFCMPGErr >+ 135291329U, // PFCMPGTrm >+ 34628033U, // PFCMPGTrr >+ 135292163U, // PFMAXrm >+ 34628867U, // PFMAXrr >+ 135289024U, // PFMINrm >+ 34625728U, // PFMINrr >+ 135288930U, // PFMULrm >+ 34625634U, // PFMULrr >+ 135286479U, // PFNACCrm >+ 34623183U, // PFNACCrr >+ 135286487U, // PFPNACCrm >+ 34623191U, // PFPNACCrr >+ 135285648U, // PFRCPIT1rm >+ 34622352U, // PFRCPIT1rr >+ 135285744U, // PFRCPIT2rm >+ 34622448U, // PFRCPIT2rr >+ 370170113U, // PFRCPrm >+ 336615681U, // PFRCPrr >+ 135285658U, // PFRSQIT1rm >+ 34622362U, // PFRSQIT1rr >+ 370172420U, // PFRSQRTrm >+ 336617988U, // PFRSQRTrr >+ 135289898U, // PFSUBRrm >+ 34626602U, // PFSUBRrr >+ 135286409U, // PFSUBrm >+ 34623113U, // PFSUBrr >+ 403722126U, // PHADDDrm >+ 34623374U, // PHADDDrr >+ 403727408U, // PHADDSWrm128 >+ 34628656U, // PHADDSWrr128 >+ 403727157U, // PHADDWrm >+ 34628405U, // PHADDWrr >+ 437282009U, // PHMINPOSUWrm128 >+ 336618713U, // PHMINPOSUWrr128 >+ 403722067U, // PHSUBDrm >+ 34623315U, // PHSUBDrr >+ 403727389U, // PHSUBSWrm128 >+ 34628637U, // PHSUBSWrr128 >+ 403727103U, // PHSUBWrm >+ 34628351U, // PHSUBWrr >+ 370167761U, // PI2FDrm >+ 336613329U, // PI2FDrr >+ 370172773U, // PI2FWrm >+ 336618341U, // PI2FWrr >+ 2316324322U, // PINSRBrm >+ 2182106594U, // PINSRBrr >+ 2249216841U, // PINSRDrm >+ 2182107977U, // PINSRDrr >+ 2282773342U, // PINSRQrm >+ 2182110046U, // PINSRQrr >+ 2215666679U, // PINSRWrmi >+ 2182112247U, // PINSRWrri >+ 403727377U, // PMADDUBSWrm128 >+ 34628625U, // PMADDUBSWrr128 >+ 403723638U, // PMADDWDrm >+ 34624886U, // PMADDWDrr >+ 403721801U, // PMAXSBrm >+ 34623049U, // PMAXSBrr >+ 403723478U, // PMAXSDrm >+ 34624726U, // PMAXSDrr >+ 403727508U, // PMAXSWrm >+ 34628756U, // PMAXSWrr >+ 403721880U, // PMAXUBrm >+ 34623128U, // PMAXUBrr >+ 403723563U, // PMAXUDrm >+ 34624811U, // PMAXUDrr >+ 403727590U, // PMAXUWrm >+ 34628838U, // PMAXUWrr >+ 403721742U, // PMINSBrm >+ 34622990U, // PMINSBrr >+ 403723398U, // PMINSDrm >+ 34624646U, // PMINSDrr >+ 403727439U, // PMINSWrm >+ 34628687U, // PMINSWrr >+ 403721857U, // PMINUBrm >+ 34623105U, // PMINUBrr >+ 403723545U, // PMINUDrm >+ 34624793U, // PMINUDrr >+ 403727568U, // PMINUWrm >+ 34628816U, // PMINUWrr >+ 336612788U, // PMOVMSKBrr >+ 303058788U, // PMOVSXBDrm >+ 336613220U, // PMOVSXBDrr >+ 470833669U, // PMOVSXBQrm >+ 336615941U, // PMOVSXBQrr >+ 370172688U, // PMOVSXBWrm >+ 336618256U, // PMOVSXBWrr >+ 370170610U, // PMOVSXDQrm >+ 336616178U, // PMOVSXDQrr >+ 370169295U, // PMOVSXWDrm >+ 336614863U, // PMOVSXWDrr >+ 303062018U, // PMOVSXWQrm >+ 336616450U, // PMOVSXWQrr >+ 303058799U, // PMOVZXBDrm >+ 336613231U, // PMOVZXBDrr >+ 470833680U, // PMOVZXBQrm >+ 336615952U, // PMOVZXBQrr >+ 370172699U, // PMOVZXBWrm >+ 336618267U, // PMOVZXBWrr >+ 370170621U, // PMOVZXDQrm >+ 336616189U, // PMOVZXDQrr >+ 370169306U, // PMOVZXWDrm >+ 336614874U, // PMOVZXWDrr >+ 303062029U, // PMOVZXWQrm >+ 336616461U, // PMOVZXWQrr >+ 403724952U, // PMULDQrm >+ 34626200U, // PMULDQrr >+ 403727462U, // PMULHRSWrm128 >+ 34628710U, // PMULHRSWrr128 >+ 135291885U, // PMULHRWrm >+ 34628589U, // PMULHRWrr >+ 403727549U, // PMULHUWrm >+ 34628797U, // PMULHUWrr >+ 403727250U, // PMULHWrm >+ 34628498U, // PMULHWrr >+ 403722268U, // PMULLDrm >+ 34623516U, // PMULLDrr >+ 403727292U, // PMULLWrm >+ 34628540U, // PMULLWrr >+ 403725032U, // PMULUDQrm >+ 34626280U, // PMULUDQrr >+ 22881U, // POP16r >+ 39265U, // POP16rmm >+ 22881U, // POP16rmr >+ 22881U, // POP32r >+ 72033U, // POP32rmm >+ 22881U, // POP32rmr >+ 22881U, // POP64r >+ 88417U, // POP64rmm >+ 22881U, // POP64rmr >+ 12198U, // POPA16 >+ 11632U, // POPA32 >+ 470835658U, // POPCNT16rm >+ 336617930U, // POPCNT16rr >+ 303063498U, // POPCNT32rm >+ 336617930U, // POPCNT32rr >+ 370172362U, // POPCNT64rm >+ 336617930U, // POPCNT64rr >+ 11940U, // POPDS16 >+ 11940U, // POPDS32 >+ 11955U, // POPES16 >+ 11955U, // POPES32 >+ 11551U, // POPF16 >+ 11338U, // POPF32 >+ 11823U, // POPF64 >+ 11970U, // POPFS16 >+ 11970U, // POPFS32 >+ 11970U, // POPFS64 >+ 11985U, // POPGS16 >+ 11985U, // POPGS32 >+ 11985U, // POPGS64 >+ 12082U, // POPSS16 >+ 12082U, // POPSS32 >+ 403725398U, // PORrm >+ 34626646U, // PORrr >+ 104199U, // PREFETCH >+ 101718U, // PREFETCHNTA >+ 101218U, // PREFETCHT0 >+ 101252U, // PREFETCHT1 >+ 101348U, // PREFETCHT2 >+ 107388U, // PREFETCHW >+ 403727040U, // PSADBWrm >+ 34628288U, // PSADBWrr >+ 403721631U, // PSHUFBrm >+ 34622879U, // PSHUFBrr >+ 2584760281U, // PSHUFDmi >+ 2484096985U, // PSHUFDri >+ 2584765320U, // PSHUFHWmi >+ 2484102024U, // PSHUFHWri >+ 2584765346U, // PSHUFLWmi >+ 2484102050U, // PSHUFLWri >+ 403721679U, // PSIGNBrm >+ 34622927U, // PSIGNBrr >+ 403722325U, // PSIGNDrm >+ 34623573U, // PSIGNDrr >+ 403727317U, // PSIGNWrm >+ 34628565U, // PSIGNWrr >+ 34626182U, // PSLLDQri >+ 34623508U, // PSLLDri >+ 403722260U, // PSLLDrm >+ 34623508U, // PSLLDrr >+ 34626336U, // PSLLQri >+ 403725088U, // PSLLQrm >+ 34626336U, // PSLLQrr >+ 34628532U, // PSLLWri >+ 403727284U, // PSLLWrm >+ 34628532U, // PSLLWrr >+ 34623286U, // PSRADri >+ 403722038U, // PSRADrm >+ 34623286U, // PSRADrr >+ 34628269U, // PSRAWri >+ 403727021U, // PSRAWrm >+ 34628269U, // PSRAWrr >+ 34626191U, // PSRLDQri >+ 34623525U, // PSRLDri >+ 403722277U, // PSRLDrm >+ 34623525U, // PSRLDrr >+ 34626344U, // PSRLQri >+ 403725096U, // PSRLQrm >+ 34626344U, // PSRLQrr >+ 34628549U, // PSRLWri >+ 403727301U, // PSRLWrm >+ 34628549U, // PSRLWrr >+ 403721615U, // PSUBBrm >+ 34622863U, // PSUBBrr >+ 403722076U, // PSUBDrm >+ 34623324U, // PSUBDrr >+ 403724797U, // PSUBQrm >+ 34626045U, // PSUBQrr >+ 403721724U, // PSUBSBrm >+ 34622972U, // PSUBSBrr >+ 403727399U, // PSUBSWrm >+ 34628647U, // PSUBSWrr >+ 403721765U, // PSUBUSBrm >+ 34623013U, // PSUBUSBrr >+ 403727481U, // PSUBUSWrm >+ 34628729U, // PSUBUSWrr >+ 403727112U, // PSUBWrm >+ 34628360U, // PSUBWrr >+ 370168219U, // PSWAPDrm >+ 336613787U, // PSWAPDrr >+ 537944616U, // PTESTrm >+ 336618024U, // PTESTrr >+ 403727068U, // PUNPCKHBWrm >+ 34628316U, // PUNPCKHBWrr >+ 403724910U, // PUNPCKHDQrm >+ 34626158U, // PUNPCKHDQrr >+ 403724961U, // PUNPCKHQDQrm >+ 34626209U, // PUNPCKHQDQrr >+ 403723648U, // PUNPCKHWDrm >+ 34624896U, // PUNPCKHWDrr >+ 403727080U, // PUNPCKLBWrm >+ 34628328U, // PUNPCKLBWrr >+ 403724922U, // PUNPCKLDQrm >+ 34626170U, // PUNPCKLDQrr >+ 403724974U, // PUNPCKLQDQrm >+ 34626222U, // PUNPCKLQDQrr >+ 403723660U, // PUNPCKLWDrm >+ 34624908U, // PUNPCKLWDrr >+ 22338U, // PUSH16i8 >+ 22338U, // PUSH16r >+ 38722U, // PUSH16rmm >+ 22338U, // PUSH16rmr >+ 22338U, // PUSH32i8 >+ 22338U, // PUSH32r >+ 71490U, // PUSH32rmm >+ 22338U, // PUSH32rmr >+ 22338U, // PUSH64i16 >+ 22338U, // PUSH64i32 >+ 22338U, // PUSH64i8 >+ 22338U, // PUSH64r >+ 87874U, // PUSH64rmm >+ 22338U, // PUSH64rmr >+ 12191U, // PUSHA16 >+ 11625U, // PUSHA32 >+ 11924U, // PUSHCS16 >+ 11924U, // PUSHCS32 >+ 11932U, // PUSHDS16 >+ 11932U, // PUSHDS32 >+ 11947U, // PUSHES16 >+ 11947U, // PUSHES32 >+ 11545U, // PUSHF16 >+ 11331U, // PUSHF32 >+ 11816U, // PUSHF64 >+ 11962U, // PUSHFS16 >+ 11962U, // PUSHFS32 >+ 11962U, // PUSHFS64 >+ 11977U, // PUSHGS16 >+ 11977U, // PUSHGS32 >+ 11977U, // PUSHGS64 >+ 12074U, // PUSHSS16 >+ 12074U, // PUSHSS32 >+ 22338U, // PUSHi16 >+ 22338U, // PUSHi32 >+ 403725426U, // PXORrm >+ 34626674U, // PXORrr >+ 13670414U, // RCL16m1 >+ 14718990U, // RCL16mCL >+ 1087502U, // RCL16mi >+ 13654030U, // RCL16r1 >+ 14702606U, // RCL16rCL >+ 34625550U, // RCL16ri >+ 13703182U, // RCL32m1 >+ 14751758U, // RCL32mCL >+ 1120270U, // RCL32mi >+ 13654030U, // RCL32r1 >+ 14702606U, // RCL32rCL >+ 34625550U, // RCL32ri >+ 13719566U, // RCL64m1 >+ 14768142U, // RCL64mCL >+ 1136654U, // RCL64mi >+ 13654030U, // RCL64r1 >+ 14702606U, // RCL64rCL >+ 34625550U, // RCL64ri >+ 13735950U, // RCL8m1 >+ 14784526U, // RCL8mCL >+ 1153038U, // RCL8mi >+ 13654030U, // RCL8r1 >+ 14702606U, // RCL8rCL >+ 34625550U, // RCL8ri >+ 537943893U, // RCPPSm >+ 537943893U, // RCPPSm_Int >+ 336617301U, // RCPPSr >+ 336617301U, // RCPPSr_Int >+ 605053224U, // RCPSSm >+ 269508904U, // RCPSSm_Int >+ 336617768U, // RCPSSr >+ 34627880U, // RCPSSr_Int >+ 13671482U, // RCR16m1 >+ 14720058U, // RCR16mCL >+ 1088570U, // RCR16mi >+ 13655098U, // RCR16r1 >+ 14703674U, // RCR16rCL >+ 34626618U, // RCR16ri >+ 13704250U, // RCR32m1 >+ 14752826U, // RCR32mCL >+ 1121338U, // RCR32mi >+ 13655098U, // RCR32r1 >+ 14703674U, // RCR32rCL >+ 34626618U, // RCR32ri >+ 13720634U, // RCR64m1 >+ 14769210U, // RCR64mCL >+ 1137722U, // RCR64mi >+ 13655098U, // RCR64r1 >+ 14703674U, // RCR64rCL >+ 34626618U, // RCR64ri >+ 13737018U, // RCR8m1 >+ 14785594U, // RCR8mCL >+ 1154106U, // RCR8mi >+ 13655098U, // RCR8r1 >+ 14703674U, // RCR8rCL >+ 34626618U, // RCR8ri >+ 22140U, // RDFSBASE >+ 22140U, // RDFSBASE64 >+ 22160U, // RDGSBASE >+ 22160U, // RDGSBASE64 >+ 11889U, // RDMSR >+ 11308U, // RDPMC >+ 20556U, // RDRAND16r >+ 20556U, // RDRAND32r >+ 20556U, // RDRAND64r >+ 20425U, // RDSEED16r >+ 20425U, // RDSEED32r >+ 20425U, // RDSEED64r >+ 11321U, // RDTSC >+ 11754U, // RDTSCP >+ 10835U, // RELEASE_MOV16mr >+ 10835U, // RELEASE_MOV32mr >+ 10835U, // RELEASE_MOV64mr >+ 10835U, // RELEASE_MOV8mr >+ 11449U, // REPNE_PREFIX >+ 11252U, // REP_MOVSB_32 >+ 11252U, // REP_MOVSB_64 >+ 11369U, // REP_MOVSD_32 >+ 11369U, // REP_MOVSD_64 >+ 11845U, // REP_MOVSQ_64 >+ 12218U, // REP_MOVSW_32 >+ 12218U, // REP_MOVSW_64 >+ 11761U, // REP_PREFIX >+ 11242U, // REP_STOSB_32 >+ 11242U, // REP_STOSB_64 >+ 11359U, // REP_STOSD_32 >+ 11359U, // REP_STOSD_64 >+ 11835U, // REP_STOSQ_64 >+ 12208U, // REP_STOSW_32 >+ 12208U, // REP_STOSW_64 >+ 25020U, // RETIL >+ 25020U, // RETIQ >+ 25020U, // RETIW >+ 12110U, // RETL >+ 12110U, // RETQ >+ 12110U, // RETW >+ 11078U, // REX64_PREFIX >+ 13670453U, // ROL16m1 >+ 14719029U, // ROL16mCL >+ 1087541U, // ROL16mi >+ 13654069U, // ROL16r1 >+ 14702645U, // ROL16rCL >+ 34625589U, // ROL16ri >+ 13703221U, // ROL32m1 >+ 14751797U, // ROL32mCL >+ 1120309U, // ROL32mi >+ 13654069U, // ROL32r1 >+ 14702645U, // ROL32rCL >+ 34625589U, // ROL32ri >+ 13719605U, // ROL64m1 >+ 14768181U, // ROL64mCL >+ 1136693U, // ROL64mi >+ 13654069U, // ROL64r1 >+ 14702645U, // ROL64rCL >+ 34625589U, // ROL64ri >+ 13735989U, // ROL8m1 >+ 14784565U, // ROL8mCL >+ 1153077U, // ROL8mi >+ 13654069U, // ROL8r1 >+ 14702645U, // ROL8rCL >+ 34625589U, // ROL8ri >+ 13671515U, // ROR16m1 >+ 14720091U, // ROR16mCL >+ 1088603U, // ROR16mi >+ 13655131U, // ROR16r1 >+ 14703707U, // ROR16rCL >+ 34626651U, // ROR16ri >+ 13704283U, // ROR32m1 >+ 14752859U, // ROR32mCL >+ 1121371U, // ROR32mi >+ 13655131U, // ROR32r1 >+ 14703707U, // ROR32rCL >+ 34626651U, // ROR32ri >+ 13720667U, // ROR64m1 >+ 14769243U, // ROR64mCL >+ 1137755U, // ROR64mi >+ 13655131U, // ROR64r1 >+ 14703707U, // ROR64rCL >+ 34626651U, // ROR64ri >+ 13737051U, // ROR8m1 >+ 14785627U, // ROR8mCL >+ 1154139U, // ROR8mi >+ 13655131U, // ROR8r1 >+ 14703707U, // ROR8rCL >+ 34626651U, // ROR8ri >+ 2450548039U, // RORX32mi >+ 2484102471U, // RORX32ri >+ 2517656903U, // RORX64mi >+ 2484102471U, // RORX64ri >+ 2685424167U, // ROUNDPDm >+ 2484097575U, // ROUNDPDr >+ 2685427394U, // ROUNDPSm >+ 2484100802U, // ROUNDPSr >+ 2383434849U, // ROUNDSDm >+ 2182108257U, // ROUNDSDr >+ 2182108257U, // ROUNDSDr_Int >+ 2416992507U, // ROUNDSSm >+ 2182111483U, // ROUNDSSr >+ 2182111483U, // ROUNDSSr_Int >+ 11696U, // RSM >+ 537943976U, // RSQRTPSm >+ 537943976U, // RSQRTPSm_Int >+ 336617384U, // RSQRTPSr >+ 336617384U, // RSQRTPSr_Int >+ 605053249U, // RSQRTSSm >+ 269508929U, // RSQRTSSm_Int >+ 336617793U, // RSQRTSSr >+ 34627905U, // RSQRTSSr_Int >+ 11540U, // SAHF >+ 13670409U, // SAL16m1 >+ 14718985U, // SAL16mCL >+ 1087497U, // SAL16mi >+ 13654025U, // SAL16r1 >+ 14702601U, // SAL16rCL >+ 34625545U, // SAL16ri >+ 13703177U, // SAL32m1 >+ 14751753U, // SAL32mCL >+ 1120265U, // SAL32mi >+ 13654025U, // SAL32r1 >+ 14702601U, // SAL32rCL >+ 34625545U, // SAL32ri >+ 13719561U, // SAL64m1 >+ 14768137U, // SAL64mCL >+ 1136649U, // SAL64mi >+ 13654025U, // SAL64r1 >+ 14702601U, // SAL64rCL >+ 34625545U, // SAL64ri >+ 13735945U, // SAL8m1 >+ 14784521U, // SAL8mCL >+ 1153033U, // SAL8mi >+ 13654025U, // SAL8r1 >+ 14702601U, // SAL8rCL >+ 34625545U, // SAL8ri >+ 11295U, // SALC >+ 13671461U, // SAR16m1 >+ 14720037U, // SAR16mCL >+ 1088549U, // SAR16mi >+ 13655077U, // SAR16r1 >+ 14703653U, // SAR16rCL >+ 34626597U, // SAR16ri >+ 13704229U, // SAR32m1 >+ 14752805U, // SAR32mCL >+ 1121317U, // SAR32mi >+ 13655077U, // SAR32r1 >+ 14703653U, // SAR32rCL >+ 34626597U, // SAR32ri >+ 13720613U, // SAR64m1 >+ 14769189U, // SAR64mCL >+ 1137701U, // SAR64mi >+ 13655077U, // SAR64r1 >+ 14703653U, // SAR64rCL >+ 34626597U, // SAR64ri >+ 13736997U, // SAR8m1 >+ 14785573U, // SAR8mCL >+ 1154085U, // SAR8mi >+ 13655077U, // SAR8r1 >+ 14703653U, // SAR8rCL >+ 34626597U, // SAR8ri >+ 2450548027U, // SARX32rm >+ 2484102459U, // SARX32rr >+ 2517656891U, // SARX64rm >+ 2484102459U, // SARX64rr >+ 26269U, // SBB16i16 >+ 1084809U, // SBB16mi >+ 1084809U, // SBB16mi8 >+ 1084809U, // SBB16mr >+ 34655625U, // SBB16ri >+ 34655625U, // SBB16ri8 >+ 68210057U, // SBB16rm >+ 34655625U, // SBB16rr >+ 34622857U, // SBB16rr_REV >+ 26403U, // SBB32i32 >+ 1117577U, // SBB32mi >+ 1117577U, // SBB32mi8 >+ 1117577U, // SBB32mr >+ 34655625U, // SBB32ri >+ 34655625U, // SBB32ri8 >+ 101764489U, // SBB32rm >+ 34655625U, // SBB32rr >+ 34622857U, // SBB32rr_REV >+ 26551U, // SBB64i32 >+ 1133961U, // SBB64mi32 >+ 1133961U, // SBB64mi8 >+ 1133961U, // SBB64mr >+ 34655625U, // SBB64ri32 >+ 34655625U, // SBB64ri8 >+ 135318921U, // SBB64rm >+ 34655625U, // SBB64rr >+ 34622857U, // SBB64rr_REV >+ 26145U, // SBB8i8 >+ 1150345U, // SBB8mi >+ 1150345U, // SBB8mr >+ 34655625U, // SBB8ri >+ 168873353U, // SBB8rm >+ 34655625U, // SBB8rr >+ 34622857U, // SBB8rr_REV >+ 304682U, // SCASB >+ 321365U, // SCASL >+ 616446U, // SCASQ >+ 337677U, // SCASW >+ 12004U, // SEG_ALLOCA_32 >+ 12004U, // SEG_ALLOCA_64 >+ 11505U, // SEH_EndPrologue >+ 11491U, // SEH_Epilogue >+ 26802U, // SEH_PushFrame >+ 26847U, // SEH_PushReg >+ 336619729U, // SEH_SaveReg >+ 336619643U, // SEH_SaveXMM >+ 336619714U, // SEH_SetFrame >+ 26785U, // SEH_StackAlloc >+ 103921U, // SETAEm >+ 22001U, // SETAEr >+ 101712U, // SETAm >+ 19792U, // SETAr >+ 103941U, // SETBEm >+ 22021U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 101969U, // SETBm >+ 20049U, // SETBr >+ 104100U, // SETEm >+ 22180U, // SETEr >+ 103986U, // SETGEm >+ 22066U, // SETGEr >+ 104186U, // SETGm >+ 22266U, // SETGr >+ 104010U, // SETLEm >+ 22090U, // SETLEr >+ 104540U, // SETLm >+ 22620U, // SETLr >+ 104038U, // SETNEm >+ 22118U, // SETNEr >+ 104663U, // SETNOm >+ 22743U, // SETNOr >+ 104775U, // SETNPm >+ 22855U, // SETNPr >+ 105709U, // SETNSm >+ 23789U, // SETNSr >+ 104678U, // SETOm >+ 22758U, // SETOr >+ 104822U, // SETPm >+ 22902U, // SETPr >+ 106887U, // SETSm >+ 24967U, // SETSr >+ 11421U, // SFENCE >+ 287134U, // SGDT16m >+ 287134U, // SGDT32m >+ 287134U, // SGDT64m >+ 403721070U, // SHA1MSG1rm >+ 34622318U, // SHA1MSG1rr >+ 403721153U, // SHA1MSG2rm >+ 34622401U, // SHA1MSG2rr >+ 403723955U, // SHA1NEXTErm >+ 34625203U, // SHA1NEXTErr >+ 2551204913U, // SHA1RNDS4rmi >+ 2182106161U, // SHA1RNDS4rri >+ 403721080U, // SHA256MSG1rm >+ 34622328U, // SHA256MSG1rr >+ 403721163U, // SHA256MSG2rm >+ 34622411U, // SHA256MSG2rr >+ 403721175U, // SHA256RNDS2rm >+ 34622423U, // SHA256RNDS2rr >+ 13670419U, // SHL16m1 >+ 14718995U, // SHL16mCL >+ 1087507U, // SHL16mi >+ 13654035U, // SHL16r1 >+ 14702611U, // SHL16rCL >+ 34625555U, // SHL16ri >+ 13703187U, // SHL32m1 >+ 14751763U, // SHL32mCL >+ 1120275U, // SHL32mi >+ 13654035U, // SHL32r1 >+ 14702611U, // SHL32rCL >+ 34625555U, // SHL32ri >+ 13719571U, // SHL64m1 >+ 14768147U, // SHL64mCL >+ 1136659U, // SHL64mi >+ 13654035U, // SHL64r1 >+ 14702611U, // SHL64rCL >+ 34625555U, // SHL64ri >+ 13735955U, // SHL8m1 >+ 14784531U, // SHL8mCL >+ 1153043U, // SHL8mi >+ 13654035U, // SHL8r1 >+ 14702611U, // SHL8rCL >+ 34625555U, // SHL8ri >+ 2148569095U, // SHLD16mrCL >+ 2148569095U, // SHLD16mri8 >+ 2182107143U, // SHLD16rrCL >+ 2182107143U, // SHLD16rri8 >+ 2148601863U, // SHLD32mrCL >+ 2148601863U, // SHLD32mri8 >+ 2182107143U, // SHLD32rrCL >+ 2182107143U, // SHLD32rri8 >+ 2148618247U, // SHLD64mrCL >+ 2148618247U, // SHLD64mri8 >+ 2182107143U, // SHLD64rrCL >+ 2182107143U, // SHLD64rri8 >+ 2450547984U, // SHLX32rm >+ 2484102416U, // SHLX32rr >+ 2517656848U, // SHLX64rm >+ 2484102416U, // SHLX64rr >+ 13671494U, // SHR16m1 >+ 14720070U, // SHR16mCL >+ 1088582U, // SHR16mi >+ 13655110U, // SHR16r1 >+ 14703686U, // SHR16rCL >+ 34626630U, // SHR16ri >+ 13704262U, // SHR32m1 >+ 14752838U, // SHR32mCL >+ 1121350U, // SHR32mi >+ 13655110U, // SHR32r1 >+ 14703686U, // SHR32rCL >+ 34626630U, // SHR32ri >+ 13720646U, // SHR64m1 >+ 14769222U, // SHR64mCL >+ 1137734U, // SHR64mi >+ 13655110U, // SHR64r1 >+ 14703686U, // SHR64rCL >+ 34626630U, // SHR64ri >+ 13737030U, // SHR8m1 >+ 14785606U, // SHR8mCL >+ 1154118U, // SHR8mi >+ 13655110U, // SHR8r1 >+ 14703686U, // SHR8rCL >+ 34626630U, // SHR8ri >+ 2148569922U, // SHRD16mrCL >+ 2148569922U, // SHRD16mri8 >+ 2182107970U, // SHRD16rrCL >+ 2182107970U, // SHRD16rri8 >+ 2148602690U, // SHRD32mrCL >+ 2148602690U, // SHRD32mri8 >+ 2182107970U, // SHRD32rrCL >+ 2182107970U, // SHRD32rri8 >+ 2148619074U, // SHRD64mrCL >+ 2148619074U, // SHRD64mri8 >+ 2182107970U, // SHRD64rrCL >+ 2182107970U, // SHRD64rri8 >+ 2450548033U, // SHRX32rm >+ 2484102465U, // SHRX32rr >+ 2517656897U, // SHRX64rm >+ 2484102465U, // SHRX64rr >+ 2349879869U, // SHUFPDrmi >+ 2182107709U, // SHUFPDrri >+ 2349883096U, // SHUFPSrmi >+ 2182110936U, // SHUFPSrri >+ 287146U, // SIDT16m >+ 287146U, // SIDT32m >+ 287146U, // SIDT64m >+ 11713U, // SIN_F >+ 0U, // SIN_Fp32 >+ 0U, // SIN_Fp64 >+ 0U, // SIN_Fp80 >+ 12287U, // SKINIT >+ 41398U, // SLDT16m >+ 25014U, // SLDT16r >+ 25014U, // SLDT32r >+ 41398U, // SLDT64m >+ 25014U, // SLDT64r >+ 42056U, // SMSW16m >+ 25672U, // SMSW16r >+ 25672U, // SMSW32r >+ 25672U, // SMSW64r >+ 537940706U, // SQRTPDm >+ 336614114U, // SQRTPDr >+ 537943977U, // SQRTPSm >+ 336617385U, // SQRTPSr >+ 571495599U, // SQRTSDm >+ 571495599U, // SQRTSDm_Int >+ 336614575U, // SQRTSDr >+ 336614575U, // SQRTSDr_Int >+ 605053250U, // SQRTSSm >+ 605053250U, // SQRTSSm_Int >+ 336617794U, // SQRTSSr >+ 336617794U, // SQRTSSr_Int >+ 12154U, // SQRT_F >+ 0U, // SQRT_Fp32 >+ 0U, // SQRT_Fp64 >+ 0U, // SQRT_Fp80 >+ 11273U, // STAC >+ 11327U, // STC >+ 11385U, // STD >+ 11575U, // STGI >+ 11590U, // STI >+ 72846U, // STMXCSR >+ 12881430U, // STOSB >+ 10802326U, // STOSL >+ 12147567U, // STOSQ >+ 9774167U, // STOSW >+ 23719U, // STR16r >+ 23719U, // STR32r >+ 23719U, // STR64r >+ 40103U, // STRm >+ 123439U, // ST_F32m >+ 139823U, // ST_F64m >+ 26100U, // ST_FCOMPST0r >+ 26100U, // ST_FCOMPST0r_alt >+ 26087U, // ST_FCOMST0r >+ 121219U, // ST_FP32m >+ 137603U, // ST_FP64m >+ 383363U, // ST_FP80m >+ 2119188U, // ST_FPNCEST0r >+ 2120067U, // ST_FPST0r >+ 2120067U, // ST_FPST0r_alt >+ 22915U, // ST_FPrr >+ 26074U, // ST_FXCHST0r >+ 26074U, // ST_FXCHST0r_alt >+ 0U, // ST_Fp32m >+ 0U, // ST_Fp64m >+ 0U, // ST_Fp64m32 >+ 0U, // ST_Fp80m32 >+ 0U, // ST_Fp80m64 >+ 0U, // ST_FpP32m >+ 0U, // ST_FpP64m >+ 0U, // ST_FpP64m32 >+ 0U, // ST_FpP80m >+ 0U, // ST_FpP80m32 >+ 0U, // ST_FpP80m64 >+ 25135U, // ST_Frr >+ 26278U, // SUB16i16 >+ 1085067U, // SUB16mi >+ 1085067U, // SUB16mi8 >+ 1085067U, // SUB16mr >+ 34655883U, // SUB16ri >+ 34655883U, // SUB16ri8 >+ 68210315U, // SUB16rm >+ 34655883U, // SUB16rr >+ 34623115U, // SUB16rr_REV >+ 26413U, // SUB32i32 >+ 1117835U, // SUB32mi >+ 1117835U, // SUB32mi8 >+ 1117835U, // SUB32mr >+ 34655883U, // SUB32ri >+ 34655883U, // SUB32ri8 >+ 101764747U, // SUB32rm >+ 34655883U, // SUB32rr >+ 34623115U, // SUB32rr_REV >+ 26561U, // SUB64i32 >+ 1134219U, // SUB64mi32 >+ 1134219U, // SUB64mi8 >+ 1134219U, // SUB64mr >+ 34655883U, // SUB64ri32 >+ 34655883U, // SUB64ri8 >+ 135319179U, // SUB64rm >+ 34655883U, // SUB64rr >+ 34623115U, // SUB64rr_REV >+ 26176U, // SUB8i8 >+ 1150603U, // SUB8mi >+ 1150603U, // SUB8mr >+ 34655883U, // SUB8ri >+ 34655883U, // SUB8ri8 >+ 168873611U, // SUB8rm >+ 34655883U, // SUB8rr >+ 34623115U, // SUB8rr_REV >+ 202396073U, // SUBPDrm >+ 34623913U, // SUBPDrr >+ 202399300U, // SUBPSrm >+ 34627140U, // SUBPSrr >+ 121899U, // SUBR_F32m >+ 138283U, // SUBR_F64m >+ 39986U, // SUBR_FI16m >+ 72754U, // SUBR_FI32m >+ 22886U, // SUBR_FPrST0 >+ 23595U, // SUBR_FST0r >+ 0U, // SUBR_Fp32m >+ 0U, // SUBR_Fp64m >+ 0U, // SUBR_Fp64m32 >+ 0U, // SUBR_Fp80m32 >+ 0U, // SUBR_Fp80m64 >+ 0U, // SUBR_FpI16m32 >+ 0U, // SUBR_FpI16m64 >+ 0U, // SUBR_FpI16m80 >+ 0U, // SUBR_FpI32m32 >+ 0U, // SUBR_FpI32m64 >+ 0U, // SUBR_FpI32m80 >+ 2120747U, // SUBR_FrST0 >+ 235951145U, // SUBSDrm >+ 235951145U, // SUBSDrm_Int >+ 34624553U, // SUBSDrr >+ 34624553U, // SUBSDrr_Int >+ 269508803U, // SUBSSrm >+ 269508803U, // SUBSSrm_Int >+ 34627779U, // SUBSSrr >+ 34627779U, // SUBSSrr_Int >+ 118410U, // SUB_F32m >+ 134794U, // SUB_F64m >+ 36496U, // SUB_FI16m >+ 69264U, // SUB_FI32m >+ 22778U, // SUB_FPrST0 >+ 20106U, // SUB_FST0r >+ 0U, // SUB_Fp32 >+ 0U, // SUB_Fp32m >+ 0U, // SUB_Fp64 >+ 0U, // SUB_Fp64m >+ 0U, // SUB_Fp64m32 >+ 0U, // SUB_Fp80 >+ 0U, // SUB_Fp80m32 >+ 0U, // SUB_Fp80m64 >+ 0U, // SUB_FpI16m32 >+ 0U, // SUB_FpI16m64 >+ 0U, // SUB_FpI16m80 >+ 0U, // SUB_FpI32m32 >+ 0U, // SUB_FpI32m64 >+ 0U, // SUB_FpI32m80 >+ 2117258U, // SUB_FrST0 >+ 11992U, // SWAPGS >+ 11653U, // SYSCALL >+ 11872U, // SYSENTER >+ 12134U, // SYSEXIT >+ 12134U, // SYSEXIT64 >+ 12114U, // SYSRET >+ 12114U, // SYSRET64 >+ 303058684U, // T1MSKC32rm >+ 336613116U, // T1MSKC32rr >+ 370167548U, // T1MSKC64rm >+ 336613116U, // T1MSKC64rr >+ 15882534U, // TAILJMPd >+ 15882534U, // TAILJMPd64 >+ 15800614U, // TAILJMPm >+ 15816998U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 15751462U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 26362U, // TEST16i16 >+ 1090089U, // TEST16mi >+ 1090089U, // TEST16mi_alt >+ 336618025U, // TEST16ri >+ 336618025U, // TEST16ri_alt >+ 1090089U, // TEST16rm >+ 336618025U, // TEST16rr >+ 26530U, // TEST32i32 >+ 1122857U, // TEST32mi >+ 1122857U, // TEST32mi_alt >+ 336618025U, // TEST32ri >+ 336618025U, // TEST32ri_alt >+ 1122857U, // TEST32rm >+ 336618025U, // TEST32rr >+ 26669U, // TEST64i32 >+ 1139241U, // TEST64mi32 >+ 1139241U, // TEST64mi32_alt >+ 336618025U, // TEST64ri32 >+ 336618025U, // TEST64ri32_alt >+ 1139241U, // TEST64rm >+ 336618025U, // TEST64rr >+ 26250U, // TEST8i8 >+ 1155625U, // TEST8mi >+ 1155625U, // TEST8mi_alt >+ 336618025U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 336618025U, // TEST8ri_alt >+ 1155625U, // TEST8rm >+ 336618025U, // TEST8rr >+ 10930U, // TLSCall_32 >+ 11034U, // TLSCall_64 >+ 10943U, // TLS_addr32 >+ 11047U, // TLS_addr64 >+ 10956U, // TLS_base_addr32 >+ 11060U, // TLS_base_addr64 >+ 10974U, // TRAP >+ 12166U, // TST_F >+ 0U, // TST_Fp32 >+ 0U, // TST_Fp64 >+ 0U, // TST_Fp80 >+ 470835673U, // TZCNT16rm >+ 336617945U, // TZCNT16rr >+ 303063513U, // TZCNT32rm >+ 336617945U, // TZCNT32rr >+ 370172377U, // TZCNT64rm >+ 336617945U, // TZCNT64rr >+ 303060994U, // TZMSK32rm >+ 336615426U, // TZMSK32rr >+ 370169858U, // TZMSK64rm >+ 336615426U, // TZMSK64rr >+ 571495531U, // UCOMISDrm >+ 336614507U, // UCOMISDrr >+ 605053189U, // UCOMISSrm >+ 336617733U, // UCOMISSrr >+ 22421U, // UCOM_FIPr >+ 22363U, // UCOM_FIr >+ 11788U, // UCOM_FPPr >+ 22842U, // UCOM_FPr >+ 0U, // UCOM_FpIr32 >+ 0U, // UCOM_FpIr64 >+ 0U, // UCOM_FpIr80 >+ 0U, // UCOM_Fpr32 >+ 0U, // UCOM_Fpr64 >+ 0U, // UCOM_Fpr80 >+ 22665U, // UCOM_Fr >+ 11207U, // UD2B >+ 202396230U, // UNPCKHPDrm >+ 34624070U, // UNPCKHPDrr >+ 202399457U, // UNPCKHPSrm >+ 34627297U, // UNPCKHPSrr >+ 202396272U, // UNPCKLPDrm >+ 34624112U, // UNPCKLPDrr >+ 202399519U, // UNPCKLPSrm >+ 34627359U, // UNPCKLPSrr >+ 2651875417U, // VAARG_64 >+ 2484097548U, // VADDPDYrm >+ 2484097548U, // VADDPDYrr >+ 2484093636U, // VADDPDZrm >+ 2484093636U, // VADDPDZrmb >+ 352338628U, // VADDPDZrmbk >+ 2499822276U, // VADDPDZrmbkz >+ 352342540U, // VADDPDZrmk >+ 2499826188U, // VADDPDZrmkz >+ 2484093636U, // VADDPDZrr >+ 352338628U, // VADDPDZrrk >+ 2499822276U, // VADDPDZrrkz >+ 2484097548U, // VADDPDrm >+ 2484097548U, // VADDPDrr >+ 2484100775U, // VADDPSYrm >+ 2484100775U, // VADDPSYrr >+ 2484095340U, // VADDPSZrm >+ 2484095340U, // VADDPSZrmb >+ 352340332U, // VADDPSZrmbk >+ 2499823980U, // VADDPSZrmbkz >+ 352345767U, // VADDPSZrmk >+ 2499829415U, // VADDPSZrmkz >+ 2484095340U, // VADDPSZrr >+ 352340332U, // VADDPSZrrk >+ 2499823980U, // VADDPSZrrkz >+ 2484100775U, // VADDPSrm >+ 2484100775U, // VADDPSrr >+ 2484098136U, // VADDSDZrm >+ 2484098136U, // VADDSDZrr >+ 2484098136U, // VADDSDrm >+ 2484098136U, // VADDSDrm_Int >+ 2484098136U, // VADDSDrr >+ 2484098136U, // VADDSDrr_Int >+ 2484101362U, // VADDSSZrm >+ 2484101362U, // VADDSSZrr >+ 2484101362U, // VADDSSrm >+ 2484101362U, // VADDSSrm_Int >+ 2484101362U, // VADDSSrr >+ 2484101362U, // VADDSSrr_Int >+ 2484097456U, // VADDSUBPDYrm >+ 2484097456U, // VADDSUBPDYrr >+ 2484097456U, // VADDSUBPDrm >+ 2484097456U, // VADDSUBPDrr >+ 2484100683U, // VADDSUBPSYrm >+ 2484100683U, // VADDSUBPSYrr >+ 2484100683U, // VADDSUBPSrm >+ 2484100683U, // VADDSUBPSrr >+ 2484101645U, // VAESDECLASTrm >+ 2484101645U, // VAESDECLASTrr >+ 2484096741U, // VAESDECrm >+ 2484096741U, // VAESDECrr >+ 2484101658U, // VAESENCLASTrm >+ 2484101658U, // VAESENCLASTrr >+ 2484096781U, // VAESENCrm >+ 2484096781U, // VAESENCrr >+ 437276420U, // VAESIMCrm >+ 336613124U, // VAESIMCrr >+ 2584764986U, // VAESKEYGENASSIST128rm >+ 2484101690U, // VAESKEYGENASSIST128rr >+ 2484093324U, // VALIGNDrmi >+ 2484093324U, // VALIGNDrri >+ 50348428U, // VALIGNDrrik >+ 2499821964U, // VALIGNDrrikz >+ 2484094801U, // VALIGNQrmi >+ 2484094801U, // VALIGNQrri >+ 50349905U, // VALIGNQrrik >+ 2499823441U, // VALIGNQrrikz >+ 2484097692U, // VANDNPDYrm >+ 2484097692U, // VANDNPDYrr >+ 2484097692U, // VANDNPDrm >+ 2484097692U, // VANDNPDrr >+ 2484100931U, // VANDNPSYrm >+ 2484100931U, // VANDNPSYrr >+ 2484100931U, // VANDNPSrm >+ 2484100931U, // VANDNPSrr >+ 2484097556U, // VANDPDYrm >+ 2484097556U, // VANDPDYrr >+ 2484097556U, // VANDPDrm >+ 2484097556U, // VANDPDrr >+ 2484100783U, // VANDPSYrm >+ 2484100783U, // VANDPSYrr >+ 2484100783U, // VANDPSrm >+ 2484100783U, // VANDPSrr >+ 2484103305U, // VASTART_SAVE_XMM_REGS >+ 352338709U, // VBLENDMPDZrm >+ 352338709U, // VBLENDMPDZrr >+ 352340413U, // VBLENDMPSZrm >+ 352340413U, // VBLENDMPSZrr >+ 2484097564U, // VBLENDPDYrmi >+ 2484097564U, // VBLENDPDYrri >+ 2484097564U, // VBLENDPDrmi >+ 2484097564U, // VBLENDPDrri >+ 2484100791U, // VBLENDPSYrmi >+ 2484100791U, // VBLENDPSYrri >+ 2484100791U, // VBLENDPSrmi >+ 2484100791U, // VBLENDPSrri >+ 2484097788U, // VBLENDVPDYrm >+ 2484097788U, // VBLENDVPDYrr >+ 2484097788U, // VBLENDVPDrm >+ 2484097788U, // VBLENDVPDrr >+ 2484101068U, // VBLENDVPSYrm >+ 2484101068U, // VBLENDVPSYrr >+ 2484101068U, // VBLENDVPSrm >+ 2484101068U, // VBLENDVPSrr >+ 537939170U, // VBROADCASTF128 >+ 437275929U, // VBROADCASTI128 >+ 2499821569U, // VBROADCASTI32X4krm >+ 437272577U, // VBROADCASTI32X4rm >+ 2499821587U, // VBROADCASTI64X4krm >+ 839925779U, // VBROADCASTI64X4rm >+ 571495607U, // VBROADCASTSDYrm >+ 336614583U, // VBROADCASTSDYrr >+ 571491443U, // VBROADCASTSDZrm >+ 336610419U, // VBROADCASTSDZrr >+ 605053267U, // VBROADCASTSSYrm >+ 336617811U, // VBROADCASTSSYrr >+ 605047459U, // VBROADCASTSSZrm >+ 336612003U, // VBROADCASTSSZrr >+ 605053267U, // VBROADCASTSSrm >+ 336617811U, // VBROADCASTSSrr >+ 2486529531U, // VCMPPDYrmi >+ 2484097716U, // VCMPPDYrmi_alt >+ 2486545915U, // VCMPPDYrri >+ 2484097716U, // VCMPPDYrri_alt >+ 890596859U, // VCMPPDZrmi >+ 2484093748U, // VCMPPDZrmi_alt >+ 51752443U, // VCMPPDZrri >+ 2484093748U, // VCMPPDZrri_alt >+ 51752443U, // VCMPPDZrrib >+ 2486529531U, // VCMPPDrmi >+ 2484097716U, // VCMPPDrmi_alt >+ 2486545915U, // VCMPPDrri >+ 2484097716U, // VCMPPDrri_alt >+ 2487578107U, // VCMPPSYrmi >+ 2484100963U, // VCMPPSYrmi_alt >+ 2487594491U, // VCMPPSYrri >+ 2484100963U, // VCMPPSYrri_alt >+ 891645435U, // VCMPPSZrmi >+ 2484095452U, // VCMPPSZrmi_alt >+ 52801019U, // VCMPPSZrri >+ 2484095452U, // VCMPPSZrri_alt >+ 52801019U, // VCMPPSZrrib >+ 2487578107U, // VCMPPSrmi >+ 2484100963U, // VCMPPSrmi_alt >+ 2487594491U, // VCMPPSrri >+ 2484100963U, // VCMPPSrri_alt >+ 2488626683U, // VCMPSDZrm >+ 2484098205U, // VCMPSDZrmi_alt >+ 2488643067U, // VCMPSDZrr >+ 2484098205U, // VCMPSDZrri_alt >+ 2488626683U, // VCMPSDrm >+ 2484098205U, // VCMPSDrm_alt >+ 2488643067U, // VCMPSDrr >+ 2484098205U, // VCMPSDrr_alt >+ 2489675259U, // VCMPSSZrm >+ 2484101423U, // VCMPSSZrmi_alt >+ 2489691643U, // VCMPSSZrr >+ 2484101423U, // VCMPSSZrri_alt >+ 2489675259U, // VCMPSSrm >+ 2484101423U, // VCMPSSrm_alt >+ 2489691643U, // VCMPSSrr >+ 2484101423U, // VCMPSSrr_alt >+ 537941108U, // VCOMISDZrm >+ 336614516U, // VCOMISDZrr >+ 537941108U, // VCOMISDrm >+ 336614516U, // VCOMISDrr >+ 537944334U, // VCOMISSZrm >+ 336617742U, // VCOMISSZrr >+ 537944334U, // VCOMISSrm >+ 336617742U, // VCOMISSrr >+ 437276966U, // VCVTDQ2PDYrm >+ 336613670U, // VCVTDQ2PDYrr >+ 839926270U, // VCVTDQ2PDZrm >+ 336609790U, // VCVTDQ2PDZrr >+ 370168102U, // VCVTDQ2PDrm >+ 336613670U, // VCVTDQ2PDrr >+ 839933396U, // VCVTDQ2PSYrm >+ 336616916U, // VCVTDQ2PSYrr >+ 907036850U, // VCVTDQ2PSZrm >+ 336611506U, // VCVTDQ2PSZrr >+ 2484095154U, // VCVTDQ2PSZrrb >+ 437280212U, // VCVTDQ2PSrm >+ 336616916U, // VCVTDQ2PSrr >+ 537945391U, // VCVTPD2DQXrm >+ 940595750U, // VCVTPD2DQYrm >+ 336615974U, // VCVTPD2DQYrr >+ 974145037U, // VCVTPD2DQZrm >+ 336610829U, // VCVTPD2DQZrr >+ 2484094477U, // VCVTPD2DQZrrb >+ 336615974U, // VCVTPD2DQrr >+ 537945421U, // VCVTPD2PSXrm >+ 940596648U, // VCVTPD2PSYrm >+ 336616872U, // VCVTPD2PSYrr >+ 974145690U, // VCVTPD2PSZrm >+ 336611482U, // VCVTPD2PSZrr >+ 2484095130U, // VCVTPD2PSZrrb >+ 336616872U, // VCVTPD2PSrr >+ 974145205U, // VCVTPD2UDQZrm >+ 336610997U, // VCVTPD2UDQZrr >+ 2484094645U, // VCVTPD2UDQZrrb >+ 537943475U, // VCVTPH2PSYrm >+ 336616883U, // VCVTPH2PSYrr >+ 940596659U, // VCVTPH2PSZrm >+ 336616883U, // VCVTPH2PSZrr >+ 571497907U, // VCVTPH2PSrm >+ 336616883U, // VCVTPH2PSrr >+ 940595782U, // VCVTPS2DQYrm >+ 336616006U, // VCVTPS2DQYrr >+ 974145062U, // VCVTPS2DQZrm >+ 336610854U, // VCVTPS2DQZrr >+ 2484094502U, // VCVTPS2DQZrrb >+ 537942598U, // VCVTPS2DQrm >+ 336616006U, // VCVTPS2DQrr >+ 537940273U, // VCVTPS2PDYrm >+ 336613681U, // VCVTPS2PDYrr >+ 940589591U, // VCVTPS2PDZrm >+ 336609815U, // VCVTPS2PDZrr >+ 571494705U, // VCVTPS2PDrm >+ 336613681U, // VCVTPS2PDrr >+ 2149127959U, // VCVTPS2PHYmr >+ 2484098839U, // VCVTPS2PHYrr >+ 2149156119U, // VCVTPS2PHZmr >+ 2484094231U, // VCVTPS2PHZrr >+ 2148669207U, // VCVTPS2PHmr >+ 2484098839U, // VCVTPS2PHrr >+ 974145232U, // VCVTPS2UDQZrm >+ 336611024U, // VCVTPS2UDQZrr >+ 2484094672U, // VCVTPS2UDQZrrb >+ 571491632U, // VCVTSD2SI64Zrm >+ 336610608U, // VCVTSD2SI64Zrr >+ 571496386U, // VCVTSD2SI64rm >+ 336615362U, // VCVTSD2SI64rr >+ 571491632U, // VCVTSD2SIZrm >+ 336610608U, // VCVTSD2SIZrr >+ 571496386U, // VCVTSD2SIrm >+ 336615362U, // VCVTSD2SIrr >+ 2484101224U, // VCVTSD2SSZrm >+ 2484101224U, // VCVTSD2SSZrr >+ 2484101224U, // VCVTSD2SSrm >+ 2484101224U, // VCVTSD2SSrr >+ 571491683U, // VCVTSD2USI64Zrm >+ 336610659U, // VCVTSD2USI64Zrr >+ 571491683U, // VCVTSD2USIZrm >+ 336610659U, // VCVTSD2USIZrr >+ 2484097990U, // VCVTSI2SD64rm >+ 2484097990U, // VCVTSI2SD64rr >+ 2484093903U, // VCVTSI2SDZrm >+ 2484093903U, // VCVTSI2SDZrr >+ 2484097990U, // VCVTSI2SDrm >+ 2484097990U, // VCVTSI2SDrr >+ 2484101235U, // VCVTSI2SS64rm >+ 2484101235U, // VCVTSI2SS64rr >+ 2484095506U, // VCVTSI2SSZrm >+ 2484095506U, // VCVTSI2SSZrr >+ 2484101235U, // VCVTSI2SSrm >+ 2484101235U, // VCVTSI2SSrr >+ 2484093903U, // VCVTSI642SDZrm >+ 2484093903U, // VCVTSI642SDZrr >+ 2484095506U, // VCVTSI642SSZrm >+ 2484095506U, // VCVTSI642SSZrr >+ 2484098013U, // VCVTSS2SDZrm >+ 2484098013U, // VCVTSS2SDZrr >+ 2484098013U, // VCVTSS2SDrm >+ 2484098013U, // VCVTSS2SDrr >+ 605046089U, // VCVTSS2SI64Zrm >+ 336610633U, // VCVTSS2SI64Zrr >+ 605050841U, // VCVTSS2SI64rm >+ 336615385U, // VCVTSS2SI64rr >+ 605046089U, // VCVTSS2SIZrm >+ 336610633U, // VCVTSS2SIZrr >+ 605050841U, // VCVTSS2SIrm >+ 336615385U, // VCVTSS2SIrr >+ 605046142U, // VCVTSS2USI64Zrm >+ 336610686U, // VCVTSS2USI64Zrr >+ 605046142U, // VCVTSS2USIZrm >+ 336610686U, // VCVTSS2USIZrr >+ 537945378U, // VCVTTPD2DQXrm >+ 940595738U, // VCVTTPD2DQYrm >+ 336615962U, // VCVTTPD2DQYrr >+ 974145024U, // VCVTTPD2DQZrm >+ 336610816U, // VCVTTPD2DQZrr >+ 336615962U, // VCVTTPD2DQrr >+ 974145191U, // VCVTTPD2UDQZrm >+ 336610983U, // VCVTTPD2UDQZrr >+ 940595770U, // VCVTTPS2DQYrm >+ 336615994U, // VCVTTPS2DQYrr >+ 974145049U, // VCVTTPS2DQZrm >+ 336610841U, // VCVTTPS2DQZrr >+ 537942586U, // VCVTTPS2DQrm >+ 336615994U, // VCVTTPS2DQrr >+ 974145218U, // VCVTTPS2UDQZrm >+ 336611010U, // VCVTTPS2UDQZrr >+ 571491619U, // VCVTTSD2SI64Zrm >+ 336610595U, // VCVTTSD2SI64Zrr >+ 571496374U, // VCVTTSD2SI64rm >+ 336615350U, // VCVTTSD2SI64rr >+ 571491619U, // VCVTTSD2SIZrm >+ 336610595U, // VCVTTSD2SIZrr >+ 571496374U, // VCVTTSD2SIrm >+ 336615350U, // VCVTTSD2SIrr >+ 571491669U, // VCVTTSD2USI64Zrm >+ 336610645U, // VCVTTSD2USI64Zrr >+ 571491669U, // VCVTTSD2USIZrm >+ 336610645U, // VCVTTSD2USIZrr >+ 605046076U, // VCVTTSS2SI64Zrm >+ 336610620U, // VCVTTSS2SI64Zrr >+ 605050829U, // VCVTTSS2SI64rm >+ 336615373U, // VCVTTSS2SI64rr >+ 605046076U, // VCVTTSS2SIZrm >+ 336610620U, // VCVTTSS2SIZrr >+ 605050829U, // VCVTTSS2SIrm >+ 336615373U, // VCVTTSS2SIrr >+ 605046128U, // VCVTTSS2USI64Zrm >+ 336610672U, // VCVTTSS2USI64Zrr >+ 605046128U, // VCVTTSS2USIZrm >+ 336610672U, // VCVTTSS2USIZrr >+ 940589578U, // VCVTUDQ2PDZrm >+ 336609802U, // VCVTUDQ2PDZrr >+ 974145726U, // VCVTUDQ2PSZrm >+ 336611518U, // VCVTUDQ2PSZrr >+ 2484095166U, // VCVTUDQ2PSZrrb >+ 2484093915U, // VCVTUSI2SDZrm >+ 2484093915U, // VCVTUSI2SDZrr >+ 2484095518U, // VCVTUSI2SSZrm >+ 2484095518U, // VCVTUSI2SSZrr >+ 2484093915U, // VCVTUSI642SDZrm >+ 2484093915U, // VCVTUSI642SDZrr >+ 2484095518U, // VCVTUSI642SSZrm >+ 2484095518U, // VCVTUSI642SSZrr >+ 2484097799U, // VDIVPDYrm >+ 2484097799U, // VDIVPDYrr >+ 2484093784U, // VDIVPDZrm >+ 2484093784U, // VDIVPDZrmb >+ 352338776U, // VDIVPDZrmbk >+ 2499822424U, // VDIVPDZrmbkz >+ 352342791U, // VDIVPDZrmk >+ 2499826439U, // VDIVPDZrmkz >+ 2484093784U, // VDIVPDZrr >+ 352338776U, // VDIVPDZrrk >+ 2499822424U, // VDIVPDZrrkz >+ 2484097799U, // VDIVPDrm >+ 2484097799U, // VDIVPDrr >+ 2484101079U, // VDIVPSYrm >+ 2484101079U, // VDIVPSYrr >+ 2484095488U, // VDIVPSZrm >+ 2484095488U, // VDIVPSZrmb >+ 352340480U, // VDIVPSZrmbk >+ 2499824128U, // VDIVPSZrmbkz >+ 352346071U, // VDIVPSZrmk >+ 2499829719U, // VDIVPSZrmkz >+ 2484095488U, // VDIVPSZrr >+ 352340480U, // VDIVPSZrrk >+ 2499824128U, // VDIVPSZrrkz >+ 2484101079U, // VDIVPSrm >+ 2484101079U, // VDIVPSrr >+ 2484098245U, // VDIVSDZrm >+ 2484098245U, // VDIVSDZrr >+ 2484098245U, // VDIVSDrm >+ 2484098245U, // VDIVSDrm_Int >+ 2484098245U, // VDIVSDrr >+ 2484098245U, // VDIVSDrr_Int >+ 2484101473U, // VDIVSSZrm >+ 2484101473U, // VDIVSSZrr >+ 2484101473U, // VDIVSSrm >+ 2484101473U, // VDIVSSrm_Int >+ 2484101473U, // VDIVSSrr >+ 2484101473U, // VDIVSSrr_Int >+ 2484097709U, // VDPPDrmi >+ 2484097709U, // VDPPDrri >+ 2484100956U, // VDPPSYrmi >+ 2484100956U, // VDPPSYrri >+ 2484100956U, // VDPPSrmi >+ 2484100956U, // VDPPSrri >+ 40056U, // VERRm >+ 23672U, // VERRr >+ 41959U, // VERWm >+ 25575U, // VERWr >+ 2149125319U, // VEXTRACTF128mr >+ 2484096199U, // VEXTRACTF128rr >+ 2149125180U, // VEXTRACTF32x4mr >+ 2484096060U, // VEXTRACTF32x4rr >+ 2149158006U, // VEXTRACTF64x4mr >+ 2484096118U, // VEXTRACTF64x4rr >+ 2148797694U, // VEXTRACTI128mr >+ 2484096254U, // VEXTRACTI128rr >+ 2148797529U, // VEXTRACTI32x4mr >+ 2484096089U, // VEXTRACTI32x4rr >+ 2149174419U, // VEXTRACTI64x4mr >+ 2484096147U, // VEXTRACTI64x4rr >+ 2148654982U, // VEXTRACTPSmr >+ 2484100998U, // VEXTRACTPSrr >+ 2148654982U, // VEXTRACTPSzmr >+ 2484100998U, // VEXTRACTPSzrr >+ 2182103509U, // VFMADD132PDZm >+ 2182103509U, // VFMADD132PDZmb >+ 2182105213U, // VFMADD132PSZm >+ 2182105213U, // VFMADD132PSZmb >+ 2182103662U, // VFMADD213PDZm >+ 2182103662U, // VFMADD213PDZmb >+ 2182103662U, // VFMADD213PDZr >+ 50348654U, // VFMADD213PDZrk >+ 2197832302U, // VFMADD213PDZrkz >+ 2182105366U, // VFMADD213PSZm >+ 2182105366U, // VFMADD213PSZmb >+ 2182105366U, // VFMADD213PSZr >+ 50350358U, // VFMADD213PSZrk >+ 2197834006U, // VFMADD213PSZrkz >+ 2484097527U, // VFMADDPD4mr >+ 2484097527U, // VFMADDPD4mrY >+ 2484097527U, // VFMADDPD4rm >+ 2484097527U, // VFMADDPD4rmY >+ 2484097527U, // VFMADDPD4rr >+ 2484097527U, // VFMADDPD4rrY >+ 2484097527U, // VFMADDPD4rrY_REV >+ 2484097527U, // VFMADDPD4rr_REV >+ 2182107381U, // VFMADDPDr132m >+ 2182107381U, // VFMADDPDr132mY >+ 2182107381U, // VFMADDPDr132r >+ 2182107381U, // VFMADDPDr132rY >+ 2182107511U, // VFMADDPDr213m >+ 2182107511U, // VFMADDPDr213mY >+ 2182107511U, // VFMADDPDr213r >+ 2182107511U, // VFMADDPDr213rY >+ 2182107295U, // VFMADDPDr231m >+ 2182107295U, // VFMADDPDr231mY >+ 2182107295U, // VFMADDPDr231r >+ 2182107295U, // VFMADDPDr231rY >+ 2484100754U, // VFMADDPS4mr >+ 2484100754U, // VFMADDPS4mrY >+ 2484100754U, // VFMADDPS4rm >+ 2484100754U, // VFMADDPS4rmY >+ 2484100754U, // VFMADDPS4rr >+ 2484100754U, // VFMADDPS4rrY >+ 2484100754U, // VFMADDPS4rrY_REV >+ 2484100754U, // VFMADDPS4rr_REV >+ 2182110605U, // VFMADDPSr132m >+ 2182110605U, // VFMADDPSr132mY >+ 2182110605U, // VFMADDPSr132r >+ 2182110605U, // VFMADDPSr132rY >+ 2182110746U, // VFMADDPSr213m >+ 2182110746U, // VFMADDPSr213mY >+ 2182110746U, // VFMADDPSr213r >+ 2182110746U, // VFMADDPSr213rY >+ 2182110519U, // VFMADDPSr231m >+ 2182110519U, // VFMADDPSr231mY >+ 2182110519U, // VFMADDPSr231r >+ 2182110519U, // VFMADDPSr231rY >+ 2484098115U, // VFMADDSD4mr >+ 2484098115U, // VFMADDSD4mr_Int >+ 2484098115U, // VFMADDSD4rm >+ 2484098115U, // VFMADDSD4rm_Int >+ 2484098115U, // VFMADDSD4rr >+ 2484098115U, // VFMADDSD4rr_Int >+ 2484098115U, // VFMADDSD4rr_REV >+ 2182104069U, // VFMADDSDZm >+ 2182104069U, // VFMADDSDZr >+ 2182108075U, // VFMADDSDr132m >+ 2182108075U, // VFMADDSDr132r >+ 2182108163U, // VFMADDSDr213m >+ 2182108163U, // VFMADDSDr213r >+ 2182108021U, // VFMADDSDr231m >+ 2182108021U, // VFMADDSDr231r >+ 2484101341U, // VFMADDSS4mr >+ 2484101341U, // VFMADDSS4mr_Int >+ 2484101341U, // VFMADDSS4rm >+ 2484101341U, // VFMADDSS4rm_Int >+ 2484101341U, // VFMADDSS4rr >+ 2484101341U, // VFMADDSS4rr_Int >+ 2484101341U, // VFMADDSS4rr_REV >+ 2182105672U, // VFMADDSSZm >+ 2182105672U, // VFMADDSSZr >+ 2182111309U, // VFMADDSSr132m >+ 2182111309U, // VFMADDSSr132r >+ 2182111397U, // VFMADDSSr213m >+ 2182111397U, // VFMADDSSr213r >+ 2182111255U, // VFMADDSSr231m >+ 2182111255U, // VFMADDSSr231r >+ 2182103446U, // VFMADDSUB132PDZm >+ 2182103446U, // VFMADDSUB132PDZmb >+ 2182105150U, // VFMADDSUB132PSZm >+ 2182105150U, // VFMADDSUB132PSZmb >+ 2182103599U, // VFMADDSUB213PDZm >+ 2182103599U, // VFMADDSUB213PDZmb >+ 2182103599U, // VFMADDSUB213PDZr >+ 50348591U, // VFMADDSUB213PDZrk >+ 2197832239U, // VFMADDSUB213PDZrkz >+ 2182105303U, // VFMADDSUB213PSZm >+ 2182105303U, // VFMADDSUB213PSZmb >+ 2182105303U, // VFMADDSUB213PSZr >+ 50350295U, // VFMADDSUB213PSZrk >+ 2197833943U, // VFMADDSUB213PSZrkz >+ 2484097443U, // VFMADDSUBPD4mr >+ 2484097443U, // VFMADDSUBPD4mrY >+ 2484097443U, // VFMADDSUBPD4rm >+ 2484097443U, // VFMADDSUBPD4rmY >+ 2484097443U, // VFMADDSUBPD4rr >+ 2484097443U, // VFMADDSUBPD4rrY >+ 2484097443U, // VFMADDSUBPD4rrY_REV >+ 2484097443U, // VFMADDSUBPD4rr_REV >+ 2182107322U, // VFMADDSUBPDr132m >+ 2182107322U, // VFMADDSUBPDr132mY >+ 2182107322U, // VFMADDSUBPDr132r >+ 2182107322U, // VFMADDSUBPDr132rY >+ 2182107452U, // VFMADDSUBPDr213m >+ 2182107452U, // VFMADDSUBPDr213mY >+ 2182107452U, // VFMADDSUBPDr213r >+ 2182107452U, // VFMADDSUBPDr213rY >+ 2182107236U, // VFMADDSUBPDr231m >+ 2182107236U, // VFMADDSUBPDr231mY >+ 2182107236U, // VFMADDSUBPDr231r >+ 2182107236U, // VFMADDSUBPDr231rY >+ 2484100670U, // VFMADDSUBPS4mr >+ 2484100670U, // VFMADDSUBPS4mrY >+ 2484100670U, // VFMADDSUBPS4rm >+ 2484100670U, // VFMADDSUBPS4rmY >+ 2484100670U, // VFMADDSUBPS4rr >+ 2484100670U, // VFMADDSUBPS4rrY >+ 2484100670U, // VFMADDSUBPS4rrY_REV >+ 2484100670U, // VFMADDSUBPS4rr_REV >+ 2182110546U, // VFMADDSUBPSr132m >+ 2182110546U, // VFMADDSUBPSr132mY >+ 2182110546U, // VFMADDSUBPSr132r >+ 2182110546U, // VFMADDSUBPSr132rY >+ 2182110687U, // VFMADDSUBPSr213m >+ 2182110687U, // VFMADDSUBPSr213mY >+ 2182110687U, // VFMADDSUBPSr213r >+ 2182110687U, // VFMADDSUBPSr213rY >+ 2182110460U, // VFMADDSUBPSr231m >+ 2182110460U, // VFMADDSUBPSr231mY >+ 2182110460U, // VFMADDSUBPSr231r >+ 2182110460U, // VFMADDSUBPSr231rY >+ 2182103463U, // VFMSUB132PDZm >+ 2182103463U, // VFMSUB132PDZmb >+ 2182105167U, // VFMSUB132PSZm >+ 2182105167U, // VFMSUB132PSZmb >+ 2182103616U, // VFMSUB213PDZm >+ 2182103616U, // VFMSUB213PDZmb >+ 2182103616U, // VFMSUB213PDZr >+ 50348608U, // VFMSUB213PDZrk >+ 2197832256U, // VFMSUB213PDZrkz >+ 2182105320U, // VFMSUB213PSZm >+ 2182105320U, // VFMSUB213PSZmb >+ 2182105320U, // VFMSUB213PSZr >+ 50350312U, // VFMSUB213PSZrk >+ 2197833960U, // VFMSUB213PSZrkz >+ 2182103492U, // VFMSUBADD132PDZm >+ 2182103492U, // VFMSUBADD132PDZmb >+ 2182105196U, // VFMSUBADD132PSZm >+ 2182105196U, // VFMSUBADD132PSZmb >+ 2182103645U, // VFMSUBADD213PDZm >+ 2182103645U, // VFMSUBADD213PDZmb >+ 2182103645U, // VFMSUBADD213PDZr >+ 50348637U, // VFMSUBADD213PDZrk >+ 2197832285U, // VFMSUBADD213PDZrkz >+ 2182105349U, // VFMSUBADD213PSZm >+ 2182105349U, // VFMSUBADD213PSZmb >+ 2182105349U, // VFMSUBADD213PSZr >+ 50350341U, // VFMSUBADD213PSZrk >+ 2197833989U, // VFMSUBADD213PSZrkz >+ 2484097505U, // VFMSUBADDPD4mr >+ 2484097505U, // VFMSUBADDPD4mrY >+ 2484097505U, // VFMSUBADDPD4rm >+ 2484097505U, // VFMSUBADDPD4rmY >+ 2484097505U, // VFMSUBADDPD4rr >+ 2484097505U, // VFMSUBADDPD4rrY >+ 2484097505U, // VFMSUBADDPD4rrY_REV >+ 2484097505U, // VFMSUBADDPD4rr_REV >+ 2182107365U, // VFMSUBADDPDr132m >+ 2182107365U, // VFMSUBADDPDr132mY >+ 2182107365U, // VFMSUBADDPDr132r >+ 2182107365U, // VFMSUBADDPDr132rY >+ 2182107495U, // VFMSUBADDPDr213m >+ 2182107495U, // VFMSUBADDPDr213mY >+ 2182107495U, // VFMSUBADDPDr213r >+ 2182107495U, // VFMSUBADDPDr213rY >+ 2182107279U, // VFMSUBADDPDr231m >+ 2182107279U, // VFMSUBADDPDr231mY >+ 2182107279U, // VFMSUBADDPDr231r >+ 2182107279U, // VFMSUBADDPDr231rY >+ 2484100732U, // VFMSUBADDPS4mr >+ 2484100732U, // VFMSUBADDPS4mrY >+ 2484100732U, // VFMSUBADDPS4rm >+ 2484100732U, // VFMSUBADDPS4rmY >+ 2484100732U, // VFMSUBADDPS4rr >+ 2484100732U, // VFMSUBADDPS4rrY >+ 2484100732U, // VFMSUBADDPS4rrY_REV >+ 2484100732U, // VFMSUBADDPS4rr_REV >+ 2182110589U, // VFMSUBADDPSr132m >+ 2182110589U, // VFMSUBADDPSr132mY >+ 2182110589U, // VFMSUBADDPSr132r >+ 2182110589U, // VFMSUBADDPSr132rY >+ 2182110730U, // VFMSUBADDPSr213m >+ 2182110730U, // VFMSUBADDPSr213mY >+ 2182110730U, // VFMSUBADDPSr213r >+ 2182110730U, // VFMSUBADDPSr213rY >+ 2182110503U, // VFMSUBADDPSr231m >+ 2182110503U, // VFMSUBADDPSr231mY >+ 2182110503U, // VFMSUBADDPSr231r >+ 2182110503U, // VFMSUBADDPSr231rY >+ 2484097476U, // VFMSUBPD4mr >+ 2484097476U, // VFMSUBPD4mrY >+ 2484097476U, // VFMSUBPD4rm >+ 2484097476U, // VFMSUBPD4rmY >+ 2484097476U, // VFMSUBPD4rr >+ 2484097476U, // VFMSUBPD4rrY >+ 2484097476U, // VFMSUBPD4rrY_REV >+ 2484097476U, // VFMSUBPD4rr_REV >+ 2182107338U, // VFMSUBPDr132m >+ 2182107338U, // VFMSUBPDr132mY >+ 2182107338U, // VFMSUBPDr132r >+ 2182107338U, // VFMSUBPDr132rY >+ 2182107468U, // VFMSUBPDr213m >+ 2182107468U, // VFMSUBPDr213mY >+ 2182107468U, // VFMSUBPDr213r >+ 2182107468U, // VFMSUBPDr213rY >+ 2182107252U, // VFMSUBPDr231m >+ 2182107252U, // VFMSUBPDr231mY >+ 2182107252U, // VFMSUBPDr231r >+ 2182107252U, // VFMSUBPDr231rY >+ 2484100703U, // VFMSUBPS4mr >+ 2484100703U, // VFMSUBPS4mrY >+ 2484100703U, // VFMSUBPS4rm >+ 2484100703U, // VFMSUBPS4rmY >+ 2484100703U, // VFMSUBPS4rr >+ 2484100703U, // VFMSUBPS4rrY >+ 2484100703U, // VFMSUBPS4rrY_REV >+ 2484100703U, // VFMSUBPS4rr_REV >+ 2182110562U, // VFMSUBPSr132m >+ 2182110562U, // VFMSUBPSr132mY >+ 2182110562U, // VFMSUBPSr132r >+ 2182110562U, // VFMSUBPSr132rY >+ 2182110703U, // VFMSUBPSr213m >+ 2182110703U, // VFMSUBPSr213mY >+ 2182110703U, // VFMSUBPSr213r >+ 2182110703U, // VFMSUBPSr213rY >+ 2182110476U, // VFMSUBPSr231m >+ 2182110476U, // VFMSUBPSr231mY >+ 2182110476U, // VFMSUBPSr231r >+ 2182110476U, // VFMSUBPSr231rY >+ 2484098086U, // VFMSUBSD4mr >+ 2484098086U, // VFMSUBSD4mr_Int >+ 2484098086U, // VFMSUBSD4rm >+ 2484098086U, // VFMSUBSD4rm_Int >+ 2484098086U, // VFMSUBSD4rr >+ 2484098086U, // VFMSUBSD4rr_Int >+ 2484098086U, // VFMSUBSD4rr_REV >+ 2182104040U, // VFMSUBSDZm >+ 2182104040U, // VFMSUBSDZr >+ 2182108048U, // VFMSUBSDr132m >+ 2182108048U, // VFMSUBSDr132r >+ 2182108136U, // VFMSUBSDr213m >+ 2182108136U, // VFMSUBSDr213r >+ 2182107994U, // VFMSUBSDr231m >+ 2182107994U, // VFMSUBSDr231r >+ 2484101312U, // VFMSUBSS4mr >+ 2484101312U, // VFMSUBSS4mr_Int >+ 2484101312U, // VFMSUBSS4rm >+ 2484101312U, // VFMSUBSS4rm_Int >+ 2484101312U, // VFMSUBSS4rr >+ 2484101312U, // VFMSUBSS4rr_Int >+ 2484101312U, // VFMSUBSS4rr_REV >+ 2182105643U, // VFMSUBSSZm >+ 2182105643U, // VFMSUBSSZr >+ 2182111282U, // VFMSUBSSr132m >+ 2182111282U, // VFMSUBSSr132r >+ 2182111370U, // VFMSUBSSr213m >+ 2182111370U, // VFMSUBSSr213r >+ 2182111228U, // VFMSUBSSr231m >+ 2182111228U, // VFMSUBSSr231r >+ 2182103523U, // VFNMADD132PDZm >+ 2182103523U, // VFNMADD132PDZmb >+ 2182105227U, // VFNMADD132PSZm >+ 2182105227U, // VFNMADD132PSZmb >+ 2182103676U, // VFNMADD213PDZm >+ 2182103676U, // VFNMADD213PDZmb >+ 2182103676U, // VFNMADD213PDZr >+ 50348668U, // VFNMADD213PDZrk >+ 2197832316U, // VFNMADD213PDZrkz >+ 2182105380U, // VFNMADD213PSZm >+ 2182105380U, // VFNMADD213PSZmb >+ 2182105380U, // VFNMADD213PSZr >+ 50350372U, // VFNMADD213PSZrk >+ 2197834020U, // VFNMADD213PSZrkz >+ 2484097537U, // VFNMADDPD4mr >+ 2484097537U, // VFNMADDPD4mrY >+ 2484097537U, // VFNMADDPD4rm >+ 2484097537U, // VFNMADDPD4rmY >+ 2484097537U, // VFNMADDPD4rr >+ 2484097537U, // VFNMADDPD4rrY >+ 2484097537U, // VFNMADDPD4rrY_REV >+ 2484097537U, // VFNMADDPD4rr_REV >+ 2182107394U, // VFNMADDPDr132m >+ 2182107394U, // VFNMADDPDr132mY >+ 2182107394U, // VFNMADDPDr132r >+ 2182107394U, // VFNMADDPDr132rY >+ 2182107524U, // VFNMADDPDr213m >+ 2182107524U, // VFNMADDPDr213mY >+ 2182107524U, // VFNMADDPDr213r >+ 2182107524U, // VFNMADDPDr213rY >+ 2182107308U, // VFNMADDPDr231m >+ 2182107308U, // VFNMADDPDr231mY >+ 2182107308U, // VFNMADDPDr231r >+ 2182107308U, // VFNMADDPDr231rY >+ 2484100764U, // VFNMADDPS4mr >+ 2484100764U, // VFNMADDPS4mrY >+ 2484100764U, // VFNMADDPS4rm >+ 2484100764U, // VFNMADDPS4rmY >+ 2484100764U, // VFNMADDPS4rr >+ 2484100764U, // VFNMADDPS4rrY >+ 2484100764U, // VFNMADDPS4rrY_REV >+ 2484100764U, // VFNMADDPS4rr_REV >+ 2182110618U, // VFNMADDPSr132m >+ 2182110618U, // VFNMADDPSr132mY >+ 2182110618U, // VFNMADDPSr132r >+ 2182110618U, // VFNMADDPSr132rY >+ 2182110759U, // VFNMADDPSr213m >+ 2182110759U, // VFNMADDPSr213mY >+ 2182110759U, // VFNMADDPSr213r >+ 2182110759U, // VFNMADDPSr213rY >+ 2182110532U, // VFNMADDPSr231m >+ 2182110532U, // VFNMADDPSr231mY >+ 2182110532U, // VFNMADDPSr231r >+ 2182110532U, // VFNMADDPSr231rY >+ 2484098125U, // VFNMADDSD4mr >+ 2484098125U, // VFNMADDSD4mr_Int >+ 2484098125U, // VFNMADDSD4rm >+ 2484098125U, // VFNMADDSD4rm_Int >+ 2484098125U, // VFNMADDSD4rr >+ 2484098125U, // VFNMADDSD4rr_Int >+ 2484098125U, // VFNMADDSD4rr_REV >+ 2182104083U, // VFNMADDSDZm >+ 2182104083U, // VFNMADDSDZr >+ 2182108088U, // VFNMADDSDr132m >+ 2182108088U, // VFNMADDSDr132r >+ 2182108176U, // VFNMADDSDr213m >+ 2182108176U, // VFNMADDSDr213r >+ 2182108034U, // VFNMADDSDr231m >+ 2182108034U, // VFNMADDSDr231r >+ 2484101351U, // VFNMADDSS4mr >+ 2484101351U, // VFNMADDSS4mr_Int >+ 2484101351U, // VFNMADDSS4rm >+ 2484101351U, // VFNMADDSS4rm_Int >+ 2484101351U, // VFNMADDSS4rr >+ 2484101351U, // VFNMADDSS4rr_Int >+ 2484101351U, // VFNMADDSS4rr_REV >+ 2182105686U, // VFNMADDSSZm >+ 2182105686U, // VFNMADDSSZr >+ 2182111322U, // VFNMADDSSr132m >+ 2182111322U, // VFNMADDSSr132r >+ 2182111410U, // VFNMADDSSr213m >+ 2182111410U, // VFNMADDSSr213r >+ 2182111268U, // VFNMADDSSr231m >+ 2182111268U, // VFNMADDSSr231r >+ 2182103477U, // VFNMSUB132PDZm >+ 2182103477U, // VFNMSUB132PDZmb >+ 2182105181U, // VFNMSUB132PSZm >+ 2182105181U, // VFNMSUB132PSZmb >+ 2182103630U, // VFNMSUB213PDZm >+ 2182103630U, // VFNMSUB213PDZmb >+ 2182103630U, // VFNMSUB213PDZr >+ 50348622U, // VFNMSUB213PDZrk >+ 2197832270U, // VFNMSUB213PDZrkz >+ 2182105334U, // VFNMSUB213PSZm >+ 2182105334U, // VFNMSUB213PSZmb >+ 2182105334U, // VFNMSUB213PSZr >+ 50350326U, // VFNMSUB213PSZrk >+ 2197833974U, // VFNMSUB213PSZrkz >+ 2484097486U, // VFNMSUBPD4mr >+ 2484097486U, // VFNMSUBPD4mrY >+ 2484097486U, // VFNMSUBPD4rm >+ 2484097486U, // VFNMSUBPD4rmY >+ 2484097486U, // VFNMSUBPD4rr >+ 2484097486U, // VFNMSUBPD4rrY >+ 2484097486U, // VFNMSUBPD4rrY_REV >+ 2484097486U, // VFNMSUBPD4rr_REV >+ 2182107351U, // VFNMSUBPDr132m >+ 2182107351U, // VFNMSUBPDr132mY >+ 2182107351U, // VFNMSUBPDr132r >+ 2182107351U, // VFNMSUBPDr132rY >+ 2182107481U, // VFNMSUBPDr213m >+ 2182107481U, // VFNMSUBPDr213mY >+ 2182107481U, // VFNMSUBPDr213r >+ 2182107481U, // VFNMSUBPDr213rY >+ 2182107265U, // VFNMSUBPDr231m >+ 2182107265U, // VFNMSUBPDr231mY >+ 2182107265U, // VFNMSUBPDr231r >+ 2182107265U, // VFNMSUBPDr231rY >+ 2484100713U, // VFNMSUBPS4mr >+ 2484100713U, // VFNMSUBPS4mrY >+ 2484100713U, // VFNMSUBPS4rm >+ 2484100713U, // VFNMSUBPS4rmY >+ 2484100713U, // VFNMSUBPS4rr >+ 2484100713U, // VFNMSUBPS4rrY >+ 2484100713U, // VFNMSUBPS4rrY_REV >+ 2484100713U, // VFNMSUBPS4rr_REV >+ 2182110575U, // VFNMSUBPSr132m >+ 2182110575U, // VFNMSUBPSr132mY >+ 2182110575U, // VFNMSUBPSr132r >+ 2182110575U, // VFNMSUBPSr132rY >+ 2182110716U, // VFNMSUBPSr213m >+ 2182110716U, // VFNMSUBPSr213mY >+ 2182110716U, // VFNMSUBPSr213r >+ 2182110716U, // VFNMSUBPSr213rY >+ 2182110489U, // VFNMSUBPSr231m >+ 2182110489U, // VFNMSUBPSr231mY >+ 2182110489U, // VFNMSUBPSr231r >+ 2182110489U, // VFNMSUBPSr231rY >+ 2484098096U, // VFNMSUBSD4mr >+ 2484098096U, // VFNMSUBSD4mr_Int >+ 2484098096U, // VFNMSUBSD4rm >+ 2484098096U, // VFNMSUBSD4rm_Int >+ 2484098096U, // VFNMSUBSD4rr >+ 2484098096U, // VFNMSUBSD4rr_Int >+ 2484098096U, // VFNMSUBSD4rr_REV >+ 2182104054U, // VFNMSUBSDZm >+ 2182104054U, // VFNMSUBSDZr >+ 2182108061U, // VFNMSUBSDr132m >+ 2182108061U, // VFNMSUBSDr132r >+ 2182108149U, // VFNMSUBSDr213m >+ 2182108149U, // VFNMSUBSDr213r >+ 2182108007U, // VFNMSUBSDr231m >+ 2182108007U, // VFNMSUBSDr231r >+ 2484101322U, // VFNMSUBSS4mr >+ 2484101322U, // VFNMSUBSS4mr_Int >+ 2484101322U, // VFNMSUBSS4rm >+ 2484101322U, // VFNMSUBSS4rm_Int >+ 2484101322U, // VFNMSUBSS4rr >+ 2484101322U, // VFNMSUBSS4rr_Int >+ 2484101322U, // VFNMSUBSS4rr_REV >+ 2182105657U, // VFNMSUBSSZm >+ 2182105657U, // VFNMSUBSSZr >+ 2182111295U, // VFNMSUBSSr132m >+ 2182111295U, // VFNMSUBSSr132r >+ 2182111383U, // VFNMSUBSSr213m >+ 2182111383U, // VFNMSUBSSr213r >+ 2182111241U, // VFNMSUBSSr231m >+ 2182111241U, // VFNMSUBSSr231r >+ 537940771U, // VFRCZPDrm >+ 940593955U, // VFRCZPDrmY >+ 336614179U, // VFRCZPDrr >+ 336614179U, // VFRCZPDrrY >+ 537944051U, // VFRCZPSrm >+ 940597235U, // VFRCZPSrmY >+ 336617459U, // VFRCZPSrr >+ 336617459U, // VFRCZPSrrY >+ 571495654U, // VFRCZSDrm >+ 336614630U, // VFRCZSDrr >+ 605053305U, // VFRCZSSrm >+ 336617849U, // VFRCZSSrr >+ 2484097692U, // VFsANDNPDrm >+ 2484097692U, // VFsANDNPDrr >+ 2484100931U, // VFsANDNPSrm >+ 2484100931U, // VFsANDNPSrr >+ 2484097556U, // VFsANDPDrm >+ 2484097556U, // VFsANDPDrr >+ 2484100783U, // VFsANDPSrm >+ 2484100783U, // VFsANDPSrr >+ 2484097736U, // VFsORPDrm >+ 2484097736U, // VFsORPDrr >+ 2484100983U, // VFsORPSrm >+ 2484100983U, // VFsORPSrr >+ 2484097743U, // VFsXORPDrm >+ 2484097743U, // VFsXORPDrr >+ 2484100990U, // VFsXORPSrm >+ 2484100990U, // VFsXORPSrr >+ 1007702576U, // VGATHERDPDYrm >+ 3204465357U, // VGATHERDPDZrm >+ 1007702576U, // VGATHERDPDrm >+ 1074814667U, // VGATHERDPSYrm >+ 1056983413U, // VGATHERDPSZrm >+ 1074814667U, // VGATHERDPSrm >+ 321941635U, // VGATHERPF0DPDm >+ 321941775U, // VGATHERPF0DPSm >+ 389050569U, // VGATHERPF0QPDm >+ 389050709U, // VGATHERPF0QPSm >+ 321941670U, // VGATHERPF1DPDm >+ 321941810U, // VGATHERPF1DPSm >+ 389050604U, // VGATHERPF1QPDm >+ 389050744U, // VGATHERPF1QPSm >+ 1007702716U, // VGATHERQPDYrm >+ 3204465469U, // VGATHERQPDZrm >+ 1007702716U, // VGATHERQPDrm >+ 1074814827U, // VGATHERQPSYrm >+ 3204467173U, // VGATHERQPSZrm >+ 1074814827U, // VGATHERQPSrm >+ 2484097518U, // VHADDPDYrm >+ 2484097518U, // VHADDPDYrr >+ 2484097518U, // VHADDPDrm >+ 2484097518U, // VHADDPDrr >+ 2484100745U, // VHADDPSYrm >+ 2484100745U, // VHADDPSYrr >+ 2484100745U, // VHADDPSrm >+ 2484100745U, // VHADDPSrr >+ 2484097467U, // VHSUBPDYrm >+ 2484097467U, // VHSUBPDYrr >+ 2484097467U, // VHSUBPDrm >+ 2484097467U, // VHSUBPDrr >+ 2484100694U, // VHSUBPSYrm >+ 2484100694U, // VHSUBPSYrr >+ 2484100694U, // VHSUBPSrm >+ 2484100694U, // VHSUBPSrr >+ 2484096213U, // VINSERTF128rm >+ 2484096213U, // VINSERTF128rr >+ 2484096075U, // VINSERTF32x4rm >+ 2484096075U, // VINSERTF32x4rr >+ 2484096133U, // VINSERTF64x4rm >+ 2484096133U, // VINSERTF64x4rr >+ 2484096268U, // VINSERTI128rm >+ 2484096268U, // VINSERTI128rr >+ 2484096104U, // VINSERTI32x4rm >+ 2484096104U, // VINSERTI32x4rr >+ 2484096162U, // VINSERTI64x4rm >+ 2484096162U, // VINSERTI64x4rr >+ 2484101020U, // VINSERTPSrm >+ 2484101020U, // VINSERTPSrr >+ 2484101020U, // VINSERTPSzrm >+ 2484101020U, // VINSERTPSzrr >+ 839934560U, // VLDDQUYrm >+ 437281376U, // VLDDQUrm >+ 72835U, // VLDMXCSR >+ 336618088U, // VMASKMOVDQU >+ 336618088U, // VMASKMOVDQU64 >+ 2149159695U, // VMASKMOVPDYmr >+ 2484097807U, // VMASKMOVPDYrm >+ 2149126927U, // VMASKMOVPDmr >+ 2484097807U, // VMASKMOVPDrm >+ 2149162975U, // VMASKMOVPSYmr >+ 2484101087U, // VMASKMOVPSYrm >+ 2149130207U, // VMASKMOVPSmr >+ 2484101087U, // VMASKMOVPSrm >+ 2484097819U, // VMAXCPDYrm >+ 2484097819U, // VMAXCPDYrr >+ 2484097819U, // VMAXCPDrm >+ 2484097819U, // VMAXCPDrr >+ 2484101099U, // VMAXCPSYrm >+ 2484101099U, // VMAXCPSYrr >+ 2484101099U, // VMAXCPSrm >+ 2484101099U, // VMAXCPSrr >+ 2484098270U, // VMAXCSDrm >+ 2484098270U, // VMAXCSDrr >+ 2484101489U, // VMAXCSSrm >+ 2484101489U, // VMAXCSSrr >+ 2484097819U, // VMAXPDYrm >+ 2484097819U, // VMAXPDYrr >+ 2484093793U, // VMAXPDZrm >+ 2484093793U, // VMAXPDZrmb >+ 352338785U, // VMAXPDZrmbk >+ 2499822433U, // VMAXPDZrmbkz >+ 352342811U, // VMAXPDZrmk >+ 2499826459U, // VMAXPDZrmkz >+ 2484093793U, // VMAXPDZrr >+ 352338785U, // VMAXPDZrrk >+ 2499822433U, // VMAXPDZrrkz >+ 2484097819U, // VMAXPDrm >+ 2484097819U, // VMAXPDrr >+ 2484101099U, // VMAXPSYrm >+ 2484101099U, // VMAXPSYrr >+ 2484095497U, // VMAXPSZrm >+ 2484095497U, // VMAXPSZrmb >+ 352340489U, // VMAXPSZrmbk >+ 2499824137U, // VMAXPSZrmbkz >+ 352346091U, // VMAXPSZrmk >+ 2499829739U, // VMAXPSZrmkz >+ 2484095497U, // VMAXPSZrr >+ 352340489U, // VMAXPSZrrk >+ 2499824137U, // VMAXPSZrrkz >+ 2484101099U, // VMAXPSrm >+ 2484101099U, // VMAXPSrr >+ 2484098270U, // VMAXSDZrm >+ 2484098270U, // VMAXSDZrr >+ 2484098270U, // VMAXSDrm >+ 2484098270U, // VMAXSDrm_Int >+ 2484098270U, // VMAXSDrr >+ 2484098270U, // VMAXSDrr_Int >+ 2484101489U, // VMAXSSZrm >+ 2484101489U, // VMAXSSZrr >+ 2484101489U, // VMAXSSrm >+ 2484101489U, // VMAXSSrm_Int >+ 2484101489U, // VMAXSSrr >+ 2484101489U, // VMAXSSrr_Int >+ 11646U, // VMCALL >+ 89111U, // VMCLEARm >+ 11314U, // VMFUNC >+ 2484097701U, // VMINCPDYrm >+ 2484097701U, // VMINCPDYrr >+ 2484097701U, // VMINCPDrm >+ 2484097701U, // VMINCPDrr >+ 2484100940U, // VMINCPSYrm >+ 2484100940U, // VMINCPSYrr >+ 2484100940U, // VMINCPSrm >+ 2484100940U, // VMINCPSrr >+ 2484098190U, // VMINCSDrm >+ 2484098190U, // VMINCSDrr >+ 2484101407U, // VMINCSSrm >+ 2484101407U, // VMINCSSrr >+ 2484097701U, // VMINPDYrm >+ 2484097701U, // VMINPDYrr >+ 2484093739U, // VMINPDZrm >+ 2484093739U, // VMINPDZrmb >+ 352338731U, // VMINPDZrmbk >+ 2499822379U, // VMINPDZrmbkz >+ 352342693U, // VMINPDZrmk >+ 2499826341U, // VMINPDZrmkz >+ 2484093739U, // VMINPDZrr >+ 352338731U, // VMINPDZrrk >+ 2499822379U, // VMINPDZrrkz >+ 2484097701U, // VMINPDrm >+ 2484097701U, // VMINPDrr >+ 2484100940U, // VMINPSYrm >+ 2484100940U, // VMINPSYrr >+ 2484095443U, // VMINPSZrm >+ 2484095443U, // VMINPSZrmb >+ 352340435U, // VMINPSZrmbk >+ 2499824083U, // VMINPSZrmbkz >+ 352345932U, // VMINPSZrmk >+ 2499829580U, // VMINPSZrmkz >+ 2484095443U, // VMINPSZrr >+ 352340435U, // VMINPSZrrk >+ 2499824083U, // VMINPSZrrkz >+ 2484100940U, // VMINPSrm >+ 2484100940U, // VMINPSrr >+ 2484098190U, // VMINSDZrm >+ 2484098190U, // VMINSDZrr >+ 2484098190U, // VMINSDrm >+ 2484098190U, // VMINSDrm_Int >+ 2484098190U, // VMINSDrr >+ 2484098190U, // VMINSDrr_Int >+ 2484101407U, // VMINSSZrm >+ 2484101407U, // VMINSSZrr >+ 2484101407U, // VMINSSrm >+ 2484101407U, // VMINSSrm_Int >+ 2484101407U, // VMINSSrr >+ 2484101407U, // VMINSSrr_Int >+ 11561U, // VMLAUNCH >+ 12255U, // VMLOAD32 >+ 12310U, // VMLOAD64 >+ 11638U, // VMMCALL >+ 336616421U, // VMOV64toPQIZrr >+ 336616421U, // VMOV64toPQIrr >+ 336616421U, // VMOV64toSDZrr >+ 370170853U, // VMOV64toSDrm >+ 336616421U, // VMOV64toSDrr >+ 1675666U, // VMOVAPDYmr >+ 940593554U, // VMOVAPDYrm >+ 336613778U, // VMOVAPDYrr >+ 336613778U, // VMOVAPDYrr_REV >+ 1642898U, // VMOVAPDZ128mr >+ 17371538U, // VMOVAPDZ128mrk >+ 537940370U, // VMOVAPDZ128rm >+ 50352530U, // VMOVAPDZ128rmk >+ 2499826066U, // VMOVAPDZ128rmkz >+ 336613778U, // VMOVAPDZ128rr >+ 336613778U, // VMOVAPDZ128rr_alt >+ 50352530U, // VMOVAPDZ128rrk >+ 50352530U, // VMOVAPDZ128rrk_alt >+ 2499826066U, // VMOVAPDZ128rrkz >+ 2499826066U, // VMOVAPDZ128rrkz_alt >+ 1675666U, // VMOVAPDZ256mr >+ 17404306U, // VMOVAPDZ256mrk >+ 940593554U, // VMOVAPDZ256rm >+ 50352530U, // VMOVAPDZ256rmk >+ 2499826066U, // VMOVAPDZ256rmkz >+ 336613778U, // VMOVAPDZ256rr >+ 336613778U, // VMOVAPDZ256rr_alt >+ 50352530U, // VMOVAPDZ256rrk >+ 50352530U, // VMOVAPDZ256rrk_alt >+ 2499826066U, // VMOVAPDZ256rrkz >+ 2499826066U, // VMOVAPDZ256rrkz_alt >+ 1708434U, // VMOVAPDZmr >+ 17437074U, // VMOVAPDZmrk >+ 974147986U, // VMOVAPDZrm >+ 50352530U, // VMOVAPDZrmk >+ 2499826066U, // VMOVAPDZrmkz >+ 336613778U, // VMOVAPDZrr >+ 336613778U, // VMOVAPDZrr_alt >+ 50352530U, // VMOVAPDZrrk >+ 50352530U, // VMOVAPDZrrk_alt >+ 2499826066U, // VMOVAPDZrrkz >+ 2499826066U, // VMOVAPDZrrkz_alt >+ 1642898U, // VMOVAPDmr >+ 537940370U, // VMOVAPDrm >+ 336613778U, // VMOVAPDrr >+ 336613778U, // VMOVAPDrr_REV >+ 1678901U, // VMOVAPSYmr >+ 940596789U, // VMOVAPSYrm >+ 336617013U, // VMOVAPSYrr >+ 336617013U, // VMOVAPSYrr_REV >+ 1646133U, // VMOVAPSZ128mr >+ 17374773U, // VMOVAPSZ128mrk >+ 537943605U, // VMOVAPSZ128rm >+ 50355765U, // VMOVAPSZ128rmk >+ 2499829301U, // VMOVAPSZ128rmkz >+ 336617013U, // VMOVAPSZ128rr >+ 336617013U, // VMOVAPSZ128rr_alt >+ 50355765U, // VMOVAPSZ128rrk >+ 50355765U, // VMOVAPSZ128rrk_alt >+ 2499829301U, // VMOVAPSZ128rrkz >+ 2499829301U, // VMOVAPSZ128rrkz_alt >+ 1678901U, // VMOVAPSZ256mr >+ 17407541U, // VMOVAPSZ256mrk >+ 940596789U, // VMOVAPSZ256rm >+ 50355765U, // VMOVAPSZ256rmk >+ 2499829301U, // VMOVAPSZ256rmkz >+ 336617013U, // VMOVAPSZ256rr >+ 336617013U, // VMOVAPSZ256rr_alt >+ 50355765U, // VMOVAPSZ256rrk >+ 50355765U, // VMOVAPSZ256rrk_alt >+ 2499829301U, // VMOVAPSZ256rrkz >+ 2499829301U, // VMOVAPSZ256rrkz_alt >+ 1711669U, // VMOVAPSZmr >+ 17440309U, // VMOVAPSZmrk >+ 974151221U, // VMOVAPSZrm >+ 50355765U, // VMOVAPSZrmk >+ 2499829301U, // VMOVAPSZrmkz >+ 336617013U, // VMOVAPSZrr >+ 336617013U, // VMOVAPSZrr_alt >+ 50355765U, // VMOVAPSZrrk >+ 50355765U, // VMOVAPSZrrk_alt >+ 2499829301U, // VMOVAPSZrrkz >+ 2499829301U, // VMOVAPSZrrkz_alt >+ 1646133U, // VMOVAPSmr >+ 537943605U, // VMOVAPSrm >+ 336617013U, // VMOVAPSrr >+ 336617013U, // VMOVAPSrr_REV >+ 940595608U, // VMOVDDUPYrm >+ 336615832U, // VMOVDDUPYrr >+ 974144907U, // VMOVDDUPZrm >+ 336610699U, // VMOVDDUPZrr >+ 571496856U, // VMOVDDUPrm >+ 336615832U, // VMOVDDUPrr >+ 303060314U, // VMOVDI2PDIZrm >+ 336614746U, // VMOVDI2PDIZrr >+ 303060314U, // VMOVDI2PDIrm >+ 336614746U, // VMOVDI2PDIrr >+ 303060314U, // VMOVDI2SSZrm >+ 336614746U, // VMOVDI2SSZrr >+ 303060314U, // VMOVDI2SSrm >+ 336614746U, // VMOVDI2SSrr >+ 1313700U, // VMOVDQA32Z128mr >+ 17042340U, // VMOVDQA32Z128mrk >+ 437275556U, // VMOVDQA32Z128rm >+ 50351012U, // VMOVDQA32Z128rmk >+ 2499824548U, // VMOVDQA32Z128rmkz >+ 336612260U, // VMOVDQA32Z128rr >+ 336612260U, // VMOVDQA32Z128rr_alt >+ 50351012U, // VMOVDQA32Z128rrk >+ 50351012U, // VMOVDQA32Z128rrk_alt >+ 2499824548U, // VMOVDQA32Z128rrkz >+ 2499824548U, // VMOVDQA32Z128rrkz_alt >+ 1690532U, // VMOVDQA32Z256mr >+ 17419172U, // VMOVDQA32Z256mrk >+ 839928740U, // VMOVDQA32Z256rm >+ 50351012U, // VMOVDQA32Z256rmk >+ 2499824548U, // VMOVDQA32Z256rmkz >+ 336612260U, // VMOVDQA32Z256rr >+ 336612260U, // VMOVDQA32Z256rr_alt >+ 50351012U, // VMOVDQA32Z256rrk >+ 50351012U, // VMOVDQA32Z256rrk_alt >+ 2499824548U, // VMOVDQA32Z256rrkz >+ 2499824548U, // VMOVDQA32Z256rrkz_alt >+ 1723300U, // VMOVDQA32Zmr >+ 17451940U, // VMOVDQA32Zmrk >+ 907037604U, // VMOVDQA32Zrm >+ 50351012U, // VMOVDQA32Zrmk >+ 2499824548U, // VMOVDQA32Zrmkz >+ 336612260U, // VMOVDQA32Zrr >+ 336612260U, // VMOVDQA32Zrr_alt >+ 50351012U, // VMOVDQA32Zrrk >+ 50351012U, // VMOVDQA32Zrrk_alt >+ 2499824548U, // VMOVDQA32Zrrkz >+ 2499824548U, // VMOVDQA32Zrrkz_alt >+ 1313786U, // VMOVDQA64Z128mr >+ 17042426U, // VMOVDQA64Z128mrk >+ 437275642U, // VMOVDQA64Z128rm >+ 50351098U, // VMOVDQA64Z128rmk >+ 2499824634U, // VMOVDQA64Z128rmkz >+ 336612346U, // VMOVDQA64Z128rr >+ 336612346U, // VMOVDQA64Z128rr_alt >+ 50351098U, // VMOVDQA64Z128rrk >+ 50351098U, // VMOVDQA64Z128rrk_alt >+ 2499824634U, // VMOVDQA64Z128rrkz >+ 2499824634U, // VMOVDQA64Z128rrkz_alt >+ 1690618U, // VMOVDQA64Z256mr >+ 17419258U, // VMOVDQA64Z256mrk >+ 839928826U, // VMOVDQA64Z256rm >+ 50351098U, // VMOVDQA64Z256rmk >+ 2499824634U, // VMOVDQA64Z256rmkz >+ 336612346U, // VMOVDQA64Z256rr >+ 336612346U, // VMOVDQA64Z256rr_alt >+ 50351098U, // VMOVDQA64Z256rrk >+ 50351098U, // VMOVDQA64Z256rrk_alt >+ 2499824634U, // VMOVDQA64Z256rrkz >+ 2499824634U, // VMOVDQA64Z256rrkz_alt >+ 1723386U, // VMOVDQA64Zmr >+ 17452026U, // VMOVDQA64Zmrk >+ 907037690U, // VMOVDQA64Zrm >+ 50351098U, // VMOVDQA64Zrmk >+ 2499824634U, // VMOVDQA64Zrmkz >+ 336612346U, // VMOVDQA64Zrr >+ 336612346U, // VMOVDQA64Zrr_alt >+ 50351098U, // VMOVDQA64Zrrk >+ 50351098U, // VMOVDQA64Zrrk_alt >+ 2499824634U, // VMOVDQA64Zrrkz >+ 2499824634U, // VMOVDQA64Zrrkz_alt >+ 1690951U, // VMOVDQAYmr >+ 839929159U, // VMOVDQAYrm >+ 336612679U, // VMOVDQAYrr >+ 336612679U, // VMOVDQAYrr_REV >+ 1314119U, // VMOVDQAmr >+ 437275975U, // VMOVDQArm >+ 336612679U, // VMOVDQArr >+ 336612679U, // VMOVDQArr_REV >+ 1313968U, // VMOVDQU16Z128mr >+ 17042608U, // VMOVDQU16Z128mrk >+ 437275824U, // VMOVDQU16Z128rm >+ 50351280U, // VMOVDQU16Z128rmk >+ 2499824816U, // VMOVDQU16Z128rmkz >+ 336612528U, // VMOVDQU16Z128rr >+ 336612528U, // VMOVDQU16Z128rr_alt >+ 50351280U, // VMOVDQU16Z128rrk >+ 50351280U, // VMOVDQU16Z128rrk_alt >+ 2499824816U, // VMOVDQU16Z128rrkz >+ 2499824816U, // VMOVDQU16Z128rrkz_alt >+ 1690800U, // VMOVDQU16Z256mr >+ 17419440U, // VMOVDQU16Z256mrk >+ 839929008U, // VMOVDQU16Z256rm >+ 50351280U, // VMOVDQU16Z256rmk >+ 2499824816U, // VMOVDQU16Z256rmkz >+ 336612528U, // VMOVDQU16Z256rr >+ 336612528U, // VMOVDQU16Z256rr_alt >+ 50351280U, // VMOVDQU16Z256rrk >+ 50351280U, // VMOVDQU16Z256rrk_alt >+ 2499824816U, // VMOVDQU16Z256rrkz >+ 2499824816U, // VMOVDQU16Z256rrkz_alt >+ 1723568U, // VMOVDQU16Zmr >+ 17452208U, // VMOVDQU16Zmrk >+ 907037872U, // VMOVDQU16Zrm >+ 50351280U, // VMOVDQU16Zrmk >+ 2499824816U, // VMOVDQU16Zrmkz >+ 336612528U, // VMOVDQU16Zrr >+ 336612528U, // VMOVDQU16Zrr_alt >+ 50351280U, // VMOVDQU16Zrrk >+ 50351280U, // VMOVDQU16Zrrk_alt >+ 2499824816U, // VMOVDQU16Zrrkz >+ 2499824816U, // VMOVDQU16Zrrkz_alt >+ 1313718U, // VMOVDQU32Z128mr >+ 17042358U, // VMOVDQU32Z128mrk >+ 437275574U, // VMOVDQU32Z128rm >+ 50351030U, // VMOVDQU32Z128rmk >+ 2499824566U, // VMOVDQU32Z128rmkz >+ 336612278U, // VMOVDQU32Z128rr >+ 336612278U, // VMOVDQU32Z128rr_alt >+ 50351030U, // VMOVDQU32Z128rrk >+ 50351030U, // VMOVDQU32Z128rrk_alt >+ 2499824566U, // VMOVDQU32Z128rrkz >+ 2499824566U, // VMOVDQU32Z128rrkz_alt >+ 1690550U, // VMOVDQU32Z256mr >+ 17419190U, // VMOVDQU32Z256mrk >+ 839928758U, // VMOVDQU32Z256rm >+ 50351030U, // VMOVDQU32Z256rmk >+ 2499824566U, // VMOVDQU32Z256rmkz >+ 336612278U, // VMOVDQU32Z256rr >+ 336612278U, // VMOVDQU32Z256rr_alt >+ 50351030U, // VMOVDQU32Z256rrk >+ 50351030U, // VMOVDQU32Z256rrk_alt >+ 2499824566U, // VMOVDQU32Z256rrkz >+ 2499824566U, // VMOVDQU32Z256rrkz_alt >+ 1723318U, // VMOVDQU32Zmr >+ 17451958U, // VMOVDQU32Zmrk >+ 907037622U, // VMOVDQU32Zrm >+ 50351030U, // VMOVDQU32Zrmk >+ 2499824566U, // VMOVDQU32Zrmkz >+ 336612278U, // VMOVDQU32Zrr >+ 336612278U, // VMOVDQU32Zrr_alt >+ 50351030U, // VMOVDQU32Zrrk >+ 50351030U, // VMOVDQU32Zrrk_alt >+ 2499824566U, // VMOVDQU32Zrrkz >+ 2499824566U, // VMOVDQU32Zrrkz_alt >+ 1313830U, // VMOVDQU64Z128mr >+ 17042470U, // VMOVDQU64Z128mrk >+ 437275686U, // VMOVDQU64Z128rm >+ 50351142U, // VMOVDQU64Z128rmk >+ 2499824678U, // VMOVDQU64Z128rmkz >+ 336612390U, // VMOVDQU64Z128rr >+ 336612390U, // VMOVDQU64Z128rr_alt >+ 50351142U, // VMOVDQU64Z128rrk >+ 50351142U, // VMOVDQU64Z128rrk_alt >+ 2499824678U, // VMOVDQU64Z128rrkz >+ 2499824678U, // VMOVDQU64Z128rrkz_alt >+ 1690662U, // VMOVDQU64Z256mr >+ 17419302U, // VMOVDQU64Z256mrk >+ 839928870U, // VMOVDQU64Z256rm >+ 50351142U, // VMOVDQU64Z256rmk >+ 2499824678U, // VMOVDQU64Z256rmkz >+ 336612390U, // VMOVDQU64Z256rr >+ 336612390U, // VMOVDQU64Z256rr_alt >+ 50351142U, // VMOVDQU64Z256rrk >+ 50351142U, // VMOVDQU64Z256rrk_alt >+ 2499824678U, // VMOVDQU64Z256rrkz >+ 2499824678U, // VMOVDQU64Z256rrkz_alt >+ 1723430U, // VMOVDQU64Zmr >+ 17452070U, // VMOVDQU64Zmrk >+ 907037734U, // VMOVDQU64Zrm >+ 50351142U, // VMOVDQU64Zrmk >+ 2499824678U, // VMOVDQU64Zrmkz >+ 336612390U, // VMOVDQU64Zrr >+ 336612390U, // VMOVDQU64Zrr_alt >+ 50351142U, // VMOVDQU64Zrrk >+ 50351142U, // VMOVDQU64Zrrk_alt >+ 2499824678U, // VMOVDQU64Zrrkz >+ 2499824678U, // VMOVDQU64Zrrkz_alt >+ 1314089U, // VMOVDQU8Z128mr >+ 17042729U, // VMOVDQU8Z128mrk >+ 437275945U, // VMOVDQU8Z128rm >+ 50351401U, // VMOVDQU8Z128rmk >+ 2499824937U, // VMOVDQU8Z128rmkz >+ 336612649U, // VMOVDQU8Z128rr >+ 336612649U, // VMOVDQU8Z128rr_alt >+ 50351401U, // VMOVDQU8Z128rrk >+ 50351401U, // VMOVDQU8Z128rrk_alt >+ 2499824937U, // VMOVDQU8Z128rrkz >+ 2499824937U, // VMOVDQU8Z128rrkz_alt >+ 1690921U, // VMOVDQU8Z256mr >+ 17419561U, // VMOVDQU8Z256mrk >+ 839929129U, // VMOVDQU8Z256rm >+ 50351401U, // VMOVDQU8Z256rmk >+ 2499824937U, // VMOVDQU8Z256rmkz >+ 336612649U, // VMOVDQU8Z256rr >+ 336612649U, // VMOVDQU8Z256rr_alt >+ 50351401U, // VMOVDQU8Z256rrk >+ 50351401U, // VMOVDQU8Z256rrk_alt >+ 2499824937U, // VMOVDQU8Z256rrkz >+ 2499824937U, // VMOVDQU8Z256rrkz_alt >+ 1723689U, // VMOVDQU8Zmr >+ 17452329U, // VMOVDQU8Zmrk >+ 907037993U, // VMOVDQU8Zrm >+ 50351401U, // VMOVDQU8Zrmk >+ 2499824937U, // VMOVDQU8Zrmkz >+ 336612649U, // VMOVDQU8Zrr >+ 336612649U, // VMOVDQU8Zrr_alt >+ 50351401U, // VMOVDQU8Zrrk >+ 50351401U, // VMOVDQU8Zrrk_alt >+ 2499824937U, // VMOVDQU8Zrrkz >+ 2499824937U, // VMOVDQU8Zrrkz_alt >+ 1696373U, // VMOVDQUYmr >+ 839934581U, // VMOVDQUYrm >+ 336618101U, // VMOVDQUYrr >+ 336618101U, // VMOVDQUYrr_REV >+ 1319541U, // VMOVDQUmr >+ 437281397U, // VMOVDQUrm >+ 336618101U, // VMOVDQUrr >+ 336618101U, // VMOVDQUrr_REV >+ 2484100873U, // VMOVHLPSZrr >+ 2484100873U, // VMOVHLPSrr >+ 1184336U, // VMOVHPDmr >+ 2484097616U, // VMOVHPDrm >+ 1187573U, // VMOVHPSmr >+ 2484100853U, // VMOVHPSrm >+ 2484100843U, // VMOVLHPSZrr >+ 2484100843U, // VMOVLHPSrr >+ 1184386U, // VMOVLPDmr >+ 2484097666U, // VMOVLPDrm >+ 1187633U, // VMOVLPSmr >+ 2484100913U, // VMOVLPSrm >+ 336613977U, // VMOVMSKPDYrr >+ 336613977U, // VMOVMSKPDrr >+ 336617214U, // VMOVMSKPSYrr >+ 336617214U, // VMOVMSKPSrr >+ 839929148U, // VMOVNTDQAYrm >+ 437275964U, // VMOVNTDQAZ128rm >+ 839929148U, // VMOVNTDQAZ256rm >+ 907038012U, // VMOVNTDQAZrm >+ 437275964U, // VMOVNTDQArm >+ 1678034U, // VMOVNTDQYmr >+ 1317586U, // VMOVNTDQZ128mr >+ 1694418U, // VMOVNTDQZ256mr >+ 1727186U, // VMOVNTDQZmr >+ 1645266U, // VMOVNTDQmr >+ 1675991U, // VMOVNTPDYmr >+ 1643223U, // VMOVNTPDZ128mr >+ 1675991U, // VMOVNTPDZ256mr >+ 1708759U, // VMOVNTPDZmr >+ 1643223U, // VMOVNTPDmr >+ 1679250U, // VMOVNTPSYmr >+ 1646482U, // VMOVNTPSZ128mr >+ 1679250U, // VMOVNTPSZ256mr >+ 1712018U, // VMOVNTPSZmr >+ 1646482U, // VMOVNTPSmr >+ 1119578U, // VMOVPDI2DIZmr >+ 336614746U, // VMOVPDI2DIZrr >+ 1119578U, // VMOVPDI2DImr >+ 336614746U, // VMOVPDI2DIrr >+ 1137637U, // VMOVPQI2QImr >+ 336616421U, // VMOVPQI2QIrr >+ 1137637U, // VMOVPQIto64Zmr >+ 336616421U, // VMOVPQIto64Zrr >+ 336616421U, // VMOVPQIto64rr >+ 370170853U, // VMOVQI2PQIZrm >+ 370170853U, // VMOVQI2PQIrm >+ 1180802U, // VMOVSDZmr >+ 571491458U, // VMOVSDZrm >+ 2484094082U, // VMOVSDZrr >+ 2484098253U, // VMOVSDZrr_REV >+ 50349186U, // VMOVSDZrrk >+ 1184973U, // VMOVSDmr >+ 571495629U, // VMOVSDrm >+ 2484098253U, // VMOVSDrr >+ 2484098253U, // VMOVSDrr_REV >+ 1137637U, // VMOVSDto64Zmr >+ 336616421U, // VMOVSDto64Zrr >+ 1137637U, // VMOVSDto64mr >+ 336616421U, // VMOVSDto64rr >+ 940595618U, // VMOVSHDUPYrm >+ 336615842U, // VMOVSHDUPYrr >+ 974144918U, // VMOVSHDUPZrm >+ 336610710U, // VMOVSHDUPZrr >+ 537942434U, // VMOVSHDUPrm >+ 336615842U, // VMOVSHDUPrr >+ 940595629U, // VMOVSLDUPYrm >+ 336615853U, // VMOVSLDUPYrr >+ 974144930U, // VMOVSLDUPZrm >+ 336610722U, // VMOVSLDUPZrr >+ 537942445U, // VMOVSLDUPrm >+ 336615853U, // VMOVSLDUPrr >+ 1119578U, // VMOVSS2DIZmr >+ 336614746U, // VMOVSS2DIZrr >+ 1119578U, // VMOVSS2DImr >+ 336614746U, // VMOVSS2DIrr >+ 1166002U, // VMOVSSZmr >+ 605047474U, // VMOVSSZrm >+ 2484095666U, // VMOVSSZrr >+ 2484101481U, // VMOVSSZrr_REV >+ 50350770U, // VMOVSSZrrk >+ 1171817U, // VMOVSSmr >+ 605053289U, // VMOVSSrm >+ 2484101481U, // VMOVSSrr >+ 2484101481U, // VMOVSSrr_REV >+ 1676019U, // VMOVUPDYmr >+ 940593907U, // VMOVUPDYrm >+ 336614131U, // VMOVUPDYrr >+ 336614131U, // VMOVUPDYrr_REV >+ 1643251U, // VMOVUPDZ128mr >+ 17371891U, // VMOVUPDZ128mrk >+ 537940723U, // VMOVUPDZ128rm >+ 50352883U, // VMOVUPDZ128rmk >+ 2499826419U, // VMOVUPDZ128rmkz >+ 336614131U, // VMOVUPDZ128rr >+ 336614131U, // VMOVUPDZ128rr_alt >+ 50352883U, // VMOVUPDZ128rrk >+ 50352883U, // VMOVUPDZ128rrk_alt >+ 2499826419U, // VMOVUPDZ128rrkz >+ 2499826419U, // VMOVUPDZ128rrkz_alt >+ 1676019U, // VMOVUPDZ256mr >+ 17404659U, // VMOVUPDZ256mrk >+ 940593907U, // VMOVUPDZ256rm >+ 50352883U, // VMOVUPDZ256rmk >+ 2499826419U, // VMOVUPDZ256rmkz >+ 336614131U, // VMOVUPDZ256rr >+ 336614131U, // VMOVUPDZ256rr_alt >+ 50352883U, // VMOVUPDZ256rrk >+ 50352883U, // VMOVUPDZ256rrk_alt >+ 2499826419U, // VMOVUPDZ256rrkz >+ 2499826419U, // VMOVUPDZ256rrkz_alt >+ 1708787U, // VMOVUPDZmr >+ 17437427U, // VMOVUPDZmrk >+ 974148339U, // VMOVUPDZrm >+ 50352883U, // VMOVUPDZrmk >+ 2499826419U, // VMOVUPDZrmkz >+ 336614131U, // VMOVUPDZrr >+ 336614131U, // VMOVUPDZrr_alt >+ 50352883U, // VMOVUPDZrrk >+ 50352883U, // VMOVUPDZrrk_alt >+ 2499826419U, // VMOVUPDZrrkz >+ 2499826419U, // VMOVUPDZrrkz_alt >+ 1643251U, // VMOVUPDmr >+ 537940723U, // VMOVUPDrm >+ 336614131U, // VMOVUPDrr >+ 336614131U, // VMOVUPDrr_REV >+ 1679299U, // VMOVUPSYmr >+ 940597187U, // VMOVUPSYrm >+ 336617411U, // VMOVUPSYrr >+ 336617411U, // VMOVUPSYrr_REV >+ 1646531U, // VMOVUPSZ128mr >+ 17375171U, // VMOVUPSZ128mrk >+ 537944003U, // VMOVUPSZ128rm >+ 50356163U, // VMOVUPSZ128rmk >+ 2499829699U, // VMOVUPSZ128rmkz >+ 336617411U, // VMOVUPSZ128rr >+ 336617411U, // VMOVUPSZ128rr_alt >+ 50356163U, // VMOVUPSZ128rrk >+ 50356163U, // VMOVUPSZ128rrk_alt >+ 2499829699U, // VMOVUPSZ128rrkz >+ 2499829699U, // VMOVUPSZ128rrkz_alt >+ 1679299U, // VMOVUPSZ256mr >+ 17407939U, // VMOVUPSZ256mrk >+ 940597187U, // VMOVUPSZ256rm >+ 50356163U, // VMOVUPSZ256rmk >+ 2499829699U, // VMOVUPSZ256rmkz >+ 336617411U, // VMOVUPSZ256rr >+ 336617411U, // VMOVUPSZ256rr_alt >+ 50356163U, // VMOVUPSZ256rrk >+ 50356163U, // VMOVUPSZ256rrk_alt >+ 2499829699U, // VMOVUPSZ256rrkz >+ 2499829699U, // VMOVUPSZ256rrkz_alt >+ 1712067U, // VMOVUPSZmr >+ 17440707U, // VMOVUPSZmrk >+ 974151619U, // VMOVUPSZrm >+ 50356163U, // VMOVUPSZrmk >+ 2499829699U, // VMOVUPSZrmkz >+ 336617411U, // VMOVUPSZrr >+ 336617411U, // VMOVUPSZrr_alt >+ 50356163U, // VMOVUPSZrrk >+ 50356163U, // VMOVUPSZrrk_alt >+ 2499829699U, // VMOVUPSZrrkz >+ 2499829699U, // VMOVUPSZrrkz_alt >+ 1646531U, // VMOVUPSmr >+ 537944003U, // VMOVUPSrm >+ 336617411U, // VMOVUPSrr >+ 336617411U, // VMOVUPSrr_REV >+ 437279717U, // VMOVZPQILo2PQIZrm >+ 336616421U, // VMOVZPQILo2PQIZrr >+ 437279717U, // VMOVZPQILo2PQIrm >+ 336616421U, // VMOVZPQILo2PQIrr >+ 370170853U, // VMOVZQI2PQIrm >+ 336616421U, // VMOVZQI2PQIrr >+ 2484101822U, // VMPSADBWYrmi >+ 2484101822U, // VMPSADBWYrri >+ 2484101822U, // VMPSADBWrmi >+ 2484101822U, // VMPSADBWrri >+ 86060U, // VMPTRLDm >+ 90700U, // VMPTRSTm >+ 1117989U, // VMREAD32rm >+ 336613157U, // VMREAD32rr >+ 1134373U, // VMREAD64rm >+ 336613157U, // VMREAD64rr >+ 11440U, // VMRESUME >+ 12277U, // VMRUN32 >+ 12332U, // VMRUN64 >+ 12266U, // VMSAVE32 >+ 12321U, // VMSAVE64 >+ 2484097658U, // VMULPDYrm >+ 2484097658U, // VMULPDYrr >+ 2484093708U, // VMULPDZrm >+ 2484093708U, // VMULPDZrmb >+ 352338700U, // VMULPDZrmbk >+ 2499822348U, // VMULPDZrmbkz >+ 352342650U, // VMULPDZrmk >+ 2499826298U, // VMULPDZrmkz >+ 2484093708U, // VMULPDZrr >+ 352338700U, // VMULPDZrrk >+ 2499822348U, // VMULPDZrrkz >+ 2484097658U, // VMULPDrm >+ 2484097658U, // VMULPDrr >+ 2484100905U, // VMULPSYrm >+ 2484100905U, // VMULPSYrr >+ 2484095412U, // VMULPSZrm >+ 2484095412U, // VMULPSZrmb >+ 352340404U, // VMULPSZrmbk >+ 2499824052U, // VMULPSZrmbkz >+ 352345897U, // VMULPSZrmk >+ 2499829545U, // VMULPSZrmkz >+ 2484095412U, // VMULPSZrr >+ 352340404U, // VMULPSZrrk >+ 2499824052U, // VMULPSZrrkz >+ 2484100905U, // VMULPSrm >+ 2484100905U, // VMULPSrr >+ 2484098173U, // VMULSDZrm >+ 2484098173U, // VMULSDZrr >+ 2484098173U, // VMULSDrm >+ 2484098173U, // VMULSDrm_Int >+ 2484098173U, // VMULSDrr >+ 2484098173U, // VMULSDrr_Int >+ 2484101399U, // VMULSSZrm >+ 2484101399U, // VMULSSZrr >+ 2484101399U, // VMULSSrm >+ 2484101399U, // VMULSSrm_Int >+ 2484101399U, // VMULSSrr >+ 2484101399U, // VMULSSrr_Int >+ 303060650U, // VMWRITE32rm >+ 336615082U, // VMWRITE32rr >+ 370169514U, // VMWRITE64rm >+ 336615082U, // VMWRITE64rr >+ 11528U, // VMXOFF >+ 88263U, // VMXON >+ 2484097736U, // VORPDYrm >+ 2484097736U, // VORPDYrr >+ 2484097736U, // VORPDrm >+ 2484097736U, // VORPDrr >+ 2484100983U, // VORPSYrm >+ 2484100983U, // VORPSYrr >+ 2484100983U, // VORPSrm >+ 2484100983U, // VORPSrr >+ 437276147U, // VPABSBrm128 >+ 839929331U, // VPABSBrm256 >+ 336612851U, // VPABSBrr128 >+ 336612851U, // VPABSBrr256 >+ 907035730U, // VPABSDZrm >+ 2450539602U, // VPABSDZrmb >+ 352339026U, // VPABSDZrmbk >+ 2499822674U, // VPABSDZrmbkz >+ 352339026U, // VPABSDZrmk >+ 2499822674U, // VPABSDZrmkz >+ 336610386U, // VPABSDZrr >+ 352339026U, // VPABSDZrrk >+ 2499822674U, // VPABSDZrrkz >+ 437277726U, // VPABSDrm128 >+ 839930910U, // VPABSDrm256 >+ 336614430U, // VPABSDrr128 >+ 336614430U, // VPABSDrr256 >+ 907036575U, // VPABSQZrm >+ 370165663U, // VPABSQZrmb >+ 352339871U, // VPABSQZrmbk >+ 2499823519U, // VPABSQZrmbkz >+ 352339871U, // VPABSQZrmk >+ 2499823519U, // VPABSQZrmkz >+ 336611231U, // VPABSQZrr >+ 352339871U, // VPABSQZrrk >+ 2499823519U, // VPABSQZrrkz >+ 437281800U, // VPABSWrm128 >+ 839934984U, // VPABSWrm256 >+ 336618504U, // VPABSWrr128 >+ 336618504U, // VPABSWrr256 >+ 2484101967U, // VPACKSSDWYrm >+ 2484101967U, // VPACKSSDWYrr >+ 2484101967U, // VPACKSSDWrm >+ 2484101967U, // VPACKSSDWrr >+ 2484096690U, // VPACKSSWBYrm >+ 2484096690U, // VPACKSSWBYrr >+ 2484096690U, // VPACKSSWBrm >+ 2484096690U, // VPACKSSWBrr >+ 2484101978U, // VPACKUSDWYrm >+ 2484101978U, // VPACKUSDWYrr >+ 2484101978U, // VPACKUSDWrm >+ 2484101978U, // VPACKUSDWrr >+ 2484096701U, // VPACKUSWBYrm >+ 2484096701U, // VPACKUSWBYrr >+ 2484096701U, // VPACKUSWBrm >+ 2484096701U, // VPACKUSWBrr >+ 2484096406U, // VPADDBYrm >+ 2484096406U, // VPADDBYrr >+ 2484096406U, // VPADDBrm >+ 2484096406U, // VPADDBrr >+ 2484096918U, // VPADDDYrm >+ 2484096918U, // VPADDDYrr >+ 2484093170U, // VPADDDZrm >+ 2484093170U, // VPADDDZrmb >+ 50348274U, // VPADDDZrmbk >+ 2499821810U, // VPADDDZrmbkz >+ 50348274U, // VPADDDZrmk >+ 2499821810U, // VPADDDZrmkz >+ 2484093170U, // VPADDDZrr >+ 50348274U, // VPADDDZrrk >+ 2499821810U, // VPADDDZrrkz >+ 2484096918U, // VPADDDrm >+ 2484096918U, // VPADDDrr >+ 2484099675U, // VPADDQYrm >+ 2484099675U, // VPADDQYrr >+ 2484094514U, // VPADDQZrm >+ 2484094514U, // VPADDQZrmb >+ 50349618U, // VPADDQZrmbk >+ 2499823154U, // VPADDQZrmbkz >+ 50349618U, // VPADDQZrmk >+ 2499823154U, // VPADDQZrmkz >+ 2484094514U, // VPADDQZrr >+ 50349618U, // VPADDQZrrk >+ 2499823154U, // VPADDQZrrkz >+ 2484099675U, // VPADDQrm >+ 2484099675U, // VPADDQrr >+ 2484096516U, // VPADDSBYrm >+ 2484096516U, // VPADDSBYrr >+ 2484096516U, // VPADDSBrm >+ 2484096516U, // VPADDSBrr >+ 2484102201U, // VPADDSWYrm >+ 2484102201U, // VPADDSWYrr >+ 2484102201U, // VPADDSWrm >+ 2484102201U, // VPADDSWrr >+ 2484096558U, // VPADDUSBYrm >+ 2484096558U, // VPADDUSBYrr >+ 2484096558U, // VPADDUSBrm >+ 2484096558U, // VPADDUSBrr >+ 2484102274U, // VPADDUSWYrm >+ 2484102274U, // VPADDUSWYrr >+ 2484102274U, // VPADDUSWrm >+ 2484102274U, // VPADDUSWrr >+ 2484101949U, // VPADDWYrm >+ 2484101949U, // VPADDWYrr >+ 2484101949U, // VPADDWrm >+ 2484101949U, // VPADDWrr >+ 2484100171U, // VPALIGNR128rm >+ 2484100171U, // VPALIGNR128rr >+ 2484100171U, // VPALIGNR256rm >+ 2484100171U, // VPALIGNR256rr >+ 2484093187U, // VPANDDZrm >+ 2484093187U, // VPANDDZrmb >+ 50348291U, // VPANDDZrmbk >+ 2499821827U, // VPANDDZrmbkz >+ 50348291U, // VPANDDZrmk >+ 2499821827U, // VPANDDZrmkz >+ 2484093187U, // VPANDDZrr >+ 50348291U, // VPANDDZrrk >+ 2499821827U, // VPANDDZrrkz >+ 2484093314U, // VPANDNDZrm >+ 2484093314U, // VPANDNDZrmb >+ 50348418U, // VPANDNDZrmbk >+ 2499821954U, // VPANDNDZrmbkz >+ 50348418U, // VPANDNDZrmk >+ 2499821954U, // VPANDNDZrmkz >+ 2484093314U, // VPANDNDZrr >+ 50348418U, // VPANDNDZrrk >+ 2499821954U, // VPANDNDZrrkz >+ 2484094791U, // VPANDNQZrm >+ 2484094791U, // VPANDNQZrmb >+ 50349895U, // VPANDNQZrmbk >+ 2499823431U, // VPANDNQZrmbkz >+ 50349895U, // VPANDNQZrmk >+ 2499823431U, // VPANDNQZrmkz >+ 2484094791U, // VPANDNQZrr >+ 50349895U, // VPANDNQZrrk >+ 2499823431U, // VPANDNQZrrkz >+ 2484099248U, // VPANDNYrm >+ 2484099248U, // VPANDNYrr >+ 2484099248U, // VPANDNrm >+ 2484099248U, // VPANDNrr >+ 2484094567U, // VPANDQZrm >+ 2484094567U, // VPANDQZrmb >+ 50349671U, // VPANDQZrmbk >+ 2499823207U, // VPANDQZrmbkz >+ 50349671U, // VPANDQZrmk >+ 2499823207U, // VPANDQZrmkz >+ 2484094567U, // VPANDQZrr >+ 50349671U, // VPANDQZrrk >+ 2499823207U, // VPANDQZrrkz >+ 2484097093U, // VPANDYrm >+ 2484097093U, // VPANDYrr >+ 2484097093U, // VPANDrm >+ 2484097093U, // VPANDrr >+ 2484096423U, // VPAVGBYrm >+ 2484096423U, // VPAVGBYrr >+ 2484096423U, // VPAVGBrm >+ 2484096423U, // VPAVGBrr >+ 2484102004U, // VPAVGWYrm >+ 2484102004U, // VPAVGWYrr >+ 2484102004U, // VPAVGWrm >+ 2484102004U, // VPAVGWrr >+ 2484096926U, // VPBLENDDYrmi >+ 2484096926U, // VPBLENDDYrri >+ 2484096926U, // VPBLENDDrmi >+ 2484096926U, // VPBLENDDrri >+ 352338253U, // VPBLENDMDZrm >+ 352338253U, // VPBLENDMDZrr >+ 352339730U, // VPBLENDMQZrm >+ 352339730U, // VPBLENDMQZrr >+ 2484096672U, // VPBLENDVBYrm >+ 2484096672U, // VPBLENDVBYrr >+ 2484096672U, // VPBLENDVBrm >+ 2484096672U, // VPBLENDVBrr >+ 2484101957U, // VPBLENDWYrmi >+ 2484101957U, // VPBLENDWYrri >+ 2484101957U, // VPBLENDWrmi >+ 2484101957U, // VPBLENDWrri >+ 504385129U, // VPBROADCASTBYrm >+ 336612969U, // VPBROADCASTBYrr >+ 504385129U, // VPBROADCASTBrm >+ 336612969U, // VPBROADCASTBrr >+ 303060225U, // VPBROADCASTDYrm >+ 336614657U, // VPBROADCASTDYrr >+ 2499822774U, // VPBROADCASTDZkrm >+ 2499822774U, // VPBROADCASTDZkrr >+ 303056054U, // VPBROADCASTDZrm >+ 336610486U, // VPBROADCASTDZrr >+ 2499822774U, // VPBROADCASTDrZkrr >+ 336610486U, // VPBROADCASTDrZrr >+ 303060225U, // VPBROADCASTDrm >+ 336614657U, // VPBROADCASTDrr >+ 336610734U, // VPBROADCASTMB2Qrr >+ 336609462U, // VPBROADCASTMW2Drr >+ 370170791U, // VPBROADCASTQYrm >+ 336616359U, // VPBROADCASTQYrr >+ 2499823581U, // VPBROADCASTQZkrm >+ 2499823581U, // VPBROADCASTQZkrr >+ 370165725U, // VPBROADCASTQZrm >+ 336611293U, // VPBROADCASTQZrr >+ 2499823581U, // VPBROADCASTQrZkrr >+ 336611293U, // VPBROADCASTQrZrr >+ 370170791U, // VPBROADCASTQrm >+ 336616359U, // VPBROADCASTQrr >+ 470836398U, // VPBROADCASTWYrm >+ 336618670U, // VPBROADCASTWYrr >+ 470836398U, // VPBROADCASTWrm >+ 336618670U, // VPBROADCASTWrr >+ 2484099770U, // VPCLMULQDQrm >+ 2484099770U, // VPCLMULQDQrr >+ 2484101788U, // VPCMOVmr >+ 2484101788U, // VPCMOVmrY >+ 2484101788U, // VPCMOVrm >+ 2484101788U, // VPCMOVrmY >+ 2484101788U, // VPCMOVrr >+ 2484101788U, // VPCMOVrrY >+ 1128623605U, // VPCMPDZrmi >+ 2484097675U, // VPCMPDZrmi_alt >+ 352342667U, // VPCMPDZrmik_alt >+ 54898165U, // VPCMPDZrri >+ 2484097675U, // VPCMPDZrri_alt >+ 352342667U, // VPCMPDZrrik_alt >+ 2484096471U, // VPCMPEQBYrm >+ 2484096471U, // VPCMPEQBYrr >+ 2484096471U, // VPCMPEQBZ128rm >+ 352341463U, // VPCMPEQBZ128rmk >+ 2484096471U, // VPCMPEQBZ128rr >+ 352341463U, // VPCMPEQBZ128rrk >+ 2484096471U, // VPCMPEQBZ256rm >+ 352341463U, // VPCMPEQBZ256rmk >+ 2484096471U, // VPCMPEQBZ256rr >+ 352341463U, // VPCMPEQBZ256rrk >+ 2484096471U, // VPCMPEQBZrm >+ 352341463U, // VPCMPEQBZrmk >+ 2484096471U, // VPCMPEQBZrr >+ 352341463U, // VPCMPEQBZrrk >+ 2484096471U, // VPCMPEQBrm >+ 2484096471U, // VPCMPEQBrr >+ 2484097836U, // VPCMPEQDYrm >+ 2484097836U, // VPCMPEQDYrr >+ 2484097836U, // VPCMPEQDZ128rm >+ 2484097836U, // VPCMPEQDZ128rmb >+ 352342828U, // VPCMPEQDZ128rmbk >+ 352342828U, // VPCMPEQDZ128rmk >+ 2484097836U, // VPCMPEQDZ128rr >+ 352342828U, // VPCMPEQDZ128rrk >+ 2484097836U, // VPCMPEQDZ256rm >+ 2484097836U, // VPCMPEQDZ256rmb >+ 352342828U, // VPCMPEQDZ256rmbk >+ 352342828U, // VPCMPEQDZ256rmk >+ 2484097836U, // VPCMPEQDZ256rr >+ 352342828U, // VPCMPEQDZ256rrk >+ 2484097836U, // VPCMPEQDZrm >+ 2484097836U, // VPCMPEQDZrmb >+ 352342828U, // VPCMPEQDZrmbk >+ 352342828U, // VPCMPEQDZrmk >+ 2484097836U, // VPCMPEQDZrr >+ 352342828U, // VPCMPEQDZrrk >+ 2484097836U, // VPCMPEQDrm >+ 2484097836U, // VPCMPEQDrr >+ 2484099911U, // VPCMPEQQYrm >+ 2484099911U, // VPCMPEQQYrr >+ 2484099911U, // VPCMPEQQZ128rm >+ 2484099911U, // VPCMPEQQZ128rmb >+ 352344903U, // VPCMPEQQZ128rmbk >+ 352344903U, // VPCMPEQQZ128rmk >+ 2484099911U, // VPCMPEQQZ128rr >+ 352344903U, // VPCMPEQQZ128rrk >+ 2484099911U, // VPCMPEQQZ256rm >+ 2484099911U, // VPCMPEQQZ256rmb >+ 352344903U, // VPCMPEQQZ256rmbk >+ 352344903U, // VPCMPEQQZ256rmk >+ 2484099911U, // VPCMPEQQZ256rr >+ 352344903U, // VPCMPEQQZ256rrk >+ 2484099911U, // VPCMPEQQZrm >+ 2484099911U, // VPCMPEQQZrmb >+ 352344903U, // VPCMPEQQZrmbk >+ 352344903U, // VPCMPEQQZrmk >+ 2484099911U, // VPCMPEQQZrr >+ 352344903U, // VPCMPEQQZrrk >+ 2484099911U, // VPCMPEQQrm >+ 2484099911U, // VPCMPEQQrr >+ 2484102109U, // VPCMPEQWYrm >+ 2484102109U, // VPCMPEQWYrr >+ 2484102109U, // VPCMPEQWZ128rm >+ 352347101U, // VPCMPEQWZ128rmk >+ 2484102109U, // VPCMPEQWZ128rr >+ 352347101U, // VPCMPEQWZ128rrk >+ 2484102109U, // VPCMPEQWZ256rm >+ 352347101U, // VPCMPEQWZ256rmk >+ 2484102109U, // VPCMPEQWZ256rr >+ 352347101U, // VPCMPEQWZ256rrk >+ 2484102109U, // VPCMPEQWZrm >+ 352347101U, // VPCMPEQWZrmk >+ 2484102109U, // VPCMPEQWZrr >+ 352347101U, // VPCMPEQWZrrk >+ 2484102109U, // VPCMPEQWrm >+ 2484102109U, // VPCMPEQWrr >+ 0U, // VPCMPESTRIMEM >+ 0U, // VPCMPESTRIREG >+ 2584762270U, // VPCMPESTRIrm >+ 2484098974U, // VPCMPESTRIrr >+ 0U, // VPCMPESTRM128MEM >+ 0U, // VPCMPESTRM128REG >+ 2584762520U, // VPCMPESTRM128rm >+ 2484099224U, // VPCMPESTRM128rr >+ 2484096599U, // VPCMPGTBYrm >+ 2484096599U, // VPCMPGTBYrr >+ 2484096599U, // VPCMPGTBZ128rm >+ 352341591U, // VPCMPGTBZ128rmk >+ 2484096599U, // VPCMPGTBZ128rr >+ 352341591U, // VPCMPGTBZ128rrk >+ 2484096599U, // VPCMPGTBZ256rm >+ 352341591U, // VPCMPGTBZ256rmk >+ 2484096599U, // VPCMPGTBZ256rr >+ 352341591U, // VPCMPGTBZ256rrk >+ 2484096599U, // VPCMPGTBZrm >+ 352341591U, // VPCMPGTBZrmk >+ 2484096599U, // VPCMPGTBZrr >+ 352341591U, // VPCMPGTBZrrk >+ 2484096599U, // VPCMPGTBrm >+ 2484096599U, // VPCMPGTBrr >+ 2484098287U, // VPCMPGTDYrm >+ 2484098287U, // VPCMPGTDYrr >+ 2484098287U, // VPCMPGTDZ128rm >+ 2484098287U, // VPCMPGTDZ128rmb >+ 352343279U, // VPCMPGTDZ128rmbk >+ 352343279U, // VPCMPGTDZ128rmk >+ 2484098287U, // VPCMPGTDZ128rr >+ 352343279U, // VPCMPGTDZ128rrk >+ 2484098287U, // VPCMPGTDZ256rm >+ 2484098287U, // VPCMPGTDZ256rmb >+ 352343279U, // VPCMPGTDZ256rmbk >+ 352343279U, // VPCMPGTDZ256rmk >+ 2484098287U, // VPCMPGTDZ256rr >+ 352343279U, // VPCMPGTDZ256rrk >+ 2484098287U, // VPCMPGTDZrm >+ 2484098287U, // VPCMPGTDZrmb >+ 352343279U, // VPCMPGTDZrmbk >+ 352343279U, // VPCMPGTDZrmk >+ 2484098287U, // VPCMPGTDZrr >+ 352343279U, // VPCMPGTDZrrk >+ 2484098287U, // VPCMPGTDrm >+ 2484098287U, // VPCMPGTDrr >+ 2484099972U, // VPCMPGTQYrm >+ 2484099972U, // VPCMPGTQYrr >+ 2484099972U, // VPCMPGTQZ128rm >+ 2484099972U, // VPCMPGTQZ128rmb >+ 352344964U, // VPCMPGTQZ128rmbk >+ 352344964U, // VPCMPGTQZ128rmk >+ 2484099972U, // VPCMPGTQZ128rr >+ 352344964U, // VPCMPGTQZ128rrk >+ 2484099972U, // VPCMPGTQZ256rm >+ 2484099972U, // VPCMPGTQZ256rmb >+ 352344964U, // VPCMPGTQZ256rmbk >+ 352344964U, // VPCMPGTQZ256rmk >+ 2484099972U, // VPCMPGTQZ256rr >+ 352344964U, // VPCMPGTQZ256rrk >+ 2484099972U, // VPCMPGTQZrm >+ 2484099972U, // VPCMPGTQZrmb >+ 352344964U, // VPCMPGTQZrmbk >+ 352344964U, // VPCMPGTQZrmk >+ 2484099972U, // VPCMPGTQZrr >+ 352344964U, // VPCMPGTQZrrk >+ 2484099972U, // VPCMPGTQrm >+ 2484099972U, // VPCMPGTQrr >+ 2484102300U, // VPCMPGTWYrm >+ 2484102300U, // VPCMPGTWYrr >+ 2484102300U, // VPCMPGTWZ128rm >+ 352347292U, // VPCMPGTWZ128rmk >+ 2484102300U, // VPCMPGTWZ128rr >+ 352347292U, // VPCMPGTWZ128rrk >+ 2484102300U, // VPCMPGTWZ256rm >+ 352347292U, // VPCMPGTWZ256rmk >+ 2484102300U, // VPCMPGTWZ256rr >+ 352347292U, // VPCMPGTWZ256rrk >+ 2484102300U, // VPCMPGTWZrm >+ 352347292U, // VPCMPGTWZrmk >+ 2484102300U, // VPCMPGTWZrr >+ 352347292U, // VPCMPGTWZrrk >+ 2484102300U, // VPCMPGTWrm >+ 2484102300U, // VPCMPGTWrr >+ 0U, // VPCMPISTRIMEM >+ 0U, // VPCMPISTRIREG >+ 2584762282U, // VPCMPISTRIrm >+ 2484098986U, // VPCMPISTRIrr >+ 0U, // VPCMPISTRM128MEM >+ 0U, // VPCMPISTRM128REG >+ 2584762532U, // VPCMPISTRM128rm >+ 2484099236U, // VPCMPISTRM128rr >+ 1129672181U, // VPCMPQZrmi >+ 2484099903U, // VPCMPQZrmi_alt >+ 352344895U, // VPCMPQZrmik_alt >+ 55946741U, // VPCMPQZrri >+ 2484099903U, // VPCMPQZrri_alt >+ 352344895U, // VPCMPQZrrik_alt >+ 1130720757U, // VPCMPUDZrmi >+ 2484098337U, // VPCMPUDZrmi_alt >+ 352343329U, // VPCMPUDZrmik_alt >+ 56995317U, // VPCMPUDZrri >+ 2484098337U, // VPCMPUDZrri_alt >+ 352343329U, // VPCMPUDZrrik_alt >+ 1131769333U, // VPCMPUQZrmi >+ 2484100030U, // VPCMPUQZrmi_alt >+ 352345022U, // VPCMPUQZrmik_alt >+ 58043893U, // VPCMPUQZrri >+ 2484100030U, // VPCMPUQZrri_alt >+ 352345022U, // VPCMPUQZrrik_alt >+ 2484096454U, // VPCOMBmi >+ 2484096454U, // VPCOMBri >+ 2484097077U, // VPCOMDmi >+ 2484097077U, // VPCOMDri >+ 2484099887U, // VPCOMQmi >+ 2484099887U, // VPCOMQri >+ 2484096631U, // VPCOMUBmi >+ 2484096631U, // VPCOMUBri >+ 2484098319U, // VPCOMUDmi >+ 2484098319U, // VPCOMUDri >+ 2484100021U, // VPCOMUQmi >+ 2484100021U, // VPCOMUQri >+ 2484102342U, // VPCOMUWmi >+ 2484102342U, // VPCOMUWri >+ 2484102092U, // VPCOMWmi >+ 2484102092U, // VPCOMWri >+ 907035797U, // VPCONFLICTDrm >+ 2450539669U, // VPCONFLICTDrmb >+ 50349205U, // VPCONFLICTDrmbk >+ 2499822741U, // VPCONFLICTDrmbkz >+ 50349205U, // VPCONFLICTDrmk >+ 2499822741U, // VPCONFLICTDrmkz >+ 336610453U, // VPCONFLICTDrr >+ 50349205U, // VPCONFLICTDrrk >+ 2499822741U, // VPCONFLICTDrrkz >+ 907036604U, // VPCONFLICTQrm >+ 370165692U, // VPCONFLICTQrmb >+ 50350012U, // VPCONFLICTQrmbk >+ 2499823548U, // VPCONFLICTQrmbkz >+ 50350012U, // VPCONFLICTQrmk >+ 2499823548U, // VPCONFLICTQrmkz >+ 336611260U, // VPCONFLICTQrr >+ 50350012U, // VPCONFLICTQrrk >+ 2499823548U, // VPCONFLICTQrrkz >+ 2484096187U, // VPERM2F128rm >+ 2484096187U, // VPERM2F128rr >+ 2484096242U, // VPERM2I128rm >+ 2484096242U, // VPERM2I128rr >+ 2484097085U, // VPERMDYrm >+ 2484097085U, // VPERMDYrr >+ 2484093285U, // VPERMDZrm >+ 2484093285U, // VPERMDZrr >+ 2182103200U, // VPERMI2Drm >+ 50348192U, // VPERMI2Drmk >+ 2197831840U, // VPERMI2Drmkz >+ 2182103200U, // VPERMI2Drr >+ 50348192U, // VPERMI2Drrk >+ 2197831840U, // VPERMI2Drrkz >+ 2182103538U, // VPERMI2PDrm >+ 50348530U, // VPERMI2PDrmk >+ 2197832178U, // VPERMI2PDrmkz >+ 2182103538U, // VPERMI2PDrr >+ 50348530U, // VPERMI2PDrrk >+ 2197832178U, // VPERMI2PDrrkz >+ 2182105254U, // VPERMI2PSrm >+ 50350246U, // VPERMI2PSrmk >+ 2197833894U, // VPERMI2PSrmkz >+ 2182105254U, // VPERMI2PSrr >+ 50350246U, // VPERMI2PSrrk >+ 2197833894U, // VPERMI2PSrrkz >+ 2182104512U, // VPERMI2Qrm >+ 50349504U, // VPERMI2Qrmk >+ 2197833152U, // VPERMI2Qrmkz >+ 2182104512U, // VPERMI2Qrr >+ 50349504U, // VPERMI2Qrrk >+ 2197833152U, // VPERMI2Qrrkz >+ 2484097306U, // VPERMIL2PDmr >+ 2484097306U, // VPERMIL2PDmrY >+ 2484097306U, // VPERMIL2PDrm >+ 2484097306U, // VPERMIL2PDrmY >+ 2484097306U, // VPERMIL2PDrr >+ 2484097306U, // VPERMIL2PDrrY >+ 2484100552U, // VPERMIL2PSmr >+ 2484100552U, // VPERMIL2PSmrY >+ 2484100552U, // VPERMIL2PSrm >+ 2484100552U, // VPERMIL2PSrmY >+ 2484100552U, // VPERMIL2PSrr >+ 2484100552U, // VPERMIL2PSrrY >+ 3088077412U, // VPERMILPDYmi >+ 2484097636U, // VPERMILPDYri >+ 2484097636U, // VPERMILPDYrm >+ 2484097636U, // VPERMILPDYrr >+ 3054519040U, // VPERMILPDZmi >+ 2484093696U, // VPERMILPDZri >+ 2685424228U, // VPERMILPDmi >+ 2484097636U, // VPERMILPDri >+ 2484097636U, // VPERMILPDrm >+ 2484097636U, // VPERMILPDrr >+ 3088080659U, // VPERMILPSYmi >+ 2484100883U, // VPERMILPSYri >+ 2484100883U, // VPERMILPSYrm >+ 2484100883U, // VPERMILPSYrr >+ 3054520744U, // VPERMILPSZmi >+ 2484095400U, // VPERMILPSZri >+ 2685427475U, // VPERMILPSmi >+ 2484100883U, // VPERMILPSri >+ 2484100883U, // VPERMILPSrm >+ 2484100883U, // VPERMILPSrr >+ 2987414163U, // VPERMPDYmi >+ 2484097683U, // VPERMPDYri >+ 3121627937U, // VPERMPDZmi >+ 2484093729U, // VPERMPDZri >+ 2484093729U, // VPERMPDZrm >+ 2484093729U, // VPERMPDZrr >+ 2484100922U, // VPERMPSYrm >+ 2484100922U, // VPERMPSYrr >+ 2484095433U, // VPERMPSZrm >+ 2484095433U, // VPERMPSZrr >+ 2987416375U, // VPERMQYmi >+ 2484099895U, // VPERMQYri >+ 3054520106U, // VPERMQZmi >+ 2484094762U, // VPERMQZri >+ 2484094762U, // VPERMQZrm >+ 2484094762U, // VPERMQZrr >+ 2182103211U, // VPERMT2Drm >+ 50348203U, // VPERMT2Drmk >+ 2197831851U, // VPERMT2Drmkz >+ 2182103211U, // VPERMT2Drr >+ 50348203U, // VPERMT2Drrk >+ 2197831851U, // VPERMT2Drrkz >+ 2182103587U, // VPERMT2PDrm >+ 50348579U, // VPERMT2PDrmk >+ 2197832227U, // VPERMT2PDrmkz >+ 2182103587U, // VPERMT2PDrr >+ 50348579U, // VPERMT2PDrrk >+ 2197832227U, // VPERMT2PDrrkz >+ 2182105291U, // VPERMT2PSrm >+ 50350283U, // VPERMT2PSrmk >+ 2197833931U, // VPERMT2PSrmkz >+ 2182105291U, // VPERMT2PSrr >+ 50350283U, // VPERMT2PSrrk >+ 2197833931U, // VPERMT2PSrrkz >+ 2182104523U, // VPERMT2Qrm >+ 50349515U, // VPERMT2Qrmk >+ 2197833163U, // VPERMT2Qrmkz >+ 2182104523U, // VPERMT2Qrr >+ 50349515U, // VPERMT2Qrrk >+ 2197833163U, // VPERMT2Qrrkz >+ 2148634090U, // VPEXTRBmr >+ 2484096490U, // VPEXTRBrr >+ 2148602705U, // VPEXTRDmr >+ 2484097873U, // VPEXTRDrr >+ 2148621158U, // VPEXTRQmr >+ 2484099942U, // VPEXTRQrr >+ 2148574207U, // VPEXTRWmr >+ 2484102143U, // VPEXTRWri >+ 2484102143U, // VPEXTRWrr_REV >+ 1074810792U, // VPGATHERDDYrm >+ 1056981260U, // VPGATHERDDZrm >+ 1074810792U, // VPGATHERDDrm >+ 1007704774U, // VPGATHERDQYrm >+ 3204466316U, // VPGATHERDQZrm >+ 1007704774U, // VPGATHERDQrm >+ 1074811702U, // VPGATHERQDYrm >+ 3204465514U, // VPGATHERQDZrm >+ 1074811702U, // VPGATHERQDrm >+ 1007704913U, // VPGATHERQQYrm >+ 3204466523U, // VPGATHERQQZrm >+ 1007704913U, // VPGATHERQQrm >+ 437276477U, // VPHADDBDrm >+ 336613181U, // VPHADDBDrr >+ 437279207U, // VPHADDBQrm >+ 336615911U, // VPHADDBQrr >+ 437281489U, // VPHADDBWrm >+ 336618193U, // VPHADDBWrr >+ 437279331U, // VPHADDDQrm >+ 336616035U, // VPHADDDQrr >+ 2484096909U, // VPHADDDYrm >+ 2484096909U, // VPHADDDYrr >+ 2484096909U, // VPHADDDrm >+ 2484096909U, // VPHADDDrr >+ 2484102191U, // VPHADDSWrm128 >+ 2484102191U, // VPHADDSWrm256 >+ 2484102191U, // VPHADDSWrr128 >+ 2484102191U, // VPHADDSWrr256 >+ 437276487U, // VPHADDUBDrm >+ 336613191U, // VPHADDUBDrr >+ 437279217U, // VPHADDUBQrm >+ 336615921U, // VPHADDUBQrr >+ 437281523U, // VPHADDUBWrm >+ 336618227U, // VPHADDUBWrr >+ 437279452U, // VPHADDUDQrm >+ 336616156U, // VPHADDUDQrr >+ 437278147U, // VPHADDUWDrm >+ 336614851U, // VPHADDUWDrr >+ 437279734U, // VPHADDUWQrm >+ 336616438U, // VPHADDUWQrr >+ 437278059U, // VPHADDWDrm >+ 336614763U, // VPHADDWDrr >+ 437279724U, // VPHADDWQrm >+ 336616428U, // VPHADDWQrr >+ 2484101940U, // VPHADDWYrm >+ 2484101940U, // VPHADDWYrr >+ 2484101940U, // VPHADDWrm >+ 2484101940U, // VPHADDWrr >+ 437282008U, // VPHMINPOSUWrm128 >+ 336618712U, // VPHMINPOSUWrr128 >+ 437281460U, // VPHSUBBWrm >+ 336618164U, // VPHSUBBWrr >+ 437279313U, // VPHSUBDQrm >+ 336616017U, // VPHSUBDQrr >+ 2484096850U, // VPHSUBDYrm >+ 2484096850U, // VPHSUBDYrr >+ 2484096850U, // VPHSUBDrm >+ 2484096850U, // VPHSUBDrr >+ 2484102172U, // VPHSUBSWrm128 >+ 2484102172U, // VPHSUBSWrm256 >+ 2484102172U, // VPHSUBSWrr128 >+ 2484102172U, // VPHSUBSWrr256 >+ 437278049U, // VPHSUBWDrm >+ 336614753U, // VPHSUBWDrr >+ 2484101886U, // VPHSUBWYrm >+ 2484101886U, // VPHSUBWYrr >+ 2484101886U, // VPHSUBWrm >+ 2484101886U, // VPHSUBWrr >+ 2484096481U, // VPINSRBrm >+ 2484096481U, // VPINSRBrr >+ 2484097864U, // VPINSRDrm >+ 2484097864U, // VPINSRDrr >+ 2484099933U, // VPINSRQrm >+ 2484099933U, // VPINSRQrr >+ 2484102134U, // VPINSRWrmi >+ 2484102134U, // VPINSRWrri >+ 907035811U, // VPLZCNTDrm >+ 2450539683U, // VPLZCNTDrmb >+ 50349219U, // VPLZCNTDrmbk >+ 2499822755U, // VPLZCNTDrmbkz >+ 50349219U, // VPLZCNTDrmk >+ 2499822755U, // VPLZCNTDrmkz >+ 336610467U, // VPLZCNTDrr >+ 50349219U, // VPLZCNTDrrk >+ 2499822755U, // VPLZCNTDrrkz >+ 907036618U, // VPLZCNTQrm >+ 370165706U, // VPLZCNTQrmb >+ 50350026U, // VPLZCNTQrmbk >+ 2499823562U, // VPLZCNTQrmbkz >+ 50350026U, // VPLZCNTQrmk >+ 2499823562U, // VPLZCNTQrmkz >+ 336611274U, // VPLZCNTQrr >+ 50350026U, // VPLZCNTQrrk >+ 2499823562U, // VPLZCNTQrrkz >+ 2484096948U, // VPMACSDDrm >+ 2484096948U, // VPMACSDDrr >+ 2484098850U, // VPMACSDQHrm >+ 2484098850U, // VPMACSDQHrr >+ 2484099136U, // VPMACSDQLrm >+ 2484099136U, // VPMACSDQLrr >+ 2484096958U, // VPMACSSDDrm >+ 2484096958U, // VPMACSSDDrr >+ 2484098861U, // VPMACSSDQHrm >+ 2484098861U, // VPMACSSDQHrr >+ 2484099147U, // VPMACSSDQLrm >+ 2484099147U, // VPMACSSDQLrr >+ 2484098476U, // VPMACSSWDrm >+ 2484098476U, // VPMACSSWDrr >+ 2484102392U, // VPMACSSWWrm >+ 2484102392U, // VPMACSSWWrr >+ 2484098455U, // VPMACSWDrm >+ 2484098455U, // VPMACSWDrr >+ 2484102382U, // VPMACSWWrm >+ 2484102382U, // VPMACSWWrr >+ 2484098487U, // VPMADCSSWDrm >+ 2484098487U, // VPMADCSSWDrr >+ 2484098465U, // VPMADCSWDrm >+ 2484098465U, // VPMADCSWDrr >+ 2484102160U, // VPMADDUBSWrm128 >+ 2484102160U, // VPMADDUBSWrm256 >+ 2484102160U, // VPMADDUBSWrr128 >+ 2484102160U, // VPMADDUBSWrr256 >+ 2484098421U, // VPMADDWDYrm >+ 2484098421U, // VPMADDWDYrr >+ 2484098421U, // VPMADDWDrm >+ 2484098421U, // VPMADDWDrr >+ 2149176654U, // VPMASKMOVDYmr >+ 2484098382U, // VPMASKMOVDYrm >+ 2148799822U, // VPMASKMOVDmr >+ 2484098382U, // VPMASKMOVDrm >+ 2149178329U, // VPMASKMOVQYmr >+ 2484100057U, // VPMASKMOVQYrm >+ 2148801497U, // VPMASKMOVQmr >+ 2484100057U, // VPMASKMOVQrm >+ 2484096584U, // VPMAXSBYrm >+ 2484096584U, // VPMAXSBYrr >+ 2484096584U, // VPMAXSBrm >+ 2484096584U, // VPMAXSBrr >+ 2484098261U, // VPMAXSDYrm >+ 2484098261U, // VPMAXSDYrr >+ 2484094091U, // VPMAXSDZrm >+ 2484094091U, // VPMAXSDZrmb >+ 50349195U, // VPMAXSDZrmbk >+ 2499822731U, // VPMAXSDZrmbkz >+ 50349195U, // VPMAXSDZrmk >+ 2499822731U, // VPMAXSDZrmkz >+ 2484094091U, // VPMAXSDZrr >+ 50349195U, // VPMAXSDZrrk >+ 2499822731U, // VPMAXSDZrrkz >+ 2484098261U, // VPMAXSDrm >+ 2484098261U, // VPMAXSDrr >+ 2484094898U, // VPMAXSQZrm >+ 2484094898U, // VPMAXSQZrmb >+ 50350002U, // VPMAXSQZrmbk >+ 2499823538U, // VPMAXSQZrmbkz >+ 50350002U, // VPMAXSQZrmk >+ 2499823538U, // VPMAXSQZrmkz >+ 2484094898U, // VPMAXSQZrr >+ 50350002U, // VPMAXSQZrrk >+ 2499823538U, // VPMAXSQZrrkz >+ 2484102291U, // VPMAXSWYrm >+ 2484102291U, // VPMAXSWYrr >+ 2484102291U, // VPMAXSWrm >+ 2484102291U, // VPMAXSWrr >+ 2484096663U, // VPMAXUBYrm >+ 2484096663U, // VPMAXUBYrr >+ 2484096663U, // VPMAXUBrm >+ 2484096663U, // VPMAXUBrr >+ 2484098346U, // VPMAXUDYrm >+ 2484098346U, // VPMAXUDYrr >+ 2484094159U, // VPMAXUDZrm >+ 2484094159U, // VPMAXUDZrmb >+ 50349263U, // VPMAXUDZrmbk >+ 2499822799U, // VPMAXUDZrmbkz >+ 50349263U, // VPMAXUDZrmk >+ 2499822799U, // VPMAXUDZrmkz >+ 2484094159U, // VPMAXUDZrr >+ 50349263U, // VPMAXUDZrrk >+ 2499822799U, // VPMAXUDZrrkz >+ 2484098346U, // VPMAXUDrm >+ 2484098346U, // VPMAXUDrr >+ 2484094966U, // VPMAXUQZrm >+ 2484094966U, // VPMAXUQZrmb >+ 50350070U, // VPMAXUQZrmbk >+ 2499823606U, // VPMAXUQZrmbkz >+ 50350070U, // VPMAXUQZrmk >+ 2499823606U, // VPMAXUQZrmkz >+ 2484094966U, // VPMAXUQZrr >+ 50350070U, // VPMAXUQZrrk >+ 2499823606U, // VPMAXUQZrrkz >+ 2484102373U, // VPMAXUWYrm >+ 2484102373U, // VPMAXUWYrr >+ 2484102373U, // VPMAXUWrm >+ 2484102373U, // VPMAXUWrr >+ 2484096525U, // VPMINSBYrm >+ 2484096525U, // VPMINSBYrr >+ 2484096525U, // VPMINSBrm >+ 2484096525U, // VPMINSBrr >+ 2484098181U, // VPMINSDYrm >+ 2484098181U, // VPMINSDYrr >+ 2484094057U, // VPMINSDZrm >+ 2484094057U, // VPMINSDZrmb >+ 50349161U, // VPMINSDZrmbk >+ 2499822697U, // VPMINSDZrmbkz >+ 50349161U, // VPMINSDZrmk >+ 2499822697U, // VPMINSDZrmkz >+ 2484094057U, // VPMINSDZrr >+ 50349161U, // VPMINSDZrrk >+ 2499822697U, // VPMINSDZrrkz >+ 2484098181U, // VPMINSDrm >+ 2484098181U, // VPMINSDrr >+ 2484094888U, // VPMINSQZrm >+ 2484094888U, // VPMINSQZrmb >+ 50349992U, // VPMINSQZrmbk >+ 2499823528U, // VPMINSQZrmbkz >+ 50349992U, // VPMINSQZrmk >+ 2499823528U, // VPMINSQZrmkz >+ 2484094888U, // VPMINSQZrr >+ 50349992U, // VPMINSQZrrk >+ 2499823528U, // VPMINSQZrrkz >+ 2484102222U, // VPMINSWYrm >+ 2484102222U, // VPMINSWYrr >+ 2484102222U, // VPMINSWrm >+ 2484102222U, // VPMINSWrr >+ 2484096640U, // VPMINUBYrm >+ 2484096640U, // VPMINUBYrr >+ 2484096640U, // VPMINUBrm >+ 2484096640U, // VPMINUBrr >+ 2484098328U, // VPMINUDYrm >+ 2484098328U, // VPMINUDYrr >+ 2484094149U, // VPMINUDZrm >+ 2484094149U, // VPMINUDZrmb >+ 50349253U, // VPMINUDZrmbk >+ 2499822789U, // VPMINUDZrmbkz >+ 50349253U, // VPMINUDZrmk >+ 2499822789U, // VPMINUDZrmkz >+ 2484094149U, // VPMINUDZrr >+ 50349253U, // VPMINUDZrrk >+ 2499822789U, // VPMINUDZrrkz >+ 2484098328U, // VPMINUDrm >+ 2484098328U, // VPMINUDrr >+ 2484094956U, // VPMINUQZrm >+ 2484094956U, // VPMINUQZrmb >+ 50350060U, // VPMINUQZrmbk >+ 2499823596U, // VPMINUQZrmbkz >+ 50350060U, // VPMINUQZrmk >+ 2499823596U, // VPMINUQZrmkz >+ 2484094956U, // VPMINUQZrr >+ 50350060U, // VPMINUQZrrk >+ 2499823596U, // VPMINUQZrrkz >+ 2484102351U, // VPMINUWYrm >+ 2484102351U, // VPMINUWYrr >+ 2484102351U, // VPMINUWrm >+ 2484102351U, // VPMINUWrr >+ 1310788U, // VPMOVDBmr >+ 17039428U, // VPMOVDBmrk >+ 336609348U, // VPMOVDBrr >+ 352337988U, // VPMOVDBrrk >+ 2499821636U, // VPMOVDBrrkz >+ 1690341U, // VPMOVDWmr >+ 17418981U, // VPMOVDWmrk >+ 336612069U, // VPMOVDWrr >+ 352340709U, // VPMOVDWrrk >+ 2499824357U, // VPMOVDWrrkz >+ 336612787U, // VPMOVMSKBYrr >+ 336612787U, // VPMOVMSKBrr >+ 1310830U, // VPMOVQBmr >+ 17039470U, // VPMOVQBmrk >+ 336609390U, // VPMOVQBrr >+ 352338030U, // VPMOVQBrrk >+ 2499821678U, // VPMOVQBrrkz >+ 1688476U, // VPMOVQDmr >+ 17417116U, // VPMOVQDmrk >+ 336610204U, // VPMOVQDrr >+ 352338844U, // VPMOVQDrrk >+ 2499822492U, // VPMOVQDrrkz >+ 1313562U, // VPMOVQWmr >+ 17042202U, // VPMOVQWmrk >+ 336612122U, // VPMOVQWrr >+ 352340762U, // VPMOVQWrrk >+ 2499824410U, // VPMOVQWrrkz >+ 1310777U, // VPMOVSDBmr >+ 17039417U, // VPMOVSDBmrk >+ 336609337U, // VPMOVSDBrr >+ 352337977U, // VPMOVSDBrrk >+ 2499821625U, // VPMOVSDBrrkz >+ 1690330U, // VPMOVSDWmr >+ 17418970U, // VPMOVSDWmrk >+ 336612058U, // VPMOVSDWrr >+ 352340698U, // VPMOVSDWrrk >+ 2499824346U, // VPMOVSDWrrkz >+ 1310819U, // VPMOVSQBmr >+ 17039459U, // VPMOVSQBmrk >+ 336609379U, // VPMOVSQBrr >+ 352338019U, // VPMOVSQBrrk >+ 2499821667U, // VPMOVSQBrrkz >+ 1688465U, // VPMOVSQDmr >+ 17417105U, // VPMOVSQDmrk >+ 336610193U, // VPMOVSQDrr >+ 352338833U, // VPMOVSQDrrk >+ 2499822481U, // VPMOVSQDrrkz >+ 1313551U, // VPMOVSQWmr >+ 17042191U, // VPMOVSQWmrk >+ 336612111U, // VPMOVSQWrr >+ 352340751U, // VPMOVSQWrrk >+ 2499824399U, // VPMOVSQWrrkz >+ 303058787U, // VPMOVSXBDYrm >+ 336613219U, // VPMOVSXBDYrr >+ 437272794U, // VPMOVSXBDZrm >+ 352338138U, // VPMOVSXBDZrmk >+ 2499821786U, // VPMOVSXBDZrmkz >+ 336609498U, // VPMOVSXBDZrr >+ 352338138U, // VPMOVSXBDZrrk >+ 2499821786U, // VPMOVSXBDZrrkz >+ 303058787U, // VPMOVSXBDrm >+ 336613219U, // VPMOVSXBDrr >+ 470833668U, // VPMOVSXBQYrm >+ 336615940U, // VPMOVSXBQYrr >+ 437274088U, // VPMOVSXBQZrm >+ 352339432U, // VPMOVSXBQZrmk >+ 2499823080U, // VPMOVSXBQZrmkz >+ 336610792U, // VPMOVSXBQZrr >+ 352339432U, // VPMOVSXBQZrrk >+ 2499823080U, // VPMOVSXBQZrrkz >+ 470833668U, // VPMOVSXBQrm >+ 336615940U, // VPMOVSXBQrr >+ 437281551U, // VPMOVSXBWYrm >+ 336618255U, // VPMOVSXBWYrr >+ 370172687U, // VPMOVSXBWrm >+ 336618255U, // VPMOVSXBWrr >+ 437279473U, // VPMOVSXDQYrm >+ 336616177U, // VPMOVSXDQYrr >+ 839927528U, // VPMOVSXDQZrm >+ 352339688U, // VPMOVSXDQZrmk >+ 2499823336U, // VPMOVSXDQZrmkz >+ 336611048U, // VPMOVSXDQZrr >+ 352339688U, // VPMOVSXDQZrrk >+ 2499823336U, // VPMOVSXDQZrrkz >+ 370170609U, // VPMOVSXDQrm >+ 336616177U, // VPMOVSXDQrr >+ 437278158U, // VPMOVSXWDYrm >+ 336614862U, // VPMOVSXWDYrr >+ 839927039U, // VPMOVSXWDZrm >+ 352339199U, // VPMOVSXWDZrmk >+ 2499822847U, // VPMOVSXWDZrmkz >+ 336610559U, // VPMOVSXWDZrr >+ 352339199U, // VPMOVSXWDZrrk >+ 2499822847U, // VPMOVSXWDZrrkz >+ 370169294U, // VPMOVSXWDrm >+ 336614862U, // VPMOVSXWDrr >+ 303062017U, // VPMOVSXWQYrm >+ 336616449U, // VPMOVSXWQYrr >+ 437274662U, // VPMOVSXWQZrm >+ 352340006U, // VPMOVSXWQZrmk >+ 2499823654U, // VPMOVSXWQZrmkz >+ 336611366U, // VPMOVSXWQZrr >+ 352340006U, // VPMOVSXWQZrrk >+ 2499823654U, // VPMOVSXWQZrrkz >+ 303062017U, // VPMOVSXWQrm >+ 336616449U, // VPMOVSXWQrr >+ 1310765U, // VPMOVUSDBmr >+ 17039405U, // VPMOVUSDBmrk >+ 336609325U, // VPMOVUSDBrr >+ 352337965U, // VPMOVUSDBrrk >+ 2499821613U, // VPMOVUSDBrrkz >+ 1690318U, // VPMOVUSDWmr >+ 17418958U, // VPMOVUSDWmrk >+ 336612046U, // VPMOVUSDWrr >+ 352340686U, // VPMOVUSDWrrk >+ 2499824334U, // VPMOVUSDWrrkz >+ 1310807U, // VPMOVUSQBmr >+ 17039447U, // VPMOVUSQBmrk >+ 336609367U, // VPMOVUSQBrr >+ 352338007U, // VPMOVUSQBrrk >+ 2499821655U, // VPMOVUSQBrrkz >+ 1688453U, // VPMOVUSQDmr >+ 17417093U, // VPMOVUSQDmrk >+ 336610181U, // VPMOVUSQDrr >+ 352338821U, // VPMOVUSQDrrk >+ 2499822469U, // VPMOVUSQDrrkz >+ 1313539U, // VPMOVUSQWmr >+ 17042179U, // VPMOVUSQWmrk >+ 336612099U, // VPMOVUSQWrr >+ 352340739U, // VPMOVUSQWrrk >+ 2499824387U, // VPMOVUSQWrrkz >+ 303058798U, // VPMOVZXBDYrm >+ 336613230U, // VPMOVZXBDYrr >+ 437272806U, // VPMOVZXBDZrm >+ 352338150U, // VPMOVZXBDZrmk >+ 2499821798U, // VPMOVZXBDZrmkz >+ 336609510U, // VPMOVZXBDZrr >+ 352338150U, // VPMOVZXBDZrrk >+ 2499821798U, // VPMOVZXBDZrrkz >+ 303058798U, // VPMOVZXBDrm >+ 336613230U, // VPMOVZXBDrr >+ 470833679U, // VPMOVZXBQYrm >+ 336615951U, // VPMOVZXBQYrr >+ 437274100U, // VPMOVZXBQZrm >+ 352339444U, // VPMOVZXBQZrmk >+ 2499823092U, // VPMOVZXBQZrmkz >+ 336610804U, // VPMOVZXBQZrr >+ 352339444U, // VPMOVZXBQZrrk >+ 2499823092U, // VPMOVZXBQZrrkz >+ 470833679U, // VPMOVZXBQrm >+ 336615951U, // VPMOVZXBQrr >+ 437281562U, // VPMOVZXBWYrm >+ 336618266U, // VPMOVZXBWYrr >+ 370172698U, // VPMOVZXBWrm >+ 336618266U, // VPMOVZXBWrr >+ 437279484U, // VPMOVZXDQYrm >+ 336616188U, // VPMOVZXDQYrr >+ 839927540U, // VPMOVZXDQZrm >+ 352339700U, // VPMOVZXDQZrmk >+ 2499823348U, // VPMOVZXDQZrmkz >+ 336611060U, // VPMOVZXDQZrr >+ 352339700U, // VPMOVZXDQZrrk >+ 2499823348U, // VPMOVZXDQZrrkz >+ 370170620U, // VPMOVZXDQrm >+ 336616188U, // VPMOVZXDQrr >+ 437278169U, // VPMOVZXWDYrm >+ 336614873U, // VPMOVZXWDYrr >+ 839927051U, // VPMOVZXWDZrm >+ 352339211U, // VPMOVZXWDZrmk >+ 2499822859U, // VPMOVZXWDZrmkz >+ 336610571U, // VPMOVZXWDZrr >+ 352339211U, // VPMOVZXWDZrrk >+ 2499822859U, // VPMOVZXWDZrrkz >+ 370169305U, // VPMOVZXWDrm >+ 336614873U, // VPMOVZXWDrr >+ 303062028U, // VPMOVZXWQYrm >+ 336616460U, // VPMOVZXWQYrr >+ 437274674U, // VPMOVZXWQZrm >+ 352340018U, // VPMOVZXWQZrmk >+ 2499823666U, // VPMOVZXWQZrmkz >+ 336611378U, // VPMOVZXWQZrr >+ 352340018U, // VPMOVZXWQZrrk >+ 2499823666U, // VPMOVZXWQZrrkz >+ 303062028U, // VPMOVZXWQrm >+ 336616460U, // VPMOVZXWQrr >+ 2484099735U, // VPMULDQYrm >+ 2484099735U, // VPMULDQYrr >+ 2484094549U, // VPMULDQZrm >+ 2484094549U, // VPMULDQZrmb >+ 352339541U, // VPMULDQZrmbk >+ 2499823189U, // VPMULDQZrmbkz >+ 352339541U, // VPMULDQZrmk >+ 2499823189U, // VPMULDQZrmkz >+ 2484094549U, // VPMULDQZrr >+ 352339541U, // VPMULDQZrrk >+ 2499823189U, // VPMULDQZrrkz >+ 2484099735U, // VPMULDQrm >+ 2484099735U, // VPMULDQrr >+ 2484102245U, // VPMULHRSWrm128 >+ 2484102245U, // VPMULHRSWrm256 >+ 2484102245U, // VPMULHRSWrr128 >+ 2484102245U, // VPMULHRSWrr256 >+ 2484102332U, // VPMULHUWYrm >+ 2484102332U, // VPMULHUWYrr >+ 2484102332U, // VPMULHUWrm >+ 2484102332U, // VPMULHUWrr >+ 2484102033U, // VPMULHWYrm >+ 2484102033U, // VPMULHWYrr >+ 2484102033U, // VPMULHWrm >+ 2484102033U, // VPMULHWrr >+ 2484097051U, // VPMULLDYrm >+ 2484097051U, // VPMULLDYrr >+ 2484093242U, // VPMULLDZrm >+ 2484093242U, // VPMULLDZrmb >+ 50348346U, // VPMULLDZrmbk >+ 2499821882U, // VPMULLDZrmbkz >+ 50348346U, // VPMULLDZrmk >+ 2499821882U, // VPMULLDZrmkz >+ 2484093242U, // VPMULLDZrr >+ 50348346U, // VPMULLDZrrk >+ 2499821882U, // VPMULLDZrrkz >+ 2484097051U, // VPMULLDrm >+ 2484097051U, // VPMULLDrr >+ 2484102075U, // VPMULLWYrm >+ 2484102075U, // VPMULLWYrr >+ 2484102075U, // VPMULLWrm >+ 2484102075U, // VPMULLWrr >+ 2484099815U, // VPMULUDQYrm >+ 2484099815U, // VPMULUDQYrr >+ 2484094685U, // VPMULUDQZrm >+ 2484094685U, // VPMULUDQZrmb >+ 352339677U, // VPMULUDQZrmbk >+ 2499823325U, // VPMULUDQZrmbkz >+ 352339677U, // VPMULUDQZrmk >+ 2499823325U, // VPMULUDQZrmkz >+ 2484094685U, // VPMULUDQZrr >+ 352339677U, // VPMULUDQZrrk >+ 2499823325U, // VPMULUDQZrrkz >+ 2484099815U, // VPMULUDQrm >+ 2484099815U, // VPMULUDQrr >+ 2484093878U, // VPORDZrm >+ 2484093878U, // VPORDZrmb >+ 50348982U, // VPORDZrmbk >+ 2499822518U, // VPORDZrmbkz >+ 50348982U, // VPORDZrmk >+ 2499822518U, // VPORDZrmkz >+ 2484093878U, // VPORDZrr >+ 50348982U, // VPORDZrrk >+ 2499822518U, // VPORDZrrkz >+ 2484094854U, // VPORQZrm >+ 2484094854U, // VPORQZrmb >+ 50349958U, // VPORQZrmbk >+ 2499823494U, // VPORQZrmbkz >+ 50349958U, // VPORQZrmk >+ 2499823494U, // VPORQZrmkz >+ 2484094854U, // VPORQZrr >+ 50349958U, // VPORQZrrk >+ 2499823494U, // VPORQZrrkz >+ 2484100181U, // VPORYrm >+ 2484100181U, // VPORYrr >+ 2484100181U, // VPORrm >+ 2484100181U, // VPORrr >+ 2484099216U, // VPPERMmr >+ 2484099216U, // VPPERMrm >+ 2484099216U, // VPPERMrr >+ 2584759905U, // VPROTBmi >+ 2584759905U, // VPROTBmr >+ 2484096609U, // VPROTBri >+ 2484096609U, // VPROTBrm >+ 2484096609U, // VPROTBrr >+ 2584761593U, // VPROTDmi >+ 2584761593U, // VPROTDmr >+ 2484098297U, // VPROTDri >+ 2484098297U, // VPROTDrm >+ 2484098297U, // VPROTDrr >+ 2584763286U, // VPROTQmi >+ 2584763286U, // VPROTQmr >+ 2484099990U, // VPROTQri >+ 2484099990U, // VPROTQrm >+ 2484099990U, // VPROTQrr >+ 2584765606U, // VPROTWmi >+ 2584765606U, // VPROTWmr >+ 2484102310U, // VPROTWri >+ 2484102310U, // VPROTWrm >+ 2484102310U, // VPROTWrr >+ 2484101832U, // VPSADBWYrm >+ 2484101832U, // VPSADBWYrr >+ 2484101832U, // VPSADBWrm >+ 2484101832U, // VPSADBWrr >+ 688409U, // VPSCATTERDDZmr >+ 706201U, // VPSCATTERDQZmr >+ 705399U, // VPSCATTERQDZmr >+ 706408U, // VPSCATTERQQZmr >+ 2584759681U, // VPSHABmr >+ 2484096385U, // VPSHABrm >+ 2484096385U, // VPSHABrr >+ 2584760109U, // VPSHADmr >+ 2484096813U, // VPSHADrm >+ 2484096813U, // VPSHADrr >+ 2584762847U, // VPSHAQmr >+ 2484099551U, // VPSHAQrm >+ 2484099551U, // VPSHAQrr >+ 2584765092U, // VPSHAWmr >+ 2484101796U, // VPSHAWrm >+ 2484101796U, // VPSHAWrr >+ 2584759742U, // VPSHLBmr >+ 2484096446U, // VPSHLBrm >+ 2484096446U, // VPSHLBrr >+ 2584760325U, // VPSHLDmr >+ 2484097029U, // VPSHLDrm >+ 2484097029U, // VPSHLDrr >+ 2584763159U, // VPSHLQmr >+ 2484099863U, // VPSHLQrm >+ 2484099863U, // VPSHLQrr >+ 2584765355U, // VPSHLWmr >+ 2484102059U, // VPSHLWrm >+ 2484102059U, // VPSHLWrr >+ 2484096414U, // VPSHUFBYrm >+ 2484096414U, // VPSHUFBYrr >+ 2484096414U, // VPSHUFBrm >+ 2484096414U, // VPSHUFBrr >+ 2987413464U, // VPSHUFDYmi >+ 2484096984U, // VPSHUFDYri >+ 3054518567U, // VPSHUFDZmi >+ 2484093223U, // VPSHUFDZri >+ 2584760280U, // VPSHUFDmi >+ 2484096984U, // VPSHUFDri >+ 2987418503U, // VPSHUFHWYmi >+ 2484102023U, // VPSHUFHWYri >+ 2584765319U, // VPSHUFHWmi >+ 2484102023U, // VPSHUFHWri >+ 2987418529U, // VPSHUFLWYmi >+ 2484102049U, // VPSHUFLWYri >+ 2584765345U, // VPSHUFLWmi >+ 2484102049U, // VPSHUFLWri >+ 2484096462U, // VPSIGNBYrm >+ 2484096462U, // VPSIGNBYrr >+ 2484096462U, // VPSIGNBrm >+ 2484096462U, // VPSIGNBrr >+ 2484097108U, // VPSIGNDYrm >+ 2484097108U, // VPSIGNDYrr >+ 2484097108U, // VPSIGNDrm >+ 2484097108U, // VPSIGNDrr >+ 2484102100U, // VPSIGNWYrm >+ 2484102100U, // VPSIGNWYrr >+ 2484102100U, // VPSIGNWrm >+ 2484102100U, // VPSIGNWrr >+ 2484099717U, // VPSLLDQYri >+ 2484099717U, // VPSLLDQri >+ 2484097043U, // VPSLLDYri >+ 2484097043U, // VPSLLDYrm >+ 2484097043U, // VPSLLDYrr >+ 3054518577U, // VPSLLDZmi >+ 352338225U, // VPSLLDZmik >+ 2484093233U, // VPSLLDZri >+ 352338225U, // VPSLLDZrik >+ 2484093233U, // VPSLLDZrm >+ 352338225U, // VPSLLDZrmk >+ 2484093233U, // VPSLLDZrr >+ 352338225U, // VPSLLDZrrk >+ 2484097043U, // VPSLLDri >+ 2484097043U, // VPSLLDrm >+ 2484097043U, // VPSLLDrr >+ 2484099871U, // VPSLLQYri >+ 2484099871U, // VPSLLQYrm >+ 2484099871U, // VPSLLQYrr >+ 3054520064U, // VPSLLQZmi >+ 352339712U, // VPSLLQZmik >+ 2484094720U, // VPSLLQZri >+ 352339712U, // VPSLLQZrik >+ 2484094720U, // VPSLLQZrm >+ 352339712U, // VPSLLQZrmk >+ 2484094720U, // VPSLLQZrr >+ 352339712U, // VPSLLQZrrk >+ 2484099871U, // VPSLLQri >+ 2484099871U, // VPSLLQrm >+ 2484099871U, // VPSLLQrr >+ 2484098364U, // VPSLLVDYrm >+ 2484098364U, // VPSLLVDYrr >+ 2484094179U, // VPSLLVDZrm >+ 2484094179U, // VPSLLVDZrr >+ 2484098364U, // VPSLLVDrm >+ 2484098364U, // VPSLLVDrr >+ 2484100039U, // VPSLLVQYrm >+ 2484100039U, // VPSLLVQYrr >+ 2484094986U, // VPSLLVQZrm >+ 2484094986U, // VPSLLVQZrr >+ 2484100039U, // VPSLLVQrm >+ 2484100039U, // VPSLLVQrr >+ 2484102067U, // VPSLLWYri >+ 2484102067U, // VPSLLWYrm >+ 2484102067U, // VPSLLWYrr >+ 2484102067U, // VPSLLWri >+ 2484102067U, // VPSLLWrm >+ 2484102067U, // VPSLLWrr >+ 2484096821U, // VPSRADYri >+ 2484096821U, // VPSRADYrm >+ 2484096821U, // VPSRADYrr >+ 3054518472U, // VPSRADZmi >+ 352338120U, // VPSRADZmik >+ 2484093128U, // VPSRADZri >+ 352338120U, // VPSRADZrik >+ 2484093128U, // VPSRADZrm >+ 352338120U, // VPSRADZrmk >+ 2484093128U, // VPSRADZrr >+ 352338120U, // VPSRADZrrk >+ 2484096821U, // VPSRADri >+ 2484096821U, // VPSRADrm >+ 2484096821U, // VPSRADrr >+ 3054519766U, // VPSRAQZmi >+ 352339414U, // VPSRAQZmik >+ 2484094422U, // VPSRAQZri >+ 352339414U, // VPSRAQZrik >+ 2484094422U, // VPSRAQZrm >+ 352339414U, // VPSRAQZrmk >+ 2484094422U, // VPSRAQZrr >+ 352339414U, // VPSRAQZrrk >+ 2484098355U, // VPSRAVDYrm >+ 2484098355U, // VPSRAVDYrr >+ 2484094169U, // VPSRAVDZrm >+ 2484094169U, // VPSRAVDZrr >+ 2484098355U, // VPSRAVDrm >+ 2484098355U, // VPSRAVDrr >+ 2484094976U, // VPSRAVQZrm >+ 2484094976U, // VPSRAVQZrr >+ 2484101804U, // VPSRAWYri >+ 2484101804U, // VPSRAWYrm >+ 2484101804U, // VPSRAWYrr >+ 2484101804U, // VPSRAWri >+ 2484101804U, // VPSRAWrm >+ 2484101804U, // VPSRAWrr >+ 2484099726U, // VPSRLDQYri >+ 2484099726U, // VPSRLDQri >+ 2484097060U, // VPSRLDYri >+ 2484097060U, // VPSRLDYrm >+ 2484097060U, // VPSRLDYrr >+ 3054518596U, // VPSRLDZmi >+ 352338244U, // VPSRLDZmik >+ 2484093252U, // VPSRLDZri >+ 352338244U, // VPSRLDZrik >+ 2484093252U, // VPSRLDZrm >+ 352338244U, // VPSRLDZrmk >+ 2484093252U, // VPSRLDZrr >+ 352338244U, // VPSRLDZrrk >+ 2484097060U, // VPSRLDri >+ 2484097060U, // VPSRLDrm >+ 2484097060U, // VPSRLDrr >+ 2484099879U, // VPSRLQYri >+ 2484099879U, // VPSRLQYrm >+ 2484099879U, // VPSRLQYrr >+ 3054520073U, // VPSRLQZmi >+ 352339721U, // VPSRLQZmik >+ 2484094729U, // VPSRLQZri >+ 352339721U, // VPSRLQZrik >+ 2484094729U, // VPSRLQZrm >+ 352339721U, // VPSRLQZrmk >+ 2484094729U, // VPSRLQZrr >+ 352339721U, // VPSRLQZrrk >+ 2484099879U, // VPSRLQri >+ 2484099879U, // VPSRLQrm >+ 2484099879U, // VPSRLQrr >+ 2484098373U, // VPSRLVDYrm >+ 2484098373U, // VPSRLVDYrr >+ 2484094189U, // VPSRLVDZrm >+ 2484094189U, // VPSRLVDZrr >+ 2484098373U, // VPSRLVDrm >+ 2484098373U, // VPSRLVDrr >+ 2484100048U, // VPSRLVQYrm >+ 2484100048U, // VPSRLVQYrr >+ 2484094996U, // VPSRLVQZrm >+ 2484094996U, // VPSRLVQZrr >+ 2484100048U, // VPSRLVQrm >+ 2484100048U, // VPSRLVQrr >+ 2484102084U, // VPSRLWYri >+ 2484102084U, // VPSRLWYrm >+ 2484102084U, // VPSRLWYrr >+ 2484102084U, // VPSRLWri >+ 2484102084U, // VPSRLWrm >+ 2484102084U, // VPSRLWrr >+ 2484096398U, // VPSUBBYrm >+ 2484096398U, // VPSUBBYrr >+ 2484096398U, // VPSUBBrm >+ 2484096398U, // VPSUBBrr >+ 2484096859U, // VPSUBDYrm >+ 2484096859U, // VPSUBDYrr >+ 2484093137U, // VPSUBDZrm >+ 2484093137U, // VPSUBDZrmb >+ 50348241U, // VPSUBDZrmbk >+ 2499821777U, // VPSUBDZrmbkz >+ 50348241U, // VPSUBDZrmk >+ 2499821777U, // VPSUBDZrmkz >+ 2484093137U, // VPSUBDZrr >+ 50348241U, // VPSUBDZrrk >+ 2499821777U, // VPSUBDZrrkz >+ 2484096859U, // VPSUBDrm >+ 2484096859U, // VPSUBDrr >+ 2484099580U, // VPSUBQYrm >+ 2484099580U, // VPSUBQYrr >+ 2484094431U, // VPSUBQZrm >+ 2484094431U, // VPSUBQZrmb >+ 50349535U, // VPSUBQZrmbk >+ 2499823071U, // VPSUBQZrmbkz >+ 50349535U, // VPSUBQZrmk >+ 2499823071U, // VPSUBQZrmkz >+ 2484094431U, // VPSUBQZrr >+ 50349535U, // VPSUBQZrrk >+ 2499823071U, // VPSUBQZrrkz >+ 2484099580U, // VPSUBQrm >+ 2484099580U, // VPSUBQrr >+ 2484096507U, // VPSUBSBYrm >+ 2484096507U, // VPSUBSBYrr >+ 2484096507U, // VPSUBSBrm >+ 2484096507U, // VPSUBSBrr >+ 2484102182U, // VPSUBSWYrm >+ 2484102182U, // VPSUBSWYrr >+ 2484102182U, // VPSUBSWrm >+ 2484102182U, // VPSUBSWrr >+ 2484096548U, // VPSUBUSBYrm >+ 2484096548U, // VPSUBUSBYrr >+ 2484096548U, // VPSUBUSBrm >+ 2484096548U, // VPSUBUSBrr >+ 2484102264U, // VPSUBUSWYrm >+ 2484102264U, // VPSUBUSWYrr >+ 2484102264U, // VPSUBUSWrm >+ 2484102264U, // VPSUBUSWrr >+ 2484101895U, // VPSUBWYrm >+ 2484101895U, // VPSUBWYrr >+ 2484101895U, // VPSUBWrm >+ 2484101895U, // VPSUBWrr >+ 2484093294U, // VPTESTMDZrm >+ 2484093294U, // VPTESTMDZrr >+ 2484094771U, // VPTESTMQZrm >+ 2484094771U, // VPTESTMQZrr >+ 2484093273U, // VPTESTNMDZrm >+ 2484093273U, // VPTESTNMDZrr >+ 2484094750U, // VPTESTNMQZrm >+ 2484094750U, // VPTESTNMQZrr >+ 839934503U, // VPTESTYrm >+ 336618023U, // VPTESTYrr >+ 537944615U, // VPTESTrm >+ 336618023U, // VPTESTrr >+ 2484101851U, // VPUNPCKHBWYrm >+ 2484101851U, // VPUNPCKHBWYrr >+ 2484101851U, // VPUNPCKHBWrm >+ 2484101851U, // VPUNPCKHBWrr >+ 2484099693U, // VPUNPCKHDQYrm >+ 2484099693U, // VPUNPCKHDQYrr >+ 2484094523U, // VPUNPCKHDQZrm >+ 2484094523U, // VPUNPCKHDQZrr >+ 2484099693U, // VPUNPCKHDQrm >+ 2484099693U, // VPUNPCKHDQrr >+ 2484099744U, // VPUNPCKHQDQYrm >+ 2484099744U, // VPUNPCKHQDQYrr >+ 2484094576U, // VPUNPCKHQDQZrm >+ 2484094576U, // VPUNPCKHQDQZrr >+ 2484099744U, // VPUNPCKHQDQrm >+ 2484099744U, // VPUNPCKHQDQrr >+ 2484098431U, // VPUNPCKHWDYrm >+ 2484098431U, // VPUNPCKHWDYrr >+ 2484098431U, // VPUNPCKHWDrm >+ 2484098431U, // VPUNPCKHWDrr >+ 2484101863U, // VPUNPCKLBWYrm >+ 2484101863U, // VPUNPCKLBWYrr >+ 2484101863U, // VPUNPCKLBWrm >+ 2484101863U, // VPUNPCKLBWrr >+ 2484099705U, // VPUNPCKLDQYrm >+ 2484099705U, // VPUNPCKLDQYrr >+ 2484094536U, // VPUNPCKLDQZrm >+ 2484094536U, // VPUNPCKLDQZrr >+ 2484099705U, // VPUNPCKLDQrm >+ 2484099705U, // VPUNPCKLDQrr >+ 2484099757U, // VPUNPCKLQDQYrm >+ 2484099757U, // VPUNPCKLQDQYrr >+ 2484094590U, // VPUNPCKLQDQZrm >+ 2484094590U, // VPUNPCKLQDQZrr >+ 2484099757U, // VPUNPCKLQDQrm >+ 2484099757U, // VPUNPCKLQDQrr >+ 2484098443U, // VPUNPCKLWDYrm >+ 2484098443U, // VPUNPCKLWDYrr >+ 2484098443U, // VPUNPCKLWDrm >+ 2484098443U, // VPUNPCKLWDrr >+ 2484093894U, // VPXORDZrm >+ 2484093894U, // VPXORDZrmb >+ 50348998U, // VPXORDZrmbk >+ 2499822534U, // VPXORDZrmbkz >+ 50348998U, // VPXORDZrmk >+ 2499822534U, // VPXORDZrmkz >+ 2484093894U, // VPXORDZrr >+ 50348998U, // VPXORDZrrk >+ 2499822534U, // VPXORDZrrkz >+ 2484094870U, // VPXORQZrm >+ 2484094870U, // VPXORQZrmb >+ 50349974U, // VPXORQZrmbk >+ 2499823510U, // VPXORQZrmbkz >+ 50349974U, // VPXORQZrmk >+ 2499823510U, // VPXORQZrmkz >+ 2484094870U, // VPXORQZrr >+ 50349974U, // VPXORQZrrk >+ 2499823510U, // VPXORQZrrkz >+ 2484100209U, // VPXORYrm >+ 2484100209U, // VPXORYrr >+ 2484100209U, // VPXORrm >+ 2484100209U, // VPXORrr >+ 974144139U, // VRCP14PDZm >+ 336609931U, // VRCP14PDZr >+ 974145843U, // VRCP14PSZm >+ 336611635U, // VRCP14PSZr >+ 2484093986U, // VRCP14SDrm >+ 2484093986U, // VRCP14SDrr >+ 2484095589U, // VRCP14SSrm >+ 2484095589U, // VRCP14SSrr >+ 974144163U, // VRCP28PDZm >+ 336609955U, // VRCP28PDZr >+ 336609955U, // VRCP28PDZrb >+ 974145867U, // VRCP28PSZm >+ 336611659U, // VRCP28PSZr >+ 336611659U, // VRCP28PSZrb >+ 2484094010U, // VRCP28SDrm >+ 2484094010U, // VRCP28SDrr >+ 2484094010U, // VRCP28SDrrb >+ 2484095613U, // VRCP28SSrm >+ 2484095613U, // VRCP28SSrr >+ 2484095613U, // VRCP28SSrrb >+ 940597076U, // VRCPPSYm >+ 940597076U, // VRCPPSYm_Int >+ 336617300U, // VRCPPSYr >+ 336617300U, // VRCPPSYr_Int >+ 537943892U, // VRCPPSm >+ 537943892U, // VRCPPSm_Int >+ 336617300U, // VRCPPSr >+ 336617300U, // VRCPPSr_Int >+ 2484101415U, // VRCPSSm >+ 2484101415U, // VRCPSSm_Int >+ 2484101415U, // VRCPSSr >+ 3121627880U, // VRNDSCALEPDZm >+ 2484093672U, // VRNDSCALEPDZr >+ 3121629584U, // VRNDSCALEPSZm >+ 2484095376U, // VRNDSCALEPSZr >+ 2484094043U, // VRNDSCALESDm >+ 2484094043U, // VRNDSCALESDr >+ 2484095637U, // VRNDSCALESSm >+ 2484095637U, // VRNDSCALESSr >+ 2685424166U, // VROUNDPDm >+ 2484097574U, // VROUNDPDr >+ 2685427393U, // VROUNDPSm >+ 2484100801U, // VROUNDPSr >+ 2484098144U, // VROUNDSDm >+ 2484098144U, // VROUNDSDr >+ 2484098144U, // VROUNDSDr_Int >+ 2484101370U, // VROUNDSSm >+ 2484101370U, // VROUNDSSr >+ 2484101370U, // VROUNDSSr_Int >+ 3088077350U, // VROUNDYPDm >+ 2484097574U, // VROUNDYPDr >+ 3088080577U, // VROUNDYPSm >+ 2484100801U, // VROUNDYPSr >+ 974144150U, // VRSQRT14PDZm >+ 336609942U, // VRSQRT14PDZr >+ 974145854U, // VRSQRT14PSZm >+ 336611646U, // VRSQRT14PSZr >+ 2484093997U, // VRSQRT14SDrm >+ 2484093997U, // VRSQRT14SDrr >+ 2484095600U, // VRSQRT14SSrm >+ 2484095600U, // VRSQRT14SSrr >+ 974144174U, // VRSQRT28PDZm >+ 336609966U, // VRSQRT28PDZr >+ 336609966U, // VRSQRT28PDZrb >+ 974145878U, // VRSQRT28PSZm >+ 336611670U, // VRSQRT28PSZr >+ 336611670U, // VRSQRT28PSZrb >+ 2484094021U, // VRSQRT28SDrm >+ 2484094021U, // VRSQRT28SDrr >+ 2484094021U, // VRSQRT28SDrrb >+ 2484095624U, // VRSQRT28SSrm >+ 2484095624U, // VRSQRT28SSrr >+ 2484095624U, // VRSQRT28SSrrb >+ 940597159U, // VRSQRTPSYm >+ 940597159U, // VRSQRTPSYm_Int >+ 336617383U, // VRSQRTPSYr >+ 336617383U, // VRSQRTPSYr_Int >+ 537943975U, // VRSQRTPSm >+ 537943975U, // VRSQRTPSm_Int >+ 336617383U, // VRSQRTPSr >+ 336617383U, // VRSQRTPSr_Int >+ 2484101440U, // VRSQRTSSm >+ 2484101440U, // VRSQRTSSm_Int >+ 2484101440U, // VRSQRTSSr >+ 705242U, // VSCATTERDPDZmr >+ 690562U, // VSCATTERDPSZmr >+ 321941652U, // VSCATTERPF0DPDm >+ 321941792U, // VSCATTERPF0DPSm >+ 389050586U, // VSCATTERPF0QPDm >+ 389050726U, // VSCATTERPF0QPSm >+ 321941687U, // VSCATTERPF1DPDm >+ 321941827U, // VSCATTERPF1DPSm >+ 389050621U, // VSCATTERPF1QPDm >+ 389050761U, // VSCATTERPF1QPSm >+ 705354U, // VSCATTERQPDZmr >+ 707058U, // VSCATTERQPSZmr >+ 2484097596U, // VSHUFPDYrmi >+ 2484097596U, // VSHUFPDYrri >+ 2484093686U, // VSHUFPDZrmi >+ 2484093686U, // VSHUFPDZrri >+ 2484097596U, // VSHUFPDrmi >+ 2484097596U, // VSHUFPDrri >+ 2484100823U, // VSHUFPSYrmi >+ 2484100823U, // VSHUFPSYrri >+ 2484095390U, // VSHUFPSZrmi >+ 2484095390U, // VSHUFPSZrri >+ 2484100823U, // VSHUFPSrmi >+ 2484100823U, // VSHUFPSrri >+ 940593889U, // VSQRTPDYm >+ 336614113U, // VSQRTPDYr >+ 974148321U, // VSQRTPDZrm >+ 336614113U, // VSQRTPDZrr >+ 537940705U, // VSQRTPDm >+ 336614113U, // VSQRTPDr >+ 940597169U, // VSQRTPSYm >+ 336617393U, // VSQRTPSYr >+ 974151601U, // VSQRTPSZrm >+ 336617393U, // VSQRTPSZrr >+ 537943985U, // VSQRTPSm >+ 336617393U, // VSQRTPSr >+ 2484098222U, // VSQRTSDZm >+ 2484098222U, // VSQRTSDZm_Int >+ 2484098222U, // VSQRTSDZr >+ 2484098222U, // VSQRTSDZr_Int >+ 2484098222U, // VSQRTSDm >+ 2484098222U, // VSQRTSDm_Int >+ 2484098222U, // VSQRTSDr >+ 2484101450U, // VSQRTSSZm >+ 2484101450U, // VSQRTSSZm_Int >+ 2484101450U, // VSQRTSSZr >+ 2484101450U, // VSQRTSSZr_Int >+ 2484101450U, // VSQRTSSm >+ 2484101450U, // VSQRTSSm_Int >+ 2484101450U, // VSQRTSSr >+ 72845U, // VSTMXCSR >+ 2484097497U, // VSUBPDYrm >+ 2484097497U, // VSUBPDYrr >+ 2484093627U, // VSUBPDZrm >+ 2484093627U, // VSUBPDZrmb >+ 352338619U, // VSUBPDZrmbk >+ 2499822267U, // VSUBPDZrmbkz >+ 352342489U, // VSUBPDZrmk >+ 2499826137U, // VSUBPDZrmkz >+ 2484093627U, // VSUBPDZrr >+ 352338619U, // VSUBPDZrrk >+ 2499822267U, // VSUBPDZrrkz >+ 2484097497U, // VSUBPDrm >+ 2484097497U, // VSUBPDrr >+ 2484100724U, // VSUBPSYrm >+ 2484100724U, // VSUBPSYrr >+ 2484095331U, // VSUBPSZrm >+ 2484095331U, // VSUBPSZrmb >+ 352340323U, // VSUBPSZrmbk >+ 2499823971U, // VSUBPSZrmbkz >+ 352345716U, // VSUBPSZrmk >+ 2499829364U, // VSUBPSZrmkz >+ 2484095331U, // VSUBPSZrr >+ 352340323U, // VSUBPSZrrk >+ 2499823971U, // VSUBPSZrrkz >+ 2484100724U, // VSUBPSrm >+ 2484100724U, // VSUBPSrr >+ 2484098107U, // VSUBSDZrm >+ 2484098107U, // VSUBSDZrr >+ 2484098107U, // VSUBSDrm >+ 2484098107U, // VSUBSDrm_Int >+ 2484098107U, // VSUBSDrr >+ 2484098107U, // VSUBSDrr_Int >+ 2484101333U, // VSUBSSZrm >+ 2484101333U, // VSUBSSZrr >+ 2484101333U, // VSUBSSrm >+ 2484101333U, // VSUBSSrm_Int >+ 2484101333U, // VSUBSSrr >+ 2484101333U, // VSUBSSrr_Int >+ 940593898U, // VTESTPDYrm >+ 336614122U, // VTESTPDYrr >+ 537940714U, // VTESTPDrm >+ 336614122U, // VTESTPDrr >+ 940597178U, // VTESTPSYrm >+ 336617402U, // VTESTPSYrr >+ 537943994U, // VTESTPSrm >+ 336617402U, // VTESTPSrr >+ 571495530U, // VUCOMISDZrm >+ 336614506U, // VUCOMISDZrr >+ 571495530U, // VUCOMISDrm >+ 336614506U, // VUCOMISDrr >+ 605053188U, // VUCOMISSZrm >+ 336617732U, // VUCOMISSZrr >+ 605053188U, // VUCOMISSrm >+ 336617732U, // VUCOMISSrr >+ 2484097605U, // VUNPCKHPDYrm >+ 2484097605U, // VUNPCKHPDYrr >+ 2484097605U, // VUNPCKHPDZrm >+ 2484097605U, // VUNPCKHPDZrr >+ 2484097605U, // VUNPCKHPDrm >+ 2484097605U, // VUNPCKHPDrr >+ 2484100832U, // VUNPCKHPSYrm >+ 2484100832U, // VUNPCKHPSYrr >+ 2484100832U, // VUNPCKHPSZrm >+ 2484100832U, // VUNPCKHPSZrr >+ 2484100832U, // VUNPCKHPSrm >+ 2484100832U, // VUNPCKHPSrr >+ 2484097647U, // VUNPCKLPDYrm >+ 2484097647U, // VUNPCKLPDYrr >+ 2484097647U, // VUNPCKLPDZrm >+ 2484097647U, // VUNPCKLPDZrr >+ 2484097647U, // VUNPCKLPDrm >+ 2484097647U, // VUNPCKLPDrr >+ 2484100894U, // VUNPCKLPSYrm >+ 2484100894U, // VUNPCKLPSYrr >+ 2484100894U, // VUNPCKLPSZrm >+ 2484100894U, // VUNPCKLPSZrr >+ 2484100894U, // VUNPCKLPSrm >+ 2484100894U, // VUNPCKLPSrr >+ 2484097743U, // VXORPDYrm >+ 2484097743U, // VXORPDYrr >+ 2484097743U, // VXORPDrm >+ 2484097743U, // VXORPDrr >+ 2484100990U, // VXORPSYrm >+ 2484100990U, // VXORPSYrr >+ 2484100990U, // VXORPSrm >+ 2484100990U, // VXORPSrr >+ 11661U, // VZEROALL >+ 11861U, // VZEROUPPER >+ 0U, // V_SET0 >+ 0U, // V_SETALLONES >+ 153629U, // W64ALLOCA >+ 12122U, // WAIT >+ 11389U, // WBINVD >+ 11718U, // WIN_ALLOCA >+ 11594U, // WIN_FTOL_32 >+ 11594U, // WIN_FTOL_64 >+ 22150U, // WRFSBASE >+ 22150U, // WRFSBASE64 >+ 22170U, // WRGSBASE >+ 22170U, // WRGSBASE64 >+ 11895U, // WRMSR >+ 25084U, // XABORT >+ 11460U, // XACQUIRE_PREFIX >+ 1085319U, // XADD16rm >+ 336613255U, // XADD16rr >+ 1118087U, // XADD32rm >+ 336613255U, // XADD32rr >+ 1134471U, // XADD64rm >+ 336613255U, // XADD64rr >+ 1150855U, // XADD8rm >+ 336613255U, // XADD8rr >+ 11129U, // XBEGIN >+ 153784U, // XBEGIN_4 >+ 26314U, // XCHG16ar >+ 464616U, // XCHG16rm >+ 726760U, // XCHG16rr >+ 26477U, // XCHG32ar >+ 26477U, // XCHG32ar64 >+ 481000U, // XCHG32rm >+ 726760U, // XCHG32rr >+ 26601U, // XCHG64ar >+ 497384U, // XCHG64rm >+ 726760U, // XCHG64rr >+ 513768U, // XCHG8rm >+ 726760U, // XCHG8rr >+ 22289U, // XCH_F >+ 11278U, // XCRYPTCBC >+ 11222U, // XCRYPTCFB >+ 11901U, // XCRYPTCTR >+ 11212U, // XCRYPTECB >+ 11232U, // XCRYPTOFB >+ 11354U, // XEND >+ 12177U, // XGETBV >+ 11262U, // XLAT >+ 26341U, // XOR16i16 >+ 1088627U, // XOR16mi >+ 1088627U, // XOR16mi8 >+ 1088627U, // XOR16mr >+ 34659443U, // XOR16ri >+ 34659443U, // XOR16ri8 >+ 68213875U, // XOR16rm >+ 34659443U, // XOR16rr >+ 34626675U, // XOR16rr_REV >+ 26507U, // XOR32i32 >+ 1121395U, // XOR32mi >+ 1121395U, // XOR32mi8 >+ 1121395U, // XOR32mr >+ 34659443U, // XOR32ri >+ 34659443U, // XOR32ri8 >+ 101768307U, // XOR32rm >+ 34659443U, // XOR32rr >+ 34626675U, // XOR32rr_REV >+ 26646U, // XOR64i32 >+ 1137779U, // XOR64mi32 >+ 1137779U, // XOR64mi8 >+ 1137779U, // XOR64mr >+ 34659443U, // XOR64ri32 >+ 34659443U, // XOR64ri8 >+ 135322739U, // XOR64rm >+ 34659443U, // XOR64rr >+ 34626675U, // XOR64rr_REV >+ 26229U, // XOR8i8 >+ 1154163U, // XOR8mi >+ 1154163U, // XOR8mr >+ 34659443U, // XOR8ri >+ 34659443U, // XOR8ri8 >+ 168877171U, // XOR8rm >+ 34659443U, // XOR8rr >+ 34626675U, // XOR8rr_REV >+ 202396368U, // XORPDrm >+ 34624208U, // XORPDrr >+ 202399615U, // XORPSrm >+ 34627455U, // XORPSrr >+ 11476U, // XRELEASE_PREFIX >+ 285801U, // XRSTOR >+ 281616U, // XRSTOR64 >+ 284359U, // XSAVE >+ 281606U, // XSAVE64 >+ 287218U, // XSAVEOPT >+ 281626U, // XSAVEOPT64 >+ 12184U, // XSETBV >+ 10856U, // XSHA1 >+ 11091U, // XSHA256 >+ 11469U, // XSTORE >+ 12160U, // XTEST >+ 0U >+ }; >+ >+ static const uint32_t OpInfo2[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 0U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 0U, // BUNDLE >+ 0U, // LIFETIME_START >+ 0U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 0U, // AAA >+ 0U, // AAD8i8 >+ 0U, // AAM8i8 >+ 0U, // AAS >+ 0U, // ABS_F >+ 0U, // ABS_Fp32 >+ 0U, // ABS_Fp64 >+ 0U, // ABS_Fp80 >+ 0U, // ACQUIRE_MOV16rm >+ 0U, // ACQUIRE_MOV32rm >+ 0U, // ACQUIRE_MOV64rm >+ 0U, // ACQUIRE_MOV8rm >+ 0U, // ADC16i16 >+ 0U, // ADC16mi >+ 0U, // ADC16mi8 >+ 0U, // ADC16mr >+ 0U, // ADC16ri >+ 0U, // ADC16ri8 >+ 0U, // ADC16rm >+ 0U, // ADC16rr >+ 0U, // ADC16rr_REV >+ 0U, // ADC32i32 >+ 0U, // ADC32mi >+ 0U, // ADC32mi8 >+ 0U, // ADC32mr >+ 0U, // ADC32ri >+ 0U, // ADC32ri8 >+ 0U, // ADC32rm >+ 0U, // ADC32rr >+ 0U, // ADC32rr_REV >+ 0U, // ADC64i32 >+ 0U, // ADC64mi32 >+ 0U, // ADC64mi8 >+ 0U, // ADC64mr >+ 0U, // ADC64ri32 >+ 0U, // ADC64ri8 >+ 0U, // ADC64rm >+ 0U, // ADC64rr >+ 0U, // ADC64rr_REV >+ 0U, // ADC8i8 >+ 0U, // ADC8mi >+ 0U, // ADC8mr >+ 0U, // ADC8ri >+ 0U, // ADC8rm >+ 0U, // ADC8rr >+ 0U, // ADC8rr_REV >+ 0U, // ADCX32rm >+ 0U, // ADCX32rr >+ 0U, // ADCX64rm >+ 0U, // ADCX64rr >+ 0U, // ADD16i16 >+ 0U, // ADD16mi >+ 0U, // ADD16mi8 >+ 0U, // ADD16mr >+ 0U, // ADD16ri >+ 0U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 0U, // ADD16rm >+ 0U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 0U, // ADD16rr_REV >+ 0U, // ADD32i32 >+ 0U, // ADD32mi >+ 0U, // ADD32mi8 >+ 0U, // ADD32mr >+ 0U, // ADD32ri >+ 0U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 0U, // ADD32rm >+ 0U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 0U, // ADD32rr_REV >+ 0U, // ADD64i32 >+ 0U, // ADD64mi32 >+ 0U, // ADD64mi8 >+ 0U, // ADD64mr >+ 0U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 0U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 0U, // ADD64rm >+ 0U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 0U, // ADD64rr_REV >+ 0U, // ADD8i8 >+ 0U, // ADD8mi >+ 0U, // ADD8mr >+ 0U, // ADD8ri >+ 0U, // ADD8ri8 >+ 0U, // ADD8rm >+ 0U, // ADD8rr >+ 0U, // ADD8rr_REV >+ 0U, // ADDPDrm >+ 0U, // ADDPDrr >+ 0U, // ADDPSrm >+ 0U, // ADDPSrr >+ 0U, // ADDSDrm >+ 0U, // ADDSDrm_Int >+ 0U, // ADDSDrr >+ 0U, // ADDSDrr_Int >+ 0U, // ADDSSrm >+ 0U, // ADDSSrm_Int >+ 0U, // ADDSSrr >+ 0U, // ADDSSrr_Int >+ 0U, // ADDSUBPDrm >+ 0U, // ADDSUBPDrr >+ 0U, // ADDSUBPSrm >+ 0U, // ADDSUBPSrr >+ 0U, // ADD_F32m >+ 0U, // ADD_F64m >+ 0U, // ADD_FI16m >+ 0U, // ADD_FI32m >+ 0U, // ADD_FPrST0 >+ 0U, // ADD_FST0r >+ 0U, // ADD_Fp32 >+ 0U, // ADD_Fp32m >+ 0U, // ADD_Fp64 >+ 0U, // ADD_Fp64m >+ 0U, // ADD_Fp64m32 >+ 0U, // ADD_Fp80 >+ 0U, // ADD_Fp80m32 >+ 0U, // ADD_Fp80m64 >+ 0U, // ADD_FpI16m32 >+ 0U, // ADD_FpI16m64 >+ 0U, // ADD_FpI16m80 >+ 0U, // ADD_FpI32m32 >+ 0U, // ADD_FpI32m64 >+ 0U, // ADD_FpI32m80 >+ 0U, // ADD_FrST0 >+ 0U, // ADJCALLSTACKDOWN32 >+ 0U, // ADJCALLSTACKDOWN64 >+ 0U, // ADJCALLSTACKUP32 >+ 0U, // ADJCALLSTACKUP64 >+ 0U, // ADOX32rm >+ 0U, // ADOX32rr >+ 0U, // ADOX64rm >+ 0U, // ADOX64rr >+ 0U, // AESDECLASTrm >+ 0U, // AESDECLASTrr >+ 0U, // AESDECrm >+ 0U, // AESDECrr >+ 0U, // AESENCLASTrm >+ 0U, // AESENCLASTrr >+ 0U, // AESENCrm >+ 0U, // AESENCrr >+ 0U, // AESIMCrm >+ 0U, // AESIMCrr >+ 0U, // AESKEYGENASSIST128rm >+ 8U, // AESKEYGENASSIST128rr >+ 0U, // AND16i16 >+ 0U, // AND16mi >+ 0U, // AND16mi8 >+ 0U, // AND16mr >+ 0U, // AND16ri >+ 0U, // AND16ri8 >+ 0U, // AND16rm >+ 0U, // AND16rr >+ 0U, // AND16rr_REV >+ 0U, // AND32i32 >+ 0U, // AND32mi >+ 0U, // AND32mi8 >+ 0U, // AND32mr >+ 0U, // AND32ri >+ 0U, // AND32ri8 >+ 0U, // AND32rm >+ 0U, // AND32rr >+ 0U, // AND32rr_REV >+ 0U, // AND64i32 >+ 0U, // AND64mi32 >+ 0U, // AND64mi8 >+ 0U, // AND64mr >+ 0U, // AND64ri32 >+ 0U, // AND64ri8 >+ 0U, // AND64rm >+ 0U, // AND64rr >+ 0U, // AND64rr_REV >+ 0U, // AND8i8 >+ 0U, // AND8mi >+ 0U, // AND8mr >+ 0U, // AND8ri >+ 0U, // AND8ri8 >+ 0U, // AND8rm >+ 0U, // AND8rr >+ 0U, // AND8rr_REV >+ 16U, // ANDN32rm >+ 8U, // ANDN32rr >+ 24U, // ANDN64rm >+ 8U, // ANDN64rr >+ 0U, // ANDNPDrm >+ 0U, // ANDNPDrr >+ 0U, // ANDNPSrm >+ 0U, // ANDNPSrr >+ 0U, // ANDPDrm >+ 0U, // ANDPDrr >+ 0U, // ANDPSrm >+ 0U, // ANDPSrr >+ 0U, // ARPL16mr >+ 0U, // ARPL16rr >+ 0U, // AVX2_SETALLONES >+ 0U, // AVX512_512_SET0 >+ 0U, // AVX_SET0 >+ 0U, // BEXTR32rm >+ 8U, // BEXTR32rr >+ 0U, // BEXTR64rm >+ 8U, // BEXTR64rr >+ 0U, // BEXTRI32mi >+ 8U, // BEXTRI32ri >+ 0U, // BEXTRI64mi >+ 8U, // BEXTRI64ri >+ 0U, // BLCFILL32rm >+ 0U, // BLCFILL32rr >+ 0U, // BLCFILL64rm >+ 0U, // BLCFILL64rr >+ 0U, // BLCI32rm >+ 0U, // BLCI32rr >+ 0U, // BLCI64rm >+ 0U, // BLCI64rr >+ 0U, // BLCIC32rm >+ 0U, // BLCIC32rr >+ 0U, // BLCIC64rm >+ 0U, // BLCIC64rr >+ 0U, // BLCMSK32rm >+ 0U, // BLCMSK32rr >+ 0U, // BLCMSK64rm >+ 0U, // BLCMSK64rr >+ 0U, // BLCS32rm >+ 0U, // BLCS32rr >+ 0U, // BLCS64rm >+ 0U, // BLCS64rr >+ 32U, // BLENDPDrmi >+ 40U, // BLENDPDrri >+ 32U, // BLENDPSrmi >+ 40U, // BLENDPSrri >+ 0U, // BLENDVPDrm0 >+ 0U, // BLENDVPDrr0 >+ 0U, // BLENDVPSrm0 >+ 0U, // BLENDVPSrr0 >+ 0U, // BLSFILL32rm >+ 0U, // BLSFILL32rr >+ 0U, // BLSFILL64rm >+ 0U, // BLSFILL64rr >+ 0U, // BLSI32rm >+ 0U, // BLSI32rr >+ 0U, // BLSI64rm >+ 0U, // BLSI64rr >+ 0U, // BLSIC32rm >+ 0U, // BLSIC32rr >+ 0U, // BLSIC64rm >+ 0U, // BLSIC64rr >+ 0U, // BLSMSK32rm >+ 0U, // BLSMSK32rr >+ 0U, // BLSMSK64rm >+ 0U, // BLSMSK64rr >+ 0U, // BLSR32rm >+ 0U, // BLSR32rr >+ 0U, // BLSR64rm >+ 0U, // BLSR64rr >+ 0U, // BOUNDS16rm >+ 0U, // BOUNDS32rm >+ 0U, // BSF16rm >+ 0U, // BSF16rr >+ 0U, // BSF32rm >+ 0U, // BSF32rr >+ 0U, // BSF64rm >+ 0U, // BSF64rr >+ 0U, // BSR16rm >+ 0U, // BSR16rr >+ 0U, // BSR32rm >+ 0U, // BSR32rr >+ 0U, // BSR64rm >+ 0U, // BSR64rr >+ 0U, // BSWAP32r >+ 0U, // BSWAP64r >+ 0U, // BT16mi8 >+ 0U, // BT16mr >+ 0U, // BT16ri8 >+ 0U, // BT16rr >+ 0U, // BT32mi8 >+ 0U, // BT32mr >+ 0U, // BT32ri8 >+ 0U, // BT32rr >+ 0U, // BT64mi8 >+ 0U, // BT64mr >+ 0U, // BT64ri8 >+ 0U, // BT64rr >+ 0U, // BTC16mi8 >+ 0U, // BTC16mr >+ 0U, // BTC16ri8 >+ 0U, // BTC16rr >+ 0U, // BTC32mi8 >+ 0U, // BTC32mr >+ 0U, // BTC32ri8 >+ 0U, // BTC32rr >+ 0U, // BTC64mi8 >+ 0U, // BTC64mr >+ 0U, // BTC64ri8 >+ 0U, // BTC64rr >+ 0U, // BTR16mi8 >+ 0U, // BTR16mr >+ 0U, // BTR16ri8 >+ 0U, // BTR16rr >+ 0U, // BTR32mi8 >+ 0U, // BTR32mr >+ 0U, // BTR32ri8 >+ 0U, // BTR32rr >+ 0U, // BTR64mi8 >+ 0U, // BTR64mr >+ 0U, // BTR64ri8 >+ 0U, // BTR64rr >+ 0U, // BTS16mi8 >+ 0U, // BTS16mr >+ 0U, // BTS16ri8 >+ 0U, // BTS16rr >+ 0U, // BTS32mi8 >+ 0U, // BTS32mr >+ 0U, // BTS32ri8 >+ 0U, // BTS32rr >+ 0U, // BTS64mi8 >+ 0U, // BTS64mr >+ 0U, // BTS64ri8 >+ 0U, // BTS64rr >+ 0U, // BZHI32rm >+ 8U, // BZHI32rr >+ 0U, // BZHI64rm >+ 8U, // BZHI64rr >+ 0U, // CALL16m >+ 0U, // CALL16r >+ 0U, // CALL32m >+ 0U, // CALL32r >+ 0U, // CALL64m >+ 0U, // CALL64pcrel32 >+ 0U, // CALL64r >+ 0U, // CALLpcrel16 >+ 0U, // CALLpcrel32 >+ 0U, // CBW >+ 0U, // CDQ >+ 0U, // CDQE >+ 0U, // CHS_F >+ 0U, // CHS_Fp32 >+ 0U, // CHS_Fp64 >+ 0U, // CHS_Fp80 >+ 0U, // CLAC >+ 0U, // CLC >+ 0U, // CLD >+ 0U, // CLFLUSH >+ 0U, // CLGI >+ 0U, // CLI >+ 0U, // CLTS >+ 0U, // CMC >+ 0U, // CMOVA16rm >+ 0U, // CMOVA16rr >+ 0U, // CMOVA32rm >+ 0U, // CMOVA32rr >+ 0U, // CMOVA64rm >+ 0U, // CMOVA64rr >+ 0U, // CMOVAE16rm >+ 0U, // CMOVAE16rr >+ 0U, // CMOVAE32rm >+ 0U, // CMOVAE32rr >+ 0U, // CMOVAE64rm >+ 0U, // CMOVAE64rr >+ 0U, // CMOVB16rm >+ 0U, // CMOVB16rr >+ 0U, // CMOVB32rm >+ 0U, // CMOVB32rr >+ 0U, // CMOVB64rm >+ 0U, // CMOVB64rr >+ 0U, // CMOVBE16rm >+ 0U, // CMOVBE16rr >+ 0U, // CMOVBE32rm >+ 0U, // CMOVBE32rr >+ 0U, // CMOVBE64rm >+ 0U, // CMOVBE64rr >+ 0U, // CMOVBE_F >+ 0U, // CMOVBE_Fp32 >+ 0U, // CMOVBE_Fp64 >+ 0U, // CMOVBE_Fp80 >+ 0U, // CMOVB_F >+ 0U, // CMOVB_Fp32 >+ 0U, // CMOVB_Fp64 >+ 0U, // CMOVB_Fp80 >+ 0U, // CMOVE16rm >+ 0U, // CMOVE16rr >+ 0U, // CMOVE32rm >+ 0U, // CMOVE32rr >+ 0U, // CMOVE64rm >+ 0U, // CMOVE64rr >+ 0U, // CMOVE_F >+ 0U, // CMOVE_Fp32 >+ 0U, // CMOVE_Fp64 >+ 0U, // CMOVE_Fp80 >+ 0U, // CMOVG16rm >+ 0U, // CMOVG16rr >+ 0U, // CMOVG32rm >+ 0U, // CMOVG32rr >+ 0U, // CMOVG64rm >+ 0U, // CMOVG64rr >+ 0U, // CMOVGE16rm >+ 0U, // CMOVGE16rr >+ 0U, // CMOVGE32rm >+ 0U, // CMOVGE32rr >+ 0U, // CMOVGE64rm >+ 0U, // CMOVGE64rr >+ 0U, // CMOVL16rm >+ 0U, // CMOVL16rr >+ 0U, // CMOVL32rm >+ 0U, // CMOVL32rr >+ 0U, // CMOVL64rm >+ 0U, // CMOVL64rr >+ 0U, // CMOVLE16rm >+ 0U, // CMOVLE16rr >+ 0U, // CMOVLE32rm >+ 0U, // CMOVLE32rr >+ 0U, // CMOVLE64rm >+ 0U, // CMOVLE64rr >+ 0U, // CMOVNBE_F >+ 0U, // CMOVNBE_Fp32 >+ 0U, // CMOVNBE_Fp64 >+ 0U, // CMOVNBE_Fp80 >+ 0U, // CMOVNB_F >+ 0U, // CMOVNB_Fp32 >+ 0U, // CMOVNB_Fp64 >+ 0U, // CMOVNB_Fp80 >+ 0U, // CMOVNE16rm >+ 0U, // CMOVNE16rr >+ 0U, // CMOVNE32rm >+ 0U, // CMOVNE32rr >+ 0U, // CMOVNE64rm >+ 0U, // CMOVNE64rr >+ 0U, // CMOVNE_F >+ 0U, // CMOVNE_Fp32 >+ 0U, // CMOVNE_Fp64 >+ 0U, // CMOVNE_Fp80 >+ 0U, // CMOVNO16rm >+ 0U, // CMOVNO16rr >+ 0U, // CMOVNO32rm >+ 0U, // CMOVNO32rr >+ 0U, // CMOVNO64rm >+ 0U, // CMOVNO64rr >+ 0U, // CMOVNP16rm >+ 0U, // CMOVNP16rr >+ 0U, // CMOVNP32rm >+ 0U, // CMOVNP32rr >+ 0U, // CMOVNP64rm >+ 0U, // CMOVNP64rr >+ 0U, // CMOVNP_F >+ 0U, // CMOVNP_Fp32 >+ 0U, // CMOVNP_Fp64 >+ 0U, // CMOVNP_Fp80 >+ 0U, // CMOVNS16rm >+ 0U, // CMOVNS16rr >+ 0U, // CMOVNS32rm >+ 0U, // CMOVNS32rr >+ 0U, // CMOVNS64rm >+ 0U, // CMOVNS64rr >+ 0U, // CMOVO16rm >+ 0U, // CMOVO16rr >+ 0U, // CMOVO32rm >+ 0U, // CMOVO32rr >+ 0U, // CMOVO64rm >+ 0U, // CMOVO64rr >+ 0U, // CMOVP16rm >+ 0U, // CMOVP16rr >+ 0U, // CMOVP32rm >+ 0U, // CMOVP32rr >+ 0U, // CMOVP64rm >+ 0U, // CMOVP64rr >+ 0U, // CMOVP_F >+ 0U, // CMOVP_Fp32 >+ 0U, // CMOVP_Fp64 >+ 0U, // CMOVP_Fp80 >+ 0U, // CMOVS16rm >+ 0U, // CMOVS16rr >+ 0U, // CMOVS32rm >+ 0U, // CMOVS32rr >+ 0U, // CMOVS64rm >+ 0U, // CMOVS64rr >+ 0U, // CMOV_FR32 >+ 0U, // CMOV_FR64 >+ 0U, // CMOV_GR16 >+ 0U, // CMOV_GR32 >+ 0U, // CMOV_GR8 >+ 0U, // CMOV_RFP32 >+ 0U, // CMOV_RFP64 >+ 0U, // CMOV_RFP80 >+ 0U, // CMOV_V16F32 >+ 0U, // CMOV_V2F64 >+ 0U, // CMOV_V2I64 >+ 0U, // CMOV_V4F32 >+ 0U, // CMOV_V4F64 >+ 0U, // CMOV_V4I64 >+ 0U, // CMOV_V8F32 >+ 0U, // CMOV_V8F64 >+ 0U, // CMOV_V8I64 >+ 0U, // CMP16i16 >+ 0U, // CMP16mi >+ 0U, // CMP16mi8 >+ 0U, // CMP16mr >+ 0U, // CMP16ri >+ 0U, // CMP16ri8 >+ 0U, // CMP16rm >+ 0U, // CMP16rr >+ 0U, // CMP16rr_REV >+ 0U, // CMP32i32 >+ 0U, // CMP32mi >+ 0U, // CMP32mi8 >+ 0U, // CMP32mr >+ 0U, // CMP32ri >+ 0U, // CMP32ri8 >+ 0U, // CMP32rm >+ 0U, // CMP32rr >+ 0U, // CMP32rr_REV >+ 0U, // CMP64i32 >+ 0U, // CMP64mi32 >+ 0U, // CMP64mi8 >+ 0U, // CMP64mr >+ 0U, // CMP64ri32 >+ 0U, // CMP64ri8 >+ 0U, // CMP64rm >+ 0U, // CMP64rr >+ 0U, // CMP64rr_REV >+ 0U, // CMP8i8 >+ 0U, // CMP8mi >+ 0U, // CMP8mr >+ 0U, // CMP8ri >+ 0U, // CMP8rm >+ 0U, // CMP8rr >+ 0U, // CMP8rr_REV >+ 0U, // CMPPDrmi >+ 32U, // CMPPDrmi_alt >+ 0U, // CMPPDrri >+ 40U, // CMPPDrri_alt >+ 0U, // CMPPSrmi >+ 32U, // CMPPSrmi_alt >+ 0U, // CMPPSrri >+ 40U, // CMPPSrri_alt >+ 0U, // CMPSB >+ 0U, // CMPSDrm >+ 32U, // CMPSDrm_alt >+ 0U, // CMPSDrr >+ 40U, // CMPSDrr_alt >+ 0U, // CMPSL >+ 0U, // CMPSQ >+ 0U, // CMPSSrm >+ 32U, // CMPSSrm_alt >+ 0U, // CMPSSrr >+ 40U, // CMPSSrr_alt >+ 0U, // CMPSW >+ 0U, // CMPXCHG16B >+ 0U, // CMPXCHG16rm >+ 0U, // CMPXCHG16rr >+ 0U, // CMPXCHG32rm >+ 0U, // CMPXCHG32rr >+ 0U, // CMPXCHG64rm >+ 0U, // CMPXCHG64rr >+ 0U, // CMPXCHG8B >+ 0U, // CMPXCHG8rm >+ 0U, // CMPXCHG8rr >+ 0U, // COMISDrm >+ 0U, // COMISDrr >+ 0U, // COMISSrm >+ 0U, // COMISSrr >+ 0U, // COMP_FST0r >+ 0U, // COM_FIPr >+ 0U, // COM_FIr >+ 0U, // COM_FST0r >+ 0U, // COS_F >+ 0U, // COS_Fp32 >+ 0U, // COS_Fp64 >+ 0U, // COS_Fp80 >+ 0U, // CPUID32 >+ 0U, // CPUID64 >+ 0U, // CQO >+ 0U, // CRC32r32m16 >+ 0U, // CRC32r32m32 >+ 0U, // CRC32r32m8 >+ 0U, // CRC32r32r16 >+ 0U, // CRC32r32r32 >+ 0U, // CRC32r32r8 >+ 0U, // CRC32r64m64 >+ 0U, // CRC32r64m8 >+ 0U, // CRC32r64r64 >+ 0U, // CRC32r64r8 >+ 0U, // CVTDQ2PDrm >+ 0U, // CVTDQ2PDrr >+ 0U, // CVTDQ2PSrm >+ 0U, // CVTDQ2PSrr >+ 0U, // CVTPD2DQrm >+ 0U, // CVTPD2DQrr >+ 0U, // CVTPD2PSrm >+ 0U, // CVTPD2PSrr >+ 0U, // CVTPS2DQrm >+ 0U, // CVTPS2DQrr >+ 0U, // CVTPS2PDrm >+ 0U, // CVTPS2PDrr >+ 0U, // CVTSD2SI64rm >+ 0U, // CVTSD2SI64rr >+ 0U, // CVTSD2SIrm >+ 0U, // CVTSD2SIrr >+ 0U, // CVTSD2SSrm >+ 0U, // CVTSD2SSrr >+ 0U, // CVTSI2SD64rm >+ 0U, // CVTSI2SD64rr >+ 0U, // CVTSI2SDrm >+ 0U, // CVTSI2SDrr >+ 0U, // CVTSI2SS64rm >+ 0U, // CVTSI2SS64rr >+ 0U, // CVTSI2SSrm >+ 0U, // CVTSI2SSrr >+ 0U, // CVTSS2SDrm >+ 0U, // CVTSS2SDrr >+ 0U, // CVTSS2SI64rm >+ 0U, // CVTSS2SI64rr >+ 0U, // CVTSS2SIrm >+ 0U, // CVTSS2SIrr >+ 0U, // CVTTPD2DQrm >+ 0U, // CVTTPD2DQrr >+ 0U, // CVTTPS2DQrm >+ 0U, // CVTTPS2DQrr >+ 0U, // CVTTSD2SI64rm >+ 0U, // CVTTSD2SI64rr >+ 0U, // CVTTSD2SIrm >+ 0U, // CVTTSD2SIrr >+ 0U, // CVTTSS2SI64rm >+ 0U, // CVTTSS2SI64rr >+ 0U, // CVTTSS2SIrm >+ 0U, // CVTTSS2SIrr >+ 0U, // CWD >+ 0U, // CWDE >+ 0U, // DAA >+ 0U, // DAS >+ 0U, // DATA16_PREFIX >+ 0U, // DEC16m >+ 0U, // DEC16r >+ 0U, // DEC32_16r >+ 0U, // DEC32_32r >+ 0U, // DEC32m >+ 0U, // DEC32r >+ 0U, // DEC64_16m >+ 0U, // DEC64_16r >+ 0U, // DEC64_32m >+ 0U, // DEC64_32r >+ 0U, // DEC64m >+ 0U, // DEC64r >+ 0U, // DEC8m >+ 0U, // DEC8r >+ 0U, // DIV16m >+ 0U, // DIV16r >+ 0U, // DIV32m >+ 0U, // DIV32r >+ 0U, // DIV64m >+ 0U, // DIV64r >+ 0U, // DIV8m >+ 0U, // DIV8r >+ 0U, // DIVPDrm >+ 0U, // DIVPDrr >+ 0U, // DIVPSrm >+ 0U, // DIVPSrr >+ 0U, // DIVR_F32m >+ 0U, // DIVR_F64m >+ 0U, // DIVR_FI16m >+ 0U, // DIVR_FI32m >+ 0U, // DIVR_FPrST0 >+ 0U, // DIVR_FST0r >+ 0U, // DIVR_Fp32m >+ 0U, // DIVR_Fp64m >+ 0U, // DIVR_Fp64m32 >+ 0U, // DIVR_Fp80m32 >+ 0U, // DIVR_Fp80m64 >+ 0U, // DIVR_FpI16m32 >+ 0U, // DIVR_FpI16m64 >+ 0U, // DIVR_FpI16m80 >+ 0U, // DIVR_FpI32m32 >+ 0U, // DIVR_FpI32m64 >+ 0U, // DIVR_FpI32m80 >+ 0U, // DIVR_FrST0 >+ 0U, // DIVSDrm >+ 0U, // DIVSDrm_Int >+ 0U, // DIVSDrr >+ 0U, // DIVSDrr_Int >+ 0U, // DIVSSrm >+ 0U, // DIVSSrm_Int >+ 0U, // DIVSSrr >+ 0U, // DIVSSrr_Int >+ 0U, // DIV_F32m >+ 0U, // DIV_F64m >+ 0U, // DIV_FI16m >+ 0U, // DIV_FI32m >+ 0U, // DIV_FPrST0 >+ 0U, // DIV_FST0r >+ 0U, // DIV_Fp32 >+ 0U, // DIV_Fp32m >+ 0U, // DIV_Fp64 >+ 0U, // DIV_Fp64m >+ 0U, // DIV_Fp64m32 >+ 0U, // DIV_Fp80 >+ 0U, // DIV_Fp80m32 >+ 0U, // DIV_Fp80m64 >+ 0U, // DIV_FpI16m32 >+ 0U, // DIV_FpI16m64 >+ 0U, // DIV_FpI16m80 >+ 0U, // DIV_FpI32m32 >+ 0U, // DIV_FpI32m64 >+ 0U, // DIV_FpI32m80 >+ 0U, // DIV_FrST0 >+ 32U, // DPPDrmi >+ 40U, // DPPDrri >+ 32U, // DPPSrmi >+ 40U, // DPPSrri >+ 0U, // EH_RETURN >+ 0U, // EH_RETURN64 >+ 0U, // EH_SjLj_LongJmp32 >+ 0U, // EH_SjLj_LongJmp64 >+ 0U, // EH_SjLj_SetJmp32 >+ 0U, // EH_SjLj_SetJmp64 >+ 0U, // EH_SjLj_Setup >+ 0U, // ENCLS >+ 0U, // ENCLU >+ 0U, // ENTER >+ 0U, // EXTRACTPSmr >+ 8U, // EXTRACTPSrr >+ 0U, // EXTRQ >+ 40U, // EXTRQI >+ 0U, // F2XM1 >+ 0U, // FARCALL16i >+ 0U, // FARCALL16m >+ 0U, // FARCALL32i >+ 0U, // FARCALL32m >+ 0U, // FARCALL64 >+ 0U, // FARJMP16i >+ 0U, // FARJMP16m >+ 0U, // FARJMP32i >+ 0U, // FARJMP32m >+ 0U, // FARJMP64 >+ 0U, // FBLDm >+ 0U, // FBSTPm >+ 0U, // FCOM32m >+ 0U, // FCOM64m >+ 0U, // FCOMP32m >+ 0U, // FCOMP64m >+ 0U, // FCOMPP >+ 0U, // FDECSTP >+ 0U, // FEMMS >+ 0U, // FFREE >+ 0U, // FICOM16m >+ 0U, // FICOM32m >+ 0U, // FICOMP16m >+ 0U, // FICOMP32m >+ 0U, // FINCSTP >+ 0U, // FLDCW16m >+ 0U, // FLDENVm >+ 0U, // FLDL2E >+ 0U, // FLDL2T >+ 0U, // FLDLG2 >+ 0U, // FLDLN2 >+ 0U, // FLDPI >+ 0U, // FNCLEX >+ 0U, // FNINIT >+ 0U, // FNOP >+ 0U, // FNSTCW16m >+ 0U, // FNSTSW16r >+ 0U, // FNSTSWm >+ 0U, // FP32_TO_INT16_IN_MEM >+ 0U, // FP32_TO_INT32_IN_MEM >+ 0U, // FP32_TO_INT64_IN_MEM >+ 0U, // FP64_TO_INT16_IN_MEM >+ 0U, // FP64_TO_INT32_IN_MEM >+ 0U, // FP64_TO_INT64_IN_MEM >+ 0U, // FP80_TO_INT16_IN_MEM >+ 0U, // FP80_TO_INT32_IN_MEM >+ 0U, // FP80_TO_INT64_IN_MEM >+ 0U, // FPATAN >+ 0U, // FPREM >+ 0U, // FPREM1 >+ 0U, // FPTAN >+ 0U, // FRNDINT >+ 0U, // FRSTORm >+ 0U, // FSAVEm >+ 0U, // FSCALE >+ 0U, // FSETPM >+ 0U, // FSINCOS >+ 0U, // FSTENVm >+ 0U, // FXAM >+ 0U, // FXRSTOR >+ 0U, // FXRSTOR64 >+ 0U, // FXSAVE >+ 0U, // FXSAVE64 >+ 0U, // FXTRACT >+ 0U, // FYL2X >+ 0U, // FYL2XP1 >+ 0U, // FsANDNPDrm >+ 0U, // FsANDNPDrr >+ 0U, // FsANDNPSrm >+ 0U, // FsANDNPSrr >+ 0U, // FsANDPDrm >+ 0U, // FsANDPDrr >+ 0U, // FsANDPSrm >+ 0U, // FsANDPSrr >+ 0U, // FsFLD0SD >+ 0U, // FsFLD0SS >+ 0U, // FsMOVAPDrm >+ 0U, // FsMOVAPSrm >+ 0U, // FsORPDrm >+ 0U, // FsORPDrr >+ 0U, // FsORPSrm >+ 0U, // FsORPSrr >+ 0U, // FsVMOVAPDrm >+ 0U, // FsVMOVAPSrm >+ 0U, // FsXORPDrm >+ 0U, // FsXORPDrr >+ 0U, // FsXORPSrm >+ 0U, // FsXORPSrr >+ 0U, // GETSEC >+ 0U, // HADDPDrm >+ 0U, // HADDPDrr >+ 0U, // HADDPSrm >+ 0U, // HADDPSrr >+ 0U, // HLT >+ 0U, // HSUBPDrm >+ 0U, // HSUBPDrr >+ 0U, // HSUBPSrm >+ 0U, // HSUBPSrr >+ 0U, // IDIV16m >+ 0U, // IDIV16r >+ 0U, // IDIV32m >+ 0U, // IDIV32r >+ 0U, // IDIV64m >+ 0U, // IDIV64r >+ 0U, // IDIV8m >+ 0U, // IDIV8r >+ 0U, // ILD_F16m >+ 0U, // ILD_F32m >+ 0U, // ILD_F64m >+ 0U, // ILD_Fp16m32 >+ 0U, // ILD_Fp16m64 >+ 0U, // ILD_Fp16m80 >+ 0U, // ILD_Fp32m32 >+ 0U, // ILD_Fp32m64 >+ 0U, // ILD_Fp32m80 >+ 0U, // ILD_Fp64m32 >+ 0U, // ILD_Fp64m64 >+ 0U, // ILD_Fp64m80 >+ 0U, // IMUL16m >+ 0U, // IMUL16r >+ 0U, // IMUL16rm >+ 0U, // IMUL16rmi >+ 0U, // IMUL16rmi8 >+ 0U, // IMUL16rr >+ 8U, // IMUL16rri >+ 8U, // IMUL16rri8 >+ 0U, // IMUL32m >+ 0U, // IMUL32r >+ 0U, // IMUL32rm >+ 0U, // IMUL32rmi >+ 0U, // IMUL32rmi8 >+ 0U, // IMUL32rr >+ 8U, // IMUL32rri >+ 8U, // IMUL32rri8 >+ 0U, // IMUL64m >+ 0U, // IMUL64r >+ 0U, // IMUL64rm >+ 0U, // IMUL64rmi32 >+ 0U, // IMUL64rmi8 >+ 0U, // IMUL64rr >+ 8U, // IMUL64rri32 >+ 8U, // IMUL64rri8 >+ 0U, // IMUL8m >+ 0U, // IMUL8r >+ 0U, // IN16ri >+ 0U, // IN16rr >+ 0U, // IN32ri >+ 0U, // IN32rr >+ 0U, // IN8ri >+ 0U, // IN8rr >+ 0U, // INC16m >+ 0U, // INC16r >+ 0U, // INC32_16r >+ 0U, // INC32_32r >+ 0U, // INC32m >+ 0U, // INC32r >+ 0U, // INC64_16m >+ 0U, // INC64_16r >+ 0U, // INC64_32m >+ 0U, // INC64_32r >+ 0U, // INC64m >+ 0U, // INC64r >+ 0U, // INC8m >+ 0U, // INC8r >+ 0U, // INSB >+ 32U, // INSERTPSrm >+ 40U, // INSERTPSrr >+ 0U, // INSERTQ >+ 296U, // INSERTQI >+ 0U, // INSL >+ 0U, // INSW >+ 0U, // INT >+ 0U, // INT1 >+ 0U, // INT3 >+ 0U, // INTO >+ 0U, // INVD >+ 0U, // INVEPT32 >+ 0U, // INVEPT64 >+ 0U, // INVLPG >+ 0U, // INVLPGA32 >+ 0U, // INVLPGA64 >+ 0U, // INVPCID32 >+ 0U, // INVPCID64 >+ 0U, // INVVPID32 >+ 0U, // INVVPID64 >+ 0U, // IRET16 >+ 0U, // IRET32 >+ 0U, // IRET64 >+ 0U, // ISTT_FP16m >+ 0U, // ISTT_FP32m >+ 0U, // ISTT_FP64m >+ 0U, // ISTT_Fp16m32 >+ 0U, // ISTT_Fp16m64 >+ 0U, // ISTT_Fp16m80 >+ 0U, // ISTT_Fp32m32 >+ 0U, // ISTT_Fp32m64 >+ 0U, // ISTT_Fp32m80 >+ 0U, // ISTT_Fp64m32 >+ 0U, // ISTT_Fp64m64 >+ 0U, // ISTT_Fp64m80 >+ 0U, // IST_F16m >+ 0U, // IST_F32m >+ 0U, // IST_FP16m >+ 0U, // IST_FP32m >+ 0U, // IST_FP64m >+ 0U, // IST_Fp16m32 >+ 0U, // IST_Fp16m64 >+ 0U, // IST_Fp16m80 >+ 0U, // IST_Fp32m32 >+ 0U, // IST_Fp32m64 >+ 0U, // IST_Fp32m80 >+ 0U, // IST_Fp64m32 >+ 0U, // IST_Fp64m64 >+ 0U, // IST_Fp64m80 >+ 0U, // Int_CMPSDrm >+ 0U, // Int_CMPSDrr >+ 0U, // Int_CMPSSrm >+ 0U, // Int_CMPSSrr >+ 0U, // Int_COMISDrm >+ 0U, // Int_COMISDrr >+ 0U, // Int_COMISSrm >+ 0U, // Int_COMISSrr >+ 0U, // Int_CVTSD2SSrm >+ 0U, // Int_CVTSD2SSrr >+ 0U, // Int_CVTSI2SD64rm >+ 0U, // Int_CVTSI2SD64rr >+ 0U, // Int_CVTSI2SDrm >+ 0U, // Int_CVTSI2SDrr >+ 0U, // Int_CVTSI2SS64rm >+ 0U, // Int_CVTSI2SS64rr >+ 0U, // Int_CVTSI2SSrm >+ 0U, // Int_CVTSI2SSrr >+ 0U, // Int_CVTSS2SDrm >+ 0U, // Int_CVTSS2SDrr >+ 0U, // Int_CVTTSD2SI64rm >+ 0U, // Int_CVTTSD2SI64rr >+ 0U, // Int_CVTTSD2SIrm >+ 0U, // Int_CVTTSD2SIrr >+ 0U, // Int_CVTTSS2SI64rm >+ 0U, // Int_CVTTSS2SI64rr >+ 0U, // Int_CVTTSS2SIrm >+ 0U, // Int_CVTTSS2SIrr >+ 0U, // Int_MemBarrier >+ 0U, // Int_UCOMISDrm >+ 0U, // Int_UCOMISDrr >+ 0U, // Int_UCOMISSrm >+ 0U, // Int_UCOMISSrr >+ 48U, // Int_VCMPSDrm >+ 8U, // Int_VCMPSDrr >+ 56U, // Int_VCMPSSrm >+ 8U, // Int_VCMPSSrr >+ 0U, // Int_VCOMISDZrm >+ 0U, // Int_VCOMISDZrr >+ 0U, // Int_VCOMISDrm >+ 0U, // Int_VCOMISDrr >+ 0U, // Int_VCOMISSZrm >+ 0U, // Int_VCOMISSZrr >+ 0U, // Int_VCOMISSrm >+ 0U, // Int_VCOMISSrr >+ 48U, // Int_VCVTSD2SSrm >+ 8U, // Int_VCVTSD2SSrr >+ 24U, // Int_VCVTSI2SD64Zrm >+ 8U, // Int_VCVTSI2SD64Zrr >+ 24U, // Int_VCVTSI2SD64rm >+ 8U, // Int_VCVTSI2SD64rr >+ 16U, // Int_VCVTSI2SDZrm >+ 8U, // Int_VCVTSI2SDZrr >+ 16U, // Int_VCVTSI2SDrm >+ 8U, // Int_VCVTSI2SDrr >+ 24U, // Int_VCVTSI2SS64Zrm >+ 8U, // Int_VCVTSI2SS64Zrr >+ 24U, // Int_VCVTSI2SS64rm >+ 8U, // Int_VCVTSI2SS64rr >+ 16U, // Int_VCVTSI2SSZrm >+ 8U, // Int_VCVTSI2SSZrr >+ 16U, // Int_VCVTSI2SSrm >+ 8U, // Int_VCVTSI2SSrr >+ 56U, // Int_VCVTSS2SDrm >+ 8U, // Int_VCVTSS2SDrr >+ 0U, // Int_VCVTTSD2SI64Zrm >+ 0U, // Int_VCVTTSD2SI64Zrr >+ 0U, // Int_VCVTTSD2SI64rm >+ 0U, // Int_VCVTTSD2SI64rr >+ 0U, // Int_VCVTTSD2SIZrm >+ 0U, // Int_VCVTTSD2SIZrr >+ 0U, // Int_VCVTTSD2SIrm >+ 0U, // Int_VCVTTSD2SIrr >+ 0U, // Int_VCVTTSD2USI64Zrm >+ 0U, // Int_VCVTTSD2USI64Zrr >+ 0U, // Int_VCVTTSD2USIZrm >+ 0U, // Int_VCVTTSD2USIZrr >+ 0U, // Int_VCVTTSS2SI64Zrm >+ 0U, // Int_VCVTTSS2SI64Zrr >+ 0U, // Int_VCVTTSS2SI64rm >+ 0U, // Int_VCVTTSS2SI64rr >+ 0U, // Int_VCVTTSS2SIZrm >+ 0U, // Int_VCVTTSS2SIZrr >+ 0U, // Int_VCVTTSS2SIrm >+ 0U, // Int_VCVTTSS2SIrr >+ 0U, // Int_VCVTTSS2USI64Zrm >+ 0U, // Int_VCVTTSS2USI64Zrr >+ 0U, // Int_VCVTTSS2USIZrm >+ 0U, // Int_VCVTTSS2USIZrr >+ 24U, // Int_VCVTUSI2SD64Zrm >+ 8U, // Int_VCVTUSI2SD64Zrr >+ 16U, // Int_VCVTUSI2SDZrm >+ 8U, // Int_VCVTUSI2SDZrr >+ 24U, // Int_VCVTUSI2SS64Zrm >+ 8U, // Int_VCVTUSI2SS64Zrr >+ 16U, // Int_VCVTUSI2SSZrm >+ 8U, // Int_VCVTUSI2SSZrr >+ 0U, // Int_VUCOMISDZrm >+ 0U, // Int_VUCOMISDZrr >+ 0U, // Int_VUCOMISDrm >+ 0U, // Int_VUCOMISDrr >+ 0U, // Int_VUCOMISSZrm >+ 0U, // Int_VUCOMISSZrr >+ 0U, // Int_VUCOMISSrm >+ 0U, // Int_VUCOMISSrr >+ 0U, // JAE_1 >+ 0U, // JAE_2 >+ 0U, // JAE_4 >+ 0U, // JA_1 >+ 0U, // JA_2 >+ 0U, // JA_4 >+ 0U, // JBE_1 >+ 0U, // JBE_2 >+ 0U, // JBE_4 >+ 0U, // JB_1 >+ 0U, // JB_2 >+ 0U, // JB_4 >+ 0U, // JCXZ >+ 0U, // JECXZ_32 >+ 0U, // JECXZ_64 >+ 0U, // JE_1 >+ 0U, // JE_2 >+ 0U, // JE_4 >+ 0U, // JGE_1 >+ 0U, // JGE_2 >+ 0U, // JGE_4 >+ 0U, // JG_1 >+ 0U, // JG_2 >+ 0U, // JG_4 >+ 0U, // JLE_1 >+ 0U, // JLE_2 >+ 0U, // JLE_4 >+ 0U, // JL_1 >+ 0U, // JL_2 >+ 0U, // JL_4 >+ 0U, // JMP16m >+ 0U, // JMP16r >+ 0U, // JMP32m >+ 0U, // JMP32r >+ 0U, // JMP64m >+ 0U, // JMP64r >+ 0U, // JMP_1 >+ 0U, // JMP_2 >+ 0U, // JMP_4 >+ 0U, // JNE_1 >+ 0U, // JNE_2 >+ 0U, // JNE_4 >+ 0U, // JNO_1 >+ 0U, // JNO_2 >+ 0U, // JNO_4 >+ 0U, // JNP_1 >+ 0U, // JNP_2 >+ 0U, // JNP_4 >+ 0U, // JNS_1 >+ 0U, // JNS_2 >+ 0U, // JNS_4 >+ 0U, // JO_1 >+ 0U, // JO_2 >+ 0U, // JO_4 >+ 0U, // JP_1 >+ 0U, // JP_2 >+ 0U, // JP_4 >+ 0U, // JRCXZ >+ 0U, // JS_1 >+ 0U, // JS_2 >+ 0U, // JS_4 >+ 8U, // KANDBrr >+ 8U, // KANDDrr >+ 8U, // KANDNBrr >+ 8U, // KANDNDrr >+ 8U, // KANDNQrr >+ 8U, // KANDNWrr >+ 8U, // KANDQrr >+ 8U, // KANDWrr >+ 0U, // KMOVBkk >+ 0U, // KMOVBkm >+ 0U, // KMOVBkr >+ 0U, // KMOVBmk >+ 0U, // KMOVBrk >+ 0U, // KMOVDkk >+ 0U, // KMOVDkm >+ 0U, // KMOVDkr >+ 0U, // KMOVDmk >+ 0U, // KMOVDrk >+ 0U, // KMOVQkk >+ 0U, // KMOVQkm >+ 0U, // KMOVQkr >+ 0U, // KMOVQmk >+ 0U, // KMOVQrk >+ 0U, // KMOVWkk >+ 0U, // KMOVWkm >+ 0U, // KMOVWkr >+ 0U, // KMOVWmk >+ 0U, // KMOVWrk >+ 0U, // KNOTBrr >+ 0U, // KNOTDrr >+ 0U, // KNOTQrr >+ 0U, // KNOTWrr >+ 8U, // KORBrr >+ 8U, // KORDrr >+ 8U, // KORQrr >+ 0U, // KORTESTWrr >+ 8U, // KORWrr >+ 0U, // KSET0B >+ 0U, // KSET0W >+ 0U, // KSET1B >+ 0U, // KSET1W >+ 8U, // KSHIFTLWri >+ 8U, // KSHIFTRWri >+ 8U, // KUNPCKBWrr >+ 8U, // KXNORBrr >+ 8U, // KXNORDrr >+ 8U, // KXNORQrr >+ 8U, // KXNORWrr >+ 8U, // KXORBrr >+ 8U, // KXORDrr >+ 8U, // KXORQrr >+ 8U, // KXORWrr >+ 0U, // LAHF >+ 0U, // LAR16rm >+ 0U, // LAR16rr >+ 0U, // LAR32rm >+ 0U, // LAR32rr >+ 0U, // LAR64rm >+ 0U, // LAR64rr >+ 0U, // LCMPXCHG16 >+ 0U, // LCMPXCHG16B >+ 0U, // LCMPXCHG32 >+ 0U, // LCMPXCHG64 >+ 0U, // LCMPXCHG8 >+ 0U, // LCMPXCHG8B >+ 0U, // LDDQUrm >+ 0U, // LDMXCSR >+ 0U, // LDS16rm >+ 0U, // LDS32rm >+ 0U, // LD_F0 >+ 0U, // LD_F1 >+ 0U, // LD_F32m >+ 0U, // LD_F64m >+ 0U, // LD_F80m >+ 0U, // LD_Fp032 >+ 0U, // LD_Fp064 >+ 0U, // LD_Fp080 >+ 0U, // LD_Fp132 >+ 0U, // LD_Fp164 >+ 0U, // LD_Fp180 >+ 0U, // LD_Fp32m >+ 0U, // LD_Fp32m64 >+ 0U, // LD_Fp32m80 >+ 0U, // LD_Fp64m >+ 0U, // LD_Fp64m80 >+ 0U, // LD_Fp80m >+ 0U, // LD_Frr >+ 0U, // LEA16r >+ 0U, // LEA32r >+ 0U, // LEA64_32r >+ 0U, // LEA64r >+ 0U, // LEAVE >+ 0U, // LEAVE64 >+ 0U, // LES16rm >+ 0U, // LES32rm >+ 0U, // LFENCE >+ 0U, // LFS16rm >+ 0U, // LFS32rm >+ 0U, // LFS64rm >+ 0U, // LGDT16m >+ 0U, // LGDT32m >+ 0U, // LGDT64m >+ 0U, // LGS16rm >+ 0U, // LGS32rm >+ 0U, // LGS64rm >+ 0U, // LIDT16m >+ 0U, // LIDT32m >+ 0U, // LIDT64m >+ 0U, // LLDT16m >+ 0U, // LLDT16r >+ 0U, // LMSW16m >+ 0U, // LMSW16r >+ 0U, // LOCK_ADD16mi >+ 0U, // LOCK_ADD16mi8 >+ 0U, // LOCK_ADD16mr >+ 0U, // LOCK_ADD32mi >+ 0U, // LOCK_ADD32mi8 >+ 0U, // LOCK_ADD32mr >+ 0U, // LOCK_ADD64mi32 >+ 0U, // LOCK_ADD64mi8 >+ 0U, // LOCK_ADD64mr >+ 0U, // LOCK_ADD8mi >+ 0U, // LOCK_ADD8mr >+ 0U, // LOCK_AND16mi >+ 0U, // LOCK_AND16mi8 >+ 0U, // LOCK_AND16mr >+ 0U, // LOCK_AND32mi >+ 0U, // LOCK_AND32mi8 >+ 0U, // LOCK_AND32mr >+ 0U, // LOCK_AND64mi32 >+ 0U, // LOCK_AND64mi8 >+ 0U, // LOCK_AND64mr >+ 0U, // LOCK_AND8mi >+ 0U, // LOCK_AND8mr >+ 0U, // LOCK_DEC16m >+ 0U, // LOCK_DEC32m >+ 0U, // LOCK_DEC64m >+ 0U, // LOCK_DEC8m >+ 0U, // LOCK_INC16m >+ 0U, // LOCK_INC32m >+ 0U, // LOCK_INC64m >+ 0U, // LOCK_INC8m >+ 0U, // LOCK_OR16mi >+ 0U, // LOCK_OR16mi8 >+ 0U, // LOCK_OR16mr >+ 0U, // LOCK_OR32mi >+ 0U, // LOCK_OR32mi8 >+ 0U, // LOCK_OR32mr >+ 0U, // LOCK_OR64mi32 >+ 0U, // LOCK_OR64mi8 >+ 0U, // LOCK_OR64mr >+ 0U, // LOCK_OR8mi >+ 0U, // LOCK_OR8mr >+ 0U, // LOCK_PREFIX >+ 0U, // LOCK_SUB16mi >+ 0U, // LOCK_SUB16mi8 >+ 0U, // LOCK_SUB16mr >+ 0U, // LOCK_SUB32mi >+ 0U, // LOCK_SUB32mi8 >+ 0U, // LOCK_SUB32mr >+ 0U, // LOCK_SUB64mi32 >+ 0U, // LOCK_SUB64mi8 >+ 0U, // LOCK_SUB64mr >+ 0U, // LOCK_SUB8mi >+ 0U, // LOCK_SUB8mr >+ 0U, // LOCK_XOR16mi >+ 0U, // LOCK_XOR16mi8 >+ 0U, // LOCK_XOR16mr >+ 0U, // LOCK_XOR32mi >+ 0U, // LOCK_XOR32mi8 >+ 0U, // LOCK_XOR32mr >+ 0U, // LOCK_XOR64mi32 >+ 0U, // LOCK_XOR64mi8 >+ 0U, // LOCK_XOR64mr >+ 0U, // LOCK_XOR8mi >+ 0U, // LOCK_XOR8mr >+ 0U, // LODSB >+ 0U, // LODSL >+ 0U, // LODSQ >+ 0U, // LODSW >+ 0U, // LOOP >+ 0U, // LOOPE >+ 0U, // LOOPNE >+ 0U, // LRETIL >+ 0U, // LRETIQ >+ 0U, // LRETIW >+ 0U, // LRETL >+ 0U, // LRETQ >+ 0U, // LRETW >+ 0U, // LSL16rm >+ 0U, // LSL16rr >+ 0U, // LSL32rm >+ 0U, // LSL32rr >+ 0U, // LSL64rm >+ 0U, // LSL64rr >+ 0U, // LSS16rm >+ 0U, // LSS32rm >+ 0U, // LSS64rm >+ 0U, // LTRm >+ 0U, // LTRr >+ 0U, // LXADD16 >+ 0U, // LXADD32 >+ 0U, // LXADD64 >+ 0U, // LXADD8 >+ 0U, // LZCNT16rm >+ 0U, // LZCNT16rr >+ 0U, // LZCNT32rm >+ 0U, // LZCNT32rr >+ 0U, // LZCNT64rm >+ 0U, // LZCNT64rr >+ 0U, // MASKMOVDQU >+ 0U, // MASKMOVDQU64 >+ 0U, // MAXCPDrm >+ 0U, // MAXCPDrr >+ 0U, // MAXCPSrm >+ 0U, // MAXCPSrr >+ 0U, // MAXCSDrm >+ 0U, // MAXCSDrr >+ 0U, // MAXCSSrm >+ 0U, // MAXCSSrr >+ 0U, // MAXPDrm >+ 0U, // MAXPDrr >+ 0U, // MAXPSrm >+ 0U, // MAXPSrr >+ 0U, // MAXSDrm >+ 0U, // MAXSDrm_Int >+ 0U, // MAXSDrr >+ 0U, // MAXSDrr_Int >+ 0U, // MAXSSrm >+ 0U, // MAXSSrm_Int >+ 0U, // MAXSSrr >+ 0U, // MAXSSrr_Int >+ 0U, // MFENCE >+ 0U, // MINCPDrm >+ 0U, // MINCPDrr >+ 0U, // MINCPSrm >+ 0U, // MINCPSrr >+ 0U, // MINCSDrm >+ 0U, // MINCSDrr >+ 0U, // MINCSSrm >+ 0U, // MINCSSrr >+ 0U, // MINPDrm >+ 0U, // MINPDrr >+ 0U, // MINPSrm >+ 0U, // MINPSrr >+ 0U, // MINSDrm >+ 0U, // MINSDrm_Int >+ 0U, // MINSDrr >+ 0U, // MINSDrr_Int >+ 0U, // MINSSrm >+ 0U, // MINSSrm_Int >+ 0U, // MINSSrr >+ 0U, // MINSSrr_Int >+ 0U, // MMX_CVTPD2PIirm >+ 0U, // MMX_CVTPD2PIirr >+ 0U, // MMX_CVTPI2PDirm >+ 0U, // MMX_CVTPI2PDirr >+ 0U, // MMX_CVTPI2PSirm >+ 0U, // MMX_CVTPI2PSirr >+ 0U, // MMX_CVTPS2PIirm >+ 0U, // MMX_CVTPS2PIirr >+ 0U, // MMX_CVTTPD2PIirm >+ 0U, // MMX_CVTTPD2PIirr >+ 0U, // MMX_CVTTPS2PIirm >+ 0U, // MMX_CVTTPS2PIirr >+ 0U, // MMX_EMMS >+ 0U, // MMX_MASKMOVQ >+ 0U, // MMX_MASKMOVQ64 >+ 0U, // MMX_MOVD64from64rr >+ 0U, // MMX_MOVD64grr >+ 0U, // MMX_MOVD64mr >+ 0U, // MMX_MOVD64rm >+ 0U, // MMX_MOVD64rr >+ 0U, // MMX_MOVD64to64rr >+ 0U, // MMX_MOVDQ2Qrr >+ 0U, // MMX_MOVFR642Qrr >+ 0U, // MMX_MOVNTQmr >+ 0U, // MMX_MOVQ2DQrr >+ 0U, // MMX_MOVQ2FR64rr >+ 0U, // MMX_MOVQ64mr >+ 0U, // MMX_MOVQ64rm >+ 0U, // MMX_MOVQ64rr >+ 0U, // MMX_MOVQ64rr_REV >+ 0U, // MMX_PABSBrm64 >+ 0U, // MMX_PABSBrr64 >+ 0U, // MMX_PABSDrm64 >+ 0U, // MMX_PABSDrr64 >+ 0U, // MMX_PABSWrm64 >+ 0U, // MMX_PABSWrr64 >+ 0U, // MMX_PACKSSDWirm >+ 0U, // MMX_PACKSSDWirr >+ 0U, // MMX_PACKSSWBirm >+ 0U, // MMX_PACKSSWBirr >+ 0U, // MMX_PACKUSWBirm >+ 0U, // MMX_PACKUSWBirr >+ 0U, // MMX_PADDBirm >+ 0U, // MMX_PADDBirr >+ 0U, // MMX_PADDDirm >+ 0U, // MMX_PADDDirr >+ 0U, // MMX_PADDQirm >+ 0U, // MMX_PADDQirr >+ 0U, // MMX_PADDSBirm >+ 0U, // MMX_PADDSBirr >+ 0U, // MMX_PADDSWirm >+ 0U, // MMX_PADDSWirr >+ 0U, // MMX_PADDUSBirm >+ 0U, // MMX_PADDUSBirr >+ 0U, // MMX_PADDUSWirm >+ 0U, // MMX_PADDUSWirr >+ 0U, // MMX_PADDWirm >+ 0U, // MMX_PADDWirr >+ 32U, // MMX_PALIGNR64irm >+ 40U, // MMX_PALIGNR64irr >+ 0U, // MMX_PANDNirm >+ 0U, // MMX_PANDNirr >+ 0U, // MMX_PANDirm >+ 0U, // MMX_PANDirr >+ 0U, // MMX_PAVGBirm >+ 0U, // MMX_PAVGBirr >+ 0U, // MMX_PAVGWirm >+ 0U, // MMX_PAVGWirr >+ 0U, // MMX_PCMPEQBirm >+ 0U, // MMX_PCMPEQBirr >+ 0U, // MMX_PCMPEQDirm >+ 0U, // MMX_PCMPEQDirr >+ 0U, // MMX_PCMPEQWirm >+ 0U, // MMX_PCMPEQWirr >+ 0U, // MMX_PCMPGTBirm >+ 0U, // MMX_PCMPGTBirr >+ 0U, // MMX_PCMPGTDirm >+ 0U, // MMX_PCMPGTDirr >+ 0U, // MMX_PCMPGTWirm >+ 0U, // MMX_PCMPGTWirr >+ 8U, // MMX_PEXTRWirri >+ 0U, // MMX_PHADDSWrm64 >+ 0U, // MMX_PHADDSWrr64 >+ 0U, // MMX_PHADDWrm64 >+ 0U, // MMX_PHADDWrr64 >+ 0U, // MMX_PHADDrm64 >+ 0U, // MMX_PHADDrr64 >+ 0U, // MMX_PHSUBDrm64 >+ 0U, // MMX_PHSUBDrr64 >+ 0U, // MMX_PHSUBSWrm64 >+ 0U, // MMX_PHSUBSWrr64 >+ 0U, // MMX_PHSUBWrm64 >+ 0U, // MMX_PHSUBWrr64 >+ 32U, // MMX_PINSRWirmi >+ 40U, // MMX_PINSRWirri >+ 0U, // MMX_PMADDUBSWrm64 >+ 0U, // MMX_PMADDUBSWrr64 >+ 0U, // MMX_PMADDWDirm >+ 0U, // MMX_PMADDWDirr >+ 0U, // MMX_PMAXSWirm >+ 0U, // MMX_PMAXSWirr >+ 0U, // MMX_PMAXUBirm >+ 0U, // MMX_PMAXUBirr >+ 0U, // MMX_PMINSWirm >+ 0U, // MMX_PMINSWirr >+ 0U, // MMX_PMINUBirm >+ 0U, // MMX_PMINUBirr >+ 0U, // MMX_PMOVMSKBrr >+ 0U, // MMX_PMULHRSWrm64 >+ 0U, // MMX_PMULHRSWrr64 >+ 0U, // MMX_PMULHUWirm >+ 0U, // MMX_PMULHUWirr >+ 0U, // MMX_PMULHWirm >+ 0U, // MMX_PMULHWirr >+ 0U, // MMX_PMULLWirm >+ 0U, // MMX_PMULLWirr >+ 0U, // MMX_PMULUDQirm >+ 0U, // MMX_PMULUDQirr >+ 0U, // MMX_PORirm >+ 0U, // MMX_PORirr >+ 0U, // MMX_PSADBWirm >+ 0U, // MMX_PSADBWirr >+ 0U, // MMX_PSHUFBrm64 >+ 0U, // MMX_PSHUFBrr64 >+ 0U, // MMX_PSHUFWmi >+ 8U, // MMX_PSHUFWri >+ 0U, // MMX_PSIGNBrm64 >+ 0U, // MMX_PSIGNBrr64 >+ 0U, // MMX_PSIGNDrm64 >+ 0U, // MMX_PSIGNDrr64 >+ 0U, // MMX_PSIGNWrm64 >+ 0U, // MMX_PSIGNWrr64 >+ 0U, // MMX_PSLLDri >+ 0U, // MMX_PSLLDrm >+ 0U, // MMX_PSLLDrr >+ 0U, // MMX_PSLLQri >+ 0U, // MMX_PSLLQrm >+ 0U, // MMX_PSLLQrr >+ 0U, // MMX_PSLLWri >+ 0U, // MMX_PSLLWrm >+ 0U, // MMX_PSLLWrr >+ 0U, // MMX_PSRADri >+ 0U, // MMX_PSRADrm >+ 0U, // MMX_PSRADrr >+ 0U, // MMX_PSRAWri >+ 0U, // MMX_PSRAWrm >+ 0U, // MMX_PSRAWrr >+ 0U, // MMX_PSRLDri >+ 0U, // MMX_PSRLDrm >+ 0U, // MMX_PSRLDrr >+ 0U, // MMX_PSRLQri >+ 0U, // MMX_PSRLQrm >+ 0U, // MMX_PSRLQrr >+ 0U, // MMX_PSRLWri >+ 0U, // MMX_PSRLWrm >+ 0U, // MMX_PSRLWrr >+ 0U, // MMX_PSUBBirm >+ 0U, // MMX_PSUBBirr >+ 0U, // MMX_PSUBDirm >+ 0U, // MMX_PSUBDirr >+ 0U, // MMX_PSUBQirm >+ 0U, // MMX_PSUBQirr >+ 0U, // MMX_PSUBSBirm >+ 0U, // MMX_PSUBSBirr >+ 0U, // MMX_PSUBSWirm >+ 0U, // MMX_PSUBSWirr >+ 0U, // MMX_PSUBUSBirm >+ 0U, // MMX_PSUBUSBirr >+ 0U, // MMX_PSUBUSWirm >+ 0U, // MMX_PSUBUSWirr >+ 0U, // MMX_PSUBWirm >+ 0U, // MMX_PSUBWirr >+ 0U, // MMX_PUNPCKHBWirm >+ 0U, // MMX_PUNPCKHBWirr >+ 0U, // MMX_PUNPCKHDQirm >+ 0U, // MMX_PUNPCKHDQirr >+ 0U, // MMX_PUNPCKHWDirm >+ 0U, // MMX_PUNPCKHWDirr >+ 0U, // MMX_PUNPCKLBWirm >+ 0U, // MMX_PUNPCKLBWirr >+ 0U, // MMX_PUNPCKLDQirm >+ 0U, // MMX_PUNPCKLDQirr >+ 0U, // MMX_PUNPCKLWDirm >+ 0U, // MMX_PUNPCKLWDirr >+ 0U, // MMX_PXORirm >+ 0U, // MMX_PXORirr >+ 0U, // MONITOR >+ 0U, // MONITORrrr >+ 0U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 0U, // MOV16ao16 >+ 0U, // MOV16ao16_16 >+ 0U, // MOV16mi >+ 0U, // MOV16mr >+ 0U, // MOV16ms >+ 0U, // MOV16o16a >+ 0U, // MOV16o16a_16 >+ 0U, // MOV16ri >+ 0U, // MOV16ri_alt >+ 0U, // MOV16rm >+ 0U, // MOV16rr >+ 0U, // MOV16rr_REV >+ 0U, // MOV16rs >+ 0U, // MOV16sm >+ 0U, // MOV16sr >+ 0U, // MOV32ao32 >+ 0U, // MOV32ao32_16 >+ 0U, // MOV32cr >+ 0U, // MOV32dr >+ 0U, // MOV32mi >+ 0U, // MOV32mr >+ 0U, // MOV32ms >+ 0U, // MOV32o32a >+ 0U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 0U, // MOV32rc >+ 0U, // MOV32rd >+ 0U, // MOV32ri >+ 0U, // MOV32ri64 >+ 0U, // MOV32ri_alt >+ 0U, // MOV32rm >+ 0U, // MOV32rr >+ 0U, // MOV32rr_REV >+ 0U, // MOV32rs >+ 0U, // MOV32sm >+ 0U, // MOV32sr >+ 0U, // MOV64ao16 >+ 0U, // MOV64ao32 >+ 0U, // MOV64ao64 >+ 0U, // MOV64ao8 >+ 0U, // MOV64cr >+ 0U, // MOV64dr >+ 0U, // MOV64mi32 >+ 0U, // MOV64mr >+ 0U, // MOV64ms >+ 0U, // MOV64o16a >+ 0U, // MOV64o32a >+ 0U, // MOV64o64a >+ 0U, // MOV64o8a >+ 0U, // MOV64rc >+ 0U, // MOV64rd >+ 0U, // MOV64ri >+ 0U, // MOV64ri32 >+ 0U, // MOV64rm >+ 0U, // MOV64rr >+ 0U, // MOV64rr_REV >+ 0U, // MOV64rs >+ 0U, // MOV64sm >+ 0U, // MOV64sr >+ 0U, // MOV64toPQIrr >+ 0U, // MOV64toSDrm >+ 0U, // MOV64toSDrr >+ 0U, // MOV8ao8 >+ 0U, // MOV8ao8_16 >+ 0U, // MOV8mi >+ 0U, // MOV8mr >+ 1U, // MOV8mr_NOREX >+ 0U, // MOV8o8a >+ 0U, // MOV8o8a_16 >+ 0U, // MOV8ri >+ 0U, // MOV8ri_alt >+ 0U, // MOV8rm >+ 1U, // MOV8rm_NOREX >+ 0U, // MOV8rr >+ 1U, // MOV8rr_NOREX >+ 0U, // MOV8rr_REV >+ 0U, // MOVAPDmr >+ 0U, // MOVAPDrm >+ 0U, // MOVAPDrr >+ 0U, // MOVAPDrr_REV >+ 0U, // MOVAPSmr >+ 0U, // MOVAPSrm >+ 0U, // MOVAPSrr >+ 0U, // MOVAPSrr_REV >+ 0U, // MOVBE16mr >+ 0U, // MOVBE16rm >+ 0U, // MOVBE32mr >+ 0U, // MOVBE32rm >+ 0U, // MOVBE64mr >+ 0U, // MOVBE64rm >+ 0U, // MOVDDUPrm >+ 0U, // MOVDDUPrr >+ 0U, // MOVDI2PDIrm >+ 0U, // MOVDI2PDIrr >+ 0U, // MOVDI2SSrm >+ 0U, // MOVDI2SSrr >+ 0U, // MOVDQAmr >+ 0U, // MOVDQArm >+ 0U, // MOVDQArr >+ 0U, // MOVDQArr_REV >+ 0U, // MOVDQUmr >+ 0U, // MOVDQUrm >+ 0U, // MOVDQUrr >+ 0U, // MOVDQUrr_REV >+ 0U, // MOVHLPSrr >+ 0U, // MOVHPDmr >+ 0U, // MOVHPDrm >+ 0U, // MOVHPSmr >+ 0U, // MOVHPSrm >+ 0U, // MOVLHPSrr >+ 0U, // MOVLPDmr >+ 0U, // MOVLPDrm >+ 0U, // MOVLPSmr >+ 0U, // MOVLPSrm >+ 0U, // MOVMSKPDrr >+ 0U, // MOVMSKPSrr >+ 0U, // MOVNTDQArm >+ 0U, // MOVNTDQmr >+ 0U, // MOVNTI_64mr >+ 0U, // MOVNTImr >+ 0U, // MOVNTPDmr >+ 0U, // MOVNTPSmr >+ 0U, // MOVNTSD >+ 0U, // MOVNTSS >+ 0U, // MOVPC32r >+ 0U, // MOVPDI2DImr >+ 0U, // MOVPDI2DIrr >+ 0U, // MOVPQI2QImr >+ 0U, // MOVPQI2QIrr >+ 0U, // MOVPQIto64rr >+ 0U, // MOVQI2PQIrm >+ 0U, // MOVSB >+ 0U, // MOVSDmr >+ 0U, // MOVSDrm >+ 0U, // MOVSDrr >+ 0U, // MOVSDrr_REV >+ 0U, // MOVSDto64mr >+ 0U, // MOVSDto64rr >+ 0U, // MOVSHDUPrm >+ 0U, // MOVSHDUPrr >+ 0U, // MOVSL >+ 0U, // MOVSLDUPrm >+ 0U, // MOVSLDUPrr >+ 0U, // MOVSQ >+ 0U, // MOVSS2DImr >+ 0U, // MOVSS2DIrr >+ 0U, // MOVSSmr >+ 0U, // MOVSSrm >+ 0U, // MOVSSrr >+ 0U, // MOVSSrr_REV >+ 0U, // MOVSW >+ 0U, // MOVSX16rm8 >+ 0U, // MOVSX16rr8 >+ 0U, // MOVSX32rm16 >+ 0U, // MOVSX32rm8 >+ 0U, // MOVSX32rr16 >+ 0U, // MOVSX32rr8 >+ 0U, // MOVSX64_NOREXrr32 >+ 0U, // MOVSX64rm16 >+ 0U, // MOVSX64rm32 >+ 0U, // MOVSX64rm8 >+ 0U, // MOVSX64rr16 >+ 0U, // MOVSX64rr32 >+ 0U, // MOVSX64rr8 >+ 0U, // MOVUPDmr >+ 0U, // MOVUPDrm >+ 0U, // MOVUPDrr >+ 0U, // MOVUPDrr_REV >+ 0U, // MOVUPSmr >+ 0U, // MOVUPSrm >+ 0U, // MOVUPSrr >+ 0U, // MOVUPSrr_REV >+ 0U, // MOVZPQILo2PQIrm >+ 0U, // MOVZPQILo2PQIrr >+ 0U, // MOVZQI2PQIrm >+ 0U, // MOVZQI2PQIrr >+ 0U, // MOVZX16rm8 >+ 0U, // MOVZX16rr8 >+ 0U, // MOVZX32_NOREXrm8 >+ 0U, // MOVZX32_NOREXrr8 >+ 0U, // MOVZX32rm16 >+ 0U, // MOVZX32rm8 >+ 0U, // MOVZX32rr16 >+ 0U, // MOVZX32rr8 >+ 0U, // MOVZX64rm16_Q >+ 0U, // MOVZX64rm8_Q >+ 0U, // MOVZX64rr16_Q >+ 0U, // MOVZX64rr8_Q >+ 32U, // MPSADBWrmi >+ 40U, // MPSADBWrri >+ 0U, // MUL16m >+ 0U, // MUL16r >+ 0U, // MUL32m >+ 0U, // MUL32r >+ 0U, // MUL64m >+ 0U, // MUL64r >+ 0U, // MUL8m >+ 0U, // MUL8r >+ 0U, // MULPDrm >+ 0U, // MULPDrr >+ 0U, // MULPSrm >+ 0U, // MULPSrr >+ 0U, // MULSDrm >+ 0U, // MULSDrm_Int >+ 0U, // MULSDrr >+ 0U, // MULSDrr_Int >+ 0U, // MULSSrm >+ 0U, // MULSSrm_Int >+ 0U, // MULSSrr >+ 0U, // MULSSrr_Int >+ 16U, // MULX32rm >+ 8U, // MULX32rr >+ 24U, // MULX64rm >+ 8U, // MULX64rr >+ 0U, // MUL_F32m >+ 0U, // MUL_F64m >+ 0U, // MUL_FI16m >+ 0U, // MUL_FI32m >+ 0U, // MUL_FPrST0 >+ 0U, // MUL_FST0r >+ 0U, // MUL_Fp32 >+ 0U, // MUL_Fp32m >+ 0U, // MUL_Fp64 >+ 0U, // MUL_Fp64m >+ 0U, // MUL_Fp64m32 >+ 0U, // MUL_Fp80 >+ 0U, // MUL_Fp80m32 >+ 0U, // MUL_Fp80m64 >+ 0U, // MUL_FpI16m32 >+ 0U, // MUL_FpI16m64 >+ 0U, // MUL_FpI16m80 >+ 0U, // MUL_FpI32m32 >+ 0U, // MUL_FpI32m64 >+ 0U, // MUL_FpI32m80 >+ 0U, // MUL_FrST0 >+ 0U, // MWAITrr >+ 0U, // NEG16m >+ 0U, // NEG16r >+ 0U, // NEG32m >+ 0U, // NEG32r >+ 0U, // NEG64m >+ 0U, // NEG64r >+ 0U, // NEG8m >+ 0U, // NEG8r >+ 0U, // NOOP >+ 0U, // NOOP18_16m4 >+ 0U, // NOOP18_16m5 >+ 0U, // NOOP18_16m6 >+ 0U, // NOOP18_16m7 >+ 0U, // NOOP18_16r4 >+ 0U, // NOOP18_16r5 >+ 0U, // NOOP18_16r6 >+ 0U, // NOOP18_16r7 >+ 0U, // NOOP18_m4 >+ 0U, // NOOP18_m5 >+ 0U, // NOOP18_m6 >+ 0U, // NOOP18_m7 >+ 0U, // NOOP18_r4 >+ 0U, // NOOP18_r5 >+ 0U, // NOOP18_r6 >+ 0U, // NOOP18_r7 >+ 0U, // NOOP19rr >+ 0U, // NOOPL >+ 0U, // NOOPL_19 >+ 0U, // NOOPL_1a >+ 0U, // NOOPL_1b >+ 0U, // NOOPL_1c >+ 0U, // NOOPL_1d >+ 0U, // NOOPL_1e >+ 0U, // NOOPW >+ 0U, // NOOPW_19 >+ 0U, // NOOPW_1a >+ 0U, // NOOPW_1b >+ 0U, // NOOPW_1c >+ 0U, // NOOPW_1d >+ 0U, // NOOPW_1e >+ 0U, // NOT16m >+ 0U, // NOT16r >+ 0U, // NOT32m >+ 0U, // NOT32r >+ 0U, // NOT64m >+ 0U, // NOT64r >+ 0U, // NOT8m >+ 0U, // NOT8r >+ 0U, // OR16i16 >+ 0U, // OR16mi >+ 0U, // OR16mi8 >+ 0U, // OR16mr >+ 0U, // OR16ri >+ 0U, // OR16ri8 >+ 0U, // OR16rm >+ 0U, // OR16rr >+ 0U, // OR16rr_REV >+ 0U, // OR32i32 >+ 0U, // OR32mi >+ 0U, // OR32mi8 >+ 0U, // OR32mr >+ 0U, // OR32mrLocked >+ 0U, // OR32ri >+ 0U, // OR32ri8 >+ 0U, // OR32rm >+ 0U, // OR32rr >+ 0U, // OR32rr_REV >+ 0U, // OR64i32 >+ 0U, // OR64mi32 >+ 0U, // OR64mi8 >+ 0U, // OR64mr >+ 0U, // OR64ri32 >+ 0U, // OR64ri8 >+ 0U, // OR64rm >+ 0U, // OR64rr >+ 0U, // OR64rr_REV >+ 0U, // OR8i8 >+ 0U, // OR8mi >+ 0U, // OR8mr >+ 0U, // OR8ri >+ 0U, // OR8ri8 >+ 0U, // OR8rm >+ 0U, // OR8rr >+ 0U, // OR8rr_REV >+ 0U, // ORPDrm >+ 0U, // ORPDrr >+ 0U, // ORPSrm >+ 0U, // ORPSrr >+ 0U, // OUT16ir >+ 0U, // OUT16rr >+ 0U, // OUT32ir >+ 0U, // OUT32rr >+ 0U, // OUT8ir >+ 0U, // OUT8rr >+ 0U, // OUTSB >+ 0U, // OUTSL >+ 0U, // OUTSW >+ 0U, // PABSBrm128 >+ 0U, // PABSBrr128 >+ 0U, // PABSDrm128 >+ 0U, // PABSDrr128 >+ 0U, // PABSWrm128 >+ 0U, // PABSWrr128 >+ 0U, // PACKSSDWrm >+ 0U, // PACKSSDWrr >+ 0U, // PACKSSWBrm >+ 0U, // PACKSSWBrr >+ 0U, // PACKUSDWrm >+ 0U, // PACKUSDWrr >+ 0U, // PACKUSWBrm >+ 0U, // PACKUSWBrr >+ 0U, // PADDBrm >+ 0U, // PADDBrr >+ 0U, // PADDDrm >+ 0U, // PADDDrr >+ 0U, // PADDQrm >+ 0U, // PADDQrr >+ 0U, // PADDSBrm >+ 0U, // PADDSBrr >+ 0U, // PADDSWrm >+ 0U, // PADDSWrr >+ 0U, // PADDUSBrm >+ 0U, // PADDUSBrr >+ 0U, // PADDUSWrm >+ 0U, // PADDUSWrr >+ 0U, // PADDWrm >+ 0U, // PADDWrr >+ 32U, // PALIGNR128rm >+ 40U, // PALIGNR128rr >+ 0U, // PANDNrm >+ 0U, // PANDNrr >+ 0U, // PANDrm >+ 0U, // PANDrr >+ 0U, // PAUSE >+ 0U, // PAVGBrm >+ 0U, // PAVGBrr >+ 0U, // PAVGUSBrm >+ 0U, // PAVGUSBrr >+ 0U, // PAVGWrm >+ 0U, // PAVGWrr >+ 0U, // PBLENDVBrm0 >+ 0U, // PBLENDVBrr0 >+ 32U, // PBLENDWrmi >+ 40U, // PBLENDWrri >+ 32U, // PCLMULQDQrm >+ 40U, // PCLMULQDQrr >+ 0U, // PCMPEQBrm >+ 0U, // PCMPEQBrr >+ 0U, // PCMPEQDrm >+ 0U, // PCMPEQDrr >+ 0U, // PCMPEQQrm >+ 0U, // PCMPEQQrr >+ 0U, // PCMPEQWrm >+ 0U, // PCMPEQWrr >+ 0U, // PCMPESTRIMEM >+ 0U, // PCMPESTRIREG >+ 0U, // PCMPESTRIrm >+ 8U, // PCMPESTRIrr >+ 0U, // PCMPESTRM128MEM >+ 0U, // PCMPESTRM128REG >+ 0U, // PCMPESTRM128rm >+ 8U, // PCMPESTRM128rr >+ 0U, // PCMPGTBrm >+ 0U, // PCMPGTBrr >+ 0U, // PCMPGTDrm >+ 0U, // PCMPGTDrr >+ 0U, // PCMPGTQrm >+ 0U, // PCMPGTQrr >+ 0U, // PCMPGTWrm >+ 0U, // PCMPGTWrr >+ 0U, // PCMPISTRIMEM >+ 0U, // PCMPISTRIREG >+ 0U, // PCMPISTRIrm >+ 8U, // PCMPISTRIrr >+ 0U, // PCMPISTRM128MEM >+ 0U, // PCMPISTRM128REG >+ 0U, // PCMPISTRM128rm >+ 8U, // PCMPISTRM128rr >+ 16U, // PDEP32rm >+ 8U, // PDEP32rr >+ 24U, // PDEP64rm >+ 8U, // PDEP64rr >+ 16U, // PEXT32rm >+ 8U, // PEXT32rr >+ 24U, // PEXT64rm >+ 8U, // PEXT64rr >+ 0U, // PEXTRBmr >+ 8U, // PEXTRBrr >+ 0U, // PEXTRDmr >+ 8U, // PEXTRDrr >+ 0U, // PEXTRQmr >+ 8U, // PEXTRQrr >+ 0U, // PEXTRWmr >+ 8U, // PEXTRWri >+ 8U, // PEXTRWrr_REV >+ 0U, // PF2IDrm >+ 0U, // PF2IDrr >+ 0U, // PF2IWrm >+ 0U, // PF2IWrr >+ 0U, // PFACCrm >+ 0U, // PFACCrr >+ 0U, // PFADDrm >+ 0U, // PFADDrr >+ 0U, // PFCMPEQrm >+ 0U, // PFCMPEQrr >+ 0U, // PFCMPGErm >+ 0U, // PFCMPGErr >+ 0U, // PFCMPGTrm >+ 0U, // PFCMPGTrr >+ 0U, // PFMAXrm >+ 0U, // PFMAXrr >+ 0U, // PFMINrm >+ 0U, // PFMINrr >+ 0U, // PFMULrm >+ 0U, // PFMULrr >+ 0U, // PFNACCrm >+ 0U, // PFNACCrr >+ 0U, // PFPNACCrm >+ 0U, // PFPNACCrr >+ 0U, // PFRCPIT1rm >+ 0U, // PFRCPIT1rr >+ 0U, // PFRCPIT2rm >+ 0U, // PFRCPIT2rr >+ 0U, // PFRCPrm >+ 0U, // PFRCPrr >+ 0U, // PFRSQIT1rm >+ 0U, // PFRSQIT1rr >+ 0U, // PFRSQRTrm >+ 0U, // PFRSQRTrr >+ 0U, // PFSUBRrm >+ 0U, // PFSUBRrr >+ 0U, // PFSUBrm >+ 0U, // PFSUBrr >+ 0U, // PHADDDrm >+ 0U, // PHADDDrr >+ 0U, // PHADDSWrm128 >+ 0U, // PHADDSWrr128 >+ 0U, // PHADDWrm >+ 0U, // PHADDWrr >+ 0U, // PHMINPOSUWrm128 >+ 0U, // PHMINPOSUWrr128 >+ 0U, // PHSUBDrm >+ 0U, // PHSUBDrr >+ 0U, // PHSUBSWrm128 >+ 0U, // PHSUBSWrr128 >+ 0U, // PHSUBWrm >+ 0U, // PHSUBWrr >+ 0U, // PI2FDrm >+ 0U, // PI2FDrr >+ 0U, // PI2FWrm >+ 0U, // PI2FWrr >+ 32U, // PINSRBrm >+ 40U, // PINSRBrr >+ 32U, // PINSRDrm >+ 40U, // PINSRDrr >+ 32U, // PINSRQrm >+ 40U, // PINSRQrr >+ 32U, // PINSRWrmi >+ 40U, // PINSRWrri >+ 0U, // PMADDUBSWrm128 >+ 0U, // PMADDUBSWrr128 >+ 0U, // PMADDWDrm >+ 0U, // PMADDWDrr >+ 0U, // PMAXSBrm >+ 0U, // PMAXSBrr >+ 0U, // PMAXSDrm >+ 0U, // PMAXSDrr >+ 0U, // PMAXSWrm >+ 0U, // PMAXSWrr >+ 0U, // PMAXUBrm >+ 0U, // PMAXUBrr >+ 0U, // PMAXUDrm >+ 0U, // PMAXUDrr >+ 0U, // PMAXUWrm >+ 0U, // PMAXUWrr >+ 0U, // PMINSBrm >+ 0U, // PMINSBrr >+ 0U, // PMINSDrm >+ 0U, // PMINSDrr >+ 0U, // PMINSWrm >+ 0U, // PMINSWrr >+ 0U, // PMINUBrm >+ 0U, // PMINUBrr >+ 0U, // PMINUDrm >+ 0U, // PMINUDrr >+ 0U, // PMINUWrm >+ 0U, // PMINUWrr >+ 0U, // PMOVMSKBrr >+ 0U, // PMOVSXBDrm >+ 0U, // PMOVSXBDrr >+ 0U, // PMOVSXBQrm >+ 0U, // PMOVSXBQrr >+ 0U, // PMOVSXBWrm >+ 0U, // PMOVSXBWrr >+ 0U, // PMOVSXDQrm >+ 0U, // PMOVSXDQrr >+ 0U, // PMOVSXWDrm >+ 0U, // PMOVSXWDrr >+ 0U, // PMOVSXWQrm >+ 0U, // PMOVSXWQrr >+ 0U, // PMOVZXBDrm >+ 0U, // PMOVZXBDrr >+ 0U, // PMOVZXBQrm >+ 0U, // PMOVZXBQrr >+ 0U, // PMOVZXBWrm >+ 0U, // PMOVZXBWrr >+ 0U, // PMOVZXDQrm >+ 0U, // PMOVZXDQrr >+ 0U, // PMOVZXWDrm >+ 0U, // PMOVZXWDrr >+ 0U, // PMOVZXWQrm >+ 0U, // PMOVZXWQrr >+ 0U, // PMULDQrm >+ 0U, // PMULDQrr >+ 0U, // PMULHRSWrm128 >+ 0U, // PMULHRSWrr128 >+ 0U, // PMULHRWrm >+ 0U, // PMULHRWrr >+ 0U, // PMULHUWrm >+ 0U, // PMULHUWrr >+ 0U, // PMULHWrm >+ 0U, // PMULHWrr >+ 0U, // PMULLDrm >+ 0U, // PMULLDrr >+ 0U, // PMULLWrm >+ 0U, // PMULLWrr >+ 0U, // PMULUDQrm >+ 0U, // PMULUDQrr >+ 0U, // POP16r >+ 0U, // POP16rmm >+ 0U, // POP16rmr >+ 0U, // POP32r >+ 0U, // POP32rmm >+ 0U, // POP32rmr >+ 0U, // POP64r >+ 0U, // POP64rmm >+ 0U, // POP64rmr >+ 0U, // POPA16 >+ 0U, // POPA32 >+ 0U, // POPCNT16rm >+ 0U, // POPCNT16rr >+ 0U, // POPCNT32rm >+ 0U, // POPCNT32rr >+ 0U, // POPCNT64rm >+ 0U, // POPCNT64rr >+ 0U, // POPDS16 >+ 0U, // POPDS32 >+ 0U, // POPES16 >+ 0U, // POPES32 >+ 0U, // POPF16 >+ 0U, // POPF32 >+ 0U, // POPF64 >+ 0U, // POPFS16 >+ 0U, // POPFS32 >+ 0U, // POPFS64 >+ 0U, // POPGS16 >+ 0U, // POPGS32 >+ 0U, // POPGS64 >+ 0U, // POPSS16 >+ 0U, // POPSS32 >+ 0U, // PORrm >+ 0U, // PORrr >+ 0U, // PREFETCH >+ 0U, // PREFETCHNTA >+ 0U, // PREFETCHT0 >+ 0U, // PREFETCHT1 >+ 0U, // PREFETCHT2 >+ 0U, // PREFETCHW >+ 0U, // PSADBWrm >+ 0U, // PSADBWrr >+ 0U, // PSHUFBrm >+ 0U, // PSHUFBrr >+ 0U, // PSHUFDmi >+ 8U, // PSHUFDri >+ 0U, // PSHUFHWmi >+ 8U, // PSHUFHWri >+ 0U, // PSHUFLWmi >+ 8U, // PSHUFLWri >+ 0U, // PSIGNBrm >+ 0U, // PSIGNBrr >+ 0U, // PSIGNDrm >+ 0U, // PSIGNDrr >+ 0U, // PSIGNWrm >+ 0U, // PSIGNWrr >+ 0U, // PSLLDQri >+ 0U, // PSLLDri >+ 0U, // PSLLDrm >+ 0U, // PSLLDrr >+ 0U, // PSLLQri >+ 0U, // PSLLQrm >+ 0U, // PSLLQrr >+ 0U, // PSLLWri >+ 0U, // PSLLWrm >+ 0U, // PSLLWrr >+ 0U, // PSRADri >+ 0U, // PSRADrm >+ 0U, // PSRADrr >+ 0U, // PSRAWri >+ 0U, // PSRAWrm >+ 0U, // PSRAWrr >+ 0U, // PSRLDQri >+ 0U, // PSRLDri >+ 0U, // PSRLDrm >+ 0U, // PSRLDrr >+ 0U, // PSRLQri >+ 0U, // PSRLQrm >+ 0U, // PSRLQrr >+ 0U, // PSRLWri >+ 0U, // PSRLWrm >+ 0U, // PSRLWrr >+ 0U, // PSUBBrm >+ 0U, // PSUBBrr >+ 0U, // PSUBDrm >+ 0U, // PSUBDrr >+ 0U, // PSUBQrm >+ 0U, // PSUBQrr >+ 0U, // PSUBSBrm >+ 0U, // PSUBSBrr >+ 0U, // PSUBSWrm >+ 0U, // PSUBSWrr >+ 0U, // PSUBUSBrm >+ 0U, // PSUBUSBrr >+ 0U, // PSUBUSWrm >+ 0U, // PSUBUSWrr >+ 0U, // PSUBWrm >+ 0U, // PSUBWrr >+ 0U, // PSWAPDrm >+ 0U, // PSWAPDrr >+ 0U, // PTESTrm >+ 0U, // PTESTrr >+ 0U, // PUNPCKHBWrm >+ 0U, // PUNPCKHBWrr >+ 0U, // PUNPCKHDQrm >+ 0U, // PUNPCKHDQrr >+ 0U, // PUNPCKHQDQrm >+ 0U, // PUNPCKHQDQrr >+ 0U, // PUNPCKHWDrm >+ 0U, // PUNPCKHWDrr >+ 0U, // PUNPCKLBWrm >+ 0U, // PUNPCKLBWrr >+ 0U, // PUNPCKLDQrm >+ 0U, // PUNPCKLDQrr >+ 0U, // PUNPCKLQDQrm >+ 0U, // PUNPCKLQDQrr >+ 0U, // PUNPCKLWDrm >+ 0U, // PUNPCKLWDrr >+ 0U, // PUSH16i8 >+ 0U, // PUSH16r >+ 0U, // PUSH16rmm >+ 0U, // PUSH16rmr >+ 0U, // PUSH32i8 >+ 0U, // PUSH32r >+ 0U, // PUSH32rmm >+ 0U, // PUSH32rmr >+ 0U, // PUSH64i16 >+ 0U, // PUSH64i32 >+ 0U, // PUSH64i8 >+ 0U, // PUSH64r >+ 0U, // PUSH64rmm >+ 0U, // PUSH64rmr >+ 0U, // PUSHA16 >+ 0U, // PUSHA32 >+ 0U, // PUSHCS16 >+ 0U, // PUSHCS32 >+ 0U, // PUSHDS16 >+ 0U, // PUSHDS32 >+ 0U, // PUSHES16 >+ 0U, // PUSHES32 >+ 0U, // PUSHF16 >+ 0U, // PUSHF32 >+ 0U, // PUSHF64 >+ 0U, // PUSHFS16 >+ 0U, // PUSHFS32 >+ 0U, // PUSHFS64 >+ 0U, // PUSHGS16 >+ 0U, // PUSHGS32 >+ 0U, // PUSHGS64 >+ 0U, // PUSHSS16 >+ 0U, // PUSHSS32 >+ 0U, // PUSHi16 >+ 0U, // PUSHi32 >+ 0U, // PXORrm >+ 0U, // PXORrr >+ 0U, // RCL16m1 >+ 0U, // RCL16mCL >+ 0U, // RCL16mi >+ 0U, // RCL16r1 >+ 0U, // RCL16rCL >+ 0U, // RCL16ri >+ 0U, // RCL32m1 >+ 0U, // RCL32mCL >+ 0U, // RCL32mi >+ 0U, // RCL32r1 >+ 0U, // RCL32rCL >+ 0U, // RCL32ri >+ 0U, // RCL64m1 >+ 0U, // RCL64mCL >+ 0U, // RCL64mi >+ 0U, // RCL64r1 >+ 0U, // RCL64rCL >+ 0U, // RCL64ri >+ 0U, // RCL8m1 >+ 0U, // RCL8mCL >+ 0U, // RCL8mi >+ 0U, // RCL8r1 >+ 0U, // RCL8rCL >+ 0U, // RCL8ri >+ 0U, // RCPPSm >+ 0U, // RCPPSm_Int >+ 0U, // RCPPSr >+ 0U, // RCPPSr_Int >+ 0U, // RCPSSm >+ 0U, // RCPSSm_Int >+ 0U, // RCPSSr >+ 0U, // RCPSSr_Int >+ 0U, // RCR16m1 >+ 0U, // RCR16mCL >+ 0U, // RCR16mi >+ 0U, // RCR16r1 >+ 0U, // RCR16rCL >+ 0U, // RCR16ri >+ 0U, // RCR32m1 >+ 0U, // RCR32mCL >+ 0U, // RCR32mi >+ 0U, // RCR32r1 >+ 0U, // RCR32rCL >+ 0U, // RCR32ri >+ 0U, // RCR64m1 >+ 0U, // RCR64mCL >+ 0U, // RCR64mi >+ 0U, // RCR64r1 >+ 0U, // RCR64rCL >+ 0U, // RCR64ri >+ 0U, // RCR8m1 >+ 0U, // RCR8mCL >+ 0U, // RCR8mi >+ 0U, // RCR8r1 >+ 0U, // RCR8rCL >+ 0U, // RCR8ri >+ 0U, // RDFSBASE >+ 0U, // RDFSBASE64 >+ 0U, // RDGSBASE >+ 0U, // RDGSBASE64 >+ 0U, // RDMSR >+ 0U, // RDPMC >+ 0U, // RDRAND16r >+ 0U, // RDRAND32r >+ 0U, // RDRAND64r >+ 0U, // RDSEED16r >+ 0U, // RDSEED32r >+ 0U, // RDSEED64r >+ 0U, // RDTSC >+ 0U, // RDTSCP >+ 0U, // RELEASE_MOV16mr >+ 0U, // RELEASE_MOV32mr >+ 0U, // RELEASE_MOV64mr >+ 0U, // RELEASE_MOV8mr >+ 0U, // REPNE_PREFIX >+ 0U, // REP_MOVSB_32 >+ 0U, // REP_MOVSB_64 >+ 0U, // REP_MOVSD_32 >+ 0U, // REP_MOVSD_64 >+ 0U, // REP_MOVSQ_64 >+ 0U, // REP_MOVSW_32 >+ 0U, // REP_MOVSW_64 >+ 0U, // REP_PREFIX >+ 0U, // REP_STOSB_32 >+ 0U, // REP_STOSB_64 >+ 0U, // REP_STOSD_32 >+ 0U, // REP_STOSD_64 >+ 0U, // REP_STOSQ_64 >+ 0U, // REP_STOSW_32 >+ 0U, // REP_STOSW_64 >+ 0U, // RETIL >+ 0U, // RETIQ >+ 0U, // RETIW >+ 0U, // RETL >+ 0U, // RETQ >+ 0U, // RETW >+ 0U, // REX64_PREFIX >+ 0U, // ROL16m1 >+ 0U, // ROL16mCL >+ 0U, // ROL16mi >+ 0U, // ROL16r1 >+ 0U, // ROL16rCL >+ 0U, // ROL16ri >+ 0U, // ROL32m1 >+ 0U, // ROL32mCL >+ 0U, // ROL32mi >+ 0U, // ROL32r1 >+ 0U, // ROL32rCL >+ 0U, // ROL32ri >+ 0U, // ROL64m1 >+ 0U, // ROL64mCL >+ 0U, // ROL64mi >+ 0U, // ROL64r1 >+ 0U, // ROL64rCL >+ 0U, // ROL64ri >+ 0U, // ROL8m1 >+ 0U, // ROL8mCL >+ 0U, // ROL8mi >+ 0U, // ROL8r1 >+ 0U, // ROL8rCL >+ 0U, // ROL8ri >+ 0U, // ROR16m1 >+ 0U, // ROR16mCL >+ 0U, // ROR16mi >+ 0U, // ROR16r1 >+ 0U, // ROR16rCL >+ 0U, // ROR16ri >+ 0U, // ROR32m1 >+ 0U, // ROR32mCL >+ 0U, // ROR32mi >+ 0U, // ROR32r1 >+ 0U, // ROR32rCL >+ 0U, // ROR32ri >+ 0U, // ROR64m1 >+ 0U, // ROR64mCL >+ 0U, // ROR64mi >+ 0U, // ROR64r1 >+ 0U, // ROR64rCL >+ 0U, // ROR64ri >+ 0U, // ROR8m1 >+ 0U, // ROR8mCL >+ 0U, // ROR8mi >+ 0U, // ROR8r1 >+ 0U, // ROR8rCL >+ 0U, // ROR8ri >+ 0U, // RORX32mi >+ 8U, // RORX32ri >+ 0U, // RORX64mi >+ 8U, // RORX64ri >+ 0U, // ROUNDPDm >+ 8U, // ROUNDPDr >+ 0U, // ROUNDPSm >+ 8U, // ROUNDPSr >+ 32U, // ROUNDSDm >+ 40U, // ROUNDSDr >+ 40U, // ROUNDSDr_Int >+ 32U, // ROUNDSSm >+ 40U, // ROUNDSSr >+ 40U, // ROUNDSSr_Int >+ 0U, // RSM >+ 0U, // RSQRTPSm >+ 0U, // RSQRTPSm_Int >+ 0U, // RSQRTPSr >+ 0U, // RSQRTPSr_Int >+ 0U, // RSQRTSSm >+ 0U, // RSQRTSSm_Int >+ 0U, // RSQRTSSr >+ 0U, // RSQRTSSr_Int >+ 0U, // SAHF >+ 0U, // SAL16m1 >+ 0U, // SAL16mCL >+ 0U, // SAL16mi >+ 0U, // SAL16r1 >+ 0U, // SAL16rCL >+ 0U, // SAL16ri >+ 0U, // SAL32m1 >+ 0U, // SAL32mCL >+ 0U, // SAL32mi >+ 0U, // SAL32r1 >+ 0U, // SAL32rCL >+ 0U, // SAL32ri >+ 0U, // SAL64m1 >+ 0U, // SAL64mCL >+ 0U, // SAL64mi >+ 0U, // SAL64r1 >+ 0U, // SAL64rCL >+ 0U, // SAL64ri >+ 0U, // SAL8m1 >+ 0U, // SAL8mCL >+ 0U, // SAL8mi >+ 0U, // SAL8r1 >+ 0U, // SAL8rCL >+ 0U, // SAL8ri >+ 0U, // SALC >+ 0U, // SAR16m1 >+ 0U, // SAR16mCL >+ 0U, // SAR16mi >+ 0U, // SAR16r1 >+ 0U, // SAR16rCL >+ 0U, // SAR16ri >+ 0U, // SAR32m1 >+ 0U, // SAR32mCL >+ 0U, // SAR32mi >+ 0U, // SAR32r1 >+ 0U, // SAR32rCL >+ 0U, // SAR32ri >+ 0U, // SAR64m1 >+ 0U, // SAR64mCL >+ 0U, // SAR64mi >+ 0U, // SAR64r1 >+ 0U, // SAR64rCL >+ 0U, // SAR64ri >+ 0U, // SAR8m1 >+ 0U, // SAR8mCL >+ 0U, // SAR8mi >+ 0U, // SAR8r1 >+ 0U, // SAR8rCL >+ 0U, // SAR8ri >+ 0U, // SARX32rm >+ 8U, // SARX32rr >+ 0U, // SARX64rm >+ 8U, // SARX64rr >+ 0U, // SBB16i16 >+ 0U, // SBB16mi >+ 0U, // SBB16mi8 >+ 0U, // SBB16mr >+ 0U, // SBB16ri >+ 0U, // SBB16ri8 >+ 0U, // SBB16rm >+ 0U, // SBB16rr >+ 0U, // SBB16rr_REV >+ 0U, // SBB32i32 >+ 0U, // SBB32mi >+ 0U, // SBB32mi8 >+ 0U, // SBB32mr >+ 0U, // SBB32ri >+ 0U, // SBB32ri8 >+ 0U, // SBB32rm >+ 0U, // SBB32rr >+ 0U, // SBB32rr_REV >+ 0U, // SBB64i32 >+ 0U, // SBB64mi32 >+ 0U, // SBB64mi8 >+ 0U, // SBB64mr >+ 0U, // SBB64ri32 >+ 0U, // SBB64ri8 >+ 0U, // SBB64rm >+ 0U, // SBB64rr >+ 0U, // SBB64rr_REV >+ 0U, // SBB8i8 >+ 0U, // SBB8mi >+ 0U, // SBB8mr >+ 0U, // SBB8ri >+ 0U, // SBB8rm >+ 0U, // SBB8rr >+ 0U, // SBB8rr_REV >+ 0U, // SCASB >+ 0U, // SCASL >+ 0U, // SCASQ >+ 0U, // SCASW >+ 0U, // SEG_ALLOCA_32 >+ 0U, // SEG_ALLOCA_64 >+ 0U, // SEH_EndPrologue >+ 0U, // SEH_Epilogue >+ 0U, // SEH_PushFrame >+ 0U, // SEH_PushReg >+ 0U, // SEH_SaveReg >+ 0U, // SEH_SaveXMM >+ 0U, // SEH_SetFrame >+ 0U, // SEH_StackAlloc >+ 0U, // SETAEm >+ 0U, // SETAEr >+ 0U, // SETAm >+ 0U, // SETAr >+ 0U, // SETBEm >+ 0U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 0U, // SETBm >+ 0U, // SETBr >+ 0U, // SETEm >+ 0U, // SETEr >+ 0U, // SETGEm >+ 0U, // SETGEr >+ 0U, // SETGm >+ 0U, // SETGr >+ 0U, // SETLEm >+ 0U, // SETLEr >+ 0U, // SETLm >+ 0U, // SETLr >+ 0U, // SETNEm >+ 0U, // SETNEr >+ 0U, // SETNOm >+ 0U, // SETNOr >+ 0U, // SETNPm >+ 0U, // SETNPr >+ 0U, // SETNSm >+ 0U, // SETNSr >+ 0U, // SETOm >+ 0U, // SETOr >+ 0U, // SETPm >+ 0U, // SETPr >+ 0U, // SETSm >+ 0U, // SETSr >+ 0U, // SFENCE >+ 0U, // SGDT16m >+ 0U, // SGDT32m >+ 0U, // SGDT64m >+ 0U, // SHA1MSG1rm >+ 0U, // SHA1MSG1rr >+ 0U, // SHA1MSG2rm >+ 0U, // SHA1MSG2rr >+ 0U, // SHA1NEXTErm >+ 0U, // SHA1NEXTErr >+ 32U, // SHA1RNDS4rmi >+ 40U, // SHA1RNDS4rri >+ 0U, // SHA256MSG1rm >+ 0U, // SHA256MSG1rr >+ 0U, // SHA256MSG2rm >+ 0U, // SHA256MSG2rr >+ 0U, // SHA256RNDS2rm >+ 0U, // SHA256RNDS2rr >+ 0U, // SHL16m1 >+ 0U, // SHL16mCL >+ 0U, // SHL16mi >+ 0U, // SHL16r1 >+ 0U, // SHL16rCL >+ 0U, // SHL16ri >+ 0U, // SHL32m1 >+ 0U, // SHL32mCL >+ 0U, // SHL32mi >+ 0U, // SHL32r1 >+ 0U, // SHL32rCL >+ 0U, // SHL32ri >+ 0U, // SHL64m1 >+ 0U, // SHL64mCL >+ 0U, // SHL64mi >+ 0U, // SHL64r1 >+ 0U, // SHL64rCL >+ 0U, // SHL64ri >+ 0U, // SHL8m1 >+ 0U, // SHL8mCL >+ 0U, // SHL8mi >+ 0U, // SHL8r1 >+ 0U, // SHL8rCL >+ 0U, // SHL8ri >+ 1U, // SHLD16mrCL >+ 0U, // SHLD16mri8 >+ 1U, // SHLD16rrCL >+ 40U, // SHLD16rri8 >+ 1U, // SHLD32mrCL >+ 0U, // SHLD32mri8 >+ 1U, // SHLD32rrCL >+ 40U, // SHLD32rri8 >+ 1U, // SHLD64mrCL >+ 0U, // SHLD64mri8 >+ 1U, // SHLD64rrCL >+ 40U, // SHLD64rri8 >+ 0U, // SHLX32rm >+ 8U, // SHLX32rr >+ 0U, // SHLX64rm >+ 8U, // SHLX64rr >+ 0U, // SHR16m1 >+ 0U, // SHR16mCL >+ 0U, // SHR16mi >+ 0U, // SHR16r1 >+ 0U, // SHR16rCL >+ 0U, // SHR16ri >+ 0U, // SHR32m1 >+ 0U, // SHR32mCL >+ 0U, // SHR32mi >+ 0U, // SHR32r1 >+ 0U, // SHR32rCL >+ 0U, // SHR32ri >+ 0U, // SHR64m1 >+ 0U, // SHR64mCL >+ 0U, // SHR64mi >+ 0U, // SHR64r1 >+ 0U, // SHR64rCL >+ 0U, // SHR64ri >+ 0U, // SHR8m1 >+ 0U, // SHR8mCL >+ 0U, // SHR8mi >+ 0U, // SHR8r1 >+ 0U, // SHR8rCL >+ 0U, // SHR8ri >+ 1U, // SHRD16mrCL >+ 0U, // SHRD16mri8 >+ 1U, // SHRD16rrCL >+ 40U, // SHRD16rri8 >+ 1U, // SHRD32mrCL >+ 0U, // SHRD32mri8 >+ 1U, // SHRD32rrCL >+ 40U, // SHRD32rri8 >+ 1U, // SHRD64mrCL >+ 0U, // SHRD64mri8 >+ 1U, // SHRD64rrCL >+ 40U, // SHRD64rri8 >+ 0U, // SHRX32rm >+ 8U, // SHRX32rr >+ 0U, // SHRX64rm >+ 8U, // SHRX64rr >+ 32U, // SHUFPDrmi >+ 40U, // SHUFPDrri >+ 32U, // SHUFPSrmi >+ 40U, // SHUFPSrri >+ 0U, // SIDT16m >+ 0U, // SIDT32m >+ 0U, // SIDT64m >+ 0U, // SIN_F >+ 0U, // SIN_Fp32 >+ 0U, // SIN_Fp64 >+ 0U, // SIN_Fp80 >+ 0U, // SKINIT >+ 0U, // SLDT16m >+ 0U, // SLDT16r >+ 0U, // SLDT32r >+ 0U, // SLDT64m >+ 0U, // SLDT64r >+ 0U, // SMSW16m >+ 0U, // SMSW16r >+ 0U, // SMSW32r >+ 0U, // SMSW64r >+ 0U, // SQRTPDm >+ 0U, // SQRTPDr >+ 0U, // SQRTPSm >+ 0U, // SQRTPSr >+ 0U, // SQRTSDm >+ 0U, // SQRTSDm_Int >+ 0U, // SQRTSDr >+ 0U, // SQRTSDr_Int >+ 0U, // SQRTSSm >+ 0U, // SQRTSSm_Int >+ 0U, // SQRTSSr >+ 0U, // SQRTSSr_Int >+ 0U, // SQRT_F >+ 0U, // SQRT_Fp32 >+ 0U, // SQRT_Fp64 >+ 0U, // SQRT_Fp80 >+ 0U, // STAC >+ 0U, // STC >+ 0U, // STD >+ 0U, // STGI >+ 0U, // STI >+ 0U, // STMXCSR >+ 0U, // STOSB >+ 0U, // STOSL >+ 0U, // STOSQ >+ 0U, // STOSW >+ 0U, // STR16r >+ 0U, // STR32r >+ 0U, // STR64r >+ 0U, // STRm >+ 0U, // ST_F32m >+ 0U, // ST_F64m >+ 0U, // ST_FCOMPST0r >+ 0U, // ST_FCOMPST0r_alt >+ 0U, // ST_FCOMST0r >+ 0U, // ST_FP32m >+ 0U, // ST_FP64m >+ 0U, // ST_FP80m >+ 0U, // ST_FPNCEST0r >+ 0U, // ST_FPST0r >+ 0U, // ST_FPST0r_alt >+ 0U, // ST_FPrr >+ 0U, // ST_FXCHST0r >+ 0U, // ST_FXCHST0r_alt >+ 0U, // ST_Fp32m >+ 0U, // ST_Fp64m >+ 0U, // ST_Fp64m32 >+ 0U, // ST_Fp80m32 >+ 0U, // ST_Fp80m64 >+ 0U, // ST_FpP32m >+ 0U, // ST_FpP64m >+ 0U, // ST_FpP64m32 >+ 0U, // ST_FpP80m >+ 0U, // ST_FpP80m32 >+ 0U, // ST_FpP80m64 >+ 0U, // ST_Frr >+ 0U, // SUB16i16 >+ 0U, // SUB16mi >+ 0U, // SUB16mi8 >+ 0U, // SUB16mr >+ 0U, // SUB16ri >+ 0U, // SUB16ri8 >+ 0U, // SUB16rm >+ 0U, // SUB16rr >+ 0U, // SUB16rr_REV >+ 0U, // SUB32i32 >+ 0U, // SUB32mi >+ 0U, // SUB32mi8 >+ 0U, // SUB32mr >+ 0U, // SUB32ri >+ 0U, // SUB32ri8 >+ 0U, // SUB32rm >+ 0U, // SUB32rr >+ 0U, // SUB32rr_REV >+ 0U, // SUB64i32 >+ 0U, // SUB64mi32 >+ 0U, // SUB64mi8 >+ 0U, // SUB64mr >+ 0U, // SUB64ri32 >+ 0U, // SUB64ri8 >+ 0U, // SUB64rm >+ 0U, // SUB64rr >+ 0U, // SUB64rr_REV >+ 0U, // SUB8i8 >+ 0U, // SUB8mi >+ 0U, // SUB8mr >+ 0U, // SUB8ri >+ 0U, // SUB8ri8 >+ 0U, // SUB8rm >+ 0U, // SUB8rr >+ 0U, // SUB8rr_REV >+ 0U, // SUBPDrm >+ 0U, // SUBPDrr >+ 0U, // SUBPSrm >+ 0U, // SUBPSrr >+ 0U, // SUBR_F32m >+ 0U, // SUBR_F64m >+ 0U, // SUBR_FI16m >+ 0U, // SUBR_FI32m >+ 0U, // SUBR_FPrST0 >+ 0U, // SUBR_FST0r >+ 0U, // SUBR_Fp32m >+ 0U, // SUBR_Fp64m >+ 0U, // SUBR_Fp64m32 >+ 0U, // SUBR_Fp80m32 >+ 0U, // SUBR_Fp80m64 >+ 0U, // SUBR_FpI16m32 >+ 0U, // SUBR_FpI16m64 >+ 0U, // SUBR_FpI16m80 >+ 0U, // SUBR_FpI32m32 >+ 0U, // SUBR_FpI32m64 >+ 0U, // SUBR_FpI32m80 >+ 0U, // SUBR_FrST0 >+ 0U, // SUBSDrm >+ 0U, // SUBSDrm_Int >+ 0U, // SUBSDrr >+ 0U, // SUBSDrr_Int >+ 0U, // SUBSSrm >+ 0U, // SUBSSrm_Int >+ 0U, // SUBSSrr >+ 0U, // SUBSSrr_Int >+ 0U, // SUB_F32m >+ 0U, // SUB_F64m >+ 0U, // SUB_FI16m >+ 0U, // SUB_FI32m >+ 0U, // SUB_FPrST0 >+ 0U, // SUB_FST0r >+ 0U, // SUB_Fp32 >+ 0U, // SUB_Fp32m >+ 0U, // SUB_Fp64 >+ 0U, // SUB_Fp64m >+ 0U, // SUB_Fp64m32 >+ 0U, // SUB_Fp80 >+ 0U, // SUB_Fp80m32 >+ 0U, // SUB_Fp80m64 >+ 0U, // SUB_FpI16m32 >+ 0U, // SUB_FpI16m64 >+ 0U, // SUB_FpI16m80 >+ 0U, // SUB_FpI32m32 >+ 0U, // SUB_FpI32m64 >+ 0U, // SUB_FpI32m80 >+ 0U, // SUB_FrST0 >+ 0U, // SWAPGS >+ 0U, // SYSCALL >+ 0U, // SYSENTER >+ 0U, // SYSEXIT >+ 0U, // SYSEXIT64 >+ 0U, // SYSRET >+ 0U, // SYSRET64 >+ 0U, // T1MSKC32rm >+ 0U, // T1MSKC32rr >+ 0U, // T1MSKC64rm >+ 0U, // T1MSKC64rr >+ 0U, // TAILJMPd >+ 0U, // TAILJMPd64 >+ 0U, // TAILJMPm >+ 0U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 0U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 0U, // TEST16i16 >+ 0U, // TEST16mi >+ 0U, // TEST16mi_alt >+ 0U, // TEST16ri >+ 0U, // TEST16ri_alt >+ 0U, // TEST16rm >+ 0U, // TEST16rr >+ 0U, // TEST32i32 >+ 0U, // TEST32mi >+ 0U, // TEST32mi_alt >+ 0U, // TEST32ri >+ 0U, // TEST32ri_alt >+ 0U, // TEST32rm >+ 0U, // TEST32rr >+ 0U, // TEST64i32 >+ 0U, // TEST64mi32 >+ 0U, // TEST64mi32_alt >+ 0U, // TEST64ri32 >+ 0U, // TEST64ri32_alt >+ 0U, // TEST64rm >+ 0U, // TEST64rr >+ 0U, // TEST8i8 >+ 0U, // TEST8mi >+ 0U, // TEST8mi_alt >+ 0U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 0U, // TEST8ri_alt >+ 0U, // TEST8rm >+ 0U, // TEST8rr >+ 0U, // TLSCall_32 >+ 0U, // TLSCall_64 >+ 0U, // TLS_addr32 >+ 0U, // TLS_addr64 >+ 0U, // TLS_base_addr32 >+ 0U, // TLS_base_addr64 >+ 0U, // TRAP >+ 0U, // TST_F >+ 0U, // TST_Fp32 >+ 0U, // TST_Fp64 >+ 0U, // TST_Fp80 >+ 0U, // TZCNT16rm >+ 0U, // TZCNT16rr >+ 0U, // TZCNT32rm >+ 0U, // TZCNT32rr >+ 0U, // TZCNT64rm >+ 0U, // TZCNT64rr >+ 0U, // TZMSK32rm >+ 0U, // TZMSK32rr >+ 0U, // TZMSK64rm >+ 0U, // TZMSK64rr >+ 0U, // UCOMISDrm >+ 0U, // UCOMISDrr >+ 0U, // UCOMISSrm >+ 0U, // UCOMISSrr >+ 0U, // UCOM_FIPr >+ 0U, // UCOM_FIr >+ 0U, // UCOM_FPPr >+ 0U, // UCOM_FPr >+ 0U, // UCOM_FpIr32 >+ 0U, // UCOM_FpIr64 >+ 0U, // UCOM_FpIr80 >+ 0U, // UCOM_Fpr32 >+ 0U, // UCOM_Fpr64 >+ 0U, // UCOM_Fpr80 >+ 0U, // UCOM_Fr >+ 0U, // UD2B >+ 0U, // UNPCKHPDrm >+ 0U, // UNPCKHPDrr >+ 0U, // UNPCKHPSrm >+ 0U, // UNPCKHPSrr >+ 0U, // UNPCKLPDrm >+ 0U, // UNPCKLPDrr >+ 0U, // UNPCKLPSrm >+ 0U, // UNPCKLPSrr >+ 35072U, // VAARG_64 >+ 64U, // VADDPDYrm >+ 8U, // VADDPDYrr >+ 72U, // VADDPDZrm >+ 560U, // VADDPDZrmb >+ 69898U, // VADDPDZrmbk >+ 69898U, // VADDPDZrmbkz >+ 6410U, // VADDPDZrmk >+ 6410U, // VADDPDZrmkz >+ 8U, // VADDPDZrr >+ 8458U, // VADDPDZrrk >+ 8458U, // VADDPDZrrkz >+ 80U, // VADDPDrm >+ 8U, // VADDPDrr >+ 64U, // VADDPSYrm >+ 8U, // VADDPSYrr >+ 72U, // VADDPSZrm >+ 824U, // VADDPSZrmb >+ 108810U, // VADDPSZrmbk >+ 108810U, // VADDPSZrmbkz >+ 6410U, // VADDPSZrmk >+ 6410U, // VADDPSZrmkz >+ 8U, // VADDPSZrr >+ 8458U, // VADDPSZrrk >+ 8458U, // VADDPSZrrkz >+ 80U, // VADDPSrm >+ 8U, // VADDPSrr >+ 48U, // VADDSDZrm >+ 8U, // VADDSDZrr >+ 48U, // VADDSDrm >+ 48U, // VADDSDrm_Int >+ 8U, // VADDSDrr >+ 8U, // VADDSDrr_Int >+ 56U, // VADDSSZrm >+ 8U, // VADDSSZrr >+ 56U, // VADDSSrm >+ 56U, // VADDSSrm_Int >+ 8U, // VADDSSrr >+ 8U, // VADDSSrr_Int >+ 64U, // VADDSUBPDYrm >+ 8U, // VADDSUBPDYrr >+ 80U, // VADDSUBPDrm >+ 8U, // VADDSUBPDrr >+ 64U, // VADDSUBPSYrm >+ 8U, // VADDSUBPSYrr >+ 80U, // VADDSUBPSrm >+ 8U, // VADDSUBPSrr >+ 88U, // VAESDECLASTrm >+ 8U, // VAESDECLASTrr >+ 88U, // VAESDECrm >+ 8U, // VAESDECrr >+ 88U, // VAESENCLASTrm >+ 8U, // VAESENCLASTrr >+ 88U, // VAESENCrm >+ 8U, // VAESENCrr >+ 0U, // VAESIMCrm >+ 0U, // VAESIMCrr >+ 0U, // VAESKEYGENASSIST128rm >+ 8U, // VAESKEYGENASSIST128rr >+ 2400U, // VALIGNDrmi >+ 8456U, // VALIGNDrri >+ 295210U, // VALIGNDrrik >+ 565514U, // VALIGNDrrikz >+ 2400U, // VALIGNQrmi >+ 8456U, // VALIGNQrri >+ 295210U, // VALIGNQrrik >+ 565514U, // VALIGNQrrikz >+ 64U, // VANDNPDYrm >+ 8U, // VANDNPDYrr >+ 80U, // VANDNPDrm >+ 8U, // VANDNPDrr >+ 64U, // VANDNPSYrm >+ 8U, // VANDNPSYrr >+ 80U, // VANDNPSrm >+ 8U, // VANDNPSrr >+ 64U, // VANDPDYrm >+ 8U, // VANDPDYrr >+ 80U, // VANDPDrm >+ 8U, // VANDPDrr >+ 64U, // VANDPSYrm >+ 8U, // VANDPSYrr >+ 80U, // VANDPSrm >+ 8U, // VANDPSrr >+ 8U, // VASTART_SAVE_XMM_REGS >+ 6410U, // VBLENDMPDZrm >+ 8458U, // VBLENDMPDZrr >+ 6410U, // VBLENDMPSZrm >+ 8458U, // VBLENDMPSZrr >+ 2368U, // VBLENDPDYrmi >+ 8456U, // VBLENDPDYrri >+ 2384U, // VBLENDPDrmi >+ 8456U, // VBLENDPDrri >+ 2368U, // VBLENDPSYrmi >+ 8456U, // VBLENDPSYrri >+ 2384U, // VBLENDPSrmi >+ 8456U, // VBLENDPSrri >+ 2368U, // VBLENDVPDYrm >+ 8456U, // VBLENDVPDYrr >+ 2384U, // VBLENDVPDrm >+ 8456U, // VBLENDVPDrr >+ 2368U, // VBLENDVPSYrm >+ 8456U, // VBLENDVPSYrr >+ 2384U, // VBLENDVPSrm >+ 8456U, // VBLENDVPSrr >+ 0U, // VBROADCASTF128 >+ 0U, // VBROADCASTI128 >+ 90U, // VBROADCASTI32X4krm >+ 0U, // VBROADCASTI32X4rm >+ 106U, // VBROADCASTI64X4krm >+ 0U, // VBROADCASTI64X4rm >+ 0U, // VBROADCASTSDYrm >+ 0U, // VBROADCASTSDYrr >+ 0U, // VBROADCASTSDZrm >+ 0U, // VBROADCASTSDZrr >+ 0U, // VBROADCASTSSYrm >+ 0U, // VBROADCASTSSYrr >+ 0U, // VBROADCASTSSZrm >+ 0U, // VBROADCASTSSZrr >+ 0U, // VBROADCASTSSrm >+ 0U, // VBROADCASTSSrr >+ 64U, // VCMPPDYrmi >+ 2368U, // VCMPPDYrmi_alt >+ 8U, // VCMPPDYrri >+ 8456U, // VCMPPDYrri_alt >+ 0U, // VCMPPDZrmi >+ 2376U, // VCMPPDZrmi_alt >+ 0U, // VCMPPDZrri >+ 8456U, // VCMPPDZrri_alt >+ 3U, // VCMPPDZrrib >+ 80U, // VCMPPDrmi >+ 2384U, // VCMPPDrmi_alt >+ 8U, // VCMPPDrri >+ 8456U, // VCMPPDrri_alt >+ 64U, // VCMPPSYrmi >+ 2368U, // VCMPPSYrmi_alt >+ 8U, // VCMPPSYrri >+ 8456U, // VCMPPSYrri_alt >+ 0U, // VCMPPSZrmi >+ 2376U, // VCMPPSZrmi_alt >+ 0U, // VCMPPSZrri >+ 8456U, // VCMPPSZrri_alt >+ 3U, // VCMPPSZrrib >+ 80U, // VCMPPSrmi >+ 2384U, // VCMPPSrmi_alt >+ 8U, // VCMPPSrri >+ 8456U, // VCMPPSrri_alt >+ 48U, // VCMPSDZrm >+ 2352U, // VCMPSDZrmi_alt >+ 8U, // VCMPSDZrr >+ 8456U, // VCMPSDZrri_alt >+ 48U, // VCMPSDrm >+ 2352U, // VCMPSDrm_alt >+ 8U, // VCMPSDrr >+ 8456U, // VCMPSDrr_alt >+ 56U, // VCMPSSZrm >+ 2360U, // VCMPSSZrmi_alt >+ 8U, // VCMPSSZrr >+ 8456U, // VCMPSSZrri_alt >+ 56U, // VCMPSSrm >+ 2360U, // VCMPSSrm_alt >+ 8U, // VCMPSSrr >+ 8456U, // VCMPSSrr_alt >+ 0U, // VCOMISDZrm >+ 0U, // VCOMISDZrr >+ 0U, // VCOMISDrm >+ 0U, // VCOMISDrr >+ 0U, // VCOMISSZrm >+ 0U, // VCOMISSZrr >+ 0U, // VCOMISSrm >+ 0U, // VCOMISSrr >+ 0U, // VCVTDQ2PDYrm >+ 0U, // VCVTDQ2PDYrr >+ 0U, // VCVTDQ2PDZrm >+ 0U, // VCVTDQ2PDZrr >+ 0U, // VCVTDQ2PDrm >+ 0U, // VCVTDQ2PDrr >+ 0U, // VCVTDQ2PSYrm >+ 0U, // VCVTDQ2PSYrr >+ 0U, // VCVTDQ2PSZrm >+ 0U, // VCVTDQ2PSZrr >+ 112U, // VCVTDQ2PSZrrb >+ 0U, // VCVTDQ2PSrm >+ 0U, // VCVTDQ2PSrr >+ 0U, // VCVTPD2DQXrm >+ 0U, // VCVTPD2DQYrm >+ 0U, // VCVTPD2DQYrr >+ 0U, // VCVTPD2DQZrm >+ 0U, // VCVTPD2DQZrr >+ 112U, // VCVTPD2DQZrrb >+ 0U, // VCVTPD2DQrr >+ 0U, // VCVTPD2PSXrm >+ 0U, // VCVTPD2PSYrm >+ 0U, // VCVTPD2PSYrr >+ 0U, // VCVTPD2PSZrm >+ 0U, // VCVTPD2PSZrr >+ 112U, // VCVTPD2PSZrrb >+ 0U, // VCVTPD2PSrr >+ 0U, // VCVTPD2UDQZrm >+ 0U, // VCVTPD2UDQZrr >+ 112U, // VCVTPD2UDQZrrb >+ 0U, // VCVTPH2PSYrm >+ 0U, // VCVTPH2PSYrr >+ 0U, // VCVTPH2PSZrm >+ 0U, // VCVTPH2PSZrr >+ 0U, // VCVTPH2PSrm >+ 0U, // VCVTPH2PSrr >+ 0U, // VCVTPS2DQYrm >+ 0U, // VCVTPS2DQYrr >+ 0U, // VCVTPS2DQZrm >+ 0U, // VCVTPS2DQZrr >+ 112U, // VCVTPS2DQZrrb >+ 0U, // VCVTPS2DQrm >+ 0U, // VCVTPS2DQrr >+ 0U, // VCVTPS2PDYrm >+ 0U, // VCVTPS2PDYrr >+ 0U, // VCVTPS2PDZrm >+ 0U, // VCVTPS2PDZrr >+ 0U, // VCVTPS2PDrm >+ 0U, // VCVTPS2PDrr >+ 0U, // VCVTPS2PHYmr >+ 8U, // VCVTPS2PHYrr >+ 0U, // VCVTPS2PHZmr >+ 8U, // VCVTPS2PHZrr >+ 0U, // VCVTPS2PHmr >+ 8U, // VCVTPS2PHrr >+ 0U, // VCVTPS2UDQZrm >+ 0U, // VCVTPS2UDQZrr >+ 112U, // VCVTPS2UDQZrrb >+ 0U, // VCVTSD2SI64Zrm >+ 0U, // VCVTSD2SI64Zrr >+ 0U, // VCVTSD2SI64rm >+ 0U, // VCVTSD2SI64rr >+ 0U, // VCVTSD2SIZrm >+ 0U, // VCVTSD2SIZrr >+ 0U, // VCVTSD2SIrm >+ 0U, // VCVTSD2SIrr >+ 48U, // VCVTSD2SSZrm >+ 8U, // VCVTSD2SSZrr >+ 48U, // VCVTSD2SSrm >+ 8U, // VCVTSD2SSrr >+ 0U, // VCVTSD2USI64Zrm >+ 0U, // VCVTSD2USI64Zrr >+ 0U, // VCVTSD2USIZrm >+ 0U, // VCVTSD2USIZrr >+ 24U, // VCVTSI2SD64rm >+ 8U, // VCVTSI2SD64rr >+ 16U, // VCVTSI2SDZrm >+ 8U, // VCVTSI2SDZrr >+ 16U, // VCVTSI2SDrm >+ 8U, // VCVTSI2SDrr >+ 24U, // VCVTSI2SS64rm >+ 8U, // VCVTSI2SS64rr >+ 16U, // VCVTSI2SSZrm >+ 8U, // VCVTSI2SSZrr >+ 16U, // VCVTSI2SSrm >+ 8U, // VCVTSI2SSrr >+ 24U, // VCVTSI642SDZrm >+ 8U, // VCVTSI642SDZrr >+ 24U, // VCVTSI642SSZrm >+ 8U, // VCVTSI642SSZrr >+ 56U, // VCVTSS2SDZrm >+ 8U, // VCVTSS2SDZrr >+ 56U, // VCVTSS2SDrm >+ 8U, // VCVTSS2SDrr >+ 0U, // VCVTSS2SI64Zrm >+ 0U, // VCVTSS2SI64Zrr >+ 0U, // VCVTSS2SI64rm >+ 0U, // VCVTSS2SI64rr >+ 0U, // VCVTSS2SIZrm >+ 0U, // VCVTSS2SIZrr >+ 0U, // VCVTSS2SIrm >+ 0U, // VCVTSS2SIrr >+ 0U, // VCVTSS2USI64Zrm >+ 0U, // VCVTSS2USI64Zrr >+ 0U, // VCVTSS2USIZrm >+ 0U, // VCVTSS2USIZrr >+ 0U, // VCVTTPD2DQXrm >+ 0U, // VCVTTPD2DQYrm >+ 0U, // VCVTTPD2DQYrr >+ 0U, // VCVTTPD2DQZrm >+ 0U, // VCVTTPD2DQZrr >+ 0U, // VCVTTPD2DQrr >+ 0U, // VCVTTPD2UDQZrm >+ 0U, // VCVTTPD2UDQZrr >+ 0U, // VCVTTPS2DQYrm >+ 0U, // VCVTTPS2DQYrr >+ 0U, // VCVTTPS2DQZrm >+ 0U, // VCVTTPS2DQZrr >+ 0U, // VCVTTPS2DQrm >+ 0U, // VCVTTPS2DQrr >+ 0U, // VCVTTPS2UDQZrm >+ 0U, // VCVTTPS2UDQZrr >+ 0U, // VCVTTSD2SI64Zrm >+ 0U, // VCVTTSD2SI64Zrr >+ 0U, // VCVTTSD2SI64rm >+ 0U, // VCVTTSD2SI64rr >+ 0U, // VCVTTSD2SIZrm >+ 0U, // VCVTTSD2SIZrr >+ 0U, // VCVTTSD2SIrm >+ 0U, // VCVTTSD2SIrr >+ 0U, // VCVTTSD2USI64Zrm >+ 0U, // VCVTTSD2USI64Zrr >+ 0U, // VCVTTSD2USIZrm >+ 0U, // VCVTTSD2USIZrr >+ 0U, // VCVTTSS2SI64Zrm >+ 0U, // VCVTTSS2SI64Zrr >+ 0U, // VCVTTSS2SI64rm >+ 0U, // VCVTTSS2SI64rr >+ 0U, // VCVTTSS2SIZrm >+ 0U, // VCVTTSS2SIZrr >+ 0U, // VCVTTSS2SIrm >+ 0U, // VCVTTSS2SIrr >+ 0U, // VCVTTSS2USI64Zrm >+ 0U, // VCVTTSS2USI64Zrr >+ 0U, // VCVTTSS2USIZrm >+ 0U, // VCVTTSS2USIZrr >+ 0U, // VCVTUDQ2PDZrm >+ 0U, // VCVTUDQ2PDZrr >+ 0U, // VCVTUDQ2PSZrm >+ 0U, // VCVTUDQ2PSZrr >+ 112U, // VCVTUDQ2PSZrrb >+ 16U, // VCVTUSI2SDZrm >+ 8U, // VCVTUSI2SDZrr >+ 16U, // VCVTUSI2SSZrm >+ 8U, // VCVTUSI2SSZrr >+ 24U, // VCVTUSI642SDZrm >+ 8U, // VCVTUSI642SDZrr >+ 24U, // VCVTUSI642SSZrm >+ 8U, // VCVTUSI642SSZrr >+ 64U, // VDIVPDYrm >+ 8U, // VDIVPDYrr >+ 72U, // VDIVPDZrm >+ 560U, // VDIVPDZrmb >+ 69898U, // VDIVPDZrmbk >+ 69898U, // VDIVPDZrmbkz >+ 6410U, // VDIVPDZrmk >+ 6410U, // VDIVPDZrmkz >+ 8U, // VDIVPDZrr >+ 8458U, // VDIVPDZrrk >+ 8458U, // VDIVPDZrrkz >+ 80U, // VDIVPDrm >+ 8U, // VDIVPDrr >+ 64U, // VDIVPSYrm >+ 8U, // VDIVPSYrr >+ 72U, // VDIVPSZrm >+ 824U, // VDIVPSZrmb >+ 108810U, // VDIVPSZrmbk >+ 108810U, // VDIVPSZrmbkz >+ 6410U, // VDIVPSZrmk >+ 6410U, // VDIVPSZrmkz >+ 8U, // VDIVPSZrr >+ 8458U, // VDIVPSZrrk >+ 8458U, // VDIVPSZrrkz >+ 80U, // VDIVPSrm >+ 8U, // VDIVPSrr >+ 48U, // VDIVSDZrm >+ 8U, // VDIVSDZrr >+ 48U, // VDIVSDrm >+ 48U, // VDIVSDrm_Int >+ 8U, // VDIVSDrr >+ 8U, // VDIVSDrr_Int >+ 56U, // VDIVSSZrm >+ 8U, // VDIVSSZrr >+ 56U, // VDIVSSrm >+ 56U, // VDIVSSrm_Int >+ 8U, // VDIVSSrr >+ 8U, // VDIVSSrr_Int >+ 2384U, // VDPPDrmi >+ 8456U, // VDPPDrri >+ 2408U, // VDPPSYrmi >+ 8456U, // VDPPSYrri >+ 2384U, // VDPPSrmi >+ 8456U, // VDPPSrri >+ 0U, // VERRm >+ 0U, // VERRr >+ 0U, // VERWm >+ 0U, // VERWr >+ 0U, // VEXTRACTF128mr >+ 8U, // VEXTRACTF128rr >+ 0U, // VEXTRACTF32x4mr >+ 8U, // VEXTRACTF32x4rr >+ 0U, // VEXTRACTF64x4mr >+ 8U, // VEXTRACTF64x4rr >+ 0U, // VEXTRACTI128mr >+ 8U, // VEXTRACTI128rr >+ 0U, // VEXTRACTI32x4mr >+ 8U, // VEXTRACTI32x4rr >+ 0U, // VEXTRACTI64x4mr >+ 8U, // VEXTRACTI64x4rr >+ 0U, // VEXTRACTPSmr >+ 8U, // VEXTRACTPSrr >+ 0U, // VEXTRACTPSzmr >+ 8U, // VEXTRACTPSzrr >+ 120U, // VFMADD132PDZm >+ 640U, // VFMADD132PDZmb >+ 120U, // VFMADD132PSZm >+ 904U, // VFMADD132PSZmb >+ 120U, // VFMADD213PDZm >+ 640U, // VFMADD213PDZmb >+ 40U, // VFMADD213PDZr >+ 298U, // VFMADD213PDZrk >+ 298U, // VFMADD213PDZrkz >+ 120U, // VFMADD213PSZm >+ 904U, // VFMADD213PSZmb >+ 40U, // VFMADD213PSZr >+ 298U, // VFMADD213PSZrk >+ 298U, // VFMADD213PSZrkz >+ 2384U, // VFMADDPD4mr >+ 2368U, // VFMADDPD4mrY >+ 12552U, // VFMADDPD4rm >+ 14600U, // VFMADDPD4rmY >+ 8456U, // VFMADDPD4rr >+ 8456U, // VFMADDPD4rrY >+ 8456U, // VFMADDPD4rrY_REV >+ 8456U, // VFMADDPD4rr_REV >+ 144U, // VFMADDPDr132m >+ 152U, // VFMADDPDr132mY >+ 40U, // VFMADDPDr132r >+ 40U, // VFMADDPDr132rY >+ 144U, // VFMADDPDr213m >+ 152U, // VFMADDPDr213mY >+ 40U, // VFMADDPDr213r >+ 40U, // VFMADDPDr213rY >+ 144U, // VFMADDPDr231m >+ 152U, // VFMADDPDr231mY >+ 40U, // VFMADDPDr231r >+ 40U, // VFMADDPDr231rY >+ 2384U, // VFMADDPS4mr >+ 2368U, // VFMADDPS4mrY >+ 12552U, // VFMADDPS4rm >+ 14600U, // VFMADDPS4rmY >+ 8456U, // VFMADDPS4rr >+ 8456U, // VFMADDPS4rrY >+ 8456U, // VFMADDPS4rrY_REV >+ 8456U, // VFMADDPS4rr_REV >+ 144U, // VFMADDPSr132m >+ 152U, // VFMADDPSr132mY >+ 40U, // VFMADDPSr132r >+ 40U, // VFMADDPSr132rY >+ 144U, // VFMADDPSr213m >+ 152U, // VFMADDPSr213mY >+ 40U, // VFMADDPSr213r >+ 40U, // VFMADDPSr213rY >+ 144U, // VFMADDPSr231m >+ 152U, // VFMADDPSr231mY >+ 40U, // VFMADDPSr231r >+ 40U, // VFMADDPSr231rY >+ 2352U, // VFMADDSD4mr >+ 2352U, // VFMADDSD4mr_Int >+ 4360U, // VFMADDSD4rm >+ 4360U, // VFMADDSD4rm_Int >+ 8456U, // VFMADDSD4rr >+ 8456U, // VFMADDSD4rr_Int >+ 8456U, // VFMADDSD4rr_REV >+ 144U, // VFMADDSDZm >+ 40U, // VFMADDSDZr >+ 128U, // VFMADDSDr132m >+ 40U, // VFMADDSDr132r >+ 128U, // VFMADDSDr213m >+ 40U, // VFMADDSDr213r >+ 128U, // VFMADDSDr231m >+ 40U, // VFMADDSDr231r >+ 2360U, // VFMADDSS4mr >+ 2360U, // VFMADDSS4mr_Int >+ 10504U, // VFMADDSS4rm >+ 10504U, // VFMADDSS4rm_Int >+ 8456U, // VFMADDSS4rr >+ 8456U, // VFMADDSS4rr_Int >+ 8456U, // VFMADDSS4rr_REV >+ 144U, // VFMADDSSZm >+ 40U, // VFMADDSSZr >+ 136U, // VFMADDSSr132m >+ 40U, // VFMADDSSr132r >+ 136U, // VFMADDSSr213m >+ 40U, // VFMADDSSr213r >+ 136U, // VFMADDSSr231m >+ 40U, // VFMADDSSr231r >+ 120U, // VFMADDSUB132PDZm >+ 640U, // VFMADDSUB132PDZmb >+ 120U, // VFMADDSUB132PSZm >+ 904U, // VFMADDSUB132PSZmb >+ 120U, // VFMADDSUB213PDZm >+ 640U, // VFMADDSUB213PDZmb >+ 40U, // VFMADDSUB213PDZr >+ 298U, // VFMADDSUB213PDZrk >+ 298U, // VFMADDSUB213PDZrkz >+ 120U, // VFMADDSUB213PSZm >+ 904U, // VFMADDSUB213PSZmb >+ 40U, // VFMADDSUB213PSZr >+ 298U, // VFMADDSUB213PSZrk >+ 298U, // VFMADDSUB213PSZrkz >+ 2384U, // VFMADDSUBPD4mr >+ 2368U, // VFMADDSUBPD4mrY >+ 12552U, // VFMADDSUBPD4rm >+ 14600U, // VFMADDSUBPD4rmY >+ 8456U, // VFMADDSUBPD4rr >+ 8456U, // VFMADDSUBPD4rrY >+ 8456U, // VFMADDSUBPD4rrY_REV >+ 8456U, // VFMADDSUBPD4rr_REV >+ 144U, // VFMADDSUBPDr132m >+ 152U, // VFMADDSUBPDr132mY >+ 40U, // VFMADDSUBPDr132r >+ 40U, // VFMADDSUBPDr132rY >+ 144U, // VFMADDSUBPDr213m >+ 152U, // VFMADDSUBPDr213mY >+ 40U, // VFMADDSUBPDr213r >+ 40U, // VFMADDSUBPDr213rY >+ 144U, // VFMADDSUBPDr231m >+ 152U, // VFMADDSUBPDr231mY >+ 40U, // VFMADDSUBPDr231r >+ 40U, // VFMADDSUBPDr231rY >+ 2384U, // VFMADDSUBPS4mr >+ 2368U, // VFMADDSUBPS4mrY >+ 12552U, // VFMADDSUBPS4rm >+ 14600U, // VFMADDSUBPS4rmY >+ 8456U, // VFMADDSUBPS4rr >+ 8456U, // VFMADDSUBPS4rrY >+ 8456U, // VFMADDSUBPS4rrY_REV >+ 8456U, // VFMADDSUBPS4rr_REV >+ 144U, // VFMADDSUBPSr132m >+ 152U, // VFMADDSUBPSr132mY >+ 40U, // VFMADDSUBPSr132r >+ 40U, // VFMADDSUBPSr132rY >+ 144U, // VFMADDSUBPSr213m >+ 152U, // VFMADDSUBPSr213mY >+ 40U, // VFMADDSUBPSr213r >+ 40U, // VFMADDSUBPSr213rY >+ 144U, // VFMADDSUBPSr231m >+ 152U, // VFMADDSUBPSr231mY >+ 40U, // VFMADDSUBPSr231r >+ 40U, // VFMADDSUBPSr231rY >+ 120U, // VFMSUB132PDZm >+ 640U, // VFMSUB132PDZmb >+ 120U, // VFMSUB132PSZm >+ 904U, // VFMSUB132PSZmb >+ 120U, // VFMSUB213PDZm >+ 640U, // VFMSUB213PDZmb >+ 40U, // VFMSUB213PDZr >+ 298U, // VFMSUB213PDZrk >+ 298U, // VFMSUB213PDZrkz >+ 120U, // VFMSUB213PSZm >+ 904U, // VFMSUB213PSZmb >+ 40U, // VFMSUB213PSZr >+ 298U, // VFMSUB213PSZrk >+ 298U, // VFMSUB213PSZrkz >+ 120U, // VFMSUBADD132PDZm >+ 640U, // VFMSUBADD132PDZmb >+ 120U, // VFMSUBADD132PSZm >+ 904U, // VFMSUBADD132PSZmb >+ 120U, // VFMSUBADD213PDZm >+ 640U, // VFMSUBADD213PDZmb >+ 40U, // VFMSUBADD213PDZr >+ 298U, // VFMSUBADD213PDZrk >+ 298U, // VFMSUBADD213PDZrkz >+ 120U, // VFMSUBADD213PSZm >+ 904U, // VFMSUBADD213PSZmb >+ 40U, // VFMSUBADD213PSZr >+ 298U, // VFMSUBADD213PSZrk >+ 298U, // VFMSUBADD213PSZrkz >+ 2384U, // VFMSUBADDPD4mr >+ 2368U, // VFMSUBADDPD4mrY >+ 12552U, // VFMSUBADDPD4rm >+ 14600U, // VFMSUBADDPD4rmY >+ 8456U, // VFMSUBADDPD4rr >+ 8456U, // VFMSUBADDPD4rrY >+ 8456U, // VFMSUBADDPD4rrY_REV >+ 8456U, // VFMSUBADDPD4rr_REV >+ 144U, // VFMSUBADDPDr132m >+ 152U, // VFMSUBADDPDr132mY >+ 40U, // VFMSUBADDPDr132r >+ 40U, // VFMSUBADDPDr132rY >+ 144U, // VFMSUBADDPDr213m >+ 152U, // VFMSUBADDPDr213mY >+ 40U, // VFMSUBADDPDr213r >+ 40U, // VFMSUBADDPDr213rY >+ 144U, // VFMSUBADDPDr231m >+ 152U, // VFMSUBADDPDr231mY >+ 40U, // VFMSUBADDPDr231r >+ 40U, // VFMSUBADDPDr231rY >+ 2384U, // VFMSUBADDPS4mr >+ 2368U, // VFMSUBADDPS4mrY >+ 12552U, // VFMSUBADDPS4rm >+ 14600U, // VFMSUBADDPS4rmY >+ 8456U, // VFMSUBADDPS4rr >+ 8456U, // VFMSUBADDPS4rrY >+ 8456U, // VFMSUBADDPS4rrY_REV >+ 8456U, // VFMSUBADDPS4rr_REV >+ 144U, // VFMSUBADDPSr132m >+ 152U, // VFMSUBADDPSr132mY >+ 40U, // VFMSUBADDPSr132r >+ 40U, // VFMSUBADDPSr132rY >+ 144U, // VFMSUBADDPSr213m >+ 152U, // VFMSUBADDPSr213mY >+ 40U, // VFMSUBADDPSr213r >+ 40U, // VFMSUBADDPSr213rY >+ 144U, // VFMSUBADDPSr231m >+ 152U, // VFMSUBADDPSr231mY >+ 40U, // VFMSUBADDPSr231r >+ 40U, // VFMSUBADDPSr231rY >+ 2384U, // VFMSUBPD4mr >+ 2368U, // VFMSUBPD4mrY >+ 12552U, // VFMSUBPD4rm >+ 14600U, // VFMSUBPD4rmY >+ 8456U, // VFMSUBPD4rr >+ 8456U, // VFMSUBPD4rrY >+ 8456U, // VFMSUBPD4rrY_REV >+ 8456U, // VFMSUBPD4rr_REV >+ 144U, // VFMSUBPDr132m >+ 152U, // VFMSUBPDr132mY >+ 40U, // VFMSUBPDr132r >+ 40U, // VFMSUBPDr132rY >+ 144U, // VFMSUBPDr213m >+ 152U, // VFMSUBPDr213mY >+ 40U, // VFMSUBPDr213r >+ 40U, // VFMSUBPDr213rY >+ 144U, // VFMSUBPDr231m >+ 152U, // VFMSUBPDr231mY >+ 40U, // VFMSUBPDr231r >+ 40U, // VFMSUBPDr231rY >+ 2384U, // VFMSUBPS4mr >+ 2368U, // VFMSUBPS4mrY >+ 12552U, // VFMSUBPS4rm >+ 14600U, // VFMSUBPS4rmY >+ 8456U, // VFMSUBPS4rr >+ 8456U, // VFMSUBPS4rrY >+ 8456U, // VFMSUBPS4rrY_REV >+ 8456U, // VFMSUBPS4rr_REV >+ 144U, // VFMSUBPSr132m >+ 152U, // VFMSUBPSr132mY >+ 40U, // VFMSUBPSr132r >+ 40U, // VFMSUBPSr132rY >+ 144U, // VFMSUBPSr213m >+ 152U, // VFMSUBPSr213mY >+ 40U, // VFMSUBPSr213r >+ 40U, // VFMSUBPSr213rY >+ 144U, // VFMSUBPSr231m >+ 152U, // VFMSUBPSr231mY >+ 40U, // VFMSUBPSr231r >+ 40U, // VFMSUBPSr231rY >+ 2352U, // VFMSUBSD4mr >+ 2352U, // VFMSUBSD4mr_Int >+ 4360U, // VFMSUBSD4rm >+ 4360U, // VFMSUBSD4rm_Int >+ 8456U, // VFMSUBSD4rr >+ 8456U, // VFMSUBSD4rr_Int >+ 8456U, // VFMSUBSD4rr_REV >+ 144U, // VFMSUBSDZm >+ 40U, // VFMSUBSDZr >+ 128U, // VFMSUBSDr132m >+ 40U, // VFMSUBSDr132r >+ 128U, // VFMSUBSDr213m >+ 40U, // VFMSUBSDr213r >+ 128U, // VFMSUBSDr231m >+ 40U, // VFMSUBSDr231r >+ 2360U, // VFMSUBSS4mr >+ 2360U, // VFMSUBSS4mr_Int >+ 10504U, // VFMSUBSS4rm >+ 10504U, // VFMSUBSS4rm_Int >+ 8456U, // VFMSUBSS4rr >+ 8456U, // VFMSUBSS4rr_Int >+ 8456U, // VFMSUBSS4rr_REV >+ 144U, // VFMSUBSSZm >+ 40U, // VFMSUBSSZr >+ 136U, // VFMSUBSSr132m >+ 40U, // VFMSUBSSr132r >+ 136U, // VFMSUBSSr213m >+ 40U, // VFMSUBSSr213r >+ 136U, // VFMSUBSSr231m >+ 40U, // VFMSUBSSr231r >+ 120U, // VFNMADD132PDZm >+ 640U, // VFNMADD132PDZmb >+ 120U, // VFNMADD132PSZm >+ 904U, // VFNMADD132PSZmb >+ 120U, // VFNMADD213PDZm >+ 640U, // VFNMADD213PDZmb >+ 40U, // VFNMADD213PDZr >+ 298U, // VFNMADD213PDZrk >+ 298U, // VFNMADD213PDZrkz >+ 120U, // VFNMADD213PSZm >+ 904U, // VFNMADD213PSZmb >+ 40U, // VFNMADD213PSZr >+ 298U, // VFNMADD213PSZrk >+ 298U, // VFNMADD213PSZrkz >+ 2384U, // VFNMADDPD4mr >+ 2368U, // VFNMADDPD4mrY >+ 12552U, // VFNMADDPD4rm >+ 14600U, // VFNMADDPD4rmY >+ 8456U, // VFNMADDPD4rr >+ 8456U, // VFNMADDPD4rrY >+ 8456U, // VFNMADDPD4rrY_REV >+ 8456U, // VFNMADDPD4rr_REV >+ 144U, // VFNMADDPDr132m >+ 152U, // VFNMADDPDr132mY >+ 40U, // VFNMADDPDr132r >+ 40U, // VFNMADDPDr132rY >+ 144U, // VFNMADDPDr213m >+ 152U, // VFNMADDPDr213mY >+ 40U, // VFNMADDPDr213r >+ 40U, // VFNMADDPDr213rY >+ 144U, // VFNMADDPDr231m >+ 152U, // VFNMADDPDr231mY >+ 40U, // VFNMADDPDr231r >+ 40U, // VFNMADDPDr231rY >+ 2384U, // VFNMADDPS4mr >+ 2368U, // VFNMADDPS4mrY >+ 12552U, // VFNMADDPS4rm >+ 14600U, // VFNMADDPS4rmY >+ 8456U, // VFNMADDPS4rr >+ 8456U, // VFNMADDPS4rrY >+ 8456U, // VFNMADDPS4rrY_REV >+ 8456U, // VFNMADDPS4rr_REV >+ 144U, // VFNMADDPSr132m >+ 152U, // VFNMADDPSr132mY >+ 40U, // VFNMADDPSr132r >+ 40U, // VFNMADDPSr132rY >+ 144U, // VFNMADDPSr213m >+ 152U, // VFNMADDPSr213mY >+ 40U, // VFNMADDPSr213r >+ 40U, // VFNMADDPSr213rY >+ 144U, // VFNMADDPSr231m >+ 152U, // VFNMADDPSr231mY >+ 40U, // VFNMADDPSr231r >+ 40U, // VFNMADDPSr231rY >+ 2352U, // VFNMADDSD4mr >+ 2352U, // VFNMADDSD4mr_Int >+ 4360U, // VFNMADDSD4rm >+ 4360U, // VFNMADDSD4rm_Int >+ 8456U, // VFNMADDSD4rr >+ 8456U, // VFNMADDSD4rr_Int >+ 8456U, // VFNMADDSD4rr_REV >+ 144U, // VFNMADDSDZm >+ 40U, // VFNMADDSDZr >+ 128U, // VFNMADDSDr132m >+ 40U, // VFNMADDSDr132r >+ 128U, // VFNMADDSDr213m >+ 40U, // VFNMADDSDr213r >+ 128U, // VFNMADDSDr231m >+ 40U, // VFNMADDSDr231r >+ 2360U, // VFNMADDSS4mr >+ 2360U, // VFNMADDSS4mr_Int >+ 10504U, // VFNMADDSS4rm >+ 10504U, // VFNMADDSS4rm_Int >+ 8456U, // VFNMADDSS4rr >+ 8456U, // VFNMADDSS4rr_Int >+ 8456U, // VFNMADDSS4rr_REV >+ 144U, // VFNMADDSSZm >+ 40U, // VFNMADDSSZr >+ 136U, // VFNMADDSSr132m >+ 40U, // VFNMADDSSr132r >+ 136U, // VFNMADDSSr213m >+ 40U, // VFNMADDSSr213r >+ 136U, // VFNMADDSSr231m >+ 40U, // VFNMADDSSr231r >+ 120U, // VFNMSUB132PDZm >+ 640U, // VFNMSUB132PDZmb >+ 120U, // VFNMSUB132PSZm >+ 904U, // VFNMSUB132PSZmb >+ 120U, // VFNMSUB213PDZm >+ 640U, // VFNMSUB213PDZmb >+ 40U, // VFNMSUB213PDZr >+ 298U, // VFNMSUB213PDZrk >+ 298U, // VFNMSUB213PDZrkz >+ 120U, // VFNMSUB213PSZm >+ 904U, // VFNMSUB213PSZmb >+ 40U, // VFNMSUB213PSZr >+ 298U, // VFNMSUB213PSZrk >+ 298U, // VFNMSUB213PSZrkz >+ 2384U, // VFNMSUBPD4mr >+ 2368U, // VFNMSUBPD4mrY >+ 12552U, // VFNMSUBPD4rm >+ 14600U, // VFNMSUBPD4rmY >+ 8456U, // VFNMSUBPD4rr >+ 8456U, // VFNMSUBPD4rrY >+ 8456U, // VFNMSUBPD4rrY_REV >+ 8456U, // VFNMSUBPD4rr_REV >+ 144U, // VFNMSUBPDr132m >+ 152U, // VFNMSUBPDr132mY >+ 40U, // VFNMSUBPDr132r >+ 40U, // VFNMSUBPDr132rY >+ 144U, // VFNMSUBPDr213m >+ 152U, // VFNMSUBPDr213mY >+ 40U, // VFNMSUBPDr213r >+ 40U, // VFNMSUBPDr213rY >+ 144U, // VFNMSUBPDr231m >+ 152U, // VFNMSUBPDr231mY >+ 40U, // VFNMSUBPDr231r >+ 40U, // VFNMSUBPDr231rY >+ 2384U, // VFNMSUBPS4mr >+ 2368U, // VFNMSUBPS4mrY >+ 12552U, // VFNMSUBPS4rm >+ 14600U, // VFNMSUBPS4rmY >+ 8456U, // VFNMSUBPS4rr >+ 8456U, // VFNMSUBPS4rrY >+ 8456U, // VFNMSUBPS4rrY_REV >+ 8456U, // VFNMSUBPS4rr_REV >+ 144U, // VFNMSUBPSr132m >+ 152U, // VFNMSUBPSr132mY >+ 40U, // VFNMSUBPSr132r >+ 40U, // VFNMSUBPSr132rY >+ 144U, // VFNMSUBPSr213m >+ 152U, // VFNMSUBPSr213mY >+ 40U, // VFNMSUBPSr213r >+ 40U, // VFNMSUBPSr213rY >+ 144U, // VFNMSUBPSr231m >+ 152U, // VFNMSUBPSr231mY >+ 40U, // VFNMSUBPSr231r >+ 40U, // VFNMSUBPSr231rY >+ 2352U, // VFNMSUBSD4mr >+ 2352U, // VFNMSUBSD4mr_Int >+ 4360U, // VFNMSUBSD4rm >+ 4360U, // VFNMSUBSD4rm_Int >+ 8456U, // VFNMSUBSD4rr >+ 8456U, // VFNMSUBSD4rr_Int >+ 8456U, // VFNMSUBSD4rr_REV >+ 144U, // VFNMSUBSDZm >+ 40U, // VFNMSUBSDZr >+ 128U, // VFNMSUBSDr132m >+ 40U, // VFNMSUBSDr132r >+ 128U, // VFNMSUBSDr213m >+ 40U, // VFNMSUBSDr213r >+ 128U, // VFNMSUBSDr231m >+ 40U, // VFNMSUBSDr231r >+ 2360U, // VFNMSUBSS4mr >+ 2360U, // VFNMSUBSS4mr_Int >+ 10504U, // VFNMSUBSS4rm >+ 10504U, // VFNMSUBSS4rm_Int >+ 8456U, // VFNMSUBSS4rr >+ 8456U, // VFNMSUBSS4rr_Int >+ 8456U, // VFNMSUBSS4rr_REV >+ 144U, // VFNMSUBSSZm >+ 40U, // VFNMSUBSSZr >+ 136U, // VFNMSUBSSr132m >+ 40U, // VFNMSUBSSr132r >+ 136U, // VFNMSUBSSr213m >+ 40U, // VFNMSUBSSr213r >+ 136U, // VFNMSUBSSr231m >+ 40U, // VFNMSUBSSr231r >+ 0U, // VFRCZPDrm >+ 0U, // VFRCZPDrmY >+ 0U, // VFRCZPDrr >+ 0U, // VFRCZPDrrY >+ 0U, // VFRCZPSrm >+ 0U, // VFRCZPSrmY >+ 0U, // VFRCZPSrr >+ 0U, // VFRCZPSrrY >+ 0U, // VFRCZSDrm >+ 0U, // VFRCZSDrr >+ 0U, // VFRCZSSrm >+ 0U, // VFRCZSSrr >+ 80U, // VFsANDNPDrm >+ 8U, // VFsANDNPDrr >+ 80U, // VFsANDNPSrm >+ 8U, // VFsANDNPSrr >+ 80U, // VFsANDPDrm >+ 8U, // VFsANDPDrr >+ 80U, // VFsANDPSrm >+ 8U, // VFsANDPSrr >+ 80U, // VFsORPDrm >+ 8U, // VFsORPDrr >+ 80U, // VFsORPSrm >+ 8U, // VFsORPSrr >+ 80U, // VFsXORPDrm >+ 8U, // VFsXORPDrr >+ 80U, // VFsXORPSrm >+ 8U, // VFsXORPSrr >+ 0U, // VGATHERDPDYrm >+ 3U, // VGATHERDPDZrm >+ 0U, // VGATHERDPDrm >+ 0U, // VGATHERDPSYrm >+ 4U, // VGATHERDPSZrm >+ 0U, // VGATHERDPSrm >+ 0U, // VGATHERPF0DPDm >+ 0U, // VGATHERPF0DPSm >+ 0U, // VGATHERPF0QPDm >+ 0U, // VGATHERPF0QPSm >+ 0U, // VGATHERPF1DPDm >+ 0U, // VGATHERPF1DPSm >+ 0U, // VGATHERPF1QPDm >+ 0U, // VGATHERPF1QPSm >+ 0U, // VGATHERQPDYrm >+ 3U, // VGATHERQPDZrm >+ 0U, // VGATHERQPDrm >+ 0U, // VGATHERQPSYrm >+ 3U, // VGATHERQPSZrm >+ 0U, // VGATHERQPSrm >+ 64U, // VHADDPDYrm >+ 8U, // VHADDPDYrr >+ 80U, // VHADDPDrm >+ 8U, // VHADDPDrr >+ 64U, // VHADDPSYrm >+ 8U, // VHADDPSYrr >+ 80U, // VHADDPSrm >+ 8U, // VHADDPSrr >+ 64U, // VHSUBPDYrm >+ 8U, // VHSUBPDYrr >+ 80U, // VHSUBPDrm >+ 8U, // VHSUBPDrr >+ 64U, // VHSUBPSYrm >+ 8U, // VHSUBPSYrr >+ 80U, // VHSUBPSrm >+ 8U, // VHSUBPSrr >+ 2384U, // VINSERTF128rm >+ 8456U, // VINSERTF128rr >+ 2384U, // VINSERTF32x4rm >+ 8456U, // VINSERTF32x4rr >+ 2408U, // VINSERTF64x4rm >+ 8456U, // VINSERTF64x4rr >+ 2392U, // VINSERTI128rm >+ 8456U, // VINSERTI128rr >+ 2392U, // VINSERTI32x4rm >+ 8456U, // VINSERTI32x4rr >+ 2408U, // VINSERTI64x4rm >+ 8456U, // VINSERTI64x4rr >+ 2360U, // VINSERTPSrm >+ 8456U, // VINSERTPSrr >+ 2360U, // VINSERTPSzrm >+ 8456U, // VINSERTPSzrr >+ 0U, // VLDDQUYrm >+ 0U, // VLDDQUrm >+ 0U, // VLDMXCSR >+ 0U, // VMASKMOVDQU >+ 0U, // VMASKMOVDQU64 >+ 0U, // VMASKMOVPDYmr >+ 64U, // VMASKMOVPDYrm >+ 0U, // VMASKMOVPDmr >+ 80U, // VMASKMOVPDrm >+ 0U, // VMASKMOVPSYmr >+ 64U, // VMASKMOVPSYrm >+ 0U, // VMASKMOVPSmr >+ 80U, // VMASKMOVPSrm >+ 64U, // VMAXCPDYrm >+ 8U, // VMAXCPDYrr >+ 80U, // VMAXCPDrm >+ 8U, // VMAXCPDrr >+ 64U, // VMAXCPSYrm >+ 8U, // VMAXCPSYrr >+ 80U, // VMAXCPSrm >+ 8U, // VMAXCPSrr >+ 48U, // VMAXCSDrm >+ 8U, // VMAXCSDrr >+ 56U, // VMAXCSSrm >+ 8U, // VMAXCSSrr >+ 64U, // VMAXPDYrm >+ 8U, // VMAXPDYrr >+ 72U, // VMAXPDZrm >+ 560U, // VMAXPDZrmb >+ 69898U, // VMAXPDZrmbk >+ 69898U, // VMAXPDZrmbkz >+ 6410U, // VMAXPDZrmk >+ 6410U, // VMAXPDZrmkz >+ 8U, // VMAXPDZrr >+ 8458U, // VMAXPDZrrk >+ 8458U, // VMAXPDZrrkz >+ 80U, // VMAXPDrm >+ 8U, // VMAXPDrr >+ 64U, // VMAXPSYrm >+ 8U, // VMAXPSYrr >+ 72U, // VMAXPSZrm >+ 824U, // VMAXPSZrmb >+ 108810U, // VMAXPSZrmbk >+ 108810U, // VMAXPSZrmbkz >+ 6410U, // VMAXPSZrmk >+ 6410U, // VMAXPSZrmkz >+ 8U, // VMAXPSZrr >+ 8458U, // VMAXPSZrrk >+ 8458U, // VMAXPSZrrkz >+ 80U, // VMAXPSrm >+ 8U, // VMAXPSrr >+ 48U, // VMAXSDZrm >+ 8U, // VMAXSDZrr >+ 48U, // VMAXSDrm >+ 48U, // VMAXSDrm_Int >+ 8U, // VMAXSDrr >+ 8U, // VMAXSDrr_Int >+ 56U, // VMAXSSZrm >+ 8U, // VMAXSSZrr >+ 56U, // VMAXSSrm >+ 56U, // VMAXSSrm_Int >+ 8U, // VMAXSSrr >+ 8U, // VMAXSSrr_Int >+ 0U, // VMCALL >+ 0U, // VMCLEARm >+ 0U, // VMFUNC >+ 64U, // VMINCPDYrm >+ 8U, // VMINCPDYrr >+ 80U, // VMINCPDrm >+ 8U, // VMINCPDrr >+ 64U, // VMINCPSYrm >+ 8U, // VMINCPSYrr >+ 80U, // VMINCPSrm >+ 8U, // VMINCPSrr >+ 48U, // VMINCSDrm >+ 8U, // VMINCSDrr >+ 56U, // VMINCSSrm >+ 8U, // VMINCSSrr >+ 64U, // VMINPDYrm >+ 8U, // VMINPDYrr >+ 72U, // VMINPDZrm >+ 560U, // VMINPDZrmb >+ 69898U, // VMINPDZrmbk >+ 69898U, // VMINPDZrmbkz >+ 6410U, // VMINPDZrmk >+ 6410U, // VMINPDZrmkz >+ 8U, // VMINPDZrr >+ 8458U, // VMINPDZrrk >+ 8458U, // VMINPDZrrkz >+ 80U, // VMINPDrm >+ 8U, // VMINPDrr >+ 64U, // VMINPSYrm >+ 8U, // VMINPSYrr >+ 72U, // VMINPSZrm >+ 824U, // VMINPSZrmb >+ 108810U, // VMINPSZrmbk >+ 108810U, // VMINPSZrmbkz >+ 6410U, // VMINPSZrmk >+ 6410U, // VMINPSZrmkz >+ 8U, // VMINPSZrr >+ 8458U, // VMINPSZrrk >+ 8458U, // VMINPSZrrkz >+ 80U, // VMINPSrm >+ 8U, // VMINPSrr >+ 48U, // VMINSDZrm >+ 8U, // VMINSDZrr >+ 48U, // VMINSDrm >+ 48U, // VMINSDrm_Int >+ 8U, // VMINSDrr >+ 8U, // VMINSDrr_Int >+ 56U, // VMINSSZrm >+ 8U, // VMINSSZrr >+ 56U, // VMINSSrm >+ 56U, // VMINSSrm_Int >+ 8U, // VMINSSrr >+ 8U, // VMINSSrr_Int >+ 0U, // VMLAUNCH >+ 0U, // VMLOAD32 >+ 0U, // VMLOAD64 >+ 0U, // VMMCALL >+ 0U, // VMOV64toPQIZrr >+ 0U, // VMOV64toPQIrr >+ 0U, // VMOV64toSDZrr >+ 0U, // VMOV64toSDrm >+ 0U, // VMOV64toSDrr >+ 0U, // VMOVAPDYmr >+ 0U, // VMOVAPDYrm >+ 0U, // VMOVAPDYrr >+ 0U, // VMOVAPDYrr_REV >+ 0U, // VMOVAPDZ128mr >+ 2U, // VMOVAPDZ128mrk >+ 0U, // VMOVAPDZ128rm >+ 146U, // VMOVAPDZ128rmk >+ 82U, // VMOVAPDZ128rmkz >+ 0U, // VMOVAPDZ128rr >+ 0U, // VMOVAPDZ128rr_alt >+ 42U, // VMOVAPDZ128rrk >+ 42U, // VMOVAPDZ128rrk_alt >+ 10U, // VMOVAPDZ128rrkz >+ 10U, // VMOVAPDZ128rrkz_alt >+ 0U, // VMOVAPDZ256mr >+ 2U, // VMOVAPDZ256mrk >+ 0U, // VMOVAPDZ256rm >+ 154U, // VMOVAPDZ256rmk >+ 66U, // VMOVAPDZ256rmkz >+ 0U, // VMOVAPDZ256rr >+ 0U, // VMOVAPDZ256rr_alt >+ 42U, // VMOVAPDZ256rrk >+ 42U, // VMOVAPDZ256rrk_alt >+ 10U, // VMOVAPDZ256rrkz >+ 10U, // VMOVAPDZ256rrkz_alt >+ 0U, // VMOVAPDZmr >+ 2U, // VMOVAPDZmrk >+ 0U, // VMOVAPDZrm >+ 122U, // VMOVAPDZrmk >+ 74U, // VMOVAPDZrmkz >+ 0U, // VMOVAPDZrr >+ 0U, // VMOVAPDZrr_alt >+ 42U, // VMOVAPDZrrk >+ 42U, // VMOVAPDZrrk_alt >+ 10U, // VMOVAPDZrrkz >+ 10U, // VMOVAPDZrrkz_alt >+ 0U, // VMOVAPDmr >+ 0U, // VMOVAPDrm >+ 0U, // VMOVAPDrr >+ 0U, // VMOVAPDrr_REV >+ 0U, // VMOVAPSYmr >+ 0U, // VMOVAPSYrm >+ 0U, // VMOVAPSYrr >+ 0U, // VMOVAPSYrr_REV >+ 0U, // VMOVAPSZ128mr >+ 2U, // VMOVAPSZ128mrk >+ 0U, // VMOVAPSZ128rm >+ 146U, // VMOVAPSZ128rmk >+ 82U, // VMOVAPSZ128rmkz >+ 0U, // VMOVAPSZ128rr >+ 0U, // VMOVAPSZ128rr_alt >+ 42U, // VMOVAPSZ128rrk >+ 42U, // VMOVAPSZ128rrk_alt >+ 10U, // VMOVAPSZ128rrkz >+ 10U, // VMOVAPSZ128rrkz_alt >+ 0U, // VMOVAPSZ256mr >+ 2U, // VMOVAPSZ256mrk >+ 0U, // VMOVAPSZ256rm >+ 154U, // VMOVAPSZ256rmk >+ 66U, // VMOVAPSZ256rmkz >+ 0U, // VMOVAPSZ256rr >+ 0U, // VMOVAPSZ256rr_alt >+ 42U, // VMOVAPSZ256rrk >+ 42U, // VMOVAPSZ256rrk_alt >+ 10U, // VMOVAPSZ256rrkz >+ 10U, // VMOVAPSZ256rrkz_alt >+ 0U, // VMOVAPSZmr >+ 2U, // VMOVAPSZmrk >+ 0U, // VMOVAPSZrm >+ 122U, // VMOVAPSZrmk >+ 74U, // VMOVAPSZrmkz >+ 0U, // VMOVAPSZrr >+ 0U, // VMOVAPSZrr_alt >+ 42U, // VMOVAPSZrrk >+ 42U, // VMOVAPSZrrk_alt >+ 10U, // VMOVAPSZrrkz >+ 10U, // VMOVAPSZrrkz_alt >+ 0U, // VMOVAPSmr >+ 0U, // VMOVAPSrm >+ 0U, // VMOVAPSrr >+ 0U, // VMOVAPSrr_REV >+ 0U, // VMOVDDUPYrm >+ 0U, // VMOVDDUPYrr >+ 0U, // VMOVDDUPZrm >+ 0U, // VMOVDDUPZrr >+ 0U, // VMOVDDUPrm >+ 0U, // VMOVDDUPrr >+ 0U, // VMOVDI2PDIZrm >+ 0U, // VMOVDI2PDIZrr >+ 0U, // VMOVDI2PDIrm >+ 0U, // VMOVDI2PDIrr >+ 0U, // VMOVDI2SSZrm >+ 0U, // VMOVDI2SSZrr >+ 0U, // VMOVDI2SSrm >+ 0U, // VMOVDI2SSrr >+ 0U, // VMOVDQA32Z128mr >+ 2U, // VMOVDQA32Z128mrk >+ 0U, // VMOVDQA32Z128rm >+ 162U, // VMOVDQA32Z128rmk >+ 90U, // VMOVDQA32Z128rmkz >+ 0U, // VMOVDQA32Z128rr >+ 0U, // VMOVDQA32Z128rr_alt >+ 42U, // VMOVDQA32Z128rrk >+ 42U, // VMOVDQA32Z128rrk_alt >+ 10U, // VMOVDQA32Z128rrkz >+ 10U, // VMOVDQA32Z128rrkz_alt >+ 0U, // VMOVDQA32Z256mr >+ 2U, // VMOVDQA32Z256mrk >+ 0U, // VMOVDQA32Z256rm >+ 170U, // VMOVDQA32Z256rmk >+ 106U, // VMOVDQA32Z256rmkz >+ 0U, // VMOVDQA32Z256rr >+ 0U, // VMOVDQA32Z256rr_alt >+ 42U, // VMOVDQA32Z256rrk >+ 42U, // VMOVDQA32Z256rrk_alt >+ 10U, // VMOVDQA32Z256rrkz >+ 10U, // VMOVDQA32Z256rrkz_alt >+ 0U, // VMOVDQA32Zmr >+ 2U, // VMOVDQA32Zmrk >+ 0U, // VMOVDQA32Zrm >+ 178U, // VMOVDQA32Zrmk >+ 98U, // VMOVDQA32Zrmkz >+ 0U, // VMOVDQA32Zrr >+ 0U, // VMOVDQA32Zrr_alt >+ 42U, // VMOVDQA32Zrrk >+ 42U, // VMOVDQA32Zrrk_alt >+ 10U, // VMOVDQA32Zrrkz >+ 10U, // VMOVDQA32Zrrkz_alt >+ 0U, // VMOVDQA64Z128mr >+ 2U, // VMOVDQA64Z128mrk >+ 0U, // VMOVDQA64Z128rm >+ 162U, // VMOVDQA64Z128rmk >+ 90U, // VMOVDQA64Z128rmkz >+ 0U, // VMOVDQA64Z128rr >+ 0U, // VMOVDQA64Z128rr_alt >+ 42U, // VMOVDQA64Z128rrk >+ 42U, // VMOVDQA64Z128rrk_alt >+ 10U, // VMOVDQA64Z128rrkz >+ 10U, // VMOVDQA64Z128rrkz_alt >+ 0U, // VMOVDQA64Z256mr >+ 2U, // VMOVDQA64Z256mrk >+ 0U, // VMOVDQA64Z256rm >+ 170U, // VMOVDQA64Z256rmk >+ 106U, // VMOVDQA64Z256rmkz >+ 0U, // VMOVDQA64Z256rr >+ 0U, // VMOVDQA64Z256rr_alt >+ 42U, // VMOVDQA64Z256rrk >+ 42U, // VMOVDQA64Z256rrk_alt >+ 10U, // VMOVDQA64Z256rrkz >+ 10U, // VMOVDQA64Z256rrkz_alt >+ 0U, // VMOVDQA64Zmr >+ 2U, // VMOVDQA64Zmrk >+ 0U, // VMOVDQA64Zrm >+ 178U, // VMOVDQA64Zrmk >+ 98U, // VMOVDQA64Zrmkz >+ 0U, // VMOVDQA64Zrr >+ 0U, // VMOVDQA64Zrr_alt >+ 42U, // VMOVDQA64Zrrk >+ 42U, // VMOVDQA64Zrrk_alt >+ 10U, // VMOVDQA64Zrrkz >+ 10U, // VMOVDQA64Zrrkz_alt >+ 0U, // VMOVDQAYmr >+ 0U, // VMOVDQAYrm >+ 0U, // VMOVDQAYrr >+ 0U, // VMOVDQAYrr_REV >+ 0U, // VMOVDQAmr >+ 0U, // VMOVDQArm >+ 0U, // VMOVDQArr >+ 0U, // VMOVDQArr_REV >+ 0U, // VMOVDQU16Z128mr >+ 2U, // VMOVDQU16Z128mrk >+ 0U, // VMOVDQU16Z128rm >+ 162U, // VMOVDQU16Z128rmk >+ 90U, // VMOVDQU16Z128rmkz >+ 0U, // VMOVDQU16Z128rr >+ 0U, // VMOVDQU16Z128rr_alt >+ 42U, // VMOVDQU16Z128rrk >+ 42U, // VMOVDQU16Z128rrk_alt >+ 10U, // VMOVDQU16Z128rrkz >+ 10U, // VMOVDQU16Z128rrkz_alt >+ 0U, // VMOVDQU16Z256mr >+ 2U, // VMOVDQU16Z256mrk >+ 0U, // VMOVDQU16Z256rm >+ 170U, // VMOVDQU16Z256rmk >+ 106U, // VMOVDQU16Z256rmkz >+ 0U, // VMOVDQU16Z256rr >+ 0U, // VMOVDQU16Z256rr_alt >+ 42U, // VMOVDQU16Z256rrk >+ 42U, // VMOVDQU16Z256rrk_alt >+ 10U, // VMOVDQU16Z256rrkz >+ 10U, // VMOVDQU16Z256rrkz_alt >+ 0U, // VMOVDQU16Zmr >+ 2U, // VMOVDQU16Zmrk >+ 0U, // VMOVDQU16Zrm >+ 178U, // VMOVDQU16Zrmk >+ 98U, // VMOVDQU16Zrmkz >+ 0U, // VMOVDQU16Zrr >+ 0U, // VMOVDQU16Zrr_alt >+ 42U, // VMOVDQU16Zrrk >+ 42U, // VMOVDQU16Zrrk_alt >+ 10U, // VMOVDQU16Zrrkz >+ 10U, // VMOVDQU16Zrrkz_alt >+ 0U, // VMOVDQU32Z128mr >+ 2U, // VMOVDQU32Z128mrk >+ 0U, // VMOVDQU32Z128rm >+ 162U, // VMOVDQU32Z128rmk >+ 90U, // VMOVDQU32Z128rmkz >+ 0U, // VMOVDQU32Z128rr >+ 0U, // VMOVDQU32Z128rr_alt >+ 42U, // VMOVDQU32Z128rrk >+ 42U, // VMOVDQU32Z128rrk_alt >+ 10U, // VMOVDQU32Z128rrkz >+ 10U, // VMOVDQU32Z128rrkz_alt >+ 0U, // VMOVDQU32Z256mr >+ 2U, // VMOVDQU32Z256mrk >+ 0U, // VMOVDQU32Z256rm >+ 170U, // VMOVDQU32Z256rmk >+ 106U, // VMOVDQU32Z256rmkz >+ 0U, // VMOVDQU32Z256rr >+ 0U, // VMOVDQU32Z256rr_alt >+ 42U, // VMOVDQU32Z256rrk >+ 42U, // VMOVDQU32Z256rrk_alt >+ 10U, // VMOVDQU32Z256rrkz >+ 10U, // VMOVDQU32Z256rrkz_alt >+ 0U, // VMOVDQU32Zmr >+ 2U, // VMOVDQU32Zmrk >+ 0U, // VMOVDQU32Zrm >+ 178U, // VMOVDQU32Zrmk >+ 98U, // VMOVDQU32Zrmkz >+ 0U, // VMOVDQU32Zrr >+ 0U, // VMOVDQU32Zrr_alt >+ 42U, // VMOVDQU32Zrrk >+ 42U, // VMOVDQU32Zrrk_alt >+ 10U, // VMOVDQU32Zrrkz >+ 10U, // VMOVDQU32Zrrkz_alt >+ 0U, // VMOVDQU64Z128mr >+ 2U, // VMOVDQU64Z128mrk >+ 0U, // VMOVDQU64Z128rm >+ 162U, // VMOVDQU64Z128rmk >+ 90U, // VMOVDQU64Z128rmkz >+ 0U, // VMOVDQU64Z128rr >+ 0U, // VMOVDQU64Z128rr_alt >+ 42U, // VMOVDQU64Z128rrk >+ 42U, // VMOVDQU64Z128rrk_alt >+ 10U, // VMOVDQU64Z128rrkz >+ 10U, // VMOVDQU64Z128rrkz_alt >+ 0U, // VMOVDQU64Z256mr >+ 2U, // VMOVDQU64Z256mrk >+ 0U, // VMOVDQU64Z256rm >+ 170U, // VMOVDQU64Z256rmk >+ 106U, // VMOVDQU64Z256rmkz >+ 0U, // VMOVDQU64Z256rr >+ 0U, // VMOVDQU64Z256rr_alt >+ 42U, // VMOVDQU64Z256rrk >+ 42U, // VMOVDQU64Z256rrk_alt >+ 10U, // VMOVDQU64Z256rrkz >+ 10U, // VMOVDQU64Z256rrkz_alt >+ 0U, // VMOVDQU64Zmr >+ 2U, // VMOVDQU64Zmrk >+ 0U, // VMOVDQU64Zrm >+ 178U, // VMOVDQU64Zrmk >+ 98U, // VMOVDQU64Zrmkz >+ 0U, // VMOVDQU64Zrr >+ 0U, // VMOVDQU64Zrr_alt >+ 42U, // VMOVDQU64Zrrk >+ 42U, // VMOVDQU64Zrrk_alt >+ 10U, // VMOVDQU64Zrrkz >+ 10U, // VMOVDQU64Zrrkz_alt >+ 0U, // VMOVDQU8Z128mr >+ 2U, // VMOVDQU8Z128mrk >+ 0U, // VMOVDQU8Z128rm >+ 162U, // VMOVDQU8Z128rmk >+ 90U, // VMOVDQU8Z128rmkz >+ 0U, // VMOVDQU8Z128rr >+ 0U, // VMOVDQU8Z128rr_alt >+ 42U, // VMOVDQU8Z128rrk >+ 42U, // VMOVDQU8Z128rrk_alt >+ 10U, // VMOVDQU8Z128rrkz >+ 10U, // VMOVDQU8Z128rrkz_alt >+ 0U, // VMOVDQU8Z256mr >+ 2U, // VMOVDQU8Z256mrk >+ 0U, // VMOVDQU8Z256rm >+ 170U, // VMOVDQU8Z256rmk >+ 106U, // VMOVDQU8Z256rmkz >+ 0U, // VMOVDQU8Z256rr >+ 0U, // VMOVDQU8Z256rr_alt >+ 42U, // VMOVDQU8Z256rrk >+ 42U, // VMOVDQU8Z256rrk_alt >+ 10U, // VMOVDQU8Z256rrkz >+ 10U, // VMOVDQU8Z256rrkz_alt >+ 0U, // VMOVDQU8Zmr >+ 2U, // VMOVDQU8Zmrk >+ 0U, // VMOVDQU8Zrm >+ 178U, // VMOVDQU8Zrmk >+ 98U, // VMOVDQU8Zrmkz >+ 0U, // VMOVDQU8Zrr >+ 0U, // VMOVDQU8Zrr_alt >+ 42U, // VMOVDQU8Zrrk >+ 42U, // VMOVDQU8Zrrk_alt >+ 10U, // VMOVDQU8Zrrkz >+ 10U, // VMOVDQU8Zrrkz_alt >+ 0U, // VMOVDQUYmr >+ 0U, // VMOVDQUYrm >+ 0U, // VMOVDQUYrr >+ 0U, // VMOVDQUYrr_REV >+ 0U, // VMOVDQUmr >+ 0U, // VMOVDQUrm >+ 0U, // VMOVDQUrr >+ 0U, // VMOVDQUrr_REV >+ 8U, // VMOVHLPSZrr >+ 8U, // VMOVHLPSrr >+ 0U, // VMOVHPDmr >+ 48U, // VMOVHPDrm >+ 0U, // VMOVHPSmr >+ 48U, // VMOVHPSrm >+ 8U, // VMOVLHPSZrr >+ 8U, // VMOVLHPSrr >+ 0U, // VMOVLPDmr >+ 48U, // VMOVLPDrm >+ 0U, // VMOVLPSmr >+ 48U, // VMOVLPSrm >+ 0U, // VMOVMSKPDYrr >+ 0U, // VMOVMSKPDrr >+ 0U, // VMOVMSKPSYrr >+ 0U, // VMOVMSKPSrr >+ 0U, // VMOVNTDQAYrm >+ 0U, // VMOVNTDQAZ128rm >+ 0U, // VMOVNTDQAZ256rm >+ 0U, // VMOVNTDQAZrm >+ 0U, // VMOVNTDQArm >+ 0U, // VMOVNTDQYmr >+ 0U, // VMOVNTDQZ128mr >+ 0U, // VMOVNTDQZ256mr >+ 0U, // VMOVNTDQZmr >+ 0U, // VMOVNTDQmr >+ 0U, // VMOVNTPDYmr >+ 0U, // VMOVNTPDZ128mr >+ 0U, // VMOVNTPDZ256mr >+ 0U, // VMOVNTPDZmr >+ 0U, // VMOVNTPDmr >+ 0U, // VMOVNTPSYmr >+ 0U, // VMOVNTPSZ128mr >+ 0U, // VMOVNTPSZ256mr >+ 0U, // VMOVNTPSZmr >+ 0U, // VMOVNTPSmr >+ 0U, // VMOVPDI2DIZmr >+ 0U, // VMOVPDI2DIZrr >+ 0U, // VMOVPDI2DImr >+ 0U, // VMOVPDI2DIrr >+ 0U, // VMOVPQI2QImr >+ 0U, // VMOVPQI2QIrr >+ 0U, // VMOVPQIto64Zmr >+ 0U, // VMOVPQIto64Zrr >+ 0U, // VMOVPQIto64rr >+ 0U, // VMOVQI2PQIZrm >+ 0U, // VMOVQI2PQIrm >+ 0U, // VMOVSDZmr >+ 0U, // VMOVSDZrm >+ 8U, // VMOVSDZrr >+ 8U, // VMOVSDZrr_REV >+ 298U, // VMOVSDZrrk >+ 0U, // VMOVSDmr >+ 0U, // VMOVSDrm >+ 8U, // VMOVSDrr >+ 8U, // VMOVSDrr_REV >+ 0U, // VMOVSDto64Zmr >+ 0U, // VMOVSDto64Zrr >+ 0U, // VMOVSDto64mr >+ 0U, // VMOVSDto64rr >+ 0U, // VMOVSHDUPYrm >+ 0U, // VMOVSHDUPYrr >+ 0U, // VMOVSHDUPZrm >+ 0U, // VMOVSHDUPZrr >+ 0U, // VMOVSHDUPrm >+ 0U, // VMOVSHDUPrr >+ 0U, // VMOVSLDUPYrm >+ 0U, // VMOVSLDUPYrr >+ 0U, // VMOVSLDUPZrm >+ 0U, // VMOVSLDUPZrr >+ 0U, // VMOVSLDUPrm >+ 0U, // VMOVSLDUPrr >+ 0U, // VMOVSS2DIZmr >+ 0U, // VMOVSS2DIZrr >+ 0U, // VMOVSS2DImr >+ 0U, // VMOVSS2DIrr >+ 0U, // VMOVSSZmr >+ 0U, // VMOVSSZrm >+ 8U, // VMOVSSZrr >+ 8U, // VMOVSSZrr_REV >+ 298U, // VMOVSSZrrk >+ 0U, // VMOVSSmr >+ 0U, // VMOVSSrm >+ 8U, // VMOVSSrr >+ 8U, // VMOVSSrr_REV >+ 0U, // VMOVUPDYmr >+ 0U, // VMOVUPDYrm >+ 0U, // VMOVUPDYrr >+ 0U, // VMOVUPDYrr_REV >+ 0U, // VMOVUPDZ128mr >+ 2U, // VMOVUPDZ128mrk >+ 0U, // VMOVUPDZ128rm >+ 146U, // VMOVUPDZ128rmk >+ 82U, // VMOVUPDZ128rmkz >+ 0U, // VMOVUPDZ128rr >+ 0U, // VMOVUPDZ128rr_alt >+ 42U, // VMOVUPDZ128rrk >+ 42U, // VMOVUPDZ128rrk_alt >+ 10U, // VMOVUPDZ128rrkz >+ 10U, // VMOVUPDZ128rrkz_alt >+ 0U, // VMOVUPDZ256mr >+ 2U, // VMOVUPDZ256mrk >+ 0U, // VMOVUPDZ256rm >+ 154U, // VMOVUPDZ256rmk >+ 66U, // VMOVUPDZ256rmkz >+ 0U, // VMOVUPDZ256rr >+ 0U, // VMOVUPDZ256rr_alt >+ 42U, // VMOVUPDZ256rrk >+ 42U, // VMOVUPDZ256rrk_alt >+ 10U, // VMOVUPDZ256rrkz >+ 10U, // VMOVUPDZ256rrkz_alt >+ 0U, // VMOVUPDZmr >+ 2U, // VMOVUPDZmrk >+ 0U, // VMOVUPDZrm >+ 122U, // VMOVUPDZrmk >+ 74U, // VMOVUPDZrmkz >+ 0U, // VMOVUPDZrr >+ 0U, // VMOVUPDZrr_alt >+ 42U, // VMOVUPDZrrk >+ 42U, // VMOVUPDZrrk_alt >+ 10U, // VMOVUPDZrrkz >+ 10U, // VMOVUPDZrrkz_alt >+ 0U, // VMOVUPDmr >+ 0U, // VMOVUPDrm >+ 0U, // VMOVUPDrr >+ 0U, // VMOVUPDrr_REV >+ 0U, // VMOVUPSYmr >+ 0U, // VMOVUPSYrm >+ 0U, // VMOVUPSYrr >+ 0U, // VMOVUPSYrr_REV >+ 0U, // VMOVUPSZ128mr >+ 2U, // VMOVUPSZ128mrk >+ 0U, // VMOVUPSZ128rm >+ 146U, // VMOVUPSZ128rmk >+ 82U, // VMOVUPSZ128rmkz >+ 0U, // VMOVUPSZ128rr >+ 0U, // VMOVUPSZ128rr_alt >+ 42U, // VMOVUPSZ128rrk >+ 42U, // VMOVUPSZ128rrk_alt >+ 10U, // VMOVUPSZ128rrkz >+ 10U, // VMOVUPSZ128rrkz_alt >+ 0U, // VMOVUPSZ256mr >+ 2U, // VMOVUPSZ256mrk >+ 0U, // VMOVUPSZ256rm >+ 154U, // VMOVUPSZ256rmk >+ 66U, // VMOVUPSZ256rmkz >+ 0U, // VMOVUPSZ256rr >+ 0U, // VMOVUPSZ256rr_alt >+ 42U, // VMOVUPSZ256rrk >+ 42U, // VMOVUPSZ256rrk_alt >+ 10U, // VMOVUPSZ256rrkz >+ 10U, // VMOVUPSZ256rrkz_alt >+ 0U, // VMOVUPSZmr >+ 2U, // VMOVUPSZmrk >+ 0U, // VMOVUPSZrm >+ 122U, // VMOVUPSZrmk >+ 74U, // VMOVUPSZrmkz >+ 0U, // VMOVUPSZrr >+ 0U, // VMOVUPSZrr_alt >+ 42U, // VMOVUPSZrrk >+ 42U, // VMOVUPSZrrk_alt >+ 10U, // VMOVUPSZrrkz >+ 10U, // VMOVUPSZrrkz_alt >+ 0U, // VMOVUPSmr >+ 0U, // VMOVUPSrm >+ 0U, // VMOVUPSrr >+ 0U, // VMOVUPSrr_REV >+ 0U, // VMOVZPQILo2PQIZrm >+ 0U, // VMOVZPQILo2PQIZrr >+ 0U, // VMOVZPQILo2PQIrm >+ 0U, // VMOVZPQILo2PQIrr >+ 0U, // VMOVZQI2PQIrm >+ 0U, // VMOVZQI2PQIrr >+ 2408U, // VMPSADBWYrmi >+ 8456U, // VMPSADBWYrri >+ 2392U, // VMPSADBWrmi >+ 8456U, // VMPSADBWrri >+ 0U, // VMPTRLDm >+ 0U, // VMPTRSTm >+ 0U, // VMREAD32rm >+ 0U, // VMREAD32rr >+ 0U, // VMREAD64rm >+ 0U, // VMREAD64rr >+ 0U, // VMRESUME >+ 0U, // VMRUN32 >+ 0U, // VMRUN64 >+ 0U, // VMSAVE32 >+ 0U, // VMSAVE64 >+ 64U, // VMULPDYrm >+ 8U, // VMULPDYrr >+ 72U, // VMULPDZrm >+ 560U, // VMULPDZrmb >+ 69898U, // VMULPDZrmbk >+ 69898U, // VMULPDZrmbkz >+ 6410U, // VMULPDZrmk >+ 6410U, // VMULPDZrmkz >+ 8U, // VMULPDZrr >+ 8458U, // VMULPDZrrk >+ 8458U, // VMULPDZrrkz >+ 80U, // VMULPDrm >+ 8U, // VMULPDrr >+ 64U, // VMULPSYrm >+ 8U, // VMULPSYrr >+ 72U, // VMULPSZrm >+ 824U, // VMULPSZrmb >+ 108810U, // VMULPSZrmbk >+ 108810U, // VMULPSZrmbkz >+ 6410U, // VMULPSZrmk >+ 6410U, // VMULPSZrmkz >+ 8U, // VMULPSZrr >+ 8458U, // VMULPSZrrk >+ 8458U, // VMULPSZrrkz >+ 80U, // VMULPSrm >+ 8U, // VMULPSrr >+ 48U, // VMULSDZrm >+ 8U, // VMULSDZrr >+ 48U, // VMULSDrm >+ 48U, // VMULSDrm_Int >+ 8U, // VMULSDrr >+ 8U, // VMULSDrr_Int >+ 56U, // VMULSSZrm >+ 8U, // VMULSSZrr >+ 56U, // VMULSSrm >+ 56U, // VMULSSrm_Int >+ 8U, // VMULSSrr >+ 8U, // VMULSSrr_Int >+ 0U, // VMWRITE32rm >+ 0U, // VMWRITE32rr >+ 0U, // VMWRITE64rm >+ 0U, // VMWRITE64rr >+ 0U, // VMXOFF >+ 0U, // VMXON >+ 64U, // VORPDYrm >+ 8U, // VORPDYrr >+ 80U, // VORPDrm >+ 8U, // VORPDrr >+ 64U, // VORPSYrm >+ 8U, // VORPSYrr >+ 80U, // VORPSrm >+ 8U, // VORPSrr >+ 0U, // VPABSBrm128 >+ 0U, // VPABSBrm256 >+ 0U, // VPABSBrr128 >+ 0U, // VPABSBrr256 >+ 0U, // VPABSDZrm >+ 4U, // VPABSDZrmb >+ 786U, // VPABSDZrmbk >+ 786U, // VPABSDZrmbkz >+ 98U, // VPABSDZrmk >+ 98U, // VPABSDZrmkz >+ 0U, // VPABSDZrr >+ 10U, // VPABSDZrrk >+ 10U, // VPABSDZrrkz >+ 0U, // VPABSDrm128 >+ 0U, // VPABSDrm256 >+ 0U, // VPABSDrr128 >+ 0U, // VPABSDrr256 >+ 0U, // VPABSQZrm >+ 5U, // VPABSQZrmb >+ 538U, // VPABSQZrmbk >+ 538U, // VPABSQZrmbkz >+ 98U, // VPABSQZrmk >+ 98U, // VPABSQZrmkz >+ 0U, // VPABSQZrr >+ 10U, // VPABSQZrrk >+ 10U, // VPABSQZrrkz >+ 0U, // VPABSWrm128 >+ 0U, // VPABSWrm256 >+ 0U, // VPABSWrr128 >+ 0U, // VPABSWrr256 >+ 104U, // VPACKSSDWYrm >+ 8U, // VPACKSSDWYrr >+ 88U, // VPACKSSDWrm >+ 8U, // VPACKSSDWrr >+ 104U, // VPACKSSWBYrm >+ 8U, // VPACKSSWBYrr >+ 88U, // VPACKSSWBrm >+ 8U, // VPACKSSWBrr >+ 104U, // VPACKUSDWYrm >+ 8U, // VPACKUSDWYrr >+ 88U, // VPACKUSDWrm >+ 8U, // VPACKUSDWrr >+ 104U, // VPACKUSWBYrm >+ 8U, // VPACKUSWBYrr >+ 88U, // VPACKUSWBrm >+ 8U, // VPACKUSWBrr >+ 104U, // VPADDBYrm >+ 8U, // VPADDBYrr >+ 88U, // VPADDBrm >+ 8U, // VPADDBrr >+ 104U, // VPADDDYrm >+ 8U, // VPADDDYrr >+ 96U, // VPADDDZrm >+ 784U, // VPADDDZrmb >+ 16682U, // VPADDDZrmbk >+ 117002U, // VPADDDZrmbkz >+ 20778U, // VPADDDZrmk >+ 22794U, // VPADDDZrmkz >+ 8U, // VPADDDZrr >+ 298U, // VPADDDZrrk >+ 8458U, // VPADDDZrrkz >+ 88U, // VPADDDrm >+ 8U, // VPADDDrr >+ 104U, // VPADDQYrm >+ 8U, // VPADDQYrr >+ 96U, // VPADDQZrm >+ 536U, // VPADDQZrmb >+ 24874U, // VPADDQZrmbk >+ 92426U, // VPADDQZrmbkz >+ 20778U, // VPADDQZrmk >+ 22794U, // VPADDQZrmkz >+ 8U, // VPADDQZrr >+ 298U, // VPADDQZrrk >+ 8458U, // VPADDQZrrkz >+ 88U, // VPADDQrm >+ 8U, // VPADDQrr >+ 104U, // VPADDSBYrm >+ 8U, // VPADDSBYrr >+ 88U, // VPADDSBrm >+ 8U, // VPADDSBrr >+ 104U, // VPADDSWYrm >+ 8U, // VPADDSWYrr >+ 88U, // VPADDSWrm >+ 8U, // VPADDSWrr >+ 104U, // VPADDUSBYrm >+ 8U, // VPADDUSBYrr >+ 88U, // VPADDUSBrm >+ 8U, // VPADDUSBrr >+ 104U, // VPADDUSWYrm >+ 8U, // VPADDUSWYrr >+ 88U, // VPADDUSWrm >+ 8U, // VPADDUSWrr >+ 104U, // VPADDWYrm >+ 8U, // VPADDWYrr >+ 88U, // VPADDWrm >+ 8U, // VPADDWrr >+ 2392U, // VPALIGNR128rm >+ 8456U, // VPALIGNR128rr >+ 2408U, // VPALIGNR256rm >+ 8456U, // VPALIGNR256rr >+ 96U, // VPANDDZrm >+ 784U, // VPANDDZrmb >+ 16682U, // VPANDDZrmbk >+ 117002U, // VPANDDZrmbkz >+ 20778U, // VPANDDZrmk >+ 22794U, // VPANDDZrmkz >+ 8U, // VPANDDZrr >+ 298U, // VPANDDZrrk >+ 8458U, // VPANDDZrrkz >+ 96U, // VPANDNDZrm >+ 784U, // VPANDNDZrmb >+ 16682U, // VPANDNDZrmbk >+ 117002U, // VPANDNDZrmbkz >+ 20778U, // VPANDNDZrmk >+ 22794U, // VPANDNDZrmkz >+ 8U, // VPANDNDZrr >+ 298U, // VPANDNDZrrk >+ 8458U, // VPANDNDZrrkz >+ 96U, // VPANDNQZrm >+ 536U, // VPANDNQZrmb >+ 24874U, // VPANDNQZrmbk >+ 92426U, // VPANDNQZrmbkz >+ 20778U, // VPANDNQZrmk >+ 22794U, // VPANDNQZrmkz >+ 8U, // VPANDNQZrr >+ 298U, // VPANDNQZrrk >+ 8458U, // VPANDNQZrrkz >+ 104U, // VPANDNYrm >+ 8U, // VPANDNYrr >+ 88U, // VPANDNrm >+ 8U, // VPANDNrr >+ 96U, // VPANDQZrm >+ 536U, // VPANDQZrmb >+ 24874U, // VPANDQZrmbk >+ 92426U, // VPANDQZrmbkz >+ 20778U, // VPANDQZrmk >+ 22794U, // VPANDQZrmkz >+ 8U, // VPANDQZrr >+ 298U, // VPANDQZrrk >+ 8458U, // VPANDQZrrkz >+ 104U, // VPANDYrm >+ 8U, // VPANDYrr >+ 88U, // VPANDrm >+ 8U, // VPANDrr >+ 104U, // VPAVGBYrm >+ 8U, // VPAVGBYrr >+ 88U, // VPAVGBrm >+ 8U, // VPAVGBrr >+ 104U, // VPAVGWYrm >+ 8U, // VPAVGWYrr >+ 88U, // VPAVGWrm >+ 8U, // VPAVGWrr >+ 2408U, // VPBLENDDYrmi >+ 8456U, // VPBLENDDYrri >+ 2392U, // VPBLENDDrmi >+ 8456U, // VPBLENDDrri >+ 6410U, // VPBLENDMDZrm >+ 8458U, // VPBLENDMDZrr >+ 6410U, // VPBLENDMQZrm >+ 8458U, // VPBLENDMQZrr >+ 2408U, // VPBLENDVBYrm >+ 8456U, // VPBLENDVBYrr >+ 2392U, // VPBLENDVBrm >+ 8456U, // VPBLENDVBrr >+ 2408U, // VPBLENDWYrmi >+ 8456U, // VPBLENDWYrri >+ 2392U, // VPBLENDWrmi >+ 8456U, // VPBLENDWrri >+ 0U, // VPBROADCASTBYrm >+ 0U, // VPBROADCASTBYrr >+ 0U, // VPBROADCASTBrm >+ 0U, // VPBROADCASTBrr >+ 0U, // VPBROADCASTDYrm >+ 0U, // VPBROADCASTDYrr >+ 18U, // VPBROADCASTDZkrm >+ 10U, // VPBROADCASTDZkrr >+ 0U, // VPBROADCASTDZrm >+ 0U, // VPBROADCASTDZrr >+ 10U, // VPBROADCASTDrZkrr >+ 0U, // VPBROADCASTDrZrr >+ 0U, // VPBROADCASTDrm >+ 0U, // VPBROADCASTDrr >+ 0U, // VPBROADCASTMB2Qrr >+ 0U, // VPBROADCASTMW2Drr >+ 0U, // VPBROADCASTQYrm >+ 0U, // VPBROADCASTQYrr >+ 26U, // VPBROADCASTQZkrm >+ 10U, // VPBROADCASTQZkrr >+ 0U, // VPBROADCASTQZrm >+ 0U, // VPBROADCASTQZrr >+ 10U, // VPBROADCASTQrZkrr >+ 0U, // VPBROADCASTQrZrr >+ 0U, // VPBROADCASTQrm >+ 0U, // VPBROADCASTQrr >+ 0U, // VPBROADCASTWYrm >+ 0U, // VPBROADCASTWYrr >+ 0U, // VPBROADCASTWrm >+ 0U, // VPBROADCASTWrr >+ 2392U, // VPCLMULQDQrm >+ 8456U, // VPCLMULQDQrr >+ 2392U, // VPCMOVmr >+ 2368U, // VPCMOVmrY >+ 28936U, // VPCMOVrm >+ 30984U, // VPCMOVrmY >+ 8456U, // VPCMOVrr >+ 8456U, // VPCMOVrrY >+ 0U, // VPCMPDZrmi >+ 2400U, // VPCMPDZrmi_alt >+ 55562U, // VPCMPDZrmik_alt >+ 0U, // VPCMPDZrri >+ 8456U, // VPCMPDZrri_alt >+ 565514U, // VPCMPDZrrik_alt >+ 104U, // VPCMPEQBYrm >+ 8U, // VPCMPEQBYrr >+ 88U, // VPCMPEQBZ128rm >+ 28938U, // VPCMPEQBZ128rmk >+ 8U, // VPCMPEQBZ128rr >+ 8458U, // VPCMPEQBZ128rrk >+ 104U, // VPCMPEQBZ256rm >+ 30986U, // VPCMPEQBZ256rmk >+ 8U, // VPCMPEQBZ256rr >+ 8458U, // VPCMPEQBZ256rrk >+ 96U, // VPCMPEQBZrm >+ 22794U, // VPCMPEQBZrmk >+ 8U, // VPCMPEQBZrr >+ 8458U, // VPCMPEQBZrrk >+ 88U, // VPCMPEQBrm >+ 8U, // VPCMPEQBrr >+ 104U, // VPCMPEQDYrm >+ 8U, // VPCMPEQDYrr >+ 88U, // VPCMPEQDZ128rm >+ 1040U, // VPCMPEQDZ128rmb >+ 149770U, // VPCMPEQDZ128rmbk >+ 28938U, // VPCMPEQDZ128rmk >+ 8U, // VPCMPEQDZ128rr >+ 8458U, // VPCMPEQDZ128rrk >+ 104U, // VPCMPEQDZ256rm >+ 528U, // VPCMPEQDZ256rmb >+ 84234U, // VPCMPEQDZ256rmbk >+ 30986U, // VPCMPEQDZ256rmk >+ 8U, // VPCMPEQDZ256rr >+ 8458U, // VPCMPEQDZ256rrk >+ 96U, // VPCMPEQDZrm >+ 784U, // VPCMPEQDZrmb >+ 117002U, // VPCMPEQDZrmbk >+ 22794U, // VPCMPEQDZrmk >+ 8U, // VPCMPEQDZrr >+ 8458U, // VPCMPEQDZrrk >+ 88U, // VPCMPEQDrm >+ 8U, // VPCMPEQDrr >+ 104U, // VPCMPEQQYrm >+ 8U, // VPCMPEQQYrr >+ 88U, // VPCMPEQQZ128rm >+ 1304U, // VPCMPEQQZ128rmb >+ 190730U, // VPCMPEQQZ128rmbk >+ 28938U, // VPCMPEQQZ128rmk >+ 8U, // VPCMPEQQZ128rr >+ 8458U, // VPCMPEQQZ128rrk >+ 104U, // VPCMPEQQZ256rm >+ 1048U, // VPCMPEQQZ256rmb >+ 157962U, // VPCMPEQQZ256rmbk >+ 30986U, // VPCMPEQQZ256rmk >+ 8U, // VPCMPEQQZ256rr >+ 8458U, // VPCMPEQQZ256rrk >+ 96U, // VPCMPEQQZrm >+ 536U, // VPCMPEQQZrmb >+ 92426U, // VPCMPEQQZrmbk >+ 22794U, // VPCMPEQQZrmk >+ 8U, // VPCMPEQQZrr >+ 8458U, // VPCMPEQQZrrk >+ 88U, // VPCMPEQQrm >+ 8U, // VPCMPEQQrr >+ 104U, // VPCMPEQWYrm >+ 8U, // VPCMPEQWYrr >+ 88U, // VPCMPEQWZ128rm >+ 28938U, // VPCMPEQWZ128rmk >+ 8U, // VPCMPEQWZ128rr >+ 8458U, // VPCMPEQWZ128rrk >+ 104U, // VPCMPEQWZ256rm >+ 30986U, // VPCMPEQWZ256rmk >+ 8U, // VPCMPEQWZ256rr >+ 8458U, // VPCMPEQWZ256rrk >+ 96U, // VPCMPEQWZrm >+ 22794U, // VPCMPEQWZrmk >+ 8U, // VPCMPEQWZrr >+ 8458U, // VPCMPEQWZrrk >+ 88U, // VPCMPEQWrm >+ 8U, // VPCMPEQWrr >+ 0U, // VPCMPESTRIMEM >+ 0U, // VPCMPESTRIREG >+ 0U, // VPCMPESTRIrm >+ 8U, // VPCMPESTRIrr >+ 0U, // VPCMPESTRM128MEM >+ 0U, // VPCMPESTRM128REG >+ 0U, // VPCMPESTRM128rm >+ 8U, // VPCMPESTRM128rr >+ 104U, // VPCMPGTBYrm >+ 8U, // VPCMPGTBYrr >+ 88U, // VPCMPGTBZ128rm >+ 28938U, // VPCMPGTBZ128rmk >+ 8U, // VPCMPGTBZ128rr >+ 8458U, // VPCMPGTBZ128rrk >+ 104U, // VPCMPGTBZ256rm >+ 30986U, // VPCMPGTBZ256rmk >+ 8U, // VPCMPGTBZ256rr >+ 8458U, // VPCMPGTBZ256rrk >+ 96U, // VPCMPGTBZrm >+ 22794U, // VPCMPGTBZrmk >+ 8U, // VPCMPGTBZrr >+ 8458U, // VPCMPGTBZrrk >+ 88U, // VPCMPGTBrm >+ 8U, // VPCMPGTBrr >+ 104U, // VPCMPGTDYrm >+ 8U, // VPCMPGTDYrr >+ 88U, // VPCMPGTDZ128rm >+ 1040U, // VPCMPGTDZ128rmb >+ 149770U, // VPCMPGTDZ128rmbk >+ 28938U, // VPCMPGTDZ128rmk >+ 8U, // VPCMPGTDZ128rr >+ 8458U, // VPCMPGTDZ128rrk >+ 104U, // VPCMPGTDZ256rm >+ 528U, // VPCMPGTDZ256rmb >+ 84234U, // VPCMPGTDZ256rmbk >+ 30986U, // VPCMPGTDZ256rmk >+ 8U, // VPCMPGTDZ256rr >+ 8458U, // VPCMPGTDZ256rrk >+ 96U, // VPCMPGTDZrm >+ 784U, // VPCMPGTDZrmb >+ 117002U, // VPCMPGTDZrmbk >+ 22794U, // VPCMPGTDZrmk >+ 8U, // VPCMPGTDZrr >+ 8458U, // VPCMPGTDZrrk >+ 88U, // VPCMPGTDrm >+ 8U, // VPCMPGTDrr >+ 104U, // VPCMPGTQYrm >+ 8U, // VPCMPGTQYrr >+ 88U, // VPCMPGTQZ128rm >+ 1304U, // VPCMPGTQZ128rmb >+ 190730U, // VPCMPGTQZ128rmbk >+ 28938U, // VPCMPGTQZ128rmk >+ 8U, // VPCMPGTQZ128rr >+ 8458U, // VPCMPGTQZ128rrk >+ 104U, // VPCMPGTQZ256rm >+ 1048U, // VPCMPGTQZ256rmb >+ 157962U, // VPCMPGTQZ256rmbk >+ 30986U, // VPCMPGTQZ256rmk >+ 8U, // VPCMPGTQZ256rr >+ 8458U, // VPCMPGTQZ256rrk >+ 96U, // VPCMPGTQZrm >+ 536U, // VPCMPGTQZrmb >+ 92426U, // VPCMPGTQZrmbk >+ 22794U, // VPCMPGTQZrmk >+ 8U, // VPCMPGTQZrr >+ 8458U, // VPCMPGTQZrrk >+ 88U, // VPCMPGTQrm >+ 8U, // VPCMPGTQrr >+ 104U, // VPCMPGTWYrm >+ 8U, // VPCMPGTWYrr >+ 88U, // VPCMPGTWZ128rm >+ 28938U, // VPCMPGTWZ128rmk >+ 8U, // VPCMPGTWZ128rr >+ 8458U, // VPCMPGTWZ128rrk >+ 104U, // VPCMPGTWZ256rm >+ 30986U, // VPCMPGTWZ256rmk >+ 8U, // VPCMPGTWZ256rr >+ 8458U, // VPCMPGTWZ256rrk >+ 96U, // VPCMPGTWZrm >+ 22794U, // VPCMPGTWZrmk >+ 8U, // VPCMPGTWZrr >+ 8458U, // VPCMPGTWZrrk >+ 88U, // VPCMPGTWrm >+ 8U, // VPCMPGTWrr >+ 0U, // VPCMPISTRIMEM >+ 0U, // VPCMPISTRIREG >+ 0U, // VPCMPISTRIrm >+ 8U, // VPCMPISTRIrr >+ 0U, // VPCMPISTRM128MEM >+ 0U, // VPCMPISTRM128REG >+ 0U, // VPCMPISTRM128rm >+ 8U, // VPCMPISTRM128rr >+ 0U, // VPCMPQZrmi >+ 2400U, // VPCMPQZrmi_alt >+ 55562U, // VPCMPQZrmik_alt >+ 0U, // VPCMPQZrri >+ 8456U, // VPCMPQZrri_alt >+ 565514U, // VPCMPQZrrik_alt >+ 0U, // VPCMPUDZrmi >+ 2400U, // VPCMPUDZrmi_alt >+ 55562U, // VPCMPUDZrmik_alt >+ 0U, // VPCMPUDZrri >+ 8456U, // VPCMPUDZrri_alt >+ 565514U, // VPCMPUDZrrik_alt >+ 0U, // VPCMPUQZrmi >+ 2400U, // VPCMPUQZrmi_alt >+ 55562U, // VPCMPUQZrmik_alt >+ 0U, // VPCMPUQZrri >+ 8456U, // VPCMPUQZrri_alt >+ 565514U, // VPCMPUQZrrik_alt >+ 2392U, // VPCOMBmi >+ 8456U, // VPCOMBri >+ 2392U, // VPCOMDmi >+ 8456U, // VPCOMDri >+ 2392U, // VPCOMQmi >+ 8456U, // VPCOMQri >+ 2392U, // VPCOMUBmi >+ 8456U, // VPCOMUBri >+ 2392U, // VPCOMUDmi >+ 8456U, // VPCOMUDri >+ 2392U, // VPCOMUQmi >+ 8456U, // VPCOMUQri >+ 2392U, // VPCOMUWmi >+ 8456U, // VPCOMUWri >+ 2392U, // VPCOMWmi >+ 8456U, // VPCOMWri >+ 0U, // VPCONFLICTDrm >+ 4U, // VPCONFLICTDrmb >+ 186U, // VPCONFLICTDrmbk >+ 786U, // VPCONFLICTDrmbkz >+ 178U, // VPCONFLICTDrmk >+ 98U, // VPCONFLICTDrmkz >+ 0U, // VPCONFLICTDrr >+ 42U, // VPCONFLICTDrrk >+ 10U, // VPCONFLICTDrrkz >+ 0U, // VPCONFLICTQrm >+ 5U, // VPCONFLICTQrmb >+ 194U, // VPCONFLICTQrmbk >+ 538U, // VPCONFLICTQrmbkz >+ 178U, // VPCONFLICTQrmk >+ 98U, // VPCONFLICTQrmkz >+ 0U, // VPCONFLICTQrr >+ 42U, // VPCONFLICTQrrk >+ 10U, // VPCONFLICTQrrkz >+ 2368U, // VPERM2F128rm >+ 8456U, // VPERM2F128rr >+ 2368U, // VPERM2I128rm >+ 8456U, // VPERM2I128rr >+ 104U, // VPERMDYrm >+ 8U, // VPERMDYrr >+ 96U, // VPERMDZrm >+ 8U, // VPERMDZrr >+ 176U, // VPERMI2Drm >+ 20778U, // VPERMI2Drmk >+ 20778U, // VPERMI2Drmkz >+ 40U, // VPERMI2Drr >+ 298U, // VPERMI2Drrk >+ 298U, // VPERMI2Drrkz >+ 176U, // VPERMI2PDrm >+ 20778U, // VPERMI2PDrmk >+ 20778U, // VPERMI2PDrmkz >+ 40U, // VPERMI2PDrr >+ 298U, // VPERMI2PDrrk >+ 298U, // VPERMI2PDrrkz >+ 176U, // VPERMI2PSrm >+ 20778U, // VPERMI2PSrmk >+ 20778U, // VPERMI2PSrmkz >+ 40U, // VPERMI2PSrr >+ 298U, // VPERMI2PSrrk >+ 298U, // VPERMI2PSrrkz >+ 176U, // VPERMI2Qrm >+ 20778U, // VPERMI2Qrmk >+ 20778U, // VPERMI2Qrmkz >+ 40U, // VPERMI2Qrr >+ 298U, // VPERMI2Qrrk >+ 298U, // VPERMI2Qrrkz >+ 35152U, // VPERMIL2PDmr >+ 35136U, // VPERMIL2PDmrY >+ 45320U, // VPERMIL2PDrm >+ 47368U, // VPERMIL2PDrmY >+ 565512U, // VPERMIL2PDrr >+ 565512U, // VPERMIL2PDrrY >+ 35152U, // VPERMIL2PSmr >+ 35136U, // VPERMIL2PSmrY >+ 45320U, // VPERMIL2PSrm >+ 47368U, // VPERMIL2PSrmY >+ 565512U, // VPERMIL2PSrr >+ 565512U, // VPERMIL2PSrrY >+ 0U, // VPERMILPDYmi >+ 8U, // VPERMILPDYri >+ 104U, // VPERMILPDYrm >+ 8U, // VPERMILPDYrr >+ 0U, // VPERMILPDZmi >+ 8U, // VPERMILPDZri >+ 0U, // VPERMILPDmi >+ 8U, // VPERMILPDri >+ 88U, // VPERMILPDrm >+ 8U, // VPERMILPDrr >+ 0U, // VPERMILPSYmi >+ 8U, // VPERMILPSYri >+ 104U, // VPERMILPSYrm >+ 8U, // VPERMILPSYrr >+ 0U, // VPERMILPSZmi >+ 8U, // VPERMILPSZri >+ 0U, // VPERMILPSmi >+ 8U, // VPERMILPSri >+ 88U, // VPERMILPSrm >+ 8U, // VPERMILPSrr >+ 0U, // VPERMPDYmi >+ 8U, // VPERMPDYri >+ 0U, // VPERMPDZmi >+ 8U, // VPERMPDZri >+ 72U, // VPERMPDZrm >+ 8U, // VPERMPDZrr >+ 104U, // VPERMPSYrm >+ 8U, // VPERMPSYrr >+ 72U, // VPERMPSZrm >+ 8U, // VPERMPSZrr >+ 0U, // VPERMQYmi >+ 8U, // VPERMQYri >+ 0U, // VPERMQZmi >+ 8U, // VPERMQZri >+ 96U, // VPERMQZrm >+ 8U, // VPERMQZrr >+ 176U, // VPERMT2Drm >+ 20778U, // VPERMT2Drmk >+ 20778U, // VPERMT2Drmkz >+ 40U, // VPERMT2Drr >+ 298U, // VPERMT2Drrk >+ 298U, // VPERMT2Drrkz >+ 176U, // VPERMT2PDrm >+ 20778U, // VPERMT2PDrmk >+ 20778U, // VPERMT2PDrmkz >+ 40U, // VPERMT2PDrr >+ 298U, // VPERMT2PDrrk >+ 298U, // VPERMT2PDrrkz >+ 176U, // VPERMT2PSrm >+ 20778U, // VPERMT2PSrmk >+ 20778U, // VPERMT2PSrmkz >+ 40U, // VPERMT2PSrr >+ 298U, // VPERMT2PSrrk >+ 298U, // VPERMT2PSrrkz >+ 176U, // VPERMT2Qrm >+ 20778U, // VPERMT2Qrmk >+ 20778U, // VPERMT2Qrmkz >+ 40U, // VPERMT2Qrr >+ 298U, // VPERMT2Qrrk >+ 298U, // VPERMT2Qrrkz >+ 0U, // VPEXTRBmr >+ 8U, // VPEXTRBrr >+ 0U, // VPEXTRDmr >+ 8U, // VPEXTRDrr >+ 0U, // VPEXTRQmr >+ 8U, // VPEXTRQrr >+ 0U, // VPEXTRWmr >+ 8U, // VPEXTRWri >+ 8U, // VPEXTRWrr_REV >+ 0U, // VPGATHERDDYrm >+ 4U, // VPGATHERDDZrm >+ 0U, // VPGATHERDDrm >+ 0U, // VPGATHERDQYrm >+ 3U, // VPGATHERDQZrm >+ 0U, // VPGATHERDQrm >+ 0U, // VPGATHERQDYrm >+ 3U, // VPGATHERQDZrm >+ 0U, // VPGATHERQDrm >+ 0U, // VPGATHERQQYrm >+ 3U, // VPGATHERQQZrm >+ 0U, // VPGATHERQQrm >+ 0U, // VPHADDBDrm >+ 0U, // VPHADDBDrr >+ 0U, // VPHADDBQrm >+ 0U, // VPHADDBQrr >+ 0U, // VPHADDBWrm >+ 0U, // VPHADDBWrr >+ 0U, // VPHADDDQrm >+ 0U, // VPHADDDQrr >+ 104U, // VPHADDDYrm >+ 8U, // VPHADDDYrr >+ 88U, // VPHADDDrm >+ 8U, // VPHADDDrr >+ 88U, // VPHADDSWrm128 >+ 104U, // VPHADDSWrm256 >+ 8U, // VPHADDSWrr128 >+ 8U, // VPHADDSWrr256 >+ 0U, // VPHADDUBDrm >+ 0U, // VPHADDUBDrr >+ 0U, // VPHADDUBQrm >+ 0U, // VPHADDUBQrr >+ 0U, // VPHADDUBWrm >+ 0U, // VPHADDUBWrr >+ 0U, // VPHADDUDQrm >+ 0U, // VPHADDUDQrr >+ 0U, // VPHADDUWDrm >+ 0U, // VPHADDUWDrr >+ 0U, // VPHADDUWQrm >+ 0U, // VPHADDUWQrr >+ 0U, // VPHADDWDrm >+ 0U, // VPHADDWDrr >+ 0U, // VPHADDWQrm >+ 0U, // VPHADDWQrr >+ 104U, // VPHADDWYrm >+ 8U, // VPHADDWYrr >+ 88U, // VPHADDWrm >+ 8U, // VPHADDWrr >+ 0U, // VPHMINPOSUWrm128 >+ 0U, // VPHMINPOSUWrr128 >+ 0U, // VPHSUBBWrm >+ 0U, // VPHSUBBWrr >+ 0U, // VPHSUBDQrm >+ 0U, // VPHSUBDQrr >+ 104U, // VPHSUBDYrm >+ 8U, // VPHSUBDYrr >+ 88U, // VPHSUBDrm >+ 8U, // VPHSUBDrr >+ 88U, // VPHSUBSWrm128 >+ 104U, // VPHSUBSWrm256 >+ 8U, // VPHSUBSWrr128 >+ 8U, // VPHSUBSWrr256 >+ 0U, // VPHSUBWDrm >+ 0U, // VPHSUBWDrr >+ 104U, // VPHSUBWYrm >+ 8U, // VPHSUBWYrr >+ 88U, // VPHSUBWrm >+ 8U, // VPHSUBWrr >+ 200U, // VPINSRBrm >+ 8456U, // VPINSRBrr >+ 2320U, // VPINSRDrm >+ 8456U, // VPINSRDrr >+ 2328U, // VPINSRQrm >+ 8456U, // VPINSRQrr >+ 208U, // VPINSRWrmi >+ 8456U, // VPINSRWrri >+ 0U, // VPLZCNTDrm >+ 4U, // VPLZCNTDrmb >+ 186U, // VPLZCNTDrmbk >+ 786U, // VPLZCNTDrmbkz >+ 178U, // VPLZCNTDrmk >+ 98U, // VPLZCNTDrmkz >+ 0U, // VPLZCNTDrr >+ 42U, // VPLZCNTDrrk >+ 10U, // VPLZCNTDrrkz >+ 0U, // VPLZCNTQrm >+ 5U, // VPLZCNTQrmb >+ 194U, // VPLZCNTQrmbk >+ 538U, // VPLZCNTQrmbkz >+ 178U, // VPLZCNTQrmk >+ 98U, // VPLZCNTQrmkz >+ 0U, // VPLZCNTQrr >+ 42U, // VPLZCNTQrrk >+ 10U, // VPLZCNTQrrkz >+ 2392U, // VPMACSDDrm >+ 8456U, // VPMACSDDrr >+ 2392U, // VPMACSDQHrm >+ 8456U, // VPMACSDQHrr >+ 2392U, // VPMACSDQLrm >+ 8456U, // VPMACSDQLrr >+ 2392U, // VPMACSSDDrm >+ 8456U, // VPMACSSDDrr >+ 2392U, // VPMACSSDQHrm >+ 8456U, // VPMACSSDQHrr >+ 2392U, // VPMACSSDQLrm >+ 8456U, // VPMACSSDQLrr >+ 2392U, // VPMACSSWDrm >+ 8456U, // VPMACSSWDrr >+ 2392U, // VPMACSSWWrm >+ 8456U, // VPMACSSWWrr >+ 2392U, // VPMACSWDrm >+ 8456U, // VPMACSWDrr >+ 2392U, // VPMACSWWrm >+ 8456U, // VPMACSWWrr >+ 2392U, // VPMADCSSWDrm >+ 8456U, // VPMADCSSWDrr >+ 2392U, // VPMADCSWDrm >+ 8456U, // VPMADCSWDrr >+ 88U, // VPMADDUBSWrm128 >+ 104U, // VPMADDUBSWrm256 >+ 8U, // VPMADDUBSWrr128 >+ 8U, // VPMADDUBSWrr256 >+ 104U, // VPMADDWDYrm >+ 8U, // VPMADDWDYrr >+ 88U, // VPMADDWDrm >+ 8U, // VPMADDWDrr >+ 0U, // VPMASKMOVDYmr >+ 104U, // VPMASKMOVDYrm >+ 0U, // VPMASKMOVDmr >+ 88U, // VPMASKMOVDrm >+ 0U, // VPMASKMOVQYmr >+ 104U, // VPMASKMOVQYrm >+ 0U, // VPMASKMOVQmr >+ 88U, // VPMASKMOVQrm >+ 104U, // VPMAXSBYrm >+ 8U, // VPMAXSBYrr >+ 88U, // VPMAXSBrm >+ 8U, // VPMAXSBrr >+ 104U, // VPMAXSDYrm >+ 8U, // VPMAXSDYrr >+ 96U, // VPMAXSDZrm >+ 784U, // VPMAXSDZrmb >+ 16682U, // VPMAXSDZrmbk >+ 117002U, // VPMAXSDZrmbkz >+ 20778U, // VPMAXSDZrmk >+ 22794U, // VPMAXSDZrmkz >+ 8U, // VPMAXSDZrr >+ 298U, // VPMAXSDZrrk >+ 8458U, // VPMAXSDZrrkz >+ 88U, // VPMAXSDrm >+ 8U, // VPMAXSDrr >+ 96U, // VPMAXSQZrm >+ 536U, // VPMAXSQZrmb >+ 24874U, // VPMAXSQZrmbk >+ 92426U, // VPMAXSQZrmbkz >+ 20778U, // VPMAXSQZrmk >+ 22794U, // VPMAXSQZrmkz >+ 8U, // VPMAXSQZrr >+ 298U, // VPMAXSQZrrk >+ 8458U, // VPMAXSQZrrkz >+ 104U, // VPMAXSWYrm >+ 8U, // VPMAXSWYrr >+ 88U, // VPMAXSWrm >+ 8U, // VPMAXSWrr >+ 104U, // VPMAXUBYrm >+ 8U, // VPMAXUBYrr >+ 88U, // VPMAXUBrm >+ 8U, // VPMAXUBrr >+ 104U, // VPMAXUDYrm >+ 8U, // VPMAXUDYrr >+ 96U, // VPMAXUDZrm >+ 784U, // VPMAXUDZrmb >+ 16682U, // VPMAXUDZrmbk >+ 117002U, // VPMAXUDZrmbkz >+ 20778U, // VPMAXUDZrmk >+ 22794U, // VPMAXUDZrmkz >+ 8U, // VPMAXUDZrr >+ 298U, // VPMAXUDZrrk >+ 8458U, // VPMAXUDZrrkz >+ 88U, // VPMAXUDrm >+ 8U, // VPMAXUDrr >+ 96U, // VPMAXUQZrm >+ 536U, // VPMAXUQZrmb >+ 24874U, // VPMAXUQZrmbk >+ 92426U, // VPMAXUQZrmbkz >+ 20778U, // VPMAXUQZrmk >+ 22794U, // VPMAXUQZrmkz >+ 8U, // VPMAXUQZrr >+ 298U, // VPMAXUQZrrk >+ 8458U, // VPMAXUQZrrkz >+ 104U, // VPMAXUWYrm >+ 8U, // VPMAXUWYrr >+ 88U, // VPMAXUWrm >+ 8U, // VPMAXUWrr >+ 104U, // VPMINSBYrm >+ 8U, // VPMINSBYrr >+ 88U, // VPMINSBrm >+ 8U, // VPMINSBrr >+ 104U, // VPMINSDYrm >+ 8U, // VPMINSDYrr >+ 96U, // VPMINSDZrm >+ 784U, // VPMINSDZrmb >+ 16682U, // VPMINSDZrmbk >+ 117002U, // VPMINSDZrmbkz >+ 20778U, // VPMINSDZrmk >+ 22794U, // VPMINSDZrmkz >+ 8U, // VPMINSDZrr >+ 298U, // VPMINSDZrrk >+ 8458U, // VPMINSDZrrkz >+ 88U, // VPMINSDrm >+ 8U, // VPMINSDrr >+ 96U, // VPMINSQZrm >+ 536U, // VPMINSQZrmb >+ 24874U, // VPMINSQZrmbk >+ 92426U, // VPMINSQZrmbkz >+ 20778U, // VPMINSQZrmk >+ 22794U, // VPMINSQZrmkz >+ 8U, // VPMINSQZrr >+ 298U, // VPMINSQZrrk >+ 8458U, // VPMINSQZrrkz >+ 104U, // VPMINSWYrm >+ 8U, // VPMINSWYrr >+ 88U, // VPMINSWrm >+ 8U, // VPMINSWrr >+ 104U, // VPMINUBYrm >+ 8U, // VPMINUBYrr >+ 88U, // VPMINUBrm >+ 8U, // VPMINUBrr >+ 104U, // VPMINUDYrm >+ 8U, // VPMINUDYrr >+ 96U, // VPMINUDZrm >+ 784U, // VPMINUDZrmb >+ 16682U, // VPMINUDZrmbk >+ 117002U, // VPMINUDZrmbkz >+ 20778U, // VPMINUDZrmk >+ 22794U, // VPMINUDZrmkz >+ 8U, // VPMINUDZrr >+ 298U, // VPMINUDZrrk >+ 8458U, // VPMINUDZrrkz >+ 88U, // VPMINUDrm >+ 8U, // VPMINUDrr >+ 96U, // VPMINUQZrm >+ 536U, // VPMINUQZrmb >+ 24874U, // VPMINUQZrmbk >+ 92426U, // VPMINUQZrmbkz >+ 20778U, // VPMINUQZrmk >+ 22794U, // VPMINUQZrmkz >+ 8U, // VPMINUQZrr >+ 298U, // VPMINUQZrrk >+ 8458U, // VPMINUQZrrkz >+ 104U, // VPMINUWYrm >+ 8U, // VPMINUWYrr >+ 88U, // VPMINUWrm >+ 8U, // VPMINUWrr >+ 0U, // VPMOVDBmr >+ 2U, // VPMOVDBmrk >+ 0U, // VPMOVDBrr >+ 10U, // VPMOVDBrrk >+ 10U, // VPMOVDBrrkz >+ 0U, // VPMOVDWmr >+ 2U, // VPMOVDWmrk >+ 0U, // VPMOVDWrr >+ 10U, // VPMOVDWrrk >+ 10U, // VPMOVDWrrkz >+ 0U, // VPMOVMSKBYrr >+ 0U, // VPMOVMSKBrr >+ 0U, // VPMOVQBmr >+ 2U, // VPMOVQBmrk >+ 0U, // VPMOVQBrr >+ 10U, // VPMOVQBrrk >+ 10U, // VPMOVQBrrkz >+ 0U, // VPMOVQDmr >+ 2U, // VPMOVQDmrk >+ 0U, // VPMOVQDrr >+ 10U, // VPMOVQDrrk >+ 10U, // VPMOVQDrrkz >+ 0U, // VPMOVQWmr >+ 2U, // VPMOVQWmrk >+ 0U, // VPMOVQWrr >+ 10U, // VPMOVQWrrk >+ 10U, // VPMOVQWrrkz >+ 0U, // VPMOVSDBmr >+ 2U, // VPMOVSDBmrk >+ 0U, // VPMOVSDBrr >+ 10U, // VPMOVSDBrrk >+ 10U, // VPMOVSDBrrkz >+ 0U, // VPMOVSDWmr >+ 2U, // VPMOVSDWmrk >+ 0U, // VPMOVSDWrr >+ 10U, // VPMOVSDWrrk >+ 10U, // VPMOVSDWrrkz >+ 0U, // VPMOVSQBmr >+ 2U, // VPMOVSQBmrk >+ 0U, // VPMOVSQBrr >+ 10U, // VPMOVSQBrrk >+ 10U, // VPMOVSQBrrkz >+ 0U, // VPMOVSQDmr >+ 2U, // VPMOVSQDmrk >+ 0U, // VPMOVSQDrr >+ 10U, // VPMOVSQDrrk >+ 10U, // VPMOVSQDrrkz >+ 0U, // VPMOVSQWmr >+ 2U, // VPMOVSQWmrk >+ 0U, // VPMOVSQWrr >+ 10U, // VPMOVSQWrrk >+ 10U, // VPMOVSQWrrkz >+ 0U, // VPMOVSXBDYrm >+ 0U, // VPMOVSXBDYrr >+ 0U, // VPMOVSXBDZrm >+ 90U, // VPMOVSXBDZrmk >+ 90U, // VPMOVSXBDZrmkz >+ 0U, // VPMOVSXBDZrr >+ 10U, // VPMOVSXBDZrrk >+ 10U, // VPMOVSXBDZrrkz >+ 0U, // VPMOVSXBDrm >+ 0U, // VPMOVSXBDrr >+ 0U, // VPMOVSXBQYrm >+ 0U, // VPMOVSXBQYrr >+ 0U, // VPMOVSXBQZrm >+ 90U, // VPMOVSXBQZrmk >+ 90U, // VPMOVSXBQZrmkz >+ 0U, // VPMOVSXBQZrr >+ 10U, // VPMOVSXBQZrrk >+ 10U, // VPMOVSXBQZrrkz >+ 0U, // VPMOVSXBQrm >+ 0U, // VPMOVSXBQrr >+ 0U, // VPMOVSXBWYrm >+ 0U, // VPMOVSXBWYrr >+ 0U, // VPMOVSXBWrm >+ 0U, // VPMOVSXBWrr >+ 0U, // VPMOVSXDQYrm >+ 0U, // VPMOVSXDQYrr >+ 0U, // VPMOVSXDQZrm >+ 106U, // VPMOVSXDQZrmk >+ 106U, // VPMOVSXDQZrmkz >+ 0U, // VPMOVSXDQZrr >+ 10U, // VPMOVSXDQZrrk >+ 10U, // VPMOVSXDQZrrkz >+ 0U, // VPMOVSXDQrm >+ 0U, // VPMOVSXDQrr >+ 0U, // VPMOVSXWDYrm >+ 0U, // VPMOVSXWDYrr >+ 0U, // VPMOVSXWDZrm >+ 106U, // VPMOVSXWDZrmk >+ 106U, // VPMOVSXWDZrmkz >+ 0U, // VPMOVSXWDZrr >+ 10U, // VPMOVSXWDZrrk >+ 10U, // VPMOVSXWDZrrkz >+ 0U, // VPMOVSXWDrm >+ 0U, // VPMOVSXWDrr >+ 0U, // VPMOVSXWQYrm >+ 0U, // VPMOVSXWQYrr >+ 0U, // VPMOVSXWQZrm >+ 90U, // VPMOVSXWQZrmk >+ 90U, // VPMOVSXWQZrmkz >+ 0U, // VPMOVSXWQZrr >+ 10U, // VPMOVSXWQZrrk >+ 10U, // VPMOVSXWQZrrkz >+ 0U, // VPMOVSXWQrm >+ 0U, // VPMOVSXWQrr >+ 0U, // VPMOVUSDBmr >+ 2U, // VPMOVUSDBmrk >+ 0U, // VPMOVUSDBrr >+ 10U, // VPMOVUSDBrrk >+ 10U, // VPMOVUSDBrrkz >+ 0U, // VPMOVUSDWmr >+ 2U, // VPMOVUSDWmrk >+ 0U, // VPMOVUSDWrr >+ 10U, // VPMOVUSDWrrk >+ 10U, // VPMOVUSDWrrkz >+ 0U, // VPMOVUSQBmr >+ 2U, // VPMOVUSQBmrk >+ 0U, // VPMOVUSQBrr >+ 10U, // VPMOVUSQBrrk >+ 10U, // VPMOVUSQBrrkz >+ 0U, // VPMOVUSQDmr >+ 2U, // VPMOVUSQDmrk >+ 0U, // VPMOVUSQDrr >+ 10U, // VPMOVUSQDrrk >+ 10U, // VPMOVUSQDrrkz >+ 0U, // VPMOVUSQWmr >+ 2U, // VPMOVUSQWmrk >+ 0U, // VPMOVUSQWrr >+ 10U, // VPMOVUSQWrrk >+ 10U, // VPMOVUSQWrrkz >+ 0U, // VPMOVZXBDYrm >+ 0U, // VPMOVZXBDYrr >+ 0U, // VPMOVZXBDZrm >+ 90U, // VPMOVZXBDZrmk >+ 90U, // VPMOVZXBDZrmkz >+ 0U, // VPMOVZXBDZrr >+ 10U, // VPMOVZXBDZrrk >+ 10U, // VPMOVZXBDZrrkz >+ 0U, // VPMOVZXBDrm >+ 0U, // VPMOVZXBDrr >+ 0U, // VPMOVZXBQYrm >+ 0U, // VPMOVZXBQYrr >+ 0U, // VPMOVZXBQZrm >+ 90U, // VPMOVZXBQZrmk >+ 90U, // VPMOVZXBQZrmkz >+ 0U, // VPMOVZXBQZrr >+ 10U, // VPMOVZXBQZrrk >+ 10U, // VPMOVZXBQZrrkz >+ 0U, // VPMOVZXBQrm >+ 0U, // VPMOVZXBQrr >+ 0U, // VPMOVZXBWYrm >+ 0U, // VPMOVZXBWYrr >+ 0U, // VPMOVZXBWrm >+ 0U, // VPMOVZXBWrr >+ 0U, // VPMOVZXDQYrm >+ 0U, // VPMOVZXDQYrr >+ 0U, // VPMOVZXDQZrm >+ 106U, // VPMOVZXDQZrmk >+ 106U, // VPMOVZXDQZrmkz >+ 0U, // VPMOVZXDQZrr >+ 10U, // VPMOVZXDQZrrk >+ 10U, // VPMOVZXDQZrrkz >+ 0U, // VPMOVZXDQrm >+ 0U, // VPMOVZXDQrr >+ 0U, // VPMOVZXWDYrm >+ 0U, // VPMOVZXWDYrr >+ 0U, // VPMOVZXWDZrm >+ 106U, // VPMOVZXWDZrmk >+ 106U, // VPMOVZXWDZrmkz >+ 0U, // VPMOVZXWDZrr >+ 10U, // VPMOVZXWDZrrk >+ 10U, // VPMOVZXWDZrrkz >+ 0U, // VPMOVZXWDrm >+ 0U, // VPMOVZXWDrr >+ 0U, // VPMOVZXWQYrm >+ 0U, // VPMOVZXWQYrr >+ 0U, // VPMOVZXWQZrm >+ 90U, // VPMOVZXWQZrmk >+ 90U, // VPMOVZXWQZrmkz >+ 0U, // VPMOVZXWQZrr >+ 10U, // VPMOVZXWQZrrk >+ 10U, // VPMOVZXWQZrrkz >+ 0U, // VPMOVZXWQrm >+ 0U, // VPMOVZXWQrr >+ 104U, // VPMULDQYrm >+ 8U, // VPMULDQYrr >+ 96U, // VPMULDQZrm >+ 536U, // VPMULDQZrmb >+ 92426U, // VPMULDQZrmbk >+ 92426U, // VPMULDQZrmbkz >+ 22794U, // VPMULDQZrmk >+ 22794U, // VPMULDQZrmkz >+ 8U, // VPMULDQZrr >+ 8458U, // VPMULDQZrrk >+ 8458U, // VPMULDQZrrkz >+ 88U, // VPMULDQrm >+ 8U, // VPMULDQrr >+ 88U, // VPMULHRSWrm128 >+ 104U, // VPMULHRSWrm256 >+ 8U, // VPMULHRSWrr128 >+ 8U, // VPMULHRSWrr256 >+ 104U, // VPMULHUWYrm >+ 8U, // VPMULHUWYrr >+ 88U, // VPMULHUWrm >+ 8U, // VPMULHUWrr >+ 104U, // VPMULHWYrm >+ 8U, // VPMULHWYrr >+ 88U, // VPMULHWrm >+ 8U, // VPMULHWrr >+ 104U, // VPMULLDYrm >+ 8U, // VPMULLDYrr >+ 96U, // VPMULLDZrm >+ 784U, // VPMULLDZrmb >+ 16682U, // VPMULLDZrmbk >+ 117002U, // VPMULLDZrmbkz >+ 20778U, // VPMULLDZrmk >+ 22794U, // VPMULLDZrmkz >+ 8U, // VPMULLDZrr >+ 298U, // VPMULLDZrrk >+ 8458U, // VPMULLDZrrkz >+ 88U, // VPMULLDrm >+ 8U, // VPMULLDrr >+ 104U, // VPMULLWYrm >+ 8U, // VPMULLWYrr >+ 88U, // VPMULLWrm >+ 8U, // VPMULLWrr >+ 104U, // VPMULUDQYrm >+ 8U, // VPMULUDQYrr >+ 96U, // VPMULUDQZrm >+ 536U, // VPMULUDQZrmb >+ 92426U, // VPMULUDQZrmbk >+ 92426U, // VPMULUDQZrmbkz >+ 22794U, // VPMULUDQZrmk >+ 22794U, // VPMULUDQZrmkz >+ 8U, // VPMULUDQZrr >+ 8458U, // VPMULUDQZrrk >+ 8458U, // VPMULUDQZrrkz >+ 88U, // VPMULUDQrm >+ 8U, // VPMULUDQrr >+ 96U, // VPORDZrm >+ 784U, // VPORDZrmb >+ 16682U, // VPORDZrmbk >+ 117002U, // VPORDZrmbkz >+ 20778U, // VPORDZrmk >+ 22794U, // VPORDZrmkz >+ 8U, // VPORDZrr >+ 298U, // VPORDZrrk >+ 8458U, // VPORDZrrkz >+ 96U, // VPORQZrm >+ 536U, // VPORQZrmb >+ 24874U, // VPORQZrmbk >+ 92426U, // VPORQZrmbkz >+ 20778U, // VPORQZrmk >+ 22794U, // VPORQZrmkz >+ 8U, // VPORQZrr >+ 298U, // VPORQZrrk >+ 8458U, // VPORQZrrkz >+ 104U, // VPORYrm >+ 8U, // VPORYrr >+ 88U, // VPORrm >+ 8U, // VPORrr >+ 2392U, // VPPERMmr >+ 28936U, // VPPERMrm >+ 8456U, // VPPERMrr >+ 0U, // VPROTBmi >+ 0U, // VPROTBmr >+ 8U, // VPROTBri >+ 88U, // VPROTBrm >+ 8U, // VPROTBrr >+ 0U, // VPROTDmi >+ 0U, // VPROTDmr >+ 8U, // VPROTDri >+ 88U, // VPROTDrm >+ 8U, // VPROTDrr >+ 0U, // VPROTQmi >+ 0U, // VPROTQmr >+ 8U, // VPROTQri >+ 88U, // VPROTQrm >+ 8U, // VPROTQrr >+ 0U, // VPROTWmi >+ 0U, // VPROTWmr >+ 8U, // VPROTWri >+ 88U, // VPROTWrm >+ 8U, // VPROTWrr >+ 104U, // VPSADBWYrm >+ 8U, // VPSADBWYrr >+ 88U, // VPSADBWrm >+ 8U, // VPSADBWrr >+ 0U, // VPSCATTERDDZmr >+ 0U, // VPSCATTERDQZmr >+ 0U, // VPSCATTERQDZmr >+ 0U, // VPSCATTERQQZmr >+ 0U, // VPSHABmr >+ 88U, // VPSHABrm >+ 8U, // VPSHABrr >+ 0U, // VPSHADmr >+ 88U, // VPSHADrm >+ 8U, // VPSHADrr >+ 0U, // VPSHAQmr >+ 88U, // VPSHAQrm >+ 8U, // VPSHAQrr >+ 0U, // VPSHAWmr >+ 88U, // VPSHAWrm >+ 8U, // VPSHAWrr >+ 0U, // VPSHLBmr >+ 88U, // VPSHLBrm >+ 8U, // VPSHLBrr >+ 0U, // VPSHLDmr >+ 88U, // VPSHLDrm >+ 8U, // VPSHLDrr >+ 0U, // VPSHLQmr >+ 88U, // VPSHLQrm >+ 8U, // VPSHLQrr >+ 0U, // VPSHLWmr >+ 88U, // VPSHLWrm >+ 8U, // VPSHLWrr >+ 104U, // VPSHUFBYrm >+ 8U, // VPSHUFBYrr >+ 88U, // VPSHUFBrm >+ 8U, // VPSHUFBrr >+ 0U, // VPSHUFDYmi >+ 8U, // VPSHUFDYri >+ 0U, // VPSHUFDZmi >+ 8U, // VPSHUFDZri >+ 0U, // VPSHUFDmi >+ 8U, // VPSHUFDri >+ 0U, // VPSHUFHWYmi >+ 8U, // VPSHUFHWYri >+ 0U, // VPSHUFHWmi >+ 8U, // VPSHUFHWri >+ 0U, // VPSHUFLWYmi >+ 8U, // VPSHUFLWYri >+ 0U, // VPSHUFLWmi >+ 8U, // VPSHUFLWri >+ 104U, // VPSIGNBYrm >+ 8U, // VPSIGNBYrr >+ 88U, // VPSIGNBrm >+ 8U, // VPSIGNBrr >+ 104U, // VPSIGNDYrm >+ 8U, // VPSIGNDYrr >+ 88U, // VPSIGNDrm >+ 8U, // VPSIGNDrr >+ 104U, // VPSIGNWYrm >+ 8U, // VPSIGNWYrr >+ 88U, // VPSIGNWrm >+ 8U, // VPSIGNWrr >+ 8U, // VPSLLDQYri >+ 8U, // VPSLLDQri >+ 8U, // VPSLLDYri >+ 88U, // VPSLLDYrm >+ 8U, // VPSLLDYrr >+ 0U, // VPSLLDZmi >+ 2402U, // VPSLLDZmik >+ 8U, // VPSLLDZri >+ 8458U, // VPSLLDZrik >+ 88U, // VPSLLDZrm >+ 28938U, // VPSLLDZrmk >+ 8U, // VPSLLDZrr >+ 8458U, // VPSLLDZrrk >+ 8U, // VPSLLDri >+ 88U, // VPSLLDrm >+ 8U, // VPSLLDrr >+ 8U, // VPSLLQYri >+ 88U, // VPSLLQYrm >+ 8U, // VPSLLQYrr >+ 0U, // VPSLLQZmi >+ 2402U, // VPSLLQZmik >+ 8U, // VPSLLQZri >+ 8458U, // VPSLLQZrik >+ 88U, // VPSLLQZrm >+ 28938U, // VPSLLQZrmk >+ 8U, // VPSLLQZrr >+ 8458U, // VPSLLQZrrk >+ 8U, // VPSLLQri >+ 88U, // VPSLLQrm >+ 8U, // VPSLLQrr >+ 104U, // VPSLLVDYrm >+ 8U, // VPSLLVDYrr >+ 96U, // VPSLLVDZrm >+ 8U, // VPSLLVDZrr >+ 88U, // VPSLLVDrm >+ 8U, // VPSLLVDrr >+ 104U, // VPSLLVQYrm >+ 8U, // VPSLLVQYrr >+ 96U, // VPSLLVQZrm >+ 8U, // VPSLLVQZrr >+ 88U, // VPSLLVQrm >+ 8U, // VPSLLVQrr >+ 8U, // VPSLLWYri >+ 88U, // VPSLLWYrm >+ 8U, // VPSLLWYrr >+ 8U, // VPSLLWri >+ 88U, // VPSLLWrm >+ 8U, // VPSLLWrr >+ 8U, // VPSRADYri >+ 88U, // VPSRADYrm >+ 8U, // VPSRADYrr >+ 0U, // VPSRADZmi >+ 2402U, // VPSRADZmik >+ 8U, // VPSRADZri >+ 8458U, // VPSRADZrik >+ 88U, // VPSRADZrm >+ 28938U, // VPSRADZrmk >+ 8U, // VPSRADZrr >+ 8458U, // VPSRADZrrk >+ 8U, // VPSRADri >+ 88U, // VPSRADrm >+ 8U, // VPSRADrr >+ 0U, // VPSRAQZmi >+ 2402U, // VPSRAQZmik >+ 8U, // VPSRAQZri >+ 8458U, // VPSRAQZrik >+ 88U, // VPSRAQZrm >+ 28938U, // VPSRAQZrmk >+ 8U, // VPSRAQZrr >+ 8458U, // VPSRAQZrrk >+ 104U, // VPSRAVDYrm >+ 8U, // VPSRAVDYrr >+ 96U, // VPSRAVDZrm >+ 8U, // VPSRAVDZrr >+ 88U, // VPSRAVDrm >+ 8U, // VPSRAVDrr >+ 96U, // VPSRAVQZrm >+ 8U, // VPSRAVQZrr >+ 8U, // VPSRAWYri >+ 88U, // VPSRAWYrm >+ 8U, // VPSRAWYrr >+ 8U, // VPSRAWri >+ 88U, // VPSRAWrm >+ 8U, // VPSRAWrr >+ 8U, // VPSRLDQYri >+ 8U, // VPSRLDQri >+ 8U, // VPSRLDYri >+ 88U, // VPSRLDYrm >+ 8U, // VPSRLDYrr >+ 0U, // VPSRLDZmi >+ 2402U, // VPSRLDZmik >+ 8U, // VPSRLDZri >+ 8458U, // VPSRLDZrik >+ 88U, // VPSRLDZrm >+ 28938U, // VPSRLDZrmk >+ 8U, // VPSRLDZrr >+ 8458U, // VPSRLDZrrk >+ 8U, // VPSRLDri >+ 88U, // VPSRLDrm >+ 8U, // VPSRLDrr >+ 8U, // VPSRLQYri >+ 88U, // VPSRLQYrm >+ 8U, // VPSRLQYrr >+ 0U, // VPSRLQZmi >+ 2402U, // VPSRLQZmik >+ 8U, // VPSRLQZri >+ 8458U, // VPSRLQZrik >+ 88U, // VPSRLQZrm >+ 28938U, // VPSRLQZrmk >+ 8U, // VPSRLQZrr >+ 8458U, // VPSRLQZrrk >+ 8U, // VPSRLQri >+ 88U, // VPSRLQrm >+ 8U, // VPSRLQrr >+ 104U, // VPSRLVDYrm >+ 8U, // VPSRLVDYrr >+ 96U, // VPSRLVDZrm >+ 8U, // VPSRLVDZrr >+ 88U, // VPSRLVDrm >+ 8U, // VPSRLVDrr >+ 104U, // VPSRLVQYrm >+ 8U, // VPSRLVQYrr >+ 96U, // VPSRLVQZrm >+ 8U, // VPSRLVQZrr >+ 88U, // VPSRLVQrm >+ 8U, // VPSRLVQrr >+ 8U, // VPSRLWYri >+ 88U, // VPSRLWYrm >+ 8U, // VPSRLWYrr >+ 8U, // VPSRLWri >+ 88U, // VPSRLWrm >+ 8U, // VPSRLWrr >+ 104U, // VPSUBBYrm >+ 8U, // VPSUBBYrr >+ 88U, // VPSUBBrm >+ 8U, // VPSUBBrr >+ 104U, // VPSUBDYrm >+ 8U, // VPSUBDYrr >+ 96U, // VPSUBDZrm >+ 784U, // VPSUBDZrmb >+ 16682U, // VPSUBDZrmbk >+ 117002U, // VPSUBDZrmbkz >+ 20778U, // VPSUBDZrmk >+ 22794U, // VPSUBDZrmkz >+ 8U, // VPSUBDZrr >+ 298U, // VPSUBDZrrk >+ 8458U, // VPSUBDZrrkz >+ 88U, // VPSUBDrm >+ 8U, // VPSUBDrr >+ 104U, // VPSUBQYrm >+ 8U, // VPSUBQYrr >+ 96U, // VPSUBQZrm >+ 536U, // VPSUBQZrmb >+ 24874U, // VPSUBQZrmbk >+ 92426U, // VPSUBQZrmbkz >+ 20778U, // VPSUBQZrmk >+ 22794U, // VPSUBQZrmkz >+ 8U, // VPSUBQZrr >+ 298U, // VPSUBQZrrk >+ 8458U, // VPSUBQZrrkz >+ 88U, // VPSUBQrm >+ 8U, // VPSUBQrr >+ 104U, // VPSUBSBYrm >+ 8U, // VPSUBSBYrr >+ 88U, // VPSUBSBrm >+ 8U, // VPSUBSBrr >+ 104U, // VPSUBSWYrm >+ 8U, // VPSUBSWYrr >+ 88U, // VPSUBSWrm >+ 8U, // VPSUBSWrr >+ 104U, // VPSUBUSBYrm >+ 8U, // VPSUBUSBYrr >+ 88U, // VPSUBUSBrm >+ 8U, // VPSUBUSBrr >+ 104U, // VPSUBUSWYrm >+ 8U, // VPSUBUSWYrr >+ 88U, // VPSUBUSWrm >+ 8U, // VPSUBUSWrr >+ 104U, // VPSUBWYrm >+ 8U, // VPSUBWYrr >+ 88U, // VPSUBWrm >+ 8U, // VPSUBWrr >+ 72U, // VPTESTMDZrm >+ 8U, // VPTESTMDZrr >+ 72U, // VPTESTMQZrm >+ 8U, // VPTESTMQZrr >+ 72U, // VPTESTNMDZrm >+ 8U, // VPTESTNMDZrr >+ 72U, // VPTESTNMQZrm >+ 8U, // VPTESTNMQZrr >+ 0U, // VPTESTYrm >+ 0U, // VPTESTYrr >+ 0U, // VPTESTrm >+ 0U, // VPTESTrr >+ 104U, // VPUNPCKHBWYrm >+ 8U, // VPUNPCKHBWYrr >+ 88U, // VPUNPCKHBWrm >+ 8U, // VPUNPCKHBWrr >+ 104U, // VPUNPCKHDQYrm >+ 8U, // VPUNPCKHDQYrr >+ 96U, // VPUNPCKHDQZrm >+ 8U, // VPUNPCKHDQZrr >+ 88U, // VPUNPCKHDQrm >+ 8U, // VPUNPCKHDQrr >+ 104U, // VPUNPCKHQDQYrm >+ 8U, // VPUNPCKHQDQYrr >+ 96U, // VPUNPCKHQDQZrm >+ 8U, // VPUNPCKHQDQZrr >+ 88U, // VPUNPCKHQDQrm >+ 8U, // VPUNPCKHQDQrr >+ 104U, // VPUNPCKHWDYrm >+ 8U, // VPUNPCKHWDYrr >+ 88U, // VPUNPCKHWDrm >+ 8U, // VPUNPCKHWDrr >+ 104U, // VPUNPCKLBWYrm >+ 8U, // VPUNPCKLBWYrr >+ 88U, // VPUNPCKLBWrm >+ 8U, // VPUNPCKLBWrr >+ 104U, // VPUNPCKLDQYrm >+ 8U, // VPUNPCKLDQYrr >+ 96U, // VPUNPCKLDQZrm >+ 8U, // VPUNPCKLDQZrr >+ 88U, // VPUNPCKLDQrm >+ 8U, // VPUNPCKLDQrr >+ 104U, // VPUNPCKLQDQYrm >+ 8U, // VPUNPCKLQDQYrr >+ 96U, // VPUNPCKLQDQZrm >+ 8U, // VPUNPCKLQDQZrr >+ 88U, // VPUNPCKLQDQrm >+ 8U, // VPUNPCKLQDQrr >+ 104U, // VPUNPCKLWDYrm >+ 8U, // VPUNPCKLWDYrr >+ 88U, // VPUNPCKLWDrm >+ 8U, // VPUNPCKLWDrr >+ 96U, // VPXORDZrm >+ 784U, // VPXORDZrmb >+ 16682U, // VPXORDZrmbk >+ 117002U, // VPXORDZrmbkz >+ 20778U, // VPXORDZrmk >+ 22794U, // VPXORDZrmkz >+ 8U, // VPXORDZrr >+ 298U, // VPXORDZrrk >+ 8458U, // VPXORDZrrkz >+ 96U, // VPXORQZrm >+ 536U, // VPXORQZrmb >+ 24874U, // VPXORQZrmbk >+ 92426U, // VPXORQZrmbkz >+ 20778U, // VPXORQZrmk >+ 22794U, // VPXORQZrmkz >+ 8U, // VPXORQZrr >+ 298U, // VPXORQZrrk >+ 8458U, // VPXORQZrrkz >+ 104U, // VPXORYrm >+ 8U, // VPXORYrr >+ 88U, // VPXORrm >+ 8U, // VPXORrr >+ 0U, // VRCP14PDZm >+ 0U, // VRCP14PDZr >+ 0U, // VRCP14PSZm >+ 0U, // VRCP14PSZr >+ 48U, // VRCP14SDrm >+ 8U, // VRCP14SDrr >+ 56U, // VRCP14SSrm >+ 8U, // VRCP14SSrr >+ 0U, // VRCP28PDZm >+ 0U, // VRCP28PDZr >+ 3U, // VRCP28PDZrb >+ 0U, // VRCP28PSZm >+ 0U, // VRCP28PSZr >+ 3U, // VRCP28PSZrb >+ 48U, // VRCP28SDrm >+ 8U, // VRCP28SDrr >+ 1544U, // VRCP28SDrrb >+ 56U, // VRCP28SSrm >+ 8U, // VRCP28SSrr >+ 1544U, // VRCP28SSrrb >+ 0U, // VRCPPSYm >+ 0U, // VRCPPSYm_Int >+ 0U, // VRCPPSYr >+ 0U, // VRCPPSYr_Int >+ 0U, // VRCPPSm >+ 0U, // VRCPPSm_Int >+ 0U, // VRCPPSr >+ 0U, // VRCPPSr_Int >+ 56U, // VRCPSSm >+ 56U, // VRCPSSm_Int >+ 8U, // VRCPSSr >+ 0U, // VRNDSCALEPDZm >+ 8U, // VRNDSCALEPDZr >+ 0U, // VRNDSCALEPSZm >+ 8U, // VRNDSCALEPSZr >+ 48U, // VRNDSCALESDm >+ 8U, // VRNDSCALESDr >+ 56U, // VRNDSCALESSm >+ 8U, // VRNDSCALESSr >+ 0U, // VROUNDPDm >+ 8U, // VROUNDPDr >+ 0U, // VROUNDPSm >+ 8U, // VROUNDPSr >+ 2352U, // VROUNDSDm >+ 8456U, // VROUNDSDr >+ 8456U, // VROUNDSDr_Int >+ 2360U, // VROUNDSSm >+ 8456U, // VROUNDSSr >+ 8456U, // VROUNDSSr_Int >+ 0U, // VROUNDYPDm >+ 8U, // VROUNDYPDr >+ 0U, // VROUNDYPSm >+ 8U, // VROUNDYPSr >+ 0U, // VRSQRT14PDZm >+ 0U, // VRSQRT14PDZr >+ 0U, // VRSQRT14PSZm >+ 0U, // VRSQRT14PSZr >+ 48U, // VRSQRT14SDrm >+ 8U, // VRSQRT14SDrr >+ 56U, // VRSQRT14SSrm >+ 8U, // VRSQRT14SSrr >+ 0U, // VRSQRT28PDZm >+ 0U, // VRSQRT28PDZr >+ 3U, // VRSQRT28PDZrb >+ 0U, // VRSQRT28PSZm >+ 0U, // VRSQRT28PSZr >+ 3U, // VRSQRT28PSZrb >+ 48U, // VRSQRT28SDrm >+ 8U, // VRSQRT28SDrr >+ 1544U, // VRSQRT28SDrrb >+ 56U, // VRSQRT28SSrm >+ 8U, // VRSQRT28SSrr >+ 1544U, // VRSQRT28SSrrb >+ 0U, // VRSQRTPSYm >+ 0U, // VRSQRTPSYm_Int >+ 0U, // VRSQRTPSYr >+ 0U, // VRSQRTPSYr_Int >+ 0U, // VRSQRTPSm >+ 0U, // VRSQRTPSm_Int >+ 0U, // VRSQRTPSr >+ 0U, // VRSQRTPSr_Int >+ 56U, // VRSQRTSSm >+ 56U, // VRSQRTSSm_Int >+ 8U, // VRSQRTSSr >+ 0U, // VSCATTERDPDZmr >+ 0U, // VSCATTERDPSZmr >+ 0U, // VSCATTERPF0DPDm >+ 0U, // VSCATTERPF0DPSm >+ 0U, // VSCATTERPF0QPDm >+ 0U, // VSCATTERPF0QPSm >+ 0U, // VSCATTERPF1DPDm >+ 0U, // VSCATTERPF1DPSm >+ 0U, // VSCATTERPF1QPDm >+ 0U, // VSCATTERPF1QPSm >+ 0U, // VSCATTERQPDZmr >+ 0U, // VSCATTERQPSZmr >+ 2368U, // VSHUFPDYrmi >+ 8456U, // VSHUFPDYrri >+ 2376U, // VSHUFPDZrmi >+ 8456U, // VSHUFPDZrri >+ 2384U, // VSHUFPDrmi >+ 8456U, // VSHUFPDrri >+ 2368U, // VSHUFPSYrmi >+ 8456U, // VSHUFPSYrri >+ 2376U, // VSHUFPSZrmi >+ 8456U, // VSHUFPSZrri >+ 2384U, // VSHUFPSrmi >+ 8456U, // VSHUFPSrri >+ 0U, // VSQRTPDYm >+ 0U, // VSQRTPDYr >+ 0U, // VSQRTPDZrm >+ 0U, // VSQRTPDZrr >+ 0U, // VSQRTPDm >+ 0U, // VSQRTPDr >+ 0U, // VSQRTPSYm >+ 0U, // VSQRTPSYr >+ 0U, // VSQRTPSZrm >+ 0U, // VSQRTPSZrr >+ 0U, // VSQRTPSm >+ 0U, // VSQRTPSr >+ 48U, // VSQRTSDZm >+ 48U, // VSQRTSDZm_Int >+ 8U, // VSQRTSDZr >+ 8U, // VSQRTSDZr_Int >+ 48U, // VSQRTSDm >+ 48U, // VSQRTSDm_Int >+ 8U, // VSQRTSDr >+ 56U, // VSQRTSSZm >+ 56U, // VSQRTSSZm_Int >+ 8U, // VSQRTSSZr >+ 8U, // VSQRTSSZr_Int >+ 56U, // VSQRTSSm >+ 56U, // VSQRTSSm_Int >+ 8U, // VSQRTSSr >+ 0U, // VSTMXCSR >+ 64U, // VSUBPDYrm >+ 8U, // VSUBPDYrr >+ 72U, // VSUBPDZrm >+ 560U, // VSUBPDZrmb >+ 69898U, // VSUBPDZrmbk >+ 69898U, // VSUBPDZrmbkz >+ 6410U, // VSUBPDZrmk >+ 6410U, // VSUBPDZrmkz >+ 8U, // VSUBPDZrr >+ 8458U, // VSUBPDZrrk >+ 8458U, // VSUBPDZrrkz >+ 80U, // VSUBPDrm >+ 8U, // VSUBPDrr >+ 64U, // VSUBPSYrm >+ 8U, // VSUBPSYrr >+ 72U, // VSUBPSZrm >+ 824U, // VSUBPSZrmb >+ 108810U, // VSUBPSZrmbk >+ 108810U, // VSUBPSZrmbkz >+ 6410U, // VSUBPSZrmk >+ 6410U, // VSUBPSZrmkz >+ 8U, // VSUBPSZrr >+ 8458U, // VSUBPSZrrk >+ 8458U, // VSUBPSZrrkz >+ 80U, // VSUBPSrm >+ 8U, // VSUBPSrr >+ 48U, // VSUBSDZrm >+ 8U, // VSUBSDZrr >+ 48U, // VSUBSDrm >+ 48U, // VSUBSDrm_Int >+ 8U, // VSUBSDrr >+ 8U, // VSUBSDrr_Int >+ 56U, // VSUBSSZrm >+ 8U, // VSUBSSZrr >+ 56U, // VSUBSSrm >+ 56U, // VSUBSSrm_Int >+ 8U, // VSUBSSrr >+ 8U, // VSUBSSrr_Int >+ 0U, // VTESTPDYrm >+ 0U, // VTESTPDYrr >+ 0U, // VTESTPDrm >+ 0U, // VTESTPDrr >+ 0U, // VTESTPSYrm >+ 0U, // VTESTPSYrr >+ 0U, // VTESTPSrm >+ 0U, // VTESTPSrr >+ 0U, // VUCOMISDZrm >+ 0U, // VUCOMISDZrr >+ 0U, // VUCOMISDrm >+ 0U, // VUCOMISDrr >+ 0U, // VUCOMISSZrm >+ 0U, // VUCOMISSZrr >+ 0U, // VUCOMISSrm >+ 0U, // VUCOMISSrr >+ 64U, // VUNPCKHPDYrm >+ 8U, // VUNPCKHPDYrr >+ 72U, // VUNPCKHPDZrm >+ 8U, // VUNPCKHPDZrr >+ 80U, // VUNPCKHPDrm >+ 8U, // VUNPCKHPDrr >+ 64U, // VUNPCKHPSYrm >+ 8U, // VUNPCKHPSYrr >+ 72U, // VUNPCKHPSZrm >+ 8U, // VUNPCKHPSZrr >+ 80U, // VUNPCKHPSrm >+ 8U, // VUNPCKHPSrr >+ 64U, // VUNPCKLPDYrm >+ 8U, // VUNPCKLPDYrr >+ 72U, // VUNPCKLPDZrm >+ 8U, // VUNPCKLPDZrr >+ 80U, // VUNPCKLPDrm >+ 8U, // VUNPCKLPDrr >+ 64U, // VUNPCKLPSYrm >+ 8U, // VUNPCKLPSYrr >+ 72U, // VUNPCKLPSZrm >+ 8U, // VUNPCKLPSZrr >+ 80U, // VUNPCKLPSrm >+ 8U, // VUNPCKLPSrr >+ 64U, // VXORPDYrm >+ 8U, // VXORPDYrr >+ 80U, // VXORPDrm >+ 8U, // VXORPDrr >+ 64U, // VXORPSYrm >+ 8U, // VXORPSYrr >+ 80U, // VXORPSrm >+ 8U, // VXORPSrr >+ 0U, // VZEROALL >+ 0U, // VZEROUPPER >+ 0U, // V_SET0 >+ 0U, // V_SETALLONES >+ 0U, // W64ALLOCA >+ 0U, // WAIT >+ 0U, // WBINVD >+ 0U, // WIN_ALLOCA >+ 0U, // WIN_FTOL_32 >+ 0U, // WIN_FTOL_64 >+ 0U, // WRFSBASE >+ 0U, // WRFSBASE64 >+ 0U, // WRGSBASE >+ 0U, // WRGSBASE64 >+ 0U, // WRMSR >+ 0U, // XABORT >+ 0U, // XACQUIRE_PREFIX >+ 0U, // XADD16rm >+ 0U, // XADD16rr >+ 0U, // XADD32rm >+ 0U, // XADD32rr >+ 0U, // XADD64rm >+ 0U, // XADD64rr >+ 0U, // XADD8rm >+ 0U, // XADD8rr >+ 0U, // XBEGIN >+ 0U, // XBEGIN_4 >+ 0U, // XCHG16ar >+ 0U, // XCHG16rm >+ 0U, // XCHG16rr >+ 0U, // XCHG32ar >+ 0U, // XCHG32ar64 >+ 0U, // XCHG32rm >+ 0U, // XCHG32rr >+ 0U, // XCHG64ar >+ 0U, // XCHG64rm >+ 0U, // XCHG64rr >+ 0U, // XCHG8rm >+ 0U, // XCHG8rr >+ 0U, // XCH_F >+ 0U, // XCRYPTCBC >+ 0U, // XCRYPTCFB >+ 0U, // XCRYPTCTR >+ 0U, // XCRYPTECB >+ 0U, // XCRYPTOFB >+ 0U, // XEND >+ 0U, // XGETBV >+ 0U, // XLAT >+ 0U, // XOR16i16 >+ 0U, // XOR16mi >+ 0U, // XOR16mi8 >+ 0U, // XOR16mr >+ 0U, // XOR16ri >+ 0U, // XOR16ri8 >+ 0U, // XOR16rm >+ 0U, // XOR16rr >+ 0U, // XOR16rr_REV >+ 0U, // XOR32i32 >+ 0U, // XOR32mi >+ 0U, // XOR32mi8 >+ 0U, // XOR32mr >+ 0U, // XOR32ri >+ 0U, // XOR32ri8 >+ 0U, // XOR32rm >+ 0U, // XOR32rr >+ 0U, // XOR32rr_REV >+ 0U, // XOR64i32 >+ 0U, // XOR64mi32 >+ 0U, // XOR64mi8 >+ 0U, // XOR64mr >+ 0U, // XOR64ri32 >+ 0U, // XOR64ri8 >+ 0U, // XOR64rm >+ 0U, // XOR64rr >+ 0U, // XOR64rr_REV >+ 0U, // XOR8i8 >+ 0U, // XOR8mi >+ 0U, // XOR8mr >+ 0U, // XOR8ri >+ 0U, // XOR8ri8 >+ 0U, // XOR8rm >+ 0U, // XOR8rr >+ 0U, // XOR8rr_REV >+ 0U, // XORPDrm >+ 0U, // XORPDrr >+ 0U, // XORPSrm >+ 0U, // XORPSrr >+ 0U, // XRELEASE_PREFIX >+ 0U, // XRSTOR >+ 0U, // XRSTOR64 >+ 0U, // XSAVE >+ 0U, // XSAVE64 >+ 0U, // XSAVEOPT >+ 0U, // XSAVEOPT64 >+ 0U, // XSETBV >+ 0U, // XSHA1 >+ 0U, // XSHA256 >+ 0U, // XSTORE >+ 0U, // XTEST >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 32, 9, 0, >+ /* 18 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 32, 9, 0, >+ /* 36 */ 'k', 'a', 'n', 'd', 'b', 32, 9, 0, >+ /* 44 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'b', 32, 9, 0, >+ /* 56 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'b', 32, 9, 0, >+ /* 67 */ 'v', 'p', 'm', 'o', 'v', 'd', 'b', 32, 9, 0, >+ /* 77 */ 'k', 'a', 'n', 'd', 'n', 'b', 32, 9, 0, >+ /* 86 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'b', 32, 9, 0, >+ /* 98 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'b', 32, 9, 0, >+ /* 109 */ 'v', 'p', 'm', 'o', 'v', 'q', 'b', 32, 9, 0, >+ /* 119 */ 'k', 'o', 'r', 'b', 32, 9, 0, >+ /* 126 */ 'k', 'x', 'n', 'o', 'r', 'b', 32, 9, 0, >+ /* 135 */ 'k', 'x', 'o', 'r', 'b', 32, 9, 0, >+ /* 143 */ 'k', 'n', 'o', 't', 'b', 32, 9, 0, >+ /* 151 */ 'k', 'm', 'o', 'v', 'b', 32, 9, 0, >+ /* 159 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'd', 32, 9, 0, >+ /* 170 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'd', 32, 9, 0, >+ /* 181 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'w', '2', 'd', 32, 9, 0, >+ /* 199 */ 'v', 'p', 's', 'r', 'a', 'd', 32, 9, 0, >+ /* 208 */ 'v', 'p', 's', 'u', 'b', 'd', 32, 9, 0, >+ /* 217 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 32, 9, 0, >+ /* 229 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 32, 9, 0, >+ /* 241 */ 'v', 'p', 'a', 'd', 'd', 'd', 32, 9, 0, >+ /* 250 */ 'k', 'a', 'n', 'd', 'd', 32, 9, 0, >+ /* 258 */ 'v', 'p', 'a', 'n', 'd', 'd', 32, 9, 0, >+ /* 267 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 32, 9, 0, >+ /* 280 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'd', 32, 9, 0, >+ /* 294 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 32, 9, 0, >+ /* 304 */ 'v', 'p', 's', 'l', 'l', 'd', 32, 9, 0, >+ /* 313 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 32, 9, 0, >+ /* 323 */ 'v', 'p', 's', 'r', 'l', 'd', 32, 9, 0, >+ /* 332 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'd', 32, 9, 0, >+ /* 344 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'd', 32, 9, 0, >+ /* 356 */ 'v', 'p', 'e', 'r', 'm', 'd', 32, 9, 0, >+ /* 365 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'd', 32, 9, 0, >+ /* 376 */ 'k', 'a', 'n', 'd', 'n', 'd', 32, 9, 0, >+ /* 385 */ 'v', 'p', 'a', 'n', 'd', 'n', 'd', 32, 9, 0, >+ /* 395 */ 'v', 'a', 'l', 'i', 'g', 'n', 'd', 32, 9, 0, >+ /* 405 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 422 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 436 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 451 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 468 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 482 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 32, 9, 0, >+ /* 497 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 'd', 32, 9, 0, >+ /* 509 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 32, 9, 0, >+ /* 521 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 'd', 32, 9, 0, >+ /* 534 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 32, 9, 0, >+ /* 546 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 'd', 32, 9, 0, >+ /* 558 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 575 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 589 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 604 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 621 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 635 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 32, 9, 0, >+ /* 650 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 'd', 32, 9, 0, >+ /* 661 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 'd', 32, 9, 0, >+ /* 674 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 'd', 32, 9, 0, >+ /* 685 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 'd', 32, 9, 0, >+ /* 698 */ 'v', 's', 'u', 'b', 'p', 'd', 32, 9, 0, >+ /* 707 */ 'v', 'a', 'd', 'd', 'p', 'd', 32, 9, 0, >+ /* 716 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 32, 9, 0, >+ /* 729 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 'd', 32, 9, 0, >+ /* 743 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 'd', 32, 9, 0, >+ /* 757 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 32, 9, 0, >+ /* 767 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 32, 9, 0, >+ /* 779 */ 'v', 'm', 'u', 'l', 'p', 'd', 32, 9, 0, >+ /* 788 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 'd', 32, 9, 0, >+ /* 800 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 32, 9, 0, >+ /* 810 */ 'v', 'm', 'i', 'n', 'p', 'd', 32, 9, 0, >+ /* 819 */ 'v', 'c', 'm', 'p', 'p', 'd', 32, 9, 0, >+ /* 828 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 32, 9, 0, >+ /* 841 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 'd', 32, 9, 0, >+ /* 855 */ 'v', 'd', 'i', 'v', 'p', 'd', 32, 9, 0, >+ /* 864 */ 'v', 'm', 'a', 'x', 'p', 'd', 32, 9, 0, >+ /* 873 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 32, 9, 0, >+ /* 886 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'd', 32, 9, 0, >+ /* 900 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'd', 32, 9, 0, >+ /* 912 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'd', 32, 9, 0, >+ /* 923 */ 'v', 'p', 'm', 'o', 'v', 'q', 'd', 32, 9, 0, >+ /* 933 */ 'k', 'o', 'r', 'd', 32, 9, 0, >+ /* 940 */ 'k', 'x', 'n', 'o', 'r', 'd', 32, 9, 0, >+ /* 949 */ 'v', 'p', 'o', 'r', 'd', 32, 9, 0, >+ /* 957 */ 'k', 'x', 'o', 'r', 'd', 32, 9, 0, >+ /* 965 */ 'v', 'p', 'x', 'o', 'r', 'd', 32, 9, 0, >+ /* 974 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 32, 9, 0, >+ /* 986 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 32, 9, 0, >+ /* 999 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1013 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1028 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1042 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 32, 9, 0, >+ /* 1057 */ 'v', 'r', 'c', 'p', '1', '4', 's', 'd', 32, 9, 0, >+ /* 1068 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 'd', 32, 9, 0, >+ /* 1081 */ 'v', 'r', 'c', 'p', '2', '8', 's', 'd', 32, 9, 0, >+ /* 1092 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 'd', 32, 9, 0, >+ /* 1105 */ 'v', 'p', 'a', 'b', 's', 'd', 32, 9, 0, >+ /* 1114 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 'd', 32, 9, 0, >+ /* 1128 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 32, 9, 0, >+ /* 1138 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 32, 9, 0, >+ /* 1153 */ 'v', 'm', 'o', 'v', 's', 'd', 32, 9, 0, >+ /* 1162 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 32, 9, 0, >+ /* 1172 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'd', 32, 9, 0, >+ /* 1186 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'd', 32, 9, 0, >+ /* 1197 */ 'k', 'n', 'o', 't', 'd', 32, 9, 0, >+ /* 1205 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 32, 9, 0, >+ /* 1220 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 32, 9, 0, >+ /* 1230 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 32, 9, 0, >+ /* 1240 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 32, 9, 0, >+ /* 1250 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 32, 9, 0, >+ /* 1260 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 32, 9, 0, >+ /* 1270 */ 'k', 'm', 'o', 'v', 'd', 32, 9, 0, >+ /* 1278 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 32, 9, 0, >+ /* 1290 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 32, 9, 0, >+ /* 1302 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 32, 9, 0, >+ /* 1314 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 32, 9, 0, >+ /* 1327 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 32, 9, 0, >+ /* 1339 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 32, 9, 0, >+ /* 1352 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 32, 9, 0, >+ /* 1364 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1378 */ 'v', 'c', 'v', 't', 's', 'd', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1391 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1405 */ 'v', 'c', 'v', 't', 's', 's', '2', 'u', 's', 'i', 32, 9, 0, >+ /* 1418 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 32, 9, 0, >+ /* 1429 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 32, 9, 0, >+ /* 1441 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 32, 9, 0, >+ /* 1453 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'm', 'b', '2', 'q', 32, 9, 0, >+ /* 1471 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'q', 32, 9, 0, >+ /* 1482 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'q', 32, 9, 0, >+ /* 1493 */ 'v', 'p', 's', 'r', 'a', 'q', 32, 9, 0, >+ /* 1502 */ 'v', 'p', 's', 'u', 'b', 'q', 32, 9, 0, >+ /* 1511 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 32, 9, 0, >+ /* 1523 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 32, 9, 0, >+ /* 1535 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 32, 9, 0, >+ /* 1548 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 32, 9, 0, >+ /* 1560 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 32, 9, 0, >+ /* 1573 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 32, 9, 0, >+ /* 1585 */ 'v', 'p', 'a', 'd', 'd', 'q', 32, 9, 0, >+ /* 1594 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 32, 9, 0, >+ /* 1607 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 32, 9, 0, >+ /* 1620 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 32, 9, 0, >+ /* 1630 */ 'k', 'a', 'n', 'd', 'q', 32, 9, 0, >+ /* 1638 */ 'v', 'p', 'a', 'n', 'd', 'q', 32, 9, 0, >+ /* 1647 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 32, 9, 0, >+ /* 1661 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 32, 9, 0, >+ /* 1675 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 32, 9, 0, >+ /* 1688 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'q', 32, 9, 0, >+ /* 1702 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1716 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1729 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1743 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'u', 'd', 'q', 32, 9, 0, >+ /* 1756 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 32, 9, 0, >+ /* 1767 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 32, 9, 0, >+ /* 1779 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 32, 9, 0, >+ /* 1791 */ 'v', 'p', 's', 'l', 'l', 'q', 32, 9, 0, >+ /* 1800 */ 'v', 'p', 's', 'r', 'l', 'q', 32, 9, 0, >+ /* 1809 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'm', 'q', 32, 9, 0, >+ /* 1821 */ 'v', 'p', 't', 'e', 's', 't', 'n', 'm', 'q', 32, 9, 0, >+ /* 1833 */ 'v', 'p', 'e', 'r', 'm', 'q', 32, 9, 0, >+ /* 1842 */ 'v', 'p', 't', 'e', 's', 't', 'm', 'q', 32, 9, 0, >+ /* 1853 */ 'k', 'a', 'n', 'd', 'n', 'q', 32, 9, 0, >+ /* 1862 */ 'v', 'p', 'a', 'n', 'd', 'n', 'q', 32, 9, 0, >+ /* 1872 */ 'v', 'a', 'l', 'i', 'g', 'n', 'q', 32, 9, 0, >+ /* 1882 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 32, 9, 0, >+ /* 1895 */ 'v', 'p', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'q', 32, 9, 0, >+ /* 1909 */ 'k', 'o', 'r', 'q', 32, 9, 0, >+ /* 1916 */ 'k', 'x', 'n', 'o', 'r', 'q', 32, 9, 0, >+ /* 1925 */ 'v', 'p', 'o', 'r', 'q', 32, 9, 0, >+ /* 1933 */ 'k', 'x', 'o', 'r', 'q', 32, 9, 0, >+ /* 1941 */ 'v', 'p', 'x', 'o', 'r', 'q', 32, 9, 0, >+ /* 1950 */ 'v', 'p', 'a', 'b', 's', 'q', 32, 9, 0, >+ /* 1959 */ 'v', 'p', 'm', 'i', 'n', 's', 'q', 32, 9, 0, >+ /* 1969 */ 'v', 'p', 'm', 'a', 'x', 's', 'q', 32, 9, 0, >+ /* 1979 */ 'v', 'p', 'c', 'o', 'n', 'f', 'l', 'i', 'c', 't', 'q', 32, 9, 0, >+ /* 1993 */ 'v', 'p', 'l', 'z', 'c', 'n', 't', 'q', 32, 9, 0, >+ /* 2004 */ 'k', 'n', 'o', 't', 'q', 32, 9, 0, >+ /* 2012 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 32, 9, 0, >+ /* 2027 */ 'v', 'p', 'm', 'i', 'n', 'u', 'q', 32, 9, 0, >+ /* 2037 */ 'v', 'p', 'm', 'a', 'x', 'u', 'q', 32, 9, 0, >+ /* 2047 */ 'v', 'p', 's', 'r', 'a', 'v', 'q', 32, 9, 0, >+ /* 2057 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 32, 9, 0, >+ /* 2067 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 32, 9, 0, >+ /* 2077 */ 'k', 'm', 'o', 'v', 'q', 32, 9, 0, >+ /* 2085 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 32, 9, 0, >+ /* 2097 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 32, 9, 0, >+ /* 2109 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2126 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2140 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2155 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2172 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2186 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 32, 9, 0, >+ /* 2201 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 32, 9, 0, >+ /* 2213 */ 'v', 'p', 'e', 'r', 'm', 'i', '2', 'p', 's', 32, 9, 0, >+ /* 2225 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 32, 9, 0, >+ /* 2237 */ 'v', 'c', 'v', 't', 'u', 'd', 'q', '2', 'p', 's', 32, 9, 0, >+ /* 2250 */ 'v', 'p', 'e', 'r', 'm', 't', '2', 'p', 's', 32, 9, 0, >+ /* 2262 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2279 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2293 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2308 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2325 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2339 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 32, 9, 0, >+ /* 2354 */ 'v', 'r', 'c', 'p', '1', '4', 'p', 's', 32, 9, 0, >+ /* 2365 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 'p', 's', 32, 9, 0, >+ /* 2378 */ 'v', 'r', 'c', 'p', '2', '8', 'p', 's', 32, 9, 0, >+ /* 2389 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 'p', 's', 32, 9, 0, >+ /* 2402 */ 'v', 's', 'u', 'b', 'p', 's', 32, 9, 0, >+ /* 2411 */ 'v', 'a', 'd', 'd', 'p', 's', 32, 9, 0, >+ /* 2420 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 32, 9, 0, >+ /* 2433 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'd', 'p', 's', 32, 9, 0, >+ /* 2447 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 'p', 's', 32, 9, 0, >+ /* 2461 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 32, 9, 0, >+ /* 2471 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 32, 9, 0, >+ /* 2483 */ 'v', 'm', 'u', 'l', 'p', 's', 32, 9, 0, >+ /* 2492 */ 'v', 'b', 'l', 'e', 'n', 'd', 'm', 'p', 's', 32, 9, 0, >+ /* 2504 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 32, 9, 0, >+ /* 2514 */ 'v', 'm', 'i', 'n', 'p', 's', 32, 9, 0, >+ /* 2523 */ 'v', 'c', 'm', 'p', 'p', 's', 32, 9, 0, >+ /* 2532 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 32, 9, 0, >+ /* 2545 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'q', 'p', 's', 32, 9, 0, >+ /* 2559 */ 'v', 'd', 'i', 'v', 'p', 's', 32, 9, 0, >+ /* 2568 */ 'v', 'm', 'a', 'x', 'p', 's', 32, 9, 0, >+ /* 2577 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 32, 9, 0, >+ /* 2589 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 32, 9, 0, >+ /* 2602 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2616 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2631 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2645 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 32, 9, 0, >+ /* 2660 */ 'v', 'r', 'c', 'p', '1', '4', 's', 's', 32, 9, 0, >+ /* 2671 */ 'v', 'r', 's', 'q', 'r', 't', '1', '4', 's', 's', 32, 9, 0, >+ /* 2684 */ 'v', 'r', 'c', 'p', '2', '8', 's', 's', 32, 9, 0, >+ /* 2695 */ 'v', 'r', 's', 'q', 'r', 't', '2', '8', 's', 's', 32, 9, 0, >+ /* 2708 */ 'v', 'r', 'n', 'd', 's', 'c', 'a', 'l', 'e', 's', 's', 32, 9, 0, >+ /* 2722 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 32, 9, 0, >+ /* 2737 */ 'v', 'm', 'o', 'v', 's', 's', 32, 9, 0, >+ /* 2746 */ 'k', 'u', 'n', 'p', 'c', 'k', 'b', 'w', 32, 9, 0, >+ /* 2757 */ 'k', 'a', 'n', 'd', 'w', 32, 9, 0, >+ /* 2765 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'd', 'w', 32, 9, 0, >+ /* 2777 */ 'v', 'p', 'm', 'o', 'v', 's', 'd', 'w', 32, 9, 0, >+ /* 2788 */ 'v', 'p', 'm', 'o', 'v', 'd', 'w', 32, 9, 0, >+ /* 2798 */ 'k', 's', 'h', 'i', 'f', 't', 'l', 'w', 32, 9, 0, >+ /* 2809 */ 'k', 'a', 'n', 'd', 'n', 'w', 32, 9, 0, >+ /* 2818 */ 'v', 'p', 'm', 'o', 'v', 'u', 's', 'q', 'w', 32, 9, 0, >+ /* 2830 */ 'v', 'p', 'm', 'o', 'v', 's', 'q', 'w', 32, 9, 0, >+ /* 2841 */ 'v', 'p', 'm', 'o', 'v', 'q', 'w', 32, 9, 0, >+ /* 2851 */ 'k', 'o', 'r', 'w', 32, 9, 0, >+ /* 2858 */ 'k', 'x', 'n', 'o', 'r', 'w', 32, 9, 0, >+ /* 2867 */ 'k', 'x', 'o', 'r', 'w', 32, 9, 0, >+ /* 2875 */ 'k', 's', 'h', 'i', 'f', 't', 'r', 'w', 32, 9, 0, >+ /* 2886 */ 'k', 'n', 'o', 't', 'w', 32, 9, 0, >+ /* 2894 */ 'k', 'o', 'r', 't', 'e', 's', 't', 'w', 32, 9, 0, >+ /* 2905 */ 'k', 'm', 'o', 'v', 'w', 32, 9, 0, >+ /* 2913 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '0', 9, 0, >+ /* 2925 */ 's', 'h', 'a', '1', 'm', 's', 'g', '1', 9, 0, >+ /* 2935 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '1', 9, 0, >+ /* 2947 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '1', 9, 0, >+ /* 2959 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '1', 9, 0, >+ /* 2969 */ 'p', 'f', 'r', 's', 'q', 'i', 't', '1', 9, 0, >+ /* 2979 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '3', '2', 9, 0, >+ /* 2990 */ 'c', 'r', 'c', '3', '2', 9, 0, >+ /* 2997 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '3', '2', 9, 0, >+ /* 3008 */ 's', 'h', 'a', '1', 'm', 's', 'g', '2', 9, 0, >+ /* 3018 */ 's', 'h', 'a', '2', '5', '6', 'm', 's', 'g', '2', 9, 0, >+ /* 3030 */ 's', 'h', 'a', '2', '5', '6', 'r', 'n', 'd', 's', '2', 9, 0, >+ /* 3043 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 't', '2', 9, 0, >+ /* 3055 */ 'p', 'f', 'r', 'c', 'p', 'i', 't', '2', 9, 0, >+ /* 3065 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', '6', '4', 9, 0, >+ /* 3076 */ 'f', 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, >+ /* 3086 */ 'f', 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, >+ /* 3097 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, >+ /* 3109 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '6', '4', 9, 0, >+ /* 3120 */ 's', 'h', 'a', '1', 'r', 'n', 'd', 's', '4', 9, 0, >+ /* 3131 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '3', '2', 'x', '4', 9, 0, >+ /* 3146 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '3', '2', 'x', '4', 9, 0, >+ /* 3160 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '3', '2', 'x', '4', 9, 0, >+ /* 3175 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '3', '2', 'x', '4', 9, 0, >+ /* 3189 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '6', '4', 'x', '4', 9, 0, >+ /* 3204 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '6', '4', 'x', '4', 9, 0, >+ /* 3218 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '6', '4', 'x', '4', 9, 0, >+ /* 3233 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '6', '4', 'x', '4', 9, 0, >+ /* 3247 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '1', '6', 9, 0, >+ /* 3258 */ 'v', 'p', 'e', 'r', 'm', '2', 'f', '1', '2', '8', 9, 0, >+ /* 3270 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3284 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3297 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'f', '1', '2', '8', 9, 0, >+ /* 3313 */ 'v', 'p', 'e', 'r', 'm', '2', 'i', '1', '2', '8', 9, 0, >+ /* 3325 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3339 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3352 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '1', '2', '8', 9, 0, >+ /* 3368 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', '8', 9, 0, >+ /* 3378 */ 'l', 'e', 'a', 9, 0, >+ /* 3383 */ 'j', 'a', 9, 0, >+ /* 3387 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 'a', 9, 0, >+ /* 3398 */ 'v', 'm', 'o', 'v', 'd', 'q', 'a', 9, 0, >+ /* 3407 */ 's', 'e', 't', 'a', 9, 0, >+ /* 3413 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 'n', 't', 'a', 9, 0, >+ /* 3426 */ 'c', 'm', 'o', 'v', 'a', 9, 0, >+ /* 3433 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, >+ /* 3445 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, >+ /* 3456 */ 'v', 'p', 's', 'h', 'a', 'b', 9, 0, >+ /* 3464 */ 's', 'b', 'b', 9, 0, >+ /* 3469 */ 'v', 'p', 's', 'u', 'b', 'b', 9, 0, >+ /* 3477 */ 'v', 'p', 'a', 'd', 'd', 'b', 9, 0, >+ /* 3485 */ 'v', 'p', 's', 'h', 'u', 'f', 'b', 9, 0, >+ /* 3494 */ 'v', 'p', 'a', 'v', 'g', 'b', 9, 0, >+ /* 3502 */ 'j', 'b', 9, 0, >+ /* 3506 */ 'v', 'p', 'm', 'o', 'v', 'm', 's', 'k', 'b', 9, 0, >+ /* 3517 */ 'v', 'p', 's', 'h', 'l', 'b', 9, 0, >+ /* 3525 */ 'v', 'p', 'c', 'o', 'm', 'b', 9, 0, >+ /* 3533 */ 'v', 'p', 's', 'i', 'g', 'n', 'b', 9, 0, >+ /* 3542 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'b', 9, 0, >+ /* 3552 */ 'v', 'p', 'i', 'n', 's', 'r', 'b', 9, 0, >+ /* 3561 */ 'v', 'p', 'e', 'x', 't', 'r', 'b', 9, 0, >+ /* 3570 */ 'v', 'p', 'a', 'b', 's', 'b', 9, 0, >+ /* 3578 */ 'v', 'p', 's', 'u', 'b', 's', 'b', 9, 0, >+ /* 3587 */ 'v', 'p', 'a', 'd', 'd', 's', 'b', 9, 0, >+ /* 3596 */ 'v', 'p', 'm', 'i', 'n', 's', 'b', 9, 0, >+ /* 3605 */ 's', 't', 'o', 's', 'b', 9, 0, >+ /* 3612 */ 'c', 'm', 'p', 's', 'b', 9, 0, >+ /* 3619 */ 'v', 'p', 's', 'u', 'b', 'u', 's', 'b', 9, 0, >+ /* 3629 */ 'v', 'p', 'a', 'd', 'd', 'u', 's', 'b', 9, 0, >+ /* 3639 */ 'p', 'a', 'v', 'g', 'u', 's', 'b', 9, 0, >+ /* 3648 */ 'm', 'o', 'v', 's', 'b', 9, 0, >+ /* 3655 */ 'v', 'p', 'm', 'a', 'x', 's', 'b', 9, 0, >+ /* 3664 */ 's', 'e', 't', 'b', 9, 0, >+ /* 3670 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'b', 9, 0, >+ /* 3680 */ 'v', 'p', 'r', 'o', 't', 'b', 9, 0, >+ /* 3688 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'b', 9, 0, >+ /* 3702 */ 'v', 'p', 'c', 'o', 'm', 'u', 'b', 9, 0, >+ /* 3711 */ 'v', 'p', 'm', 'i', 'n', 'u', 'b', 9, 0, >+ /* 3720 */ 'p', 'f', 's', 'u', 'b', 9, 0, >+ /* 3727 */ 'f', 'i', 's', 'u', 'b', 9, 0, >+ /* 3734 */ 'v', 'p', 'm', 'a', 'x', 'u', 'b', 9, 0, >+ /* 3743 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'v', 'b', 9, 0, >+ /* 3754 */ 'c', 'm', 'o', 'v', 'b', 9, 0, >+ /* 3761 */ 'v', 'p', 'a', 'c', 'k', 's', 's', 'w', 'b', 9, 0, >+ /* 3772 */ 'v', 'p', 'a', 'c', 'k', 'u', 's', 'w', 'b', 9, 0, >+ /* 3783 */ 'p', 'f', 'a', 'c', 'c', 9, 0, >+ /* 3790 */ 'p', 'f', 'n', 'a', 'c', 'c', 9, 0, >+ /* 3798 */ 'p', 'f', 'p', 'n', 'a', 'c', 'c', 9, 0, >+ /* 3807 */ 'a', 'd', 'c', 9, 0, >+ /* 3812 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 9, 0, >+ /* 3821 */ 'b', 'l', 'c', 'i', 'c', 9, 0, >+ /* 3828 */ 'b', 'l', 's', 'i', 'c', 9, 0, >+ /* 3835 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, >+ /* 3843 */ 'v', 'a', 'e', 's', 'i', 'm', 'c', 9, 0, >+ /* 3852 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 9, 0, >+ /* 3861 */ 'i', 'n', 'c', 9, 0, >+ /* 3866 */ 'b', 't', 'c', 9, 0, >+ /* 3871 */ 'a', 'a', 'd', 9, 0, >+ /* 3876 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, >+ /* 3884 */ 'v', 'p', 's', 'h', 'a', 'd', 9, 0, >+ /* 3892 */ 'v', 'p', 's', 'r', 'a', 'd', 9, 0, >+ /* 3900 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'd', 9, 0, >+ /* 3910 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'd', 9, 0, >+ /* 3921 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 9, 0, >+ /* 3930 */ 'v', 'p', 's', 'u', 'b', 'd', 9, 0, >+ /* 3938 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'd', 9, 0, >+ /* 3949 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'd', 9, 0, >+ /* 3960 */ 'p', 'f', 'a', 'd', 'd', 9, 0, >+ /* 3967 */ 'f', 'i', 'a', 'd', 'd', 9, 0, >+ /* 3974 */ 'x', 'a', 'd', 'd', 9, 0, >+ /* 3980 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 9, 0, >+ /* 3989 */ 'v', 'p', 'a', 'd', 'd', 'd', 9, 0, >+ /* 3997 */ 'v', 'p', 'b', 'l', 'e', 'n', 'd', 'd', 9, 0, >+ /* 4007 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'd', 9, 0, >+ /* 4019 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'd', 9, 0, >+ /* 4029 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'd', 9, 0, >+ /* 4040 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, >+ /* 4048 */ 'p', 'i', '2', 'f', 'd', 9, 0, >+ /* 4055 */ 'v', 'p', 's', 'h', 'u', 'f', 'd', 9, 0, >+ /* 4064 */ 'p', 'f', '2', 'i', 'd', 9, 0, >+ /* 4071 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, >+ /* 4080 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, >+ /* 4089 */ 'f', 'b', 'l', 'd', 9, 0, >+ /* 4095 */ 'f', 'l', 'd', 9, 0, >+ /* 4100 */ 'v', 'p', 's', 'h', 'l', 'd', 9, 0, >+ /* 4108 */ 'f', 'i', 'l', 'd', 9, 0, >+ /* 4114 */ 'v', 'p', 's', 'l', 'l', 'd', 9, 0, >+ /* 4122 */ 'v', 'p', 'm', 'u', 'l', 'l', 'd', 9, 0, >+ /* 4131 */ 'v', 'p', 's', 'r', 'l', 'd', 9, 0, >+ /* 4139 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, >+ /* 4148 */ 'v', 'p', 'c', 'o', 'm', 'd', 9, 0, >+ /* 4156 */ 'v', 'p', 'e', 'r', 'm', 'd', 9, 0, >+ /* 4164 */ 'v', 'p', 'a', 'n', 'd', 9, 0, >+ /* 4171 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, >+ /* 4179 */ 'v', 'p', 's', 'i', 'g', 'n', 'd', 9, 0, >+ /* 4188 */ 'b', 'o', 'u', 'n', 'd', 9, 0, >+ /* 4195 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4211 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4224 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4238 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4254 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4267 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 'd', 9, 0, >+ /* 4281 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4297 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4310 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4324 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4340 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4353 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 'd', 9, 0, >+ /* 4367 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 'd', 9, 0, >+ /* 4377 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 'd', 9, 0, >+ /* 4389 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 'd', 9, 0, >+ /* 4400 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'd', 9, 0, >+ /* 4411 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4427 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4440 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4454 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4470 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4483 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 'd', 9, 0, >+ /* 4497 */ 'v', 'm', 'o', 'v', 'a', 'p', 'd', 9, 0, >+ /* 4506 */ 'p', 's', 'w', 'a', 'p', 'd', 9, 0, >+ /* 4514 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4527 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4538 */ 'v', 'h', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4547 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4557 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4568 */ 'v', 's', 'u', 'b', 'p', 'd', 9, 0, >+ /* 4576 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4589 */ 'v', 'h', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4598 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4608 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4619 */ 'v', 'a', 'd', 'd', 'p', 'd', 9, 0, >+ /* 4627 */ 'v', 'a', 'n', 'd', 'p', 'd', 9, 0, >+ /* 4635 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 'd', 9, 0, >+ /* 4645 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 'd', 9, 0, >+ /* 4655 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 'd', 9, 0, >+ /* 4667 */ 'v', 's', 'h', 'u', 'f', 'p', 'd', 9, 0, >+ /* 4676 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 'd', 9, 0, >+ /* 4687 */ 'v', 'm', 'o', 'v', 'h', 'p', 'd', 9, 0, >+ /* 4696 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 'd', 9, 0, >+ /* 4707 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 'd', 9, 0, >+ /* 4718 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 'd', 9, 0, >+ /* 4729 */ 'v', 'm', 'u', 'l', 'p', 'd', 9, 0, >+ /* 4737 */ 'v', 'm', 'o', 'v', 'l', 'p', 'd', 9, 0, >+ /* 4746 */ 'v', 'p', 'c', 'm', 'p', 'd', 9, 0, >+ /* 4754 */ 'v', 'p', 'e', 'r', 'm', 'p', 'd', 9, 0, >+ /* 4763 */ 'v', 'a', 'n', 'd', 'n', 'p', 'd', 9, 0, >+ /* 4772 */ 'v', 'm', 'i', 'n', 'p', 'd', 9, 0, >+ /* 4780 */ 'v', 'd', 'p', 'p', 'd', 9, 0, >+ /* 4787 */ 'v', 'c', 'm', 'p', 'p', 'd', 9, 0, >+ /* 4795 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 'd', 9, 0, >+ /* 4807 */ 'v', 'o', 'r', 'p', 'd', 9, 0, >+ /* 4814 */ 'v', 'x', 'o', 'r', 'p', 'd', 9, 0, >+ /* 4822 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 'd', 9, 0, >+ /* 4832 */ 'v', 's', 'q', 'r', 't', 'p', 'd', 9, 0, >+ /* 4841 */ 'v', 't', 'e', 's', 't', 'p', 'd', 9, 0, >+ /* 4850 */ 'v', 'm', 'o', 'v', 'u', 'p', 'd', 9, 0, >+ /* 4859 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 'd', 9, 0, >+ /* 4870 */ 'v', 'd', 'i', 'v', 'p', 'd', 9, 0, >+ /* 4878 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 'd', 9, 0, >+ /* 4890 */ 'v', 'm', 'a', 'x', 'p', 'd', 9, 0, >+ /* 4898 */ 'v', 'f', 'r', 'c', 'z', 'p', 'd', 9, 0, >+ /* 4907 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'd', 9, 0, >+ /* 4917 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'd', 9, 0, >+ /* 4929 */ 's', 'h', 'r', 'd', 9, 0, >+ /* 4935 */ 'v', 'p', 'i', 'n', 's', 'r', 'd', 9, 0, >+ /* 4944 */ 'v', 'p', 'e', 'x', 't', 'r', 'd', 9, 0, >+ /* 4953 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, >+ /* 4966 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 'd', 9, 0, >+ /* 4980 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, >+ /* 4993 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 'd', 9, 0, >+ /* 5007 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5020 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5034 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5047 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 'd', 9, 0, >+ /* 5061 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 'd', 9, 0, >+ /* 5072 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 'd', 9, 0, >+ /* 5084 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'd', 9, 0, >+ /* 5095 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5108 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5122 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5135 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 'd', 9, 0, >+ /* 5149 */ 'v', 'p', 'a', 'b', 's', 'd', 9, 0, >+ /* 5157 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5167 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5178 */ 'v', 's', 'u', 'b', 's', 'd', 9, 0, >+ /* 5186 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5196 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5207 */ 'v', 'a', 'd', 'd', 's', 'd', 9, 0, >+ /* 5215 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 'd', 9, 0, >+ /* 5225 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, >+ /* 5235 */ 'v', 'c', 'o', 'm', 'i', 's', 'd', 9, 0, >+ /* 5244 */ 'v', 'm', 'u', 'l', 's', 'd', 9, 0, >+ /* 5252 */ 'v', 'p', 'm', 'i', 'n', 's', 'd', 9, 0, >+ /* 5261 */ 'v', 'm', 'i', 'n', 's', 'd', 9, 0, >+ /* 5269 */ 's', 't', 'o', 's', 'd', 9, 0, >+ /* 5276 */ 'v', 'c', 'm', 'p', 's', 'd', 9, 0, >+ /* 5284 */ 'm', 'o', 'v', 'n', 't', 's', 'd', 9, 0, >+ /* 5293 */ 'v', 's', 'q', 'r', 't', 's', 'd', 9, 0, >+ /* 5302 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 'd', 9, 0, >+ /* 5316 */ 'v', 'd', 'i', 'v', 's', 'd', 9, 0, >+ /* 5324 */ 'v', 'm', 'o', 'v', 's', 'd', 9, 0, >+ /* 5332 */ 'v', 'p', 'm', 'a', 'x', 's', 'd', 9, 0, >+ /* 5341 */ 'v', 'm', 'a', 'x', 's', 'd', 9, 0, >+ /* 5349 */ 'v', 'f', 'r', 'c', 'z', 's', 'd', 9, 0, >+ /* 5358 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'd', 9, 0, >+ /* 5368 */ 'v', 'p', 'r', 'o', 't', 'd', 9, 0, >+ /* 5376 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'd', 9, 0, >+ /* 5390 */ 'v', 'p', 'c', 'o', 'm', 'u', 'd', 9, 0, >+ /* 5399 */ 'v', 'p', 'm', 'i', 'n', 'u', 'd', 9, 0, >+ /* 5408 */ 'v', 'p', 'c', 'm', 'p', 'u', 'd', 9, 0, >+ /* 5417 */ 'v', 'p', 'm', 'a', 'x', 'u', 'd', 9, 0, >+ /* 5426 */ 'v', 'p', 's', 'r', 'a', 'v', 'd', 9, 0, >+ /* 5435 */ 'v', 'p', 's', 'l', 'l', 'v', 'd', 9, 0, >+ /* 5444 */ 'v', 'p', 's', 'r', 'l', 'v', 'd', 9, 0, >+ /* 5453 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 9, 0, >+ /* 5465 */ 'v', 'm', 'o', 'v', 'd', 9, 0, >+ /* 5472 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 'd', 9, 0, >+ /* 5482 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'd', 9, 0, >+ /* 5492 */ 'v', 'p', 'm', 'a', 'd', 'd', 'w', 'd', 9, 0, >+ /* 5502 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'w', 'd', 9, 0, >+ /* 5514 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'w', 'd', 9, 0, >+ /* 5526 */ 'v', 'p', 'm', 'a', 'c', 's', 'w', 'd', 9, 0, >+ /* 5536 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 'w', 'd', 9, 0, >+ /* 5547 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'w', 'd', 9, 0, >+ /* 5558 */ 'v', 'p', 'm', 'a', 'd', 'c', 's', 's', 'w', 'd', 9, 0, >+ /* 5570 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'd', 9, 0, >+ /* 5581 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'd', 9, 0, >+ /* 5592 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'd', 9, 0, >+ /* 5603 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, >+ /* 5611 */ 'j', 'a', 'e', 9, 0, >+ /* 5616 */ 's', 'e', 't', 'a', 'e', 9, 0, >+ /* 5623 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, >+ /* 5631 */ 'j', 'b', 'e', 9, 0, >+ /* 5636 */ 's', 'e', 't', 'b', 'e', 9, 0, >+ /* 5643 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, >+ /* 5651 */ 'f', 's', 't', 'p', 'n', 'c', 'e', 9, 0, >+ /* 5660 */ 'f', 'f', 'r', 'e', 'e', 9, 0, >+ /* 5667 */ 'j', 'g', 'e', 9, 0, >+ /* 5672 */ 'p', 'f', 'c', 'm', 'p', 'g', 'e', 9, 0, >+ /* 5681 */ 's', 'e', 't', 'g', 'e', 9, 0, >+ /* 5688 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, >+ /* 5696 */ 'j', 'e', 9, 0, >+ /* 5700 */ 'j', 'l', 'e', 9, 0, >+ /* 5705 */ 's', 'e', 't', 'l', 'e', 9, 0, >+ /* 5712 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, >+ /* 5720 */ 'j', 'n', 'e', 9, 0, >+ /* 5725 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, >+ /* 5733 */ 's', 'e', 't', 'n', 'e', 9, 0, >+ /* 5740 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, >+ /* 5748 */ 'l', 'o', 'o', 'p', 'e', 9, 0, >+ /* 5755 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 5765 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 5775 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 5785 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 5795 */ 's', 'e', 't', 'e', 9, 0, >+ /* 5801 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, >+ /* 5810 */ 's', 'h', 'a', '1', 'n', 'e', 'x', 't', 'e', 9, 0, >+ /* 5821 */ 'f', 'n', 's', 'a', 'v', 'e', 9, 0, >+ /* 5829 */ 'f', 'x', 's', 'a', 'v', 'e', 9, 0, >+ /* 5837 */ 'c', 'm', 'o', 'v', 'e', 9, 0, >+ /* 5844 */ 'b', 's', 'f', 9, 0, >+ /* 5849 */ 'r', 'e', 't', 'f', 9, 0, >+ /* 5855 */ 'n', 'e', 'g', 9, 0, >+ /* 5860 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, >+ /* 5869 */ 'j', 'g', 9, 0, >+ /* 5873 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, >+ /* 5881 */ 's', 'e', 't', 'g', 9, 0, >+ /* 5887 */ 'c', 'm', 'o', 'v', 'g', 9, 0, >+ /* 5894 */ 'p', 'r', 'e', 'f', 'e', 't', 'c', 'h', 9, 0, >+ /* 5904 */ 'f', 'x', 'c', 'h', 9, 0, >+ /* 5910 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'p', 'h', 9, 0, >+ /* 5921 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'h', 9, 0, >+ /* 5932 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'h', 9, 0, >+ /* 5944 */ 'c', 'l', 'f', 'l', 'u', 's', 'h', 9, 0, >+ /* 5953 */ 'p', 'u', 's', 'h', 9, 0, >+ /* 5959 */ 'b', 'l', 'c', 'i', 9, 0, >+ /* 5965 */ 'b', 'z', 'h', 'i', 9, 0, >+ /* 5971 */ 'f', 'c', 'o', 'm', 'i', 9, 0, >+ /* 5978 */ 'f', 'u', 'c', 'o', 'm', 'i', 9, 0, >+ /* 5986 */ 'c', 'v', 't', 't', 'p', 'd', '2', 'p', 'i', 9, 0, >+ /* 5997 */ 'c', 'v', 't', 'p', 'd', '2', 'p', 'i', 9, 0, >+ /* 6007 */ 'c', 'v', 't', 't', 'p', 's', '2', 'p', 'i', 9, 0, >+ /* 6018 */ 'c', 'v', 't', 'p', 's', '2', 'p', 'i', 9, 0, >+ /* 6028 */ 'f', 'c', 'o', 'm', 'p', 'i', 9, 0, >+ /* 6036 */ 'f', 'u', 'c', 'o', 'm', 'p', 'i', 9, 0, >+ /* 6045 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'i', 9, 0, >+ /* 6057 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'i', 9, 0, >+ /* 6069 */ 'v', 'c', 'v', 't', 't', 's', 'd', '2', 's', 'i', 9, 0, >+ /* 6081 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 'i', 9, 0, >+ /* 6092 */ 'v', 'c', 'v', 't', 't', 's', 's', '2', 's', 'i', 9, 0, >+ /* 6104 */ 'v', 'c', 'v', 't', 's', 's', '2', 's', 'i', 9, 0, >+ /* 6115 */ 'b', 'l', 's', 'i', 9, 0, >+ /* 6121 */ 'm', 'o', 'v', 'n', 't', 'i', 9, 0, >+ /* 6129 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, >+ /* 6137 */ 'b', 'l', 's', 'm', 's', 'k', 9, 0, >+ /* 6145 */ 't', 'z', 'm', 's', 'k', 9, 0, >+ /* 6152 */ 's', 'a', 'l', 9, 0, >+ /* 6157 */ 'r', 'c', 'l', 9, 0, >+ /* 6162 */ 's', 'h', 'l', 9, 0, >+ /* 6167 */ 'j', 'l', 9, 0, >+ /* 6171 */ 'l', 'c', 'a', 'l', 'l', 9, 0, >+ /* 6178 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, >+ /* 6187 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, >+ /* 6196 */ 'r', 'o', 'l', 9, 0, >+ /* 6201 */ 'a', 'r', 'p', 'l', 9, 0, >+ /* 6207 */ 'v', 'p', 'm', 'a', 'c', 's', 'd', 'q', 'l', 9, 0, >+ /* 6218 */ 'v', 'p', 'm', 'a', 'c', 's', 's', 'd', 'q', 'l', 9, 0, >+ /* 6230 */ 'l', 's', 'l', 9, 0, >+ /* 6235 */ 's', 'e', 't', 'l', 9, 0, >+ /* 6241 */ 'p', 'f', 'm', 'u', 'l', 9, 0, >+ /* 6248 */ 'f', 'i', 'm', 'u', 'l', 9, 0, >+ /* 6255 */ 'c', 'm', 'o', 'v', 'l', 9, 0, >+ /* 6262 */ 'a', 'a', 'm', 9, 0, >+ /* 6267 */ 'f', 'c', 'o', 'm', 9, 0, >+ /* 6273 */ 'f', 'i', 'c', 'o', 'm', 9, 0, >+ /* 6280 */ 'f', 'u', 'c', 'o', 'm', 9, 0, >+ /* 6287 */ 'v', 'p', 'p', 'e', 'r', 'm', 9, 0, >+ /* 6295 */ 'v', 'p', 'c', 'm', 'p', 'e', 's', 't', 'r', 'm', 9, 0, >+ /* 6307 */ 'v', 'p', 'c', 'm', 'p', 'i', 's', 't', 'r', 'm', 9, 0, >+ /* 6319 */ 'v', 'p', 'a', 'n', 'd', 'n', 9, 0, >+ /* 6327 */ 'x', 'b', 'e', 'g', 'i', 'n', 9, 0, >+ /* 6335 */ 'p', 'f', 'm', 'i', 'n', 9, 0, >+ /* 6342 */ 'v', 'm', 'x', 'o', 'n', 9, 0, >+ /* 6349 */ 'j', 'o', 9, 0, >+ /* 6353 */ 'j', 'n', 'o', 9, 0, >+ /* 6358 */ 's', 'e', 't', 'n', 'o', 9, 0, >+ /* 6365 */ 'c', 'm', 'o', 'v', 'n', 'o', 9, 0, >+ /* 6373 */ 's', 'e', 't', 'o', 9, 0, >+ /* 6379 */ 'c', 'm', 'o', 'v', 'o', 9, 0, >+ /* 6386 */ 'b', 's', 'w', 'a', 'p', 9, 0, >+ /* 6393 */ 'f', 's', 'u', 'b', 'p', 9, 0, >+ /* 6400 */ 'p', 'f', 'r', 'c', 'p', 9, 0, >+ /* 6407 */ 'f', 'a', 'd', 'd', 'p', 9, 0, >+ /* 6414 */ 'p', 'd', 'e', 'p', 9, 0, >+ /* 6420 */ 'j', 'p', 9, 0, >+ /* 6424 */ 'f', 'm', 'u', 'l', 'p', 9, 0, >+ /* 6431 */ 'c', 'm', 'p', 9, 0, >+ /* 6436 */ 'l', 'j', 'm', 'p', 9, 0, >+ /* 6442 */ 'f', 'c', 'o', 'm', 'p', 9, 0, >+ /* 6449 */ 'f', 'i', 'c', 'o', 'm', 'p', 9, 0, >+ /* 6457 */ 'f', 'u', 'c', 'o', 'm', 'p', 9, 0, >+ /* 6465 */ 'j', 'n', 'p', 9, 0, >+ /* 6470 */ 's', 'e', 't', 'n', 'p', 9, 0, >+ /* 6477 */ 'c', 'm', 'o', 'v', 'n', 'p', 9, 0, >+ /* 6485 */ 'n', 'o', 'p', 9, 0, >+ /* 6490 */ 'l', 'o', 'o', 'p', 9, 0, >+ /* 6496 */ 'p', 'o', 'p', 9, 0, >+ /* 6501 */ 'f', 's', 'u', 'b', 'r', 'p', 9, 0, >+ /* 6509 */ 'f', 'd', 'i', 'v', 'r', 'p', 9, 0, >+ /* 6517 */ 's', 'e', 't', 'p', 9, 0, >+ /* 6523 */ 'f', 'b', 's', 't', 'p', 9, 0, >+ /* 6530 */ 'f', 's', 't', 'p', 9, 0, >+ /* 6536 */ 'f', 'i', 's', 't', 'p', 9, 0, >+ /* 6543 */ 'f', 'i', 's', 't', 't', 'p', 9, 0, >+ /* 6551 */ 'v', 'm', 'o', 'v', 'd', 'd', 'u', 'p', 9, 0, >+ /* 6561 */ 'v', 'm', 'o', 'v', 's', 'h', 'd', 'u', 'p', 9, 0, >+ /* 6572 */ 'v', 'm', 'o', 'v', 's', 'l', 'd', 'u', 'p', 9, 0, >+ /* 6583 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, >+ /* 6599 */ 'f', 'd', 'i', 'v', 'p', 9, 0, >+ /* 6606 */ 'c', 'm', 'o', 'v', 'p', 9, 0, >+ /* 6613 */ 'm', 'o', 'v', 'd', 'q', '2', 'q', 9, 0, >+ /* 6622 */ 'v', 'p', 's', 'h', 'a', 'q', 9, 0, >+ /* 6630 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'q', 9, 0, >+ /* 6640 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'q', 9, 0, >+ /* 6651 */ 'v', 'p', 's', 'u', 'b', 'q', 9, 0, >+ /* 6659 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'b', 'q', 9, 0, >+ /* 6670 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'b', 'q', 9, 0, >+ /* 6681 */ 'v', 'c', 'v', 't', 't', 'p', 'd', '2', 'd', 'q', 9, 0, >+ /* 6693 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'd', 'q', 9, 0, >+ /* 6704 */ 'm', 'o', 'v', 'q', '2', 'd', 'q', 9, 0, >+ /* 6713 */ 'v', 'c', 'v', 't', 't', 'p', 's', '2', 'd', 'q', 9, 0, >+ /* 6725 */ 'v', 'c', 'v', 't', 'p', 's', '2', 'd', 'q', 9, 0, >+ /* 6736 */ 'v', 'p', 'h', 's', 'u', 'b', 'd', 'q', 9, 0, >+ /* 6746 */ 'v', 'p', 'a', 'd', 'd', 'q', 9, 0, >+ /* 6754 */ 'v', 'p', 'h', 'a', 'd', 'd', 'd', 'q', 9, 0, >+ /* 6764 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'd', 'q', 9, 0, >+ /* 6776 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'd', 'q', 9, 0, >+ /* 6788 */ 'v', 'p', 's', 'l', 'l', 'd', 'q', 9, 0, >+ /* 6797 */ 'v', 'p', 's', 'r', 'l', 'd', 'q', 9, 0, >+ /* 6806 */ 'v', 'p', 'm', 'u', 'l', 'd', 'q', 9, 0, >+ /* 6815 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'q', 'd', 'q', 9, 0, >+ /* 6828 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'q', 'd', 'q', 9, 0, >+ /* 6841 */ 'v', 'p', 'c', 'l', 'm', 'u', 'l', 'q', 'd', 'q', 9, 0, >+ /* 6853 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'q', 9, 0, >+ /* 6865 */ 'v', 'm', 'o', 'v', 'n', 't', 'd', 'q', 9, 0, >+ /* 6875 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'd', 'q', 9, 0, >+ /* 6886 */ 'v', 'p', 'm', 'u', 'l', 'u', 'd', 'q', 9, 0, >+ /* 6896 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'd', 'q', 9, 0, >+ /* 6907 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'd', 'q', 9, 0, >+ /* 6918 */ 'p', 'f', 'c', 'm', 'p', 'e', 'q', 9, 0, >+ /* 6927 */ 'r', 'e', 't', 'f', 'q', 9, 0, >+ /* 6934 */ 'v', 'p', 's', 'h', 'l', 'q', 9, 0, >+ /* 6942 */ 'v', 'p', 's', 'l', 'l', 'q', 9, 0, >+ /* 6950 */ 'v', 'p', 's', 'r', 'l', 'q', 9, 0, >+ /* 6958 */ 'v', 'p', 'c', 'o', 'm', 'q', 9, 0, >+ /* 6966 */ 'v', 'p', 'e', 'r', 'm', 'q', 9, 0, >+ /* 6974 */ 'v', 'p', 'c', 'm', 'p', 'q', 9, 0, >+ /* 6982 */ 'v', 'p', 'c', 'm', 'p', 'e', 'q', 'q', 9, 0, >+ /* 6992 */ 'v', 'p', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'q', 9, 0, >+ /* 7004 */ 'v', 'p', 'i', 'n', 's', 'r', 'q', 9, 0, >+ /* 7013 */ 'v', 'p', 'e', 'x', 't', 'r', 'q', 9, 0, >+ /* 7022 */ 's', 't', 'o', 's', 'q', 9, 0, >+ /* 7029 */ 'c', 'm', 'p', 's', 'q', 9, 0, >+ /* 7036 */ 'm', 'o', 'v', 's', 'q', 9, 0, >+ /* 7043 */ 'v', 'p', 'c', 'm', 'p', 'g', 't', 'q', 9, 0, >+ /* 7053 */ 'm', 'o', 'v', 'n', 't', 'q', 9, 0, >+ /* 7061 */ 'v', 'p', 'r', 'o', 't', 'q', 9, 0, >+ /* 7069 */ 'i', 'n', 's', 'e', 'r', 't', 'q', 9, 0, >+ /* 7078 */ 'v', 'p', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'q', 9, 0, >+ /* 7092 */ 'v', 'p', 'c', 'o', 'm', 'u', 'q', 9, 0, >+ /* 7101 */ 'v', 'p', 'c', 'm', 'p', 'u', 'q', 9, 0, >+ /* 7110 */ 'v', 'p', 's', 'l', 'l', 'v', 'q', 9, 0, >+ /* 7119 */ 'v', 'p', 's', 'r', 'l', 'v', 'q', 9, 0, >+ /* 7128 */ 'v', 'p', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'q', 9, 0, >+ /* 7140 */ 'v', 'm', 'o', 'v', 'q', 9, 0, >+ /* 7147 */ 'v', 'p', 'h', 'a', 'd', 'd', 'w', 'q', 9, 0, >+ /* 7157 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'w', 'q', 9, 0, >+ /* 7168 */ 'v', 'p', 'm', 'o', 'v', 's', 'x', 'w', 'q', 9, 0, >+ /* 7179 */ 'v', 'p', 'm', 'o', 'v', 'z', 'x', 'w', 'q', 9, 0, >+ /* 7190 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, >+ /* 7199 */ 'l', 'a', 'r', 9, 0, >+ /* 7204 */ 's', 'a', 'r', 9, 0, >+ /* 7209 */ 'p', 'f', 's', 'u', 'b', 'r', 9, 0, >+ /* 7217 */ 'f', 'i', 's', 'u', 'b', 'r', 9, 0, >+ /* 7225 */ 'r', 'c', 'r', 9, 0, >+ /* 7230 */ 'e', 'n', 't', 'e', 'r', 9, 0, >+ /* 7237 */ 's', 'h', 'r', 9, 0, >+ /* 7242 */ 'v', 'p', 'a', 'l', 'i', 'g', 'n', 'r', 9, 0, >+ /* 7252 */ 'v', 'p', 'o', 'r', 9, 0, >+ /* 7258 */ 'r', 'o', 'r', 9, 0, >+ /* 7263 */ 'f', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 7271 */ 'f', 'x', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 7280 */ 'v', 'p', 'x', 'o', 'r', 9, 0, >+ /* 7287 */ 'v', 'e', 'r', 'r', 9, 0, >+ /* 7293 */ 'b', 's', 'r', 9, 0, >+ /* 7298 */ 'v', 'l', 'd', 'm', 'x', 'c', 's', 'r', 9, 0, >+ /* 7308 */ 'v', 's', 't', 'm', 'x', 'c', 's', 'r', 9, 0, >+ /* 7318 */ 'b', 'l', 's', 'r', 9, 0, >+ /* 7324 */ 'b', 't', 'r', 9, 0, >+ /* 7329 */ 'l', 't', 'r', 9, 0, >+ /* 7334 */ 's', 't', 'r', 9, 0, >+ /* 7339 */ 'b', 'e', 'x', 't', 'r', 9, 0, >+ /* 7346 */ 'f', 'd', 'i', 'v', 'r', 9, 0, >+ /* 7353 */ 'f', 'i', 'd', 'i', 'v', 'r', 9, 0, >+ /* 7361 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, >+ /* 7369 */ 'b', 'l', 'c', 's', 9, 0, >+ /* 7375 */ 'l', 'd', 's', 9, 0, >+ /* 7380 */ 'l', 'e', 's', 9, 0, >+ /* 7385 */ 'l', 'f', 's', 9, 0, >+ /* 7390 */ 'l', 'g', 's', 9, 0, >+ /* 7395 */ 'j', 's', 9, 0, >+ /* 7399 */ 'j', 'n', 's', 9, 0, >+ /* 7404 */ 's', 'e', 't', 'n', 's', 9, 0, >+ /* 7411 */ 'c', 'm', 'o', 'v', 'n', 's', 9, 0, >+ /* 7419 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7435 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7448 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7462 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7478 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7491 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 'p', 's', 9, 0, >+ /* 7505 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7521 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7534 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7548 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7564 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7577 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 'p', 's', 9, 0, >+ /* 7591 */ 'v', 'c', 'v', 't', 'p', 'd', '2', 'p', 's', 9, 0, >+ /* 7602 */ 'v', 'c', 'v', 't', 'p', 'h', '2', 'p', 's', 9, 0, >+ /* 7613 */ 'c', 'v', 't', 'p', 'i', '2', 'p', 's', 9, 0, >+ /* 7623 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', '2', 'p', 's', 9, 0, >+ /* 7635 */ 'v', 'c', 'v', 't', 'd', 'q', '2', 'p', 's', 9, 0, >+ /* 7646 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7662 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7675 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7689 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7705 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7718 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 'p', 's', 9, 0, >+ /* 7732 */ 'v', 'm', 'o', 'v', 'a', 'p', 's', 9, 0, >+ /* 7741 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7754 */ 'v', 'a', 'd', 'd', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7765 */ 'v', 'h', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7774 */ 'v', 'f', 'm', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7784 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7795 */ 'v', 's', 'u', 'b', 'p', 's', 9, 0, >+ /* 7803 */ 'v', 'f', 'm', 's', 'u', 'b', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 7816 */ 'v', 'h', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 7825 */ 'v', 'f', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 7835 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 7846 */ 'v', 'a', 'd', 'd', 'p', 's', 9, 0, >+ /* 7854 */ 'v', 'a', 'n', 'd', 'p', 's', 9, 0, >+ /* 7862 */ 'v', 'b', 'l', 'e', 'n', 'd', 'p', 's', 9, 0, >+ /* 7872 */ 'v', 'r', 'o', 'u', 'n', 'd', 'p', 's', 9, 0, >+ /* 7882 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'd', 'p', 's', 9, 0, >+ /* 7894 */ 'v', 's', 'h', 'u', 'f', 'p', 's', 9, 0, >+ /* 7903 */ 'v', 'u', 'n', 'p', 'c', 'k', 'h', 'p', 's', 9, 0, >+ /* 7914 */ 'v', 'm', 'o', 'v', 'l', 'h', 'p', 's', 9, 0, >+ /* 7924 */ 'v', 'm', 'o', 'v', 'h', 'p', 's', 9, 0, >+ /* 7933 */ 'v', 'm', 'o', 'v', 'm', 's', 'k', 'p', 's', 9, 0, >+ /* 7944 */ 'v', 'm', 'o', 'v', 'h', 'l', 'p', 's', 9, 0, >+ /* 7954 */ 'v', 'p', 'e', 'r', 'm', 'i', 'l', 'p', 's', 9, 0, >+ /* 7965 */ 'v', 'u', 'n', 'p', 'c', 'k', 'l', 'p', 's', 9, 0, >+ /* 7976 */ 'v', 'm', 'u', 'l', 'p', 's', 9, 0, >+ /* 7984 */ 'v', 'm', 'o', 'v', 'l', 'p', 's', 9, 0, >+ /* 7993 */ 'v', 'p', 'e', 'r', 'm', 'p', 's', 9, 0, >+ /* 8002 */ 'v', 'a', 'n', 'd', 'n', 'p', 's', 9, 0, >+ /* 8011 */ 'v', 'm', 'i', 'n', 'p', 's', 9, 0, >+ /* 8019 */ 'v', 'r', 'c', 'p', 'p', 's', 9, 0, >+ /* 8027 */ 'v', 'd', 'p', 'p', 's', 9, 0, >+ /* 8034 */ 'v', 'c', 'm', 'p', 'p', 's', 9, 0, >+ /* 8042 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'q', 'p', 's', 9, 0, >+ /* 8054 */ 'v', 'o', 'r', 'p', 's', 9, 0, >+ /* 8061 */ 'v', 'x', 'o', 'r', 'p', 's', 9, 0, >+ /* 8069 */ 'v', 'e', 'x', 't', 'r', 'a', 'c', 't', 'p', 's', 9, 0, >+ /* 8081 */ 'v', 'm', 'o', 'v', 'n', 't', 'p', 's', 9, 0, >+ /* 8091 */ 'v', 'i', 'n', 's', 'e', 'r', 't', 'p', 's', 9, 0, >+ /* 8102 */ 'v', 'r', 's', 'q', 'r', 't', 'p', 's', 9, 0, >+ /* 8112 */ 'v', 's', 'q', 'r', 't', 'p', 's', 9, 0, >+ /* 8121 */ 'v', 't', 'e', 's', 't', 'p', 's', 9, 0, >+ /* 8130 */ 'v', 'm', 'o', 'v', 'u', 'p', 's', 9, 0, >+ /* 8139 */ 'v', 'b', 'l', 'e', 'n', 'd', 'v', 'p', 's', 9, 0, >+ /* 8150 */ 'v', 'd', 'i', 'v', 'p', 's', 9, 0, >+ /* 8158 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'p', 's', 9, 0, >+ /* 8170 */ 'v', 'm', 'a', 'x', 'p', 's', 9, 0, >+ /* 8178 */ 'v', 'f', 'r', 'c', 'z', 'p', 's', 9, 0, >+ /* 8187 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, >+ /* 8200 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '3', '1', 's', 's', 9, 0, >+ /* 8214 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, >+ /* 8227 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '3', '1', 's', 's', 9, 0, >+ /* 8241 */ 'v', 'f', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, >+ /* 8254 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '1', '3', '2', 's', 's', 9, 0, >+ /* 8268 */ 'v', 'f', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, >+ /* 8281 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '1', '3', '2', 's', 's', 9, 0, >+ /* 8295 */ 'v', 'c', 'v', 't', 's', 'd', '2', 's', 's', 9, 0, >+ /* 8306 */ 'v', 'c', 'v', 't', 's', 'i', '2', 's', 's', 9, 0, >+ /* 8317 */ 'v', 'c', 'v', 't', 'u', 's', 'i', '2', 's', 's', 9, 0, >+ /* 8329 */ 'v', 'f', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, >+ /* 8342 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', '2', '1', '3', 's', 's', 9, 0, >+ /* 8356 */ 'v', 'f', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, >+ /* 8369 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', '2', '1', '3', 's', 's', 9, 0, >+ /* 8383 */ 'v', 'f', 'm', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 8393 */ 'v', 'f', 'n', 'm', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 8404 */ 'v', 's', 'u', 'b', 's', 's', 9, 0, >+ /* 8412 */ 'v', 'f', 'm', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 8422 */ 'v', 'f', 'n', 'm', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 8433 */ 'v', 'a', 'd', 'd', 's', 's', 9, 0, >+ /* 8441 */ 'v', 'r', 'o', 'u', 'n', 'd', 's', 's', 9, 0, >+ /* 8451 */ 'v', 'u', 'c', 'o', 'm', 'i', 's', 's', 9, 0, >+ /* 8461 */ 'v', 'c', 'o', 'm', 'i', 's', 's', 9, 0, >+ /* 8470 */ 'v', 'm', 'u', 'l', 's', 's', 9, 0, >+ /* 8478 */ 'v', 'm', 'i', 'n', 's', 's', 9, 0, >+ /* 8486 */ 'v', 'r', 'c', 'p', 's', 's', 9, 0, >+ /* 8494 */ 'v', 'c', 'm', 'p', 's', 's', 9, 0, >+ /* 8502 */ 'm', 'o', 'v', 'n', 't', 's', 's', 9, 0, >+ /* 8511 */ 'v', 'r', 's', 'q', 'r', 't', 's', 's', 9, 0, >+ /* 8521 */ 'v', 's', 'q', 'r', 't', 's', 's', 9, 0, >+ /* 8530 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 's', 's', 9, 0, >+ /* 8544 */ 'v', 'd', 'i', 'v', 's', 's', 9, 0, >+ /* 8552 */ 'v', 'm', 'o', 'v', 's', 's', 9, 0, >+ /* 8560 */ 'v', 'm', 'a', 'x', 's', 's', 9, 0, >+ /* 8568 */ 'v', 'f', 'r', 'c', 'z', 's', 's', 9, 0, >+ /* 8577 */ 'b', 't', 's', 9, 0, >+ /* 8582 */ 's', 'e', 't', 's', 9, 0, >+ /* 8588 */ 'c', 'm', 'o', 'v', 's', 9, 0, >+ /* 8595 */ 'b', 't', 9, 0, >+ /* 8599 */ 'l', 'g', 'd', 't', 9, 0, >+ /* 8605 */ 's', 'g', 'd', 't', 9, 0, >+ /* 8611 */ 'l', 'i', 'd', 't', 9, 0, >+ /* 8617 */ 's', 'i', 'd', 't', 9, 0, >+ /* 8623 */ 'l', 'l', 'd', 't', 9, 0, >+ /* 8629 */ 's', 'l', 'd', 't', 9, 0, >+ /* 8635 */ 'r', 'e', 't', 9, 0, >+ /* 8640 */ 'p', 'f', 'c', 'm', 'p', 'g', 't', 9, 0, >+ /* 8649 */ 'p', 'o', 'p', 'c', 'n', 't', 9, 0, >+ /* 8657 */ 'l', 'z', 'c', 'n', 't', 9, 0, >+ /* 8664 */ 't', 'z', 'c', 'n', 't', 9, 0, >+ /* 8671 */ 'i', 'n', 't', 9, 0, >+ /* 8676 */ 'n', 'o', 't', 9, 0, >+ /* 8681 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, >+ /* 8689 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, >+ /* 8699 */ 'x', 'a', 'b', 'o', 'r', 't', 9, 0, >+ /* 8707 */ 'p', 'f', 'r', 's', 'q', 'r', 't', 9, 0, >+ /* 8716 */ 'v', 'a', 'e', 's', 'd', 'e', 'c', 'l', 'a', 's', 't', 9, 0, >+ /* 8729 */ 'v', 'a', 'e', 's', 'e', 'n', 'c', 'l', 'a', 's', 't', 9, 0, >+ /* 8742 */ 'v', 'p', 't', 'e', 's', 't', 9, 0, >+ /* 8750 */ 'f', 's', 't', 9, 0, >+ /* 8755 */ 'f', 'i', 's', 't', 9, 0, >+ /* 8761 */ 'v', 'a', 'e', 's', 'k', 'e', 'y', 'g', 'e', 'n', 'a', 's', 's', 'i', 's', 't', 9, 0, >+ /* 8779 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, >+ /* 8788 */ 'o', 'u', 't', 9, 0, >+ /* 8793 */ 'p', 'e', 'x', 't', 9, 0, >+ /* 8799 */ 'v', 'l', 'd', 'd', 'q', 'u', 9, 0, >+ /* 8807 */ 'v', 'm', 'a', 's', 'k', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, >+ /* 8820 */ 'v', 'm', 'o', 'v', 'd', 'q', 'u', 9, 0, >+ /* 8829 */ 'f', 'd', 'i', 'v', 9, 0, >+ /* 8835 */ 'f', 'i', 'd', 'i', 'v', 9, 0, >+ /* 8842 */ 'f', 'l', 'd', 'e', 'n', 'v', 9, 0, >+ /* 8850 */ 'f', 'n', 's', 't', 'e', 'n', 'v', 9, 0, >+ /* 8859 */ 'v', 'p', 'c', 'm', 'o', 'v', 9, 0, >+ /* 8867 */ 'v', 'p', 's', 'h', 'a', 'w', 9, 0, >+ /* 8875 */ 'v', 'p', 's', 'r', 'a', 'w', 9, 0, >+ /* 8883 */ 'v', 'p', 'h', 's', 'u', 'b', 'b', 'w', 9, 0, >+ /* 8893 */ 'v', 'm', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, >+ /* 8903 */ 'v', 'p', 's', 'a', 'd', 'b', 'w', 9, 0, >+ /* 8912 */ 'v', 'p', 'h', 'a', 'd', 'd', 'b', 'w', 9, 0, >+ /* 8922 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'h', 'b', 'w', 9, 0, >+ /* 8934 */ 'v', 'p', 'u', 'n', 'p', 'c', 'k', 'l', 'b', 'w', 9, 0, >+ /* 8946 */ 'v', 'p', 'h', 'a', 'd', 'd', 'u', 'b', 'w', 9, 0, >+ /* 8957 */ 'v', 'p', 'h', 's', 'u', 'b', 'w', 9, 0, >+ /* 8966 */ 'v', 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'!', 0, >+ /* 10656 */ '#', 'C', 'M', 'O', 'V', '_', 'V', '4', 'F', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10676 */ '#', 'C', 'M', 'O', 'V', '_', 'V', '8', 'F', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10696 */ '#', 'C', 'M', 'O', 'V', '_', 'V', '2', 'I', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10716 */ '#', 'C', 'M', 'O', 'V', '_', 'V', '4', 'I', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10736 */ '#', 'C', 'M', 'O', 'V', '_', 'V', '8', 'I', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10756 */ '#', 'C', 'M', 'O', 'V', '_', 'R', 'F', 'P', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10776 */ '#', 'C', 'M', 'O', 'V', '_', 'F', 'R', '6', '4', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10795 */ '#', 'C', 'M', 'O', 'V', '_', 'G', 'R', '8', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10813 */ '#', 'A', 'C', 'Q', 'U', 'I', 'R', 'E', '_', 'M', 'O', 'V', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10834 */ '#', 'R', 'E', 'L', 'E', 'A', 'S', 'E', '_', 'M', 'O', 'V', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0, >+ /* 10855 */ 'x', 's', 'h', 'a', '1', 0, >+ /* 10861 */ 'f', 'l', 'd', '1', 0, >+ /* 10866 */ 'f', 'p', 'r', 'e', 'm', '1', 0, >+ /* 10873 */ 'f', '2', 'x', 'm', '1', 0, >+ /* 10879 */ 'f', 'y', 'l', '2', 'x', 'p', '1', 0, >+ /* 10887 */ 'i', 'n', 't', '1', 0, >+ /* 10892 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '3', '2', 0, >+ /* 10911 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '3', '2', 0, >+ /* 10929 */ '#', 32, 'T', 'L', 'S', 'C', 'a', 'l', 'l', '_', '3', '2', 0, >+ /* 10942 */ '#', 32, 'T', 'L', 'S', '_', 'a', 'd', 'd', 'r', '3', '2', 0, >+ /* 10955 */ '#', 32, 'T', 'L', 'S', '_', 'b', 'a', 's', 'e', '_', 'a', 'd', 'd', 'r', '3', '2', 0, >+ /* 10973 */ 'u', 'd', '2', 0, >+ /* 10977 */ 'f', 'l', 'd', 'l', 'g', '2', 0, >+ /* 10984 */ 'f', 'l', 'd', 'l', 'n', '2', 0, >+ /* 10991 */ 'i', 'n', 't', '3', 0, >+ /* 10996 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'L', 'O', 'N', 'G', 'J', 'M', 'P', '6', '4', 0, >+ /* 11015 */ '#', 'E', 'H', '_', 'S', 'J', 'L', 'J', '_', 'S', 'E', 'T', 'J', 'M', 'P', '6', '4', 0, >+ /* 11033 */ '#', 32, 'T', 'L', 'S', 'C', 'a', 'l', 'l', '_', '6', '4', 0, >+ /* 11046 */ '#', 32, 'T', 'L', 'S', '_', 'a', 'd', 'd', 'r', '6', '4', 0, >+ /* 11059 */ '#', 32, 'T', 'L', 'S', '_', 'b', 'a', 's', 'e', '_', 'a', 'd', 'd', 'r', '6', '4', 0, >+ /* 11077 */ 'r', 'e', 'x', '6', '4', 0, >+ /* 11083 */ 'd', 'a', 't', 'a', '1', '6', 0, >+ /* 11090 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, >+ /* 11098 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 11111 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 11118 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 11128 */ '#', 32, 'X', 'B', 'E', 'G', 'I', 'N', 0, >+ /* 11137 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0, >+ /* 11155 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0, >+ /* 11171 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, >+ /* 11183 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 11198 */ 'a', 'a', 'a', 0, >+ /* 11202 */ 'd', 'a', 'a', 0, >+ /* 11206 */ 'u', 'd', '2', 'b', 0, >+ /* 11211 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, >+ /* 11221 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, >+ /* 11231 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, >+ /* 11241 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'b', 0, >+ /* 11251 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'b', 0, >+ /* 11261 */ 'x', 'l', 'a', 't', 'b', 0, >+ /* 11267 */ 'c', 'l', 'a', 'c', 0, >+ /* 11272 */ 's', 't', 'a', 'c', 0, >+ /* 11277 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, >+ /* 11287 */ 'g', 'e', 't', 's', 'e', 'c', 0, >+ /* 11294 */ 's', 'a', 'l', 'c', 0, >+ /* 11299 */ 'c', 'l', 'c', 0, >+ /* 11303 */ 'c', 'm', 'c', 0, >+ /* 11307 */ 'r', 'd', 'p', 'm', 'c', 0, >+ /* 11313 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, >+ /* 11320 */ 'r', 'd', 't', 's', 'c', 0, >+ /* 11326 */ 's', 't', 'c', 0, >+ /* 11330 */ 'p', 'u', 's', 'h', 'f', 'd', 0, >+ /* 11337 */ 'p', 'o', 'p', 'f', 'd', 0, >+ /* 11343 */ 'c', 'p', 'u', 'i', 'd', 0, >+ /* 11349 */ 'c', 'l', 'd', 0, >+ /* 11353 */ 'x', 'e', 'n', 'd', 0, >+ /* 11358 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'd', 0, >+ /* 11368 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'd', 0, >+ /* 11378 */ 'i', 'r', 'e', 't', 'd', 0, >+ /* 11384 */ 's', 't', 'd', 0, >+ /* 11388 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, >+ /* 11395 */ 'c', 'w', 'd', 0, >+ /* 11399 */ 'f', 'l', 'd', 'l', '2', 'e', 0, >+ /* 11406 */ 'l', 'f', 'e', 'n', 'c', 'e', 0, >+ /* 11413 */ 'm', 'f', 'e', 'n', 'c', 'e', 0, >+ /* 11420 */ 's', 'f', 'e', 'n', 'c', 'e', 0, >+ /* 11427 */ 'c', 'w', 'd', 'e', 0, >+ /* 11432 */ 'f', 's', 'c', 'a', 'l', 'e', 0, >+ /* 11439 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, >+ /* 11448 */ 'r', 'e', 'p', 'n', 'e', 0, >+ /* 11454 */ 'c', 'd', 'q', 'e', 0, >+ /* 11459 */ 'x', 'a', 'c', 'q', 'u', 'i', 'r', 'e', 0, >+ /* 11468 */ 'x', 's', 't', 'o', 'r', 'e', 0, >+ /* 11475 */ 'x', 'r', 'e', 'l', 'e', 'a', 's', 'e', 0, >+ /* 11484 */ 'p', 'a', 'u', 's', 'e', 0, >+ /* 11490 */ '#', 'S', 'E', 'H', '_', 'E', 'p', 'i', 'l', 'o', 'g', 'u', 'e', 0, >+ /* 11504 */ '#', 'S', 'E', 'H', '_', 'E', 'n', 'd', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', 0, >+ /* 11521 */ 'l', 'e', 'a', 'v', 'e', 0, >+ /* 11527 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, >+ /* 11534 */ 'l', 'a', 'h', 'f', 0, >+ /* 11539 */ 's', 'a', 'h', 'f', 0, >+ /* 11544 */ 'p', 'u', 's', 'h', 'f', 0, >+ /* 11550 */ 'p', 'o', 'p', 'f', 0, >+ /* 11555 */ 'r', 'e', 't', 'f', 0, >+ /* 11560 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, >+ /* 11569 */ 'c', 'l', 'g', 'i', 0, >+ /* 11574 */ 's', 't', 'g', 'i', 0, >+ /* 11579 */ 'c', 'l', 'i', 0, >+ /* 11583 */ 'f', 'l', 'd', 'p', 'i', 0, >+ /* 11589 */ 's', 't', 'i', 0, >+ /* 11593 */ '#', 32, 'w', 'i', 'n', '3', '2', 32, 'f', 'p', 't', 'o', 'u', 'i', 0, >+ /* 11608 */ 'l', 'o', 'c', 'k', 0, >+ /* 11613 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, >+ /* 11624 */ 'p', 'u', 's', 'h', 'a', 'l', 0, >+ /* 11631 */ 'p', 'o', 'p', 'a', 'l', 0, >+ /* 11637 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 11645 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 11652 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, >+ /* 11660 */ 'v', 'z', 'e', 'r', 'o', 'a', 'l', 'l', 0, >+ /* 11669 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, >+ /* 11677 */ 'f', 'x', 'a', 'm', 0, >+ /* 11682 */ 'f', 'p', 'r', 'e', 'm', 0, >+ /* 11688 */ 'f', 's', 'e', 't', 'p', 'm', 0, >+ /* 11695 */ 'r', 's', 'm', 0, >+ /* 11699 */ 'f', 'p', 'a', 't', 'a', 'n', 0, >+ /* 11706 */ 'f', 'p', 't', 'a', 'n', 0, >+ /* 11712 */ 'f', 's', 'i', 'n', 0, >+ /* 11717 */ '#', 32, 'd', 'y', 'n', 'a', 'm', 'i', 'c', 32, 's', 't', 'a', 'c', 'k', 32, 'a', 'l', 'l', 'o', 'c', 'a', 't', 'i', 'o', 'n', 0, >+ /* 11744 */ 'c', 'q', 'o', 0, >+ /* 11748 */ 'i', 'n', 't', 'o', 0, >+ /* 11753 */ 'r', 'd', 't', 's', 'c', 'p', 0, >+ /* 11760 */ 'r', 'e', 'p', 0, >+ /* 11764 */ 'v', 'p', 'c', 'm', 'p', 0, >+ /* 11770 */ 'v', 'c', 'm', 'p', 0, >+ /* 11775 */ 'f', 'n', 'o', 'p', 0, >+ /* 11780 */ 'f', 'c', 'o', 'm', 'p', 'p', 0, >+ /* 11787 */ 'f', 'u', 'c', 'o', 'm', 'p', 'p', 0, >+ /* 11795 */ 'f', 'd', 'e', 'c', 's', 't', 'p', 0, >+ /* 11803 */ 'f', 'i', 'n', 'c', 's', 't', 'p', 0, >+ /* 11811 */ 'c', 'd', 'q', 0, >+ /* 11815 */ 'p', 'u', 's', 'h', 'f', 'q', 0, >+ /* 11822 */ 'p', 'o', 'p', 'f', 'q', 0, >+ /* 11828 */ 'r', 'e', 't', 'f', 'q', 0, >+ /* 11834 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'q', 0, >+ /* 11844 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'q', 0, >+ /* 11854 */ 'i', 'r', 'e', 't', 'q', 0, >+ /* 11860 */ 'v', 'z', 'e', 'r', 'o', 'u', 'p', 'p', 'e', 'r', 0, >+ /* 11871 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, >+ /* 11880 */ 'm', 'o', 'n', 'i', 't', 'o', 'r', 0, >+ /* 11888 */ 'r', 'd', 'm', 's', 'r', 0, >+ /* 11894 */ 'w', 'r', 'm', 's', 'r', 0, >+ /* 11900 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, >+ /* 11910 */ 'a', 'a', 's', 0, >+ /* 11914 */ 'd', 'a', 's', 0, >+ /* 11918 */ 'f', 'a', 'b', 's', 0, >+ /* 11923 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, >+ /* 11931 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, >+ /* 11939 */ 'p', 'o', 'p', 9, 'd', 's', 0, >+ /* 11946 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, >+ /* 11954 */ 'p', 'o', 'p', 9, 'e', 's', 0, >+ /* 11961 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, >+ /* 11969 */ 'p', 'o', 'p', 9, 'f', 's', 0, >+ /* 11976 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, >+ /* 11984 */ 'p', 'o', 'p', 9, 'g', 's', 0, >+ /* 11991 */ 's', 'w', 'a', 'p', 'g', 's', 0, >+ /* 11998 */ 'f', 'c', 'h', 's', 0, >+ /* 12003 */ '#', 32, 'v', 'a', 'r', 'i', 'a', 'b', 'l', 'e', 32, 's', 'i', 'z', 'e', 'd', 32, 'a', 'l', 'l', 'o', 'c', 'a', 32, 'f', 'o', 'r', 32, 's', 'e', 'g', 'm', 'e', 'n', 't', 'e', 'd', 32, 's', 't', 'a', 'c', 'k', 's', 0, >+ /* 12048 */ 'e', 'n', 'c', 'l', 's', 0, >+ /* 12054 */ 'f', 'e', 'm', 'm', 's', 0, >+ /* 12060 */ 'f', 'c', 'o', 's', 0, >+ /* 12065 */ 'f', 's', 'i', 'n', 'c', 'o', 's', 0, >+ /* 12073 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, >+ /* 12081 */ 'p', 'o', 'p', 9, 's', 's', 0, >+ /* 12088 */ 'c', 'l', 't', 's', 0, >+ /* 12093 */ 'f', 'l', 'd', 'l', '2', 't', 0, >+ /* 12100 */ 'f', 'x', 't', 'r', 'a', 'c', 't', 0, >+ /* 12108 */ 'i', 'r', 'e', 't', 0, >+ /* 12113 */ 's', 'y', 's', 'r', 'e', 't', 0, >+ /* 12120 */ 'm', 'w', 'a', 'i', 't', 0, >+ /* 12126 */ 'f', 'n', 'i', 'n', 'i', 't', 0, >+ /* 12133 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, >+ /* 12141 */ 'h', 'l', 't', 0, >+ /* 12145 */ 'f', 'r', 'n', 'd', 'i', 'n', 't', 0, >+ /* 12153 */ 'f', 's', 'q', 'r', 't', 0, >+ /* 12159 */ 'x', 't', 'e', 's', 't', 0, >+ /* 12165 */ 'f', 't', 's', 't', 0, >+ /* 12170 */ 'e', 'n', 'c', 'l', 'u', 0, >+ /* 12176 */ 'x', 'g', 'e', 't', 'b', 'v', 0, >+ /* 12183 */ 'x', 's', 'e', 't', 'b', 'v', 0, >+ /* 12190 */ 'p', 'u', 's', 'h', 'a', 'w', 0, >+ /* 12197 */ 'p', 'o', 'p', 'a', 'w', 0, >+ /* 12203 */ 'c', 'b', 'w', 0, >+ /* 12207 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'w', 0, >+ /* 12217 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'w', 0, >+ /* 12227 */ 'f', 'y', 'l', '2', 'x', 0, >+ /* 12233 */ 'f', 'n', 's', 't', 's', 'w', 9, 'a', 'x', 0, >+ /* 12243 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, >+ /* 12254 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, >+ /* 12265 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, >+ /* 12276 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, >+ /* 12286 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, >+ /* 12297 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, >+ /* 12309 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, >+ /* 12320 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, >+ /* 12331 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, >+ /* 12341 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, >+ /* 12358 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, >+ /* 12375 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, >+ /* 12385 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, >+ /* 12395 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, >+ /* 12406 */ 'f', 'n', 'c', 'l', 'e', 'x', 0, >+ /* 12413 */ 'f', 'l', 'd', 'z', 0, >+ /* 12418 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 32, 9, '{', 0, >+ /* 12435 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 'd', 32, 9, '{', 0, >+ /* 12453 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 32, 9, '{', 0, >+ /* 12470 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 'd', 32, 9, '{', 0, >+ /* 12488 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 32, 9, '{', 0, >+ /* 12505 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 'd', 32, 9, '{', 0, >+ /* 12523 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 32, 9, '{', 0, >+ /* 12540 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 'd', 32, 9, '{', 0, >+ /* 12558 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 32, 9, '{', 0, >+ /* 12575 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'd', 'p', 's', 32, 9, '{', 0, >+ /* 12593 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 32, 9, '{', 0, >+ /* 12610 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'd', 'p', 's', 32, 9, '{', 0, >+ /* 12628 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 32, 9, '{', 0, >+ /* 12645 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '0', 'q', 'p', 's', 32, 9, '{', 0, >+ /* 12663 */ 'v', 'g', 'a', 't', 'h', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 32, 9, '{', 0, >+ /* 12680 */ 'v', 's', 'c', 'a', 't', 't', 'e', 'r', 'p', 'f', '1', 'q', 'p', 's', 32, 9, '{', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ unsigned int opcode = MCInst_getOpcode(MI); >+ //printf(">> opcode = %u\n", opcode); >+ uint64_t Bits1 = OpInfo[opcode]; >+ uint64_t Bits2 = OpInfo2[opcode]; >+ uint64_t Bits = (Bits2 << 32) | Bits1; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+ if (!X86_lockrep(MI, O)) >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 16383)-1); >+#else >+ ; >+#endif >+ >+ >+ // Fragment 0 encoded into 6 bits for 45 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 63); >+ switch ((Bits >> 14) & 63) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, AAA, AAS, ABS_F, ACQU... >+ return; >+ break; >+ case 1: >+ // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, ADD_FI16m, AND... >+ printi16mem(MI, 0, O); >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... >+ printOperand(MI, 1, O); >+ break; >+ case 4: >+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, ADD_FI32m, AND... >+ printi32mem(MI, 0, O); >+ break; >+ case 5: >+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... >+ printi64mem(MI, 0, O); >+ break; >+ case 6: >+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CLFLUSH, CMP8mi, CMP8m... >+ printi8mem(MI, 0, O); >+ break; >+ case 7: >+ // ADD_F32m, DIVR_F32m, DIV_F32m, EXTRACTPSmr, FBLDm, FBSTPm, FCOM32m, FC... >+ printf32mem(MI, 0, O); >+ break; >+ case 8: >+ // ADD_F64m, DIVR_F64m, DIV_F64m, FCOM64m, FCOMP64m, LD_F64m, MOVHPDmr, M... >+ printf64mem(MI, 0, O); >+ break; >+ case 9: >+ // CALL64pcrel32, CALLpcrel16, CALLpcrel32, EH_SjLj_Setup, JAE_1, JAE_2, ... >+ printPCRelImm(MI, 0, O); >+ break; >+ case 10: >+ // CMPPDrmi, CMPPSrmi, CMPSDrm, CMPSSrm, Int_CMPSDrm, Int_CMPSSrm >+ printSSECC(MI, 7, O); >+ break; >+ case 11: >+ // CMPPDrri, CMPPSrri, CMPSDrr, CMPSSrr, Int_CMPSDrr, Int_CMPSSrr >+ printSSECC(MI, 3, O); >+ break; >+ case 12: >+ // CMPSB >+ printSrcIdx8(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx8(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // CMPSL >+ printSrcIdx32(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx32(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // CMPSQ >+ printSrcIdx64(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx64(MI, 0, O); >+ return; >+ break; >+ case 15: >+ // CMPSW >+ printSrcIdx16(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx16(MI, 0, O); >+ return; >+ break; >+ case 16: >+ // CMPXCHG16B, LCMPXCHG16B, MOVDQAmr, MOVDQUmr, VEXTRACTI128mr, VEXTRACTI... >+ printi128mem(MI, 0, O); >+ break; >+ case 17: >+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, FXR... >+ printopaquemem(MI, 0, O); >+ return; >+ break; >+ case 18: >+ // INSB, MOVSB, SCASB, STOSB >+ printDstIdx8(MI, 0, O); >+ break; >+ case 19: >+ // INSL, MOVSL, SCASL, STOSL >+ printDstIdx32(MI, 0, O); >+ break; >+ case 20: >+ // INSW, MOVSW, SCASW, STOSW >+ printDstIdx16(MI, 0, O); >+ break; >+ case 21: >+ // Int_VCMPSDrm, Int_VCMPSSrm, VCMPPDYrmi, VCMPPDZrmi, VCMPPDrmi, VCMPPSY... >+ printAVXCC(MI, 7, O); >+ break; >+ case 22: >+ // Int_VCMPSDrr, Int_VCMPSSrr, VCMPPDYrri, VCMPPDZrri, VCMPPDZrrib, VCMPP... >+ printAVXCC(MI, 3, O); >+ break; >+ case 23: >+ // LD_F80m, ST_FP80m >+ printf80mem(MI, 0, O); >+ return; >+ break; >+ case 24: >+ // LODSB, OUTSB >+ printSrcIdx8(MI, 0, O); >+ return; >+ break; >+ case 25: >+ // LODSL, OUTSL >+ printSrcIdx32(MI, 0, O); >+ return; >+ break; >+ case 26: >+ // LODSQ >+ printSrcIdx64(MI, 0, O); >+ return; >+ break; >+ case 27: >+ // LODSW, OUTSW >+ printSrcIdx16(MI, 0, O); >+ return; >+ break; >+ case 28: >+ // LXADD16, XCHG16rm >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 29: >+ // LXADD32, XCHG32rm >+ printi32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 30: >+ // LXADD64, XCHG64rm >+ printi64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 31: >+ // LXADD8, XCHG8rm >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 32: >+ // MOV16ao16, MOV16ao16_16, MOV16o16a, MOV16o16a_16, MOV64ao16, MOV64o16a >+ printMemOffs16(MI, 0, O); >+ break; >+ case 33: >+ // MOV32ao32, MOV32ao32_16, MOV32o32a, MOV32o32a_16, MOV64ao32, MOV64o32a >+ printMemOffs32(MI, 0, O); >+ break; >+ case 34: >+ // MOV64ao64, MOV64o64a >+ printMemOffs64(MI, 0, O); >+ break; >+ case 35: >+ // MOV64ao8, MOV64o8a, MOV8ao8, MOV8ao8_16, MOV8o8a, MOV8o8a_16 >+ printMemOffs8(MI, 0, O); >+ break; >+ case 36: >+ // MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVNTPDmr, MOVNTPSmr, MOVUPDmr, MOVUPSm... >+ printf128mem(MI, 0, O); >+ break; >+ case 37: >+ // MOVSQ, SCASQ, STOSQ >+ printDstIdx64(MI, 0, O); >+ break; >+ case 38: >+ // VCVTPS2PHZmr, VEXTRACTF64x4mr, VMASKMOVPDYmr, VMASKMOVPSYmr, VMOVAPDYm... >+ printf256mem(MI, 0, O); >+ break; >+ case 39: >+ // VEXTRACTI64x4mr, VMOVDQA32Z256mr, VMOVDQA32Z256mrk, VMOVDQA64Z256mr, V... >+ printi256mem(MI, 0, O); >+ break; >+ case 40: >+ // VMOVAPDZmr, VMOVAPDZmrk, VMOVAPSZmr, VMOVAPSZmrk, VMOVNTPDZmr, VMOVNTP... >+ printf512mem(MI, 0, O); >+ break; >+ case 41: >+ // VMOVDQA32Zmr, VMOVDQA32Zmrk, VMOVDQA64Zmr, VMOVDQA64Zmrk, VMOVDQU16Zmr... >+ printi512mem(MI, 0, O); >+ break; >+ case 42: >+ // VPSCATTERDDZmr, VSCATTERDPSZmr >+ printi32mem(MI, 1, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "}, "); >+ printOperand(MI, 7, O); >+ return; >+ break; >+ case 43: >+ // VPSCATTERDQZmr, VPSCATTERQDZmr, VPSCATTERQQZmr, VSCATTERDPDZmr, VSCATT... >+ printi64mem(MI, 1, O); >+ SStream_concat0(O, " {"); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, "}, "); >+ printOperand(MI, 7, O); >+ return; >+ break; >+ case 44: >+ // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 5 bits for 24 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 20) & 31); >+ switch ((Bits >> 20) & 31) { >+ default: // unreachable. >+ case 0: >+ // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... >+ return; >+ break; >+ case 1: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // ADD_FrST0, DIVR_FrST0, DIV_FrST0, MUL_FrST0, ST_FPNCEST0r, ST_FPST0r, ... >+ SStream_concat0(O, ", st(0)"); >+ op_addReg(MI, X86_REG_ST0); >+ return; >+ break; >+ case 3: >+ // CMPPDrmi, CMPPDrri, VCMPPDYrmi, VCMPPDYrri, VCMPPDrmi, VCMPPDrri >+ SStream_concat0(O, "pd\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // CMPPSrmi, CMPPSrri, VCMPPSYrmi, VCMPPSYrri, VCMPPSrmi, VCMPPSrri >+ SStream_concat0(O, "ps\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // CMPSDrm, CMPSDrr, Int_CMPSDrm, Int_CMPSDrr, Int_VCMPSDrm, Int_VCMPSDrr... >+ SStream_concat0(O, "sd\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 6: >+ // CMPSSrm, CMPSSrr, Int_CMPSSrm, Int_CMPSSrr, Int_VCMPSSrm, Int_VCMPSSrr... >+ SStream_concat0(O, "ss\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 7: >+ // FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i >+ SStream_concat0(O, ":"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 8: >+ // INSB, INSL, INSW >+ SStream_concat0(O, ", dx"); >+ op_addReg(MI, X86_REG_DX); >+ return; >+ break; >+ case 9: >+ // MOV16ao16, MOV16ao16_16, MOV64ao16, OUT16ir, STOSW >+ SStream_concat0(O, ", ax"); >+ op_addReg(MI, X86_REG_AX); >+ return; >+ break; >+ case 10: >+ // MOV32ao32, MOV32ao32_16, MOV64ao32, OUT32ir, STOSL >+ SStream_concat0(O, ", eax"); >+ op_addReg(MI, X86_REG_EAX); >+ return; >+ break; >+ case 11: >+ // MOV64ao64, STOSQ >+ SStream_concat0(O, ", rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 12: >+ // MOV64ao8, MOV8ao8, MOV8ao8_16, OUT8ir, STOSB >+ SStream_concat0(O, ", al"); >+ op_addReg(MI, X86_REG_AL); >+ return; >+ break; >+ case 13: >+ // RCL16m1, RCL16r1, RCL32m1, RCL32r1, RCL64m1, RCL64r1, RCL8m1, RCL8r1, ... >+ SStream_concat0(O, ", 1"); >+ op_addImm(MI, 1); >+ return; >+ break; >+ case 14: >+ // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... >+ SStream_concat0(O, ", cl"); >+ op_addReg(MI, X86_REG_CL); >+ return; >+ break; >+ case 15: >+ // TAILJMPd, TAILJMPd64, TAILJMPm, TAILJMPm64, TAILJMPr64 >+ return; >+ break; >+ case 16: >+ // VADDPDZrmbk, VADDPDZrmbkz, VADDPDZrmk, VADDPDZrmkz, VADDPDZrrk, VADDPD... >+ SStream_concat0(O, " {"); >+ break; >+ case 17: >+ // VCMPPDZrmi, VCMPPDZrri, VCMPPDZrrib >+ SStream_concat0(O, "pd \t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 18: >+ // VCMPPSZrmi, VCMPPSZrri, VCMPPSZrrib >+ SStream_concat0(O, "ps \t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // VGATHERPF0DPDm, VGATHERPF0DPSm, VGATHERPF0QPDm, VGATHERPF0QPSm, VGATHE... >+ SStream_concat0(O, "}, "); >+ break; >+ case 20: >+ // VPCMPDZrmi, VPCMPDZrri >+ SStream_concat0(O, "d\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 21: >+ // VPCMPQZrmi, VPCMPQZrri >+ SStream_concat0(O, "q\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 22: >+ // VPCMPUDZrmi, VPCMPUDZrri >+ SStream_concat0(O, "ud\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 23: >+ // VPCMPUQZrmi, VPCMPUQZrri >+ SStream_concat0(O, "uq\t"); >+ printOperand(MI, 0, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ SStream_concat0(O, ", "); >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 6 bits for 34 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 25) & 63); >+ switch ((Bits >> 25) & 63) { >+ default: // unreachable. >+ case 0: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... >+ printOperand(MI, 5, O); >+ break; >+ case 1: >+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... >+ printi16mem(MI, 2, O); >+ break; >+ case 3: >+ // ADC32rm, ADCX32rm, ADD32rm, AND32rm, CMOVA32rm, CMOVAE32rm, CMOVB32rm,... >+ printi32mem(MI, 2, O); >+ break; >+ case 4: >+ // ADC64rm, ADCX64rm, ADD64rm, AND64rm, CMOVA64rm, CMOVAE64rm, CMOVB64rm,... >+ printi64mem(MI, 2, O); >+ break; >+ case 5: >+ // ADC8rm, ADD8rm, AND8rm, CRC32r32m8, CRC32r64m8, OR8rm, PINSRBrm, SBB8r... >+ printi8mem(MI, 2, O); >+ break; >+ case 6: >+ // ADDPDrm, ADDPSrm, ADDSUBPDrm, ADDSUBPSrm, ANDNPDrm, ANDNPSrm, ANDPDrm,... >+ printf128mem(MI, 2, O); >+ break; >+ case 7: >+ // ADDSDrm, ADDSDrm_Int, CMPSDrm, CMPSDrm_alt, DIVSDrm, DIVSDrm_Int, Int_... >+ printf64mem(MI, 2, O); >+ break; >+ case 8: >+ // ADDSSrm, ADDSSrm_Int, CMPSSrm, CMPSSrm_alt, DIVSSrm, DIVSSrm_Int, INSE... >+ printf32mem(MI, 2, O); >+ break; >+ case 9: >+ // ADOX32rm, BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLC... >+ printi32mem(MI, 1, O); >+ break; >+ case 10: >+ // ADOX32rr, ADOX64rr, AESIMCrr, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr... >+ printOperand(MI, 1, O); >+ break; >+ case 11: >+ // ADOX64rm, BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLC... >+ printi64mem(MI, 1, O); >+ break; >+ case 12: >+ // AESDECLASTrm, AESDECrm, AESENCLASTrm, AESENCrm, MPSADBWrmi, PACKSSDWrm... >+ printi128mem(MI, 2, O); >+ break; >+ case 13: >+ // AESIMCrm, AESKEYGENASSIST128rm, CVTDQ2PSrm, INVEPT32, INVEPT64, INVPCI... >+ printi128mem(MI, 1, O); >+ break; >+ case 14: >+ // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, KMOVWkm, LAR16rm, LA... >+ printi16mem(MI, 1, O); >+ break; >+ case 15: >+ // CMP8rm, KMOVBkm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64... >+ printi8mem(MI, 1, O); >+ break; >+ case 16: >+ // COMISDrm, COMISSrm, CVTPD2DQrm, CVTPD2PSrm, CVTPS2DQrm, CVTTPD2DQrm, C... >+ printf128mem(MI, 1, O); >+ break; >+ case 17: >+ // CVTPS2PDrm, CVTSD2SI64rm, CVTSD2SIrm, CVTSD2SSrm, CVTTSD2SI64rm, CVTTS... >+ printf64mem(MI, 1, O); >+ return; >+ break; >+ case 18: >+ // CVTSS2SDrm, CVTSS2SI64rm, CVTSS2SIrm, CVTTSS2SI64rm, CVTTSS2SIrm, Int_... >+ printf32mem(MI, 1, O); >+ return; >+ break; >+ case 19: >+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... >+ printopaquemem(MI, 1, O); >+ return; >+ break; >+ case 20: >+ // MOVSB >+ printSrcIdx8(MI, 1, O); >+ return; >+ break; >+ case 21: >+ // MOVSL >+ printSrcIdx32(MI, 1, O); >+ return; >+ break; >+ case 22: >+ // MOVSQ >+ printSrcIdx64(MI, 1, O); >+ return; >+ break; >+ case 23: >+ // MOVSW >+ printSrcIdx16(MI, 1, O); >+ return; >+ break; >+ case 24: >+ // NOOP19rr >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 25: >+ // VBROADCASTI64X4rm, VCVTDQ2PDZrm, VCVTDQ2PSYrm, VLDDQUYrm, VMOVDQA32Z25... >+ printi256mem(MI, 1, O); >+ break; >+ case 26: >+ // VCMPPDZrmi, VCMPPSZrmi >+ printf512mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printAVXCC(MI, 7, O); >+ return; >+ break; >+ case 27: >+ // VCVTDQ2PSZrm, VMOVDQA32Zrm, VMOVDQA64Zrm, VMOVDQU16Zrm, VMOVDQU32Zrm, ... >+ printi512mem(MI, 1, O); >+ break; >+ case 28: >+ // VCVTPD2DQYrm, VCVTPD2PSYrm, VCVTPH2PSZrm, VCVTPS2DQYrm, VCVTPS2PDZrm, ... >+ printf256mem(MI, 1, O); >+ break; >+ case 29: >+ // VCVTPD2DQZrm, VCVTPD2PSZrm, VCVTPD2UDQZrm, VCVTPS2DQZrm, VCVTPS2UDQZrm... >+ printf512mem(MI, 1, O); >+ break; >+ case 30: >+ // VGATHERDPDYrm, VGATHERDPDrm, VGATHERQPDYrm, VGATHERQPDrm, VPGATHERDQYr... >+ printi64mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 8, O); >+ return; >+ break; >+ case 31: >+ // VGATHERDPDZrm, VGATHERDPSZrm, VGATHERQPDZrm, VGATHERQPSZrm, VPGATHERDD... >+ printOperand(MI, 3, O); >+ SStream_concat0(O, "}, "); >+ break; >+ case 32: >+ // VGATHERDPSYrm, VGATHERDPSrm, VGATHERQPSYrm, VGATHERQPSrm, VPGATHERDDYr... >+ printi32mem(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 8, O); >+ return; >+ break; >+ case 33: >+ // VPCMPDZrmi, VPCMPQZrmi, VPCMPUDZrmi, VPCMPUQZrmi >+ printi512mem(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 4 bits for 11 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 31) & 15); >+ switch ((Bits >> 31) & 15) { >+ default: // unreachable. >+ case 0: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... >+ return; >+ break; >+ case 1: >+ // AESKEYGENASSIST128rm, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // MOV8mr_NOREX, MOV8rm_NOREX, MOV8rr_NOREX >+ return; >+ break; >+ case 3: >+ // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... >+ SStream_concat0(O, ", cl"); >+ op_addReg(MI, X86_REG_CL); >+ return; >+ break; >+ case 4: >+ // VADDPDZrmbk, VADDPDZrmk, VADDPDZrrk, VADDPSZrmbk, VADDPSZrmk, VADDPSZr... >+ SStream_concat0(O, "}, "); >+ break; >+ case 5: >+ // VADDPDZrmbkz, VADDPDZrmkz, VADDPDZrrkz, VADDPSZrmbkz, VADDPSZrmkz, VAD... >+ SStream_concat0(O, "} {z}, "); >+ op_addAvxZeroOpmask(MI); >+ break; >+ case 6: >+ // VCMPPDZrrib, VCMPPSZrrib, VRCP28PDZrb, VRCP28PSZrb, VRSQRT28PDZrb, VRS... >+ SStream_concat0(O, ", {sae}"); >+ op_addAvxSae(MI); >+ return; >+ break; >+ case 7: >+ // VGATHERDPDZrm, VGATHERQPDZrm, VGATHERQPSZrm, VPGATHERDQZrm, VPGATHERQD... >+ printi64mem(MI, 4, O); >+ return; >+ break; >+ case 8: >+ // VGATHERDPSZrm, VPGATHERDDZrm >+ printi32mem(MI, 4, O); >+ return; >+ break; >+ case 9: >+ // VPABSDZrmb, VPCONFLICTDrmb, VPLZCNTDrmb >+ SStream_concat0(O, "{1to16}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ return; >+ break; >+ case 10: >+ // VPABSQZrmb, VPCONFLICTQrmb, VPLZCNTQrmb >+ SStream_concat0(O, "{1to8}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 5 bits for 27 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); >+ switch ((Bits >> 35) & 31) { >+ default: // unreachable. >+ case 0: >+ // AESKEYGENASSIST128rm, BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZ... >+ printOperand(MI, 6, O); >+ break; >+ case 1: >+ // AESKEYGENASSIST128rr, ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // ANDN32rm, Int_VCVTSI2SDZrm, Int_VCVTSI2SDrm, Int_VCVTSI2SSZrm, Int_VCV... >+ printi32mem(MI, 2, O); >+ break; >+ case 3: >+ // ANDN64rm, Int_VCVTSI2SD64Zrm, Int_VCVTSI2SD64rm, Int_VCVTSI2SS64Zrm, I... >+ printi64mem(MI, 2, O); >+ break; >+ case 4: >+ // BLENDPDrmi, BLENDPSrmi, CMPPDrmi_alt, CMPPSrmi_alt, CMPSDrm_alt, CMPSS... >+ printOperand(MI, 7, O); >+ return; >+ break; >+ case 5: >+ // BLENDPDrri, BLENDPSrri, CMPPDrri_alt, CMPPSrri_alt, CMPSDrr_alt, CMPSS... >+ printOperand(MI, 3, O); >+ break; >+ case 6: >+ // Int_VCMPSDrm, Int_VCVTSD2SSrm, VADDPDZrmb, VADDSDZrm, VADDSDrm, VADDSD... >+ printf64mem(MI, 2, O); >+ break; >+ case 7: >+ // Int_VCMPSSrm, Int_VCVTSS2SDrm, VADDPSZrmb, VADDSSZrm, VADDSSrm, VADDSS... >+ printf32mem(MI, 2, O); >+ break; >+ case 8: >+ // VADDPDYrm, VADDPSYrm, VADDSUBPDYrm, VADDSUBPSYrm, VANDNPDYrm, VANDNPSY... >+ printf256mem(MI, 2, O); >+ break; >+ case 9: >+ // VADDPDZrm, VADDPSZrm, VCMPPDZrmi_alt, VCMPPSZrmi_alt, VDIVPDZrm, VDIVP... >+ printf512mem(MI, 2, O); >+ break; >+ case 10: >+ // VADDPDrm, VADDPSrm, VADDSUBPDrm, VADDSUBPSrm, VANDNPDrm, VANDNPSrm, VA... >+ printf128mem(MI, 2, O); >+ break; >+ case 11: >+ // VAESDECLASTrm, VAESDECrm, VAESENCLASTrm, VAESENCrm, VBROADCASTI32X4krm... >+ printi128mem(MI, 2, O); >+ break; >+ case 12: >+ // VALIGNDrmi, VALIGNQrmi, VMOVDQA32Zrmkz, VMOVDQA64Zrmkz, VMOVDQU16Zrmkz... >+ printi512mem(MI, 2, O); >+ break; >+ case 13: >+ // VBROADCASTI64X4krm, VDPPSYrmi, VINSERTF64x4rm, VINSERTI64x4rm, VMOVDQA... >+ printi256mem(MI, 2, O); >+ break; >+ case 14: >+ // VCVTDQ2PSZrrb, VCVTPD2DQZrrb, VCVTPD2PSZrrb, VCVTPD2UDQZrrb, VCVTPS2DQ... >+ printRoundingControl(MI, 2, O); >+ return; >+ break; >+ case 15: >+ // VFMADD132PDZm, VFMADD132PSZm, VFMADD213PDZm, VFMADD213PSZm, VFMADDSUB1... >+ printf512mem(MI, 3, O); >+ return; >+ break; >+ case 16: >+ // VFMADD132PDZmb, VFMADD213PDZmb, VFMADDSDr132m, VFMADDSDr213m, VFMADDSD... >+ printf64mem(MI, 3, O); >+ break; >+ case 17: >+ // VFMADD132PSZmb, VFMADD213PSZmb, VFMADDSSr132m, VFMADDSSr213m, VFMADDSS... >+ printf32mem(MI, 3, O); >+ break; >+ case 18: >+ // VFMADDPDr132m, VFMADDPDr213m, VFMADDPDr231m, VFMADDPSr132m, VFMADDPSr2... >+ printf128mem(MI, 3, O); >+ return; >+ break; >+ case 19: >+ // VFMADDPDr132mY, VFMADDPDr213mY, VFMADDPDr231mY, VFMADDPSr132mY, VFMADD... >+ printf256mem(MI, 3, O); >+ return; >+ break; >+ case 20: >+ // VMOVDQA32Z128rmk, VMOVDQA64Z128rmk, VMOVDQU16Z128rmk, VMOVDQU32Z128rmk... >+ printi128mem(MI, 3, O); >+ return; >+ break; >+ case 21: >+ // VMOVDQA32Z256rmk, VMOVDQA64Z256rmk, VMOVDQU16Z256rmk, VMOVDQU32Z256rmk... >+ printi256mem(MI, 3, O); >+ return; >+ break; >+ case 22: >+ // VMOVDQA32Zrmk, VMOVDQA64Zrmk, VMOVDQU16Zrmk, VMOVDQU32Zrmk, VMOVDQU64Z... >+ printi512mem(MI, 3, O); >+ return; >+ break; >+ case 23: >+ // VPCONFLICTDrmbk, VPLZCNTDrmbk >+ printi32mem(MI, 3, O); >+ SStream_concat0(O, "{1to16}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ return; >+ break; >+ case 24: >+ // VPCONFLICTQrmbk, VPLZCNTQrmbk >+ printi64mem(MI, 3, O); >+ SStream_concat0(O, "{1to8}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ return; >+ break; >+ case 25: >+ // VPINSRBrm >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 7, O); >+ return; >+ break; >+ case 26: >+ // VPINSRWrmi >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 7, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 3 bits for 7 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 7); >+ switch ((Bits >> 40) & 7) { >+ default: // unreachable. >+ case 0: >+ // AESKEYGENASSIST128rm, AESKEYGENASSIST128rr, ANDN32rm, ANDN32rr, ANDN64... >+ return; >+ break; >+ case 1: >+ // INSERTQI, VAARG_64, VADDPDZrmbk, VADDPDZrmbkz, VADDPDZrmk, VADDPDZrmkz... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // VADDPDZrmb, VDIVPDZrmb, VFMADD132PDZmb, VFMADD213PDZmb, VFMADDSUB132PD... >+ SStream_concat0(O, "{1to8}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ return; >+ break; >+ case 3: >+ // VADDPSZrmb, VDIVPSZrmb, VFMADD132PSZmb, VFMADD213PSZmb, VFMADDSUB132PS... >+ SStream_concat0(O, "{1to16}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ return; >+ break; >+ case 4: >+ // VPCMPEQDZ128rmb, VPCMPEQQZ256rmb, VPCMPGTDZ128rmb, VPCMPGTQZ256rmb >+ SStream_concat0(O, "{1to4}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_4); >+ return; >+ break; >+ case 5: >+ // VPCMPEQQZ128rmb, VPCMPGTQZ128rmb >+ SStream_concat0(O, "{1to2}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_2); >+ return; >+ break; >+ case 6: >+ // VRCP28SDrrb, VRCP28SSrrb, VRSQRT28SDrrb, VRSQRT28SSrrb >+ SStream_concat0(O, ", {sae}"); >+ op_addAvxSae(MI); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 6 encoded into 4 bits for 16 unique commands. >+ //printf("Frag-6: %"PRIu64"\n", (Bits >> 43) & 15); >+ switch ((Bits >> 43) & 15) { >+ default: // unreachable. >+ case 0: >+ // INSERTQI, VALIGNDrrik, VALIGNQrrik, VFMADD213PDZrk, VFMADD213PDZrkz, V... >+ printOperand(MI, 4, O); >+ break; >+ case 1: >+ // VAARG_64, VALIGNDrmi, VALIGNQrmi, VBLENDPDYrmi, VBLENDPDrmi, VBLENDPSY... >+ printOperand(MI, 7, O); >+ break; >+ case 2: >+ // VADDPDZrmbk, VADDPDZrmbkz, VDIVPDZrmbk, VDIVPDZrmbkz, VFMADDSD4rm, VFM... >+ printf64mem(MI, 3, O); >+ break; >+ case 3: >+ // VADDPDZrmk, VADDPDZrmkz, VADDPSZrmk, VADDPSZrmkz, VBLENDMPDZrm, VBLEND... >+ printf512mem(MI, 3, O); >+ return; >+ break; >+ case 4: >+ // VADDPDZrrk, VADDPDZrrkz, VADDPSZrrk, VADDPSZrrkz, VALIGNDrri, VALIGNDr... >+ printOperand(MI, 3, O); >+ break; >+ case 5: >+ // VADDPSZrmbk, VADDPSZrmbkz, VDIVPSZrmbk, VDIVPSZrmbkz, VFMADDSS4rm, VFM... >+ printf32mem(MI, 3, O); >+ break; >+ case 6: >+ // VFMADDPD4rm, VFMADDPS4rm, VFMADDSUBPD4rm, VFMADDSUBPS4rm, VFMSUBADDPD4... >+ printf128mem(MI, 3, O); >+ break; >+ case 7: >+ // VFMADDPD4rmY, VFMADDPS4rmY, VFMADDSUBPD4rmY, VFMADDSUBPS4rmY, VFMSUBAD... >+ printf256mem(MI, 3, O); >+ break; >+ case 8: >+ // VPADDDZrmbk, VPANDDZrmbk, VPANDNDZrmbk, VPMAXSDZrmbk, VPMAXUDZrmbk, VP... >+ printi32mem(MI, 4, O); >+ SStream_concat0(O, "{1to16}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ return; >+ break; >+ case 9: >+ // VPADDDZrmbkz, VPANDDZrmbkz, VPANDNDZrmbkz, VPCMPEQDZ128rmbk, VPCMPEQDZ... >+ printi32mem(MI, 3, O); >+ break; >+ case 10: >+ // VPADDDZrmk, VPADDQZrmk, VPANDDZrmk, VPANDNDZrmk, VPANDNQZrmk, VPANDQZr... >+ printi512mem(MI, 4, O); >+ return; >+ break; >+ case 11: >+ // VPADDDZrmkz, VPADDQZrmkz, VPANDDZrmkz, VPANDNDZrmkz, VPANDNQZrmkz, VPA... >+ printi512mem(MI, 3, O); >+ break; >+ case 12: >+ // VPADDQZrmbk, VPANDNQZrmbk, VPANDQZrmbk, VPMAXSQZrmbk, VPMAXUQZrmbk, VP... >+ printi64mem(MI, 4, O); >+ SStream_concat0(O, "{1to8}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ return; >+ break; >+ case 13: >+ // VPADDQZrmbkz, VPANDNQZrmbkz, VPANDQZrmbkz, VPCMPEQQZ128rmbk, VPCMPEQQZ... >+ printi64mem(MI, 3, O); >+ break; >+ case 14: >+ // VPCMOVrm, VPCMPEQBZ128rmk, VPCMPEQDZ128rmk, VPCMPEQQZ128rmk, VPCMPEQWZ... >+ printi128mem(MI, 3, O); >+ return; >+ break; >+ case 15: >+ // VPCMOVrmY, VPCMPEQBZ256rmk, VPCMPEQDZ256rmk, VPCMPEQQZ256rmk, VPCMPEQW... >+ printi256mem(MI, 3, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 7 encoded into 3 bits for 6 unique commands. >+ //printf("Frag-7: %"PRIu64"\n", (Bits >> 47) & 7); >+ switch ((Bits >> 47) & 7) { >+ default: // unreachable. >+ case 0: >+ // INSERTQI, VADDPDZrrk, VADDPDZrrkz, VADDPSZrrk, VADDPSZrrkz, VALIGNDrmi... >+ return; >+ break; >+ case 1: >+ // VAARG_64, VALIGNDrrik, VALIGNDrrikz, VALIGNQrrik, VALIGNQrrikz, VPCMPD... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // VADDPDZrmbk, VADDPDZrmbkz, VDIVPDZrmbk, VDIVPDZrmbkz, VMAXPDZrmbk, VMA... >+ SStream_concat0(O, "{1to8}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_8); >+ return; >+ break; >+ case 3: >+ // VADDPSZrmbk, VADDPSZrmbkz, VDIVPSZrmbk, VDIVPSZrmbkz, VMAXPSZrmbk, VMA... >+ SStream_concat0(O, "{1to16}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_16); >+ return; >+ break; >+ case 4: >+ // VPCMPEQDZ128rmbk, VPCMPEQQZ256rmbk, VPCMPGTDZ128rmbk, VPCMPGTQZ256rmbk >+ SStream_concat0(O, "{1to4}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_4); >+ return; >+ break; >+ case 5: >+ // VPCMPEQQZ128rmbk, VPCMPGTQZ128rmbk >+ SStream_concat0(O, "{1to2}"); >+ op_addAvxBroadcast(MI, X86_AVX_BCAST_2); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 8 encoded into 2 bits for 3 unique commands. >+ //printf("Frag-8: %"PRIu64"\n", (Bits >> 50) & 3); >+ switch ((Bits >> 50) & 3) { >+ default: // unreachable. >+ case 0: >+ // VAARG_64, VPCMPDZrmik_alt, VPCMPQZrmik_alt, VPCMPUDZrmik_alt, VPCMPUQZ... >+ printOperand(MI, 8, O); >+ return; >+ break; >+ case 1: >+ // VALIGNDrrik, VALIGNQrrik >+ printOperand(MI, 5, O); >+ return; >+ break; >+ case 2: >+ // VALIGNDrrikz, VALIGNQrrikz, VPCMPDZrrik_alt, VPCMPQZrrik_alt, VPCMPUDZ... >+ printOperand(MI, 4, O); >+ return; >+ break; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 234 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 't', '(', '0', ')', 0, >+ /* 6 */ 's', 't', '(', '1', ')', 0, >+ /* 12 */ 's', 't', '(', '2', ')', 0, >+ /* 18 */ 's', 't', '(', '3', ')', 0, >+ /* 24 */ 's', 't', '(', '4', ')', 0, >+ /* 30 */ 's', 't', '(', '5', ')', 0, >+ /* 36 */ 's', 't', '(', '6', ')', 0, >+ /* 42 */ 's', 't', '(', '7', ')', 0, >+ /* 48 */ 'x', 'm', 'm', '1', '0', 0, >+ /* 54 */ 'y', 'm', 'm', '1', '0', 0, >+ /* 60 */ 'z', 'm', 'm', '1', '0', 0, >+ /* 66 */ 'c', 'r', '1', '0', 0, >+ /* 71 */ 'x', 'm', 'm', '2', '0', 0, >+ /* 77 */ 'y', 'm', 'm', '2', '0', 0, >+ /* 83 */ 'z', 'm', 'm', '2', '0', 0, >+ /* 89 */ 'x', 'm', 'm', '3', '0', 0, >+ /* 95 */ 'y', 'm', 'm', '3', '0', 0, >+ /* 101 */ 'z', 'm', 'm', '3', '0', 0, >+ /* 107 */ 'k', '0', 0, >+ /* 110 */ 'x', 'm', 'm', '0', 0, >+ /* 115 */ 'y', 'm', 'm', '0', 0, >+ /* 120 */ 'z', 'm', 'm', '0', 0, >+ /* 125 */ 'f', 'p', '0', 0, >+ /* 129 */ 'c', 'r', '0', 0, >+ /* 133 */ 'd', 'r', '0', 0, >+ /* 137 */ 'x', 'm', 'm', '1', '1', 0, >+ /* 143 */ 'y', 'm', 'm', '1', '1', 0, >+ /* 149 */ 'z', 'm', 'm', '1', '1', 0, >+ /* 155 */ 'c', 'r', '1', '1', 0, >+ /* 160 */ 'x', 'm', 'm', '2', '1', 0, >+ /* 166 */ 'y', 'm', 'm', '2', '1', 0, >+ /* 172 */ 'z', 'm', 'm', '2', '1', 0, >+ /* 178 */ 'x', 'm', 'm', '3', '1', 0, >+ /* 184 */ 'y', 'm', 'm', '3', '1', 0, >+ /* 190 */ 'z', 'm', 'm', '3', '1', 0, >+ /* 196 */ 'k', '1', 0, >+ /* 199 */ 'x', 'm', 'm', '1', 0, >+ /* 204 */ 'y', 'm', 'm', '1', 0, >+ /* 209 */ 'z', 'm', 'm', '1', 0, >+ /* 214 */ 'f', 'p', '1', 0, >+ /* 218 */ 'c', 'r', '1', 0, >+ /* 222 */ 'd', 'r', '1', 0, >+ /* 226 */ 'x', 'm', 'm', '1', '2', 0, >+ /* 232 */ 'y', 'm', 'm', '1', '2', 0, >+ /* 238 */ 'z', 'm', 'm', '1', '2', 0, >+ /* 244 */ 'c', 'r', '1', '2', 0, >+ /* 249 */ 'x', 'm', 'm', '2', '2', 0, >+ /* 255 */ 'y', 'm', 'm', '2', '2', 0, >+ /* 261 */ 'z', 'm', 'm', '2', '2', 0, >+ /* 267 */ 'k', '2', 0, >+ /* 270 */ 'x', 'm', 'm', '2', 0, >+ /* 275 */ 'y', 'm', 'm', '2', 0, >+ /* 280 */ 'z', 'm', 'm', '2', 0, >+ /* 285 */ 'f', 'p', '2', 0, >+ /* 289 */ 'c', 'r', '2', 0, >+ /* 293 */ 'd', 'r', '2', 0, >+ /* 297 */ 'x', 'm', 'm', '1', '3', 0, >+ /* 303 */ 'y', 'm', 'm', '1', '3', 0, >+ /* 309 */ 'z', 'm', 'm', '1', '3', 0, >+ /* 315 */ 'c', 'r', '1', '3', 0, >+ /* 320 */ 'x', 'm', 'm', '2', '3', 0, >+ /* 326 */ 'y', 'm', 'm', '2', '3', 0, >+ /* 332 */ 'z', 'm', 'm', '2', '3', 0, >+ /* 338 */ 'k', '3', 0, >+ /* 341 */ 'x', 'm', 'm', '3', 0, >+ /* 346 */ 'y', 'm', 'm', '3', 0, >+ /* 351 */ 'z', 'm', 'm', '3', 0, >+ /* 356 */ 'f', 'p', '3', 0, >+ /* 360 */ 'c', 'r', '3', 0, >+ /* 364 */ 'd', 'r', '3', 0, >+ /* 368 */ 'x', 'm', 'm', '1', '4', 0, >+ /* 374 */ 'y', 'm', 'm', '1', '4', 0, >+ /* 380 */ 'z', 'm', 'm', '1', '4', 0, >+ /* 386 */ 'c', 'r', '1', '4', 0, >+ /* 391 */ 'x', 'm', 'm', '2', '4', 0, >+ /* 397 */ 'y', 'm', 'm', '2', '4', 0, >+ /* 403 */ 'z', 'm', 'm', '2', '4', 0, >+ /* 409 */ 'k', '4', 0, >+ /* 412 */ 'x', 'm', 'm', '4', 0, >+ /* 417 */ 'y', 'm', 'm', '4', 0, >+ /* 422 */ 'z', 'm', 'm', '4', 0, >+ /* 427 */ 'f', 'p', '4', 0, >+ /* 431 */ 'c', 'r', '4', 0, >+ /* 435 */ 'd', 'r', '4', 0, >+ /* 439 */ 'x', 'm', 'm', '1', '5', 0, >+ /* 445 */ 'y', 'm', 'm', '1', '5', 0, >+ /* 451 */ 'z', 'm', 'm', '1', '5', 0, >+ /* 457 */ 'c', 'r', '1', '5', 0, >+ /* 462 */ 'x', 'm', 'm', '2', '5', 0, >+ /* 468 */ 'y', 'm', 'm', '2', '5', 0, >+ /* 474 */ 'z', 'm', 'm', '2', '5', 0, >+ /* 480 */ 'k', '5', 0, >+ /* 483 */ 'x', 'm', 'm', '5', 0, >+ /* 488 */ 'y', 'm', 'm', '5', 0, >+ /* 493 */ 'z', 'm', 'm', '5', 0, >+ /* 498 */ 'f', 'p', '5', 0, >+ /* 502 */ 'c', 'r', '5', 0, >+ /* 506 */ 'd', 'r', '5', 0, >+ /* 510 */ 'x', 'm', 'm', '1', '6', 0, >+ /* 516 */ 'y', 'm', 'm', '1', '6', 0, >+ /* 522 */ 'z', 'm', 'm', '1', '6', 0, >+ /* 528 */ 'x', 'm', 'm', '2', '6', 0, >+ /* 534 */ 'y', 'm', 'm', '2', '6', 0, >+ /* 540 */ 'z', 'm', 'm', '2', '6', 0, >+ /* 546 */ 'k', '6', 0, >+ /* 549 */ 'x', 'm', 'm', '6', 0, >+ /* 554 */ 'y', 'm', 'm', '6', 0, >+ /* 559 */ 'z', 'm', 'm', '6', 0, >+ /* 564 */ 'f', 'p', '6', 0, >+ /* 568 */ 'c', 'r', '6', 0, >+ /* 572 */ 'd', 'r', '6', 0, >+ /* 576 */ 'x', 'm', 'm', '1', '7', 0, >+ /* 582 */ 'y', 'm', 'm', '1', '7', 0, >+ /* 588 */ 'z', 'm', 'm', '1', '7', 0, >+ /* 594 */ 'x', 'm', 'm', '2', '7', 0, >+ /* 600 */ 'y', 'm', 'm', '2', '7', 0, >+ /* 606 */ 'z', 'm', 'm', '2', '7', 0, >+ /* 612 */ 'k', '7', 0, >+ /* 615 */ 'x', 'm', 'm', '7', 0, >+ /* 620 */ 'y', 'm', 'm', '7', 0, >+ /* 625 */ 'z', 'm', 'm', '7', 0, >+ /* 630 */ 'f', 'p', '7', 0, >+ /* 634 */ 'c', 'r', '7', 0, >+ /* 638 */ 'd', 'r', '7', 0, >+ /* 642 */ 'x', 'm', 'm', '1', '8', 0, >+ /* 648 */ 'y', 'm', 'm', '1', '8', 0, >+ /* 654 */ 'z', 'm', 'm', '1', '8', 0, >+ /* 660 */ 'x', 'm', 'm', '2', '8', 0, >+ /* 666 */ 'y', 'm', 'm', '2', '8', 0, >+ /* 672 */ 'z', 'm', 'm', '2', '8', 0, >+ /* 678 */ 'x', 'm', 'm', '8', 0, >+ /* 683 */ 'y', 'm', 'm', '8', 0, >+ /* 688 */ 'z', 'm', 'm', '8', 0, >+ /* 693 */ 'c', 'r', '8', 0, >+ /* 697 */ 'x', 'm', 'm', '1', '9', 0, >+ /* 703 */ 'y', 'm', 'm', '1', '9', 0, >+ /* 709 */ 'z', 'm', 'm', '1', '9', 0, >+ /* 715 */ 'x', 'm', 'm', '2', '9', 0, >+ /* 721 */ 'y', 'm', 'm', '2', '9', 0, >+ /* 727 */ 'z', 'm', 'm', '2', '9', 0, >+ /* 733 */ 'x', 'm', 'm', '9', 0, >+ /* 738 */ 'y', 'm', 'm', '9', 0, >+ /* 743 */ 'z', 'm', 'm', '9', 0, >+ /* 748 */ 'c', 'r', '9', 0, >+ /* 752 */ 'r', '1', '0', 'b', 0, >+ /* 757 */ 'r', '1', '1', 'b', 0, >+ /* 762 */ 'r', '1', '2', 'b', 0, >+ /* 767 */ 'r', '1', '3', 'b', 0, >+ /* 772 */ 'r', '1', '4', 'b', 0, >+ /* 777 */ 'r', '1', '5', 'b', 0, >+ /* 782 */ 'r', '8', 'b', 0, >+ /* 786 */ 'r', '9', 'b', 0, >+ /* 790 */ 'r', '1', '0', 'd', 0, >+ /* 795 */ 'r', '1', '1', 'd', 0, >+ /* 800 */ 'r', '1', '2', 'd', 0, >+ /* 805 */ 'r', '1', '3', 'd', 0, >+ /* 810 */ 'r', '1', '4', 'd', 0, >+ /* 815 */ 'r', '1', '5', 'd', 0, >+ /* 820 */ 'r', '8', 'd', 0, >+ /* 824 */ 'r', '9', 'd', 0, >+ /* 828 */ 'a', 'h', 0, >+ /* 831 */ 'b', 'h', 0, >+ /* 834 */ 'c', 'h', 0, >+ /* 837 */ 'd', 'h', 0, >+ /* 840 */ 'e', 'd', 'i', 0, >+ /* 844 */ 'r', 'd', 'i', 0, >+ /* 848 */ 'e', 's', 'i', 0, >+ /* 852 */ 'r', 's', 'i', 0, >+ /* 856 */ 'a', 'l', 0, >+ /* 859 */ 'b', 'l', 0, >+ /* 862 */ 'c', 'l', 0, >+ /* 865 */ 'd', 'l', 0, >+ /* 868 */ 'd', 'i', 'l', 0, >+ /* 872 */ 's', 'i', 'l', 0, >+ /* 876 */ 'b', 'p', 'l', 0, >+ /* 880 */ 's', 'p', 'l', 0, >+ /* 884 */ 'e', 'b', 'p', 0, >+ /* 888 */ 'r', 'b', 'p', 0, >+ /* 892 */ 'e', 'i', 'p', 0, >+ /* 896 */ 'r', 'i', 'p', 0, >+ /* 900 */ 'e', 's', 'p', 0, >+ /* 904 */ 'r', 's', 'p', 0, >+ /* 908 */ 'c', 's', 0, >+ /* 911 */ 'd', 's', 0, >+ /* 914 */ 'e', 's', 0, >+ /* 917 */ 'f', 's', 0, >+ /* 920 */ 'f', 'l', 'a', 'g', 's', 0, >+ /* 926 */ 's', 's', 0, >+ /* 929 */ 'r', '1', '0', 'w', 0, >+ /* 934 */ 'r', '1', '1', 'w', 0, >+ /* 939 */ 'r', '1', '2', 'w', 0, >+ /* 944 */ 'r', '1', '3', 'w', 0, >+ /* 949 */ 'r', '1', '4', 'w', 0, >+ /* 954 */ 'r', '1', '5', 'w', 0, >+ /* 959 */ 'r', '8', 'w', 0, >+ /* 963 */ 'r', '9', 'w', 0, >+ /* 967 */ 'f', 'p', 's', 'w', 0, >+ /* 972 */ 'e', 'a', 'x', 0, >+ /* 976 */ 'r', 'a', 'x', 0, >+ /* 980 */ 'e', 'b', 'x', 0, >+ /* 984 */ 'r', 'b', 'x', 0, >+ /* 988 */ 'e', 'c', 'x', 0, >+ /* 992 */ 'r', 'c', 'x', 0, >+ /* 996 */ 'e', 'd', 'x', 0, >+ /* 1000 */ 'r', 'd', 'x', 0, >+ /* 1004 */ 'e', 'i', 'z', 0, >+ /* 1008 */ 'r', 'i', 'z', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 828, 856, 973, 831, 859, 885, 876, 981, 834, 862, 908, 989, 837, 841, >+ 868, 865, 911, 997, 972, 884, 980, 988, 840, 996, 920, 892, 1004, 914, >+ 848, 900, 967, 917, 923, 893, 976, 888, 984, 992, 844, 1000, 896, 1008, >+ 852, 904, 849, 872, 901, 880, 926, 129, 218, 289, 360, 431, 502, 568, >+ 634, 693, 748, 66, 155, 244, 315, 386, 457, 133, 222, 293, 364, 435, >+ 506, 572, 638, 125, 214, 285, 356, 427, 498, 564, 630, 107, 196, 267, >+ 338, 409, 480, 546, 612, 111, 200, 271, 342, 413, 484, 550, 616, 694, >+ 749, 67, 156, 245, 316, 387, 458, 0, 6, 12, 18, 24, 30, 36, >+ 42, 110, 199, 270, 341, 412, 483, 549, 615, 678, 733, 48, 137, 226, >+ 297, 368, 439, 510, 576, 642, 697, 71, 160, 249, 320, 391, 462, 528, >+ 594, 660, 715, 89, 178, 115, 204, 275, 346, 417, 488, 554, 620, 683, >+ 738, 54, 143, 232, 303, 374, 445, 516, 582, 648, 703, 77, 166, 255, >+ 326, 397, 468, 534, 600, 666, 721, 95, 184, 120, 209, 280, 351, 422, >+ 493, 559, 625, 688, 743, 60, 149, 238, 309, 380, 451, 522, 588, 654, >+ 709, 83, 172, 261, 332, 403, 474, 540, 606, 672, 727, 101, 190, 782, >+ 786, 752, 757, 762, 767, 772, 777, 820, 824, 790, 795, 800, 805, 810, >+ 815, 959, 963, 929, 934, 939, 944, 949, 954, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+#ifndef CAPSTONE_DIET >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+ switch (PrintMethodIdx) { >+ default: >+ // llvm_unreachable("Unknown PrintMethod kind"); >+ break; >+ case 0: >+ printf64mem(MI, OpIdx, OS); >+ break; >+ } >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ MCRegisterInfo *MRI = (MCRegisterInfo *)info; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case X86_AAD8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAD8i8 10) >+ AsmString = "aad"; >+ break; >+ } >+ return NULL; >+ case X86_AAM8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAM8i8 10) >+ AsmString = "aam"; >+ break; >+ } >+ return NULL; >+ case X86_CVTSD2SI64rm: >+ if (MCInst_getNumOperands(MI) == 6 && >+ MCOperand_isReg(MCInst_getOperand(MI, 0)) && >+ GETREGCLASS_CONTAIN(X86_GR64RegClassID, 0)) { >+ // (CVTSD2SI64rm GR64:$dst, sdmem:$src) >+ AsmString = "cvtsd2si $\x01, $\xFF\x02\x01"; >+ break; >+ } >+ return NULL; >+ case X86_XSTORE: >+ if (MCInst_getNumOperands(MI) == 0) { >+ // (XSTORE) >+ AsmString = "xstorerng"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1_reduce.inc b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1_reduce.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..00f71cd7a071f516fe6cbf75698a14647821f4f6 >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter1_reduce.inc >@@ -0,0 +1,2839 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 2566U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 2559U, // BUNDLE >+ 2622U, // LIFETIME_START >+ 2546U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 2637U, // AAA >+ 4269U, // AAD8i8 >+ 4749U, // AAM8i8 >+ 3179U, // AAS >+ 2301U, // ACQUIRE_MOV16rm >+ 2301U, // ACQUIRE_MOV32rm >+ 2301U, // ACQUIRE_MOV64rm >+ 2301U, // ACQUIRE_MOV8rm >+ 5486U, // ADC16i16 >+ 139395U, // ADC16mi >+ 139395U, // ADC16mi8 >+ 139395U, // ADC16mr >+ 2240643U, // ADC16ri >+ 2240643U, // ADC16ri8 >+ 4337795U, // ADC16rm >+ 2240643U, // ADC16rr >+ 2232451U, // ADC16rr_REV >+ 5622U, // ADC32i32 >+ 147587U, // ADC32mi >+ 147587U, // ADC32mi8 >+ 147587U, // ADC32mr >+ 2240643U, // ADC32ri >+ 2240643U, // ADC32ri8 >+ 6434947U, // ADC32rm >+ 2240643U, // ADC32rr >+ 2232451U, // ADC32rr_REV >+ 5770U, // ADC64i32 >+ 151683U, // ADC64mi32 >+ 151683U, // ADC64mi8 >+ 151683U, // ADC64mr >+ 2240643U, // ADC64ri32 >+ 2240643U, // ADC64ri8 >+ 8532099U, // ADC64rm >+ 2240643U, // ADC64rr >+ 2232451U, // ADC64rr_REV >+ 5384U, // ADC8i8 >+ 155779U, // ADC8mi >+ 155779U, // ADC8mr >+ 2240643U, // ADC8ri >+ 10629251U, // ADC8rm >+ 2240643U, // ADC8rr >+ 2232451U, // ADC8rr_REV >+ 6427796U, // ADCX32rm >+ 2233492U, // ADCX32rr >+ 8524948U, // ADCX64rm >+ 2233492U, // ADCX64rr >+ 5495U, // ADD16i16 >+ 139451U, // ADD16mi >+ 139451U, // ADD16mi8 >+ 139451U, // ADD16mr >+ 2240699U, // ADD16ri >+ 2240699U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 4337851U, // ADD16rm >+ 2240699U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 2232507U, // ADD16rr_REV >+ 5632U, // ADD32i32 >+ 147643U, // ADD32mi >+ 147643U, // ADD32mi8 >+ 147643U, // ADD32mr >+ 2240699U, // ADD32ri >+ 2240699U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 6435003U, // ADD32rm >+ 2240699U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 2232507U, // ADD32rr_REV >+ 5780U, // ADD64i32 >+ 151739U, // ADD64mi32 >+ 151739U, // ADD64mi8 >+ 151739U, // ADD64mr >+ 2240699U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 2240699U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 8532155U, // ADD64rm >+ 2240699U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 2232507U, // ADD64rr_REV >+ 5393U, // ADD8i8 >+ 155835U, // ADD8mi >+ 155835U, // ADD8mr >+ 2240699U, // ADD8ri >+ 2240699U, // ADD8ri8 >+ 10629307U, // ADD8rm >+ 2240699U, // ADD8rr >+ 2232507U, // ADD8rr_REV >+ 2576U, // ADJCALLSTACKDOWN32 >+ 2576U, // ADJCALLSTACKDOWN64 >+ 2594U, // ADJCALLSTACKUP32 >+ 2594U, // ADJCALLSTACKUP64 >+ 12719270U, // ADOX32rm >+ 14816422U, // ADOX32rr >+ 16913574U, // ADOX64rm >+ 14816422U, // ADOX64rr >+ 5504U, // AND16i16 >+ 139500U, // AND16mi >+ 139500U, // AND16mi8 >+ 139500U, // AND16mr >+ 2240748U, // AND16ri >+ 2240748U, // AND16ri8 >+ 4337900U, // AND16rm >+ 2240748U, // AND16rr >+ 2232556U, // AND16rr_REV >+ 5642U, // AND32i32 >+ 147692U, // AND32mi >+ 147692U, // AND32mi8 >+ 147692U, // AND32mr >+ 2240748U, // AND32ri >+ 2240748U, // AND32ri8 >+ 6435052U, // AND32rm >+ 2240748U, // AND32rr >+ 2232556U, // AND32rr_REV >+ 5790U, // AND64i32 >+ 151788U, // AND64mi32 >+ 151788U, // AND64mi8 >+ 151788U, // AND64mr >+ 2240748U, // AND64ri32 >+ 2240748U, // AND64ri8 >+ 8532204U, // AND64rm >+ 2240748U, // AND64rr >+ 2232556U, // AND64rr_REV >+ 5402U, // AND8i8 >+ 155884U, // AND8mi >+ 155884U, // AND8mr >+ 2240748U, // AND8ri >+ 2240748U, // AND8ri8 >+ 10629356U, // AND8rm >+ 2240748U, // AND8rr >+ 2232556U, // AND8rr_REV >+ 81924754U, // ANDN32rm >+ 350360210U, // ANDN32rr >+ 618795666U, // ANDN64rm >+ 350360210U, // ANDN64rr >+ 139887U, // ARPL16mr >+ 14815855U, // ARPL16rr >+ 885134227U, // BEXTR32rm >+ 350360467U, // BEXTR32rr >+ 889328531U, // BEXTR64rm >+ 350360467U, // BEXTR64rr >+ 885134227U, // BEXTRI32mi >+ 350360467U, // BEXTRI32ri >+ 889328531U, // BEXTRI64mi >+ 350360467U, // BEXTRI64ri >+ 12718680U, // BLCFILL32rm >+ 14815832U, // BLCFILL32rr >+ 16912984U, // BLCFILL64rm >+ 14815832U, // BLCFILL64rr >+ 12718613U, // BLCI32rm >+ 14815765U, // BLCI32rr >+ 16912917U, // BLCI64rm >+ 14815765U, // BLCI64rr >+ 12718221U, // BLCIC32rm >+ 14815373U, // BLCIC32rr >+ 16912525U, // BLCIC64rm >+ 14815373U, // BLCIC64rr >+ 12718631U, // BLCMSK32rm >+ 14815783U, // BLCMSK32rr >+ 16912935U, // BLCMSK64rm >+ 14815783U, // BLCMSK64rr >+ 12719010U, // BLCS32rm >+ 14816162U, // BLCS32rr >+ 16913314U, // BLCS64rm >+ 14816162U, // BLCS64rr >+ 12718689U, // BLSFILL32rm >+ 14815841U, // BLSFILL32rr >+ 16912993U, // BLSFILL64rm >+ 14815841U, // BLSFILL64rr >+ 12718625U, // BLSI32rm >+ 14815777U, // BLSI32rr >+ 16912929U, // BLSI64rm >+ 14815777U, // BLSI64rr >+ 12718228U, // BLSIC32rm >+ 14815380U, // BLSIC32rr >+ 16912532U, // BLSIC64rm >+ 14815380U, // BLSIC64rr >+ 12718639U, // BLSMSK32rm >+ 14815791U, // BLSMSK32rr >+ 16912943U, // BLSMSK64rm >+ 14815791U, // BLSMSK64rr >+ 12718974U, // BLSR32rm >+ 14816126U, // BLSR32rr >+ 16913278U, // BLSR64rm >+ 14816126U, // BLSR64rr >+ 12718321U, // BOUNDS16rm >+ 16912625U, // BOUNDS32rm >+ 19010013U, // BSF16rm >+ 14815709U, // BSF16rr >+ 12718557U, // BSF32rm >+ 14815709U, // BSF32rr >+ 16912861U, // BSF64rm >+ 14815709U, // BSF64rr >+ 19010425U, // BSR16rm >+ 14816121U, // BSR16rr >+ 12718969U, // BSR32rm >+ 14816121U, // BSR32rr >+ 16913273U, // BSR64rm >+ 14816121U, // BSR64rr >+ 4804U, // BSWAP32r >+ 4804U, // BSWAP64r >+ 140267U, // BT16mi8 >+ 140267U, // BT16mr >+ 14816235U, // BT16ri8 >+ 14816235U, // BT16rr >+ 148459U, // BT32mi8 >+ 148459U, // BT32mr >+ 14816235U, // BT32ri8 >+ 14816235U, // BT32rr >+ 152555U, // BT64mi8 >+ 152555U, // BT64mr >+ 14816235U, // BT64ri8 >+ 14816235U, // BT64rr >+ 139432U, // BTC16mi8 >+ 139432U, // BTC16mr >+ 14815400U, // BTC16ri8 >+ 14815400U, // BTC16rr >+ 147624U, // BTC32mi8 >+ 147624U, // BTC32mr >+ 14815400U, // BTC32ri8 >+ 14815400U, // BTC32rr >+ 151720U, // BTC64mi8 >+ 151720U, // BTC64mr >+ 14815400U, // BTC64ri8 >+ 14815400U, // BTC64rr >+ 140164U, // BTR16mi8 >+ 140164U, // BTR16mr >+ 14816132U, // BTR16ri8 >+ 14816132U, // BTR16rr >+ 148356U, // BTR32mi8 >+ 148356U, // BTR32mr >+ 14816132U, // BTR32ri8 >+ 14816132U, // BTR32rr >+ 152452U, // BTR64mi8 >+ 152452U, // BTR64mr >+ 14816132U, // BTR64ri8 >+ 14816132U, // BTR64rr >+ 140249U, // BTS16mi8 >+ 140249U, // BTS16mr >+ 14816217U, // BTS16ri8 >+ 14816217U, // BTS16rr >+ 148441U, // BTS32mi8 >+ 148441U, // BTS32mr >+ 14816217U, // BTS32ri8 >+ 14816217U, // BTS32rr >+ 152537U, // BTS64mi8 >+ 152537U, // BTS64mr >+ 14816217U, // BTS64ri8 >+ 14816217U, // BTS64rr >+ 885133851U, // BZHI32rm >+ 350360091U, // BZHI32rr >+ 889328155U, // BZHI64rm >+ 350360091U, // BZHI64rr >+ 8786U, // CALL16m >+ 4690U, // CALL16r >+ 16978U, // CALL32m >+ 4690U, // CALL32r >+ 21074U, // CALL64m >+ 29266U, // CALL64pcrel32 >+ 4690U, // CALL64r >+ 29266U, // CALLpcrel16 >+ 29266U, // CALLpcrel32 >+ 3378U, // CBW >+ 3099U, // CDQ >+ 2853U, // CDQE >+ 2706U, // CLAC >+ 2738U, // CLC >+ 2788U, // CLD >+ 2944U, // CLGI >+ 2954U, // CLI >+ 3322U, // CLTS >+ 2742U, // CMC >+ 4329519U, // CMOVA16rm >+ 2232367U, // CMOVA16rr >+ 6426671U, // CMOVA32rm >+ 2232367U, // CMOVA32rr >+ 8523823U, // CMOVA64rm >+ 2232367U, // CMOVA64rr >+ 4329773U, // CMOVAE16rm >+ 2232621U, // CMOVAE16rr >+ 6426925U, // CMOVAE32rm >+ 2232621U, // CMOVAE32rr >+ 8524077U, // CMOVAE64rm >+ 2232621U, // CMOVAE64rr >+ 4329596U, // CMOVB16rm >+ 2232444U, // CMOVB16rr >+ 6426748U, // CMOVB32rm >+ 2232444U, // CMOVB32rr >+ 8523900U, // CMOVB64rm >+ 2232444U, // CMOVB64rr >+ 4329793U, // CMOVBE16rm >+ 2232641U, // CMOVBE16rr >+ 6426945U, // CMOVBE32rm >+ 2232641U, // CMOVBE32rr >+ 8524097U, // CMOVBE64rm >+ 2232641U, // CMOVBE64rr >+ 4329942U, // CMOVE16rm >+ 2232790U, // CMOVE16rr >+ 6427094U, // CMOVE32rm >+ 2232790U, // CMOVE32rr >+ 8524246U, // CMOVE64rm >+ 2232790U, // CMOVE64rr >+ 4329992U, // CMOVG16rm >+ 2232840U, // CMOVG16rr >+ 6427144U, // CMOVG32rm >+ 2232840U, // CMOVG32rr >+ 8524296U, // CMOVG64rm >+ 2232840U, // CMOVG64rr >+ 4329813U, // CMOVGE16rm >+ 2232661U, // CMOVGE16rr >+ 6426965U, // CMOVGE32rm >+ 2232661U, // CMOVGE32rr >+ 8524117U, // CMOVGE64rm >+ 2232661U, // CMOVGE64rr >+ 4330118U, // CMOVL16rm >+ 2232966U, // CMOVL16rr >+ 6427270U, // CMOVL32rm >+ 2232966U, // CMOVL32rr >+ 8524422U, // CMOVL64rm >+ 2232966U, // CMOVL64rr >+ 4329837U, // CMOVLE16rm >+ 2232685U, // CMOVLE16rr >+ 6426989U, // CMOVLE32rm >+ 2232685U, // CMOVLE32rr >+ 8524141U, // CMOVLE64rm >+ 2232685U, // CMOVLE64rr >+ 4329865U, // CMOVNE16rm >+ 2232713U, // CMOVNE16rr >+ 6427017U, // CMOVNE32rm >+ 2232713U, // CMOVNE32rr >+ 8524169U, // CMOVNE64rm >+ 2232713U, // CMOVNE64rr >+ 4330159U, // CMOVNO16rm >+ 2233007U, // CMOVNO16rr >+ 6427311U, // CMOVNO32rm >+ 2233007U, // CMOVNO32rr >+ 8524463U, // CMOVNO64rm >+ 2233007U, // CMOVNO64rr >+ 4330220U, // CMOVNP16rm >+ 2233068U, // CMOVNP16rr >+ 6427372U, // CMOVNP32rm >+ 2233068U, // CMOVNP32rr >+ 8524524U, // CMOVNP64rm >+ 2233068U, // CMOVNP64rr >+ 4330444U, // CMOVNS16rm >+ 2233292U, // CMOVNS16rr >+ 6427596U, // CMOVNS32rm >+ 2233292U, // CMOVNS32rr >+ 8524748U, // CMOVNS64rm >+ 2233292U, // CMOVNS64rr >+ 4330173U, // CMOVO16rm >+ 2233021U, // CMOVO16rr >+ 6427325U, // CMOVO32rm >+ 2233021U, // CMOVO32rr >+ 8524477U, // CMOVO64rm >+ 2233021U, // CMOVO64rr >+ 4330266U, // CMOVP16rm >+ 2233114U, // CMOVP16rr >+ 6427418U, // CMOVP32rm >+ 2233114U, // CMOVP32rr >+ 8524570U, // CMOVP64rm >+ 2233114U, // CMOVP64rr >+ 4330468U, // CMOVS16rm >+ 2233316U, // CMOVS16rr >+ 6427620U, // CMOVS32rm >+ 2233316U, // CMOVS32rr >+ 8524772U, // CMOVS64rm >+ 2233316U, // CMOVS64rr >+ 2105U, // CMOV_FR32 >+ 2264U, // CMOV_FR64 >+ 1984U, // CMOV_GR16 >+ 1964U, // CMOV_GR32 >+ 2283U, // CMOV_GR8 >+ 2085U, // CMOV_RFP32 >+ 2244U, // CMOV_RFP64 >+ 2004U, // CMOV_RFP80 >+ 2044U, // CMOV_V16F32 >+ 2124U, // CMOV_V2F64 >+ 2184U, // CMOV_V2I64 >+ 2024U, // CMOV_V4F32 >+ 2144U, // CMOV_V4F64 >+ 2204U, // CMOV_V4I64 >+ 2065U, // CMOV_V8F32 >+ 2164U, // CMOV_V8F64 >+ 2224U, // CMOV_V8I64 >+ 5531U, // CMP16i16 >+ 139989U, // CMP16mi >+ 139989U, // CMP16mi8 >+ 139989U, // CMP16mr >+ 14815957U, // CMP16ri >+ 14815957U, // CMP16ri8 >+ 19010261U, // CMP16rm >+ 14815957U, // CMP16rr >+ 14815957U, // CMP16rr_REV >+ 5696U, // CMP32i32 >+ 148181U, // CMP32mi >+ 148181U, // CMP32mi8 >+ 148181U, // CMP32mr >+ 14815957U, // CMP32ri >+ 14815957U, // CMP32ri8 >+ 12718805U, // CMP32rm >+ 14815957U, // CMP32rr >+ 14815957U, // CMP32rr_REV >+ 5811U, // CMP64i32 >+ 152277U, // CMP64mi32 >+ 152277U, // CMP64mi8 >+ 152277U, // CMP64mr >+ 14815957U, // CMP64ri32 >+ 14815957U, // CMP64ri8 >+ 16913109U, // CMP64rm >+ 14815957U, // CMP64rr >+ 14815957U, // CMP64rr_REV >+ 5419U, // CMP8i8 >+ 156373U, // CMP8mi >+ 156373U, // CMP8mr >+ 14815957U, // CMP8ri >+ 21107413U, // CMP8rm >+ 14815957U, // CMP8rr >+ 14815957U, // CMP8rr_REV >+ 32867U, // CMPSB >+ 37131U, // CMPSL >+ 41775U, // CMPSQ >+ 46214U, // CMPSW >+ 49206U, // CMPXCHG16B >+ 139757U, // CMPXCHG16rm >+ 14815725U, // CMPXCHG16rr >+ 147949U, // CMPXCHG32rm >+ 14815725U, // CMPXCHG32rr >+ 152045U, // CMPXCHG64rm >+ 14815725U, // CMPXCHG64rr >+ 20546U, // CMPXCHG8B >+ 156141U, // CMPXCHG8rm >+ 14815725U, // CMPXCHG8rr >+ 2782U, // CPUID32 >+ 2782U, // CPUID64 >+ 3075U, // CQO >+ 2829U, // CWD >+ 2833U, // CWDE >+ 2641U, // DAA >+ 3183U, // DAS >+ 2531U, // DATA16_PREFIX >+ 8328U, // DEC16m >+ 4232U, // DEC16r >+ 4232U, // DEC32_16r >+ 4232U, // DEC32_32r >+ 16520U, // DEC32m >+ 4232U, // DEC32r >+ 8328U, // DEC64_16m >+ 4232U, // DEC64_16r >+ 16520U, // DEC64_32m >+ 4232U, // DEC64_32r >+ 20616U, // DEC64m >+ 4232U, // DEC64r >+ 24712U, // DEC8m >+ 4232U, // DEC8r >+ 9309U, // DIV16m >+ 5213U, // DIV16r >+ 17501U, // DIV32m >+ 5213U, // DIV32r >+ 21597U, // DIV64m >+ 5213U, // DIV64r >+ 25693U, // DIV8m >+ 5213U, // DIV8r >+ 5923U, // EH_RETURN >+ 5923U, // EH_RETURN64 >+ 2354U, // EH_SjLj_LongJmp32 >+ 2444U, // EH_SjLj_LongJmp64 >+ 2373U, // EH_SjLj_SetJmp32 >+ 2463U, // EH_SjLj_SetJmp64 >+ 29450U, // EH_SjLj_Setup >+ 14816085U, // ENTER >+ 275025U, // FARCALL16i >+ 53841U, // FARCALL16m >+ 275025U, // FARCALL32i >+ 53841U, // FARCALL32m >+ 53841U, // FARCALL64 >+ 275162U, // FARJMP16i >+ 53978U, // FARJMP16m >+ 275162U, // FARJMP32i >+ 53978U, // FARJMP32m >+ 53978U, // FARJMP64 >+ 3037U, // FSETPM >+ 2726U, // GETSEC >+ 3347U, // HLT >+ 9308U, // IDIV16m >+ 5212U, // IDIV16r >+ 17500U, // IDIV32m >+ 5212U, // IDIV32r >+ 21596U, // IDIV64m >+ 5212U, // IDIV64r >+ 25692U, // IDIV8m >+ 5212U, // IDIV8r >+ 8832U, // IMUL16m >+ 4736U, // IMUL16r >+ 4330112U, // IMUL16rm >+ 891425408U, // IMUL16rmi >+ 891425408U, // IMUL16rmi8 >+ 2232960U, // IMUL16rr >+ 350360192U, // IMUL16rri >+ 350360192U, // IMUL16rri8 >+ 17024U, // IMUL32m >+ 4736U, // IMUL32r >+ 6427264U, // IMUL32rm >+ 885133952U, // IMUL32rmi >+ 885133952U, // IMUL32rmi8 >+ 2232960U, // IMUL32rr >+ 350360192U, // IMUL32rri >+ 350360192U, // IMUL32rri8 >+ 21120U, // IMUL64m >+ 4736U, // IMUL64r >+ 8524416U, // IMUL64rm >+ 889328256U, // IMUL64rmi32 >+ 889328256U, // IMUL64rmi8 >+ 2232960U, // IMUL64rr >+ 350360192U, // IMUL64rri32 >+ 350360192U, // IMUL64rri8 >+ 25216U, // IMUL8m >+ 4736U, // IMUL8r >+ 5523U, // IN16ri >+ 3544U, // IN16rr >+ 5687U, // IN32ri >+ 3554U, // IN32rr >+ 5411U, // IN8ri >+ 3534U, // IN8rr >+ 8355U, // INC16m >+ 4259U, // INC16r >+ 4259U, // INC32_16r >+ 4259U, // INC32_32r >+ 16547U, // INC32m >+ 4259U, // INC32r >+ 8355U, // INC64_16m >+ 4259U, // INC64_16r >+ 16547U, // INC64_32m >+ 4259U, // INC64_32r >+ 20643U, // INC64m >+ 4259U, // INC64r >+ 24739U, // INC8m >+ 4259U, // INC8r >+ 450646U, // INSB >+ 454910U, // INSL >+ 459897U, // INSW >+ 5158U, // INT >+ 2349U, // INT1 >+ 2439U, // INT3 >+ 3079U, // INTO >+ 2824U, // INVD >+ 23204912U, // INVEPT32 >+ 23204912U, // INVEPT64 >+ 25082U, // INVLPG >+ 3500U, // INVLPGA32 >+ 3517U, // INVLPGA64 >+ 23204040U, // INVPCID32 >+ 23204040U, // INVPCID64 >+ 23204049U, // INVVPID32 >+ 23204049U, // INVVPID64 >+ 3327U, // IRET16 >+ 2812U, // IRET32 >+ 3142U, // IRET64 >+ 2610U, // Int_MemBarrier >+ 28961U, // JAE_1 >+ 28961U, // JAE_2 >+ 28961U, // JAE_4 >+ 28709U, // JA_1 >+ 28709U, // JA_2 >+ 28709U, // JA_4 >+ 28981U, // JBE_1 >+ 28981U, // JBE_2 >+ 28981U, // JBE_4 >+ 28754U, // JB_1 >+ 28754U, // JB_2 >+ 28754U, // JB_4 >+ 29907U, // JCXZ >+ 29900U, // JECXZ_32 >+ 29900U, // JECXZ_64 >+ 29021U, // JE_1 >+ 29021U, // JE_2 >+ 29021U, // JE_4 >+ 29001U, // JGE_1 >+ 29001U, // JGE_2 >+ 29001U, // JGE_4 >+ 29174U, // JG_1 >+ 29174U, // JG_2 >+ 29174U, // JG_4 >+ 29025U, // JLE_1 >+ 29025U, // JLE_2 >+ 29025U, // JLE_4 >+ 29261U, // JL_1 >+ 29261U, // JL_2 >+ 29261U, // JL_4 >+ 8923U, // JMP16m >+ 4827U, // JMP16r >+ 17115U, // JMP32m >+ 4827U, // JMP32r >+ 21211U, // JMP64m >+ 4827U, // JMP64r >+ 29403U, // JMP_1 >+ 29403U, // JMP_2 >+ 29403U, // JMP_4 >+ 29045U, // JNE_1 >+ 29045U, // JNE_2 >+ 29045U, // JNE_4 >+ 29347U, // JNO_1 >+ 29347U, // JNO_2 >+ 29347U, // JNO_4 >+ 29408U, // JNP_1 >+ 29408U, // JNP_2 >+ 29408U, // JNP_4 >+ 29632U, // JNS_1 >+ 29632U, // JNS_2 >+ 29632U, // JNS_4 >+ 29343U, // JO_1 >+ 29343U, // JO_2 >+ 29343U, // JO_4 >+ 29393U, // JP_1 >+ 29393U, // JP_2 >+ 29393U, // JP_4 >+ 29913U, // JRCXZ >+ 29628U, // JS_1 >+ 29628U, // JS_2 >+ 29628U, // JS_4 >+ 2909U, // LAHF >+ 19010374U, // LAR16rm >+ 14816070U, // LAR16rr >+ 19010374U, // LAR32rm >+ 14816070U, // LAR32rr >+ 19010374U, // LAR64rm >+ 14816070U, // LAR64rr >+ 139757U, // LCMPXCHG16 >+ 49206U, // LCMPXCHG16B >+ 147949U, // LCMPXCHG32 >+ 152045U, // LCMPXCHG64 >+ 156141U, // LCMPXCHG8 >+ 20546U, // LCMPXCHG8B >+ 25301928U, // LDS16rm >+ 25301928U, // LDS32rm >+ 19009568U, // LEA16r >+ 12718112U, // LEA32r >+ 12718112U, // LEA64_32r >+ 16912416U, // LEA64r >+ 2896U, // LEAVE >+ 2896U, // LEAVE64 >+ 25301933U, // LES16rm >+ 25301933U, // LES32rm >+ 25301938U, // LFS16rm >+ 25301938U, // LFS32rm >+ 25301938U, // LFS64rm >+ 54255U, // LGDT16m >+ 54255U, // LGDT32m >+ 54255U, // LGDT64m >+ 25301943U, // LGS16rm >+ 25301943U, // LGS32rm >+ 25301943U, // LGS64rm >+ 54267U, // LIDT16m >+ 54267U, // LIDT32m >+ 54267U, // LIDT64m >+ 9223U, // LLDT16m >+ 5127U, // LLDT16r >+ 9325U, // LMSW16m >+ 5229U, // LMSW16r >+ 139451U, // LOCK_ADD16mi >+ 139451U, // LOCK_ADD16mi8 >+ 139451U, // LOCK_ADD16mr >+ 147643U, // LOCK_ADD32mi >+ 147643U, // LOCK_ADD32mi8 >+ 147643U, // LOCK_ADD32mr >+ 151739U, // LOCK_ADD64mi32 >+ 151739U, // LOCK_ADD64mi8 >+ 151739U, // LOCK_ADD64mr >+ 155835U, // LOCK_ADD8mi >+ 155835U, // LOCK_ADD8mr >+ 139500U, // LOCK_AND16mi >+ 139500U, // LOCK_AND16mi8 >+ 139500U, // LOCK_AND16mr >+ 147692U, // LOCK_AND32mi >+ 147692U, // LOCK_AND32mi8 >+ 147692U, // LOCK_AND32mr >+ 151788U, // LOCK_AND64mi32 >+ 151788U, // LOCK_AND64mi8 >+ 151788U, // LOCK_AND64mr >+ 155884U, // LOCK_AND8mi >+ 155884U, // LOCK_AND8mr >+ 8328U, // LOCK_DEC16m >+ 16520U, // LOCK_DEC32m >+ 20616U, // LOCK_DEC64m >+ 24712U, // LOCK_DEC8m >+ 8355U, // LOCK_INC16m >+ 16547U, // LOCK_INC32m >+ 20643U, // LOCK_INC64m >+ 24739U, // LOCK_INC8m >+ 140130U, // LOCK_OR16mi >+ 140130U, // LOCK_OR16mi8 >+ 140130U, // LOCK_OR16mr >+ 148322U, // LOCK_OR32mi >+ 148322U, // LOCK_OR32mi8 >+ 148322U, // LOCK_OR32mr >+ 152418U, // LOCK_OR64mi32 >+ 152418U, // LOCK_OR64mi8 >+ 152418U, // LOCK_OR64mr >+ 156514U, // LOCK_OR8mi >+ 156514U, // LOCK_OR8mr >+ 2977U, // LOCK_PREFIX >+ 139383U, // LOCK_SUB16mi >+ 139383U, // LOCK_SUB16mi8 >+ 139383U, // LOCK_SUB16mr >+ 147575U, // LOCK_SUB32mi >+ 147575U, // LOCK_SUB32mi8 >+ 147575U, // LOCK_SUB32mr >+ 151671U, // LOCK_SUB64mi32 >+ 151671U, // LOCK_SUB64mi8 >+ 151671U, // LOCK_SUB64mr >+ 155767U, // LOCK_SUB8mi >+ 155767U, // LOCK_SUB8mr >+ 140142U, // LOCK_XOR16mi >+ 140142U, // LOCK_XOR16mi8 >+ 140142U, // LOCK_XOR16mr >+ 148334U, // LOCK_XOR32mi >+ 148334U, // LOCK_XOR32mi8 >+ 148334U, // LOCK_XOR32mr >+ 152430U, // LOCK_XOR64mi32 >+ 152430U, // LOCK_XOR64mi8 >+ 152430U, // LOCK_XOR64mr >+ 156526U, // LOCK_XOR8mi >+ 156526U, // LOCK_XOR8mr >+ 70900U, // LODSB >+ 75296U, // LODSL >+ 79561U, // LODSQ >+ 83415U, // LODSW >+ 29433U, // LOOP >+ 29073U, // LOOPE >+ 29050U, // LOOPNE >+ 4578U, // LRETIL >+ 4897U, // LRETIQ >+ 4578U, // LRETIW >+ 2930U, // LRETL >+ 3116U, // LRETQ >+ 2930U, // LRETW >+ 19010165U, // LSL16rm >+ 14815861U, // LSL16rr >+ 12718709U, // LSL32rm >+ 14815861U, // LSL32rr >+ 16913013U, // LSL64rm >+ 14815861U, // LSL64rr >+ 25301972U, // LSS16rm >+ 25301972U, // LSS32rm >+ 25301972U, // LSS64rm >+ 9097U, // LTRm >+ 5001U, // LTRr >+ 86202U, // LXADD16 >+ 90298U, // LXADD32 >+ 94394U, // LXADD64 >+ 98490U, // LXADD8 >+ 19010584U, // LZCNT16rm >+ 14816280U, // LZCNT16rr >+ 12719128U, // LZCNT32rm >+ 14816280U, // LZCNT32rr >+ 16913432U, // LZCNT64rm >+ 14816280U, // LZCNT64rr >+ 3029U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 627810U, // MOV16ao16 >+ 627810U, // MOV16ao16_16 >+ 140386U, // MOV16mi >+ 140386U, // MOV16mr >+ 140386U, // MOV16ms >+ 103875U, // MOV16o16a >+ 103875U, // MOV16o16a_16 >+ 14816354U, // MOV16ri >+ 14816354U, // MOV16ri_alt >+ 19010658U, // MOV16rm >+ 14816354U, // MOV16rr >+ 14816354U, // MOV16rr_REV >+ 14816354U, // MOV16rs >+ 19010658U, // MOV16sm >+ 14816354U, // MOV16sr >+ 762978U, // MOV32ao32 >+ 762978U, // MOV32ao32_16 >+ 14816354U, // MOV32cr >+ 14816354U, // MOV32dr >+ 148578U, // MOV32mi >+ 148578U, // MOV32mr >+ 140386U, // MOV32ms >+ 108140U, // MOV32o32a >+ 108140U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 14816354U, // MOV32rc >+ 14816354U, // MOV32rd >+ 14816354U, // MOV32ri >+ 0U, // MOV32ri64 >+ 14816354U, // MOV32ri_alt >+ 12719202U, // MOV32rm >+ 14816354U, // MOV32rr >+ 14816354U, // MOV32rr_REV >+ 14816354U, // MOV32rs >+ 19010658U, // MOV32sm >+ 14816354U, // MOV32sr >+ 627610U, // MOV64ao16 >+ 762778U, // MOV64ao32 >+ 897946U, // MOV64ao64 >+ 1033114U, // MOV64ao8 >+ 14816354U, // MOV64cr >+ 14816354U, // MOV64dr >+ 152674U, // MOV64mi32 >+ 152674U, // MOV64mr >+ 140386U, // MOV64ms >+ 103853U, // MOV64o16a >+ 108116U, // MOV64o32a >+ 112351U, // MOV64o64a >+ 116029U, // MOV64o8a >+ 14816354U, // MOV64rc >+ 14816354U, // MOV64rd >+ 14816154U, // MOV64ri >+ 14816354U, // MOV64ri32 >+ 16913506U, // MOV64rm >+ 14816354U, // MOV64rr >+ 14816354U, // MOV64rr_REV >+ 14816354U, // MOV64rs >+ 19010658U, // MOV64sm >+ 14816354U, // MOV64sr >+ 1033314U, // MOV8ao8 >+ 1033314U, // MOV8ao8_16 >+ 156770U, // MOV8mi >+ 156770U, // MOV8mr >+ 134374498U, // MOV8mr_NOREX >+ 116051U, // MOV8o8a >+ 116051U, // MOV8o8a_16 >+ 14816354U, // MOV8ri >+ 14816354U, // MOV8ri_alt >+ 21107810U, // MOV8rm >+ 155325538U, // MOV8rm_NOREX >+ 14816354U, // MOV8rr >+ 149034082U, // MOV8rr_NOREX >+ 14816354U, // MOV8rr_REV >+ 139586U, // MOVBE16mr >+ 19009858U, // MOVBE16rm >+ 147778U, // MOVBE32mr >+ 12718402U, // MOVBE32rm >+ 151874U, // MOVBE64mr >+ 16912706U, // MOVBE64rm >+ 0U, // MOVPC32r >+ 27451498U, // MOVSB >+ 29552914U, // MOVSL >+ 31707958U, // MOVSQ >+ 33752205U, // MOVSW >+ 21107902U, // MOVSX16rm8 >+ 14816446U, // MOVSX16rr8 >+ 19010750U, // MOVSX32rm16 >+ 21107902U, // MOVSX32rm8 >+ 14816446U, // MOVSX32rr16 >+ 14816446U, // MOVSX32rr8 >+ 14815513U, // MOVSX64_NOREXrr32 >+ 19010750U, // MOVSX64rm16 >+ 12718361U, // MOVSX64rm32 >+ 21107902U, // MOVSX64rm8 >+ 14816446U, // MOVSX64rr16 >+ 14815513U, // MOVSX64rr32 >+ 14816446U, // MOVSX64rr8 >+ 21107909U, // MOVZX16rm8 >+ 14816453U, // MOVZX16rr8 >+ 21107909U, // MOVZX32_NOREXrm8 >+ 14816453U, // MOVZX32_NOREXrr8 >+ 19010757U, // MOVZX32rm16 >+ 21107909U, // MOVZX32rm8 >+ 14816453U, // MOVZX32rr16 >+ 14816453U, // MOVZX32rr8 >+ 19010757U, // MOVZX64rm16_Q >+ 21107909U, // MOVZX64rm8_Q >+ 14816453U, // MOVZX64rr16_Q >+ 14816453U, // MOVZX64rr8_Q >+ 8833U, // MUL16m >+ 4737U, // MUL16r >+ 17025U, // MUL32m >+ 4737U, // MUL32r >+ 21121U, // MUL64m >+ 4737U, // MUL64r >+ 25217U, // MUL8m >+ 4737U, // MUL8r >+ 81925280U, // MULX32rm >+ 350360736U, // MULX32rr >+ 618796192U, // MULX64rm >+ 350360736U, // MULX64rr >+ 8680U, // NEG16m >+ 4584U, // NEG16r >+ 16872U, // NEG32m >+ 4584U, // NEG32r >+ 20968U, // NEG64m >+ 4584U, // NEG64r >+ 25064U, // NEG8m >+ 4584U, // NEG8r >+ 3095U, // NOOP >+ 8948U, // NOOP18_16m4 >+ 8948U, // NOOP18_16m5 >+ 8948U, // NOOP18_16m6 >+ 8948U, // NOOP18_16m7 >+ 4852U, // NOOP18_16r4 >+ 4852U, // NOOP18_16r5 >+ 4852U, // NOOP18_16r6 >+ 4852U, // NOOP18_16r7 >+ 17140U, // NOOP18_m4 >+ 17140U, // NOOP18_m5 >+ 17140U, // NOOP18_m6 >+ 17140U, // NOOP18_m7 >+ 4852U, // NOOP18_r4 >+ 4852U, // NOOP18_r5 >+ 4852U, // NOOP18_r6 >+ 4852U, // NOOP18_r7 >+ 35795700U, // NOOP19rr >+ 17140U, // NOOPL >+ 17140U, // NOOPL_19 >+ 17140U, // NOOPL_1a >+ 17140U, // NOOPL_1b >+ 17140U, // NOOPL_1c >+ 17140U, // NOOPL_1d >+ 17140U, // NOOPL_1e >+ 8948U, // NOOPW >+ 8948U, // NOOPW_19 >+ 8948U, // NOOPW_1a >+ 8948U, // NOOPW_1b >+ 8948U, // NOOPW_1c >+ 8948U, // NOOPW_1d >+ 8948U, // NOOPW_1e >+ 9259U, // NOT16m >+ 5163U, // NOT16r >+ 17451U, // NOT32m >+ 5163U, // NOT32r >+ 21547U, // NOT64m >+ 5163U, // NOT64r >+ 25643U, // NOT8m >+ 5163U, // NOT8r >+ 5541U, // OR16i16 >+ 140130U, // OR16mi >+ 140130U, // OR16mi8 >+ 140130U, // OR16mr >+ 2241378U, // OR16ri >+ 2241378U, // OR16ri8 >+ 4338530U, // OR16rm >+ 2241378U, // OR16rr >+ 2233186U, // OR16rr_REV >+ 5707U, // OR32i32 >+ 148322U, // OR32mi >+ 148322U, // OR32mi8 >+ 148322U, // OR32mr >+ 148322U, // OR32mrLocked >+ 2241378U, // OR32ri >+ 2241378U, // OR32ri8 >+ 6435682U, // OR32rm >+ 2241378U, // OR32rr >+ 2233186U, // OR32rr_REV >+ 5846U, // OR64i32 >+ 152418U, // OR64mi32 >+ 152418U, // OR64mi8 >+ 152418U, // OR64mr >+ 2241378U, // OR64ri32 >+ 2241378U, // OR64ri8 >+ 8532834U, // OR64rm >+ 2241378U, // OR64rr >+ 2233186U, // OR64rr_REV >+ 5429U, // OR8i8 >+ 156514U, // OR8mi >+ 156514U, // OR8mr >+ 2241378U, // OR8ri >+ 2241378U, // OR8ri8 >+ 10629986U, // OR8rm >+ 2241378U, // OR8rr >+ 2233186U, // OR8rr_REV >+ 529489U, // OUT16ir >+ 3402U, // OUT16rr >+ 660561U, // OUT32ir >+ 3456U, // OUT32rr >+ 922705U, // OUT8ir >+ 2982U, // OUT8rr >+ 71415U, // OUTSB >+ 75522U, // OUTSL >+ 83725U, // OUTSW >+ 81924811U, // PDEP32rm >+ 350360267U, // PDEP32rr >+ 618795723U, // PDEP64rm >+ 350360267U, // PDEP64rr >+ 81925206U, // PEXT32rm >+ 350360662U, // PEXT32rr >+ 618796118U, // PEXT64rm >+ 350360662U, // PEXT64rr >+ 4863U, // POP16r >+ 8959U, // POP16rmm >+ 4863U, // POP16rmr >+ 4863U, // POP32r >+ 17151U, // POP32rmm >+ 4863U, // POP32rmr >+ 4863U, // POP64r >+ 21247U, // POP64rmm >+ 4863U, // POP64rmr >+ 3372U, // POPA16 >+ 3000U, // POPA32 >+ 3203U, // POPDS16 >+ 3203U, // POPDS32 >+ 3218U, // POPES16 >+ 3218U, // POPES32 >+ 2925U, // POPF16 >+ 2776U, // POPF32 >+ 3110U, // POPF64 >+ 3233U, // POPFS16 >+ 3233U, // POPFS32 >+ 3233U, // POPFS64 >+ 3248U, // POPGS16 >+ 3248U, // POPGS32 >+ 3248U, // POPGS64 >+ 3315U, // POPSS16 >+ 3315U, // POPSS32 >+ 4623U, // PUSH16i8 >+ 4623U, // PUSH16r >+ 8719U, // PUSH16rmm >+ 4623U, // PUSH16rmr >+ 4623U, // PUSH32i8 >+ 4623U, // PUSH32r >+ 16911U, // PUSH32rmm >+ 4623U, // PUSH32rmr >+ 4623U, // PUSH64i16 >+ 4623U, // PUSH64i32 >+ 4623U, // PUSH64i8 >+ 4623U, // PUSH64r >+ 21007U, // PUSH64rmm >+ 4623U, // PUSH64rmr >+ 3365U, // PUSHA16 >+ 2993U, // PUSHA32 >+ 3187U, // PUSHCS16 >+ 3187U, // PUSHCS32 >+ 3195U, // PUSHDS16 >+ 3195U, // PUSHDS32 >+ 3210U, // PUSHES16 >+ 3210U, // PUSHES32 >+ 2919U, // PUSHF16 >+ 2769U, // PUSHF32 >+ 3103U, // PUSHF64 >+ 3225U, // PUSHFS16 >+ 3225U, // PUSHFS32 >+ 3225U, // PUSHFS64 >+ 3240U, // PUSHGS16 >+ 3240U, // PUSHGS32 >+ 3240U, // PUSHGS64 >+ 3307U, // PUSHSS16 >+ 3307U, // PUSHSS32 >+ 4623U, // PUSHi16 >+ 4623U, // PUSHi32 >+ 1057347U, // RCL16m1 >+ 1188419U, // RCL16mCL >+ 139843U, // RCL16mi >+ 1053251U, // RCL16r1 >+ 1184323U, // RCL16rCL >+ 2232899U, // RCL16ri >+ 1065539U, // RCL32m1 >+ 1196611U, // RCL32mCL >+ 148035U, // RCL32mi >+ 1053251U, // RCL32r1 >+ 1184323U, // RCL32rCL >+ 2232899U, // RCL32ri >+ 1069635U, // RCL64m1 >+ 1200707U, // RCL64mCL >+ 152131U, // RCL64mi >+ 1053251U, // RCL64r1 >+ 1184323U, // RCL64rCL >+ 2232899U, // RCL64ri >+ 1073731U, // RCL8m1 >+ 1204803U, // RCL8mCL >+ 156227U, // RCL8mi >+ 1053251U, // RCL8r1 >+ 1184323U, // RCL8rCL >+ 2232899U, // RCL8ri >+ 1057616U, // RCR16m1 >+ 1188688U, // RCR16mCL >+ 140112U, // RCR16mi >+ 1053520U, // RCR16r1 >+ 1184592U, // RCR16rCL >+ 2233168U, // RCR16ri >+ 1065808U, // RCR32m1 >+ 1196880U, // RCR32mCL >+ 148304U, // RCR32mi >+ 1053520U, // RCR32r1 >+ 1184592U, // RCR32rCL >+ 2233168U, // RCR32ri >+ 1069904U, // RCR64m1 >+ 1200976U, // RCR64mCL >+ 152400U, // RCR64mi >+ 1053520U, // RCR64r1 >+ 1184592U, // RCR64rCL >+ 2233168U, // RCR64ri >+ 1074000U, // RCR8m1 >+ 1205072U, // RCR8mCL >+ 156496U, // RCR8mi >+ 1053520U, // RCR8r1 >+ 1184592U, // RCR8rCL >+ 2233168U, // RCR8ri >+ 4504U, // RDFSBASE >+ 4504U, // RDFSBASE64 >+ 4524U, // RDGSBASE >+ 4524U, // RDGSBASE64 >+ 3157U, // RDMSR >+ 2746U, // RDPMC >+ 4329U, // RDRAND16r >+ 4329U, // RDRAND32r >+ 4329U, // RDRAND64r >+ 4288U, // RDSEED16r >+ 4288U, // RDSEED32r >+ 4288U, // RDSEED64r >+ 2759U, // RDTSC >+ 3084U, // RDTSCP >+ 2322U, // RELEASE_MOV16mr >+ 2322U, // RELEASE_MOV32mr >+ 2322U, // RELEASE_MOV64mr >+ 2322U, // RELEASE_MOV8mr >+ 2847U, // REPNE_PREFIX >+ 2690U, // REP_MOVSB_32 >+ 2690U, // REP_MOVSB_64 >+ 2802U, // REP_MOVSD_32 >+ 2802U, // REP_MOVSD_64 >+ 3132U, // REP_MOVSQ_64 >+ 3392U, // REP_MOVSW_32 >+ 3392U, // REP_MOVSW_64 >+ 3091U, // REP_PREFIX >+ 2680U, // REP_STOSB_32 >+ 2680U, // REP_STOSB_64 >+ 2792U, // REP_STOSD_32 >+ 2792U, // REP_STOSD_64 >+ 3122U, // REP_STOSQ_64 >+ 3382U, // REP_STOSW_32 >+ 3382U, // REP_STOSW_64 >+ 5139U, // RETIL >+ 5139U, // RETIQ >+ 5139U, // RETIW >+ 3328U, // RETL >+ 3328U, // RETQ >+ 3328U, // RETW >+ 2525U, // REX64_PREFIX >+ 1057386U, // ROL16m1 >+ 1188458U, // ROL16mCL >+ 139882U, // ROL16mi >+ 1053290U, // ROL16r1 >+ 1184362U, // ROL16rCL >+ 2232938U, // ROL16ri >+ 1065578U, // ROL32m1 >+ 1196650U, // ROL32mCL >+ 148074U, // ROL32mi >+ 1053290U, // ROL32r1 >+ 1184362U, // ROL32rCL >+ 2232938U, // ROL32ri >+ 1069674U, // ROL64m1 >+ 1200746U, // ROL64mCL >+ 152170U, // ROL64mi >+ 1053290U, // ROL64r1 >+ 1184362U, // ROL64rCL >+ 2232938U, // ROL64ri >+ 1073770U, // ROL8m1 >+ 1204842U, // ROL8mCL >+ 156266U, // ROL8mi >+ 1053290U, // ROL8r1 >+ 1184362U, // ROL8rCL >+ 2232938U, // ROL8ri >+ 1057633U, // ROR16m1 >+ 1188705U, // ROR16mCL >+ 140129U, // ROR16mi >+ 1053537U, // ROR16r1 >+ 1184609U, // ROR16rCL >+ 2233185U, // ROR16ri >+ 1065825U, // ROR32m1 >+ 1196897U, // ROR32mCL >+ 148321U, // ROR32mi >+ 1053537U, // ROR32r1 >+ 1184609U, // ROR32rCL >+ 2233185U, // ROR32ri >+ 1069921U, // ROR64m1 >+ 1200993U, // ROR64mCL >+ 152417U, // ROR64mi >+ 1053537U, // ROR64r1 >+ 1184609U, // ROR64rCL >+ 2233185U, // ROR64ri >+ 1074017U, // ROR8m1 >+ 1205089U, // ROR8mCL >+ 156513U, // ROR8mi >+ 1053537U, // ROR8r1 >+ 1184609U, // ROR8rCL >+ 2233185U, // ROR8ri >+ 885134520U, // RORX32mi >+ 350360760U, // RORX32ri >+ 889328824U, // RORX64mi >+ 350360760U, // RORX64ri >+ 3044U, // RSM >+ 2914U, // SAHF >+ 1057342U, // SAL16m1 >+ 1188414U, // SAL16mCL >+ 139838U, // SAL16mi >+ 1053246U, // SAL16r1 >+ 1184318U, // SAL16rCL >+ 2232894U, // SAL16ri >+ 1065534U, // SAL32m1 >+ 1196606U, // SAL32mCL >+ 148030U, // SAL32mi >+ 1053246U, // SAL32r1 >+ 1184318U, // SAL32rCL >+ 2232894U, // SAL32ri >+ 1069630U, // SAL64m1 >+ 1200702U, // SAL64mCL >+ 152126U, // SAL64mi >+ 1053246U, // SAL64r1 >+ 1184318U, // SAL64rCL >+ 2232894U, // SAL64ri >+ 1073726U, // SAL8m1 >+ 1204798U, // SAL8mCL >+ 156222U, // SAL8mi >+ 1053246U, // SAL8r1 >+ 1184318U, // SAL8rCL >+ 2232894U, // SAL8ri >+ 2733U, // SALC >+ 1057611U, // SAR16m1 >+ 1188683U, // SAR16mCL >+ 140107U, // SAR16mi >+ 1053515U, // SAR16r1 >+ 1184587U, // SAR16rCL >+ 2233163U, // SAR16ri >+ 1065803U, // SAR32m1 >+ 1196875U, // SAR32mCL >+ 148299U, // SAR32mi >+ 1053515U, // SAR32r1 >+ 1184587U, // SAR32rCL >+ 2233163U, // SAR32ri >+ 1069899U, // SAR64m1 >+ 1200971U, // SAR64mCL >+ 152395U, // SAR64mi >+ 1053515U, // SAR64r1 >+ 1184587U, // SAR64rCL >+ 2233163U, // SAR64ri >+ 1073995U, // SAR8m1 >+ 1205067U, // SAR8mCL >+ 156491U, // SAR8mi >+ 1053515U, // SAR8r1 >+ 1184587U, // SAR8rCL >+ 2233163U, // SAR8ri >+ 885134508U, // SARX32rm >+ 350360748U, // SARX32rr >+ 889328812U, // SARX64rm >+ 350360748U, // SARX64rr >+ 5468U, // SBB16i16 >+ 139341U, // SBB16mi >+ 139341U, // SBB16mi8 >+ 139341U, // SBB16mr >+ 2240589U, // SBB16ri >+ 2240589U, // SBB16ri8 >+ 4337741U, // SBB16rm >+ 2240589U, // SBB16rr >+ 2232397U, // SBB16rr_REV >+ 5602U, // SBB32i32 >+ 147533U, // SBB32mi >+ 147533U, // SBB32mi8 >+ 147533U, // SBB32mr >+ 2240589U, // SBB32ri >+ 2240589U, // SBB32ri8 >+ 6434893U, // SBB32rm >+ 2240589U, // SBB32rr >+ 2232397U, // SBB32rr_REV >+ 5750U, // SBB64i32 >+ 151629U, // SBB64mi32 >+ 151629U, // SBB64mi8 >+ 151629U, // SBB64mr >+ 2240589U, // SBB64ri32 >+ 2240589U, // SBB64ri8 >+ 8532045U, // SBB64rm >+ 2240589U, // SBB64rr >+ 2232397U, // SBB64rr_REV >+ 5344U, // SBB8i8 >+ 155725U, // SBB8mi >+ 155725U, // SBB8mr >+ 2240589U, // SBB8ri >+ 10629197U, // SBB8rm >+ 2240589U, // SBB8rr >+ 2232397U, // SBB8rr_REV >+ 58601U, // SCASB >+ 62996U, // SCASL >+ 120509U, // SCASQ >+ 67020U, // SCASW >+ 3262U, // SEG_ALLOCA_32 >+ 3262U, // SEG_ALLOCA_64 >+ 2879U, // SEH_EndPrologue >+ 2865U, // SEH_Epilogue >+ 6001U, // SEH_PushFrame >+ 6046U, // SEH_PushReg >+ 14817168U, // SEH_SaveReg >+ 14817082U, // SEH_SaveXMM >+ 14817153U, // SEH_SetFrame >+ 5984U, // SEH_StackAlloc >+ 24870U, // SETAEm >+ 4390U, // SETAEr >+ 24617U, // SETAm >+ 4137U, // SETAr >+ 24890U, // SETBEm >+ 4410U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 24689U, // SETBm >+ 4209U, // SETBr >+ 25024U, // SETEm >+ 4544U, // SETEr >+ 24910U, // SETGEm >+ 4430U, // SETGEr >+ 25090U, // SETGm >+ 4610U, // SETGr >+ 24934U, // SETLEm >+ 4454U, // SETLEr >+ 25210U, // SETLm >+ 4730U, // SETLr >+ 24962U, // SETNEm >+ 4482U, // SETNEr >+ 25256U, // SETNOm >+ 4776U, // SETNOr >+ 25317U, // SETNPm >+ 4837U, // SETNPr >+ 25541U, // SETNSm >+ 5061U, // SETNSr >+ 25271U, // SETOm >+ 4791U, // SETOr >+ 25348U, // SETPm >+ 4868U, // SETPr >+ 25566U, // SETSm >+ 5086U, // SETSr >+ 54261U, // SGDT16m >+ 54261U, // SGDT32m >+ 54261U, // SGDT64m >+ 1057352U, // SHL16m1 >+ 1188424U, // SHL16mCL >+ 139848U, // SHL16mi >+ 1053256U, // SHL16r1 >+ 1184328U, // SHL16rCL >+ 2232904U, // SHL16ri >+ 1065544U, // SHL32m1 >+ 1196616U, // SHL32mCL >+ 148040U, // SHL32mi >+ 1053256U, // SHL32r1 >+ 1184328U, // SHL32rCL >+ 2232904U, // SHL32ri >+ 1069640U, // SHL64m1 >+ 1200712U, // SHL64mCL >+ 152136U, // SHL64mi >+ 1053256U, // SHL64r1 >+ 1184328U, // SHL64rCL >+ 2232904U, // SHL64ri >+ 1073736U, // SHL8m1 >+ 1204808U, // SHL8mCL >+ 156232U, // SHL8mi >+ 1053256U, // SHL8r1 >+ 1184328U, // SHL8rCL >+ 2232904U, // SHL8ri >+ 201466074U, // SHLD16mrCL >+ 872554714U, // SHLD16mri8 >+ 203559130U, // SHLD16rrCL >+ 1143083226U, // SHLD16rri8 >+ 201474266U, // SHLD32mrCL >+ 872562906U, // SHLD32mri8 >+ 203559130U, // SHLD32rrCL >+ 1143083226U, // SHLD32rri8 >+ 201478362U, // SHLD64mrCL >+ 872567002U, // SHLD64mri8 >+ 203559130U, // SHLD64rrCL >+ 1143083226U, // SHLD64rri8 >+ 885134490U, // SHLX32rm >+ 350360730U, // SHLX32rr >+ 889328794U, // SHLX64rm >+ 350360730U, // SHLX64rr >+ 1057628U, // SHR16m1 >+ 1188700U, // SHR16mCL >+ 140124U, // SHR16mi >+ 1053532U, // SHR16r1 >+ 1184604U, // SHR16rCL >+ 2233180U, // SHR16ri >+ 1065820U, // SHR32m1 >+ 1196892U, // SHR32mCL >+ 148316U, // SHR32mi >+ 1053532U, // SHR32r1 >+ 1184604U, // SHR32rCL >+ 2233180U, // SHR32ri >+ 1069916U, // SHR64m1 >+ 1200988U, // SHR64mCL >+ 152412U, // SHR64mi >+ 1053532U, // SHR64r1 >+ 1184604U, // SHR64rCL >+ 2233180U, // SHR64ri >+ 1074012U, // SHR8m1 >+ 1205084U, // SHR8mCL >+ 156508U, // SHR8mi >+ 1053532U, // SHR8r1 >+ 1184604U, // SHR8rCL >+ 2233180U, // SHR8ri >+ 201466104U, // SHRD16mrCL >+ 872554744U, // SHRD16mri8 >+ 203559160U, // SHRD16rrCL >+ 1143083256U, // SHRD16rri8 >+ 201474296U, // SHRD32mrCL >+ 872562936U, // SHRD32mri8 >+ 203559160U, // SHRD32rrCL >+ 1143083256U, // SHRD32rri8 >+ 201478392U, // SHRD64mrCL >+ 872567032U, // SHRD64mri8 >+ 203559160U, // SHRD64rrCL >+ 1143083256U, // SHRD64rri8 >+ 885134514U, // SHRX32rm >+ 350360754U, // SHRX32rr >+ 889328818U, // SHRX64rm >+ 350360754U, // SHRX64rr >+ 54273U, // SIDT16m >+ 54273U, // SIDT32m >+ 54273U, // SIDT64m >+ 3445U, // SKINIT >+ 9229U, // SLDT16m >+ 5133U, // SLDT16r >+ 5133U, // SLDT32r >+ 9229U, // SLDT64m >+ 5133U, // SLDT64r >+ 9331U, // SMSW16m >+ 5235U, // SMSW16r >+ 5235U, // SMSW32r >+ 5235U, // SMSW64r >+ 2711U, // STAC >+ 2765U, // STC >+ 2818U, // STD >+ 2949U, // STGI >+ 2958U, // STI >+ 974940U, // STOSB >+ 717060U, // STOSL >+ 906024U, // STOSQ >+ 590975U, // STOSW >+ 5006U, // STR16r >+ 5006U, // STR32r >+ 5006U, // STR64r >+ 9102U, // STRm >+ 5477U, // SUB16i16 >+ 139383U, // SUB16mi >+ 139383U, // SUB16mi8 >+ 139383U, // SUB16mr >+ 2240631U, // SUB16ri >+ 2240631U, // SUB16ri8 >+ 4337783U, // SUB16rm >+ 2240631U, // SUB16rr >+ 2232439U, // SUB16rr_REV >+ 5612U, // SUB32i32 >+ 147575U, // SUB32mi >+ 147575U, // SUB32mi8 >+ 147575U, // SUB32mr >+ 2240631U, // SUB32ri >+ 2240631U, // SUB32ri8 >+ 6434935U, // SUB32rm >+ 2240631U, // SUB32rr >+ 2232439U, // SUB32rr_REV >+ 5760U, // SUB64i32 >+ 151671U, // SUB64mi32 >+ 151671U, // SUB64mi8 >+ 151671U, // SUB64mr >+ 2240631U, // SUB64ri32 >+ 2240631U, // SUB64ri8 >+ 8532087U, // SUB64rm >+ 2240631U, // SUB64rr >+ 2232439U, // SUB64rr_REV >+ 5375U, // SUB8i8 >+ 155767U, // SUB8mi >+ 155767U, // SUB8mr >+ 2240631U, // SUB8ri >+ 2240631U, // SUB8ri8 >+ 10629239U, // SUB8rm >+ 2240631U, // SUB8rr >+ 2232439U, // SUB8rr_REV >+ 3255U, // SWAPGS >+ 3021U, // SYSCALL >+ 3148U, // SYSENTER >+ 3339U, // SYSEXIT >+ 3339U, // SYSEXIT64 >+ 3332U, // SYSRET >+ 3332U, // SYSRET64 >+ 12718235U, // T1MSKC32rm >+ 14815387U, // T1MSKC32rr >+ 16912539U, // T1MSKC64rm >+ 14815387U, // T1MSKC64rr >+ 1340123U, // TAILJMPd >+ 1340123U, // TAILJMPd64 >+ 1327835U, // TAILJMPm >+ 1331931U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 1315547U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 5561U, // TEST16i16 >+ 140354U, // TEST16mi >+ 140354U, // TEST16mi_alt >+ 14816322U, // TEST16ri >+ 14816322U, // TEST16ri_alt >+ 140354U, // TEST16rm >+ 14816322U, // TEST16rr >+ 5729U, // TEST32i32 >+ 148546U, // TEST32mi >+ 148546U, // TEST32mi_alt >+ 14816322U, // TEST32ri >+ 14816322U, // TEST32ri_alt >+ 148546U, // TEST32rm >+ 14816322U, // TEST32rr >+ 5868U, // TEST64i32 >+ 152642U, // TEST64mi32 >+ 152642U, // TEST64mi32_alt >+ 14816322U, // TEST64ri32 >+ 14816322U, // TEST64ri32_alt >+ 152642U, // TEST64rm >+ 14816322U, // TEST64rr >+ 5449U, // TEST8i8 >+ 156738U, // TEST8mi >+ 156738U, // TEST8mi_alt >+ 14816322U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 14816322U, // TEST8ri_alt >+ 156738U, // TEST8rm >+ 14816322U, // TEST8rr >+ 2391U, // TLSCall_32 >+ 2481U, // TLSCall_64 >+ 2404U, // TLS_addr32 >+ 2494U, // TLS_addr64 >+ 2417U, // TLS_base_addr32 >+ 2507U, // TLS_base_addr64 >+ 2435U, // TRAP >+ 19010591U, // TZCNT16rm >+ 14816287U, // TZCNT16rr >+ 12719135U, // TZCNT32rm >+ 14816287U, // TZCNT32rr >+ 16913439U, // TZCNT64rm >+ 14816287U, // TZCNT64rr >+ 12718647U, // TZMSK32rm >+ 14815799U, // TZMSK32rr >+ 16912951U, // TZMSK64rm >+ 14815799U, // TZMSK64rr >+ 2645U, // UD2B >+ 3041007384U, // VAARG_64 >+ 350361416U, // VASTART_SAVE_XMM_REGS >+ 9075U, // VERRm >+ 4979U, // VERRr >+ 9319U, // VERWm >+ 5223U, // VERWr >+ 3014U, // VMCALL >+ 21309U, // VMCLEARm >+ 2752U, // VMFUNC >+ 2935U, // VMLAUNCH >+ 3413U, // VMLOAD32 >+ 3468U, // VMLOAD64 >+ 3006U, // VMMCALL >+ 20704U, // VMPTRLDm >+ 21576U, // VMPTRSTm >+ 147634U, // VMREAD32rm >+ 14815410U, // VMREAD32rr >+ 151730U, // VMREAD64rm >+ 14815410U, // VMREAD64rr >+ 2838U, // VMRESUME >+ 3435U, // VMRUN32 >+ 3490U, // VMRUN64 >+ 3424U, // VMSAVE32 >+ 3479U, // VMSAVE64 >+ 12718534U, // VMWRITE32rm >+ 14815686U, // VMWRITE32rr >+ 16912838U, // VMWRITE64rm >+ 14815686U, // VMWRITE64rr >+ 2902U, // VMXOFF >+ 21144U, // VMXON >+ 29266U, // W64ALLOCA >+ 2822U, // WBINVD >+ 3048U, // WIN_ALLOCA >+ 2962U, // WIN_FTOL_32 >+ 2962U, // WIN_FTOL_64 >+ 4514U, // WRFSBASE >+ 4514U, // WRFSBASE64 >+ 4534U, // WRGSBASE >+ 4534U, // WRGSBASE64 >+ 3163U, // WRMSR >+ 139450U, // XADD16rm >+ 14815418U, // XADD16rr >+ 147642U, // XADD32rm >+ 14815418U, // XADD32rr >+ 151738U, // XADD64rm >+ 14815418U, // XADD64rr >+ 155834U, // XADD8rm >+ 14815418U, // XADD8rr >+ 5513U, // XCHG16ar >+ 86512U, // XCHG16rm >+ 123376U, // XCHG16rr >+ 5676U, // XCHG32ar >+ 5676U, // XCHG32ar64 >+ 90608U, // XCHG32rm >+ 123376U, // XCHG32rr >+ 5800U, // XCHG64ar >+ 94704U, // XCHG64rm >+ 123376U, // XCHG64rr >+ 98800U, // XCHG8rm >+ 123376U, // XCHG8rr >+ 2716U, // XCRYPTCBC >+ 2660U, // XCRYPTCFB >+ 3169U, // XCRYPTCTR >+ 2650U, // XCRYPTECB >+ 2670U, // XCRYPTOFB >+ 3351U, // XGETBV >+ 2700U, // XLAT >+ 5540U, // XOR16i16 >+ 140142U, // XOR16mi >+ 140142U, // XOR16mi8 >+ 140142U, // XOR16mr >+ 2241390U, // XOR16ri >+ 2241390U, // XOR16ri8 >+ 4338542U, // XOR16rm >+ 2241390U, // XOR16rr >+ 2233198U, // XOR16rr_REV >+ 5706U, // XOR32i32 >+ 148334U, // XOR32mi >+ 148334U, // XOR32mi8 >+ 148334U, // XOR32mr >+ 2241390U, // XOR32ri >+ 2241390U, // XOR32ri8 >+ 6435694U, // XOR32rm >+ 2241390U, // XOR32rr >+ 2233198U, // XOR32rr_REV >+ 5845U, // XOR64i32 >+ 152430U, // XOR64mi32 >+ 152430U, // XOR64mi8 >+ 152430U, // XOR64mr >+ 2241390U, // XOR64ri32 >+ 2241390U, // XOR64ri8 >+ 8532846U, // XOR64rm >+ 2241390U, // XOR64rr >+ 2233198U, // XOR64rr_REV >+ 5428U, // XOR8i8 >+ 156526U, // XOR8mi >+ 156526U, // XOR8mr >+ 2241390U, // XOR8ri >+ 2241390U, // XOR8ri8 >+ 10629998U, // XOR8rm >+ 2241390U, // XOR8rr >+ 2233198U, // XOR8rr_REV >+ 54118U, // XRSTOR >+ 53258U, // XRSTOR64 >+ 53711U, // XSAVE >+ 53249U, // XSAVE64 >+ 54328U, // XSAVEOPT >+ 53268U, // XSAVEOPT64 >+ 3358U, // XSETBV >+ 2343U, // XSHA1 >+ 2538U, // XSHA256 >+ 2858U, // XSTORE >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0, >+ /* 9 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0, >+ /* 19 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0, >+ /* 31 */ 'l', 'e', 'a', 9, 0, >+ /* 36 */ 'j', 'a', 9, 0, >+ /* 40 */ 's', 'e', 't', 'a', 9, 0, >+ /* 46 */ 'c', 'm', 'o', 'v', 'a', 9, 0, >+ /* 53 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, >+ /* 65 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, >+ /* 76 */ 's', 'b', 'b', 9, 0, >+ /* 81 */ 'j', 'b', 9, 0, >+ /* 85 */ 'i', 'n', 's', 'b', 9, 0, >+ /* 91 */ 's', 't', 'o', 's', 'b', 9, 0, >+ /* 98 */ 'c', 'm', 'p', 's', 'b', 9, 0, >+ /* 105 */ 'm', 'o', 'v', 's', 'b', 9, 0, >+ /* 112 */ 's', 'e', 't', 'b', 9, 0, >+ /* 118 */ 's', 'u', 'b', 9, 0, >+ /* 123 */ 'c', 'm', 'o', 'v', 'b', 9, 0, >+ /* 130 */ 'a', 'd', 'c', 9, 0, >+ /* 135 */ 'd', 'e', 'c', 9, 0, >+ /* 140 */ 'b', 'l', 'c', 'i', 'c', 9, 0, >+ /* 147 */ 'b', 'l', 's', 'i', 'c', 9, 0, >+ /* 154 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, >+ /* 162 */ 'i', 'n', 'c', 9, 0, >+ /* 167 */ 'b', 't', 'c', 9, 0, >+ /* 172 */ 'a', 'a', 'd', 9, 0, >+ /* 177 */ 'v', 'm', 'r', 'e', 'a', 'd', 9, 0, >+ /* 185 */ 'x', 'a', 'd', 'd', 9, 0, >+ /* 191 */ 'r', 'd', 's', 'e', 'e', 'd', 9, 0, >+ /* 199 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, >+ /* 208 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, >+ /* 217 */ 's', 'h', 'l', 'd', 9, 0, >+ /* 223 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, >+ /* 232 */ 'r', 'd', 'r', 'a', 'n', 'd', 9, 0, >+ /* 240 */ 'b', 'o', 'u', 'n', 'd', 9, 0, >+ /* 247 */ 's', 'h', 'r', 'd', 9, 0, >+ /* 253 */ 'i', 'n', 's', 'd', 9, 0, >+ /* 259 */ 's', 't', 'o', 's', 'd', 9, 0, >+ /* 266 */ 'c', 'm', 'p', 's', 'd', 9, 0, >+ /* 273 */ 'm', 'o', 'v', 's', 'd', 9, 0, >+ /* 280 */ 'm', 'o', 'v', 's', 'x', 'd', 9, 0, >+ /* 288 */ 'j', 'a', 'e', 9, 0, >+ /* 293 */ 's', 'e', 't', 'a', 'e', 9, 0, >+ /* 300 */ 'c', 'm', 'o', 'v', 'a', 'e', 9, 0, >+ /* 308 */ 'j', 'b', 'e', 9, 0, >+ /* 313 */ 's', 'e', 't', 'b', 'e', 9, 0, >+ /* 320 */ 'c', 'm', 'o', 'v', 'b', 'e', 9, 0, >+ /* 328 */ 'j', 'g', 'e', 9, 0, >+ /* 333 */ 's', 'e', 't', 'g', 'e', 9, 0, >+ /* 340 */ 'c', 'm', 'o', 'v', 'g', 'e', 9, 0, >+ /* 348 */ 'j', 'e', 9, 0, >+ /* 352 */ 'j', 'l', 'e', 9, 0, >+ /* 357 */ 's', 'e', 't', 'l', 'e', 9, 0, >+ /* 364 */ 'c', 'm', 'o', 'v', 'l', 'e', 9, 0, >+ /* 372 */ 'j', 'n', 'e', 9, 0, >+ /* 377 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, >+ /* 385 */ 's', 'e', 't', 'n', 'e', 9, 0, >+ /* 392 */ 'c', 'm', 'o', 'v', 'n', 'e', 9, 0, >+ /* 400 */ 'l', 'o', 'o', 'p', 'e', 9, 0, >+ /* 407 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 417 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 427 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 437 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 9, 0, >+ /* 447 */ 's', 'e', 't', 'e', 9, 0, >+ /* 453 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 9, 0, >+ /* 462 */ 'x', 's', 'a', 'v', 'e', 9, 0, >+ /* 469 */ 'c', 'm', 'o', 'v', 'e', 9, 0, >+ /* 476 */ 'b', 's', 'f', 9, 0, >+ /* 481 */ 'r', 'e', 't', 'f', 9, 0, >+ /* 487 */ 'n', 'e', 'g', 9, 0, >+ /* 492 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 9, 0, >+ /* 501 */ 'j', 'g', 9, 0, >+ /* 505 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, >+ /* 513 */ 's', 'e', 't', 'g', 9, 0, >+ /* 519 */ 'c', 'm', 'o', 'v', 'g', 9, 0, >+ /* 526 */ 'p', 'u', 's', 'h', 9, 0, >+ /* 532 */ 'b', 'l', 'c', 'i', 9, 0, >+ /* 538 */ 'b', 'z', 'h', 'i', 9, 0, >+ /* 544 */ 'b', 'l', 's', 'i', 9, 0, >+ /* 550 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, >+ /* 558 */ 'b', 'l', 's', 'm', 's', 'k', 9, 0, >+ /* 566 */ 't', 'z', 'm', 's', 'k', 9, 0, >+ /* 573 */ 's', 'a', 'l', 9, 0, >+ /* 578 */ 'r', 'c', 'l', 9, 0, >+ /* 583 */ 's', 'h', 'l', 9, 0, >+ /* 588 */ 'j', 'l', 9, 0, >+ /* 592 */ 'l', 'c', 'a', 'l', 'l', 9, 0, >+ /* 599 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, >+ /* 608 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, >+ /* 617 */ 'r', 'o', 'l', 9, 0, >+ /* 622 */ 'a', 'r', 'p', 'l', 9, 0, >+ /* 628 */ 'l', 's', 'l', 9, 0, >+ /* 633 */ 's', 'e', 't', 'l', 9, 0, >+ /* 639 */ 'i', 'm', 'u', 'l', 9, 0, >+ /* 645 */ 'c', 'm', 'o', 'v', 'l', 9, 0, >+ /* 652 */ 'a', 'a', 'm', 9, 0, >+ /* 657 */ 'a', 'n', 'd', 'n', 9, 0, >+ /* 663 */ 'v', 'm', 'x', 'o', 'n', 9, 0, >+ /* 670 */ 'j', 'o', 9, 0, >+ /* 674 */ 'j', 'n', 'o', 9, 0, >+ /* 679 */ 's', 'e', 't', 'n', 'o', 9, 0, >+ /* 686 */ 'c', 'm', 'o', 'v', 'n', 'o', 9, 0, >+ /* 694 */ 's', 'e', 't', 'o', 9, 0, >+ /* 700 */ 'c', 'm', 'o', 'v', 'o', 9, 0, >+ /* 707 */ 'b', 's', 'w', 'a', 'p', 9, 0, >+ /* 714 */ 'p', 'd', 'e', 'p', 9, 0, >+ /* 720 */ 'j', 'p', 9, 0, >+ /* 724 */ 'c', 'm', 'p', 9, 0, >+ /* 729 */ 'l', 'j', 'm', 'p', 9, 0, >+ /* 735 */ 'j', 'n', 'p', 9, 0, >+ /* 740 */ 's', 'e', 't', 'n', 'p', 9, 0, >+ /* 747 */ 'c', 'm', 'o', 'v', 'n', 'p', 9, 0, >+ /* 755 */ 'n', 'o', 'p', 9, 0, >+ /* 760 */ 'l', 'o', 'o', 'p', 9, 0, >+ /* 766 */ 'p', 'o', 'p', 9, 0, >+ /* 771 */ 's', 'e', 't', 'p', 9, 0, >+ /* 777 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, >+ /* 793 */ 'c', 'm', 'o', 'v', 'p', 9, 0, >+ /* 800 */ 'r', 'e', 't', 'f', 'q', 9, 0, >+ /* 807 */ 's', 't', 'o', 's', 'q', 9, 0, >+ /* 814 */ 'c', 'm', 'p', 's', 'q', 9, 0, >+ /* 821 */ 'm', 'o', 'v', 's', 'q', 9, 0, >+ /* 828 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, >+ /* 837 */ 'l', 'a', 'r', 9, 0, >+ /* 842 */ 's', 'a', 'r', 9, 0, >+ /* 847 */ 'r', 'c', 'r', 9, 0, >+ /* 852 */ 'e', 'n', 't', 'e', 'r', 9, 0, >+ /* 859 */ 's', 'h', 'r', 9, 0, >+ /* 864 */ 'r', 'o', 'r', 9, 0, >+ /* 869 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 877 */ 'x', 'o', 'r', 9, 0, >+ /* 882 */ 'v', 'e', 'r', 'r', 9, 0, >+ /* 888 */ 'b', 's', 'r', 9, 0, >+ /* 893 */ 'b', 'l', 's', 'r', 9, 0, >+ /* 899 */ 'b', 't', 'r', 9, 0, >+ /* 904 */ 'l', 't', 'r', 9, 0, >+ /* 909 */ 's', 't', 'r', 9, 0, >+ /* 914 */ 'b', 'e', 'x', 't', 'r', 9, 0, >+ /* 921 */ 'm', 'o', 'v', 'a', 'b', 's', 9, 0, >+ /* 929 */ 'b', 'l', 'c', 's', 9, 0, >+ /* 935 */ 'l', 'd', 's', 9, 0, >+ /* 940 */ 'l', 'e', 's', 9, 0, >+ /* 945 */ 'l', 'f', 's', 9, 0, >+ /* 950 */ 'l', 'g', 's', 9, 0, >+ /* 955 */ 'j', 's', 9, 0, >+ /* 959 */ 'j', 'n', 's', 9, 0, >+ /* 964 */ 's', 'e', 't', 'n', 's', 9, 0, >+ /* 971 */ 'c', 'm', 'o', 'v', 'n', 's', 9, 0, >+ /* 979 */ 'l', 's', 's', 9, 0, >+ /* 984 */ 'b', 't', 's', 9, 0, >+ /* 989 */ 's', 'e', 't', 's', 9, 0, >+ /* 995 */ 'c', 'm', 'o', 'v', 's', 9, 0, >+ /* 1002 */ 'b', 't', 9, 0, >+ /* 1006 */ 'l', 'g', 'd', 't', 9, 0, >+ /* 1012 */ 's', 'g', 'd', 't', 9, 0, >+ /* 1018 */ 'l', 'i', 'd', 't', 9, 0, >+ /* 1024 */ 's', 'i', 'd', 't', 9, 0, >+ /* 1030 */ 'l', 'l', 'd', 't', 9, 0, >+ /* 1036 */ 's', 'l', 'd', 't', 9, 0, >+ /* 1042 */ 'r', 'e', 't', 9, 0, >+ /* 1047 */ 'l', 'z', 'c', 'n', 't', 9, 0, >+ /* 1054 */ 't', 'z', 'c', 'n', 't', 9, 0, >+ /* 1061 */ 'i', 'n', 't', 9, 0, >+ /* 1066 */ 'n', 'o', 't', 9, 0, >+ /* 1071 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, >+ /* 1079 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, >+ /* 1089 */ 't', 'e', 's', 't', 9, 0, >+ /* 1095 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, >+ /* 1104 */ 'o', 'u', 't', 9, 0, >+ /* 1109 */ 'p', 'e', 'x', 't', 9, 0, >+ /* 1115 */ 'i', 'd', 'i', 'v', 9, 0, >+ /* 1121 */ 'm', 'o', 'v', 9, 0, >+ /* 1126 */ 'v', 'e', 'r', 'w', 9, 0, >+ /* 1132 */ 'l', 'm', 's', 'w', 9, 0, >+ /* 1138 */ 's', 'm', 's', 'w', 9, 0, >+ /* 1144 */ 'i', 'n', 's', 'w', 9, 0, >+ /* 1150 */ 's', 't', 'o', 's', 'w', 9, 0, >+ /* 1157 */ 'c', 'm', 'p', 's', 'w', 9, 0, >+ /* 1164 */ 'm', 'o', 'v', 's', 'w', 9, 0, >+ /* 1171 */ 'a', 'd', 'c', 'x', 9, 0, >+ /* 1177 */ 's', 'h', 'l', 'x', 9, 0, >+ /* 1183 */ 'm', 'u', 'l', 'x', 9, 0, >+ /* 1189 */ 'a', 'd', 'o', 'x', 9, 0, >+ /* 1195 */ 's', 'a', 'r', 'x', 9, 0, >+ /* 1201 */ 's', 'h', 'r', 'x', 9, 0, >+ /* 1207 */ 'r', 'o', 'r', 'x', 9, 0, >+ /* 1213 */ 'm', 'o', 'v', 's', 'x', 9, 0, >+ /* 1220 */ 'm', 'o', 'v', 'z', 'x', 9, 0, >+ /* 1227 */ 'j', 'e', 'c', 'x', 'z', 9, 0, >+ /* 1234 */ 'j', 'c', 'x', 'z', 9, 0, >+ /* 1240 */ 'j', 'r', 'c', 'x', 'z', 9, 0, >+ /* 1247 */ 's', 'b', 'b', 9, 'a', 'l', ',', 32, 0, >+ /* 1256 */ 's', 'c', 'a', 's', 'b', 9, 'a', 'l', ',', 32, 0, >+ /* 1267 */ 'l', 'o', 'd', 's', 'b', 9, 'a', 'l', ',', 32, 0, >+ /* 1278 */ 's', 'u', 'b', 9, 'a', 'l', ',', 32, 0, >+ /* 1287 */ 'a', 'd', 'c', 9, 'a', 'l', ',', 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'i', 'n', '3', '2', 32, 'f', 'p', 't', 'o', 'u', 'i', 0, >+ /* 2976 */ 'l', 'o', 'c', 'k', 0, >+ /* 2981 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'l', 0, >+ /* 2992 */ 'p', 'u', 's', 'h', 'a', 'l', 0, >+ /* 2999 */ 'p', 'o', 'p', 'a', 'l', 0, >+ /* 3005 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 3013 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 3020 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, >+ /* 3028 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, >+ /* 3036 */ 'f', 's', 'e', 't', 'p', 'm', 0, >+ /* 3043 */ 'r', 's', 'm', 0, >+ /* 3047 */ '#', 32, 'd', 'y', 'n', 'a', 'm', 'i', 'c', 32, 's', 't', 'a', 'c', 'k', 32, 'a', 'l', 'l', 'o', 'c', 'a', 't', 'i', 'o', 'n', 0, >+ /* 3074 */ 'c', 'q', 'o', 0, >+ /* 3078 */ 'i', 'n', 't', 'o', 0, >+ /* 3083 */ 'r', 'd', 't', 's', 'c', 'p', 0, >+ /* 3090 */ 'r', 'e', 'p', 0, >+ /* 3094 */ 'n', 'o', 'p', 0, >+ /* 3098 */ 'c', 'd', 'q', 0, >+ /* 3102 */ 'p', 'u', 's', 'h', 'f', 'q', 0, >+ /* 3109 */ 'p', 'o', 'p', 'f', 'q', 0, >+ /* 3115 */ 'r', 'e', 't', 'f', 'q', 0, >+ /* 3121 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'q', 0, >+ /* 3131 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'q', 0, >+ /* 3141 */ 'i', 'r', 'e', 't', 'q', 0, >+ /* 3147 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, >+ /* 3156 */ 'r', 'd', 'm', 's', 'r', 0, >+ /* 3162 */ 'w', 'r', 'm', 's', 'r', 0, >+ /* 3168 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, >+ /* 3178 */ 'a', 'a', 's', 0, >+ /* 3182 */ 'd', 'a', 's', 0, >+ /* 3186 */ 'p', 'u', 's', 'h', 9, 'c', 's', 0, >+ /* 3194 */ 'p', 'u', 's', 'h', 9, 'd', 's', 0, >+ /* 3202 */ 'p', 'o', 'p', 9, 'd', 's', 0, >+ /* 3209 */ 'p', 'u', 's', 'h', 9, 'e', 's', 0, >+ /* 3217 */ 'p', 'o', 'p', 9, 'e', 's', 0, >+ /* 3224 */ 'p', 'u', 's', 'h', 9, 'f', 's', 0, >+ /* 3232 */ 'p', 'o', 'p', 9, 'f', 's', 0, >+ /* 3239 */ 'p', 'u', 's', 'h', 9, 'g', 's', 0, >+ /* 3247 */ 'p', 'o', 'p', 9, 'g', 's', 0, >+ /* 3254 */ 's', 'w', 'a', 'p', 'g', 's', 0, >+ /* 3261 */ '#', 32, 'v', 'a', 'r', 'i', 'a', 'b', 'l', 'e', 32, 's', 'i', 'z', 'e', 'd', 32, 'a', 'l', 'l', 'o', 'c', 'a', 32, 'f', 'o', 'r', 32, 's', 'e', 'g', 'm', 'e', 'n', 't', 'e', 'd', 32, 's', 't', 'a', 'c', 'k', 's', 0, >+ /* 3306 */ 'p', 'u', 's', 'h', 9, 's', 's', 0, >+ /* 3314 */ 'p', 'o', 'p', 9, 's', 's', 0, >+ /* 3321 */ 'c', 'l', 't', 's', 0, >+ /* 3326 */ 'i', 'r', 'e', 't', 0, >+ /* 3331 */ 's', 'y', 's', 'r', 'e', 't', 0, >+ /* 3338 */ 's', 'y', 's', 'e', 'x', 'i', 't', 0, >+ /* 3346 */ 'h', 'l', 't', 0, >+ /* 3350 */ 'x', 'g', 'e', 't', 'b', 'v', 0, >+ /* 3357 */ 'x', 's', 'e', 't', 'b', 'v', 0, >+ /* 3364 */ 'p', 'u', 's', 'h', 'a', 'w', 0, >+ /* 3371 */ 'p', 'o', 'p', 'a', 'w', 0, >+ /* 3377 */ 'c', 'b', 'w', 0, >+ /* 3381 */ 'r', 'e', 'p', 32, 's', 't', 'o', 's', 'w', 0, >+ /* 3391 */ 'r', 'e', 'p', 32, 'm', 'o', 'v', 's', 'w', 0, >+ /* 3401 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'a', 'x', 0, >+ /* 3412 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'e', 'a', 'x', 0, >+ /* 3423 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'e', 'a', 'x', 0, >+ /* 3434 */ 'v', 'm', 'r', 'u', 'n', 9, 'e', 'a', 'x', 0, >+ /* 3444 */ 's', 'k', 'i', 'n', 'i', 't', 9, 'e', 'a', 'x', 0, >+ /* 3455 */ 'o', 'u', 't', 9, 'd', 'x', ',', 32, 'e', 'a', 'x', 0, >+ /* 3467 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, 'r', 'a', 'x', 0, >+ /* 3478 */ 'v', 'm', 's', 'a', 'v', 'e', 9, 'r', 'a', 'x', 0, >+ /* 3489 */ 'v', 'm', 'r', 'u', 'n', 9, 'r', 'a', 'x', 0, >+ /* 3499 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'e', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, >+ /* 3516 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, 'r', 'a', 'x', ',', 32, 'e', 'c', 'x', 0, >+ /* 3533 */ 'i', 'n', 9, 'a', 'l', ',', 32, 'd', 'x', 0, >+ /* 3543 */ 'i', 'n', 9, 'a', 'x', ',', 32, 'd', 'x', 0, >+ /* 3553 */ 'i', 'n', 9, 'e', 'a', 'x', ',', 32, 'd', 'x', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 4095)-1); >+#endif >+ >+ // Fragment 0 encoded into 5 bits for 31 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 31); >+ switch ((Bits >> 12) & 31) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, AAA, AAS, ACQUIRE_MOV... >+ return; >+ break; >+ case 1: >+ // AAD8i8, AAM8i8, ADC16i16, ADC16rr_REV, ADC32i32, ADC32rr_REV, ADC64i32... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... >+ printi16mem(MI, 0, O); >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... >+ printOperand(MI, 1, O); >+ break; >+ case 4: >+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... >+ printi32mem(MI, 0, O); >+ break; >+ case 5: >+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... >+ printi64mem(MI, 0, O); >+ break; >+ case 6: >+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH... >+ printi8mem(MI, 0, O); >+ break; >+ case 7: >+ // CALL64pcrel32, CALLpcrel16, CALLpcrel32, EH_SjLj_Setup, JAE_1, JAE_2, ... >+ printPCRelImm(MI, 0, O); >+ break; >+ case 8: >+ // CMPSB >+ printSrcIdx8(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx8(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // CMPSL >+ printSrcIdx32(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx32(MI, 0, O); >+ return; >+ break; >+ case 10: >+ // CMPSQ >+ printSrcIdx64(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx64(MI, 0, O); >+ return; >+ break; >+ case 11: >+ // CMPSW >+ printSrcIdx16(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx16(MI, 0, O); >+ return; >+ break; >+ case 12: >+ // CMPXCHG16B, LCMPXCHG16B >+ printi128mem(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... >+ printopaquemem(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // INSB, MOVSB, SCASB, STOSB >+ printDstIdx8(MI, 0, O); >+ break; >+ case 15: >+ // INSL, MOVSL, SCASL, STOSL >+ printDstIdx32(MI, 0, O); >+ break; >+ case 16: >+ // INSW, MOVSW, SCASW, STOSW >+ printDstIdx16(MI, 0, O); >+ break; >+ case 17: >+ // LODSB, OUTSB >+ printSrcIdx8(MI, 0, O); >+ return; >+ break; >+ case 18: >+ // LODSL, OUTSL >+ printSrcIdx32(MI, 0, O); >+ return; >+ break; >+ case 19: >+ // LODSQ >+ printSrcIdx64(MI, 0, O); >+ return; >+ break; >+ case 20: >+ // LODSW, OUTSW >+ printSrcIdx16(MI, 0, O); >+ return; >+ break; >+ case 21: >+ // LXADD16, XCHG16rm >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 22: >+ // LXADD32, XCHG32rm >+ printi32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 23: >+ // LXADD64, XCHG64rm >+ printi64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 24: >+ // LXADD8, XCHG8rm >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 25: >+ // MOV16ao16, MOV16ao16_16, MOV16o16a, MOV16o16a_16, MOV64ao16, MOV64o16a >+ printMemOffs16(MI, 0, O); >+ break; >+ case 26: >+ // MOV32ao32, MOV32ao32_16, MOV32o32a, MOV32o32a_16, MOV64ao32, MOV64o32a >+ printMemOffs32(MI, 0, O); >+ break; >+ case 27: >+ // MOV64ao64, MOV64o64a >+ printMemOffs64(MI, 0, O); >+ break; >+ case 28: >+ // MOV64ao8, MOV64o8a, MOV8ao8, MOV8ao8_16, MOV8o8a, MOV8o8a_16 >+ printMemOffs8(MI, 0, O); >+ break; >+ case 29: >+ // MOVSQ, SCASQ, STOSQ >+ printDstIdx64(MI, 0, O); >+ break; >+ case 30: >+ // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 4 bits for 11 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 17) & 15); >+ switch ((Bits >> 17) & 15) { >+ default: // unreachable. >+ case 0: >+ // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... >+ return; >+ break; >+ case 1: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC16... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i >+ SStream_concat0(O, ":"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // INSB, INSL, INSW >+ SStream_concat0(O, ", dx"); >+ op_addReg(MI, X86_REG_DX); >+ return; >+ break; >+ case 4: >+ // MOV16ao16, MOV16ao16_16, MOV64ao16, OUT16ir, STOSW >+ SStream_concat0(O, ", ax"); >+ op_addReg(MI, X86_REG_AX); >+ return; >+ break; >+ case 5: >+ // MOV32ao32, MOV32ao32_16, MOV64ao32, OUT32ir, STOSL >+ SStream_concat0(O, ", eax"); >+ op_addReg(MI, X86_REG_EAX); >+ return; >+ break; >+ case 6: >+ // MOV64ao64, STOSQ >+ SStream_concat0(O, ", rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 7: >+ // MOV64ao8, MOV8ao8, MOV8ao8_16, OUT8ir, STOSB >+ SStream_concat0(O, ", al"); >+ op_addReg(MI, X86_REG_AL); >+ return; >+ break; >+ case 8: >+ // RCL16m1, RCL16r1, RCL32m1, RCL32r1, RCL64m1, RCL64r1, RCL8m1, RCL8r1, ... >+ SStream_concat0(O, ", 1"); >+ op_addImm(MI, 1); >+ return; >+ break; >+ case 9: >+ // RCL16mCL, RCL16rCL, RCL32mCL, RCL32rCL, RCL64mCL, RCL64rCL, RCL8mCL, R... >+ SStream_concat0(O, ", cl"); >+ op_addReg(MI, X86_REG_CL); >+ return; >+ break; >+ case 10: >+ // TAILJMPd, TAILJMPd64, TAILJMPm, TAILJMPm64, TAILJMPr64 >+ return; >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 5 bits for 18 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 21) & 31); >+ switch ((Bits >> 21) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... >+ printOperand(MI, 5, O); >+ break; >+ case 1: >+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... >+ printOperand(MI, 2, O); >+ break; >+ case 2: >+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... >+ printi16mem(MI, 2, O); >+ return; >+ break; >+ case 3: >+ // ADC32rm, ADCX32rm, ADD32rm, AND32rm, CMOVA32rm, CMOVAE32rm, CMOVB32rm,... >+ printi32mem(MI, 2, O); >+ return; >+ break; >+ case 4: >+ // ADC64rm, ADCX64rm, ADD64rm, AND64rm, CMOVA64rm, CMOVAE64rm, CMOVB64rm,... >+ printi64mem(MI, 2, O); >+ return; >+ break; >+ case 5: >+ // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm >+ printi8mem(MI, 2, O); >+ return; >+ break; >+ case 6: >+ // ADOX32rm, BEXTR32rm, BEXTRI32mi, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLC... >+ printi32mem(MI, 1, O); >+ break; >+ case 7: >+ // ADOX32rr, ADOX64rr, ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, ARPL16rr, ... >+ printOperand(MI, 1, O); >+ break; >+ case 8: >+ // ADOX64rm, BEXTR64rm, BEXTRI64mi, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLC... >+ printi64mem(MI, 1, O); >+ break; >+ case 9: >+ // BSF16rm, BSR16rm, CMP16rm, IMUL16rmi, IMUL16rmi8, LAR16rm, LAR32rm, LA... >+ printi16mem(MI, 1, O); >+ break; >+ case 10: >+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ... >+ printi8mem(MI, 1, O); >+ break; >+ case 11: >+ // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 >+ printi128mem(MI, 1, O); >+ return; >+ break; >+ case 12: >+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... >+ printopaquemem(MI, 1, O); >+ return; >+ break; >+ case 13: >+ // MOVSB >+ printSrcIdx8(MI, 1, O); >+ return; >+ break; >+ case 14: >+ // MOVSL >+ printSrcIdx32(MI, 1, O); >+ return; >+ break; >+ case 15: >+ // MOVSQ >+ printSrcIdx64(MI, 1, O); >+ return; >+ break; >+ case 16: >+ // MOVSW >+ printSrcIdx16(MI, 1, O); >+ return; >+ break; >+ case 17: >+ // NOOP19rr >+ printOperand(MI, 0, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 2 bits for 4 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 26) & 3); >+ switch ((Bits >> 26) & 3) { >+ default: // unreachable. >+ case 0: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, A... >+ return; >+ break; >+ case 1: >+ // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rm, BEXTR32rr, BEXTR64r... >+ SStream_concat0(O, ", "); >+ break; >+ case 2: >+ // MOV8mr_NOREX, MOV8rm_NOREX, MOV8rr_NOREX >+ return; >+ break; >+ case 3: >+ // SHLD16mrCL, SHLD16rrCL, SHLD32mrCL, SHLD32rrCL, SHLD64mrCL, SHLD64rrCL... >+ SStream_concat0(O, ", cl"); >+ op_addReg(MI, X86_REG_CL); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 4 encoded into 3 bits for 5 unique commands. >+ //printf("Frag-4: %"PRIu64"\n", (Bits >> 28) & 7); >+ switch ((Bits >> 28) & 7) { >+ default: // unreachable. >+ case 0: >+ // ANDN32rm, MULX32rm, PDEP32rm, PEXT32rm >+ printi32mem(MI, 2, O); >+ return; >+ break; >+ case 1: >+ // ANDN32rr, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32ri, BEXTRI64ri, BZHI... >+ printOperand(MI, 2, O); >+ return; >+ break; >+ case 2: >+ // ANDN64rm, MULX64rm, PDEP64rm, PEXT64rm >+ printi64mem(MI, 2, O); >+ return; >+ break; >+ case 3: >+ // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... >+ printOperand(MI, 6, O); >+ break; >+ case 4: >+ // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 >+ printOperand(MI, 3, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 5 encoded into 1 bits for 2 unique commands. >+ //printf("Frag-5: %"PRIu64"\n", (Bits >> 31) & 1); >+ if ((Bits >> 31) & 1) { >+ // VAARG_64 >+ SStream_concat0(O, ", "); >+ printOperand(MI, 7, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 8, O); >+ return; >+ } else { >+ // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... >+ return; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 234 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 't', '(', '0', ')', 0, >+ /* 6 */ 's', 't', '(', '1', ')', 0, >+ /* 12 */ 's', 't', '(', '2', ')', 0, >+ /* 18 */ 's', 't', '(', '3', ')', 0, >+ /* 24 */ 's', 't', '(', '4', ')', 0, >+ /* 30 */ 's', 't', '(', '5', ')', 0, >+ /* 36 */ 's', 't', '(', '6', ')', 0, >+ /* 42 */ 's', 't', '(', '7', ')', 0, >+ /* 48 */ 'x', 'm', 'm', '1', '0', 0, >+ /* 54 */ 'y', 'm', 'm', '1', '0', 0, >+ /* 60 */ 'z', 'm', 'm', '1', '0', 0, >+ /* 66 */ 'c', 'r', '1', '0', 0, >+ /* 71 */ 'x', 'm', 'm', '2', '0', 0, >+ /* 77 */ 'y', 'm', 'm', '2', '0', 0, >+ /* 83 */ 'z', 'm', 'm', '2', '0', 0, >+ /* 89 */ 'x', 'm', 'm', '3', '0', 0, >+ /* 95 */ 'y', 'm', 'm', '3', '0', 0, >+ /* 101 */ 'z', 'm', 'm', '3', '0', 0, >+ /* 107 */ 'k', '0', 0, >+ /* 110 */ 'x', 'm', 'm', '0', 0, >+ /* 115 */ 'y', 'm', 'm', '0', 0, >+ /* 120 */ 'z', 'm', 'm', '0', 0, >+ /* 125 */ 'f', 'p', '0', 0, >+ /* 129 */ 'c', 'r', '0', 0, >+ /* 133 */ 'd', 'r', '0', 0, >+ /* 137 */ 'x', 'm', 'm', '1', '1', 0, >+ /* 143 */ 'y', 'm', 'm', '1', '1', 0, >+ /* 149 */ 'z', 'm', 'm', '1', '1', 0, >+ /* 155 */ 'c', 'r', '1', '1', 0, >+ /* 160 */ 'x', 'm', 'm', '2', '1', 0, >+ /* 166 */ 'y', 'm', 'm', '2', '1', 0, >+ /* 172 */ 'z', 'm', 'm', '2', '1', 0, >+ /* 178 */ 'x', 'm', 'm', '3', '1', 0, >+ /* 184 */ 'y', 'm', 'm', '3', '1', 0, >+ /* 190 */ 'z', 'm', 'm', '3', '1', 0, >+ /* 196 */ 'k', '1', 0, >+ /* 199 */ 'x', 'm', 'm', '1', 0, >+ /* 204 */ 'y', 'm', 'm', '1', 0, >+ /* 209 */ 'z', 'm', 'm', '1', 0, >+ /* 214 */ 'f', 'p', '1', 0, >+ /* 218 */ 'c', 'r', '1', 0, >+ /* 222 */ 'd', 'r', '1', 0, >+ /* 226 */ 'x', 'm', 'm', '1', '2', 0, >+ /* 232 */ 'y', 'm', 'm', '1', '2', 0, >+ /* 238 */ 'z', 'm', 'm', '1', '2', 0, >+ /* 244 */ 'c', 'r', '1', '2', 0, >+ /* 249 */ 'x', 'm', 'm', '2', '2', 0, >+ /* 255 */ 'y', 'm', 'm', '2', '2', 0, >+ /* 261 */ 'z', 'm', 'm', '2', '2', 0, >+ /* 267 */ 'k', '2', 0, >+ /* 270 */ 'x', 'm', 'm', '2', 0, >+ /* 275 */ 'y', 'm', 'm', '2', 0, >+ /* 280 */ 'z', 'm', 'm', '2', 0, >+ /* 285 */ 'f', 'p', '2', 0, >+ /* 289 */ 'c', 'r', '2', 0, >+ /* 293 */ 'd', 'r', '2', 0, >+ /* 297 */ 'x', 'm', 'm', '1', '3', 0, >+ /* 303 */ 'y', 'm', 'm', '1', '3', 0, >+ /* 309 */ 'z', 'm', 'm', '1', '3', 0, >+ /* 315 */ 'c', 'r', '1', '3', 0, >+ /* 320 */ 'x', 'm', 'm', '2', '3', 0, >+ /* 326 */ 'y', 'm', 'm', '2', '3', 0, >+ /* 332 */ 'z', 'm', 'm', '2', '3', 0, >+ /* 338 */ 'k', '3', 0, >+ /* 341 */ 'x', 'm', 'm', '3', 0, >+ /* 346 */ 'y', 'm', 'm', '3', 0, >+ /* 351 */ 'z', 'm', 'm', '3', 0, >+ /* 356 */ 'f', 'p', '3', 0, >+ /* 360 */ 'c', 'r', '3', 0, >+ /* 364 */ 'd', 'r', '3', 0, >+ /* 368 */ 'x', 'm', 'm', '1', '4', 0, >+ /* 374 */ 'y', 'm', 'm', '1', '4', 0, >+ /* 380 */ 'z', 'm', 'm', '1', '4', 0, >+ /* 386 */ 'c', 'r', '1', '4', 0, >+ /* 391 */ 'x', 'm', 'm', '2', '4', 0, >+ /* 397 */ 'y', 'm', 'm', '2', '4', 0, >+ /* 403 */ 'z', 'm', 'm', '2', '4', 0, >+ /* 409 */ 'k', '4', 0, >+ /* 412 */ 'x', 'm', 'm', '4', 0, >+ /* 417 */ 'y', 'm', 'm', '4', 0, >+ /* 422 */ 'z', 'm', 'm', '4', 0, >+ /* 427 */ 'f', 'p', '4', 0, >+ /* 431 */ 'c', 'r', '4', 0, >+ /* 435 */ 'd', 'r', '4', 0, >+ /* 439 */ 'x', 'm', 'm', '1', '5', 0, >+ /* 445 */ 'y', 'm', 'm', '1', '5', 0, >+ /* 451 */ 'z', 'm', 'm', '1', '5', 0, >+ /* 457 */ 'c', 'r', '1', '5', 0, >+ /* 462 */ 'x', 'm', 'm', '2', '5', 0, >+ /* 468 */ 'y', 'm', 'm', '2', '5', 0, >+ /* 474 */ 'z', 'm', 'm', '2', '5', 0, >+ /* 480 */ 'k', '5', 0, >+ /* 483 */ 'x', 'm', 'm', '5', 0, >+ /* 488 */ 'y', 'm', 'm', '5', 0, >+ /* 493 */ 'z', 'm', 'm', '5', 0, >+ /* 498 */ 'f', 'p', '5', 0, >+ /* 502 */ 'c', 'r', '5', 0, >+ /* 506 */ 'd', 'r', '5', 0, >+ /* 510 */ 'x', 'm', 'm', '1', '6', 0, >+ /* 516 */ 'y', 'm', 'm', '1', '6', 0, >+ /* 522 */ 'z', 'm', 'm', '1', '6', 0, >+ /* 528 */ 'x', 'm', 'm', '2', '6', 0, >+ /* 534 */ 'y', 'm', 'm', '2', '6', 0, >+ /* 540 */ 'z', 'm', 'm', '2', '6', 0, >+ /* 546 */ 'k', '6', 0, >+ /* 549 */ 'x', 'm', 'm', '6', 0, >+ /* 554 */ 'y', 'm', 'm', '6', 0, >+ /* 559 */ 'z', 'm', 'm', '6', 0, >+ /* 564 */ 'f', 'p', '6', 0, >+ /* 568 */ 'c', 'r', '6', 0, >+ /* 572 */ 'd', 'r', '6', 0, >+ /* 576 */ 'x', 'm', 'm', '1', '7', 0, >+ /* 582 */ 'y', 'm', 'm', '1', '7', 0, >+ /* 588 */ 'z', 'm', 'm', '1', '7', 0, >+ /* 594 */ 'x', 'm', 'm', '2', '7', 0, >+ /* 600 */ 'y', 'm', 'm', '2', '7', 0, >+ /* 606 */ 'z', 'm', 'm', '2', '7', 0, >+ /* 612 */ 'k', '7', 0, >+ /* 615 */ 'x', 'm', 'm', '7', 0, >+ /* 620 */ 'y', 'm', 'm', '7', 0, >+ /* 625 */ 'z', 'm', 'm', '7', 0, >+ /* 630 */ 'f', 'p', '7', 0, >+ /* 634 */ 'c', 'r', '7', 0, >+ /* 638 */ 'd', 'r', '7', 0, >+ /* 642 */ 'x', 'm', 'm', '1', '8', 0, >+ /* 648 */ 'y', 'm', 'm', '1', '8', 0, >+ /* 654 */ 'z', 'm', 'm', '1', '8', 0, >+ /* 660 */ 'x', 'm', 'm', '2', '8', 0, >+ /* 666 */ 'y', 'm', 'm', '2', '8', 0, >+ /* 672 */ 'z', 'm', 'm', '2', '8', 0, >+ /* 678 */ 'x', 'm', 'm', '8', 0, >+ /* 683 */ 'y', 'm', 'm', '8', 0, >+ /* 688 */ 'z', 'm', 'm', '8', 0, >+ /* 693 */ 'c', 'r', '8', 0, >+ /* 697 */ 'x', 'm', 'm', '1', '9', 0, >+ /* 703 */ 'y', 'm', 'm', '1', '9', 0, >+ /* 709 */ 'z', 'm', 'm', '1', '9', 0, >+ /* 715 */ 'x', 'm', 'm', '2', '9', 0, >+ /* 721 */ 'y', 'm', 'm', '2', '9', 0, >+ /* 727 */ 'z', 'm', 'm', '2', '9', 0, >+ /* 733 */ 'x', 'm', 'm', '9', 0, >+ /* 738 */ 'y', 'm', 'm', '9', 0, >+ /* 743 */ 'z', 'm', 'm', '9', 0, >+ /* 748 */ 'c', 'r', '9', 0, >+ /* 752 */ 'r', '1', '0', 'b', 0, >+ /* 757 */ 'r', '1', '1', 'b', 0, >+ /* 762 */ 'r', '1', '2', 'b', 0, >+ /* 767 */ 'r', '1', '3', 'b', 0, >+ /* 772 */ 'r', '1', '4', 'b', 0, >+ /* 777 */ 'r', '1', '5', 'b', 0, >+ /* 782 */ 'r', '8', 'b', 0, >+ /* 786 */ 'r', '9', 'b', 0, >+ /* 790 */ 'r', '1', '0', 'd', 0, >+ /* 795 */ 'r', '1', '1', 'd', 0, >+ /* 800 */ 'r', '1', '2', 'd', 0, >+ /* 805 */ 'r', '1', '3', 'd', 0, >+ /* 810 */ 'r', '1', '4', 'd', 0, >+ /* 815 */ 'r', '1', '5', 'd', 0, >+ /* 820 */ 'r', '8', 'd', 0, >+ /* 824 */ 'r', '9', 'd', 0, >+ /* 828 */ 'a', 'h', 0, >+ /* 831 */ 'b', 'h', 0, >+ /* 834 */ 'c', 'h', 0, >+ /* 837 */ 'd', 'h', 0, >+ /* 840 */ 'e', 'd', 'i', 0, >+ /* 844 */ 'r', 'd', 'i', 0, >+ /* 848 */ 'e', 's', 'i', 0, >+ /* 852 */ 'r', 's', 'i', 0, >+ /* 856 */ 'a', 'l', 0, >+ /* 859 */ 'b', 'l', 0, >+ /* 862 */ 'c', 'l', 0, >+ /* 865 */ 'd', 'l', 0, >+ /* 868 */ 'd', 'i', 'l', 0, >+ /* 872 */ 's', 'i', 'l', 0, >+ /* 876 */ 'b', 'p', 'l', 0, >+ /* 880 */ 's', 'p', 'l', 0, >+ /* 884 */ 'e', 'b', 'p', 0, >+ /* 888 */ 'r', 'b', 'p', 0, >+ /* 892 */ 'e', 'i', 'p', 0, >+ /* 896 */ 'r', 'i', 'p', 0, >+ /* 900 */ 'e', 's', 'p', 0, >+ /* 904 */ 'r', 's', 'p', 0, >+ /* 908 */ 'c', 's', 0, >+ /* 911 */ 'd', 's', 0, >+ /* 914 */ 'e', 's', 0, >+ /* 917 */ 'f', 's', 0, >+ /* 920 */ 'f', 'l', 'a', 'g', 's', 0, >+ /* 926 */ 's', 's', 0, >+ /* 929 */ 'r', '1', '0', 'w', 0, >+ /* 934 */ 'r', '1', '1', 'w', 0, >+ /* 939 */ 'r', '1', '2', 'w', 0, >+ /* 944 */ 'r', '1', '3', 'w', 0, >+ /* 949 */ 'r', '1', '4', 'w', 0, >+ /* 954 */ 'r', '1', '5', 'w', 0, >+ /* 959 */ 'r', '8', 'w', 0, >+ /* 963 */ 'r', '9', 'w', 0, >+ /* 967 */ 'f', 'p', 's', 'w', 0, >+ /* 972 */ 'e', 'a', 'x', 0, >+ /* 976 */ 'r', 'a', 'x', 0, >+ /* 980 */ 'e', 'b', 'x', 0, >+ /* 984 */ 'r', 'b', 'x', 0, >+ /* 988 */ 'e', 'c', 'x', 0, >+ /* 992 */ 'r', 'c', 'x', 0, >+ /* 996 */ 'e', 'd', 'x', 0, >+ /* 1000 */ 'r', 'd', 'x', 0, >+ /* 1004 */ 'e', 'i', 'z', 0, >+ /* 1008 */ 'r', 'i', 'z', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 828, 856, 973, 831, 859, 885, 876, 981, 834, 862, 908, 989, 837, 841, >+ 868, 865, 911, 997, 972, 884, 980, 988, 840, 996, 920, 892, 1004, 914, >+ 848, 900, 967, 917, 923, 893, 976, 888, 984, 992, 844, 1000, 896, 1008, >+ 852, 904, 849, 872, 901, 880, 926, 129, 218, 289, 360, 431, 502, 568, >+ 634, 693, 748, 66, 155, 244, 315, 386, 457, 133, 222, 293, 364, 435, >+ 506, 572, 638, 125, 214, 285, 356, 427, 498, 564, 630, 107, 196, 267, >+ 338, 409, 480, 546, 612, 111, 200, 271, 342, 413, 484, 550, 616, 694, >+ 749, 67, 156, 245, 316, 387, 458, 0, 6, 12, 18, 24, 30, 36, >+ 42, 110, 199, 270, 341, 412, 483, 549, 615, 678, 733, 48, 137, 226, >+ 297, 368, 439, 510, 576, 642, 697, 71, 160, 249, 320, 391, 462, 528, >+ 594, 660, 715, 89, 178, 115, 204, 275, 346, 417, 488, 554, 620, 683, >+ 738, 54, 143, 232, 303, 374, 445, 516, 582, 648, 703, 77, 166, 255, >+ 326, 397, 468, 534, 600, 666, 721, 95, 184, 120, 209, 280, 351, 422, >+ 493, 559, 625, 688, 743, 60, 149, 238, 309, 380, 451, 522, 588, 654, >+ 709, 83, 172, 261, 332, 403, 474, 540, 606, 672, 727, 101, 190, 782, >+ 786, 752, 757, 762, 767, 772, 777, 820, 824, 790, 795, 800, 805, 810, >+ 815, 959, 963, 929, 934, 939, 944, 949, 954, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+#ifndef CAPSTONE_DIET >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case X86_AAD8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAD8i8 10) >+ AsmString = "aad"; >+ break; >+ } >+ return NULL; >+ case X86_AAM8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAM8i8 10) >+ AsmString = "aam"; >+ break; >+ } >+ return NULL; >+ case X86_XSTORE: >+ if (MCInst_getNumOperands(MI) == 0) { >+ // (XSTORE) >+ AsmString = "xstorerng"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter_reduce.inc b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter_reduce.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..809a60010bfabdb2e7daad1ece5c137bc783c63f >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86GenAsmWriter_reduce.inc >@@ -0,0 +1,3151 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|*Assembly Writer Source Fragment *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+/// printInstruction - This method is automatically generated by tablegen >+/// from the instruction set description. >+static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) >+{ >+ static const uint32_t OpInfo[] = { >+ 0U, // PHI >+ 0U, // INLINEASM >+ 0U, // CFI_INSTRUCTION >+ 0U, // EH_LABEL >+ 0U, // GC_LABEL >+ 0U, // KILL >+ 0U, // EXTRACT_SUBREG >+ 0U, // INSERT_SUBREG >+ 0U, // IMPLICIT_DEF >+ 0U, // SUBREG_TO_REG >+ 0U, // COPY_TO_REGCLASS >+ 4533U, // DBG_VALUE >+ 0U, // REG_SEQUENCE >+ 0U, // COPY >+ 4526U, // BUNDLE >+ 4589U, // LIFETIME_START >+ 4513U, // LIFETIME_END >+ 0U, // STACKMAP >+ 0U, // PATCHPOINT >+ 0U, // LOAD_STACK_GUARD >+ 4604U, // AAA >+ 8459U, // AAD8i8 >+ 9418U, // AAM8i8 >+ 5175U, // AAS >+ 4217U, // ACQUIRE_MOV16rm >+ 4217U, // ACQUIRE_MOV32rm >+ 4217U, // ACQUIRE_MOV64rm >+ 4217U, // ACQUIRE_MOV8rm >+ 534694U, // ADC16i16 >+ 1067174U, // ADC16mi >+ 1067174U, // ADC16mi8 >+ 1067174U, // ADC16mr >+ 1599654U, // ADC16ri >+ 1599654U, // ADC16ri8 >+ 1607846U, // ADC16rm >+ 1599654U, // ADC16rr >+ 2123942U, // ADC16rr_REV >+ 2630119U, // ADC32i32 >+ 3162599U, // ADC32mi >+ 3162599U, // ADC32mi8 >+ 3162599U, // ADC32mr >+ 1597927U, // ADC32ri >+ 1597927U, // ADC32ri8 >+ 1614311U, // ADC32rm >+ 1597927U, // ADC32rr >+ 2122215U, // ADC32rr_REV >+ 3679572U, // ADC64i32 >+ 4212052U, // ADC64mi32 >+ 4212052U, // ADC64mi8 >+ 4212052U, // ADC64mr >+ 1598804U, // ADC64ri32 >+ 1598804U, // ADC64ri8 >+ 1623380U, // ADC64rm >+ 1598804U, // ADC64rr >+ 2123092U, // ADC64rr_REV >+ 4726830U, // ADC8i8 >+ 5259310U, // ADC8mi >+ 5259310U, // ADC8mr >+ 1597486U, // ADC8ri >+ 57390U, // ADC8rm >+ 1597486U, // ADC8rr >+ 2121774U, // ADC8rr_REV >+ 2139289U, // ADCX32rm >+ 2122905U, // ADCX32rr >+ 2148322U, // ADCX64rm >+ 2123746U, // ADCX64rr >+ 534719U, // ADD16i16 >+ 1067199U, // ADD16mi >+ 1067199U, // ADD16mi8 >+ 1067199U, // ADD16mr >+ 1599679U, // ADD16ri >+ 1599679U, // ADD16ri8 >+ 0U, // ADD16ri8_DB >+ 0U, // ADD16ri_DB >+ 1607871U, // ADD16rm >+ 1599679U, // ADD16rr >+ 0U, // ADD16rr_DB >+ 2123967U, // ADD16rr_REV >+ 2630153U, // ADD32i32 >+ 3162633U, // ADD32mi >+ 3162633U, // ADD32mi8 >+ 3162633U, // ADD32mr >+ 1597961U, // ADD32ri >+ 1597961U, // ADD32ri8 >+ 0U, // ADD32ri8_DB >+ 0U, // ADD32ri_DB >+ 1614345U, // ADD32rm >+ 1597961U, // ADD32rr >+ 0U, // ADD32rr_DB >+ 2122249U, // ADD32rr_REV >+ 3679606U, // ADD64i32 >+ 4212086U, // ADD64mi32 >+ 4212086U, // ADD64mi8 >+ 4212086U, // ADD64mr >+ 1598838U, // ADD64ri32 >+ 0U, // ADD64ri32_DB >+ 1598838U, // ADD64ri8 >+ 0U, // ADD64ri8_DB >+ 1623414U, // ADD64rm >+ 1598838U, // ADD64rr >+ 0U, // ADD64rr_DB >+ 2123126U, // ADD64rr_REV >+ 4726849U, // ADD8i8 >+ 5259329U, // ADD8mi >+ 5259329U, // ADD8mr >+ 1597505U, // ADD8ri >+ 1597505U, // ADD8ri8 >+ 57409U, // ADD8rm >+ 1597505U, // ADD8rr >+ 2121793U, // ADD8rr_REV >+ 4543U, // ADJCALLSTACKDOWN32 >+ 4543U, // ADJCALLSTACKDOWN64 >+ 4561U, // ADJCALLSTACKUP32 >+ 4561U, // ADJCALLSTACKUP64 >+ 66734U, // ADOX32rm >+ 22619310U, // ADOX32rr >+ 83959U, // ADOX64rm >+ 22620151U, // ADOX64rr >+ 534744U, // AND16i16 >+ 1067224U, // AND16mi >+ 1067224U, // AND16mi8 >+ 1067224U, // AND16mr >+ 1599704U, // AND16ri >+ 1599704U, // AND16ri8 >+ 1607896U, // AND16rm >+ 1599704U, // AND16rr >+ 2123992U, // AND16rr_REV >+ 2630178U, // AND32i32 >+ 3162658U, // AND32mi >+ 3162658U, // AND32mi8 >+ 3162658U, // AND32mr >+ 1597986U, // AND32ri >+ 1597986U, // AND32ri8 >+ 1614370U, // AND32rm >+ 1597986U, // AND32rr >+ 2122274U, // AND32rr_REV >+ 3679631U, // AND64i32 >+ 4212111U, // AND64mi32 >+ 4212111U, // AND64mi8 >+ 4212111U, // AND64mr >+ 1598863U, // AND64ri32 >+ 1598863U, // AND64ri8 >+ 1623439U, // AND64rm >+ 1598863U, // AND64rr >+ 2123151U, // AND64rr_REV >+ 4726855U, // AND8i8 >+ 5259335U, // AND8mi >+ 5259335U, // AND8mr >+ 1597511U, // AND8ri >+ 1597511U, // AND8ri8 >+ 57415U, // AND8rm >+ 1597511U, // AND8rr >+ 2121799U, // AND8rr_REV >+ 35169057U, // ANDN32rm >+ 35152673U, // ANDN32rr >+ 35178119U, // ANDN64rm >+ 35153543U, // ANDN64rr >+ 1065839U, // ARPL16mr >+ 22618991U, // ARPL16rr >+ 6382522U, // BEXTR32rm >+ 35152826U, // BEXTR32rr >+ 6907665U, // BEXTR64rm >+ 35153681U, // BEXTR64rr >+ 6383665U, // BEXTRI32mi >+ 35153969U, // BEXTRI32ri >+ 6907953U, // BEXTRI64mi >+ 35153969U, // BEXTRI64ri >+ 66284U, // BLCFILL32rm >+ 22618860U, // BLCFILL32rr >+ 82668U, // BLCFILL64rm >+ 22618860U, // BLCFILL64rr >+ 65952U, // BLCI32rm >+ 22618528U, // BLCI32rr >+ 82336U, // BLCI64rm >+ 22618528U, // BLCI64rr >+ 65781U, // BLCIC32rm >+ 22618357U, // BLCIC32rr >+ 82165U, // BLCIC64rm >+ 22618357U, // BLCIC64rr >+ 65958U, // BLCMSK32rm >+ 22618534U, // BLCMSK32rr >+ 82342U, // BLCMSK64rm >+ 22618534U, // BLCMSK64rr >+ 67640U, // BLCS32rm >+ 22620216U, // BLCS32rr >+ 84024U, // BLCS64rm >+ 22620216U, // BLCS64rr >+ 66293U, // BLSFILL32rm >+ 22618869U, // BLSFILL32rr >+ 82677U, // BLSFILL64rm >+ 22618869U, // BLSFILL64rr >+ 66246U, // BLSI32rm >+ 22618822U, // BLSI32rr >+ 83515U, // BLSI64rm >+ 22619707U, // BLSI64rr >+ 65788U, // BLSIC32rm >+ 22618364U, // BLSIC32rr >+ 82172U, // BLSIC64rm >+ 22618364U, // BLSIC64rr >+ 66257U, // BLSMSK32rm >+ 22618833U, // BLSMSK32rr >+ 83522U, // BLSMSK64rm >+ 22619714U, // BLSMSK64rr >+ 66471U, // BLSR32rm >+ 22619047U, // BLSR32rr >+ 83710U, // BLSR64rm >+ 22619902U, // BLSR64rr >+ 65835U, // BOUNDS16rm >+ 82219U, // BOUNDS32rm >+ 100634U, // BSF16rm >+ 22620442U, // BSF16rr >+ 66202U, // BSF32rm >+ 22618778U, // BSF32rr >+ 83471U, // BSF64rm >+ 22619663U, // BSF64rr >+ 100830U, // BSR16rm >+ 22620638U, // BSR16rr >+ 66465U, // BSR32rm >+ 22619041U, // BSR32rr >+ 83704U, // BSR64rm >+ 22619896U, // BSR64rr >+ 9022U, // BSWAP32r >+ 9887U, // BSWAP64r >+ 1067600U, // BT16mi8 >+ 1067600U, // BT16mr >+ 22620752U, // BT16ri8 >+ 22620752U, // BT16rr >+ 3163164U, // BT32mi8 >+ 3163164U, // BT32mr >+ 22619164U, // BT32ri8 >+ 22619164U, // BT32rr >+ 4212576U, // BT64mi8 >+ 4212576U, // BT64mr >+ 22620000U, // BT64ri8 >+ 22620000U, // BT64rr >+ 1067192U, // BTC16mi8 >+ 1067192U, // BTC16mr >+ 22620344U, // BTC16ri8 >+ 22620344U, // BTC16rr >+ 3162617U, // BTC32mi8 >+ 3162617U, // BTC32mr >+ 22618617U, // BTC32ri8 >+ 22618617U, // BTC32rr >+ 4212070U, // BTC64mi8 >+ 4212070U, // BTC64mr >+ 22619494U, // BTC64ri8 >+ 22619494U, // BTC64rr >+ 1067492U, // BTR16mi8 >+ 1067492U, // BTR16mr >+ 22620644U, // BTR16ri8 >+ 22620644U, // BTR16rr >+ 3163054U, // BTR32mi8 >+ 3163054U, // BTR32mr >+ 22619054U, // BTR32ri8 >+ 22619054U, // BTR32rr >+ 4212485U, // BTR64mi8 >+ 4212485U, // BTR64mr >+ 22619909U, // BTR64ri8 >+ 22619909U, // BTR64rr >+ 1067579U, // BTS16mi8 >+ 1067579U, // BTS16mr >+ 22620731U, // BTS16ri8 >+ 22620731U, // BTS16rr >+ 3163143U, // BTS32mi8 >+ 3163143U, // BTS32mr >+ 22619143U, // BTS32ri8 >+ 22619143U, // BTS32rr >+ 4212562U, // BTS64mi8 >+ 4212562U, // BTS64mr >+ 22619986U, // BTS64ri8 >+ 22619986U, // BTS64rr >+ 6382271U, // BZHI32rm >+ 35152575U, // BZHI32rr >+ 6907444U, // BZHI64rm >+ 35153460U, // BZHI64rr >+ 110790U, // CALL16m >+ 12486U, // CALL16r >+ 118948U, // CALL32m >+ 12452U, // CALL32r >+ 127157U, // CALL64m >+ 132701U, // CALL64pcrel32 >+ 12469U, // CALL64r >+ 133458U, // CALLpcrel16 >+ 131839U, // CALLpcrel32 >+ 5552U, // CBW >+ 4746U, // CDQ >+ 5139U, // CDQE >+ 4673U, // CLAC >+ 4705U, // CLC >+ 4742U, // CLD >+ 4852U, // CLGI >+ 4862U, // CLI >+ 5483U, // CLTS >+ 4709U, // CMC >+ 2132090U, // CMOVA16rm >+ 2123898U, // CMOVA16rr >+ 2138555U, // CMOVA32rm >+ 2122171U, // CMOVA32rr >+ 2147624U, // CMOVA64rm >+ 2123048U, // CMOVA64rr >+ 2132197U, // CMOVAE16rm >+ 2124005U, // CMOVAE16rr >+ 2138671U, // CMOVAE32rm >+ 2122287U, // CMOVAE32rr >+ 2147740U, // CMOVAE64rm >+ 2123164U, // CMOVAE64rr >+ 2132118U, // CMOVB16rm >+ 2123926U, // CMOVB16rr >+ 2138583U, // CMOVB32rm >+ 2122199U, // CMOVB32rr >+ 2147652U, // CMOVB64rm >+ 2123076U, // CMOVB64rr >+ 2132206U, // CMOVBE16rm >+ 2124014U, // CMOVBE16rr >+ 2138680U, // CMOVBE32rm >+ 2122296U, // CMOVBE32rr >+ 2147749U, // CMOVBE64rm >+ 2123173U, // CMOVBE64rr >+ 2132242U, // CMOVE16rm >+ 2124050U, // CMOVE16rr >+ 2138770U, // CMOVE32rm >+ 2122386U, // CMOVE32rr >+ 2147847U, // CMOVE64rm >+ 2123271U, // CMOVE64rr >+ 2132272U, // CMOVG16rm >+ 2124080U, // CMOVG16rr >+ 2138800U, // CMOVG32rm >+ 2122416U, // CMOVG32rr >+ 2147877U, // CMOVG64rm >+ 2123301U, // CMOVG64rr >+ 2132215U, // CMOVGE16rm >+ 2124023U, // CMOVGE16rr >+ 2138689U, // CMOVGE32rm >+ 2122305U, // CMOVGE32rr >+ 2147758U, // CMOVGE64rm >+ 2123182U, // CMOVGE64rr >+ 2132332U, // CMOVL16rm >+ 2124140U, // CMOVL16rr >+ 2138905U, // CMOVL32rm >+ 2122521U, // CMOVL32rr >+ 2147967U, // CMOVL64rm >+ 2123391U, // CMOVL64rr >+ 2132224U, // CMOVLE16rm >+ 2124032U, // CMOVLE16rr >+ 2138698U, // CMOVLE32rm >+ 2122314U, // CMOVLE32rr >+ 2147767U, // CMOVLE64rm >+ 2123191U, // CMOVLE64rr >+ 2132233U, // CMOVNE16rm >+ 2124041U, // CMOVNE16rr >+ 2138707U, // CMOVNE32rm >+ 2122323U, // CMOVNE32rr >+ 2147776U, // CMOVNE64rm >+ 2123200U, // CMOVNE64rr >+ 2132345U, // CMOVNO16rm >+ 2124153U, // CMOVNO16rr >+ 2138925U, // CMOVNO32rm >+ 2122541U, // CMOVNO32rr >+ 2147982U, // CMOVNO64rm >+ 2123406U, // CMOVNO64rr >+ 2132375U, // CMOVNP16rm >+ 2124183U, // CMOVNP16rr >+ 2138970U, // CMOVNP32rm >+ 2122586U, // CMOVNP32rr >+ 2148020U, // CMOVNP64rm >+ 2123444U, // CMOVNP64rr >+ 2132517U, // CMOVNS16rm >+ 2124325U, // CMOVNS16rr >+ 2139121U, // CMOVNS32rm >+ 2122737U, // CMOVNS32rr >+ 2148156U, // CMOVNS64rm >+ 2123580U, // CMOVNS64rr >+ 2132354U, // CMOVO16rm >+ 2124162U, // CMOVO16rr >+ 2138934U, // CMOVO32rm >+ 2122550U, // CMOVO32rr >+ 2147991U, // CMOVO64rm >+ 2123415U, // CMOVO64rr >+ 2132396U, // CMOVP16rm >+ 2124204U, // CMOVP16rr >+ 2138997U, // CMOVP32rm >+ 2122613U, // CMOVP32rr >+ 2148035U, // CMOVP64rm >+ 2123459U, // CMOVP64rr >+ 2132552U, // CMOVS16rm >+ 2124360U, // CMOVS16rr >+ 2139156U, // CMOVS32rm >+ 2122772U, // CMOVS32rr >+ 2148184U, // CMOVS64rm >+ 2123608U, // CMOVS64rr >+ 4021U, // CMOV_FR32 >+ 4180U, // CMOV_FR64 >+ 3900U, // CMOV_GR16 >+ 3880U, // CMOV_GR32 >+ 4199U, // CMOV_GR8 >+ 4001U, // CMOV_RFP32 >+ 4160U, // CMOV_RFP64 >+ 3920U, // CMOV_RFP80 >+ 3960U, // CMOV_V16F32 >+ 4040U, // CMOV_V2F64 >+ 4100U, // CMOV_V2I64 >+ 3940U, // CMOV_V4F32 >+ 4060U, // CMOV_V4F64 >+ 4120U, // CMOV_V4I64 >+ 3981U, // CMOV_V8F32 >+ 4080U, // CMOV_V8F64 >+ 4140U, // CMOV_V8I64 >+ 534922U, // CMP16i16 >+ 1067402U, // CMP16mi >+ 1067402U, // CMP16mi8 >+ 1067402U, // CMP16mr >+ 22620554U, // CMP16ri >+ 22620554U, // CMP16ri8 >+ 100746U, // CMP16rm >+ 22620554U, // CMP16rr >+ 22620554U, // CMP16rr_REV >+ 2630477U, // CMP32i32 >+ 3162957U, // CMP32mi >+ 3162957U, // CMP32mi8 >+ 3162957U, // CMP32mr >+ 22618957U, // CMP32ri >+ 22618957U, // CMP32ri8 >+ 66381U, // CMP32rm >+ 22618957U, // CMP32rr >+ 22618957U, // CMP32rr_REV >+ 3679918U, // CMP64i32 >+ 4212398U, // CMP64mi32 >+ 4212398U, // CMP64mi8 >+ 4212398U, // CMP64mr >+ 22619822U, // CMP64ri32 >+ 22619822U, // CMP64ri8 >+ 83630U, // CMP64rm >+ 22619822U, // CMP64rr >+ 22619822U, // CMP64rr_REV >+ 4726917U, // CMP8i8 >+ 5259397U, // CMP8mi >+ 5259397U, // CMP8mr >+ 22618245U, // CMP8ri >+ 139397U, // CMP8rm >+ 22618245U, // CMP8rr >+ 22618245U, // CMP8rr_REV >+ 56246464U, // CMPSB >+ 73032698U, // CMPSL >+ 89818949U, // CMPSQ >+ 106605102U, // CMPSW >+ 180235U, // CMPXCHG16B >+ 1067302U, // CMPXCHG16rm >+ 22620454U, // CMPXCHG16rr >+ 3162790U, // CMPXCHG32rm >+ 22618790U, // CMPXCHG32rr >+ 4212251U, // CMPXCHG64rm >+ 22619675U, // CMPXCHG64rr >+ 122903U, // CMPXCHG8B >+ 5259347U, // CMPXCHG8rm >+ 22618195U, // CMPXCHG8rr >+ 4736U, // CPUID32 >+ 4736U, // CPUID64 >+ 5057U, // CQO >+ 4755U, // CWD >+ 5001U, // CWDE >+ 4608U, // DAA >+ 5179U, // DAS >+ 4498U, // DATA16_PREFIX >+ 108716U, // DEC16m >+ 10412U, // DEC16r >+ 10412U, // DEC32_16r >+ 8685U, // DEC32_32r >+ 115181U, // DEC32m >+ 8685U, // DEC32r >+ 108716U, // DEC64_16m >+ 10412U, // DEC64_16r >+ 115181U, // DEC64_32m >+ 8685U, // DEC64_32r >+ 124250U, // DEC64m >+ 9562U, // DEC64r >+ 188468U, // DEC8m >+ 8244U, // DEC8r >+ 109220U, // DIV16m >+ 10916U, // DIV16r >+ 115830U, // DIV32m >+ 9334U, // DIV32r >+ 124863U, // DIV64m >+ 10175U, // DIV64r >+ 188649U, // DIV8m >+ 8425U, // DIV8r >+ 11935U, // EH_RETURN >+ 11935U, // EH_RETURN64 >+ 4321U, // EH_SjLj_LongJmp32 >+ 4411U, // EH_SjLj_LongJmp64 >+ 4340U, // EH_SjLj_SetJmp32 >+ 4430U, // EH_SjLj_SetJmp64 >+ 132370U, // EH_SjLj_Setup >+ 123217948U, // ENTER >+ 7416145U, // FARCALL16i >+ 200901U, // FARCALL16m >+ 7414526U, // FARCALL32i >+ 200867U, // FARCALL32m >+ 200884U, // FARCALL64 >+ 7416208U, // FARJMP16i >+ 200910U, // FARJMP16m >+ 7414611U, // FARJMP32i >+ 200876U, // FARJMP32m >+ 200893U, // FARJMP64 >+ 5014U, // FSETPM >+ 4693U, // GETSEC >+ 5488U, // HLT >+ 109219U, // IDIV16m >+ 10915U, // IDIV16r >+ 115829U, // IDIV32m >+ 9333U, // IDIV32r >+ 124862U, // IDIV64m >+ 10174U, // IDIV64r >+ 188648U, // IDIV8m >+ 8424U, // IDIV8r >+ 108901U, // IMUL16m >+ 10597U, // IMUL16r >+ 2132325U, // IMUL16rm >+ 7956837U, // IMUL16rmi >+ 7956837U, // IMUL16rmi8 >+ 2124133U, // IMUL16rr >+ 35154277U, // IMUL16rri >+ 35154277U, // IMUL16rri8 >+ 115474U, // IMUL32m >+ 8978U, // IMUL32r >+ 2138898U, // IMUL32rm >+ 6382354U, // IMUL32rmi >+ 6382354U, // IMUL32rmi8 >+ 2122514U, // IMUL32rr >+ 35152658U, // IMUL32rri >+ 35152658U, // IMUL32rri8 >+ 124536U, // IMUL64m >+ 9848U, // IMUL64r >+ 2147960U, // IMUL64rm >+ 6907512U, // IMUL64rmi32 >+ 6907512U, // IMUL64rmi8 >+ 2123384U, // IMUL64rr >+ 35153528U, // IMUL64rri32 >+ 35153528U, // IMUL64rri8 >+ 188537U, // IMUL8m >+ 8313U, // IMUL8r >+ 534900U, // IN16ri >+ 5569U, // IN16rr >+ 2630440U, // IN32ri >+ 5648U, // IN32rr >+ 4726912U, // IN8ri >+ 4890U, // IN8rr >+ 108722U, // INC16m >+ 10418U, // INC16r >+ 10418U, // INC32_16r >+ 8691U, // INC32_32r >+ 115187U, // INC32m >+ 8691U, // INC32r >+ 108722U, // INC64_16m >+ 10418U, // INC64_16r >+ 115187U, // INC64_32m >+ 8691U, // INC64_32r >+ 124256U, // INC64m >+ 9568U, // INC64r >+ 188474U, // INC8m >+ 8250U, // INC8r >+ 151146U, // INSB >+ 159349U, // INSL >+ 175744U, // INSW >+ 10324U, // INT >+ 4316U, // INT1 >+ 4406U, // INT3 >+ 5052U, // INTO >+ 4762U, // INVD >+ 206937U, // INVEPT32 >+ 206937U, // INVEPT64 >+ 188818U, // INVLPG >+ 5629U, // INVLPGA32 >+ 5697U, // INVLPGA64 >+ 205072U, // INVPCID32 >+ 205072U, // INVPCID64 >+ 205081U, // INVVPID32 >+ 205081U, // INVVPID64 >+ 5557U, // IRET16 >+ 4972U, // IRET32 >+ 5110U, // IRET64 >+ 4577U, // Int_MemBarrier >+ 131378U, // JAE_1 >+ 131378U, // JAE_2 >+ 131378U, // JAE_4 >+ 131073U, // JA_1 >+ 131073U, // JA_2 >+ 131073U, // JA_4 >+ 131390U, // JBE_1 >+ 131390U, // JBE_2 >+ 131390U, // JBE_4 >+ 131165U, // JB_1 >+ 131165U, // JB_2 >+ 131165U, // JB_4 >+ 133829U, // JCXZ >+ 133822U, // JECXZ_32 >+ 133822U, // JECXZ_64 >+ 131414U, // JE_1 >+ 131414U, // JE_2 >+ 131414U, // JE_4 >+ 131402U, // JGE_1 >+ 131402U, // JGE_2 >+ 131402U, // JGE_4 >+ 131470U, // JG_1 >+ 131470U, // JG_2 >+ 131470U, // JG_4 >+ 131418U, // JLE_1 >+ 131418U, // JLE_2 >+ 131418U, // JLE_4 >+ 131789U, // JL_1 >+ 131789U, // JL_2 >+ 131789U, // JL_4 >+ 110799U, // JMP16m >+ 12495U, // JMP16r >+ 118957U, // JMP32m >+ 12461U, // JMP32r >+ 127166U, // JMP64m >+ 12478U, // JMP64r >+ 132336U, // JMP_1 >+ 132336U, // JMP_2 >+ 132336U, // JMP_4 >+ 131430U, // JNE_1 >+ 131430U, // JNE_2 >+ 131430U, // JNE_4 >+ 132314U, // JNO_1 >+ 132314U, // JNO_2 >+ 132314U, // JNO_4 >+ 132341U, // JNP_1 >+ 132341U, // JNP_2 >+ 132341U, // JNP_4 >+ 133186U, // JNS_1 >+ 133186U, // JNS_2 >+ 133186U, // JNS_4 >+ 132310U, // JO_1 >+ 132310U, // JO_2 >+ 132310U, // JO_4 >+ 132332U, // JP_1 >+ 132332U, // JP_2 >+ 132332U, // JP_4 >+ 133835U, // JRCXZ >+ 133182U, // JS_1 >+ 133182U, // JS_2 >+ 133182U, // JS_4 >+ 4833U, // LAHF >+ 100788U, // LAR16rm >+ 22620596U, // LAR16rr >+ 99197U, // LAR32rm >+ 22619005U, // LAR32rr >+ 100043U, // LAR64rm >+ 22619851U, // LAR64rr >+ 1067302U, // LCMPXCHG16 >+ 180235U, // LCMPXCHG16B >+ 3162790U, // LCMPXCHG32 >+ 4212251U, // LCMPXCHG64 >+ 5259347U, // LCMPXCHG8 >+ 122903U, // LCMPXCHG8B >+ 215558U, // LDS16rm >+ 213970U, // LDS32rm >+ 100468U, // LEA16r >+ 65973U, // LEA32r >+ 65973U, // LEA64_32r >+ 83234U, // LEA64r >+ 4820U, // LEAVE >+ 4820U, // LEAVE64 >+ 215571U, // LES16rm >+ 213983U, // LES32rm >+ 215577U, // LFS16rm >+ 213989U, // LFS32rm >+ 214832U, // LFS64rm >+ 199253U, // LGDT16m >+ 197665U, // LGDT32m >+ 198501U, // LGDT64m >+ 215583U, // LGS16rm >+ 213995U, // LGS32rm >+ 214838U, // LGS64rm >+ 199267U, // LIDT16m >+ 197679U, // LIDT32m >+ 198515U, // LIDT64m >+ 109169U, // LLDT16m >+ 10865U, // LLDT16r >+ 109232U, // LMSW16m >+ 10928U, // LMSW16r >+ 1067199U, // LOCK_ADD16mi >+ 1067199U, // LOCK_ADD16mi8 >+ 1067199U, // LOCK_ADD16mr >+ 3162633U, // LOCK_ADD32mi >+ 3162633U, // LOCK_ADD32mi8 >+ 3162633U, // LOCK_ADD32mr >+ 4212086U, // LOCK_ADD64mi32 >+ 4212086U, // LOCK_ADD64mi8 >+ 4212086U, // LOCK_ADD64mr >+ 5259329U, // LOCK_ADD8mi >+ 5259329U, // LOCK_ADD8mr >+ 1067224U, // LOCK_AND16mi >+ 1067224U, // LOCK_AND16mi8 >+ 1067224U, // LOCK_AND16mr >+ 3162658U, // LOCK_AND32mi >+ 3162658U, // LOCK_AND32mi8 >+ 3162658U, // LOCK_AND32mr >+ 4212111U, // LOCK_AND64mi32 >+ 4212111U, // LOCK_AND64mi8 >+ 4212111U, // LOCK_AND64mr >+ 5259335U, // LOCK_AND8mi >+ 5259335U, // LOCK_AND8mr >+ 108716U, // LOCK_DEC16m >+ 115181U, // LOCK_DEC32m >+ 124250U, // LOCK_DEC64m >+ 188468U, // LOCK_DEC8m >+ 108722U, // LOCK_INC16m >+ 115187U, // LOCK_INC32m >+ 124256U, // LOCK_INC64m >+ 188474U, // LOCK_INC8m >+ 1067475U, // LOCK_OR16mi >+ 1067475U, // LOCK_OR16mi8 >+ 1067475U, // LOCK_OR16mr >+ 3163030U, // LOCK_OR32mi >+ 3163030U, // LOCK_OR32mi8 >+ 3163030U, // LOCK_OR32mr >+ 4212452U, // LOCK_OR64mi32 >+ 4212452U, // LOCK_OR64mi8 >+ 4212452U, // LOCK_OR64mr >+ 5259422U, // LOCK_OR8mi >+ 5259422U, // LOCK_OR8mr >+ 4885U, // LOCK_PREFIX >+ 1067152U, // LOCK_SUB16mi >+ 1067152U, // LOCK_SUB16mi8 >+ 1067152U, // LOCK_SUB16mr >+ 3162577U, // LOCK_SUB32mi >+ 3162577U, // LOCK_SUB32mi8 >+ 3162577U, // LOCK_SUB32mr >+ 4212030U, // LOCK_SUB64mi32 >+ 4212030U, // LOCK_SUB64mi8 >+ 4212030U, // LOCK_SUB64mr >+ 5259304U, // LOCK_SUB8mi >+ 5259304U, // LOCK_SUB8mr >+ 1067480U, // LOCK_XOR16mi >+ 1067480U, // LOCK_XOR16mi8 >+ 1067480U, // LOCK_XOR16mr >+ 3163035U, // LOCK_XOR32mi >+ 3163035U, // LOCK_XOR32mi8 >+ 3163035U, // LOCK_XOR32mr >+ 4212466U, // LOCK_XOR64mi32 >+ 4212466U, // LOCK_XOR64mi8 >+ 4212466U, // LOCK_XOR64mr >+ 5259427U, // LOCK_XOR8mi >+ 5259427U, // LOCK_XOR8mr >+ 4939961U, // LODSB >+ 2851800U, // LODSL >+ 239401U, // LODSQ >+ 772620U, // LODSW >+ 132358U, // LOOP >+ 131450U, // LOOPE >+ 131435U, // LOOPNE >+ 9284U, // LRETIL >+ 10120U, // LRETIQ >+ 10879U, // LRETIW >+ 4978U, // LRETL >+ 5116U, // LRETQ >+ 5563U, // LRETW >+ 100703U, // LSL16rm >+ 22620511U, // LSL16rr >+ 66316U, // LSL32rm >+ 22618892U, // LSL32rr >+ 83562U, // LSL64rm >+ 22619754U, // LSL64rr >+ 215605U, // LSS16rm >+ 214017U, // LSS32rm >+ 214860U, // LSS64rm >+ 109034U, // LTRm >+ 10730U, // LTRr >+ 140060862U, // LXADD16 >+ 156836360U, // LXADD32 >+ 173614453U, // LXADD64 >+ 190390336U, // LXADD8 >+ 100998U, // LZCNT16rm >+ 22620806U, // LZCNT16rr >+ 66641U, // LZCNT32rm >+ 22619217U, // LZCNT32rr >+ 83855U, // LZCNT64rm >+ 22620047U, // LZCNT64rr >+ 5006U, // MONTMUL >+ 0U, // MORESTACK_RET >+ 0U, // MORESTACK_RET_RESTORE_R10 >+ 257551U, // MOV16ao16 >+ 257551U, // MOV16ao16_16 >+ 1067690U, // MOV16mi >+ 1067690U, // MOV16mr >+ 1067690U, // MOV16ms >+ 780970U, // MOV16o16a >+ 780970U, // MOV16o16a_16 >+ 22620842U, // MOV16ri >+ 22620842U, // MOV16ri_alt >+ 101034U, // MOV16rm >+ 22620842U, // MOV16rr >+ 22620842U, // MOV16rr_REV >+ 22620842U, // MOV16rs >+ 101034U, // MOV16sm >+ 22620842U, // MOV16sr >+ 265794U, // MOV32ao32 >+ 265794U, // MOV32ao32_16 >+ 22619260U, // MOV32cr >+ 22619260U, // MOV32dr >+ 3163260U, // MOV32mi >+ 3163260U, // MOV32mr >+ 1066108U, // MOV32ms >+ 2884732U, // MOV32o32a >+ 2884732U, // MOV32o32a_16 >+ 0U, // MOV32r0 >+ 22619260U, // MOV32rc >+ 22619260U, // MOV32rd >+ 22619260U, // MOV32ri >+ 0U, // MOV32ri64 >+ 22619260U, // MOV32ri_alt >+ 66684U, // MOV32rm >+ 22619260U, // MOV32rr >+ 22619260U, // MOV32rr_REV >+ 22619260U, // MOV32rs >+ 99452U, // MOV32sm >+ 22619260U, // MOV32sr >+ 257514U, // MOV64ao16 >+ 265754U, // MOV64ao32 >+ 273998U, // MOV64ao64 >+ 281618U, // MOV64ao8 >+ 22620101U, // MOV64cr >+ 22620101U, // MOV64dr >+ 4212677U, // MOV64mi32 >+ 4212677U, // MOV64mr >+ 1066949U, // MOV64ms >+ 780797U, // MOV64o16a >+ 2884553U, // MOV64o32a >+ 3942176U, // MOV64o64a >+ 4997296U, // MOV64o8a >+ 22620101U, // MOV64rc >+ 22620101U, // MOV64rd >+ 22619936U, // MOV64ri >+ 22620101U, // MOV64ri32 >+ 83909U, // MOV64rm >+ 22620101U, // MOV64rr >+ 22620101U, // MOV64rr_REV >+ 22620101U, // MOV64rs >+ 100293U, // MOV64sm >+ 22620101U, // MOV64sr >+ 281655U, // MOV8ao8 >+ 281655U, // MOV8ao8_16 >+ 5259503U, // MOV8mi >+ 5259503U, // MOV8mr >+ 206586095U, // MOV8mr_NOREX >+ 4997359U, // MOV8o8a >+ 4997359U, // MOV8o8a_16 >+ 22618351U, // MOV8ri >+ 22618351U, // MOV8ri_alt >+ 139503U, // MOV8rm >+ 8528111U, // MOV8rm_NOREX >+ 22618351U, // MOV8rr >+ 559489263U, // MOV8rr_NOREX >+ 22618351U, // MOV8rr_REV >+ 1067247U, // MOVBE16mr >+ 100591U, // MOVBE16rm >+ 3162681U, // MOVBE32mr >+ 66105U, // MOVBE32rm >+ 4212134U, // MOVBE64mr >+ 83366U, // MOVBE64rm >+ 0U, // MOVPC32r >+ 286926U, // MOVSB >+ 295957U, // MOVSL >+ 304985U, // MOVSQ >+ 313929U, // MOVSW >+ 141448U, // MOVSX16rm8 >+ 22620296U, // MOVSX16rr8 >+ 99465U, // MOVSX32rm16 >+ 139721U, // MOVSX32rm8 >+ 22619273U, // MOVSX32rr16 >+ 22618569U, // MOVSX32rr8 >+ 22619760U, // MOVSX64_NOREXrr32 >+ 100306U, // MOVSX64rm16 >+ 67184U, // MOVSX64rm32 >+ 140598U, // MOVSX64rm8 >+ 22620114U, // MOVSX64rr16 >+ 22619760U, // MOVSX64rr32 >+ 22619446U, // MOVSX64rr8 >+ 141470U, // MOVZX16rm8 >+ 22620318U, // MOVZX16rr8 >+ 139743U, // MOVZX32_NOREXrm8 >+ 22618591U, // MOVZX32_NOREXrr8 >+ 99473U, // MOVZX32rm16 >+ 139743U, // MOVZX32rm8 >+ 22619281U, // MOVZX32rr16 >+ 22618591U, // MOVZX32rr8 >+ 100314U, // MOVZX64rm16_Q >+ 140620U, // MOVZX64rm8_Q >+ 22620122U, // MOVZX64rr16_Q >+ 22619468U, // MOVZX64rr8_Q >+ 108902U, // MUL16m >+ 10598U, // MUL16r >+ 115475U, // MUL32m >+ 8979U, // MUL32r >+ 124537U, // MUL64m >+ 9849U, // MUL64r >+ 188538U, // MUL8m >+ 8314U, // MUL8r >+ 35169447U, // MULX32rm >+ 35153063U, // MULX32rr >+ 35178480U, // MULX64rm >+ 35153904U, // MULX64rr >+ 108832U, // NEG16m >+ 10528U, // NEG16r >+ 115360U, // NEG32m >+ 8864U, // NEG32r >+ 124437U, // NEG64m >+ 9749U, // NEG64r >+ 188493U, // NEG8m >+ 8269U, // NEG8r >+ 5073U, // NOOP >+ 108960U, // NOOP18_16m4 >+ 108960U, // NOOP18_16m5 >+ 108960U, // NOOP18_16m6 >+ 108960U, // NOOP18_16m7 >+ 10656U, // NOOP18_16r4 >+ 10656U, // NOOP18_16r5 >+ 10656U, // NOOP18_16r6 >+ 10656U, // NOOP18_16r7 >+ 115555U, // NOOP18_m4 >+ 115555U, // NOOP18_m5 >+ 115555U, // NOOP18_m6 >+ 115555U, // NOOP18_m7 >+ 9059U, // NOOP18_r4 >+ 9059U, // NOOP18_r5 >+ 9059U, // NOOP18_r6 >+ 9059U, // NOOP18_r7 >+ 123217153U, // NOOP19rr >+ 115555U, // NOOPL >+ 115555U, // NOOPL_19 >+ 115555U, // NOOPL_1a >+ 115555U, // NOOPL_1b >+ 115555U, // NOOPL_1c >+ 115555U, // NOOPL_1d >+ 115555U, // NOOPL_1e >+ 108960U, // NOOPW >+ 108960U, // NOOPW_19 >+ 108960U, // NOOPW_1a >+ 108960U, // NOOPW_1b >+ 108960U, // NOOPW_1c >+ 108960U, // NOOPW_1d >+ 108960U, // NOOPW_1e >+ 109206U, // NOT16m >+ 10902U, // NOT16r >+ 115809U, // NOT32m >+ 9313U, // NOT32r >+ 124831U, // NOT64m >+ 10143U, // NOT64r >+ 188635U, // NOT8m >+ 8411U, // NOT8r >+ 534995U, // OR16i16 >+ 1067475U, // OR16mi >+ 1067475U, // OR16mi8 >+ 1067475U, // OR16mr >+ 1599955U, // OR16ri >+ 1599955U, // OR16ri8 >+ 1608147U, // OR16rm >+ 1599955U, // OR16rr >+ 2124243U, // OR16rr_REV >+ 2630550U, // OR32i32 >+ 3163030U, // OR32mi >+ 3163030U, // OR32mi8 >+ 3163030U, // OR32mr >+ 3163030U, // OR32mrLocked >+ 1598358U, // OR32ri >+ 1598358U, // OR32ri8 >+ 1614742U, // OR32rm >+ 1598358U, // OR32rr >+ 2122646U, // OR32rr_REV >+ 3679972U, // OR64i32 >+ 4212452U, // OR64mi32 >+ 4212452U, // OR64mi8 >+ 4212452U, // OR64mr >+ 1599204U, // OR64ri32 >+ 1599204U, // OR64ri8 >+ 1623780U, // OR64rm >+ 1599204U, // OR64rr >+ 2123492U, // OR64rr_REV >+ 4726942U, // OR8i8 >+ 5259422U, // OR8mi >+ 5259422U, // OR8mr >+ 1597598U, // OR8ri >+ 1597598U, // OR8ri8 >+ 57502U, // OR8rm >+ 1597598U, // OR8rr >+ 2121886U, // OR8rr_REV >+ 11780U, // OUT16ir >+ 5730U, // OUT16rr >+ 11830U, // OUT32ir >+ 5744U, // OUT32rr >+ 11308U, // OUT8ir >+ 5716U, // OUT8rr >+ 9134279U, // OUTSB >+ 9143309U, // OUTSL >+ 9161281U, // OUTSW >+ 35169094U, // PDEP32rm >+ 35152710U, // PDEP32rr >+ 35178151U, // PDEP64rm >+ 35153575U, // PDEP64rr >+ 35169390U, // PEXT32rm >+ 35153006U, // PEXT32rr >+ 35178423U, // PEXT64rm >+ 35153847U, // PEXT64rr >+ 10662U, // POP16r >+ 108966U, // POP16rmm >+ 10662U, // POP16rmr >+ 9065U, // POP32r >+ 115561U, // POP32rmm >+ 9065U, // POP32rmr >+ 9917U, // POP64r >+ 124605U, // POP64rmm >+ 9917U, // POP64rmr >+ 5513U, // POPA16 >+ 4910U, // POPA32 >+ 5232U, // POPDS16 >+ 5213U, // POPDS32 >+ 5270U, // POPES16 >+ 5251U, // POPES32 >+ 5526U, // POPF16 >+ 4923U, // POPF32 >+ 5084U, // POPF64 >+ 5327U, // POPFS16 >+ 5289U, // POPFS32 >+ 5308U, // POPFS64 >+ 5384U, // POPGS16 >+ 5346U, // POPGS32 >+ 5365U, // POPGS64 >+ 5474U, // POPSS16 >+ 5455U, // POPSS32 >+ 10552U, // PUSH16i8 >+ 10552U, // PUSH16r >+ 108856U, // PUSH16rmm >+ 10552U, // PUSH16rmr >+ 8888U, // PUSH32i8 >+ 8888U, // PUSH32r >+ 115384U, // PUSH32rmm >+ 8888U, // PUSH32rmr >+ 10552U, // PUSH64i16 >+ 9773U, // PUSH64i32 >+ 9773U, // PUSH64i8 >+ 9773U, // PUSH64r >+ 124461U, // PUSH64rmm >+ 9773U, // PUSH64rmr >+ 5506U, // PUSHA16 >+ 4903U, // PUSHA32 >+ 5193U, // PUSHCS16 >+ 5183U, // PUSHCS32 >+ 5222U, // PUSHDS16 >+ 5203U, // PUSHDS32 >+ 5260U, // PUSHES16 >+ 5241U, // PUSHES32 >+ 5519U, // PUSHF16 >+ 4916U, // PUSHF32 >+ 5077U, // PUSHF64 >+ 5317U, // PUSHFS16 >+ 5279U, // PUSHFS32 >+ 5298U, // PUSHFS64 >+ 5374U, // PUSHGS16 >+ 5336U, // PUSHGS32 >+ 5355U, // PUSHGS64 >+ 5464U, // PUSHSS16 >+ 5445U, // PUSHSS32 >+ 10552U, // PUSHi16 >+ 8888U, // PUSHi32 >+ 109516U, // RCL16m1 >+ 109981U, // RCL16mCL >+ 1067333U, // RCL16mi >+ 11212U, // RCL16r1 >+ 11677U, // RCL16rCL >+ 2124101U, // RCL16ri >+ 118411U, // RCL32m1 >+ 117949U, // RCL32mCL >+ 3162848U, // RCL32mi >+ 11052U, // RCL32r1 >+ 11453U, // RCL32rCL >+ 2122464U, // RCL32ri >+ 125820U, // RCL64m1 >+ 126253U, // RCL64mCL >+ 4212305U, // RCL64mi >+ 11132U, // RCL64r1 >+ 11565U, // RCL64rCL >+ 2123345U, // RCL64ri >+ 191196U, // RCL8m1 >+ 191565U, // RCL8mCL >+ 5259367U, // RCL8mi >+ 10972U, // RCL8r1 >+ 11341U, // RCL8rCL >+ 2121831U, // RCL8ri >+ 109556U, // RCR16m1 >+ 110025U, // RCR16mCL >+ 1067456U, // RCR16mi >+ 11252U, // RCR16r1 >+ 11721U, // RCR16rCL >+ 2124224U, // RCR16ri >+ 117588U, // RCR32m1 >+ 117993U, // RCR32mCL >+ 3163017U, // RCR32mi >+ 11092U, // RCR32r1 >+ 11497U, // RCR32rCL >+ 2122633U, // RCR32ri >+ 125860U, // RCR64m1 >+ 126297U, // RCR64mCL >+ 4212439U, // RCR64mi >+ 11172U, // RCR64r1 >+ 11609U, // RCR64rCL >+ 2123479U, // RCR64ri >+ 191236U, // RCR8m1 >+ 191609U, // RCR8mCL >+ 5259409U, // RCR8mi >+ 11012U, // RCR8r1 >+ 11385U, // RCR8rCL >+ 2121873U, // RCR8ri >+ 8796U, // RDFSBASE >+ 9673U, // RDFSBASE64 >+ 8818U, // RDGSBASE >+ 9695U, // RDGSBASE64 >+ 5153U, // RDMSR >+ 4713U, // RDPMC >+ 10453U, // RDRAND16r >+ 8735U, // RDRAND32r >+ 9612U, // RDRAND64r >+ 10437U, // RDSEED16r >+ 8719U, // RDSEED32r >+ 9596U, // RDSEED64r >+ 4726U, // RDTSC >+ 5062U, // RDTSCP >+ 4238U, // RELEASE_MOV16mr >+ 4238U, // RELEASE_MOV32mr >+ 4238U, // RELEASE_MOV64mr >+ 4238U, // RELEASE_MOV8mr >+ 4776U, // REPNE_PREFIX >+ 4657U, // REP_MOVSB_32 >+ 4657U, // REP_MOVSB_64 >+ 4962U, // REP_MOVSD_32 >+ 4962U, // REP_MOVSD_64 >+ 5100U, // REP_MOVSQ_64 >+ 5542U, // REP_MOVSW_32 >+ 5542U, // REP_MOVSW_64 >+ 5069U, // REP_PREFIX >+ 4647U, // REP_STOSB_32 >+ 4647U, // REP_STOSB_64 >+ 4952U, // REP_STOSD_32 >+ 4952U, // REP_STOSD_64 >+ 5090U, // REP_STOSQ_64 >+ 5532U, // REP_STOSW_32 >+ 5532U, // REP_STOSW_64 >+ 9285U, // RETIL >+ 10121U, // RETIQ >+ 10880U, // RETIW >+ 4973U, // RETL >+ 5111U, // RETQ >+ 5558U, // RETW >+ 4492U, // REX64_PREFIX >+ 109536U, // ROL16m1 >+ 110003U, // ROL16mCL >+ 1067353U, // ROL16mi >+ 11232U, // ROL16r1 >+ 11699U, // ROL16rCL >+ 2124121U, // ROL16ri >+ 117568U, // ROL32m1 >+ 117971U, // ROL32mCL >+ 3162886U, // ROL32mi >+ 11072U, // ROL32r1 >+ 11475U, // ROL32rCL >+ 2122502U, // ROL32ri >+ 125840U, // ROL64m1 >+ 126275U, // ROL64mCL >+ 4212324U, // ROL64mi >+ 11152U, // ROL64r1 >+ 11587U, // ROL64rCL >+ 2123364U, // ROL64ri >+ 191216U, // ROL8m1 >+ 191587U, // ROL8mCL >+ 5259379U, // ROL8mi >+ 10992U, // ROL8r1 >+ 11363U, // ROL8rCL >+ 2121843U, // ROL8ri >+ 109576U, // ROR16m1 >+ 110047U, // ROR16mCL >+ 1067474U, // ROR16mi >+ 11272U, // ROR16r1 >+ 11743U, // ROR16rCL >+ 2124242U, // ROR16ri >+ 117608U, // ROR32m1 >+ 118015U, // ROR32mCL >+ 3163029U, // ROR32mi >+ 11112U, // ROR32r1 >+ 11519U, // ROR32rCL >+ 2122645U, // ROR32ri >+ 125880U, // ROR64m1 >+ 126319U, // ROR64mCL >+ 4212451U, // ROR64mi >+ 11192U, // ROR64r1 >+ 11631U, // ROR64rCL >+ 2123491U, // ROR64ri >+ 191256U, // ROR8m1 >+ 191631U, // ROR8mCL >+ 5259421U, // ROR8mi >+ 11032U, // ROR8r1 >+ 11407U, // ROR8rCL >+ 2121885U, // ROR8ri >+ 6382787U, // RORX32mi >+ 35153091U, // RORX32ri >+ 6907916U, // RORX64mi >+ 35153932U, // RORX64ri >+ 5021U, // RSM >+ 4838U, // SAHF >+ 109506U, // SAL16m1 >+ 109970U, // SAL16mCL >+ 1067327U, // SAL16mi >+ 11202U, // SAL16r1 >+ 11666U, // SAL16rCL >+ 2124095U, // SAL16ri >+ 117538U, // SAL32m1 >+ 117938U, // SAL32mCL >+ 3162842U, // SAL32mi >+ 11042U, // SAL32r1 >+ 11442U, // SAL32rCL >+ 2122458U, // SAL32ri >+ 125810U, // SAL64m1 >+ 126242U, // SAL64mCL >+ 4212299U, // SAL64mi >+ 11122U, // SAL64r1 >+ 11554U, // SAL64rCL >+ 2123339U, // SAL64ri >+ 191186U, // SAL8m1 >+ 191554U, // SAL8mCL >+ 5259361U, // SAL8mi >+ 10962U, // SAL8r1 >+ 11330U, // SAL8rCL >+ 2121825U, // SAL8ri >+ 4700U, // SALC >+ 109546U, // SAR16m1 >+ 110014U, // SAR16mCL >+ 1067450U, // SAR16mi >+ 11242U, // SAR16r1 >+ 11710U, // SAR16rCL >+ 2124218U, // SAR16ri >+ 117578U, // SAR32m1 >+ 117982U, // SAR32mCL >+ 3163011U, // SAR32mi >+ 11082U, // SAR32r1 >+ 11486U, // SAR32rCL >+ 2122627U, // SAR32ri >+ 125850U, // SAR64m1 >+ 126286U, // SAR64mCL >+ 4212433U, // SAR64mi >+ 11162U, // SAR64r1 >+ 11598U, // SAR64rCL >+ 2123473U, // SAR64ri >+ 191226U, // SAR8m1 >+ 191598U, // SAR8mCL >+ 5259403U, // SAR8mi >+ 11002U, // SAR8r1 >+ 11374U, // SAR8rCL >+ 2121867U, // SAR8ri >+ 6382773U, // SARX32rm >+ 35153077U, // SARX32rr >+ 6907902U, // SARX64rm >+ 35153918U, // SARX64rr >+ 534658U, // SBB16i16 >+ 1067138U, // SBB16mi >+ 1067138U, // SBB16mi8 >+ 1067138U, // SBB16mr >+ 1599618U, // SBB16ri >+ 1599618U, // SBB16ri8 >+ 1607810U, // SBB16rm >+ 1599618U, // SBB16rr >+ 2123906U, // SBB16rr_REV >+ 2630083U, // SBB32i32 >+ 3162563U, // SBB32mi >+ 3162563U, // SBB32mi8 >+ 3162563U, // SBB32mr >+ 1597891U, // SBB32ri >+ 1597891U, // SBB32ri8 >+ 1614275U, // SBB32rm >+ 1597891U, // SBB32rr >+ 2122179U, // SBB32rr_REV >+ 3679536U, // SBB64i32 >+ 4212016U, // SBB64mi32 >+ 4212016U, // SBB64mi8 >+ 4212016U, // SBB64mr >+ 1598768U, // SBB64ri32 >+ 1598768U, // SBB64ri8 >+ 1623344U, // SBB64rm >+ 1598768U, // SBB64rr >+ 2123056U, // SBB64rr_REV >+ 4726818U, // SBB8i8 >+ 5259298U, // SBB8mi >+ 5259298U, // SBB8mr >+ 1597474U, // SBB8ri >+ 57378U, // SBB8rm >+ 1597474U, // SBB8rr >+ 2121762U, // SBB8rr_REV >+ 4866217U, // SCASB >+ 2778050U, // SCASL >+ 3835673U, // SCASQ >+ 698870U, // SCASW >+ 5400U, // SEG_ALLOCA_32 >+ 5400U, // SEG_ALLOCA_64 >+ 4803U, // SEH_EndPrologue >+ 4789U, // SEH_Epilogue >+ 12013U, // SEH_PushFrame >+ 12058U, // SEH_PushReg >+ 123219724U, // SEH_SaveReg >+ 123219638U, // SEH_SaveXMM >+ 123219709U, // SEH_SetFrame >+ 11996U, // SEH_StackAlloc >+ 188727U, // SETAEm >+ 8503U, // SETAEr >+ 188421U, // SETAm >+ 8197U, // SETAr >+ 188739U, // SETBEm >+ 8515U, // SETBEr >+ 0U, // SETB_C16r >+ 0U, // SETB_C32r >+ 0U, // SETB_C64r >+ 0U, // SETB_C8r >+ 188629U, // SETBm >+ 8405U, // SETBr >+ 188801U, // SETEm >+ 8577U, // SETEr >+ 188751U, // SETGEm >+ 8527U, // SETGEr >+ 188826U, // SETGm >+ 8602U, // SETGr >+ 188767U, // SETLEm >+ 8543U, // SETLEr >+ 189515U, // SETLm >+ 9291U, // SETLr >+ 188787U, // SETNEm >+ 8563U, // SETNEr >+ 189663U, // SETNOm >+ 9439U, // SETNOr >+ 189690U, // SETNPm >+ 9466U, // SETNPr >+ 190535U, // SETNSm >+ 10311U, // SETNSr >+ 189670U, // SETOm >+ 9446U, // SETOr >+ 189708U, // SETPm >+ 9484U, // SETPr >+ 190542U, // SETSm >+ 10318U, // SETSr >+ 199260U, // SGDT16m >+ 197672U, // SGDT32m >+ 198508U, // SGDT64m >+ 109526U, // SHL16m1 >+ 109992U, // SHL16mCL >+ 1067339U, // SHL16mi >+ 11222U, // SHL16r1 >+ 11688U, // SHL16rCL >+ 2124107U, // SHL16ri >+ 117558U, // SHL32m1 >+ 117960U, // SHL32mCL >+ 3162854U, // SHL32mi >+ 11062U, // SHL32r1 >+ 11464U, // SHL32rCL >+ 2122470U, // SHL32ri >+ 125830U, // SHL64m1 >+ 126264U, // SHL64mCL >+ 4212311U, // SHL64mi >+ 11142U, // SHL64r1 >+ 11576U, // SHL64rCL >+ 2123351U, // SHL64ri >+ 191206U, // SHL8m1 >+ 191576U, // SHL8mCL >+ 5259373U, // SHL8mi >+ 10982U, // SHL8r1 >+ 11352U, // SHL8rCL >+ 2121837U, // SHL8ri >+ 1068410U, // SHLD16mrCL >+ 227633358U, // SHLD16mri8 >+ 2125178U, // SHLD16rrCL >+ 321742U, // SHLD16rri8 >+ 3165338U, // SHLD32mrCL >+ 244408856U, // SHLD32mri8 >+ 2124954U, // SHLD32rrCL >+ 320024U, // SHLD32rri8 >+ 4214026U, // SHLD64mrCL >+ 261186949U, // SHLD64mri8 >+ 2125066U, // SHLD64rrCL >+ 320901U, // SHLD64rri8 >+ 6382752U, // SHLX32rm >+ 35153056U, // SHLX32rr >+ 6907881U, // SHLX64rm >+ 35153897U, // SHLX64rr >+ 109566U, // SHR16m1 >+ 110036U, // SHR16mCL >+ 1067468U, // SHR16mi >+ 11262U, // SHR16r1 >+ 11732U, // SHR16rCL >+ 2124236U, // SHR16ri >+ 117598U, // SHR32m1 >+ 118004U, // SHR32mCL >+ 3163023U, // SHR32mi >+ 11102U, // SHR32r1 >+ 11508U, // SHR32rCL >+ 2122639U, // SHR32ri >+ 125870U, // SHR64m1 >+ 126308U, // SHR64mCL >+ 4212445U, // SHR64mi >+ 11182U, // SHR64r1 >+ 11620U, // SHR64rCL >+ 2123485U, // SHR64ri >+ 191246U, // SHR8m1 >+ 191620U, // SHR8mCL >+ 5259415U, // SHR8mi >+ 11022U, // SHR8r1 >+ 11396U, // SHR8rCL >+ 2121879U, // SHR8ri >+ 1068422U, // SHRD16mrCL >+ 227633374U, // SHRD16mri8 >+ 2125190U, // SHRD16rrCL >+ 321758U, // SHRD16rri8 >+ 3165350U, // SHRD32mrCL >+ 244408872U, // SHRD32mri8 >+ 2124966U, // SHRD32rrCL >+ 320040U, // SHRD32rri8 >+ 4214038U, // SHRD64mrCL >+ 261186965U, // SHRD64mri8 >+ 2125078U, // SHRD64rrCL >+ 320917U, // SHRD64rri8 >+ 6382780U, // SHRX32rm >+ 35153084U, // SHRX32rr >+ 6907909U, // SHRX64rm >+ 35153925U, // SHRX64rr >+ 199274U, // SIDT16m >+ 197686U, // SIDT32m >+ 198522U, // SIDT64m >+ 5617U, // SKINIT >+ 109176U, // SLDT16m >+ 10872U, // SLDT16r >+ 9277U, // SLDT32r >+ 108417U, // SLDT64m >+ 10113U, // SLDT64r >+ 109239U, // SMSW16m >+ 10935U, // SMSW16r >+ 9346U, // SMSW32r >+ 10187U, // SMSW64r >+ 4678U, // STAC >+ 4732U, // STC >+ 4751U, // STD >+ 4857U, // STGI >+ 4866U, // STI >+ 150560U, // STOSB >+ 159273U, // STOSL >+ 167517U, // STOSQ >+ 175608U, // STOSW >+ 10736U, // STR16r >+ 9140U, // STR32r >+ 9995U, // STR64r >+ 109040U, // STRm >+ 534672U, // SUB16i16 >+ 1067152U, // SUB16mi >+ 1067152U, // SUB16mi8 >+ 1067152U, // SUB16mr >+ 1599632U, // SUB16ri >+ 1599632U, // SUB16ri8 >+ 1607824U, // SUB16rm >+ 1599632U, // SUB16rr >+ 2123920U, // SUB16rr_REV >+ 2630097U, // SUB32i32 >+ 3162577U, // SUB32mi >+ 3162577U, // SUB32mi8 >+ 3162577U, // SUB32mr >+ 1597905U, // SUB32ri >+ 1597905U, // SUB32ri8 >+ 1614289U, // SUB32rm >+ 1597905U, // SUB32rr >+ 2122193U, // SUB32rr_REV >+ 3679550U, // SUB64i32 >+ 4212030U, // SUB64mi32 >+ 4212030U, // SUB64mi8 >+ 4212030U, // SUB64mr >+ 1598782U, // SUB64ri32 >+ 1598782U, // SUB64ri8 >+ 1623358U, // SUB64rm >+ 1598782U, // SUB64rr >+ 2123070U, // SUB64rr_REV >+ 4726824U, // SUB8i8 >+ 5259304U, // SUB8mi >+ 5259304U, // SUB8mr >+ 1597480U, // SUB8ri >+ 1597480U, // SUB8ri8 >+ 57384U, // SUB8rm >+ 1597480U, // SUB8rr >+ 2121768U, // SUB8rr_REV >+ 5393U, // SWAPGS >+ 4944U, // SYSCALL >+ 5144U, // SYSENTER >+ 4992U, // SYSEXIT >+ 5130U, // SYSEXIT64 >+ 4984U, // SYSRET >+ 5122U, // SYSRET64 >+ 65795U, // T1MSKC32rm >+ 22618371U, // T1MSKC32rr >+ 82179U, // T1MSKC64rm >+ 22618371U, // T1MSKC64rr >+ 10093808U, // TAILJMPd >+ 10093808U, // TAILJMPd64 >+ 10080429U, // TAILJMPm >+ 10088638U, // TAILJMPm64 >+ 0U, // TAILJMPr >+ 9973950U, // TAILJMPr64 >+ 0U, // TCRETURNdi >+ 0U, // TCRETURNdi64 >+ 0U, // TCRETURNmi >+ 0U, // TCRETURNmi64 >+ 0U, // TCRETURNri >+ 0U, // TCRETURNri64 >+ 535196U, // TEST16i16 >+ 1067676U, // TEST16mi >+ 1067676U, // TEST16mi_alt >+ 22620828U, // TEST16ri >+ 22620828U, // TEST16ri_alt >+ 1067676U, // TEST16rm >+ 22620828U, // TEST16rr >+ 2630759U, // TEST32i32 >+ 3163239U, // TEST32mi >+ 3163239U, // TEST32mi_alt >+ 22619239U, // TEST32ri >+ 22619239U, // TEST32ri_alt >+ 3163239U, // TEST32rm >+ 22619239U, // TEST32rr >+ 3680176U, // TEST64i32 >+ 4212656U, // TEST64mi32 >+ 4212656U, // TEST64mi32_alt >+ 22620080U, // TEST64ri32 >+ 22620080U, // TEST64ri32_alt >+ 4212656U, // TEST64rm >+ 22620080U, // TEST64rr >+ 4727009U, // TEST8i8 >+ 5259489U, // TEST8mi >+ 5259489U, // TEST8mi_alt >+ 22618337U, // TEST8ri >+ 0U, // TEST8ri_NOREX >+ 22618337U, // TEST8ri_alt >+ 5259489U, // TEST8rm >+ 22618337U, // TEST8rr >+ 4358U, // TLSCall_32 >+ 4448U, // TLSCall_64 >+ 4371U, // TLS_addr32 >+ 4461U, // TLS_addr64 >+ 4384U, // TLS_base_addr32 >+ 4474U, // TLS_base_addr64 >+ 4402U, // TRAP >+ 101006U, // TZCNT16rm >+ 22620814U, // TZCNT16rr >+ 66649U, // TZCNT32rm >+ 22619225U, // TZCNT32rr >+ 83863U, // TZCNT64rm >+ 22620055U, // TZCNT64rr >+ 65966U, // TZMSK32rm >+ 22618542U, // TZMSK32rr >+ 82350U, // TZMSK64rm >+ 22618542U, // TZMSK64rr >+ 4612U, // UD2B >+ 274214548U, // VAARG_64 >+ 1196961476U, // VASTART_SAVE_XMM_REGS >+ 108587U, // VERRm >+ 10283U, // VERRr >+ 108998U, // VERWm >+ 10694U, // VERWr >+ 4937U, // VMCALL >+ 124947U, // VMCLEARm >+ 4719U, // VMFUNC >+ 4843U, // VMLAUNCH >+ 5582U, // VMLOAD32 >+ 5662U, // VMLOAD64 >+ 4929U, // VMMCALL >+ 123170U, // VMPTRLDm >+ 125035U, // VMPTRSTm >+ 3162623U, // VMREAD32rm >+ 22618623U, // VMREAD32rr >+ 4212076U, // VMREAD64rm >+ 22619500U, // VMREAD64rr >+ 4767U, // VMRESUME >+ 5606U, // VMRUN32 >+ 5686U, // VMRUN64 >+ 5594U, // VMSAVE32 >+ 5674U, // VMSAVE64 >+ 66184U, // VMWRITE32rm >+ 22618760U, // VMWRITE32rr >+ 83445U, // VMWRITE64rm >+ 22619637U, // VMWRITE64rr >+ 4826U, // VMXOFF >+ 124111U, // VMXON >+ 132701U, // W64ALLOCA >+ 4760U, // WBINVD >+ 5025U, // WIN_ALLOCA >+ 4870U, // WIN_FTOL_32 >+ 4870U, // WIN_FTOL_64 >+ 8807U, // WRFSBASE >+ 9684U, // WRFSBASE64 >+ 8829U, // WRGSBASE >+ 9706U, // WRGSBASE64 >+ 5159U, // WRMSR >+ 1067198U, // XADD16rm >+ 22620350U, // XADD16rr >+ 3162632U, // XADD32rm >+ 22618632U, // XADD32rr >+ 4212085U, // XADD64rm >+ 22619509U, // XADD64rr >+ 5259328U, // XADD8rm >+ 22618176U, // XADD8rr >+ 534825U, // XCHG16ar >+ 140060969U, // XCHG16rm >+ 291055913U, // XCHG16rr >+ 2630313U, // XCHG32ar >+ 2630313U, // XCHG32ar64 >+ 156836521U, // XCHG32rm >+ 291054249U, // XCHG32rr >+ 3679774U, // XCHG64ar >+ 173614622U, // XCHG64rm >+ 291055134U, // XCHG64rr >+ 190390358U, // XCHG8rm >+ 291053654U, // XCHG8rr >+ 4683U, // XCRYPTCBC >+ 4627U, // XCRYPTCFB >+ 5165U, // XCRYPTCTR >+ 4617U, // XCRYPTECB >+ 4637U, // XCRYPTOFB >+ 5492U, // XGETBV >+ 4667U, // XLAT >+ 535000U, // XOR16i16 >+ 1067480U, // XOR16mi >+ 1067480U, // XOR16mi8 >+ 1067480U, // XOR16mr >+ 1599960U, // XOR16ri >+ 1599960U, // XOR16ri8 >+ 1608152U, // XOR16rm >+ 1599960U, // XOR16rr >+ 2124248U, // XOR16rr_REV >+ 2630555U, // XOR32i32 >+ 3163035U, // XOR32mi >+ 3163035U, // XOR32mi8 >+ 3163035U, // XOR32mr >+ 1598363U, // XOR32ri >+ 1598363U, // XOR32ri8 >+ 1614747U, // XOR32rm >+ 1598363U, // XOR32rr >+ 2122651U, // XOR32rr_REV >+ 3679986U, // XOR64i32 >+ 4212466U, // XOR64mi32 >+ 4212466U, // XOR64mi8 >+ 4212466U, // XOR64mr >+ 1599218U, // XOR64ri32 >+ 1599218U, // XOR64ri8 >+ 1623794U, // XOR64rm >+ 1599218U, // XOR64rr >+ 2123506U, // XOR64rr_REV >+ 4726947U, // XOR8i8 >+ 5259427U, // XOR8mi >+ 5259427U, // XOR8mr >+ 1597603U, // XOR8ri >+ 1597603U, // XOR8ri8 >+ 57507U, // XOR8rm >+ 1597603U, // XOR8rr >+ 2121891U, // XOR8rr_REV >+ 198691U, // XRSTOR >+ 198377U, // XRSTOR64 >+ 196999U, // XSAVE >+ 198143U, // XSAVE64 >+ 198753U, // XSAVEOPT >+ 198565U, // XSAVEOPT64 >+ 5499U, // XSETBV >+ 4310U, // XSHA1 >+ 4505U, // XSHA256 >+ 4782U, // XSTORE >+ 0U >+ }; >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 'j', 'a', 9, 0, >+ /* 4 */ 's', 'e', 't', 'a', 9, 0, >+ /* 10 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0, >+ /* 22 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '8', 'b', 9, 0, >+ /* 33 */ 's', 'b', 'b', 'b', 9, 0, >+ /* 39 */ 's', 'u', 'b', 'b', 9, 0, >+ /* 45 */ 'a', 'd', 'c', 'b', 9, 0, >+ /* 51 */ 'd', 'e', 'c', 'b', 9, 0, >+ /* 57 */ 'i', 'n', 'c', 'b', 9, 0, >+ /* 63 */ 'x', 'a', 'd', 'd', 'b', 9, 0, >+ /* 70 */ 'a', 'n', 'd', 'b', 9, 0, >+ /* 76 */ 'n', 'e', 'g', 'b', 9, 0, >+ /* 82 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'b', 9, 0, >+ /* 92 */ 'j', 'b', 9, 0, >+ /* 96 */ 's', 'a', 'l', 'b', 9, 0, >+ /* 102 */ 'r', 'c', 'l', 'b', 9, 0, >+ /* 108 */ 's', 'h', 'l', 'b', 9, 0, >+ /* 114 */ 'r', 'o', 'l', 'b', 9, 0, >+ /* 120 */ 'i', 'm', 'u', 'l', 'b', 9, 0, >+ /* 127 */ 'i', 'n', 'b', 9, 0, >+ /* 132 */ 'c', 'm', 'p', 'b', 9, 0, >+ /* 138 */ 's', 'a', 'r', 'b', 9, 0, >+ /* 144 */ 'r', 'c', 'r', 'b', 9, 0, >+ /* 150 */ 's', 'h', 'r', 'b', 9, 0, >+ /* 156 */ 'r', 'o', 'r', 'b', 9, 0, >+ /* 162 */ 'x', 'o', 'r', 'b', 9, 0, >+ /* 168 */ 's', 'c', 'a', 's', 'b', 9, 0, >+ /* 175 */ 'm', 'o', 'v', 'a', 'b', 's', 'b', 9, 0, >+ /* 184 */ 'l', 'o', 'd', 's', 'b', 9, 0, >+ /* 191 */ 'c', 'm', 'p', 's', 'b', 9, 0, >+ /* 198 */ 'o', 'u', 't', 's', 'b', 9, 0, >+ /* 205 */ 'm', 'o', 'v', 's', 'b', 9, 0, >+ /* 212 */ 's', 'e', 't', 'b', 9, 0, >+ /* 218 */ 'n', 'o', 't', 'b', 9, 0, >+ /* 224 */ 't', 'e', 's', 't', 'b', 9, 0, >+ /* 231 */ 'i', 'd', 'i', 'v', 'b', 9, 0, >+ /* 238 */ 'm', 'o', 'v', 'b', 9, 0, >+ /* 244 */ 'b', 'l', 'c', 'i', 'c', 9, 0, >+ /* 251 */ 'b', 'l', 's', 'i', 'c', 9, 0, >+ /* 258 */ 't', '1', 'm', 's', 'k', 'c', 9, 0, >+ /* 266 */ 'a', 'a', 'd', 9, 0, >+ /* 271 */ 'i', 'n', 'v', 'p', 'c', 'i', 'd', 9, 0, >+ /* 280 */ 'i', 'n', 'v', 'v', 'p', 'i', 'd', 9, 0, >+ /* 289 */ 'v', 'm', 'p', 't', 'r', 'l', 'd', 9, 0, >+ /* 298 */ 'b', 'o', 'u', 'n', 'd', 9, 0, >+ /* 305 */ 'j', 'a', 'e', 9, 0, >+ /* 310 */ 's', 'e', 't', 'a', 'e', 9, 0, >+ /* 317 */ 'j', 'b', 'e', 9, 0, >+ /* 322 */ 's', 'e', 't', 'b', 'e', 9, 0, >+ /* 329 */ 'j', 'g', 'e', 9, 0, >+ /* 334 */ 's', 'e', 't', 'g', 'e', 9, 0, >+ /* 341 */ 'j', 'e', 9, 0, >+ /* 345 */ 'j', 'l', 'e', 9, 0, >+ /* 350 */ 's', 'e', 't', 'l', 'e', 9, 0, >+ /* 357 */ 'j', 'n', 'e', 9, 0, >+ /* 362 */ 'l', 'o', 'o', 'p', 'n', 'e', 9, 0, >+ /* 370 */ 's', 'e', 't', 'n', 'e', 9, 0, >+ /* 377 */ 'l', 'o', 'o', 'p', 'e', 9, 0, >+ /* 384 */ 's', 'e', 't', 'e', 9, 0, >+ /* 390 */ 'x', 's', 'a', 'v', 'e', 9, 0, >+ /* 397 */ 'j', 'g', 9, 0, >+ /* 401 */ 'i', 'n', 'v', 'l', 'p', 'g', 9, 0, >+ /* 409 */ 's', 'e', 't', 'g', 9, 0, >+ /* 415 */ 'b', 'l', 'c', 'i', 9, 0, >+ /* 421 */ 'b', 'l', 'c', 'm', 's', 'k', 9, 0, >+ /* 429 */ 't', 'z', 'm', 's', 'k', 9, 0, >+ /* 436 */ 'l', 'e', 'a', 'l', 9, 0, >+ /* 442 */ 'c', 'm', 'o', 'v', 'a', 'l', 9, 0, >+ /* 450 */ 's', 'b', 'b', 'l', 9, 0, >+ /* 456 */ 'm', 'o', 'v', 's', 'b', 'l', 9, 0, >+ /* 464 */ 's', 'u', 'b', 'l', 9, 0, >+ /* 470 */ 'c', 'm', 'o', 'v', 'b', 'l', 9, 0, >+ /* 478 */ 'm', 'o', 'v', 'z', 'b', 'l', 9, 0, >+ /* 486 */ 'a', 'd', 'c', 'l', 9, 0, >+ /* 492 */ 'd', 'e', 'c', 'l', 9, 0, >+ /* 498 */ 'i', 'n', 'c', 'l', 9, 0, >+ /* 504 */ 'b', 't', 'c', 'l', 9, 0, >+ /* 510 */ 'v', 'm', 'r', 'e', 'a', 'd', 'l', 9, 0, >+ /* 519 */ 'x', 'a', 'd', 'd', 'l', 9, 0, >+ /* 526 */ 'r', 'd', 's', 'e', 'e', 'd', 'l', 9, 0, >+ /* 535 */ 's', 'h', 'l', 'd', 'l', 9, 0, >+ /* 542 */ 'r', 'd', 'r', 'a', 'n', 'd', 'l', 9, 0, >+ /* 551 */ 's', 'h', 'r', 'd', 'l', 9, 0, >+ /* 558 */ 'c', 'm', 'o', 'v', 'a', 'e', 'l', 9, 0, >+ /* 567 */ 'c', 'm', 'o', 'v', 'b', 'e', 'l', 9, 0, >+ /* 576 */ 'c', 'm', 'o', 'v', 'g', 'e', 'l', 9, 0, >+ /* 585 */ 'c', 'm', 'o', 'v', 'l', 'e', 'l', 9, 0, >+ /* 594 */ 'c', 'm', 'o', 'v', 'n', 'e', 'l', 9, 0, >+ /* 603 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 614 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 625 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 636 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'l', 9, 0, >+ /* 647 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'l', 9, 0, >+ /* 657 */ 'c', 'm', 'o', 'v', 'e', 'l', 9, 0, >+ /* 665 */ 'b', 's', 'f', 'l', 9, 0, >+ /* 671 */ 'n', 'e', 'g', 'l', 9, 0, >+ /* 677 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'l', 9, 0, >+ /* 687 */ 'c', 'm', 'o', 'v', 'g', 'l', 9, 0, >+ /* 695 */ 'p', 'u', 's', 'h', 'l', 9, 0, >+ /* 702 */ 'b', 'z', 'h', 'i', 'l', 9, 0, >+ /* 709 */ 'b', 'l', 's', 'i', 'l', 9, 0, >+ /* 716 */ 'j', 'l', 9, 0, >+ /* 720 */ 'b', 'l', 's', 'm', 's', 'k', 'l', 9, 0, >+ /* 729 */ 's', 'a', 'l', 'l', 9, 0, >+ /* 735 */ 'r', 'c', 'l', 'l', 9, 0, >+ /* 741 */ 's', 'h', 'l', 'l', 9, 0, >+ /* 747 */ 'b', 'l', 'c', 'f', 'i', 'l', 'l', 9, 0, >+ /* 756 */ 'b', 'l', 's', 'f', 'i', 'l', 'l', 9, 0, >+ /* 765 */ 'l', 'c', 'a', 'l', 'l', 'l', 9, 0, >+ /* 773 */ 'r', 'o', 'l', 'l', 9, 0, >+ /* 779 */ 'l', 's', 'l', 'l', 9, 0, >+ /* 785 */ 'i', 'm', 'u', 'l', 'l', 9, 0, >+ /* 792 */ 'c', 'm', 'o', 'v', 'l', 'l', 9, 0, >+ /* 800 */ 'a', 'n', 'd', 'n', 'l', 9, 0, >+ /* 807 */ 'i', 'n', 'l', 9, 0, >+ /* 812 */ 'c', 'm', 'o', 'v', 'n', 'o', 'l', 9, 0, >+ /* 821 */ 'c', 'm', 'o', 'v', 'o', 'l', 9, 0, >+ /* 829 */ 'b', 's', 'w', 'a', 'p', 'l', 9, 0, >+ /* 837 */ 'p', 'd', 'e', 'p', 'l', 9, 0, >+ /* 844 */ 'c', 'm', 'p', 'l', 9, 0, >+ /* 850 */ 'l', 'j', 'm', 'p', 'l', 9, 0, >+ /* 857 */ 'c', 'm', 'o', 'v', 'n', 'p', 'l', 9, 0, >+ /* 866 */ 'n', 'o', 'p', 'l', 9, 0, >+ /* 872 */ 'p', 'o', 'p', 'l', 9, 0, >+ /* 878 */ 'a', 'r', 'p', 'l', 9, 0, >+ /* 884 */ 'c', 'm', 'o', 'v', 'p', 'l', 9, 0, >+ /* 892 */ 'l', 'a', 'r', 'l', 9, 0, >+ /* 898 */ 's', 'a', 'r', 'l', 9, 0, >+ /* 904 */ 'r', 'c', 'r', 'l', 9, 0, >+ /* 910 */ 's', 'h', 'r', 'l', 9, 0, >+ /* 916 */ 'r', 'o', 'r', 'l', 9, 0, >+ /* 922 */ 'x', 'o', 'r', 'l', 9, 0, >+ /* 928 */ 'b', 's', 'r', 'l', 9, 0, >+ /* 934 */ 'b', 'l', 's', 'r', 'l', 9, 0, >+ /* 941 */ 'b', 't', 'r', 'l', 9, 0, >+ /* 947 */ 's', 't', 'r', 'l', 9, 0, >+ /* 953 */ 'b', 'e', 'x', 't', 'r', 'l', 9, 0, >+ /* 961 */ 's', 'c', 'a', 's', 'l', 9, 0, >+ /* 968 */ 'm', 'o', 'v', 'a', 'b', 's', 'l', 9, 0, >+ /* 977 */ 'l', 'd', 's', 'l', 9, 0, >+ /* 983 */ 'l', 'o', 'd', 's', 'l', 9, 0, >+ /* 990 */ 'l', 'e', 's', 'l', 9, 0, >+ /* 996 */ 'l', 'f', 's', 'l', 9, 0, >+ /* 1002 */ 'l', 'g', 's', 'l', 9, 0, >+ /* 1008 */ 'c', 'm', 'o', 'v', 'n', 's', 'l', 9, 0, >+ /* 1017 */ 'c', 'm', 'p', 's', 'l', 9, 0, >+ /* 1024 */ 'l', 's', 's', 'l', 9, 0, >+ /* 1030 */ 'b', 't', 's', 'l', 9, 0, >+ /* 1036 */ 'o', 'u', 't', 's', 'l', 9, 0, >+ /* 1043 */ 'c', 'm', 'o', 'v', 's', 'l', 9, 0, >+ /* 1051 */ 'b', 't', 'l', 9, 0, >+ /* 1056 */ 'l', 'g', 'd', 't', 'l', 9, 0, >+ /* 1063 */ 's', 'g', 'd', 't', 'l', 9, 0, >+ /* 1070 */ 'l', 'i', 'd', 't', 'l', 9, 0, >+ /* 1077 */ 's', 'i', 'd', 't', 'l', 9, 0, >+ /* 1084 */ 's', 'l', 'd', 't', 'l', 9, 0, >+ /* 1091 */ 'l', 'r', 'e', 't', 'l', 9, 0, >+ /* 1098 */ 's', 'e', 't', 'l', 9, 0, >+ /* 1104 */ 'l', 'z', 'c', 'n', 't', 'l', 9, 0, >+ /* 1112 */ 't', 'z', 'c', 'n', 't', 'l', 9, 0, >+ /* 1120 */ 'n', 'o', 't', 'l', 9, 0, >+ /* 1126 */ 't', 'e', 's', 't', 'l', 9, 0, >+ /* 1133 */ 'p', 'e', 'x', 't', 'l', 9, 0, >+ /* 1140 */ 'i', 'd', 'i', 'v', 'l', 9, 0, >+ /* 1147 */ 'm', 'o', 'v', 'l', 9, 0, >+ /* 1153 */ 's', 'm', 's', 'w', 'l', 9, 0, >+ /* 1160 */ 'm', 'o', 'v', 's', 'w', 'l', 9, 0, >+ /* 1168 */ 'm', 'o', 'v', 'z', 'w', 'l', 9, 0, >+ /* 1176 */ 'a', 'd', 'c', 'x', 'l', 9, 0, >+ /* 1183 */ 's', 'h', 'l', 'x', 'l', 9, 0, >+ /* 1190 */ 'm', 'u', 'l', 'x', 'l', 9, 0, >+ /* 1197 */ 'a', 'd', 'o', 'x', 'l', 9, 0, >+ /* 1204 */ 's', 'a', 'r', 'x', 'l', 9, 0, >+ /* 1211 */ 's', 'h', 'r', 'x', 'l', 9, 0, >+ /* 1218 */ 'r', 'o', 'r', 'x', 'l', 9, 0, >+ /* 1225 */ 'a', 'a', 'm', 9, 0, >+ /* 1230 */ 'v', 'm', 'x', 'o', 'n', 9, 0, >+ /* 1237 */ 'j', 'o', 9, 0, >+ /* 1241 */ 'j', 'n', 'o', 9, 0, >+ /* 1246 */ 's', 'e', 't', 'n', 'o', 9, 0, >+ /* 1253 */ 's', 'e', 't', 'o', 9, 0, >+ /* 1259 */ 'j', 'p', 9, 0, >+ /* 1263 */ 'j', 'm', 'p', 9, 0, >+ /* 1268 */ 'j', 'n', 'p', 9, 0, >+ /* 1273 */ 's', 'e', 't', 'n', 'p', 9, 0, >+ /* 1280 */ 'n', 'o', 'p', 9, 0, >+ /* 1285 */ 'l', 'o', 'o', 'p', 9, 0, >+ /* 1291 */ 's', 'e', 't', 'p', 9, 0, >+ /* 1297 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0, >+ /* 1313 */ 'l', 'e', 'a', 'q', 9, 0, >+ /* 1319 */ 'c', 'm', 'o', 'v', 'a', 'q', 9, 0, >+ /* 1327 */ 's', 'b', 'b', 'q', 9, 0, >+ /* 1333 */ 'm', 'o', 'v', 's', 'b', 'q', 9, 0, >+ /* 1341 */ 's', 'u', 'b', 'q', 9, 0, >+ /* 1347 */ 'c', 'm', 'o', 'v', 'b', 'q', 9, 0, >+ /* 1355 */ 'm', 'o', 'v', 'z', 'b', 'q', 9, 0, >+ /* 1363 */ 'a', 'd', 'c', 'q', 9, 0, >+ /* 1369 */ 'd', 'e', 'c', 'q', 9, 0, >+ /* 1375 */ 'i', 'n', 'c', 'q', 9, 0, >+ /* 1381 */ 'b', 't', 'c', 'q', 9, 0, >+ /* 1387 */ 'v', 'm', 'r', 'e', 'a', 'd', 'q', 9, 0, >+ /* 1396 */ 'x', 'a', 'd', 'd', 'q', 9, 0, >+ /* 1403 */ 'r', 'd', 's', 'e', 'e', 'd', 'q', 9, 0, >+ /* 1412 */ 's', 'h', 'l', 'd', 'q', 9, 0, >+ /* 1419 */ 'r', 'd', 'r', 'a', 'n', 'd', 'q', 9, 0, >+ /* 1428 */ 's', 'h', 'r', 'd', 'q', 9, 0, >+ /* 1435 */ 'c', 'm', 'o', 'v', 'a', 'e', 'q', 9, 0, >+ /* 1444 */ 'c', 'm', 'o', 'v', 'b', 'e', 'q', 9, 0, >+ /* 1453 */ 'c', 'm', 'o', 'v', 'g', 'e', 'q', 9, 0, >+ /* 1462 */ 'c', 'm', 'o', 'v', 'l', 'e', 'q', 9, 0, >+ /* 1471 */ 'c', 'm', 'o', 'v', 'n', 'e', 'q', 9, 0, >+ /* 1480 */ 'r', 'd', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 1491 */ 'w', 'r', 'f', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 1502 */ 'r', 'd', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 1513 */ 'w', 'r', 'g', 's', 'b', 'a', 's', 'e', 'q', 9, 0, >+ /* 1524 */ 'v', 'm', 'w', 'r', 'i', 't', 'e', 'q', 9, 0, >+ /* 1534 */ 'x', 's', 'a', 'v', 'e', 'q', 9, 0, >+ /* 1542 */ 'c', 'm', 'o', 'v', 'e', 'q', 9, 0, >+ /* 1550 */ 'b', 's', 'f', 'q', 9, 0, >+ /* 1556 */ 'n', 'e', 'g', 'q', 9, 0, >+ /* 1562 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'q', 9, 0, >+ /* 1572 */ 'c', 'm', 'o', 'v', 'g', 'q', 9, 0, >+ /* 1580 */ 'p', 'u', 's', 'h', 'q', 9, 0, >+ /* 1587 */ 'b', 'z', 'h', 'i', 'q', 9, 0, >+ /* 1594 */ 'b', 'l', 's', 'i', 'q', 9, 0, >+ /* 1601 */ 'b', 'l', 's', 'm', 's', 'k', 'q', 9, 0, >+ /* 1610 */ 's', 'a', 'l', 'q', 9, 0, >+ /* 1616 */ 'r', 'c', 'l', 'q', 9, 0, >+ /* 1622 */ 's', 'h', 'l', 'q', 9, 0, >+ /* 1628 */ 'c', 'a', 'l', 'l', 'q', 9, 0, >+ /* 1635 */ 'r', 'o', 'l', 'q', 9, 0, >+ /* 1641 */ 'l', 's', 'l', 'q', 9, 0, >+ /* 1647 */ 'm', 'o', 'v', 's', 'l', 'q', 9, 0, >+ /* 1655 */ 'i', 'm', 'u', 'l', 'q', 9, 0, >+ /* 1662 */ 'c', 'm', 'o', 'v', 'l', 'q', 9, 0, >+ /* 1670 */ 'a', 'n', 'd', 'n', 'q', 9, 0, >+ /* 1677 */ 'c', 'm', 'o', 'v', 'n', 'o', 'q', 9, 0, >+ /* 1686 */ 'c', 'm', 'o', 'v', 'o', 'q', 9, 0, >+ /* 1694 */ 'b', 's', 'w', 'a', 'p', 'q', 9, 0, >+ /* 1702 */ 'p', 'd', 'e', 'p', 'q', 9, 0, >+ /* 1709 */ 'c', 'm', 'p', 'q', 9, 0, >+ /* 1715 */ 'c', 'm', 'o', 'v', 'n', 'p', 'q', 9, 0, >+ /* 1724 */ 'p', 'o', 'p', 'q', 9, 0, >+ /* 1730 */ 'c', 'm', 'o', 'v', 'p', 'q', 9, 0, >+ /* 1738 */ 'l', 'a', 'r', 'q', 9, 0, >+ /* 1744 */ 's', 'a', 'r', 'q', 9, 0, >+ /* 1750 */ 'r', 'c', 'r', 'q', 9, 0, >+ /* 1756 */ 's', 'h', 'r', 'q', 9, 0, >+ /* 1762 */ 'r', 'o', 'r', 'q', 9, 0, >+ /* 1768 */ 'x', 'r', 's', 't', 'o', 'r', 'q', 9, 0, >+ /* 1777 */ 'x', 'o', 'r', 'q', 9, 0, >+ /* 1783 */ 'b', 's', 'r', 'q', 9, 0, >+ /* 1789 */ 'b', 'l', 's', 'r', 'q', 9, 0, >+ /* 1796 */ 'b', 't', 'r', 'q', 9, 0, >+ /* 1802 */ 's', 't', 'r', 'q', 9, 0, >+ /* 1808 */ 'b', 'e', 'x', 't', 'r', 'q', 9, 0, >+ /* 1816 */ 's', 'c', 'a', 's', 'q', 9, 0, >+ /* 1823 */ 'm', 'o', 'v', 'a', 'b', 's', 'q', 9, 0, >+ /* 1832 */ 'l', 'o', 'd', 's', 'q', 9, 0, >+ /* 1839 */ 'l', 'f', 's', 'q', 9, 0, >+ /* 1845 */ 'l', 'g', 's', 'q', 9, 0, >+ /* 1851 */ 'c', 'm', 'o', 'v', 'n', 's', 'q', 9, 0, >+ /* 1860 */ 'c', 'm', 'p', 's', 'q', 9, 0, >+ /* 1867 */ 'l', 's', 's', 'q', 9, 0, >+ /* 1873 */ 'b', 't', 's', 'q', 9, 0, >+ /* 1879 */ 'c', 'm', 'o', 'v', 's', 'q', 9, 0, >+ /* 1887 */ 'b', 't', 'q', 9, 0, >+ /* 1892 */ 'l', 'g', 'd', 't', 'q', 9, 0, >+ /* 1899 */ 's', 'g', 'd', 't', 'q', 9, 0, >+ /* 1906 */ 'l', 'i', 'd', 't', 'q', 9, 0, >+ /* 1913 */ 's', 'i', 'd', 't', 'q', 9, 0, >+ /* 1920 */ 's', 'l', 'd', 't', 'q', 9, 0, >+ /* 1927 */ 'l', 'r', 'e', 't', 'q', 9, 0, >+ /* 1934 */ 'l', 'z', 'c', 'n', 't', 'q', 9, 0, >+ /* 1942 */ 't', 'z', 'c', 'n', 't', 'q', 9, 0, >+ /* 1950 */ 'n', 'o', 't', 'q', 9, 0, >+ /* 1956 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 'q', 9, 0, >+ /* 1967 */ 't', 'e', 's', 't', 'q', 9, 0, >+ /* 1974 */ 'p', 'e', 'x', 't', 'q', 9, 0, >+ /* 1981 */ 'i', 'd', 'i', 'v', 'q', 9, 0, >+ /* 1988 */ 'm', 'o', 'v', 'q', 9, 0, >+ /* 1994 */ 's', 'm', 's', 'w', 'q', 9, 0, >+ /* 2001 */ 'm', 'o', 'v', 's', 'w', 'q', 9, 0, >+ /* 2009 */ 'm', 'o', 'v', 'z', 'w', 'q', 9, 0, >+ /* 2017 */ 'a', 'd', 'c', 'x', 'q', 9, 0, >+ /* 2024 */ 's', 'h', 'l', 'x', 'q', 9, 0, >+ /* 2031 */ 'm', 'u', 'l', 'x', 'q', 9, 0, >+ /* 2038 */ 'a', 'd', 'o', 'x', 'q', 9, 0, >+ /* 2045 */ 's', 'a', 'r', 'x', 'q', 9, 0, >+ /* 2052 */ 's', 'h', 'r', 'x', 'q', 9, 0, >+ /* 2059 */ 'r', 'o', 'r', 'x', 'q', 9, 0, >+ /* 2066 */ 'v', 'm', 'c', 'l', 'e', 'a', 'r', 9, 0, >+ /* 2075 */ 'e', 'n', 't', 'e', 'r', 9, 0, >+ /* 2082 */ 'x', 'r', 's', 't', 'o', 'r', 9, 0, >+ /* 2090 */ 'v', 'e', 'r', 'r', 9, 0, >+ /* 2096 */ 'b', 'e', 'x', 't', 'r', 9, 0, >+ /* 2103 */ 'b', 'l', 'c', 's', 9, 0, >+ /* 2109 */ 'j', 's', 9, 0, >+ /* 2113 */ 'j', 'n', 's', 9, 0, >+ /* 2118 */ 's', 'e', 't', 'n', 's', 9, 0, >+ /* 2125 */ 's', 'e', 't', 's', 9, 0, >+ /* 2131 */ 'i', 'n', 't', 9, 0, >+ /* 2136 */ 'i', 'n', 'v', 'e', 'p', 't', 9, 0, >+ /* 2144 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', 9, 0, >+ /* 2154 */ 'v', 'm', 'p', 't', 'r', 's', 't', 9, 0, >+ /* 2163 */ 'l', 'e', 'a', 'w', 9, 0, >+ /* 2169 */ 'c', 'm', 'o', 'v', 'a', 'w', 9, 0, >+ /* 2177 */ 's', 'b', 'b', 'w', 9, 0, >+ /* 2183 */ 'm', 'o', 'v', 's', 'b', 'w', 9, 0, >+ /* 2191 */ 's', 'u', 'b', 'w', 9, 0, >+ /* 2197 */ 'c', 'm', 'o', 'v', 'b', 'w', 9, 0, >+ /* 2205 */ 'm', 'o', 'v', 'z', 'b', 'w', 9, 0, >+ /* 2213 */ 'a', 'd', 'c', 'w', 9, 0, >+ /* 2219 */ 'd', 'e', 'c', 'w', 9, 0, >+ /* 2225 */ 'i', 'n', 'c', 'w', 9, 0, >+ /* 2231 */ 'b', 't', 'c', 'w', 9, 0, >+ /* 2237 */ 'x', 'a', 'd', 'd', 'w', 9, 0, >+ /* 2244 */ 'r', 'd', 's', 'e', 'e', 'd', 'w', 9, 0, >+ /* 2253 */ 's', 'h', 'l', 'd', 'w', 9, 0, >+ /* 2260 */ 'r', 'd', 'r', 'a', 'n', 'd', 'w', 9, 0, >+ /* 2269 */ 's', 'h', 'r', 'd', 'w', 9, 0, >+ /* 2276 */ 'c', 'm', 'o', 'v', 'a', 'e', 'w', 9, 0, >+ /* 2285 */ 'c', 'm', 'o', 'v', 'b', 'e', 'w', 9, 0, >+ /* 2294 */ 'c', 'm', 'o', 'v', 'g', 'e', 'w', 9, 0, >+ /* 2303 */ 'c', 'm', 'o', 'v', 'l', 'e', 'w', 9, 0, >+ /* 2312 */ 'c', 'm', 'o', 'v', 'n', 'e', 'w', 9, 0, >+ /* 2321 */ 'c', 'm', 'o', 'v', 'e', 'w', 9, 0, >+ /* 2329 */ 'b', 's', 'f', 'w', 9, 0, >+ /* 2335 */ 'n', 'e', 'g', 'w', 9, 0, >+ /* 2341 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', 'w', 9, 0, >+ /* 2351 */ 'c', 'm', 'o', 'v', 'g', 'w', 9, 0, >+ /* 2359 */ 'p', 'u', 's', 'h', 'w', 9, 0, >+ /* 2366 */ 's', 'a', 'l', 'w', 9, 0, >+ /* 2372 */ 'r', 'c', 'l', 'w', 9, 0, >+ /* 2378 */ 's', 'h', 'l', 'w', 9, 0, >+ /* 2384 */ 'l', 'c', 'a', 'l', 'l', 'w', 9, 0, >+ /* 2392 */ 'r', 'o', 'l', 'w', 9, 0, >+ /* 2398 */ 'l', 's', 'l', 'w', 9, 0, >+ /* 2404 */ 'i', 'm', 'u', 'l', 'w', 9, 0, >+ /* 2411 */ 'c', 'm', 'o', 'v', 'l', 'w', 9, 0, >+ /* 2419 */ 'i', 'n', 'w', 9, 0, >+ /* 2424 */ 'c', 'm', 'o', 'v', 'n', 'o', 'w', 9, 0, >+ /* 2433 */ 'c', 'm', 'o', 'v', 'o', 'w', 9, 0, >+ /* 2441 */ 'c', 'm', 'p', 'w', 9, 0, >+ /* 2447 */ 'l', 'j', 'm', 'p', 'w', 9, 0, >+ /* 2454 */ 'c', 'm', 'o', 'v', 'n', 'p', 'w', 9, 0, >+ /* 2463 */ 'n', 'o', 'p', 'w', 9, 0, >+ /* 2469 */ 'p', 'o', 'p', 'w', 9, 0, >+ /* 2475 */ 'c', 'm', 'o', 'v', 'p', 'w', 9, 0, >+ /* 2483 */ 'l', 'a', 'r', 'w', 9, 0, >+ /* 2489 */ 's', 'a', 'r', 'w', 9, 0, >+ /* 2495 */ 'r', 'c', 'r', 'w', 9, 0, >+ /* 2501 */ 'v', 'e', 'r', 'w', 9, 0, >+ /* 2507 */ 's', 'h', 'r', 'w', 9, 0, >+ /* 2513 */ 'r', 'o', 'r', 'w', 9, 0, >+ /* 2519 */ 'x', 'o', 'r', 'w', 9, 0, >+ /* 2525 */ 'b', 's', 'r', 'w', 9, 0, >+ /* 2531 */ 'b', 't', 'r', 'w', 9, 0, >+ /* 2537 */ 'l', 't', 'r', 'w', 9, 0, >+ /* 2543 */ 's', 't', 'r', 'w', 9, 0, >+ /* 2549 */ 's', 'c', 'a', 's', 'w', 9, 0, >+ /* 2556 */ 'm', 'o', 'v', 'a', 'b', 's', 'w', 9, 0, >+ /* 2565 */ 'l', 'd', 's', 'w', 9, 0, >+ /* 2571 */ 'l', 'o', 'd', 's', 'w', 9, 0, >+ /* 2578 */ 'l', 'e', 's', 'w', 9, 0, >+ /* 2584 */ 'l', 'f', 's', 'w', 9, 0, >+ /* 2590 */ 'l', 'g', 's', 'w', 9, 0, >+ /* 2596 */ 'c', 'm', 'o', 'v', 'n', 's', 'w', 9, 0, >+ /* 2605 */ 'c', 'm', 'p', 's', 'w', 9, 0, >+ /* 2612 */ 'l', 's', 's', 'w', 9, 0, >+ /* 2618 */ 'b', 't', 's', 'w', 9, 0, >+ /* 2624 */ 'o', 'u', 't', 's', 'w', 9, 0, >+ /* 2631 */ 'c', 'm', 'o', 'v', 's', 'w', 9, 0, >+ /* 2639 */ 'b', 't', 'w', 9, 0, >+ /* 2644 */ 'l', 'g', 'd', 't', 'w', 9, 0, >+ /* 2651 */ 's', 'g', 'd', 't', 'w', 9, 0, >+ /* 2658 */ 'l', 'i', 'd', 't', 'w', 9, 0, >+ /* 2665 */ 's', 'i', 'd', 't', 'w', 9, 0, >+ /* 2672 */ 'l', 'l', 'd', 't', 'w', 9, 0, >+ /* 2679 */ 's', 'l', 'd', 't', 'w', 9, 0, >+ /* 2686 */ 'l', 'r', 'e', 't', 'w', 9, 0, >+ /* 2693 */ 'l', 'z', 'c', 'n', 't', 'w', 9, 0, >+ /* 2701 */ 't', 'z', 'c', 'n', 't', 'w', 9, 0, >+ /* 2709 */ 'n', 'o', 't', 'w', 9, 0, >+ /* 2715 */ 't', 'e', 's', 't', 'w', 9, 0, >+ /* 2722 */ 'i', 'd', 'i', 'v', 'w', 9, 0, >+ /* 2729 */ 'm', 'o', 'v', 'w', 9, 0, >+ /* 2735 */ 'l', 'm', 's', 'w', 'w', 9, 0, >+ /* 2742 */ 's', 'm', 's', 'w', 'w', 9, 0, >+ /* 2749 */ 'j', 'e', 'c', 'x', 'z', 9, 0, >+ /* 2756 */ 'j', 'c', 'x', 'z', 9, 0, >+ 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',', 32, 0, >+ /* 3103 */ 's', 't', 'o', 's', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 3115 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 3126 */ 'm', 'o', 'v', 'b', 9, '%', 'a', 'l', ',', 32, 0, >+ /* 3137 */ 's', 'a', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3148 */ 'r', 'c', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3159 */ 's', 'h', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3170 */ 'r', 'o', 'l', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3181 */ 's', 'a', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3192 */ 'r', 'c', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3203 */ 's', 'h', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3214 */ 'r', 'o', 'r', 'b', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3225 */ 's', 'h', 'l', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3237 */ 's', 'h', 'r', 'd', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3249 */ 's', 'a', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3260 */ 'r', 'c', 'l', 'l', 9, '%', 'c', 'l', ',', 32, 0, >+ /* 3271 */ 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'e', 'x', '6', '4', 0, >+ /* 4497 */ 'd', 'a', 't', 'a', '1', '6', 0, >+ /* 4504 */ 'x', 's', 'h', 'a', '2', '5', '6', 0, >+ /* 4512 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, >+ /* 4525 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, >+ /* 4532 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, >+ /* 4542 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0, >+ /* 4560 */ '#', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0, >+ /* 4576 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, >+ /* 4588 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, >+ /* 4603 */ 'a', 'a', 'a', 0, >+ /* 4607 */ 'd', 'a', 'a', 0, >+ /* 4611 */ 'u', 'd', '2', 'b', 0, >+ /* 4616 */ 'x', 'c', 'r', 'y', 'p', 't', 'e', 'c', 'b', 0, >+ /* 4626 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'f', 'b', 0, >+ /* 4636 */ 'x', 'c', 'r', 'y', 'p', 't', 'o', 'f', 'b', 0, >+ /* 4646 */ 'r', 'e', 'p', ';', 's', 't', 'o', 's', 'b', 0, >+ /* 4656 */ 'r', 'e', 'p', ';', 'm', 'o', 'v', 's', 'b', 0, >+ /* 4666 */ 'x', 'l', 'a', 't', 'b', 0, >+ /* 4672 */ 'c', 'l', 'a', 'c', 0, >+ /* 4677 */ 's', 't', 'a', 'c', 0, >+ /* 4682 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 'b', 'c', 0, >+ /* 4692 */ 'g', 'e', 't', 's', 'e', 'c', 0, >+ /* 4699 */ 's', 'a', 'l', 'c', 0, >+ /* 4704 */ 'c', 'l', 'c', 0, >+ /* 4708 */ 'c', 'm', 'c', 0, >+ /* 4712 */ 'r', 'd', 'p', 'm', 'c', 0, >+ /* 4718 */ 'v', 'm', 'f', 'u', 'n', 'c', 0, >+ /* 4725 */ 'r', 'd', 't', 's', 'c', 0, >+ /* 4731 */ 's', 't', 'c', 0, >+ /* 4735 */ 'c', 'p', 'u', 'i', 'd', 0, >+ /* 4741 */ 'c', 'l', 'd', 0, >+ /* 4745 */ 'c', 'l', 't', 'd', 0, >+ /* 4750 */ 's', 't', 'd', 0, >+ /* 4754 */ 'c', 'w', 't', 'd', 0, >+ /* 4759 */ 'w', 'b', 'i', 'n', 'v', 'd', 0, >+ /* 4766 */ 'v', 'm', 'r', 'e', 's', 'u', 'm', 'e', 0, >+ /* 4775 */ 'r', 'e', 'p', 'n', 'e', 0, >+ /* 4781 */ 'x', 's', 't', 'o', 'r', 'e', 0, >+ /* 4788 */ '#', 'S', 'E', 'H', '_', 'E', 'p', 'i', 'l', 'o', 'g', 'u', 'e', 0, >+ /* 4802 */ '#', 'S', 'E', 'H', '_', 'E', 'n', 'd', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', 0, >+ /* 4819 */ 'l', 'e', 'a', 'v', 'e', 0, >+ /* 4825 */ 'v', 'm', 'x', 'o', 'f', 'f', 0, >+ /* 4832 */ 'l', 'a', 'h', 'f', 0, >+ /* 4837 */ 's', 'a', 'h', 'f', 0, >+ /* 4842 */ 'v', 'm', 'l', 'a', 'u', 'n', 'c', 'h', 0, >+ /* 4851 */ 'c', 'l', 'g', 'i', 0, >+ /* 4856 */ 's', 't', 'g', 'i', 0, >+ /* 4861 */ 'c', 'l', 'i', 0, >+ /* 4865 */ 's', 't', 'i', 0, >+ /* 4869 */ '#', 32, 'w', 'i', 'n', '3', '2', 32, 'f', 'p', 't', 'o', 'u', 'i', 0, >+ /* 4884 */ 'l', 'o', 'c', 'k', 0, >+ /* 4889 */ 'i', 'n', 'b', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'l', 0, >+ /* 4902 */ 'p', 'u', 's', 'h', 'a', 'l', 0, >+ /* 4909 */ 'p', 'o', 'p', 'a', 'l', 0, >+ /* 4915 */ 'p', 'u', 's', 'h', 'f', 'l', 0, >+ /* 4922 */ 'p', 'o', 'p', 'f', 'l', 0, >+ /* 4928 */ 'v', 'm', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 4936 */ 'v', 'm', 'c', 'a', 'l', 'l', 0, >+ /* 4943 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 0, >+ /* 4951 */ 'r', 'e', 'p', ';', 's', 't', 'o', 's', 'l', 0, >+ /* 4961 */ 'r', 'e', 'p', ';', 'm', 'o', 'v', 's', 'l', 0, >+ /* 4971 */ 'i', 'r', 'e', 't', 'l', 0, >+ /* 4977 */ 'l', 'r', 'e', 't', 'l', 0, >+ /* 4983 */ 's', 'y', 's', 'r', 'e', 't', 'l', 0, >+ /* 4991 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'l', 0, >+ /* 5000 */ 'c', 'w', 't', 'l', 0, >+ /* 5005 */ 'm', 'o', 'n', 't', 'm', 'u', 'l', 0, >+ /* 5013 */ 'f', 's', 'e', 't', 'p', 'm', 0, >+ /* 5020 */ 'r', 's', 'm', 0, >+ /* 5024 */ '#', 32, 'd', 'y', 'n', 'a', 'm', 'i', 'c', 32, 's', 't', 'a', 'c', 'k', 32, 'a', 'l', 'l', 'o', 'c', 'a', 't', 'i', 'o', 'n', 0, >+ /* 5051 */ 'i', 'n', 't', 'o', 0, >+ /* 5056 */ 'c', 'q', 't', 'o', 0, >+ /* 5061 */ 'r', 'd', 't', 's', 'c', 'p', 0, >+ /* 5068 */ 'r', 'e', 'p', 0, >+ /* 5072 */ 'n', 'o', 'p', 0, >+ /* 5076 */ 'p', 'u', 's', 'h', 'f', 'q', 0, >+ /* 5083 */ 'p', 'o', 'p', 'f', 'q', 0, >+ /* 5089 */ 'r', 'e', 'p', ';', 's', 't', 'o', 's', 'q', 0, >+ /* 5099 */ 'r', 'e', 'p', ';', 'm', 'o', 'v', 's', 'q', 0, >+ /* 5109 */ 'i', 'r', 'e', 't', 'q', 0, >+ /* 5115 */ 'l', 'r', 'e', 't', 'q', 0, >+ /* 5121 */ 's', 'y', 's', 'r', 'e', 't', 'q', 0, >+ /* 5129 */ 's', 'y', 's', 'e', 'x', 'i', 't', 'q', 0, >+ /* 5138 */ 'c', 'l', 't', 'q', 0, >+ /* 5143 */ 's', 'y', 's', 'e', 'n', 't', 'e', 'r', 0, >+ /* 5152 */ 'r', 'd', 'm', 's', 'r', 0, >+ /* 5158 */ 'w', 'r', 'm', 's', 'r', 0, >+ /* 5164 */ 'x', 'c', 'r', 'y', 'p', 't', 'c', 't', 'r', 0, >+ /* 5174 */ 'a', 'a', 's', 0, >+ /* 5178 */ 'd', 'a', 's', 0, >+ /* 5182 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'c', 's', 0, >+ /* 5192 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'c', 's', 0, >+ /* 5202 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'd', 's', 0, >+ /* 5212 */ 'p', 'o', 'p', 'l', 9, '%', 'd', 's', 0, >+ /* 5221 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'd', 's', 0, >+ /* 5231 */ 'p', 'o', 'p', 'w', 9, '%', 'd', 's', 0, >+ /* 5240 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'e', 's', 0, >+ /* 5250 */ 'p', 'o', 'p', 'l', 9, '%', 'e', 's', 0, >+ /* 5259 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'e', 's', 0, >+ /* 5269 */ 'p', 'o', 'p', 'w', 9, '%', 'e', 's', 0, >+ /* 5278 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'f', 's', 0, >+ /* 5288 */ 'p', 'o', 'p', 'l', 9, '%', 'f', 's', 0, >+ /* 5297 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'f', 's', 0, >+ /* 5307 */ 'p', 'o', 'p', 'q', 9, '%', 'f', 's', 0, >+ /* 5316 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'f', 's', 0, >+ /* 5326 */ 'p', 'o', 'p', 'w', 9, '%', 'f', 's', 0, >+ /* 5335 */ 'p', 'u', 's', 'h', 'l', 9, '%', 'g', 's', 0, >+ /* 5345 */ 'p', 'o', 'p', 'l', 9, '%', 'g', 's', 0, >+ /* 5354 */ 'p', 'u', 's', 'h', 'q', 9, '%', 'g', 's', 0, >+ /* 5364 */ 'p', 'o', 'p', 'q', 9, '%', 'g', 's', 0, >+ /* 5373 */ 'p', 'u', 's', 'h', 'w', 9, '%', 'g', 's', 0, >+ /* 5383 */ 'p', 'o', 'p', 'w', 9, '%', 'g', 's', 0, >+ /* 5392 */ 's', 'w', 'a', 'p', 'g', 's', 0, >+ /* 5399 */ '#', 32, 'v', 'a', 'r', 'i', 'a', 'b', 'l', 'e', 32, 's', 'i', 'z', 'e', 'd', 32, 'a', 'l', 'l', 'o', 'c', 'a', 32, 'f', 'o', 'r', 32, 's', 'e', 'g', 'm', 'e', 'n', 't', 'e', 'd', 32, 's', 't', 'a', 'c', 'k', 's', 0, >+ /* 5444 */ 'p', 'u', 's', 'h', 'l', 9, '%', 's', 's', 0, >+ /* 5454 */ 'p', 'o', 'p', 'l', 9, '%', 's', 's', 0, >+ /* 5463 */ 'p', 'u', 's', 'h', 'w', 9, '%', 's', 's', 0, >+ /* 5473 */ 'p', 'o', 'p', 'w', 9, '%', 's', 's', 0, >+ /* 5482 */ 'c', 'l', 't', 's', 0, >+ /* 5487 */ 'h', 'l', 't', 0, >+ /* 5491 */ 'x', 'g', 'e', 't', 'b', 'v', 0, >+ /* 5498 */ 'x', 's', 'e', 't', 'b', 'v', 0, >+ /* 5505 */ 'p', 'u', 's', 'h', 'a', 'w', 0, >+ /* 5512 */ 'p', 'o', 'p', 'a', 'w', 0, >+ /* 5518 */ 'p', 'u', 's', 'h', 'f', 'w', 0, >+ /* 5525 */ 'p', 'o', 'p', 'f', 'w', 0, >+ /* 5531 */ 'r', 'e', 'p', ';', 's', 't', 'o', 's', 'w', 0, >+ /* 5541 */ 'r', 'e', 'p', ';', 'm', 'o', 'v', 's', 'w', 0, >+ /* 5551 */ 'c', 'b', 't', 'w', 0, >+ /* 5556 */ 'i', 'r', 'e', 't', 'w', 0, >+ /* 5562 */ 'l', 'r', 'e', 't', 'w', 0, >+ /* 5568 */ 'i', 'n', 'w', 9, '%', 'd', 'x', ',', 32, '%', 'a', 'x', 0, >+ /* 5581 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'e', 'a', 'x', 0, >+ /* 5593 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'e', 'a', 'x', 0, >+ /* 5605 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'e', 'a', 'x', 0, >+ /* 5616 */ 's', 'k', 'i', 'n', 'i', 't', 9, '%', 'e', 'a', 'x', 0, >+ /* 5628 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'c', 'x', ',', 32, '%', 'e', 'a', 'x', 0, >+ /* 5647 */ 'i', 'n', 'l', 9, '%', 'd', 'x', ',', 32, '%', 'e', 'a', 'x', 0, >+ /* 5661 */ 'v', 'm', 'l', 'o', 'a', 'd', 9, '%', 'r', 'a', 'x', 0, >+ /* 5673 */ 'v', 'm', 's', 'a', 'v', 'e', 9, '%', 'r', 'a', 'x', 0, >+ /* 5685 */ 'v', 'm', 'r', 'u', 'n', 9, '%', 'r', 'a', 'x', 0, >+ /* 5696 */ 'i', 'n', 'v', 'l', 'p', 'g', 'a', 9, '%', 'e', 'c', 'x', ',', 32, '%', 'r', 'a', 'x', 0, >+ /* 5715 */ 'o', 'u', 't', 'b', 9, '%', 'a', 'l', ',', 32, '%', 'd', 'x', 0, >+ /* 5729 */ 'o', 'u', 't', 'w', 9, '%', 'a', 'x', ',', 32, '%', 'd', 'x', 0, >+ /* 5743 */ 'o', 'u', 't', 'l', 9, '%', 'e', 'a', 'x', ',', 32, '%', 'd', 'x', 0, >+ }; >+#endif >+ >+ // Emit the opcode for the instruction. >+ uint32_t Bits = OpInfo[MCInst_getOpcode(MI)]; >+ // assert(Bits != 0 && "Cannot print this instruction."); >+#ifndef CAPSTONE_DIET >+ SStream_concat0(O, AsmStrs+(Bits & 8191)-1); >+#endif >+ >+ // Fragment 0 encoded into 6 bits for 40 unique commands. >+ //printf("Frag-0: %"PRIu64"\n", (Bits >> 13) & 63); >+ switch ((Bits >> 13) & 63) { >+ default: // unreachable. >+ case 0: >+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, AAA, AAS, ACQUIRE_MOV... >+ return; >+ break; >+ case 1: >+ // AAD8i8, AAM8i8, ADC16i16, ADC32i32, ADC64i32, ADC8i8, ADD16i16, ADD32i... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADC32mi, ADC32mi8, ADC32mr, ADC64mi32, ADC... >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rr, ADC16rr_REV, ADC32ri, ADC32ri8, ADC32rr, A... >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 4: >+ // ADC16rm, ADD16rm, AND16rm, CMOVA16rm, CMOVAE16rm, CMOVB16rm, CMOVBE16r... >+ printi16mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 5: >+ // ADC32rm, ADCX32rm, ADD32rm, AND32rm, ANDN32rm, CMOVA32rm, CMOVAE32rm, ... >+ printi32mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 6: >+ // ADC64rm, ADCX64rm, ADD64rm, AND64rm, ANDN64rm, CMOVA64rm, CMOVAE64rm, ... >+ printi64mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 7: >+ // ADC8rm, ADD8rm, AND8rm, OR8rm, SBB8rm, SUB8rm, XOR8rm >+ printi8mem(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 1, O); >+ return; >+ break; >+ case 8: >+ // ADOX32rm, BLCFILL32rm, BLCI32rm, BLCIC32rm, BLCMSK32rm, BLCS32rm, BLSF... >+ printi32mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // ADOX32rr, ADOX64rr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI... >+ printOperand(MI, 1, O); >+ break; >+ case 10: >+ // ADOX64rm, BLCFILL64rm, BLCI64rm, BLCIC64rm, BLCMSK64rm, BLCS64rm, BLSF... >+ printi64mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 11: >+ // BEXTR32rm, BEXTR64rm, BEXTRI32mi, BEXTRI64mi, BZHI32rm, BZHI64rm, IMUL... >+ printOperand(MI, 6, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 12: >+ // BSF16rm, BSR16rm, CMP16rm, LAR16rm, LAR32rm, LAR64rm, LEA16r, LSL16rm,... >+ printi16mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // CALL16m, DEC16m, DEC64_16m, DIV16m, IDIV16m, IMUL16m, INC16m, INC64_16... >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // CALL32m, DEC32m, DEC64_32m, DIV32m, IDIV32m, IMUL32m, INC32m, INC64_32... >+ printi32mem(MI, 0, O); >+ break; >+ case 15: >+ // CALL64m, CMPXCHG8B, DEC64m, DIV64m, IDIV64m, IMUL64m, INC64m, JMP64m, ... >+ printi64mem(MI, 0, O); >+ break; >+ case 16: >+ // CALL64pcrel32, CALLpcrel16, CALLpcrel32, EH_SjLj_Setup, JAE_1, JAE_2, ... >+ printPCRelImm(MI, 0, O); >+ break; >+ case 17: >+ // CMP8rm, MOV8rm, MOV8rm_NOREX, MOVSX16rm8, MOVSX32rm8, MOVSX64rm8, MOVZ... >+ printi8mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ break; >+ case 18: >+ // CMPSB, INSB, SCASB, STOSB >+ printDstIdx8(MI, 0, O); >+ break; >+ case 19: >+ // CMPSL, INSL, SCASL, STOSL >+ printDstIdx32(MI, 0, O); >+ break; >+ case 20: >+ // CMPSQ, SCASQ, STOSQ >+ printDstIdx64(MI, 0, O); >+ break; >+ case 21: >+ // CMPSW, INSW, SCASW, STOSW >+ printDstIdx16(MI, 0, O); >+ break; >+ case 22: >+ // CMPXCHG16B, LCMPXCHG16B >+ printi128mem(MI, 0, O); >+ return; >+ break; >+ case 23: >+ // DEC8m, DIV8m, IDIV8m, IMUL8m, INC8m, INVLPG, LOCK_DEC8m, LOCK_INC8m, M... >+ printi8mem(MI, 0, O); >+ return; >+ break; >+ case 24: >+ // FARCALL16m, FARCALL32m, FARCALL64, FARJMP16m, FARJMP32m, FARJMP64, LGD... >+ printopaquemem(MI, 0, O); >+ return; >+ break; >+ case 25: >+ // INVEPT32, INVEPT64, INVPCID32, INVPCID64, INVVPID32, INVVPID64 >+ printi128mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 26: >+ // LDS16rm, LDS32rm, LES16rm, LES32rm, LFS16rm, LFS32rm, LFS64rm, LGS16rm... >+ printopaquemem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 27: >+ // LODSB, OUTSB >+ printSrcIdx8(MI, 0, O); >+ break; >+ case 28: >+ // LODSL, OUTSL >+ printSrcIdx32(MI, 0, O); >+ break; >+ case 29: >+ // LODSQ >+ printSrcIdx64(MI, 0, O); >+ SStream_concat0(O, ", %rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 30: >+ // LODSW, OUTSW >+ printSrcIdx16(MI, 0, O); >+ break; >+ case 31: >+ // MOV16ao16, MOV16ao16_16, MOV16o16a, MOV16o16a_16, MOV64ao16, MOV64o16a >+ printMemOffs16(MI, 0, O); >+ break; >+ case 32: >+ // MOV32ao32, MOV32ao32_16, MOV32o32a, MOV32o32a_16, MOV64ao32, MOV64o32a >+ printMemOffs32(MI, 0, O); >+ break; >+ case 33: >+ // MOV64ao64, MOV64o64a >+ printMemOffs64(MI, 0, O); >+ break; >+ case 34: >+ // MOV64ao8, MOV64o8a, MOV8ao8, MOV8ao8_16, MOV8o8a, MOV8o8a_16 >+ printMemOffs8(MI, 0, O); >+ break; >+ case 35: >+ // MOVSB >+ printSrcIdx8(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx8(MI, 0, O); >+ return; >+ break; >+ case 36: >+ // MOVSL >+ printSrcIdx32(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx32(MI, 0, O); >+ return; >+ break; >+ case 37: >+ // MOVSQ >+ printSrcIdx64(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx64(MI, 0, O); >+ return; >+ break; >+ case 38: >+ // MOVSW >+ printSrcIdx16(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printDstIdx16(MI, 0, O); >+ return; >+ break; >+ case 39: >+ // SHLD16rri8, SHLD32rri8, SHLD64rri8, SHRD16rri8, SHRD32rri8, SHRD64rri8 >+ printOperand(MI, 3, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 1 encoded into 5 bits for 20 unique commands. >+ //printf("Frag-1: %"PRIu64"\n", (Bits >> 19) & 31); >+ switch ((Bits >> 19) & 31) { >+ default: // unreachable. >+ case 0: >+ // AAD8i8, AAM8i8, BSWAP32r, BSWAP64r, CALL16r, CALL32m, CALL32r, CALL64m... >+ return; >+ break; >+ case 1: >+ // ADC16i16, ADD16i16, AND16i16, CMP16i16, IN16ri, LODSW, MOV16o16a, MOV1... >+ SStream_concat0(O, ", %ax"); >+ op_addReg(MI, X86_REG_AX); >+ return; >+ break; >+ case 2: >+ // ADC16mi, ADC16mi8, ADC16mr, ADD16mi, ADD16mi8, ADD16mr, AND16mi, AND16... >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... >+ printOperand(MI, 1, O); >+ break; >+ case 4: >+ // ADC16rr_REV, ADC32rr_REV, ADC64rr_REV, ADC8rr_REV, ADCX32rm, ADCX32rr,... >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 5: >+ // ADC32i32, ADD32i32, AND32i32, CMP32i32, IN32ri, LODSL, MOV32o32a, MOV3... >+ SStream_concat0(O, ", %eax"); >+ op_addReg(MI, X86_REG_EAX); >+ return; >+ break; >+ case 6: >+ // ADC32mi, ADC32mi8, ADC32mr, ADD32mi, ADD32mi8, ADD32mr, AND32mi, AND32... >+ printi32mem(MI, 0, O); >+ return; >+ break; >+ case 7: >+ // ADC64i32, ADD64i32, AND64i32, CMP64i32, MOV64o64a, OR64i32, SBB64i32, ... >+ SStream_concat0(O, ", %rax"); >+ op_addReg(MI, X86_REG_RAX); >+ return; >+ break; >+ case 8: >+ // ADC64mi32, ADC64mi8, ADC64mr, ADD64mi32, ADD64mi8, ADD64mr, AND64mi32,... >+ printi64mem(MI, 0, O); >+ return; >+ break; >+ case 9: >+ // ADC8i8, ADD8i8, AND8i8, CMP8i8, IN8ri, LODSB, MOV64o8a, MOV8o8a, MOV8o... >+ SStream_concat0(O, ", %al"); >+ op_addReg(MI, X86_REG_AL); >+ return; >+ break; >+ case 10: >+ // ADC8mi, ADC8mr, ADD8mi, ADD8mr, AND8mi, AND8mr, CMP8mi, CMP8mr, CMPXCH... >+ printi8mem(MI, 0, O); >+ break; >+ case 11: >+ // ADOX32rr, ADOX64rr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI... >+ SStream_concat0(O, ", "); >+ break; >+ case 12: >+ // BEXTR32rm, BEXTRI32mi, BZHI32rm, IMUL32rmi, IMUL32rmi8, RORX32mi, SARX... >+ printi32mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 13: >+ // BEXTR64rm, BEXTRI64mi, BZHI64rm, IMUL64rmi32, IMUL64rmi8, RORX64mi, SA... >+ printi64mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // FARCALL16i, FARCALL32i, FARJMP16i, FARJMP32i >+ SStream_concat0(O, ":"); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 15: >+ // IMUL16rmi, IMUL16rmi8 >+ printi16mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 16: >+ // MOV8rm_NOREX >+ return; >+ break; >+ case 17: >+ // OUTSB, OUTSL, OUTSW >+ SStream_concat0(O, ", %dx"); >+ op_addReg(MI, X86_REG_DX); >+ return; >+ break; >+ case 18: >+ // SHLD16mri8, SHLD32mri8, SHLD64mri8, SHRD16mri8, SHRD32mri8, SHRD64mri8 >+ printOperand(MI, 5, O); >+ SStream_concat0(O, ", "); >+ break; >+ case 19: >+ // TAILJMPd, TAILJMPd64, TAILJMPm, TAILJMPm64, TAILJMPr64 >+ return; >+ break; >+ } >+ >+ >+ // Fragment 2 encoded into 5 bits for 18 unique commands. >+ //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); >+ switch ((Bits >> 24) & 31) { >+ default: // unreachable. >+ case 0: >+ // ADC16ri, ADC16ri8, ADC16rm, ADC16rr, ADC32ri, ADC32ri8, ADC32rm, ADC32... >+ return; >+ break; >+ case 1: >+ // ADOX32rr, ADOX64rr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI... >+ printOperand(MI, 0, O); >+ break; >+ case 2: >+ // ANDN32rm, ANDN32rr, ANDN64rm, ANDN64rr, BEXTR32rr, BEXTR64rr, BEXTRI32... >+ SStream_concat0(O, ", "); >+ printOperand(MI, 0, O); >+ return; >+ break; >+ case 3: >+ // CMPSB >+ printSrcIdx8(MI, 1, O); >+ return; >+ break; >+ case 4: >+ // CMPSL >+ printSrcIdx32(MI, 1, O); >+ return; >+ break; >+ case 5: >+ // CMPSQ >+ printSrcIdx64(MI, 1, O); >+ return; >+ break; >+ case 6: >+ // CMPSW >+ printSrcIdx16(MI, 1, O); >+ return; >+ break; >+ case 7: >+ // ENTER, NOOP19rr, SEH_SaveReg, SEH_SaveXMM, SEH_SetFrame, VASTART_SAVE_... >+ printOperand(MI, 1, O); >+ break; >+ case 8: >+ // LXADD16, XCHG16rm >+ printi16mem(MI, 2, O); >+ return; >+ break; >+ case 9: >+ // LXADD32, XCHG32rm >+ printi32mem(MI, 2, O); >+ return; >+ break; >+ case 10: >+ // LXADD64, XCHG64rm >+ printi64mem(MI, 2, O); >+ return; >+ break; >+ case 11: >+ // LXADD8, XCHG8rm >+ printi8mem(MI, 2, O); >+ return; >+ break; >+ case 12: >+ // MOV8mr_NOREX >+ return; >+ break; >+ case 13: >+ // SHLD16mri8, SHRD16mri8 >+ printi16mem(MI, 0, O); >+ return; >+ break; >+ case 14: >+ // SHLD32mri8, SHRD32mri8 >+ printi32mem(MI, 0, O); >+ return; >+ break; >+ case 15: >+ // SHLD64mri8, SHRD64mri8 >+ printi64mem(MI, 0, O); >+ return; >+ break; >+ case 16: >+ // VAARG_64 >+ printi8mem(MI, 1, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 6, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 7, O); >+ SStream_concat0(O, ", "); >+ printOperand(MI, 8, O); >+ return; >+ break; >+ case 17: >+ // XCHG16rr, XCHG32rr, XCHG64rr, XCHG8rr >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+ >+ >+ // Fragment 3 encoded into 2 bits for 3 unique commands. >+ //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 3); >+ switch ((Bits >> 29) & 3) { >+ default: // unreachable. >+ case 0: >+ // ADOX32rr, ADOX64rr, ARPL16rr, BLCFILL32rr, BLCFILL64rr, BLCI32rr, BLCI... >+ return; >+ break; >+ case 1: >+ // MOV8rr_NOREX >+ return; >+ break; >+ case 2: >+ // VASTART_SAVE_XMM_REGS >+ SStream_concat0(O, ", "); >+ printOperand(MI, 2, O); >+ return; >+ break; >+ } >+} >+ >+ >+/// getRegisterName - This method is automatically generated by tblgen >+/// from the register set description. This returns the assembler name >+/// for the specified register. >+static const char *getRegisterName(unsigned RegNo) >+{ >+ // assert(RegNo && RegNo < 234 && "Invalid register number!"); >+ >+#ifndef CAPSTONE_DIET >+ static const char AsmStrs[] = { >+ /* 0 */ 's', 't', '(', '0', ')', 0, >+ /* 6 */ 's', 't', '(', '1', ')', 0, >+ /* 12 */ 's', 't', '(', '2', ')', 0, >+ /* 18 */ 's', 't', '(', '3', ')', 0, >+ /* 24 */ 's', 't', '(', '4', ')', 0, >+ /* 30 */ 's', 't', '(', '5', ')', 0, >+ /* 36 */ 's', 't', '(', '6', ')', 0, >+ /* 42 */ 's', 't', '(', '7', ')', 0, >+ /* 48 */ 'x', 'm', 'm', '1', '0', 0, >+ /* 54 */ 'y', 'm', 'm', '1', '0', 0, >+ /* 60 */ 'z', 'm', 'm', '1', '0', 0, >+ /* 66 */ 'c', 'r', '1', '0', 0, >+ /* 71 */ 'x', 'm', 'm', '2', '0', 0, >+ /* 77 */ 'y', 'm', 'm', '2', '0', 0, >+ /* 83 */ 'z', 'm', 'm', '2', '0', 0, >+ /* 89 */ 'x', 'm', 'm', '3', '0', 0, >+ /* 95 */ 'y', 'm', 'm', '3', '0', 0, >+ /* 101 */ 'z', 'm', 'm', '3', '0', 0, >+ /* 107 */ 'k', '0', 0, >+ /* 110 */ 'x', 'm', 'm', '0', 0, >+ /* 115 */ 'y', 'm', 'm', '0', 0, >+ /* 120 */ 'z', 'm', 'm', '0', 0, >+ /* 125 */ 'f', 'p', '0', 0, >+ /* 129 */ 'c', 'r', '0', 0, >+ /* 133 */ 'd', 'r', '0', 0, >+ /* 137 */ 'x', 'm', 'm', '1', '1', 0, >+ /* 143 */ 'y', 'm', 'm', '1', '1', 0, >+ /* 149 */ 'z', 'm', 'm', '1', '1', 0, >+ /* 155 */ 'c', 'r', '1', '1', 0, >+ /* 160 */ 'x', 'm', 'm', '2', '1', 0, >+ /* 166 */ 'y', 'm', 'm', '2', '1', 0, >+ /* 172 */ 'z', 'm', 'm', '2', '1', 0, >+ /* 178 */ 'x', 'm', 'm', '3', '1', 0, >+ /* 184 */ 'y', 'm', 'm', '3', '1', 0, >+ /* 190 */ 'z', 'm', 'm', '3', '1', 0, >+ /* 196 */ 'k', '1', 0, >+ /* 199 */ 'x', 'm', 'm', '1', 0, >+ /* 204 */ 'y', 'm', 'm', '1', 0, >+ /* 209 */ 'z', 'm', 'm', '1', 0, >+ /* 214 */ 'f', 'p', '1', 0, >+ /* 218 */ 'c', 'r', '1', 0, >+ /* 222 */ 'd', 'r', '1', 0, >+ /* 226 */ 'x', 'm', 'm', '1', '2', 0, >+ /* 232 */ 'y', 'm', 'm', '1', '2', 0, >+ /* 238 */ 'z', 'm', 'm', '1', '2', 0, >+ /* 244 */ 'c', 'r', '1', '2', 0, >+ /* 249 */ 'x', 'm', 'm', '2', '2', 0, >+ /* 255 */ 'y', 'm', 'm', '2', '2', 0, >+ /* 261 */ 'z', 'm', 'm', '2', '2', 0, >+ /* 267 */ 'k', '2', 0, >+ /* 270 */ 'x', 'm', 'm', '2', 0, >+ /* 275 */ 'y', 'm', 'm', '2', 0, >+ /* 280 */ 'z', 'm', 'm', '2', 0, >+ /* 285 */ 'f', 'p', '2', 0, >+ /* 289 */ 'c', 'r', '2', 0, >+ /* 293 */ 'd', 'r', '2', 0, >+ /* 297 */ 'x', 'm', 'm', '1', '3', 0, >+ /* 303 */ 'y', 'm', 'm', '1', '3', 0, >+ /* 309 */ 'z', 'm', 'm', '1', '3', 0, >+ /* 315 */ 'c', 'r', '1', '3', 0, >+ /* 320 */ 'x', 'm', 'm', '2', '3', 0, >+ /* 326 */ 'y', 'm', 'm', '2', '3', 0, >+ /* 332 */ 'z', 'm', 'm', '2', '3', 0, >+ /* 338 */ 'k', '3', 0, >+ /* 341 */ 'x', 'm', 'm', '3', 0, >+ /* 346 */ 'y', 'm', 'm', '3', 0, >+ /* 351 */ 'z', 'm', 'm', '3', 0, >+ /* 356 */ 'f', 'p', '3', 0, >+ /* 360 */ 'c', 'r', '3', 0, >+ /* 364 */ 'd', 'r', '3', 0, >+ /* 368 */ 'x', 'm', 'm', '1', '4', 0, >+ /* 374 */ 'y', 'm', 'm', '1', '4', 0, >+ /* 380 */ 'z', 'm', 'm', '1', '4', 0, >+ /* 386 */ 'c', 'r', '1', '4', 0, >+ /* 391 */ 'x', 'm', 'm', '2', '4', 0, >+ /* 397 */ 'y', 'm', 'm', '2', '4', 0, >+ /* 403 */ 'z', 'm', 'm', '2', '4', 0, >+ /* 409 */ 'k', '4', 0, >+ /* 412 */ 'x', 'm', 'm', '4', 0, >+ /* 417 */ 'y', 'm', 'm', '4', 0, >+ /* 422 */ 'z', 'm', 'm', '4', 0, >+ /* 427 */ 'f', 'p', '4', 0, >+ /* 431 */ 'c', 'r', '4', 0, >+ /* 435 */ 'd', 'r', '4', 0, >+ /* 439 */ 'x', 'm', 'm', '1', '5', 0, >+ /* 445 */ 'y', 'm', 'm', '1', '5', 0, >+ /* 451 */ 'z', 'm', 'm', '1', '5', 0, >+ /* 457 */ 'c', 'r', '1', '5', 0, >+ /* 462 */ 'x', 'm', 'm', '2', '5', 0, >+ /* 468 */ 'y', 'm', 'm', '2', '5', 0, >+ /* 474 */ 'z', 'm', 'm', '2', '5', 0, >+ /* 480 */ 'k', '5', 0, >+ /* 483 */ 'x', 'm', 'm', '5', 0, >+ /* 488 */ 'y', 'm', 'm', '5', 0, >+ /* 493 */ 'z', 'm', 'm', '5', 0, >+ /* 498 */ 'f', 'p', '5', 0, >+ /* 502 */ 'c', 'r', '5', 0, >+ /* 506 */ 'd', 'r', '5', 0, >+ /* 510 */ 'x', 'm', 'm', '1', '6', 0, >+ /* 516 */ 'y', 'm', 'm', '1', '6', 0, >+ /* 522 */ 'z', 'm', 'm', '1', '6', 0, >+ /* 528 */ 'x', 'm', 'm', '2', '6', 0, >+ /* 534 */ 'y', 'm', 'm', '2', '6', 0, >+ /* 540 */ 'z', 'm', 'm', '2', '6', 0, >+ /* 546 */ 'k', '6', 0, >+ /* 549 */ 'x', 'm', 'm', '6', 0, >+ /* 554 */ 'y', 'm', 'm', '6', 0, >+ /* 559 */ 'z', 'm', 'm', '6', 0, >+ /* 564 */ 'f', 'p', '6', 0, >+ /* 568 */ 'c', 'r', '6', 0, >+ /* 572 */ 'd', 'r', '6', 0, >+ /* 576 */ 'x', 'm', 'm', '1', '7', 0, >+ /* 582 */ 'y', 'm', 'm', '1', '7', 0, >+ /* 588 */ 'z', 'm', 'm', '1', '7', 0, >+ /* 594 */ 'x', 'm', 'm', '2', '7', 0, >+ /* 600 */ 'y', 'm', 'm', '2', '7', 0, >+ /* 606 */ 'z', 'm', 'm', '2', '7', 0, >+ /* 612 */ 'k', '7', 0, >+ /* 615 */ 'x', 'm', 'm', '7', 0, >+ /* 620 */ 'y', 'm', 'm', '7', 0, >+ /* 625 */ 'z', 'm', 'm', '7', 0, >+ /* 630 */ 'f', 'p', '7', 0, >+ /* 634 */ 'c', 'r', '7', 0, >+ /* 638 */ 'd', 'r', '7', 0, >+ /* 642 */ 'x', 'm', 'm', '1', '8', 0, >+ /* 648 */ 'y', 'm', 'm', '1', '8', 0, >+ /* 654 */ 'z', 'm', 'm', '1', '8', 0, >+ /* 660 */ 'x', 'm', 'm', '2', '8', 0, >+ /* 666 */ 'y', 'm', 'm', '2', '8', 0, >+ /* 672 */ 'z', 'm', 'm', '2', '8', 0, >+ /* 678 */ 'x', 'm', 'm', '8', 0, >+ /* 683 */ 'y', 'm', 'm', '8', 0, >+ /* 688 */ 'z', 'm', 'm', '8', 0, >+ /* 693 */ 'c', 'r', '8', 0, >+ /* 697 */ 'x', 'm', 'm', '1', '9', 0, >+ /* 703 */ 'y', 'm', 'm', '1', '9', 0, >+ /* 709 */ 'z', 'm', 'm', '1', '9', 0, >+ /* 715 */ 'x', 'm', 'm', '2', '9', 0, >+ /* 721 */ 'y', 'm', 'm', '2', '9', 0, >+ /* 727 */ 'z', 'm', 'm', '2', '9', 0, >+ /* 733 */ 'x', 'm', 'm', '9', 0, >+ /* 738 */ 'y', 'm', 'm', '9', 0, >+ /* 743 */ 'z', 'm', 'm', '9', 0, >+ /* 748 */ 'c', 'r', '9', 0, >+ /* 752 */ 'r', '1', '0', 'b', 0, >+ /* 757 */ 'r', '1', '1', 'b', 0, >+ /* 762 */ 'r', '1', '2', 'b', 0, >+ /* 767 */ 'r', '1', '3', 'b', 0, >+ /* 772 */ 'r', '1', '4', 'b', 0, >+ /* 777 */ 'r', '1', '5', 'b', 0, >+ /* 782 */ 'r', '8', 'b', 0, >+ /* 786 */ 'r', '9', 'b', 0, >+ /* 790 */ 'r', '1', '0', 'd', 0, >+ /* 795 */ 'r', '1', '1', 'd', 0, >+ /* 800 */ 'r', '1', '2', 'd', 0, >+ /* 805 */ 'r', '1', '3', 'd', 0, >+ /* 810 */ 'r', '1', '4', 'd', 0, >+ /* 815 */ 'r', '1', '5', 'd', 0, >+ /* 820 */ 'r', '8', 'd', 0, >+ /* 824 */ 'r', '9', 'd', 0, >+ /* 828 */ 'a', 'h', 0, >+ /* 831 */ 'b', 'h', 0, >+ /* 834 */ 'c', 'h', 0, >+ /* 837 */ 'd', 'h', 0, >+ /* 840 */ 'e', 'd', 'i', 0, >+ /* 844 */ 'r', 'd', 'i', 0, >+ /* 848 */ 'e', 's', 'i', 0, >+ /* 852 */ 'r', 's', 'i', 0, >+ /* 856 */ 'a', 'l', 0, >+ /* 859 */ 'b', 'l', 0, >+ /* 862 */ 'c', 'l', 0, >+ /* 865 */ 'd', 'l', 0, >+ /* 868 */ 'd', 'i', 'l', 0, >+ /* 872 */ 's', 'i', 'l', 0, >+ /* 876 */ 'b', 'p', 'l', 0, >+ /* 880 */ 's', 'p', 'l', 0, >+ /* 884 */ 'e', 'b', 'p', 0, >+ /* 888 */ 'r', 'b', 'p', 0, >+ /* 892 */ 'e', 'i', 'p', 0, >+ /* 896 */ 'r', 'i', 'p', 0, >+ /* 900 */ 'e', 's', 'p', 0, >+ /* 904 */ 'r', 's', 'p', 0, >+ /* 908 */ 'c', 's', 0, >+ /* 911 */ 'd', 's', 0, >+ /* 914 */ 'e', 's', 0, >+ /* 917 */ 'f', 's', 0, >+ /* 920 */ 'f', 'l', 'a', 'g', 's', 0, >+ /* 926 */ 's', 's', 0, >+ /* 929 */ 'r', '1', '0', 'w', 0, >+ /* 934 */ 'r', '1', '1', 'w', 0, >+ /* 939 */ 'r', '1', '2', 'w', 0, >+ /* 944 */ 'r', '1', '3', 'w', 0, >+ /* 949 */ 'r', '1', '4', 'w', 0, >+ /* 954 */ 'r', '1', '5', 'w', 0, >+ /* 959 */ 'r', '8', 'w', 0, >+ /* 963 */ 'r', '9', 'w', 0, >+ /* 967 */ 'f', 'p', 's', 'w', 0, >+ /* 972 */ 'e', 'a', 'x', 0, >+ /* 976 */ 'r', 'a', 'x', 0, >+ /* 980 */ 'e', 'b', 'x', 0, >+ /* 984 */ 'r', 'b', 'x', 0, >+ /* 988 */ 'e', 'c', 'x', 0, >+ /* 992 */ 'r', 'c', 'x', 0, >+ /* 996 */ 'e', 'd', 'x', 0, >+ /* 1000 */ 'r', 'd', 'x', 0, >+ /* 1004 */ 'e', 'i', 'z', 0, >+ /* 1008 */ 'r', 'i', 'z', 0, >+ }; >+ >+ static const uint32_t RegAsmOffset[] = { >+ 828, 856, 973, 831, 859, 885, 876, 981, 834, 862, 908, 989, 837, 841, >+ 868, 865, 911, 997, 972, 884, 980, 988, 840, 996, 920, 892, 1004, 914, >+ 848, 900, 967, 917, 923, 893, 976, 888, 984, 992, 844, 1000, 896, 1008, >+ 852, 904, 849, 872, 901, 880, 926, 129, 218, 289, 360, 431, 502, 568, >+ 634, 693, 748, 66, 155, 244, 315, 386, 457, 133, 222, 293, 364, 435, >+ 506, 572, 638, 125, 214, 285, 356, 427, 498, 564, 630, 107, 196, 267, >+ 338, 409, 480, 546, 612, 111, 200, 271, 342, 413, 484, 550, 616, 694, >+ 749, 67, 156, 245, 316, 387, 458, 0, 6, 12, 18, 24, 30, 36, >+ 42, 110, 199, 270, 341, 412, 483, 549, 615, 678, 733, 48, 137, 226, >+ 297, 368, 439, 510, 576, 642, 697, 71, 160, 249, 320, 391, 462, 528, >+ 594, 660, 715, 89, 178, 115, 204, 275, 346, 417, 488, 554, 620, 683, >+ 738, 54, 143, 232, 303, 374, 445, 516, 582, 648, 703, 77, 166, 255, >+ 326, 397, 468, 534, 600, 666, 721, 95, 184, 120, 209, 280, 351, 422, >+ 493, 559, 625, 688, 743, 60, 149, 238, 309, 380, 451, 522, 588, 654, >+ 709, 83, 172, 261, 332, 403, 474, 540, 606, 672, 727, 101, 190, 782, >+ 786, 752, 757, 762, 767, 772, 777, 820, 824, 790, 795, 800, 805, 810, >+ 815, 959, 963, 929, 934, 939, 944, 949, 954, >+ }; >+ >+ //int i; >+ //for (i = 0; i < sizeof(RegAsmOffset)/4; i++) >+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1); >+ //printf("*************************\n"); >+ return AsmStrs+RegAsmOffset[RegNo-1]; >+#else >+ return NULL; >+#endif >+} >+ >+#ifdef PRINT_ALIAS_INSTR >+#undef PRINT_ALIAS_INSTR >+ >+static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, >+ unsigned PrintMethodIdx, SStream *OS) >+{ >+} >+ >+static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) >+{ >+ #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) >+ const char *AsmString; >+ char *tmp, *AsmMnem, *AsmOps, *c; >+ int OpIdx, PrintMethodIdx; >+ switch (MCInst_getOpcode(MI)) { >+ default: return NULL; >+ case X86_AAD8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAD8i8 10) >+ AsmString = "aad"; >+ break; >+ } >+ return NULL; >+ case X86_AAM8i8: >+ if (MCInst_getNumOperands(MI) == 1 && >+ MCOperand_isImm(MCInst_getOperand(MI, 0)) && >+ MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) { >+ // (AAM8i8 10) >+ AsmString = "aam"; >+ break; >+ } >+ return NULL; >+ case X86_XSTORE: >+ if (MCInst_getNumOperands(MI) == 0) { >+ // (XSTORE) >+ AsmString = "xstorerng"; >+ break; >+ } >+ return NULL; >+ } >+ >+ tmp = cs_strdup(AsmString); >+ AsmMnem = tmp; >+ for(AsmOps = tmp; *AsmOps; AsmOps++) { >+ if (*AsmOps == ' ' || *AsmOps == '\t') { >+ *AsmOps = '\0'; >+ AsmOps++; >+ break; >+ } >+ } >+ SStream_concat0(OS, AsmMnem); >+ if (*AsmOps) { >+ SStream_concat0(OS, "\t"); >+ for (c = AsmOps; *c; c++) { >+ if (*c == '$') { >+ c += 1; >+ if (*c == (char)0xff) { >+ c += 1; >+ OpIdx = *c - 1; >+ c += 1; >+ PrintMethodIdx = *c - 1; >+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); >+ } else >+ printOperand(MI, *c - 1, OS); >+ } else { >+ SStream_concat(OS, "%c", *c); >+ } >+ } >+ } >+ return tmp; >+} >+ >+#endif // PRINT_ALIAS_INSTR >diff --git a/Source/ThirdParty/capstone/Source/arch/X86/X86GenDisassemblerTables.inc b/Source/ThirdParty/capstone/Source/arch/X86/X86GenDisassemblerTables.inc >new file mode 100644 >index 0000000000000000000000000000000000000000..f9c855cb08f796cf405527411e1939aaf370ec9a >--- /dev/null >+++ b/Source/ThirdParty/capstone/Source/arch/X86/X86GenDisassemblerTables.inc >@@ -0,0 +1,374257 @@ >+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ >+|* *| >+|* * X86 Disassembler *| >+|* *| >+|* Automatically generated file, do not edit! *| >+|* *| >+\*===----------------------------------------------------------------------===*/ >+ >+/* Capstone Disassembly Engine, http://www.capstone-engine.org */ >+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ >+ >+static const struct OpcodeDecision emptyTable = { >+ /* IC_OF */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+}; >+ >+static const struct OperandSpecifier x86OperandSets[][6] = { >+ { /* 0 */ >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 1 */ >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 2 */ >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 3 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 4 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 5 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 6 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 7 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 8 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 9 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 10 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 11 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 12 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 13 */ >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 14 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 15 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 16 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 17 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 18 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 19 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 20 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 21 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 22 */ >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 23 */ >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 24 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 25 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 26 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 27 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 28 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 29 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 30 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 31 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 32 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 33 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 34 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 35 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 36 */ >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 37 */ >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 38 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 39 */ >+ { ENCODING_FP, TYPE_ST }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 40 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 41 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 42 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 43 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 44 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 45 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 46 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 47 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 48 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 49 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 50 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 51 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 52 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_R16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 53 */ >+ { ENCODING_RM, TYPE_R16 }, >+ { ENCODING_REG, TYPE_R16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 54 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 55 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 56 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 57 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 58 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 59 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 60 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 61 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 62 */ >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 63 */ >+ { ENCODING_VVVV, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 64 */ >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 65 */ >+ { ENCODING_VVVV, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 66 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 67 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 68 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 69 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 70 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_Rv, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 71 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RO, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 72 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 73 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 74 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 75 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 76 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 77 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 78 */ >+ { ENCODING_ID, TYPE_REL64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 79 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 80 */ >+ { ENCODING_IW, TYPE_REL16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 81 */ >+ { ENCODING_ID, TYPE_REL32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 82 */ >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 83 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 84 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_ID, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 85 */ >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 86 */ >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 87 */ >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 88 */ >+ { ENCODING_REG, TYPE_R8 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 89 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 90 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 91 */ >+ { ENCODING_DI, TYPE_DSTIDX8 }, >+ { ENCODING_SI, TYPE_SRCIDX8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 92 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 93 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 94 */ >+ { ENCODING_DI, TYPE_DSTIDX32 }, >+ { ENCODING_SI, TYPE_SRCIDX32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 95 */ >+ { ENCODING_DI, TYPE_DSTIDX64 }, >+ { ENCODING_SI, TYPE_SRCIDX64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 96 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 97 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM3 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 98 */ >+ { ENCODING_DI, TYPE_DSTIDX16 }, >+ { ENCODING_SI, TYPE_SRCIDX16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 99 */ >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 100 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 101 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 102 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 103 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 104 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 105 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 106 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 107 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 108 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 109 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 110 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 111 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 112 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 113 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 114 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 115 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 116 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 117 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 118 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 119 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 120 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 121 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 122 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 123 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 124 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 125 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 126 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 127 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 128 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 129 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 130 */ >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 131 */ >+ { ENCODING_IW, TYPE_IMM16 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 132 */ >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 133 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 134 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 135 */ >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 136 */ >+ { ENCODING_RM, TYPE_M1616 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 137 */ >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_IW, TYPE_IMM16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 138 */ >+ { ENCODING_RM, TYPE_M1632 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 139 */ >+ { ENCODING_RM, TYPE_M1664 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 140 */ >+ { ENCODING_RM, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 141 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 142 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 143 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 144 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 145 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 146 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 147 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 148 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 149 */ >+ { ENCODING_DI, TYPE_DSTIDX8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 150 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 151 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 152 */ >+ { ENCODING_DI, TYPE_DSTIDX32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 153 */ >+ { ENCODING_DI, TYPE_DSTIDX16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 154 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 155 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 156 */ >+ { ENCODING_IB, TYPE_REL8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 157 */ >+ { ENCODING_Iv, TYPE_RELv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 158 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_VK8 }, >+ { ENCODING_RM, TYPE_VK8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 159 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_VK32 }, >+ { ENCODING_RM, TYPE_VK32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 160 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_VVVV, TYPE_VK64 }, >+ { ENCODING_RM, TYPE_VK64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 161 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_VK16 }, >+ { ENCODING_RM, TYPE_VK16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 162 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_RM, TYPE_VK8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 163 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 164 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 165 */ >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 166 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_VK8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 167 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_RM, TYPE_VK32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 168 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 169 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 170 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 171 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_VK32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 172 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_RM, TYPE_VK64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 173 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 174 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 175 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 176 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_VK64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 177 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_RM, TYPE_VK16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 178 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 179 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 180 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 181 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_VK16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 182 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_RM, TYPE_VK16 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 183 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 184 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_M1616 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 185 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_M1632 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 186 */ >+ { ENCODING_RM, TYPE_M80FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 187 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_LEA }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 188 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_LEA }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 189 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M1664 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 190 */ >+ { ENCODING_RM, TYPE_R16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 191 */ >+ { ENCODING_SI, TYPE_SRCIDX8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 192 */ >+ { ENCODING_SI, TYPE_SRCIDX32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 193 */ >+ { ENCODING_SI, TYPE_SRCIDX64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 194 */ >+ { ENCODING_SI, TYPE_SRCIDX16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 195 */ >+ { ENCODING_IW, TYPE_IMM16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 196 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 197 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 198 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 199 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 200 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 201 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 202 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 203 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 204 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 205 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 206 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 207 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 208 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 209 */ >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 210 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 211 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 212 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 213 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 214 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 215 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 216 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 217 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 218 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 219 */ >+ { ENCODING_REG, TYPE_MM64 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 220 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_MM64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 221 */ >+ { ENCODING_Ia, TYPE_MOFFS16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 222 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 223 */ >+ { ENCODING_Rv, TYPE_Rv }, >+ { ENCODING_Iv, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 224 */ >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 225 */ >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 226 */ >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 227 */ >+ { ENCODING_Ia, TYPE_MOFFS32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 228 */ >+ { ENCODING_REG, TYPE_CONTROLREG }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 229 */ >+ { ENCODING_REG, TYPE_DEBUGREG }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 230 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_CONTROLREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 231 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_DEBUGREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 232 */ >+ { ENCODING_Ia, TYPE_MOFFS64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 233 */ >+ { ENCODING_Ia, TYPE_MOFFS8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 234 */ >+ { ENCODING_REG, TYPE_CONTROLREG }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 235 */ >+ { ENCODING_REG, TYPE_DEBUGREG }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 236 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_CONTROLREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 237 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_DEBUGREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 238 */ >+ { ENCODING_RO, TYPE_R64 }, >+ { ENCODING_IO, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 239 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 240 */ >+ { ENCODING_REG, TYPE_SEGMENTREG }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 241 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 242 */ >+ { ENCODING_RB, TYPE_R8 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 243 */ >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 244 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 245 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 246 */ >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 247 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 248 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 249 */ >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 250 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 251 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 252 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 253 */ >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 254 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 255 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 256 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 257 */ >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 258 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 259 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 260 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 261 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 262 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 263 */ >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_RM, TYPE_R16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 264 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 265 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 266 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 267 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 268 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 269 */ >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 270 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 271 */ >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 272 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 273 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 274 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 275 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 276 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 277 */ >+ { ENCODING_Rv, TYPE_Rv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 278 */ >+ { ENCODING_RO, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 279 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 280 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 281 */ >+ { ENCODING_IB, TYPE_IMMv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 282 */ >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 283 */ >+ { ENCODING_IB, TYPE_IMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 284 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 285 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 286 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 287 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 288 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 289 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 290 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 291 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 292 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 293 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 294 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 295 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 296 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 297 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 298 */ >+ { ENCODING_DI, TYPE_DSTIDX64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 299 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 300 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_Rv }, >+ { ENCODING_REG, TYPE_Rv }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 301 */ >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 302 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 303 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 304 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 305 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 306 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 307 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 308 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 309 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 310 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 311 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 312 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 313 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 314 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 315 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 316 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 317 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 318 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 319 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 320 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 321 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 322 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 323 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 324 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 325 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 326 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 327 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 328 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ }, >+ { /* 329 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 330 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ }, >+ { /* 331 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 332 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 333 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 334 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 335 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 336 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 337 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 338 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 339 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 340 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 341 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 342 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 343 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 344 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 345 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 346 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 347 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 348 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 349 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 350 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 351 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 352 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 353 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 354 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 355 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 356 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 357 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 358 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 359 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 360 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 361 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 362 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 363 */ >+ { ENCODING_REG, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD16, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 364 */ >+ { ENCODING_REG, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD16, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 365 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 366 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 367 */ >+ { ENCODING_REG, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD16, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 368 */ >+ { ENCODING_REG, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD16, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 369 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 370 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM5 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 371 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 372 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 373 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 374 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 375 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 376 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 377 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 378 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 379 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 380 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 381 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 382 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 383 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 384 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 385 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM_CD8, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 386 */ >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 387 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 388 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 389 */ >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 390 */ >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 391 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 392 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 393 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 394 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 395 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 396 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 397 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD16, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 398 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 399 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 400 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 401 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 402 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 403 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD4, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 404 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 405 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 406 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 407 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 408 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 409 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 410 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 411 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 412 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 413 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD8, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 414 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 415 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD16, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 416 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 417 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 418 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 419 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD4, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 420 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 421 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD4, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 422 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 423 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 424 */ >+ { ENCODING_REG, TYPE_R64 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 425 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 426 */ >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 427 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 428 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 429 */ >+ { ENCODING_RM_CD64, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 430 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 431 */ >+ { ENCODING_RM_CD64, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 432 */ >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 433 */ >+ { ENCODING_RM_CD16, TYPE_R32 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 434 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 435 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 436 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 437 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 438 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 439 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 440 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 441 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 442 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 443 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 444 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 445 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 446 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 447 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 448 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 449 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 450 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 451 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 452 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 453 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 454 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 455 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 456 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 457 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 458 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 459 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 460 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 461 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 462 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 463 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 464 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP4 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M64 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 465 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP3 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_M64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 466 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP4 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 467 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP4 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M32 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 468 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP3 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD4, TYPE_M32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 469 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP4 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M32 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 470 */ >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD4, TYPE_M32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 471 */ >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD4, TYPE_M32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 472 */ >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_M64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 473 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_DUP, TYPE_DUP3 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD4, TYPE_M64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 474 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 475 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 476 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 477 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 478 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 479 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 480 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 481 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 482 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 483 */ >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 484 */ >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 485 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 486 */ >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 487 */ >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 488 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 489 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 490 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 491 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 492 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 493 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 494 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 495 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 496 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 497 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 498 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 499 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 500 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 501 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 502 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 503 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 504 */ >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 505 */ >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 506 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 507 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 508 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 509 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 510 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 511 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 512 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 513 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 514 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 515 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 516 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 517 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 518 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 519 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 520 */ >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 521 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 522 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 523 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 524 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 525 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 526 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 527 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 528 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 529 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 530 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 531 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 532 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 533 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 534 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 535 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 536 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 537 */ >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 538 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 539 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 540 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 541 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 542 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 543 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 544 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 545 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 546 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 547 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 548 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 549 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 550 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 551 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 552 */ >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 553 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 554 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 555 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 556 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 557 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 558 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 559 */ >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 560 */ >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 561 */ >+ { ENCODING_RM_CD16, TYPE_R32 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 562 */ >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 563 */ >+ { ENCODING_RM_CD16, TYPE_R64 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 564 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 565 */ >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 566 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 567 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 568 */ >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 569 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 570 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 571 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 572 */ >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 573 */ >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 574 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 575 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 576 */ >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 577 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_WRITEMASK, TYPE_VK1 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 578 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 579 */ >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 580 */ >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_REG, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 581 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 582 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 583 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 584 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 585 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 586 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 587 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 588 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 589 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 590 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 591 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 592 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 593 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 594 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 595 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 596 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 597 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 598 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 599 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 600 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD4, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 601 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 602 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_R32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 603 */ >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 604 */ >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 605 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 606 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 607 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_R64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 608 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 609 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 610 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 611 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 612 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 613 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 614 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 615 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 616 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 617 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 618 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 619 */ >+ { ENCODING_REG, TYPE_VK64 }, >+ { ENCODING_WRITEMASK, TYPE_VK64 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 620 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 621 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 622 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 623 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 624 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 625 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 626 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 627 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 628 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 629 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 630 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 631 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 632 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 633 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 634 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 635 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 636 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 637 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 638 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 639 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 640 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 641 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 642 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 643 */ >+ { ENCODING_REG, TYPE_VK2 }, >+ { ENCODING_WRITEMASK, TYPE_VK2 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 644 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 645 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 646 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 647 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 648 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 649 */ >+ { ENCODING_REG, TYPE_VK4 }, >+ { ENCODING_WRITEMASK, TYPE_VK4 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 650 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 651 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 652 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 653 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 654 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 655 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 656 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 657 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 658 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 659 */ >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 660 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 661 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 662 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 663 */ >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 664 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 665 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 666 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 667 */ >+ { ENCODING_REG, TYPE_VK32 }, >+ { ENCODING_WRITEMASK, TYPE_VK32 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 668 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD4, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 669 */ >+ { ENCODING_DUP, TYPE_DUP1 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_Mv }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 670 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 671 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 672 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 673 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 674 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 675 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 676 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 677 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 678 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 679 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 680 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M8 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 681 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 682 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_Mv }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 683 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_R64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 684 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 685 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 686 */ >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 687 */ >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_IB, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 688 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 689 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 690 */ >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 691 */ >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_VK16 }, >+ { ENCODING_IB, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 692 */ >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 693 */ >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 694 */ >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 695 */ >+ { ENCODING_RM_CD8, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_IB, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 696 */ >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 697 */ >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_IB, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 698 */ >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 699 */ >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_REG, TYPE_VK8 }, >+ { ENCODING_IB, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 700 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 701 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 702 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 703 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD8, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 704 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_M256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 705 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 706 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD32, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 707 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 708 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 709 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 710 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 711 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_RM_CD4, TYPE_M32 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 712 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_RM_CD8, TYPE_M64 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 713 */ >+ { ENCODING_DUP, TYPE_DUP2 }, >+ { ENCODING_RM_CD4, TYPE_M64 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 714 */ >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 715 */ >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 716 */ >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 717 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 718 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_VVVV, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 719 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 720 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 721 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 722 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 723 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 724 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 725 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 726 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK16 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 727 */ >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_XMM128 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 728 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 729 */ >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM8 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 730 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_M128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 731 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_WRITEMASK, TYPE_VK8 }, >+ { ENCODING_VVVV, TYPE_XMM512 }, >+ { ENCODING_RM_CD16, TYPE_XMM128 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 732 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD8, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 733 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD4, TYPE_XMM512 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 734 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_M512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 735 */ >+ { ENCODING_REG, TYPE_XMM512 }, >+ { ENCODING_RM_CD64, TYPE_XMM512 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 736 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 737 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 738 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_M32FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 739 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 740 */ >+ { ENCODING_REG, TYPE_XMM128 }, >+ { ENCODING_VVVV, TYPE_XMM128 }, >+ { ENCODING_RM, TYPE_M64FP }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 741 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM, TYPE_XMM64 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 742 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM, TYPE_XMM32 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 743 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_M256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 744 */ >+ { ENCODING_REG, TYPE_XMM256 }, >+ { ENCODING_RM, TYPE_XMM256 }, >+ { ENCODING_IB, TYPE_IMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 745 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_VVVV, TYPE_XMM64 }, >+ { ENCODING_RM_CD16, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 746 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_VVVV, TYPE_XMM32 }, >+ { ENCODING_RM_CD16, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 747 */ >+ { ENCODING_REG, TYPE_XMM64 }, >+ { ENCODING_RM_CD8, TYPE_XMM64 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+ { /* 748 */ >+ { ENCODING_REG, TYPE_XMM32 }, >+ { ENCODING_RM_CD4, TYPE_XMM32 }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ { ENCODING_NONE, TYPE_NONE }, >+ }, >+}; >+ >+static const struct InstructionSpecifier x86DisassemblerInstrSpecifiers[6267] = { >+ { /* 0 */ >+ 0, >+ /* */ >+ }, >+ { /* 1 */ >+ 0, >+ /* */ >+ }, >+ { /* 2 */ >+ 0, >+ /* */ >+ }, >+ { /* 3 */ >+ 0, >+ /* */ >+ }, >+ { /* 4 */ >+ 0, >+ /* */ >+ }, >+ { /* 5 */ >+ 0, >+ /* */ >+ }, >+ { /* 6 */ >+ 0, >+ /* */ >+ }, >+ { /* 7 */ >+ 0, >+ /* */ >+ }, >+ { /* 8 */ >+ 0, >+ /* */ >+ }, >+ { /* 9 */ >+ 0, >+ /* */ >+ }, >+ { /* 10 */ >+ 0, >+ /* */ >+ }, >+ { /* 11 */ >+ 0, >+ /* */ >+ }, >+ { /* 12 */ >+ 0, >+ /* */ >+ }, >+ { /* 13 */ >+ 0, >+ /* */ >+ }, >+ { /* 14 */ >+ 0, >+ /* */ >+ }, >+ { /* 15 */ >+ 0, >+ /* */ >+ }, >+ { /* 16 */ >+ 0, >+ /* */ >+ }, >+ { /* 17 */ >+ 0, >+ /* */ >+ }, >+ { /* 18 */ >+ 0, >+ /* */ >+ }, >+ { /* 19 */ >+ 0, >+ /* */ >+ }, >+ { /* 20 */ >+ 0, >+ /* AAA */ >+ }, >+ { /* 21 */ >+ 1, >+ /* AAD8i8 */ >+ }, >+ { /* 22 */ >+ 1, >+ /* AAM8i8 */ >+ }, >+ { /* 23 */ >+ 0, >+ /* AAS */ >+ }, >+ { /* 24 */ >+ 0, >+ /* ABS_F */ >+ }, >+ { /* 25 */ >+ 0, >+ /* */ >+ }, >+ { /* 26 */ >+ 0, >+ /* */ >+ }, >+ { /* 27 */ >+ 0, >+ /* */ >+ }, >+ { /* 28 */ >+ 0, >+ /* */ >+ }, >+ { /* 29 */ >+ 0, >+ /* */ >+ }, >+ { /* 30 */ >+ 0, >+ /* */ >+ }, >+ { /* 31 */ >+ 0, >+ /* */ >+ }, >+ { /* 32 */ >+ 2, >+ /* ADC16i16 */ >+ }, >+ { /* 33 */ >+ 3, >+ /* ADC16mi */ >+ }, >+ { /* 34 */ >+ 4, >+ /* ADC16mi8 */ >+ }, >+ { /* 35 */ >+ 5, >+ /* ADC16mr */ >+ }, >+ { /* 36 */ >+ 6, >+ /* ADC16ri */ >+ }, >+ { /* 37 */ >+ 7, >+ /* ADC16ri8 */ >+ }, >+ { /* 38 */ >+ 8, >+ /* ADC16rm */ >+ }, >+ { /* 39 */ >+ 9, >+ /* ADC16rr */ >+ }, >+ { /* 40 */ >+ 10, >+ /* ADC16rr_REV */ >+ }, >+ { /* 41 */ >+ 2, >+ /* ADC32i32 */ >+ }, >+ { /* 42 */ >+ 3, >+ /* ADC32mi */ >+ }, >+ { /* 43 */ >+ 11, >+ /* ADC32mi8 */ >+ }, >+ { /* 44 */ >+ 5, >+ /* ADC32mr */ >+ }, >+ { /* 45 */ >+ 6, >+ /* ADC32ri */ >+ }, >+ { /* 46 */ >+ 12, >+ /* ADC32ri8 */ >+ }, >+ { /* 47 */ >+ 8, >+ /* ADC32rm */ >+ }, >+ { /* 48 */ >+ 9, >+ /* ADC32rr */ >+ }, >+ { /* 49 */ >+ 10, >+ /* ADC32rr_REV */ >+ }, >+ { /* 50 */ >+ 13, >+ /* ADC64i32 */ >+ }, >+ { /* 51 */ >+ 14, >+ /* ADC64mi32 */ >+ }, >+ { /* 52 */ >+ 15, >+ /* ADC64mi8 */ >+ }, >+ { /* 53 */ >+ 16, >+ /* ADC64mr */ >+ }, >+ { /* 54 */ >+ 17, >+ /* ADC64ri32 */ >+ }, >+ { /* 55 */ >+ 18, >+ /* ADC64ri8 */ >+ }, >+ { /* 56 */ >+ 19, >+ /* ADC64rm */ >+ }, >+ { /* 57 */ >+ 20, >+ /* ADC64rr */ >+ }, >+ { /* 58 */ >+ 21, >+ /* ADC64rr_REV */ >+ }, >+ { /* 59 */ >+ 1, >+ /* ADC8i8 */ >+ }, >+ { /* 60 */ >+ 22, >+ /* ADC8mi */ >+ }, >+ { /* 61 */ >+ 23, >+ /* ADC8mr */ >+ }, >+ { /* 62 */ >+ 24, >+ /* ADC8ri */ >+ }, >+ { /* 63 */ >+ 25, >+ /* ADC8rm */ >+ }, >+ { /* 64 */ >+ 26, >+ /* ADC8rr */ >+ }, >+ { /* 65 */ >+ 27, >+ /* ADC8rr_REV */ >+ }, >+ { /* 66 */ >+ 28, >+ /* ADCX32rm */ >+ }, >+ { /* 67 */ >+ 29, >+ /* ADCX32rr */ >+ }, >+ { /* 68 */ >+ 19, >+ /* ADCX64rm */ >+ }, >+ { /* 69 */ >+ 21, >+ /* ADCX64rr */ >+ }, >+ { /* 70 */ >+ 2, >+ /* ADD16i16 */ >+ }, >+ { /* 71 */ >+ 3, >+ /* ADD16mi */ >+ }, >+ { /* 72 */ >+ 4, >+ /* ADD16mi8 */ >+ }, >+ { /* 73 */ >+ 5, >+ /* ADD16mr */ >+ }, >+ { /* 74 */ >+ 6, >+ /* ADD16ri */ >+ }, >+ { /* 75 */ >+ 7, >+ /* ADD16ri8 */ >+ }, >+ { /* 76 */ >+ 0, >+ /* */ >+ }, >+ { /* 77 */ >+ 0, >+ /* */ >+ }, >+ { /* 78 */ >+ 8, >+ /* ADD16rm */ >+ }, >+ { /* 79 */ >+ 9, >+ /* ADD16rr */ >+ }, >+ { /* 80 */ >+ 0, >+ /* */ >+ }, >+ { /* 81 */ >+ 10, >+ /* ADD16rr_REV */ >+ }, >+ { /* 82 */ >+ 2, >+ /* ADD32i32 */ >+ }, >+ { /* 83 */ >+ 3, >+ /* ADD32mi */ >+ }, >+ { /* 84 */ >+ 11, >+ /* ADD32mi8 */ >+ }, >+ { /* 85 */ >+ 5, >+ /* ADD32mr */ >+ }, >+ { /* 86 */ >+ 6, >+ /* ADD32ri */ >+ }, >+ { /* 87 */ >+ 12, >+ /* ADD32ri8 */ >+ }, >+ { /* 88 */ >+ 0, >+ /* */ >+ }, >+ { /* 89 */ >+ 0, >+ /* */ >+ }, >+ { /* 90 */ >+ 8, >+ /* ADD32rm */ >+ }, >+ { /* 91 */ >+ 9, >+ /* ADD32rr */ >+ }, >+ { /* 92 */ >+ 0, >+ /* */ >+ }, >+ { /* 93 */ >+ 10, >+ /* ADD32rr_REV */ >+ }, >+ { /* 94 */ >+ 13, >+ /* ADD64i32 */ >+ }, >+ { /* 95 */ >+ 14, >+ /* ADD64mi32 */ >+ }, >+ { /* 96 */ >+ 15, >+ /* ADD64mi8 */ >+ }, >+ { /* 97 */ >+ 16, >+ /* ADD64mr */ >+ }, >+ { /* 98 */ >+ 17, >+ /* ADD64ri32 */ >+ }, >+ { /* 99 */ >+ 0, >+ /* */ >+ }, >+ { /* 100 */ >+ 18, >+ /* ADD64ri8 */ >+ }, >+ { /* 101 */ >+ 0, >+ /* */ >+ }, >+ { /* 102 */ >+ 19, >+ /* ADD64rm */ >+ }, >+ { /* 103 */ >+ 20, >+ /* ADD64rr */ >+ }, >+ { /* 104 */ >+ 0, >+ /* */ >+ }, >+ { /* 105 */ >+ 21, >+ /* ADD64rr_REV */ >+ }, >+ { /* 106 */ >+ 1, >+ /* ADD8i8 */ >+ }, >+ { /* 107 */ >+ 22, >+ /* ADD8mi */ >+ }, >+ { /* 108 */ >+ 23, >+ /* ADD8mr */ >+ }, >+ { /* 109 */ >+ 24, >+ /* ADD8ri */ >+ }, >+ { /* 110 */ >+ 24, >+ /* ADD8ri8 */ >+ }, >+ { /* 111 */ >+ 25, >+ /* ADD8rm */ >+ }, >+ { /* 112 */ >+ 26, >+ /* ADD8rr */ >+ }, >+ { /* 113 */ >+ 27, >+ /* ADD8rr_REV */ >+ }, >+ { /* 114 */ >+ 30, >+ /* ADDPDrm */ >+ }, >+ { /* 115 */ >+ 31, >+ /* ADDPDrr */ >+ }, >+ { /* 116 */ >+ 30, >+ /* ADDPSrm */ >+ }, >+ { /* 117 */ >+ 31, >+ /* ADDPSrr */ >+ }, >+ { /* 118 */ >+ 32, >+ /* ADDSDrm */ >+ }, >+ { /* 119 */ >+ 0, >+ /* */ >+ }, >+ { /* 120 */ >+ 33, >+ /* ADDSDrr */ >+ }, >+ { /* 121 */ >+ 0, >+ /* */ >+ }, >+ { /* 122 */ >+ 34, >+ /* ADDSSrm */ >+ }, >+ { /* 123 */ >+ 0, >+ /* */ >+ }, >+ { /* 124 */ >+ 35, >+ /* ADDSSrr */ >+ }, >+ { /* 125 */ >+ 0, >+ /* */ >+ }, >+ { /* 126 */ >+ 30, >+ /* ADDSUBPDrm */ >+ }, >+ { /* 127 */ >+ 31, >+ /* ADDSUBPDrr */ >+ }, >+ { /* 128 */ >+ 30, >+ /* ADDSUBPSrm */ >+ }, >+ { /* 129 */ >+ 31, >+ /* ADDSUBPSrr */ >+ }, >+ { /* 130 */ >+ 36, >+ /* ADD_F32m */ >+ }, >+ { /* 131 */ >+ 37, >+ /* ADD_F64m */ >+ }, >+ { /* 132 */ >+ 38, >+ /* ADD_FI16m */ >+ }, >+ { /* 133 */ >+ 38, >+ /* ADD_FI32m */ >+ }, >+ { /* 134 */ >+ 39, >+ /* ADD_FPrST0 */ >+ }, >+ { /* 135 */ >+ 39, >+ /* ADD_FST0r */ >+ }, >+ { /* 136 */ >+ 0, >+ /* */ >+ }, >+ { /* 137 */ >+ 0, >+ /* */ >+ }, >+ { /* 138 */ >+ 0, >+ /* */ >+ }, >+ { /* 139 */ >+ 0, >+ /* */ >+ }, >+ { /* 140 */ >+ 0, >+ /* */ >+ }, >+ { /* 141 */ >+ 0, >+ /* */ >+ }, >+ { /* 142 */ >+ 0, >+ /* */ >+ }, >+ { /* 143 */ >+ 0, >+ /* */ >+ }, >+ { /* 144 */ >+ 0, >+ /* */ >+ }, >+ { /* 145 */ >+ 0, >+ /* */ >+ }, >+ { /* 146 */ >+ 0, >+ /* */ >+ }, >+ { /* 147 */ >+ 0, >+ /* */ >+ }, >+ { /* 148 */ >+ 0, >+ /* */ >+ }, >+ { /* 149 */ >+ 0, >+ /* */ >+ }, >+ { /* 150 */ >+ 39, >+ /* ADD_FrST0 */ >+ }, >+ { /* 151 */ >+ 0, >+ /* */ >+ }, >+ { /* 152 */ >+ 0, >+ /* */ >+ }, >+ { /* 153 */ >+ 0, >+ /* */ >+ }, >+ { /* 154 */ >+ 0, >+ /* */ >+ }, >+ { /* 155 */ >+ 40, >+ /* ADOX32rm */ >+ }, >+ { /* 156 */ >+ 41, >+ /* ADOX32rr */ >+ }, >+ { /* 157 */ >+ 42, >+ /* ADOX64rm */ >+ }, >+ { /* 158 */ >+ 43, >+ /* ADOX64rr */ >+ }, >+ { /* 159 */ >+ 30, >+ /* AESDECLASTrm */ >+ }, >+ { /* 160 */ >+ 31, >+ /* AESDECLASTrr */ >+ }, >+ { /* 161 */ >+ 30, >+ /* AESDECrm */ >+ }, >+ { /* 162 */ >+ 31, >+ /* AESDECrr */ >+ }, >+ { /* 163 */ >+ 30, >+ /* AESENCLASTrm */ >+ }, >+ { /* 164 */ >+ 31, >+ /* AESENCLASTrr */ >+ }, >+ { /* 165 */ >+ 30, >+ /* AESENCrm */ >+ }, >+ { /* 166 */ >+ 31, >+ /* AESENCrr */ >+ }, >+ { /* 167 */ >+ 44, >+ /* AESIMCrm */ >+ }, >+ { /* 168 */ >+ 45, >+ /* AESIMCrr */ >+ }, >+ { /* 169 */ >+ 46, >+ /* AESKEYGENASSIST128rm */ >+ }, >+ { /* 170 */ >+ 47, >+ /* AESKEYGENASSIST128rr */ >+ }, >+ { /* 171 */ >+ 2, >+ /* AND16i16 */ >+ }, >+ { /* 172 */ >+ 3, >+ /* AND16mi */ >+ }, >+ { /* 173 */ >+ 4, >+ /* AND16mi8 */ >+ }, >+ { /* 174 */ >+ 5, >+ /* AND16mr */ >+ }, >+ { /* 175 */ >+ 6, >+ /* AND16ri */ >+ }, >+ { /* 176 */ >+ 7, >+ /* AND16ri8 */ >+ }, >+ { /* 177 */ >+ 8, >+ /* AND16rm */ >+ }, >+ { /* 178 */ >+ 9, >+ /* AND16rr */ >+ }, >+ { /* 179 */ >+ 10, >+ /* AND16rr_REV */ >+ }, >+ { /* 180 */ >+ 2, >+ /* AND32i32 */ >+ }, >+ { /* 181 */ >+ 3, >+ /* AND32mi */ >+ }, >+ { /* 182 */ >+ 11, >+ /* AND32mi8 */ >+ }, >+ { /* 183 */ >+ 5, >+ /* AND32mr */ >+ }, >+ { /* 184 */ >+ 6, >+ /* AND32ri */ >+ }, >+ { /* 185 */ >+ 12, >+ /* AND32ri8 */ >+ }, >+ { /* 186 */ >+ 8, >+ /* AND32rm */ >+ }, >+ { /* 187 */ >+ 9, >+ /* AND32rr */ >+ }, >+ { /* 188 */ >+ 10, >+ /* AND32rr_REV */ >+ }, >+ { /* 189 */ >+ 13, >+ /* AND64i32 */ >+ }, >+ { /* 190 */ >+ 14, >+ /* AND64mi32 */ >+ }, >+ { /* 191 */ >+ 15, >+ /* AND64mi8 */ >+ }, >+ { /* 192 */ >+ 16, >+ /* AND64mr */ >+ }, >+ { /* 193 */ >+ 17, >+ /* AND64ri32 */ >+ }, >+ { /* 194 */ >+ 18, >+ /* AND64ri8 */ >+ }, >+ { /* 195 */ >+ 19, >+ /* AND64rm */ >+ }, >+ { /* 196 */ >+ 20, >+ /* AND64rr */ >+ }, >+ { /* 197 */ >+ 21, >+ /* AND64rr_REV */ >+ }, >+ { /* 198 */ >+ 1, >+ /* AND8i8 */ >+ }, >+ { /* 199 */ >+ 22, >+ /* AND8mi */ >+ }, >+ { /* 200 */ >+ 23, >+ /* AND8mr */ >+ }, >+ { /* 201 */ >+ 24, >+ /* AND8ri */ >+ }, >+ { /* 202 */ >+ 24, >+ /* AND8ri8 */ >+ }, >+ { /* 203 */ >+ 25, >+ /* AND8rm */ >+ }, >+ { /* 204 */ >+ 26, >+ /* AND8rr */ >+ }, >+ { /* 205 */ >+ 27, >+ /* AND8rr_REV */ >+ }, >+ { /* 206 */ >+ 48, >+ /* ANDN32rm */ >+ }, >+ { /* 207 */ >+ 49, >+ /* ANDN32rr */ >+ }, >+ { /* 208 */ >+ 50, >+ /* ANDN64rm */ >+ }, >+ { /* 209 */ >+ 51, >+ /* ANDN64rr */ >+ }, >+ { /* 210 */ >+ 30, >+ /* ANDNPDrm */ >+ }, >+ { /* 211 */ >+ 31, >+ /* ANDNPDrr */ >+ }, >+ { /* 212 */ >+ 30, >+ /* ANDNPSrm */ >+ }, >+ { /* 213 */ >+ 31, >+ /* ANDNPSrr */ >+ }, >+ { /* 214 */ >+ 30, >+ /* ANDPDrm */ >+ }, >+ { /* 215 */ >+ 31, >+ /* ANDPDrr */ >+ }, >+ { /* 216 */ >+ 30, >+ /* ANDPSrm */ >+ }, >+ { /* 217 */ >+ 31, >+ /* ANDPSrr */ >+ }, >+ { /* 218 */ >+ 52, >+ /* ARPL16mr */ >+ }, >+ { /* 219 */ >+ 53, >+ /* ARPL16rr */ >+ }, >+ { /* 220 */ >+ 0, >+ /* */ >+ }, >+ { /* 221 */ >+ 0, >+ /* */ >+ }, >+ { /* 222 */ >+ 0, >+ /* */ >+ }, >+ { /* 223 */ >+ 54, >+ /* BEXTR32rm */ >+ }, >+ { /* 224 */ >+ 55, >+ /* BEXTR32rr */ >+ }, >+ { /* 225 */ >+ 56, >+ /* BEXTR64rm */ >+ }, >+ { /* 226 */ >+ 57, >+ /* BEXTR64rr */ >+ }, >+ { /* 227 */ >+ 58, >+ /* BEXTRI32mi */ >+ }, >+ { /* 228 */ >+ 59, >+ /* BEXTRI32ri */ >+ }, >+ { /* 229 */ >+ 60, >+ /* BEXTRI64mi */ >+ }, >+ { /* 230 */ >+ 61, >+ /* BEXTRI64ri */ >+ }, >+ { /* 231 */ >+ 62, >+ /* BLCFILL32rm */ >+ }, >+ { /* 232 */ >+ 63, >+ /* BLCFILL32rr */ >+ }, >+ { /* 233 */ >+ 64, >+ /* BLCFILL64rm */ >+ }, >+ { /* 234 */ >+ 65, >+ /* BLCFILL64rr */ >+ }, >+ { /* 235 */ >+ 62, >+ /* BLCI32rm */ >+ }, >+ { /* 236 */ >+ 63, >+ /* BLCI32rr */ >+ }, >+ { /* 237 */ >+ 64, >+ /* BLCI64rm */ >+ }, >+ { /* 238 */ >+ 65, >+ /* BLCI64rr */ >+ }, >+ { /* 239 */ >+ 62, >+ /* BLCIC32rm */ >+ }, >+ { /* 240 */ >+ 63, >+ /* BLCIC32rr */ >+ }, >+ { /* 241 */ >+ 64, >+ /* BLCIC64rm */ >+ }, >+ { /* 242 */ >+ 65, >+ /* BLCIC64rr */ >+ }, >+ { /* 243 */ >+ 62, >+ /* BLCMSK32rm */ >+ }, >+ { /* 244 */ >+ 63, >+ /* BLCMSK32rr */ >+ }, >+ { /* 245 */ >+ 64, >+ /* BLCMSK64rm */ >+ }, >+ { /* 246 */ >+ 65, >+ /* BLCMSK64rr */ >+ }, >+ { /* 247 */ >+ 62, >+ /* BLCS32rm */ >+ }, >+ { /* 248 */ >+ 63, >+ /* BLCS32rr */ >+ }, >+ { /* 249 */ >+ 64, >+ /* BLCS64rm */ >+ }, >+ { /* 250 */ >+ 65, >+ /* BLCS64rr */ >+ }, >+ { /* 251 */ >+ 66, >+ /* BLENDPDrmi */ >+ }, >+ { /* 252 */ >+ 67, >+ /* BLENDPDrri */ >+ }, >+ { /* 253 */ >+ 66, >+ /* BLENDPSrmi */ >+ }, >+ { /* 254 */ >+ 67, >+ /* BLENDPSrri */ >+ }, >+ { /* 255 */ >+ 30, >+ /* BLENDVPDrm0 */ >+ }, >+ { /* 256 */ >+ 31, >+ /* BLENDVPDrr0 */ >+ }, >+ { /* 257 */ >+ 30, >+ /* BLENDVPSrm0 */ >+ }, >+ { /* 258 */ >+ 31, >+ /* BLENDVPSrr0 */ >+ }, >+ { /* 259 */ >+ 62, >+ /* BLSFILL32rm */ >+ }, >+ { /* 260 */ >+ 63, >+ /* BLSFILL32rr */ >+ }, >+ { /* 261 */ >+ 64, >+ /* BLSFILL64rm */ >+ }, >+ { /* 262 */ >+ 65, >+ /* BLSFILL64rr */ >+ }, >+ { /* 263 */ >+ 62, >+ /* BLSI32rm */ >+ }, >+ { /* 264 */ >+ 63, >+ /* BLSI32rr */ >+ }, >+ { /* 265 */ >+ 64, >+ /* BLSI64rm */ >+ }, >+ { /* 266 */ >+ 65, >+ /* BLSI64rr */ >+ }, >+ { /* 267 */ >+ 62, >+ /* BLSIC32rm */ >+ }, >+ { /* 268 */ >+ 63, >+ /* BLSIC32rr */ >+ }, >+ { /* 269 */ >+ 64, >+ /* BLSIC64rm */ >+ }, >+ { /* 270 */ >+ 65, >+ /* BLSIC64rr */ >+ }, >+ { /* 271 */ >+ 62, >+ /* BLSMSK32rm */ >+ }, >+ { /* 272 */ >+ 63, >+ /* BLSMSK32rr */ >+ }, >+ { /* 273 */ >+ 64, >+ /* BLSMSK64rm */ >+ }, >+ { /* 274 */ >+ 65, >+ /* BLSMSK64rr */ >+ }, >+ { /* 275 */ >+ 62, >+ /* BLSR32rm */ >+ }, >+ { /* 276 */ >+ 63, >+ /* BLSR32rr */ >+ }, >+ { /* 277 */ >+ 64, >+ /* BLSR64rm */ >+ }, >+ { /* 278 */ >+ 65, >+ /* BLSR64rr */ >+ }, >+ { /* 279 */ >+ 68, >+ /* BOUNDS16rm */ >+ }, >+ { /* 280 */ >+ 68, >+ /* BOUNDS32rm */ >+ }, >+ { /* 281 */ >+ 68, >+ /* BSF16rm */ >+ }, >+ { /* 282 */ >+ 69, >+ /* BSF16rr */ >+ }, >+ { /* 283 */ >+ 68, >+ /* BSF32rm */ >+ }, >+ { /* 284 */ >+ 69, >+ /* BSF32rr */ >+ }, >+ { /* 285 */ >+ 42, >+ /* BSF64rm */ >+ }, >+ { /* 286 */ >+ 43, >+ /* BSF64rr */ >+ }, >+ { /* 287 */ >+ 68, >+ /* BSR16rm */ >+ }, >+ { /* 288 */ >+ 69, >+ /* BSR16rr */ >+ }, >+ { /* 289 */ >+ 68, >+ /* BSR32rm */ >+ }, >+ { /* 290 */ >+ 69, >+ /* BSR32rr */ >+ }, >+ { /* 291 */ >+ 42, >+ /* BSR64rm */ >+ }, >+ { /* 292 */ >+ 43, >+ /* BSR64rr */ >+ }, >+ { /* 293 */ >+ 70, >+ /* BSWAP32r */ >+ }, >+ { /* 294 */ >+ 71, >+ /* BSWAP64r */ >+ }, >+ { /* 295 */ >+ 4, >+ /* BT16mi8 */ >+ }, >+ { /* 296 */ >+ 5, >+ /* BT16mr */ >+ }, >+ { /* 297 */ >+ 72, >+ /* BT16ri8 */ >+ }, >+ { /* 298 */ >+ 73, >+ /* BT16rr */ >+ }, >+ { /* 299 */ >+ 11, >+ /* BT32mi8 */ >+ }, >+ { /* 300 */ >+ 5, >+ /* BT32mr */ >+ }, >+ { /* 301 */ >+ 74, >+ /* BT32ri8 */ >+ }, >+ { /* 302 */ >+ 73, >+ /* BT32rr */ >+ }, >+ { /* 303 */ >+ 15, >+ /* BT64mi8 */ >+ }, >+ { /* 304 */ >+ 16, >+ /* BT64mr */ >+ }, >+ { /* 305 */ >+ 75, >+ /* BT64ri8 */ >+ }, >+ { /* 306 */ >+ 76, >+ /* BT64rr */ >+ }, >+ { /* 307 */ >+ 4, >+ /* BTC16mi8 */ >+ }, >+ { /* 308 */ >+ 5, >+ /* BTC16mr */ >+ }, >+ { /* 309 */ >+ 72, >+ /* BTC16ri8 */ >+ }, >+ { /* 310 */ >+ 73, >+ /* BTC16rr */ >+ }, >+ { /* 311 */ >+ 11, >+ /* BTC32mi8 */ >+ }, >+ { /* 312 */ >+ 5, >+ /* BTC32mr */ >+ }, >+ { /* 313 */ >+ 74, >+ /* BTC32ri8 */ >+ }, >+ { /* 314 */ >+ 73, >+ /* BTC32rr */ >+ }, >+ { /* 315 */ >+ 15, >+ /* BTC64mi8 */ >+ }, >+ { /* 316 */ >+ 16, >+ /* BTC64mr */ >+ }, >+ { /* 317 */ >+ 75, >+ /* BTC64ri8 */ >+ }, >+ { /* 318 */ >+ 76, >+ /* BTC64rr */ >+ }, >+ { /* 319 */ >+ 4, >+ /* BTR16mi8 */ >+ }, >+ { /* 320 */ >+ 5, >+ /* BTR16mr */ >+ }, >+ { /* 321 */ >+ 72, >+ /* BTR16ri8 */ >+ }, >+ { /* 322 */ >+ 73, >+ /* BTR16rr */ >+ }, >+ { /* 323 */ >+ 11, >+ /* BTR32mi8 */ >+ }, >+ { /* 324 */ >+ 5, >+ /* BTR32mr */ >+ }, >+ { /* 325 */ >+ 74, >+ /* BTR32ri8 */ >+ }, >+ { /* 326 */ >+ 73, >+ /* BTR32rr */ >+ }, >+ { /* 327 */ >+ 15, >+ /* BTR64mi8 */ >+ }, >+ { /* 328 */ >+ 16, >+ /* BTR64mr */ >+ }, >+ { /* 329 */ >+ 75, >+ /* BTR64ri8 */ >+ }, >+ { /* 330 */ >+ 76, >+ /* BTR64rr */ >+ }, >+ { /* 331 */ >+ 4, >+ /* BTS16mi8 */ >+ }, >+ { /* 332 */ >+ 5, >+ /* BTS16mr */ >+ }, >+ { /* 333 */ >+ 72, >+ /* BTS16ri8 */ >+ }, >+ { /* 334 */ >+ 73, >+ /* BTS16rr */ >+ }, >+ { /* 335 */ >+ 11, >+ /* BTS32mi8 */ >+ }, >+ { /* 336 */ >+ 5, >+ /* BTS32mr */ >+ }, >+ { /* 337 */ >+ 74, >+ /* BTS32ri8 */ >+ }, >+ { /* 338 */ >+ 73, >+ /* BTS32rr */ >+ }, >+ { /* 339 */ >+ 15, >+ /* BTS64mi8 */ >+ }, >+ { /* 340 */ >+ 16, >+ /* BTS64mr */ >+ }, >+ { /* 341 */ >+ 75, >+ /* BTS64ri8 */ >+ }, >+ { /* 342 */ >+ 76, >+ /* BTS64rr */ >+ }, >+ { /* 343 */ >+ 54, >+ /* BZHI32rm */ >+ }, >+ { /* 344 */ >+ 55, >+ /* BZHI32rr */ >+ }, >+ { /* 345 */ >+ 56, >+ /* BZHI64rm */ >+ }, >+ { /* 346 */ >+ 57, >+ /* BZHI64rr */ >+ }, >+ { /* 347 */ >+ 38, >+ /* CALL16m */ >+ }, >+ { /* 348 */ >+ 77, >+ /* CALL16r */ >+ }, >+ { /* 349 */ >+ 38, >+ /* CALL32m */ >+ }, >+ { /* 350 */ >+ 77, >+ /* CALL32r */ >+ }, >+ { /* 351 */ >+ 38, >+ /* CALL64m */ >+ }, >+ { /* 352 */ >+ 78, >+ /* CALL64pcrel32 */ >+ }, >+ { /* 353 */ >+ 79, >+ /* CALL64r */ >+ }, >+ { /* 354 */ >+ 80, >+ /* CALLpcrel16 */ >+ }, >+ { /* 355 */ >+ 81, >+ /* CALLpcrel32 */ >+ }, >+ { /* 356 */ >+ 0, >+ /* CBW */ >+ }, >+ { /* 357 */ >+ 0, >+ /* CDQ */ >+ }, >+ { /* 358 */ >+ 0, >+ /* CDQE */ >+ }, >+ { /* 359 */ >+ 0, >+ /* CHS_F */ >+ }, >+ { /* 360 */ >+ 0, >+ /* */ >+ }, >+ { /* 361 */ >+ 0, >+ /* */ >+ }, >+ { /* 362 */ >+ 0, >+ /* */ >+ }, >+ { /* 363 */ >+ 0, >+ /* CLAC */ >+ }, >+ { /* 364 */ >+ 0, >+ /* CLC */ >+ }, >+ { /* 365 */ >+ 0, >+ /* CLD */ >+ }, >+ { /* 366 */ >+ 82, >+ /* CLFLUSH */ >+ }, >+ { /* 367 */ >+ 0, >+ /* CLGI */ >+ }, >+ { /* 368 */ >+ 0, >+ /* CLI */ >+ }, >+ { /* 369 */ >+ 0, >+ /* CLTS */ >+ }, >+ { /* 370 */ >+ 0, >+ /* CMC */ >+ }, >+ { /* 371 */ >+ 8, >+ /* CMOVA16rm */ >+ }, >+ { /* 372 */ >+ 10, >+ /* CMOVA16rr */ >+ }, >+ { /* 373 */ >+ 8, >+ /* CMOVA32rm */ >+ }, >+ { /* 374 */ >+ 10, >+ /* CMOVA32rr */ >+ }, >+ { /* 375 */ >+ 19, >+ /* CMOVA64rm */ >+ }, >+ { /* 376 */ >+ 21, >+ /* CMOVA64rr */ >+ }, >+ { /* 377 */ >+ 8, >+ /* CMOVAE16rm */ >+ }, >+ { /* 378 */ >+ 10, >+ /* CMOVAE16rr */ >+ }, >+ { /* 379 */ >+ 8, >+ /* CMOVAE32rm */ >+ }, >+ { /* 380 */ >+ 10, >+ /* CMOVAE32rr */ >+ }, >+ { /* 381 */ >+ 19, >+ /* CMOVAE64rm */ >+ }, >+ { /* 382 */ >+ 21, >+ /* CMOVAE64rr */ >+ }, >+ { /* 383 */ >+ 8, >+ /* CMOVB16rm */ >+ }, >+ { /* 384 */ >+ 10, >+ /* CMOVB16rr */ >+ }, >+ { /* 385 */ >+ 8, >+ /* CMOVB32rm */ >+ }, >+ { /* 386 */ >+ 10, >+ /* CMOVB32rr */ >+ }, >+ { /* 387 */ >+ 19, >+ /* CMOVB64rm */ >+ }, >+ { /* 388 */ >+ 21, >+ /* CMOVB64rr */ >+ }, >+ { /* 389 */ >+ 8, >+ /* CMOVBE16rm */ >+ }, >+ { /* 390 */ >+ 10, >+ /* CMOVBE16rr */ >+ }, >+ { /* 391 */ >+ 8, >+ /* CMOVBE32rm */ >+ }, >+ { /* 392 */ >+ 10, >+ /* CMOVBE32rr */ >+ }, >+ { /* 393 */ >+ 19, >+ /* CMOVBE64rm */ >+ }, >+ { /* 394 */ >+ 21, >+ /* CMOVBE64rr */ >+ }, >+ { /* 395 */ >+ 39, >+ /* CMOVBE_F */ >+ }, >+ { /* 396 */ >+ 0, >+ /* */ >+ }, >+ { /* 397 */ >+ 0, >+ /* */ >+ }, >+ { /* 398 */ >+ 0, >+ /* */ >+ }, >+ { /* 399 */ >+ 39, >+ /* CMOVB_F */ >+ }, >+ { /* 400 */ >+ 0, >+ /* */ >+ }, >+ { /* 401 */ >+ 0, >+ /* */ >+ }, >+ { /* 402 */ >+ 0, >+ /* */ >+ }, >+ { /* 403 */ >+ 8, >+ /* CMOVE16rm */ >+ }, >+ { /* 404 */ >+ 10, >+ /* CMOVE16rr */ >+ }, >+ { /* 405 */ >+ 8, >+ /* CMOVE32rm */ >+ }, >+ { /* 406 */ >+ 10, >+ /* CMOVE32rr */ >+ }, >+ { /* 407 */ >+ 19, >+ /* CMOVE64rm */ >+ }, >+ { /* 408 */ >+ 21, >+ /* CMOVE64rr */ >+ }, >+ { /* 409 */ >+ 39, >+ /* CMOVE_F */ >+ }, >+ { /* 410 */ >+ 0, >+ /* */ >+ }, >+ { /* 411 */ >+ 0, >+ /* */ >+ }, >+ { /* 412 */ >+ 0, >+ /* */ >+ }, >+ { /* 413 */ >+ 8, >+ /* CMOVG16rm */ >+ }, >+ { /* 414 */ >+ 10, >+ /* CMOVG16rr */ >+ }, >+ { /* 415 */ >+ 8, >+ /* CMOVG32rm */ >+ }, >+ { /* 416 */ >+ 10, >+ /* CMOVG32rr */ >+ }, >+ { /* 417 */ >+ 19, >+ /* CMOVG64rm */ >+ }, >+ { /* 418 */ >+ 21, >+ /* CMOVG64rr */ >+ }, >+ { /* 419 */ >+ 8, >+ /* CMOVGE16rm */ >+ }, >+ { /* 420 */ >+ 10, >+ /* CMOVGE16rr */ >+ }, >+ { /* 421 */ >+ 8, >+ /* CMOVGE32rm */ >+ }, >+ { /* 422 */ >+ 10, >+ /* CMOVGE32rr */ >+ }, >+ { /* 423 */ >+ 19, >+ /* CMOVGE64rm */ >+ }, >+ { /* 424 */ >+ 21, >+ /* CMOVGE64rr */ >+ }, >+ { /* 425 */ >+ 8, >+ /* CMOVL16rm */ >+ }, >+ { /* 426 */ >+ 10, >+ /* CMOVL16rr */ >+ }, >+ { /* 427 */ >+ 8, >+ /* CMOVL32rm */ >+ }, >+ { /* 428 */ >+ 10, >+ /* CMOVL32rr */ >+ }, >+ { /* 429 */ >+ 19, >+ /* CMOVL64rm */ >+ }, >+ { /* 430 */ >+ 21, >+ /* CMOVL64rr */ >+ }, >+ { /* 431 */ >+ 8, >+ /* CMOVLE16rm */ >+ }, >+ { /* 432 */ >+ 10, >+ /* CMOVLE16rr */ >+ }, >+ { /* 433 */ >+ 8, >+ /* CMOVLE32rm */ >+ }, >+ { /* 434 */ >+ 10, >+ /* CMOVLE32rr */ >+ }, >+ { /* 435 */ >+ 19, >+ /* CMOVLE64rm */ >+ }, >+ { /* 436 */ >+ 21, >+ /* CMOVLE64rr */ >+ }, >+ { /* 437 */ >+ 39, >+ /* CMOVNBE_F */ >+ }, >+ { /* 438 */ >+ 0, >+ /* */ >+ }, >+ { /* 439 */ >+ 0, >+ /* */ >+ }, >+ { /* 440 */ >+ 0, >+ /* */ >+ }, >+ { /* 441 */ >+ 39, >+ /* CMOVNB_F */ >+ }, >+ { /* 442 */ >+ 0, >+ /* */ >+ }, >+ { /* 443 */ >+ 0, >+ /* */ >+ }, >+ { /* 444 */ >+ 0, >+ /* */ >+ }, >+ { /* 445 */ >+ 8, >+ /* CMOVNE16rm */ >+ }, >+ { /* 446 */ >+ 10, >+ /* CMOVNE16rr */ >+ }, >+ { /* 447 */ >+ 8, >+ /* CMOVNE32rm */ >+ }, >+ { /* 448 */ >+ 10, >+ /* CMOVNE32rr */ >+ }, >+ { /* 449 */ >+ 19, >+ /* CMOVNE64rm */ >+ }, >+ { /* 450 */ >+ 21, >+ /* CMOVNE64rr */ >+ }, >+ { /* 451 */ >+ 39, >+ /* CMOVNE_F */ >+ }, >+ { /* 452 */ >+ 0, >+ /* */ >+ }, >+ { /* 453 */ >+ 0, >+ /* */ >+ }, >+ { /* 454 */ >+ 0, >+ /* */ >+ }, >+ { /* 455 */ >+ 8, >+ /* CMOVNO16rm */ >+ }, >+ { /* 456 */ >+ 10, >+ /* CMOVNO16rr */ >+ }, >+ { /* 457 */ >+ 8, >+ /* CMOVNO32rm */ >+ }, >+ { /* 458 */ >+ 10, >+ /* CMOVNO32rr */ >+ }, >+ { /* 459 */ >+ 19, >+ /* CMOVNO64rm */ >+ }, >+ { /* 460 */ >+ 21, >+ /* CMOVNO64rr */ >+ }, >+ { /* 461 */ >+ 8, >+ /* CMOVNP16rm */ >+ }, >+ { /* 462 */ >+ 10, >+ /* CMOVNP16rr */ >+ }, >+ { /* 463 */ >+ 8, >+ /* CMOVNP32rm */ >+ }, >+ { /* 464 */ >+ 10, >+ /* CMOVNP32rr */ >+ }, >+ { /* 465 */ >+ 19, >+ /* CMOVNP64rm */ >+ }, >+ { /* 466 */ >+ 21, >+ /* CMOVNP64rr */ >+ }, >+ { /* 467 */ >+ 39, >+ /* CMOVNP_F */ >+ }, >+ { /* 468 */ >+ 0, >+ /* */ >+ }, >+ { /* 469 */ >+ 0, >+ /* */ >+ }, >+ { /* 470 */ >+ 0, >+ /* */ >+ }, >+ { /* 471 */ >+ 8, >+ /* CMOVNS16rm */ >+ }, >+ { /* 472 */ >+ 10, >+ /* CMOVNS16rr */ >+ }, >+ { /* 473 */ >+ 8, >+ /* CMOVNS32rm */ >+ }, >+ { /* 474 */ >+ 10, >+ /* CMOVNS32rr */ >+ }, >+ { /* 475 */ >+ 19, >+ /* CMOVNS64rm */ >+ }, >+ { /* 476 */ >+ 21, >+ /* CMOVNS64rr */ >+ }, >+ { /* 477 */ >+ 8, >+ /* CMOVO16rm */ >+ }, >+ { /* 478 */ >+ 10, >+ /* CMOVO16rr */ >+ }, >+ { /* 479 */ >+ 8, >+ /* CMOVO32rm */ >+ }, >+ { /* 480 */ >+ 10, >+ /* CMOVO32rr */ >+ }, >+ { /* 481 */ >+ 19, >+ /* CMOVO64rm */ >+ }, >+ { /* 482 */ >+ 21, >+ /* CMOVO64rr */ >+ }, >+ { /* 483 */ >+ 8, >+ /* CMOVP16rm */ >+ }, >+ { /* 484 */ >+ 10, >+ /* CMOVP16rr */ >+ }, >+ { /* 485 */ >+ 8, >+ /* CMOVP32rm */ >+ }, >+ { /* 486 */ >+ 10, >+ /* CMOVP32rr */ >+ }, >+ { /* 487 */ >+ 19, >+ /* CMOVP64rm */ >+ }, >+ { /* 488 */ >+ 21, >+ /* CMOVP64rr */ >+ }, >+ { /* 489 */ >+ 39, >+ /* CMOVP_F */ >+ }, >+ { /* 490 */ >+ 0, >+ /* */ >+ }, >+ { /* 491 */ >+ 0, >+ /* */ >+ }, >+ { /* 492 */ >+ 0, >+ /* */ >+ }, >+ { /* 493 */ >+ 8, >+ /* CMOVS16rm */ >+ }, >+ { /* 494 */ >+ 10, >+ /* CMOVS16rr */ >+ }, >+ { /* 495 */ >+ 8, >+ /* CMOVS32rm */ >+ }, >+ { /* 496 */ >+ 10, >+ /* CMOVS32rr */ >+ }, >+ { /* 497 */ >+ 19, >+ /* CMOVS64rm */ >+ }, >+ { /* 498 */ >+ 21, >+ /* CMOVS64rr */ >+ }, >+ { /* 499 */ >+ 0, >+ /* */ >+ }, >+ { /* 500 */ >+ 0, >+ /* */ >+ }, >+ { /* 501 */ >+ 0, >+ /* */ >+ }, >+ { /* 502 */ >+ 0, >+ /* */ >+ }, >+ { /* 503 */ >+ 0, >+ /* */ >+ }, >+ { /* 504 */ >+ 0, >+ /* */ >+ }, >+ { /* 505 */ >+ 0, >+ /* */ >+ }, >+ { /* 506 */ >+ 0, >+ /* */ >+ }, >+ { /* 507 */ >+ 0, >+ /* */ >+ }, >+ { /* 508 */ >+ 0, >+ /* */ >+ }, >+ { /* 509 */ >+ 0, >+ /* */ >+ }, >+ { /* 510 */ >+ 0, >+ /* */ >+ }, >+ { /* 511 */ >+ 0, >+ /* */ >+ }, >+ { /* 512 */ >+ 0, >+ /* */ >+ }, >+ { /* 513 */ >+ 0, >+ /* */ >+ }, >+ { /* 514 */ >+ 0, >+ /* */ >+ }, >+ { /* 515 */ >+ 0, >+ /* */ >+ }, >+ { /* 516 */ >+ 2, >+ /* CMP16i16 */ >+ }, >+ { /* 517 */ >+ 3, >+ /* CMP16mi */ >+ }, >+ { /* 518 */ >+ 4, >+ /* CMP16mi8 */ >+ }, >+ { /* 519 */ >+ 5, >+ /* CMP16mr */ >+ }, >+ { /* 520 */ >+ 83, >+ /* CMP16ri */ >+ }, >+ { /* 521 */ >+ 72, >+ /* CMP16ri8 */ >+ }, >+ { /* 522 */ >+ 68, >+ /* CMP16rm */ >+ }, >+ { /* 523 */ >+ 73, >+ /* CMP16rr */ >+ }, >+ { /* 524 */ >+ 69, >+ /* CMP16rr_REV */ >+ }, >+ { /* 525 */ >+ 2, >+ /* CMP32i32 */ >+ }, >+ { /* 526 */ >+ 3, >+ /* CMP32mi */ >+ }, >+ { /* 527 */ >+ 11, >+ /* CMP32mi8 */ >+ }, >+ { /* 528 */ >+ 5, >+ /* CMP32mr */ >+ }, >+ { /* 529 */ >+ 83, >+ /* CMP32ri */ >+ }, >+ { /* 530 */ >+ 74, >+ /* CMP32ri8 */ >+ }, >+ { /* 531 */ >+ 68, >+ /* CMP32rm */ >+ }, >+ { /* 532 */ >+ 73, >+ /* CMP32rr */ >+ }, >+ { /* 533 */ >+ 69, >+ /* CMP32rr_REV */ >+ }, >+ { /* 534 */ >+ 13, >+ /* CMP64i32 */ >+ }, >+ { /* 535 */ >+ 14, >+ /* CMP64mi32 */ >+ }, >+ { /* 536 */ >+ 15, >+ /* CMP64mi8 */ >+ }, >+ { /* 537 */ >+ 16, >+ /* CMP64mr */ >+ }, >+ { /* 538 */ >+ 84, >+ /* CMP64ri32 */ >+ }, >+ { /* 539 */ >+ 75, >+ /* CMP64ri8 */ >+ }, >+ { /* 540 */ >+ 42, >+ /* CMP64rm */ >+ }, >+ { /* 541 */ >+ 76, >+ /* CMP64rr */ >+ }, >+ { /* 542 */ >+ 43, >+ /* CMP64rr_REV */ >+ }, >+ { /* 543 */ >+ 1, >+ /* CMP8i8 */ >+ }, >+ { /* 544 */ >+ 22, >+ /* CMP8mi */ >+ }, >+ { /* 545 */ >+ 23, >+ /* CMP8mr */ >+ }, >+ { /* 546 */ >+ 85, >+ /* CMP8ri */ >+ }, >+ { /* 547 */ >+ 86, >+ /* CMP8rm */ >+ }, >+ { /* 548 */ >+ 87, >+ /* CMP8rr */ >+ }, >+ { /* 549 */ >+ 88, >+ /* CMP8rr_REV */ >+ }, >+ { /* 550 */ >+ 89, >+ /* CMPPDrmi */ >+ }, >+ { /* 551 */ >+ 0, >+ /* */ >+ }, >+ { /* 552 */ >+ 90, >+ /* CMPPDrri */ >+ }, >+ { /* 553 */ >+ 0, >+ /* */ >+ }, >+ { /* 554 */ >+ 89, >+ /* CMPPSrmi */ >+ }, >+ { /* 555 */ >+ 0, >+ /* */ >+ }, >+ { /* 556 */ >+ 90, >+ /* CMPPSrri */ >+ }, >+ { /* 557 */ >+ 0, >+ /* */ >+ }, >+ { /* 558 */ >+ 91, >+ /* CMPSB */ >+ }, >+ { /* 559 */ >+ 92, >+ /* CMPSDrm */ >+ }, >+ { /* 560 */ >+ 0, >+ /* */ >+ }, >+ { /* 561 */ >+ 93, >+ /* CMPSDrr */ >+ }, >+ { /* 562 */ >+ 0, >+ /* */ >+ }, >+ { /* 563 */ >+ 94, >+ /* CMPSL */ >+ }, >+ { /* 564 */ >+ 95, >+ /* CMPSQ */ >+ }, >+ { /* 565 */ >+ 96, >+ /* CMPSSrm */ >+ }, >+ { /* 566 */ >+ 0, >+ /* */ >+ }, >+ { /* 567 */ >+ 97, >+ /* CMPSSrr */ >+ }, >+ { /* 568 */ >+ 0, >+ /* */ >+ }, >+ { /* 569 */ >+ 98, >+ /* CMPSW */ >+ }, >+ { /* 570 */ >+ 99, >+ /* CMPXCHG16B */ >+ }, >+ { /* 571 */ >+ 5, >+ /* CMPXCHG16rm */ >+ }, >+ { /* 572 */ >+ 73, >+ /* CMPXCHG16rr */ >+ }, >+ { /* 573 */ >+ 5, >+ /* CMPXCHG32rm */ >+ }, >+ { /* 574 */ >+ 73, >+ /* CMPXCHG32rr */ >+ }, >+ { /* 575 */ >+ 16, >+ /* CMPXCHG64rm */ >+ }, >+ { /* 576 */ >+ 76, >+ /* CMPXCHG64rr */ >+ }, >+ { /* 577 */ >+ 38, >+ /* CMPXCHG8B */ >+ }, >+ { /* 578 */ >+ 23, >+ /* CMPXCHG8rm */ >+ }, >+ { /* 579 */ >+ 87, >+ /* CMPXCHG8rr */ >+ }, >+ { /* 580 */ >+ 44, >+ /* COMISDrm */ >+ }, >+ { /* 581 */ >+ 45, >+ /* COMISDrr */ >+ }, >+ { /* 582 */ >+ 44, >+ /* COMISSrm */ >+ }, >+ { /* 583 */ >+ 45, >+ /* COMISSrr */ >+ }, >+ { /* 584 */ >+ 39, >+ /* COMP_FST0r */ >+ }, >+ { /* 585 */ >+ 39, >+ /* COM_FIPr */ >+ }, >+ { /* 586 */ >+ 39, >+ /* COM_FIr */ >+ }, >+ { /* 587 */ >+ 39, >+ /* COM_FST0r */ >+ }, >+ { /* 588 */ >+ 0, >+ /* COS_F */ >+ }, >+ { /* 589 */ >+ 0, >+ /* */ >+ }, >+ { /* 590 */ >+ 0, >+ /* */ >+ }, >+ { /* 591 */ >+ 0, >+ /* */ >+ }, >+ { /* 592 */ >+ 0, >+ /* CPUID32 */ >+ }, >+ { /* 593 */ >+ 0, >+ /* CPUID64 */ >+ }, >+ { /* 594 */ >+ 0, >+ /* CQO */ >+ }, >+ { /* 595 */ >+ 28, >+ /* CRC32r32m16 */ >+ }, >+ { /* 596 */ >+ 8, >+ /* CRC32r32m32 */ >+ }, >+ { /* 597 */ >+ 100, >+ /* CRC32r32m8 */ >+ }, >+ { /* 598 */ >+ 101, >+ /* CRC32r32r16 */ >+ }, >+ { /* 599 */ >+ 10, >+ /* CRC32r32r32 */ >+ }, >+ { /* 600 */ >+ 102, >+ /* CRC32r32r8 */ >+ }, >+ { /* 601 */ >+ 19, >+ /* CRC32r64m64 */ >+ }, >+ { /* 602 */ >+ 103, >+ /* CRC32r64m8 */ >+ }, >+ { /* 603 */ >+ 21, >+ /* CRC32r64r64 */ >+ }, >+ { /* 604 */ >+ 104, >+ /* CRC32r64r8 */ >+ }, >+ { /* 605 */ >+ 105, >+ /* CVTDQ2PDrm */ >+ }, >+ { /* 606 */ >+ 45, >+ /* CVTDQ2PDrr */ >+ }, >+ { /* 607 */ >+ 44, >+ /* CVTDQ2PSrm */ >+ }, >+ { /* 608 */ >+ 45, >+ /* CVTDQ2PSrr */ >+ }, >+ { /* 609 */ >+ 44, >+ /* CVTPD2DQrm */ >+ }, >+ { /* 610 */ >+ 45, >+ /* CVTPD2DQrr */ >+ }, >+ { /* 611 */ >+ 44, >+ /* CVTPD2PSrm */ >+ }, >+ { /* 612 */ >+ 45, >+ /* CVTPD2PSrr */ >+ }, >+ { /* 613 */ >+ 44, >+ /* CVTPS2DQrm */ >+ }, >+ { /* 614 */ >+ 45, >+ /* CVTPS2DQrr */ >+ }, >+ { /* 615 */ >+ 106, >+ /* CVTPS2PDrm */ >+ }, >+ { /* 616 */ >+ 45, >+ /* CVTPS2PDrr */ >+ }, >+ { /* 617 */ >+ 107, >+ /* CVTSD2SI64rm */ >+ }, >+ { /* 618 */ >+ 108, >+ /* CVTSD2SI64rr */ >+ }, >+ { /* 619 */ >+ 109, >+ /* CVTSD2SIrm */ >+ }, >+ { /* 620 */ >+ 110, >+ /* CVTSD2SIrr */ >+ }, >+ { /* 621 */ >+ 111, >+ /* CVTSD2SSrm */ >+ }, >+ { /* 622 */ >+ 112, >+ /* CVTSD2SSrr */ >+ }, >+ { /* 623 */ >+ 113, >+ /* CVTSI2SD64rm */ >+ }, >+ { /* 624 */ >+ 114, >+ /* CVTSI2SD64rr */ >+ }, >+ { /* 625 */ >+ 113, >+ /* CVTSI2SDrm */ >+ }, >+ { /* 626 */ >+ 115, >+ /* CVTSI2SDrr */ >+ }, >+ { /* 627 */ >+ 116, >+ /* CVTSI2SS64rm */ >+ }, >+ { /* 628 */ >+ 117, >+ /* CVTSI2SS64rr */ >+ }, >+ { /* 629 */ >+ 116, >+ /* CVTSI2SSrm */ >+ }, >+ { /* 630 */ >+ 118, >+ /* CVTSI2SSrr */ >+ }, >+ { /* 631 */ >+ 119, >+ /* CVTSS2SDrm */ >+ }, >+ { /* 632 */ >+ 120, >+ /* CVTSS2SDrr */ >+ }, >+ { /* 633 */ >+ 121, >+ /* CVTSS2SI64rm */ >+ }, >+ { /* 634 */ >+ 108, >+ /* CVTSS2SI64rr */ >+ }, >+ { /* 635 */ >+ 122, >+ /* CVTSS2SIrm */ >+ }, >+ { /* 636 */ >+ 110, >+ /* CVTSS2SIrr */ >+ }, >+ { /* 637 */ >+ 44, >+ /* CVTTPD2DQrm */ >+ }, >+ { /* 638 */ >+ 45, >+ /* CVTTPD2DQrr */ >+ }, >+ { /* 639 */ >+ 44, >+ /* CVTTPS2DQrm */ >+ }, >+ { /* 640 */ >+ 45, >+ /* CVTTPS2DQrr */ >+ }, >+ { /* 641 */ >+ 107, >+ /* CVTTSD2SI64rm */ >+ }, >+ { /* 642 */ >+ 123, >+ /* CVTTSD2SI64rr */ >+ }, >+ { /* 643 */ >+ 109, >+ /* CVTTSD2SIrm */ >+ }, >+ { /* 644 */ >+ 124, >+ /* CVTTSD2SIrr */ >+ }, >+ { /* 645 */ >+ 121, >+ /* CVTTSS2SI64rm */ >+ }, >+ { /* 646 */ >+ 125, >+ /* CVTTSS2SI64rr */ >+ }, >+ { /* 647 */ >+ 122, >+ /* CVTTSS2SIrm */ >+ }, >+ { /* 648 */ >+ 126, >+ /* CVTTSS2SIrr */ >+ }, >+ { /* 649 */ >+ 0, >+ /* CWD */ >+ }, >+ { /* 650 */ >+ 0, >+ /* CWDE */ >+ }, >+ { /* 651 */ >+ 0, >+ /* DAA */ >+ }, >+ { /* 652 */ >+ 0, >+ /* DAS */ >+ }, >+ { /* 653 */ >+ 0, >+ /* DATA16_PREFIX */ >+ }, >+ { /* 654 */ >+ 38, >+ /* DEC16m */ >+ }, >+ { /* 655 */ >+ 70, >+ /* DEC16r */ >+ }, >+ { /* 656 */ >+ 127, >+ /* DEC32_16r */ >+ }, >+ { /* 657 */ >+ 127, >+ /* DEC32_32r */ >+ }, >+ { /* 658 */ >+ 38, >+ /* DEC32m */ >+ }, >+ { /* 659 */ >+ 70, >+ /* DEC32r */ >+ }, >+ { /* 660 */ >+ 38, >+ /* DEC64_16m */ >+ }, >+ { /* 661 */ >+ 127, >+ /* DEC64_16r */ >+ }, >+ { /* 662 */ >+ 38, >+ /* DEC64_32m */ >+ }, >+ { /* 663 */ >+ 127, >+ /* DEC64_32r */ >+ }, >+ { /* 664 */ >+ 38, >+ /* DEC64m */ >+ }, >+ { /* 665 */ >+ 128, >+ /* DEC64r */ >+ }, >+ { /* 666 */ >+ 82, >+ /* DEC8m */ >+ }, >+ { /* 667 */ >+ 129, >+ /* DEC8r */ >+ }, >+ { /* 668 */ >+ 38, >+ /* DIV16m */ >+ }, >+ { /* 669 */ >+ 77, >+ /* DIV16r */ >+ }, >+ { /* 670 */ >+ 38, >+ /* DIV32m */ >+ }, >+ { /* 671 */ >+ 77, >+ /* DIV32r */ >+ }, >+ { /* 672 */ >+ 38, >+ /* DIV64m */ >+ }, >+ { /* 673 */ >+ 79, >+ /* DIV64r */ >+ }, >+ { /* 674 */ >+ 82, >+ /* DIV8m */ >+ }, >+ { /* 675 */ >+ 130, >+ /* DIV8r */ >+ }, >+ { /* 676 */ >+ 30, >+ /* DIVPDrm */ >+ }, >+ { /* 677 */ >+ 31, >+ /* DIVPDrr */ >+ }, >+ { /* 678 */ >+ 30, >+ /* DIVPSrm */ >+ }, >+ { /* 679 */ >+ 31, >+ /* DIVPSrr */ >+ }, >+ { /* 680 */ >+ 36, >+ /* DIVR_F32m */ >+ }, >+ { /* 681 */ >+ 37, >+ /* DIVR_F64m */ >+ }, >+ { /* 682 */ >+ 38, >+ /* DIVR_FI16m */ >+ }, >+ { /* 683 */ >+ 38, >+ /* DIVR_FI32m */ >+ }, >+ { /* 684 */ >+ 39, >+ /* DIVR_FPrST0 */ >+ }, >+ { /* 685 */ >+ 39, >+ /* DIVR_FST0r */ >+ }, >+ { /* 686 */ >+ 0, >+ /* */ >+ }, >+ { /* 687 */ >+ 0, >+ /* */ >+ }, >+ { /* 688 */ >+ 0, >+ /* */ >+ }, >+ { /* 689 */ >+ 0, >+ /* */ >+ }, >+ { /* 690 */ >+ 0, >+ /* */ >+ }, >+ { /* 691 */ >+ 0, >+ /* */ >+ }, >+ { /* 692 */ >+ 0, >+ /* */ >+ }, >+ { /* 693 */ >+ 0, >+ /* */ >+ }, >+ { /* 694 */ >+ 0, >+ /* */ >+ }, >+ { /* 695 */ >+ 0, >+ /* */ >+ }, >+ { /* 696 */ >+ 0, >+ /* */ >+ }, >+ { /* 697 */ >+ 39, >+ /* DIVR_FrST0 */ >+ }, >+ { /* 698 */ >+ 32, >+ /* DIVSDrm */ >+ }, >+ { /* 699 */ >+ 0, >+ /* */ >+ }, >+ { /* 700 */ >+ 33, >+ /* DIVSDrr */ >+ }, >+ { /* 701 */ >+ 0, >+ /* */ >+ }, >+ { /* 702 */ >+ 34, >+ /* DIVSSrm */ >+ }, >+ { /* 703 */ >+ 0, >+ /* */ >+ }, >+ { /* 704 */ >+ 35, >+ /* DIVSSrr */ >+ }, >+ { /* 705 */ >+ 0, >+ /* */ >+ }, >+ { /* 706 */ >+ 36, >+ /* DIV_F32m */ >+ }, >+ { /* 707 */ >+ 37, >+ /* DIV_F64m */ >+ }, >+ { /* 708 */ >+ 38, >+ /* DIV_FI16m */ >+ }, >+ { /* 709 */ >+ 38, >+ /* DIV_FI32m */ >+ }, >+ { /* 710 */ >+ 39, >+ /* DIV_FPrST0 */ >+ }, >+ { /* 711 */ >+ 39, >+ /* DIV_FST0r */ >+ }, >+ { /* 712 */ >+ 0, >+ /* */ >+ }, >+ { /* 713 */ >+ 0, >+ /* */ >+ }, >+ { /* 714 */ >+ 0, >+ /* */ >+ }, >+ { /* 715 */ >+ 0, >+ /* */ >+ }, >+ { /* 716 */ >+ 0, >+ /* */ >+ }, >+ { /* 717 */ >+ 0, >+ /* */ >+ }, >+ { /* 718 */ >+ 0, >+ /* */ >+ }, >+ { /* 719 */ >+ 0, >+ /* */ >+ }, >+ { /* 720 */ >+ 0, >+ /* */ >+ }, >+ { /* 721 */ >+ 0, >+ /* */ >+ }, >+ { /* 722 */ >+ 0, >+ /* */ >+ }, >+ { /* 723 */ >+ 0, >+ /* */ >+ }, >+ { /* 724 */ >+ 0, >+ /* */ >+ }, >+ { /* 725 */ >+ 0, >+ /* */ >+ }, >+ { /* 726 */ >+ 39, >+ /* DIV_FrST0 */ >+ }, >+ { /* 727 */ >+ 66, >+ /* DPPDrmi */ >+ }, >+ { /* 728 */ >+ 67, >+ /* DPPDrri */ >+ }, >+ { /* 729 */ >+ 66, >+ /* DPPSrmi */ >+ }, >+ { /* 730 */ >+ 67, >+ /* DPPSrri */ >+ }, >+ { /* 731 */ >+ 0, >+ /* */ >+ }, >+ { /* 732 */ >+ 0, >+ /* */ >+ }, >+ { /* 733 */ >+ 0, >+ /* */ >+ }, >+ { /* 734 */ >+ 0, >+ /* */ >+ }, >+ { /* 735 */ >+ 0, >+ /* */ >+ }, >+ { /* 736 */ >+ 0, >+ /* */ >+ }, >+ { /* 737 */ >+ 0, >+ /* */ >+ }, >+ { /* 738 */ >+ 0, >+ /* ENCLS */ >+ }, >+ { /* 739 */ >+ 0, >+ /* ENCLU */ >+ }, >+ { /* 740 */ >+ 131, >+ /* ENTER */ >+ }, >+ { /* 741 */ >+ 132, >+ /* EXTRACTPSmr */ >+ }, >+ { /* 742 */ >+ 133, >+ /* EXTRACTPSrr */ >+ }, >+ { /* 743 */ >+ 31, >+ /* EXTRQ */ >+ }, >+ { /* 744 */ >+ 134, >+ /* EXTRQI */ >+ }, >+ { /* 745 */ >+ 0, >+ /* F2XM1 */ >+ }, >+ { /* 746 */ >+ 135, >+ /* FARCALL16i */ >+ }, >+ { /* 747 */ >+ 136, >+ /* FARCALL16m */ >+ }, >+ { /* 748 */ >+ 137, >+ /* FARCALL32i */ >+ }, >+ { /* 749 */ >+ 138, >+ /* FARCALL32m */ >+ }, >+ { /* 750 */ >+ 139, >+ /* FARCALL64 */ >+ }, >+ { /* 751 */ >+ 135, >+ /* FARJMP16i */ >+ }, >+ { /* 752 */ >+ 136, >+ /* FARJMP16m */ >+ }, >+ { /* 753 */ >+ 137, >+ /* FARJMP32i */ >+ }, >+ { /* 754 */ >+ 138, >+ /* FARJMP32m */ >+ }, >+ { /* 755 */ >+ 139, >+ /* FARJMP64 */ >+ }, >+ { /* 756 */ >+ 36, >+ /* FBLDm */ >+ }, >+ { /* 757 */ >+ 36, >+ /* FBSTPm */ >+ }, >+ { /* 758 */ >+ 36, >+ /* FCOM32m */ >+ }, >+ { /* 759 */ >+ 37, >+ /* FCOM64m */ >+ }, >+ { /* 760 */ >+ 36, >+ /* FCOMP32m */ >+ }, >+ { /* 761 */ >+ 37, >+ /* FCOMP64m */ >+ }, >+ { /* 762 */ >+ 0, >+ /* FCOMPP */ >+ }, >+ { /* 763 */ >+ 0, >+ /* FDECSTP */ >+ }, >+ { /* 764 */ >+ 0, >+ /* FEMMS */ >+ }, >+ { /* 765 */ >+ 39, >+ /* FFREE */ >+ }, >+ { /* 766 */ >+ 38, >+ /* FICOM16m */ >+ }, >+ { /* 767 */ >+ 38, >+ /* FICOM32m */ >+ }, >+ { /* 768 */ >+ 38, >+ /* FICOMP16m */ >+ }, >+ { /* 769 */ >+ 38, >+ /* FICOMP32m */ >+ }, >+ { /* 770 */ >+ 0, >+ /* FINCSTP */ >+ }, >+ { /* 771 */ >+ 38, >+ /* FLDCW16m */ >+ }, >+ { /* 772 */ >+ 36, >+ /* FLDENVm */ >+ }, >+ { /* 773 */ >+ 0, >+ /* FLDL2E */ >+ }, >+ { /* 774 */ >+ 0, >+ /* FLDL2T */ >+ }, >+ { /* 775 */ >+ 0, >+ /* FLDLG2 */ >+ }, >+ { /* 776 */ >+ 0, >+ /* FLDLN2 */ >+ }, >+ { /* 777 */ >+ 0, >+ /* FLDPI */ >+ }, >+ { /* 778 */ >+ 0, >+ /* FNCLEX */ >+ }, >+ { /* 779 */ >+ 0, >+ /* FNINIT */ >+ }, >+ { /* 780 */ >+ 0, >+ /* FNOP */ >+ }, >+ { /* 781 */ >+ 38, >+ /* FNSTCW16m */ >+ }, >+ { /* 782 */ >+ 0, >+ /* FNSTSW16r */ >+ }, >+ { /* 783 */ >+ 36, >+ /* FNSTSWm */ >+ }, >+ { /* 784 */ >+ 0, >+ /* */ >+ }, >+ { /* 785 */ >+ 0, >+ /* */ >+ }, >+ { /* 786 */ >+ 0, >+ /* */ >+ }, >+ { /* 787 */ >+ 0, >+ /* */ >+ }, >+ { /* 788 */ >+ 0, >+ /* */ >+ }, >+ { /* 789 */ >+ 0, >+ /* */ >+ }, >+ { /* 790 */ >+ 0, >+ /* */ >+ }, >+ { /* 791 */ >+ 0, >+ /* */ >+ }, >+ { /* 792 */ >+ 0, >+ /* */ >+ }, >+ { /* 793 */ >+ 0, >+ /* FPATAN */ >+ }, >+ { /* 794 */ >+ 0, >+ /* FPREM */ >+ }, >+ { /* 795 */ >+ 0, >+ /* FPREM1 */ >+ }, >+ { /* 796 */ >+ 0, >+ /* FPTAN */ >+ }, >+ { /* 797 */ >+ 0, >+ /* FRNDINT */ >+ }, >+ { /* 798 */ >+ 36, >+ /* FRSTORm */ >+ }, >+ { /* 799 */ >+ 36, >+ /* FSAVEm */ >+ }, >+ { /* 800 */ >+ 0, >+ /* FSCALE */ >+ }, >+ { /* 801 */ >+ 0, >+ /* FSETPM */ >+ }, >+ { /* 802 */ >+ 0, >+ /* FSINCOS */ >+ }, >+ { /* 803 */ >+ 36, >+ /* FSTENVm */ >+ }, >+ { /* 804 */ >+ 0, >+ /* FXAM */ >+ }, >+ { /* 805 */ >+ 140, >+ /* FXRSTOR */ >+ }, >+ { /* 806 */ >+ 140, >+ /* FXRSTOR64 */ >+ }, >+ { /* 807 */ >+ 140, >+ /* FXSAVE */ >+ }, >+ { /* 808 */ >+ 140, >+ /* FXSAVE64 */ >+ }, >+ { /* 809 */ >+ 0, >+ /* FXTRACT */ >+ }, >+ { /* 810 */ >+ 0, >+ /* FYL2X */ >+ }, >+ { /* 811 */ >+ 0, >+ /* FYL2XP1 */ >+ }, >+ { /* 812 */ >+ 0, >+ /* */ >+ }, >+ { /* 813 */ >+ 0, >+ /* */ >+ }, >+ { /* 814 */ >+ 0, >+ /* */ >+ }, >+ { /* 815 */ >+ 0, >+ /* */ >+ }, >+ { /* 816 */ >+ 0, >+ /* */ >+ }, >+ { /* 817 */ >+ 0, >+ /* */ >+ }, >+ { /* 818 */ >+ 0, >+ /* */ >+ }, >+ { /* 819 */ >+ 0, >+ /* */ >+ }, >+ { /* 820 */ >+ 0, >+ /* */ >+ }, >+ { /* 821 */ >+ 0, >+ /* */ >+ }, >+ { /* 822 */ >+ 0, >+ /* */ >+ }, >+ { /* 823 */ >+ 0, >+ /* */ >+ }, >+ { /* 824 */ >+ 0, >+ /* */ >+ }, >+ { /* 825 */ >+ 0, >+ /* */ >+ }, >+ { /* 826 */ >+ 0, >+ /* */ >+ }, >+ { /* 827 */ >+ 0, >+ /* */ >+ }, >+ { /* 828 */ >+ 0, >+ /* */ >+ }, >+ { /* 829 */ >+ 0, >+ /* */ >+ }, >+ { /* 830 */ >+ 0, >+ /* */ >+ }, >+ { /* 831 */ >+ 0, >+ /* */ >+ }, >+ { /* 832 */ >+ 0, >+ /* */ >+ }, >+ { /* 833 */ >+ 0, >+ /* */ >+ }, >+ { /* 834 */ >+ 0, >+ /* GETSEC */ >+ }, >+ { /* 835 */ >+ 30, >+ /* HADDPDrm */ >+ }, >+ { /* 836 */ >+ 31, >+ /* HADDPDrr */ >+ }, >+ { /* 837 */ >+ 30, >+ /* HADDPSrm */ >+ }, >+ { /* 838 */ >+ 31, >+ /* HADDPSrr */ >+ }, >+ { /* 839 */ >+ 0, >+ /* HLT */ >+ }, >+ { /* 840 */ >+ 30, >+ /* HSUBPDrm */ >+ }, >+ { /* 841 */ >+ 31, >+ /* HSUBPDrr */ >+ }, >+ { /* 842 */ >+ 30, >+ /* HSUBPSrm */ >+ }, >+ { /* 843 */ >+ 31, >+ /* HSUBPSrr */ >+ }, >+ { /* 844 */ >+ 38, >+ /* IDIV16m */ >+ }, >+ { /* 845 */ >+ 77, >+ /* IDIV16r */ >+ }, >+ { /* 846 */ >+ 38, >+ /* IDIV32m */ >+ }, >+ { /* 847 */ >+ 77, >+ /* IDIV32r */ >+ }, >+ { /* 848 */ >+ 38, >+ /* IDIV64m */ >+ }, >+ { /* 849 */ >+ 79, >+ /* IDIV64r */ >+ }, >+ { /* 850 */ >+ 82, >+ /* IDIV8m */ >+ }, >+ { /* 851 */ >+ 130, >+ /* IDIV8r */ >+ }, >+ { /* 852 */ >+ 38, >+ /* ILD_F16m */ >+ }, >+ { /* 853 */ >+ 38, >+ /* ILD_F32m */ >+ }, >+ { /* 854 */ >+ 38, >+ /* ILD_F64m */ >+ }, >+ { /* 855 */ >+ 0, >+ /* */ >+ }, >+ { /* 856 */ >+ 0, >+ /* */ >+ }, >+ { /* 857 */ >+ 0, >+ /* */ >+ }, >+ { /* 858 */ >+ 0, >+ /* */ >+ }, >+ { /* 859 */ >+ 0, >+ /* */ >+ }, >+ { /* 860 */ >+ 0, >+ /* */ >+ }, >+ { /* 861 */ >+ 0, >+ /* */ >+ }, >+ { /* 862 */ >+ 0, >+ /* */ >+ }, >+ { /* 863 */ >+ 0, >+ /* */ >+ }, >+ { /* 864 */ >+ 38, >+ /* IMUL16m */ >+ }, >+ { /* 865 */ >+ 77, >+ /* IMUL16r */ >+ }, >+ { /* 866 */ >+ 8, >+ /* IMUL16rm */ >+ }, >+ { /* 867 */ >+ 141, >+ /* IMUL16rmi */ >+ }, >+ { /* 868 */ >+ 142, >+ /* IMUL16rmi8 */ >+ }, >+ { /* 869 */ >+ 10, >+ /* IMUL16rr */ >+ }, >+ { /* 870 */ >+ 143, >+ /* IMUL16rri */ >+ }, >+ { /* 871 */ >+ 144, >+ /* IMUL16rri8 */ >+ }, >+ { /* 872 */ >+ 38, >+ /* IMUL32m */ >+ }, >+ { /* 873 */ >+ 77, >+ /* IMUL32r */ >+ }, >+ { /* 874 */ >+ 8, >+ /* IMUL32rm */ >+ }, >+ { /* 875 */ >+ 141, >+ /* IMUL32rmi */ >+ }, >+ { /* 876 */ >+ 145, >+ /* IMUL32rmi8 */ >+ }, >+ { /* 877 */ >+ 10, >+ /* IMUL32rr */ >+ }, >+ { /* 878 */ >+ 143, >+ /* IMUL32rri */ >+ }, >+ { /* 879 */ >+ 146, >+ /* IMUL32rri8 */ >+ }, >+ { /* 880 */ >+ 38, >+ /* IMUL64m */ >+ }, >+ { /* 881 */ >+ 79, >+ /* IMUL64r */ >+ }, >+ { /* 882 */ >+ 19, >+ /* IMUL64rm */ >+ }, >+ { /* 883 */ >+ 60, >+ /* IMUL64rmi32 */ >+ }, >+ { /* 884 */ >+ 147, >+ /* IMUL64rmi8 */ >+ }, >+ { /* 885 */ >+ 21, >+ /* IMUL64rr */ >+ }, >+ { /* 886 */ >+ 61, >+ /* IMUL64rri32 */ >+ }, >+ { /* 887 */ >+ 148, >+ /* IMUL64rri8 */ >+ }, >+ { /* 888 */ >+ 82, >+ /* IMUL8m */ >+ }, >+ { /* 889 */ >+ 130, >+ /* IMUL8r */ >+ }, >+ { /* 890 */ >+ 1, >+ /* IN16ri */ >+ }, >+ { /* 891 */ >+ 0, >+ /* IN16rr */ >+ }, >+ { /* 892 */ >+ 1, >+ /* IN32ri */ >+ }, >+ { /* 893 */ >+ 0, >+ /* IN32rr */ >+ }, >+ { /* 894 */ >+ 1, >+ /* IN8ri */ >+ }, >+ { /* 895 */ >+ 0, >+ /* IN8rr */ >+ }, >+ { /* 896 */ >+ 38, >+ /* INC16m */ >+ }, >+ { /* 897 */ >+ 70, >+ /* INC16r */ >+ }, >+ { /* 898 */ >+ 127, >+ /* INC32_16r */ >+ }, >+ { /* 899 */ >+ 127, >+ /* INC32_32r */ >+ }, >+ { /* 900 */ >+ 38, >+ /* INC32m */ >+ }, >+ { /* 901 */ >+ 70, >+ /* INC32r */ >+ }, >+ { /* 902 */ >+ 38, >+ /* INC64_16m */ >+ }, >+ { /* 903 */ >+ 127, >+ /* INC64_16r */ >+ }, >+ { /* 904 */ >+ 38, >+ /* INC64_32m */ >+ }, >+ { /* 905 */ >+ 127, >+ /* INC64_32r */ >+ }, >+ { /* 906 */ >+ 38, >+ /* INC64m */ >+ }, >+ { /* 907 */ >+ 128, >+ /* INC64r */ >+ }, >+ { /* 908 */ >+ 82, >+ /* INC8m */ >+ }, >+ { /* 909 */ >+ 129, >+ /* INC8r */ >+ }, >+ { /* 910 */ >+ 149, >+ /* INSB */ >+ }, >+ { /* 911 */ >+ 150, >+ /* INSERTPSrm */ >+ }, >+ { /* 912 */ >+ 67, >+ /* INSERTPSrr */ >+ }, >+ { /* 913 */ >+ 31, >+ /* INSERTQ */ >+ }, >+ { /* 914 */ >+ 151, >+ /* INSERTQI */ >+ }, >+ { /* 915 */ >+ 152, >+ /* INSL */ >+ }, >+ { /* 916 */ >+ 153, >+ /* INSW */ >+ }, >+ { /* 917 */ >+ 1, >+ /* INT */ >+ }, >+ { /* 918 */ >+ 0, >+ /* INT1 */ >+ }, >+ { /* 919 */ >+ 0, >+ /* INT3 */ >+ }, >+ { /* 920 */ >+ 0, >+ /* INTO */ >+ }, >+ { /* 921 */ >+ 0, >+ /* INVD */ >+ }, >+ { /* 922 */ >+ 154, >+ /* INVEPT32 */ >+ }, >+ { /* 923 */ >+ 155, >+ /* INVEPT64 */ >+ }, >+ { /* 924 */ >+ 82, >+ /* INVLPG */ >+ }, >+ { /* 925 */ >+ 0, >+ /* INVLPGA32 */ >+ }, >+ { /* 926 */ >+ 0, >+ /* INVLPGA64 */ >+ }, >+ { /* 927 */ >+ 154, >+ /* INVPCID32 */ >+ }, >+ { /* 928 */ >+ 155, >+ /* INVPCID64 */ >+ }, >+ { /* 929 */ >+ 154, >+ /* INVVPID32 */ >+ }, >+ { /* 930 */ >+ 155, >+ /* INVVPID64 */ >+ }, >+ { /* 931 */ >+ 0, >+ /* IRET16 */ >+ }, >+ { /* 932 */ >+ 0, >+ /* IRET32 */ >+ }, >+ { /* 933 */ >+ 0, >+ /* IRET64 */ >+ }, >+ { /* 934 */ >+ 38, >+ /* ISTT_FP16m */ >+ }, >+ { /* 935 */ >+ 38, >+ /* ISTT_FP32m */ >+ }, >+ { /* 936 */ >+ 38, >+ /* ISTT_FP64m */ >+ }, >+ { /* 937 */ >+ 0, >+ /* */ >+ }, >+ { /* 938 */ >+ 0, >+ /* */ >+ }, >+ { /* 939 */ >+ 0, >+ /* */ >+ }, >+ { /* 940 */ >+ 0, >+ /* */ >+ }, >+ { /* 941 */ >+ 0, >+ /* */ >+ }, >+ { /* 942 */ >+ 0, >+ /* */ >+ }, >+ { /* 943 */ >+ 0, >+ /* */ >+ }, >+ { /* 944 */ >+ 0, >+ /* */ >+ }, >+ { /* 945 */ >+ 0, >+ /* */ >+ }, >+ { /* 946 */ >+ 38, >+ /* IST_F16m */ >+ }, >+ { /* 947 */ >+ 38, >+ /* IST_F32m */ >+ }, >+ { /* 948 */ >+ 38, >+ /* IST_FP16m */ >+ }, >+ { /* 949 */ >+ 38, >+ /* IST_FP32m */ >+ }, >+ { /* 950 */ >+ 38, >+ /* IST_FP64m */ >+ }, >+ { /* 951 */ >+ 0, >+ /* */ >+ }, >+ { /* 952 */ >+ 0, >+ /* */ >+ }, >+ { /* 953 */ >+ 0, >+ /* */ >+ }, >+ { /* 954 */ >+ 0, >+ /* */ >+ }, >+ { /* 955 */ >+ 0, >+ /* */ >+ }, >+ { /* 956 */ >+ 0, >+ /* */ >+ }, >+ { /* 957 */ >+ 0, >+ /* */ >+ }, >+ { /* 958 */ >+ 0, >+ /* */ >+ }, >+ { /* 959 */ >+ 0, >+ /* */ >+ }, >+ { /* 960 */ >+ 0, >+ /* */ >+ }, >+ { /* 961 */ >+ 0, >+ /* */ >+ }, >+ { /* 962 */ >+ 0, >+ /* */ >+ }, >+ { /* 963 */ >+ 0, >+ /* */ >+ }, >+ { /* 964 */ >+ 0, >+ /* */ >+ }, >+ { /* 965 */ >+ 0, >+ /* */ >+ }, >+ { /* 966 */ >+ 0, >+ /* */ >+ }, >+ { /* 967 */ >+ 0, >+ /* */ >+ }, >+ { /* 968 */ >+ 0, >+ /* */ >+ }, >+ { /* 969 */ >+ 0, >+ /* */ >+ }, >+ { /* 970 */ >+ 0, >+ /* */ >+ }, >+ { /* 971 */ >+ 0, >+ /* */ >+ }, >+ { /* 972 */ >+ 0, >+ /* */ >+ }, >+ { /* 973 */ >+ 0, >+ /* */ >+ }, >+ { /* 974 */ >+ 0, >+ /* */ >+ }, >+ { /* 975 */ >+ 0, >+ /* */ >+ }, >+ { /* 976 */ >+ 0, >+ /* */ >+ }, >+ { /* 977 */ >+ 0, >+ /* */ >+ }, >+ { /* 978 */ >+ 0, >+ /* */ >+ }, >+ { /* 979 */ >+ 0, >+ /* */ >+ }, >+ { /* 980 */ >+ 0, >+ /* */ >+ }, >+ { /* 981 */ >+ 0, >+ /* */ >+ }, >+ { /* 982 */ >+ 0, >+ /* */ >+ }, >+ { /* 983 */ >+ 0, >+ /* */ >+ }, >+ { /* 984 */ >+ 0, >+ /* */ >+ }, >+ { /* 985 */ >+ 0, >+ /* */ >+ }, >+ { /* 986 */ >+ 0, >+ /* */ >+ }, >+ { /* 987 */ >+ 0, >+ /* */ >+ }, >+ { /* 988 */ >+ 0, >+ /* */ >+ }, >+ { /* 989 */ >+ 0, >+ /* */ >+ }, >+ { /* 990 */ >+ 0, >+ /* */ >+ }, >+ { /* 991 */ >+ 0, >+ /* */ >+ }, >+ { /* 992 */ >+ 0, >+ /* */ >+ }, >+ { /* 993 */ >+ 0, >+ /* */ >+ }, >+ { /* 994 */ >+ 0, >+ /* */ >+ }, >+ { /* 995 */ >+ 0, >+ /* */ >+ }, >+ { /* 996 */ >+ 0, >+ /* */ >+ }, >+ { /* 997 */ >+ 0, >+ /* */ >+ }, >+ { /* 998 */ >+ 0, >+ /* */ >+ }, >+ { /* 999 */ >+ 0, >+ /* */ >+ }, >+ { /* 1000 */ >+ 0, >+ /* */ >+ }, >+ { /* 1001 */ >+ 0, >+ /* */ >+ }, >+ { /* 1002 */ >+ 0, >+ /* */ >+ }, >+ { /* 1003 */ >+ 0, >+ /* */ >+ }, >+ { /* 1004 */ >+ 0, >+ /* */ >+ }, >+ { /* 1005 */ >+ 0, >+ /* */ >+ }, >+ { /* 1006 */ >+ 0, >+ /* */ >+ }, >+ { /* 1007 */ >+ 0, >+ /* */ >+ }, >+ { /* 1008 */ >+ 0, >+ /* */ >+ }, >+ { /* 1009 */ >+ 0, >+ /* */ >+ }, >+ { /* 1010 */ >+ 0, >+ /* */ >+ }, >+ { /* 1011 */ >+ 0, >+ /* */ >+ }, >+ { /* 1012 */ >+ 0, >+ /* */ >+ }, >+ { /* 1013 */ >+ 0, >+ /* */ >+ }, >+ { /* 1014 */ >+ 0, >+ /* */ >+ }, >+ { /* 1015 */ >+ 0, >+ /* */ >+ }, >+ { /* 1016 */ >+ 0, >+ /* */ >+ }, >+ { /* 1017 */ >+ 0, >+ /* */ >+ }, >+ { /* 1018 */ >+ 0, >+ /* */ >+ }, >+ { /* 1019 */ >+ 0, >+ /* */ >+ }, >+ { /* 1020 */ >+ 0, >+ /* */ >+ }, >+ { /* 1021 */ >+ 0, >+ /* */ >+ }, >+ { /* 1022 */ >+ 0, >+ /* */ >+ }, >+ { /* 1023 */ >+ 0, >+ /* */ >+ }, >+ { /* 1024 */ >+ 0, >+ /* */ >+ }, >+ { /* 1025 */ >+ 0, >+ /* */ >+ }, >+ { /* 1026 */ >+ 0, >+ /* */ >+ }, >+ { /* 1027 */ >+ 0, >+ /* */ >+ }, >+ { /* 1028 */ >+ 0, >+ /* */ >+ }, >+ { /* 1029 */ >+ 0, >+ /* */ >+ }, >+ { /* 1030 */ >+ 0, >+ /* */ >+ }, >+ { /* 1031 */ >+ 0, >+ /* */ >+ }, >+ { /* 1032 */ >+ 0, >+ /* */ >+ }, >+ { /* 1033 */ >+ 0, >+ /* */ >+ }, >+ { /* 1034 */ >+ 0, >+ /* */ >+ }, >+ { /* 1035 */ >+ 0, >+ /* */ >+ }, >+ { /* 1036 */ >+ 0, >+ /* */ >+ }, >+ { /* 1037 */ >+ 0, >+ /* */ >+ }, >+ { /* 1038 */ >+ 0, >+ /* */ >+ }, >+ { /* 1039 */ >+ 0, >+ /* */ >+ }, >+ { /* 1040 */ >+ 0, >+ /* */ >+ }, >+ { /* 1041 */ >+ 0, >+ /* */ >+ }, >+ { /* 1042 */ >+ 0, >+ /* */ >+ }, >+ { /* 1043 */ >+ 0, >+ /* */ >+ }, >+ { /* 1044 */ >+ 0, >+ /* */ >+ }, >+ { /* 1045 */ >+ 0, >+ /* */ >+ }, >+ { /* 1046 */ >+ 0, >+ /* */ >+ }, >+ { /* 1047 */ >+ 0, >+ /* */ >+ }, >+ { /* 1048 */ >+ 0, >+ /* */ >+ }, >+ { /* 1049 */ >+ 0, >+ /* */ >+ }, >+ { /* 1050 */ >+ 0, >+ /* */ >+ }, >+ { /* 1051 */ >+ 0, >+ /* */ >+ }, >+ { /* 1052 */ >+ 0, >+ /* */ >+ }, >+ { /* 1053 */ >+ 0, >+ /* */ >+ }, >+ { /* 1054 */ >+ 0, >+ /* */ >+ }, >+ { /* 1055 */ >+ 0, >+ /* */ >+ }, >+ { /* 1056 */ >+ 0, >+ /* */ >+ }, >+ { /* 1057 */ >+ 0, >+ /* */ >+ }, >+ { /* 1058 */ >+ 0, >+ /* */ >+ }, >+ { /* 1059 */ >+ 0, >+ /* */ >+ }, >+ { /* 1060 */ >+ 0, >+ /* */ >+ }, >+ { /* 1061 */ >+ 0, >+ /* */ >+ }, >+ { /* 1062 */ >+ 0, >+ /* */ >+ }, >+ { /* 1063 */ >+ 0, >+ /* */ >+ }, >+ { /* 1064 */ >+ 0, >+ /* */ >+ }, >+ { /* 1065 */ >+ 156, >+ /* JAE_1 */ >+ }, >+ { /* 1066 */ >+ 157, >+ /* JAE_2 */ >+ }, >+ { /* 1067 */ >+ 157, >+ /* JAE_4 */ >+ }, >+ { /* 1068 */ >+ 156, >+ /* JA_1 */ >+ }, >+ { /* 1069 */ >+ 157, >+ /* JA_2 */ >+ }, >+ { /* 1070 */ >+ 157, >+ /* JA_4 */ >+ }, >+ { /* 1071 */ >+ 156, >+ /* JBE_1 */ >+ }, >+ { /* 1072 */ >+ 157, >+ /* JBE_2 */ >+ }, >+ { /* 1073 */ >+ 157, >+ /* JBE_4 */ >+ }, >+ { /* 1074 */ >+ 156, >+ /* JB_1 */ >+ }, >+ { /* 1075 */ >+ 157, >+ /* JB_2 */ >+ }, >+ { /* 1076 */ >+ 157, >+ /* JB_4 */ >+ }, >+ { /* 1077 */ >+ 156, >+ /* JCXZ */ >+ }, >+ { /* 1078 */ >+ 156, >+ /* JECXZ_32 */ >+ }, >+ { /* 1079 */ >+ 156, >+ /* JECXZ_64 */ >+ }, >+ { /* 1080 */ >+ 156, >+ /* JE_1 */ >+ }, >+ { /* 1081 */ >+ 157, >+ /* JE_2 */ >+ }, >+ { /* 1082 */ >+ 157, >+ /* JE_4 */ >+ }, >+ { /* 1083 */ >+ 156, >+ /* JGE_1 */ >+ }, >+ { /* 1084 */ >+ 157, >+ /* JGE_2 */ >+ }, >+ { /* 1085 */ >+ 157, >+ /* JGE_4 */ >+ }, >+ { /* 1086 */ >+ 156, >+ /* JG_1 */ >+ }, >+ { /* 1087 */ >+ 157, >+ /* JG_2 */ >+ }, >+ { /* 1088 */ >+ 157, >+ /* JG_4 */ >+ }, >+ { /* 1089 */ >+ 156, >+ /* JLE_1 */ >+ }, >+ { /* 1090 */ >+ 157, >+ /* JLE_2 */ >+ }, >+ { /* 1091 */ >+ 157, >+ /* JLE_4 */ >+ }, >+ { /* 1092 */ >+ 156, >+ /* JL_1 */ >+ }, >+ { /* 1093 */ >+ 157, >+ /* JL_2 */ >+ }, >+ { /* 1094 */ >+ 157, >+ /* JL_4 */ >+ }, >+ { /* 1095 */ >+ 38, >+ /* JMP16m */ >+ }, >+ { /* 1096 */ >+ 77, >+ /* JMP16r */ >+ }, >+ { /* 1097 */ >+ 38, >+ /* JMP32m */ >+ }, >+ { /* 1098 */ >+ 77, >+ /* JMP32r */ >+ }, >+ { /* 1099 */ >+ 38, >+ /* JMP64m */ >+ }, >+ { /* 1100 */ >+ 79, >+ /* JMP64r */ >+ }, >+ { /* 1101 */ >+ 156, >+ /* JMP_1 */ >+ }, >+ { /* 1102 */ >+ 157, >+ /* JMP_2 */ >+ }, >+ { /* 1103 */ >+ 157, >+ /* JMP_4 */ >+ }, >+ { /* 1104 */ >+ 156, >+ /* JNE_1 */ >+ }, >+ { /* 1105 */ >+ 157, >+ /* JNE_2 */ >+ }, >+ { /* 1106 */ >+ 157, >+ /* JNE_4 */ >+ }, >+ { /* 1107 */ >+ 156, >+ /* JNO_1 */ >+ }, >+ { /* 1108 */ >+ 157, >+ /* JNO_2 */ >+ }, >+ { /* 1109 */ >+ 157, >+ /* JNO_4 */ >+ }, >+ { /* 1110 */ >+ 156, >+ /* JNP_1 */ >+ }, >+ { /* 1111 */ >+ 157, >+ /* JNP_2 */ >+ }, >+ { /* 1112 */ >+ 157, >+ /* JNP_4 */ >+ }, >+ { /* 1113 */ >+ 156, >+ /* JNS_1 */ >+ }, >+ { /* 1114 */ >+ 157, >+ /* JNS_2 */ >+ }, >+ { /* 1115 */ >+ 157, >+ /* JNS_4 */ >+ }, >+ { /* 1116 */ >+ 156, >+ /* JO_1 */ >+ }, >+ { /* 1117 */ >+ 157, >+ /* JO_2 */ >+ }, >+ { /* 1118 */ >+ 157, >+ /* JO_4 */ >+ }, >+ { /* 1119 */ >+ 156, >+ /* JP_1 */ >+ }, >+ { /* 1120 */ >+ 157, >+ /* JP_2 */ >+ }, >+ { /* 1121 */ >+ 157, >+ /* JP_4 */ >+ }, >+ { /* 1122 */ >+ 156, >+ /* JRCXZ */ >+ }, >+ { /* 1123 */ >+ 156, >+ /* JS_1 */ >+ }, >+ { /* 1124 */ >+ 157, >+ /* JS_2 */ >+ }, >+ { /* 1125 */ >+ 157, >+ /* JS_4 */ >+ }, >+ { /* 1126 */ >+ 158, >+ /* KANDBrr */ >+ }, >+ { /* 1127 */ >+ 159, >+ /* KANDDrr */ >+ }, >+ { /* 1128 */ >+ 158, >+ /* KANDNBrr */ >+ }, >+ { /* 1129 */ >+ 159, >+ /* KANDNDrr */ >+ }, >+ { /* 1130 */ >+ 160, >+ /* KANDNQrr */ >+ }, >+ { /* 1131 */ >+ 161, >+ /* KANDNWrr */ >+ }, >+ { /* 1132 */ >+ 160, >+ /* KANDQrr */ >+ }, >+ { /* 1133 */ >+ 161, >+ /* KANDWrr */ >+ }, >+ { /* 1134 */ >+ 162, >+ /* KMOVBkk */ >+ }, >+ { /* 1135 */ >+ 163, >+ /* KMOVBkm */ >+ }, >+ { /* 1136 */ >+ 164, >+ /* KMOVBkr */ >+ }, >+ { /* 1137 */ >+ 165, >+ /* KMOVBmk */ >+ }, >+ { /* 1138 */ >+ 166, >+ /* KMOVBrk */ >+ }, >+ { /* 1139 */ >+ 167, >+ /* KMOVDkk */ >+ }, >+ { /* 1140 */ >+ 168, >+ /* KMOVDkm */ >+ }, >+ { /* 1141 */ >+ 169, >+ /* KMOVDkr */ >+ }, >+ { /* 1142 */ >+ 170, >+ /* KMOVDmk */ >+ }, >+ { /* 1143 */ >+ 171, >+ /* KMOVDrk */ >+ }, >+ { /* 1144 */ >+ 172, >+ /* KMOVQkk */ >+ }, >+ { /* 1145 */ >+ 173, >+ /* KMOVQkm */ >+ }, >+ { /* 1146 */ >+ 174, >+ /* KMOVQkr */ >+ }, >+ { /* 1147 */ >+ 175, >+ /* KMOVQmk */ >+ }, >+ { /* 1148 */ >+ 176, >+ /* KMOVQrk */ >+ }, >+ { /* 1149 */ >+ 177, >+ /* KMOVWkk */ >+ }, >+ { /* 1150 */ >+ 178, >+ /* KMOVWkm */ >+ }, >+ { /* 1151 */ >+ 179, >+ /* KMOVWkr */ >+ }, >+ { /* 1152 */ >+ 180, >+ /* KMOVWmk */ >+ }, >+ { /* 1153 */ >+ 181, >+ /* KMOVWrk */ >+ }, >+ { /* 1154 */ >+ 162, >+ /* KNOTBrr */ >+ }, >+ { /* 1155 */ >+ 167, >+ /* KNOTDrr */ >+ }, >+ { /* 1156 */ >+ 172, >+ /* KNOTQrr */ >+ }, >+ { /* 1157 */ >+ 177, >+ /* KNOTWrr */ >+ }, >+ { /* 1158 */ >+ 158, >+ /* KORBrr */ >+ }, >+ { /* 1159 */ >+ 159, >+ /* KORDrr */ >+ }, >+ { /* 1160 */ >+ 160, >+ /* KORQrr */ >+ }, >+ { /* 1161 */ >+ 177, >+ /* KORTESTWrr */ >+ }, >+ { /* 1162 */ >+ 161, >+ /* KORWrr */ >+ }, >+ { /* 1163 */ >+ 0, >+ /* */ >+ }, >+ { /* 1164 */ >+ 0, >+ /* */ >+ }, >+ { /* 1165 */ >+ 0, >+ /* */ >+ }, >+ { /* 1166 */ >+ 0, >+ /* */ >+ }, >+ { /* 1167 */ >+ 182, >+ /* KSHIFTLWri */ >+ }, >+ { /* 1168 */ >+ 182, >+ /* KSHIFTRWri */ >+ }, >+ { /* 1169 */ >+ 161, >+ /* KUNPCKBWrr */ >+ }, >+ { /* 1170 */ >+ 158, >+ /* KXNORBrr */ >+ }, >+ { /* 1171 */ >+ 159, >+ /* KXNORDrr */ >+ }, >+ { /* 1172 */ >+ 160, >+ /* KXNORQrr */ >+ }, >+ { /* 1173 */ >+ 161, >+ /* KXNORWrr */ >+ }, >+ { /* 1174 */ >+ 158, >+ /* KXORBrr */ >+ }, >+ { /* 1175 */ >+ 159, >+ /* KXORDrr */ >+ }, >+ { /* 1176 */ >+ 160, >+ /* KXORQrr */ >+ }, >+ { /* 1177 */ >+ 161, >+ /* KXORWrr */ >+ }, >+ { /* 1178 */ >+ 0, >+ /* LAHF */ >+ }, >+ { /* 1179 */ >+ 68, >+ /* LAR16rm */ >+ }, >+ { /* 1180 */ >+ 69, >+ /* LAR16rr */ >+ }, >+ { /* 1181 */ >+ 68, >+ /* LAR32rm */ >+ }, >+ { /* 1182 */ >+ 69, >+ /* LAR32rr */ >+ }, >+ { /* 1183 */ >+ 42, >+ /* LAR64rm */ >+ }, >+ { /* 1184 */ >+ 183, >+ /* LAR64rr */ >+ }, >+ { /* 1185 */ >+ 0, >+ /* */ >+ }, >+ { /* 1186 */ >+ 0, >+ /* */ >+ }, >+ { /* 1187 */ >+ 0, >+ /* */ >+ }, >+ { /* 1188 */ >+ 0, >+ /* */ >+ }, >+ { /* 1189 */ >+ 0, >+ /* */ >+ }, >+ { /* 1190 */ >+ 0, >+ /* */ >+ }, >+ { /* 1191 */ >+ 44, >+ /* LDDQUrm */ >+ }, >+ { /* 1192 */ >+ 38, >+ /* LDMXCSR */ >+ }, >+ { /* 1193 */ >+ 184, >+ /* LDS16rm */ >+ }, >+ { /* 1194 */ >+ 185, >+ /* LDS32rm */ >+ }, >+ { /* 1195 */ >+ 0, >+ /* LD_F0 */ >+ }, >+ { /* 1196 */ >+ 0, >+ /* LD_F1 */ >+ }, >+ { /* 1197 */ >+ 36, >+ /* LD_F32m */ >+ }, >+ { /* 1198 */ >+ 37, >+ /* LD_F64m */ >+ }, >+ { /* 1199 */ >+ 186, >+ /* LD_F80m */ >+ }, >+ { /* 1200 */ >+ 0, >+ /* */ >+ }, >+ { /* 1201 */ >+ 0, >+ /* */ >+ }, >+ { /* 1202 */ >+ 0, >+ /* */ >+ }, >+ { /* 1203 */ >+ 0, >+ /* */ >+ }, >+ { /* 1204 */ >+ 0, >+ /* */ >+ }, >+ { /* 1205 */ >+ 0, >+ /* */ >+ }, >+ { /* 1206 */ >+ 0, >+ /* */ >+ }, >+ { /* 1207 */ >+ 0, >+ /* */ >+ }, >+ { /* 1208 */ >+ 0, >+ /* */ >+ }, >+ { /* 1209 */ >+ 0, >+ /* */ >+ }, >+ { /* 1210 */ >+ 0, >+ /* */ >+ }, >+ { /* 1211 */ >+ 0, >+ /* */ >+ }, >+ { /* 1212 */ >+ 39, >+ /* LD_Frr */ >+ }, >+ { /* 1213 */ >+ 68, >+ /* LEA16r */ >+ }, >+ { /* 1214 */ >+ 68, >+ /* LEA32r */ >+ }, >+ { /* 1215 */ >+ 187, >+ /* LEA64_32r */ >+ }, >+ { /* 1216 */ >+ 188, >+ /* LEA64r */ >+ }, >+ { /* 1217 */ >+ 0, >+ /* LEAVE */ >+ }, >+ { /* 1218 */ >+ 0, >+ /* LEAVE64 */ >+ }, >+ { /* 1219 */ >+ 184, >+ /* LES16rm */ >+ }, >+ { /* 1220 */ >+ 185, >+ /* LES32rm */ >+ }, >+ { /* 1221 */ >+ 0, >+ /* LFENCE */ >+ }, >+ { /* 1222 */ >+ 184, >+ /* LFS16rm */ >+ }, >+ { /* 1223 */ >+ 185, >+ /* LFS32rm */ >+ }, >+ { /* 1224 */ >+ 189, >+ /* LFS64rm */ >+ }, >+ { /* 1225 */ >+ 138, >+ /* LGDT16m */ >+ }, >+ { /* 1226 */ >+ 138, >+ /* LGDT32m */ >+ }, >+ { /* 1227 */ >+ 139, >+ /* LGDT64m */ >+ }, >+ { /* 1228 */ >+ 184, >+ /* LGS16rm */ >+ }, >+ { /* 1229 */ >+ 185, >+ /* LGS32rm */ >+ }, >+ { /* 1230 */ >+ 189, >+ /* LGS64rm */ >+ }, >+ { /* 1231 */ >+ 138, >+ /* LIDT16m */ >+ }, >+ { /* 1232 */ >+ 138, >+ /* LIDT32m */ >+ }, >+ { /* 1233 */ >+ 139, >+ /* LIDT64m */ >+ }, >+ { /* 1234 */ >+ 38, >+ /* LLDT16m */ >+ }, >+ { /* 1235 */ >+ 190, >+ /* LLDT16r */ >+ }, >+ { /* 1236 */ >+ 38, >+ /* LMSW16m */ >+ }, >+ { /* 1237 */ >+ 190, >+ /* LMSW16r */ >+ }, >+ { /* 1238 */ >+ 0, >+ /* */ >+ }, >+ { /* 1239 */ >+ 0, >+ /* */ >+ }, >+ { /* 1240 */ >+ 0, >+ /* */ >+ }, >+ { /* 1241 */ >+ 0, >+ /* */ >+ }, >+ { /* 1242 */ >+ 0, >+ /* */ >+ }, >+ { /* 1243 */ >+ 0, >+ /* */ >+ }, >+ { /* 1244 */ >+ 0, >+ /* */ >+ }, >+ { /* 1245 */ >+ 0, >+ /* */ >+ }, >+ { /* 1246 */ >+ 0, >+ /* */ >+ }, >+ { /* 1247 */ >+ 0, >+ /* */ >+ }, >+ { /* 1248 */ >+ 0, >+ /* */ >+ }, >+ { /* 1249 */ >+ 0, >+ /* */ >+ }, >+ { /* 1250 */ >+ 0, >+ /* */ >+ }, >+ { /* 1251 */ >+ 0, >+ /* */ >+ }, >+ { /* 1252 */ >+ 0, >+ /* */ >+ }, >+ { /* 1253 */ >+ 0, >+ /* */ >+ }, >+ { /* 1254 */ >+ 0, >+ /* */ >+ }, >+ { /* 1255 */ >+ 0, >+ /* */ >+ }, >+ { /* 1256 */ >+ 0, >+ /* */ >+ }, >+ { /* 1257 */ >+ 0, >+ /* */ >+ }, >+ { /* 1258 */ >+ 0, >+ /* */ >+ }, >+ { /* 1259 */ >+ 0, >+ /* */ >+ }, >+ { /* 1260 */ >+ 0, >+ /* */ >+ }, >+ { /* 1261 */ >+ 0, >+ /* */ >+ }, >+ { /* 1262 */ >+ 0, >+ /* */ >+ }, >+ { /* 1263 */ >+ 0, >+ /* */ >+ }, >+ { /* 1264 */ >+ 0, >+ /* */ >+ }, >+ { /* 1265 */ >+ 0, >+ /* */ >+ }, >+ { /* 1266 */ >+ 0, >+ /* */ >+ }, >+ { /* 1267 */ >+ 0, >+ /* */ >+ }, >+ { /* 1268 */ >+ 0, >+ /* */ >+ }, >+ { /* 1269 */ >+ 0, >+ /* */ >+ }, >+ { /* 1270 */ >+ 0, >+ /* */ >+ }, >+ { /* 1271 */ >+ 0, >+ /* */ >+ }, >+ { /* 1272 */ >+ 0, >+ /* */ >+ }, >+ { /* 1273 */ >+ 0, >+ /* */ >+ }, >+ { /* 1274 */ >+ 0, >+ /* */ >+ }, >+ { /* 1275 */ >+ 0, >+ /* */ >+ }, >+ { /* 1276 */ >+ 0, >+ /* */ >+ }, >+ { /* 1277 */ >+ 0, >+ /* */ >+ }, >+ { /* 1278 */ >+ 0, >+ /* */ >+ }, >+ { /* 1279 */ >+ 0, >+ /* LOCK_PREFIX */ >+ }, >+ { /* 1280 */ >+ 0, >+ /* */ >+ }, >+ { /* 1281 */ >+ 0, >+ /* */ >+ }, >+ { /* 1282 */ >+ 0, >+ /* */ >+ }, >+ { /* 1283 */ >+ 0, >+ /* */ >+ }, >+ { /* 1284 */ >+ 0, >+ /* */ >+ }, >+ { /* 1285 */ >+ 0, >+ /* */ >+ }, >+ { /* 1286 */ >+ 0, >+ /* */ >+ }, >+ { /* 1287 */ >+ 0, >+ /* */ >+ }, >+ { /* 1288 */ >+ 0, >+ /* */ >+ }, >+ { /* 1289 */ >+ 0, >+ /* */ >+ }, >+ { /* 1290 */ >+ 0, >+ /* */ >+ }, >+ { /* 1291 */ >+ 0, >+ /* */ >+ }, >+ { /* 1292 */ >+ 0, >+ /* */ >+ }, >+ { /* 1293 */ >+ 0, >+ /* */ >+ }, >+ { /* 1294 */ >+ 0, >+ /* */ >+ }, >+ { /* 1295 */ >+ 0, >+ /* */ >+ }, >+ { /* 1296 */ >+ 0, >+ /* */ >+ }, >+ { /* 1297 */ >+ 0, >+ /* */ >+ }, >+ { /* 1298 */ >+ 0, >+ /* */ >+ }, >+ { /* 1299 */ >+ 0, >+ /* */ >+ }, >+ { /* 1300 */ >+ 0, >+ /* */ >+ }, >+ { /* 1301 */ >+ 0, >+ /* */ >+ }, >+ { /* 1302 */ >+ 191, >+ /* LODSB */ >+ }, >+ { /* 1303 */ >+ 192, >+ /* LODSL */ >+ }, >+ { /* 1304 */ >+ 193, >+ /* LODSQ */ >+ }, >+ { /* 1305 */ >+ 194, >+ /* LODSW */ >+ }, >+ { /* 1306 */ >+ 156, >+ /* LOOP */ >+ }, >+ { /* 1307 */ >+ 156, >+ /* LOOPE */ >+ }, >+ { /* 1308 */ >+ 156, >+ /* LOOPNE */ >+ }, >+ { /* 1309 */ >+ 195, >+ /* LRETIL */ >+ }, >+ { /* 1310 */ >+ 195, >+ /* LRETIQ */ >+ }, >+ { /* 1311 */ >+ 2, >+ /* LRETIW */ >+ }, >+ { /* 1312 */ >+ 0, >+ /* LRETL */ >+ }, >+ { /* 1313 */ >+ 0, >+ /* LRETQ */ >+ }, >+ { /* 1314 */ >+ 0, >+ /* LRETW */ >+ }, >+ { /* 1315 */ >+ 68, >+ /* LSL16rm */ >+ }, >+ { /* 1316 */ >+ 69, >+ /* LSL16rr */ >+ }, >+ { /* 1317 */ >+ 68, >+ /* LSL32rm */ >+ }, >+ { /* 1318 */ >+ 69, >+ /* LSL32rr */ >+ }, >+ { /* 1319 */ >+ 42, >+ /* LSL64rm */ >+ }, >+ { /* 1320 */ >+ 43, >+ /* LSL64rr */ >+ }, >+ { /* 1321 */ >+ 184, >+ /* LSS16rm */ >+ }, >+ { /* 1322 */ >+ 185, >+ /* LSS32rm */ >+ }, >+ { /* 1323 */ >+ 189, >+ /* LSS64rm */ >+ }, >+ { /* 1324 */ >+ 38, >+ /* LTRm */ >+ }, >+ { /* 1325 */ >+ 190, >+ /* LTRr */ >+ }, >+ { /* 1326 */ >+ 0, >+ /* */ >+ }, >+ { /* 1327 */ >+ 0, >+ /* */ >+ }, >+ { /* 1328 */ >+ 0, >+ /* */ >+ }, >+ { /* 1329 */ >+ 0, >+ /* */ >+ }, >+ { /* 1330 */ >+ 68, >+ /* LZCNT16rm */ >+ }, >+ { /* 1331 */ >+ 69, >+ /* LZCNT16rr */ >+ }, >+ { /* 1332 */ >+ 68, >+ /* LZCNT32rm */ >+ }, >+ { /* 1333 */ >+ 69, >+ /* LZCNT32rr */ >+ }, >+ { /* 1334 */ >+ 42, >+ /* LZCNT64rm */ >+ }, >+ { /* 1335 */ >+ 43, >+ /* LZCNT64rr */ >+ }, >+ { /* 1336 */ >+ 45, >+ /* MASKMOVDQU */ >+ }, >+ { /* 1337 */ >+ 45, >+ /* MASKMOVDQU64 */ >+ }, >+ { /* 1338 */ >+ 0, >+ /* */ >+ }, >+ { /* 1339 */ >+ 0, >+ /* */ >+ }, >+ { /* 1340 */ >+ 0, >+ /* */ >+ }, >+ { /* 1341 */ >+ 0, >+ /* */ >+ }, >+ { /* 1342 */ >+ 0, >+ /* */ >+ }, >+ { /* 1343 */ >+ 0, >+ /* */ >+ }, >+ { /* 1344 */ >+ 0, >+ /* */ >+ }, >+ { /* 1345 */ >+ 0, >+ /* */ >+ }, >+ { /* 1346 */ >+ 30, >+ /* MAXPDrm */ >+ }, >+ { /* 1347 */ >+ 31, >+ /* MAXPDrr */ >+ }, >+ { /* 1348 */ >+ 30, >+ /* MAXPSrm */ >+ }, >+ { /* 1349 */ >+ 31, >+ /* MAXPSrr */ >+ }, >+ { /* 1350 */ >+ 32, >+ /* MAXSDrm */ >+ }, >+ { /* 1351 */ >+ 0, >+ /* */ >+ }, >+ { /* 1352 */ >+ 33, >+ /* MAXSDrr */ >+ }, >+ { /* 1353 */ >+ 0, >+ /* */ >+ }, >+ { /* 1354 */ >+ 34, >+ /* MAXSSrm */ >+ }, >+ { /* 1355 */ >+ 0, >+ /* */ >+ }, >+ { /* 1356 */ >+ 35, >+ /* MAXSSrr */ >+ }, >+ { /* 1357 */ >+ 0, >+ /* */ >+ }, >+ { /* 1358 */ >+ 0, >+ /* MFENCE */ >+ }, >+ { /* 1359 */ >+ 0, >+ /* */ >+ }, >+ { /* 1360 */ >+ 0, >+ /* */ >+ }, >+ { /* 1361 */ >+ 0, >+ /* */ >+ }, >+ { /* 1362 */ >+ 0, >+ /* */ >+ }, >+ { /* 1363 */ >+ 0, >+ /* */ >+ }, >+ { /* 1364 */ >+ 0, >+ /* */ >+ }, >+ { /* 1365 */ >+ 0, >+ /* */ >+ }, >+ { /* 1366 */ >+ 0, >+ /* */ >+ }, >+ { /* 1367 */ >+ 30, >+ /* MINPDrm */ >+ }, >+ { /* 1368 */ >+ 31, >+ /* MINPDrr */ >+ }, >+ { /* 1369 */ >+ 30, >+ /* MINPSrm */ >+ }, >+ { /* 1370 */ >+ 31, >+ /* MINPSrr */ >+ }, >+ { /* 1371 */ >+ 32, >+ /* MINSDrm */ >+ }, >+ { /* 1372 */ >+ 0, >+ /* */ >+ }, >+ { /* 1373 */ >+ 33, >+ /* MINSDrr */ >+ }, >+ { /* 1374 */ >+ 0, >+ /* */ >+ }, >+ { /* 1375 */ >+ 34, >+ /* MINSSrm */ >+ }, >+ { /* 1376 */ >+ 0, >+ /* */ >+ }, >+ { /* 1377 */ >+ 35, >+ /* MINSSrr */ >+ }, >+ { /* 1378 */ >+ 0, >+ /* */ >+ }, >+ { /* 1379 */ >+ 196, >+ /* MMX_CVTPD2PIirm */ >+ }, >+ { /* 1380 */ >+ 197, >+ /* MMX_CVTPD2PIirr */ >+ }, >+ { /* 1381 */ >+ 105, >+ /* MMX_CVTPI2PDirm */ >+ }, >+ { /* 1382 */ >+ 198, >+ /* MMX_CVTPI2PDirr */ >+ }, >+ { /* 1383 */ >+ 199, >+ /* MMX_CVTPI2PSirm */ >+ }, >+ { /* 1384 */ >+ 200, >+ /* MMX_CVTPI2PSirr */ >+ }, >+ { /* 1385 */ >+ 201, >+ /* MMX_CVTPS2PIirm */ >+ }, >+ { /* 1386 */ >+ 197, >+ /* MMX_CVTPS2PIirr */ >+ }, >+ { /* 1387 */ >+ 196, >+ /* MMX_CVTTPD2PIirm */ >+ }, >+ { /* 1388 */ >+ 197, >+ /* MMX_CVTTPD2PIirr */ >+ }, >+ { /* 1389 */ >+ 201, >+ /* MMX_CVTTPS2PIirm */ >+ }, >+ { /* 1390 */ >+ 197, >+ /* MMX_CVTTPS2PIirr */ >+ }, >+ { /* 1391 */ >+ 0, >+ /* MMX_EMMS */ >+ }, >+ { /* 1392 */ >+ 202, >+ /* MMX_MASKMOVQ */ >+ }, >+ { /* 1393 */ >+ 202, >+ /* MMX_MASKMOVQ64 */ >+ }, >+ { /* 1394 */ >+ 203, >+ /* MMX_MOVD64from64rr */ >+ }, >+ { /* 1395 */ >+ 204, >+ /* MMX_MOVD64grr */ >+ }, >+ { /* 1396 */ >+ 205, >+ /* MMX_MOVD64mr */ >+ }, >+ { /* 1397 */ >+ 206, >+ /* MMX_MOVD64rm */ >+ }, >+ { /* 1398 */ >+ 207, >+ /* MMX_MOVD64rr */ >+ }, >+ { /* 1399 */ >+ 208, >+ /* MMX_MOVD64to64rr */ >+ }, >+ { /* 1400 */ >+ 197, >+ /* MMX_MOVDQ2Qrr */ >+ }, >+ { /* 1401 */ >+ 0, >+ /* */ >+ }, >+ { /* 1402 */ >+ 205, >+ /* MMX_MOVNTQmr */ >+ }, >+ { /* 1403 */ >+ 198, >+ /* MMX_MOVQ2DQrr */ >+ }, >+ { /* 1404 */ >+ 0, >+ /* */ >+ }, >+ { /* 1405 */ >+ 205, >+ /* MMX_MOVQ64mr */ >+ }, >+ { /* 1406 */ >+ 206, >+ /* MMX_MOVQ64rm */ >+ }, >+ { /* 1407 */ >+ 202, >+ /* MMX_MOVQ64rr */ >+ }, >+ { /* 1408 */ >+ 209, >+ /* MMX_MOVQ64rr_REV */ >+ }, >+ { /* 1409 */ >+ 206, >+ /* MMX_PABSBrm64 */ >+ }, >+ { /* 1410 */ >+ 202, >+ /* MMX_PABSBrr64 */ >+ }, >+ { /* 1411 */ >+ 206, >+ /* MMX_PABSDrm64 */ >+ }, >+ { /* 1412 */ >+ 202, >+ /* MMX_PABSDrr64 */ >+ }, >+ { /* 1413 */ >+ 206, >+ /* MMX_PABSWrm64 */ >+ }, >+ { /* 1414 */ >+ 202, >+ /* MMX_PABSWrr64 */ >+ }, >+ { /* 1415 */ >+ 210, >+ /* MMX_PACKSSDWirm */ >+ }, >+ { /* 1416 */ >+ 211, >+ /* MMX_PACKSSDWirr */ >+ }, >+ { /* 1417 */ >+ 210, >+ /* MMX_PACKSSWBirm */ >+ }, >+ { /* 1418 */ >+ 211, >+ /* MMX_PACKSSWBirr */ >+ }, >+ { /* 1419 */ >+ 210, >+ /* MMX_PACKUSWBirm */ >+ }, >+ { /* 1420 */ >+ 211, >+ /* MMX_PACKUSWBirr */ >+ }, >+ { /* 1421 */ >+ 210, >+ /* MMX_PADDBirm */ >+ }, >+ { /* 1422 */ >+ 211, >+ /* MMX_PADDBirr */ >+ }, >+ { /* 1423 */ >+ 210, >+ /* MMX_PADDDirm */ >+ }, >+ { /* 1424 */ >+ 211, >+ /* MMX_PADDDirr */ >+ }, >+ { /* 1425 */ >+ 210, >+ /* MMX_PADDQirm */ >+ }, >+ { /* 1426 */ >+ 211, >+ /* MMX_PADDQirr */ >+ }, >+ { /* 1427 */ >+ 210, >+ /* MMX_PADDSBirm */ >+ }, >+ { /* 1428 */ >+ 211, >+ /* MMX_PADDSBirr */ >+ }, >+ { /* 1429 */ >+ 210, >+ /* MMX_PADDSWirm */ >+ }, >+ { /* 1430 */ >+ 211, >+ /* MMX_PADDSWirr */ >+ }, >+ { /* 1431 */ >+ 210, >+ /* MMX_PADDUSBirm */ >+ }, >+ { /* 1432 */ >+ 211, >+ /* MMX_PADDUSBirr */ >+ }, >+ { /* 1433 */ >+ 210, >+ /* MMX_PADDUSWirm */ >+ }, >+ { /* 1434 */ >+ 211, >+ /* MMX_PADDUSWirr */ >+ }, >+ { /* 1435 */ >+ 210, >+ /* MMX_PADDWirm */ >+ }, >+ { /* 1436 */ >+ 211, >+ /* MMX_PADDWirr */ >+ }, >+ { /* 1437 */ >+ 212, >+ /* MMX_PALIGNR64irm */ >+ }, >+ { /* 1438 */ >+ 213, >+ /* MMX_PALIGNR64irr */ >+ }, >+ { /* 1439 */ >+ 210, >+ /* MMX_PANDNirm */ >+ }, >+ { /* 1440 */ >+ 211, >+ /* MMX_PANDNirr */ >+ }, >+ { /* 1441 */ >+ 210, >+ /* MMX_PANDirm */ >+ }, >+ { /* 1442 */ >+ 211, >+ /* MMX_PANDirr */ >+ }, >+ { /* 1443 */ >+ 210, >+ /* MMX_PAVGBirm */ >+ }, >+ { /* 1444 */ >+ 211, >+ /* MMX_PAVGBirr */ >+ }, >+ { /* 1445 */ >+ 210, >+ /* MMX_PAVGWirm */ >+ }, >+ { /* 1446 */ >+ 211, >+ /* MMX_PAVGWirr */ >+ }, >+ { /* 1447 */ >+ 210, >+ /* MMX_PCMPEQBirm */ >+ }, >+ { /* 1448 */ >+ 211, >+ /* MMX_PCMPEQBirr */ >+ }, >+ { /* 1449 */ >+ 210, >+ /* MMX_PCMPEQDirm */ >+ }, >+ { /* 1450 */ >+ 211, >+ /* MMX_PCMPEQDirr */ >+ }, >+ { /* 1451 */ >+ 210, >+ /* MMX_PCMPEQWirm */ >+ }, >+ { /* 1452 */ >+ 211, >+ /* MMX_PCMPEQWirr */ >+ }, >+ { /* 1453 */ >+ 210, >+ /* MMX_PCMPGTBirm */ >+ }, >+ { /* 1454 */ >+ 211, >+ /* MMX_PCMPGTBirr */ >+ }, >+ { /* 1455 */ >+ 210, >+ /* MMX_PCMPGTDirm */ >+ }, >+ { /* 1456 */ >+ 211, >+ /* MMX_PCMPGTDirr */ >+ }, >+ { /* 1457 */ >+ 210, >+ /* MMX_PCMPGTWirm */ >+ }, >+ { /* 1458 */ >+ 211, >+ /* MMX_PCMPGTWirr */ >+ }, >+ { /* 1459 */ >+ 214, >+ /* MMX_PEXTRWirri */ >+ }, >+ { /* 1460 */ >+ 210, >+ /* MMX_PHADDSWrm64 */ >+ }, >+ { /* 1461 */ >+ 211, >+ /* MMX_PHADDSWrr64 */ >+ }, >+ { /* 1462 */ >+ 210, >+ /* MMX_PHADDWrm64 */ >+ }, >+ { /* 1463 */ >+ 211, >+ /* MMX_PHADDWrr64 */ >+ }, >+ { /* 1464 */ >+ 210, >+ /* MMX_PHADDrm64 */ >+ }, >+ { /* 1465 */ >+ 211, >+ /* MMX_PHADDrr64 */ >+ }, >+ { /* 1466 */ >+ 210, >+ /* MMX_PHSUBDrm64 */ >+ }, >+ { /* 1467 */ >+ 211, >+ /* MMX_PHSUBDrr64 */ >+ }, >+ { /* 1468 */ >+ 210, >+ /* MMX_PHSUBSWrm64 */ >+ }, >+ { /* 1469 */ >+ 211, >+ /* MMX_PHSUBSWrr64 */ >+ }, >+ { /* 1470 */ >+ 210, >+ /* MMX_PHSUBWrm64 */ >+ }, >+ { /* 1471 */ >+ 211, >+ /* MMX_PHSUBWrr64 */ >+ }, >+ { /* 1472 */ >+ 215, >+ /* MMX_PINSRWirmi */ >+ }, >+ { /* 1473 */ >+ 216, >+ /* MMX_PINSRWirri */ >+ }, >+ { /* 1474 */ >+ 210, >+ /* MMX_PMADDUBSWrm64 */ >+ }, >+ { /* 1475 */ >+ 211, >+ /* MMX_PMADDUBSWrr64 */ >+ }, >+ { /* 1476 */ >+ 210, >+ /* MMX_PMADDWDirm */ >+ }, >+ { /* 1477 */ >+ 211, >+ /* MMX_PMADDWDirr */ >+ }, >+ { /* 1478 */ >+ 210, >+ /* MMX_PMAXSWirm */ >+ }, >+ { /* 1479 */ >+ 211, >+ /* MMX_PMAXSWirr */ >+ }, >+ { /* 1480 */ >+ 210, >+ /* MMX_PMAXUBirm */ >+ }, >+ { /* 1481 */ >+ 211, >+ /* MMX_PMAXUBirr */ >+ }, >+ { /* 1482 */ >+ 210, >+ /* MMX_PMINSWirm */ >+ }, >+ { /* 1483 */ >+ 211, >+ /* MMX_PMINSWirr */ >+ }, >+ { /* 1484 */ >+ 210, >+ /* MMX_PMINUBirm */ >+ }, >+ { /* 1485 */ >+ 211, >+ /* MMX_PMINUBirr */ >+ }, >+ { /* 1486 */ >+ 217, >+ /* MMX_PMOVMSKBrr */ >+ }, >+ { /* 1487 */ >+ 210, >+ /* MMX_PMULHRSWrm64 */ >+ }, >+ { /* 1488 */ >+ 211, >+ /* MMX_PMULHRSWrr64 */ >+ }, >+ { /* 1489 */ >+ 210, >+ /* MMX_PMULHUWirm */ >+ }, >+ { /* 1490 */ >+ 211, >+ /* MMX_PMULHUWirr */ >+ }, >+ { /* 1491 */ >+ 210, >+ /* MMX_PMULHWirm */ >+ }, >+ { /* 1492 */ >+ 211, >+ /* MMX_PMULHWirr */ >+ }, >+ { /* 1493 */ >+ 210, >+ /* MMX_PMULLWirm */ >+ }, >+ { /* 1494 */ >+ 211, >+ /* MMX_PMULLWirr */ >+ }, >+ { /* 1495 */ >+ 210, >+ /* MMX_PMULUDQirm */ >+ }, >+ { /* 1496 */ >+ 211, >+ /* MMX_PMULUDQirr */ >+ }, >+ { /* 1497 */ >+ 210, >+ /* MMX_PORirm */ >+ }, >+ { /* 1498 */ >+ 211, >+ /* MMX_PORirr */ >+ }, >+ { /* 1499 */ >+ 210, >+ /* MMX_PSADBWirm */ >+ }, >+ { /* 1500 */ >+ 211, >+ /* MMX_PSADBWirr */ >+ }, >+ { /* 1501 */ >+ 210, >+ /* MMX_PSHUFBrm64 */ >+ }, >+ { /* 1502 */ >+ 211, >+ /* MMX_PSHUFBrr64 */ >+ }, >+ { /* 1503 */ >+ 218, >+ /* MMX_PSHUFWmi */ >+ }, >+ { /* 1504 */ >+ 219, >+ /* MMX_PSHUFWri */ >+ }, >+ { /* 1505 */ >+ 210, >+ /* MMX_PSIGNBrm64 */ >+ }, >+ { /* 1506 */ >+ 211, >+ /* MMX_PSIGNBrr64 */ >+ }, >+ { /* 1507 */ >+ 210, >+ /* MMX_PSIGNDrm64 */ >+ }, >+ { /* 1508 */ >+ 211, >+ /* MMX_PSIGNDrr64 */ >+ }, >+ { /* 1509 */ >+ 210, >+ /* MMX_PSIGNWrm64 */ >+ }, >+ { /* 1510 */ >+ 211, >+ /* MMX_PSIGNWrr64 */ >+ }, >+ { /* 1511 */ >+ 220, >+ /* MMX_PSLLDri */ >+ }, >+ { /* 1512 */ >+ 210, >+ /* MMX_PSLLDrm */ >+ }, >+ { /* 1513 */ >+ 211, >+ /* MMX_PSLLDrr */ >+ }, >+ { /* 1514 */ >+ 220, >+ /* MMX_PSLLQri */ >+ }, >+ { /* 1515 */ >+ 210, >+ /* MMX_PSLLQrm */ >+ }, >+ { /* 1516 */ >+ 211, >+ /* MMX_PSLLQrr */ >+ }, >+ { /* 1517 */ >+ 220, >+ /* MMX_PSLLWri */ >+ }, >+ { /* 1518 */ >+ 210, >+ /* MMX_PSLLWrm */ >+ }, >+ { /* 1519 */ >+ 211, >+ /* MMX_PSLLWrr */ >+ }, >+ { /* 1520 */ >+ 220, >+ /* MMX_PSRADri */ >+ }, >+ { /* 1521 */ >+ 210, >+ /* MMX_PSRADrm */ >+ }, >+ { /* 1522 */ >+ 211, >+ /* MMX_PSRADrr */ >+ }, >+ { /* 1523 */ >+ 220, >+ /* MMX_PSRAWri */ >+ }, >+ { /* 1524 */ >+ 210, >+ /* MMX_PSRAWrm */ >+ }, >+ { /* 1525 */ >+ 211, >+ /* MMX_PSRAWrr */ >+ }, >+ { /* 1526 */ >+ 220, >+ /* MMX_PSRLDri */ >+ }, >+ { /* 1527 */ >+ 210, >+ /* MMX_PSRLDrm */ >+ }, >+ { /* 1528 */ >+ 211, >+ /* MMX_PSRLDrr */ >+ }, >+ { /* 1529 */ >+ 220, >+ /* MMX_PSRLQri */ >+ }, >+ { /* 1530 */ >+ 210, >+ /* MMX_PSRLQrm */ >+ }, >+ { /* 1531 */ >+ 211, >+ /* MMX_PSRLQrr */ >+ }, >+ { /* 1532 */ >+ 220, >+ /* MMX_PSRLWri */ >+ }, >+ { /* 1533 */ >+ 210, >+ /* MMX_PSRLWrm */ >+ }, >+ { /* 1534 */ >+ 211, >+ /* MMX_PSRLWrr */ >+ }, >+ { /* 1535 */ >+ 210, >+ /* MMX_PSUBBirm */ >+ }, >+ { /* 1536 */ >+ 211, >+ /* MMX_PSUBBirr */ >+ }, >+ { /* 1537 */ >+ 210, >+ /* MMX_PSUBDirm */ >+ }, >+ { /* 1538 */ >+ 211, >+ /* MMX_PSUBDirr */ >+ }, >+ { /* 1539 */ >+ 210, >+ /* MMX_PSUBQirm */ >+ }, >+ { /* 1540 */ >+ 211, >+ /* MMX_PSUBQirr */ >+ }, >+ { /* 1541 */ >+ 210, >+ /* MMX_PSUBSBirm */ >+ }, >+ { /* 1542 */ >+ 211, >+ /* MMX_PSUBSBirr */ >+ }, >+ { /* 1543 */ >+ 210, >+ /* MMX_PSUBSWirm */ >+ }, >+ { /* 1544 */ >+ 211, >+ /* MMX_PSUBSWirr */ >+ }, >+ { /* 1545 */ >+ 210, >+ /* MMX_PSUBUSBirm */ >+ }, >+ { /* 1546 */ >+ 211, >+ /* MMX_PSUBUSBirr */ >+ }, >+ { /* 1547 */ >+ 210, >+ /* MMX_PSUBUSWirm */ >+ }, >+ { /* 1548 */ >+ 211, >+ /* MMX_PSUBUSWirr */ >+ }, >+ { /* 1549 */ >+ 210, >+ /* MMX_PSUBWirm */ >+ }, >+ { /* 1550 */ >+ 211, >+ /* MMX_PSUBWirr */ >+ }, >+ { /* 1551 */ >+ 210, >+ /* MMX_PUNPCKHBWirm */ >+ }, >+ { /* 1552 */ >+ 211, >+ /* MMX_PUNPCKHBWirr */ >+ }, >+ { /* 1553 */ >+ 210, >+ /* MMX_PUNPCKHDQirm */ >+ }, >+ { /* 1554 */ >+ 211, >+ /* MMX_PUNPCKHDQirr */ >+ }, >+ { /* 1555 */ >+ 210, >+ /* MMX_PUNPCKHWDirm */ >+ }, >+ { /* 1556 */ >+ 211, >+ /* MMX_PUNPCKHWDirr */ >+ }, >+ { /* 1557 */ >+ 210, >+ /* MMX_PUNPCKLBWirm */ >+ }, >+ { /* 1558 */ >+ 211, >+ /* MMX_PUNPCKLBWirr */ >+ }, >+ { /* 1559 */ >+ 210, >+ /* MMX_PUNPCKLDQirm */ >+ }, >+ { /* 1560 */ >+ 211, >+ /* MMX_PUNPCKLDQirr */ >+ }, >+ { /* 1561 */ >+ 210, >+ /* MMX_PUNPCKLWDirm */ >+ }, >+ { /* 1562 */ >+ 211, >+ /* MMX_PUNPCKLWDirr */ >+ }, >+ { /* 1563 */ >+ 210, >+ /* MMX_PXORirm */ >+ }, >+ { /* 1564 */ >+ 211, >+ /* MMX_PXORirr */ >+ }, >+ { /* 1565 */ >+ 0, >+ /* */ >+ }, >+ { /* 1566 */ >+ 0, >+ /* MONITORrrr */ >+ }, >+ { /* 1567 */ >+ 0, >+ /* MONTMUL */ >+ }, >+ { /* 1568 */ >+ 0, >+ /* */ >+ }, >+ { /* 1569 */ >+ 0, >+ /* */ >+ }, >+ { /* 1570 */ >+ 221, >+ /* MOV16ao16 */ >+ }, >+ { /* 1571 */ >+ 221, >+ /* MOV16ao16_16 */ >+ }, >+ { /* 1572 */ >+ 3, >+ /* MOV16mi */ >+ }, >+ { /* 1573 */ >+ 5, >+ /* MOV16mr */ >+ }, >+ { /* 1574 */ >+ 222, >+ /* MOV16ms */ >+ }, >+ { /* 1575 */ >+ 221, >+ /* MOV16o16a */ >+ }, >+ { /* 1576 */ >+ 221, >+ /* MOV16o16a_16 */ >+ }, >+ { /* 1577 */ >+ 223, >+ /* MOV16ri */ >+ }, >+ { /* 1578 */ >+ 83, >+ /* MOV16ri_alt */ >+ }, >+ { /* 1579 */ >+ 68, >+ /* MOV16rm */ >+ }, >+ { /* 1580 */ >+ 73, >+ /* MOV16rr */ >+ }, >+ { /* 1581 */ >+ 69, >+ /* MOV16rr_REV */ >+ }, >+ { /* 1582 */ >+ 224, >+ /* MOV16rs */ >+ }, >+ { /* 1583 */ >+ 225, >+ /* MOV16sm */ >+ }, >+ { /* 1584 */ >+ 226, >+ /* MOV16sr */ >+ }, >+ { /* 1585 */ >+ 227, >+ /* MOV32ao32 */ >+ }, >+ { /* 1586 */ >+ 227, >+ /* MOV32ao32_16 */ >+ }, >+ { /* 1587 */ >+ 228, >+ /* MOV32cr */ >+ }, >+ { /* 1588 */ >+ 229, >+ /* MOV32dr */ >+ }, >+ { /* 1589 */ >+ 3, >+ /* MOV32mi */ >+ }, >+ { /* 1590 */ >+ 5, >+ /* MOV32mr */ >+ }, >+ { /* 1591 */ >+ 222, >+ /* MOV32ms */ >+ }, >+ { /* 1592 */ >+ 227, >+ /* MOV32o32a */ >+ }, >+ { /* 1593 */ >+ 227, >+ /* MOV32o32a_16 */ >+ }, >+ { /* 1594 */ >+ 0, >+ /* */ >+ }, >+ { /* 1595 */ >+ 230, >+ /* MOV32rc */ >+ }, >+ { /* 1596 */ >+ 231, >+ /* MOV32rd */ >+ }, >+ { /* 1597 */ >+ 223, >+ /* MOV32ri */ >+ }, >+ { /* 1598 */ >+ 0, >+ /* */ >+ }, >+ { /* 1599 */ >+ 83, >+ /* MOV32ri_alt */ >+ }, >+ { /* 1600 */ >+ 68, >+ /* MOV32rm */ >+ }, >+ { /* 1601 */ >+ 73, >+ /* MOV32rr */ >+ }, >+ { /* 1602 */ >+ 69, >+ /* MOV32rr_REV */ >+ }, >+ { /* 1603 */ >+ 224, >+ /* MOV32rs */ >+ }, >+ { /* 1604 */ >+ 225, >+ /* MOV32sm */ >+ }, >+ { /* 1605 */ >+ 226, >+ /* MOV32sr */ >+ }, >+ { /* 1606 */ >+ 221, >+ /* MOV64ao16 */ >+ }, >+ { /* 1607 */ >+ 227, >+ /* MOV64ao32 */ >+ }, >+ { /* 1608 */ >+ 232, >+ /* MOV64ao64 */ >+ }, >+ { /* 1609 */ >+ 233, >+ /* MOV64ao8 */ >+ }, >+ { /* 1610 */ >+ 234, >+ /* MOV64cr */ >+ }, >+ { /* 1611 */ >+ 235, >+ /* MOV64dr */ >+ }, >+ { /* 1612 */ >+ 14, >+ /* MOV64mi32 */ >+ }, >+ { /* 1613 */ >+ 16, >+ /* MOV64mr */ >+ }, >+ { /* 1614 */ >+ 222, >+ /* MOV64ms */ >+ }, >+ { /* 1615 */ >+ 221, >+ /* MOV64o16a */ >+ }, >+ { /* 1616 */ >+ 227, >+ /* MOV64o32a */ >+ }, >+ { /* 1617 */ >+ 232, >+ /* MOV64o64a */ >+ }, >+ { /* 1618 */ >+ 233, >+ /* MOV64o8a */ >+ }, >+ { /* 1619 */ >+ 236, >+ /* MOV64rc */ >+ }, >+ { /* 1620 */ >+ 237, >+ /* MOV64rd */ >+ }, >+ { /* 1621 */ >+ 238, >+ /* MOV64ri */ >+ }, >+ { /* 1622 */ >+ 84, >+ /* MOV64ri32 */ >+ }, >+ { /* 1623 */ >+ 42, >+ /* MOV64rm */ >+ }, >+ { /* 1624 */ >+ 76, >+ /* MOV64rr */ >+ }, >+ { /* 1625 */ >+ 43, >+ /* MOV64rr_REV */ >+ }, >+ { /* 1626 */ >+ 239, >+ /* MOV64rs */ >+ }, >+ { /* 1627 */ >+ 225, >+ /* MOV64sm */ >+ }, >+ { /* 1628 */ >+ 240, >+ /* MOV64sr */ >+ }, >+ { /* 1629 */ >+ 241, >+ /* MOV64toPQIrr */ >+ }, >+ { /* 1630 */ >+ 0, >+ /* */ >+ }, >+ { /* 1631 */ >+ 0, >+ /* */ >+ }, >+ { /* 1632 */ >+ 233, >+ /* MOV8ao8 */ >+ }, >+ { /* 1633 */ >+ 233, >+ /* MOV8ao8_16 */ >+ }, >+ { /* 1634 */ >+ 22, >+ /* MOV8mi */ >+ }, >+ { /* 1635 */ >+ 23, >+ /* MOV8mr */ >+ }, >+ { /* 1636 */ >+ 0, >+ /* */ >+ }, >+ { /* 1637 */ >+ 233, >+ /* MOV8o8a */ >+ }, >+ { /* 1638 */ >+ 233, >+ /* MOV8o8a_16 */ >+ }, >+ { /* 1639 */ >+ 242, >+ /* MOV8ri */ >+ }, >+ { /* 1640 */ >+ 85, >+ /* MOV8ri_alt */ >+ }, >+ { /* 1641 */ >+ 86, >+ /* MOV8rm */ >+ }, >+ { /* 1642 */ >+ 0, >+ /* */ >+ }, >+ { /* 1643 */ >+ 87, >+ /* MOV8rr */ >+ }, >+ { /* 1644 */ >+ 0, >+ /* */ >+ }, >+ { /* 1645 */ >+ 88, >+ /* MOV8rr_REV */ >+ }, >+ { /* 1646 */ >+ 243, >+ /* MOVAPDmr */ >+ }, >+ { /* 1647 */ >+ 44, >+ /* MOVAPDrm */ >+ }, >+ { /* 1648 */ >+ 45, >+ /* MOVAPDrr */ >+ }, >+ { /* 1649 */ >+ 244, >+ /* MOVAPDrr_REV */ >+ }, >+ { /* 1650 */ >+ 243, >+ /* MOVAPSmr */ >+ }, >+ { /* 1651 */ >+ 44, >+ /* MOVAPSrm */ >+ }, >+ { /* 1652 */ >+ 45, >+ /* MOVAPSrr */ >+ }, >+ { /* 1653 */ >+ 244, >+ /* MOVAPSrr_REV */ >+ }, >+ { /* 1654 */ >+ 5, >+ /* MOVBE16mr */ >+ }, >+ { /* 1655 */ >+ 68, >+ /* MOVBE16rm */ >+ }, >+ { /* 1656 */ >+ 5, >+ /* MOVBE32mr */ >+ }, >+ { /* 1657 */ >+ 68, >+ /* MOVBE32rm */ >+ }, >+ { /* 1658 */ >+ 16, >+ /* MOVBE64mr */ >+ }, >+ { /* 1659 */ >+ 42, >+ /* MOVBE64rm */ >+ }, >+ { /* 1660 */ >+ 106, >+ /* MOVDDUPrm */ >+ }, >+ { /* 1661 */ >+ 45, >+ /* MOVDDUPrr */ >+ }, >+ { /* 1662 */ >+ 105, >+ /* MOVDI2PDIrm */ >+ }, >+ { /* 1663 */ >+ 245, >+ /* MOVDI2PDIrr */ >+ }, >+ { /* 1664 */ >+ 0, >+ /* */ >+ }, >+ { /* 1665 */ >+ 0, >+ /* */ >+ }, >+ { /* 1666 */ >+ 243, >+ /* MOVDQAmr */ >+ }, >+ { /* 1667 */ >+ 44, >+ /* MOVDQArm */ >+ }, >+ { /* 1668 */ >+ 45, >+ /* MOVDQArr */ >+ }, >+ { /* 1669 */ >+ 244, >+ /* MOVDQArr_REV */ >+ }, >+ { /* 1670 */ >+ 243, >+ /* MOVDQUmr */ >+ }, >+ { /* 1671 */ >+ 44, >+ /* MOVDQUrm */ >+ }, >+ { /* 1672 */ >+ 45, >+ /* MOVDQUrr */ >+ }, >+ { /* 1673 */ >+ 244, >+ /* MOVDQUrr_REV */ >+ }, >+ { /* 1674 */ >+ 31, >+ /* MOVHLPSrr */ >+ }, >+ { /* 1675 */ >+ 246, >+ /* MOVHPDmr */ >+ }, >+ { /* 1676 */ >+ 247, >+ /* MOVHPDrm */ >+ }, >+ { /* 1677 */ >+ 246, >+ /* MOVHPSmr */ >+ }, >+ { /* 1678 */ >+ 247, >+ /* MOVHPSrm */ >+ }, >+ { /* 1679 */ >+ 31, >+ /* MOVLHPSrr */ >+ }, >+ { /* 1680 */ >+ 246, >+ /* MOVLPDmr */ >+ }, >+ { /* 1681 */ >+ 247, >+ /* MOVLPDrm */ >+ }, >+ { /* 1682 */ >+ 246, >+ /* MOVLPSmr */ >+ }, >+ { /* 1683 */ >+ 247, >+ /* MOVLPSrm */ >+ }, >+ { /* 1684 */ >+ 110, >+ /* MOVMSKPDrr */ >+ }, >+ { /* 1685 */ >+ 110, >+ /* MOVMSKPSrr */ >+ }, >+ { /* 1686 */ >+ 44, >+ /* MOVNTDQArm */ >+ }, >+ { /* 1687 */ >+ 243, >+ /* MOVNTDQmr */ >+ }, >+ { /* 1688 */ >+ 16, >+ /* MOVNTI_64mr */ >+ }, >+ { /* 1689 */ >+ 248, >+ /* MOVNTImr */ >+ }, >+ { /* 1690 */ >+ 243, >+ /* MOVNTPDmr */ >+ }, >+ { /* 1691 */ >+ 243, >+ /* MOVNTPSmr */ >+ }, >+ { /* 1692 */ >+ 246, >+ /* MOVNTSD */ >+ }, >+ { /* 1693 */ >+ 249, >+ /* MOVNTSS */ >+ }, >+ { /* 1694 */ >+ 0, >+ /* */ >+ }, >+ { /* 1695 */ >+ 250, >+ /* MOVPDI2DImr */ >+ }, >+ { /* 1696 */ >+ 251, >+ /* MOVPDI2DIrr */ >+ }, >+ { /* 1697 */ >+ 250, >+ /* MOVPQI2QImr */ >+ }, >+ { /* 1698 */ >+ 244, >+ /* MOVPQI2QIrr */ >+ }, >+ { /* 1699 */ >+ 252, >+ /* MOVPQIto64rr */ >+ }, >+ { /* 1700 */ >+ 105, >+ /* MOVQI2PQIrm */ >+ }, >+ { /* 1701 */ >+ 91, >+ /* MOVSB */ >+ }, >+ { /* 1702 */ >+ 253, >+ /* MOVSDmr */ >+ }, >+ { /* 1703 */ >+ 254, >+ /* MOVSDrm */ >+ }, >+ { /* 1704 */ >+ 255, >+ /* MOVSDrr */ >+ }, >+ { /* 1705 */ >+ 256, >+ /* MOVSDrr_REV */ >+ }, >+ { /* 1706 */ >+ 0, >+ /* */ >+ }, >+ { /* 1707 */ >+ 0, >+ /* */ >+ }, >+ { /* 1708 */ >+ 44, >+ /* MOVSHDUPrm */ >+ }, >+ { /* 1709 */ >+ 45, >+ /* MOVSHDUPrr */ >+ }, >+ { /* 1710 */ >+ 94, >+ /* MOVSL */ >+ }, >+ { /* 1711 */ >+ 44, >+ /* MOVSLDUPrm */ >+ }, >+ { /* 1712 */ >+ 45, >+ /* MOVSLDUPrr */ >+ }, >+ { /* 1713 */ >+ 95, >+ /* MOVSQ */ >+ }, >+ { /* 1714 */ >+ 0, >+ /* */ >+ }, >+ { /* 1715 */ >+ 0, >+ /* */ >+ }, >+ { /* 1716 */ >+ 257, >+ /* MOVSSmr */ >+ }, >+ { /* 1717 */ >+ 258, >+ /* MOVSSrm */ >+ }, >+ { /* 1718 */ >+ 259, >+ /* MOVSSrr */ >+ }, >+ { /* 1719 */ >+ 260, >+ /* MOVSSrr_REV */ >+ }, >+ { /* 1720 */ >+ 98, >+ /* MOVSW */ >+ }, >+ { /* 1721 */ >+ 261, >+ /* MOVSX16rm8 */ >+ }, >+ { /* 1722 */ >+ 262, >+ /* MOVSX16rr8 */ >+ }, >+ { /* 1723 */ >+ 68, >+ /* MOVSX32rm16 */ >+ }, >+ { /* 1724 */ >+ 261, >+ /* MOVSX32rm8 */ >+ }, >+ { /* 1725 */ >+ 263, >+ /* MOVSX32rr16 */ >+ }, >+ { /* 1726 */ >+ 262, >+ /* MOVSX32rr8 */ >+ }, >+ { /* 1727 */ >+ 183, >+ /* MOVSX64_NOREXrr32 */ >+ }, >+ { /* 1728 */ >+ 42, >+ /* MOVSX64rm16 */ >+ }, >+ { /* 1729 */ >+ 42, >+ /* MOVSX64rm32 */ >+ }, >+ { /* 1730 */ >+ 264, >+ /* MOVSX64rm8 */ >+ }, >+ { /* 1731 */ >+ 265, >+ /* MOVSX64rr16 */ >+ }, >+ { /* 1732 */ >+ 183, >+ /* MOVSX64rr32 */ >+ }, >+ { /* 1733 */ >+ 266, >+ /* MOVSX64rr8 */ >+ }, >+ { /* 1734 */ >+ 243, >+ /* MOVUPDmr */ >+ }, >+ { /* 1735 */ >+ 44, >+ /* MOVUPDrm */ >+ }, >+ { /* 1736 */ >+ 45, >+ /* MOVUPDrr */ >+ }, >+ { /* 1737 */ >+ 244, >+ /* MOVUPDrr_REV */ >+ }, >+ { /* 1738 */ >+ 243, >+ /* MOVUPSmr */ >+ }, >+ { /* 1739 */ >+ 44, >+ /* MOVUPSrm */ >+ }, >+ { /* 1740 */ >+ 45, >+ /* MOVUPSrr */ >+ }, >+ { /* 1741 */ >+ 244, >+ /* MOVUPSrr_REV */ >+ }, >+ { /* 1742 */ >+ 0, >+ /* */ >+ }, >+ { /* 1743 */ >+ 45, >+ /* MOVZPQILo2PQIrr */ >+ }, >+ { /* 1744 */ >+ 0, >+ /* */ >+ }, >+ { /* 1745 */ >+ 0, >+ /* */ >+ }, >+ { /* 1746 */ >+ 261, >+ /* MOVZX16rm8 */ >+ }, >+ { /* 1747 */ >+ 262, >+ /* MOVZX16rr8 */ >+ }, >+ { /* 1748 */ >+ 0, >+ /* */ >+ }, >+ { /* 1749 */ >+ 0, >+ /* */ >+ }, >+ { /* 1750 */ >+ 68, >+ /* MOVZX32rm16 */ >+ }, >+ { /* 1751 */ >+ 261, >+ /* MOVZX32rm8 */ >+ }, >+ { /* 1752 */ >+ 263, >+ /* MOVZX32rr16 */ >+ }, >+ { /* 1753 */ >+ 262, >+ /* MOVZX32rr8 */ >+ }, >+ { /* 1754 */ >+ 42, >+ /* MOVZX64rm16_Q */ >+ }, >+ { /* 1755 */ >+ 264, >+ /* MOVZX64rm8_Q */ >+ }, >+ { /* 1756 */ >+ 265, >+ /* MOVZX64rr16_Q */ >+ }, >+ { /* 1757 */ >+ 266, >+ /* MOVZX64rr8_Q */ >+ }, >+ { /* 1758 */ >+ 66, >+ /* MPSADBWrmi */ >+ }, >+ { /* 1759 */ >+ 67, >+ /* MPSADBWrri */ >+ }, >+ { /* 1760 */ >+ 38, >+ /* MUL16m */ >+ }, >+ { /* 1761 */ >+ 77, >+ /* MUL16r */ >+ }, >+ { /* 1762 */ >+ 38, >+ /* MUL32m */ >+ }, >+ { /* 1763 */ >+ 77, >+ /* MUL32r */ >+ }, >+ { /* 1764 */ >+ 38, >+ /* MUL64m */ >+ }, >+ { /* 1765 */ >+ 79, >+ /* MUL64r */ >+ }, >+ { /* 1766 */ >+ 82, >+ /* MUL8m */ >+ }, >+ { /* 1767 */ >+ 130, >+ /* MUL8r */ >+ }, >+ { /* 1768 */ >+ 30, >+ /* MULPDrm */ >+ }, >+ { /* 1769 */ >+ 31, >+ /* MULPDrr */ >+ }, >+ { /* 1770 */ >+ 30, >+ /* MULPSrm */ >+ }, >+ { /* 1771 */ >+ 31, >+ /* MULPSrr */ >+ }, >+ { /* 1772 */ >+ 32, >+ /* MULSDrm */ >+ }, >+ { /* 1773 */ >+ 0, >+ /* */ >+ }, >+ { /* 1774 */ >+ 33, >+ /* MULSDrr */ >+ }, >+ { /* 1775 */ >+ 0, >+ /* */ >+ }, >+ { /* 1776 */ >+ 34, >+ /* MULSSrm */ >+ }, >+ { /* 1777 */ >+ 0, >+ /* */ >+ }, >+ { /* 1778 */ >+ 35, >+ /* MULSSrr */ >+ }, >+ { /* 1779 */ >+ 0, >+ /* */ >+ }, >+ { /* 1780 */ >+ 48, >+ /* MULX32rm */ >+ }, >+ { /* 1781 */ >+ 49, >+ /* MULX32rr */ >+ }, >+ { /* 1782 */ >+ 50, >+ /* MULX64rm */ >+ }, >+ { /* 1783 */ >+ 51, >+ /* MULX64rr */ >+ }, >+ { /* 1784 */ >+ 36, >+ /* MUL_F32m */ >+ }, >+ { /* 1785 */ >+ 37, >+ /* MUL_F64m */ >+ }, >+ { /* 1786 */ >+ 38, >+ /* MUL_FI16m */ >+ }, >+ { /* 1787 */ >+ 38, >+ /* MUL_FI32m */ >+ }, >+ { /* 1788 */ >+ 39, >+ /* MUL_FPrST0 */ >+ }, >+ { /* 1789 */ >+ 39, >+ /* MUL_FST0r */ >+ }, >+ { /* 1790 */ >+ 0, >+ /* */ >+ }, >+ { /* 1791 */ >+ 0, >+ /* */ >+ }, >+ { /* 1792 */ >+ 0, >+ /* */ >+ }, >+ { /* 1793 */ >+ 0, >+ /* */ >+ }, >+ { /* 1794 */ >+ 0, >+ /* */ >+ }, >+ { /* 1795 */ >+ 0, >+ /* */ >+ }, >+ { /* 1796 */ >+ 0, >+ /* */ >+ }, >+ { /* 1797 */ >+ 0, >+ /* */ >+ }, >+ { /* 1798 */ >+ 0, >+ /* */ >+ }, >+ { /* 1799 */ >+ 0, >+ /* */ >+ }, >+ { /* 1800 */ >+ 0, >+ /* */ >+ }, >+ { /* 1801 */ >+ 0, >+ /* */ >+ }, >+ { /* 1802 */ >+ 0, >+ /* */ >+ }, >+ { /* 1803 */ >+ 0, >+ /* */ >+ }, >+ { /* 1804 */ >+ 39, >+ /* MUL_FrST0 */ >+ }, >+ { /* 1805 */ >+ 0, >+ /* MWAITrr */ >+ }, >+ { /* 1806 */ >+ 38, >+ /* NEG16m */ >+ }, >+ { /* 1807 */ >+ 127, >+ /* NEG16r */ >+ }, >+ { /* 1808 */ >+ 38, >+ /* NEG32m */ >+ }, >+ { /* 1809 */ >+ 127, >+ /* NEG32r */ >+ }, >+ { /* 1810 */ >+ 38, >+ /* NEG64m */ >+ }, >+ { /* 1811 */ >+ 128, >+ /* NEG64r */ >+ }, >+ { /* 1812 */ >+ 82, >+ /* NEG8m */ >+ }, >+ { /* 1813 */ >+ 129, >+ /* NEG8r */ >+ }, >+ { /* 1814 */ >+ 0, >+ /* NOOP */ >+ }, >+ { /* 1815 */ >+ 38, >+ /* NOOP18_16m4 */ >+ }, >+ { /* 1816 */ >+ 38, >+ /* NOOP18_16m5 */ >+ }, >+ { /* 1817 */ >+ 38, >+ /* NOOP18_16m6 */ >+ }, >+ { /* 1818 */ >+ 38, >+ /* NOOP18_16m7 */ >+ }, >+ { /* 1819 */ >+ 77, >+ /* NOOP18_16r4 */ >+ }, >+ { /* 1820 */ >+ 77, >+ /* NOOP18_16r5 */ >+ }, >+ { /* 1821 */ >+ 77, >+ /* NOOP18_16r6 */ >+ }, >+ { /* 1822 */ >+ 77, >+ /* NOOP18_16r7 */ >+ }, >+ { /* 1823 */ >+ 38, >+ /* NOOP18_m4 */ >+ }, >+ { /* 1824 */ >+ 38, >+ /* NOOP18_m5 */ >+ }, >+ { /* 1825 */ >+ 38, >+ /* NOOP18_m6 */ >+ }, >+ { /* 1826 */ >+ 38, >+ /* NOOP18_m7 */ >+ }, >+ { /* 1827 */ >+ 77, >+ /* NOOP18_r4 */ >+ }, >+ { /* 1828 */ >+ 77, >+ /* NOOP18_r5 */ >+ }, >+ { /* 1829 */ >+ 77, >+ /* NOOP18_r6 */ >+ }, >+ { /* 1830 */ >+ 77, >+ /* NOOP18_r7 */ >+ }, >+ { /* 1831 */ >+ 69, >+ /* NOOP19rr */ >+ }, >+ { /* 1832 */ >+ 38, >+ /* NOOPL */ >+ }, >+ { /* 1833 */ >+ 38, >+ /* NOOPL_19 */ >+ }, >+ { /* 1834 */ >+ 38, >+ /* NOOPL_1a */ >+ }, >+ { /* 1835 */ >+ 38, >+ /* NOOPL_1b */ >+ }, >+ { /* 1836 */ >+ 38, >+ /* NOOPL_1c */ >+ }, >+ { /* 1837 */ >+ 38, >+ /* NOOPL_1d */ >+ }, >+ { /* 1838 */ >+ 38, >+ /* NOOPL_1e */ >+ }, >+ { /* 1839 */ >+ 38, >+ /* NOOPW */ >+ }, >+ { /* 1840 */ >+ 38, >+ /* NOOPW_19 */ >+ }, >+ { /* 1841 */ >+ 38, >+ /* NOOPW_1a */ >+ }, >+ { /* 1842 */ >+ 38, >+ /* NOOPW_1b */ >+ }, >+ { /* 1843 */ >+ 38, >+ /* NOOPW_1c */ >+ }, >+ { /* 1844 */ >+ 38, >+ /* NOOPW_1d */ >+ }, >+ { /* 1845 */ >+ 38, >+ /* NOOPW_1e */ >+ }, >+ { /* 1846 */ >+ 38, >+ /* NOT16m */ >+ }, >+ { /* 1847 */ >+ 127, >+ /* NOT16r */ >+ }, >+ { /* 1848 */ >+ 38, >+ /* NOT32m */ >+ }, >+ { /* 1849 */ >+ 127, >+ /* NOT32r */ >+ }, >+ { /* 1850 */ >+ 38, >+ /* NOT64m */ >+ }, >+ { /* 1851 */ >+ 128, >+ /* NOT64r */ >+ }, >+ { /* 1852 */ >+ 82, >+ /* NOT8m */ >+ }, >+ { /* 1853 */ >+ 129, >+ /* NOT8r */ >+ }, >+ { /* 1854 */ >+ 2, >+ /* OR16i16 */ >+ }, >+ { /* 1855 */ >+ 3, >+ /* OR16mi */ >+ }, >+ { /* 1856 */ >+ 4, >+ /* OR16mi8 */ >+ }, >+ { /* 1857 */ >+ 5, >+ /* OR16mr */ >+ }, >+ { /* 1858 */ >+ 6, >+ /* OR16ri */ >+ }, >+ { /* 1859 */ >+ 7, >+ /* OR16ri8 */ >+ }, >+ { /* 1860 */ >+ 8, >+ /* OR16rm */ >+ }, >+ { /* 1861 */ >+ 9, >+ /* OR16rr */ >+ }, >+ { /* 1862 */ >+ 10, >+ /* OR16rr_REV */ >+ }, >+ { /* 1863 */ >+ 2, >+ /* OR32i32 */ >+ }, >+ { /* 1864 */ >+ 3, >+ /* OR32mi */ >+ }, >+ { /* 1865 */ >+ 11, >+ /* OR32mi8 */ >+ }, >+ { /* 1866 */ >+ 5, >+ /* OR32mr */ >+ }, >+ { /* 1867 */ >+ 0, >+ /* */ >+ }, >+ { /* 1868 */ >+ 6, >+ /* OR32ri */ >+ }, >+ { /* 1869 */ >+ 12, >+ /* OR32ri8 */ >+ }, >+ { /* 1870 */ >+ 8, >+ /* OR32rm */ >+ }, >+ { /* 1871 */ >+ 9, >+ /* OR32rr */ >+ }, >+ { /* 1872 */ >+ 10, >+ /* OR32rr_REV */ >+ }, >+ { /* 1873 */ >+ 13, >+ /* OR64i32 */ >+ }, >+ { /* 1874 */ >+ 14, >+ /* OR64mi32 */ >+ }, >+ { /* 1875 */ >+ 15, >+ /* OR64mi8 */ >+ }, >+ { /* 1876 */ >+ 16, >+ /* OR64mr */ >+ }, >+ { /* 1877 */ >+ 17, >+ /* OR64ri32 */ >+ }, >+ { /* 1878 */ >+ 18, >+ /* OR64ri8 */ >+ }, >+ { /* 1879 */ >+ 19, >+ /* OR64rm */ >+ }, >+ { /* 1880 */ >+ 20, >+ /* OR64rr */ >+ }, >+ { /* 1881 */ >+ 21, >+ /* OR64rr_REV */ >+ }, >+ { /* 1882 */ >+ 1, >+ /* OR8i8 */ >+ }, >+ { /* 1883 */ >+ 22, >+ /* OR8mi */ >+ }, >+ { /* 1884 */ >+ 23, >+ /* OR8mr */ >+ }, >+ { /* 1885 */ >+ 24, >+ /* OR8ri */ >+ }, >+ { /* 1886 */ >+ 24, >+ /* OR8ri8 */ >+ }, >+ { /* 1887 */ >+ 25, >+ /* OR8rm */ >+ }, >+ { /* 1888 */ >+ 26, >+ /* OR8rr */ >+ }, >+ { /* 1889 */ >+ 27, >+ /* OR8rr_REV */ >+ }, >+ { /* 1890 */ >+ 30, >+ /* ORPDrm */ >+ }, >+ { /* 1891 */ >+ 31, >+ /* ORPDrr */ >+ }, >+ { /* 1892 */ >+ 30, >+ /* ORPSrm */ >+ }, >+ { /* 1893 */ >+ 31, >+ /* ORPSrr */ >+ }, >+ { /* 1894 */ >+ 1, >+ /* OUT16ir */ >+ }, >+ { /* 1895 */ >+ 0, >+ /* OUT16rr */ >+ }, >+ { /* 1896 */ >+ 1, >+ /* OUT32ir */ >+ }, >+ { /* 1897 */ >+ 0, >+ /* OUT32rr */ >+ }, >+ { /* 1898 */ >+ 1, >+ /* OUT8ir */ >+ }, >+ { /* 1899 */ >+ 0, >+ /* OUT8rr */ >+ }, >+ { /* 1900 */ >+ 191, >+ /* OUTSB */ >+ }, >+ { /* 1901 */ >+ 192, >+ /* OUTSL */ >+ }, >+ { /* 1902 */ >+ 194, >+ /* OUTSW */ >+ }, >+ { /* 1903 */ >+ 44, >+ /* PABSBrm128 */ >+ }, >+ { /* 1904 */ >+ 45, >+ /* PABSBrr128 */ >+ }, >+ { /* 1905 */ >+ 44, >+ /* PABSDrm128 */ >+ }, >+ { /* 1906 */ >+ 45, >+ /* PABSDrr128 */ >+ }, >+ { /* 1907 */ >+ 44, >+ /* PABSWrm128 */ >+ }, >+ { /* 1908 */ >+ 45, >+ /* PABSWrr128 */ >+ }, >+ { /* 1909 */ >+ 30, >+ /* PACKSSDWrm */ >+ }, >+ { /* 1910 */ >+ 31, >+ /* PACKSSDWrr */ >+ }, >+ { /* 1911 */ >+ 30, >+ /* PACKSSWBrm */ >+ }, >+ { /* 1912 */ >+ 31, >+ /* PACKSSWBrr */ >+ }, >+ { /* 1913 */ >+ 30, >+ /* PACKUSDWrm */ >+ }, >+ { /* 1914 */ >+ 31, >+ /* PACKUSDWrr */ >+ }, >+ { /* 1915 */ >+ 30, >+ /* PACKUSWBrm */ >+ }, >+ { /* 1916 */ >+ 31, >+ /* PACKUSWBrr */ >+ }, >+ { /* 1917 */ >+ 30, >+ /* PADDBrm */ >+ }, >+ { /* 1918 */ >+ 31, >+ /* PADDBrr */ >+ }, >+ { /* 1919 */ >+ 30, >+ /* PADDDrm */ >+ }, >+ { /* 1920 */ >+ 31, >+ /* PADDDrr */ >+ }, >+ { /* 1921 */ >+ 30, >+ /* PADDQrm */ >+ }, >+ { /* 1922 */ >+ 31, >+ /* PADDQrr */ >+ }, >+ { /* 1923 */ >+ 30, >+ /* PADDSBrm */ >+ }, >+ { /* 1924 */ >+ 31, >+ /* PADDSBrr */ >+ }, >+ { /* 1925 */ >+ 30, >+ /* PADDSWrm */ >+ }, >+ { /* 1926 */ >+ 31, >+ /* PADDSWrr */ >+ }, >+ { /* 1927 */ >+ 30, >+ /* PADDUSBrm */ >+ }, >+ { /* 1928 */ >+ 31, >+ /* PADDUSBrr */ >+ }, >+ { /* 1929 */ >+ 30, >+ /* PADDUSWrm */ >+ }, >+ { /* 1930 */ >+ 31, >+ /* PADDUSWrr */ >+ }, >+ { /* 1931 */ >+ 30, >+ /* PADDWrm */ >+ }, >+ { /* 1932 */ >+ 31, >+ /* PADDWrr */ >+ }, >+ { /* 1933 */ >+ 267, >+ /* PALIGNR128rm */ >+ }, >+ { /* 1934 */ >+ 268, >+ /* PALIGNR128rr */ >+ }, >+ { /* 1935 */ >+ 30, >+ /* PANDNrm */ >+ }, >+ { /* 1936 */ >+ 31, >+ /* PANDNrr */ >+ }, >+ { /* 1937 */ >+ 30, >+ /* PANDrm */ >+ }, >+ { /* 1938 */ >+ 31, >+ /* PANDrr */ >+ }, >+ { /* 1939 */ >+ 0, >+ /* PAUSE */ >+ }, >+ { /* 1940 */ >+ 30, >+ /* PAVGBrm */ >+ }, >+ { /* 1941 */ >+ 31, >+ /* PAVGBrr */ >+ }, >+ { /* 1942 */ >+ 210, >+ /* PAVGUSBrm */ >+ }, >+ { /* 1943 */ >+ 211, >+ /* PAVGUSBrr */ >+ }, >+ { /* 1944 */ >+ 30, >+ /* PAVGWrm */ >+ }, >+ { /* 1945 */ >+ 31, >+ /* PAVGWrr */ >+ }, >+ { /* 1946 */ >+ 30, >+ /* PBLENDVBrm0 */ >+ }, >+ { /* 1947 */ >+ 31, >+ /* PBLENDVBrr0 */ >+ }, >+ { /* 1948 */ >+ 66, >+ /* PBLENDWrmi */ >+ }, >+ { /* 1949 */ >+ 67, >+ /* PBLENDWrri */ >+ }, >+ { /* 1950 */ >+ 267, >+ /* PCLMULQDQrm */ >+ }, >+ { /* 1951 */ >+ 268, >+ /* PCLMULQDQrr */ >+ }, >+ { /* 1952 */ >+ 30, >+ /* PCMPEQBrm */ >+ }, >+ { /* 1953 */ >+ 31, >+ /* PCMPEQBrr */ >+ }, >+ { /* 1954 */ >+ 30, >+ /* PCMPEQDrm */ >+ }, >+ { /* 1955 */ >+ 31, >+ /* PCMPEQDrr */ >+ }, >+ { /* 1956 */ >+ 30, >+ /* PCMPEQQrm */ >+ }, >+ { /* 1957 */ >+ 31, >+ /* PCMPEQQrr */ >+ }, >+ { /* 1958 */ >+ 30, >+ /* PCMPEQWrm */ >+ }, >+ { /* 1959 */ >+ 31, >+ /* PCMPEQWrr */ >+ }, >+ { /* 1960 */ >+ 0, >+ /* */ >+ }, >+ { /* 1961 */ >+ 0, >+ /* */ >+ }, >+ { /* 1962 */ >+ 46, >+ /* PCMPESTRIrm */ >+ }, >+ { /* 1963 */ >+ 47, >+ /* PCMPESTRIrr */ >+ }, >+ { /* 1964 */ >+ 0, >+ /* */ >+ }, >+ { /* 1965 */ >+ 0, >+ /* */ >+ }, >+ { /* 1966 */ >+ 46, >+ /* PCMPESTRM128rm */ >+ }, >+ { /* 1967 */ >+ 47, >+ /* PCMPESTRM128rr */ >+ }, >+ { /* 1968 */ >+ 30, >+ /* PCMPGTBrm */ >+ }, >+ { /* 1969 */ >+ 31, >+ /* PCMPGTBrr */ >+ }, >+ { /* 1970 */ >+ 30, >+ /* PCMPGTDrm */ >+ }, >+ { /* 1971 */ >+ 31, >+ /* PCMPGTDrr */ >+ }, >+ { /* 1972 */ >+ 30, >+ /* PCMPGTQrm */ >+ }, >+ { /* 1973 */ >+ 31, >+ /* PCMPGTQrr */ >+ }, >+ { /* 1974 */ >+ 30, >+ /* PCMPGTWrm */ >+ }, >+ { /* 1975 */ >+ 31, >+ /* PCMPGTWrr */ >+ }, >+ { /* 1976 */ >+ 0, >+ /* */ >+ }, >+ { /* 1977 */ >+ 0, >+ /* */ >+ }, >+ { /* 1978 */ >+ 46, >+ /* PCMPISTRIrm */ >+ }, >+ { /* 1979 */ >+ 47, >+ /* PCMPISTRIrr */ >+ }, >+ { /* 1980 */ >+ 0, >+ /* */ >+ }, >+ { /* 1981 */ >+ 0, >+ /* */ >+ }, >+ { /* 1982 */ >+ 46, >+ /* PCMPISTRM128rm */ >+ }, >+ { /* 1983 */ >+ 47, >+ /* PCMPISTRM128rr */ >+ }, >+ { /* 1984 */ >+ 48, >+ /* PDEP32rm */ >+ }, >+ { /* 1985 */ >+ 49, >+ /* PDEP32rr */ >+ }, >+ { /* 1986 */ >+ 50, >+ /* PDEP64rm */ >+ }, >+ { /* 1987 */ >+ 51, >+ /* PDEP64rr */ >+ }, >+ { /* 1988 */ >+ 48, >+ /* PEXT32rm */ >+ }, >+ { /* 1989 */ >+ 49, >+ /* PEXT32rr */ >+ }, >+ { /* 1990 */ >+ 50, >+ /* PEXT64rm */ >+ }, >+ { /* 1991 */ >+ 51, >+ /* PEXT64rr */ >+ }, >+ { /* 1992 */ >+ 269, >+ /* PEXTRBmr */ >+ }, >+ { /* 1993 */ >+ 133, >+ /* PEXTRBrr */ >+ }, >+ { /* 1994 */ >+ 270, >+ /* PEXTRDmr */ >+ }, >+ { /* 1995 */ >+ 133, >+ /* PEXTRDrr */ >+ }, >+ { /* 1996 */ >+ 270, >+ /* PEXTRQmr */ >+ }, >+ { /* 1997 */ >+ 271, >+ /* PEXTRQrr */ >+ }, >+ { /* 1998 */ >+ 270, >+ /* PEXTRWmr */ >+ }, >+ { /* 1999 */ >+ 272, >+ /* PEXTRWri */ >+ }, >+ { /* 2000 */ >+ 133, >+ /* PEXTRWrr_REV */ >+ }, >+ { /* 2001 */ >+ 206, >+ /* PF2IDrm */ >+ }, >+ { /* 2002 */ >+ 202, >+ /* PF2IDrr */ >+ }, >+ { /* 2003 */ >+ 206, >+ /* PF2IWrm */ >+ }, >+ { /* 2004 */ >+ 202, >+ /* PF2IWrr */ >+ }, >+ { /* 2005 */ >+ 210, >+ /* PFACCrm */ >+ }, >+ { /* 2006 */ >+ 211, >+ /* PFACCrr */ >+ }, >+ { /* 2007 */ >+ 210, >+ /* PFADDrm */ >+ }, >+ { /* 2008 */ >+ 211, >+ /* PFADDrr */ >+ }, >+ { /* 2009 */ >+ 210, >+ /* PFCMPEQrm */ >+ }, >+ { /* 2010 */ >+ 211, >+ /* PFCMPEQrr */ >+ }, >+ { /* 2011 */ >+ 210, >+ /* PFCMPGErm */ >+ }, >+ { /* 2012 */ >+ 211, >+ /* PFCMPGErr */ >+ }, >+ { /* 2013 */ >+ 210, >+ /* PFCMPGTrm */ >+ }, >+ { /* 2014 */ >+ 211, >+ /* PFCMPGTrr */ >+ }, >+ { /* 2015 */ >+ 210, >+ /* PFMAXrm */ >+ }, >+ { /* 2016 */ >+ 211, >+ /* PFMAXrr */ >+ }, >+ { /* 2017 */ >+ 210, >+ /* PFMINrm */ >+ }, >+ { /* 2018 */ >+ 211, >+ /* PFMINrr */ >+ }, >+ { /* 2019 */ >+ 210, >+ /* PFMULrm */ >+ }, >+ { /* 2020 */ >+ 211, >+ /* PFMULrr */ >+ }, >+ { /* 2021 */ >+ 210, >+ /* PFNACCrm */ >+ }, >+ { /* 2022 */ >+ 211, >+ /* PFNACCrr */ >+ }, >+ { /* 2023 */ >+ 210, >+ /* PFPNACCrm */ >+ }, >+ { /* 2024 */ >+ 211, >+ /* PFPNACCrr */ >+ }, >+ { /* 2025 */ >+ 210, >+ /* PFRCPIT1rm */ >+ }, >+ { /* 2026 */ >+ 211, >+ /* PFRCPIT1rr */ >+ }, >+ { /* 2027 */ >+ 210, >+ /* PFRCPIT2rm */ >+ }, >+ { /* 2028 */ >+ 211, >+ /* PFRCPIT2rr */ >+ }, >+ { /* 2029 */ >+ 206, >+ /* PFRCPrm */ >+ }, >+ { /* 2030 */ >+ 202, >+ /* PFRCPrr */ >+ }, >+ { /* 2031 */ >+ 210, >+ /* PFRSQIT1rm */ >+ }, >+ { /* 2032 */ >+ 211, >+ /* PFRSQIT1rr */ >+ }, >+ { /* 2033 */ >+ 206, >+ /* PFRSQRTrm */ >+ }, >+ { /* 2034 */ >+ 202, >+ /* PFRSQRTrr */ >+ }, >+ { /* 2035 */ >+ 210, >+ /* PFSUBRrm */ >+ }, >+ { /* 2036 */ >+ 211, >+ /* PFSUBRrr */ >+ }, >+ { /* 2037 */ >+ 210, >+ /* PFSUBrm */ >+ }, >+ { /* 2038 */ >+ 211, >+ /* PFSUBrr */ >+ }, >+ { /* 2039 */ >+ 30, >+ /* PHADDDrm */ >+ }, >+ { /* 2040 */ >+ 31, >+ /* PHADDDrr */ >+ }, >+ { /* 2041 */ >+ 30, >+ /* PHADDSWrm128 */ >+ }, >+ { /* 2042 */ >+ 31, >+ /* PHADDSWrr128 */ >+ }, >+ { /* 2043 */ >+ 30, >+ /* PHADDWrm */ >+ }, >+ { /* 2044 */ >+ 31, >+ /* PHADDWrr */ >+ }, >+ { /* 2045 */ >+ 44, >+ /* PHMINPOSUWrm128 */ >+ }, >+ { /* 2046 */ >+ 45, >+ /* PHMINPOSUWrr128 */ >+ }, >+ { /* 2047 */ >+ 30, >+ /* PHSUBDrm */ >+ }, >+ { /* 2048 */ >+ 31, >+ /* PHSUBDrr */ >+ }, >+ { /* 2049 */ >+ 30, >+ /* PHSUBSWrm128 */ >+ }, >+ { /* 2050 */ >+ 31, >+ /* PHSUBSWrr128 */ >+ }, >+ { /* 2051 */ >+ 30, >+ /* PHSUBWrm */ >+ }, >+ { /* 2052 */ >+ 31, >+ /* PHSUBWrr */ >+ }, >+ { /* 2053 */ >+ 206, >+ /* PI2FDrm */ >+ }, >+ { /* 2054 */ >+ 202, >+ /* PI2FDrr */ >+ }, >+ { /* 2055 */ >+ 206, >+ /* PI2FWrm */ >+ }, >+ { /* 2056 */ >+ 202, >+ /* PI2FWrr */ >+ }, >+ { /* 2057 */ >+ 273, >+ /* PINSRBrm */ >+ }, >+ { /* 2058 */ >+ 274, >+ /* PINSRBrr */ >+ }, >+ { /* 2059 */ >+ 275, >+ /* PINSRDrm */ >+ }, >+ { /* 2060 */ >+ 274, >+ /* PINSRDrr */ >+ }, >+ { /* 2061 */ >+ 275, >+ /* PINSRQrm */ >+ }, >+ { /* 2062 */ >+ 276, >+ /* PINSRQrr */ >+ }, >+ { /* 2063 */ >+ 275, >+ /* PINSRWrmi */ >+ }, >+ { /* 2064 */ >+ 274, >+ /* PINSRWrri */ >+ }, >+ { /* 2065 */ >+ 30, >+ /* PMADDUBSWrm128 */ >+ }, >+ { /* 2066 */ >+ 31, >+ /* PMADDUBSWrr128 */ >+ }, >+ { /* 2067 */ >+ 30, >+ /* PMADDWDrm */ >+ }, >+ { /* 2068 */ >+ 31, >+ /* PMADDWDrr */ >+ }, >+ { /* 2069 */ >+ 30, >+ /* PMAXSBrm */ >+ }, >+ { /* 2070 */ >+ 31, >+ /* PMAXSBrr */ >+ }, >+ { /* 2071 */ >+ 30, >+ /* PMAXSDrm */ >+ }, >+ { /* 2072 */ >+ 31, >+ /* PMAXSDrr */ >+ }, >+ { /* 2073 */ >+ 30, >+ /* PMAXSWrm */ >+ }, >+ { /* 2074 */ >+ 31, >+ /* PMAXSWrr */ >+ }, >+ { /* 2075 */ >+ 30, >+ /* PMAXUBrm */ >+ }, >+ { /* 2076 */ >+ 31, >+ /* PMAXUBrr */ >+ }, >+ { /* 2077 */ >+ 30, >+ /* PMAXUDrm */ >+ }, >+ { /* 2078 */ >+ 31, >+ /* PMAXUDrr */ >+ }, >+ { /* 2079 */ >+ 30, >+ /* PMAXUWrm */ >+ }, >+ { /* 2080 */ >+ 31, >+ /* PMAXUWrr */ >+ }, >+ { /* 2081 */ >+ 30, >+ /* PMINSBrm */ >+ }, >+ { /* 2082 */ >+ 31, >+ /* PMINSBrr */ >+ }, >+ { /* 2083 */ >+ 30, >+ /* PMINSDrm */ >+ }, >+ { /* 2084 */ >+ 31, >+ /* PMINSDrr */ >+ }, >+ { /* 2085 */ >+ 30, >+ /* PMINSWrm */ >+ }, >+ { /* 2086 */ >+ 31, >+ /* PMINSWrr */ >+ }, >+ { /* 2087 */ >+ 30, >+ /* PMINUBrm */ >+ }, >+ { /* 2088 */ >+ 31, >+ /* PMINUBrr */ >+ }, >+ { /* 2089 */ >+ 30, >+ /* PMINUDrm */ >+ }, >+ { /* 2090 */ >+ 31, >+ /* PMINUDrr */ >+ }, >+ { /* 2091 */ >+ 30, >+ /* PMINUWrm */ >+ }, >+ { /* 2092 */ >+ 31, >+ /* PMINUWrr */ >+ }, >+ { /* 2093 */ >+ 110, >+ /* PMOVMSKBrr */ >+ }, >+ { /* 2094 */ >+ 105, >+ /* PMOVSXBDrm */ >+ }, >+ { /* 2095 */ >+ 45, >+ /* PMOVSXBDrr */ >+ }, >+ { /* 2096 */ >+ 105, >+ /* PMOVSXBQrm */ >+ }, >+ { /* 2097 */ >+ 45, >+ /* PMOVSXBQrr */ >+ }, >+ { /* 2098 */ >+ 105, >+ /* PMOVSXBWrm */ >+ }, >+ { /* 2099 */ >+ 45, >+ /* PMOVSXBWrr */ >+ }, >+ { /* 2100 */ >+ 105, >+ /* PMOVSXDQrm */ >+ }, >+ { /* 2101 */ >+ 45, >+ /* PMOVSXDQrr */ >+ }, >+ { /* 2102 */ >+ 105, >+ /* PMOVSXWDrm */ >+ }, >+ { /* 2103 */ >+ 45, >+ /* PMOVSXWDrr */ >+ }, >+ { /* 2104 */ >+ 105, >+ /* PMOVSXWQrm */ >+ }, >+ { /* 2105 */ >+ 45, >+ /* PMOVSXWQrr */ >+ }, >+ { /* 2106 */ >+ 105, >+ /* PMOVZXBDrm */ >+ }, >+ { /* 2107 */ >+ 45, >+ /* PMOVZXBDrr */ >+ }, >+ { /* 2108 */ >+ 105, >+ /* PMOVZXBQrm */ >+ }, >+ { /* 2109 */ >+ 45, >+ /* PMOVZXBQrr */ >+ }, >+ { /* 2110 */ >+ 105, >+ /* PMOVZXBWrm */ >+ }, >+ { /* 2111 */ >+ 45, >+ /* PMOVZXBWrr */ >+ }, >+ { /* 2112 */ >+ 105, >+ /* PMOVZXDQrm */ >+ }, >+ { /* 2113 */ >+ 45, >+ /* PMOVZXDQrr */ >+ }, >+ { /* 2114 */ >+ 105, >+ /* PMOVZXWDrm */ >+ }, >+ { /* 2115 */ >+ 45, >+ /* PMOVZXWDrr */ >+ }, >+ { /* 2116 */ >+ 105, >+ /* PMOVZXWQrm */ >+ }, >+ { /* 2117 */ >+ 45, >+ /* PMOVZXWQrr */ >+ }, >+ { /* 2118 */ >+ 30, >+ /* PMULDQrm */ >+ }, >+ { /* 2119 */ >+ 31, >+ /* PMULDQrr */ >+ }, >+ { /* 2120 */ >+ 30, >+ /* PMULHRSWrm128 */ >+ }, >+ { /* 2121 */ >+ 31, >+ /* PMULHRSWrr128 */ >+ }, >+ { /* 2122 */ >+ 210, >+ /* PMULHRWrm */ >+ }, >+ { /* 2123 */ >+ 211, >+ /* PMULHRWrr */ >+ }, >+ { /* 2124 */ >+ 30, >+ /* PMULHUWrm */ >+ }, >+ { /* 2125 */ >+ 31, >+ /* PMULHUWrr */ >+ }, >+ { /* 2126 */ >+ 30, >+ /* PMULHWrm */ >+ }, >+ { /* 2127 */ >+ 31, >+ /* PMULHWrr */ >+ }, >+ { /* 2128 */ >+ 30, >+ /* PMULLDrm */ >+ }, >+ { /* 2129 */ >+ 31, >+ /* PMULLDrr */ >+ }, >+ { /* 2130 */ >+ 30, >+ /* PMULLWrm */ >+ }, >+ { /* 2131 */ >+ 31, >+ /* PMULLWrr */ >+ }, >+ { /* 2132 */ >+ 30, >+ /* PMULUDQrm */ >+ }, >+ { /* 2133 */ >+ 31, >+ /* PMULUDQrr */ >+ }, >+ { /* 2134 */ >+ 277, >+ /* POP16r */ >+ }, >+ { /* 2135 */ >+ 38, >+ /* POP16rmm */ >+ }, >+ { /* 2136 */ >+ 77, >+ /* POP16rmr */ >+ }, >+ { /* 2137 */ >+ 277, >+ /* POP32r */ >+ }, >+ { /* 2138 */ >+ 38, >+ /* POP32rmm */ >+ }, >+ { /* 2139 */ >+ 77, >+ /* POP32rmr */ >+ }, >+ { /* 2140 */ >+ 278, >+ /* POP64r */ >+ }, >+ { /* 2141 */ >+ 38, >+ /* POP64rmm */ >+ }, >+ { /* 2142 */ >+ 79, >+ /* POP64rmr */ >+ }, >+ { /* 2143 */ >+ 0, >+ /* POPA16 */ >+ }, >+ { /* 2144 */ >+ 0, >+ /* POPA32 */ >+ }, >+ { /* 2145 */ >+ 68, >+ /* POPCNT16rm */ >+ }, >+ { /* 2146 */ >+ 69, >+ /* POPCNT16rr */ >+ }, >+ { /* 2147 */ >+ 68, >+ /* POPCNT32rm */ >+ }, >+ { /* 2148 */ >+ 69, >+ /* POPCNT32rr */ >+ }, >+ { /* 2149 */ >+ 42, >+ /* POPCNT64rm */ >+ }, >+ { /* 2150 */ >+ 43, >+ /* POPCNT64rr */ >+ }, >+ { /* 2151 */ >+ 0, >+ /* POPDS16 */ >+ }, >+ { /* 2152 */ >+ 0, >+ /* POPDS32 */ >+ }, >+ { /* 2153 */ >+ 0, >+ /* POPES16 */ >+ }, >+ { /* 2154 */ >+ 0, >+ /* POPES32 */ >+ }, >+ { /* 2155 */ >+ 0, >+ /* POPF16 */ >+ }, >+ { /* 2156 */ >+ 0, >+ /* POPF32 */ >+ }, >+ { /* 2157 */ >+ 0, >+ /* POPF64 */ >+ }, >+ { /* 2158 */ >+ 0, >+ /* POPFS16 */ >+ }, >+ { /* 2159 */ >+ 0, >+ /* POPFS32 */ >+ }, >+ { /* 2160 */ >+ 0, >+ /* POPFS64 */ >+ }, >+ { /* 2161 */ >+ 0, >+ /* POPGS16 */ >+ }, >+ { /* 2162 */ >+ 0, >+ /* POPGS32 */ >+ }, >+ { /* 2163 */ >+ 0, >+ /* POPGS64 */ >+ }, >+ { /* 2164 */ >+ 0, >+ /* POPSS16 */ >+ }, >+ { /* 2165 */ >+ 0, >+ /* POPSS32 */ >+ }, >+ { /* 2166 */ >+ 30, >+ /* PORrm */ >+ }, >+ { /* 2167 */ >+ 31, >+ /* PORrr */ >+ }, >+ { /* 2168 */ >+ 82, >+ /* PREFETCH */ >+ }, >+ { /* 2169 */ >+ 82, >+ /* PREFETCHNTA */ >+ }, >+ { /* 2170 */ >+ 82, >+ /* PREFETCHT0 */ >+ }, >+ { /* 2171 */ >+ 82, >+ /* PREFETCHT1 */ >+ }, >+ { /* 2172 */ >+ 82, >+ /* PREFETCHT2 */ >+ }, >+ { /* 2173 */ >+ 82, >+ /* PREFETCHW */ >+ }, >+ { /* 2174 */ >+ 30, >+ /* PSADBWrm */ >+ }, >+ { /* 2175 */ >+ 31, >+ /* PSADBWrr */ >+ }, >+ { /* 2176 */ >+ 30, >+ /* PSHUFBrm */ >+ }, >+ { /* 2177 */ >+ 31, >+ /* PSHUFBrr */ >+ }, >+ { /* 2178 */ >+ 46, >+ /* PSHUFDmi */ >+ }, >+ { /* 2179 */ >+ 47, >+ /* PSHUFDri */ >+ }, >+ { /* 2180 */ >+ 46, >+ /* PSHUFHWmi */ >+ }, >+ { /* 2181 */ >+ 47, >+ /* PSHUFHWri */ >+ }, >+ { /* 2182 */ >+ 46, >+ /* PSHUFLWmi */ >+ }, >+ { /* 2183 */ >+ 47, >+ /* PSHUFLWri */ >+ }, >+ { /* 2184 */ >+ 30, >+ /* PSIGNBrm */ >+ }, >+ { /* 2185 */ >+ 31, >+ /* PSIGNBrr */ >+ }, >+ { /* 2186 */ >+ 30, >+ /* PSIGNDrm */ >+ }, >+ { /* 2187 */ >+ 31, >+ /* PSIGNDrr */ >+ }, >+ { /* 2188 */ >+ 30, >+ /* PSIGNWrm */ >+ }, >+ { /* 2189 */ >+ 31, >+ /* PSIGNWrr */ >+ }, >+ { /* 2190 */ >+ 279, >+ /* PSLLDQri */ >+ }, >+ { /* 2191 */ >+ 280, >+ /* PSLLDri */ >+ }, >+ { /* 2192 */ >+ 30, >+ /* PSLLDrm */ >+ }, >+ { /* 2193 */ >+ 31, >+ /* PSLLDrr */ >+ }, >+ { /* 2194 */ >+ 280, >+ /* PSLLQri */ >+ }, >+ { /* 2195 */ >+ 30, >+ /* PSLLQrm */ >+ }, >+ { /* 2196 */ >+ 31, >+ /* PSLLQrr */ >+ }, >+ { /* 2197 */ >+ 280, >+ /* PSLLWri */ >+ }, >+ { /* 2198 */ >+ 30, >+ /* PSLLWrm */ >+ }, >+ { /* 2199 */ >+ 31, >+ /* PSLLWrr */ >+ }, >+ { /* 2200 */ >+ 280, >+ /* PSRADri */ >+ }, >+ { /* 2201 */ >+ 30, >+ /* PSRADrm */ >+ }, >+ { /* 2202 */ >+ 31, >+ /* PSRADrr */ >+ }, >+ { /* 2203 */ >+ 280, >+ /* PSRAWri */ >+ }, >+ { /* 2204 */ >+ 30, >+ /* PSRAWrm */ >+ }, >+ { /* 2205 */ >+ 31, >+ /* PSRAWrr */ >+ }, >+ { /* 2206 */ >+ 279, >+ /* PSRLDQri */ >+ }, >+ { /* 2207 */ >+ 280, >+ /* PSRLDri */ >+ }, >+ { /* 2208 */ >+ 30, >+ /* PSRLDrm */ >+ }, >+ { /* 2209 */ >+ 31, >+ /* PSRLDrr */ >+ }, >+ { /* 2210 */ >+ 280, >+ /* PSRLQri */ >+ }, >+ { /* 2211 */ >+ 30, >+ /* PSRLQrm */ >+ }, >+ { /* 2212 */ >+ 31, >+ /* PSRLQrr */ >+ }, >+ { /* 2213 */ >+ 280, >+ /* PSRLWri */ >+ }, >+ { /* 2214 */ >+ 30, >+ /* PSRLWrm */ >+ }, >+ { /* 2215 */ >+ 31, >+ /* PSRLWrr */ >+ }, >+ { /* 2216 */ >+ 30, >+ /* PSUBBrm */ >+ }, >+ { /* 2217 */ >+ 31, >+ /* PSUBBrr */ >+ }, >+ { /* 2218 */ >+ 30, >+ /* PSUBDrm */ >+ }, >+ { /* 2219 */ >+ 31, >+ /* PSUBDrr */ >+ }, >+ { /* 2220 */ >+ 30, >+ /* PSUBQrm */ >+ }, >+ { /* 2221 */ >+ 31, >+ /* PSUBQrr */ >+ }, >+ { /* 2222 */ >+ 30, >+ /* PSUBSBrm */ >+ }, >+ { /* 2223 */ >+ 31, >+ /* PSUBSBrr */ >+ }, >+ { /* 2224 */ >+ 30, >+ /* PSUBSWrm */ >+ }, >+ { /* 2225 */ >+ 31, >+ /* PSUBSWrr */ >+ }, >+ { /* 2226 */ >+ 30, >+ /* PSUBUSBrm */ >+ }, >+ { /* 2227 */ >+ 31, >+ /* PSUBUSBrr */ >+ }, >+ { /* 2228 */ >+ 30, >+ /* PSUBUSWrm */ >+ }, >+ { /* 2229 */ >+ 31, >+ /* PSUBUSWrr */ >+ }, >+ { /* 2230 */ >+ 30, >+ /* PSUBWrm */ >+ }, >+ { /* 2231 */ >+ 31, >+ /* PSUBWrr */ >+ }, >+ { /* 2232 */ >+ 206, >+ /* PSWAPDrm */ >+ }, >+ { /* 2233 */ >+ 202, >+ /* PSWAPDrr */ >+ }, >+ { /* 2234 */ >+ 44, >+ /* PTESTrm */ >+ }, >+ { /* 2235 */ >+ 45, >+ /* PTESTrr */ >+ }, >+ { /* 2236 */ >+ 30, >+ /* PUNPCKHBWrm */ >+ }, >+ { /* 2237 */ >+ 31, >+ /* PUNPCKHBWrr */ >+ }, >+ { /* 2238 */ >+ 30, >+ /* PUNPCKHDQrm */ >+ }, >+ { /* 2239 */ >+ 31, >+ /* PUNPCKHDQrr */ >+ }, >+ { /* 2240 */ >+ 30, >+ /* PUNPCKHQDQrm */ >+ }, >+ { /* 2241 */ >+ 31, >+ /* PUNPCKHQDQrr */ >+ }, >+ { /* 2242 */ >+ 30, >+ /* PUNPCKHWDrm */ >+ }, >+ { /* 2243 */ >+ 31, >+ /* PUNPCKHWDrr */ >+ }, >+ { /* 2244 */ >+ 30, >+ /* PUNPCKLBWrm */ >+ }, >+ { /* 2245 */ >+ 31, >+ /* PUNPCKLBWrr */ >+ }, >+ { /* 2246 */ >+ 30, >+ /* PUNPCKLDQrm */ >+ }, >+ { /* 2247 */ >+ 31, >+ /* PUNPCKLDQrr */ >+ }, >+ { /* 2248 */ >+ 30, >+ /* PUNPCKLQDQrm */ >+ }, >+ { /* 2249 */ >+ 31, >+ /* PUNPCKLQDQrr */ >+ }, >+ { /* 2250 */ >+ 30, >+ /* PUNPCKLWDrm */ >+ }, >+ { /* 2251 */ >+ 31, >+ /* PUNPCKLWDrr */ >+ }, >+ { /* 2252 */ >+ 281, >+ /* PUSH16i8 */ >+ }, >+ { /* 2253 */ >+ 277, >+ /* PUSH16r */ >+ }, >+ { /* 2254 */ >+ 38, >+ /* PUSH16rmm */ >+ }, >+ { /* 2255 */ >+ 77, >+ /* PUSH16rmr */ >+ }, >+ { /* 2256 */ >+ 282, >+ /* PUSH32i8 */ >+ }, >+ { /* 2257 */ >+ 277, >+ /* PUSH32r */ >+ }, >+ { /* 2258 */ >+ 38, >+ /* PUSH32rmm */ >+ }, >+ { /* 2259 */ >+ 77, >+ /* PUSH32rmr */ >+ }, >+ { /* 2260 */ >+ 2, >+ /* PUSH64i16 */ >+ }, >+ { /* 2261 */ >+ 13, >+ /* PUSH64i32 */ >+ }, >+ { /* 2262 */ >+ 283, >+ /* PUSH64i8 */ >+ }, >+ { /* 2263 */ >+ 278, >+ /* PUSH64r */ >+ }, >+ { /* 2264 */ >+ 38, >+ /* PUSH64rmm */ >+ }, >+ { /* 2265 */ >+ 79, >+ /* PUSH64rmr */ >+ }, >+ { /* 2266 */ >+ 0, >+ /* PUSHA16 */ >+ }, >+ { /* 2267 */ >+ 0, >+ /* PUSHA32 */ >+ }, >+ { /* 2268 */ >+ 0, >+ /* PUSHCS16 */ >+ }, >+ { /* 2269 */ >+ 0, >+ /* PUSHCS32 */ >+ }, >+ { /* 2270 */ >+ 0, >+ /* PUSHDS16 */ >+ }, >+ { /* 2271 */ >+ 0, >+ /* PUSHDS32 */ >+ }, >+ { /* 2272 */ >+ 0, >+ /* PUSHES16 */ >+ }, >+ { /* 2273 */ >+ 0, >+ /* PUSHES32 */ >+ }, >+ { /* 2274 */ >+ 0, >+ /* PUSHF16 */ >+ }, >+ { /* 2275 */ >+ 0, >+ /* PUSHF32 */ >+ }, >+ { /* 2276 */ >+ 0, >+ /* PUSHF64 */ >+ }, >+ { /* 2277 */ >+ 0, >+ /* PUSHFS16 */ >+ }, >+ { /* 2278 */ >+ 0, >+ /* PUSHFS32 */ >+ }, >+ { /* 2279 */ >+ 0, >+ /* PUSHFS64 */ >+ }, >+ { /* 2280 */ >+ 0, >+ /* PUSHGS16 */ >+ }, >+ { /* 2281 */ >+ 0, >+ /* PUSHGS32 */ >+ }, >+ { /* 2282 */ >+ 0, >+ /* PUSHGS64 */ >+ }, >+ { /* 2283 */ >+ 0, >+ /* PUSHSS16 */ >+ }, >+ { /* 2284 */ >+ 0, >+ /* PUSHSS32 */ >+ }, >+ { /* 2285 */ >+ 2, >+ /* PUSHi16 */ >+ }, >+ { /* 2286 */ >+ 2, >+ /* PUSHi32 */ >+ }, >+ { /* 2287 */ >+ 30, >+ /* PXORrm */ >+ }, >+ { /* 2288 */ >+ 31, >+ /* PXORrr */ >+ }, >+ { /* 2289 */ >+ 38, >+ /* RCL16m1 */ >+ }, >+ { /* 2290 */ >+ 38, >+ /* RCL16mCL */ >+ }, >+ { /* 2291 */ >+ 284, >+ /* RCL16mi */ >+ }, >+ { /* 2292 */ >+ 127, >+ /* RCL16r1 */ >+ }, >+ { /* 2293 */ >+ 127, >+ /* RCL16rCL */ >+ }, >+ { /* 2294 */ >+ 285, >+ /* RCL16ri */ >+ }, >+ { /* 2295 */ >+ 38, >+ /* RCL32m1 */ >+ }, >+ { /* 2296 */ >+ 38, >+ /* RCL32mCL */ >+ }, >+ { /* 2297 */ >+ 284, >+ /* RCL32mi */ >+ }, >+ { /* 2298 */ >+ 127, >+ /* RCL32r1 */ >+ }, >+ { /* 2299 */ >+ 127, >+ /* RCL32rCL */ >+ }, >+ { /* 2300 */ >+ 285, >+ /* RCL32ri */ >+ }, >+ { /* 2301 */ >+ 38, >+ /* RCL64m1 */ >+ }, >+ { /* 2302 */ >+ 38, >+ /* RCL64mCL */ >+ }, >+ { /* 2303 */ >+ 284, >+ /* RCL64mi */ >+ }, >+ { /* 2304 */ >+ 128, >+ /* RCL64r1 */ >+ }, >+ { /* 2305 */ >+ 128, >+ /* RCL64rCL */ >+ }, >+ { /* 2306 */ >+ 286, >+ /* RCL64ri */ >+ }, >+ { /* 2307 */ >+ 82, >+ /* RCL8m1 */ >+ }, >+ { /* 2308 */ >+ 82, >+ /* RCL8mCL */ >+ }, >+ { /* 2309 */ >+ 22, >+ /* RCL8mi */ >+ }, >+ { /* 2310 */ >+ 129, >+ /* RCL8r1 */ >+ }, >+ { /* 2311 */ >+ 129, >+ /* RCL8rCL */ >+ }, >+ { /* 2312 */ >+ 24, >+ /* RCL8ri */ >+ }, >+ { /* 2313 */ >+ 44, >+ /* RCPPSm */ >+ }, >+ { /* 2314 */ >+ 0, >+ /* */ >+ }, >+ { /* 2315 */ >+ 45, >+ /* RCPPSr */ >+ }, >+ { /* 2316 */ >+ 0, >+ /* */ >+ }, >+ { /* 2317 */ >+ 258, >+ /* RCPSSm */ >+ }, >+ { /* 2318 */ >+ 0, >+ /* */ >+ }, >+ { /* 2319 */ >+ 287, >+ /* RCPSSr */ >+ }, >+ { /* 2320 */ >+ 0, >+ /* */ >+ }, >+ { /* 2321 */ >+ 38, >+ /* RCR16m1 */ >+ }, >+ { /* 2322 */ >+ 38, >+ /* RCR16mCL */ >+ }, >+ { /* 2323 */ >+ 284, >+ /* RCR16mi */ >+ }, >+ { /* 2324 */ >+ 127, >+ /* RCR16r1 */ >+ }, >+ { /* 2325 */ >+ 127, >+ /* RCR16rCL */ >+ }, >+ { /* 2326 */ >+ 285, >+ /* RCR16ri */ >+ }, >+ { /* 2327 */ >+ 38, >+ /* RCR32m1 */ >+ }, >+ { /* 2328 */ >+ 38, >+ /* RCR32mCL */ >+ }, >+ { /* 2329 */ >+ 284, >+ /* RCR32mi */ >+ }, >+ { /* 2330 */ >+ 127, >+ /* RCR32r1 */ >+ }, >+ { /* 2331 */ >+ 127, >+ /* RCR32rCL */ >+ }, >+ { /* 2332 */ >+ 285, >+ /* RCR32ri */ >+ }, >+ { /* 2333 */ >+ 38, >+ /* RCR64m1 */ >+ }, >+ { /* 2334 */ >+ 38, >+ /* RCR64mCL */ >+ }, >+ { /* 2335 */ >+ 284, >+ /* RCR64mi */ >+ }, >+ { /* 2336 */ >+ 128, >+ /* RCR64r1 */ >+ }, >+ { /* 2337 */ >+ 128, >+ /* RCR64rCL */ >+ }, >+ { /* 2338 */ >+ 286, >+ /* RCR64ri */ >+ }, >+ { /* 2339 */ >+ 82, >+ /* RCR8m1 */ >+ }, >+ { /* 2340 */ >+ 82, >+ /* RCR8mCL */ >+ }, >+ { /* 2341 */ >+ 22, >+ /* RCR8mi */ >+ }, >+ { /* 2342 */ >+ 129, >+ /* RCR8r1 */ >+ }, >+ { /* 2343 */ >+ 129, >+ /* RCR8rCL */ >+ }, >+ { /* 2344 */ >+ 24, >+ /* RCR8ri */ >+ }, >+ { /* 2345 */ >+ 288, >+ /* RDFSBASE */ >+ }, >+ { /* 2346 */ >+ 79, >+ /* RDFSBASE64 */ >+ }, >+ { /* 2347 */ >+ 288, >+ /* RDGSBASE */ >+ }, >+ { /* 2348 */ >+ 79, >+ /* RDGSBASE64 */ >+ }, >+ { /* 2349 */ >+ 0, >+ /* RDMSR */ >+ }, >+ { /* 2350 */ >+ 0, >+ /* RDPMC */ >+ }, >+ { /* 2351 */ >+ 77, >+ /* RDRAND16r */ >+ }, >+ { /* 2352 */ >+ 77, >+ /* RDRAND32r */ >+ }, >+ { /* 2353 */ >+ 79, >+ /* RDRAND64r */ >+ }, >+ { /* 2354 */ >+ 77, >+ /* RDSEED16r */ >+ }, >+ { /* 2355 */ >+ 77, >+ /* RDSEED32r */ >+ }, >+ { /* 2356 */ >+ 79, >+ /* RDSEED64r */ >+ }, >+ { /* 2357 */ >+ 0, >+ /* RDTSC */ >+ }, >+ { /* 2358 */ >+ 0, >+ /* RDTSCP */ >+ }, >+ { /* 2359 */ >+ 0, >+ /* */ >+ }, >+ { /* 2360 */ >+ 0, >+ /* */ >+ }, >+ { /* 2361 */ >+ 0, >+ /* */ >+ }, >+ { /* 2362 */ >+ 0, >+ /* */ >+ }, >+ { /* 2363 */ >+ 0, >+ /* REPNE_PREFIX */ >+ }, >+ { /* 2364 */ >+ 0, >+ /* */ >+ }, >+ { /* 2365 */ >+ 0, >+ /* */ >+ }, >+ { /* 2366 */ >+ 0, >+ /* */ >+ }, >+ { /* 2367 */ >+ 0, >+ /* */ >+ }, >+ { /* 2368 */ >+ 0, >+ /* */ >+ }, >+ { /* 2369 */ >+ 0, >+ /* */ >+ }, >+ { /* 2370 */ >+ 0, >+ /* */ >+ }, >+ { /* 2371 */ >+ 0, >+ /* REP_PREFIX */ >+ }, >+ { /* 2372 */ >+ 0, >+ /* */ >+ }, >+ { /* 2373 */ >+ 0, >+ /* */ >+ }, >+ { /* 2374 */ >+ 0, >+ /* */ >+ }, >+ { /* 2375 */ >+ 0, >+ /* */ >+ }, >+ { /* 2376 */ >+ 0, >+ /* */ >+ }, >+ { /* 2377 */ >+ 0, >+ /* */ >+ }, >+ { /* 2378 */ >+ 0, >+ /* */ >+ }, >+ { /* 2379 */ >+ 195, >+ /* RETIL */ >+ }, >+ { /* 2380 */ >+ 195, >+ /* RETIQ */ >+ }, >+ { /* 2381 */ >+ 2, >+ /* RETIW */ >+ }, >+ { /* 2382 */ >+ 0, >+ /* RETL */ >+ }, >+ { /* 2383 */ >+ 0, >+ /* RETQ */ >+ }, >+ { /* 2384 */ >+ 0, >+ /* RETW */ >+ }, >+ { /* 2385 */ >+ 0, >+ /* REX64_PREFIX */ >+ }, >+ { /* 2386 */ >+ 38, >+ /* ROL16m1 */ >+ }, >+ { /* 2387 */ >+ 38, >+ /* ROL16mCL */ >+ }, >+ { /* 2388 */ >+ 284, >+ /* ROL16mi */ >+ }, >+ { /* 2389 */ >+ 127, >+ /* ROL16r1 */ >+ }, >+ { /* 2390 */ >+ 127, >+ /* ROL16rCL */ >+ }, >+ { /* 2391 */ >+ 285, >+ /* ROL16ri */ >+ }, >+ { /* 2392 */ >+ 38, >+ /* ROL32m1 */ >+ }, >+ { /* 2393 */ >+ 38, >+ /* ROL32mCL */ >+ }, >+ { /* 2394 */ >+ 284, >+ /* ROL32mi */ >+ }, >+ { /* 2395 */ >+ 127, >+ /* ROL32r1 */ >+ }, >+ { /* 2396 */ >+ 127, >+ /* ROL32rCL */ >+ }, >+ { /* 2397 */ >+ 285, >+ /* ROL32ri */ >+ }, >+ { /* 2398 */ >+ 38, >+ /* ROL64m1 */ >+ }, >+ { /* 2399 */ >+ 38, >+ /* ROL64mCL */ >+ }, >+ { /* 2400 */ >+ 284, >+ /* ROL64mi */ >+ }, >+ { /* 2401 */ >+ 128, >+ /* ROL64r1 */ >+ }, >+ { /* 2402 */ >+ 128, >+ /* ROL64rCL */ >+ }, >+ { /* 2403 */ >+ 286, >+ /* ROL64ri */ >+ }, >+ { /* 2404 */ >+ 82, >+ /* ROL8m1 */ >+ }, >+ { /* 2405 */ >+ 82, >+ /* ROL8mCL */ >+ }, >+ { /* 2406 */ >+ 22, >+ /* ROL8mi */ >+ }, >+ { /* 2407 */ >+ 129, >+ /* ROL8r1 */ >+ }, >+ { /* 2408 */ >+ 129, >+ /* ROL8rCL */ >+ }, >+ { /* 2409 */ >+ 24, >+ /* ROL8ri */ >+ }, >+ { /* 2410 */ >+ 38, >+ /* ROR16m1 */ >+ }, >+ { /* 2411 */ >+ 38, >+ /* ROR16mCL */ >+ }, >+ { /* 2412 */ >+ 284, >+ /* ROR16mi */ >+ }, >+ { /* 2413 */ >+ 127, >+ /* ROR16r1 */ >+ }, >+ { /* 2414 */ >+ 127, >+ /* ROR16rCL */ >+ }, >+ { /* 2415 */ >+ 285, >+ /* ROR16ri */ >+ }, >+ { /* 2416 */ >+ 38, >+ /* ROR32m1 */ >+ }, >+ { /* 2417 */ >+ 38, >+ /* ROR32mCL */ >+ }, >+ { /* 2418 */ >+ 284, >+ /* ROR32mi */ >+ }, >+ { /* 2419 */ >+ 127, >+ /* ROR32r1 */ >+ }, >+ { /* 2420 */ >+ 127, >+ /* ROR32rCL */ >+ }, >+ { /* 2421 */ >+ 285, >+ /* ROR32ri */ >+ }, >+ { /* 2422 */ >+ 38, >+ /* ROR64m1 */ >+ }, >+ { /* 2423 */ >+ 38, >+ /* ROR64mCL */ >+ }, >+ { /* 2424 */ >+ 284, >+ /* ROR64mi */ >+ }, >+ { /* 2425 */ >+ 128, >+ /* ROR64r1 */ >+ }, >+ { /* 2426 */ >+ 128, >+ /* ROR64rCL */ >+ }, >+ { /* 2427 */ >+ 286, >+ /* ROR64ri */ >+ }, >+ { /* 2428 */ >+ 82, >+ /* ROR8m1 */ >+ }, >+ { /* 2429 */ >+ 82, >+ /* ROR8mCL */ >+ }, >+ { /* 2430 */ >+ 22, >+ /* ROR8mi */ >+ }, >+ { /* 2431 */ >+ 129, >+ /* ROR8r1 */ >+ }, >+ { /* 2432 */ >+ 129, >+ /* ROR8rCL */ >+ }, >+ { /* 2433 */ >+ 24, >+ /* ROR8ri */ >+ }, >+ { /* 2434 */ >+ 289, >+ /* RORX32mi */ >+ }, >+ { /* 2435 */ >+ 290, >+ /* RORX32ri */ >+ }, >+ { /* 2436 */ >+ 291, >+ /* RORX64mi */ >+ }, >+ { /* 2437 */ >+ 292, >+ /* RORX64ri */ >+ }, >+ { /* 2438 */ >+ 293, >+ /* ROUNDPDm */ >+ }, >+ { /* 2439 */ >+ 294, >+ /* ROUNDPDr */ >+ }, >+ { /* 2440 */ >+ 293, >+ /* ROUNDPSm */ >+ }, >+ { /* 2441 */ >+ 294, >+ /* ROUNDPSr */ >+ }, >+ { /* 2442 */ >+ 295, >+ /* ROUNDSDm */ >+ }, >+ { /* 2443 */ >+ 296, >+ /* ROUNDSDr */ >+ }, >+ { /* 2444 */ >+ 0, >+ /* */ >+ }, >+ { /* 2445 */ >+ 150, >+ /* ROUNDSSm */ >+ }, >+ { /* 2446 */ >+ 297, >+ /* ROUNDSSr */ >+ }, >+ { /* 2447 */ >+ 0, >+ /* */ >+ }, >+ { /* 2448 */ >+ 0, >+ /* RSM */ >+ }, >+ { /* 2449 */ >+ 44, >+ /* RSQRTPSm */ >+ }, >+ { /* 2450 */ >+ 0, >+ /* */ >+ }, >+ { /* 2451 */ >+ 45, >+ /* RSQRTPSr */ >+ }, >+ { /* 2452 */ >+ 0, >+ /* */ >+ }, >+ { /* 2453 */ >+ 258, >+ /* RSQRTSSm */ >+ }, >+ { /* 2454 */ >+ 0, >+ /* */ >+ }, >+ { /* 2455 */ >+ 287, >+ /* RSQRTSSr */ >+ }, >+ { /* 2456 */ >+ 0, >+ /* */ >+ }, >+ { /* 2457 */ >+ 0, >+ /* SAHF */ >+ }, >+ { /* 2458 */ >+ 38, >+ /* SAL16m1 */ >+ }, >+ { /* 2459 */ >+ 38, >+ /* SAL16mCL */ >+ }, >+ { /* 2460 */ >+ 284, >+ /* SAL16mi */ >+ }, >+ { /* 2461 */ >+ 127, >+ /* SAL16r1 */ >+ }, >+ { /* 2462 */ >+ 127, >+ /* SAL16rCL */ >+ }, >+ { /* 2463 */ >+ 285, >+ /* SAL16ri */ >+ }, >+ { /* 2464 */ >+ 38, >+ /* SAL32m1 */ >+ }, >+ { /* 2465 */ >+ 38, >+ /* SAL32mCL */ >+ }, >+ { /* 2466 */ >+ 284, >+ /* SAL32mi */ >+ }, >+ { /* 2467 */ >+ 127, >+ /* SAL32r1 */ >+ }, >+ { /* 2468 */ >+ 127, >+ /* SAL32rCL */ >+ }, >+ { /* 2469 */ >+ 285, >+ /* SAL32ri */ >+ }, >+ { /* 2470 */ >+ 38, >+ /* SAL64m1 */ >+ }, >+ { /* 2471 */ >+ 38, >+ /* SAL64mCL */ >+ }, >+ { /* 2472 */ >+ 284, >+ /* SAL64mi */ >+ }, >+ { /* 2473 */ >+ 128, >+ /* SAL64r1 */ >+ }, >+ { /* 2474 */ >+ 128, >+ /* SAL64rCL */ >+ }, >+ { /* 2475 */ >+ 286, >+ /* SAL64ri */ >+ }, >+ { /* 2476 */ >+ 82, >+ /* SAL8m1 */ >+ }, >+ { /* 2477 */ >+ 82, >+ /* SAL8mCL */ >+ }, >+ { /* 2478 */ >+ 22, >+ /* SAL8mi */ >+ }, >+ { /* 2479 */ >+ 129, >+ /* SAL8r1 */ >+ }, >+ { /* 2480 */ >+ 129, >+ /* SAL8rCL */ >+ }, >+ { /* 2481 */ >+ 24, >+ /* SAL8ri */ >+ }, >+ { /* 2482 */ >+ 0, >+ /* SALC */ >+ }, >+ { /* 2483 */ >+ 38, >+ /* SAR16m1 */ >+ }, >+ { /* 2484 */ >+ 38, >+ /* SAR16mCL */ >+ }, >+ { /* 2485 */ >+ 284, >+ /* SAR16mi */ >+ }, >+ { /* 2486 */ >+ 127, >+ /* SAR16r1 */ >+ }, >+ { /* 2487 */ >+ 127, >+ /* SAR16rCL */ >+ }, >+ { /* 2488 */ >+ 285, >+ /* SAR16ri */ >+ }, >+ { /* 2489 */ >+ 38, >+ /* SAR32m1 */ >+ }, >+ { /* 2490 */ >+ 38, >+ /* SAR32mCL */ >+ }, >+ { /* 2491 */ >+ 284, >+ /* SAR32mi */ >+ }, >+ { /* 2492 */ >+ 127, >+ /* SAR32r1 */ >+ }, >+ { /* 2493 */ >+ 127, >+ /* SAR32rCL */ >+ }, >+ { /* 2494 */ >+ 285, >+ /* SAR32ri */ >+ }, >+ { /* 2495 */ >+ 38, >+ /* SAR64m1 */ >+ }, >+ { /* 2496 */ >+ 38, >+ /* SAR64mCL */ >+ }, >+ { /* 2497 */ >+ 284, >+ /* SAR64mi */ >+ }, >+ { /* 2498 */ >+ 128, >+ /* SAR64r1 */ >+ }, >+ { /* 2499 */ >+ 128, >+ /* SAR64rCL */ >+ }, >+ { /* 2500 */ >+ 286, >+ /* SAR64ri */ >+ }, >+ { /* 2501 */ >+ 82, >+ /* SAR8m1 */ >+ }, >+ { /* 2502 */ >+ 82, >+ /* SAR8mCL */ >+ }, >+ { /* 2503 */ >+ 22, >+ /* SAR8mi */ >+ }, >+ { /* 2504 */ >+ 129, >+ /* SAR8r1 */ >+ }, >+ { /* 2505 */ >+ 129, >+ /* SAR8rCL */ >+ }, >+ { /* 2506 */ >+ 24, >+ /* SAR8ri */ >+ }, >+ { /* 2507 */ >+ 54, >+ /* SARX32rm */ >+ }, >+ { /* 2508 */ >+ 55, >+ /* SARX32rr */ >+ }, >+ { /* 2509 */ >+ 56, >+ /* SARX64rm */ >+ }, >+ { /* 2510 */ >+ 57, >+ /* SARX64rr */ >+ }, >+ { /* 2511 */ >+ 2, >+ /* SBB16i16 */ >+ }, >+ { /* 2512 */ >+ 3, >+ /* SBB16mi */ >+ }, >+ { /* 2513 */ >+ 4, >+ /* SBB16mi8 */ >+ }, >+ { /* 2514 */ >+ 5, >+ /* SBB16mr */ >+ }, >+ { /* 2515 */ >+ 6, >+ /* SBB16ri */ >+ }, >+ { /* 2516 */ >+ 7, >+ /* SBB16ri8 */ >+ }, >+ { /* 2517 */ >+ 8, >+ /* SBB16rm */ >+ }, >+ { /* 2518 */ >+ 9, >+ /* SBB16rr */ >+ }, >+ { /* 2519 */ >+ 10, >+ /* SBB16rr_REV */ >+ }, >+ { /* 2520 */ >+ 2, >+ /* SBB32i32 */ >+ }, >+ { /* 2521 */ >+ 3, >+ /* SBB32mi */ >+ }, >+ { /* 2522 */ >+ 11, >+ /* SBB32mi8 */ >+ }, >+ { /* 2523 */ >+ 5, >+ /* SBB32mr */ >+ }, >+ { /* 2524 */ >+ 6, >+ /* SBB32ri */ >+ }, >+ { /* 2525 */ >+ 12, >+ /* SBB32ri8 */ >+ }, >+ { /* 2526 */ >+ 8, >+ /* SBB32rm */ >+ }, >+ { /* 2527 */ >+ 9, >+ /* SBB32rr */ >+ }, >+ { /* 2528 */ >+ 10, >+ /* SBB32rr_REV */ >+ }, >+ { /* 2529 */ >+ 13, >+ /* SBB64i32 */ >+ }, >+ { /* 2530 */ >+ 14, >+ /* SBB64mi32 */ >+ }, >+ { /* 2531 */ >+ 15, >+ /* SBB64mi8 */ >+ }, >+ { /* 2532 */ >+ 16, >+ /* SBB64mr */ >+ }, >+ { /* 2533 */ >+ 17, >+ /* SBB64ri32 */ >+ }, >+ { /* 2534 */ >+ 18, >+ /* SBB64ri8 */ >+ }, >+ { /* 2535 */ >+ 19, >+ /* SBB64rm */ >+ }, >+ { /* 2536 */ >+ 20, >+ /* SBB64rr */ >+ }, >+ { /* 2537 */ >+ 21, >+ /* SBB64rr_REV */ >+ }, >+ { /* 2538 */ >+ 1, >+ /* SBB8i8 */ >+ }, >+ { /* 2539 */ >+ 22, >+ /* SBB8mi */ >+ }, >+ { /* 2540 */ >+ 23, >+ /* SBB8mr */ >+ }, >+ { /* 2541 */ >+ 24, >+ /* SBB8ri */ >+ }, >+ { /* 2542 */ >+ 25, >+ /* SBB8rm */ >+ }, >+ { /* 2543 */ >+ 26, >+ /* SBB8rr */ >+ }, >+ { /* 2544 */ >+ 27, >+ /* SBB8rr_REV */ >+ }, >+ { /* 2545 */ >+ 149, >+ /* SCASB */ >+ }, >+ { /* 2546 */ >+ 152, >+ /* SCASL */ >+ }, >+ { /* 2547 */ >+ 298, >+ /* SCASQ */ >+ }, >+ { /* 2548 */ >+ 153, >+ /* SCASW */ >+ }, >+ { /* 2549 */ >+ 0, >+ /* */ >+ }, >+ { /* 2550 */ >+ 0, >+ /* */ >+ }, >+ { /* 2551 */ >+ 0, >+ /* */ >+ }, >+ { /* 2552 */ >+ 0, >+ /* */ >+ }, >+ { /* 2553 */ >+ 0, >+ /* */ >+ }, >+ { /* 2554 */ >+ 0, >+ /* */ >+ }, >+ { /* 2555 */ >+ 0, >+ /* */ >+ }, >+ { /* 2556 */ >+ 0, >+ /* */ >+ }, >+ { /* 2557 */ >+ 0, >+ /* */ >+ }, >+ { /* 2558 */ >+ 0, >+ /* */ >+ }, >+ { /* 2559 */ >+ 82, >+ /* SETAEm */ >+ }, >+ { /* 2560 */ >+ 130, >+ /* SETAEr */ >+ }, >+ { /* 2561 */ >+ 82, >+ /* SETAm */ >+ }, >+ { /* 2562 */ >+ 130, >+ /* SETAr */ >+ }, >+ { /* 2563 */ >+ 82, >+ /* SETBEm */ >+ }, >+ { /* 2564 */ >+ 130, >+ /* SETBEr */ >+ }, >+ { /* 2565 */ >+ 0, >+ /* */ >+ }, >+ { /* 2566 */ >+ 0, >+ /* */ >+ }, >+ { /* 2567 */ >+ 0, >+ /* */ >+ }, >+ { /* 2568 */ >+ 0, >+ /* */ >+ }, >+ { /* 2569 */ >+ 82, >+ /* SETBm */ >+ }, >+ { /* 2570 */ >+ 130, >+ /* SETBr */ >+ }, >+ { /* 2571 */ >+ 82, >+ /* SETEm */ >+ }, >+ { /* 2572 */ >+ 130, >+ /* SETEr */ >+ }, >+ { /* 2573 */ >+ 82, >+ /* SETGEm */ >+ }, >+ { /* 2574 */ >+ 130, >+ /* SETGEr */ >+ }, >+ { /* 2575 */ >+ 82, >+ /* SETGm */ >+ }, >+ { /* 2576 */ >+ 130, >+ /* SETGr */ >+ }, >+ { /* 2577 */ >+ 82, >+ /* SETLEm */ >+ }, >+ { /* 2578 */ >+ 130, >+ /* SETLEr */ >+ }, >+ { /* 2579 */ >+ 82, >+ /* SETLm */ >+ }, >+ { /* 2580 */ >+ 130, >+ /* SETLr */ >+ }, >+ { /* 2581 */ >+ 82, >+ /* SETNEm */ >+ }, >+ { /* 2582 */ >+ 130, >+ /* SETNEr */ >+ }, >+ { /* 2583 */ >+ 82, >+ /* SETNOm */ >+ }, >+ { /* 2584 */ >+ 130, >+ /* SETNOr */ >+ }, >+ { /* 2585 */ >+ 82, >+ /* SETNPm */ >+ }, >+ { /* 2586 */ >+ 130, >+ /* SETNPr */ >+ }, >+ { /* 2587 */ >+ 82, >+ /* SETNSm */ >+ }, >+ { /* 2588 */ >+ 130, >+ /* SETNSr */ >+ }, >+ { /* 2589 */ >+ 82, >+ /* SETOm */ >+ }, >+ { /* 2590 */ >+ 130, >+ /* SETOr */ >+ }, >+ { /* 2591 */ >+ 82, >+ /* SETPm */ >+ }, >+ { /* 2592 */ >+ 130, >+ /* SETPr */ >+ }, >+ { /* 2593 */ >+ 82, >+ /* SETSm */ >+ }, >+ { /* 2594 */ >+ 130, >+ /* SETSr */ >+ }, >+ { /* 2595 */ >+ 0, >+ /* SFENCE */ >+ }, >+ { /* 2596 */ >+ 138, >+ /* SGDT16m */ >+ }, >+ { /* 2597 */ >+ 138, >+ /* SGDT32m */ >+ }, >+ { /* 2598 */ >+ 139, >+ /* SGDT64m */ >+ }, >+ { /* 2599 */ >+ 30, >+ /* SHA1MSG1rm */ >+ }, >+ { /* 2600 */ >+ 31, >+ /* SHA1MSG1rr */ >+ }, >+ { /* 2601 */ >+ 30, >+ /* SHA1MSG2rm */ >+ }, >+ { /* 2602 */ >+ 31, >+ /* SHA1MSG2rr */ >+ }, >+ { /* 2603 */ >+ 30, >+ /* SHA1NEXTErm */ >+ }, >+ { /* 2604 */ >+ 31, >+ /* SHA1NEXTErr */ >+ }, >+ { /* 2605 */ >+ 267, >+ /* SHA1RNDS4rmi */ >+ }, >+ { /* 2606 */ >+ 268, >+ /* SHA1RNDS4rri */ >+ }, >+ { /* 2607 */ >+ 30, >+ /* SHA256MSG1rm */ >+ }, >+ { /* 2608 */ >+ 31, >+ /* SHA256MSG1rr */ >+ }, >+ { /* 2609 */ >+ 30, >+ /* SHA256MSG2rm */ >+ }, >+ { /* 2610 */ >+ 31, >+ /* SHA256MSG2rr */ >+ }, >+ { /* 2611 */ >+ 30, >+ /* SHA256RNDS2rm */ >+ }, >+ { /* 2612 */ >+ 31, >+ /* SHA256RNDS2rr */ >+ }, >+ { /* 2613 */ >+ 38, >+ /* SHL16m1 */ >+ }, >+ { /* 2614 */ >+ 38, >+ /* SHL16mCL */ >+ }, >+ { /* 2615 */ >+ 284, >+ /* SHL16mi */ >+ }, >+ { /* 2616 */ >+ 127, >+ /* SHL16r1 */ >+ }, >+ { /* 2617 */ >+ 127, >+ /* SHL16rCL */ >+ }, >+ { /* 2618 */ >+ 285, >+ /* SHL16ri */ >+ }, >+ { /* 2619 */ >+ 38, >+ /* SHL32m1 */ >+ }, >+ { /* 2620 */ >+ 38, >+ /* SHL32mCL */ >+ }, >+ { /* 2621 */ >+ 284, >+ /* SHL32mi */ >+ }, >+ { /* 2622 */ >+ 127, >+ /* SHL32r1 */ >+ }, >+ { /* 2623 */ >+ 127, >+ /* SHL32rCL */ >+ }, >+ { /* 2624 */ >+ 285, >+ /* SHL32ri */ >+ }, >+ { /* 2625 */ >+ 38, >+ /* SHL64m1 */ >+ }, >+ { /* 2626 */ >+ 38, >+ /* SHL64mCL */ >+ }, >+ { /* 2627 */ >+ 284, >+ /* SHL64mi */ >+ }, >+ { /* 2628 */ >+ 128, >+ /* SHL64r1 */ >+ }, >+ { /* 2629 */ >+ 128, >+ /* SHL64rCL */ >+ }, >+ { /* 2630 */ >+ 286, >+ /* SHL64ri */ >+ }, >+ { /* 2631 */ >+ 82, >+ /* SHL8m1 */ >+ }, >+ { /* 2632 */ >+ 82, >+ /* SHL8mCL */ >+ }, >+ { /* 2633 */ >+ 22, >+ /* SHL8mi */ >+ }, >+ { /* 2634 */ >+ 129, >+ /* SHL8r1 */ >+ }, >+ { /* 2635 */ >+ 129, >+ /* SHL8rCL */ >+ }, >+ { /* 2636 */ >+ 24, >+ /* SHL8ri */ >+ }, >+ { /* 2637 */ >+ 5, >+ /* SHLD16mrCL */ >+ }, >+ { /* 2638 */ >+ 299, >+ /* SHLD16mri8 */ >+ }, >+ { /* 2639 */ >+ 9, >+ /* SHLD16rrCL */ >+ }, >+ { /* 2640 */ >+ 300, >+ /* SHLD16rri8 */ >+ }, >+ { /* 2641 */ >+ 5, >+ /* SHLD32mrCL */ >+ }, >+ { /* 2642 */ >+ 299, >+ /* SHLD32mri8 */ >+ }, >+ { /* 2643 */ >+ 9, >+ /* SHLD32rrCL */ >+ }, >+ { /* 2644 */ >+ 300, >+ /* SHLD32rri8 */ >+ }, >+ { /* 2645 */ >+ 16, >+ /* SHLD64mrCL */ >+ }, >+ { /* 2646 */ >+ 301, >+ /* SHLD64mri8 */ >+ }, >+ { /* 2647 */ >+ 20, >+ /* SHLD64rrCL */ >+ }, >+ { /* 2648 */ >+ 302, >+ /* SHLD64rri8 */ >+ }, >+ { /* 2649 */ >+ 54, >+ /* SHLX32rm */ >+ }, >+ { /* 2650 */ >+ 55, >+ /* SHLX32rr */ >+ }, >+ { /* 2651 */ >+ 56, >+ /* SHLX64rm */ >+ }, >+ { /* 2652 */ >+ 57, >+ /* SHLX64rr */ >+ }, >+ { /* 2653 */ >+ 38, >+ /* SHR16m1 */ >+ }, >+ { /* 2654 */ >+ 38, >+ /* SHR16mCL */ >+ }, >+ { /* 2655 */ >+ 284, >+ /* SHR16mi */ >+ }, >+ { /* 2656 */ >+ 127, >+ /* SHR16r1 */ >+ }, >+ { /* 2657 */ >+ 127, >+ /* SHR16rCL */ >+ }, >+ { /* 2658 */ >+ 285, >+ /* SHR16ri */ >+ }, >+ { /* 2659 */ >+ 38, >+ /* SHR32m1 */ >+ }, >+ { /* 2660 */ >+ 38, >+ /* SHR32mCL */ >+ }, >+ { /* 2661 */ >+ 284, >+ /* SHR32mi */ >+ }, >+ { /* 2662 */ >+ 127, >+ /* SHR32r1 */ >+ }, >+ { /* 2663 */ >+ 127, >+ /* SHR32rCL */ >+ }, >+ { /* 2664 */ >+ 285, >+ /* SHR32ri */ >+ }, >+ { /* 2665 */ >+ 38, >+ /* SHR64m1 */ >+ }, >+ { /* 2666 */ >+ 38, >+ /* SHR64mCL */ >+ }, >+ { /* 2667 */ >+ 284, >+ /* SHR64mi */ >+ }, >+ { /* 2668 */ >+ 128, >+ /* SHR64r1 */ >+ }, >+ { /* 2669 */ >+ 128, >+ /* SHR64rCL */ >+ }, >+ { /* 2670 */ >+ 286, >+ /* SHR64ri */ >+ }, >+ { /* 2671 */ >+ 82, >+ /* SHR8m1 */ >+ }, >+ { /* 2672 */ >+ 82, >+ /* SHR8mCL */ >+ }, >+ { /* 2673 */ >+ 22, >+ /* SHR8mi */ >+ }, >+ { /* 2674 */ >+ 129, >+ /* SHR8r1 */ >+ }, >+ { /* 2675 */ >+ 129, >+ /* SHR8rCL */ >+ }, >+ { /* 2676 */ >+ 24, >+ /* SHR8ri */ >+ }, >+ { /* 2677 */ >+ 5, >+ /* SHRD16mrCL */ >+ }, >+ { /* 2678 */ >+ 299, >+ /* SHRD16mri8 */ >+ }, >+ { /* 2679 */ >+ 9, >+ /* SHRD16rrCL */ >+ }, >+ { /* 2680 */ >+ 300, >+ /* SHRD16rri8 */ >+ }, >+ { /* 2681 */ >+ 5, >+ /* SHRD32mrCL */ >+ }, >+ { /* 2682 */ >+ 299, >+ /* SHRD32mri8 */ >+ }, >+ { /* 2683 */ >+ 9, >+ /* SHRD32rrCL */ >+ }, >+ { /* 2684 */ >+ 300, >+ /* SHRD32rri8 */ >+ }, >+ { /* 2685 */ >+ 16, >+ /* SHRD64mrCL */ >+ }, >+ { /* 2686 */ >+ 301, >+ /* SHRD64mri8 */ >+ }, >+ { /* 2687 */ >+ 20, >+ /* SHRD64rrCL */ >+ }, >+ { /* 2688 */ >+ 302, >+ /* SHRD64rri8 */ >+ }, >+ { /* 2689 */ >+ 54, >+ /* SHRX32rm */ >+ }, >+ { /* 2690 */ >+ 55, >+ /* SHRX32rr */ >+ }, >+ { /* 2691 */ >+ 56, >+ /* SHRX64rm */ >+ }, >+ { /* 2692 */ >+ 57, >+ /* SHRX64rr */ >+ }, >+ { /* 2693 */ >+ 267, >+ /* SHUFPDrmi */ >+ }, >+ { /* 2694 */ >+ 268, >+ /* SHUFPDrri */ >+ }, >+ { /* 2695 */ >+ 267, >+ /* SHUFPSrmi */ >+ }, >+ { /* 2696 */ >+ 268, >+ /* SHUFPSrri */ >+ }, >+ { /* 2697 */ >+ 138, >+ /* SIDT16m */ >+ }, >+ { /* 2698 */ >+ 138, >+ /* SIDT32m */ >+ }, >+ { /* 2699 */ >+ 139, >+ /* SIDT64m */ >+ }, >+ { /* 2700 */ >+ 0, >+ /* SIN_F */ >+ }, >+ { /* 2701 */ >+ 0, >+ /* */ >+ }, >+ { /* 2702 */ >+ 0, >+ /* */ >+ }, >+ { /* 2703 */ >+ 0, >+ /* */ >+ }, >+ { /* 2704 */ >+ 0, >+ /* SKINIT */ >+ }, >+ { /* 2705 */ >+ 38, >+ /* SLDT16m */ >+ }, >+ { /* 2706 */ >+ 77, >+ /* SLDT16r */ >+ }, >+ { /* 2707 */ >+ 77, >+ /* SLDT32r */ >+ }, >+ { /* 2708 */ >+ 38, >+ /* SLDT64m */ >+ }, >+ { /* 2709 */ >+ 79, >+ /* SLDT64r */ >+ }, >+ { /* 2710 */ >+ 38, >+ /* SMSW16m */ >+ }, >+ { /* 2711 */ >+ 77, >+ /* SMSW16r */ >+ }, >+ { /* 2712 */ >+ 77, >+ /* SMSW32r */ >+ }, >+ { /* 2713 */ >+ 79, >+ /* SMSW64r */ >+ }, >+ { /* 2714 */ >+ 44, >+ /* SQRTPDm */ >+ }, >+ { /* 2715 */ >+ 45, >+ /* SQRTPDr */ >+ }, >+ { /* 2716 */ >+ 44, >+ /* SQRTPSm */ >+ }, >+ { /* 2717 */ >+ 45, >+ /* SQRTPSr */ >+ }, >+ { /* 2718 */ >+ 254, >+ /* SQRTSDm */ >+ }, >+ { /* 2719 */ >+ 0, >+ /* */ >+ }, >+ { /* 2720 */ >+ 303, >+ /* SQRTSDr */ >+ }, >+ { /* 2721 */ >+ 0, >+ /* */ >+ }, >+ { /* 2722 */ >+ 258, >+ /* SQRTSSm */ >+ }, >+ { /* 2723 */ >+ 0, >+ /* */ >+ }, >+ { /* 2724 */ >+ 287, >+ /* SQRTSSr */ >+ }, >+ { /* 2725 */ >+ 0, >+ /* */ >+ }, >+ { /* 2726 */ >+ 0, >+ /* SQRT_F */ >+ }, >+ { /* 2727 */ >+ 0, >+ /* */ >+ }, >+ { /* 2728 */ >+ 0, >+ /* */ >+ }, >+ { /* 2729 */ >+ 0, >+ /* */ >+ }, >+ { /* 2730 */ >+ 0, >+ /* STAC */ >+ }, >+ { /* 2731 */ >+ 0, >+ /* STC */ >+ }, >+ { /* 2732 */ >+ 0, >+ /* STD */ >+ }, >+ { /* 2733 */ >+ 0, >+ /* STGI */ >+ }, >+ { /* 2734 */ >+ 0, >+ /* STI */ >+ }, >+ { /* 2735 */ >+ 38, >+ /* STMXCSR */ >+ }, >+ { /* 2736 */ >+ 149, >+ /* STOSB */ >+ }, >+ { /* 2737 */ >+ 152, >+ /* STOSL */ >+ }, >+ { /* 2738 */ >+ 298, >+ /* STOSQ */ >+ }, >+ { /* 2739 */ >+ 153, >+ /* STOSW */ >+ }, >+ { /* 2740 */ >+ 77, >+ /* STR16r */ >+ }, >+ { /* 2741 */ >+ 77, >+ /* STR32r */ >+ }, >+ { /* 2742 */ >+ 79, >+ /* STR64r */ >+ }, >+ { /* 2743 */ >+ 38, >+ /* STRm */ >+ }, >+ { /* 2744 */ >+ 36, >+ /* ST_F32m */ >+ }, >+ { /* 2745 */ >+ 37, >+ /* ST_F64m */ >+ }, >+ { /* 2746 */ >+ 39, >+ /* ST_FCOMPST0r */ >+ }, >+ { /* 2747 */ >+ 39, >+ /* ST_FCOMPST0r_alt */ >+ }, >+ { /* 2748 */ >+ 39, >+ /* ST_FCOMST0r */ >+ }, >+ { /* 2749 */ >+ 36, >+ /* ST_FP32m */ >+ }, >+ { /* 2750 */ >+ 37, >+ /* ST_FP64m */ >+ }, >+ { /* 2751 */ >+ 186, >+ /* ST_FP80m */ >+ }, >+ { /* 2752 */ >+ 39, >+ /* ST_FPNCEST0r */ >+ }, >+ { /* 2753 */ >+ 39, >+ /* ST_FPST0r */ >+ }, >+ { /* 2754 */ >+ 39, >+ /* ST_FPST0r_alt */ >+ }, >+ { /* 2755 */ >+ 39, >+ /* ST_FPrr */ >+ }, >+ { /* 2756 */ >+ 39, >+ /* ST_FXCHST0r */ >+ }, >+ { /* 2757 */ >+ 39, >+ /* ST_FXCHST0r_alt */ >+ }, >+ { /* 2758 */ >+ 0, >+ /* */ >+ }, >+ { /* 2759 */ >+ 0, >+ /* */ >+ }, >+ { /* 2760 */ >+ 0, >+ /* */ >+ }, >+ { /* 2761 */ >+ 0, >+ /* */ >+ }, >+ { /* 2762 */ >+ 0, >+ /* */ >+ }, >+ { /* 2763 */ >+ 0, >+ /* */ >+ }, >+ { /* 2764 */ >+ 0, >+ /* */ >+ }, >+ { /* 2765 */ >+ 0, >+ /* */ >+ }, >+ { /* 2766 */ >+ 0, >+ /* */ >+ }, >+ { /* 2767 */ >+ 0, >+ /* */ >+ }, >+ { /* 2768 */ >+ 0, >+ /* */ >+ }, >+ { /* 2769 */ >+ 39, >+ /* ST_Frr */ >+ }, >+ { /* 2770 */ >+ 2, >+ /* SUB16i16 */ >+ }, >+ { /* 2771 */ >+ 3, >+ /* SUB16mi */ >+ }, >+ { /* 2772 */ >+ 4, >+ /* SUB16mi8 */ >+ }, >+ { /* 2773 */ >+ 5, >+ /* SUB16mr */ >+ }, >+ { /* 2774 */ >+ 6, >+ /* SUB16ri */ >+ }, >+ { /* 2775 */ >+ 7, >+ /* SUB16ri8 */ >+ }, >+ { /* 2776 */ >+ 8, >+ /* SUB16rm */ >+ }, >+ { /* 2777 */ >+ 9, >+ /* SUB16rr */ >+ }, >+ { /* 2778 */ >+ 10, >+ /* SUB16rr_REV */ >+ }, >+ { /* 2779 */ >+ 2, >+ /* SUB32i32 */ >+ }, >+ { /* 2780 */ >+ 3, >+ /* SUB32mi */ >+ }, >+ { /* 2781 */ >+ 11, >+ /* SUB32mi8 */ >+ }, >+ { /* 2782 */ >+ 5, >+ /* SUB32mr */ >+ }, >+ { /* 2783 */ >+ 6, >+ /* SUB32ri */ >+ }, >+ { /* 2784 */ >+ 12, >+ /* SUB32ri8 */ >+ }, >+ { /* 2785 */ >+ 8, >+ /* SUB32rm */ >+ }, >+ { /* 2786 */ >+ 9, >+ /* SUB32rr */ >+ }, >+ { /* 2787 */ >+ 10, >+ /* SUB32rr_REV */ >+ }, >+ { /* 2788 */ >+ 13, >+ /* SUB64i32 */ >+ }, >+ { /* 2789 */ >+ 14, >+ /* SUB64mi32 */ >+ }, >+ { /* 2790 */ >+ 15, >+ /* SUB64mi8 */ >+ }, >+ { /* 2791 */ >+ 16, >+ /* SUB64mr */ >+ }, >+ { /* 2792 */ >+ 17, >+ /* SUB64ri32 */ >+ }, >+ { /* 2793 */ >+ 18, >+ /* SUB64ri8 */ >+ }, >+ { /* 2794 */ >+ 19, >+ /* SUB64rm */ >+ }, >+ { /* 2795 */ >+ 20, >+ /* SUB64rr */ >+ }, >+ { /* 2796 */ >+ 21, >+ /* SUB64rr_REV */ >+ }, >+ { /* 2797 */ >+ 1, >+ /* SUB8i8 */ >+ }, >+ { /* 2798 */ >+ 22, >+ /* SUB8mi */ >+ }, >+ { /* 2799 */ >+ 23, >+ /* SUB8mr */ >+ }, >+ { /* 2800 */ >+ 24, >+ /* SUB8ri */ >+ }, >+ { /* 2801 */ >+ 24, >+ /* SUB8ri8 */ >+ }, >+ { /* 2802 */ >+ 25, >+ /* SUB8rm */ >+ }, >+ { /* 2803 */ >+ 26, >+ /* SUB8rr */ >+ }, >+ { /* 2804 */ >+ 27, >+ /* SUB8rr_REV */ >+ }, >+ { /* 2805 */ >+ 30, >+ /* SUBPDrm */ >+ }, >+ { /* 2806 */ >+ 31, >+ /* SUBPDrr */ >+ }, >+ { /* 2807 */ >+ 30, >+ /* SUBPSrm */ >+ }, >+ { /* 2808 */ >+ 31, >+ /* SUBPSrr */ >+ }, >+ { /* 2809 */ >+ 36, >+ /* SUBR_F32m */ >+ }, >+ { /* 2810 */ >+ 37, >+ /* SUBR_F64m */ >+ }, >+ { /* 2811 */ >+ 38, >+ /* SUBR_FI16m */ >+ }, >+ { /* 2812 */ >+ 38, >+ /* SUBR_FI32m */ >+ }, >+ { /* 2813 */ >+ 39, >+ /* SUBR_FPrST0 */ >+ }, >+ { /* 2814 */ >+ 39, >+ /* SUBR_FST0r */ >+ }, >+ { /* 2815 */ >+ 0, >+ /* */ >+ }, >+ { /* 2816 */ >+ 0, >+ /* */ >+ }, >+ { /* 2817 */ >+ 0, >+ /* */ >+ }, >+ { /* 2818 */ >+ 0, >+ /* */ >+ }, >+ { /* 2819 */ >+ 0, >+ /* */ >+ }, >+ { /* 2820 */ >+ 0, >+ /* */ >+ }, >+ { /* 2821 */ >+ 0, >+ /* */ >+ }, >+ { /* 2822 */ >+ 0, >+ /* */ >+ }, >+ { /* 2823 */ >+ 0, >+ /* */ >+ }, >+ { /* 2824 */ >+ 0, >+ /* */ >+ }, >+ { /* 2825 */ >+ 0, >+ /* */ >+ }, >+ { /* 2826 */ >+ 39, >+ /* SUBR_FrST0 */ >+ }, >+ { /* 2827 */ >+ 32, >+ /* SUBSDrm */ >+ }, >+ { /* 2828 */ >+ 0, >+ /* */ >+ }, >+ { /* 2829 */ >+ 33, >+ /* SUBSDrr */ >+ }, >+ { /* 2830 */ >+ 0, >+ /* */ >+ }, >+ { /* 2831 */ >+ 34, >+ /* SUBSSrm */ >+ }, >+ { /* 2832 */ >+ 0, >+ /* */ >+ }, >+ { /* 2833 */ >+ 35, >+ /* SUBSSrr */ >+ }, >+ { /* 2834 */ >+ 0, >+ /* */ >+ }, >+ { /* 2835 */ >+ 36, >+ /* SUB_F32m */ >+ }, >+ { /* 2836 */ >+ 37, >+ /* SUB_F64m */ >+ }, >+ { /* 2837 */ >+ 38, >+ /* SUB_FI16m */ >+ }, >+ { /* 2838 */ >+ 38, >+ /* SUB_FI32m */ >+ }, >+ { /* 2839 */ >+ 39, >+ /* SUB_FPrST0 */ >+ }, >+ { /* 2840 */ >+ 39, >+ /* SUB_FST0r */ >+ }, >+ { /* 2841 */ >+ 0, >+ /* */ >+ }, >+ { /* 2842 */ >+ 0, >+ /* */ >+ }, >+ { /* 2843 */ >+ 0, >+ /* */ >+ }, >+ { /* 2844 */ >+ 0, >+ /* */ >+ }, >+ { /* 2845 */ >+ 0, >+ /* */ >+ }, >+ { /* 2846 */ >+ 0, >+ /* */ >+ }, >+ { /* 2847 */ >+ 0, >+ /* */ >+ }, >+ { /* 2848 */ >+ 0, >+ /* */ >+ }, >+ { /* 2849 */ >+ 0, >+ /* */ >+ }, >+ { /* 2850 */ >+ 0, >+ /* */ >+ }, >+ { /* 2851 */ >+ 0, >+ /* */ >+ }, >+ { /* 2852 */ >+ 0, >+ /* */ >+ }, >+ { /* 2853 */ >+ 0, >+ /* */ >+ }, >+ { /* 2854 */ >+ 0, >+ /* */ >+ }, >+ { /* 2855 */ >+ 39, >+ /* SUB_FrST0 */ >+ }, >+ { /* 2856 */ >+ 0, >+ /* SWAPGS */ >+ }, >+ { /* 2857 */ >+ 0, >+ /* SYSCALL */ >+ }, >+ { /* 2858 */ >+ 0, >+ /* SYSENTER */ >+ }, >+ { /* 2859 */ >+ 0, >+ /* SYSEXIT */ >+ }, >+ { /* 2860 */ >+ 0, >+ /* SYSEXIT64 */ >+ }, >+ { /* 2861 */ >+ 0, >+ /* SYSRET */ >+ }, >+ { /* 2862 */ >+ 0, >+ /* SYSRET64 */ >+ }, >+ { /* 2863 */ >+ 62, >+ /* T1MSKC32rm */ >+ }, >+ { /* 2864 */ >+ 63, >+ /* T1MSKC32rr */ >+ }, >+ { /* 2865 */ >+ 64, >+ /* T1MSKC64rm */ >+ }, >+ { /* 2866 */ >+ 65, >+ /* T1MSKC64rr */ >+ }, >+ { /* 2867 */ >+ 0, >+ /* */ >+ }, >+ { /* 2868 */ >+ 0, >+ /* */ >+ }, >+ { /* 2869 */ >+ 0, >+ /* */ >+ }, >+ { /* 2870 */ >+ 0, >+ /* */ >+ }, >+ { /* 2871 */ >+ 0, >+ /* */ >+ }, >+ { /* 2872 */ >+ 0, >+ /* */ >+ }, >+ { /* 2873 */ >+ 0, >+ /* */ >+ }, >+ { /* 2874 */ >+ 0, >+ /* */ >+ }, >+ { /* 2875 */ >+ 0, >+ /* */ >+ }, >+ { /* 2876 */ >+ 0, >+ /* */ >+ }, >+ { /* 2877 */ >+ 0, >+ /* */ >+ }, >+ { /* 2878 */ >+ 0, >+ /* */ >+ }, >+ { /* 2879 */ >+ 2, >+ /* TEST16i16 */ >+ }, >+ { /* 2880 */ >+ 3, >+ /* TEST16mi */ >+ }, >+ { /* 2881 */ >+ 3, >+ /* TEST16mi_alt */ >+ }, >+ { /* 2882 */ >+ 83, >+ /* TEST16ri */ >+ }, >+ { /* 2883 */ >+ 83, >+ /* TEST16ri_alt */ >+ }, >+ { /* 2884 */ >+ 5, >+ /* TEST16rm */ >+ }, >+ { /* 2885 */ >+ 73, >+ /* TEST16rr */ >+ }, >+ { /* 2886 */ >+ 2, >+ /* TEST32i32 */ >+ }, >+ { /* 2887 */ >+ 3, >+ /* TEST32mi */ >+ }, >+ { /* 2888 */ >+ 3, >+ /* TEST32mi_alt */ >+ }, >+ { /* 2889 */ >+ 83, >+ /* TEST32ri */ >+ }, >+ { /* 2890 */ >+ 83, >+ /* TEST32ri_alt */ >+ }, >+ { /* 2891 */ >+ 5, >+ /* TEST32rm */ >+ }, >+ { /* 2892 */ >+ 73, >+ /* TEST32rr */ >+ }, >+ { /* 2893 */ >+ 13, >+ /* TEST64i32 */ >+ }, >+ { /* 2894 */ >+ 14, >+ /* TEST64mi32 */ >+ }, >+ { /* 2895 */ >+ 14, >+ /* TEST64mi32_alt */ >+ }, >+ { /* 2896 */ >+ 84, >+ /* TEST64ri32 */ >+ }, >+ { /* 2897 */ >+ 84, >+ /* TEST64ri32_alt */ >+ }, >+ { /* 2898 */ >+ 16, >+ /* TEST64rm */ >+ }, >+ { /* 2899 */ >+ 76, >+ /* TEST64rr */ >+ }, >+ { /* 2900 */ >+ 1, >+ /* TEST8i8 */ >+ }, >+ { /* 2901 */ >+ 22, >+ /* TEST8mi */ >+ }, >+ { /* 2902 */ >+ 22, >+ /* TEST8mi_alt */ >+ }, >+ { /* 2903 */ >+ 85, >+ /* TEST8ri */ >+ }, >+ { /* 2904 */ >+ 0, >+ /* */ >+ }, >+ { /* 2905 */ >+ 85, >+ /* TEST8ri_alt */ >+ }, >+ { /* 2906 */ >+ 23, >+ /* TEST8rm */ >+ }, >+ { /* 2907 */ >+ 87, >+ /* TEST8rr */ >+ }, >+ { /* 2908 */ >+ 0, >+ /* */ >+ }, >+ { /* 2909 */ >+ 0, >+ /* */ >+ }, >+ { /* 2910 */ >+ 0, >+ /* */ >+ }, >+ { /* 2911 */ >+ 0, >+ /* */ >+ }, >+ { /* 2912 */ >+ 0, >+ /* */ >+ }, >+ { /* 2913 */ >+ 0, >+ /* */ >+ }, >+ { /* 2914 */ >+ 0, >+ /* TRAP */ >+ }, >+ { /* 2915 */ >+ 0, >+ /* TST_F */ >+ }, >+ { /* 2916 */ >+ 0, >+ /* */ >+ }, >+ { /* 2917 */ >+ 0, >+ /* */ >+ }, >+ { /* 2918 */ >+ 0, >+ /* */ >+ }, >+ { /* 2919 */ >+ 68, >+ /* TZCNT16rm */ >+ }, >+ { /* 2920 */ >+ 69, >+ /* TZCNT16rr */ >+ }, >+ { /* 2921 */ >+ 68, >+ /* TZCNT32rm */ >+ }, >+ { /* 2922 */ >+ 69, >+ /* TZCNT32rr */ >+ }, >+ { /* 2923 */ >+ 42, >+ /* TZCNT64rm */ >+ }, >+ { /* 2924 */ >+ 43, >+ /* TZCNT64rr */ >+ }, >+ { /* 2925 */ >+ 62, >+ /* TZMSK32rm */ >+ }, >+ { /* 2926 */ >+ 63, >+ /* TZMSK32rr */ >+ }, >+ { /* 2927 */ >+ 64, >+ /* TZMSK64rm */ >+ }, >+ { /* 2928 */ >+ 65, >+ /* TZMSK64rr */ >+ }, >+ { /* 2929 */ >+ 254, >+ /* UCOMISDrm */ >+ }, >+ { /* 2930 */ >+ 303, >+ /* UCOMISDrr */ >+ }, >+ { /* 2931 */ >+ 258, >+ /* UCOMISSrm */ >+ }, >+ { /* 2932 */ >+ 287, >+ /* UCOMISSrr */ >+ }, >+ { /* 2933 */ >+ 39, >+ /* UCOM_FIPr */ >+ }, >+ { /* 2934 */ >+ 39, >+ /* UCOM_FIr */ >+ }, >+ { /* 2935 */ >+ 0, >+ /* UCOM_FPPr */ >+ }, >+ { /* 2936 */ >+ 39, >+ /* UCOM_FPr */ >+ }, >+ { /* 2937 */ >+ 0, >+ /* */ >+ }, >+ { /* 2938 */ >+ 0, >+ /* */ >+ }, >+ { /* 2939 */ >+ 0, >+ /* */ >+ }, >+ { /* 2940 */ >+ 0, >+ /* */ >+ }, >+ { /* 2941 */ >+ 0, >+ /* */ >+ }, >+ { /* 2942 */ >+ 0, >+ /* */ >+ }, >+ { /* 2943 */ >+ 39, >+ /* UCOM_Fr */ >+ }, >+ { /* 2944 */ >+ 0, >+ /* UD2B */ >+ }, >+ { /* 2945 */ >+ 30, >+ /* UNPCKHPDrm */ >+ }, >+ { /* 2946 */ >+ 31, >+ /* UNPCKHPDrr */ >+ }, >+ { /* 2947 */ >+ 30, >+ /* UNPCKHPSrm */ >+ }, >+ { /* 2948 */ >+ 31, >+ /* UNPCKHPSrr */ >+ }, >+ { /* 2949 */ >+ 30, >+ /* UNPCKLPDrm */ >+ }, >+ { /* 2950 */ >+ 31, >+ /* UNPCKLPDrr */ >+ }, >+ { /* 2951 */ >+ 30, >+ /* UNPCKLPSrm */ >+ }, >+ { /* 2952 */ >+ 31, >+ /* UNPCKLPSrr */ >+ }, >+ { /* 2953 */ >+ 0, >+ /* */ >+ }, >+ { /* 2954 */ >+ 304, >+ /* VADDPDYrm */ >+ }, >+ { /* 2955 */ >+ 305, >+ /* VADDPDYrr */ >+ }, >+ { /* 2956 */ >+ 306, >+ /* VADDPDZrm */ >+ }, >+ { /* 2957 */ >+ 307, >+ /* VADDPDZrmb */ >+ }, >+ { /* 2958 */ >+ 308, >+ /* VADDPDZrmbk */ >+ }, >+ { /* 2959 */ >+ 308, >+ /* VADDPDZrmbkz */ >+ }, >+ { /* 2960 */ >+ 309, >+ /* VADDPDZrmk */ >+ }, >+ { /* 2961 */ >+ 309, >+ /* VADDPDZrmkz */ >+ }, >+ { /* 2962 */ >+ 310, >+ /* VADDPDZrr */ >+ }, >+ { /* 2963 */ >+ 311, >+ /* VADDPDZrrk */ >+ }, >+ { /* 2964 */ >+ 311, >+ /* VADDPDZrrkz */ >+ }, >+ { /* 2965 */ >+ 312, >+ /* VADDPDrm */ >+ }, >+ { /* 2966 */ >+ 313, >+ /* VADDPDrr */ >+ }, >+ { /* 2967 */ >+ 304, >+ /* VADDPSYrm */ >+ }, >+ { /* 2968 */ >+ 305, >+ /* VADDPSYrr */ >+ }, >+ { /* 2969 */ >+ 306, >+ /* VADDPSZrm */ >+ }, >+ { /* 2970 */ >+ 314, >+ /* VADDPSZrmb */ >+ }, >+ { /* 2971 */ >+ 315, >+ /* VADDPSZrmbk */ >+ }, >+ { /* 2972 */ >+ 315, >+ /* VADDPSZrmbkz */ >+ }, >+ { /* 2973 */ >+ 316, >+ /* VADDPSZrmk */ >+ }, >+ { /* 2974 */ >+ 316, >+ /* VADDPSZrmkz */ >+ }, >+ { /* 2975 */ >+ 310, >+ /* VADDPSZrr */ >+ }, >+ { /* 2976 */ >+ 317, >+ /* VADDPSZrrk */ >+ }, >+ { /* 2977 */ >+ 317, >+ /* VADDPSZrrkz */ >+ }, >+ { /* 2978 */ >+ 312, >+ /* VADDPSrm */ >+ }, >+ { /* 2979 */ >+ 313, >+ /* VADDPSrr */ >+ }, >+ { /* 2980 */ >+ 318, >+ /* VADDSDZrm */ >+ }, >+ { /* 2981 */ >+ 319, >+ /* VADDSDZrr */ >+ }, >+ { /* 2982 */ >+ 320, >+ /* VADDSDrm */ >+ }, >+ { /* 2983 */ >+ 0, >+ /* */ >+ }, >+ { /* 2984 */ >+ 321, >+ /* VADDSDrr */ >+ }, >+ { /* 2985 */ >+ 0, >+ /* */ >+ }, >+ { /* 2986 */ >+ 322, >+ /* VADDSSZrm */ >+ }, >+ { /* 2987 */ >+ 323, >+ /* VADDSSZrr */ >+ }, >+ { /* 2988 */ >+ 324, >+ /* VADDSSrm */ >+ }, >+ { /* 2989 */ >+ 0, >+ /* */ >+ }, >+ { /* 2990 */ >+ 325, >+ /* VADDSSrr */ >+ }, >+ { /* 2991 */ >+ 0, >+ /* */ >+ }, >+ { /* 2992 */ >+ 304, >+ /* VADDSUBPDYrm */ >+ }, >+ { /* 2993 */ >+ 305, >+ /* VADDSUBPDYrr */ >+ }, >+ { /* 2994 */ >+ 312, >+ /* VADDSUBPDrm */ >+ }, >+ { /* 2995 */ >+ 313, >+ /* VADDSUBPDrr */ >+ }, >+ { /* 2996 */ >+ 304, >+ /* VADDSUBPSYrm */ >+ }, >+ { /* 2997 */ >+ 305, >+ /* VADDSUBPSYrr */ >+ }, >+ { /* 2998 */ >+ 312, >+ /* VADDSUBPSrm */ >+ }, >+ { /* 2999 */ >+ 313, >+ /* VADDSUBPSrr */ >+ }, >+ { /* 3000 */ >+ 312, >+ /* VAESDECLASTrm */ >+ }, >+ { /* 3001 */ >+ 313, >+ /* VAESDECLASTrr */ >+ }, >+ { /* 3002 */ >+ 312, >+ /* VAESDECrm */ >+ }, >+ { /* 3003 */ >+ 313, >+ /* VAESDECrr */ >+ }, >+ { /* 3004 */ >+ 312, >+ /* VAESENCLASTrm */ >+ }, >+ { /* 3005 */ >+ 313, >+ /* VAESENCLASTrr */ >+ }, >+ { /* 3006 */ >+ 312, >+ /* VAESENCrm */ >+ }, >+ { /* 3007 */ >+ 313, >+ /* VAESENCrr */ >+ }, >+ { /* 3008 */ >+ 44, >+ /* VAESIMCrm */ >+ }, >+ { /* 3009 */ >+ 45, >+ /* VAESIMCrr */ >+ }, >+ { /* 3010 */ >+ 46, >+ /* VAESKEYGENASSIST128rm */ >+ }, >+ { /* 3011 */ >+ 47, >+ /* VAESKEYGENASSIST128rr */ >+ }, >+ { /* 3012 */ >+ 326, >+ /* VALIGNDrmi */ >+ }, >+ { /* 3013 */ >+ 327, >+ /* VALIGNDrri */ >+ }, >+ { /* 3014 */ >+ 328, >+ /* VALIGNDrrik */ >+ }, >+ { /* 3015 */ >+ 329, >+ /* VALIGNDrrikz */ >+ }, >+ { /* 3016 */ >+ 326, >+ /* VALIGNQrmi */ >+ }, >+ { /* 3017 */ >+ 327, >+ /* VALIGNQrri */ >+ }, >+ { /* 3018 */ >+ 330, >+ /* VALIGNQrrik */ >+ }, >+ { /* 3019 */ >+ 331, >+ /* VALIGNQrrikz */ >+ }, >+ { /* 3020 */ >+ 304, >+ /* VANDNPDYrm */ >+ }, >+ { /* 3021 */ >+ 305, >+ /* VANDNPDYrr */ >+ }, >+ { /* 3022 */ >+ 312, >+ /* VANDNPDrm */ >+ }, >+ { /* 3023 */ >+ 313, >+ /* VANDNPDrr */ >+ }, >+ { /* 3024 */ >+ 304, >+ /* VANDNPSYrm */ >+ }, >+ { /* 3025 */ >+ 305, >+ /* VANDNPSYrr */ >+ }, >+ { /* 3026 */ >+ 312, >+ /* VANDNPSrm */ >+ }, >+ { /* 3027 */ >+ 313, >+ /* VANDNPSrr */ >+ }, >+ { /* 3028 */ >+ 304, >+ /* VANDPDYrm */ >+ }, >+ { /* 3029 */ >+ 305, >+ /* VANDPDYrr */ >+ }, >+ { /* 3030 */ >+ 312, >+ /* VANDPDrm */ >+ }, >+ { /* 3031 */ >+ 313, >+ /* VANDPDrr */ >+ }, >+ { /* 3032 */ >+ 304, >+ /* VANDPSYrm */ >+ }, >+ { /* 3033 */ >+ 305, >+ /* VANDPSYrr */ >+ }, >+ { /* 3034 */ >+ 312, >+ /* VANDPSrm */ >+ }, >+ { /* 3035 */ >+ 313, >+ /* VANDPSrr */ >+ }, >+ { /* 3036 */ >+ 0, >+ /* */ >+ }, >+ { /* 3037 */ >+ 309, >+ /* VBLENDMPDZrm */ >+ }, >+ { /* 3038 */ >+ 311, >+ /* VBLENDMPDZrr */ >+ }, >+ { /* 3039 */ >+ 316, >+ /* VBLENDMPSZrm */ >+ }, >+ { /* 3040 */ >+ 317, >+ /* VBLENDMPSZrr */ >+ }, >+ { /* 3041 */ >+ 332, >+ /* VBLENDPDYrmi */ >+ }, >+ { /* 3042 */ >+ 333, >+ /* VBLENDPDYrri */ >+ }, >+ { /* 3043 */ >+ 334, >+ /* VBLENDPDrmi */ >+ }, >+ { /* 3044 */ >+ 335, >+ /* VBLENDPDrri */ >+ }, >+ { /* 3045 */ >+ 332, >+ /* VBLENDPSYrmi */ >+ }, >+ { /* 3046 */ >+ 333, >+ /* VBLENDPSYrri */ >+ }, >+ { /* 3047 */ >+ 334, >+ /* VBLENDPSrmi */ >+ }, >+ { /* 3048 */ >+ 335, >+ /* VBLENDPSrri */ >+ }, >+ { /* 3049 */ >+ 336, >+ /* VBLENDVPDYrm */ >+ }, >+ { /* 3050 */ >+ 337, >+ /* VBLENDVPDYrr */ >+ }, >+ { /* 3051 */ >+ 338, >+ /* VBLENDVPDrm */ >+ }, >+ { /* 3052 */ >+ 339, >+ /* VBLENDVPDrr */ >+ }, >+ { /* 3053 */ >+ 336, >+ /* VBLENDVPSYrm */ >+ }, >+ { /* 3054 */ >+ 337, >+ /* VBLENDVPSYrr */ >+ }, >+ { /* 3055 */ >+ 338, >+ /* VBLENDVPSrm */ >+ }, >+ { /* 3056 */ >+ 339, >+ /* VBLENDVPSrr */ >+ }, >+ { /* 3057 */ >+ 340, >+ /* VBROADCASTF128 */ >+ }, >+ { /* 3058 */ >+ 340, >+ /* VBROADCASTI128 */ >+ }, >+ { /* 3059 */ >+ 341, >+ /* VBROADCASTI32X4krm */ >+ }, >+ { /* 3060 */ >+ 342, >+ /* VBROADCASTI32X4rm */ >+ }, >+ { /* 3061 */ >+ 343, >+ /* VBROADCASTI64X4krm */ >+ }, >+ { /* 3062 */ >+ 344, >+ /* VBROADCASTI64X4rm */ >+ }, >+ { /* 3063 */ >+ 345, >+ /* VBROADCASTSDYrm */ >+ }, >+ { /* 3064 */ >+ 346, >+ /* VBROADCASTSDYrr */ >+ }, >+ { /* 3065 */ >+ 347, >+ /* VBROADCASTSDZrm */ >+ }, >+ { /* 3066 */ >+ 348, >+ /* VBROADCASTSDZrr */ >+ }, >+ { /* 3067 */ >+ 349, >+ /* VBROADCASTSSYrm */ >+ }, >+ { /* 3068 */ >+ 346, >+ /* VBROADCASTSSYrr */ >+ }, >+ { /* 3069 */ >+ 350, >+ /* VBROADCASTSSZrm */ >+ }, >+ { /* 3070 */ >+ 351, >+ /* VBROADCASTSSZrr */ >+ }, >+ { /* 3071 */ >+ 352, >+ /* VBROADCASTSSrm */ >+ }, >+ { /* 3072 */ >+ 45, >+ /* VBROADCASTSSrr */ >+ }, >+ { /* 3073 */ >+ 353, >+ /* VCMPPDYrmi */ >+ }, >+ { /* 3074 */ >+ 0, >+ /* */ >+ }, >+ { /* 3075 */ >+ 354, >+ /* VCMPPDYrri */ >+ }, >+ { /* 3076 */ >+ 0, >+ /* */ >+ }, >+ { /* 3077 */ >+ 355, >+ /* VCMPPDZrmi */ >+ }, >+ { /* 3078 */ >+ 0, >+ /* */ >+ }, >+ { /* 3079 */ >+ 356, >+ /* VCMPPDZrri */ >+ }, >+ { /* 3080 */ >+ 0, >+ /* */ >+ }, >+ { /* 3081 */ >+ 357, >+ /* VCMPPDZrrib */ >+ }, >+ { /* 3082 */ >+ 358, >+ /* VCMPPDrmi */ >+ }, >+ { /* 3083 */ >+ 0, >+ /* */ >+ }, >+ { /* 3084 */ >+ 359, >+ /* VCMPPDrri */ >+ }, >+ { /* 3085 */ >+ 0, >+ /* */ >+ }, >+ { /* 3086 */ >+ 353, >+ /* VCMPPSYrmi */ >+ }, >+ { /* 3087 */ >+ 0, >+ /* */ >+ }, >+ { /* 3088 */ >+ 354, >+ /* VCMPPSYrri */ >+ }, >+ { /* 3089 */ >+ 0, >+ /* */ >+ }, >+ { /* 3090 */ >+ 360, >+ /* VCMPPSZrmi */ >+ }, >+ { /* 3091 */ >+ 0, >+ /* */ >+ }, >+ { /* 3092 */ >+ 361, >+ /* VCMPPSZrri */ >+ }, >+ { /* 3093 */ >+ 0, >+ /* */ >+ }, >+ { /* 3094 */ >+ 362, >+ /* VCMPPSZrrib */ >+ }, >+ { /* 3095 */ >+ 358, >+ /* VCMPPSrmi */ >+ }, >+ { /* 3096 */ >+ 0, >+ /* */ >+ }, >+ { /* 3097 */ >+ 359, >+ /* VCMPPSrri */ >+ }, >+ { /* 3098 */ >+ 0, >+ /* */ >+ }, >+ { /* 3099 */ >+ 363, >+ /* VCMPSDZrm */ >+ }, >+ { /* 3100 */ >+ 0, >+ /* */ >+ }, >+ { /* 3101 */ >+ 364, >+ /* VCMPSDZrr */ >+ }, >+ { /* 3102 */ >+ 0, >+ /* */ >+ }, >+ { /* 3103 */ >+ 365, >+ /* VCMPSDrm */ >+ }, >+ { /* 3104 */ >+ 0, >+ /* */ >+ }, >+ { /* 3105 */ >+ 366, >+ /* VCMPSDrr */ >+ }, >+ { /* 3106 */ >+ 0, >+ /* */ >+ }, >+ { /* 3107 */ >+ 367, >+ /* VCMPSSZrm */ >+ }, >+ { /* 3108 */ >+ 0, >+ /* */ >+ }, >+ { /* 3109 */ >+ 368, >+ /* VCMPSSZrr */ >+ }, >+ { /* 3110 */ >+ 0, >+ /* */ >+ }, >+ { /* 3111 */ >+ 369, >+ /* VCMPSSrm */ >+ }, >+ { /* 3112 */ >+ 0, >+ /* */ >+ }, >+ { /* 3113 */ >+ 370, >+ /* VCMPSSrr */ >+ }, >+ { /* 3114 */ >+ 0, >+ /* */ >+ }, >+ { /* 3115 */ >+ 371, >+ /* VCOMISDZrm */ >+ }, >+ { /* 3116 */ >+ 372, >+ /* VCOMISDZrr */ >+ }, >+ { /* 3117 */ >+ 44, >+ /* VCOMISDrm */ >+ }, >+ { /* 3118 */ >+ 45, >+ /* VCOMISDrr */ >+ }, >+ { /* 3119 */ >+ 373, >+ /* VCOMISSZrm */ >+ }, >+ { /* 3120 */ >+ 374, >+ /* VCOMISSZrr */ >+ }, >+ { /* 3121 */ >+ 44, >+ /* VCOMISSrm */ >+ }, >+ { /* 3122 */ >+ 45, >+ /* VCOMISSrr */ >+ }, >+ { /* 3123 */ >+ 340, >+ /* VCVTDQ2PDYrm */ >+ }, >+ { /* 3124 */ >+ 346, >+ /* VCVTDQ2PDYrr */ >+ }, >+ { /* 3125 */ >+ 344, >+ /* VCVTDQ2PDZrm */ >+ }, >+ { /* 3126 */ >+ 375, >+ /* VCVTDQ2PDZrr */ >+ }, >+ { /* 3127 */ >+ 105, >+ /* VCVTDQ2PDrm */ >+ }, >+ { /* 3128 */ >+ 45, >+ /* VCVTDQ2PDrr */ >+ }, >+ { /* 3129 */ >+ 376, >+ /* VCVTDQ2PSYrm */ >+ }, >+ { /* 3130 */ >+ 377, >+ /* VCVTDQ2PSYrr */ >+ }, >+ { /* 3131 */ >+ 378, >+ /* VCVTDQ2PSZrm */ >+ }, >+ { /* 3132 */ >+ 379, >+ /* VCVTDQ2PSZrr */ >+ }, >+ { /* 3133 */ >+ 380, >+ /* VCVTDQ2PSZrrb */ >+ }, >+ { /* 3134 */ >+ 44, >+ /* VCVTDQ2PSrm */ >+ }, >+ { /* 3135 */ >+ 45, >+ /* VCVTDQ2PSrr */ >+ }, >+ { /* 3136 */ >+ 44, >+ /* VCVTPD2DQXrm */ >+ }, >+ { /* 3137 */ >+ 381, >+ /* VCVTPD2DQYrm */ >+ }, >+ { /* 3138 */ >+ 382, >+ /* VCVTPD2DQYrr */ >+ }, >+ { /* 3139 */ >+ 383, >+ /* VCVTPD2DQZrm */ >+ }, >+ { /* 3140 */ >+ 384, >+ /* VCVTPD2DQZrr */ >+ }, >+ { /* 3141 */ >+ 385, >+ /* VCVTPD2DQZrrb */ >+ }, >+ { /* 3142 */ >+ 45, >+ /* VCVTPD2DQrr */ >+ }, >+ { /* 3143 */ >+ 44, >+ /* VCVTPD2PSXrm */ >+ }, >+ { /* 3144 */ >+ 381, >+ /* VCVTPD2PSYrm */ >+ }, >+ { /* 3145 */ >+ 382, >+ /* VCVTPD2PSYrr */ >+ }, >+ { /* 3146 */ >+ 383, >+ /* VCVTPD2PSZrm */ >+ }, >+ { /* 3147 */ >+ 384, >+ /* VCVTPD2PSZrr */ >+ }, >+ { /* 3148 */ >+ 385, >+ /* VCVTPD2PSZrrb */ >+ }, >+ { /* 3149 */ >+ 45, >+ /* VCVTPD2PSrr */ >+ }, >+ { /* 3150 */ >+ 383, >+ /* VCVTPD2UDQZrm */ >+ }, >+ { /* 3151 */ >+ 384, >+ /* VCVTPD2UDQZrr */ >+ }, >+ { /* 3152 */ >+ 385, >+ /* VCVTPD2UDQZrrb */ >+ }, >+ { /* 3153 */ >+ 340, >+ /* VCVTPH2PSYrm */ >+ }, >+ { /* 3154 */ >+ 346, >+ /* VCVTPH2PSYrr */ >+ }, >+ { /* 3155 */ >+ 344, >+ /* VCVTPH2PSZrm */ >+ }, >+ { /* 3156 */ >+ 375, >+ /* VCVTPH2PSZrr */ >+ }, >+ { /* 3157 */ >+ 106, >+ /* VCVTPH2PSrm */ >+ }, >+ { /* 3158 */ >+ 45, >+ /* VCVTPH2PSrr */ >+ }, >+ { /* 3159 */ >+ 376, >+ /* VCVTPS2DQYrm */ >+ }, >+ { /* 3160 */ >+ 377, >+ /* VCVTPS2DQYrr */ >+ }, >+ { /* 3161 */ >+ 378, >+ /* VCVTPS2DQZrm */ >+ }, >+ { /* 3162 */ >+ 379, >+ /* VCVTPS2DQZrr */ >+ }, >+ { /* 3163 */ >+ 380, >+ /* VCVTPS2DQZrrb */ >+ }, >+ { /* 3164 */ >+ 44, >+ /* VCVTPS2DQrm */ >+ }, >+ { /* 3165 */ >+ 45, >+ /* VCVTPS2DQrr */ >+ }, >+ { /* 3166 */ >+ 340, >+ /* VCVTPS2PDYrm */ >+ }, >+ { /* 3167 */ >+ 346, >+ /* VCVTPS2PDYrr */ >+ }, >+ { /* 3168 */ >+ 344, >+ /* VCVTPS2PDZrm */ >+ }, >+ { /* 3169 */ >+ 375, >+ /* VCVTPS2PDZrr */ >+ }, >+ { /* 3170 */ >+ 106, >+ /* VCVTPS2PDrm */ >+ }, >+ { /* 3171 */ >+ 45, >+ /* VCVTPS2PDrr */ >+ }, >+ { /* 3172 */ >+ 386, >+ /* VCVTPS2PHYmr */ >+ }, >+ { /* 3173 */ >+ 387, >+ /* VCVTPS2PHYrr */ >+ }, >+ { /* 3174 */ >+ 388, >+ /* VCVTPS2PHZmr */ >+ }, >+ { /* 3175 */ >+ 389, >+ /* VCVTPS2PHZrr */ >+ }, >+ { /* 3176 */ >+ 390, >+ /* VCVTPS2PHmr */ >+ }, >+ { /* 3177 */ >+ 391, >+ /* VCVTPS2PHrr */ >+ }, >+ { /* 3178 */ >+ 378, >+ /* VCVTPS2UDQZrm */ >+ }, >+ { /* 3179 */ >+ 379, >+ /* VCVTPS2UDQZrr */ >+ }, >+ { /* 3180 */ >+ 380, >+ /* VCVTPS2UDQZrrb */ >+ }, >+ { /* 3181 */ >+ 392, >+ /* VCVTSD2SI64Zrm */ >+ }, >+ { /* 3182 */ >+ 393, >+ /* VCVTSD2SI64Zrr */ >+ }, >+ { /* 3183 */ >+ 107, >+ /* VCVTSD2SI64rm */ >+ }, >+ { /* 3184 */ >+ 108, >+ /* VCVTSD2SI64rr */ >+ }, >+ { /* 3185 */ >+ 394, >+ /* VCVTSD2SIZrm */ >+ }, >+ { /* 3186 */ >+ 395, >+ /* VCVTSD2SIZrr */ >+ }, >+ { /* 3187 */ >+ 109, >+ /* VCVTSD2SIrm */ >+ }, >+ { /* 3188 */ >+ 110, >+ /* VCVTSD2SIrr */ >+ }, >+ { /* 3189 */ >+ 396, >+ /* VCVTSD2SSZrm */ >+ }, >+ { /* 3190 */ >+ 397, >+ /* VCVTSD2SSZrr */ >+ }, >+ { /* 3191 */ >+ 398, >+ /* VCVTSD2SSrm */ >+ }, >+ { /* 3192 */ >+ 399, >+ /* VCVTSD2SSrr */ >+ }, >+ { /* 3193 */ >+ 392, >+ /* VCVTSD2USI64Zrm */ >+ }, >+ { /* 3194 */ >+ 393, >+ /* VCVTSD2USI64Zrr */ >+ }, >+ { /* 3195 */ >+ 394, >+ /* VCVTSD2USIZrm */ >+ }, >+ { /* 3196 */ >+ 395, >+ /* VCVTSD2USIZrr */ >+ }, >+ { /* 3197 */ >+ 400, >+ /* VCVTSI2SD64rm */ >+ }, >+ { /* 3198 */ >+ 401, >+ /* VCVTSI2SD64rr */ >+ }, >+ { /* 3199 */ >+ 402, >+ /* VCVTSI2SDZrm */ >+ }, >+ { /* 3200 */ >+ 403, >+ /* VCVTSI2SDZrr */ >+ }, >+ { /* 3201 */ >+ 400, >+ /* VCVTSI2SDrm */ >+ }, >+ { /* 3202 */ >+ 404, >+ /* VCVTSI2SDrr */ >+ }, >+ { /* 3203 */ >+ 405, >+ /* VCVTSI2SS64rm */ >+ }, >+ { /* 3204 */ >+ 406, >+ /* VCVTSI2SS64rr */ >+ }, >+ { /* 3205 */ >+ 407, >+ /* VCVTSI2SSZrm */ >+ }, >+ { /* 3206 */ >+ 408, >+ /* VCVTSI2SSZrr */ >+ }, >+ { /* 3207 */ >+ 405, >+ /* VCVTSI2SSrm */ >+ }, >+ { /* 3208 */ >+ 409, >+ /* VCVTSI2SSrr */ >+ }, >+ { /* 3209 */ >+ 410, >+ /* VCVTSI642SDZrm */ >+ }, >+ { /* 3210 */ >+ 411, >+ /* VCVTSI642SDZrr */ >+ }, >+ { /* 3211 */ >+ 412, >+ /* VCVTSI642SSZrm */ >+ }, >+ { /* 3212 */ >+ 413, >+ /* VCVTSI642SSZrr */ >+ }, >+ { /* 3213 */ >+ 414, >+ /* VCVTSS2SDZrm */ >+ }, >+ { /* 3214 */ >+ 415, >+ /* VCVTSS2SDZrr */ >+ }, >+ { /* 3215 */ >+ 416, >+ /* VCVTSS2SDrm */ >+ }, >+ { /* 3216 */ >+ 417, >+ /* VCVTSS2SDrr */ >+ }, >+ { /* 3217 */ >+ 418, >+ /* VCVTSS2SI64Zrm */ >+ }, >+ { /* 3218 */ >+ 419, >+ /* VCVTSS2SI64Zrr */ >+ }, >+ { /* 3219 */ >+ 121, >+ /* VCVTSS2SI64rm */ >+ }, >+ { /* 3220 */ >+ 108, >+ /* VCVTSS2SI64rr */ >+ }, >+ { /* 3221 */ >+ 420, >+ /* VCVTSS2SIZrm */ >+ }, >+ { /* 3222 */ >+ 421, >+ /* VCVTSS2SIZrr */ >+ }, >+ { /* 3223 */ >+ 122, >+ /* VCVTSS2SIrm */ >+ }, >+ { /* 3224 */ >+ 110, >+ /* VCVTSS2SIrr */ >+ }, >+ { /* 3225 */ >+ 418, >+ /* VCVTSS2USI64Zrm */ >+ }, >+ { /* 3226 */ >+ 419, >+ /* VCVTSS2USI64Zrr */ >+ }, >+ { /* 3227 */ >+ 420, >+ /* VCVTSS2USIZrm */ >+ }, >+ { /* 3228 */ >+ 421, >+ /* VCVTSS2USIZrr */ >+ }, >+ { /* 3229 */ >+ 44, >+ /* VCVTTPD2DQXrm */ >+ }, >+ { /* 3230 */ >+ 381, >+ /* VCVTTPD2DQYrm */ >+ }, >+ { /* 3231 */ >+ 382, >+ /* VCVTTPD2DQYrr */ >+ }, >+ { /* 3232 */ >+ 383, >+ /* VCVTTPD2DQZrm */ >+ }, >+ { /* 3233 */ >+ 384, >+ /* VCVTTPD2DQZrr */ >+ }, >+ { /* 3234 */ >+ 45, >+ /* VCVTTPD2DQrr */ >+ }, >+ { /* 3235 */ >+ 383, >+ /* VCVTTPD2UDQZrm */ >+ }, >+ { /* 3236 */ >+ 384, >+ /* VCVTTPD2UDQZrr */ >+ }, >+ { /* 3237 */ >+ 376, >+ /* VCVTTPS2DQYrm */ >+ }, >+ { /* 3238 */ >+ 377, >+ /* VCVTTPS2DQYrr */ >+ }, >+ { /* 3239 */ >+ 378, >+ /* VCVTTPS2DQZrm */ >+ }, >+ { /* 3240 */ >+ 379, >+ /* VCVTTPS2DQZrr */ >+ }, >+ { /* 3241 */ >+ 44, >+ /* VCVTTPS2DQrm */ >+ }, >+ { /* 3242 */ >+ 45, >+ /* VCVTTPS2DQrr */ >+ }, >+ { /* 3243 */ >+ 378, >+ /* VCVTTPS2UDQZrm */ >+ }, >+ { /* 3244 */ >+ 379, >+ /* VCVTTPS2UDQZrr */ >+ }, >+ { /* 3245 */ >+ 392, >+ /* VCVTTSD2SI64Zrm */ >+ }, >+ { /* 3246 */ >+ 422, >+ /* VCVTTSD2SI64Zrr */ >+ }, >+ { /* 3247 */ >+ 107, >+ /* VCVTTSD2SI64rm */ >+ }, >+ { /* 3248 */ >+ 123, >+ /* VCVTTSD2SI64rr */ >+ }, >+ { /* 3249 */ >+ 394, >+ /* VCVTTSD2SIZrm */ >+ }, >+ { /* 3250 */ >+ 423, >+ /* VCVTTSD2SIZrr */ >+ }, >+ { /* 3251 */ >+ 109, >+ /* VCVTTSD2SIrm */ >+ }, >+ { /* 3252 */ >+ 124, >+ /* VCVTTSD2SIrr */ >+ }, >+ { /* 3253 */ >+ 392, >+ /* VCVTTSD2USI64Zrm */ >+ }, >+ { /* 3254 */ >+ 422, >+ /* VCVTTSD2USI64Zrr */ >+ }, >+ { /* 3255 */ >+ 394, >+ /* VCVTTSD2USIZrm */ >+ }, >+ { /* 3256 */ >+ 423, >+ /* VCVTTSD2USIZrr */ >+ }, >+ { /* 3257 */ >+ 418, >+ /* VCVTTSS2SI64Zrm */ >+ }, >+ { /* 3258 */ >+ 424, >+ /* VCVTTSS2SI64Zrr */ >+ }, >+ { /* 3259 */ >+ 121, >+ /* VCVTTSS2SI64rm */ >+ }, >+ { /* 3260 */ >+ 125, >+ /* VCVTTSS2SI64rr */ >+ }, >+ { /* 3261 */ >+ 420, >+ /* VCVTTSS2SIZrm */ >+ }, >+ { /* 3262 */ >+ 425, >+ /* VCVTTSS2SIZrr */ >+ }, >+ { /* 3263 */ >+ 122, >+ /* VCVTTSS2SIrm */ >+ }, >+ { /* 3264 */ >+ 126, >+ /* VCVTTSS2SIrr */ >+ }, >+ { /* 3265 */ >+ 418, >+ /* VCVTTSS2USI64Zrm */ >+ }, >+ { /* 3266 */ >+ 424, >+ /* VCVTTSS2USI64Zrr */ >+ }, >+ { /* 3267 */ >+ 420, >+ /* VCVTTSS2USIZrm */ >+ }, >+ { /* 3268 */ >+ 425, >+ /* VCVTTSS2USIZrr */ >+ }, >+ { /* 3269 */ >+ 344, >+ /* VCVTUDQ2PDZrm */ >+ }, >+ { /* 3270 */ >+ 375, >+ /* VCVTUDQ2PDZrr */ >+ }, >+ { /* 3271 */ >+ 378, >+ /* VCVTUDQ2PSZrm */ >+ }, >+ { /* 3272 */ >+ 379, >+ /* VCVTUDQ2PSZrr */ >+ }, >+ { /* 3273 */ >+ 380, >+ /* VCVTUDQ2PSZrrb */ >+ }, >+ { /* 3274 */ >+ 402, >+ /* VCVTUSI2SDZrm */ >+ }, >+ { /* 3275 */ >+ 403, >+ /* VCVTUSI2SDZrr */ >+ }, >+ { /* 3276 */ >+ 407, >+ /* VCVTUSI2SSZrm */ >+ }, >+ { /* 3277 */ >+ 408, >+ /* VCVTUSI2SSZrr */ >+ }, >+ { /* 3278 */ >+ 410, >+ /* VCVTUSI642SDZrm */ >+ }, >+ { /* 3279 */ >+ 411, >+ /* VCVTUSI642SDZrr */ >+ }, >+ { /* 3280 */ >+ 412, >+ /* VCVTUSI642SSZrm */ >+ }, >+ { /* 3281 */ >+ 413, >+ /* VCVTUSI642SSZrr */ >+ }, >+ { /* 3282 */ >+ 304, >+ /* VDIVPDYrm */ >+ }, >+ { /* 3283 */ >+ 305, >+ /* VDIVPDYrr */ >+ }, >+ { /* 3284 */ >+ 306, >+ /* VDIVPDZrm */ >+ }, >+ { /* 3285 */ >+ 307, >+ /* VDIVPDZrmb */ >+ }, >+ { /* 3286 */ >+ 308, >+ /* VDIVPDZrmbk */ >+ }, >+ { /* 3287 */ >+ 308, >+ /* VDIVPDZrmbkz */ >+ }, >+ { /* 3288 */ >+ 309, >+ /* VDIVPDZrmk */ >+ }, >+ { /* 3289 */ >+ 309, >+ /* VDIVPDZrmkz */ >+ }, >+ { /* 3290 */ >+ 310, >+ /* VDIVPDZrr */ >+ }, >+ { /* 3291 */ >+ 311, >+ /* VDIVPDZrrk */ >+ }, >+ { /* 3292 */ >+ 311, >+ /* VDIVPDZrrkz */ >+ }, >+ { /* 3293 */ >+ 312, >+ /* VDIVPDrm */ >+ }, >+ { /* 3294 */ >+ 313, >+ /* VDIVPDrr */ >+ }, >+ { /* 3295 */ >+ 304, >+ /* VDIVPSYrm */ >+ }, >+ { /* 3296 */ >+ 305, >+ /* VDIVPSYrr */ >+ }, >+ { /* 3297 */ >+ 306, >+ /* VDIVPSZrm */ >+ }, >+ { /* 3298 */ >+ 314, >+ /* VDIVPSZrmb */ >+ }, >+ { /* 3299 */ >+ 315, >+ /* VDIVPSZrmbk */ >+ }, >+ { /* 3300 */ >+ 315, >+ /* VDIVPSZrmbkz */ >+ }, >+ { /* 3301 */ >+ 316, >+ /* VDIVPSZrmk */ >+ }, >+ { /* 3302 */ >+ 316, >+ /* VDIVPSZrmkz */ >+ }, >+ { /* 3303 */ >+ 310, >+ /* VDIVPSZrr */ >+ }, >+ { /* 3304 */ >+ 317, >+ /* VDIVPSZrrk */ >+ }, >+ { /* 3305 */ >+ 317, >+ /* VDIVPSZrrkz */ >+ }, >+ { /* 3306 */ >+ 312, >+ /* VDIVPSrm */ >+ }, >+ { /* 3307 */ >+ 313, >+ /* VDIVPSrr */ >+ }, >+ { /* 3308 */ >+ 318, >+ /* VDIVSDZrm */ >+ }, >+ { /* 3309 */ >+ 319, >+ /* VDIVSDZrr */ >+ }, >+ { /* 3310 */ >+ 320, >+ /* VDIVSDrm */ >+ }, >+ { /* 3311 */ >+ 0, >+ /* */ >+ }, >+ { /* 3312 */ >+ 321, >+ /* VDIVSDrr */ >+ }, >+ { /* 3313 */ >+ 0, >+ /* */ >+ }, >+ { /* 3314 */ >+ 322, >+ /* VDIVSSZrm */ >+ }, >+ { /* 3315 */ >+ 323, >+ /* VDIVSSZrr */ >+ }, >+ { /* 3316 */ >+ 324, >+ /* VDIVSSrm */ >+ }, >+ { /* 3317 */ >+ 0, >+ /* */ >+ }, >+ { /* 3318 */ >+ 325, >+ /* VDIVSSrr */ >+ }, >+ { /* 3319 */ >+ 0, >+ /* */ >+ }, >+ { /* 3320 */ >+ 334, >+ /* VDPPDrmi */ >+ }, >+ { /* 3321 */ >+ 335, >+ /* VDPPDrri */ >+ }, >+ { /* 3322 */ >+ 332, >+ /* VDPPSYrmi */ >+ }, >+ { /* 3323 */ >+ 333, >+ /* VDPPSYrri */ >+ }, >+ { /* 3324 */ >+ 334, >+ /* VDPPSrmi */ >+ }, >+ { /* 3325 */ >+ 335, >+ /* VDPPSrri */ >+ }, >+ { /* 3326 */ >+ 38, >+ /* VERRm */ >+ }, >+ { /* 3327 */ >+ 190, >+ /* VERRr */ >+ }, >+ { /* 3328 */ >+ 38, >+ /* VERWm */ >+ }, >+ { /* 3329 */ >+ 190, >+ /* VERWr */ >+ }, >+ { /* 3330 */ >+ 426, >+ /* VEXTRACTF128mr */ >+ }, >+ { /* 3331 */ >+ 427, >+ /* VEXTRACTF128rr */ >+ }, >+ { /* 3332 */ >+ 428, >+ /* VEXTRACTF32x4mr */ >+ }, >+ { /* 3333 */ >+ 429, >+ /* VEXTRACTF32x4rr */ >+ }, >+ { /* 3334 */ >+ 430, >+ /* VEXTRACTF64x4mr */ >+ }, >+ { /* 3335 */ >+ 431, >+ /* VEXTRACTF64x4rr */ >+ }, >+ { /* 3336 */ >+ 426, >+ /* VEXTRACTI128mr */ >+ }, >+ { /* 3337 */ >+ 427, >+ /* VEXTRACTI128rr */ >+ }, >+ { /* 3338 */ >+ 428, >+ /* VEXTRACTI32x4mr */ >+ }, >+ { /* 3339 */ >+ 429, >+ /* VEXTRACTI32x4rr */ >+ }, >+ { /* 3340 */ >+ 430, >+ /* VEXTRACTI64x4mr */ >+ }, >+ { /* 3341 */ >+ 431, >+ /* VEXTRACTI64x4rr */ >+ }, >+ { /* 3342 */ >+ 132, >+ /* VEXTRACTPSmr */ >+ }, >+ { /* 3343 */ >+ 133, >+ /* VEXTRACTPSrr */ >+ }, >+ { /* 3344 */ >+ 432, >+ /* VEXTRACTPSzmr */ >+ }, >+ { /* 3345 */ >+ 433, >+ /* VEXTRACTPSzrr */ >+ }, >+ { /* 3346 */ >+ 434, >+ /* VFMADD132PDZm */ >+ }, >+ { /* 3347 */ >+ 435, >+ /* VFMADD132PDZmb */ >+ }, >+ { /* 3348 */ >+ 434, >+ /* VFMADD132PSZm */ >+ }, >+ { /* 3349 */ >+ 436, >+ /* VFMADD132PSZmb */ >+ }, >+ { /* 3350 */ >+ 434, >+ /* VFMADD213PDZm */ >+ }, >+ { /* 3351 */ >+ 435, >+ /* VFMADD213PDZmb */ >+ }, >+ { /* 3352 */ >+ 437, >+ /* VFMADD213PDZr */ >+ }, >+ { /* 3353 */ >+ 438, >+ /* VFMADD213PDZrk */ >+ }, >+ { /* 3354 */ >+ 438, >+ /* VFMADD213PDZrkz */ >+ }, >+ { /* 3355 */ >+ 434, >+ /* VFMADD213PSZm */ >+ }, >+ { /* 3356 */ >+ 436, >+ /* VFMADD213PSZmb */ >+ }, >+ { /* 3357 */ >+ 437, >+ /* VFMADD213PSZr */ >+ }, >+ { /* 3358 */ >+ 439, >+ /* VFMADD213PSZrk */ >+ }, >+ { /* 3359 */ >+ 439, >+ /* VFMADD213PSZrkz */ >+ }, >+ { /* 3360 */ >+ 338, >+ /* VFMADDPD4mr */ >+ }, >+ { /* 3361 */ >+ 336, >+ /* VFMADDPD4mrY */ >+ }, >+ { /* 3362 */ >+ 440, >+ /* VFMADDPD4rm */ >+ }, >+ { /* 3363 */ >+ 441, >+ /* VFMADDPD4rmY */ >+ }, >+ { /* 3364 */ >+ 442, >+ /* VFMADDPD4rr */ >+ }, >+ { /* 3365 */ >+ 443, >+ /* VFMADDPD4rrY */ >+ }, >+ { /* 3366 */ >+ 337, >+ /* VFMADDPD4rrY_REV */ >+ }, >+ { /* 3367 */ >+ 339, >+ /* VFMADDPD4rr_REV */ >+ }, >+ { /* 3368 */ >+ 444, >+ /* VFMADDPDr132m */ >+ }, >+ { /* 3369 */ >+ 445, >+ /* VFMADDPDr132mY */ >+ }, >+ { /* 3370 */ >+ 446, >+ /* VFMADDPDr132r */ >+ }, >+ { /* 3371 */ >+ 447, >+ /* VFMADDPDr132rY */ >+ }, >+ { /* 3372 */ >+ 444, >+ /* VFMADDPDr213m */ >+ }, >+ { /* 3373 */ >+ 445, >+ /* VFMADDPDr213mY */ >+ }, >+ { /* 3374 */ >+ 446, >+ /* VFMADDPDr213r */ >+ }, >+ { /* 3375 */ >+ 447, >+ /* VFMADDPDr213rY */ >+ }, >+ { /* 3376 */ >+ 444, >+ /* VFMADDPDr231m */ >+ }, >+ { /* 3377 */ >+ 445, >+ /* VFMADDPDr231mY */ >+ }, >+ { /* 3378 */ >+ 446, >+ /* VFMADDPDr231r */ >+ }, >+ { /* 3379 */ >+ 447, >+ /* VFMADDPDr231rY */ >+ }, >+ { /* 3380 */ >+ 338, >+ /* VFMADDPS4mr */ >+ }, >+ { /* 3381 */ >+ 336, >+ /* VFMADDPS4mrY */ >+ }, >+ { /* 3382 */ >+ 440, >+ /* VFMADDPS4rm */ >+ }, >+ { /* 3383 */ >+ 441, >+ /* VFMADDPS4rmY */ >+ }, >+ { /* 3384 */ >+ 442, >+ /* VFMADDPS4rr */ >+ }, >+ { /* 3385 */ >+ 443, >+ /* VFMADDPS4rrY */ >+ }, >+ { /* 3386 */ >+ 337, >+ /* VFMADDPS4rrY_REV */ >+ }, >+ { /* 3387 */ >+ 339, >+ /* VFMADDPS4rr_REV */ >+ }, >+ { /* 3388 */ >+ 444, >+ /* VFMADDPSr132m */ >+ }, >+ { /* 3389 */ >+ 445, >+ /* VFMADDPSr132mY */ >+ }, >+ { /* 3390 */ >+ 446, >+ /* VFMADDPSr132r */ >+ }, >+ { /* 3391 */ >+ 447, >+ /* VFMADDPSr132rY */ >+ }, >+ { /* 3392 */ >+ 444, >+ /* VFMADDPSr213m */ >+ }, >+ { /* 3393 */ >+ 445, >+ /* VFMADDPSr213mY */ >+ }, >+ { /* 3394 */ >+ 446, >+ /* VFMADDPSr213r */ >+ }, >+ { /* 3395 */ >+ 447, >+ /* VFMADDPSr213rY */ >+ }, >+ { /* 3396 */ >+ 444, >+ /* VFMADDPSr231m */ >+ }, >+ { /* 3397 */ >+ 445, >+ /* VFMADDPSr231mY */ >+ }, >+ { /* 3398 */ >+ 446, >+ /* VFMADDPSr231r */ >+ }, >+ { /* 3399 */ >+ 447, >+ /* VFMADDPSr231rY */ >+ }, >+ { /* 3400 */ >+ 448, >+ /* VFMADDSD4mr */ >+ }, >+ { /* 3401 */ >+ 0, >+ /* */ >+ }, >+ { /* 3402 */ >+ 449, >+ /* VFMADDSD4rm */ >+ }, >+ { /* 3403 */ >+ 0, >+ /* */ >+ }, >+ { /* 3404 */ >+ 450, >+ /* VFMADDSD4rr */ >+ }, >+ { /* 3405 */ >+ 0, >+ /* */ >+ }, >+ { /* 3406 */ >+ 451, >+ /* VFMADDSD4rr_REV */ >+ }, >+ { /* 3407 */ >+ 452, >+ /* VFMADDSDZm */ >+ }, >+ { /* 3408 */ >+ 453, >+ /* VFMADDSDZr */ >+ }, >+ { /* 3409 */ >+ 454, >+ /* VFMADDSDr132m */ >+ }, >+ { /* 3410 */ >+ 455, >+ /* VFMADDSDr132r */ >+ }, >+ { /* 3411 */ >+ 454, >+ /* VFMADDSDr213m */ >+ }, >+ { /* 3412 */ >+ 455, >+ /* VFMADDSDr213r */ >+ }, >+ { /* 3413 */ >+ 454, >+ /* VFMADDSDr231m */ >+ }, >+ { /* 3414 */ >+ 455, >+ /* VFMADDSDr231r */ >+ }, >+ { /* 3415 */ >+ 456, >+ /* VFMADDSS4mr */ >+ }, >+ { /* 3416 */ >+ 0, >+ /* */ >+ }, >+ { /* 3417 */ >+ 457, >+ /* VFMADDSS4rm */ >+ }, >+ { /* 3418 */ >+ 0, >+ /* */ >+ }, >+ { /* 3419 */ >+ 458, >+ /* VFMADDSS4rr */ >+ }, >+ { /* 3420 */ >+ 0, >+ /* */ >+ }, >+ { /* 3421 */ >+ 459, >+ /* VFMADDSS4rr_REV */ >+ }, >+ { /* 3422 */ >+ 460, >+ /* VFMADDSSZm */ >+ }, >+ { /* 3423 */ >+ 461, >+ /* VFMADDSSZr */ >+ }, >+ { /* 3424 */ >+ 462, >+ /* VFMADDSSr132m */ >+ }, >+ { /* 3425 */ >+ 463, >+ /* VFMADDSSr132r */ >+ }, >+ { /* 3426 */ >+ 462, >+ /* VFMADDSSr213m */ >+ }, >+ { /* 3427 */ >+ 463, >+ /* VFMADDSSr213r */ >+ }, >+ { /* 3428 */ >+ 462, >+ /* VFMADDSSr231m */ >+ }, >+ { /* 3429 */ >+ 463, >+ /* VFMADDSSr231r */ >+ }, >+ { /* 3430 */ >+ 434, >+ /* VFMADDSUB132PDZm */ >+ }, >+ { /* 3431 */ >+ 435, >+ /* VFMADDSUB132PDZmb */ >+ }, >+ { /* 3432 */ >+ 434, >+ /* VFMADDSUB132PSZm */ >+ }, >+ { /* 3433 */ >+ 436, >+ /* VFMADDSUB132PSZmb */ >+ }, >+ { /* 3434 */ >+ 434, >+ /* VFMADDSUB213PDZm */ >+ }, >+ { /* 3435 */ >+ 435, >+ /* VFMADDSUB213PDZmb */ >+ }, >+ { /* 3436 */ >+ 437, >+ /* VFMADDSUB213PDZr */ >+ }, >+ { /* 3437 */ >+ 438, >+ /* VFMADDSUB213PDZrk */ >+ }, >+ { /* 3438 */ >+ 438, >+ /* VFMADDSUB213PDZrkz */ >+ }, >+ { /* 3439 */ >+ 434, >+ /* VFMADDSUB213PSZm */ >+ }, >+ { /* 3440 */ >+ 436, >+ /* VFMADDSUB213PSZmb */ >+ }, >+ { /* 3441 */ >+ 437, >+ /* VFMADDSUB213PSZr */ >+ }, >+ { /* 3442 */ >+ 439, >+ /* VFMADDSUB213PSZrk */ >+ }, >+ { /* 3443 */ >+ 439, >+ /* VFMADDSUB213PSZrkz */ >+ }, >+ { /* 3444 */ >+ 338, >+ /* VFMADDSUBPD4mr */ >+ }, >+ { /* 3445 */ >+ 336, >+ /* VFMADDSUBPD4mrY */ >+ }, >+ { /* 3446 */ >+ 440, >+ /* VFMADDSUBPD4rm */ >+ }, >+ { /* 3447 */ >+ 441, >+ /* VFMADDSUBPD4rmY */ >+ }, >+ { /* 3448 */ >+ 442, >+ /* VFMADDSUBPD4rr */ >+ }, >+ { /* 3449 */ >+ 443, >+ /* VFMADDSUBPD4rrY */ >+ }, >+ { /* 3450 */ >+ 337, >+ /* VFMADDSUBPD4rrY_REV */ >+ }, >+ { /* 3451 */ >+ 339, >+ /* VFMADDSUBPD4rr_REV */ >+ }, >+ { /* 3452 */ >+ 444, >+ /* VFMADDSUBPDr132m */ >+ }, >+ { /* 3453 */ >+ 445, >+ /* VFMADDSUBPDr132mY */ >+ }, >+ { /* 3454 */ >+ 446, >+ /* VFMADDSUBPDr132r */ >+ }, >+ { /* 3455 */ >+ 447, >+ /* VFMADDSUBPDr132rY */ >+ }, >+ { /* 3456 */ >+ 444, >+ /* VFMADDSUBPDr213m */ >+ }, >+ { /* 3457 */ >+ 445, >+ /* VFMADDSUBPDr213mY */ >+ }, >+ { /* 3458 */ >+ 446, >+ /* VFMADDSUBPDr213r */ >+ }, >+ { /* 3459 */ >+ 447, >+ /* VFMADDSUBPDr213rY */ >+ }, >+ { /* 3460 */ >+ 444, >+ /* VFMADDSUBPDr231m */ >+ }, >+ { /* 3461 */ >+ 445, >+ /* VFMADDSUBPDr231mY */ >+ }, >+ { /* 3462 */ >+ 446, >+ /* VFMADDSUBPDr231r */ >+ }, >+ { /* 3463 */ >+ 447, >+ /* VFMADDSUBPDr231rY */ >+ }, >+ { /* 3464 */ >+ 338, >+ /* VFMADDSUBPS4mr */ >+ }, >+ { /* 3465 */ >+ 336, >+ /* VFMADDSUBPS4mrY */ >+ }, >+ { /* 3466 */ >+ 440, >+ /* VFMADDSUBPS4rm */ >+ }, >+ { /* 3467 */ >+ 441, >+ /* VFMADDSUBPS4rmY */ >+ }, >+ { /* 3468 */ >+ 442, >+ /* VFMADDSUBPS4rr */ >+ }, >+ { /* 3469 */ >+ 443, >+ /* VFMADDSUBPS4rrY */ >+ }, >+ { /* 3470 */ >+ 337, >+ /* VFMADDSUBPS4rrY_REV */ >+ }, >+ { /* 3471 */ >+ 339, >+ /* VFMADDSUBPS4rr_REV */ >+ }, >+ { /* 3472 */ >+ 444, >+ /* VFMADDSUBPSr132m */ >+ }, >+ { /* 3473 */ >+ 445, >+ /* VFMADDSUBPSr132mY */ >+ }, >+ { /* 3474 */ >+ 446, >+ /* VFMADDSUBPSr132r */ >+ }, >+ { /* 3475 */ >+ 447, >+ /* VFMADDSUBPSr132rY */ >+ }, >+ { /* 3476 */ >+ 444, >+ /* VFMADDSUBPSr213m */ >+ }, >+ { /* 3477 */ >+ 445, >+ /* VFMADDSUBPSr213mY */ >+ }, >+ { /* 3478 */ >+ 446, >+ /* VFMADDSUBPSr213r */ >+ }, >+ { /* 3479 */ >+ 447, >+ /* VFMADDSUBPSr213rY */ >+ }, >+ { /* 3480 */ >+ 444, >+ /* VFMADDSUBPSr231m */ >+ }, >+ { /* 3481 */ >+ 445, >+ /* VFMADDSUBPSr231mY */ >+ }, >+ { /* 3482 */ >+ 446, >+ /* VFMADDSUBPSr231r */ >+ }, >+ { /* 3483 */ >+ 447, >+ /* VFMADDSUBPSr231rY */ >+ }, >+ { /* 3484 */ >+ 434, >+ /* VFMSUB132PDZm */ >+ }, >+ { /* 3485 */ >+ 435, >+ /* VFMSUB132PDZmb */ >+ }, >+ { /* 3486 */ >+ 434, >+ /* VFMSUB132PSZm */ >+ }, >+ { /* 3487 */ >+ 436, >+ /* VFMSUB132PSZmb */ >+ }, >+ { /* 3488 */ >+ 434, >+ /* VFMSUB213PDZm */ >+ }, >+ { /* 3489 */ >+ 435, >+ /* VFMSUB213PDZmb */ >+ }, >+ { /* 3490 */ >+ 437, >+ /* VFMSUB213PDZr */ >+ }, >+ { /* 3491 */ >+ 438, >+ /* VFMSUB213PDZrk */ >+ }, >+ { /* 3492 */ >+ 438, >+ /* VFMSUB213PDZrkz */ >+ }, >+ { /* 3493 */ >+ 434, >+ /* VFMSUB213PSZm */ >+ }, >+ { /* 3494 */ >+ 436, >+ /* VFMSUB213PSZmb */ >+ }, >+ { /* 3495 */ >+ 437, >+ /* VFMSUB213PSZr */ >+ }, >+ { /* 3496 */ >+ 439, >+ /* VFMSUB213PSZrk */ >+ }, >+ { /* 3497 */ >+ 439, >+ /* VFMSUB213PSZrkz */ >+ }, >+ { /* 3498 */ >+ 434, >+ /* VFMSUBADD132PDZm */ >+ }, >+ { /* 3499 */ >+ 435, >+ /* VFMSUBADD132PDZmb */ >+ }, >+ { /* 3500 */ >+ 434, >+ /* VFMSUBADD132PSZm */ >+ }, >+ { /* 3501 */ >+ 436, >+ /* VFMSUBADD132PSZmb */ >+ }, >+ { /* 3502 */ >+ 434, >+ /* VFMSUBADD213PDZm */ >+ }, >+ { /* 3503 */ >+ 435, >+ /* VFMSUBADD213PDZmb */ >+ }, >+ { /* 3504 */ >+ 437, >+ /* VFMSUBADD213PDZr */ >+ }, >+ { /* 3505 */ >+ 438, >+ /* VFMSUBADD213PDZrk */ >+ }, >+ { /* 3506 */ >+ 438, >+ /* VFMSUBADD213PDZrkz */ >+ }, >+ { /* 3507 */ >+ 434, >+ /* VFMSUBADD213PSZm */ >+ }, >+ { /* 3508 */ >+ 436, >+ /* VFMSUBADD213PSZmb */ >+ }, >+ { /* 3509 */ >+ 437, >+ /* VFMSUBADD213PSZr */ >+ }, >+ { /* 3510 */ >+ 439, >+ /* VFMSUBADD213PSZrk */ >+ }, >+ { /* 3511 */ >+ 439, >+ /* VFMSUBADD213PSZrkz */ >+ }, >+ { /* 3512 */ >+ 338, >+ /* VFMSUBADDPD4mr */ >+ }, >+ { /* 3513 */ >+ 336, >+ /* VFMSUBADDPD4mrY */ >+ }, >+ { /* 3514 */ >+ 440, >+ /* VFMSUBADDPD4rm */ >+ }, >+ { /* 3515 */ >+ 441, >+ /* VFMSUBADDPD4rmY */ >+ }, >+ { /* 3516 */ >+ 442, >+ /* VFMSUBADDPD4rr */ >+ }, >+ { /* 3517 */ >+ 443, >+ /* VFMSUBADDPD4rrY */ >+ }, >+ { /* 3518 */ >+ 337, >+ /* VFMSUBADDPD4rrY_REV */ >+ }, >+ { /* 3519 */ >+ 339, >+ /* VFMSUBADDPD4rr_REV */ >+ }, >+ { /* 3520 */ >+ 444, >+ /* VFMSUBADDPDr132m */ >+ }, >+ { /* 3521 */ >+ 445, >+ /* VFMSUBADDPDr132mY */ >+ }, >+ { /* 3522 */ >+ 446, >+ /* VFMSUBADDPDr132r */ >+ }, >+ { /* 3523 */ >+ 447, >+ /* VFMSUBADDPDr132rY */ >+ }, >+ { /* 3524 */ >+ 444, >+ /* VFMSUBADDPDr213m */ >+ }, >+ { /* 3525 */ >+ 445, >+ /* VFMSUBADDPDr213mY */ >+ }, >+ { /* 3526 */ >+ 446, >+ /* VFMSUBADDPDr213r */ >+ }, >+ { /* 3527 */ >+ 447, >+ /* VFMSUBADDPDr213rY */ >+ }, >+ { /* 3528 */ >+ 444, >+ /* VFMSUBADDPDr231m */ >+ }, >+ { /* 3529 */ >+ 445, >+ /* VFMSUBADDPDr231mY */ >+ }, >+ { /* 3530 */ >+ 446, >+ /* VFMSUBADDPDr231r */ >+ }, >+ { /* 3531 */ >+ 447, >+ /* VFMSUBADDPDr231rY */ >+ }, >+ { /* 3532 */ >+ 338, >+ /* VFMSUBADDPS4mr */ >+ }, >+ { /* 3533 */ >+ 336, >+ /* VFMSUBADDPS4mrY */ >+ }, >+ { /* 3534 */ >+ 440, >+ /* VFMSUBADDPS4rm */ >+ }, >+ { /* 3535 */ >+ 441, >+ /* VFMSUBADDPS4rmY */ >+ }, >+ { /* 3536 */ >+ 442, >+ /* VFMSUBADDPS4rr */ >+ }, >+ { /* 3537 */ >+ 443, >+ /* VFMSUBADDPS4rrY */ >+ }, >+ { /* 3538 */ >+ 337, >+ /* VFMSUBADDPS4rrY_REV */ >+ }, >+ { /* 3539 */ >+ 339, >+ /* VFMSUBADDPS4rr_REV */ >+ }, >+ { /* 3540 */ >+ 444, >+ /* VFMSUBADDPSr132m */ >+ }, >+ { /* 3541 */ >+ 445, >+ /* VFMSUBADDPSr132mY */ >+ }, >+ { /* 3542 */ >+ 446, >+ /* VFMSUBADDPSr132r */ >+ }, >+ { /* 3543 */ >+ 447, >+ /* VFMSUBADDPSr132rY */ >+ }, >+ { /* 3544 */ >+ 444, >+ /* VFMSUBADDPSr213m */ >+ }, >+ { /* 3545 */ >+ 445, >+ /* VFMSUBADDPSr213mY */ >+ }, >+ { /* 3546 */ >+ 446, >+ /* VFMSUBADDPSr213r */ >+ }, >+ { /* 3547 */ >+ 447, >+ /* VFMSUBADDPSr213rY */ >+ }, >+ { /* 3548 */ >+ 444, >+ /* VFMSUBADDPSr231m */ >+ }, >+ { /* 3549 */ >+ 445, >+ /* VFMSUBADDPSr231mY */ >+ }, >+ { /* 3550 */ >+ 446, >+ /* VFMSUBADDPSr231r */ >+ }, >+ { /* 3551 */ >+ 447, >+ /* VFMSUBADDPSr231rY */ >+ }, >+ { /* 3552 */ >+ 338, >+ /* VFMSUBPD4mr */ >+ }, >+ { /* 3553 */ >+ 336, >+ /* VFMSUBPD4mrY */ >+ }, >+ { /* 3554 */ >+ 440, >+ /* VFMSUBPD4rm */ >+ }, >+ { /* 3555 */ >+ 441, >+ /* VFMSUBPD4rmY */ >+ }, >+ { /* 3556 */ >+ 442, >+ /* VFMSUBPD4rr */ >+ }, >+ { /* 3557 */ >+ 443, >+ /* VFMSUBPD4rrY */ >+ }, >+ { /* 3558 */ >+ 337, >+ /* VFMSUBPD4rrY_REV */ >+ }, >+ { /* 3559 */ >+ 339, >+ /* VFMSUBPD4rr_REV */ >+ }, >+ { /* 3560 */ >+ 444, >+ /* VFMSUBPDr132m */ >+ }, >+ { /* 3561 */ >+ 445, >+ /* VFMSUBPDr132mY */ >+ }, >+ { /* 3562 */ >+ 446, >+ /* VFMSUBPDr132r */ >+ }, >+ { /* 3563 */ >+ 447, >+ /* VFMSUBPDr132rY */ >+ }, >+ { /* 3564 */ >+ 444, >+ /* VFMSUBPDr213m */ >+ }, >+ { /* 3565 */ >+ 445, >+ /* VFMSUBPDr213mY */ >+ }, >+ { /* 3566 */ >+ 446, >+ /* VFMSUBPDr213r */ >+ }, >+ { /* 3567 */ >+ 447, >+ /* VFMSUBPDr213rY */ >+ }, >+ { /* 3568 */ >+ 444, >+ /* VFMSUBPDr231m */ >+ }, >+ { /* 3569 */ >+ 445, >+ /* VFMSUBPDr231mY */ >+ }, >+ { /* 3570 */ >+ 446, >+ /* VFMSUBPDr231r */ >+ }, >+ { /* 3571 */ >+ 447, >+ /* VFMSUBPDr231rY */ >+ }, >+ { /* 3572 */ >+ 338, >+ /* VFMSUBPS4mr */ >+ }, >+ { /* 3573 */ >+ 336, >+ /* VFMSUBPS4mrY */ >+ }, >+ { /* 3574 */ >+ 440, >+ /* VFMSUBPS4rm */ >+ }, >+ { /* 3575 */ >+ 441, >+ /* VFMSUBPS4rmY */ >+ }, >+ { /* 3576 */ >+ 442, >+ /* VFMSUBPS4rr */ >+ }, >+ { /* 3577 */ >+ 443, >+ /* VFMSUBPS4rrY */ >+ }, >+ { /* 3578 */ >+ 337, >+ /* VFMSUBPS4rrY_REV */ >+ }, >+ { /* 3579 */ >+ 339, >+ /* VFMSUBPS4rr_REV */ >+ }, >+ { /* 3580 */ >+ 444, >+ /* VFMSUBPSr132m */ >+ }, >+ { /* 3581 */ >+ 445, >+ /* VFMSUBPSr132mY */ >+ }, >+ { /* 3582 */ >+ 446, >+ /* VFMSUBPSr132r */ >+ }, >+ { /* 3583 */ >+ 447, >+ /* VFMSUBPSr132rY */ >+ }, >+ { /* 3584 */ >+ 444, >+ /* VFMSUBPSr213m */ >+ }, >+ { /* 3585 */ >+ 445, >+ /* VFMSUBPSr213mY */ >+ }, >+ { /* 3586 */ >+ 446, >+ /* VFMSUBPSr213r */ >+ }, >+ { /* 3587 */ >+ 447, >+ /* VFMSUBPSr213rY */ >+ }, >+ { /* 3588 */ >+ 444, >+ /* VFMSUBPSr231m */ >+ }, >+ { /* 3589 */ >+ 445, >+ /* VFMSUBPSr231mY */ >+ }, >+ { /* 3590 */ >+ 446, >+ /* VFMSUBPSr231r */ >+ }, >+ { /* 3591 */ >+ 447, >+ /* VFMSUBPSr231rY */ >+ }, >+ { /* 3592 */ >+ 448, >+ /* VFMSUBSD4mr */ >+ }, >+ { /* 3593 */ >+ 0, >+ /* */ >+ }, >+ { /* 3594 */ >+ 449, >+ /* VFMSUBSD4rm */ >+ }, >+ { /* 3595 */ >+ 0, >+ /* */ >+ }, >+ { /* 3596 */ >+ 450, >+ /* VFMSUBSD4rr */ >+ }, >+ { /* 3597 */ >+ 0, >+ /* */ >+ }, >+ { /* 3598 */ >+ 451, >+ /* VFMSUBSD4rr_REV */ >+ }, >+ { /* 3599 */ >+ 452, >+ /* VFMSUBSDZm */ >+ }, >+ { /* 3600 */ >+ 453, >+ /* VFMSUBSDZr */ >+ }, >+ { /* 3601 */ >+ 454, >+ /* VFMSUBSDr132m */ >+ }, >+ { /* 3602 */ >+ 455, >+ /* VFMSUBSDr132r */ >+ }, >+ { /* 3603 */ >+ 454, >+ /* VFMSUBSDr213m */ >+ }, >+ { /* 3604 */ >+ 455, >+ /* VFMSUBSDr213r */ >+ }, >+ { /* 3605 */ >+ 454, >+ /* VFMSUBSDr231m */ >+ }, >+ { /* 3606 */ >+ 455, >+ /* VFMSUBSDr231r */ >+ }, >+ { /* 3607 */ >+ 456, >+ /* VFMSUBSS4mr */ >+ }, >+ { /* 3608 */ >+ 0, >+ /* */ >+ }, >+ { /* 3609 */ >+ 457, >+ /* VFMSUBSS4rm */ >+ }, >+ { /* 3610 */ >+ 0, >+ /* */ >+ }, >+ { /* 3611 */ >+ 458, >+ /* VFMSUBSS4rr */ >+ }, >+ { /* 3612 */ >+ 0, >+ /* */ >+ }, >+ { /* 3613 */ >+ 459, >+ /* VFMSUBSS4rr_REV */ >+ }, >+ { /* 3614 */ >+ 460, >+ /* VFMSUBSSZm */ >+ }, >+ { /* 3615 */ >+ 461, >+ /* VFMSUBSSZr */ >+ }, >+ { /* 3616 */ >+ 462, >+ /* VFMSUBSSr132m */ >+ }, >+ { /* 3617 */ >+ 463, >+ /* VFMSUBSSr132r */ >+ }, >+ { /* 3618 */ >+ 462, >+ /* VFMSUBSSr213m */ >+ }, >+ { /* 3619 */ >+ 463, >+ /* VFMSUBSSr213r */ >+ }, >+ { /* 3620 */ >+ 462, >+ /* VFMSUBSSr231m */ >+ }, >+ { /* 3621 */ >+ 463, >+ /* VFMSUBSSr231r */ >+ }, >+ { /* 3622 */ >+ 434, >+ /* VFNMADD132PDZm */ >+ }, >+ { /* 3623 */ >+ 435, >+ /* VFNMADD132PDZmb */ >+ }, >+ { /* 3624 */ >+ 434, >+ /* VFNMADD132PSZm */ >+ }, >+ { /* 3625 */ >+ 436, >+ /* VFNMADD132PSZmb */ >+ }, >+ { /* 3626 */ >+ 434, >+ /* VFNMADD213PDZm */ >+ }, >+ { /* 3627 */ >+ 435, >+ /* VFNMADD213PDZmb */ >+ }, >+ { /* 3628 */ >+ 437, >+ /* VFNMADD213PDZr */ >+ }, >+ { /* 3629 */ >+ 438, >+ /* VFNMADD213PDZrk */ >+ }, >+ { /* 3630 */ >+ 438, >+ /* VFNMADD213PDZrkz */ >+ }, >+ { /* 3631 */ >+ 434, >+ /* VFNMADD213PSZm */ >+ }, >+ { /* 3632 */ >+ 436, >+ /* VFNMADD213PSZmb */ >+ }, >+ { /* 3633 */ >+ 437, >+ /* VFNMADD213PSZr */ >+ }, >+ { /* 3634 */ >+ 439, >+ /* VFNMADD213PSZrk */ >+ }, >+ { /* 3635 */ >+ 439, >+ /* VFNMADD213PSZrkz */ >+ }, >+ { /* 3636 */ >+ 338, >+ /* VFNMADDPD4mr */ >+ }, >+ { /* 3637 */ >+ 336, >+ /* VFNMADDPD4mrY */ >+ }, >+ { /* 3638 */ >+ 440, >+ /* VFNMADDPD4rm */ >+ }, >+ { /* 3639 */ >+ 441, >+ /* VFNMADDPD4rmY */ >+ }, >+ { /* 3640 */ >+ 442, >+ /* VFNMADDPD4rr */ >+ }, >+ { /* 3641 */ >+ 443, >+ /* VFNMADDPD4rrY */ >+ }, >+ { /* 3642 */ >+ 337, >+ /* VFNMADDPD4rrY_REV */ >+ }, >+ { /* 3643 */ >+ 339, >+ /* VFNMADDPD4rr_REV */ >+ }, >+ { /* 3644 */ >+ 444, >+ /* VFNMADDPDr132m */ >+ }, >+ { /* 3645 */ >+ 445, >+ /* VFNMADDPDr132mY */ >+ }, >+ { /* 3646 */ >+ 446, >+ /* VFNMADDPDr132r */ >+ }, >+ { /* 3647 */ >+ 447, >+ /* VFNMADDPDr132rY */ >+ }, >+ { /* 3648 */ >+ 444, >+ /* VFNMADDPDr213m */ >+ }, >+ { /* 3649 */ >+ 445, >+ /* VFNMADDPDr213mY */ >+ }, >+ { /* 3650 */ >+ 446, >+ /* VFNMADDPDr213r */ >+ }, >+ { /* 3651 */ >+ 447, >+ /* VFNMADDPDr213rY */ >+ }, >+ { /* 3652 */ >+ 444, >+ /* VFNMADDPDr231m */ >+ }, >+ { /* 3653 */ >+ 445, >+ /* VFNMADDPDr231mY */ >+ }, >+ { /* 3654 */ >+ 446, >+ /* VFNMADDPDr231r */ >+ }, >+ { /* 3655 */ >+ 447, >+ /* VFNMADDPDr231rY */ >+ }, >+ { /* 3656 */ >+ 338, >+ /* VFNMADDPS4mr */ >+ }, >+ { /* 3657 */ >+ 336, >+ /* VFNMADDPS4mrY */ >+ }, >+ { /* 3658 */ >+ 440, >+ /* VFNMADDPS4rm */ >+ }, >+ { /* 3659 */ >+ 441, >+ /* VFNMADDPS4rmY */ >+ }, >+ { /* 3660 */ >+ 442, >+ /* VFNMADDPS4rr */ >+ }, >+ { /* 3661 */ >+ 443, >+ /* VFNMADDPS4rrY */ >+ }, >+ { /* 3662 */ >+ 337, >+ /* VFNMADDPS4rrY_REV */ >+ }, >+ { /* 3663 */ >+ 339, >+ /* VFNMADDPS4rr_REV */ >+ }, >+ { /* 3664 */ >+ 444, >+ /* VFNMADDPSr132m */ >+ }, >+ { /* 3665 */ >+ 445, >+ /* VFNMADDPSr132mY */ >+ }, >+ { /* 3666 */ >+ 446, >+ /* VFNMADDPSr132r */ >+ }, >+ { /* 3667 */ >+ 447, >+ /* VFNMADDPSr132rY */ >+ }, >+ { /* 3668 */ >+ 444, >+ /* VFNMADDPSr213m */ >+ }, >+ { /* 3669 */ >+ 445, >+ /* VFNMADDPSr213mY */ >+ }, >+ { /* 3670 */ >+ 446, >+ /* VFNMADDPSr213r */ >+ }, >+ { /* 3671 */ >+ 447, >+ /* VFNMADDPSr213rY */ >+ }, >+ { /* 3672 */ >+ 444, >+ /* VFNMADDPSr231m */ >+ }, >+ { /* 3673 */ >+ 445, >+ /* VFNMADDPSr231mY */ >+ }, >+ { /* 3674 */ >+ 446, >+ /* VFNMADDPSr231r */ >+ }, >+ { /* 3675 */ >+ 447, >+ /* VFNMADDPSr231rY */ >+ }, >+ { /* 3676 */ >+ 448, >+ /* VFNMADDSD4mr */ >+ }, >+ { /* 3677 */ >+ 0, >+ /* */ >+ }, >+ { /* 3678 */ >+ 449, >+ /* VFNMADDSD4rm */ >+ }, >+ { /* 3679 */ >+ 0, >+ /* */ >+ }, >+ { /* 3680 */ >+ 450, >+ /* VFNMADDSD4rr */ >+ }, >+ { /* 3681 */ >+ 0, >+ /* */ >+ }, >+ { /* 3682 */ >+ 451, >+ /* VFNMADDSD4rr_REV */ >+ }, >+ { /* 3683 */ >+ 452, >+ /* VFNMADDSDZm */ >+ }, >+ { /* 3684 */ >+ 453, >+ /* VFNMADDSDZr */ >+ }, >+ { /* 3685 */ >+ 454, >+ /* VFNMADDSDr132m */ >+ }, >+ { /* 3686 */ >+ 455, >+ /* VFNMADDSDr132r */ >+ }, >+ { /* 3687 */ >+ 454, >+ /* VFNMADDSDr213m */ >+ }, >+ { /* 3688 */ >+ 455, >+ /* VFNMADDSDr213r */ >+ }, >+ { /* 3689 */ >+ 454, >+ /* VFNMADDSDr231m */ >+ }, >+ { /* 3690 */ >+ 455, >+ /* VFNMADDSDr231r */ >+ }, >+ { /* 3691 */ >+ 456, >+ /* VFNMADDSS4mr */ >+ }, >+ { /* 3692 */ >+ 0, >+ /* */ >+ }, >+ { /* 3693 */ >+ 457, >+ /* VFNMADDSS4rm */ >+ }, >+ { /* 3694 */ >+ 0, >+ /* */ >+ }, >+ { /* 3695 */ >+ 458, >+ /* VFNMADDSS4rr */ >+ }, >+ { /* 3696 */ >+ 0, >+ /* */ >+ }, >+ { /* 3697 */ >+ 459, >+ /* VFNMADDSS4rr_REV */ >+ }, >+ { /* 3698 */ >+ 460, >+ /* VFNMADDSSZm */ >+ }, >+ { /* 3699 */ >+ 461, >+ /* VFNMADDSSZr */ >+ }, >+ { /* 3700 */ >+ 462, >+ /* VFNMADDSSr132m */ >+ }, >+ { /* 3701 */ >+ 463, >+ /* VFNMADDSSr132r */ >+ }, >+ { /* 3702 */ >+ 462, >+ /* VFNMADDSSr213m */ >+ }, >+ { /* 3703 */ >+ 463, >+ /* VFNMADDSSr213r */ >+ }, >+ { /* 3704 */ >+ 462, >+ /* VFNMADDSSr231m */ >+ }, >+ { /* 3705 */ >+ 463, >+ /* VFNMADDSSr231r */ >+ }, >+ { /* 3706 */ >+ 434, >+ /* VFNMSUB132PDZm */ >+ }, >+ { /* 3707 */ >+ 435, >+ /* VFNMSUB132PDZmb */ >+ }, >+ { /* 3708 */ >+ 434, >+ /* VFNMSUB132PSZm */ >+ }, >+ { /* 3709 */ >+ 436, >+ /* VFNMSUB132PSZmb */ >+ }, >+ { /* 3710 */ >+ 434, >+ /* VFNMSUB213PDZm */ >+ }, >+ { /* 3711 */ >+ 435, >+ /* VFNMSUB213PDZmb */ >+ }, >+ { /* 3712 */ >+ 437, >+ /* VFNMSUB213PDZr */ >+ }, >+ { /* 3713 */ >+ 438, >+ /* VFNMSUB213PDZrk */ >+ }, >+ { /* 3714 */ >+ 438, >+ /* VFNMSUB213PDZrkz */ >+ }, >+ { /* 3715 */ >+ 434, >+ /* VFNMSUB213PSZm */ >+ }, >+ { /* 3716 */ >+ 436, >+ /* VFNMSUB213PSZmb */ >+ }, >+ { /* 3717 */ >+ 437, >+ /* VFNMSUB213PSZr */ >+ }, >+ { /* 3718 */ >+ 439, >+ /* VFNMSUB213PSZrk */ >+ }, >+ { /* 3719 */ >+ 439, >+ /* VFNMSUB213PSZrkz */ >+ }, >+ { /* 3720 */ >+ 338, >+ /* VFNMSUBPD4mr */ >+ }, >+ { /* 3721 */ >+ 336, >+ /* VFNMSUBPD4mrY */ >+ }, >+ { /* 3722 */ >+ 440, >+ /* VFNMSUBPD4rm */ >+ }, >+ { /* 3723 */ >+ 441, >+ /* VFNMSUBPD4rmY */ >+ }, >+ { /* 3724 */ >+ 442, >+ /* VFNMSUBPD4rr */ >+ }, >+ { /* 3725 */ >+ 443, >+ /* VFNMSUBPD4rrY */ >+ }, >+ { /* 3726 */ >+ 337, >+ /* VFNMSUBPD4rrY_REV */ >+ }, >+ { /* 3727 */ >+ 339, >+ /* VFNMSUBPD4rr_REV */ >+ }, >+ { /* 3728 */ >+ 444, >+ /* VFNMSUBPDr132m */ >+ }, >+ { /* 3729 */ >+ 445, >+ /* VFNMSUBPDr132mY */ >+ }, >+ { /* 3730 */ >+ 446, >+ /* VFNMSUBPDr132r */ >+ }, >+ { /* 3731 */ >+ 447, >+ /* VFNMSUBPDr132rY */ >+ }, >+ { /* 3732 */ >+ 444, >+ /* VFNMSUBPDr213m */ >+ }, >+ { /* 3733 */ >+ 445, >+ /* VFNMSUBPDr213mY */ >+ }, >+ { /* 3734 */ >+ 446, >+ /* VFNMSUBPDr213r */ >+ }, >+ { /* 3735 */ >+ 447, >+ /* VFNMSUBPDr213rY */ >+ }, >+ { /* 3736 */ >+ 444, >+ /* VFNMSUBPDr231m */ >+ }, >+ { /* 3737 */ >+ 445, >+ /* VFNMSUBPDr231mY */ >+ }, >+ { /* 3738 */ >+ 446, >+ /* VFNMSUBPDr231r */ >+ }, >+ { /* 3739 */ >+ 447, >+ /* VFNMSUBPDr231rY */ >+ }, >+ { /* 3740 */ >+ 338, >+ /* VFNMSUBPS4mr */ >+ }, >+ { /* 3741 */ >+ 336, >+ /* VFNMSUBPS4mrY */ >+ }, >+ { /* 3742 */ >+ 440, >+ /* VFNMSUBPS4rm */ >+ }, >+ { /* 3743 */ >+ 441, >+ /* VFNMSUBPS4rmY */ >+ }, >+ { /* 3744 */ >+ 442, >+ /* VFNMSUBPS4rr */ >+ }, >+ { /* 3745 */ >+ 443, >+ /* VFNMSUBPS4rrY */ >+ }, >+ { /* 3746 */ >+ 337, >+ /* VFNMSUBPS4rrY_REV */ >+ }, >+ { /* 3747 */ >+ 339, >+ /* VFNMSUBPS4rr_REV */ >+ }, >+ { /* 3748 */ >+ 444, >+ /* VFNMSUBPSr132m */ >+ }, >+ { /* 3749 */ >+ 445, >+ /* VFNMSUBPSr132mY */ >+ }, >+ { /* 3750 */ >+ 446, >+ /* VFNMSUBPSr132r */ >+ }, >+ { /* 3751 */ >+ 447, >+ /* VFNMSUBPSr132rY */ >+ }, >+ { /* 3752 */ >+ 444, >+ /* VFNMSUBPSr213m */ >+ }, >+ { /* 3753 */ >+ 445, >+ /* VFNMSUBPSr213mY */ >+ }, >+ { /* 3754 */ >+ 446, >+ /* VFNMSUBPSr213r */ >+ }, >+ { /* 3755 */ >+ 447, >+ /* VFNMSUBPSr213rY */ >+ }, >+ { /* 3756 */ >+ 444, >+ /* VFNMSUBPSr231m */ >+ }, >+ { /* 3757 */ >+ 445, >+ /* VFNMSUBPSr231mY */ >+ }, >+ { /* 3758 */ >+ 446, >+ /* VFNMSUBPSr231r */ >+ }, >+ { /* 3759 */ >+ 447, >+ /* VFNMSUBPSr231rY */ >+ }, >+ { /* 3760 */ >+ 448, >+ /* VFNMSUBSD4mr */ >+ }, >+ { /* 3761 */ >+ 0, >+ /* */ >+ }, >+ { /* 3762 */ >+ 449, >+ /* VFNMSUBSD4rm */ >+ }, >+ { /* 3763 */ >+ 0, >+ /* */ >+ }, >+ { /* 3764 */ >+ 450, >+ /* VFNMSUBSD4rr */ >+ }, >+ { /* 3765 */ >+ 0, >+ /* */ >+ }, >+ { /* 3766 */ >+ 451, >+ /* VFNMSUBSD4rr_REV */ >+ }, >+ { /* 3767 */ >+ 452, >+ /* VFNMSUBSDZm */ >+ }, >+ { /* 3768 */ >+ 453, >+ /* VFNMSUBSDZr */ >+ }, >+ { /* 3769 */ >+ 454, >+ /* VFNMSUBSDr132m */ >+ }, >+ { /* 3770 */ >+ 455, >+ /* VFNMSUBSDr132r */ >+ }, >+ { /* 3771 */ >+ 454, >+ /* VFNMSUBSDr213m */ >+ }, >+ { /* 3772 */ >+ 455, >+ /* VFNMSUBSDr213r */ >+ }, >+ { /* 3773 */ >+ 454, >+ /* VFNMSUBSDr231m */ >+ }, >+ { /* 3774 */ >+ 455, >+ /* VFNMSUBSDr231r */ >+ }, >+ { /* 3775 */ >+ 456, >+ /* VFNMSUBSS4mr */ >+ }, >+ { /* 3776 */ >+ 0, >+ /* */ >+ }, >+ { /* 3777 */ >+ 457, >+ /* VFNMSUBSS4rm */ >+ }, >+ { /* 3778 */ >+ 0, >+ /* */ >+ }, >+ { /* 3779 */ >+ 458, >+ /* VFNMSUBSS4rr */ >+ }, >+ { /* 3780 */ >+ 0, >+ /* */ >+ }, >+ { /* 3781 */ >+ 459, >+ /* VFNMSUBSS4rr_REV */ >+ }, >+ { /* 3782 */ >+ 460, >+ /* VFNMSUBSSZm */ >+ }, >+ { /* 3783 */ >+ 461, >+ /* VFNMSUBSSZr */ >+ }, >+ { /* 3784 */ >+ 462, >+ /* VFNMSUBSSr132m */ >+ }, >+ { /* 3785 */ >+ 463, >+ /* VFNMSUBSSr132r */ >+ }, >+ { /* 3786 */ >+ 462, >+ /* VFNMSUBSSr213m */ >+ }, >+ { /* 3787 */ >+ 463, >+ /* VFNMSUBSSr213r */ >+ }, >+ { /* 3788 */ >+ 462, >+ /* VFNMSUBSSr231m */ >+ }, >+ { /* 3789 */ >+ 463, >+ /* VFNMSUBSSr231r */ >+ }, >+ { /* 3790 */ >+ 44, >+ /* VFRCZPDrm */ >+ }, >+ { /* 3791 */ >+ 376, >+ /* VFRCZPDrmY */ >+ }, >+ { /* 3792 */ >+ 45, >+ /* VFRCZPDrr */ >+ }, >+ { /* 3793 */ >+ 377, >+ /* VFRCZPDrrY */ >+ }, >+ { /* 3794 */ >+ 44, >+ /* VFRCZPSrm */ >+ }, >+ { /* 3795 */ >+ 376, >+ /* VFRCZPSrmY */ >+ }, >+ { /* 3796 */ >+ 45, >+ /* VFRCZPSrr */ >+ }, >+ { /* 3797 */ >+ 377, >+ /* VFRCZPSrrY */ >+ }, >+ { /* 3798 */ >+ 106, >+ /* VFRCZSDrm */ >+ }, >+ { /* 3799 */ >+ 45, >+ /* VFRCZSDrr */ >+ }, >+ { /* 3800 */ >+ 352, >+ /* VFRCZSSrm */ >+ }, >+ { /* 3801 */ >+ 45, >+ /* VFRCZSSrr */ >+ }, >+ { /* 3802 */ >+ 0, >+ /* */ >+ }, >+ { /* 3803 */ >+ 0, >+ /* */ >+ }, >+ { /* 3804 */ >+ 0, >+ /* */ >+ }, >+ { /* 3805 */ >+ 0, >+ /* */ >+ }, >+ { /* 3806 */ >+ 0, >+ /* */ >+ }, >+ { /* 3807 */ >+ 0, >+ /* */ >+ }, >+ { /* 3808 */ >+ 0, >+ /* */ >+ }, >+ { /* 3809 */ >+ 0, >+ /* */ >+ }, >+ { /* 3810 */ >+ 0, >+ /* */ >+ }, >+ { /* 3811 */ >+ 0, >+ /* */ >+ }, >+ { /* 3812 */ >+ 0, >+ /* */ >+ }, >+ { /* 3813 */ >+ 0, >+ /* */ >+ }, >+ { /* 3814 */ >+ 0, >+ /* */ >+ }, >+ { /* 3815 */ >+ 0, >+ /* */ >+ }, >+ { /* 3816 */ >+ 0, >+ /* */ >+ }, >+ { /* 3817 */ >+ 0, >+ /* */ >+ }, >+ { /* 3818 */ >+ 464, >+ /* VGATHERDPDYrm */ >+ }, >+ { /* 3819 */ >+ 465, >+ /* VGATHERDPDZrm */ >+ }, >+ { /* 3820 */ >+ 466, >+ /* VGATHERDPDrm */ >+ }, >+ { /* 3821 */ >+ 467, >+ /* VGATHERDPSYrm */ >+ }, >+ { /* 3822 */ >+ 468, >+ /* VGATHERDPSZrm */ >+ }, >+ { /* 3823 */ >+ 469, >+ /* VGATHERDPSrm */ >+ }, >+ { /* 3824 */ >+ 470, >+ /* VGATHERPF0DPDm */ >+ }, >+ { /* 3825 */ >+ 471, >+ /* VGATHERPF0DPSm */ >+ }, >+ { /* 3826 */ >+ 472, >+ /* VGATHERPF0QPDm */ >+ }, >+ { /* 3827 */ >+ 472, >+ /* VGATHERPF0QPSm */ >+ }, >+ { /* 3828 */ >+ 470, >+ /* VGATHERPF1DPDm */ >+ }, >+ { /* 3829 */ >+ 471, >+ /* VGATHERPF1DPSm */ >+ }, >+ { /* 3830 */ >+ 472, >+ /* VGATHERPF1QPDm */ >+ }, >+ { /* 3831 */ >+ 472, >+ /* VGATHERPF1QPSm */ >+ }, >+ { /* 3832 */ >+ 464, >+ /* VGATHERQPDYrm */ >+ }, >+ { /* 3833 */ >+ 465, >+ /* VGATHERQPDZrm */ >+ }, >+ { /* 3834 */ >+ 466, >+ /* VGATHERQPDrm */ >+ }, >+ { /* 3835 */ >+ 469, >+ /* VGATHERQPSYrm */ >+ }, >+ { /* 3836 */ >+ 473, >+ /* VGATHERQPSZrm */ >+ }, >+ { /* 3837 */ >+ 469, >+ /* VGATHERQPSrm */ >+ }, >+ { /* 3838 */ >+ 304, >+ /* VHADDPDYrm */ >+ }, >+ { /* 3839 */ >+ 305, >+ /* VHADDPDYrr */ >+ }, >+ { /* 3840 */ >+ 312, >+ /* VHADDPDrm */ >+ }, >+ { /* 3841 */ >+ 313, >+ /* VHADDPDrr */ >+ }, >+ { /* 3842 */ >+ 304, >+ /* VHADDPSYrm */ >+ }, >+ { /* 3843 */ >+ 305, >+ /* VHADDPSYrr */ >+ }, >+ { /* 3844 */ >+ 312, >+ /* VHADDPSrm */ >+ }, >+ { /* 3845 */ >+ 313, >+ /* VHADDPSrr */ >+ }, >+ { /* 3846 */ >+ 304, >+ /* VHSUBPDYrm */ >+ }, >+ { /* 3847 */ >+ 305, >+ /* VHSUBPDYrr */ >+ }, >+ { /* 3848 */ >+ 312, >+ /* VHSUBPDrm */ >+ }, >+ { /* 3849 */ >+ 313, >+ /* VHSUBPDrr */ >+ }, >+ { /* 3850 */ >+ 304, >+ /* VHSUBPSYrm */ >+ }, >+ { /* 3851 */ >+ 305, >+ /* VHSUBPSYrr */ >+ }, >+ { /* 3852 */ >+ 312, >+ /* VHSUBPSrm */ >+ }, >+ { /* 3853 */ >+ 313, >+ /* VHSUBPSrr */ >+ }, >+ { /* 3854 */ >+ 474, >+ /* VINSERTF128rm */ >+ }, >+ { /* 3855 */ >+ 475, >+ /* VINSERTF128rr */ >+ }, >+ { /* 3856 */ >+ 476, >+ /* VINSERTF32x4rm */ >+ }, >+ { /* 3857 */ >+ 477, >+ /* VINSERTF32x4rr */ >+ }, >+ { /* 3858 */ >+ 478, >+ /* VINSERTF64x4rm */ >+ }, >+ { /* 3859 */ >+ 479, >+ /* VINSERTF64x4rr */ >+ }, >+ { /* 3860 */ >+ 474, >+ /* VINSERTI128rm */ >+ }, >+ { /* 3861 */ >+ 475, >+ /* VINSERTI128rr */ >+ }, >+ { /* 3862 */ >+ 476, >+ /* VINSERTI32x4rm */ >+ }, >+ { /* 3863 */ >+ 477, >+ /* VINSERTI32x4rr */ >+ }, >+ { /* 3864 */ >+ 478, >+ /* VINSERTI64x4rm */ >+ }, >+ { /* 3865 */ >+ 479, >+ /* VINSERTI64x4rr */ >+ }, >+ { /* 3866 */ >+ 480, >+ /* VINSERTPSrm */ >+ }, >+ { /* 3867 */ >+ 335, >+ /* VINSERTPSrr */ >+ }, >+ { /* 3868 */ >+ 481, >+ /* VINSERTPSzrm */ >+ }, >+ { /* 3869 */ >+ 482, >+ /* VINSERTPSzrr */ >+ }, >+ { /* 3870 */ >+ 376, >+ /* VLDDQUYrm */ >+ }, >+ { /* 3871 */ >+ 44, >+ /* VLDDQUrm */ >+ }, >+ { /* 3872 */ >+ 38, >+ /* VLDMXCSR */ >+ }, >+ { /* 3873 */ >+ 45, >+ /* VMASKMOVDQU */ >+ }, >+ { /* 3874 */ >+ 0, >+ /* */ >+ }, >+ { /* 3875 */ >+ 483, >+ /* VMASKMOVPDYmr */ >+ }, >+ { /* 3876 */ >+ 304, >+ /* VMASKMOVPDYrm */ >+ }, >+ { /* 3877 */ >+ 484, >+ /* VMASKMOVPDmr */ >+ }, >+ { /* 3878 */ >+ 312, >+ /* VMASKMOVPDrm */ >+ }, >+ { /* 3879 */ >+ 483, >+ /* VMASKMOVPSYmr */ >+ }, >+ { /* 3880 */ >+ 304, >+ /* VMASKMOVPSYrm */ >+ }, >+ { /* 3881 */ >+ 484, >+ /* VMASKMOVPSmr */ >+ }, >+ { /* 3882 */ >+ 312, >+ /* VMASKMOVPSrm */ >+ }, >+ { /* 3883 */ >+ 0, >+ /* */ >+ }, >+ { /* 3884 */ >+ 0, >+ /* */ >+ }, >+ { /* 3885 */ >+ 0, >+ /* */ >+ }, >+ { /* 3886 */ >+ 0, >+ /* */ >+ }, >+ { /* 3887 */ >+ 0, >+ /* */ >+ }, >+ { /* 3888 */ >+ 0, >+ /* */ >+ }, >+ { /* 3889 */ >+ 0, >+ /* */ >+ }, >+ { /* 3890 */ >+ 0, >+ /* */ >+ }, >+ { /* 3891 */ >+ 0, >+ /* */ >+ }, >+ { /* 3892 */ >+ 0, >+ /* */ >+ }, >+ { /* 3893 */ >+ 0, >+ /* */ >+ }, >+ { /* 3894 */ >+ 0, >+ /* */ >+ }, >+ { /* 3895 */ >+ 304, >+ /* VMAXPDYrm */ >+ }, >+ { /* 3896 */ >+ 305, >+ /* VMAXPDYrr */ >+ }, >+ { /* 3897 */ >+ 306, >+ /* VMAXPDZrm */ >+ }, >+ { /* 3898 */ >+ 307, >+ /* VMAXPDZrmb */ >+ }, >+ { /* 3899 */ >+ 308, >+ /* VMAXPDZrmbk */ >+ }, >+ { /* 3900 */ >+ 308, >+ /* VMAXPDZrmbkz */ >+ }, >+ { /* 3901 */ >+ 309, >+ /* VMAXPDZrmk */ >+ }, >+ { /* 3902 */ >+ 309, >+ /* VMAXPDZrmkz */ >+ }, >+ { /* 3903 */ >+ 310, >+ /* VMAXPDZrr */ >+ }, >+ { /* 3904 */ >+ 311, >+ /* VMAXPDZrrk */ >+ }, >+ { /* 3905 */ >+ 311, >+ /* VMAXPDZrrkz */ >+ }, >+ { /* 3906 */ >+ 312, >+ /* VMAXPDrm */ >+ }, >+ { /* 3907 */ >+ 313, >+ /* VMAXPDrr */ >+ }, >+ { /* 3908 */ >+ 304, >+ /* VMAXPSYrm */ >+ }, >+ { /* 3909 */ >+ 305, >+ /* VMAXPSYrr */ >+ }, >+ { /* 3910 */ >+ 306, >+ /* VMAXPSZrm */ >+ }, >+ { /* 3911 */ >+ 314, >+ /* VMAXPSZrmb */ >+ }, >+ { /* 3912 */ >+ 315, >+ /* VMAXPSZrmbk */ >+ }, >+ { /* 3913 */ >+ 315, >+ /* VMAXPSZrmbkz */ >+ }, >+ { /* 3914 */ >+ 316, >+ /* VMAXPSZrmk */ >+ }, >+ { /* 3915 */ >+ 316, >+ /* VMAXPSZrmkz */ >+ }, >+ { /* 3916 */ >+ 310, >+ /* VMAXPSZrr */ >+ }, >+ { /* 3917 */ >+ 317, >+ /* VMAXPSZrrk */ >+ }, >+ { /* 3918 */ >+ 317, >+ /* VMAXPSZrrkz */ >+ }, >+ { /* 3919 */ >+ 312, >+ /* VMAXPSrm */ >+ }, >+ { /* 3920 */ >+ 313, >+ /* VMAXPSrr */ >+ }, >+ { /* 3921 */ >+ 318, >+ /* VMAXSDZrm */ >+ }, >+ { /* 3922 */ >+ 319, >+ /* VMAXSDZrr */ >+ }, >+ { /* 3923 */ >+ 320, >+ /* VMAXSDrm */ >+ }, >+ { /* 3924 */ >+ 0, >+ /* */ >+ }, >+ { /* 3925 */ >+ 321, >+ /* VMAXSDrr */ >+ }, >+ { /* 3926 */ >+ 0, >+ /* */ >+ }, >+ { /* 3927 */ >+ 322, >+ /* VMAXSSZrm */ >+ }, >+ { /* 3928 */ >+ 323, >+ /* VMAXSSZrr */ >+ }, >+ { /* 3929 */ >+ 324, >+ /* VMAXSSrm */ >+ }, >+ { /* 3930 */ >+ 0, >+ /* */ >+ }, >+ { /* 3931 */ >+ 325, >+ /* VMAXSSrr */ >+ }, >+ { /* 3932 */ >+ 0, >+ /* */ >+ }, >+ { /* 3933 */ >+ 0, >+ /* VMCALL */ >+ }, >+ { /* 3934 */ >+ 38, >+ /* VMCLEARm */ >+ }, >+ { /* 3935 */ >+ 0, >+ /* VMFUNC */ >+ }, >+ { /* 3936 */ >+ 0, >+ /* */ >+ }, >+ { /* 3937 */ >+ 0, >+ /* */ >+ }, >+ { /* 3938 */ >+ 0, >+ /* */ >+ }, >+ { /* 3939 */ >+ 0, >+ /* */ >+ }, >+ { /* 3940 */ >+ 0, >+ /* */ >+ }, >+ { /* 3941 */ >+ 0, >+ /* */ >+ }, >+ { /* 3942 */ >+ 0, >+ /* */ >+ }, >+ { /* 3943 */ >+ 0, >+ /* */ >+ }, >+ { /* 3944 */ >+ 0, >+ /* */ >+ }, >+ { /* 3945 */ >+ 0, >+ /* */ >+ }, >+ { /* 3946 */ >+ 0, >+ /* */ >+ }, >+ { /* 3947 */ >+ 0, >+ /* */ >+ }, >+ { /* 3948 */ >+ 304, >+ /* VMINPDYrm */ >+ }, >+ { /* 3949 */ >+ 305, >+ /* VMINPDYrr */ >+ }, >+ { /* 3950 */ >+ 306, >+ /* VMINPDZrm */ >+ }, >+ { /* 3951 */ >+ 307, >+ /* VMINPDZrmb */ >+ }, >+ { /* 3952 */ >+ 308, >+ /* VMINPDZrmbk */ >+ }, >+ { /* 3953 */ >+ 308, >+ /* VMINPDZrmbkz */ >+ }, >+ { /* 3954 */ >+ 309, >+ /* VMINPDZrmk */ >+ }, >+ { /* 3955 */ >+ 309, >+ /* VMINPDZrmkz */ >+ }, >+ { /* 3956 */ >+ 310, >+ /* VMINPDZrr */ >+ }, >+ { /* 3957 */ >+ 311, >+ /* VMINPDZrrk */ >+ }, >+ { /* 3958 */ >+ 311, >+ /* VMINPDZrrkz */ >+ }, >+ { /* 3959 */ >+ 312, >+ /* VMINPDrm */ >+ }, >+ { /* 3960 */ >+ 313, >+ /* VMINPDrr */ >+ }, >+ { /* 3961 */ >+ 304, >+ /* VMINPSYrm */ >+ }, >+ { /* 3962 */ >+ 305, >+ /* VMINPSYrr */ >+ }, >+ { /* 3963 */ >+ 306, >+ /* VMINPSZrm */ >+ }, >+ { /* 3964 */ >+ 314, >+ /* VMINPSZrmb */ >+ }, >+ { /* 3965 */ >+ 315, >+ /* VMINPSZrmbk */ >+ }, >+ { /* 3966 */ >+ 315, >+ /* VMINPSZrmbkz */ >+ }, >+ { /* 3967 */ >+ 316, >+ /* VMINPSZrmk */ >+ }, >+ { /* 3968 */ >+ 316, >+ /* VMINPSZrmkz */ >+ }, >+ { /* 3969 */ >+ 310, >+ /* VMINPSZrr */ >+ }, >+ { /* 3970 */ >+ 317, >+ /* VMINPSZrrk */ >+ }, >+ { /* 3971 */ >+ 317, >+ /* VMINPSZrrkz */ >+ }, >+ { /* 3972 */ >+ 312, >+ /* VMINPSrm */ >+ }, >+ { /* 3973 */ >+ 313, >+ /* VMINPSrr */ >+ }, >+ { /* 3974 */ >+ 318, >+ /* VMINSDZrm */ >+ }, >+ { /* 3975 */ >+ 319, >+ /* VMINSDZrr */ >+ }, >+ { /* 3976 */ >+ 320, >+ /* VMINSDrm */ >+ }, >+ { /* 3977 */ >+ 0, >+ /* */ >+ }, >+ { /* 3978 */ >+ 321, >+ /* VMINSDrr */ >+ }, >+ { /* 3979 */ >+ 0, >+ /* */ >+ }, >+ { /* 3980 */ >+ 322, >+ /* VMINSSZrm */ >+ }, >+ { /* 3981 */ >+ 323, >+ /* VMINSSZrr */ >+ }, >+ { /* 3982 */ >+ 324, >+ /* VMINSSrm */ >+ }, >+ { /* 3983 */ >+ 0, >+ /* */ >+ }, >+ { /* 3984 */ >+ 325, >+ /* VMINSSrr */ >+ }, >+ { /* 3985 */ >+ 0, >+ /* */ >+ }, >+ { /* 3986 */ >+ 0, >+ /* VMLAUNCH */ >+ }, >+ { /* 3987 */ >+ 0, >+ /* VMLOAD32 */ >+ }, >+ { /* 3988 */ >+ 0, >+ /* VMLOAD64 */ >+ }, >+ { /* 3989 */ >+ 0, >+ /* VMMCALL */ >+ }, >+ { /* 3990 */ >+ 485, >+ /* VMOV64toPQIZrr */ >+ }, >+ { /* 3991 */ >+ 241, >+ /* VMOV64toPQIrr */ >+ }, >+ { /* 3992 */ >+ 0, >+ /* */ >+ }, >+ { /* 3993 */ >+ 0, >+ /* */ >+ }, >+ { /* 3994 */ >+ 0, >+ /* */ >+ }, >+ { /* 3995 */ >+ 486, >+ /* VMOVAPDYmr */ >+ }, >+ { /* 3996 */ >+ 376, >+ /* VMOVAPDYrm */ >+ }, >+ { /* 3997 */ >+ 377, >+ /* VMOVAPDYrr */ >+ }, >+ { /* 3998 */ >+ 487, >+ /* VMOVAPDYrr_REV */ >+ }, >+ { /* 3999 */ >+ 488, >+ /* VMOVAPDZ128mr */ >+ }, >+ { /* 4000 */ >+ 489, >+ /* VMOVAPDZ128mrk */ >+ }, >+ { /* 4001 */ >+ 490, >+ /* VMOVAPDZ128rm */ >+ }, >+ { /* 4002 */ >+ 491, >+ /* VMOVAPDZ128rmk */ >+ }, >+ { /* 4003 */ >+ 492, >+ /* VMOVAPDZ128rmkz */ >+ }, >+ { /* 4004 */ >+ 493, >+ /* VMOVAPDZ128rr */ >+ }, >+ { /* 4005 */ >+ 0, >+ /* */ >+ }, >+ { /* 4006 */ >+ 494, >+ /* VMOVAPDZ128rrk */ >+ }, >+ { /* 4007 */ >+ 0, >+ /* */ >+ }, >+ { /* 4008 */ >+ 495, >+ /* VMOVAPDZ128rrkz */ >+ }, >+ { /* 4009 */ >+ 0, >+ /* */ >+ }, >+ { /* 4010 */ >+ 496, >+ /* VMOVAPDZ256mr */ >+ }, >+ { /* 4011 */ >+ 497, >+ /* VMOVAPDZ256mrk */ >+ }, >+ { /* 4012 */ >+ 498, >+ /* VMOVAPDZ256rm */ >+ }, >+ { /* 4013 */ >+ 499, >+ /* VMOVAPDZ256rmk */ >+ }, >+ { /* 4014 */ >+ 500, >+ /* VMOVAPDZ256rmkz */ >+ }, >+ { /* 4015 */ >+ 501, >+ /* VMOVAPDZ256rr */ >+ }, >+ { /* 4016 */ >+ 0, >+ /* */ >+ }, >+ { /* 4017 */ >+ 502, >+ /* VMOVAPDZ256rrk */ >+ }, >+ { /* 4018 */ >+ 0, >+ /* */ >+ }, >+ { /* 4019 */ >+ 503, >+ /* VMOVAPDZ256rrkz */ >+ }, >+ { /* 4020 */ >+ 0, >+ /* */ >+ }, >+ { /* 4021 */ >+ 504, >+ /* VMOVAPDZmr */ >+ }, >+ { /* 4022 */ >+ 505, >+ /* VMOVAPDZmrk */ >+ }, >+ { /* 4023 */ >+ 378, >+ /* VMOVAPDZrm */ >+ }, >+ { /* 4024 */ >+ 506, >+ /* VMOVAPDZrmk */ >+ }, >+ { /* 4025 */ >+ 507, >+ /* VMOVAPDZrmkz */ >+ }, >+ { /* 4026 */ >+ 379, >+ /* VMOVAPDZrr */ >+ }, >+ { /* 4027 */ >+ 0, >+ /* */ >+ }, >+ { /* 4028 */ >+ 508, >+ /* VMOVAPDZrrk */ >+ }, >+ { /* 4029 */ >+ 0, >+ /* */ >+ }, >+ { /* 4030 */ >+ 509, >+ /* VMOVAPDZrrkz */ >+ }, >+ { /* 4031 */ >+ 0, >+ /* */ >+ }, >+ { /* 4032 */ >+ 243, >+ /* VMOVAPDmr */ >+ }, >+ { /* 4033 */ >+ 44, >+ /* VMOVAPDrm */ >+ }, >+ { /* 4034 */ >+ 45, >+ /* VMOVAPDrr */ >+ }, >+ { /* 4035 */ >+ 244, >+ /* VMOVAPDrr_REV */ >+ }, >+ { /* 4036 */ >+ 486, >+ /* VMOVAPSYmr */ >+ }, >+ { /* 4037 */ >+ 376, >+ /* VMOVAPSYrm */ >+ }, >+ { /* 4038 */ >+ 377, >+ /* VMOVAPSYrr */ >+ }, >+ { /* 4039 */ >+ 487, >+ /* VMOVAPSYrr_REV */ >+ }, >+ { /* 4040 */ >+ 488, >+ /* VMOVAPSZ128mr */ >+ }, >+ { /* 4041 */ >+ 510, >+ /* VMOVAPSZ128mrk */ >+ }, >+ { /* 4042 */ >+ 490, >+ /* VMOVAPSZ128rm */ >+ }, >+ { /* 4043 */ >+ 511, >+ /* VMOVAPSZ128rmk */ >+ }, >+ { /* 4044 */ >+ 512, >+ /* VMOVAPSZ128rmkz */ >+ }, >+ { /* 4045 */ >+ 493, >+ /* VMOVAPSZ128rr */ >+ }, >+ { /* 4046 */ >+ 0, >+ /* */ >+ }, >+ { /* 4047 */ >+ 513, >+ /* VMOVAPSZ128rrk */ >+ }, >+ { /* 4048 */ >+ 0, >+ /* */ >+ }, >+ { /* 4049 */ >+ 514, >+ /* VMOVAPSZ128rrkz */ >+ }, >+ { /* 4050 */ >+ 0, >+ /* */ >+ }, >+ { /* 4051 */ >+ 496, >+ /* VMOVAPSZ256mr */ >+ }, >+ { /* 4052 */ >+ 515, >+ /* VMOVAPSZ256mrk */ >+ }, >+ { /* 4053 */ >+ 498, >+ /* VMOVAPSZ256rm */ >+ }, >+ { /* 4054 */ >+ 516, >+ /* VMOVAPSZ256rmk */ >+ }, >+ { /* 4055 */ >+ 517, >+ /* VMOVAPSZ256rmkz */ >+ }, >+ { /* 4056 */ >+ 501, >+ /* VMOVAPSZ256rr */ >+ }, >+ { /* 4057 */ >+ 0, >+ /* */ >+ }, >+ { /* 4058 */ >+ 518, >+ /* VMOVAPSZ256rrk */ >+ }, >+ { /* 4059 */ >+ 0, >+ /* */ >+ }, >+ { /* 4060 */ >+ 519, >+ /* VMOVAPSZ256rrkz */ >+ }, >+ { /* 4061 */ >+ 0, >+ /* */ >+ }, >+ { /* 4062 */ >+ 504, >+ /* VMOVAPSZmr */ >+ }, >+ { /* 4063 */ >+ 520, >+ /* VMOVAPSZmrk */ >+ }, >+ { /* 4064 */ >+ 378, >+ /* VMOVAPSZrm */ >+ }, >+ { /* 4065 */ >+ 521, >+ /* VMOVAPSZrmk */ >+ }, >+ { /* 4066 */ >+ 522, >+ /* VMOVAPSZrmkz */ >+ }, >+ { /* 4067 */ >+ 379, >+ /* VMOVAPSZrr */ >+ }, >+ { /* 4068 */ >+ 0, >+ /* */ >+ }, >+ { /* 4069 */ >+ 523, >+ /* VMOVAPSZrrk */ >+ }, >+ { /* 4070 */ >+ 0, >+ /* */ >+ }, >+ { /* 4071 */ >+ 524, >+ /* VMOVAPSZrrkz */ >+ }, >+ { /* 4072 */ >+ 0, >+ /* */ >+ }, >+ { /* 4073 */ >+ 243, >+ /* VMOVAPSmr */ >+ }, >+ { /* 4074 */ >+ 44, >+ /* VMOVAPSrm */ >+ }, >+ { /* 4075 */ >+ 45, >+ /* VMOVAPSrr */ >+ }, >+ { /* 4076 */ >+ 244, >+ /* VMOVAPSrr_REV */ >+ }, >+ { /* 4077 */ >+ 376, >+ /* VMOVDDUPYrm */ >+ }, >+ { /* 4078 */ >+ 377, >+ /* VMOVDDUPYrr */ >+ }, >+ { /* 4079 */ >+ 378, >+ /* VMOVDDUPZrm */ >+ }, >+ { /* 4080 */ >+ 379, >+ /* VMOVDDUPZrr */ >+ }, >+ { /* 4081 */ >+ 106, >+ /* VMOVDDUPrm */ >+ }, >+ { /* 4082 */ >+ 45, >+ /* VMOVDDUPrr */ >+ }, >+ { /* 4083 */ >+ 525, >+ /* VMOVDI2PDIZrm */ >+ }, >+ { /* 4084 */ >+ 526, >+ /* VMOVDI2PDIZrr */ >+ }, >+ { /* 4085 */ >+ 105, >+ /* VMOVDI2PDIrm */ >+ }, >+ { /* 4086 */ >+ 245, >+ /* VMOVDI2PDIrr */ >+ }, >+ { /* 4087 */ >+ 0, >+ /* */ >+ }, >+ { /* 4088 */ >+ 0, >+ /* */ >+ }, >+ { /* 4089 */ >+ 0, >+ /* */ >+ }, >+ { /* 4090 */ >+ 0, >+ /* */ >+ }, >+ { /* 4091 */ >+ 488, >+ /* VMOVDQA32Z128mr */ >+ }, >+ { /* 4092 */ >+ 510, >+ /* VMOVDQA32Z128mrk */ >+ }, >+ { /* 4093 */ >+ 490, >+ /* VMOVDQA32Z128rm */ >+ }, >+ { /* 4094 */ >+ 511, >+ /* VMOVDQA32Z128rmk */ >+ }, >+ { /* 4095 */ >+ 512, >+ /* VMOVDQA32Z128rmkz */ >+ }, >+ { /* 4096 */ >+ 493, >+ /* VMOVDQA32Z128rr */ >+ }, >+ { /* 4097 */ >+ 0, >+ /* */ >+ }, >+ { /* 4098 */ >+ 513, >+ /* VMOVDQA32Z128rrk */ >+ }, >+ { /* 4099 */ >+ 0, >+ /* */ >+ }, >+ { /* 4100 */ >+ 514, >+ /* VMOVDQA32Z128rrkz */ >+ }, >+ { /* 4101 */ >+ 0, >+ /* */ >+ }, >+ { /* 4102 */ >+ 496, >+ /* VMOVDQA32Z256mr */ >+ }, >+ { /* 4103 */ >+ 515, >+ /* VMOVDQA32Z256mrk */ >+ }, >+ { /* 4104 */ >+ 498, >+ /* VMOVDQA32Z256rm */ >+ }, >+ { /* 4105 */ >+ 516, >+ /* VMOVDQA32Z256rmk */ >+ }, >+ { /* 4106 */ >+ 517, >+ /* VMOVDQA32Z256rmkz */ >+ }, >+ { /* 4107 */ >+ 501, >+ /* VMOVDQA32Z256rr */ >+ }, >+ { /* 4108 */ >+ 0, >+ /* */ >+ }, >+ { /* 4109 */ >+ 518, >+ /* VMOVDQA32Z256rrk */ >+ }, >+ { /* 4110 */ >+ 0, >+ /* */ >+ }, >+ { /* 4111 */ >+ 519, >+ /* VMOVDQA32Z256rrkz */ >+ }, >+ { /* 4112 */ >+ 0, >+ /* */ >+ }, >+ { /* 4113 */ >+ 504, >+ /* VMOVDQA32Zmr */ >+ }, >+ { /* 4114 */ >+ 520, >+ /* VMOVDQA32Zmrk */ >+ }, >+ { /* 4115 */ >+ 378, >+ /* VMOVDQA32Zrm */ >+ }, >+ { /* 4116 */ >+ 521, >+ /* VMOVDQA32Zrmk */ >+ }, >+ { /* 4117 */ >+ 522, >+ /* VMOVDQA32Zrmkz */ >+ }, >+ { /* 4118 */ >+ 379, >+ /* VMOVDQA32Zrr */ >+ }, >+ { /* 4119 */ >+ 0, >+ /* */ >+ }, >+ { /* 4120 */ >+ 523, >+ /* VMOVDQA32Zrrk */ >+ }, >+ { /* 4121 */ >+ 0, >+ /* */ >+ }, >+ { /* 4122 */ >+ 524, >+ /* VMOVDQA32Zrrkz */ >+ }, >+ { /* 4123 */ >+ 0, >+ /* */ >+ }, >+ { /* 4124 */ >+ 488, >+ /* VMOVDQA64Z128mr */ >+ }, >+ { /* 4125 */ >+ 489, >+ /* VMOVDQA64Z128mrk */ >+ }, >+ { /* 4126 */ >+ 490, >+ /* VMOVDQA64Z128rm */ >+ }, >+ { /* 4127 */ >+ 491, >+ /* VMOVDQA64Z128rmk */ >+ }, >+ { /* 4128 */ >+ 492, >+ /* VMOVDQA64Z128rmkz */ >+ }, >+ { /* 4129 */ >+ 493, >+ /* VMOVDQA64Z128rr */ >+ }, >+ { /* 4130 */ >+ 0, >+ /* */ >+ }, >+ { /* 4131 */ >+ 494, >+ /* VMOVDQA64Z128rrk */ >+ }, >+ { /* 4132 */ >+ 0, >+ /* */ >+ }, >+ { /* 4133 */ >+ 495, >+ /* VMOVDQA64Z128rrkz */ >+ }, >+ { /* 4134 */ >+ 0, >+ /* */ >+ }, >+ { /* 4135 */ >+ 496, >+ /* VMOVDQA64Z256mr */ >+ }, >+ { /* 4136 */ >+ 497, >+ /* VMOVDQA64Z256mrk */ >+ }, >+ { /* 4137 */ >+ 498, >+ /* VMOVDQA64Z256rm */ >+ }, >+ { /* 4138 */ >+ 499, >+ /* VMOVDQA64Z256rmk */ >+ }, >+ { /* 4139 */ >+ 500, >+ /* VMOVDQA64Z256rmkz */ >+ }, >+ { /* 4140 */ >+ 501, >+ /* VMOVDQA64Z256rr */ >+ }, >+ { /* 4141 */ >+ 0, >+ /* */ >+ }, >+ { /* 4142 */ >+ 502, >+ /* VMOVDQA64Z256rrk */ >+ }, >+ { /* 4143 */ >+ 0, >+ /* */ >+ }, >+ { /* 4144 */ >+ 503, >+ /* VMOVDQA64Z256rrkz */ >+ }, >+ { /* 4145 */ >+ 0, >+ /* */ >+ }, >+ { /* 4146 */ >+ 504, >+ /* VMOVDQA64Zmr */ >+ }, >+ { /* 4147 */ >+ 505, >+ /* VMOVDQA64Zmrk */ >+ }, >+ { /* 4148 */ >+ 378, >+ /* VMOVDQA64Zrm */ >+ }, >+ { /* 4149 */ >+ 506, >+ /* VMOVDQA64Zrmk */ >+ }, >+ { /* 4150 */ >+ 507, >+ /* VMOVDQA64Zrmkz */ >+ }, >+ { /* 4151 */ >+ 379, >+ /* VMOVDQA64Zrr */ >+ }, >+ { /* 4152 */ >+ 0, >+ /* */ >+ }, >+ { /* 4153 */ >+ 508, >+ /* VMOVDQA64Zrrk */ >+ }, >+ { /* 4154 */ >+ 0, >+ /* */ >+ }, >+ { /* 4155 */ >+ 509, >+ /* VMOVDQA64Zrrkz */ >+ }, >+ { /* 4156 */ >+ 0, >+ /* */ >+ }, >+ { /* 4157 */ >+ 486, >+ /* VMOVDQAYmr */ >+ }, >+ { /* 4158 */ >+ 376, >+ /* VMOVDQAYrm */ >+ }, >+ { /* 4159 */ >+ 377, >+ /* VMOVDQAYrr */ >+ }, >+ { /* 4160 */ >+ 487, >+ /* VMOVDQAYrr_REV */ >+ }, >+ { /* 4161 */ >+ 243, >+ /* VMOVDQAmr */ >+ }, >+ { /* 4162 */ >+ 44, >+ /* VMOVDQArm */ >+ }, >+ { /* 4163 */ >+ 45, >+ /* VMOVDQArr */ >+ }, >+ { /* 4164 */ >+ 244, >+ /* VMOVDQArr_REV */ >+ }, >+ { /* 4165 */ >+ 488, >+ /* VMOVDQU16Z128mr */ >+ }, >+ { /* 4166 */ >+ 527, >+ /* VMOVDQU16Z128mrk */ >+ }, >+ { /* 4167 */ >+ 490, >+ /* VMOVDQU16Z128rm */ >+ }, >+ { /* 4168 */ >+ 528, >+ /* VMOVDQU16Z128rmk */ >+ }, >+ { /* 4169 */ >+ 529, >+ /* VMOVDQU16Z128rmkz */ >+ }, >+ { /* 4170 */ >+ 493, >+ /* VMOVDQU16Z128rr */ >+ }, >+ { /* 4171 */ >+ 0, >+ /* */ >+ }, >+ { /* 4172 */ >+ 530, >+ /* VMOVDQU16Z128rrk */ >+ }, >+ { /* 4173 */ >+ 0, >+ /* */ >+ }, >+ { /* 4174 */ >+ 531, >+ /* VMOVDQU16Z128rrkz */ >+ }, >+ { /* 4175 */ >+ 0, >+ /* */ >+ }, >+ { /* 4176 */ >+ 496, >+ /* VMOVDQU16Z256mr */ >+ }, >+ { /* 4177 */ >+ 532, >+ /* VMOVDQU16Z256mrk */ >+ }, >+ { /* 4178 */ >+ 498, >+ /* VMOVDQU16Z256rm */ >+ }, >+ { /* 4179 */ >+ 533, >+ /* VMOVDQU16Z256rmk */ >+ }, >+ { /* 4180 */ >+ 534, >+ /* VMOVDQU16Z256rmkz */ >+ }, >+ { /* 4181 */ >+ 501, >+ /* VMOVDQU16Z256rr */ >+ }, >+ { /* 4182 */ >+ 0, >+ /* */ >+ }, >+ { /* 4183 */ >+ 535, >+ /* VMOVDQU16Z256rrk */ >+ }, >+ { /* 4184 */ >+ 0, >+ /* */ >+ }, >+ { /* 4185 */ >+ 536, >+ /* VMOVDQU16Z256rrkz */ >+ }, >+ { /* 4186 */ >+ 0, >+ /* */ >+ }, >+ { /* 4187 */ >+ 504, >+ /* VMOVDQU16Zmr */ >+ }, >+ { /* 4188 */ >+ 537, >+ /* VMOVDQU16Zmrk */ >+ }, >+ { /* 4189 */ >+ 378, >+ /* VMOVDQU16Zrm */ >+ }, >+ { /* 4190 */ >+ 538, >+ /* VMOVDQU16Zrmk */ >+ }, >+ { /* 4191 */ >+ 539, >+ /* VMOVDQU16Zrmkz */ >+ }, >+ { /* 4192 */ >+ 379, >+ /* VMOVDQU16Zrr */ >+ }, >+ { /* 4193 */ >+ 0, >+ /* */ >+ }, >+ { /* 4194 */ >+ 540, >+ /* VMOVDQU16Zrrk */ >+ }, >+ { /* 4195 */ >+ 0, >+ /* */ >+ }, >+ { /* 4196 */ >+ 541, >+ /* VMOVDQU16Zrrkz */ >+ }, >+ { /* 4197 */ >+ 0, >+ /* */ >+ }, >+ { /* 4198 */ >+ 488, >+ /* VMOVDQU32Z128mr */ >+ }, >+ { /* 4199 */ >+ 510, >+ /* VMOVDQU32Z128mrk */ >+ }, >+ { /* 4200 */ >+ 490, >+ /* VMOVDQU32Z128rm */ >+ }, >+ { /* 4201 */ >+ 511, >+ /* VMOVDQU32Z128rmk */ >+ }, >+ { /* 4202 */ >+ 512, >+ /* VMOVDQU32Z128rmkz */ >+ }, >+ { /* 4203 */ >+ 493, >+ /* VMOVDQU32Z128rr */ >+ }, >+ { /* 4204 */ >+ 0, >+ /* */ >+ }, >+ { /* 4205 */ >+ 513, >+ /* VMOVDQU32Z128rrk */ >+ }, >+ { /* 4206 */ >+ 0, >+ /* */ >+ }, >+ { /* 4207 */ >+ 514, >+ /* VMOVDQU32Z128rrkz */ >+ }, >+ { /* 4208 */ >+ 0, >+ /* */ >+ }, >+ { /* 4209 */ >+ 496, >+ /* VMOVDQU32Z256mr */ >+ }, >+ { /* 4210 */ >+ 515, >+ /* VMOVDQU32Z256mrk */ >+ }, >+ { /* 4211 */ >+ 498, >+ /* VMOVDQU32Z256rm */ >+ }, >+ { /* 4212 */ >+ 516, >+ /* VMOVDQU32Z256rmk */ >+ }, >+ { /* 4213 */ >+ 517, >+ /* VMOVDQU32Z256rmkz */ >+ }, >+ { /* 4214 */ >+ 501, >+ /* VMOVDQU32Z256rr */ >+ }, >+ { /* 4215 */ >+ 0, >+ /* */ >+ }, >+ { /* 4216 */ >+ 518, >+ /* VMOVDQU32Z256rrk */ >+ }, >+ { /* 4217 */ >+ 0, >+ /* */ >+ }, >+ { /* 4218 */ >+ 519, >+ /* VMOVDQU32Z256rrkz */ >+ }, >+ { /* 4219 */ >+ 0, >+ /* */ >+ }, >+ { /* 4220 */ >+ 504, >+ /* VMOVDQU32Zmr */ >+ }, >+ { /* 4221 */ >+ 520, >+ /* VMOVDQU32Zmrk */ >+ }, >+ { /* 4222 */ >+ 378, >+ /* VMOVDQU32Zrm */ >+ }, >+ { /* 4223 */ >+ 521, >+ /* VMOVDQU32Zrmk */ >+ }, >+ { /* 4224 */ >+ 522, >+ /* VMOVDQU32Zrmkz */ >+ }, >+ { /* 4225 */ >+ 379, >+ /* VMOVDQU32Zrr */ >+ }, >+ { /* 4226 */ >+ 0, >+ /* */ >+ }, >+ { /* 4227 */ >+ 523, >+ /* VMOVDQU32Zrrk */ >+ }, >+ { /* 4228 */ >+ 0, >+ /* */ >+ }, >+ { /* 4229 */ >+ 524, >+ /* VMOVDQU32Zrrkz */ >+ }, >+ { /* 4230 */ >+ 0, >+ /* */ >+ }, >+ { /* 4231 */ >+ 488, >+ /* VMOVDQU64Z128mr */ >+ }, >+ { /* 4232 */ >+ 489, >+ /* VMOVDQU64Z128mrk */ >+ }, >+ { /* 4233 */ >+ 490, >+ /* VMOVDQU64Z128rm */ >+ }, >+ { /* 4234 */ >+ 491, >+ /* VMOVDQU64Z128rmk */ >+ }, >+ { /* 4235 */ >+ 492, >+ /* VMOVDQU64Z128rmkz */ >+ }, >+ { /* 4236 */ >+ 493, >+ /* VMOVDQU64Z128rr */ >+ }, >+ { /* 4237 */ >+ 0, >+ /* */ >+ }, >+ { /* 4238 */ >+ 494, >+ /* VMOVDQU64Z128rrk */ >+ }, >+ { /* 4239 */ >+ 0, >+ /* */ >+ }, >+ { /* 4240 */ >+ 495, >+ /* VMOVDQU64Z128rrkz */ >+ }, >+ { /* 4241 */ >+ 0, >+ /* */ >+ }, >+ { /* 4242 */ >+ 496, >+ /* VMOVDQU64Z256mr */ >+ }, >+ { /* 4243 */ >+ 497, >+ /* VMOVDQU64Z256mrk */ >+ }, >+ { /* 4244 */ >+ 498, >+ /* VMOVDQU64Z256rm */ >+ }, >+ { /* 4245 */ >+ 499, >+ /* VMOVDQU64Z256rmk */ >+ }, >+ { /* 4246 */ >+ 500, >+ /* VMOVDQU64Z256rmkz */ >+ }, >+ { /* 4247 */ >+ 501, >+ /* VMOVDQU64Z256rr */ >+ }, >+ { /* 4248 */ >+ 0, >+ /* */ >+ }, >+ { /* 4249 */ >+ 502, >+ /* VMOVDQU64Z256rrk */ >+ }, >+ { /* 4250 */ >+ 0, >+ /* */ >+ }, >+ { /* 4251 */ >+ 503, >+ /* VMOVDQU64Z256rrkz */ >+ }, >+ { /* 4252 */ >+ 0, >+ /* */ >+ }, >+ { /* 4253 */ >+ 504, >+ /* VMOVDQU64Zmr */ >+ }, >+ { /* 4254 */ >+ 505, >+ /* VMOVDQU64Zmrk */ >+ }, >+ { /* 4255 */ >+ 378, >+ /* VMOVDQU64Zrm */ >+ }, >+ { /* 4256 */ >+ 506, >+ /* VMOVDQU64Zrmk */ >+ }, >+ { /* 4257 */ >+ 507, >+ /* VMOVDQU64Zrmkz */ >+ }, >+ { /* 4258 */ >+ 379, >+ /* VMOVDQU64Zrr */ >+ }, >+ { /* 4259 */ >+ 0, >+ /* */ >+ }, >+ { /* 4260 */ >+ 508, >+ /* VMOVDQU64Zrrk */ >+ }, >+ { /* 4261 */ >+ 0, >+ /* */ >+ }, >+ { /* 4262 */ >+ 509, >+ /* VMOVDQU64Zrrkz */ >+ }, >+ { /* 4263 */ >+ 0, >+ /* */ >+ }, >+ { /* 4264 */ >+ 488, >+ /* VMOVDQU8Z128mr */ >+ }, >+ { /* 4265 */ >+ 542, >+ /* VMOVDQU8Z128mrk */ >+ }, >+ { /* 4266 */ >+ 490, >+ /* VMOVDQU8Z128rm */ >+ }, >+ { /* 4267 */ >+ 543, >+ /* VMOVDQU8Z128rmk */ >+ }, >+ { /* 4268 */ >+ 544, >+ /* VMOVDQU8Z128rmkz */ >+ }, >+ { /* 4269 */ >+ 493, >+ /* VMOVDQU8Z128rr */ >+ }, >+ { /* 4270 */ >+ 0, >+ /* */ >+ }, >+ { /* 4271 */ >+ 545, >+ /* VMOVDQU8Z128rrk */ >+ }, >+ { /* 4272 */ >+ 0, >+ /* */ >+ }, >+ { /* 4273 */ >+ 546, >+ /* VMOVDQU8Z128rrkz */ >+ }, >+ { /* 4274 */ >+ 0, >+ /* */ >+ }, >+ { /* 4275 */ >+ 496, >+ /* VMOVDQU8Z256mr */ >+ }, >+ { /* 4276 */ >+ 547, >+ /* VMOVDQU8Z256mrk */ >+ }, >+ { /* 4277 */ >+ 498, >+ /* VMOVDQU8Z256rm */ >+ }, >+ { /* 4278 */ >+ 548, >+ /* VMOVDQU8Z256rmk */ >+ }, >+ { /* 4279 */ >+ 549, >+ /* VMOVDQU8Z256rmkz */ >+ }, >+ { /* 4280 */ >+ 501, >+ /* VMOVDQU8Z256rr */ >+ }, >+ { /* 4281 */ >+ 0, >+ /* */ >+ }, >+ { /* 4282 */ >+ 550, >+ /* VMOVDQU8Z256rrk */ >+ }, >+ { /* 4283 */ >+ 0, >+ /* */ >+ }, >+ { /* 4284 */ >+ 551, >+ /* VMOVDQU8Z256rrkz */ >+ }, >+ { /* 4285 */ >+ 0, >+ /* */ >+ }, >+ { /* 4286 */ >+ 504, >+ /* VMOVDQU8Zmr */ >+ }, >+ { /* 4287 */ >+ 552, >+ /* VMOVDQU8Zmrk */ >+ }, >+ { /* 4288 */ >+ 378, >+ /* VMOVDQU8Zrm */ >+ }, >+ { /* 4289 */ >+ 553, >+ /* VMOVDQU8Zrmk */ >+ }, >+ { /* 4290 */ >+ 554, >+ /* VMOVDQU8Zrmkz */ >+ }, >+ { /* 4291 */ >+ 379, >+ /* VMOVDQU8Zrr */ >+ }, >+ { /* 4292 */ >+ 0, >+ /* */ >+ }, >+ { /* 4293 */ >+ 555, >+ /* VMOVDQU8Zrrk */ >+ }, >+ { /* 4294 */ >+ 0, >+ /* */ >+ }, >+ { /* 4295 */ >+ 556, >+ /* VMOVDQU8Zrrkz */ >+ }, >+ { /* 4296 */ >+ 0, >+ /* */ >+ }, >+ { /* 4297 */ >+ 486, >+ /* VMOVDQUYmr */ >+ }, >+ { /* 4298 */ >+ 376, >+ /* VMOVDQUYrm */ >+ }, >+ { /* 4299 */ >+ 377, >+ /* VMOVDQUYrr */ >+ }, >+ { /* 4300 */ >+ 487, >+ /* VMOVDQUYrr_REV */ >+ }, >+ { /* 4301 */ >+ 243, >+ /* VMOVDQUmr */ >+ }, >+ { /* 4302 */ >+ 44, >+ /* VMOVDQUrm */ >+ }, >+ { /* 4303 */ >+ 45, >+ /* VMOVDQUrr */ >+ }, >+ { /* 4304 */ >+ 244, >+ /* VMOVDQUrr_REV */ >+ }, >+ { /* 4305 */ >+ 557, >+ /* VMOVHLPSZrr */ >+ }, >+ { /* 4306 */ >+ 313, >+ /* VMOVHLPSrr */ >+ }, >+ { /* 4307 */ >+ 246, >+ /* VMOVHPDmr */ >+ }, >+ { /* 4308 */ >+ 558, >+ /* VMOVHPDrm */ >+ }, >+ { /* 4309 */ >+ 246, >+ /* VMOVHPSmr */ >+ }, >+ { /* 4310 */ >+ 558, >+ /* VMOVHPSrm */ >+ }, >+ { /* 4311 */ >+ 557, >+ /* VMOVLHPSZrr */ >+ }, >+ { /* 4312 */ >+ 313, >+ /* VMOVLHPSrr */ >+ }, >+ { /* 4313 */ >+ 246, >+ /* VMOVLPDmr */ >+ }, >+ { /* 4314 */ >+ 558, >+ /* VMOVLPDrm */ >+ }, >+ { /* 4315 */ >+ 246, >+ /* VMOVLPSmr */ >+ }, >+ { /* 4316 */ >+ 558, >+ /* VMOVLPSrm */ >+ }, >+ { /* 4317 */ >+ 559, >+ /* VMOVMSKPDYrr */ >+ }, >+ { /* 4318 */ >+ 110, >+ /* VMOVMSKPDrr */ >+ }, >+ { /* 4319 */ >+ 559, >+ /* VMOVMSKPSYrr */ >+ }, >+ { /* 4320 */ >+ 110, >+ /* VMOVMSKPSrr */ >+ }, >+ { /* 4321 */ >+ 376, >+ /* VMOVNTDQAYrm */ >+ }, >+ { /* 4322 */ >+ 490, >+ /* VMOVNTDQAZ128rm */ >+ }, >+ { /* 4323 */ >+ 498, >+ /* VMOVNTDQAZ256rm */ >+ }, >+ { /* 4324 */ >+ 378, >+ /* VMOVNTDQAZrm */ >+ }, >+ { /* 4325 */ >+ 44, >+ /* VMOVNTDQArm */ >+ }, >+ { /* 4326 */ >+ 486, >+ /* VMOVNTDQYmr */ >+ }, >+ { /* 4327 */ >+ 488, >+ /* VMOVNTDQZ128mr */ >+ }, >+ { /* 4328 */ >+ 496, >+ /* VMOVNTDQZ256mr */ >+ }, >+ { /* 4329 */ >+ 504, >+ /* VMOVNTDQZmr */ >+ }, >+ { /* 4330 */ >+ 243, >+ /* VMOVNTDQmr */ >+ }, >+ { /* 4331 */ >+ 486, >+ /* VMOVNTPDYmr */ >+ }, >+ { /* 4332 */ >+ 488, >+ /* VMOVNTPDZ128mr */ >+ }, >+ { /* 4333 */ >+ 496, >+ /* VMOVNTPDZ256mr */ >+ }, >+ { /* 4334 */ >+ 504, >+ /* VMOVNTPDZmr */ >+ }, >+ { /* 4335 */ >+ 243, >+ /* VMOVNTPDmr */ >+ }, >+ { /* 4336 */ >+ 486, >+ /* VMOVNTPSYmr */ >+ }, >+ { /* 4337 */ >+ 488, >+ /* VMOVNTPSZ128mr */ >+ }, >+ { /* 4338 */ >+ 496, >+ /* VMOVNTPSZ256mr */ >+ }, >+ { /* 4339 */ >+ 504, >+ /* VMOVNTPSZmr */ >+ }, >+ { /* 4340 */ >+ 243, >+ /* VMOVNTPSmr */ >+ }, >+ { /* 4341 */ >+ 560, >+ /* VMOVPDI2DIZmr */ >+ }, >+ { /* 4342 */ >+ 561, >+ /* VMOVPDI2DIZrr */ >+ }, >+ { /* 4343 */ >+ 250, >+ /* VMOVPDI2DImr */ >+ }, >+ { /* 4344 */ >+ 251, >+ /* VMOVPDI2DIrr */ >+ }, >+ { /* 4345 */ >+ 250, >+ /* VMOVPQI2QImr */ >+ }, >+ { /* 4346 */ >+ 244, >+ /* VMOVPQI2QIrr */ >+ }, >+ { /* 4347 */ >+ 562, >+ /* VMOVPQIto64Zmr */ >+ }, >+ { /* 4348 */ >+ 563, >+ /* VMOVPQIto64Zrr */ >+ }, >+ { /* 4349 */ >+ 252, >+ /* VMOVPQIto64rr */ >+ }, >+ { /* 4350 */ >+ 564, >+ /* VMOVQI2PQIZrm */ >+ }, >+ { /* 4351 */ >+ 105, >+ /* VMOVQI2PQIrm */ >+ }, >+ { /* 4352 */ >+ 565, >+ /* VMOVSDZmr */ >+ }, >+ { /* 4353 */ >+ 566, >+ /* VMOVSDZrm */ >+ }, >+ { /* 4354 */ >+ 567, >+ /* VMOVSDZrr */ >+ }, >+ { /* 4355 */ >+ 568, >+ /* VMOVSDZrr_REV */ >+ }, >+ { /* 4356 */ >+ 569, >+ /* VMOVSDZrrk */ >+ }, >+ { /* 4357 */ >+ 253, >+ /* VMOVSDmr */ >+ }, >+ { /* 4358 */ >+ 254, >+ /* VMOVSDrm */ >+ }, >+ { /* 4359 */ >+ 570, >+ /* VMOVSDrr */ >+ }, >+ { /* 4360 */ >+ 571, >+ /* VMOVSDrr_REV */ >+ }, >+ { /* 4361 */ >+ 572, >+ /* VMOVSDto64Zmr */ >+ }, >+ { /* 4362 */ >+ 0, >+ /* */ >+ }, >+ { /* 4363 */ >+ 0, >+ /* */ >+ }, >+ { /* 4364 */ >+ 0, >+ /* */ >+ }, >+ { /* 4365 */ >+ 376, >+ /* VMOVSHDUPYrm */ >+ }, >+ { /* 4366 */ >+ 377, >+ /* VMOVSHDUPYrr */ >+ }, >+ { /* 4367 */ >+ 378, >+ /* VMOVSHDUPZrm */ >+ }, >+ { /* 4368 */ >+ 379, >+ /* VMOVSHDUPZrr */ >+ }, >+ { /* 4369 */ >+ 44, >+ /* VMOVSHDUPrm */ >+ }, >+ { /* 4370 */ >+ 45, >+ /* VMOVSHDUPrr */ >+ }, >+ { /* 4371 */ >+ 376, >+ /* VMOVSLDUPYrm */ >+ }, >+ { /* 4372 */ >+ 377, >+ /* VMOVSLDUPYrr */ >+ }, >+ { /* 4373 */ >+ 378, >+ /* VMOVSLDUPZrm */ >+ }, >+ { /* 4374 */ >+ 379, >+ /* VMOVSLDUPZrr */ >+ }, >+ { /* 4375 */ >+ 44, >+ /* VMOVSLDUPrm */ >+ }, >+ { /* 4376 */ >+ 45, >+ /* VMOVSLDUPrr */ >+ }, >+ { /* 4377 */ >+ 0, >+ /* */ >+ }, >+ { /* 4378 */ >+ 0, >+ /* */ >+ }, >+ { /* 4379 */ >+ 0, >+ /* */ >+ }, >+ { /* 4380 */ >+ 0, >+ /* */ >+ }, >+ { /* 4381 */ >+ 573, >+ /* VMOVSSZmr */ >+ }, >+ { /* 4382 */ >+ 574, >+ /* VMOVSSZrm */ >+ }, >+ { /* 4383 */ >+ 575, >+ /* VMOVSSZrr */ >+ }, >+ { /* 4384 */ >+ 576, >+ /* VMOVSSZrr_REV */ >+ }, >+ { /* 4385 */ >+ 577, >+ /* VMOVSSZrrk */ >+ }, >+ { /* 4386 */ >+ 257, >+ /* VMOVSSmr */ >+ }, >+ { /* 4387 */ >+ 258, >+ /* VMOVSSrm */ >+ }, >+ { /* 4388 */ >+ 578, >+ /* VMOVSSrr */ >+ }, >+ { /* 4389 */ >+ 579, >+ /* VMOVSSrr_REV */ >+ }, >+ { /* 4390 */ >+ 486, >+ /* VMOVUPDYmr */ >+ }, >+ { /* 4391 */ >+ 376, >+ /* VMOVUPDYrm */ >+ }, >+ { /* 4392 */ >+ 377, >+ /* VMOVUPDYrr */ >+ }, >+ { /* 4393 */ >+ 487, >+ /* VMOVUPDYrr_REV */ >+ }, >+ { /* 4394 */ >+ 488, >+ /* VMOVUPDZ128mr */ >+ }, >+ { /* 4395 */ >+ 489, >+ /* VMOVUPDZ128mrk */ >+ }, >+ { /* 4396 */ >+ 490, >+ /* VMOVUPDZ128rm */ >+ }, >+ { /* 4397 */ >+ 491, >+ /* VMOVUPDZ128rmk */ >+ }, >+ { /* 4398 */ >+ 492, >+ /* VMOVUPDZ128rmkz */ >+ }, >+ { /* 4399 */ >+ 493, >+ /* VMOVUPDZ128rr */ >+ }, >+ { /* 4400 */ >+ 0, >+ /* */ >+ }, >+ { /* 4401 */ >+ 494, >+ /* VMOVUPDZ128rrk */ >+ }, >+ { /* 4402 */ >+ 0, >+ /* */ >+ }, >+ { /* 4403 */ >+ 495, >+ /* VMOVUPDZ128rrkz */ >+ }, >+ { /* 4404 */ >+ 0, >+ /* */ >+ }, >+ { /* 4405 */ >+ 496, >+ /* VMOVUPDZ256mr */ >+ }, >+ { /* 4406 */ >+ 497, >+ /* VMOVUPDZ256mrk */ >+ }, >+ { /* 4407 */ >+ 498, >+ /* VMOVUPDZ256rm */ >+ }, >+ { /* 4408 */ >+ 499, >+ /* VMOVUPDZ256rmk */ >+ }, >+ { /* 4409 */ >+ 500, >+ /* VMOVUPDZ256rmkz */ >+ }, >+ { /* 4410 */ >+ 501, >+ /* VMOVUPDZ256rr */ >+ }, >+ { /* 4411 */ >+ 0, >+ /* */ >+ }, >+ { /* 4412 */ >+ 502, >+ /* VMOVUPDZ256rrk */ >+ }, >+ { /* 4413 */ >+ 0, >+ /* */ >+ }, >+ { /* 4414 */ >+ 503, >+ /* VMOVUPDZ256rrkz */ >+ }, >+ { /* 4415 */ >+ 0, >+ /* */ >+ }, >+ { /* 4416 */ >+ 504, >+ /* VMOVUPDZmr */ >+ }, >+ { /* 4417 */ >+ 505, >+ /* VMOVUPDZmrk */ >+ }, >+ { /* 4418 */ >+ 378, >+ /* VMOVUPDZrm */ >+ }, >+ { /* 4419 */ >+ 506, >+ /* VMOVUPDZrmk */ >+ }, >+ { /* 4420 */ >+ 507, >+ /* VMOVUPDZrmkz */ >+ }, >+ { /* 4421 */ >+ 379, >+ /* VMOVUPDZrr */ >+ }, >+ { /* 4422 */ >+ 0, >+ /* */ >+ }, >+ { /* 4423 */ >+ 508, >+ /* VMOVUPDZrrk */ >+ }, >+ { /* 4424 */ >+ 0, >+ /* */ >+ }, >+ { /* 4425 */ >+ 509, >+ /* VMOVUPDZrrkz */ >+ }, >+ { /* 4426 */ >+ 0, >+ /* */ >+ }, >+ { /* 4427 */ >+ 243, >+ /* VMOVUPDmr */ >+ }, >+ { /* 4428 */ >+ 44, >+ /* VMOVUPDrm */ >+ }, >+ { /* 4429 */ >+ 45, >+ /* VMOVUPDrr */ >+ }, >+ { /* 4430 */ >+ 244, >+ /* VMOVUPDrr_REV */ >+ }, >+ { /* 4431 */ >+ 486, >+ /* VMOVUPSYmr */ >+ }, >+ { /* 4432 */ >+ 376, >+ /* VMOVUPSYrm */ >+ }, >+ { /* 4433 */ >+ 377, >+ /* VMOVUPSYrr */ >+ }, >+ { /* 4434 */ >+ 487, >+ /* VMOVUPSYrr_REV */ >+ }, >+ { /* 4435 */ >+ 488, >+ /* VMOVUPSZ128mr */ >+ }, >+ { /* 4436 */ >+ 510, >+ /* VMOVUPSZ128mrk */ >+ }, >+ { /* 4437 */ >+ 490, >+ /* VMOVUPSZ128rm */ >+ }, >+ { /* 4438 */ >+ 511, >+ /* VMOVUPSZ128rmk */ >+ }, >+ { /* 4439 */ >+ 512, >+ /* VMOVUPSZ128rmkz */ >+ }, >+ { /* 4440 */ >+ 493, >+ /* VMOVUPSZ128rr */ >+ }, >+ { /* 4441 */ >+ 0, >+ /* */ >+ }, >+ { /* 4442 */ >+ 513, >+ /* VMOVUPSZ128rrk */ >+ }, >+ { /* 4443 */ >+ 0, >+ /* */ >+ }, >+ { /* 4444 */ >+ 514, >+ /* VMOVUPSZ128rrkz */ >+ }, >+ { /* 4445 */ >+ 0, >+ /* */ >+ }, >+ { /* 4446 */ >+ 496, >+ /* VMOVUPSZ256mr */ >+ }, >+ { /* 4447 */ >+ 515, >+ /* VMOVUPSZ256mrk */ >+ }, >+ { /* 4448 */ >+ 498, >+ /* VMOVUPSZ256rm */ >+ }, >+ { /* 4449 */ >+ 516, >+ /* VMOVUPSZ256rmk */ >+ }, >+ { /* 4450 */ >+ 517, >+ /* VMOVUPSZ256rmkz */ >+ }, >+ { /* 4451 */ >+ 501, >+ /* VMOVUPSZ256rr */ >+ }, >+ { /* 4452 */ >+ 0, >+ /* */ >+ }, >+ { /* 4453 */ >+ 518, >+ /* VMOVUPSZ256rrk */ >+ }, >+ { /* 4454 */ >+ 0, >+ /* */ >+ }, >+ { /* 4455 */ >+ 519, >+ /* VMOVUPSZ256rrkz */ >+ }, >+ { /* 4456 */ >+ 0, >+ /* */ >+ }, >+ { /* 4457 */ >+ 504, >+ /* VMOVUPSZmr */ >+ }, >+ { /* 4458 */ >+ 520, >+ /* VMOVUPSZmrk */ >+ }, >+ { /* 4459 */ >+ 378, >+ /* VMOVUPSZrm */ >+ }, >+ { /* 4460 */ >+ 521, >+ /* VMOVUPSZrmk */ >+ }, >+ { /* 4461 */ >+ 522, >+ /* VMOVUPSZrmkz */ >+ }, >+ { /* 4462 */ >+ 379, >+ /* VMOVUPSZrr */ >+ }, >+ { /* 4463 */ >+ 0, >+ /* */ >+ }, >+ { /* 4464 */ >+ 523, >+ /* VMOVUPSZrrk */ >+ }, >+ { /* 4465 */ >+ 0, >+ /* */ >+ }, >+ { /* 4466 */ >+ 524, >+ /* VMOVUPSZrrkz */ >+ }, >+ { /* 4467 */ >+ 0, >+ /* */ >+ }, >+ { /* 4468 */ >+ 243, >+ /* VMOVUPSmr */ >+ }, >+ { /* 4469 */ >+ 44, >+ /* VMOVUPSrm */ >+ }, >+ { /* 4470 */ >+ 45, >+ /* VMOVUPSrr */ >+ }, >+ { /* 4471 */ >+ 244, >+ /* VMOVUPSrr_REV */ >+ }, >+ { /* 4472 */ >+ 371, >+ /* VMOVZPQILo2PQIZrm */ >+ }, >+ { /* 4473 */ >+ 493, >+ /* VMOVZPQILo2PQIZrr */ >+ }, >+ { /* 4474 */ >+ 0, >+ /* */ >+ }, >+ { /* 4475 */ >+ 45, >+ /* VMOVZPQILo2PQIrr */ >+ }, >+ { /* 4476 */ >+ 0, >+ /* */ >+ }, >+ { /* 4477 */ >+ 0, >+ /* */ >+ }, >+ { /* 4478 */ >+ 332, >+ /* VMPSADBWYrmi */ >+ }, >+ { /* 4479 */ >+ 333, >+ /* VMPSADBWYrri */ >+ }, >+ { /* 4480 */ >+ 334, >+ /* VMPSADBWrmi */ >+ }, >+ { /* 4481 */ >+ 335, >+ /* VMPSADBWrri */ >+ }, >+ { /* 4482 */ >+ 38, >+ /* VMPTRLDm */ >+ }, >+ { /* 4483 */ >+ 38, >+ /* VMPTRSTm */ >+ }, >+ { /* 4484 */ >+ 248, >+ /* VMREAD32rm */ >+ }, >+ { /* 4485 */ >+ 580, >+ /* VMREAD32rr */ >+ }, >+ { /* 4486 */ >+ 16, >+ /* VMREAD64rm */ >+ }, >+ { /* 4487 */ >+ 76, >+ /* VMREAD64rr */ >+ }, >+ { /* 4488 */ >+ 0, >+ /* VMRESUME */ >+ }, >+ { /* 4489 */ >+ 0, >+ /* VMRUN32 */ >+ }, >+ { /* 4490 */ >+ 0, >+ /* VMRUN64 */ >+ }, >+ { /* 4491 */ >+ 0, >+ /* VMSAVE32 */ >+ }, >+ { /* 4492 */ >+ 0, >+ /* VMSAVE64 */ >+ }, >+ { /* 4493 */ >+ 304, >+ /* VMULPDYrm */ >+ }, >+ { /* 4494 */ >+ 305, >+ /* VMULPDYrr */ >+ }, >+ { /* 4495 */ >+ 306, >+ /* VMULPDZrm */ >+ }, >+ { /* 4496 */ >+ 307, >+ /* VMULPDZrmb */ >+ }, >+ { /* 4497 */ >+ 308, >+ /* VMULPDZrmbk */ >+ }, >+ { /* 4498 */ >+ 308, >+ /* VMULPDZrmbkz */ >+ }, >+ { /* 4499 */ >+ 309, >+ /* VMULPDZrmk */ >+ }, >+ { /* 4500 */ >+ 309, >+ /* VMULPDZrmkz */ >+ }, >+ { /* 4501 */ >+ 310, >+ /* VMULPDZrr */ >+ }, >+ { /* 4502 */ >+ 311, >+ /* VMULPDZrrk */ >+ }, >+ { /* 4503 */ >+ 311, >+ /* VMULPDZrrkz */ >+ }, >+ { /* 4504 */ >+ 312, >+ /* VMULPDrm */ >+ }, >+ { /* 4505 */ >+ 313, >+ /* VMULPDrr */ >+ }, >+ { /* 4506 */ >+ 304, >+ /* VMULPSYrm */ >+ }, >+ { /* 4507 */ >+ 305, >+ /* VMULPSYrr */ >+ }, >+ { /* 4508 */ >+ 306, >+ /* VMULPSZrm */ >+ }, >+ { /* 4509 */ >+ 314, >+ /* VMULPSZrmb */ >+ }, >+ { /* 4510 */ >+ 315, >+ /* VMULPSZrmbk */ >+ }, >+ { /* 4511 */ >+ 315, >+ /* VMULPSZrmbkz */ >+ }, >+ { /* 4512 */ >+ 316, >+ /* VMULPSZrmk */ >+ }, >+ { /* 4513 */ >+ 316, >+ /* VMULPSZrmkz */ >+ }, >+ { /* 4514 */ >+ 310, >+ /* VMULPSZrr */ >+ }, >+ { /* 4515 */ >+ 317, >+ /* VMULPSZrrk */ >+ }, >+ { /* 4516 */ >+ 317, >+ /* VMULPSZrrkz */ >+ }, >+ { /* 4517 */ >+ 312, >+ /* VMULPSrm */ >+ }, >+ { /* 4518 */ >+ 313, >+ /* VMULPSrr */ >+ }, >+ { /* 4519 */ >+ 318, >+ /* VMULSDZrm */ >+ }, >+ { /* 4520 */ >+ 319, >+ /* VMULSDZrr */ >+ }, >+ { /* 4521 */ >+ 320, >+ /* VMULSDrm */ >+ }, >+ { /* 4522 */ >+ 0, >+ /* */ >+ }, >+ { /* 4523 */ >+ 321, >+ /* VMULSDrr */ >+ }, >+ { /* 4524 */ >+ 0, >+ /* */ >+ }, >+ { /* 4525 */ >+ 322, >+ /* VMULSSZrm */ >+ }, >+ { /* 4526 */ >+ 323, >+ /* VMULSSZrr */ >+ }, >+ { /* 4527 */ >+ 324, >+ /* VMULSSrm */ >+ }, >+ { /* 4528 */ >+ 0, >+ /* */ >+ }, >+ { /* 4529 */ >+ 325, >+ /* VMULSSrr */ >+ }, >+ { /* 4530 */ >+ 0, >+ /* */ >+ }, >+ { /* 4531 */ >+ 40, >+ /* VMWRITE32rm */ >+ }, >+ { /* 4532 */ >+ 41, >+ /* VMWRITE32rr */ >+ }, >+ { /* 4533 */ >+ 42, >+ /* VMWRITE64rm */ >+ }, >+ { /* 4534 */ >+ 43, >+ /* VMWRITE64rr */ >+ }, >+ { /* 4535 */ >+ 0, >+ /* VMXOFF */ >+ }, >+ { /* 4536 */ >+ 38, >+ /* VMXON */ >+ }, >+ { /* 4537 */ >+ 304, >+ /* VORPDYrm */ >+ }, >+ { /* 4538 */ >+ 305, >+ /* VORPDYrr */ >+ }, >+ { /* 4539 */ >+ 312, >+ /* VORPDrm */ >+ }, >+ { /* 4540 */ >+ 313, >+ /* VORPDrr */ >+ }, >+ { /* 4541 */ >+ 304, >+ /* VORPSYrm */ >+ }, >+ { /* 4542 */ >+ 305, >+ /* VORPSYrr */ >+ }, >+ { /* 4543 */ >+ 312, >+ /* VORPSrm */ >+ }, >+ { /* 4544 */ >+ 313, >+ /* VORPSrr */ >+ }, >+ { /* 4545 */ >+ 44, >+ /* VPABSBrm128 */ >+ }, >+ { /* 4546 */ >+ 376, >+ /* VPABSBrm256 */ >+ }, >+ { /* 4547 */ >+ 45, >+ /* VPABSBrr128 */ >+ }, >+ { /* 4548 */ >+ 377, >+ /* VPABSBrr256 */ >+ }, >+ { /* 4549 */ >+ 378, >+ /* VPABSDZrm */ >+ }, >+ { /* 4550 */ >+ 581, >+ /* VPABSDZrmb */ >+ }, >+ { /* 4551 */ >+ 582, >+ /* VPABSDZrmbk */ >+ }, >+ { /* 4552 */ >+ 582, >+ /* VPABSDZrmbkz */ >+ }, >+ { /* 4553 */ >+ 522, >+ /* VPABSDZrmk */ >+ }, >+ { /* 4554 */ >+ 522, >+ /* VPABSDZrmkz */ >+ }, >+ { /* 4555 */ >+ 379, >+ /* VPABSDZrr */ >+ }, >+ { /* 4556 */ >+ 524, >+ /* VPABSDZrrk */ >+ }, >+ { /* 4557 */ >+ 524, >+ /* VPABSDZrrkz */ >+ }, >+ { /* 4558 */ >+ 44, >+ /* VPABSDrm128 */ >+ }, >+ { /* 4559 */ >+ 376, >+ /* VPABSDrm256 */ >+ }, >+ { /* 4560 */ >+ 45, >+ /* VPABSDrr128 */ >+ }, >+ { /* 4561 */ >+ 377, >+ /* VPABSDrr256 */ >+ }, >+ { /* 4562 */ >+ 378, >+ /* VPABSQZrm */ >+ }, >+ { /* 4563 */ >+ 583, >+ /* VPABSQZrmb */ >+ }, >+ { /* 4564 */ >+ 584, >+ /* VPABSQZrmbk */ >+ }, >+ { /* 4565 */ >+ 584, >+ /* VPABSQZrmbkz */ >+ }, >+ { /* 4566 */ >+ 507, >+ /* VPABSQZrmk */ >+ }, >+ { /* 4567 */ >+ 507, >+ /* VPABSQZrmkz */ >+ }, >+ { /* 4568 */ >+ 379, >+ /* VPABSQZrr */ >+ }, >+ { /* 4569 */ >+ 509, >+ /* VPABSQZrrk */ >+ }, >+ { /* 4570 */ >+ 509, >+ /* VPABSQZrrkz */ >+ }, >+ { /* 4571 */ >+ 44, >+ /* VPABSWrm128 */ >+ }, >+ { /* 4572 */ >+ 376, >+ /* VPABSWrm256 */ >+ }, >+ { /* 4573 */ >+ 45, >+ /* VPABSWrr128 */ >+ }, >+ { /* 4574 */ >+ 377, >+ /* VPABSWrr256 */ >+ }, >+ { /* 4575 */ >+ 304, >+ /* VPACKSSDWYrm */ >+ }, >+ { /* 4576 */ >+ 305, >+ /* VPACKSSDWYrr */ >+ }, >+ { /* 4577 */ >+ 312, >+ /* VPACKSSDWrm */ >+ }, >+ { /* 4578 */ >+ 313, >+ /* VPACKSSDWrr */ >+ }, >+ { /* 4579 */ >+ 304, >+ /* VPACKSSWBYrm */ >+ }, >+ { /* 4580 */ >+ 305, >+ /* VPACKSSWBYrr */ >+ }, >+ { /* 4581 */ >+ 312, >+ /* VPACKSSWBrm */ >+ }, >+ { /* 4582 */ >+ 313, >+ /* VPACKSSWBrr */ >+ }, >+ { /* 4583 */ >+ 304, >+ /* VPACKUSDWYrm */ >+ }, >+ { /* 4584 */ >+ 305, >+ /* VPACKUSDWYrr */ >+ }, >+ { /* 4585 */ >+ 312, >+ /* VPACKUSDWrm */ >+ }, >+ { /* 4586 */ >+ 313, >+ /* VPACKUSDWrr */ >+ }, >+ { /* 4587 */ >+ 304, >+ /* VPACKUSWBYrm */ >+ }, >+ { /* 4588 */ >+ 305, >+ /* VPACKUSWBYrr */ >+ }, >+ { /* 4589 */ >+ 312, >+ /* VPACKUSWBrm */ >+ }, >+ { /* 4590 */ >+ 313, >+ /* VPACKUSWBrr */ >+ }, >+ { /* 4591 */ >+ 304, >+ /* VPADDBYrm */ >+ }, >+ { /* 4592 */ >+ 305, >+ /* VPADDBYrr */ >+ }, >+ { /* 4593 */ >+ 312, >+ /* VPADDBrm */ >+ }, >+ { /* 4594 */ >+ 313, >+ /* VPADDBrr */ >+ }, >+ { /* 4595 */ >+ 304, >+ /* VPADDDYrm */ >+ }, >+ { /* 4596 */ >+ 305, >+ /* VPADDDYrr */ >+ }, >+ { /* 4597 */ >+ 306, >+ /* VPADDDZrm */ >+ }, >+ { /* 4598 */ >+ 585, >+ /* VPADDDZrmb */ >+ }, >+ { /* 4599 */ >+ 586, >+ /* VPADDDZrmbk */ >+ }, >+ { /* 4600 */ >+ 587, >+ /* VPADDDZrmbkz */ >+ }, >+ { /* 4601 */ >+ 588, >+ /* VPADDDZrmk */ >+ }, >+ { /* 4602 */ >+ 316, >+ /* VPADDDZrmkz */ >+ }, >+ { /* 4603 */ >+ 310, >+ /* VPADDDZrr */ >+ }, >+ { /* 4604 */ >+ 439, >+ /* VPADDDZrrk */ >+ }, >+ { /* 4605 */ >+ 317, >+ /* VPADDDZrrkz */ >+ }, >+ { /* 4606 */ >+ 312, >+ /* VPADDDrm */ >+ }, >+ { /* 4607 */ >+ 313, >+ /* VPADDDrr */ >+ }, >+ { /* 4608 */ >+ 304, >+ /* VPADDQYrm */ >+ }, >+ { /* 4609 */ >+ 305, >+ /* VPADDQYrr */ >+ }, >+ { /* 4610 */ >+ 306, >+ /* VPADDQZrm */ >+ }, >+ { /* 4611 */ >+ 589, >+ /* VPADDQZrmb */ >+ }, >+ { /* 4612 */ >+ 590, >+ /* VPADDQZrmbk */ >+ }, >+ { /* 4613 */ >+ 591, >+ /* VPADDQZrmbkz */ >+ }, >+ { /* 4614 */ >+ 592, >+ /* VPADDQZrmk */ >+ }, >+ { /* 4615 */ >+ 309, >+ /* VPADDQZrmkz */ >+ }, >+ { /* 4616 */ >+ 310, >+ /* VPADDQZrr */ >+ }, >+ { /* 4617 */ >+ 438, >+ /* VPADDQZrrk */ >+ }, >+ { /* 4618 */ >+ 311, >+ /* VPADDQZrrkz */ >+ }, >+ { /* 4619 */ >+ 312, >+ /* VPADDQrm */ >+ }, >+ { /* 4620 */ >+ 313, >+ /* VPADDQrr */ >+ }, >+ { /* 4621 */ >+ 304, >+ /* VPADDSBYrm */ >+ }, >+ { /* 4622 */ >+ 305, >+ /* VPADDSBYrr */ >+ }, >+ { /* 4623 */ >+ 312, >+ /* VPADDSBrm */ >+ }, >+ { /* 4624 */ >+ 313, >+ /* VPADDSBrr */ >+ }, >+ { /* 4625 */ >+ 304, >+ /* VPADDSWYrm */ >+ }, >+ { /* 4626 */ >+ 305, >+ /* VPADDSWYrr */ >+ }, >+ { /* 4627 */ >+ 312, >+ /* VPADDSWrm */ >+ }, >+ { /* 4628 */ >+ 313, >+ /* VPADDSWrr */ >+ }, >+ { /* 4629 */ >+ 304, >+ /* VPADDUSBYrm */ >+ }, >+ { /* 4630 */ >+ 305, >+ /* VPADDUSBYrr */ >+ }, >+ { /* 4631 */ >+ 312, >+ /* VPADDUSBrm */ >+ }, >+ { /* 4632 */ >+ 313, >+ /* VPADDUSBrr */ >+ }, >+ { /* 4633 */ >+ 304, >+ /* VPADDUSWYrm */ >+ }, >+ { /* 4634 */ >+ 305, >+ /* VPADDUSWYrr */ >+ }, >+ { /* 4635 */ >+ 312, >+ /* VPADDUSWrm */ >+ }, >+ { /* 4636 */ >+ 313, >+ /* VPADDUSWrr */ >+ }, >+ { /* 4637 */ >+ 304, >+ /* VPADDWYrm */ >+ }, >+ { /* 4638 */ >+ 305, >+ /* VPADDWYrr */ >+ }, >+ { /* 4639 */ >+ 312, >+ /* VPADDWrm */ >+ }, >+ { /* 4640 */ >+ 313, >+ /* VPADDWrr */ >+ }, >+ { /* 4641 */ >+ 593, >+ /* VPALIGNR128rm */ >+ }, >+ { /* 4642 */ >+ 594, >+ /* VPALIGNR128rr */ >+ }, >+ { /* 4643 */ >+ 595, >+ /* VPALIGNR256rm */ >+ }, >+ { /* 4644 */ >+ 596, >+ /* VPALIGNR256rr */ >+ }, >+ { /* 4645 */ >+ 306, >+ /* VPANDDZrm */ >+ }, >+ { /* 4646 */ >+ 585, >+ /* VPANDDZrmb */ >+ }, >+ { /* 4647 */ >+ 586, >+ /* VPANDDZrmbk */ >+ }, >+ { /* 4648 */ >+ 587, >+ /* VPANDDZrmbkz */ >+ }, >+ { /* 4649 */ >+ 588, >+ /* VPANDDZrmk */ >+ }, >+ { /* 4650 */ >+ 316, >+ /* VPANDDZrmkz */ >+ }, >+ { /* 4651 */ >+ 310, >+ /* VPANDDZrr */ >+ }, >+ { /* 4652 */ >+ 439, >+ /* VPANDDZrrk */ >+ }, >+ { /* 4653 */ >+ 317, >+ /* VPANDDZrrkz */ >+ }, >+ { /* 4654 */ >+ 306, >+ /* VPANDNDZrm */ >+ }, >+ { /* 4655 */ >+ 585, >+ /* VPANDNDZrmb */ >+ }, >+ { /* 4656 */ >+ 586, >+ /* VPANDNDZrmbk */ >+ }, >+ { /* 4657 */ >+ 587, >+ /* VPANDNDZrmbkz */ >+ }, >+ { /* 4658 */ >+ 588, >+ /* VPANDNDZrmk */ >+ }, >+ { /* 4659 */ >+ 316, >+ /* VPANDNDZrmkz */ >+ }, >+ { /* 4660 */ >+ 310, >+ /* VPANDNDZrr */ >+ }, >+ { /* 4661 */ >+ 439, >+ /* VPANDNDZrrk */ >+ }, >+ { /* 4662 */ >+ 317, >+ /* VPANDNDZrrkz */ >+ }, >+ { /* 4663 */ >+ 306, >+ /* VPANDNQZrm */ >+ }, >+ { /* 4664 */ >+ 589, >+ /* VPANDNQZrmb */ >+ }, >+ { /* 4665 */ >+ 590, >+ /* VPANDNQZrmbk */ >+ }, >+ { /* 4666 */ >+ 591, >+ /* VPANDNQZrmbkz */ >+ }, >+ { /* 4667 */ >+ 592, >+ /* VPANDNQZrmk */ >+ }, >+ { /* 4668 */ >+ 309, >+ /* VPANDNQZrmkz */ >+ }, >+ { /* 4669 */ >+ 310, >+ /* VPANDNQZrr */ >+ }, >+ { /* 4670 */ >+ 438, >+ /* VPANDNQZrrk */ >+ }, >+ { /* 4671 */ >+ 311, >+ /* VPANDNQZrrkz */ >+ }, >+ { /* 4672 */ >+ 304, >+ /* VPANDNYrm */ >+ }, >+ { /* 4673 */ >+ 305, >+ /* VPANDNYrr */ >+ }, >+ { /* 4674 */ >+ 312, >+ /* VPANDNrm */ >+ }, >+ { /* 4675 */ >+ 313, >+ /* VPANDNrr */ >+ }, >+ { /* 4676 */ >+ 306, >+ /* VPANDQZrm */ >+ }, >+ { /* 4677 */ >+ 589, >+ /* VPANDQZrmb */ >+ }, >+ { /* 4678 */ >+ 590, >+ /* VPANDQZrmbk */ >+ }, >+ { /* 4679 */ >+ 591, >+ /* VPANDQZrmbkz */ >+ }, >+ { /* 4680 */ >+ 592, >+ /* VPANDQZrmk */ >+ }, >+ { /* 4681 */ >+ 309, >+ /* VPANDQZrmkz */ >+ }, >+ { /* 4682 */ >+ 310, >+ /* VPANDQZrr */ >+ }, >+ { /* 4683 */ >+ 438, >+ /* VPANDQZrrk */ >+ }, >+ { /* 4684 */ >+ 311, >+ /* VPANDQZrrkz */ >+ }, >+ { /* 4685 */ >+ 304, >+ /* VPANDYrm */ >+ }, >+ { /* 4686 */ >+ 305, >+ /* VPANDYrr */ >+ }, >+ { /* 4687 */ >+ 312, >+ /* VPANDrm */ >+ }, >+ { /* 4688 */ >+ 313, >+ /* VPANDrr */ >+ }, >+ { /* 4689 */ >+ 304, >+ /* VPAVGBYrm */ >+ }, >+ { /* 4690 */ >+ 305, >+ /* VPAVGBYrr */ >+ }, >+ { /* 4691 */ >+ 312, >+ /* VPAVGBrm */ >+ }, >+ { /* 4692 */ >+ 313, >+ /* VPAVGBrr */ >+ }, >+ { /* 4693 */ >+ 304, >+ /* VPAVGWYrm */ >+ }, >+ { /* 4694 */ >+ 305, >+ /* VPAVGWYrr */ >+ }, >+ { /* 4695 */ >+ 312, >+ /* VPAVGWrm */ >+ }, >+ { /* 4696 */ >+ 313, >+ /* VPAVGWrr */ >+ }, >+ { /* 4697 */ >+ 332, >+ /* VPBLENDDYrmi */ >+ }, >+ { /* 4698 */ >+ 333, >+ /* VPBLENDDYrri */ >+ }, >+ { /* 4699 */ >+ 334, >+ /* VPBLENDDrmi */ >+ }, >+ { /* 4700 */ >+ 335, >+ /* VPBLENDDrri */ >+ }, >+ { /* 4701 */ >+ 316, >+ /* VPBLENDMDZrm */ >+ }, >+ { /* 4702 */ >+ 317, >+ /* VPBLENDMDZrr */ >+ }, >+ { /* 4703 */ >+ 309, >+ /* VPBLENDMQZrm */ >+ }, >+ { /* 4704 */ >+ 311, >+ /* VPBLENDMQZrr */ >+ }, >+ { /* 4705 */ >+ 336, >+ /* VPBLENDVBYrm */ >+ }, >+ { /* 4706 */ >+ 337, >+ /* VPBLENDVBYrr */ >+ }, >+ { /* 4707 */ >+ 338, >+ /* VPBLENDVBrm */ >+ }, >+ { /* 4708 */ >+ 339, >+ /* VPBLENDVBrr */ >+ }, >+ { /* 4709 */ >+ 332, >+ /* VPBLENDWYrmi */ >+ }, >+ { /* 4710 */ >+ 333, >+ /* VPBLENDWYrri */ >+ }, >+ { /* 4711 */ >+ 334, >+ /* VPBLENDWrmi */ >+ }, >+ { /* 4712 */ >+ 335, >+ /* VPBLENDWrri */ >+ }, >+ { /* 4713 */ >+ 597, >+ /* VPBROADCASTBYrm */ >+ }, >+ { /* 4714 */ >+ 346, >+ /* VPBROADCASTBYrr */ >+ }, >+ { /* 4715 */ >+ 598, >+ /* VPBROADCASTBrm */ >+ }, >+ { /* 4716 */ >+ 45, >+ /* VPBROADCASTBrr */ >+ }, >+ { /* 4717 */ >+ 599, >+ /* VPBROADCASTDYrm */ >+ }, >+ { /* 4718 */ >+ 346, >+ /* VPBROADCASTDYrr */ >+ }, >+ { /* 4719 */ >+ 582, >+ /* VPBROADCASTDZkrm */ >+ }, >+ { /* 4720 */ >+ 600, >+ /* VPBROADCASTDZkrr */ >+ }, >+ { /* 4721 */ >+ 581, >+ /* VPBROADCASTDZrm */ >+ }, >+ { /* 4722 */ >+ 351, >+ /* VPBROADCASTDZrr */ >+ }, >+ { /* 4723 */ >+ 601, >+ /* VPBROADCASTDrZkrr */ >+ }, >+ { /* 4724 */ >+ 602, >+ /* VPBROADCASTDrZrr */ >+ }, >+ { /* 4725 */ >+ 105, >+ /* VPBROADCASTDrm */ >+ }, >+ { /* 4726 */ >+ 45, >+ /* VPBROADCASTDrr */ >+ }, >+ { /* 4727 */ >+ 603, >+ /* VPBROADCASTMB2Qrr */ >+ }, >+ { /* 4728 */ >+ 604, >+ /* VPBROADCASTMW2Drr */ >+ }, >+ { /* 4729 */ >+ 599, >+ /* VPBROADCASTQYrm */ >+ }, >+ { /* 4730 */ >+ 346, >+ /* VPBROADCASTQYrr */ >+ }, >+ { /* 4731 */ >+ 584, >+ /* VPBROADCASTQZkrm */ >+ }, >+ { /* 4732 */ >+ 605, >+ /* VPBROADCASTQZkrr */ >+ }, >+ { /* 4733 */ >+ 583, >+ /* VPBROADCASTQZrm */ >+ }, >+ { /* 4734 */ >+ 348, >+ /* VPBROADCASTQZrr */ >+ }, >+ { /* 4735 */ >+ 606, >+ /* VPBROADCASTQrZkrr */ >+ }, >+ { /* 4736 */ >+ 607, >+ /* VPBROADCASTQrZrr */ >+ }, >+ { /* 4737 */ >+ 105, >+ /* VPBROADCASTQrm */ >+ }, >+ { /* 4738 */ >+ 45, >+ /* VPBROADCASTQrr */ >+ }, >+ { /* 4739 */ >+ 599, >+ /* VPBROADCASTWYrm */ >+ }, >+ { /* 4740 */ >+ 346, >+ /* VPBROADCASTWYrr */ >+ }, >+ { /* 4741 */ >+ 105, >+ /* VPBROADCASTWrm */ >+ }, >+ { /* 4742 */ >+ 45, >+ /* VPBROADCASTWrr */ >+ }, >+ { /* 4743 */ >+ 593, >+ /* VPCLMULQDQrm */ >+ }, >+ { /* 4744 */ >+ 594, >+ /* VPCLMULQDQrr */ >+ }, >+ { /* 4745 */ >+ 338, >+ /* VPCMOVmr */ >+ }, >+ { /* 4746 */ >+ 336, >+ /* VPCMOVmrY */ >+ }, >+ { /* 4747 */ >+ 440, >+ /* VPCMOVrm */ >+ }, >+ { /* 4748 */ >+ 441, >+ /* VPCMOVrmY */ >+ }, >+ { /* 4749 */ >+ 339, >+ /* VPCMOVrr */ >+ }, >+ { /* 4750 */ >+ 337, >+ /* VPCMOVrrY */ >+ }, >+ { /* 4751 */ >+ 360, >+ /* VPCMPDZrmi */ >+ }, >+ { /* 4752 */ >+ 0, >+ /* */ >+ }, >+ { /* 4753 */ >+ 0, >+ /* */ >+ }, >+ { /* 4754 */ >+ 361, >+ /* VPCMPDZrri */ >+ }, >+ { /* 4755 */ >+ 0, >+ /* */ >+ }, >+ { /* 4756 */ >+ 0, >+ /* */ >+ }, >+ { /* 4757 */ >+ 304, >+ /* VPCMPEQBYrm */ >+ }, >+ { /* 4758 */ >+ 305, >+ /* VPCMPEQBYrr */ >+ }, >+ { /* 4759 */ >+ 608, >+ /* VPCMPEQBZ128rm */ >+ }, >+ { /* 4760 */ >+ 609, >+ /* VPCMPEQBZ128rmk */ >+ }, >+ { /* 4761 */ >+ 610, >+ /* VPCMPEQBZ128rr */ >+ }, >+ { /* 4762 */ >+ 611, >+ /* VPCMPEQBZ128rrk */ >+ }, >+ { /* 4763 */ >+ 612, >+ /* VPCMPEQBZ256rm */ >+ }, >+ { /* 4764 */ >+ 613, >+ /* VPCMPEQBZ256rmk */ >+ }, >+ { /* 4765 */ >+ 614, >+ /* VPCMPEQBZ256rr */ >+ }, >+ { /* 4766 */ >+ 615, >+ /* VPCMPEQBZ256rrk */ >+ }, >+ { /* 4767 */ >+ 616, >+ /* VPCMPEQBZrm */ >+ }, >+ { /* 4768 */ >+ 617, >+ /* VPCMPEQBZrmk */ >+ }, >+ { /* 4769 */ >+ 618, >+ /* VPCMPEQBZrr */ >+ }, >+ { /* 4770 */ >+ 619, >+ /* VPCMPEQBZrrk */ >+ }, >+ { /* 4771 */ >+ 312, >+ /* VPCMPEQBrm */ >+ }, >+ { /* 4772 */ >+ 313, >+ /* VPCMPEQBrr */ >+ }, >+ { /* 4773 */ >+ 304, >+ /* VPCMPEQDYrm */ >+ }, >+ { /* 4774 */ >+ 305, >+ /* VPCMPEQDYrr */ >+ }, >+ { /* 4775 */ >+ 620, >+ /* VPCMPEQDZ128rm */ >+ }, >+ { /* 4776 */ >+ 621, >+ /* VPCMPEQDZ128rmb */ >+ }, >+ { /* 4777 */ >+ 622, >+ /* VPCMPEQDZ128rmbk */ >+ }, >+ { /* 4778 */ >+ 623, >+ /* VPCMPEQDZ128rmk */ >+ }, >+ { /* 4779 */ >+ 624, >+ /* VPCMPEQDZ128rr */ >+ }, >+ { /* 4780 */ >+ 625, >+ /* VPCMPEQDZ128rrk */ >+ }, >+ { /* 4781 */ >+ 626, >+ /* VPCMPEQDZ256rm */ >+ }, >+ { /* 4782 */ >+ 627, >+ /* VPCMPEQDZ256rmb */ >+ }, >+ { /* 4783 */ >+ 628, >+ /* VPCMPEQDZ256rmbk */ >+ }, >+ { /* 4784 */ >+ 629, >+ /* VPCMPEQDZ256rmk */ >+ }, >+ { /* 4785 */ >+ 630, >+ /* VPCMPEQDZ256rr */ >+ }, >+ { /* 4786 */ >+ 631, >+ /* VPCMPEQDZ256rrk */ >+ }, >+ { /* 4787 */ >+ 632, >+ /* VPCMPEQDZrm */ >+ }, >+ { /* 4788 */ >+ 633, >+ /* VPCMPEQDZrmb */ >+ }, >+ { /* 4789 */ >+ 634, >+ /* VPCMPEQDZrmbk */ >+ }, >+ { /* 4790 */ >+ 635, >+ /* VPCMPEQDZrmk */ >+ }, >+ { /* 4791 */ >+ 636, >+ /* VPCMPEQDZrr */ >+ }, >+ { /* 4792 */ >+ 637, >+ /* VPCMPEQDZrrk */ >+ }, >+ { /* 4793 */ >+ 312, >+ /* VPCMPEQDrm */ >+ }, >+ { /* 4794 */ >+ 313, >+ /* VPCMPEQDrr */ >+ }, >+ { /* 4795 */ >+ 304, >+ /* VPCMPEQQYrm */ >+ }, >+ { /* 4796 */ >+ 305, >+ /* VPCMPEQQYrr */ >+ }, >+ { /* 4797 */ >+ 638, >+ /* VPCMPEQQZ128rm */ >+ }, >+ { /* 4798 */ >+ 639, >+ /* VPCMPEQQZ128rmb */ >+ }, >+ { /* 4799 */ >+ 640, >+ /* VPCMPEQQZ128rmbk */ >+ }, >+ { /* 4800 */ >+ 641, >+ /* VPCMPEQQZ128rmk */ >+ }, >+ { /* 4801 */ >+ 642, >+ /* VPCMPEQQZ128rr */ >+ }, >+ { /* 4802 */ >+ 643, >+ /* VPCMPEQQZ128rrk */ >+ }, >+ { /* 4803 */ >+ 644, >+ /* VPCMPEQQZ256rm */ >+ }, >+ { /* 4804 */ >+ 645, >+ /* VPCMPEQQZ256rmb */ >+ }, >+ { /* 4805 */ >+ 646, >+ /* VPCMPEQQZ256rmbk */ >+ }, >+ { /* 4806 */ >+ 647, >+ /* VPCMPEQQZ256rmk */ >+ }, >+ { /* 4807 */ >+ 648, >+ /* VPCMPEQQZ256rr */ >+ }, >+ { /* 4808 */ >+ 649, >+ /* VPCMPEQQZ256rrk */ >+ }, >+ { /* 4809 */ >+ 650, >+ /* VPCMPEQQZrm */ >+ }, >+ { /* 4810 */ >+ 651, >+ /* VPCMPEQQZrmb */ >+ }, >+ { /* 4811 */ >+ 652, >+ /* VPCMPEQQZrmbk */ >+ }, >+ { /* 4812 */ >+ 653, >+ /* VPCMPEQQZrmk */ >+ }, >+ { /* 4813 */ >+ 654, >+ /* VPCMPEQQZrr */ >+ }, >+ { /* 4814 */ >+ 655, >+ /* VPCMPEQQZrrk */ >+ }, >+ { /* 4815 */ >+ 312, >+ /* VPCMPEQQrm */ >+ }, >+ { /* 4816 */ >+ 313, >+ /* VPCMPEQQrr */ >+ }, >+ { /* 4817 */ >+ 304, >+ /* VPCMPEQWYrm */ >+ }, >+ { /* 4818 */ >+ 305, >+ /* VPCMPEQWYrr */ >+ }, >+ { /* 4819 */ >+ 656, >+ /* VPCMPEQWZ128rm */ >+ }, >+ { /* 4820 */ >+ 657, >+ /* VPCMPEQWZ128rmk */ >+ }, >+ { /* 4821 */ >+ 658, >+ /* VPCMPEQWZ128rr */ >+ }, >+ { /* 4822 */ >+ 659, >+ /* VPCMPEQWZ128rrk */ >+ }, >+ { /* 4823 */ >+ 660, >+ /* VPCMPEQWZ256rm */ >+ }, >+ { /* 4824 */ >+ 661, >+ /* VPCMPEQWZ256rmk */ >+ }, >+ { /* 4825 */ >+ 662, >+ /* VPCMPEQWZ256rr */ >+ }, >+ { /* 4826 */ >+ 663, >+ /* VPCMPEQWZ256rrk */ >+ }, >+ { /* 4827 */ >+ 664, >+ /* VPCMPEQWZrm */ >+ }, >+ { /* 4828 */ >+ 665, >+ /* VPCMPEQWZrmk */ >+ }, >+ { /* 4829 */ >+ 666, >+ /* VPCMPEQWZrr */ >+ }, >+ { /* 4830 */ >+ 667, >+ /* VPCMPEQWZrrk */ >+ }, >+ { /* 4831 */ >+ 312, >+ /* VPCMPEQWrm */ >+ }, >+ { /* 4832 */ >+ 313, >+ /* VPCMPEQWrr */ >+ }, >+ { /* 4833 */ >+ 0, >+ /* */ >+ }, >+ { /* 4834 */ >+ 0, >+ /* */ >+ }, >+ { /* 4835 */ >+ 46, >+ /* VPCMPESTRIrm */ >+ }, >+ { /* 4836 */ >+ 47, >+ /* VPCMPESTRIrr */ >+ }, >+ { /* 4837 */ >+ 0, >+ /* */ >+ }, >+ { /* 4838 */ >+ 0, >+ /* */ >+ }, >+ { /* 4839 */ >+ 46, >+ /* VPCMPESTRM128rm */ >+ }, >+ { /* 4840 */ >+ 47, >+ /* VPCMPESTRM128rr */ >+ }, >+ { /* 4841 */ >+ 304, >+ /* VPCMPGTBYrm */ >+ }, >+ { /* 4842 */ >+ 305, >+ /* VPCMPGTBYrr */ >+ }, >+ { /* 4843 */ >+ 608, >+ /* VPCMPGTBZ128rm */ >+ }, >+ { /* 4844 */ >+ 609, >+ /* VPCMPGTBZ128rmk */ >+ }, >+ { /* 4845 */ >+ 610, >+ /* VPCMPGTBZ128rr */ >+ }, >+ { /* 4846 */ >+ 611, >+ /* VPCMPGTBZ128rrk */ >+ }, >+ { /* 4847 */ >+ 612, >+ /* VPCMPGTBZ256rm */ >+ }, >+ { /* 4848 */ >+ 613, >+ /* VPCMPGTBZ256rmk */ >+ }, >+ { /* 4849 */ >+ 614, >+ /* VPCMPGTBZ256rr */ >+ }, >+ { /* 4850 */ >+ 615, >+ /* VPCMPGTBZ256rrk */ >+ }, >+ { /* 4851 */ >+ 616, >+ /* VPCMPGTBZrm */ >+ }, >+ { /* 4852 */ >+ 617, >+ /* VPCMPGTBZrmk */ >+ }, >+ { /* 4853 */ >+ 618, >+ /* VPCMPGTBZrr */ >+ }, >+ { /* 4854 */ >+ 619, >+ /* VPCMPGTBZrrk */ >+ }, >+ { /* 4855 */ >+ 312, >+ /* VPCMPGTBrm */ >+ }, >+ { /* 4856 */ >+ 313, >+ /* VPCMPGTBrr */ >+ }, >+ { /* 4857 */ >+ 304, >+ /* VPCMPGTDYrm */ >+ }, >+ { /* 4858 */ >+ 305, >+ /* VPCMPGTDYrr */ >+ }, >+ { /* 4859 */ >+ 620, >+ /* VPCMPGTDZ128rm */ >+ }, >+ { /* 4860 */ >+ 621, >+ /* VPCMPGTDZ128rmb */ >+ }, >+ { /* 4861 */ >+ 622, >+ /* VPCMPGTDZ128rmbk */ >+ }, >+ { /* 4862 */ >+ 623, >+ /* VPCMPGTDZ128rmk */ >+ }, >+ { /* 4863 */ >+ 624, >+ /* VPCMPGTDZ128rr */ >+ }, >+ { /* 4864 */ >+ 625, >+ /* VPCMPGTDZ128rrk */ >+ }, >+ { /* 4865 */ >+ 626, >+ /* VPCMPGTDZ256rm */ >+ }, >+ { /* 4866 */ >+ 627, >+ /* VPCMPGTDZ256rmb */ >+ }, >+ { /* 4867 */ >+ 628, >+ /* VPCMPGTDZ256rmbk */ >+ }, >+ { /* 4868 */ >+ 629, >+ /* VPCMPGTDZ256rmk */ >+ }, >+ { /* 4869 */ >+ 630, >+ /* VPCMPGTDZ256rr */ >+ }, >+ { /* 4870 */ >+ 631, >+ /* VPCMPGTDZ256rrk */ >+ }, >+ { /* 4871 */ >+ 632, >+ /* VPCMPGTDZrm */ >+ }, >+ { /* 4872 */ >+ 633, >+ /* VPCMPGTDZrmb */ >+ }, >+ { /* 4873 */ >+ 634, >+ /* VPCMPGTDZrmbk */ >+ }, >+ { /* 4874 */ >+ 635, >+ /* VPCMPGTDZrmk */ >+ }, >+ { /* 4875 */ >+ 636, >+ /* VPCMPGTDZrr */ >+ }, >+ { /* 4876 */ >+ 637, >+ /* VPCMPGTDZrrk */ >+ }, >+ { /* 4877 */ >+ 312, >+ /* VPCMPGTDrm */ >+ }, >+ { /* 4878 */ >+ 313, >+ /* VPCMPGTDrr */ >+ }, >+ { /* 4879 */ >+ 304, >+ /* VPCMPGTQYrm */ >+ }, >+ { /* 4880 */ >+ 305, >+ /* VPCMPGTQYrr */ >+ }, >+ { /* 4881 */ >+ 638, >+ /* VPCMPGTQZ128rm */ >+ }, >+ { /* 4882 */ >+ 639, >+ /* VPCMPGTQZ128rmb */ >+ }, >+ { /* 4883 */ >+ 640, >+ /* VPCMPGTQZ128rmbk */ >+ }, >+ { /* 4884 */ >+ 641, >+ /* VPCMPGTQZ128rmk */ >+ }, >+ { /* 4885 */ >+ 642, >+ /* VPCMPGTQZ128rr */ >+ }, >+ { /* 4886 */ >+ 643, >+ /* VPCMPGTQZ128rrk */ >+ }, >+ { /* 4887 */ >+ 644, >+ /* VPCMPGTQZ256rm */ >+ }, >+ { /* 4888 */ >+ 645, >+ /* VPCMPGTQZ256rmb */ >+ }, >+ { /* 4889 */ >+ 646, >+ /* VPCMPGTQZ256rmbk */ >+ }, >+ { /* 4890 */ >+ 647, >+ /* VPCMPGTQZ256rmk */ >+ }, >+ { /* 4891 */ >+ 648, >+ /* VPCMPGTQZ256rr */ >+ }, >+ { /* 4892 */ >+ 649, >+ /* VPCMPGTQZ256rrk */ >+ }, >+ { /* 4893 */ >+ 650, >+ /* VPCMPGTQZrm */ >+ }, >+ { /* 4894 */ >+ 651, >+ /* VPCMPGTQZrmb */ >+ }, >+ { /* 4895 */ >+ 652, >+ /* VPCMPGTQZrmbk */ >+ }, >+ { /* 4896 */ >+ 653, >+ /* VPCMPGTQZrmk */ >+ }, >+ { /* 4897 */ >+ 654, >+ /* VPCMPGTQZrr */ >+ }, >+ { /* 4898 */ >+ 655, >+ /* VPCMPGTQZrrk */ >+ }, >+ { /* 4899 */ >+ 312, >+ /* VPCMPGTQrm */ >+ }, >+ { /* 4900 */ >+ 313, >+ /* VPCMPGTQrr */ >+ }, >+ { /* 4901 */ >+ 304, >+ /* VPCMPGTWYrm */ >+ }, >+ { /* 4902 */ >+ 305, >+ /* VPCMPGTWYrr */ >+ }, >+ { /* 4903 */ >+ 656, >+ /* VPCMPGTWZ128rm */ >+ }, >+ { /* 4904 */ >+ 657, >+ /* VPCMPGTWZ128rmk */ >+ }, >+ { /* 4905 */ >+ 658, >+ /* VPCMPGTWZ128rr */ >+ }, >+ { /* 4906 */ >+ 659, >+ /* VPCMPGTWZ128rrk */ >+ }, >+ { /* 4907 */ >+ 660, >+ /* VPCMPGTWZ256rm */ >+ }, >+ { /* 4908 */ >+ 661, >+ /* VPCMPGTWZ256rmk */ >+ }, >+ { /* 4909 */ >+ 662, >+ /* VPCMPGTWZ256rr */ >+ }, >+ { /* 4910 */ >+ 663, >+ /* VPCMPGTWZ256rrk */ >+ }, >+ { /* 4911 */ >+ 664, >+ /* VPCMPGTWZrm */ >+ }, >+ { /* 4912 */ >+ 665, >+ /* VPCMPGTWZrmk */ >+ }, >+ { /* 4913 */ >+ 666, >+ /* VPCMPGTWZrr */ >+ }, >+ { /* 4914 */ >+ 667, >+ /* VPCMPGTWZrrk */ >+ }, >+ { /* 4915 */ >+ 312, >+ /* VPCMPGTWrm */ >+ }, >+ { /* 4916 */ >+ 313, >+ /* VPCMPGTWrr */ >+ }, >+ { /* 4917 */ >+ 0, >+ /* */ >+ }, >+ { /* 4918 */ >+ 0, >+ /* */ >+ }, >+ { /* 4919 */ >+ 46, >+ /* VPCMPISTRIrm */ >+ }, >+ { /* 4920 */ >+ 47, >+ /* VPCMPISTRIrr */ >+ }, >+ { /* 4921 */ >+ 0, >+ /* */ >+ }, >+ { /* 4922 */ >+ 0, >+ /* */ >+ }, >+ { /* 4923 */ >+ 46, >+ /* VPCMPISTRM128rm */ >+ }, >+ { /* 4924 */ >+ 47, >+ /* VPCMPISTRM128rr */ >+ }, >+ { /* 4925 */ >+ 355, >+ /* VPCMPQZrmi */ >+ }, >+ { /* 4926 */ >+ 0, >+ /* */ >+ }, >+ { /* 4927 */ >+ 0, >+ /* */ >+ }, >+ { /* 4928 */ >+ 356, >+ /* VPCMPQZrri */ >+ }, >+ { /* 4929 */ >+ 0, >+ /* */ >+ }, >+ { /* 4930 */ >+ 0, >+ /* */ >+ }, >+ { /* 4931 */ >+ 360, >+ /* VPCMPUDZrmi */ >+ }, >+ { /* 4932 */ >+ 0, >+ /* */ >+ }, >+ { /* 4933 */ >+ 0, >+ /* */ >+ }, >+ { /* 4934 */ >+ 361, >+ /* VPCMPUDZrri */ >+ }, >+ { /* 4935 */ >+ 0, >+ /* */ >+ }, >+ { /* 4936 */ >+ 0, >+ /* */ >+ }, >+ { /* 4937 */ >+ 355, >+ /* VPCMPUQZrmi */ >+ }, >+ { /* 4938 */ >+ 0, >+ /* */ >+ }, >+ { /* 4939 */ >+ 0, >+ /* */ >+ }, >+ { /* 4940 */ >+ 356, >+ /* VPCMPUQZrri */ >+ }, >+ { /* 4941 */ >+ 0, >+ /* */ >+ }, >+ { /* 4942 */ >+ 0, >+ /* */ >+ }, >+ { /* 4943 */ >+ 593, >+ /* VPCOMBmi */ >+ }, >+ { /* 4944 */ >+ 594, >+ /* VPCOMBri */ >+ }, >+ { /* 4945 */ >+ 593, >+ /* VPCOMDmi */ >+ }, >+ { /* 4946 */ >+ 594, >+ /* VPCOMDri */ >+ }, >+ { /* 4947 */ >+ 593, >+ /* VPCOMQmi */ >+ }, >+ { /* 4948 */ >+ 594, >+ /* VPCOMQri */ >+ }, >+ { /* 4949 */ >+ 593, >+ /* VPCOMUBmi */ >+ }, >+ { /* 4950 */ >+ 594, >+ /* VPCOMUBri */ >+ }, >+ { /* 4951 */ >+ 593, >+ /* VPCOMUDmi */ >+ }, >+ { /* 4952 */ >+ 594, >+ /* VPCOMUDri */ >+ }, >+ { /* 4953 */ >+ 593, >+ /* VPCOMUQmi */ >+ }, >+ { /* 4954 */ >+ 594, >+ /* VPCOMUQri */ >+ }, >+ { /* 4955 */ >+ 593, >+ /* VPCOMUWmi */ >+ }, >+ { /* 4956 */ >+ 594, >+ /* VPCOMUWri */ >+ }, >+ { /* 4957 */ >+ 593, >+ /* VPCOMWmi */ >+ }, >+ { /* 4958 */ >+ 594, >+ /* VPCOMWri */ >+ }, >+ { /* 4959 */ >+ 378, >+ /* VPCONFLICTDrm */ >+ }, >+ { /* 4960 */ >+ 581, >+ /* VPCONFLICTDrmb */ >+ }, >+ { /* 4961 */ >+ 668, >+ /* VPCONFLICTDrmbk */ >+ }, >+ { /* 4962 */ >+ 582, >+ /* VPCONFLICTDrmbkz */ >+ }, >+ { /* 4963 */ >+ 521, >+ /* VPCONFLICTDrmk */ >+ }, >+ { /* 4964 */ >+ 522, >+ /* VPCONFLICTDrmkz */ >+ }, >+ { /* 4965 */ >+ 379, >+ /* VPCONFLICTDrr */ >+ }, >+ { /* 4966 */ >+ 523, >+ /* VPCONFLICTDrrk */ >+ }, >+ { /* 4967 */ >+ 524, >+ /* VPCONFLICTDrrkz */ >+ }, >+ { /* 4968 */ >+ 378, >+ /* VPCONFLICTQrm */ >+ }, >+ { /* 4969 */ >+ 583, >+ /* VPCONFLICTQrmb */ >+ }, >+ { /* 4970 */ >+ 669, >+ /* VPCONFLICTQrmbk */ >+ }, >+ { /* 4971 */ >+ 584, >+ /* VPCONFLICTQrmbkz */ >+ }, >+ { /* 4972 */ >+ 506, >+ /* VPCONFLICTQrmk */ >+ }, >+ { /* 4973 */ >+ 507, >+ /* VPCONFLICTQrmkz */ >+ }, >+ { /* 4974 */ >+ 379, >+ /* VPCONFLICTQrr */ >+ }, >+ { /* 4975 */ >+ 508, >+ /* VPCONFLICTQrrk */ >+ }, >+ { /* 4976 */ >+ 509, >+ /* VPCONFLICTQrrkz */ >+ }, >+ { /* 4977 */ >+ 595, >+ /* VPERM2F128rm */ >+ }, >+ { /* 4978 */ >+ 596, >+ /* VPERM2F128rr */ >+ }, >+ { /* 4979 */ >+ 595, >+ /* VPERM2I128rm */ >+ }, >+ { /* 4980 */ >+ 596, >+ /* VPERM2I128rr */ >+ }, >+ { /* 4981 */ >+ 304, >+ /* VPERMDYrm */ >+ }, >+ { /* 4982 */ >+ 305, >+ /* VPERMDYrr */ >+ }, >+ { /* 4983 */ >+ 306, >+ /* VPERMDZrm */ >+ }, >+ { /* 4984 */ >+ 310, >+ /* VPERMDZrr */ >+ }, >+ { /* 4985 */ >+ 434, >+ /* VPERMI2Drm */ >+ }, >+ { /* 4986 */ >+ 588, >+ /* VPERMI2Drmk */ >+ }, >+ { /* 4987 */ >+ 588, >+ /* VPERMI2Drmkz */ >+ }, >+ { /* 4988 */ >+ 437, >+ /* VPERMI2Drr */ >+ }, >+ { /* 4989 */ >+ 439, >+ /* VPERMI2Drrk */ >+ }, >+ { /* 4990 */ >+ 439, >+ /* VPERMI2Drrkz */ >+ }, >+ { /* 4991 */ >+ 434, >+ /* VPERMI2PDrm */ >+ }, >+ { /* 4992 */ >+ 592, >+ /* VPERMI2PDrmk */ >+ }, >+ { /* 4993 */ >+ 592, >+ /* VPERMI2PDrmkz */ >+ }, >+ { /* 4994 */ >+ 437, >+ /* VPERMI2PDrr */ >+ }, >+ { /* 4995 */ >+ 438, >+ /* VPERMI2PDrrk */ >+ }, >+ { /* 4996 */ >+ 438, >+ /* VPERMI2PDrrkz */ >+ }, >+ { /* 4997 */ >+ 434, >+ /* VPERMI2PSrm */ >+ }, >+ { /* 4998 */ >+ 588, >+ /* VPERMI2PSrmk */ >+ }, >+ { /* 4999 */ >+ 588, >+ /* VPERMI2PSrmkz */ >+ }, >+ { /* 5000 */ >+ 437, >+ /* VPERMI2PSrr */ >+ }, >+ { /* 5001 */ >+ 439, >+ /* VPERMI2PSrrk */ >+ }, >+ { /* 5002 */ >+ 439, >+ /* VPERMI2PSrrkz */ >+ }, >+ { /* 5003 */ >+ 434, >+ /* VPERMI2Qrm */ >+ }, >+ { /* 5004 */ >+ 592, >+ /* VPERMI2Qrmk */ >+ }, >+ { /* 5005 */ >+ 592, >+ /* VPERMI2Qrmkz */ >+ }, >+ { /* 5006 */ >+ 437, >+ /* VPERMI2Qrr */ >+ }, >+ { /* 5007 */ >+ 438, >+ /* VPERMI2Qrrk */ >+ }, >+ { /* 5008 */ >+ 438, >+ /* VPERMI2Qrrkz */ >+ }, >+ { /* 5009 */ >+ 670, >+ /* VPERMIL2PDmr */ >+ }, >+ { /* 5010 */ >+ 671, >+ /* VPERMIL2PDmrY */ >+ }, >+ { /* 5011 */ >+ 672, >+ /* VPERMIL2PDrm */ >+ }, >+ { /* 5012 */ >+ 673, >+ /* VPERMIL2PDrmY */ >+ }, >+ { /* 5013 */ >+ 674, >+ /* VPERMIL2PDrr */ >+ }, >+ { /* 5014 */ >+ 675, >+ /* VPERMIL2PDrrY */ >+ }, >+ { /* 5015 */ >+ 670, >+ /* VPERMIL2PSmr */ >+ }, >+ { /* 5016 */ >+ 671, >+ /* VPERMIL2PSmrY */ >+ }, >+ { /* 5017 */ >+ 672, >+ /* VPERMIL2PSrm */ >+ }, >+ { /* 5018 */ >+ 673, >+ /* VPERMIL2PSrmY */ >+ }, >+ { /* 5019 */ >+ 674, >+ /* VPERMIL2PSrr */ >+ }, >+ { /* 5020 */ >+ 675, >+ /* VPERMIL2PSrrY */ >+ }, >+ { /* 5021 */ >+ 676, >+ /* VPERMILPDYmi */ >+ }, >+ { /* 5022 */ >+ 677, >+ /* VPERMILPDYri */ >+ }, >+ { /* 5023 */ >+ 304, >+ /* VPERMILPDYrm */ >+ }, >+ { /* 5024 */ >+ 305, >+ /* VPERMILPDYrr */ >+ }, >+ { /* 5025 */ >+ 678, >+ /* VPERMILPDZmi */ >+ }, >+ { /* 5026 */ >+ 679, >+ /* VPERMILPDZri */ >+ }, >+ { /* 5027 */ >+ 46, >+ /* VPERMILPDmi */ >+ }, >+ { /* 5028 */ >+ 47, >+ /* VPERMILPDri */ >+ }, >+ { /* 5029 */ >+ 312, >+ /* VPERMILPDrm */ >+ }, >+ { /* 5030 */ >+ 313, >+ /* VPERMILPDrr */ >+ }, >+ { /* 5031 */ >+ 676, >+ /* VPERMILPSYmi */ >+ }, >+ { /* 5032 */ >+ 677, >+ /* VPERMILPSYri */ >+ }, >+ { /* 5033 */ >+ 304, >+ /* VPERMILPSYrm */ >+ }, >+ { /* 5034 */ >+ 305, >+ /* VPERMILPSYrr */ >+ }, >+ { /* 5035 */ >+ 678, >+ /* VPERMILPSZmi */ >+ }, >+ { /* 5036 */ >+ 679, >+ /* VPERMILPSZri */ >+ }, >+ { /* 5037 */ >+ 46, >+ /* VPERMILPSmi */ >+ }, >+ { /* 5038 */ >+ 47, >+ /* VPERMILPSri */ >+ }, >+ { /* 5039 */ >+ 312, >+ /* VPERMILPSrm */ >+ }, >+ { /* 5040 */ >+ 313, >+ /* VPERMILPSrr */ >+ }, >+ { /* 5041 */ >+ 676, >+ /* VPERMPDYmi */ >+ }, >+ { /* 5042 */ >+ 677, >+ /* VPERMPDYri */ >+ }, >+ { /* 5043 */ >+ 678, >+ /* VPERMPDZmi */ >+ }, >+ { /* 5044 */ >+ 679, >+ /* VPERMPDZri */ >+ }, >+ { /* 5045 */ >+ 306, >+ /* VPERMPDZrm */ >+ }, >+ { /* 5046 */ >+ 310, >+ /* VPERMPDZrr */ >+ }, >+ { /* 5047 */ >+ 304, >+ /* VPERMPSYrm */ >+ }, >+ { /* 5048 */ >+ 305, >+ /* VPERMPSYrr */ >+ }, >+ { /* 5049 */ >+ 306, >+ /* VPERMPSZrm */ >+ }, >+ { /* 5050 */ >+ 310, >+ /* VPERMPSZrr */ >+ }, >+ { /* 5051 */ >+ 676, >+ /* VPERMQYmi */ >+ }, >+ { /* 5052 */ >+ 677, >+ /* VPERMQYri */ >+ }, >+ { /* 5053 */ >+ 678, >+ /* VPERMQZmi */ >+ }, >+ { /* 5054 */ >+ 679, >+ /* VPERMQZri */ >+ }, >+ { /* 5055 */ >+ 306, >+ /* VPERMQZrm */ >+ }, >+ { /* 5056 */ >+ 310, >+ /* VPERMQZrr */ >+ }, >+ { /* 5057 */ >+ 434, >+ /* VPERMT2Drm */ >+ }, >+ { /* 5058 */ >+ 588, >+ /* VPERMT2Drmk */ >+ }, >+ { /* 5059 */ >+ 588, >+ /* VPERMT2Drmkz */ >+ }, >+ { /* 5060 */ >+ 437, >+ /* VPERMT2Drr */ >+ }, >+ { /* 5061 */ >+ 439, >+ /* VPERMT2Drrk */ >+ }, >+ { /* 5062 */ >+ 439, >+ /* VPERMT2Drrkz */ >+ }, >+ { /* 5063 */ >+ 434, >+ /* VPERMT2PDrm */ >+ }, >+ { /* 5064 */ >+ 592, >+ /* VPERMT2PDrmk */ >+ }, >+ { /* 5065 */ >+ 592, >+ /* VPERMT2PDrmkz */ >+ }, >+ { /* 5066 */ >+ 437, >+ /* VPERMT2PDrr */ >+ }, >+ { /* 5067 */ >+ 438, >+ /* VPERMT2PDrrk */ >+ }, >+ { /* 5068 */ >+ 438, >+ /* VPERMT2PDrrkz */ >+ }, >+ { /* 5069 */ >+ 434, >+ /* VPERMT2PSrm */ >+ }, >+ { /* 5070 */ >+ 588, >+ /* VPERMT2PSrmk */ >+ }, >+ { /* 5071 */ >+ 588, >+ /* VPERMT2PSrmkz */ >+ }, >+ { /* 5072 */ >+ 437, >+ /* VPERMT2PSrr */ >+ }, >+ { /* 5073 */ >+ 439, >+ /* VPERMT2PSrrk */ >+ }, >+ { /* 5074 */ >+ 439, >+ /* VPERMT2PSrrkz */ >+ }, >+ { /* 5075 */ >+ 434, >+ /* VPERMT2Qrm */ >+ }, >+ { /* 5076 */ >+ 592, >+ /* VPERMT2Qrmk */ >+ }, >+ { /* 5077 */ >+ 592, >+ /* VPERMT2Qrmkz */ >+ }, >+ { /* 5078 */ >+ 437, >+ /* VPERMT2Qrr */ >+ }, >+ { /* 5079 */ >+ 438, >+ /* VPERMT2Qrrk */ >+ }, >+ { /* 5080 */ >+ 438, >+ /* VPERMT2Qrrkz */ >+ }, >+ { /* 5081 */ >+ 269, >+ /* VPEXTRBmr */ >+ }, >+ { /* 5082 */ >+ 133, >+ /* VPEXTRBrr */ >+ }, >+ { /* 5083 */ >+ 270, >+ /* VPEXTRDmr */ >+ }, >+ { /* 5084 */ >+ 133, >+ /* VPEXTRDrr */ >+ }, >+ { /* 5085 */ >+ 270, >+ /* VPEXTRQmr */ >+ }, >+ { /* 5086 */ >+ 271, >+ /* VPEXTRQrr */ >+ }, >+ { /* 5087 */ >+ 270, >+ /* VPEXTRWmr */ >+ }, >+ { /* 5088 */ >+ 272, >+ /* VPEXTRWri */ >+ }, >+ { /* 5089 */ >+ 133, >+ /* VPEXTRWrr_REV */ >+ }, >+ { /* 5090 */ >+ 467, >+ /* VPGATHERDDYrm */ >+ }, >+ { /* 5091 */ >+ 468, >+ /* VPGATHERDDZrm */ >+ }, >+ { /* 5092 */ >+ 469, >+ /* VPGATHERDDrm */ >+ }, >+ { /* 5093 */ >+ 464, >+ /* VPGATHERDQYrm */ >+ }, >+ { /* 5094 */ >+ 465, >+ /* VPGATHERDQZrm */ >+ }, >+ { /* 5095 */ >+ 466, >+ /* VPGATHERDQrm */ >+ }, >+ { /* 5096 */ >+ 469, >+ /* VPGATHERQDYrm */ >+ }, >+ { /* 5097 */ >+ 473, >+ /* VPGATHERQDZrm */ >+ }, >+ { /* 5098 */ >+ 469, >+ /* VPGATHERQDrm */ >+ }, >+ { /* 5099 */ >+ 464, >+ /* VPGATHERQQYrm */ >+ }, >+ { /* 5100 */ >+ 465, >+ /* VPGATHERQQZrm */ >+ }, >+ { /* 5101 */ >+ 466, >+ /* VPGATHERQQrm */ >+ }, >+ { /* 5102 */ >+ 44, >+ /* VPHADDBDrm */ >+ }, >+ { /* 5103 */ >+ 45, >+ /* VPHADDBDrr */ >+ }, >+ { /* 5104 */ >+ 44, >+ /* VPHADDBQrm */ >+ }, >+ { /* 5105 */ >+ 45, >+ /* VPHADDBQrr */ >+ }, >+ { /* 5106 */ >+ 44, >+ /* VPHADDBWrm */ >+ }, >+ { /* 5107 */ >+ 45, >+ /* VPHADDBWrr */ >+ }, >+ { /* 5108 */ >+ 44, >+ /* VPHADDDQrm */ >+ }, >+ { /* 5109 */ >+ 45, >+ /* VPHADDDQrr */ >+ }, >+ { /* 5110 */ >+ 304, >+ /* VPHADDDYrm */ >+ }, >+ { /* 5111 */ >+ 305, >+ /* VPHADDDYrr */ >+ }, >+ { /* 5112 */ >+ 312, >+ /* VPHADDDrm */ >+ }, >+ { /* 5113 */ >+ 313, >+ /* VPHADDDrr */ >+ }, >+ { /* 5114 */ >+ 312, >+ /* VPHADDSWrm128 */ >+ }, >+ { /* 5115 */ >+ 304, >+ /* VPHADDSWrm256 */ >+ }, >+ { /* 5116 */ >+ 313, >+ /* VPHADDSWrr128 */ >+ }, >+ { /* 5117 */ >+ 305, >+ /* VPHADDSWrr256 */ >+ }, >+ { /* 5118 */ >+ 44, >+ /* VPHADDUBDrm */ >+ }, >+ { /* 5119 */ >+ 45, >+ /* VPHADDUBDrr */ >+ }, >+ { /* 5120 */ >+ 44, >+ /* VPHADDUBQrm */ >+ }, >+ { /* 5121 */ >+ 45, >+ /* VPHADDUBQrr */ >+ }, >+ { /* 5122 */ >+ 44, >+ /* VPHADDUBWrm */ >+ }, >+ { /* 5123 */ >+ 45, >+ /* VPHADDUBWrr */ >+ }, >+ { /* 5124 */ >+ 44, >+ /* VPHADDUDQrm */ >+ }, >+ { /* 5125 */ >+ 45, >+ /* VPHADDUDQrr */ >+ }, >+ { /* 5126 */ >+ 44, >+ /* VPHADDUWDrm */ >+ }, >+ { /* 5127 */ >+ 45, >+ /* VPHADDUWDrr */ >+ }, >+ { /* 5128 */ >+ 44, >+ /* VPHADDUWQrm */ >+ }, >+ { /* 5129 */ >+ 45, >+ /* VPHADDUWQrr */ >+ }, >+ { /* 5130 */ >+ 44, >+ /* VPHADDWDrm */ >+ }, >+ { /* 5131 */ >+ 45, >+ /* VPHADDWDrr */ >+ }, >+ { /* 5132 */ >+ 44, >+ /* VPHADDWQrm */ >+ }, >+ { /* 5133 */ >+ 45, >+ /* VPHADDWQrr */ >+ }, >+ { /* 5134 */ >+ 304, >+ /* VPHADDWYrm */ >+ }, >+ { /* 5135 */ >+ 305, >+ /* VPHADDWYrr */ >+ }, >+ { /* 5136 */ >+ 312, >+ /* VPHADDWrm */ >+ }, >+ { /* 5137 */ >+ 313, >+ /* VPHADDWrr */ >+ }, >+ { /* 5138 */ >+ 44, >+ /* VPHMINPOSUWrm128 */ >+ }, >+ { /* 5139 */ >+ 45, >+ /* VPHMINPOSUWrr128 */ >+ }, >+ { /* 5140 */ >+ 44, >+ /* VPHSUBBWrm */ >+ }, >+ { /* 5141 */ >+ 45, >+ /* VPHSUBBWrr */ >+ }, >+ { /* 5142 */ >+ 44, >+ /* VPHSUBDQrm */ >+ }, >+ { /* 5143 */ >+ 45, >+ /* VPHSUBDQrr */ >+ }, >+ { /* 5144 */ >+ 304, >+ /* VPHSUBDYrm */ >+ }, >+ { /* 5145 */ >+ 305, >+ /* VPHSUBDYrr */ >+ }, >+ { /* 5146 */ >+ 312, >+ /* VPHSUBDrm */ >+ }, >+ { /* 5147 */ >+ 313, >+ /* VPHSUBDrr */ >+ }, >+ { /* 5148 */ >+ 312, >+ /* VPHSUBSWrm128 */ >+ }, >+ { /* 5149 */ >+ 304, >+ /* VPHSUBSWrm256 */ >+ }, >+ { /* 5150 */ >+ 313, >+ /* VPHSUBSWrr128 */ >+ }, >+ { /* 5151 */ >+ 305, >+ /* VPHSUBSWrr256 */ >+ }, >+ { /* 5152 */ >+ 44, >+ /* VPHSUBWDrm */ >+ }, >+ { /* 5153 */ >+ 45, >+ /* VPHSUBWDrr */ >+ }, >+ { /* 5154 */ >+ 304, >+ /* VPHSUBWYrm */ >+ }, >+ { /* 5155 */ >+ 305, >+ /* VPHSUBWYrr */ >+ }, >+ { /* 5156 */ >+ 312, >+ /* VPHSUBWrm */ >+ }, >+ { /* 5157 */ >+ 313, >+ /* VPHSUBWrr */ >+ }, >+ { /* 5158 */ >+ 680, >+ /* VPINSRBrm */ >+ }, >+ { /* 5159 */ >+ 681, >+ /* VPINSRBrr */ >+ }, >+ { /* 5160 */ >+ 682, >+ /* VPINSRDrm */ >+ }, >+ { /* 5161 */ >+ 681, >+ /* VPINSRDrr */ >+ }, >+ { /* 5162 */ >+ 682, >+ /* VPINSRQrm */ >+ }, >+ { /* 5163 */ >+ 683, >+ /* VPINSRQrr */ >+ }, >+ { /* 5164 */ >+ 682, >+ /* VPINSRWrmi */ >+ }, >+ { /* 5165 */ >+ 681, >+ /* VPINSRWrri */ >+ }, >+ { /* 5166 */ >+ 378, >+ /* VPLZCNTDrm */ >+ }, >+ { /* 5167 */ >+ 581, >+ /* VPLZCNTDrmb */ >+ }, >+ { /* 5168 */ >+ 668, >+ /* VPLZCNTDrmbk */ >+ }, >+ { /* 5169 */ >+ 582, >+ /* VPLZCNTDrmbkz */ >+ }, >+ { /* 5170 */ >+ 521, >+ /* VPLZCNTDrmk */ >+ }, >+ { /* 5171 */ >+ 522, >+ /* VPLZCNTDrmkz */ >+ }, >+ { /* 5172 */ >+ 379, >+ /* VPLZCNTDrr */ >+ }, >+ { /* 5173 */ >+ 523, >+ /* VPLZCNTDrrk */ >+ }, >+ { /* 5174 */ >+ 524, >+ /* VPLZCNTDrrkz */ >+ }, >+ { /* 5175 */ >+ 378, >+ /* VPLZCNTQrm */ >+ }, >+ { /* 5176 */ >+ 583, >+ /* VPLZCNTQrmb */ >+ }, >+ { /* 5177 */ >+ 669, >+ /* VPLZCNTQrmbk */ >+ }, >+ { /* 5178 */ >+ 584, >+ /* VPLZCNTQrmbkz */ >+ }, >+ { /* 5179 */ >+ 506, >+ /* VPLZCNTQrmk */ >+ }, >+ { /* 5180 */ >+ 507, >+ /* VPLZCNTQrmkz */ >+ }, >+ { /* 5181 */ >+ 379, >+ /* VPLZCNTQrr */ >+ }, >+ { /* 5182 */ >+ 508, >+ /* VPLZCNTQrrk */ >+ }, >+ { /* 5183 */ >+ 509, >+ /* VPLZCNTQrrkz */ >+ }, >+ { /* 5184 */ >+ 338, >+ /* VPMACSDDrm */ >+ }, >+ { /* 5185 */ >+ 339, >+ /* VPMACSDDrr */ >+ }, >+ { /* 5186 */ >+ 338, >+ /* VPMACSDQHrm */ >+ }, >+ { /* 5187 */ >+ 339, >+ /* VPMACSDQHrr */ >+ }, >+ { /* 5188 */ >+ 338, >+ /* VPMACSDQLrm */ >+ }, >+ { /* 5189 */ >+ 339, >+ /* VPMACSDQLrr */ >+ }, >+ { /* 5190 */ >+ 338, >+ /* VPMACSSDDrm */ >+ }, >+ { /* 5191 */ >+ 339, >+ /* VPMACSSDDrr */ >+ }, >+ { /* 5192 */ >+ 338, >+ /* VPMACSSDQHrm */ >+ }, >+ { /* 5193 */ >+ 339, >+ /* VPMACSSDQHrr */ >+ }, >+ { /* 5194 */ >+ 338, >+ /* VPMACSSDQLrm */ >+ }, >+ { /* 5195 */ >+ 339, >+ /* VPMACSSDQLrr */ >+ }, >+ { /* 5196 */ >+ 338, >+ /* VPMACSSWDrm */ >+ }, >+ { /* 5197 */ >+ 339, >+ /* VPMACSSWDrr */ >+ }, >+ { /* 5198 */ >+ 338, >+ /* VPMACSSWWrm */ >+ }, >+ { /* 5199 */ >+ 339, >+ /* VPMACSSWWrr */ >+ }, >+ { /* 5200 */ >+ 338, >+ /* VPMACSWDrm */ >+ }, >+ { /* 5201 */ >+ 339, >+ /* VPMACSWDrr */ >+ }, >+ { /* 5202 */ >+ 338, >+ /* VPMACSWWrm */ >+ }, >+ { /* 5203 */ >+ 339, >+ /* VPMACSWWrr */ >+ }, >+ { /* 5204 */ >+ 338, >+ /* VPMADCSSWDrm */ >+ }, >+ { /* 5205 */ >+ 339, >+ /* VPMADCSSWDrr */ >+ }, >+ { /* 5206 */ >+ 338, >+ /* VPMADCSWDrm */ >+ }, >+ { /* 5207 */ >+ 339, >+ /* VPMADCSWDrr */ >+ }, >+ { /* 5208 */ >+ 312, >+ /* VPMADDUBSWrm128 */ >+ }, >+ { /* 5209 */ >+ 304, >+ /* VPMADDUBSWrm256 */ >+ }, >+ { /* 5210 */ >+ 313, >+ /* VPMADDUBSWrr128 */ >+ }, >+ { /* 5211 */ >+ 305, >+ /* VPMADDUBSWrr256 */ >+ }, >+ { /* 5212 */ >+ 304, >+ /* VPMADDWDYrm */ >+ }, >+ { /* 5213 */ >+ 305, >+ /* VPMADDWDYrr */ >+ }, >+ { /* 5214 */ >+ 312, >+ /* VPMADDWDrm */ >+ }, >+ { /* 5215 */ >+ 313, >+ /* VPMADDWDrr */ >+ }, >+ { /* 5216 */ >+ 483, >+ /* VPMASKMOVDYmr */ >+ }, >+ { /* 5217 */ >+ 304, >+ /* VPMASKMOVDYrm */ >+ }, >+ { /* 5218 */ >+ 484, >+ /* VPMASKMOVDmr */ >+ }, >+ { /* 5219 */ >+ 312, >+ /* VPMASKMOVDrm */ >+ }, >+ { /* 5220 */ >+ 483, >+ /* VPMASKMOVQYmr */ >+ }, >+ { /* 5221 */ >+ 304, >+ /* VPMASKMOVQYrm */ >+ }, >+ { /* 5222 */ >+ 484, >+ /* VPMASKMOVQmr */ >+ }, >+ { /* 5223 */ >+ 312, >+ /* VPMASKMOVQrm */ >+ }, >+ { /* 5224 */ >+ 304, >+ /* VPMAXSBYrm */ >+ }, >+ { /* 5225 */ >+ 305, >+ /* VPMAXSBYrr */ >+ }, >+ { /* 5226 */ >+ 312, >+ /* VPMAXSBrm */ >+ }, >+ { /* 5227 */ >+ 313, >+ /* VPMAXSBrr */ >+ }, >+ { /* 5228 */ >+ 304, >+ /* VPMAXSDYrm */ >+ }, >+ { /* 5229 */ >+ 305, >+ /* VPMAXSDYrr */ >+ }, >+ { /* 5230 */ >+ 306, >+ /* VPMAXSDZrm */ >+ }, >+ { /* 5231 */ >+ 585, >+ /* VPMAXSDZrmb */ >+ }, >+ { /* 5232 */ >+ 586, >+ /* VPMAXSDZrmbk */ >+ }, >+ { /* 5233 */ >+ 587, >+ /* VPMAXSDZrmbkz */ >+ }, >+ { /* 5234 */ >+ 588, >+ /* VPMAXSDZrmk */ >+ }, >+ { /* 5235 */ >+ 316, >+ /* VPMAXSDZrmkz */ >+ }, >+ { /* 5236 */ >+ 310, >+ /* VPMAXSDZrr */ >+ }, >+ { /* 5237 */ >+ 439, >+ /* VPMAXSDZrrk */ >+ }, >+ { /* 5238 */ >+ 317, >+ /* VPMAXSDZrrkz */ >+ }, >+ { /* 5239 */ >+ 312, >+ /* VPMAXSDrm */ >+ }, >+ { /* 5240 */ >+ 313, >+ /* VPMAXSDrr */ >+ }, >+ { /* 5241 */ >+ 306, >+ /* VPMAXSQZrm */ >+ }, >+ { /* 5242 */ >+ 589, >+ /* VPMAXSQZrmb */ >+ }, >+ { /* 5243 */ >+ 590, >+ /* VPMAXSQZrmbk */ >+ }, >+ { /* 5244 */ >+ 591, >+ /* VPMAXSQZrmbkz */ >+ }, >+ { /* 5245 */ >+ 592, >+ /* VPMAXSQZrmk */ >+ }, >+ { /* 5246 */ >+ 309, >+ /* VPMAXSQZrmkz */ >+ }, >+ { /* 5247 */ >+ 310, >+ /* VPMAXSQZrr */ >+ }, >+ { /* 5248 */ >+ 438, >+ /* VPMAXSQZrrk */ >+ }, >+ { /* 5249 */ >+ 311, >+ /* VPMAXSQZrrkz */ >+ }, >+ { /* 5250 */ >+ 304, >+ /* VPMAXSWYrm */ >+ }, >+ { /* 5251 */ >+ 305, >+ /* VPMAXSWYrr */ >+ }, >+ { /* 5252 */ >+ 312, >+ /* VPMAXSWrm */ >+ }, >+ { /* 5253 */ >+ 313, >+ /* VPMAXSWrr */ >+ }, >+ { /* 5254 */ >+ 304, >+ /* VPMAXUBYrm */ >+ }, >+ { /* 5255 */ >+ 305, >+ /* VPMAXUBYrr */ >+ }, >+ { /* 5256 */ >+ 312, >+ /* VPMAXUBrm */ >+ }, >+ { /* 5257 */ >+ 313, >+ /* VPMAXUBrr */ >+ }, >+ { /* 5258 */ >+ 304, >+ /* VPMAXUDYrm */ >+ }, >+ { /* 5259 */ >+ 305, >+ /* VPMAXUDYrr */ >+ }, >+ { /* 5260 */ >+ 306, >+ /* VPMAXUDZrm */ >+ }, >+ { /* 5261 */ >+ 585, >+ /* VPMAXUDZrmb */ >+ }, >+ { /* 5262 */ >+ 586, >+ /* VPMAXUDZrmbk */ >+ }, >+ { /* 5263 */ >+ 587, >+ /* VPMAXUDZrmbkz */ >+ }, >+ { /* 5264 */ >+ 588, >+ /* VPMAXUDZrmk */ >+ }, >+ { /* 5265 */ >+ 316, >+ /* VPMAXUDZrmkz */ >+ }, >+ { /* 5266 */ >+ 310, >+ /* VPMAXUDZrr */ >+ }, >+ { /* 5267 */ >+ 439, >+ /* VPMAXUDZrrk */ >+ }, >+ { /* 5268 */ >+ 317, >+ /* VPMAXUDZrrkz */ >+ }, >+ { /* 5269 */ >+ 312, >+ /* VPMAXUDrm */ >+ }, >+ { /* 5270 */ >+ 313, >+ /* VPMAXUDrr */ >+ }, >+ { /* 5271 */ >+ 306, >+ /* VPMAXUQZrm */ >+ }, >+ { /* 5272 */ >+ 589, >+ /* VPMAXUQZrmb */ >+ }, >+ { /* 5273 */ >+ 590, >+ /* VPMAXUQZrmbk */ >+ }, >+ { /* 5274 */ >+ 591, >+ /* VPMAXUQZrmbkz */ >+ }, >+ { /* 5275 */ >+ 592, >+ /* VPMAXUQZrmk */ >+ }, >+ { /* 5276 */ >+ 309, >+ /* VPMAXUQZrmkz */ >+ }, >+ { /* 5277 */ >+ 310, >+ /* VPMAXUQZrr */ >+ }, >+ { /* 5278 */ >+ 438, >+ /* VPMAXUQZrrk */ >+ }, >+ { /* 5279 */ >+ 311, >+ /* VPMAXUQZrrkz */ >+ }, >+ { /* 5280 */ >+ 304, >+ /* VPMAXUWYrm */ >+ }, >+ { /* 5281 */ >+ 305, >+ /* VPMAXUWYrr */ >+ }, >+ { /* 5282 */ >+ 312, >+ /* VPMAXUWrm */ >+ }, >+ { /* 5283 */ >+ 313, >+ /* VPMAXUWrr */ >+ }, >+ { /* 5284 */ >+ 304, >+ /* VPMINSBYrm */ >+ }, >+ { /* 5285 */ >+ 305, >+ /* VPMINSBYrr */ >+ }, >+ { /* 5286 */ >+ 312, >+ /* VPMINSBrm */ >+ }, >+ { /* 5287 */ >+ 313, >+ /* VPMINSBrr */ >+ }, >+ { /* 5288 */ >+ 304, >+ /* VPMINSDYrm */ >+ }, >+ { /* 5289 */ >+ 305, >+ /* VPMINSDYrr */ >+ }, >+ { /* 5290 */ >+ 306, >+ /* VPMINSDZrm */ >+ }, >+ { /* 5291 */ >+ 585, >+ /* VPMINSDZrmb */ >+ }, >+ { /* 5292 */ >+ 586, >+ /* VPMINSDZrmbk */ >+ }, >+ { /* 5293 */ >+ 587, >+ /* VPMINSDZrmbkz */ >+ }, >+ { /* 5294 */ >+ 588, >+ /* VPMINSDZrmk */ >+ }, >+ { /* 5295 */ >+ 316, >+ /* VPMINSDZrmkz */ >+ }, >+ { /* 5296 */ >+ 310, >+ /* VPMINSDZrr */ >+ }, >+ { /* 5297 */ >+ 439, >+ /* VPMINSDZrrk */ >+ }, >+ { /* 5298 */ >+ 317, >+ /* VPMINSDZrrkz */ >+ }, >+ { /* 5299 */ >+ 312, >+ /* VPMINSDrm */ >+ }, >+ { /* 5300 */ >+ 313, >+ /* VPMINSDrr */ >+ }, >+ { /* 5301 */ >+ 306, >+ /* VPMINSQZrm */ >+ }, >+ { /* 5302 */ >+ 589, >+ /* VPMINSQZrmb */ >+ }, >+ { /* 5303 */ >+ 590, >+ /* VPMINSQZrmbk */ >+ }, >+ { /* 5304 */ >+ 591, >+ /* VPMINSQZrmbkz */ >+ }, >+ { /* 5305 */ >+ 592, >+ /* VPMINSQZrmk */ >+ }, >+ { /* 5306 */ >+ 309, >+ /* VPMINSQZrmkz */ >+ }, >+ { /* 5307 */ >+ 310, >+ /* VPMINSQZrr */ >+ }, >+ { /* 5308 */ >+ 438, >+ /* VPMINSQZrrk */ >+ }, >+ { /* 5309 */ >+ 311, >+ /* VPMINSQZrrkz */ >+ }, >+ { /* 5310 */ >+ 304, >+ /* VPMINSWYrm */ >+ }, >+ { /* 5311 */ >+ 305, >+ /* VPMINSWYrr */ >+ }, >+ { /* 5312 */ >+ 312, >+ /* VPMINSWrm */ >+ }, >+ { /* 5313 */ >+ 313, >+ /* VPMINSWrr */ >+ }, >+ { /* 5314 */ >+ 304, >+ /* VPMINUBYrm */ >+ }, >+ { /* 5315 */ >+ 305, >+ /* VPMINUBYrr */ >+ }, >+ { /* 5316 */ >+ 312, >+ /* VPMINUBrm */ >+ }, >+ { /* 5317 */ >+ 313, >+ /* VPMINUBrr */ >+ }, >+ { /* 5318 */ >+ 304, >+ /* VPMINUDYrm */ >+ }, >+ { /* 5319 */ >+ 305, >+ /* VPMINUDYrr */ >+ }, >+ { /* 5320 */ >+ 306, >+ /* VPMINUDZrm */ >+ }, >+ { /* 5321 */ >+ 585, >+ /* VPMINUDZrmb */ >+ }, >+ { /* 5322 */ >+ 586, >+ /* VPMINUDZrmbk */ >+ }, >+ { /* 5323 */ >+ 587, >+ /* VPMINUDZrmbkz */ >+ }, >+ { /* 5324 */ >+ 588, >+ /* VPMINUDZrmk */ >+ }, >+ { /* 5325 */ >+ 316, >+ /* VPMINUDZrmkz */ >+ }, >+ { /* 5326 */ >+ 310, >+ /* VPMINUDZrr */ >+ }, >+ { /* 5327 */ >+ 439, >+ /* VPMINUDZrrk */ >+ }, >+ { /* 5328 */ >+ 317, >+ /* VPMINUDZrrkz */ >+ }, >+ { /* 5329 */ >+ 312, >+ /* VPMINUDrm */ >+ }, >+ { /* 5330 */ >+ 313, >+ /* VPMINUDrr */ >+ }, >+ { /* 5331 */ >+ 306, >+ /* VPMINUQZrm */ >+ }, >+ { /* 5332 */ >+ 589, >+ /* VPMINUQZrmb */ >+ }, >+ { /* 5333 */ >+ 590, >+ /* VPMINUQZrmbk */ >+ }, >+ { /* 5334 */ >+ 591, >+ /* VPMINUQZrmbkz */ >+ }, >+ { /* 5335 */ >+ 592, >+ /* VPMINUQZrmk */ >+ }, >+ { /* 5336 */ >+ 309, >+ /* VPMINUQZrmkz */ >+ }, >+ { /* 5337 */ >+ 310, >+ /* VPMINUQZrr */ >+ }, >+ { /* 5338 */ >+ 438, >+ /* VPMINUQZrrk */ >+ }, >+ { /* 5339 */ >+ 311, >+ /* VPMINUQZrrkz */ >+ }, >+ { /* 5340 */ >+ 304, >+ /* VPMINUWYrm */ >+ }, >+ { /* 5341 */ >+ 305, >+ /* VPMINUWYrr */ >+ }, >+ { /* 5342 */ >+ 312, >+ /* VPMINUWrm */ >+ }, >+ { /* 5343 */ >+ 313, >+ /* VPMINUWrr */ >+ }, >+ { /* 5344 */ >+ 684, >+ /* VPMOVDBmr */ >+ }, >+ { /* 5345 */ >+ 685, >+ /* VPMOVDBmrk */ >+ }, >+ { /* 5346 */ >+ 686, >+ /* VPMOVDBrr */ >+ }, >+ { /* 5347 */ >+ 687, >+ /* VPMOVDBrrk */ >+ }, >+ { /* 5348 */ >+ 687, >+ /* VPMOVDBrrkz */ >+ }, >+ { /* 5349 */ >+ 688, >+ /* VPMOVDWmr */ >+ }, >+ { /* 5350 */ >+ 689, >+ /* VPMOVDWmrk */ >+ }, >+ { /* 5351 */ >+ 690, >+ /* VPMOVDWrr */ >+ }, >+ { /* 5352 */ >+ 691, >+ /* VPMOVDWrrk */ >+ }, >+ { /* 5353 */ >+ 691, >+ /* VPMOVDWrrkz */ >+ }, >+ { /* 5354 */ >+ 559, >+ /* VPMOVMSKBYrr */ >+ }, >+ { /* 5355 */ >+ 110, >+ /* VPMOVMSKBrr */ >+ }, >+ { /* 5356 */ >+ 692, >+ /* VPMOVQBmr */ >+ }, >+ { /* 5357 */ >+ 693, >+ /* VPMOVQBmrk */ >+ }, >+ { /* 5358 */ >+ 694, >+ /* VPMOVQBrr */ >+ }, >+ { /* 5359 */ >+ 695, >+ /* VPMOVQBrrk */ >+ }, >+ { /* 5360 */ >+ 695, >+ /* VPMOVQBrrkz */ >+ }, >+ { /* 5361 */ >+ 688, >+ /* VPMOVQDmr */ >+ }, >+ { /* 5362 */ >+ 696, >+ /* VPMOVQDmrk */ >+ }, >+ { /* 5363 */ >+ 690, >+ /* VPMOVQDrr */ >+ }, >+ { /* 5364 */ >+ 697, >+ /* VPMOVQDrrk */ >+ }, >+ { /* 5365 */ >+ 697, >+ /* VPMOVQDrrkz */ >+ }, >+ { /* 5366 */ >+ 684, >+ /* VPMOVQWmr */ >+ }, >+ { /* 5367 */ >+ 698, >+ /* VPMOVQWmrk */ >+ }, >+ { /* 5368 */ >+ 686, >+ /* VPMOVQWrr */ >+ }, >+ { /* 5369 */ >+ 699, >+ /* VPMOVQWrrk */ >+ }, >+ { /* 5370 */ >+ 699, >+ /* VPMOVQWrrkz */ >+ }, >+ { /* 5371 */ >+ 684, >+ /* VPMOVSDBmr */ >+ }, >+ { /* 5372 */ >+ 685, >+ /* VPMOVSDBmrk */ >+ }, >+ { /* 5373 */ >+ 686, >+ /* VPMOVSDBrr */ >+ }, >+ { /* 5374 */ >+ 687, >+ /* VPMOVSDBrrk */ >+ }, >+ { /* 5375 */ >+ 687, >+ /* VPMOVSDBrrkz */ >+ }, >+ { /* 5376 */ >+ 688, >+ /* VPMOVSDWmr */ >+ }, >+ { /* 5377 */ >+ 689, >+ /* VPMOVSDWmrk */ >+ }, >+ { /* 5378 */ >+ 690, >+ /* VPMOVSDWrr */ >+ }, >+ { /* 5379 */ >+ 691, >+ /* VPMOVSDWrrk */ >+ }, >+ { /* 5380 */ >+ 691, >+ /* VPMOVSDWrrkz */ >+ }, >+ { /* 5381 */ >+ 692, >+ /* VPMOVSQBmr */ >+ }, >+ { /* 5382 */ >+ 693, >+ /* VPMOVSQBmrk */ >+ }, >+ { /* 5383 */ >+ 694, >+ /* VPMOVSQBrr */ >+ }, >+ { /* 5384 */ >+ 695, >+ /* VPMOVSQBrrk */ >+ }, >+ { /* 5385 */ >+ 695, >+ /* VPMOVSQBrrkz */ >+ }, >+ { /* 5386 */ >+ 688, >+ /* VPMOVSQDmr */ >+ }, >+ { /* 5387 */ >+ 696, >+ /* VPMOVSQDmrk */ >+ }, >+ { /* 5388 */ >+ 690, >+ /* VPMOVSQDrr */ >+ }, >+ { /* 5389 */ >+ 697, >+ /* VPMOVSQDrrk */ >+ }, >+ { /* 5390 */ >+ 697, >+ /* VPMOVSQDrrkz */ >+ }, >+ { /* 5391 */ >+ 684, >+ /* VPMOVSQWmr */ >+ }, >+ { /* 5392 */ >+ 698, >+ /* VPMOVSQWmrk */ >+ }, >+ { /* 5393 */ >+ 686, >+ /* VPMOVSQWrr */ >+ }, >+ { /* 5394 */ >+ 699, >+ /* VPMOVSQWrrk */ >+ }, >+ { /* 5395 */ >+ 699, >+ /* VPMOVSQWrrkz */ >+ }, >+ { /* 5396 */ >+ 599, >+ /* VPMOVSXBDYrm */ >+ }, >+ { /* 5397 */ >+ 346, >+ /* VPMOVSXBDYrr */ >+ }, >+ { /* 5398 */ >+ 342, >+ /* VPMOVSXBDZrm */ >+ }, >+ { /* 5399 */ >+ 341, >+ /* VPMOVSXBDZrmk */ >+ }, >+ { /* 5400 */ >+ 341, >+ /* VPMOVSXBDZrmkz */ >+ }, >+ { /* 5401 */ >+ 700, >+ /* VPMOVSXBDZrr */ >+ }, >+ { /* 5402 */ >+ 701, >+ /* VPMOVSXBDZrrk */ >+ }, >+ { /* 5403 */ >+ 701, >+ /* VPMOVSXBDZrrkz */ >+ }, >+ { /* 5404 */ >+ 105, >+ /* VPMOVSXBDrm */ >+ }, >+ { /* 5405 */ >+ 45, >+ /* VPMOVSXBDrr */ >+ }, >+ { /* 5406 */ >+ 599, >+ /* VPMOVSXBQYrm */ >+ }, >+ { /* 5407 */ >+ 346, >+ /* VPMOVSXBQYrr */ >+ }, >+ { /* 5408 */ >+ 702, >+ /* VPMOVSXBQZrm */ >+ }, >+ { /* 5409 */ >+ 703, >+ /* VPMOVSXBQZrmk */ >+ }, >+ { /* 5410 */ >+ 703, >+ /* VPMOVSXBQZrmkz */ >+ }, >+ { /* 5411 */ >+ 348, >+ /* VPMOVSXBQZrr */ >+ }, >+ { /* 5412 */ >+ 605, >+ /* VPMOVSXBQZrrk */ >+ }, >+ { /* 5413 */ >+ 605, >+ /* VPMOVSXBQZrrkz */ >+ }, >+ { /* 5414 */ >+ 105, >+ /* VPMOVSXBQrm */ >+ }, >+ { /* 5415 */ >+ 45, >+ /* VPMOVSXBQrr */ >+ }, >+ { /* 5416 */ >+ 340, >+ /* VPMOVSXBWYrm */ >+ }, >+ { /* 5417 */ >+ 346, >+ /* VPMOVSXBWYrr */ >+ }, >+ { /* 5418 */ >+ 105, >+ /* VPMOVSXBWrm */ >+ }, >+ { /* 5419 */ >+ 45, >+ /* VPMOVSXBWrr */ >+ }, >+ { /* 5420 */ >+ 340, >+ /* VPMOVSXDQYrm */ >+ }, >+ { /* 5421 */ >+ 346, >+ /* VPMOVSXDQYrr */ >+ }, >+ { /* 5422 */ >+ 344, >+ /* VPMOVSXDQZrm */ >+ }, >+ { /* 5423 */ >+ 704, >+ /* VPMOVSXDQZrmk */ >+ }, >+ { /* 5424 */ >+ 704, >+ /* VPMOVSXDQZrmkz */ >+ }, >+ { /* 5425 */ >+ 375, >+ /* VPMOVSXDQZrr */ >+ }, >+ { /* 5426 */ >+ 705, >+ /* VPMOVSXDQZrrk */ >+ }, >+ { /* 5427 */ >+ 705, >+ /* VPMOVSXDQZrrkz */ >+ }, >+ { /* 5428 */ >+ 105, >+ /* VPMOVSXDQrm */ >+ }, >+ { /* 5429 */ >+ 45, >+ /* VPMOVSXDQrr */ >+ }, >+ { /* 5430 */ >+ 340, >+ /* VPMOVSXWDYrm */ >+ }, >+ { /* 5431 */ >+ 346, >+ /* VPMOVSXWDYrr */ >+ }, >+ { /* 5432 */ >+ 344, >+ /* VPMOVSXWDZrm */ >+ }, >+ { /* 5433 */ >+ 343, >+ /* VPMOVSXWDZrmk */ >+ }, >+ { /* 5434 */ >+ 343, >+ /* VPMOVSXWDZrmkz */ >+ }, >+ { /* 5435 */ >+ 375, >+ /* VPMOVSXWDZrr */ >+ }, >+ { /* 5436 */ >+ 706, >+ /* VPMOVSXWDZrrk */ >+ }, >+ { /* 5437 */ >+ 706, >+ /* VPMOVSXWDZrrkz */ >+ }, >+ { /* 5438 */ >+ 105, >+ /* VPMOVSXWDrm */ >+ }, >+ { /* 5439 */ >+ 45, >+ /* VPMOVSXWDrr */ >+ }, >+ { /* 5440 */ >+ 599, >+ /* VPMOVSXWQYrm */ >+ }, >+ { /* 5441 */ >+ 346, >+ /* VPMOVSXWQYrr */ >+ }, >+ { /* 5442 */ >+ 342, >+ /* VPMOVSXWQZrm */ >+ }, >+ { /* 5443 */ >+ 707, >+ /* VPMOVSXWQZrmk */ >+ }, >+ { /* 5444 */ >+ 707, >+ /* VPMOVSXWQZrmkz */ >+ }, >+ { /* 5445 */ >+ 700, >+ /* VPMOVSXWQZrr */ >+ }, >+ { /* 5446 */ >+ 708, >+ /* VPMOVSXWQZrrk */ >+ }, >+ { /* 5447 */ >+ 708, >+ /* VPMOVSXWQZrrkz */ >+ }, >+ { /* 5448 */ >+ 105, >+ /* VPMOVSXWQrm */ >+ }, >+ { /* 5449 */ >+ 45, >+ /* VPMOVSXWQrr */ >+ }, >+ { /* 5450 */ >+ 684, >+ /* VPMOVUSDBmr */ >+ }, >+ { /* 5451 */ >+ 685, >+ /* VPMOVUSDBmrk */ >+ }, >+ { /* 5452 */ >+ 686, >+ /* VPMOVUSDBrr */ >+ }, >+ { /* 5453 */ >+ 687, >+ /* VPMOVUSDBrrk */ >+ }, >+ { /* 5454 */ >+ 687, >+ /* VPMOVUSDBrrkz */ >+ }, >+ { /* 5455 */ >+ 688, >+ /* VPMOVUSDWmr */ >+ }, >+ { /* 5456 */ >+ 689, >+ /* VPMOVUSDWmrk */ >+ }, >+ { /* 5457 */ >+ 690, >+ /* VPMOVUSDWrr */ >+ }, >+ { /* 5458 */ >+ 691, >+ /* VPMOVUSDWrrk */ >+ }, >+ { /* 5459 */ >+ 691, >+ /* VPMOVUSDWrrkz */ >+ }, >+ { /* 5460 */ >+ 692, >+ /* VPMOVUSQBmr */ >+ }, >+ { /* 5461 */ >+ 693, >+ /* VPMOVUSQBmrk */ >+ }, >+ { /* 5462 */ >+ 694, >+ /* VPMOVUSQBrr */ >+ }, >+ { /* 5463 */ >+ 695, >+ /* VPMOVUSQBrrk */ >+ }, >+ { /* 5464 */ >+ 695, >+ /* VPMOVUSQBrrkz */ >+ }, >+ { /* 5465 */ >+ 688, >+ /* VPMOVUSQDmr */ >+ }, >+ { /* 5466 */ >+ 696, >+ /* VPMOVUSQDmrk */ >+ }, >+ { /* 5467 */ >+ 690, >+ /* VPMOVUSQDrr */ >+ }, >+ { /* 5468 */ >+ 697, >+ /* VPMOVUSQDrrk */ >+ }, >+ { /* 5469 */ >+ 697, >+ /* VPMOVUSQDrrkz */ >+ }, >+ { /* 5470 */ >+ 684, >+ /* VPMOVUSQWmr */ >+ }, >+ { /* 5471 */ >+ 698, >+ /* VPMOVUSQWmrk */ >+ }, >+ { /* 5472 */ >+ 686, >+ /* VPMOVUSQWrr */ >+ }, >+ { /* 5473 */ >+ 699, >+ /* VPMOVUSQWrrk */ >+ }, >+ { /* 5474 */ >+ 699, >+ /* VPMOVUSQWrrkz */ >+ }, >+ { /* 5475 */ >+ 599, >+ /* VPMOVZXBDYrm */ >+ }, >+ { /* 5476 */ >+ 346, >+ /* VPMOVZXBDYrr */ >+ }, >+ { /* 5477 */ >+ 342, >+ /* VPMOVZXBDZrm */ >+ }, >+ { /* 5478 */ >+ 341, >+ /* VPMOVZXBDZrmk */ >+ }, >+ { /* 5479 */ >+ 341, >+ /* VPMOVZXBDZrmkz */ >+ }, >+ { /* 5480 */ >+ 700, >+ /* VPMOVZXBDZrr */ >+ }, >+ { /* 5481 */ >+ 701, >+ /* VPMOVZXBDZrrk */ >+ }, >+ { /* 5482 */ >+ 701, >+ /* VPMOVZXBDZrrkz */ >+ }, >+ { /* 5483 */ >+ 105, >+ /* VPMOVZXBDrm */ >+ }, >+ { /* 5484 */ >+ 45, >+ /* VPMOVZXBDrr */ >+ }, >+ { /* 5485 */ >+ 599, >+ /* VPMOVZXBQYrm */ >+ }, >+ { /* 5486 */ >+ 346, >+ /* VPMOVZXBQYrr */ >+ }, >+ { /* 5487 */ >+ 702, >+ /* VPMOVZXBQZrm */ >+ }, >+ { /* 5488 */ >+ 703, >+ /* VPMOVZXBQZrmk */ >+ }, >+ { /* 5489 */ >+ 703, >+ /* VPMOVZXBQZrmkz */ >+ }, >+ { /* 5490 */ >+ 348, >+ /* VPMOVZXBQZrr */ >+ }, >+ { /* 5491 */ >+ 605, >+ /* VPMOVZXBQZrrk */ >+ }, >+ { /* 5492 */ >+ 605, >+ /* VPMOVZXBQZrrkz */ >+ }, >+ { /* 5493 */ >+ 105, >+ /* VPMOVZXBQrm */ >+ }, >+ { /* 5494 */ >+ 45, >+ /* VPMOVZXBQrr */ >+ }, >+ { /* 5495 */ >+ 340, >+ /* VPMOVZXBWYrm */ >+ }, >+ { /* 5496 */ >+ 346, >+ /* VPMOVZXBWYrr */ >+ }, >+ { /* 5497 */ >+ 105, >+ /* VPMOVZXBWrm */ >+ }, >+ { /* 5498 */ >+ 45, >+ /* VPMOVZXBWrr */ >+ }, >+ { /* 5499 */ >+ 340, >+ /* VPMOVZXDQYrm */ >+ }, >+ { /* 5500 */ >+ 346, >+ /* VPMOVZXDQYrr */ >+ }, >+ { /* 5501 */ >+ 344, >+ /* VPMOVZXDQZrm */ >+ }, >+ { /* 5502 */ >+ 704, >+ /* VPMOVZXDQZrmk */ >+ }, >+ { /* 5503 */ >+ 704, >+ /* VPMOVZXDQZrmkz */ >+ }, >+ { /* 5504 */ >+ 375, >+ /* VPMOVZXDQZrr */ >+ }, >+ { /* 5505 */ >+ 705, >+ /* VPMOVZXDQZrrk */ >+ }, >+ { /* 5506 */ >+ 705, >+ /* VPMOVZXDQZrrkz */ >+ }, >+ { /* 5507 */ >+ 105, >+ /* VPMOVZXDQrm */ >+ }, >+ { /* 5508 */ >+ 45, >+ /* VPMOVZXDQrr */ >+ }, >+ { /* 5509 */ >+ 340, >+ /* VPMOVZXWDYrm */ >+ }, >+ { /* 5510 */ >+ 346, >+ /* VPMOVZXWDYrr */ >+ }, >+ { /* 5511 */ >+ 344, >+ /* VPMOVZXWDZrm */ >+ }, >+ { /* 5512 */ >+ 343, >+ /* VPMOVZXWDZrmk */ >+ }, >+ { /* 5513 */ >+ 343, >+ /* VPMOVZXWDZrmkz */ >+ }, >+ { /* 5514 */ >+ 375, >+ /* VPMOVZXWDZrr */ >+ }, >+ { /* 5515 */ >+ 706, >+ /* VPMOVZXWDZrrk */ >+ }, >+ { /* 5516 */ >+ 706, >+ /* VPMOVZXWDZrrkz */ >+ }, >+ { /* 5517 */ >+ 105, >+ /* VPMOVZXWDrm */ >+ }, >+ { /* 5518 */ >+ 45, >+ /* VPMOVZXWDrr */ >+ }, >+ { /* 5519 */ >+ 599, >+ /* VPMOVZXWQYrm */ >+ }, >+ { /* 5520 */ >+ 346, >+ /* VPMOVZXWQYrr */ >+ }, >+ { /* 5521 */ >+ 342, >+ /* VPMOVZXWQZrm */ >+ }, >+ { /* 5522 */ >+ 707, >+ /* VPMOVZXWQZrmk */ >+ }, >+ { /* 5523 */ >+ 707, >+ /* VPMOVZXWQZrmkz */ >+ }, >+ { /* 5524 */ >+ 700, >+ /* VPMOVZXWQZrr */ >+ }, >+ { /* 5525 */ >+ 708, >+ /* VPMOVZXWQZrrk */ >+ }, >+ { /* 5526 */ >+ 708, >+ /* VPMOVZXWQZrrkz */ >+ }, >+ { /* 5527 */ >+ 105, >+ /* VPMOVZXWQrm */ >+ }, >+ { /* 5528 */ >+ 45, >+ /* VPMOVZXWQrr */ >+ }, >+ { /* 5529 */ >+ 304, >+ /* VPMULDQYrm */ >+ }, >+ { /* 5530 */ >+ 305, >+ /* VPMULDQYrr */ >+ }, >+ { /* 5531 */ >+ 306, >+ /* VPMULDQZrm */ >+ }, >+ { /* 5532 */ >+ 589, >+ /* VPMULDQZrmb */ >+ }, >+ { /* 5533 */ >+ 591, >+ /* VPMULDQZrmbk */ >+ }, >+ { /* 5534 */ >+ 591, >+ /* VPMULDQZrmbkz */ >+ }, >+ { /* 5535 */ >+ 309, >+ /* VPMULDQZrmk */ >+ }, >+ { /* 5536 */ >+ 309, >+ /* VPMULDQZrmkz */ >+ }, >+ { /* 5537 */ >+ 310, >+ /* VPMULDQZrr */ >+ }, >+ { /* 5538 */ >+ 311, >+ /* VPMULDQZrrk */ >+ }, >+ { /* 5539 */ >+ 311, >+ /* VPMULDQZrrkz */ >+ }, >+ { /* 5540 */ >+ 312, >+ /* VPMULDQrm */ >+ }, >+ { /* 5541 */ >+ 313, >+ /* VPMULDQrr */ >+ }, >+ { /* 5542 */ >+ 312, >+ /* VPMULHRSWrm128 */ >+ }, >+ { /* 5543 */ >+ 304, >+ /* VPMULHRSWrm256 */ >+ }, >+ { /* 5544 */ >+ 313, >+ /* VPMULHRSWrr128 */ >+ }, >+ { /* 5545 */ >+ 305, >+ /* VPMULHRSWrr256 */ >+ }, >+ { /* 5546 */ >+ 304, >+ /* VPMULHUWYrm */ >+ }, >+ { /* 5547 */ >+ 305, >+ /* VPMULHUWYrr */ >+ }, >+ { /* 5548 */ >+ 312, >+ /* VPMULHUWrm */ >+ }, >+ { /* 5549 */ >+ 313, >+ /* VPMULHUWrr */ >+ }, >+ { /* 5550 */ >+ 304, >+ /* VPMULHWYrm */ >+ }, >+ { /* 5551 */ >+ 305, >+ /* VPMULHWYrr */ >+ }, >+ { /* 5552 */ >+ 312, >+ /* VPMULHWrm */ >+ }, >+ { /* 5553 */ >+ 313, >+ /* VPMULHWrr */ >+ }, >+ { /* 5554 */ >+ 304, >+ /* VPMULLDYrm */ >+ }, >+ { /* 5555 */ >+ 305, >+ /* VPMULLDYrr */ >+ }, >+ { /* 5556 */ >+ 306, >+ /* VPMULLDZrm */ >+ }, >+ { /* 5557 */ >+ 585, >+ /* VPMULLDZrmb */ >+ }, >+ { /* 5558 */ >+ 586, >+ /* VPMULLDZrmbk */ >+ }, >+ { /* 5559 */ >+ 587, >+ /* VPMULLDZrmbkz */ >+ }, >+ { /* 5560 */ >+ 588, >+ /* VPMULLDZrmk */ >+ }, >+ { /* 5561 */ >+ 316, >+ /* VPMULLDZrmkz */ >+ }, >+ { /* 5562 */ >+ 310, >+ /* VPMULLDZrr */ >+ }, >+ { /* 5563 */ >+ 439, >+ /* VPMULLDZrrk */ >+ }, >+ { /* 5564 */ >+ 317, >+ /* VPMULLDZrrkz */ >+ }, >+ { /* 5565 */ >+ 312, >+ /* VPMULLDrm */ >+ }, >+ { /* 5566 */ >+ 313, >+ /* VPMULLDrr */ >+ }, >+ { /* 5567 */ >+ 304, >+ /* VPMULLWYrm */ >+ }, >+ { /* 5568 */ >+ 305, >+ /* VPMULLWYrr */ >+ }, >+ { /* 5569 */ >+ 312, >+ /* VPMULLWrm */ >+ }, >+ { /* 5570 */ >+ 313, >+ /* VPMULLWrr */ >+ }, >+ { /* 5571 */ >+ 304, >+ /* VPMULUDQYrm */ >+ }, >+ { /* 5572 */ >+ 305, >+ /* VPMULUDQYrr */ >+ }, >+ { /* 5573 */ >+ 306, >+ /* VPMULUDQZrm */ >+ }, >+ { /* 5574 */ >+ 589, >+ /* VPMULUDQZrmb */ >+ }, >+ { /* 5575 */ >+ 591, >+ /* VPMULUDQZrmbk */ >+ }, >+ { /* 5576 */ >+ 591, >+ /* VPMULUDQZrmbkz */ >+ }, >+ { /* 5577 */ >+ 309, >+ /* VPMULUDQZrmk */ >+ }, >+ { /* 5578 */ >+ 309, >+ /* VPMULUDQZrmkz */ >+ }, >+ { /* 5579 */ >+ 310, >+ /* VPMULUDQZrr */ >+ }, >+ { /* 5580 */ >+ 311, >+ /* VPMULUDQZrrk */ >+ }, >+ { /* 5581 */ >+ 311, >+ /* VPMULUDQZrrkz */ >+ }, >+ { /* 5582 */ >+ 312, >+ /* VPMULUDQrm */ >+ }, >+ { /* 5583 */ >+ 313, >+ /* VPMULUDQrr */ >+ }, >+ { /* 5584 */ >+ 306, >+ /* VPORDZrm */ >+ }, >+ { /* 5585 */ >+ 585, >+ /* VPORDZrmb */ >+ }, >+ { /* 5586 */ >+ 586, >+ /* VPORDZrmbk */ >+ }, >+ { /* 5587 */ >+ 587, >+ /* VPORDZrmbkz */ >+ }, >+ { /* 5588 */ >+ 588, >+ /* VPORDZrmk */ >+ }, >+ { /* 5589 */ >+ 316, >+ /* VPORDZrmkz */ >+ }, >+ { /* 5590 */ >+ 310, >+ /* VPORDZrr */ >+ }, >+ { /* 5591 */ >+ 439, >+ /* VPORDZrrk */ >+ }, >+ { /* 5592 */ >+ 317, >+ /* VPORDZrrkz */ >+ }, >+ { /* 5593 */ >+ 306, >+ /* VPORQZrm */ >+ }, >+ { /* 5594 */ >+ 589, >+ /* VPORQZrmb */ >+ }, >+ { /* 5595 */ >+ 590, >+ /* VPORQZrmbk */ >+ }, >+ { /* 5596 */ >+ 591, >+ /* VPORQZrmbkz */ >+ }, >+ { /* 5597 */ >+ 592, >+ /* VPORQZrmk */ >+ }, >+ { /* 5598 */ >+ 309, >+ /* VPORQZrmkz */ >+ }, >+ { /* 5599 */ >+ 310, >+ /* VPORQZrr */ >+ }, >+ { /* 5600 */ >+ 438, >+ /* VPORQZrrk */ >+ }, >+ { /* 5601 */ >+ 311, >+ /* VPORQZrrkz */ >+ }, >+ { /* 5602 */ >+ 304, >+ /* VPORYrm */ >+ }, >+ { /* 5603 */ >+ 305, >+ /* VPORYrr */ >+ }, >+ { /* 5604 */ >+ 312, >+ /* VPORrm */ >+ }, >+ { /* 5605 */ >+ 313, >+ /* VPORrr */ >+ }, >+ { /* 5606 */ >+ 338, >+ /* VPPERMmr */ >+ }, >+ { /* 5607 */ >+ 440, >+ /* VPPERMrm */ >+ }, >+ { /* 5608 */ >+ 339, >+ /* VPPERMrr */ >+ }, >+ { /* 5609 */ >+ 46, >+ /* VPROTBmi */ >+ }, >+ { /* 5610 */ >+ 709, >+ /* VPROTBmr */ >+ }, >+ { /* 5611 */ >+ 47, >+ /* VPROTBri */ >+ }, >+ { /* 5612 */ >+ 312, >+ /* VPROTBrm */ >+ }, >+ { /* 5613 */ >+ 710, >+ /* VPROTBrr */ >+ }, >+ { /* 5614 */ >+ 46, >+ /* VPROTDmi */ >+ }, >+ { /* 5615 */ >+ 709, >+ /* VPROTDmr */ >+ }, >+ { /* 5616 */ >+ 47, >+ /* VPROTDri */ >+ }, >+ { /* 5617 */ >+ 312, >+ /* VPROTDrm */ >+ }, >+ { /* 5618 */ >+ 710, >+ /* VPROTDrr */ >+ }, >+ { /* 5619 */ >+ 46, >+ /* VPROTQmi */ >+ }, >+ { /* 5620 */ >+ 709, >+ /* VPROTQmr */ >+ }, >+ { /* 5621 */ >+ 47, >+ /* VPROTQri */ >+ }, >+ { /* 5622 */ >+ 312, >+ /* VPROTQrm */ >+ }, >+ { /* 5623 */ >+ 710, >+ /* VPROTQrr */ >+ }, >+ { /* 5624 */ >+ 46, >+ /* VPROTWmi */ >+ }, >+ { /* 5625 */ >+ 709, >+ /* VPROTWmr */ >+ }, >+ { /* 5626 */ >+ 47, >+ /* VPROTWri */ >+ }, >+ { /* 5627 */ >+ 312, >+ /* VPROTWrm */ >+ }, >+ { /* 5628 */ >+ 710, >+ /* VPROTWrr */ >+ }, >+ { /* 5629 */ >+ 304, >+ /* VPSADBWYrm */ >+ }, >+ { /* 5630 */ >+ 305, >+ /* VPSADBWYrr */ >+ }, >+ { /* 5631 */ >+ 312, >+ /* VPSADBWrm */ >+ }, >+ { /* 5632 */ >+ 313, >+ /* VPSADBWrr */ >+ }, >+ { /* 5633 */ >+ 711, >+ /* VPSCATTERDDZmr */ >+ }, >+ { /* 5634 */ >+ 712, >+ /* VPSCATTERDQZmr */ >+ }, >+ { /* 5635 */ >+ 713, >+ /* VPSCATTERQDZmr */ >+ }, >+ { /* 5636 */ >+ 712, >+ /* VPSCATTERQQZmr */ >+ }, >+ { /* 5637 */ >+ 709, >+ /* VPSHABmr */ >+ }, >+ { /* 5638 */ >+ 312, >+ /* VPSHABrm */ >+ }, >+ { /* 5639 */ >+ 710, >+ /* VPSHABrr */ >+ }, >+ { /* 5640 */ >+ 709, >+ /* VPSHADmr */ >+ }, >+ { /* 5641 */ >+ 312, >+ /* VPSHADrm */ >+ }, >+ { /* 5642 */ >+ 710, >+ /* VPSHADrr */ >+ }, >+ { /* 5643 */ >+ 709, >+ /* VPSHAQmr */ >+ }, >+ { /* 5644 */ >+ 312, >+ /* VPSHAQrm */ >+ }, >+ { /* 5645 */ >+ 710, >+ /* VPSHAQrr */ >+ }, >+ { /* 5646 */ >+ 709, >+ /* VPSHAWmr */ >+ }, >+ { /* 5647 */ >+ 312, >+ /* VPSHAWrm */ >+ }, >+ { /* 5648 */ >+ 710, >+ /* VPSHAWrr */ >+ }, >+ { /* 5649 */ >+ 709, >+ /* VPSHLBmr */ >+ }, >+ { /* 5650 */ >+ 312, >+ /* VPSHLBrm */ >+ }, >+ { /* 5651 */ >+ 710, >+ /* VPSHLBrr */ >+ }, >+ { /* 5652 */ >+ 709, >+ /* VPSHLDmr */ >+ }, >+ { /* 5653 */ >+ 312, >+ /* VPSHLDrm */ >+ }, >+ { /* 5654 */ >+ 710, >+ /* VPSHLDrr */ >+ }, >+ { /* 5655 */ >+ 709, >+ /* VPSHLQmr */ >+ }, >+ { /* 5656 */ >+ 312, >+ /* VPSHLQrm */ >+ }, >+ { /* 5657 */ >+ 710, >+ /* VPSHLQrr */ >+ }, >+ { /* 5658 */ >+ 709, >+ /* VPSHLWmr */ >+ }, >+ { /* 5659 */ >+ 312, >+ /* VPSHLWrm */ >+ }, >+ { /* 5660 */ >+ 710, >+ /* VPSHLWrr */ >+ }, >+ { /* 5661 */ >+ 304, >+ /* VPSHUFBYrm */ >+ }, >+ { /* 5662 */ >+ 305, >+ /* VPSHUFBYrr */ >+ }, >+ { /* 5663 */ >+ 312, >+ /* VPSHUFBrm */ >+ }, >+ { /* 5664 */ >+ 313, >+ /* VPSHUFBrr */ >+ }, >+ { /* 5665 */ >+ 676, >+ /* VPSHUFDYmi */ >+ }, >+ { /* 5666 */ >+ 677, >+ /* VPSHUFDYri */ >+ }, >+ { /* 5667 */ >+ 678, >+ /* VPSHUFDZmi */ >+ }, >+ { /* 5668 */ >+ 679, >+ /* VPSHUFDZri */ >+ }, >+ { /* 5669 */ >+ 46, >+ /* VPSHUFDmi */ >+ }, >+ { /* 5670 */ >+ 47, >+ /* VPSHUFDri */ >+ }, >+ { /* 5671 */ >+ 676, >+ /* VPSHUFHWYmi */ >+ }, >+ { /* 5672 */ >+ 677, >+ /* VPSHUFHWYri */ >+ }, >+ { /* 5673 */ >+ 46, >+ /* VPSHUFHWmi */ >+ }, >+ { /* 5674 */ >+ 47, >+ /* VPSHUFHWri */ >+ }, >+ { /* 5675 */ >+ 676, >+ /* VPSHUFLWYmi */ >+ }, >+ { /* 5676 */ >+ 677, >+ /* VPSHUFLWYri */ >+ }, >+ { /* 5677 */ >+ 46, >+ /* VPSHUFLWmi */ >+ }, >+ { /* 5678 */ >+ 47, >+ /* VPSHUFLWri */ >+ }, >+ { /* 5679 */ >+ 304, >+ /* VPSIGNBYrm */ >+ }, >+ { /* 5680 */ >+ 305, >+ /* VPSIGNBYrr */ >+ }, >+ { /* 5681 */ >+ 312, >+ /* VPSIGNBrm */ >+ }, >+ { /* 5682 */ >+ 313, >+ /* VPSIGNBrr */ >+ }, >+ { /* 5683 */ >+ 304, >+ /* VPSIGNDYrm */ >+ }, >+ { /* 5684 */ >+ 305, >+ /* VPSIGNDYrr */ >+ }, >+ { /* 5685 */ >+ 312, >+ /* VPSIGNDrm */ >+ }, >+ { /* 5686 */ >+ 313, >+ /* VPSIGNDrr */ >+ }, >+ { /* 5687 */ >+ 304, >+ /* VPSIGNWYrm */ >+ }, >+ { /* 5688 */ >+ 305, >+ /* VPSIGNWYrr */ >+ }, >+ { /* 5689 */ >+ 312, >+ /* VPSIGNWrm */ >+ }, >+ { /* 5690 */ >+ 313, >+ /* VPSIGNWrr */ >+ }, >+ { /* 5691 */ >+ 714, >+ /* VPSLLDQYri */ >+ }, >+ { /* 5692 */ >+ 715, >+ /* VPSLLDQri */ >+ }, >+ { /* 5693 */ >+ 716, >+ /* VPSLLDYri */ >+ }, >+ { /* 5694 */ >+ 717, >+ /* VPSLLDYrm */ >+ }, >+ { /* 5695 */ >+ 718, >+ /* VPSLLDYrr */ >+ }, >+ { /* 5696 */ >+ 719, >+ /* VPSLLDZmi */ >+ }, >+ { /* 5697 */ >+ 720, >+ /* VPSLLDZmik */ >+ }, >+ { /* 5698 */ >+ 721, >+ /* VPSLLDZri */ >+ }, >+ { /* 5699 */ >+ 722, >+ /* VPSLLDZrik */ >+ }, >+ { /* 5700 */ >+ 723, >+ /* VPSLLDZrm */ >+ }, >+ { /* 5701 */ >+ 724, >+ /* VPSLLDZrmk */ >+ }, >+ { /* 5702 */ >+ 725, >+ /* VPSLLDZrr */ >+ }, >+ { /* 5703 */ >+ 726, >+ /* VPSLLDZrrk */ >+ }, >+ { /* 5704 */ >+ 727, >+ /* VPSLLDri */ >+ }, >+ { /* 5705 */ >+ 312, >+ /* VPSLLDrm */ >+ }, >+ { /* 5706 */ >+ 313, >+ /* VPSLLDrr */ >+ }, >+ { /* 5707 */ >+ 716, >+ /* VPSLLQYri */ >+ }, >+ { /* 5708 */ >+ 717, >+ /* VPSLLQYrm */ >+ }, >+ { /* 5709 */ >+ 718, >+ /* VPSLLQYrr */ >+ }, >+ { /* 5710 */ >+ 719, >+ /* VPSLLQZmi */ >+ }, >+ { /* 5711 */ >+ 728, >+ /* VPSLLQZmik */ >+ }, >+ { /* 5712 */ >+ 721, >+ /* VPSLLQZri */ >+ }, >+ { /* 5713 */ >+ 729, >+ /* VPSLLQZrik */ >+ }, >+ { /* 5714 */ >+ 723, >+ /* VPSLLQZrm */ >+ }, >+ { /* 5715 */ >+ 730, >+ /* VPSLLQZrmk */ >+ }, >+ { /* 5716 */ >+ 725, >+ /* VPSLLQZrr */ >+ }, >+ { /* 5717 */ >+ 731, >+ /* VPSLLQZrrk */ >+ }, >+ { /* 5718 */ >+ 727, >+ /* VPSLLQri */ >+ }, >+ { /* 5719 */ >+ 312, >+ /* VPSLLQrm */ >+ }, >+ { /* 5720 */ >+ 313, >+ /* VPSLLQrr */ >+ }, >+ { /* 5721 */ >+ 304, >+ /* VPSLLVDYrm */ >+ }, >+ { /* 5722 */ >+ 305, >+ /* VPSLLVDYrr */ >+ }, >+ { /* 5723 */ >+ 306, >+ /* VPSLLVDZrm */ >+ }, >+ { /* 5724 */ >+ 310, >+ /* VPSLLVDZrr */ >+ }, >+ { /* 5725 */ >+ 312, >+ /* VPSLLVDrm */ >+ }, >+ { /* 5726 */ >+ 313, >+ /* VPSLLVDrr */ >+ }, >+ { /* 5727 */ >+ 304, >+ /* VPSLLVQYrm */ >+ }, >+ { /* 5728 */ >+ 305, >+ /* VPSLLVQYrr */ >+ }, >+ { /* 5729 */ >+ 306, >+ /* VPSLLVQZrm */ >+ }, >+ { /* 5730 */ >+ 310, >+ /* VPSLLVQZrr */ >+ }, >+ { /* 5731 */ >+ 312, >+ /* VPSLLVQrm */ >+ }, >+ { /* 5732 */ >+ 313, >+ /* VPSLLVQrr */ >+ }, >+ { /* 5733 */ >+ 716, >+ /* VPSLLWYri */ >+ }, >+ { /* 5734 */ >+ 717, >+ /* VPSLLWYrm */ >+ }, >+ { /* 5735 */ >+ 718, >+ /* VPSLLWYrr */ >+ }, >+ { /* 5736 */ >+ 727, >+ /* VPSLLWri */ >+ }, >+ { /* 5737 */ >+ 312, >+ /* VPSLLWrm */ >+ }, >+ { /* 5738 */ >+ 313, >+ /* VPSLLWrr */ >+ }, >+ { /* 5739 */ >+ 716, >+ /* VPSRADYri */ >+ }, >+ { /* 5740 */ >+ 717, >+ /* VPSRADYrm */ >+ }, >+ { /* 5741 */ >+ 718, >+ /* VPSRADYrr */ >+ }, >+ { /* 5742 */ >+ 719, >+ /* VPSRADZmi */ >+ }, >+ { /* 5743 */ >+ 720, >+ /* VPSRADZmik */ >+ }, >+ { /* 5744 */ >+ 721, >+ /* VPSRADZri */ >+ }, >+ { /* 5745 */ >+ 722, >+ /* VPSRADZrik */ >+ }, >+ { /* 5746 */ >+ 723, >+ /* VPSRADZrm */ >+ }, >+ { /* 5747 */ >+ 724, >+ /* VPSRADZrmk */ >+ }, >+ { /* 5748 */ >+ 725, >+ /* VPSRADZrr */ >+ }, >+ { /* 5749 */ >+ 726, >+ /* VPSRADZrrk */ >+ }, >+ { /* 5750 */ >+ 727, >+ /* VPSRADri */ >+ }, >+ { /* 5751 */ >+ 312, >+ /* VPSRADrm */ >+ }, >+ { /* 5752 */ >+ 313, >+ /* VPSRADrr */ >+ }, >+ { /* 5753 */ >+ 719, >+ /* VPSRAQZmi */ >+ }, >+ { /* 5754 */ >+ 728, >+ /* VPSRAQZmik */ >+ }, >+ { /* 5755 */ >+ 721, >+ /* VPSRAQZri */ >+ }, >+ { /* 5756 */ >+ 729, >+ /* VPSRAQZrik */ >+ }, >+ { /* 5757 */ >+ 723, >+ /* VPSRAQZrm */ >+ }, >+ { /* 5758 */ >+ 730, >+ /* VPSRAQZrmk */ >+ }, >+ { /* 5759 */ >+ 725, >+ /* VPSRAQZrr */ >+ }, >+ { /* 5760 */ >+ 731, >+ /* VPSRAQZrrk */ >+ }, >+ { /* 5761 */ >+ 304, >+ /* VPSRAVDYrm */ >+ }, >+ { /* 5762 */ >+ 305, >+ /* VPSRAVDYrr */ >+ }, >+ { /* 5763 */ >+ 306, >+ /* VPSRAVDZrm */ >+ }, >+ { /* 5764 */ >+ 310, >+ /* VPSRAVDZrr */ >+ }, >+ { /* 5765 */ >+ 312, >+ /* VPSRAVDrm */ >+ }, >+ { /* 5766 */ >+ 313, >+ /* VPSRAVDrr */ >+ }, >+ { /* 5767 */ >+ 306, >+ /* VPSRAVQZrm */ >+ }, >+ { /* 5768 */ >+ 310, >+ /* VPSRAVQZrr */ >+ }, >+ { /* 5769 */ >+ 716, >+ /* VPSRAWYri */ >+ }, >+ { /* 5770 */ >+ 717, >+ /* VPSRAWYrm */ >+ }, >+ { /* 5771 */ >+ 718, >+ /* VPSRAWYrr */ >+ }, >+ { /* 5772 */ >+ 727, >+ /* VPSRAWri */ >+ }, >+ { /* 5773 */ >+ 312, >+ /* VPSRAWrm */ >+ }, >+ { /* 5774 */ >+ 313, >+ /* VPSRAWrr */ >+ }, >+ { /* 5775 */ >+ 714, >+ /* VPSRLDQYri */ >+ }, >+ { /* 5776 */ >+ 715, >+ /* VPSRLDQri */ >+ }, >+ { /* 5777 */ >+ 716, >+ /* VPSRLDYri */ >+ }, >+ { /* 5778 */ >+ 717, >+ /* VPSRLDYrm */ >+ }, >+ { /* 5779 */ >+ 718, >+ /* VPSRLDYrr */ >+ }, >+ { /* 5780 */ >+ 719, >+ /* VPSRLDZmi */ >+ }, >+ { /* 5781 */ >+ 720, >+ /* VPSRLDZmik */ >+ }, >+ { /* 5782 */ >+ 721, >+ /* VPSRLDZri */ >+ }, >+ { /* 5783 */ >+ 722, >+ /* VPSRLDZrik */ >+ }, >+ { /* 5784 */ >+ 723, >+ /* VPSRLDZrm */ >+ }, >+ { /* 5785 */ >+ 724, >+ /* VPSRLDZrmk */ >+ }, >+ { /* 5786 */ >+ 725, >+ /* VPSRLDZrr */ >+ }, >+ { /* 5787 */ >+ 726, >+ /* VPSRLDZrrk */ >+ }, >+ { /* 5788 */ >+ 727, >+ /* VPSRLDri */ >+ }, >+ { /* 5789 */ >+ 312, >+ /* VPSRLDrm */ >+ }, >+ { /* 5790 */ >+ 313, >+ /* VPSRLDrr */ >+ }, >+ { /* 5791 */ >+ 716, >+ /* VPSRLQYri */ >+ }, >+ { /* 5792 */ >+ 717, >+ /* VPSRLQYrm */ >+ }, >+ { /* 5793 */ >+ 718, >+ /* VPSRLQYrr */ >+ }, >+ { /* 5794 */ >+ 719, >+ /* VPSRLQZmi */ >+ }, >+ { /* 5795 */ >+ 728, >+ /* VPSRLQZmik */ >+ }, >+ { /* 5796 */ >+ 721, >+ /* VPSRLQZri */ >+ }, >+ { /* 5797 */ >+ 729, >+ /* VPSRLQZrik */ >+ }, >+ { /* 5798 */ >+ 723, >+ /* VPSRLQZrm */ >+ }, >+ { /* 5799 */ >+ 730, >+ /* VPSRLQZrmk */ >+ }, >+ { /* 5800 */ >+ 725, >+ /* VPSRLQZrr */ >+ }, >+ { /* 5801 */ >+ 731, >+ /* VPSRLQZrrk */ >+ }, >+ { /* 5802 */ >+ 727, >+ /* VPSRLQri */ >+ }, >+ { /* 5803 */ >+ 312, >+ /* VPSRLQrm */ >+ }, >+ { /* 5804 */ >+ 313, >+ /* VPSRLQrr */ >+ }, >+ { /* 5805 */ >+ 304, >+ /* VPSRLVDYrm */ >+ }, >+ { /* 5806 */ >+ 305, >+ /* VPSRLVDYrr */ >+ }, >+ { /* 5807 */ >+ 306, >+ /* VPSRLVDZrm */ >+ }, >+ { /* 5808 */ >+ 310, >+ /* VPSRLVDZrr */ >+ }, >+ { /* 5809 */ >+ 312, >+ /* VPSRLVDrm */ >+ }, >+ { /* 5810 */ >+ 313, >+ /* VPSRLVDrr */ >+ }, >+ { /* 5811 */ >+ 304, >+ /* VPSRLVQYrm */ >+ }, >+ { /* 5812 */ >+ 305, >+ /* VPSRLVQYrr */ >+ }, >+ { /* 5813 */ >+ 306, >+ /* VPSRLVQZrm */ >+ }, >+ { /* 5814 */ >+ 310, >+ /* VPSRLVQZrr */ >+ }, >+ { /* 5815 */ >+ 312, >+ /* VPSRLVQrm */ >+ }, >+ { /* 5816 */ >+ 313, >+ /* VPSRLVQrr */ >+ }, >+ { /* 5817 */ >+ 716, >+ /* VPSRLWYri */ >+ }, >+ { /* 5818 */ >+ 717, >+ /* VPSRLWYrm */ >+ }, >+ { /* 5819 */ >+ 718, >+ /* VPSRLWYrr */ >+ }, >+ { /* 5820 */ >+ 727, >+ /* VPSRLWri */ >+ }, >+ { /* 5821 */ >+ 312, >+ /* VPSRLWrm */ >+ }, >+ { /* 5822 */ >+ 313, >+ /* VPSRLWrr */ >+ }, >+ { /* 5823 */ >+ 304, >+ /* VPSUBBYrm */ >+ }, >+ { /* 5824 */ >+ 305, >+ /* VPSUBBYrr */ >+ }, >+ { /* 5825 */ >+ 312, >+ /* VPSUBBrm */ >+ }, >+ { /* 5826 */ >+ 313, >+ /* VPSUBBrr */ >+ }, >+ { /* 5827 */ >+ 304, >+ /* VPSUBDYrm */ >+ }, >+ { /* 5828 */ >+ 305, >+ /* VPSUBDYrr */ >+ }, >+ { /* 5829 */ >+ 306, >+ /* VPSUBDZrm */ >+ }, >+ { /* 5830 */ >+ 585, >+ /* VPSUBDZrmb */ >+ }, >+ { /* 5831 */ >+ 586, >+ /* VPSUBDZrmbk */ >+ }, >+ { /* 5832 */ >+ 587, >+ /* VPSUBDZrmbkz */ >+ }, >+ { /* 5833 */ >+ 588, >+ /* VPSUBDZrmk */ >+ }, >+ { /* 5834 */ >+ 316, >+ /* VPSUBDZrmkz */ >+ }, >+ { /* 5835 */ >+ 310, >+ /* VPSUBDZrr */ >+ }, >+ { /* 5836 */ >+ 439, >+ /* VPSUBDZrrk */ >+ }, >+ { /* 5837 */ >+ 317, >+ /* VPSUBDZrrkz */ >+ }, >+ { /* 5838 */ >+ 312, >+ /* VPSUBDrm */ >+ }, >+ { /* 5839 */ >+ 313, >+ /* VPSUBDrr */ >+ }, >+ { /* 5840 */ >+ 304, >+ /* VPSUBQYrm */ >+ }, >+ { /* 5841 */ >+ 305, >+ /* VPSUBQYrr */ >+ }, >+ { /* 5842 */ >+ 306, >+ /* VPSUBQZrm */ >+ }, >+ { /* 5843 */ >+ 589, >+ /* VPSUBQZrmb */ >+ }, >+ { /* 5844 */ >+ 590, >+ /* VPSUBQZrmbk */ >+ }, >+ { /* 5845 */ >+ 591, >+ /* VPSUBQZrmbkz */ >+ }, >+ { /* 5846 */ >+ 592, >+ /* VPSUBQZrmk */ >+ }, >+ { /* 5847 */ >+ 309, >+ /* VPSUBQZrmkz */ >+ }, >+ { /* 5848 */ >+ 310, >+ /* VPSUBQZrr */ >+ }, >+ { /* 5849 */ >+ 438, >+ /* VPSUBQZrrk */ >+ }, >+ { /* 5850 */ >+ 311, >+ /* VPSUBQZrrkz */ >+ }, >+ { /* 5851 */ >+ 312, >+ /* VPSUBQrm */ >+ }, >+ { /* 5852 */ >+ 313, >+ /* VPSUBQrr */ >+ }, >+ { /* 5853 */ >+ 304, >+ /* VPSUBSBYrm */ >+ }, >+ { /* 5854 */ >+ 305, >+ /* VPSUBSBYrr */ >+ }, >+ { /* 5855 */ >+ 312, >+ /* VPSUBSBrm */ >+ }, >+ { /* 5856 */ >+ 313, >+ /* VPSUBSBrr */ >+ }, >+ { /* 5857 */ >+ 304, >+ /* VPSUBSWYrm */ >+ }, >+ { /* 5858 */ >+ 305, >+ /* VPSUBSWYrr */ >+ }, >+ { /* 5859 */ >+ 312, >+ /* VPSUBSWrm */ >+ }, >+ { /* 5860 */ >+ 313, >+ /* VPSUBSWrr */ >+ }, >+ { /* 5861 */ >+ 304, >+ /* VPSUBUSBYrm */ >+ }, >+ { /* 5862 */ >+ 305, >+ /* VPSUBUSBYrr */ >+ }, >+ { /* 5863 */ >+ 312, >+ /* VPSUBUSBrm */ >+ }, >+ { /* 5864 */ >+ 313, >+ /* VPSUBUSBrr */ >+ }, >+ { /* 5865 */ >+ 304, >+ /* VPSUBUSWYrm */ >+ }, >+ { /* 5866 */ >+ 305, >+ /* VPSUBUSWYrr */ >+ }, >+ { /* 5867 */ >+ 312, >+ /* VPSUBUSWrm */ >+ }, >+ { /* 5868 */ >+ 313, >+ /* VPSUBUSWrr */ >+ }, >+ { /* 5869 */ >+ 304, >+ /* VPSUBWYrm */ >+ }, >+ { /* 5870 */ >+ 305, >+ /* VPSUBWYrr */ >+ }, >+ { /* 5871 */ >+ 312, >+ /* VPSUBWrm */ >+ }, >+ { /* 5872 */ >+ 313, >+ /* VPSUBWrr */ >+ }, >+ { /* 5873 */ >+ 632, >+ /* VPTESTMDZrm */ >+ }, >+ { /* 5874 */ >+ 636, >+ /* VPTESTMDZrr */ >+ }, >+ { /* 5875 */ >+ 650, >+ /* VPTESTMQZrm */ >+ }, >+ { /* 5876 */ >+ 654, >+ /* VPTESTMQZrr */ >+ }, >+ { /* 5877 */ >+ 632, >+ /* VPTESTNMDZrm */ >+ }, >+ { /* 5878 */ >+ 636, >+ /* VPTESTNMDZrr */ >+ }, >+ { /* 5879 */ >+ 650, >+ /* VPTESTNMQZrm */ >+ }, >+ { /* 5880 */ >+ 654, >+ /* VPTESTNMQZrr */ >+ }, >+ { /* 5881 */ >+ 376, >+ /* VPTESTYrm */ >+ }, >+ { /* 5882 */ >+ 377, >+ /* VPTESTYrr */ >+ }, >+ { /* 5883 */ >+ 44, >+ /* VPTESTrm */ >+ }, >+ { /* 5884 */ >+ 45, >+ /* VPTESTrr */ >+ }, >+ { /* 5885 */ >+ 304, >+ /* VPUNPCKHBWYrm */ >+ }, >+ { /* 5886 */ >+ 305, >+ /* VPUNPCKHBWYrr */ >+ }, >+ { /* 5887 */ >+ 312, >+ /* VPUNPCKHBWrm */ >+ }, >+ { /* 5888 */ >+ 313, >+ /* VPUNPCKHBWrr */ >+ }, >+ { /* 5889 */ >+ 304, >+ /* VPUNPCKHDQYrm */ >+ }, >+ { /* 5890 */ >+ 305, >+ /* VPUNPCKHDQYrr */ >+ }, >+ { /* 5891 */ >+ 306, >+ /* VPUNPCKHDQZrm */ >+ }, >+ { /* 5892 */ >+ 310, >+ /* VPUNPCKHDQZrr */ >+ }, >+ { /* 5893 */ >+ 312, >+ /* VPUNPCKHDQrm */ >+ }, >+ { /* 5894 */ >+ 313, >+ /* VPUNPCKHDQrr */ >+ }, >+ { /* 5895 */ >+ 304, >+ /* VPUNPCKHQDQYrm */ >+ }, >+ { /* 5896 */ >+ 305, >+ /* VPUNPCKHQDQYrr */ >+ }, >+ { /* 5897 */ >+ 306, >+ /* VPUNPCKHQDQZrm */ >+ }, >+ { /* 5898 */ >+ 310, >+ /* VPUNPCKHQDQZrr */ >+ }, >+ { /* 5899 */ >+ 312, >+ /* VPUNPCKHQDQrm */ >+ }, >+ { /* 5900 */ >+ 313, >+ /* VPUNPCKHQDQrr */ >+ }, >+ { /* 5901 */ >+ 304, >+ /* VPUNPCKHWDYrm */ >+ }, >+ { /* 5902 */ >+ 305, >+ /* VPUNPCKHWDYrr */ >+ }, >+ { /* 5903 */ >+ 312, >+ /* VPUNPCKHWDrm */ >+ }, >+ { /* 5904 */ >+ 313, >+ /* VPUNPCKHWDrr */ >+ }, >+ { /* 5905 */ >+ 304, >+ /* VPUNPCKLBWYrm */ >+ }, >+ { /* 5906 */ >+ 305, >+ /* VPUNPCKLBWYrr */ >+ }, >+ { /* 5907 */ >+ 312, >+ /* VPUNPCKLBWrm */ >+ }, >+ { /* 5908 */ >+ 313, >+ /* VPUNPCKLBWrr */ >+ }, >+ { /* 5909 */ >+ 304, >+ /* VPUNPCKLDQYrm */ >+ }, >+ { /* 5910 */ >+ 305, >+ /* VPUNPCKLDQYrr */ >+ }, >+ { /* 5911 */ >+ 306, >+ /* VPUNPCKLDQZrm */ >+ }, >+ { /* 5912 */ >+ 310, >+ /* VPUNPCKLDQZrr */ >+ }, >+ { /* 5913 */ >+ 312, >+ /* VPUNPCKLDQrm */ >+ }, >+ { /* 5914 */ >+ 313, >+ /* VPUNPCKLDQrr */ >+ }, >+ { /* 5915 */ >+ 304, >+ /* VPUNPCKLQDQYrm */ >+ }, >+ { /* 5916 */ >+ 305, >+ /* VPUNPCKLQDQYrr */ >+ }, >+ { /* 5917 */ >+ 306, >+ /* VPUNPCKLQDQZrm */ >+ }, >+ { /* 5918 */ >+ 310, >+ /* VPUNPCKLQDQZrr */ >+ }, >+ { /* 5919 */ >+ 312, >+ /* VPUNPCKLQDQrm */ >+ }, >+ { /* 5920 */ >+ 313, >+ /* VPUNPCKLQDQrr */ >+ }, >+ { /* 5921 */ >+ 304, >+ /* VPUNPCKLWDYrm */ >+ }, >+ { /* 5922 */ >+ 305, >+ /* VPUNPCKLWDYrr */ >+ }, >+ { /* 5923 */ >+ 312, >+ /* VPUNPCKLWDrm */ >+ }, >+ { /* 5924 */ >+ 313, >+ /* VPUNPCKLWDrr */ >+ }, >+ { /* 5925 */ >+ 306, >+ /* VPXORDZrm */ >+ }, >+ { /* 5926 */ >+ 585, >+ /* VPXORDZrmb */ >+ }, >+ { /* 5927 */ >+ 586, >+ /* VPXORDZrmbk */ >+ }, >+ { /* 5928 */ >+ 587, >+ /* VPXORDZrmbkz */ >+ }, >+ { /* 5929 */ >+ 588, >+ /* VPXORDZrmk */ >+ }, >+ { /* 5930 */ >+ 316, >+ /* VPXORDZrmkz */ >+ }, >+ { /* 5931 */ >+ 310, >+ /* VPXORDZrr */ >+ }, >+ { /* 5932 */ >+ 439, >+ /* VPXORDZrrk */ >+ }, >+ { /* 5933 */ >+ 317, >+ /* VPXORDZrrkz */ >+ }, >+ { /* 5934 */ >+ 306, >+ /* VPXORQZrm */ >+ }, >+ { /* 5935 */ >+ 589, >+ /* VPXORQZrmb */ >+ }, >+ { /* 5936 */ >+ 590, >+ /* VPXORQZrmbk */ >+ }, >+ { /* 5937 */ >+ 591, >+ /* VPXORQZrmbkz */ >+ }, >+ { /* 5938 */ >+ 592, >+ /* VPXORQZrmk */ >+ }, >+ { /* 5939 */ >+ 309, >+ /* VPXORQZrmkz */ >+ }, >+ { /* 5940 */ >+ 310, >+ /* VPXORQZrr */ >+ }, >+ { /* 5941 */ >+ 438, >+ /* VPXORQZrrk */ >+ }, >+ { /* 5942 */ >+ 311, >+ /* VPXORQZrrkz */ >+ }, >+ { /* 5943 */ >+ 304, >+ /* VPXORYrm */ >+ }, >+ { /* 5944 */ >+ 305, >+ /* VPXORYrr */ >+ }, >+ { /* 5945 */ >+ 312, >+ /* VPXORrm */ >+ }, >+ { /* 5946 */ >+ 313, >+ /* VPXORrr */ >+ }, >+ { /* 5947 */ >+ 378, >+ /* VRCP14PDZm */ >+ }, >+ { /* 5948 */ >+ 379, >+ /* VRCP14PDZr */ >+ }, >+ { /* 5949 */ >+ 378, >+ /* VRCP14PSZm */ >+ }, >+ { /* 5950 */ >+ 379, >+ /* VRCP14PSZr */ >+ }, >+ { /* 5951 */ >+ 318, >+ /* VRCP14SDrm */ >+ }, >+ { /* 5952 */ >+ 319, >+ /* VRCP14SDrr */ >+ }, >+ { /* 5953 */ >+ 322, >+ /* VRCP14SSrm */ >+ }, >+ { /* 5954 */ >+ 323, >+ /* VRCP14SSrr */ >+ }, >+ { /* 5955 */ >+ 378, >+ /* VRCP28PDZm */ >+ }, >+ { /* 5956 */ >+ 379, >+ /* VRCP28PDZr */ >+ }, >+ { /* 5957 */ >+ 732, >+ /* VRCP28PDZrb */ >+ }, >+ { /* 5958 */ >+ 378, >+ /* VRCP28PSZm */ >+ }, >+ { /* 5959 */ >+ 379, >+ /* VRCP28PSZr */ >+ }, >+ { /* 5960 */ >+ 733, >+ /* VRCP28PSZrb */ >+ }, >+ { /* 5961 */ >+ 318, >+ /* VRCP28SDrm */ >+ }, >+ { /* 5962 */ >+ 319, >+ /* VRCP28SDrr */ >+ }, >+ { /* 5963 */ >+ 319, >+ /* VRCP28SDrrb */ >+ }, >+ { /* 5964 */ >+ 322, >+ /* VRCP28SSrm */ >+ }, >+ { /* 5965 */ >+ 323, >+ /* VRCP28SSrr */ >+ }, >+ { /* 5966 */ >+ 323, >+ /* VRCP28SSrrb */ >+ }, >+ { /* 5967 */ >+ 376, >+ /* VRCPPSYm */ >+ }, >+ { /* 5968 */ >+ 0, >+ /* */ >+ }, >+ { /* 5969 */ >+ 377, >+ /* VRCPPSYr */ >+ }, >+ { /* 5970 */ >+ 0, >+ /* */ >+ }, >+ { /* 5971 */ >+ 44, >+ /* VRCPPSm */ >+ }, >+ { /* 5972 */ >+ 0, >+ /* */ >+ }, >+ { /* 5973 */ >+ 45, >+ /* VRCPPSr */ >+ }, >+ { /* 5974 */ >+ 0, >+ /* */ >+ }, >+ { /* 5975 */ >+ 324, >+ /* VRCPSSm */ >+ }, >+ { /* 5976 */ >+ 0, >+ /* */ >+ }, >+ { /* 5977 */ >+ 325, >+ /* VRCPSSr */ >+ }, >+ { /* 5978 */ >+ 734, >+ /* VRNDSCALEPDZm */ >+ }, >+ { /* 5979 */ >+ 735, >+ /* VRNDSCALEPDZr */ >+ }, >+ { /* 5980 */ >+ 734, >+ /* VRNDSCALEPSZm */ >+ }, >+ { /* 5981 */ >+ 735, >+ /* VRNDSCALEPSZr */ >+ }, >+ { /* 5982 */ >+ 736, >+ /* VRNDSCALESDm */ >+ }, >+ { /* 5983 */ >+ 737, >+ /* VRNDSCALESDr */ >+ }, >+ { /* 5984 */ >+ 738, >+ /* VRNDSCALESSm */ >+ }, >+ { /* 5985 */ >+ 739, >+ /* VRNDSCALESSr */ >+ }, >+ { /* 5986 */ >+ 293, >+ /* VROUNDPDm */ >+ }, >+ { /* 5987 */ >+ 294, >+ /* VROUNDPDr */ >+ }, >+ { /* 5988 */ >+ 293, >+ /* VROUNDPSm */ >+ }, >+ { /* 5989 */ >+ 294, >+ /* VROUNDPSr */ >+ }, >+ { /* 5990 */ >+ 740, >+ /* VROUNDSDm */ >+ }, >+ { /* 5991 */ >+ 741, >+ /* VROUNDSDr */ >+ }, >+ { /* 5992 */ >+ 0, >+ /* */ >+ }, >+ { /* 5993 */ >+ 480, >+ /* VROUNDSSm */ >+ }, >+ { /* 5994 */ >+ 742, >+ /* VROUNDSSr */ >+ }, >+ { /* 5995 */ >+ 0, >+ /* */ >+ }, >+ { /* 5996 */ >+ 743, >+ /* VROUNDYPDm */ >+ }, >+ { /* 5997 */ >+ 744, >+ /* VROUNDYPDr */ >+ }, >+ { /* 5998 */ >+ 743, >+ /* VROUNDYPSm */ >+ }, >+ { /* 5999 */ >+ 744, >+ /* VROUNDYPSr */ >+ }, >+ { /* 6000 */ >+ 378, >+ /* VRSQRT14PDZm */ >+ }, >+ { /* 6001 */ >+ 379, >+ /* VRSQRT14PDZr */ >+ }, >+ { /* 6002 */ >+ 378, >+ /* VRSQRT14PSZm */ >+ }, >+ { /* 6003 */ >+ 379, >+ /* VRSQRT14PSZr */ >+ }, >+ { /* 6004 */ >+ 318, >+ /* VRSQRT14SDrm */ >+ }, >+ { /* 6005 */ >+ 319, >+ /* VRSQRT14SDrr */ >+ }, >+ { /* 6006 */ >+ 322, >+ /* VRSQRT14SSrm */ >+ }, >+ { /* 6007 */ >+ 323, >+ /* VRSQRT14SSrr */ >+ }, >+ { /* 6008 */ >+ 378, >+ /* VRSQRT28PDZm */ >+ }, >+ { /* 6009 */ >+ 379, >+ /* VRSQRT28PDZr */ >+ }, >+ { /* 6010 */ >+ 732, >+ /* VRSQRT28PDZrb */ >+ }, >+ { /* 6011 */ >+ 378, >+ /* VRSQRT28PSZm */ >+ }, >+ { /* 6012 */ >+ 379, >+ /* VRSQRT28PSZr */ >+ }, >+ { /* 6013 */ >+ 733, >+ /* VRSQRT28PSZrb */ >+ }, >+ { /* 6014 */ >+ 318, >+ /* VRSQRT28SDrm */ >+ }, >+ { /* 6015 */ >+ 319, >+ /* VRSQRT28SDrr */ >+ }, >+ { /* 6016 */ >+ 319, >+ /* VRSQRT28SDrrb */ >+ }, >+ { /* 6017 */ >+ 322, >+ /* VRSQRT28SSrm */ >+ }, >+ { /* 6018 */ >+ 323, >+ /* VRSQRT28SSrr */ >+ }, >+ { /* 6019 */ >+ 323, >+ /* VRSQRT28SSrrb */ >+ }, >+ { /* 6020 */ >+ 376, >+ /* VRSQRTPSYm */ >+ }, >+ { /* 6021 */ >+ 0, >+ /* */ >+ }, >+ { /* 6022 */ >+ 377, >+ /* VRSQRTPSYr */ >+ }, >+ { /* 6023 */ >+ 0, >+ /* */ >+ }, >+ { /* 6024 */ >+ 44, >+ /* VRSQRTPSm */ >+ }, >+ { /* 6025 */ >+ 0, >+ /* */ >+ }, >+ { /* 6026 */ >+ 45, >+ /* VRSQRTPSr */ >+ }, >+ { /* 6027 */ >+ 0, >+ /* */ >+ }, >+ { /* 6028 */ >+ 324, >+ /* VRSQRTSSm */ >+ }, >+ { /* 6029 */ >+ 0, >+ /* */ >+ }, >+ { /* 6030 */ >+ 325, >+ /* VRSQRTSSr */ >+ }, >+ { /* 6031 */ >+ 712, >+ /* VSCATTERDPDZmr */ >+ }, >+ { /* 6032 */ >+ 711, >+ /* VSCATTERDPSZmr */ >+ }, >+ { /* 6033 */ >+ 470, >+ /* VSCATTERPF0DPDm */ >+ }, >+ { /* 6034 */ >+ 471, >+ /* VSCATTERPF0DPSm */ >+ }, >+ { /* 6035 */ >+ 472, >+ /* VSCATTERPF0QPDm */ >+ }, >+ { /* 6036 */ >+ 472, >+ /* VSCATTERPF0QPSm */ >+ }, >+ { /* 6037 */ >+ 470, >+ /* VSCATTERPF1DPDm */ >+ }, >+ { /* 6038 */ >+ 471, >+ /* VSCATTERPF1DPSm */ >+ }, >+ { /* 6039 */ >+ 472, >+ /* VSCATTERPF1QPDm */ >+ }, >+ { /* 6040 */ >+ 472, >+ /* VSCATTERPF1QPSm */ >+ }, >+ { /* 6041 */ >+ 712, >+ /* VSCATTERQPDZmr */ >+ }, >+ { /* 6042 */ >+ 713, >+ /* VSCATTERQPSZmr */ >+ }, >+ { /* 6043 */ >+ 595, >+ /* VSHUFPDYrmi */ >+ }, >+ { /* 6044 */ >+ 596, >+ /* VSHUFPDYrri */ >+ }, >+ { /* 6045 */ >+ 326, >+ /* VSHUFPDZrmi */ >+ }, >+ { /* 6046 */ >+ 327, >+ /* VSHUFPDZrri */ >+ }, >+ { /* 6047 */ >+ 593, >+ /* VSHUFPDrmi */ >+ }, >+ { /* 6048 */ >+ 594, >+ /* VSHUFPDrri */ >+ }, >+ { /* 6049 */ >+ 595, >+ /* VSHUFPSYrmi */ >+ }, >+ { /* 6050 */ >+ 596, >+ /* VSHUFPSYrri */ >+ }, >+ { /* 6051 */ >+ 326, >+ /* VSHUFPSZrmi */ >+ }, >+ { /* 6052 */ >+ 327, >+ /* VSHUFPSZrri */ >+ }, >+ { /* 6053 */ >+ 593, >+ /* VSHUFPSrmi */ >+ }, >+ { /* 6054 */ >+ 594, >+ /* VSHUFPSrri */ >+ }, >+ { /* 6055 */ >+ 376, >+ /* VSQRTPDYm */ >+ }, >+ { /* 6056 */ >+ 377, >+ /* VSQRTPDYr */ >+ }, >+ { /* 6057 */ >+ 378, >+ /* VSQRTPDZrm */ >+ }, >+ { /* 6058 */ >+ 379, >+ /* VSQRTPDZrr */ >+ }, >+ { /* 6059 */ >+ 44, >+ /* VSQRTPDm */ >+ }, >+ { /* 6060 */ >+ 45, >+ /* VSQRTPDr */ >+ }, >+ { /* 6061 */ >+ 376, >+ /* VSQRTPSYm */ >+ }, >+ { /* 6062 */ >+ 377, >+ /* VSQRTPSYr */ >+ }, >+ { /* 6063 */ >+ 378, >+ /* VSQRTPSZrm */ >+ }, >+ { /* 6064 */ >+ 379, >+ /* VSQRTPSZrr */ >+ }, >+ { /* 6065 */ >+ 44, >+ /* VSQRTPSm */ >+ }, >+ { /* 6066 */ >+ 45, >+ /* VSQRTPSr */ >+ }, >+ { /* 6067 */ >+ 318, >+ /* VSQRTSDZm */ >+ }, >+ { /* 6068 */ >+ 0, >+ /* */ >+ }, >+ { /* 6069 */ >+ 745, >+ /* VSQRTSDZr */ >+ }, >+ { /* 6070 */ >+ 0, >+ /* */ >+ }, >+ { /* 6071 */ >+ 320, >+ /* VSQRTSDm */ >+ }, >+ { /* 6072 */ >+ 0, >+ /* */ >+ }, >+ { /* 6073 */ >+ 321, >+ /* VSQRTSDr */ >+ }, >+ { /* 6074 */ >+ 322, >+ /* VSQRTSSZm */ >+ }, >+ { /* 6075 */ >+ 0, >+ /* */ >+ }, >+ { /* 6076 */ >+ 746, >+ /* VSQRTSSZr */ >+ }, >+ { /* 6077 */ >+ 0, >+ /* */ >+ }, >+ { /* 6078 */ >+ 324, >+ /* VSQRTSSm */ >+ }, >+ { /* 6079 */ >+ 0, >+ /* */ >+ }, >+ { /* 6080 */ >+ 325, >+ /* VSQRTSSr */ >+ }, >+ { /* 6081 */ >+ 38, >+ /* VSTMXCSR */ >+ }, >+ { /* 6082 */ >+ 304, >+ /* VSUBPDYrm */ >+ }, >+ { /* 6083 */ >+ 305, >+ /* VSUBPDYrr */ >+ }, >+ { /* 6084 */ >+ 306, >+ /* VSUBPDZrm */ >+ }, >+ { /* 6085 */ >+ 307, >+ /* VSUBPDZrmb */ >+ }, >+ { /* 6086 */ >+ 308, >+ /* VSUBPDZrmbk */ >+ }, >+ { /* 6087 */ >+ 308, >+ /* VSUBPDZrmbkz */ >+ }, >+ { /* 6088 */ >+ 309, >+ /* VSUBPDZrmk */ >+ }, >+ { /* 6089 */ >+ 309, >+ /* VSUBPDZrmkz */ >+ }, >+ { /* 6090 */ >+ 310, >+ /* VSUBPDZrr */ >+ }, >+ { /* 6091 */ >+ 311, >+ /* VSUBPDZrrk */ >+ }, >+ { /* 6092 */ >+ 311, >+ /* VSUBPDZrrkz */ >+ }, >+ { /* 6093 */ >+ 312, >+ /* VSUBPDrm */ >+ }, >+ { /* 6094 */ >+ 313, >+ /* VSUBPDrr */ >+ }, >+ { /* 6095 */ >+ 304, >+ /* VSUBPSYrm */ >+ }, >+ { /* 6096 */ >+ 305, >+ /* VSUBPSYrr */ >+ }, >+ { /* 6097 */ >+ 306, >+ /* VSUBPSZrm */ >+ }, >+ { /* 6098 */ >+ 314, >+ /* VSUBPSZrmb */ >+ }, >+ { /* 6099 */ >+ 315, >+ /* VSUBPSZrmbk */ >+ }, >+ { /* 6100 */ >+ 315, >+ /* VSUBPSZrmbkz */ >+ }, >+ { /* 6101 */ >+ 316, >+ /* VSUBPSZrmk */ >+ }, >+ { /* 6102 */ >+ 316, >+ /* VSUBPSZrmkz */ >+ }, >+ { /* 6103 */ >+ 310, >+ /* VSUBPSZrr */ >+ }, >+ { /* 6104 */ >+ 317, >+ /* VSUBPSZrrk */ >+ }, >+ { /* 6105 */ >+ 317, >+ /* VSUBPSZrrkz */ >+ }, >+ { /* 6106 */ >+ 312, >+ /* VSUBPSrm */ >+ }, >+ { /* 6107 */ >+ 313, >+ /* VSUBPSrr */ >+ }, >+ { /* 6108 */ >+ 318, >+ /* VSUBSDZrm */ >+ }, >+ { /* 6109 */ >+ 319, >+ /* VSUBSDZrr */ >+ }, >+ { /* 6110 */ >+ 320, >+ /* VSUBSDrm */ >+ }, >+ { /* 6111 */ >+ 0, >+ /* */ >+ }, >+ { /* 6112 */ >+ 321, >+ /* VSUBSDrr */ >+ }, >+ { /* 6113 */ >+ 0, >+ /* */ >+ }, >+ { /* 6114 */ >+ 322, >+ /* VSUBSSZrm */ >+ }, >+ { /* 6115 */ >+ 323, >+ /* VSUBSSZrr */ >+ }, >+ { /* 6116 */ >+ 324, >+ /* VSUBSSrm */ >+ }, >+ { /* 6117 */ >+ 0, >+ /* */ >+ }, >+ { /* 6118 */ >+ 325, >+ /* VSUBSSrr */ >+ }, >+ { /* 6119 */ >+ 0, >+ /* */ >+ }, >+ { /* 6120 */ >+ 376, >+ /* VTESTPDYrm */ >+ }, >+ { /* 6121 */ >+ 377, >+ /* VTESTPDYrr */ >+ }, >+ { /* 6122 */ >+ 44, >+ /* VTESTPDrm */ >+ }, >+ { /* 6123 */ >+ 45, >+ /* VTESTPDrr */ >+ }, >+ { /* 6124 */ >+ 376, >+ /* VTESTPSYrm */ >+ }, >+ { /* 6125 */ >+ 377, >+ /* VTESTPSYrr */ >+ }, >+ { /* 6126 */ >+ 44, >+ /* VTESTPSrm */ >+ }, >+ { /* 6127 */ >+ 45, >+ /* VTESTPSrr */ >+ }, >+ { /* 6128 */ >+ 566, >+ /* VUCOMISDZrm */ >+ }, >+ { /* 6129 */ >+ 747, >+ /* VUCOMISDZrr */ >+ }, >+ { /* 6130 */ >+ 254, >+ /* VUCOMISDrm */ >+ }, >+ { /* 6131 */ >+ 303, >+ /* VUCOMISDrr */ >+ }, >+ { /* 6132 */ >+ 574, >+ /* VUCOMISSZrm */ >+ }, >+ { /* 6133 */ >+ 748, >+ /* VUCOMISSZrr */ >+ }, >+ { /* 6134 */ >+ 258, >+ /* VUCOMISSrm */ >+ }, >+ { /* 6135 */ >+ 287, >+ /* VUCOMISSrr */ >+ }, >+ { /* 6136 */ >+ 304, >+ /* VUNPCKHPDYrm */ >+ }, >+ { /* 6137 */ >+ 305, >+ /* VUNPCKHPDYrr */ >+ }, >+ { /* 6138 */ >+ 306, >+ /* VUNPCKHPDZrm */ >+ }, >+ { /* 6139 */ >+ 310, >+ /* VUNPCKHPDZrr */ >+ }, >+ { /* 6140 */ >+ 312, >+ /* VUNPCKHPDrm */ >+ }, >+ { /* 6141 */ >+ 313, >+ /* VUNPCKHPDrr */ >+ }, >+ { /* 6142 */ >+ 304, >+ /* VUNPCKHPSYrm */ >+ }, >+ { /* 6143 */ >+ 305, >+ /* VUNPCKHPSYrr */ >+ }, >+ { /* 6144 */ >+ 306, >+ /* VUNPCKHPSZrm */ >+ }, >+ { /* 6145 */ >+ 310, >+ /* VUNPCKHPSZrr */ >+ }, >+ { /* 6146 */ >+ 312, >+ /* VUNPCKHPSrm */ >+ }, >+ { /* 6147 */ >+ 313, >+ /* VUNPCKHPSrr */ >+ }, >+ { /* 6148 */ >+ 304, >+ /* VUNPCKLPDYrm */ >+ }, >+ { /* 6149 */ >+ 305, >+ /* VUNPCKLPDYrr */ >+ }, >+ { /* 6150 */ >+ 306, >+ /* VUNPCKLPDZrm */ >+ }, >+ { /* 6151 */ >+ 310, >+ /* VUNPCKLPDZrr */ >+ }, >+ { /* 6152 */ >+ 312, >+ /* VUNPCKLPDrm */ >+ }, >+ { /* 6153 */ >+ 313, >+ /* VUNPCKLPDrr */ >+ }, >+ { /* 6154 */ >+ 304, >+ /* VUNPCKLPSYrm */ >+ }, >+ { /* 6155 */ >+ 305, >+ /* VUNPCKLPSYrr */ >+ }, >+ { /* 6156 */ >+ 306, >+ /* VUNPCKLPSZrm */ >+ }, >+ { /* 6157 */ >+ 310, >+ /* VUNPCKLPSZrr */ >+ }, >+ { /* 6158 */ >+ 312, >+ /* VUNPCKLPSrm */ >+ }, >+ { /* 6159 */ >+ 313, >+ /* VUNPCKLPSrr */ >+ }, >+ { /* 6160 */ >+ 304, >+ /* VXORPDYrm */ >+ }, >+ { /* 6161 */ >+ 305, >+ /* VXORPDYrr */ >+ }, >+ { /* 6162 */ >+ 312, >+ /* VXORPDrm */ >+ }, >+ { /* 6163 */ >+ 313, >+ /* VXORPDrr */ >+ }, >+ { /* 6164 */ >+ 304, >+ /* VXORPSYrm */ >+ }, >+ { /* 6165 */ >+ 305, >+ /* VXORPSYrr */ >+ }, >+ { /* 6166 */ >+ 312, >+ /* VXORPSrm */ >+ }, >+ { /* 6167 */ >+ 313, >+ /* VXORPSrr */ >+ }, >+ { /* 6168 */ >+ 0, >+ /* VZEROALL */ >+ }, >+ { /* 6169 */ >+ 0, >+ /* VZEROUPPER */ >+ }, >+ { /* 6170 */ >+ 0, >+ /* */ >+ }, >+ { /* 6171 */ >+ 0, >+ /* */ >+ }, >+ { /* 6172 */ >+ 0, >+ /* */ >+ }, >+ { /* 6173 */ >+ 0, >+ /* WAIT */ >+ }, >+ { /* 6174 */ >+ 0, >+ /* WBINVD */ >+ }, >+ { /* 6175 */ >+ 0, >+ /* */ >+ }, >+ { /* 6176 */ >+ 0, >+ /* */ >+ }, >+ { /* 6177 */ >+ 0, >+ /* */ >+ }, >+ { /* 6178 */ >+ 288, >+ /* WRFSBASE */ >+ }, >+ { /* 6179 */ >+ 79, >+ /* WRFSBASE64 */ >+ }, >+ { /* 6180 */ >+ 288, >+ /* WRGSBASE */ >+ }, >+ { /* 6181 */ >+ 79, >+ /* WRGSBASE64 */ >+ }, >+ { /* 6182 */ >+ 0, >+ /* WRMSR */ >+ }, >+ { /* 6183 */ >+ 1, >+ /* XABORT */ >+ }, >+ { /* 6184 */ >+ 0, >+ /* */ >+ }, >+ { /* 6185 */ >+ 5, >+ /* XADD16rm */ >+ }, >+ { /* 6186 */ >+ 73, >+ /* XADD16rr */ >+ }, >+ { /* 6187 */ >+ 5, >+ /* XADD32rm */ >+ }, >+ { /* 6188 */ >+ 73, >+ /* XADD32rr */ >+ }, >+ { /* 6189 */ >+ 16, >+ /* XADD64rm */ >+ }, >+ { /* 6190 */ >+ 76, >+ /* XADD64rr */ >+ }, >+ { /* 6191 */ >+ 23, >+ /* XADD8rm */ >+ }, >+ { /* 6192 */ >+ 87, >+ /* XADD8rr */ >+ }, >+ { /* 6193 */ >+ 0, >+ /* */ >+ }, >+ { /* 6194 */ >+ 157, >+ /* XBEGIN_4 */ >+ }, >+ { /* 6195 */ >+ 277, >+ /* XCHG16ar */ >+ }, >+ { /* 6196 */ >+ 8, >+ /* XCHG16rm */ >+ }, >+ { /* 6197 */ >+ 10, >+ /* XCHG16rr */ >+ }, >+ { /* 6198 */ >+ 277, >+ /* XCHG32ar */ >+ }, >+ { /* 6199 */ >+ 277, >+ /* XCHG32ar64 */ >+ }, >+ { /* 6200 */ >+ 8, >+ /* XCHG32rm */ >+ }, >+ { /* 6201 */ >+ 10, >+ /* XCHG32rr */ >+ }, >+ { /* 6202 */ >+ 278, >+ /* XCHG64ar */ >+ }, >+ { /* 6203 */ >+ 19, >+ /* XCHG64rm */ >+ }, >+ { /* 6204 */ >+ 21, >+ /* XCHG64rr */ >+ }, >+ { /* 6205 */ >+ 25, >+ /* XCHG8rm */ >+ }, >+ { /* 6206 */ >+ 27, >+ /* XCHG8rr */ >+ }, >+ { /* 6207 */ >+ 39, >+ /* XCH_F */ >+ }, >+ { /* 6208 */ >+ 0, >+ /* XCRYPTCBC */ >+ }, >+ { /* 6209 */ >+ 0, >+ /* XCRYPTCFB */ >+ }, >+ { /* 6210 */ >+ 0, >+ /* XCRYPTCTR */ >+ }, >+ { /* 6211 */ >+ 0, >+ /* XCRYPTECB */ >+ }, >+ { /* 6212 */ >+ 0, >+ /* XCRYPTOFB */ >+ }, >+ { /* 6213 */ >+ 0, >+ /* XEND */ >+ }, >+ { /* 6214 */ >+ 0, >+ /* XGETBV */ >+ }, >+ { /* 6215 */ >+ 0, >+ /* XLAT */ >+ }, >+ { /* 6216 */ >+ 2, >+ /* XOR16i16 */ >+ }, >+ { /* 6217 */ >+ 3, >+ /* XOR16mi */ >+ }, >+ { /* 6218 */ >+ 4, >+ /* XOR16mi8 */ >+ }, >+ { /* 6219 */ >+ 5, >+ /* XOR16mr */ >+ }, >+ { /* 6220 */ >+ 6, >+ /* XOR16ri */ >+ }, >+ { /* 6221 */ >+ 7, >+ /* XOR16ri8 */ >+ }, >+ { /* 6222 */ >+ 8, >+ /* XOR16rm */ >+ }, >+ { /* 6223 */ >+ 9, >+ /* XOR16rr */ >+ }, >+ { /* 6224 */ >+ 10, >+ /* XOR16rr_REV */ >+ }, >+ { /* 6225 */ >+ 2, >+ /* XOR32i32 */ >+ }, >+ { /* 6226 */ >+ 3, >+ /* XOR32mi */ >+ }, >+ { /* 6227 */ >+ 11, >+ /* XOR32mi8 */ >+ }, >+ { /* 6228 */ >+ 5, >+ /* XOR32mr */ >+ }, >+ { /* 6229 */ >+ 6, >+ /* XOR32ri */ >+ }, >+ { /* 6230 */ >+ 12, >+ /* XOR32ri8 */ >+ }, >+ { /* 6231 */ >+ 8, >+ /* XOR32rm */ >+ }, >+ { /* 6232 */ >+ 9, >+ /* XOR32rr */ >+ }, >+ { /* 6233 */ >+ 10, >+ /* XOR32rr_REV */ >+ }, >+ { /* 6234 */ >+ 13, >+ /* XOR64i32 */ >+ }, >+ { /* 6235 */ >+ 14, >+ /* XOR64mi32 */ >+ }, >+ { /* 6236 */ >+ 15, >+ /* XOR64mi8 */ >+ }, >+ { /* 6237 */ >+ 16, >+ /* XOR64mr */ >+ }, >+ { /* 6238 */ >+ 17, >+ /* XOR64ri32 */ >+ }, >+ { /* 6239 */ >+ 18, >+ /* XOR64ri8 */ >+ }, >+ { /* 6240 */ >+ 19, >+ /* XOR64rm */ >+ }, >+ { /* 6241 */ >+ 20, >+ /* XOR64rr */ >+ }, >+ { /* 6242 */ >+ 21, >+ /* XOR64rr_REV */ >+ }, >+ { /* 6243 */ >+ 1, >+ /* XOR8i8 */ >+ }, >+ { /* 6244 */ >+ 22, >+ /* XOR8mi */ >+ }, >+ { /* 6245 */ >+ 23, >+ /* XOR8mr */ >+ }, >+ { /* 6246 */ >+ 24, >+ /* XOR8ri */ >+ }, >+ { /* 6247 */ >+ 24, >+ /* XOR8ri8 */ >+ }, >+ { /* 6248 */ >+ 25, >+ /* XOR8rm */ >+ }, >+ { /* 6249 */ >+ 26, >+ /* XOR8rr */ >+ }, >+ { /* 6250 */ >+ 27, >+ /* XOR8rr_REV */ >+ }, >+ { /* 6251 */ >+ 30, >+ /* XORPDrm */ >+ }, >+ { /* 6252 */ >+ 31, >+ /* XORPDrr */ >+ }, >+ { /* 6253 */ >+ 30, >+ /* XORPSrm */ >+ }, >+ { /* 6254 */ >+ 31, >+ /* XORPSrr */ >+ }, >+ { /* 6255 */ >+ 0, >+ /* */ >+ }, >+ { /* 6256 */ >+ 140, >+ /* XRSTOR */ >+ }, >+ { /* 6257 */ >+ 140, >+ /* XRSTOR64 */ >+ }, >+ { /* 6258 */ >+ 140, >+ /* XSAVE */ >+ }, >+ { /* 6259 */ >+ 140, >+ /* XSAVE64 */ >+ }, >+ { /* 6260 */ >+ 140, >+ /* XSAVEOPT */ >+ }, >+ { /* 6261 */ >+ 140, >+ /* XSAVEOPT64 */ >+ }, >+ { /* 6262 */ >+ 0, >+ /* XSETBV */ >+ }, >+ { /* 6263 */ >+ 0, >+ /* XSHA1 */ >+ }, >+ { /* 6264 */ >+ 0, >+ /* XSHA256 */ >+ }, >+ { /* 6265 */ >+ 0, >+ /* XSTORE */ >+ }, >+ { /* 6266 */ >+ 0, >+ /* XTEST */ >+ } >+}; >+ >+static const uint8_t x86DisassemblerContexts[16384] = { >+ IC, /* 0 */ >+ IC_64BIT, /* 1 */ >+ IC_XS, /* 2 */ >+ IC_64BIT_XS, /* 3 */ >+ IC_XD, /* 4 */ >+ IC_64BIT_XD, /* 5 */ >+ IC_XS, /* 6 */ >+ IC_64BIT_XS, /* 7 */ >+ IC, /* 8 */ >+ IC_64BIT_REXW, /* 9 */ >+ IC_XS, /* 10 */ >+ IC_64BIT_REXW_XS, /* 11 */ >+ IC_XD, /* 12 */ >+ IC_64BIT_REXW_XD, /* 13 */ >+ IC_XS, /* 14 */ >+ IC_64BIT_REXW_XS, /* 15 */ >+ IC_OPSIZE, /* 16 */ >+ IC_64BIT_OPSIZE, /* 17 */ >+ IC_XS_OPSIZE, /* 18 */ >+ IC_64BIT_XS_OPSIZE, /* 19 */ >+ IC_XD_OPSIZE, /* 20 */ >+ IC_64BIT_XD_OPSIZE, /* 21 */ >+ IC_XS_OPSIZE, /* 22 */ >+ IC_64BIT_XD_OPSIZE, /* 23 */ >+ IC_OPSIZE, /* 24 */ >+ IC_64BIT_REXW_OPSIZE, /* 25 */ >+ IC_XS_OPSIZE, /* 26 */ >+ IC_64BIT_REXW_XS, /* 27 */ >+ IC_XD_OPSIZE, /* 28 */ >+ IC_64BIT_REXW_XD, /* 29 */ >+ IC_XS_OPSIZE, /* 30 */ >+ IC_64BIT_REXW_XS, /* 31 */ >+ IC_ADSIZE, /* 32 */ >+ IC_64BIT_ADSIZE, /* 33 */ >+ IC_XS, /* 34 */ >+ IC_64BIT_XS, /* 35 */ >+ IC_XD, /* 36 */ >+ IC_64BIT_XD, /* 37 */ >+ IC_XS, /* 38 */ >+ IC_64BIT_XS, /* 39 */ >+ IC_ADSIZE, /* 40 */ >+ IC_64BIT_ADSIZE, /* 41 */ >+ IC_XS, /* 42 */ >+ IC_64BIT_REXW_XS, /* 43 */ >+ IC_XD, /* 44 */ >+ IC_64BIT_REXW_XD, /* 45 */ >+ IC_XS, /* 46 */ >+ IC_64BIT_REXW_XS, /* 47 */ >+ IC_OPSIZE, /* 48 */ >+ IC_64BIT_OPSIZE, /* 49 */ >+ IC_XS_OPSIZE, /* 50 */ >+ IC_64BIT_XS_OPSIZE, /* 51 */ >+ IC_XD_OPSIZE, /* 52 */ >+ IC_64BIT_XD_OPSIZE, /* 53 */ >+ IC_XS_OPSIZE, /* 54 */ >+ IC_64BIT_XD_OPSIZE, /* 55 */ >+ IC_OPSIZE, /* 56 */ >+ IC_64BIT_REXW_OPSIZE, /* 57 */ >+ IC_XS_OPSIZE, /* 58 */ >+ IC_64BIT_REXW_XS, /* 59 */ >+ IC_XD_OPSIZE, /* 60 */ >+ IC_64BIT_REXW_XD, /* 61 */ >+ IC_XS_OPSIZE, /* 62 */ >+ IC_64BIT_REXW_XS, /* 63 */ >+ IC_VEX, /* 64 */ >+ IC_VEX, /* 65 */ >+ IC_VEX_XS, /* 66 */ >+ IC_VEX_XS, /* 67 */ >+ IC_VEX_XD, /* 68 */ >+ IC_VEX_XD, /* 69 */ >+ IC_VEX_XD, /* 70 */ >+ IC_VEX_XD, /* 71 */ >+ IC_VEX_W, /* 72 */ >+ IC_VEX_W, /* 73 */ >+ IC_VEX_W_XS, /* 74 */ >+ IC_VEX_W_XS, /* 75 */ >+ IC_VEX_W_XD, /* 76 */ >+ IC_VEX_W_XD, /* 77 */ >+ IC_VEX_W_XD, /* 78 */ >+ IC_VEX_W_XD, /* 79 */ >+ IC_VEX_OPSIZE, /* 80 */ >+ IC_VEX_OPSIZE, /* 81 */ >+ IC_VEX_OPSIZE, /* 82 */ >+ IC_VEX_OPSIZE, /* 83 */ >+ IC_VEX_OPSIZE, /* 84 */ >+ IC_VEX_OPSIZE, /* 85 */ >+ IC_VEX_OPSIZE, /* 86 */ >+ IC_VEX_OPSIZE, /* 87 */ >+ IC_VEX_W_OPSIZE, /* 88 */ >+ IC_VEX_W_OPSIZE, /* 89 */ >+ IC_VEX_W_OPSIZE, /* 90 */ >+ IC_VEX_W_OPSIZE, /* 91 */ >+ IC_VEX_W_OPSIZE, /* 92 */ >+ IC_VEX_W_OPSIZE, /* 93 */ >+ IC_VEX_W_OPSIZE, /* 94 */ >+ IC_VEX_W_OPSIZE, /* 95 */ >+ IC_VEX, /* 96 */ >+ IC_VEX, /* 97 */ >+ IC_VEX_XS, /* 98 */ >+ IC_VEX_XS, /* 99 */ >+ IC_VEX_XD, /* 100 */ >+ IC_VEX_XD, /* 101 */ >+ IC_VEX_XD, /* 102 */ >+ IC_VEX_XD, /* 103 */ >+ IC_VEX_W, /* 104 */ >+ IC_VEX_W, /* 105 */ >+ IC_VEX_W_XS, /* 106 */ >+ IC_VEX_W_XS, /* 107 */ >+ IC_VEX_W_XD, /* 108 */ >+ IC_VEX_W_XD, /* 109 */ >+ IC_VEX_W_XD, /* 110 */ >+ IC_VEX_W_XD, /* 111 */ >+ IC_VEX_OPSIZE, /* 112 */ >+ IC_VEX_OPSIZE, /* 113 */ >+ IC_VEX_OPSIZE, /* 114 */ >+ IC_VEX_OPSIZE, /* 115 */ >+ IC_VEX_OPSIZE, /* 116 */ >+ IC_VEX_OPSIZE, /* 117 */ >+ IC_VEX_OPSIZE, /* 118 */ >+ IC_VEX_OPSIZE, /* 119 */ >+ IC_VEX_W_OPSIZE, /* 120 */ >+ IC_VEX_W_OPSIZE, /* 121 */ >+ IC_VEX_W_OPSIZE, /* 122 */ >+ IC_VEX_W_OPSIZE, /* 123 */ >+ IC_VEX_W_OPSIZE, /* 124 */ >+ IC_VEX_W_OPSIZE, /* 125 */ >+ IC_VEX_W_OPSIZE, /* 126 */ >+ IC_VEX_W_OPSIZE, /* 127 */ >+ IC_VEX_L, /* 128 */ >+ IC_VEX_L, /* 129 */ >+ IC_VEX_L_XS, /* 130 */ >+ IC_VEX_L_XS, /* 131 */ >+ IC_VEX_L_XD, /* 132 */ >+ IC_VEX_L_XD, /* 133 */ >+ IC_VEX_L_XD, /* 134 */ >+ IC_VEX_L_XD, /* 135 */ >+ IC_VEX_L_W, /* 136 */ >+ IC_VEX_L_W, /* 137 */ >+ IC_VEX_L_W_XS, /* 138 */ >+ IC_VEX_L_W_XS, /* 139 */ >+ IC_VEX_L_W_XD, /* 140 */ >+ IC_VEX_L_W_XD, /* 141 */ >+ IC_VEX_L_W_XD, /* 142 */ >+ IC_VEX_L_W_XD, /* 143 */ >+ IC_VEX_L_OPSIZE, /* 144 */ >+ IC_VEX_L_OPSIZE, /* 145 */ >+ IC_VEX_L_OPSIZE, /* 146 */ >+ IC_VEX_L_OPSIZE, /* 147 */ >+ IC_VEX_L_OPSIZE, /* 148 */ >+ IC_VEX_L_OPSIZE, /* 149 */ >+ IC_VEX_L_OPSIZE, /* 150 */ >+ IC_VEX_L_OPSIZE, /* 151 */ >+ IC_VEX_L_W_OPSIZE, /* 152 */ >+ IC_VEX_L_W_OPSIZE, /* 153 */ >+ IC_VEX_L_W_OPSIZE, /* 154 */ >+ IC_VEX_L_W_OPSIZE, /* 155 */ >+ IC_VEX_L_W_OPSIZE, /* 156 */ >+ IC_VEX_L_W_OPSIZE, /* 157 */ >+ IC_VEX_L_W_OPSIZE, /* 158 */ >+ IC_VEX_L_W_OPSIZE, /* 159 */ >+ IC_VEX_L, /* 160 */ >+ IC_VEX_L, /* 161 */ >+ IC_VEX_L_XS, /* 162 */ >+ IC_VEX_L_XS, /* 163 */ >+ IC_VEX_L_XD, /* 164 */ >+ IC_VEX_L_XD, /* 165 */ >+ IC_VEX_L_XD, /* 166 */ >+ IC_VEX_L_XD, /* 167 */ >+ IC_VEX_L_W, /* 168 */ >+ IC_VEX_L_W, /* 169 */ >+ IC_VEX_L_W_XS, /* 170 */ >+ IC_VEX_L_W_XS, /* 171 */ >+ IC_VEX_L_W_XD, /* 172 */ >+ IC_VEX_L_W_XD, /* 173 */ >+ IC_VEX_L_W_XD, /* 174 */ >+ IC_VEX_L_W_XD, /* 175 */ >+ IC_VEX_L_OPSIZE, /* 176 */ >+ IC_VEX_L_OPSIZE, /* 177 */ >+ IC_VEX_L_OPSIZE, /* 178 */ >+ IC_VEX_L_OPSIZE, /* 179 */ >+ IC_VEX_L_OPSIZE, /* 180 */ >+ IC_VEX_L_OPSIZE, /* 181 */ >+ IC_VEX_L_OPSIZE, /* 182 */ >+ IC_VEX_L_OPSIZE, /* 183 */ >+ IC_VEX_L_W_OPSIZE, /* 184 */ >+ IC_VEX_L_W_OPSIZE, /* 185 */ >+ IC_VEX_L_W_OPSIZE, /* 186 */ >+ IC_VEX_L_W_OPSIZE, /* 187 */ >+ IC_VEX_L_W_OPSIZE, /* 188 */ >+ IC_VEX_L_W_OPSIZE, /* 189 */ >+ IC_VEX_L_W_OPSIZE, /* 190 */ >+ IC_VEX_L_W_OPSIZE, /* 191 */ >+ IC_VEX_L, /* 192 */ >+ IC_VEX_L, /* 193 */ >+ IC_VEX_L_XS, /* 194 */ >+ IC_VEX_L_XS, /* 195 */ >+ IC_VEX_L_XD, /* 196 */ >+ IC_VEX_L_XD, /* 197 */ >+ IC_VEX_L_XD, /* 198 */ >+ IC_VEX_L_XD, /* 199 */ >+ IC_VEX_L_W, /* 200 */ >+ IC_VEX_L_W, /* 201 */ >+ IC_VEX_L_W_XS, /* 202 */ >+ IC_VEX_L_W_XS, /* 203 */ >+ IC_VEX_L_W_XD, /* 204 */ >+ IC_VEX_L_W_XD, /* 205 */ >+ IC_VEX_L_W_XD, /* 206 */ >+ IC_VEX_L_W_XD, /* 207 */ >+ IC_VEX_L_OPSIZE, /* 208 */ >+ IC_VEX_L_OPSIZE, /* 209 */ >+ IC_VEX_L_OPSIZE, /* 210 */ >+ IC_VEX_L_OPSIZE, /* 211 */ >+ IC_VEX_L_OPSIZE, /* 212 */ >+ IC_VEX_L_OPSIZE, /* 213 */ >+ IC_VEX_L_OPSIZE, /* 214 */ >+ IC_VEX_L_OPSIZE, /* 215 */ >+ IC_VEX_L_W_OPSIZE, /* 216 */ >+ IC_VEX_L_W_OPSIZE, /* 217 */ >+ IC_VEX_L_W_OPSIZE, /* 218 */ >+ IC_VEX_L_W_OPSIZE, /* 219 */ >+ IC_VEX_L_W_OPSIZE, /* 220 */ >+ IC_VEX_L_W_OPSIZE, /* 221 */ >+ IC_VEX_L_W_OPSIZE, /* 222 */ >+ IC_VEX_L_W_OPSIZE, /* 223 */ >+ IC_VEX_L, /* 224 */ >+ IC_VEX_L, /* 225 */ >+ IC_VEX_L_XS, /* 226 */ >+ IC_VEX_L_XS, /* 227 */ >+ IC_VEX_L_XD, /* 228 */ >+ IC_VEX_L_XD, /* 229 */ >+ IC_VEX_L_XD, /* 230 */ >+ IC_VEX_L_XD, /* 231 */ >+ IC_VEX_L_W, /* 232 */ >+ IC_VEX_L_W, /* 233 */ >+ IC_VEX_L_W_XS, /* 234 */ >+ IC_VEX_L_W_XS, /* 235 */ >+ IC_VEX_L_W_XD, /* 236 */ >+ IC_VEX_L_W_XD, /* 237 */ >+ IC_VEX_L_W_XD, /* 238 */ >+ IC_VEX_L_W_XD, /* 239 */ >+ IC_VEX_L_OPSIZE, /* 240 */ >+ IC_VEX_L_OPSIZE, /* 241 */ >+ IC_VEX_L_OPSIZE, /* 242 */ >+ IC_VEX_L_OPSIZE, /* 243 */ >+ IC_VEX_L_OPSIZE, /* 244 */ >+ IC_VEX_L_OPSIZE, /* 245 */ >+ IC_VEX_L_OPSIZE, /* 246 */ >+ IC_VEX_L_OPSIZE, /* 247 */ >+ IC_VEX_L_W_OPSIZE, /* 248 */ >+ IC_VEX_L_W_OPSIZE, /* 249 */ >+ IC_VEX_L_W_OPSIZE, /* 250 */ >+ IC_VEX_L_W_OPSIZE, /* 251 */ >+ IC_VEX_L_W_OPSIZE, /* 252 */ >+ IC_VEX_L_W_OPSIZE, /* 253 */ >+ IC_VEX_L_W_OPSIZE, /* 254 */ >+ IC_VEX_L_W_OPSIZE, /* 255 */ >+ IC_EVEX, /* 256 */ >+ IC_EVEX, /* 257 */ >+ IC_EVEX_XS, /* 258 */ >+ IC_EVEX_XS, /* 259 */ >+ IC_EVEX_XD, /* 260 */ >+ IC_EVEX_XD, /* 261 */ >+ IC_EVEX_XD, /* 262 */ >+ IC_EVEX_XD, /* 263 */ >+ IC_EVEX_W, /* 264 */ >+ IC_EVEX_W, /* 265 */ >+ IC_EVEX_W_XS, /* 266 */ >+ IC_EVEX_W_XS, /* 267 */ >+ IC_EVEX_W_XD, /* 268 */ >+ IC_EVEX_W_XD, /* 269 */ >+ IC_EVEX_W_XD, /* 270 */ >+ IC_EVEX_W_XD, /* 271 */ >+ IC_EVEX_OPSIZE, /* 272 */ >+ IC_EVEX_OPSIZE, /* 273 */ >+ IC_EVEX_OPSIZE, /* 274 */ >+ IC_EVEX_OPSIZE, /* 275 */ >+ IC_EVEX_OPSIZE, /* 276 */ >+ IC_EVEX_OPSIZE, /* 277 */ >+ IC_EVEX_OPSIZE, /* 278 */ >+ IC_EVEX_OPSIZE, /* 279 */ >+ IC_EVEX_W_OPSIZE, /* 280 */ >+ IC_EVEX_W_OPSIZE, /* 281 */ >+ IC_EVEX_W_OPSIZE, /* 282 */ >+ IC_EVEX_W_OPSIZE, /* 283 */ >+ IC_EVEX_W_OPSIZE, /* 284 */ >+ IC_EVEX_W_OPSIZE, /* 285 */ >+ IC_EVEX_W_OPSIZE, /* 286 */ >+ IC_EVEX_W_OPSIZE, /* 287 */ >+ IC_EVEX, /* 288 */ >+ IC_EVEX, /* 289 */ >+ IC_EVEX_XS, /* 290 */ >+ IC_EVEX_XS, /* 291 */ >+ IC_EVEX_XD, /* 292 */ >+ IC_EVEX_XD, /* 293 */ >+ IC_EVEX_XD, /* 294 */ >+ IC_EVEX_XD, /* 295 */ >+ IC_EVEX_W, /* 296 */ >+ IC_EVEX_W, /* 297 */ >+ IC_EVEX_W_XS, /* 298 */ >+ IC_EVEX_W_XS, /* 299 */ >+ IC_EVEX_W_XD, /* 300 */ >+ IC_EVEX_W_XD, /* 301 */ >+ IC_EVEX_W_XD, /* 302 */ >+ IC_EVEX_W_XD, /* 303 */ >+ IC_EVEX_OPSIZE, /* 304 */ >+ IC_EVEX_OPSIZE, /* 305 */ >+ IC_EVEX_OPSIZE, /* 306 */ >+ IC_EVEX_OPSIZE, /* 307 */ >+ IC_EVEX_OPSIZE, /* 308 */ >+ IC_EVEX_OPSIZE, /* 309 */ >+ IC_EVEX_OPSIZE, /* 310 */ >+ IC_EVEX_OPSIZE, /* 311 */ >+ IC_EVEX_W_OPSIZE, /* 312 */ >+ IC_EVEX_W_OPSIZE, /* 313 */ >+ IC_EVEX_W_OPSIZE, /* 314 */ >+ IC_EVEX_W_OPSIZE, /* 315 */ >+ IC_EVEX_W_OPSIZE, /* 316 */ >+ IC_EVEX_W_OPSIZE, /* 317 */ >+ IC_EVEX_W_OPSIZE, /* 318 */ >+ IC_EVEX_W_OPSIZE, /* 319 */ >+ IC_EVEX, /* 320 */ >+ IC_EVEX, /* 321 */ >+ IC_EVEX_XS, /* 322 */ >+ IC_EVEX_XS, /* 323 */ >+ IC_EVEX_XD, /* 324 */ >+ IC_EVEX_XD, /* 325 */ >+ IC_EVEX_XD, /* 326 */ >+ IC_EVEX_XD, /* 327 */ >+ IC_EVEX_W, /* 328 */ >+ IC_EVEX_W, /* 329 */ >+ IC_EVEX_W_XS, /* 330 */ >+ IC_EVEX_W_XS, /* 331 */ >+ IC_EVEX_W_XD, /* 332 */ >+ IC_EVEX_W_XD, /* 333 */ >+ IC_EVEX_W_XD, /* 334 */ >+ IC_EVEX_W_XD, /* 335 */ >+ IC_EVEX_OPSIZE, /* 336 */ >+ IC_EVEX_OPSIZE, /* 337 */ >+ IC_EVEX_OPSIZE, /* 338 */ >+ IC_EVEX_OPSIZE, /* 339 */ >+ IC_EVEX_OPSIZE, /* 340 */ >+ IC_EVEX_OPSIZE, /* 341 */ >+ IC_EVEX_OPSIZE, /* 342 */ >+ IC_EVEX_OPSIZE, /* 343 */ >+ IC_EVEX_W_OPSIZE, /* 344 */ >+ IC_EVEX_W_OPSIZE, /* 345 */ >+ IC_EVEX_W_OPSIZE, /* 346 */ >+ IC_EVEX_W_OPSIZE, /* 347 */ >+ IC_EVEX_W_OPSIZE, /* 348 */ >+ IC_EVEX_W_OPSIZE, /* 349 */ >+ IC_EVEX_W_OPSIZE, /* 350 */ >+ IC_EVEX_W_OPSIZE, /* 351 */ >+ IC_EVEX, /* 352 */ >+ IC_EVEX, /* 353 */ >+ IC_EVEX_XS, /* 354 */ >+ IC_EVEX_XS, /* 355 */ >+ IC_EVEX_XD, /* 356 */ >+ IC_EVEX_XD, /* 357 */ >+ IC_EVEX_XD, /* 358 */ >+ IC_EVEX_XD, /* 359 */ >+ IC_EVEX_W, /* 360 */ >+ IC_EVEX_W, /* 361 */ >+ IC_EVEX_W_XS, /* 362 */ >+ IC_EVEX_W_XS, /* 363 */ >+ IC_EVEX_W_XD, /* 364 */ >+ IC_EVEX_W_XD, /* 365 */ >+ IC_EVEX_W_XD, /* 366 */ >+ IC_EVEX_W_XD, /* 367 */ >+ IC_EVEX_OPSIZE, /* 368 */ >+ IC_EVEX_OPSIZE, /* 369 */ >+ IC_EVEX_OPSIZE, /* 370 */ >+ IC_EVEX_OPSIZE, /* 371 */ >+ IC_EVEX_OPSIZE, /* 372 */ >+ IC_EVEX_OPSIZE, /* 373 */ >+ IC_EVEX_OPSIZE, /* 374 */ >+ IC_EVEX_OPSIZE, /* 375 */ >+ IC_EVEX_W_OPSIZE, /* 376 */ >+ IC_EVEX_W_OPSIZE, /* 377 */ >+ IC_EVEX_W_OPSIZE, /* 378 */ >+ IC_EVEX_W_OPSIZE, /* 379 */ >+ IC_EVEX_W_OPSIZE, /* 380 */ >+ IC_EVEX_W_OPSIZE, /* 381 */ >+ IC_EVEX_W_OPSIZE, /* 382 */ >+ IC_EVEX_W_OPSIZE, /* 383 */ >+ IC_EVEX, /* 384 */ >+ IC_EVEX, /* 385 */ >+ IC_EVEX_XS, /* 386 */ >+ IC_EVEX_XS, /* 387 */ >+ IC_EVEX_XD, /* 388 */ >+ IC_EVEX_XD, /* 389 */ >+ IC_EVEX_XD, /* 390 */ >+ IC_EVEX_XD, /* 391 */ >+ IC_EVEX_W, /* 392 */ >+ IC_EVEX_W, /* 393 */ >+ IC_EVEX_W_XS, /* 394 */ >+ IC_EVEX_W_XS, /* 395 */ >+ IC_EVEX_W_XD, /* 396 */ >+ IC_EVEX_W_XD, /* 397 */ >+ IC_EVEX_W_XD, /* 398 */ >+ IC_EVEX_W_XD, /* 399 */ >+ IC_EVEX_OPSIZE, /* 400 */ >+ IC_EVEX_OPSIZE, /* 401 */ >+ IC_EVEX_OPSIZE, /* 402 */ >+ IC_EVEX_OPSIZE, /* 403 */ >+ IC_EVEX_OPSIZE, /* 404 */ >+ IC_EVEX_OPSIZE, /* 405 */ >+ IC_EVEX_OPSIZE, /* 406 */ >+ IC_EVEX_OPSIZE, /* 407 */ >+ IC_EVEX_W_OPSIZE, /* 408 */ >+ IC_EVEX_W_OPSIZE, /* 409 */ >+ IC_EVEX_W_OPSIZE, /* 410 */ >+ IC_EVEX_W_OPSIZE, /* 411 */ >+ IC_EVEX_W_OPSIZE, /* 412 */ >+ IC_EVEX_W_OPSIZE, /* 413 */ >+ IC_EVEX_W_OPSIZE, /* 414 */ >+ IC_EVEX_W_OPSIZE, /* 415 */ >+ IC_EVEX, /* 416 */ >+ IC_EVEX, /* 417 */ >+ IC_EVEX_XS, /* 418 */ >+ IC_EVEX_XS, /* 419 */ >+ IC_EVEX_XD, /* 420 */ >+ IC_EVEX_XD, /* 421 */ >+ IC_EVEX_XD, /* 422 */ >+ IC_EVEX_XD, /* 423 */ >+ IC_EVEX_W, /* 424 */ >+ IC_EVEX_W, /* 425 */ >+ IC_EVEX_W_XS, /* 426 */ >+ IC_EVEX_W_XS, /* 427 */ >+ IC_EVEX_W_XD, /* 428 */ >+ IC_EVEX_W_XD, /* 429 */ >+ IC_EVEX_W_XD, /* 430 */ >+ IC_EVEX_W_XD, /* 431 */ >+ IC_EVEX_OPSIZE, /* 432 */ >+ IC_EVEX_OPSIZE, /* 433 */ >+ IC_EVEX_OPSIZE, /* 434 */ >+ IC_EVEX_OPSIZE, /* 435 */ >+ IC_EVEX_OPSIZE, /* 436 */ >+ IC_EVEX_OPSIZE, /* 437 */ >+ IC_EVEX_OPSIZE, /* 438 */ >+ IC_EVEX_OPSIZE, /* 439 */ >+ IC_EVEX_W_OPSIZE, /* 440 */ >+ IC_EVEX_W_OPSIZE, /* 441 */ >+ IC_EVEX_W_OPSIZE, /* 442 */ >+ IC_EVEX_W_OPSIZE, /* 443 */ >+ IC_EVEX_W_OPSIZE, /* 444 */ >+ IC_EVEX_W_OPSIZE, /* 445 */ >+ IC_EVEX_W_OPSIZE, /* 446 */ >+ IC_EVEX_W_OPSIZE, /* 447 */ >+ IC_EVEX, /* 448 */ >+ IC_EVEX, /* 449 */ >+ IC_EVEX_XS, /* 450 */ >+ IC_EVEX_XS, /* 451 */ >+ IC_EVEX_XD, /* 452 */ >+ IC_EVEX_XD, /* 453 */ >+ IC_EVEX_XD, /* 454 */ >+ IC_EVEX_XD, /* 455 */ >+ IC_EVEX_W, /* 456 */ >+ IC_EVEX_W, /* 457 */ >+ IC_EVEX_W_XS, /* 458 */ >+ IC_EVEX_W_XS, /* 459 */ >+ IC_EVEX_W_XD, /* 460 */ >+ IC_EVEX_W_XD, /* 461 */ >+ IC_EVEX_W_XD, /* 462 */ >+ IC_EVEX_W_XD, /* 463 */ >+ IC_EVEX_OPSIZE, /* 464 */ >+ IC_EVEX_OPSIZE, /* 465 */ >+ IC_EVEX_OPSIZE, /* 466 */ >+ IC_EVEX_OPSIZE, /* 467 */ >+ IC_EVEX_OPSIZE, /* 468 */ >+ IC_EVEX_OPSIZE, /* 469 */ >+ IC_EVEX_OPSIZE, /* 470 */ >+ IC_EVEX_OPSIZE, /* 471 */ >+ IC_EVEX_W_OPSIZE, /* 472 */ >+ IC_EVEX_W_OPSIZE, /* 473 */ >+ IC_EVEX_W_OPSIZE, /* 474 */ >+ IC_EVEX_W_OPSIZE, /* 475 */ >+ IC_EVEX_W_OPSIZE, /* 476 */ >+ IC_EVEX_W_OPSIZE, /* 477 */ >+ IC_EVEX_W_OPSIZE, /* 478 */ >+ IC_EVEX_W_OPSIZE, /* 479 */ >+ IC_EVEX, /* 480 */ >+ IC_EVEX, /* 481 */ >+ IC_EVEX_XS, /* 482 */ >+ IC_EVEX_XS, /* 483 */ >+ IC_EVEX_XD, /* 484 */ >+ IC_EVEX_XD, /* 485 */ >+ IC_EVEX_XD, /* 486 */ >+ IC_EVEX_XD, /* 487 */ >+ IC_EVEX_W, /* 488 */ >+ IC_EVEX_W, /* 489 */ >+ IC_EVEX_W_XS, /* 490 */ >+ IC_EVEX_W_XS, /* 491 */ >+ IC_EVEX_W_XD, /* 492 */ >+ IC_EVEX_W_XD, /* 493 */ >+ IC_EVEX_W_XD, /* 494 */ >+ IC_EVEX_W_XD, /* 495 */ >+ IC_EVEX_OPSIZE, /* 496 */ >+ IC_EVEX_OPSIZE, /* 497 */ >+ IC_EVEX_OPSIZE, /* 498 */ >+ IC_EVEX_OPSIZE, /* 499 */ >+ IC_EVEX_OPSIZE, /* 500 */ >+ IC_EVEX_OPSIZE, /* 501 */ >+ IC_EVEX_OPSIZE, /* 502 */ >+ IC_EVEX_OPSIZE, /* 503 */ >+ IC_EVEX_W_OPSIZE, /* 504 */ >+ IC_EVEX_W_OPSIZE, /* 505 */ >+ IC_EVEX_W_OPSIZE, /* 506 */ >+ IC_EVEX_W_OPSIZE, /* 507 */ >+ IC_EVEX_W_OPSIZE, /* 508 */ >+ IC_EVEX_W_OPSIZE, /* 509 */ >+ IC_EVEX_W_OPSIZE, /* 510 */ >+ IC_EVEX_W_OPSIZE, /* 511 */ >+ IC, /* 512 */ >+ IC_64BIT, /* 513 */ >+ IC_XS, /* 514 */ >+ IC_64BIT_XS, /* 515 */ >+ IC_XD, /* 516 */ >+ IC_64BIT_XD, /* 517 */ >+ IC_XS, /* 518 */ >+ IC_64BIT_XS, /* 519 */ >+ IC, /* 520 */ >+ IC_64BIT_REXW, /* 521 */ >+ IC_XS, /* 522 */ >+ IC_64BIT_REXW_XS, /* 523 */ >+ IC_XD, /* 524 */ >+ IC_64BIT_REXW_XD, /* 525 */ >+ IC_XS, /* 526 */ >+ IC_64BIT_REXW_XS, /* 527 */ >+ IC_OPSIZE, /* 528 */ >+ IC_64BIT_OPSIZE, /* 529 */ >+ IC_XS_OPSIZE, /* 530 */ >+ IC_64BIT_XS_OPSIZE, /* 531 */ >+ IC_XD_OPSIZE, /* 532 */ >+ IC_64BIT_XD_OPSIZE, /* 533 */ >+ IC_XS_OPSIZE, /* 534 */ >+ IC_64BIT_XD_OPSIZE, /* 535 */ >+ IC_OPSIZE, /* 536 */ >+ IC_64BIT_REXW_OPSIZE, /* 537 */ >+ IC_XS_OPSIZE, /* 538 */ >+ IC_64BIT_REXW_XS, /* 539 */ >+ IC_XD_OPSIZE, /* 540 */ >+ IC_64BIT_REXW_XD, /* 541 */ >+ IC_XS_OPSIZE, /* 542 */ >+ IC_64BIT_REXW_XS, /* 543 */ >+ IC_ADSIZE, /* 544 */ >+ IC_64BIT_ADSIZE, /* 545 */ >+ IC_XS, /* 546 */ >+ IC_64BIT_XS, /* 547 */ >+ IC_XD, /* 548 */ >+ IC_64BIT_XD, /* 549 */ >+ IC_XS, /* 550 */ >+ IC_64BIT_XS, /* 551 */ >+ IC_ADSIZE, /* 552 */ >+ IC_64BIT_ADSIZE, /* 553 */ >+ IC_XS, /* 554 */ >+ IC_64BIT_REXW_XS, /* 555 */ >+ IC_XD, /* 556 */ >+ IC_64BIT_REXW_XD, /* 557 */ >+ IC_XS, /* 558 */ >+ IC_64BIT_REXW_XS, /* 559 */ >+ IC_OPSIZE, /* 560 */ >+ IC_64BIT_OPSIZE, /* 561 */ >+ IC_XS_OPSIZE, /* 562 */ >+ IC_64BIT_XS_OPSIZE, /* 563 */ >+ IC_XD_OPSIZE, /* 564 */ >+ IC_64BIT_XD_OPSIZE, /* 565 */ >+ IC_XS_OPSIZE, /* 566 */ >+ IC_64BIT_XD_OPSIZE, /* 567 */ >+ IC_OPSIZE, /* 568 */ >+ IC_64BIT_REXW_OPSIZE, /* 569 */ >+ IC_XS_OPSIZE, /* 570 */ >+ IC_64BIT_REXW_XS, /* 571 */ >+ IC_XD_OPSIZE, /* 572 */ >+ IC_64BIT_REXW_XD, /* 573 */ >+ IC_XS_OPSIZE, /* 574 */ >+ IC_64BIT_REXW_XS, /* 575 */ >+ IC_VEX, /* 576 */ >+ IC_VEX, /* 577 */ >+ IC_VEX_XS, /* 578 */ >+ IC_VEX_XS, /* 579 */ >+ IC_VEX_XD, /* 580 */ >+ IC_VEX_XD, /* 581 */ >+ IC_VEX_XD, /* 582 */ >+ IC_VEX_XD, /* 583 */ >+ IC_VEX_W, /* 584 */ >+ IC_VEX_W, /* 585 */ >+ IC_VEX_W_XS, /* 586 */ >+ IC_VEX_W_XS, /* 587 */ >+ IC_VEX_W_XD, /* 588 */ >+ IC_VEX_W_XD, /* 589 */ >+ IC_VEX_W_XD, /* 590 */ >+ IC_VEX_W_XD, /* 591 */ >+ IC_VEX_OPSIZE, /* 592 */ >+ IC_VEX_OPSIZE, /* 593 */ >+ IC_VEX_OPSIZE, /* 594 */ >+ IC_VEX_OPSIZE, /* 595 */ >+ IC_VEX_OPSIZE, /* 596 */ >+ IC_VEX_OPSIZE, /* 597 */ >+ IC_VEX_OPSIZE, /* 598 */ >+ IC_VEX_OPSIZE, /* 599 */ >+ IC_VEX_W_OPSIZE, /* 600 */ >+ IC_VEX_W_OPSIZE, /* 601 */ >+ IC_VEX_W_OPSIZE, /* 602 */ >+ IC_VEX_W_OPSIZE, /* 603 */ >+ IC_VEX_W_OPSIZE, /* 604 */ >+ IC_VEX_W_OPSIZE, /* 605 */ >+ IC_VEX_W_OPSIZE, /* 606 */ >+ IC_VEX_W_OPSIZE, /* 607 */ >+ IC_VEX, /* 608 */ >+ IC_VEX, /* 609 */ >+ IC_VEX_XS, /* 610 */ >+ IC_VEX_XS, /* 611 */ >+ IC_VEX_XD, /* 612 */ >+ IC_VEX_XD, /* 613 */ >+ IC_VEX_XD, /* 614 */ >+ IC_VEX_XD, /* 615 */ >+ IC_VEX_W, /* 616 */ >+ IC_VEX_W, /* 617 */ >+ IC_VEX_W_XS, /* 618 */ >+ IC_VEX_W_XS, /* 619 */ >+ IC_VEX_W_XD, /* 620 */ >+ IC_VEX_W_XD, /* 621 */ >+ IC_VEX_W_XD, /* 622 */ >+ IC_VEX_W_XD, /* 623 */ >+ IC_VEX_OPSIZE, /* 624 */ >+ IC_VEX_OPSIZE, /* 625 */ >+ IC_VEX_OPSIZE, /* 626 */ >+ IC_VEX_OPSIZE, /* 627 */ >+ IC_VEX_OPSIZE, /* 628 */ >+ IC_VEX_OPSIZE, /* 629 */ >+ IC_VEX_OPSIZE, /* 630 */ >+ IC_VEX_OPSIZE, /* 631 */ >+ IC_VEX_W_OPSIZE, /* 632 */ >+ IC_VEX_W_OPSIZE, /* 633 */ >+ IC_VEX_W_OPSIZE, /* 634 */ >+ IC_VEX_W_OPSIZE, /* 635 */ >+ IC_VEX_W_OPSIZE, /* 636 */ >+ IC_VEX_W_OPSIZE, /* 637 */ >+ IC_VEX_W_OPSIZE, /* 638 */ >+ IC_VEX_W_OPSIZE, /* 639 */ >+ IC_VEX_L, /* 640 */ >+ IC_VEX_L, /* 641 */ >+ IC_VEX_L_XS, /* 642 */ >+ IC_VEX_L_XS, /* 643 */ >+ IC_VEX_L_XD, /* 644 */ >+ IC_VEX_L_XD, /* 645 */ >+ IC_VEX_L_XD, /* 646 */ >+ IC_VEX_L_XD, /* 647 */ >+ IC_VEX_L_W, /* 648 */ >+ IC_VEX_L_W, /* 649 */ >+ IC_VEX_L_W_XS, /* 650 */ >+ IC_VEX_L_W_XS, /* 651 */ >+ IC_VEX_L_W_XD, /* 652 */ >+ IC_VEX_L_W_XD, /* 653 */ >+ IC_VEX_L_W_XD, /* 654 */ >+ IC_VEX_L_W_XD, /* 655 */ >+ IC_VEX_L_OPSIZE, /* 656 */ >+ IC_VEX_L_OPSIZE, /* 657 */ >+ IC_VEX_L_OPSIZE, /* 658 */ >+ IC_VEX_L_OPSIZE, /* 659 */ >+ IC_VEX_L_OPSIZE, /* 660 */ >+ IC_VEX_L_OPSIZE, /* 661 */ >+ IC_VEX_L_OPSIZE, /* 662 */ >+ IC_VEX_L_OPSIZE, /* 663 */ >+ IC_VEX_L_W_OPSIZE, /* 664 */ >+ IC_VEX_L_W_OPSIZE, /* 665 */ >+ IC_VEX_L_W_OPSIZE, /* 666 */ >+ IC_VEX_L_W_OPSIZE, /* 667 */ >+ IC_VEX_L_W_OPSIZE, /* 668 */ >+ IC_VEX_L_W_OPSIZE, /* 669 */ >+ IC_VEX_L_W_OPSIZE, /* 670 */ >+ IC_VEX_L_W_OPSIZE, /* 671 */ >+ IC_VEX_L, /* 672 */ >+ IC_VEX_L, /* 673 */ >+ IC_VEX_L_XS, /* 674 */ >+ IC_VEX_L_XS, /* 675 */ >+ IC_VEX_L_XD, /* 676 */ >+ IC_VEX_L_XD, /* 677 */ >+ IC_VEX_L_XD, /* 678 */ >+ IC_VEX_L_XD, /* 679 */ >+ IC_VEX_L_W, /* 680 */ >+ IC_VEX_L_W, /* 681 */ >+ IC_VEX_L_W_XS, /* 682 */ >+ IC_VEX_L_W_XS, /* 683 */ >+ IC_VEX_L_W_XD, /* 684 */ >+ IC_VEX_L_W_XD, /* 685 */ >+ IC_VEX_L_W_XD, /* 686 */ >+ IC_VEX_L_W_XD, /* 687 */ >+ IC_VEX_L_OPSIZE, /* 688 */ >+ IC_VEX_L_OPSIZE, /* 689 */ >+ IC_VEX_L_OPSIZE, /* 690 */ >+ IC_VEX_L_OPSIZE, /* 691 */ >+ IC_VEX_L_OPSIZE, /* 692 */ >+ IC_VEX_L_OPSIZE, /* 693 */ >+ IC_VEX_L_OPSIZE, /* 694 */ >+ IC_VEX_L_OPSIZE, /* 695 */ >+ IC_VEX_L_W_OPSIZE, /* 696 */ >+ IC_VEX_L_W_OPSIZE, /* 697 */ >+ IC_VEX_L_W_OPSIZE, /* 698 */ >+ IC_VEX_L_W_OPSIZE, /* 699 */ >+ IC_VEX_L_W_OPSIZE, /* 700 */ >+ IC_VEX_L_W_OPSIZE, /* 701 */ >+ IC_VEX_L_W_OPSIZE, /* 702 */ >+ IC_VEX_L_W_OPSIZE, /* 703 */ >+ IC_VEX_L, /* 704 */ >+ IC_VEX_L, /* 705 */ >+ IC_VEX_L_XS, /* 706 */ >+ IC_VEX_L_XS, /* 707 */ >+ IC_VEX_L_XD, /* 708 */ >+ IC_VEX_L_XD, /* 709 */ >+ IC_VEX_L_XD, /* 710 */ >+ IC_VEX_L_XD, /* 711 */ >+ IC_VEX_L_W, /* 712 */ >+ IC_VEX_L_W, /* 713 */ >+ IC_VEX_L_W_XS, /* 714 */ >+ IC_VEX_L_W_XS, /* 715 */ >+ IC_VEX_L_W_XD, /* 716 */ >+ IC_VEX_L_W_XD, /* 717 */ >+ IC_VEX_L_W_XD, /* 718 */ >+ IC_VEX_L_W_XD, /* 719 */ >+ IC_VEX_L_OPSIZE, /* 720 */ >+ IC_VEX_L_OPSIZE, /* 721 */ >+ IC_VEX_L_OPSIZE, /* 722 */ >+ IC_VEX_L_OPSIZE, /* 723 */ >+ IC_VEX_L_OPSIZE, /* 724 */ >+ IC_VEX_L_OPSIZE, /* 725 */ >+ IC_VEX_L_OPSIZE, /* 726 */ >+ IC_VEX_L_OPSIZE, /* 727 */ >+ IC_VEX_L_W_OPSIZE, /* 728 */ >+ IC_VEX_L_W_OPSIZE, /* 729 */ >+ IC_VEX_L_W_OPSIZE, /* 730 */ >+ IC_VEX_L_W_OPSIZE, /* 731 */ >+ IC_VEX_L_W_OPSIZE, /* 732 */ >+ IC_VEX_L_W_OPSIZE, /* 733 */ >+ IC_VEX_L_W_OPSIZE, /* 734 */ >+ IC_VEX_L_W_OPSIZE, /* 735 */ >+ IC_VEX_L, /* 736 */ >+ IC_VEX_L, /* 737 */ >+ IC_VEX_L_XS, /* 738 */ >+ IC_VEX_L_XS, /* 739 */ >+ IC_VEX_L_XD, /* 740 */ >+ IC_VEX_L_XD, /* 741 */ >+ IC_VEX_L_XD, /* 742 */ >+ IC_VEX_L_XD, /* 743 */ >+ IC_VEX_L_W, /* 744 */ >+ IC_VEX_L_W, /* 745 */ >+ IC_VEX_L_W_XS, /* 746 */ >+ IC_VEX_L_W_XS, /* 747 */ >+ IC_VEX_L_W_XD, /* 748 */ >+ IC_VEX_L_W_XD, /* 749 */ >+ IC_VEX_L_W_XD, /* 750 */ >+ IC_VEX_L_W_XD, /* 751 */ >+ IC_VEX_L_OPSIZE, /* 752 */ >+ IC_VEX_L_OPSIZE, /* 753 */ >+ IC_VEX_L_OPSIZE, /* 754 */ >+ IC_VEX_L_OPSIZE, /* 755 */ >+ IC_VEX_L_OPSIZE, /* 756 */ >+ IC_VEX_L_OPSIZE, /* 757 */ >+ IC_VEX_L_OPSIZE, /* 758 */ >+ IC_VEX_L_OPSIZE, /* 759 */ >+ IC_VEX_L_W_OPSIZE, /* 760 */ >+ IC_VEX_L_W_OPSIZE, /* 761 */ >+ IC_VEX_L_W_OPSIZE, /* 762 */ >+ IC_VEX_L_W_OPSIZE, /* 763 */ >+ IC_VEX_L_W_OPSIZE, /* 764 */ >+ IC_VEX_L_W_OPSIZE, /* 765 */ >+ IC_VEX_L_W_OPSIZE, /* 766 */ >+ IC_VEX_L_W_OPSIZE, /* 767 */ >+ IC_EVEX_L, /* 768 */ >+ IC_EVEX_L, /* 769 */ >+ IC_EVEX_L_XS, /* 770 */ >+ IC_EVEX_L_XS, /* 771 */ >+ IC_EVEX_L_XD, /* 772 */ >+ IC_EVEX_L_XD, /* 773 */ >+ IC_EVEX_L_XD, /* 774 */ >+ IC_EVEX_L_XD, /* 775 */ >+ IC_EVEX_L_W, /* 776 */ >+ IC_EVEX_L_W, /* 777 */ >+ IC_EVEX_L_W_XS, /* 778 */ >+ IC_EVEX_L_W_XS, /* 779 */ >+ IC_EVEX_L_W_XD, /* 780 */ >+ IC_EVEX_L_W_XD, /* 781 */ >+ IC_EVEX_L_W_XD, /* 782 */ >+ IC_EVEX_L_W_XD, /* 783 */ >+ IC_EVEX_L_OPSIZE, /* 784 */ >+ IC_EVEX_L_OPSIZE, /* 785 */ >+ IC_EVEX_L_OPSIZE, /* 786 */ >+ IC_EVEX_L_OPSIZE, /* 787 */ >+ IC_EVEX_L_OPSIZE, /* 788 */ >+ IC_EVEX_L_OPSIZE, /* 789 */ >+ IC_EVEX_L_OPSIZE, /* 790 */ >+ IC_EVEX_L_OPSIZE, /* 791 */ >+ IC_EVEX_L_W_OPSIZE, /* 792 */ >+ IC_EVEX_L_W_OPSIZE, /* 793 */ >+ IC_EVEX_L_W_OPSIZE, /* 794 */ >+ IC_EVEX_L_W_OPSIZE, /* 795 */ >+ IC_EVEX_L_W_OPSIZE, /* 796 */ >+ IC_EVEX_L_W_OPSIZE, /* 797 */ >+ IC_EVEX_L_W_OPSIZE, /* 798 */ >+ IC_EVEX_L_W_OPSIZE, /* 799 */ >+ IC_EVEX_L, /* 800 */ >+ IC_EVEX_L, /* 801 */ >+ IC_EVEX_L_XS, /* 802 */ >+ IC_EVEX_L_XS, /* 803 */ >+ IC_EVEX_L_XD, /* 804 */ >+ IC_EVEX_L_XD, /* 805 */ >+ IC_EVEX_L_XD, /* 806 */ >+ IC_EVEX_L_XD, /* 807 */ >+ IC_EVEX_L_W, /* 808 */ >+ IC_EVEX_L_W, /* 809 */ >+ IC_EVEX_L_W_XS, /* 810 */ >+ IC_EVEX_L_W_XS, /* 811 */ >+ IC_EVEX_L_W_XD, /* 812 */ >+ IC_EVEX_L_W_XD, /* 813 */ >+ IC_EVEX_L_W_XD, /* 814 */ >+ IC_EVEX_L_W_XD, /* 815 */ >+ IC_EVEX_L_OPSIZE, /* 816 */ >+ IC_EVEX_L_OPSIZE, /* 817 */ >+ IC_EVEX_L_OPSIZE, /* 818 */ >+ IC_EVEX_L_OPSIZE, /* 819 */ >+ IC_EVEX_L_OPSIZE, /* 820 */ >+ IC_EVEX_L_OPSIZE, /* 821 */ >+ IC_EVEX_L_OPSIZE, /* 822 */ >+ IC_EVEX_L_OPSIZE, /* 823 */ >+ IC_EVEX_L_W_OPSIZE, /* 824 */ >+ IC_EVEX_L_W_OPSIZE, /* 825 */ >+ IC_EVEX_L_W_OPSIZE, /* 826 */ >+ IC_EVEX_L_W_OPSIZE, /* 827 */ >+ IC_EVEX_L_W_OPSIZE, /* 828 */ >+ IC_EVEX_L_W_OPSIZE, /* 829 */ >+ IC_EVEX_L_W_OPSIZE, /* 830 */ >+ IC_EVEX_L_W_OPSIZE, /* 831 */ >+ IC_EVEX_L, /* 832 */ >+ IC_EVEX_L, /* 833 */ >+ IC_EVEX_L_XS, /* 834 */ >+ IC_EVEX_L_XS, /* 835 */ >+ IC_EVEX_L_XD, /* 836 */ >+ IC_EVEX_L_XD, /* 837 */ >+ IC_EVEX_L_XD, /* 838 */ >+ IC_EVEX_L_XD, /* 839 */ >+ IC_EVEX_L_W, /* 840 */ >+ IC_EVEX_L_W, /* 841 */ >+ IC_EVEX_L_W_XS, /* 842 */ >+ IC_EVEX_L_W_XS, /* 843 */ >+ IC_EVEX_L_W_XD, /* 844 */ >+ IC_EVEX_L_W_XD, /* 845 */ >+ IC_EVEX_L_W_XD, /* 846 */ >+ IC_EVEX_L_W_XD, /* 847 */ >+ IC_EVEX_L_OPSIZE, /* 848 */ >+ IC_EVEX_L_OPSIZE, /* 849 */ >+ IC_EVEX_L_OPSIZE, /* 850 */ >+ IC_EVEX_L_OPSIZE, /* 851 */ >+ IC_EVEX_L_OPSIZE, /* 852 */ >+ IC_EVEX_L_OPSIZE, /* 853 */ >+ IC_EVEX_L_OPSIZE, /* 854 */ >+ IC_EVEX_L_OPSIZE, /* 855 */ >+ IC_EVEX_L_W_OPSIZE, /* 856 */ >+ IC_EVEX_L_W_OPSIZE, /* 857 */ >+ IC_EVEX_L_W_OPSIZE, /* 858 */ >+ IC_EVEX_L_W_OPSIZE, /* 859 */ >+ IC_EVEX_L_W_OPSIZE, /* 860 */ >+ IC_EVEX_L_W_OPSIZE, /* 861 */ >+ IC_EVEX_L_W_OPSIZE, /* 862 */ >+ IC_EVEX_L_W_OPSIZE, /* 863 */ >+ IC_EVEX_L, /* 864 */ >+ IC_EVEX_L, /* 865 */ >+ IC_EVEX_L_XS, /* 866 */ >+ IC_EVEX_L_XS, /* 867 */ >+ IC_EVEX_L_XD, /* 868 */ >+ IC_EVEX_L_XD, /* 869 */ >+ IC_EVEX_L_XD, /* 870 */ >+ IC_EVEX_L_XD, /* 871 */ >+ IC_EVEX_L_W, /* 872 */ >+ IC_EVEX_L_W, /* 873 */ >+ IC_EVEX_L_W_XS, /* 874 */ >+ IC_EVEX_L_W_XS, /* 875 */ >+ IC_EVEX_L_W_XD, /* 876 */ >+ IC_EVEX_L_W_XD, /* 877 */ >+ IC_EVEX_L_W_XD, /* 878 */ >+ IC_EVEX_L_W_XD, /* 879 */ >+ IC_EVEX_L_OPSIZE, /* 880 */ >+ IC_EVEX_L_OPSIZE, /* 881 */ >+ IC_EVEX_L_OPSIZE, /* 882 */ >+ IC_EVEX_L_OPSIZE, /* 883 */ >+ IC_EVEX_L_OPSIZE, /* 884 */ >+ IC_EVEX_L_OPSIZE, /* 885 */ >+ IC_EVEX_L_OPSIZE, /* 886 */ >+ IC_EVEX_L_OPSIZE, /* 887 */ >+ IC_EVEX_L_W_OPSIZE, /* 888 */ >+ IC_EVEX_L_W_OPSIZE, /* 889 */ >+ IC_EVEX_L_W_OPSIZE, /* 890 */ >+ IC_EVEX_L_W_OPSIZE, /* 891 */ >+ IC_EVEX_L_W_OPSIZE, /* 892 */ >+ IC_EVEX_L_W_OPSIZE, /* 893 */ >+ IC_EVEX_L_W_OPSIZE, /* 894 */ >+ IC_EVEX_L_W_OPSIZE, /* 895 */ >+ IC_EVEX_L, /* 896 */ >+ IC_EVEX_L, /* 897 */ >+ IC_EVEX_L_XS, /* 898 */ >+ IC_EVEX_L_XS, /* 899 */ >+ IC_EVEX_L_XD, /* 900 */ >+ IC_EVEX_L_XD, /* 901 */ >+ IC_EVEX_L_XD, /* 902 */ >+ IC_EVEX_L_XD, /* 903 */ >+ IC_EVEX_L_W, /* 904 */ >+ IC_EVEX_L_W, /* 905 */ >+ IC_EVEX_L_W_XS, /* 906 */ >+ IC_EVEX_L_W_XS, /* 907 */ >+ IC_EVEX_L_W_XD, /* 908 */ >+ IC_EVEX_L_W_XD, /* 909 */ >+ IC_EVEX_L_W_XD, /* 910 */ >+ IC_EVEX_L_W_XD, /* 911 */ >+ IC_EVEX_L_OPSIZE, /* 912 */ >+ IC_EVEX_L_OPSIZE, /* 913 */ >+ IC_EVEX_L_OPSIZE, /* 914 */ >+ IC_EVEX_L_OPSIZE, /* 915 */ >+ IC_EVEX_L_OPSIZE, /* 916 */ >+ IC_EVEX_L_OPSIZE, /* 917 */ >+ IC_EVEX_L_OPSIZE, /* 918 */ >+ IC_EVEX_L_OPSIZE, /* 919 */ >+ IC_EVEX_L_W_OPSIZE, /* 920 */ >+ IC_EVEX_L_W_OPSIZE, /* 921 */ >+ IC_EVEX_L_W_OPSIZE, /* 922 */ >+ IC_EVEX_L_W_OPSIZE, /* 923 */ >+ IC_EVEX_L_W_OPSIZE, /* 924 */ >+ IC_EVEX_L_W_OPSIZE, /* 925 */ >+ IC_EVEX_L_W_OPSIZE, /* 926 */ >+ IC_EVEX_L_W_OPSIZE, /* 927 */ >+ IC_EVEX_L, /* 928 */ >+ IC_EVEX_L, /* 929 */ >+ IC_EVEX_L_XS, /* 930 */ >+ IC_EVEX_L_XS, /* 931 */ >+ IC_EVEX_L_XD, /* 932 */ >+ IC_EVEX_L_XD, /* 933 */ >+ IC_EVEX_L_XD, /* 934 */ >+ IC_EVEX_L_XD, /* 935 */ >+ IC_EVEX_L_W, /* 936 */ >+ IC_EVEX_L_W, /* 937 */ >+ IC_EVEX_L_W_XS, /* 938 */ >+ IC_EVEX_L_W_XS, /* 939 */ >+ IC_EVEX_L_W_XD, /* 940 */ >+ IC_EVEX_L_W_XD, /* 941 */ >+ IC_EVEX_L_W_XD, /* 942 */ >+ IC_EVEX_L_W_XD, /* 943 */ >+ IC_EVEX_L_OPSIZE, /* 944 */ >+ IC_EVEX_L_OPSIZE, /* 945 */ >+ IC_EVEX_L_OPSIZE, /* 946 */ >+ IC_EVEX_L_OPSIZE, /* 947 */ >+ IC_EVEX_L_OPSIZE, /* 948 */ >+ IC_EVEX_L_OPSIZE, /* 949 */ >+ IC_EVEX_L_OPSIZE, /* 950 */ >+ IC_EVEX_L_OPSIZE, /* 951 */ >+ IC_EVEX_L_W_OPSIZE, /* 952 */ >+ IC_EVEX_L_W_OPSIZE, /* 953 */ >+ IC_EVEX_L_W_OPSIZE, /* 954 */ >+ IC_EVEX_L_W_OPSIZE, /* 955 */ >+ IC_EVEX_L_W_OPSIZE, /* 956 */ >+ IC_EVEX_L_W_OPSIZE, /* 957 */ >+ IC_EVEX_L_W_OPSIZE, /* 958 */ >+ IC_EVEX_L_W_OPSIZE, /* 959 */ >+ IC_EVEX_L, /* 960 */ >+ IC_EVEX_L, /* 961 */ >+ IC_EVEX_L_XS, /* 962 */ >+ IC_EVEX_L_XS, /* 963 */ >+ IC_EVEX_L_XD, /* 964 */ >+ IC_EVEX_L_XD, /* 965 */ >+ IC_EVEX_L_XD, /* 966 */ >+ IC_EVEX_L_XD, /* 967 */ >+ IC_EVEX_L_W, /* 968 */ >+ IC_EVEX_L_W, /* 969 */ >+ IC_EVEX_L_W_XS, /* 970 */ >+ IC_EVEX_L_W_XS, /* 971 */ >+ IC_EVEX_L_W_XD, /* 972 */ >+ IC_EVEX_L_W_XD, /* 973 */ >+ IC_EVEX_L_W_XD, /* 974 */ >+ IC_EVEX_L_W_XD, /* 975 */ >+ IC_EVEX_L_OPSIZE, /* 976 */ >+ IC_EVEX_L_OPSIZE, /* 977 */ >+ IC_EVEX_L_OPSIZE, /* 978 */ >+ IC_EVEX_L_OPSIZE, /* 979 */ >+ IC_EVEX_L_OPSIZE, /* 980 */ >+ IC_EVEX_L_OPSIZE, /* 981 */ >+ IC_EVEX_L_OPSIZE, /* 982 */ >+ IC_EVEX_L_OPSIZE, /* 983 */ >+ IC_EVEX_L_W_OPSIZE, /* 984 */ >+ IC_EVEX_L_W_OPSIZE, /* 985 */ >+ IC_EVEX_L_W_OPSIZE, /* 986 */ >+ IC_EVEX_L_W_OPSIZE, /* 987 */ >+ IC_EVEX_L_W_OPSIZE, /* 988 */ >+ IC_EVEX_L_W_OPSIZE, /* 989 */ >+ IC_EVEX_L_W_OPSIZE, /* 990 */ >+ IC_EVEX_L_W_OPSIZE, /* 991 */ >+ IC_EVEX_L, /* 992 */ >+ IC_EVEX_L, /* 993 */ >+ IC_EVEX_L_XS, /* 994 */ >+ IC_EVEX_L_XS, /* 995 */ >+ IC_EVEX_L_XD, /* 996 */ >+ IC_EVEX_L_XD, /* 997 */ >+ IC_EVEX_L_XD, /* 998 */ >+ IC_EVEX_L_XD, /* 999 */ >+ IC_EVEX_L_W, /* 1000 */ >+ IC_EVEX_L_W, /* 1001 */ >+ IC_EVEX_L_W_XS, /* 1002 */ >+ IC_EVEX_L_W_XS, /* 1003 */ >+ IC_EVEX_L_W_XD, /* 1004 */ >+ IC_EVEX_L_W_XD, /* 1005 */ >+ IC_EVEX_L_W_XD, /* 1006 */ >+ IC_EVEX_L_W_XD, /* 1007 */ >+ IC_EVEX_L_OPSIZE, /* 1008 */ >+ IC_EVEX_L_OPSIZE, /* 1009 */ >+ IC_EVEX_L_OPSIZE, /* 1010 */ >+ IC_EVEX_L_OPSIZE, /* 1011 */ >+ IC_EVEX_L_OPSIZE, /* 1012 */ >+ IC_EVEX_L_OPSIZE, /* 1013 */ >+ IC_EVEX_L_OPSIZE, /* 1014 */ >+ IC_EVEX_L_OPSIZE, /* 1015 */ >+ IC_EVEX_L_W_OPSIZE, /* 1016 */ >+ IC_EVEX_L_W_OPSIZE, /* 1017 */ >+ IC_EVEX_L_W_OPSIZE, /* 1018 */ >+ IC_EVEX_L_W_OPSIZE, /* 1019 */ >+ IC_EVEX_L_W_OPSIZE, /* 1020 */ >+ IC_EVEX_L_W_OPSIZE, /* 1021 */ >+ IC_EVEX_L_W_OPSIZE, /* 1022 */ >+ IC_EVEX_L_W_OPSIZE, /* 1023 */ >+ IC, /* 1024 */ >+ IC_64BIT, /* 1025 */ >+ IC_XS, /* 1026 */ >+ IC_64BIT_XS, /* 1027 */ >+ IC_XD, /* 1028 */ >+ IC_64BIT_XD, /* 1029 */ >+ IC_XS, /* 1030 */ >+ IC_64BIT_XS, /* 1031 */ >+ IC, /* 1032 */ >+ IC_64BIT_REXW, /* 1033 */ >+ IC_XS, /* 1034 */ >+ IC_64BIT_REXW_XS, /* 1035 */ >+ IC_XD, /* 1036 */ >+ IC_64BIT_REXW_XD, /* 1037 */ >+ IC_XS, /* 1038 */ >+ IC_64BIT_REXW_XS, /* 1039 */ >+ IC_OPSIZE, /* 1040 */ >+ IC_64BIT_OPSIZE, /* 1041 */ >+ IC_XS_OPSIZE, /* 1042 */ >+ IC_64BIT_XS_OPSIZE, /* 1043 */ >+ IC_XD_OPSIZE, /* 1044 */ >+ IC_64BIT_XD_OPSIZE, /* 1045 */ >+ IC_XS_OPSIZE, /* 1046 */ >+ IC_64BIT_XD_OPSIZE, /* 1047 */ >+ IC_OPSIZE, /* 1048 */ >+ IC_64BIT_REXW_OPSIZE, /* 1049 */ >+ IC_XS_OPSIZE, /* 1050 */ >+ IC_64BIT_REXW_XS, /* 1051 */ >+ IC_XD_OPSIZE, /* 1052 */ >+ IC_64BIT_REXW_XD, /* 1053 */ >+ IC_XS_OPSIZE, /* 1054 */ >+ IC_64BIT_REXW_XS, /* 1055 */ >+ IC_ADSIZE, /* 1056 */ >+ IC_64BIT_ADSIZE, /* 1057 */ >+ IC_XS, /* 1058 */ >+ IC_64BIT_XS, /* 1059 */ >+ IC_XD, /* 1060 */ >+ IC_64BIT_XD, /* 1061 */ >+ IC_XS, /* 1062 */ >+ IC_64BIT_XS, /* 1063 */ >+ IC_ADSIZE, /* 1064 */ >+ IC_64BIT_ADSIZE, /* 1065 */ >+ IC_XS, /* 1066 */ >+ IC_64BIT_REXW_XS, /* 1067 */ >+ IC_XD, /* 1068 */ >+ IC_64BIT_REXW_XD, /* 1069 */ >+ IC_XS, /* 1070 */ >+ IC_64BIT_REXW_XS, /* 1071 */ >+ IC_OPSIZE, /* 1072 */ >+ IC_64BIT_OPSIZE, /* 1073 */ >+ IC_XS_OPSIZE, /* 1074 */ >+ IC_64BIT_XS_OPSIZE, /* 1075 */ >+ IC_XD_OPSIZE, /* 1076 */ >+ IC_64BIT_XD_OPSIZE, /* 1077 */ >+ IC_XS_OPSIZE, /* 1078 */ >+ IC_64BIT_XD_OPSIZE, /* 1079 */ >+ IC_OPSIZE, /* 1080 */ >+ IC_64BIT_REXW_OPSIZE, /* 1081 */ >+ IC_XS_OPSIZE, /* 1082 */ >+ IC_64BIT_REXW_XS, /* 1083 */ >+ IC_XD_OPSIZE, /* 1084 */ >+ IC_64BIT_REXW_XD, /* 1085 */ >+ IC_XS_OPSIZE, /* 1086 */ >+ IC_64BIT_REXW_XS, /* 1087 */ >+ IC_VEX, /* 1088 */ >+ IC_VEX, /* 1089 */ >+ IC_VEX_XS, /* 1090 */ >+ IC_VEX_XS, /* 1091 */ >+ IC_VEX_XD, /* 1092 */ >+ IC_VEX_XD, /* 1093 */ >+ IC_VEX_XD, /* 1094 */ >+ IC_VEX_XD, /* 1095 */ >+ IC_VEX_W, /* 1096 */ >+ IC_VEX_W, /* 1097 */ >+ IC_VEX_W_XS, /* 1098 */ >+ IC_VEX_W_XS, /* 1099 */ >+ IC_VEX_W_XD, /* 1100 */ >+ IC_VEX_W_XD, /* 1101 */ >+ IC_VEX_W_XD, /* 1102 */ >+ IC_VEX_W_XD, /* 1103 */ >+ IC_VEX_OPSIZE, /* 1104 */ >+ IC_VEX_OPSIZE, /* 1105 */ >+ IC_VEX_OPSIZE, /* 1106 */ >+ IC_VEX_OPSIZE, /* 1107 */ >+ IC_VEX_OPSIZE, /* 1108 */ >+ IC_VEX_OPSIZE, /* 1109 */ >+ IC_VEX_OPSIZE, /* 1110 */ >+ IC_VEX_OPSIZE, /* 1111 */ >+ IC_VEX_W_OPSIZE, /* 1112 */ >+ IC_VEX_W_OPSIZE, /* 1113 */ >+ IC_VEX_W_OPSIZE, /* 1114 */ >+ IC_VEX_W_OPSIZE, /* 1115 */ >+ IC_VEX_W_OPSIZE, /* 1116 */ >+ IC_VEX_W_OPSIZE, /* 1117 */ >+ IC_VEX_W_OPSIZE, /* 1118 */ >+ IC_VEX_W_OPSIZE, /* 1119 */ >+ IC_VEX, /* 1120 */ >+ IC_VEX, /* 1121 */ >+ IC_VEX_XS, /* 1122 */ >+ IC_VEX_XS, /* 1123 */ >+ IC_VEX_XD, /* 1124 */ >+ IC_VEX_XD, /* 1125 */ >+ IC_VEX_XD, /* 1126 */ >+ IC_VEX_XD, /* 1127 */ >+ IC_VEX_W, /* 1128 */ >+ IC_VEX_W, /* 1129 */ >+ IC_VEX_W_XS, /* 1130 */ >+ IC_VEX_W_XS, /* 1131 */ >+ IC_VEX_W_XD, /* 1132 */ >+ IC_VEX_W_XD, /* 1133 */ >+ IC_VEX_W_XD, /* 1134 */ >+ IC_VEX_W_XD, /* 1135 */ >+ IC_VEX_OPSIZE, /* 1136 */ >+ IC_VEX_OPSIZE, /* 1137 */ >+ IC_VEX_OPSIZE, /* 1138 */ >+ IC_VEX_OPSIZE, /* 1139 */ >+ IC_VEX_OPSIZE, /* 1140 */ >+ IC_VEX_OPSIZE, /* 1141 */ >+ IC_VEX_OPSIZE, /* 1142 */ >+ IC_VEX_OPSIZE, /* 1143 */ >+ IC_VEX_W_OPSIZE, /* 1144 */ >+ IC_VEX_W_OPSIZE, /* 1145 */ >+ IC_VEX_W_OPSIZE, /* 1146 */ >+ IC_VEX_W_OPSIZE, /* 1147 */ >+ IC_VEX_W_OPSIZE, /* 1148 */ >+ IC_VEX_W_OPSIZE, /* 1149 */ >+ IC_VEX_W_OPSIZE, /* 1150 */ >+ IC_VEX_W_OPSIZE, /* 1151 */ >+ IC_VEX_L, /* 1152 */ >+ IC_VEX_L, /* 1153 */ >+ IC_VEX_L_XS, /* 1154 */ >+ IC_VEX_L_XS, /* 1155 */ >+ IC_VEX_L_XD, /* 1156 */ >+ IC_VEX_L_XD, /* 1157 */ >+ IC_VEX_L_XD, /* 1158 */ >+ IC_VEX_L_XD, /* 1159 */ >+ IC_VEX_L_W, /* 1160 */ >+ IC_VEX_L_W, /* 1161 */ >+ IC_VEX_L_W_XS, /* 1162 */ >+ IC_VEX_L_W_XS, /* 1163 */ >+ IC_VEX_L_W_XD, /* 1164 */ >+ IC_VEX_L_W_XD, /* 1165 */ >+ IC_VEX_L_W_XD, /* 1166 */ >+ IC_VEX_L_W_XD, /* 1167 */ >+ IC_VEX_L_OPSIZE, /* 1168 */ >+ IC_VEX_L_OPSIZE, /* 1169 */ >+ IC_VEX_L_OPSIZE, /* 1170 */ >+ IC_VEX_L_OPSIZE, /* 1171 */ >+ IC_VEX_L_OPSIZE, /* 1172 */ >+ IC_VEX_L_OPSIZE, /* 1173 */ >+ IC_VEX_L_OPSIZE, /* 1174 */ >+ IC_VEX_L_OPSIZE, /* 1175 */ >+ IC_VEX_L_W_OPSIZE, /* 1176 */ >+ IC_VEX_L_W_OPSIZE, /* 1177 */ >+ IC_VEX_L_W_OPSIZE, /* 1178 */ >+ IC_VEX_L_W_OPSIZE, /* 1179 */ >+ IC_VEX_L_W_OPSIZE, /* 1180 */ >+ IC_VEX_L_W_OPSIZE, /* 1181 */ >+ IC_VEX_L_W_OPSIZE, /* 1182 */ >+ IC_VEX_L_W_OPSIZE, /* 1183 */ >+ IC_VEX_L, /* 1184 */ >+ IC_VEX_L, /* 1185 */ >+ IC_VEX_L_XS, /* 1186 */ >+ IC_VEX_L_XS, /* 1187 */ >+ IC_VEX_L_XD, /* 1188 */ >+ IC_VEX_L_XD, /* 1189 */ >+ IC_VEX_L_XD, /* 1190 */ >+ IC_VEX_L_XD, /* 1191 */ >+ IC_VEX_L_W, /* 1192 */ >+ IC_VEX_L_W, /* 1193 */ >+ IC_VEX_L_W_XS, /* 1194 */ >+ IC_VEX_L_W_XS, /* 1195 */ >+ IC_VEX_L_W_XD, /* 1196 */ >+ IC_VEX_L_W_XD, /* 1197 */ >+ IC_VEX_L_W_XD, /* 1198 */ >+ IC_VEX_L_W_XD, /* 1199 */ >+ IC_VEX_L_OPSIZE, /* 1200 */ >+ IC_VEX_L_OPSIZE, /* 1201 */ >+ IC_VEX_L_OPSIZE, /* 1202 */ >+ IC_VEX_L_OPSIZE, /* 1203 */ >+ IC_VEX_L_OPSIZE, /* 1204 */ >+ IC_VEX_L_OPSIZE, /* 1205 */ >+ IC_VEX_L_OPSIZE, /* 1206 */ >+ IC_VEX_L_OPSIZE, /* 1207 */ >+ IC_VEX_L_W_OPSIZE, /* 1208 */ >+ IC_VEX_L_W_OPSIZE, /* 1209 */ >+ IC_VEX_L_W_OPSIZE, /* 1210 */ >+ IC_VEX_L_W_OPSIZE, /* 1211 */ >+ IC_VEX_L_W_OPSIZE, /* 1212 */ >+ IC_VEX_L_W_OPSIZE, /* 1213 */ >+ IC_VEX_L_W_OPSIZE, /* 1214 */ >+ IC_VEX_L_W_OPSIZE, /* 1215 */ >+ IC_VEX_L, /* 1216 */ >+ IC_VEX_L, /* 1217 */ >+ IC_VEX_L_XS, /* 1218 */ >+ IC_VEX_L_XS, /* 1219 */ >+ IC_VEX_L_XD, /* 1220 */ >+ IC_VEX_L_XD, /* 1221 */ >+ IC_VEX_L_XD, /* 1222 */ >+ IC_VEX_L_XD, /* 1223 */ >+ IC_VEX_L_W, /* 1224 */ >+ IC_VEX_L_W, /* 1225 */ >+ IC_VEX_L_W_XS, /* 1226 */ >+ IC_VEX_L_W_XS, /* 1227 */ >+ IC_VEX_L_W_XD, /* 1228 */ >+ IC_VEX_L_W_XD, /* 1229 */ >+ IC_VEX_L_W_XD, /* 1230 */ >+ IC_VEX_L_W_XD, /* 1231 */ >+ IC_VEX_L_OPSIZE, /* 1232 */ >+ IC_VEX_L_OPSIZE, /* 1233 */ >+ IC_VEX_L_OPSIZE, /* 1234 */ >+ IC_VEX_L_OPSIZE, /* 1235 */ >+ IC_VEX_L_OPSIZE, /* 1236 */ >+ IC_VEX_L_OPSIZE, /* 1237 */ >+ IC_VEX_L_OPSIZE, /* 1238 */ >+ IC_VEX_L_OPSIZE, /* 1239 */ >+ IC_VEX_L_W_OPSIZE, /* 1240 */ >+ IC_VEX_L_W_OPSIZE, /* 1241 */ >+ IC_VEX_L_W_OPSIZE, /* 1242 */ >+ IC_VEX_L_W_OPSIZE, /* 1243 */ >+ IC_VEX_L_W_OPSIZE, /* 1244 */ >+ IC_VEX_L_W_OPSIZE, /* 1245 */ >+ IC_VEX_L_W_OPSIZE, /* 1246 */ >+ IC_VEX_L_W_OPSIZE, /* 1247 */ >+ IC_VEX_L, /* 1248 */ >+ IC_VEX_L, /* 1249 */ >+ IC_VEX_L_XS, /* 1250 */ >+ IC_VEX_L_XS, /* 1251 */ >+ IC_VEX_L_XD, /* 1252 */ >+ IC_VEX_L_XD, /* 1253 */ >+ IC_VEX_L_XD, /* 1254 */ >+ IC_VEX_L_XD, /* 1255 */ >+ IC_VEX_L_W, /* 1256 */ >+ IC_VEX_L_W, /* 1257 */ >+ IC_VEX_L_W_XS, /* 1258 */ >+ IC_VEX_L_W_XS, /* 1259 */ >+ IC_VEX_L_W_XD, /* 1260 */ >+ IC_VEX_L_W_XD, /* 1261 */ >+ IC_VEX_L_W_XD, /* 1262 */ >+ IC_VEX_L_W_XD, /* 1263 */ >+ IC_VEX_L_OPSIZE, /* 1264 */ >+ IC_VEX_L_OPSIZE, /* 1265 */ >+ IC_VEX_L_OPSIZE, /* 1266 */ >+ IC_VEX_L_OPSIZE, /* 1267 */ >+ IC_VEX_L_OPSIZE, /* 1268 */ >+ IC_VEX_L_OPSIZE, /* 1269 */ >+ IC_VEX_L_OPSIZE, /* 1270 */ >+ IC_VEX_L_OPSIZE, /* 1271 */ >+ IC_VEX_L_W_OPSIZE, /* 1272 */ >+ IC_VEX_L_W_OPSIZE, /* 1273 */ >+ IC_VEX_L_W_OPSIZE, /* 1274 */ >+ IC_VEX_L_W_OPSIZE, /* 1275 */ >+ IC_VEX_L_W_OPSIZE, /* 1276 */ >+ IC_VEX_L_W_OPSIZE, /* 1277 */ >+ IC_VEX_L_W_OPSIZE, /* 1278 */ >+ IC_VEX_L_W_OPSIZE, /* 1279 */ >+ IC_EVEX_L2, /* 1280 */ >+ IC_EVEX_L2, /* 1281 */ >+ IC_EVEX_L2_XS, /* 1282 */ >+ IC_EVEX_L2_XS, /* 1283 */ >+ IC_EVEX_L2_XD, /* 1284 */ >+ IC_EVEX_L2_XD, /* 1285 */ >+ IC_EVEX_L2_XD, /* 1286 */ >+ IC_EVEX_L2_XD, /* 1287 */ >+ IC_EVEX_L2_W, /* 1288 */ >+ IC_EVEX_L2_W, /* 1289 */ >+ IC_EVEX_L2_W_XS, /* 1290 */ >+ IC_EVEX_L2_W_XS, /* 1291 */ >+ IC_EVEX_L2_W_XD, /* 1292 */ >+ IC_EVEX_L2_W_XD, /* 1293 */ >+ IC_EVEX_L2_W_XD, /* 1294 */ >+ IC_EVEX_L2_W_XD, /* 1295 */ >+ IC_EVEX_L2_OPSIZE, /* 1296 */ >+ IC_EVEX_L2_OPSIZE, /* 1297 */ >+ IC_EVEX_L2_OPSIZE, /* 1298 */ >+ IC_EVEX_L2_OPSIZE, /* 1299 */ >+ IC_EVEX_L2_OPSIZE, /* 1300 */ >+ IC_EVEX_L2_OPSIZE, /* 1301 */ >+ IC_EVEX_L2_OPSIZE, /* 1302 */ >+ IC_EVEX_L2_OPSIZE, /* 1303 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1304 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1305 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1306 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1307 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1308 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1309 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1310 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1311 */ >+ IC_EVEX_L2, /* 1312 */ >+ IC_EVEX_L2, /* 1313 */ >+ IC_EVEX_L2_XS, /* 1314 */ >+ IC_EVEX_L2_XS, /* 1315 */ >+ IC_EVEX_L2_XD, /* 1316 */ >+ IC_EVEX_L2_XD, /* 1317 */ >+ IC_EVEX_L2_XD, /* 1318 */ >+ IC_EVEX_L2_XD, /* 1319 */ >+ IC_EVEX_L2_W, /* 1320 */ >+ IC_EVEX_L2_W, /* 1321 */ >+ IC_EVEX_L2_W_XS, /* 1322 */ >+ IC_EVEX_L2_W_XS, /* 1323 */ >+ IC_EVEX_L2_W_XD, /* 1324 */ >+ IC_EVEX_L2_W_XD, /* 1325 */ >+ IC_EVEX_L2_W_XD, /* 1326 */ >+ IC_EVEX_L2_W_XD, /* 1327 */ >+ IC_EVEX_L2_OPSIZE, /* 1328 */ >+ IC_EVEX_L2_OPSIZE, /* 1329 */ >+ IC_EVEX_L2_OPSIZE, /* 1330 */ >+ IC_EVEX_L2_OPSIZE, /* 1331 */ >+ IC_EVEX_L2_OPSIZE, /* 1332 */ >+ IC_EVEX_L2_OPSIZE, /* 1333 */ >+ IC_EVEX_L2_OPSIZE, /* 1334 */ >+ IC_EVEX_L2_OPSIZE, /* 1335 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1336 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1337 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1338 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1339 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1340 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1341 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1342 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1343 */ >+ IC_EVEX_L2, /* 1344 */ >+ IC_EVEX_L2, /* 1345 */ >+ IC_EVEX_L2_XS, /* 1346 */ >+ IC_EVEX_L2_XS, /* 1347 */ >+ IC_EVEX_L2_XD, /* 1348 */ >+ IC_EVEX_L2_XD, /* 1349 */ >+ IC_EVEX_L2_XD, /* 1350 */ >+ IC_EVEX_L2_XD, /* 1351 */ >+ IC_EVEX_L2_W, /* 1352 */ >+ IC_EVEX_L2_W, /* 1353 */ >+ IC_EVEX_L2_W_XS, /* 1354 */ >+ IC_EVEX_L2_W_XS, /* 1355 */ >+ IC_EVEX_L2_W_XD, /* 1356 */ >+ IC_EVEX_L2_W_XD, /* 1357 */ >+ IC_EVEX_L2_W_XD, /* 1358 */ >+ IC_EVEX_L2_W_XD, /* 1359 */ >+ IC_EVEX_L2_OPSIZE, /* 1360 */ >+ IC_EVEX_L2_OPSIZE, /* 1361 */ >+ IC_EVEX_L2_OPSIZE, /* 1362 */ >+ IC_EVEX_L2_OPSIZE, /* 1363 */ >+ IC_EVEX_L2_OPSIZE, /* 1364 */ >+ IC_EVEX_L2_OPSIZE, /* 1365 */ >+ IC_EVEX_L2_OPSIZE, /* 1366 */ >+ IC_EVEX_L2_OPSIZE, /* 1367 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1368 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1369 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1370 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1371 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1372 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1373 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1374 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1375 */ >+ IC_EVEX_L2, /* 1376 */ >+ IC_EVEX_L2, /* 1377 */ >+ IC_EVEX_L2_XS, /* 1378 */ >+ IC_EVEX_L2_XS, /* 1379 */ >+ IC_EVEX_L2_XD, /* 1380 */ >+ IC_EVEX_L2_XD, /* 1381 */ >+ IC_EVEX_L2_XD, /* 1382 */ >+ IC_EVEX_L2_XD, /* 1383 */ >+ IC_EVEX_L2_W, /* 1384 */ >+ IC_EVEX_L2_W, /* 1385 */ >+ IC_EVEX_L2_W_XS, /* 1386 */ >+ IC_EVEX_L2_W_XS, /* 1387 */ >+ IC_EVEX_L2_W_XD, /* 1388 */ >+ IC_EVEX_L2_W_XD, /* 1389 */ >+ IC_EVEX_L2_W_XD, /* 1390 */ >+ IC_EVEX_L2_W_XD, /* 1391 */ >+ IC_EVEX_L2_OPSIZE, /* 1392 */ >+ IC_EVEX_L2_OPSIZE, /* 1393 */ >+ IC_EVEX_L2_OPSIZE, /* 1394 */ >+ IC_EVEX_L2_OPSIZE, /* 1395 */ >+ IC_EVEX_L2_OPSIZE, /* 1396 */ >+ IC_EVEX_L2_OPSIZE, /* 1397 */ >+ IC_EVEX_L2_OPSIZE, /* 1398 */ >+ IC_EVEX_L2_OPSIZE, /* 1399 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1400 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1401 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1402 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1403 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1404 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1405 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1406 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1407 */ >+ IC_EVEX_L2, /* 1408 */ >+ IC_EVEX_L2, /* 1409 */ >+ IC_EVEX_L2_XS, /* 1410 */ >+ IC_EVEX_L2_XS, /* 1411 */ >+ IC_EVEX_L2_XD, /* 1412 */ >+ IC_EVEX_L2_XD, /* 1413 */ >+ IC_EVEX_L2_XD, /* 1414 */ >+ IC_EVEX_L2_XD, /* 1415 */ >+ IC_EVEX_L2_W, /* 1416 */ >+ IC_EVEX_L2_W, /* 1417 */ >+ IC_EVEX_L2_W_XS, /* 1418 */ >+ IC_EVEX_L2_W_XS, /* 1419 */ >+ IC_EVEX_L2_W_XD, /* 1420 */ >+ IC_EVEX_L2_W_XD, /* 1421 */ >+ IC_EVEX_L2_W_XD, /* 1422 */ >+ IC_EVEX_L2_W_XD, /* 1423 */ >+ IC_EVEX_L2_OPSIZE, /* 1424 */ >+ IC_EVEX_L2_OPSIZE, /* 1425 */ >+ IC_EVEX_L2_OPSIZE, /* 1426 */ >+ IC_EVEX_L2_OPSIZE, /* 1427 */ >+ IC_EVEX_L2_OPSIZE, /* 1428 */ >+ IC_EVEX_L2_OPSIZE, /* 1429 */ >+ IC_EVEX_L2_OPSIZE, /* 1430 */ >+ IC_EVEX_L2_OPSIZE, /* 1431 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1432 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1433 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1434 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1435 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1436 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1437 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1438 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1439 */ >+ IC_EVEX_L2, /* 1440 */ >+ IC_EVEX_L2, /* 1441 */ >+ IC_EVEX_L2_XS, /* 1442 */ >+ IC_EVEX_L2_XS, /* 1443 */ >+ IC_EVEX_L2_XD, /* 1444 */ >+ IC_EVEX_L2_XD, /* 1445 */ >+ IC_EVEX_L2_XD, /* 1446 */ >+ IC_EVEX_L2_XD, /* 1447 */ >+ IC_EVEX_L2_W, /* 1448 */ >+ IC_EVEX_L2_W, /* 1449 */ >+ IC_EVEX_L2_W_XS, /* 1450 */ >+ IC_EVEX_L2_W_XS, /* 1451 */ >+ IC_EVEX_L2_W_XD, /* 1452 */ >+ IC_EVEX_L2_W_XD, /* 1453 */ >+ IC_EVEX_L2_W_XD, /* 1454 */ >+ IC_EVEX_L2_W_XD, /* 1455 */ >+ IC_EVEX_L2_OPSIZE, /* 1456 */ >+ IC_EVEX_L2_OPSIZE, /* 1457 */ >+ IC_EVEX_L2_OPSIZE, /* 1458 */ >+ IC_EVEX_L2_OPSIZE, /* 1459 */ >+ IC_EVEX_L2_OPSIZE, /* 1460 */ >+ IC_EVEX_L2_OPSIZE, /* 1461 */ >+ IC_EVEX_L2_OPSIZE, /* 1462 */ >+ IC_EVEX_L2_OPSIZE, /* 1463 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1464 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1465 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1466 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1467 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1468 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1469 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1470 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1471 */ >+ IC_EVEX_L2, /* 1472 */ >+ IC_EVEX_L2, /* 1473 */ >+ IC_EVEX_L2_XS, /* 1474 */ >+ IC_EVEX_L2_XS, /* 1475 */ >+ IC_EVEX_L2_XD, /* 1476 */ >+ IC_EVEX_L2_XD, /* 1477 */ >+ IC_EVEX_L2_XD, /* 1478 */ >+ IC_EVEX_L2_XD, /* 1479 */ >+ IC_EVEX_L2_W, /* 1480 */ >+ IC_EVEX_L2_W, /* 1481 */ >+ IC_EVEX_L2_W_XS, /* 1482 */ >+ IC_EVEX_L2_W_XS, /* 1483 */ >+ IC_EVEX_L2_W_XD, /* 1484 */ >+ IC_EVEX_L2_W_XD, /* 1485 */ >+ IC_EVEX_L2_W_XD, /* 1486 */ >+ IC_EVEX_L2_W_XD, /* 1487 */ >+ IC_EVEX_L2_OPSIZE, /* 1488 */ >+ IC_EVEX_L2_OPSIZE, /* 1489 */ >+ IC_EVEX_L2_OPSIZE, /* 1490 */ >+ IC_EVEX_L2_OPSIZE, /* 1491 */ >+ IC_EVEX_L2_OPSIZE, /* 1492 */ >+ IC_EVEX_L2_OPSIZE, /* 1493 */ >+ IC_EVEX_L2_OPSIZE, /* 1494 */ >+ IC_EVEX_L2_OPSIZE, /* 1495 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1496 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1497 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1498 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1499 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1500 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1501 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1502 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1503 */ >+ IC_EVEX_L2, /* 1504 */ >+ IC_EVEX_L2, /* 1505 */ >+ IC_EVEX_L2_XS, /* 1506 */ >+ IC_EVEX_L2_XS, /* 1507 */ >+ IC_EVEX_L2_XD, /* 1508 */ >+ IC_EVEX_L2_XD, /* 1509 */ >+ IC_EVEX_L2_XD, /* 1510 */ >+ IC_EVEX_L2_XD, /* 1511 */ >+ IC_EVEX_L2_W, /* 1512 */ >+ IC_EVEX_L2_W, /* 1513 */ >+ IC_EVEX_L2_W_XS, /* 1514 */ >+ IC_EVEX_L2_W_XS, /* 1515 */ >+ IC_EVEX_L2_W_XD, /* 1516 */ >+ IC_EVEX_L2_W_XD, /* 1517 */ >+ IC_EVEX_L2_W_XD, /* 1518 */ >+ IC_EVEX_L2_W_XD, /* 1519 */ >+ IC_EVEX_L2_OPSIZE, /* 1520 */ >+ IC_EVEX_L2_OPSIZE, /* 1521 */ >+ IC_EVEX_L2_OPSIZE, /* 1522 */ >+ IC_EVEX_L2_OPSIZE, /* 1523 */ >+ IC_EVEX_L2_OPSIZE, /* 1524 */ >+ IC_EVEX_L2_OPSIZE, /* 1525 */ >+ IC_EVEX_L2_OPSIZE, /* 1526 */ >+ IC_EVEX_L2_OPSIZE, /* 1527 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1528 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1529 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1530 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1531 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1532 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1533 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1534 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1535 */ >+ IC, /* 1536 */ >+ IC_64BIT, /* 1537 */ >+ IC_XS, /* 1538 */ >+ IC_64BIT_XS, /* 1539 */ >+ IC_XD, /* 1540 */ >+ IC_64BIT_XD, /* 1541 */ >+ IC_XS, /* 1542 */ >+ IC_64BIT_XS, /* 1543 */ >+ IC, /* 1544 */ >+ IC_64BIT_REXW, /* 1545 */ >+ IC_XS, /* 1546 */ >+ IC_64BIT_REXW_XS, /* 1547 */ >+ IC_XD, /* 1548 */ >+ IC_64BIT_REXW_XD, /* 1549 */ >+ IC_XS, /* 1550 */ >+ IC_64BIT_REXW_XS, /* 1551 */ >+ IC_OPSIZE, /* 1552 */ >+ IC_64BIT_OPSIZE, /* 1553 */ >+ IC_XS_OPSIZE, /* 1554 */ >+ IC_64BIT_XS_OPSIZE, /* 1555 */ >+ IC_XD_OPSIZE, /* 1556 */ >+ IC_64BIT_XD_OPSIZE, /* 1557 */ >+ IC_XS_OPSIZE, /* 1558 */ >+ IC_64BIT_XD_OPSIZE, /* 1559 */ >+ IC_OPSIZE, /* 1560 */ >+ IC_64BIT_REXW_OPSIZE, /* 1561 */ >+ IC_XS_OPSIZE, /* 1562 */ >+ IC_64BIT_REXW_XS, /* 1563 */ >+ IC_XD_OPSIZE, /* 1564 */ >+ IC_64BIT_REXW_XD, /* 1565 */ >+ IC_XS_OPSIZE, /* 1566 */ >+ IC_64BIT_REXW_XS, /* 1567 */ >+ IC_ADSIZE, /* 1568 */ >+ IC_64BIT_ADSIZE, /* 1569 */ >+ IC_XS, /* 1570 */ >+ IC_64BIT_XS, /* 1571 */ >+ IC_XD, /* 1572 */ >+ IC_64BIT_XD, /* 1573 */ >+ IC_XS, /* 1574 */ >+ IC_64BIT_XS, /* 1575 */ >+ IC_ADSIZE, /* 1576 */ >+ IC_64BIT_ADSIZE, /* 1577 */ >+ IC_XS, /* 1578 */ >+ IC_64BIT_REXW_XS, /* 1579 */ >+ IC_XD, /* 1580 */ >+ IC_64BIT_REXW_XD, /* 1581 */ >+ IC_XS, /* 1582 */ >+ IC_64BIT_REXW_XS, /* 1583 */ >+ IC_OPSIZE, /* 1584 */ >+ IC_64BIT_OPSIZE, /* 1585 */ >+ IC_XS_OPSIZE, /* 1586 */ >+ IC_64BIT_XS_OPSIZE, /* 1587 */ >+ IC_XD_OPSIZE, /* 1588 */ >+ IC_64BIT_XD_OPSIZE, /* 1589 */ >+ IC_XS_OPSIZE, /* 1590 */ >+ IC_64BIT_XD_OPSIZE, /* 1591 */ >+ IC_OPSIZE, /* 1592 */ >+ IC_64BIT_REXW_OPSIZE, /* 1593 */ >+ IC_XS_OPSIZE, /* 1594 */ >+ IC_64BIT_REXW_XS, /* 1595 */ >+ IC_XD_OPSIZE, /* 1596 */ >+ IC_64BIT_REXW_XD, /* 1597 */ >+ IC_XS_OPSIZE, /* 1598 */ >+ IC_64BIT_REXW_XS, /* 1599 */ >+ IC_VEX, /* 1600 */ >+ IC_VEX, /* 1601 */ >+ IC_VEX_XS, /* 1602 */ >+ IC_VEX_XS, /* 1603 */ >+ IC_VEX_XD, /* 1604 */ >+ IC_VEX_XD, /* 1605 */ >+ IC_VEX_XD, /* 1606 */ >+ IC_VEX_XD, /* 1607 */ >+ IC_VEX_W, /* 1608 */ >+ IC_VEX_W, /* 1609 */ >+ IC_VEX_W_XS, /* 1610 */ >+ IC_VEX_W_XS, /* 1611 */ >+ IC_VEX_W_XD, /* 1612 */ >+ IC_VEX_W_XD, /* 1613 */ >+ IC_VEX_W_XD, /* 1614 */ >+ IC_VEX_W_XD, /* 1615 */ >+ IC_VEX_OPSIZE, /* 1616 */ >+ IC_VEX_OPSIZE, /* 1617 */ >+ IC_VEX_OPSIZE, /* 1618 */ >+ IC_VEX_OPSIZE, /* 1619 */ >+ IC_VEX_OPSIZE, /* 1620 */ >+ IC_VEX_OPSIZE, /* 1621 */ >+ IC_VEX_OPSIZE, /* 1622 */ >+ IC_VEX_OPSIZE, /* 1623 */ >+ IC_VEX_W_OPSIZE, /* 1624 */ >+ IC_VEX_W_OPSIZE, /* 1625 */ >+ IC_VEX_W_OPSIZE, /* 1626 */ >+ IC_VEX_W_OPSIZE, /* 1627 */ >+ IC_VEX_W_OPSIZE, /* 1628 */ >+ IC_VEX_W_OPSIZE, /* 1629 */ >+ IC_VEX_W_OPSIZE, /* 1630 */ >+ IC_VEX_W_OPSIZE, /* 1631 */ >+ IC_VEX, /* 1632 */ >+ IC_VEX, /* 1633 */ >+ IC_VEX_XS, /* 1634 */ >+ IC_VEX_XS, /* 1635 */ >+ IC_VEX_XD, /* 1636 */ >+ IC_VEX_XD, /* 1637 */ >+ IC_VEX_XD, /* 1638 */ >+ IC_VEX_XD, /* 1639 */ >+ IC_VEX_W, /* 1640 */ >+ IC_VEX_W, /* 1641 */ >+ IC_VEX_W_XS, /* 1642 */ >+ IC_VEX_W_XS, /* 1643 */ >+ IC_VEX_W_XD, /* 1644 */ >+ IC_VEX_W_XD, /* 1645 */ >+ IC_VEX_W_XD, /* 1646 */ >+ IC_VEX_W_XD, /* 1647 */ >+ IC_VEX_OPSIZE, /* 1648 */ >+ IC_VEX_OPSIZE, /* 1649 */ >+ IC_VEX_OPSIZE, /* 1650 */ >+ IC_VEX_OPSIZE, /* 1651 */ >+ IC_VEX_OPSIZE, /* 1652 */ >+ IC_VEX_OPSIZE, /* 1653 */ >+ IC_VEX_OPSIZE, /* 1654 */ >+ IC_VEX_OPSIZE, /* 1655 */ >+ IC_VEX_W_OPSIZE, /* 1656 */ >+ IC_VEX_W_OPSIZE, /* 1657 */ >+ IC_VEX_W_OPSIZE, /* 1658 */ >+ IC_VEX_W_OPSIZE, /* 1659 */ >+ IC_VEX_W_OPSIZE, /* 1660 */ >+ IC_VEX_W_OPSIZE, /* 1661 */ >+ IC_VEX_W_OPSIZE, /* 1662 */ >+ IC_VEX_W_OPSIZE, /* 1663 */ >+ IC_VEX_L, /* 1664 */ >+ IC_VEX_L, /* 1665 */ >+ IC_VEX_L_XS, /* 1666 */ >+ IC_VEX_L_XS, /* 1667 */ >+ IC_VEX_L_XD, /* 1668 */ >+ IC_VEX_L_XD, /* 1669 */ >+ IC_VEX_L_XD, /* 1670 */ >+ IC_VEX_L_XD, /* 1671 */ >+ IC_VEX_L_W, /* 1672 */ >+ IC_VEX_L_W, /* 1673 */ >+ IC_VEX_L_W_XS, /* 1674 */ >+ IC_VEX_L_W_XS, /* 1675 */ >+ IC_VEX_L_W_XD, /* 1676 */ >+ IC_VEX_L_W_XD, /* 1677 */ >+ IC_VEX_L_W_XD, /* 1678 */ >+ IC_VEX_L_W_XD, /* 1679 */ >+ IC_VEX_L_OPSIZE, /* 1680 */ >+ IC_VEX_L_OPSIZE, /* 1681 */ >+ IC_VEX_L_OPSIZE, /* 1682 */ >+ IC_VEX_L_OPSIZE, /* 1683 */ >+ IC_VEX_L_OPSIZE, /* 1684 */ >+ IC_VEX_L_OPSIZE, /* 1685 */ >+ IC_VEX_L_OPSIZE, /* 1686 */ >+ IC_VEX_L_OPSIZE, /* 1687 */ >+ IC_VEX_L_W_OPSIZE, /* 1688 */ >+ IC_VEX_L_W_OPSIZE, /* 1689 */ >+ IC_VEX_L_W_OPSIZE, /* 1690 */ >+ IC_VEX_L_W_OPSIZE, /* 1691 */ >+ IC_VEX_L_W_OPSIZE, /* 1692 */ >+ IC_VEX_L_W_OPSIZE, /* 1693 */ >+ IC_VEX_L_W_OPSIZE, /* 1694 */ >+ IC_VEX_L_W_OPSIZE, /* 1695 */ >+ IC_VEX_L, /* 1696 */ >+ IC_VEX_L, /* 1697 */ >+ IC_VEX_L_XS, /* 1698 */ >+ IC_VEX_L_XS, /* 1699 */ >+ IC_VEX_L_XD, /* 1700 */ >+ IC_VEX_L_XD, /* 1701 */ >+ IC_VEX_L_XD, /* 1702 */ >+ IC_VEX_L_XD, /* 1703 */ >+ IC_VEX_L_W, /* 1704 */ >+ IC_VEX_L_W, /* 1705 */ >+ IC_VEX_L_W_XS, /* 1706 */ >+ IC_VEX_L_W_XS, /* 1707 */ >+ IC_VEX_L_W_XD, /* 1708 */ >+ IC_VEX_L_W_XD, /* 1709 */ >+ IC_VEX_L_W_XD, /* 1710 */ >+ IC_VEX_L_W_XD, /* 1711 */ >+ IC_VEX_L_OPSIZE, /* 1712 */ >+ IC_VEX_L_OPSIZE, /* 1713 */ >+ IC_VEX_L_OPSIZE, /* 1714 */ >+ IC_VEX_L_OPSIZE, /* 1715 */ >+ IC_VEX_L_OPSIZE, /* 1716 */ >+ IC_VEX_L_OPSIZE, /* 1717 */ >+ IC_VEX_L_OPSIZE, /* 1718 */ >+ IC_VEX_L_OPSIZE, /* 1719 */ >+ IC_VEX_L_W_OPSIZE, /* 1720 */ >+ IC_VEX_L_W_OPSIZE, /* 1721 */ >+ IC_VEX_L_W_OPSIZE, /* 1722 */ >+ IC_VEX_L_W_OPSIZE, /* 1723 */ >+ IC_VEX_L_W_OPSIZE, /* 1724 */ >+ IC_VEX_L_W_OPSIZE, /* 1725 */ >+ IC_VEX_L_W_OPSIZE, /* 1726 */ >+ IC_VEX_L_W_OPSIZE, /* 1727 */ >+ IC_VEX_L, /* 1728 */ >+ IC_VEX_L, /* 1729 */ >+ IC_VEX_L_XS, /* 1730 */ >+ IC_VEX_L_XS, /* 1731 */ >+ IC_VEX_L_XD, /* 1732 */ >+ IC_VEX_L_XD, /* 1733 */ >+ IC_VEX_L_XD, /* 1734 */ >+ IC_VEX_L_XD, /* 1735 */ >+ IC_VEX_L_W, /* 1736 */ >+ IC_VEX_L_W, /* 1737 */ >+ IC_VEX_L_W_XS, /* 1738 */ >+ IC_VEX_L_W_XS, /* 1739 */ >+ IC_VEX_L_W_XD, /* 1740 */ >+ IC_VEX_L_W_XD, /* 1741 */ >+ IC_VEX_L_W_XD, /* 1742 */ >+ IC_VEX_L_W_XD, /* 1743 */ >+ IC_VEX_L_OPSIZE, /* 1744 */ >+ IC_VEX_L_OPSIZE, /* 1745 */ >+ IC_VEX_L_OPSIZE, /* 1746 */ >+ IC_VEX_L_OPSIZE, /* 1747 */ >+ IC_VEX_L_OPSIZE, /* 1748 */ >+ IC_VEX_L_OPSIZE, /* 1749 */ >+ IC_VEX_L_OPSIZE, /* 1750 */ >+ IC_VEX_L_OPSIZE, /* 1751 */ >+ IC_VEX_L_W_OPSIZE, /* 1752 */ >+ IC_VEX_L_W_OPSIZE, /* 1753 */ >+ IC_VEX_L_W_OPSIZE, /* 1754 */ >+ IC_VEX_L_W_OPSIZE, /* 1755 */ >+ IC_VEX_L_W_OPSIZE, /* 1756 */ >+ IC_VEX_L_W_OPSIZE, /* 1757 */ >+ IC_VEX_L_W_OPSIZE, /* 1758 */ >+ IC_VEX_L_W_OPSIZE, /* 1759 */ >+ IC_VEX_L, /* 1760 */ >+ IC_VEX_L, /* 1761 */ >+ IC_VEX_L_XS, /* 1762 */ >+ IC_VEX_L_XS, /* 1763 */ >+ IC_VEX_L_XD, /* 1764 */ >+ IC_VEX_L_XD, /* 1765 */ >+ IC_VEX_L_XD, /* 1766 */ >+ IC_VEX_L_XD, /* 1767 */ >+ IC_VEX_L_W, /* 1768 */ >+ IC_VEX_L_W, /* 1769 */ >+ IC_VEX_L_W_XS, /* 1770 */ >+ IC_VEX_L_W_XS, /* 1771 */ >+ IC_VEX_L_W_XD, /* 1772 */ >+ IC_VEX_L_W_XD, /* 1773 */ >+ IC_VEX_L_W_XD, /* 1774 */ >+ IC_VEX_L_W_XD, /* 1775 */ >+ IC_VEX_L_OPSIZE, /* 1776 */ >+ IC_VEX_L_OPSIZE, /* 1777 */ >+ IC_VEX_L_OPSIZE, /* 1778 */ >+ IC_VEX_L_OPSIZE, /* 1779 */ >+ IC_VEX_L_OPSIZE, /* 1780 */ >+ IC_VEX_L_OPSIZE, /* 1781 */ >+ IC_VEX_L_OPSIZE, /* 1782 */ >+ IC_VEX_L_OPSIZE, /* 1783 */ >+ IC_VEX_L_W_OPSIZE, /* 1784 */ >+ IC_VEX_L_W_OPSIZE, /* 1785 */ >+ IC_VEX_L_W_OPSIZE, /* 1786 */ >+ IC_VEX_L_W_OPSIZE, /* 1787 */ >+ IC_VEX_L_W_OPSIZE, /* 1788 */ >+ IC_VEX_L_W_OPSIZE, /* 1789 */ >+ IC_VEX_L_W_OPSIZE, /* 1790 */ >+ IC_VEX_L_W_OPSIZE, /* 1791 */ >+ IC_EVEX_L2, /* 1792 */ >+ IC_EVEX_L2, /* 1793 */ >+ IC_EVEX_L2_XS, /* 1794 */ >+ IC_EVEX_L2_XS, /* 1795 */ >+ IC_EVEX_L2_XD, /* 1796 */ >+ IC_EVEX_L2_XD, /* 1797 */ >+ IC_EVEX_L2_XD, /* 1798 */ >+ IC_EVEX_L2_XD, /* 1799 */ >+ IC_EVEX_L2_W, /* 1800 */ >+ IC_EVEX_L2_W, /* 1801 */ >+ IC_EVEX_L2_W_XS, /* 1802 */ >+ IC_EVEX_L2_W_XS, /* 1803 */ >+ IC_EVEX_L2_W_XD, /* 1804 */ >+ IC_EVEX_L2_W_XD, /* 1805 */ >+ IC_EVEX_L2_W_XD, /* 1806 */ >+ IC_EVEX_L2_W_XD, /* 1807 */ >+ IC_EVEX_L2_OPSIZE, /* 1808 */ >+ IC_EVEX_L2_OPSIZE, /* 1809 */ >+ IC_EVEX_L2_OPSIZE, /* 1810 */ >+ IC_EVEX_L2_OPSIZE, /* 1811 */ >+ IC_EVEX_L2_OPSIZE, /* 1812 */ >+ IC_EVEX_L2_OPSIZE, /* 1813 */ >+ IC_EVEX_L2_OPSIZE, /* 1814 */ >+ IC_EVEX_L2_OPSIZE, /* 1815 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1816 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1817 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1818 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1819 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1820 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1821 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1822 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1823 */ >+ IC_EVEX_L2, /* 1824 */ >+ IC_EVEX_L2, /* 1825 */ >+ IC_EVEX_L2_XS, /* 1826 */ >+ IC_EVEX_L2_XS, /* 1827 */ >+ IC_EVEX_L2_XD, /* 1828 */ >+ IC_EVEX_L2_XD, /* 1829 */ >+ IC_EVEX_L2_XD, /* 1830 */ >+ IC_EVEX_L2_XD, /* 1831 */ >+ IC_EVEX_L2_W, /* 1832 */ >+ IC_EVEX_L2_W, /* 1833 */ >+ IC_EVEX_L2_W_XS, /* 1834 */ >+ IC_EVEX_L2_W_XS, /* 1835 */ >+ IC_EVEX_L2_W_XD, /* 1836 */ >+ IC_EVEX_L2_W_XD, /* 1837 */ >+ IC_EVEX_L2_W_XD, /* 1838 */ >+ IC_EVEX_L2_W_XD, /* 1839 */ >+ IC_EVEX_L2_OPSIZE, /* 1840 */ >+ IC_EVEX_L2_OPSIZE, /* 1841 */ >+ IC_EVEX_L2_OPSIZE, /* 1842 */ >+ IC_EVEX_L2_OPSIZE, /* 1843 */ >+ IC_EVEX_L2_OPSIZE, /* 1844 */ >+ IC_EVEX_L2_OPSIZE, /* 1845 */ >+ IC_EVEX_L2_OPSIZE, /* 1846 */ >+ IC_EVEX_L2_OPSIZE, /* 1847 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1848 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1849 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1850 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1851 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1852 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1853 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1854 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1855 */ >+ IC_EVEX_L2, /* 1856 */ >+ IC_EVEX_L2, /* 1857 */ >+ IC_EVEX_L2_XS, /* 1858 */ >+ IC_EVEX_L2_XS, /* 1859 */ >+ IC_EVEX_L2_XD, /* 1860 */ >+ IC_EVEX_L2_XD, /* 1861 */ >+ IC_EVEX_L2_XD, /* 1862 */ >+ IC_EVEX_L2_XD, /* 1863 */ >+ IC_EVEX_L2_W, /* 1864 */ >+ IC_EVEX_L2_W, /* 1865 */ >+ IC_EVEX_L2_W_XS, /* 1866 */ >+ IC_EVEX_L2_W_XS, /* 1867 */ >+ IC_EVEX_L2_W_XD, /* 1868 */ >+ IC_EVEX_L2_W_XD, /* 1869 */ >+ IC_EVEX_L2_W_XD, /* 1870 */ >+ IC_EVEX_L2_W_XD, /* 1871 */ >+ IC_EVEX_L2_OPSIZE, /* 1872 */ >+ IC_EVEX_L2_OPSIZE, /* 1873 */ >+ IC_EVEX_L2_OPSIZE, /* 1874 */ >+ IC_EVEX_L2_OPSIZE, /* 1875 */ >+ IC_EVEX_L2_OPSIZE, /* 1876 */ >+ IC_EVEX_L2_OPSIZE, /* 1877 */ >+ IC_EVEX_L2_OPSIZE, /* 1878 */ >+ IC_EVEX_L2_OPSIZE, /* 1879 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1880 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1881 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1882 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1883 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1884 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1885 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1886 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1887 */ >+ IC_EVEX_L2, /* 1888 */ >+ IC_EVEX_L2, /* 1889 */ >+ IC_EVEX_L2_XS, /* 1890 */ >+ IC_EVEX_L2_XS, /* 1891 */ >+ IC_EVEX_L2_XD, /* 1892 */ >+ IC_EVEX_L2_XD, /* 1893 */ >+ IC_EVEX_L2_XD, /* 1894 */ >+ IC_EVEX_L2_XD, /* 1895 */ >+ IC_EVEX_L2_W, /* 1896 */ >+ IC_EVEX_L2_W, /* 1897 */ >+ IC_EVEX_L2_W_XS, /* 1898 */ >+ IC_EVEX_L2_W_XS, /* 1899 */ >+ IC_EVEX_L2_W_XD, /* 1900 */ >+ IC_EVEX_L2_W_XD, /* 1901 */ >+ IC_EVEX_L2_W_XD, /* 1902 */ >+ IC_EVEX_L2_W_XD, /* 1903 */ >+ IC_EVEX_L2_OPSIZE, /* 1904 */ >+ IC_EVEX_L2_OPSIZE, /* 1905 */ >+ IC_EVEX_L2_OPSIZE, /* 1906 */ >+ IC_EVEX_L2_OPSIZE, /* 1907 */ >+ IC_EVEX_L2_OPSIZE, /* 1908 */ >+ IC_EVEX_L2_OPSIZE, /* 1909 */ >+ IC_EVEX_L2_OPSIZE, /* 1910 */ >+ IC_EVEX_L2_OPSIZE, /* 1911 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1912 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1913 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1914 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1915 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1916 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1917 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1918 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1919 */ >+ IC_EVEX_L2, /* 1920 */ >+ IC_EVEX_L2, /* 1921 */ >+ IC_EVEX_L2_XS, /* 1922 */ >+ IC_EVEX_L2_XS, /* 1923 */ >+ IC_EVEX_L2_XD, /* 1924 */ >+ IC_EVEX_L2_XD, /* 1925 */ >+ IC_EVEX_L2_XD, /* 1926 */ >+ IC_EVEX_L2_XD, /* 1927 */ >+ IC_EVEX_L2_W, /* 1928 */ >+ IC_EVEX_L2_W, /* 1929 */ >+ IC_EVEX_L2_W_XS, /* 1930 */ >+ IC_EVEX_L2_W_XS, /* 1931 */ >+ IC_EVEX_L2_W_XD, /* 1932 */ >+ IC_EVEX_L2_W_XD, /* 1933 */ >+ IC_EVEX_L2_W_XD, /* 1934 */ >+ IC_EVEX_L2_W_XD, /* 1935 */ >+ IC_EVEX_L2_OPSIZE, /* 1936 */ >+ IC_EVEX_L2_OPSIZE, /* 1937 */ >+ IC_EVEX_L2_OPSIZE, /* 1938 */ >+ IC_EVEX_L2_OPSIZE, /* 1939 */ >+ IC_EVEX_L2_OPSIZE, /* 1940 */ >+ IC_EVEX_L2_OPSIZE, /* 1941 */ >+ IC_EVEX_L2_OPSIZE, /* 1942 */ >+ IC_EVEX_L2_OPSIZE, /* 1943 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1944 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1945 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1946 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1947 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1948 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1949 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1950 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1951 */ >+ IC_EVEX_L2, /* 1952 */ >+ IC_EVEX_L2, /* 1953 */ >+ IC_EVEX_L2_XS, /* 1954 */ >+ IC_EVEX_L2_XS, /* 1955 */ >+ IC_EVEX_L2_XD, /* 1956 */ >+ IC_EVEX_L2_XD, /* 1957 */ >+ IC_EVEX_L2_XD, /* 1958 */ >+ IC_EVEX_L2_XD, /* 1959 */ >+ IC_EVEX_L2_W, /* 1960 */ >+ IC_EVEX_L2_W, /* 1961 */ >+ IC_EVEX_L2_W_XS, /* 1962 */ >+ IC_EVEX_L2_W_XS, /* 1963 */ >+ IC_EVEX_L2_W_XD, /* 1964 */ >+ IC_EVEX_L2_W_XD, /* 1965 */ >+ IC_EVEX_L2_W_XD, /* 1966 */ >+ IC_EVEX_L2_W_XD, /* 1967 */ >+ IC_EVEX_L2_OPSIZE, /* 1968 */ >+ IC_EVEX_L2_OPSIZE, /* 1969 */ >+ IC_EVEX_L2_OPSIZE, /* 1970 */ >+ IC_EVEX_L2_OPSIZE, /* 1971 */ >+ IC_EVEX_L2_OPSIZE, /* 1972 */ >+ IC_EVEX_L2_OPSIZE, /* 1973 */ >+ IC_EVEX_L2_OPSIZE, /* 1974 */ >+ IC_EVEX_L2_OPSIZE, /* 1975 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1976 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1977 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1978 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1979 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1980 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1981 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1982 */ >+ IC_EVEX_L2_W_OPSIZE, /* 1983 */ >+ IC_EVEX_L2, /* 1984 */ >+ IC_EVEX_L2, /* 1985 */ >+ IC_EVEX_L2_XS, /* 1986 */ >+ IC_EVEX_L2_XS, /* 1987 */ >+ IC_EVEX_L2_XD, /* 1988 */ >+ IC_EVEX_L2_XD, /* 1989 */ >+ IC_EVEX_L2_XD, /* 1990 */ >+ IC_EVEX_L2_XD, /* 1991 */ >+ IC_EVEX_L2_W, /* 1992 */ >+ IC_EVEX_L2_W, /* 1993 */ >+ IC_EVEX_L2_W_XS, /* 1994 */ >+ IC_EVEX_L2_W_XS, /* 1995 */ >+ IC_EVEX_L2_W_XD, /* 1996 */ >+ IC_EVEX_L2_W_XD, /* 1997 */ >+ IC_EVEX_L2_W_XD, /* 1998 */ >+ IC_EVEX_L2_W_XD, /* 1999 */ >+ IC_EVEX_L2_OPSIZE, /* 2000 */ >+ IC_EVEX_L2_OPSIZE, /* 2001 */ >+ IC_EVEX_L2_OPSIZE, /* 2002 */ >+ IC_EVEX_L2_OPSIZE, /* 2003 */ >+ IC_EVEX_L2_OPSIZE, /* 2004 */ >+ IC_EVEX_L2_OPSIZE, /* 2005 */ >+ IC_EVEX_L2_OPSIZE, /* 2006 */ >+ IC_EVEX_L2_OPSIZE, /* 2007 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2008 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2009 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2010 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2011 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2012 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2013 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2014 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2015 */ >+ IC_EVEX_L2, /* 2016 */ >+ IC_EVEX_L2, /* 2017 */ >+ IC_EVEX_L2_XS, /* 2018 */ >+ IC_EVEX_L2_XS, /* 2019 */ >+ IC_EVEX_L2_XD, /* 2020 */ >+ IC_EVEX_L2_XD, /* 2021 */ >+ IC_EVEX_L2_XD, /* 2022 */ >+ IC_EVEX_L2_XD, /* 2023 */ >+ IC_EVEX_L2_W, /* 2024 */ >+ IC_EVEX_L2_W, /* 2025 */ >+ IC_EVEX_L2_W_XS, /* 2026 */ >+ IC_EVEX_L2_W_XS, /* 2027 */ >+ IC_EVEX_L2_W_XD, /* 2028 */ >+ IC_EVEX_L2_W_XD, /* 2029 */ >+ IC_EVEX_L2_W_XD, /* 2030 */ >+ IC_EVEX_L2_W_XD, /* 2031 */ >+ IC_EVEX_L2_OPSIZE, /* 2032 */ >+ IC_EVEX_L2_OPSIZE, /* 2033 */ >+ IC_EVEX_L2_OPSIZE, /* 2034 */ >+ IC_EVEX_L2_OPSIZE, /* 2035 */ >+ IC_EVEX_L2_OPSIZE, /* 2036 */ >+ IC_EVEX_L2_OPSIZE, /* 2037 */ >+ IC_EVEX_L2_OPSIZE, /* 2038 */ >+ IC_EVEX_L2_OPSIZE, /* 2039 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2040 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2041 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2042 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2043 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2044 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2045 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2046 */ >+ IC_EVEX_L2_W_OPSIZE, /* 2047 */ >+ IC, /* 2048 */ >+ IC_64BIT, /* 2049 */ >+ IC_XS, /* 2050 */ >+ IC_64BIT_XS, /* 2051 */ >+ IC_XD, /* 2052 */ >+ IC_64BIT_XD, /* 2053 */ >+ IC_XS, /* 2054 */ >+ IC_64BIT_XS, /* 2055 */ >+ IC, /* 2056 */ >+ IC_64BIT_REXW, /* 2057 */ >+ IC_XS, /* 2058 */ >+ IC_64BIT_REXW_XS, /* 2059 */ >+ IC_XD, /* 2060 */ >+ IC_64BIT_REXW_XD, /* 2061 */ >+ IC_XS, /* 2062 */ >+ IC_64BIT_REXW_XS, /* 2063 */ >+ IC_OPSIZE, /* 2064 */ >+ IC_64BIT_OPSIZE, /* 2065 */ >+ IC_XS_OPSIZE, /* 2066 */ >+ IC_64BIT_XS_OPSIZE, /* 2067 */ >+ IC_XD_OPSIZE, /* 2068 */ >+ IC_64BIT_XD_OPSIZE, /* 2069 */ >+ IC_XS_OPSIZE, /* 2070 */ >+ IC_64BIT_XD_OPSIZE, /* 2071 */ >+ IC_OPSIZE, /* 2072 */ >+ IC_64BIT_REXW_OPSIZE, /* 2073 */ >+ IC_XS_OPSIZE, /* 2074 */ >+ IC_64BIT_REXW_XS, /* 2075 */ >+ IC_XD_OPSIZE, /* 2076 */ >+ IC_64BIT_REXW_XD, /* 2077 */ >+ IC_XS_OPSIZE, /* 2078 */ >+ IC_64BIT_REXW_XS, /* 2079 */ >+ IC_ADSIZE, /* 2080 */ >+ IC_64BIT_ADSIZE, /* 2081 */ >+ IC_XS, /* 2082 */ >+ IC_64BIT_XS, /* 2083 */ >+ IC_XD, /* 2084 */ >+ IC_64BIT_XD, /* 2085 */ >+ IC_XS, /* 2086 */ >+ IC_64BIT_XS, /* 2087 */ >+ IC_ADSIZE, /* 2088 */ >+ IC_64BIT_ADSIZE, /* 2089 */ >+ IC_XS, /* 2090 */ >+ IC_64BIT_REXW_XS, /* 2091 */ >+ IC_XD, /* 2092 */ >+ IC_64BIT_REXW_XD, /* 2093 */ >+ IC_XS, /* 2094 */ >+ IC_64BIT_REXW_XS, /* 2095 */ >+ IC_OPSIZE, /* 2096 */ >+ IC_64BIT_OPSIZE, /* 2097 */ >+ IC_XS_OPSIZE, /* 2098 */ >+ IC_64BIT_XS_OPSIZE, /* 2099 */ >+ IC_XD_OPSIZE, /* 2100 */ >+ IC_64BIT_XD_OPSIZE, /* 2101 */ >+ IC_XS_OPSIZE, /* 2102 */ >+ IC_64BIT_XD_OPSIZE, /* 2103 */ >+ IC_OPSIZE, /* 2104 */ >+ IC_64BIT_REXW_OPSIZE, /* 2105 */ >+ IC_XS_OPSIZE, /* 2106 */ >+ IC_64BIT_REXW_XS, /* 2107 */ >+ IC_XD_OPSIZE, /* 2108 */ >+ IC_64BIT_REXW_XD, /* 2109 */ >+ IC_XS_OPSIZE, /* 2110 */ >+ IC_64BIT_REXW_XS, /* 2111 */ >+ IC_VEX, /* 2112 */ >+ IC_VEX, /* 2113 */ >+ IC_VEX_XS, /* 2114 */ >+ IC_VEX_XS, /* 2115 */ >+ IC_VEX_XD, /* 2116 */ >+ IC_VEX_XD, /* 2117 */ >+ IC_VEX_XD, /* 2118 */ >+ IC_VEX_XD, /* 2119 */ >+ IC_VEX_W, /* 2120 */ >+ IC_VEX_W, /* 2121 */ >+ IC_VEX_W_XS, /* 2122 */ >+ IC_VEX_W_XS, /* 2123 */ >+ IC_VEX_W_XD, /* 2124 */ >+ IC_VEX_W_XD, /* 2125 */ >+ IC_VEX_W_XD, /* 2126 */ >+ IC_VEX_W_XD, /* 2127 */ >+ IC_VEX_OPSIZE, /* 2128 */ >+ IC_VEX_OPSIZE, /* 2129 */ >+ IC_VEX_OPSIZE, /* 2130 */ >+ IC_VEX_OPSIZE, /* 2131 */ >+ IC_VEX_OPSIZE, /* 2132 */ >+ IC_VEX_OPSIZE, /* 2133 */ >+ IC_VEX_OPSIZE, /* 2134 */ >+ IC_VEX_OPSIZE, /* 2135 */ >+ IC_VEX_W_OPSIZE, /* 2136 */ >+ IC_VEX_W_OPSIZE, /* 2137 */ >+ IC_VEX_W_OPSIZE, /* 2138 */ >+ IC_VEX_W_OPSIZE, /* 2139 */ >+ IC_VEX_W_OPSIZE, /* 2140 */ >+ IC_VEX_W_OPSIZE, /* 2141 */ >+ IC_VEX_W_OPSIZE, /* 2142 */ >+ IC_VEX_W_OPSIZE, /* 2143 */ >+ IC_VEX, /* 2144 */ >+ IC_VEX, /* 2145 */ >+ IC_VEX_XS, /* 2146 */ >+ IC_VEX_XS, /* 2147 */ >+ IC_VEX_XD, /* 2148 */ >+ IC_VEX_XD, /* 2149 */ >+ IC_VEX_XD, /* 2150 */ >+ IC_VEX_XD, /* 2151 */ >+ IC_VEX_W, /* 2152 */ >+ IC_VEX_W, /* 2153 */ >+ IC_VEX_W_XS, /* 2154 */ >+ IC_VEX_W_XS, /* 2155 */ >+ IC_VEX_W_XD, /* 2156 */ >+ IC_VEX_W_XD, /* 2157 */ >+ IC_VEX_W_XD, /* 2158 */ >+ IC_VEX_W_XD, /* 2159 */ >+ IC_VEX_OPSIZE, /* 2160 */ >+ IC_VEX_OPSIZE, /* 2161 */ >+ IC_VEX_OPSIZE, /* 2162 */ >+ IC_VEX_OPSIZE, /* 2163 */ >+ IC_VEX_OPSIZE, /* 2164 */ >+ IC_VEX_OPSIZE, /* 2165 */ >+ IC_VEX_OPSIZE, /* 2166 */ >+ IC_VEX_OPSIZE, /* 2167 */ >+ IC_VEX_W_OPSIZE, /* 2168 */ >+ IC_VEX_W_OPSIZE, /* 2169 */ >+ IC_VEX_W_OPSIZE, /* 2170 */ >+ IC_VEX_W_OPSIZE, /* 2171 */ >+ IC_VEX_W_OPSIZE, /* 2172 */ >+ IC_VEX_W_OPSIZE, /* 2173 */ >+ IC_VEX_W_OPSIZE, /* 2174 */ >+ IC_VEX_W_OPSIZE, /* 2175 */ >+ IC_VEX_L, /* 2176 */ >+ IC_VEX_L, /* 2177 */ >+ IC_VEX_L_XS, /* 2178 */ >+ IC_VEX_L_XS, /* 2179 */ >+ IC_VEX_L_XD, /* 2180 */ >+ IC_VEX_L_XD, /* 2181 */ >+ IC_VEX_L_XD, /* 2182 */ >+ IC_VEX_L_XD, /* 2183 */ >+ IC_VEX_L_W, /* 2184 */ >+ IC_VEX_L_W, /* 2185 */ >+ IC_VEX_L_W_XS, /* 2186 */ >+ IC_VEX_L_W_XS, /* 2187 */ >+ IC_VEX_L_W_XD, /* 2188 */ >+ IC_VEX_L_W_XD, /* 2189 */ >+ IC_VEX_L_W_XD, /* 2190 */ >+ IC_VEX_L_W_XD, /* 2191 */ >+ IC_VEX_L_OPSIZE, /* 2192 */ >+ IC_VEX_L_OPSIZE, /* 2193 */ >+ IC_VEX_L_OPSIZE, /* 2194 */ >+ IC_VEX_L_OPSIZE, /* 2195 */ >+ IC_VEX_L_OPSIZE, /* 2196 */ >+ IC_VEX_L_OPSIZE, /* 2197 */ >+ IC_VEX_L_OPSIZE, /* 2198 */ >+ IC_VEX_L_OPSIZE, /* 2199 */ >+ IC_VEX_L_W_OPSIZE, /* 2200 */ >+ IC_VEX_L_W_OPSIZE, /* 2201 */ >+ IC_VEX_L_W_OPSIZE, /* 2202 */ >+ IC_VEX_L_W_OPSIZE, /* 2203 */ >+ IC_VEX_L_W_OPSIZE, /* 2204 */ >+ IC_VEX_L_W_OPSIZE, /* 2205 */ >+ IC_VEX_L_W_OPSIZE, /* 2206 */ >+ IC_VEX_L_W_OPSIZE, /* 2207 */ >+ IC_VEX_L, /* 2208 */ >+ IC_VEX_L, /* 2209 */ >+ IC_VEX_L_XS, /* 2210 */ >+ IC_VEX_L_XS, /* 2211 */ >+ IC_VEX_L_XD, /* 2212 */ >+ IC_VEX_L_XD, /* 2213 */ >+ IC_VEX_L_XD, /* 2214 */ >+ IC_VEX_L_XD, /* 2215 */ >+ IC_VEX_L_W, /* 2216 */ >+ IC_VEX_L_W, /* 2217 */ >+ IC_VEX_L_W_XS, /* 2218 */ >+ IC_VEX_L_W_XS, /* 2219 */ >+ IC_VEX_L_W_XD, /* 2220 */ >+ IC_VEX_L_W_XD, /* 2221 */ >+ IC_VEX_L_W_XD, /* 2222 */ >+ IC_VEX_L_W_XD, /* 2223 */ >+ IC_VEX_L_OPSIZE, /* 2224 */ >+ IC_VEX_L_OPSIZE, /* 2225 */ >+ IC_VEX_L_OPSIZE, /* 2226 */ >+ IC_VEX_L_OPSIZE, /* 2227 */ >+ IC_VEX_L_OPSIZE, /* 2228 */ >+ IC_VEX_L_OPSIZE, /* 2229 */ >+ IC_VEX_L_OPSIZE, /* 2230 */ >+ IC_VEX_L_OPSIZE, /* 2231 */ >+ IC_VEX_L_W_OPSIZE, /* 2232 */ >+ IC_VEX_L_W_OPSIZE, /* 2233 */ >+ IC_VEX_L_W_OPSIZE, /* 2234 */ >+ IC_VEX_L_W_OPSIZE, /* 2235 */ >+ IC_VEX_L_W_OPSIZE, /* 2236 */ >+ IC_VEX_L_W_OPSIZE, /* 2237 */ >+ IC_VEX_L_W_OPSIZE, /* 2238 */ >+ IC_VEX_L_W_OPSIZE, /* 2239 */ >+ IC_VEX_L, /* 2240 */ >+ IC_VEX_L, /* 2241 */ >+ IC_VEX_L_XS, /* 2242 */ >+ IC_VEX_L_XS, /* 2243 */ >+ IC_VEX_L_XD, /* 2244 */ >+ IC_VEX_L_XD, /* 2245 */ >+ IC_VEX_L_XD, /* 2246 */ >+ IC_VEX_L_XD, /* 2247 */ >+ IC_VEX_L_W, /* 2248 */ >+ IC_VEX_L_W, /* 2249 */ >+ IC_VEX_L_W_XS, /* 2250 */ >+ IC_VEX_L_W_XS, /* 2251 */ >+ IC_VEX_L_W_XD, /* 2252 */ >+ IC_VEX_L_W_XD, /* 2253 */ >+ IC_VEX_L_W_XD, /* 2254 */ >+ IC_VEX_L_W_XD, /* 2255 */ >+ IC_VEX_L_OPSIZE, /* 2256 */ >+ IC_VEX_L_OPSIZE, /* 2257 */ >+ IC_VEX_L_OPSIZE, /* 2258 */ >+ IC_VEX_L_OPSIZE, /* 2259 */ >+ IC_VEX_L_OPSIZE, /* 2260 */ >+ IC_VEX_L_OPSIZE, /* 2261 */ >+ IC_VEX_L_OPSIZE, /* 2262 */ >+ IC_VEX_L_OPSIZE, /* 2263 */ >+ IC_VEX_L_W_OPSIZE, /* 2264 */ >+ IC_VEX_L_W_OPSIZE, /* 2265 */ >+ IC_VEX_L_W_OPSIZE, /* 2266 */ >+ IC_VEX_L_W_OPSIZE, /* 2267 */ >+ IC_VEX_L_W_OPSIZE, /* 2268 */ >+ IC_VEX_L_W_OPSIZE, /* 2269 */ >+ IC_VEX_L_W_OPSIZE, /* 2270 */ >+ IC_VEX_L_W_OPSIZE, /* 2271 */ >+ IC_VEX_L, /* 2272 */ >+ IC_VEX_L, /* 2273 */ >+ IC_VEX_L_XS, /* 2274 */ >+ IC_VEX_L_XS, /* 2275 */ >+ IC_VEX_L_XD, /* 2276 */ >+ IC_VEX_L_XD, /* 2277 */ >+ IC_VEX_L_XD, /* 2278 */ >+ IC_VEX_L_XD, /* 2279 */ >+ IC_VEX_L_W, /* 2280 */ >+ IC_VEX_L_W, /* 2281 */ >+ IC_VEX_L_W_XS, /* 2282 */ >+ IC_VEX_L_W_XS, /* 2283 */ >+ IC_VEX_L_W_XD, /* 2284 */ >+ IC_VEX_L_W_XD, /* 2285 */ >+ IC_VEX_L_W_XD, /* 2286 */ >+ IC_VEX_L_W_XD, /* 2287 */ >+ IC_VEX_L_OPSIZE, /* 2288 */ >+ IC_VEX_L_OPSIZE, /* 2289 */ >+ IC_VEX_L_OPSIZE, /* 2290 */ >+ IC_VEX_L_OPSIZE, /* 2291 */ >+ IC_VEX_L_OPSIZE, /* 2292 */ >+ IC_VEX_L_OPSIZE, /* 2293 */ >+ IC_VEX_L_OPSIZE, /* 2294 */ >+ IC_VEX_L_OPSIZE, /* 2295 */ >+ IC_VEX_L_W_OPSIZE, /* 2296 */ >+ IC_VEX_L_W_OPSIZE, /* 2297 */ >+ IC_VEX_L_W_OPSIZE, /* 2298 */ >+ IC_VEX_L_W_OPSIZE, /* 2299 */ >+ IC_VEX_L_W_OPSIZE, /* 2300 */ >+ IC_VEX_L_W_OPSIZE, /* 2301 */ >+ IC_VEX_L_W_OPSIZE, /* 2302 */ >+ IC_VEX_L_W_OPSIZE, /* 2303 */ >+ IC_EVEX_K, /* 2304 */ >+ IC_EVEX_K, /* 2305 */ >+ IC_EVEX_XS_K, /* 2306 */ >+ IC_EVEX_XS_K, /* 2307 */ >+ IC_EVEX_XD_K, /* 2308 */ >+ IC_EVEX_XD_K, /* 2309 */ >+ IC_EVEX_XD_K, /* 2310 */ >+ IC_EVEX_XD_K, /* 2311 */ >+ IC_EVEX_W_K, /* 2312 */ >+ IC_EVEX_W_K, /* 2313 */ >+ IC_EVEX_W_XS_K, /* 2314 */ >+ IC_EVEX_W_XS_K, /* 2315 */ >+ IC_EVEX_W_XD_K, /* 2316 */ >+ IC_EVEX_W_XD_K, /* 2317 */ >+ IC_EVEX_W_XD_K, /* 2318 */ >+ IC_EVEX_W_XD_K, /* 2319 */ >+ IC_EVEX_OPSIZE_K, /* 2320 */ >+ IC_EVEX_OPSIZE_K, /* 2321 */ >+ IC_EVEX_OPSIZE_K, /* 2322 */ >+ IC_EVEX_OPSIZE_K, /* 2323 */ >+ IC_EVEX_OPSIZE_K, /* 2324 */ >+ IC_EVEX_OPSIZE_K, /* 2325 */ >+ IC_EVEX_OPSIZE_K, /* 2326 */ >+ IC_EVEX_OPSIZE_K, /* 2327 */ >+ IC_EVEX_W_OPSIZE_K, /* 2328 */ >+ IC_EVEX_W_OPSIZE_K, /* 2329 */ >+ IC_EVEX_W_OPSIZE_K, /* 2330 */ >+ IC_EVEX_W_OPSIZE_K, /* 2331 */ >+ IC_EVEX_W_OPSIZE_K, /* 2332 */ >+ IC_EVEX_W_OPSIZE_K, /* 2333 */ >+ IC_EVEX_W_OPSIZE_K, /* 2334 */ >+ IC_EVEX_W_OPSIZE_K, /* 2335 */ >+ IC_EVEX_K, /* 2336 */ >+ IC_EVEX_K, /* 2337 */ >+ IC_EVEX_XS_K, /* 2338 */ >+ IC_EVEX_XS_K, /* 2339 */ >+ IC_EVEX_XD_K, /* 2340 */ >+ IC_EVEX_XD_K, /* 2341 */ >+ IC_EVEX_XD_K, /* 2342 */ >+ IC_EVEX_XD_K, /* 2343 */ >+ IC_EVEX_W_K, /* 2344 */ >+ IC_EVEX_W_K, /* 2345 */ >+ IC_EVEX_W_XS_K, /* 2346 */ >+ IC_EVEX_W_XS_K, /* 2347 */ >+ IC_EVEX_W_XD_K, /* 2348 */ >+ IC_EVEX_W_XD_K, /* 2349 */ >+ IC_EVEX_W_XD_K, /* 2350 */ >+ IC_EVEX_W_XD_K, /* 2351 */ >+ IC_EVEX_OPSIZE_K, /* 2352 */ >+ IC_EVEX_OPSIZE_K, /* 2353 */ >+ IC_EVEX_OPSIZE_K, /* 2354 */ >+ IC_EVEX_OPSIZE_K, /* 2355 */ >+ IC_EVEX_OPSIZE_K, /* 2356 */ >+ IC_EVEX_OPSIZE_K, /* 2357 */ >+ IC_EVEX_OPSIZE_K, /* 2358 */ >+ IC_EVEX_OPSIZE_K, /* 2359 */ >+ IC_EVEX_W_OPSIZE_K, /* 2360 */ >+ IC_EVEX_W_OPSIZE_K, /* 2361 */ >+ IC_EVEX_W_OPSIZE_K, /* 2362 */ >+ IC_EVEX_W_OPSIZE_K, /* 2363 */ >+ IC_EVEX_W_OPSIZE_K, /* 2364 */ >+ IC_EVEX_W_OPSIZE_K, /* 2365 */ >+ IC_EVEX_W_OPSIZE_K, /* 2366 */ >+ IC_EVEX_W_OPSIZE_K, /* 2367 */ >+ IC_EVEX_K, /* 2368 */ >+ IC_EVEX_K, /* 2369 */ >+ IC_EVEX_XS_K, /* 2370 */ >+ IC_EVEX_XS_K, /* 2371 */ >+ IC_EVEX_XD_K, /* 2372 */ >+ IC_EVEX_XD_K, /* 2373 */ >+ IC_EVEX_XD_K, /* 2374 */ >+ IC_EVEX_XD_K, /* 2375 */ >+ IC_EVEX_W_K, /* 2376 */ >+ IC_EVEX_W_K, /* 2377 */ >+ IC_EVEX_W_XS_K, /* 2378 */ >+ IC_EVEX_W_XS_K, /* 2379 */ >+ IC_EVEX_W_XD_K, /* 2380 */ >+ IC_EVEX_W_XD_K, /* 2381 */ >+ IC_EVEX_W_XD_K, /* 2382 */ >+ IC_EVEX_W_XD_K, /* 2383 */ >+ IC_EVEX_OPSIZE_K, /* 2384 */ >+ IC_EVEX_OPSIZE_K, /* 2385 */ >+ IC_EVEX_OPSIZE_K, /* 2386 */ >+ IC_EVEX_OPSIZE_K, /* 2387 */ >+ IC_EVEX_OPSIZE_K, /* 2388 */ >+ IC_EVEX_OPSIZE_K, /* 2389 */ >+ IC_EVEX_OPSIZE_K, /* 2390 */ >+ IC_EVEX_OPSIZE_K, /* 2391 */ >+ IC_EVEX_W_OPSIZE_K, /* 2392 */ >+ IC_EVEX_W_OPSIZE_K, /* 2393 */ >+ IC_EVEX_W_OPSIZE_K, /* 2394 */ >+ IC_EVEX_W_OPSIZE_K, /* 2395 */ >+ IC_EVEX_W_OPSIZE_K, /* 2396 */ >+ IC_EVEX_W_OPSIZE_K, /* 2397 */ >+ IC_EVEX_W_OPSIZE_K, /* 2398 */ >+ IC_EVEX_W_OPSIZE_K, /* 2399 */ >+ IC_EVEX_K, /* 2400 */ >+ IC_EVEX_K, /* 2401 */ >+ IC_EVEX_XS_K, /* 2402 */ >+ IC_EVEX_XS_K, /* 2403 */ >+ IC_EVEX_XD_K, /* 2404 */ >+ IC_EVEX_XD_K, /* 2405 */ >+ IC_EVEX_XD_K, /* 2406 */ >+ IC_EVEX_XD_K, /* 2407 */ >+ IC_EVEX_W_K, /* 2408 */ >+ IC_EVEX_W_K, /* 2409 */ >+ IC_EVEX_W_XS_K, /* 2410 */ >+ IC_EVEX_W_XS_K, /* 2411 */ >+ IC_EVEX_W_XD_K, /* 2412 */ >+ IC_EVEX_W_XD_K, /* 2413 */ >+ IC_EVEX_W_XD_K, /* 2414 */ >+ IC_EVEX_W_XD_K, /* 2415 */ >+ IC_EVEX_OPSIZE_K, /* 2416 */ >+ IC_EVEX_OPSIZE_K, /* 2417 */ >+ IC_EVEX_OPSIZE_K, /* 2418 */ >+ IC_EVEX_OPSIZE_K, /* 2419 */ >+ IC_EVEX_OPSIZE_K, /* 2420 */ >+ IC_EVEX_OPSIZE_K, /* 2421 */ >+ IC_EVEX_OPSIZE_K, /* 2422 */ >+ IC_EVEX_OPSIZE_K, /* 2423 */ >+ IC_EVEX_W_OPSIZE_K, /* 2424 */ >+ IC_EVEX_W_OPSIZE_K, /* 2425 */ >+ IC_EVEX_W_OPSIZE_K, /* 2426 */ >+ IC_EVEX_W_OPSIZE_K, /* 2427 */ >+ IC_EVEX_W_OPSIZE_K, /* 2428 */ >+ IC_EVEX_W_OPSIZE_K, /* 2429 */ >+ IC_EVEX_W_OPSIZE_K, /* 2430 */ >+ IC_EVEX_W_OPSIZE_K, /* 2431 */ >+ IC_EVEX_K, /* 2432 */ >+ IC_EVEX_K, /* 2433 */ >+ IC_EVEX_XS_K, /* 2434 */ >+ IC_EVEX_XS_K, /* 2435 */ >+ IC_EVEX_XD_K, /* 2436 */ >+ IC_EVEX_XD_K, /* 2437 */ >+ IC_EVEX_XD_K, /* 2438 */ >+ IC_EVEX_XD_K, /* 2439 */ >+ IC_EVEX_W_K, /* 2440 */ >+ IC_EVEX_W_K, /* 2441 */ >+ IC_EVEX_W_XS_K, /* 2442 */ >+ IC_EVEX_W_XS_K, /* 2443 */ >+ IC_EVEX_W_XD_K, /* 2444 */ >+ IC_EVEX_W_XD_K, /* 2445 */ >+ IC_EVEX_W_XD_K, /* 2446 */ >+ IC_EVEX_W_XD_K, /* 2447 */ >+ IC_EVEX_OPSIZE_K, /* 2448 */ >+ IC_EVEX_OPSIZE_K, /* 2449 */ >+ IC_EVEX_OPSIZE_K, /* 2450 */ >+ IC_EVEX_OPSIZE_K, /* 2451 */ >+ IC_EVEX_OPSIZE_K, /* 2452 */ >+ IC_EVEX_OPSIZE_K, /* 2453 */ >+ IC_EVEX_OPSIZE_K, /* 2454 */ >+ IC_EVEX_OPSIZE_K, /* 2455 */ >+ IC_EVEX_W_OPSIZE_K, /* 2456 */ >+ IC_EVEX_W_OPSIZE_K, /* 2457 */ >+ IC_EVEX_W_OPSIZE_K, /* 2458 */ >+ IC_EVEX_W_OPSIZE_K, /* 2459 */ >+ IC_EVEX_W_OPSIZE_K, /* 2460 */ >+ IC_EVEX_W_OPSIZE_K, /* 2461 */ >+ IC_EVEX_W_OPSIZE_K, /* 2462 */ >+ IC_EVEX_W_OPSIZE_K, /* 2463 */ >+ IC_EVEX_K, /* 2464 */ >+ IC_EVEX_K, /* 2465 */ >+ IC_EVEX_XS_K, /* 2466 */ >+ IC_EVEX_XS_K, /* 2467 */ >+ IC_EVEX_XD_K, /* 2468 */ >+ IC_EVEX_XD_K, /* 2469 */ >+ IC_EVEX_XD_K, /* 2470 */ >+ IC_EVEX_XD_K, /* 2471 */ >+ IC_EVEX_W_K, /* 2472 */ >+ IC_EVEX_W_K, /* 2473 */ >+ IC_EVEX_W_XS_K, /* 2474 */ >+ IC_EVEX_W_XS_K, /* 2475 */ >+ IC_EVEX_W_XD_K, /* 2476 */ >+ IC_EVEX_W_XD_K, /* 2477 */ >+ IC_EVEX_W_XD_K, /* 2478 */ >+ IC_EVEX_W_XD_K, /* 2479 */ >+ IC_EVEX_OPSIZE_K, /* 2480 */ >+ IC_EVEX_OPSIZE_K, /* 2481 */ >+ IC_EVEX_OPSIZE_K, /* 2482 */ >+ IC_EVEX_OPSIZE_K, /* 2483 */ >+ IC_EVEX_OPSIZE_K, /* 2484 */ >+ IC_EVEX_OPSIZE_K, /* 2485 */ >+ IC_EVEX_OPSIZE_K, /* 2486 */ >+ IC_EVEX_OPSIZE_K, /* 2487 */ >+ IC_EVEX_W_OPSIZE_K, /* 2488 */ >+ IC_EVEX_W_OPSIZE_K, /* 2489 */ >+ IC_EVEX_W_OPSIZE_K, /* 2490 */ >+ IC_EVEX_W_OPSIZE_K, /* 2491 */ >+ IC_EVEX_W_OPSIZE_K, /* 2492 */ >+ IC_EVEX_W_OPSIZE_K, /* 2493 */ >+ IC_EVEX_W_OPSIZE_K, /* 2494 */ >+ IC_EVEX_W_OPSIZE_K, /* 2495 */ >+ IC_EVEX_K, /* 2496 */ >+ IC_EVEX_K, /* 2497 */ >+ IC_EVEX_XS_K, /* 2498 */ >+ IC_EVEX_XS_K, /* 2499 */ >+ IC_EVEX_XD_K, /* 2500 */ >+ IC_EVEX_XD_K, /* 2501 */ >+ IC_EVEX_XD_K, /* 2502 */ >+ IC_EVEX_XD_K, /* 2503 */ >+ IC_EVEX_W_K, /* 2504 */ >+ IC_EVEX_W_K, /* 2505 */ >+ IC_EVEX_W_XS_K, /* 2506 */ >+ IC_EVEX_W_XS_K, /* 2507 */ >+ IC_EVEX_W_XD_K, /* 2508 */ >+ IC_EVEX_W_XD_K, /* 2509 */ >+ IC_EVEX_W_XD_K, /* 2510 */ >+ IC_EVEX_W_XD_K, /* 2511 */ >+ IC_EVEX_OPSIZE_K, /* 2512 */ >+ IC_EVEX_OPSIZE_K, /* 2513 */ >+ IC_EVEX_OPSIZE_K, /* 2514 */ >+ IC_EVEX_OPSIZE_K, /* 2515 */ >+ IC_EVEX_OPSIZE_K, /* 2516 */ >+ IC_EVEX_OPSIZE_K, /* 2517 */ >+ IC_EVEX_OPSIZE_K, /* 2518 */ >+ IC_EVEX_OPSIZE_K, /* 2519 */ >+ IC_EVEX_W_OPSIZE_K, /* 2520 */ >+ IC_EVEX_W_OPSIZE_K, /* 2521 */ >+ IC_EVEX_W_OPSIZE_K, /* 2522 */ >+ IC_EVEX_W_OPSIZE_K, /* 2523 */ >+ IC_EVEX_W_OPSIZE_K, /* 2524 */ >+ IC_EVEX_W_OPSIZE_K, /* 2525 */ >+ IC_EVEX_W_OPSIZE_K, /* 2526 */ >+ IC_EVEX_W_OPSIZE_K, /* 2527 */ >+ IC_EVEX_K, /* 2528 */ >+ IC_EVEX_K, /* 2529 */ >+ IC_EVEX_XS_K, /* 2530 */ >+ IC_EVEX_XS_K, /* 2531 */ >+ IC_EVEX_XD_K, /* 2532 */ >+ IC_EVEX_XD_K, /* 2533 */ >+ IC_EVEX_XD_K, /* 2534 */ >+ IC_EVEX_XD_K, /* 2535 */ >+ IC_EVEX_W_K, /* 2536 */ >+ IC_EVEX_W_K, /* 2537 */ >+ IC_EVEX_W_XS_K, /* 2538 */ >+ IC_EVEX_W_XS_K, /* 2539 */ >+ IC_EVEX_W_XD_K, /* 2540 */ >+ IC_EVEX_W_XD_K, /* 2541 */ >+ IC_EVEX_W_XD_K, /* 2542 */ >+ IC_EVEX_W_XD_K, /* 2543 */ >+ IC_EVEX_OPSIZE_K, /* 2544 */ >+ IC_EVEX_OPSIZE_K, /* 2545 */ >+ IC_EVEX_OPSIZE_K, /* 2546 */ >+ IC_EVEX_OPSIZE_K, /* 2547 */ >+ IC_EVEX_OPSIZE_K, /* 2548 */ >+ IC_EVEX_OPSIZE_K, /* 2549 */ >+ IC_EVEX_OPSIZE_K, /* 2550 */ >+ IC_EVEX_OPSIZE_K, /* 2551 */ >+ IC_EVEX_W_OPSIZE_K, /* 2552 */ >+ IC_EVEX_W_OPSIZE_K, /* 2553 */ >+ IC_EVEX_W_OPSIZE_K, /* 2554 */ >+ IC_EVEX_W_OPSIZE_K, /* 2555 */ >+ IC_EVEX_W_OPSIZE_K, /* 2556 */ >+ IC_EVEX_W_OPSIZE_K, /* 2557 */ >+ IC_EVEX_W_OPSIZE_K, /* 2558 */ >+ IC_EVEX_W_OPSIZE_K, /* 2559 */ >+ IC, /* 2560 */ >+ IC_64BIT, /* 2561 */ >+ IC_XS, /* 2562 */ >+ IC_64BIT_XS, /* 2563 */ >+ IC_XD, /* 2564 */ >+ IC_64BIT_XD, /* 2565 */ >+ IC_XS, /* 2566 */ >+ IC_64BIT_XS, /* 2567 */ >+ IC, /* 2568 */ >+ IC_64BIT_REXW, /* 2569 */ >+ IC_XS, /* 2570 */ >+ IC_64BIT_REXW_XS, /* 2571 */ >+ IC_XD, /* 2572 */ >+ IC_64BIT_REXW_XD, /* 2573 */ >+ IC_XS, /* 2574 */ >+ IC_64BIT_REXW_XS, /* 2575 */ >+ IC_OPSIZE, /* 2576 */ >+ IC_64BIT_OPSIZE, /* 2577 */ >+ IC_XS_OPSIZE, /* 2578 */ >+ IC_64BIT_XS_OPSIZE, /* 2579 */ >+ IC_XD_OPSIZE, /* 2580 */ >+ IC_64BIT_XD_OPSIZE, /* 2581 */ >+ IC_XS_OPSIZE, /* 2582 */ >+ IC_64BIT_XD_OPSIZE, /* 2583 */ >+ IC_OPSIZE, /* 2584 */ >+ IC_64BIT_REXW_OPSIZE, /* 2585 */ >+ IC_XS_OPSIZE, /* 2586 */ >+ IC_64BIT_REXW_XS, /* 2587 */ >+ IC_XD_OPSIZE, /* 2588 */ >+ IC_64BIT_REXW_XD, /* 2589 */ >+ IC_XS_OPSIZE, /* 2590 */ >+ IC_64BIT_REXW_XS, /* 2591 */ >+ IC_ADSIZE, /* 2592 */ >+ IC_64BIT_ADSIZE, /* 2593 */ >+ IC_XS, /* 2594 */ >+ IC_64BIT_XS, /* 2595 */ >+ IC_XD, /* 2596 */ >+ IC_64BIT_XD, /* 2597 */ >+ IC_XS, /* 2598 */ >+ IC_64BIT_XS, /* 2599 */ >+ IC_ADSIZE, /* 2600 */ >+ IC_64BIT_ADSIZE, /* 2601 */ >+ IC_XS, /* 2602 */ >+ IC_64BIT_REXW_XS, /* 2603 */ >+ IC_XD, /* 2604 */ >+ IC_64BIT_REXW_XD, /* 2605 */ >+ IC_XS, /* 2606 */ >+ IC_64BIT_REXW_XS, /* 2607 */ >+ IC_OPSIZE, /* 2608 */ >+ IC_64BIT_OPSIZE, /* 2609 */ >+ IC_XS_OPSIZE, /* 2610 */ >+ IC_64BIT_XS_OPSIZE, /* 2611 */ >+ IC_XD_OPSIZE, /* 2612 */ >+ IC_64BIT_XD_OPSIZE, /* 2613 */ >+ IC_XS_OPSIZE, /* 2614 */ >+ IC_64BIT_XD_OPSIZE, /* 2615 */ >+ IC_OPSIZE, /* 2616 */ >+ IC_64BIT_REXW_OPSIZE, /* 2617 */ >+ IC_XS_OPSIZE, /* 2618 */ >+ IC_64BIT_REXW_XS, /* 2619 */ >+ IC_XD_OPSIZE, /* 2620 */ >+ IC_64BIT_REXW_XD, /* 2621 */ >+ IC_XS_OPSIZE, /* 2622 */ >+ IC_64BIT_REXW_XS, /* 2623 */ >+ IC_VEX, /* 2624 */ >+ IC_VEX, /* 2625 */ >+ IC_VEX_XS, /* 2626 */ >+ IC_VEX_XS, /* 2627 */ >+ IC_VEX_XD, /* 2628 */ >+ IC_VEX_XD, /* 2629 */ >+ IC_VEX_XD, /* 2630 */ >+ IC_VEX_XD, /* 2631 */ >+ IC_VEX_W, /* 2632 */ >+ IC_VEX_W, /* 2633 */ >+ IC_VEX_W_XS, /* 2634 */ >+ IC_VEX_W_XS, /* 2635 */ >+ IC_VEX_W_XD, /* 2636 */ >+ IC_VEX_W_XD, /* 2637 */ >+ IC_VEX_W_XD, /* 2638 */ >+ IC_VEX_W_XD, /* 2639 */ >+ IC_VEX_OPSIZE, /* 2640 */ >+ IC_VEX_OPSIZE, /* 2641 */ >+ IC_VEX_OPSIZE, /* 2642 */ >+ IC_VEX_OPSIZE, /* 2643 */ >+ IC_VEX_OPSIZE, /* 2644 */ >+ IC_VEX_OPSIZE, /* 2645 */ >+ IC_VEX_OPSIZE, /* 2646 */ >+ IC_VEX_OPSIZE, /* 2647 */ >+ IC_VEX_W_OPSIZE, /* 2648 */ >+ IC_VEX_W_OPSIZE, /* 2649 */ >+ IC_VEX_W_OPSIZE, /* 2650 */ >+ IC_VEX_W_OPSIZE, /* 2651 */ >+ IC_VEX_W_OPSIZE, /* 2652 */ >+ IC_VEX_W_OPSIZE, /* 2653 */ >+ IC_VEX_W_OPSIZE, /* 2654 */ >+ IC_VEX_W_OPSIZE, /* 2655 */ >+ IC_VEX, /* 2656 */ >+ IC_VEX, /* 2657 */ >+ IC_VEX_XS, /* 2658 */ >+ IC_VEX_XS, /* 2659 */ >+ IC_VEX_XD, /* 2660 */ >+ IC_VEX_XD, /* 2661 */ >+ IC_VEX_XD, /* 2662 */ >+ IC_VEX_XD, /* 2663 */ >+ IC_VEX_W, /* 2664 */ >+ IC_VEX_W, /* 2665 */ >+ IC_VEX_W_XS, /* 2666 */ >+ IC_VEX_W_XS, /* 2667 */ >+ IC_VEX_W_XD, /* 2668 */ >+ IC_VEX_W_XD, /* 2669 */ >+ IC_VEX_W_XD, /* 2670 */ >+ IC_VEX_W_XD, /* 2671 */ >+ IC_VEX_OPSIZE, /* 2672 */ >+ IC_VEX_OPSIZE, /* 2673 */ >+ IC_VEX_OPSIZE, /* 2674 */ >+ IC_VEX_OPSIZE, /* 2675 */ >+ IC_VEX_OPSIZE, /* 2676 */ >+ IC_VEX_OPSIZE, /* 2677 */ >+ IC_VEX_OPSIZE, /* 2678 */ >+ IC_VEX_OPSIZE, /* 2679 */ >+ IC_VEX_W_OPSIZE, /* 2680 */ >+ IC_VEX_W_OPSIZE, /* 2681 */ >+ IC_VEX_W_OPSIZE, /* 2682 */ >+ IC_VEX_W_OPSIZE, /* 2683 */ >+ IC_VEX_W_OPSIZE, /* 2684 */ >+ IC_VEX_W_OPSIZE, /* 2685 */ >+ IC_VEX_W_OPSIZE, /* 2686 */ >+ IC_VEX_W_OPSIZE, /* 2687 */ >+ IC_VEX_L, /* 2688 */ >+ IC_VEX_L, /* 2689 */ >+ IC_VEX_L_XS, /* 2690 */ >+ IC_VEX_L_XS, /* 2691 */ >+ IC_VEX_L_XD, /* 2692 */ >+ IC_VEX_L_XD, /* 2693 */ >+ IC_VEX_L_XD, /* 2694 */ >+ IC_VEX_L_XD, /* 2695 */ >+ IC_VEX_L_W, /* 2696 */ >+ IC_VEX_L_W, /* 2697 */ >+ IC_VEX_L_W_XS, /* 2698 */ >+ IC_VEX_L_W_XS, /* 2699 */ >+ IC_VEX_L_W_XD, /* 2700 */ >+ IC_VEX_L_W_XD, /* 2701 */ >+ IC_VEX_L_W_XD, /* 2702 */ >+ IC_VEX_L_W_XD, /* 2703 */ >+ IC_VEX_L_OPSIZE, /* 2704 */ >+ IC_VEX_L_OPSIZE, /* 2705 */ >+ IC_VEX_L_OPSIZE, /* 2706 */ >+ IC_VEX_L_OPSIZE, /* 2707 */ >+ IC_VEX_L_OPSIZE, /* 2708 */ >+ IC_VEX_L_OPSIZE, /* 2709 */ >+ IC_VEX_L_OPSIZE, /* 2710 */ >+ IC_VEX_L_OPSIZE, /* 2711 */ >+ IC_VEX_L_W_OPSIZE, /* 2712 */ >+ IC_VEX_L_W_OPSIZE, /* 2713 */ >+ IC_VEX_L_W_OPSIZE, /* 2714 */ >+ IC_VEX_L_W_OPSIZE, /* 2715 */ >+ IC_VEX_L_W_OPSIZE, /* 2716 */ >+ IC_VEX_L_W_OPSIZE, /* 2717 */ >+ IC_VEX_L_W_OPSIZE, /* 2718 */ >+ IC_VEX_L_W_OPSIZE, /* 2719 */ >+ IC_VEX_L, /* 2720 */ >+ IC_VEX_L, /* 2721 */ >+ IC_VEX_L_XS, /* 2722 */ >+ IC_VEX_L_XS, /* 2723 */ >+ IC_VEX_L_XD, /* 2724 */ >+ IC_VEX_L_XD, /* 2725 */ >+ IC_VEX_L_XD, /* 2726 */ >+ IC_VEX_L_XD, /* 2727 */ >+ IC_VEX_L_W, /* 2728 */ >+ IC_VEX_L_W, /* 2729 */ >+ IC_VEX_L_W_XS, /* 2730 */ >+ IC_VEX_L_W_XS, /* 2731 */ >+ IC_VEX_L_W_XD, /* 2732 */ >+ IC_VEX_L_W_XD, /* 2733 */ >+ IC_VEX_L_W_XD, /* 2734 */ >+ IC_VEX_L_W_XD, /* 2735 */ >+ IC_VEX_L_OPSIZE, /* 2736 */ >+ IC_VEX_L_OPSIZE, /* 2737 */ >+ IC_VEX_L_OPSIZE, /* 2738 */ >+ IC_VEX_L_OPSIZE, /* 2739 */ >+ IC_VEX_L_OPSIZE, /* 2740 */ >+ IC_VEX_L_OPSIZE, /* 2741 */ >+ IC_VEX_L_OPSIZE, /* 2742 */ >+ IC_VEX_L_OPSIZE, /* 2743 */ >+ IC_VEX_L_W_OPSIZE, /* 2744 */ >+ IC_VEX_L_W_OPSIZE, /* 2745 */ >+ IC_VEX_L_W_OPSIZE, /* 2746 */ >+ IC_VEX_L_W_OPSIZE, /* 2747 */ >+ IC_VEX_L_W_OPSIZE, /* 2748 */ >+ IC_VEX_L_W_OPSIZE, /* 2749 */ >+ IC_VEX_L_W_OPSIZE, /* 2750 */ >+ IC_VEX_L_W_OPSIZE, /* 2751 */ >+ IC_VEX_L, /* 2752 */ >+ IC_VEX_L, /* 2753 */ >+ IC_VEX_L_XS, /* 2754 */ >+ IC_VEX_L_XS, /* 2755 */ >+ IC_VEX_L_XD, /* 2756 */ >+ IC_VEX_L_XD, /* 2757 */ >+ IC_VEX_L_XD, /* 2758 */ >+ IC_VEX_L_XD, /* 2759 */ >+ IC_VEX_L_W, /* 2760 */ >+ IC_VEX_L_W, /* 2761 */ >+ IC_VEX_L_W_XS, /* 2762 */ >+ IC_VEX_L_W_XS, /* 2763 */ >+ IC_VEX_L_W_XD, /* 2764 */ >+ IC_VEX_L_W_XD, /* 2765 */ >+ IC_VEX_L_W_XD, /* 2766 */ >+ IC_VEX_L_W_XD, /* 2767 */ >+ IC_VEX_L_OPSIZE, /* 2768 */ >+ IC_VEX_L_OPSIZE, /* 2769 */ >+ IC_VEX_L_OPSIZE, /* 2770 */ >+ IC_VEX_L_OPSIZE, /* 2771 */ >+ IC_VEX_L_OPSIZE, /* 2772 */ >+ IC_VEX_L_OPSIZE, /* 2773 */ >+ IC_VEX_L_OPSIZE, /* 2774 */ >+ IC_VEX_L_OPSIZE, /* 2775 */ >+ IC_VEX_L_W_OPSIZE, /* 2776 */ >+ IC_VEX_L_W_OPSIZE, /* 2777 */ >+ IC_VEX_L_W_OPSIZE, /* 2778 */ >+ IC_VEX_L_W_OPSIZE, /* 2779 */ >+ IC_VEX_L_W_OPSIZE, /* 2780 */ >+ IC_VEX_L_W_OPSIZE, /* 2781 */ >+ IC_VEX_L_W_OPSIZE, /* 2782 */ >+ IC_VEX_L_W_OPSIZE, /* 2783 */ >+ IC_VEX_L, /* 2784 */ >+ IC_VEX_L, /* 2785 */ >+ IC_VEX_L_XS, /* 2786 */ >+ IC_VEX_L_XS, /* 2787 */ >+ IC_VEX_L_XD, /* 2788 */ >+ IC_VEX_L_XD, /* 2789 */ >+ IC_VEX_L_XD, /* 2790 */ >+ IC_VEX_L_XD, /* 2791 */ >+ IC_VEX_L_W, /* 2792 */ >+ IC_VEX_L_W, /* 2793 */ >+ IC_VEX_L_W_XS, /* 2794 */ >+ IC_VEX_L_W_XS, /* 2795 */ >+ IC_VEX_L_W_XD, /* 2796 */ >+ IC_VEX_L_W_XD, /* 2797 */ >+ IC_VEX_L_W_XD, /* 2798 */ >+ IC_VEX_L_W_XD, /* 2799 */ >+ IC_VEX_L_OPSIZE, /* 2800 */ >+ IC_VEX_L_OPSIZE, /* 2801 */ >+ IC_VEX_L_OPSIZE, /* 2802 */ >+ IC_VEX_L_OPSIZE, /* 2803 */ >+ IC_VEX_L_OPSIZE, /* 2804 */ >+ IC_VEX_L_OPSIZE, /* 2805 */ >+ IC_VEX_L_OPSIZE, /* 2806 */ >+ IC_VEX_L_OPSIZE, /* 2807 */ >+ IC_VEX_L_W_OPSIZE, /* 2808 */ >+ IC_VEX_L_W_OPSIZE, /* 2809 */ >+ IC_VEX_L_W_OPSIZE, /* 2810 */ >+ IC_VEX_L_W_OPSIZE, /* 2811 */ >+ IC_VEX_L_W_OPSIZE, /* 2812 */ >+ IC_VEX_L_W_OPSIZE, /* 2813 */ >+ IC_VEX_L_W_OPSIZE, /* 2814 */ >+ IC_VEX_L_W_OPSIZE, /* 2815 */ >+ IC_EVEX_L_K, /* 2816 */ >+ IC_EVEX_L_K, /* 2817 */ >+ IC_EVEX_L_XS_K, /* 2818 */ >+ IC_EVEX_L_XS_K, /* 2819 */ >+ IC_EVEX_L_XD_K, /* 2820 */ >+ IC_EVEX_L_XD_K, /* 2821 */ >+ IC_EVEX_L_XD_K, /* 2822 */ >+ IC_EVEX_L_XD_K, /* 2823 */ >+ IC_EVEX_L_W_K, /* 2824 */ >+ IC_EVEX_L_W_K, /* 2825 */ >+ IC_EVEX_L_W_XS_K, /* 2826 */ >+ IC_EVEX_L_W_XS_K, /* 2827 */ >+ IC_EVEX_L_W_XD_K, /* 2828 */ >+ IC_EVEX_L_W_XD_K, /* 2829 */ >+ IC_EVEX_L_W_XD_K, /* 2830 */ >+ IC_EVEX_L_W_XD_K, /* 2831 */ >+ IC_EVEX_L_OPSIZE_K, /* 2832 */ >+ IC_EVEX_L_OPSIZE_K, /* 2833 */ >+ IC_EVEX_L_OPSIZE_K, /* 2834 */ >+ IC_EVEX_L_OPSIZE_K, /* 2835 */ >+ IC_EVEX_L_OPSIZE_K, /* 2836 */ >+ IC_EVEX_L_OPSIZE_K, /* 2837 */ >+ IC_EVEX_L_OPSIZE_K, /* 2838 */ >+ IC_EVEX_L_OPSIZE_K, /* 2839 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2840 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2841 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2842 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2843 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2844 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2845 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2846 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2847 */ >+ IC_EVEX_L_K, /* 2848 */ >+ IC_EVEX_L_K, /* 2849 */ >+ IC_EVEX_L_XS_K, /* 2850 */ >+ IC_EVEX_L_XS_K, /* 2851 */ >+ IC_EVEX_L_XD_K, /* 2852 */ >+ IC_EVEX_L_XD_K, /* 2853 */ >+ IC_EVEX_L_XD_K, /* 2854 */ >+ IC_EVEX_L_XD_K, /* 2855 */ >+ IC_EVEX_L_W_K, /* 2856 */ >+ IC_EVEX_L_W_K, /* 2857 */ >+ IC_EVEX_L_W_XS_K, /* 2858 */ >+ IC_EVEX_L_W_XS_K, /* 2859 */ >+ IC_EVEX_L_W_XD_K, /* 2860 */ >+ IC_EVEX_L_W_XD_K, /* 2861 */ >+ IC_EVEX_L_W_XD_K, /* 2862 */ >+ IC_EVEX_L_W_XD_K, /* 2863 */ >+ IC_EVEX_L_OPSIZE_K, /* 2864 */ >+ IC_EVEX_L_OPSIZE_K, /* 2865 */ >+ IC_EVEX_L_OPSIZE_K, /* 2866 */ >+ IC_EVEX_L_OPSIZE_K, /* 2867 */ >+ IC_EVEX_L_OPSIZE_K, /* 2868 */ >+ IC_EVEX_L_OPSIZE_K, /* 2869 */ >+ IC_EVEX_L_OPSIZE_K, /* 2870 */ >+ IC_EVEX_L_OPSIZE_K, /* 2871 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2872 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2873 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2874 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2875 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2876 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2877 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2878 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2879 */ >+ IC_EVEX_L_K, /* 2880 */ >+ IC_EVEX_L_K, /* 2881 */ >+ IC_EVEX_L_XS_K, /* 2882 */ >+ IC_EVEX_L_XS_K, /* 2883 */ >+ IC_EVEX_L_XD_K, /* 2884 */ >+ IC_EVEX_L_XD_K, /* 2885 */ >+ IC_EVEX_L_XD_K, /* 2886 */ >+ IC_EVEX_L_XD_K, /* 2887 */ >+ IC_EVEX_L_W_K, /* 2888 */ >+ IC_EVEX_L_W_K, /* 2889 */ >+ IC_EVEX_L_W_XS_K, /* 2890 */ >+ IC_EVEX_L_W_XS_K, /* 2891 */ >+ IC_EVEX_L_W_XD_K, /* 2892 */ >+ IC_EVEX_L_W_XD_K, /* 2893 */ >+ IC_EVEX_L_W_XD_K, /* 2894 */ >+ IC_EVEX_L_W_XD_K, /* 2895 */ >+ IC_EVEX_L_OPSIZE_K, /* 2896 */ >+ IC_EVEX_L_OPSIZE_K, /* 2897 */ >+ IC_EVEX_L_OPSIZE_K, /* 2898 */ >+ IC_EVEX_L_OPSIZE_K, /* 2899 */ >+ IC_EVEX_L_OPSIZE_K, /* 2900 */ >+ IC_EVEX_L_OPSIZE_K, /* 2901 */ >+ IC_EVEX_L_OPSIZE_K, /* 2902 */ >+ IC_EVEX_L_OPSIZE_K, /* 2903 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2904 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2905 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2906 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2907 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2908 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2909 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2910 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2911 */ >+ IC_EVEX_L_K, /* 2912 */ >+ IC_EVEX_L_K, /* 2913 */ >+ IC_EVEX_L_XS_K, /* 2914 */ >+ IC_EVEX_L_XS_K, /* 2915 */ >+ IC_EVEX_L_XD_K, /* 2916 */ >+ IC_EVEX_L_XD_K, /* 2917 */ >+ IC_EVEX_L_XD_K, /* 2918 */ >+ IC_EVEX_L_XD_K, /* 2919 */ >+ IC_EVEX_L_W_K, /* 2920 */ >+ IC_EVEX_L_W_K, /* 2921 */ >+ IC_EVEX_L_W_XS_K, /* 2922 */ >+ IC_EVEX_L_W_XS_K, /* 2923 */ >+ IC_EVEX_L_W_XD_K, /* 2924 */ >+ IC_EVEX_L_W_XD_K, /* 2925 */ >+ IC_EVEX_L_W_XD_K, /* 2926 */ >+ IC_EVEX_L_W_XD_K, /* 2927 */ >+ IC_EVEX_L_OPSIZE_K, /* 2928 */ >+ IC_EVEX_L_OPSIZE_K, /* 2929 */ >+ IC_EVEX_L_OPSIZE_K, /* 2930 */ >+ IC_EVEX_L_OPSIZE_K, /* 2931 */ >+ IC_EVEX_L_OPSIZE_K, /* 2932 */ >+ IC_EVEX_L_OPSIZE_K, /* 2933 */ >+ IC_EVEX_L_OPSIZE_K, /* 2934 */ >+ IC_EVEX_L_OPSIZE_K, /* 2935 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2936 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2937 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2938 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2939 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2940 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2941 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2942 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2943 */ >+ IC_EVEX_L_K, /* 2944 */ >+ IC_EVEX_L_K, /* 2945 */ >+ IC_EVEX_L_XS_K, /* 2946 */ >+ IC_EVEX_L_XS_K, /* 2947 */ >+ IC_EVEX_L_XD_K, /* 2948 */ >+ IC_EVEX_L_XD_K, /* 2949 */ >+ IC_EVEX_L_XD_K, /* 2950 */ >+ IC_EVEX_L_XD_K, /* 2951 */ >+ IC_EVEX_L_W_K, /* 2952 */ >+ IC_EVEX_L_W_K, /* 2953 */ >+ IC_EVEX_L_W_XS_K, /* 2954 */ >+ IC_EVEX_L_W_XS_K, /* 2955 */ >+ IC_EVEX_L_W_XD_K, /* 2956 */ >+ IC_EVEX_L_W_XD_K, /* 2957 */ >+ IC_EVEX_L_W_XD_K, /* 2958 */ >+ IC_EVEX_L_W_XD_K, /* 2959 */ >+ IC_EVEX_L_OPSIZE_K, /* 2960 */ >+ IC_EVEX_L_OPSIZE_K, /* 2961 */ >+ IC_EVEX_L_OPSIZE_K, /* 2962 */ >+ IC_EVEX_L_OPSIZE_K, /* 2963 */ >+ IC_EVEX_L_OPSIZE_K, /* 2964 */ >+ IC_EVEX_L_OPSIZE_K, /* 2965 */ >+ IC_EVEX_L_OPSIZE_K, /* 2966 */ >+ IC_EVEX_L_OPSIZE_K, /* 2967 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2968 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2969 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2970 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2971 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2972 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2973 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2974 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 2975 */ >+ IC_EVEX_L_K, /* 2976 */ >+ IC_EVEX_L_K, /* 2977 */ >+ IC_EVEX_L_XS_K, /* 2978 */ >+ IC_EVEX_L_XS_K, /* 2979 */ >+ IC_EVEX_L_XD_K, /* 2980 */ >+ IC_EVEX_L_XD_K, /* 2981 */ >+ IC_EVEX_L_XD_K, /* 2982 */ >+ IC_EVEX_L_XD_K, /* 2983 */ >+ IC_EVEX_L_W_K, /* 2984 */ >+ IC_EVEX_L_W_K, /* 2985 */ >+ IC_EVEX_L_W_XS_K, /* 2986 */ >+ IC_EVEX_L_W_XS_K, /* 2987 */ >+ IC_EVEX_L_W_XD_K, /* 2988 */ >+ IC_EVEX_L_W_XD_K, /* 2989 */ >+ IC_EVEX_L_W_XD_K, /* 2990 */ >+ IC_EVEX_L_W_XD_K, /* 2991 */ >+ IC_EVEX_L_OPSIZE_K, /* 2992 */ >+ IC_EVEX_L_OPSIZE_K, /* 2993 */ >+ IC_EVEX_L_OPSIZE_K, /* 2994 */ >+ IC_EVEX_L_OPSIZE_K, /* 2995 */ >+ IC_EVEX_L_OPSIZE_K, /* 2996 */ >+ IC_EVEX_L_OPSIZE_K, /* 2997 */ >+ IC_EVEX_L_OPSIZE_K, /* 2998 */ >+ IC_EVEX_L_OPSIZE_K, /* 2999 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3000 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3001 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3002 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3003 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3004 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3005 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3006 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3007 */ >+ IC_EVEX_L_K, /* 3008 */ >+ IC_EVEX_L_K, /* 3009 */ >+ IC_EVEX_L_XS_K, /* 3010 */ >+ IC_EVEX_L_XS_K, /* 3011 */ >+ IC_EVEX_L_XD_K, /* 3012 */ >+ IC_EVEX_L_XD_K, /* 3013 */ >+ IC_EVEX_L_XD_K, /* 3014 */ >+ IC_EVEX_L_XD_K, /* 3015 */ >+ IC_EVEX_L_W_K, /* 3016 */ >+ IC_EVEX_L_W_K, /* 3017 */ >+ IC_EVEX_L_W_XS_K, /* 3018 */ >+ IC_EVEX_L_W_XS_K, /* 3019 */ >+ IC_EVEX_L_W_XD_K, /* 3020 */ >+ IC_EVEX_L_W_XD_K, /* 3021 */ >+ IC_EVEX_L_W_XD_K, /* 3022 */ >+ IC_EVEX_L_W_XD_K, /* 3023 */ >+ IC_EVEX_L_OPSIZE_K, /* 3024 */ >+ IC_EVEX_L_OPSIZE_K, /* 3025 */ >+ IC_EVEX_L_OPSIZE_K, /* 3026 */ >+ IC_EVEX_L_OPSIZE_K, /* 3027 */ >+ IC_EVEX_L_OPSIZE_K, /* 3028 */ >+ IC_EVEX_L_OPSIZE_K, /* 3029 */ >+ IC_EVEX_L_OPSIZE_K, /* 3030 */ >+ IC_EVEX_L_OPSIZE_K, /* 3031 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3032 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3033 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3034 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3035 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3036 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3037 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3038 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3039 */ >+ IC_EVEX_L_K, /* 3040 */ >+ IC_EVEX_L_K, /* 3041 */ >+ IC_EVEX_L_XS_K, /* 3042 */ >+ IC_EVEX_L_XS_K, /* 3043 */ >+ IC_EVEX_L_XD_K, /* 3044 */ >+ IC_EVEX_L_XD_K, /* 3045 */ >+ IC_EVEX_L_XD_K, /* 3046 */ >+ IC_EVEX_L_XD_K, /* 3047 */ >+ IC_EVEX_L_W_K, /* 3048 */ >+ IC_EVEX_L_W_K, /* 3049 */ >+ IC_EVEX_L_W_XS_K, /* 3050 */ >+ IC_EVEX_L_W_XS_K, /* 3051 */ >+ IC_EVEX_L_W_XD_K, /* 3052 */ >+ IC_EVEX_L_W_XD_K, /* 3053 */ >+ IC_EVEX_L_W_XD_K, /* 3054 */ >+ IC_EVEX_L_W_XD_K, /* 3055 */ >+ IC_EVEX_L_OPSIZE_K, /* 3056 */ >+ IC_EVEX_L_OPSIZE_K, /* 3057 */ >+ IC_EVEX_L_OPSIZE_K, /* 3058 */ >+ IC_EVEX_L_OPSIZE_K, /* 3059 */ >+ IC_EVEX_L_OPSIZE_K, /* 3060 */ >+ IC_EVEX_L_OPSIZE_K, /* 3061 */ >+ IC_EVEX_L_OPSIZE_K, /* 3062 */ >+ IC_EVEX_L_OPSIZE_K, /* 3063 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3064 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3065 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3066 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3067 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3068 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3069 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3070 */ >+ IC_EVEX_L_W_OPSIZE_K, /* 3071 */ >+ IC, /* 3072 */ >+ IC_64BIT, /* 3073 */ >+ IC_XS, /* 3074 */ >+ IC_64BIT_XS, /* 3075 */ >+ IC_XD, /* 3076 */ >+ IC_64BIT_XD, /* 3077 */ >+ IC_XS, /* 3078 */ >+ IC_64BIT_XS, /* 3079 */ >+ IC, /* 3080 */ >+ IC_64BIT_REXW, /* 3081 */ >+ IC_XS, /* 3082 */ >+ IC_64BIT_REXW_XS, /* 3083 */ >+ IC_XD, /* 3084 */ >+ IC_64BIT_REXW_XD, /* 3085 */ >+ IC_XS, /* 3086 */ >+ IC_64BIT_REXW_XS, /* 3087 */ >+ IC_OPSIZE, /* 3088 */ >+ IC_64BIT_OPSIZE, /* 3089 */ >+ IC_XS_OPSIZE, /* 3090 */ >+ IC_64BIT_XS_OPSIZE, /* 3091 */ >+ IC_XD_OPSIZE, /* 3092 */ >+ IC_64BIT_XD_OPSIZE, /* 3093 */ >+ IC_XS_OPSIZE, /* 3094 */ >+ IC_64BIT_XD_OPSIZE, /* 3095 */ >+ IC_OPSIZE, /* 3096 */ >+ IC_64BIT_REXW_OPSIZE, /* 3097 */ >+ IC_XS_OPSIZE, /* 3098 */ >+ IC_64BIT_REXW_XS, /* 3099 */ >+ IC_XD_OPSIZE, /* 3100 */ >+ IC_64BIT_REXW_XD, /* 3101 */ >+ IC_XS_OPSIZE, /* 3102 */ >+ IC_64BIT_REXW_XS, /* 3103 */ >+ IC_ADSIZE, /* 3104 */ >+ IC_64BIT_ADSIZE, /* 3105 */ >+ IC_XS, /* 3106 */ >+ IC_64BIT_XS, /* 3107 */ >+ IC_XD, /* 3108 */ >+ IC_64BIT_XD, /* 3109 */ >+ IC_XS, /* 3110 */ >+ IC_64BIT_XS, /* 3111 */ >+ IC_ADSIZE, /* 3112 */ >+ IC_64BIT_ADSIZE, /* 3113 */ >+ IC_XS, /* 3114 */ >+ IC_64BIT_REXW_XS, /* 3115 */ >+ IC_XD, /* 3116 */ >+ IC_64BIT_REXW_XD, /* 3117 */ >+ IC_XS, /* 3118 */ >+ IC_64BIT_REXW_XS, /* 3119 */ >+ IC_OPSIZE, /* 3120 */ >+ IC_64BIT_OPSIZE, /* 3121 */ >+ IC_XS_OPSIZE, /* 3122 */ >+ IC_64BIT_XS_OPSIZE, /* 3123 */ >+ IC_XD_OPSIZE, /* 3124 */ >+ IC_64BIT_XD_OPSIZE, /* 3125 */ >+ IC_XS_OPSIZE, /* 3126 */ >+ IC_64BIT_XD_OPSIZE, /* 3127 */ >+ IC_OPSIZE, /* 3128 */ >+ IC_64BIT_REXW_OPSIZE, /* 3129 */ >+ IC_XS_OPSIZE, /* 3130 */ >+ IC_64BIT_REXW_XS, /* 3131 */ >+ IC_XD_OPSIZE, /* 3132 */ >+ IC_64BIT_REXW_XD, /* 3133 */ >+ IC_XS_OPSIZE, /* 3134 */ >+ IC_64BIT_REXW_XS, /* 3135 */ >+ IC_VEX, /* 3136 */ >+ IC_VEX, /* 3137 */ >+ IC_VEX_XS, /* 3138 */ >+ IC_VEX_XS, /* 3139 */ >+ IC_VEX_XD, /* 3140 */ >+ IC_VEX_XD, /* 3141 */ >+ IC_VEX_XD, /* 3142 */ >+ IC_VEX_XD, /* 3143 */ >+ IC_VEX_W, /* 3144 */ >+ IC_VEX_W, /* 3145 */ >+ IC_VEX_W_XS, /* 3146 */ >+ IC_VEX_W_XS, /* 3147 */ >+ IC_VEX_W_XD, /* 3148 */ >+ IC_VEX_W_XD, /* 3149 */ >+ IC_VEX_W_XD, /* 3150 */ >+ IC_VEX_W_XD, /* 3151 */ >+ IC_VEX_OPSIZE, /* 3152 */ >+ IC_VEX_OPSIZE, /* 3153 */ >+ IC_VEX_OPSIZE, /* 3154 */ >+ IC_VEX_OPSIZE, /* 3155 */ >+ IC_VEX_OPSIZE, /* 3156 */ >+ IC_VEX_OPSIZE, /* 3157 */ >+ IC_VEX_OPSIZE, /* 3158 */ >+ IC_VEX_OPSIZE, /* 3159 */ >+ IC_VEX_W_OPSIZE, /* 3160 */ >+ IC_VEX_W_OPSIZE, /* 3161 */ >+ IC_VEX_W_OPSIZE, /* 3162 */ >+ IC_VEX_W_OPSIZE, /* 3163 */ >+ IC_VEX_W_OPSIZE, /* 3164 */ >+ IC_VEX_W_OPSIZE, /* 3165 */ >+ IC_VEX_W_OPSIZE, /* 3166 */ >+ IC_VEX_W_OPSIZE, /* 3167 */ >+ IC_VEX, /* 3168 */ >+ IC_VEX, /* 3169 */ >+ IC_VEX_XS, /* 3170 */ >+ IC_VEX_XS, /* 3171 */ >+ IC_VEX_XD, /* 3172 */ >+ IC_VEX_XD, /* 3173 */ >+ IC_VEX_XD, /* 3174 */ >+ IC_VEX_XD, /* 3175 */ >+ IC_VEX_W, /* 3176 */ >+ IC_VEX_W, /* 3177 */ >+ IC_VEX_W_XS, /* 3178 */ >+ IC_VEX_W_XS, /* 3179 */ >+ IC_VEX_W_XD, /* 3180 */ >+ IC_VEX_W_XD, /* 3181 */ >+ IC_VEX_W_XD, /* 3182 */ >+ IC_VEX_W_XD, /* 3183 */ >+ IC_VEX_OPSIZE, /* 3184 */ >+ IC_VEX_OPSIZE, /* 3185 */ >+ IC_VEX_OPSIZE, /* 3186 */ >+ IC_VEX_OPSIZE, /* 3187 */ >+ IC_VEX_OPSIZE, /* 3188 */ >+ IC_VEX_OPSIZE, /* 3189 */ >+ IC_VEX_OPSIZE, /* 3190 */ >+ IC_VEX_OPSIZE, /* 3191 */ >+ IC_VEX_W_OPSIZE, /* 3192 */ >+ IC_VEX_W_OPSIZE, /* 3193 */ >+ IC_VEX_W_OPSIZE, /* 3194 */ >+ IC_VEX_W_OPSIZE, /* 3195 */ >+ IC_VEX_W_OPSIZE, /* 3196 */ >+ IC_VEX_W_OPSIZE, /* 3197 */ >+ IC_VEX_W_OPSIZE, /* 3198 */ >+ IC_VEX_W_OPSIZE, /* 3199 */ >+ IC_VEX_L, /* 3200 */ >+ IC_VEX_L, /* 3201 */ >+ IC_VEX_L_XS, /* 3202 */ >+ IC_VEX_L_XS, /* 3203 */ >+ IC_VEX_L_XD, /* 3204 */ >+ IC_VEX_L_XD, /* 3205 */ >+ IC_VEX_L_XD, /* 3206 */ >+ IC_VEX_L_XD, /* 3207 */ >+ IC_VEX_L_W, /* 3208 */ >+ IC_VEX_L_W, /* 3209 */ >+ IC_VEX_L_W_XS, /* 3210 */ >+ IC_VEX_L_W_XS, /* 3211 */ >+ IC_VEX_L_W_XD, /* 3212 */ >+ IC_VEX_L_W_XD, /* 3213 */ >+ IC_VEX_L_W_XD, /* 3214 */ >+ IC_VEX_L_W_XD, /* 3215 */ >+ IC_VEX_L_OPSIZE, /* 3216 */ >+ IC_VEX_L_OPSIZE, /* 3217 */ >+ IC_VEX_L_OPSIZE, /* 3218 */ >+ IC_VEX_L_OPSIZE, /* 3219 */ >+ IC_VEX_L_OPSIZE, /* 3220 */ >+ IC_VEX_L_OPSIZE, /* 3221 */ >+ IC_VEX_L_OPSIZE, /* 3222 */ >+ IC_VEX_L_OPSIZE, /* 3223 */ >+ IC_VEX_L_W_OPSIZE, /* 3224 */ >+ IC_VEX_L_W_OPSIZE, /* 3225 */ >+ IC_VEX_L_W_OPSIZE, /* 3226 */ >+ IC_VEX_L_W_OPSIZE, /* 3227 */ >+ IC_VEX_L_W_OPSIZE, /* 3228 */ >+ IC_VEX_L_W_OPSIZE, /* 3229 */ >+ IC_VEX_L_W_OPSIZE, /* 3230 */ >+ IC_VEX_L_W_OPSIZE, /* 3231 */ >+ IC_VEX_L, /* 3232 */ >+ IC_VEX_L, /* 3233 */ >+ IC_VEX_L_XS, /* 3234 */ >+ IC_VEX_L_XS, /* 3235 */ >+ IC_VEX_L_XD, /* 3236 */ >+ IC_VEX_L_XD, /* 3237 */ >+ IC_VEX_L_XD, /* 3238 */ >+ IC_VEX_L_XD, /* 3239 */ >+ IC_VEX_L_W, /* 3240 */ >+ IC_VEX_L_W, /* 3241 */ >+ IC_VEX_L_W_XS, /* 3242 */ >+ IC_VEX_L_W_XS, /* 3243 */ >+ IC_VEX_L_W_XD, /* 3244 */ >+ IC_VEX_L_W_XD, /* 3245 */ >+ IC_VEX_L_W_XD, /* 3246 */ >+ IC_VEX_L_W_XD, /* 3247 */ >+ IC_VEX_L_OPSIZE, /* 3248 */ >+ IC_VEX_L_OPSIZE, /* 3249 */ >+ IC_VEX_L_OPSIZE, /* 3250 */ >+ IC_VEX_L_OPSIZE, /* 3251 */ >+ IC_VEX_L_OPSIZE, /* 3252 */ >+ IC_VEX_L_OPSIZE, /* 3253 */ >+ IC_VEX_L_OPSIZE, /* 3254 */ >+ IC_VEX_L_OPSIZE, /* 3255 */ >+ IC_VEX_L_W_OPSIZE, /* 3256 */ >+ IC_VEX_L_W_OPSIZE, /* 3257 */ >+ IC_VEX_L_W_OPSIZE, /* 3258 */ >+ IC_VEX_L_W_OPSIZE, /* 3259 */ >+ IC_VEX_L_W_OPSIZE, /* 3260 */ >+ IC_VEX_L_W_OPSIZE, /* 3261 */ >+ IC_VEX_L_W_OPSIZE, /* 3262 */ >+ IC_VEX_L_W_OPSIZE, /* 3263 */ >+ IC_VEX_L, /* 3264 */ >+ IC_VEX_L, /* 3265 */ >+ IC_VEX_L_XS, /* 3266 */ >+ IC_VEX_L_XS, /* 3267 */ >+ IC_VEX_L_XD, /* 3268 */ >+ IC_VEX_L_XD, /* 3269 */ >+ IC_VEX_L_XD, /* 3270 */ >+ IC_VEX_L_XD, /* 3271 */ >+ IC_VEX_L_W, /* 3272 */ >+ IC_VEX_L_W, /* 3273 */ >+ IC_VEX_L_W_XS, /* 3274 */ >+ IC_VEX_L_W_XS, /* 3275 */ >+ IC_VEX_L_W_XD, /* 3276 */ >+ IC_VEX_L_W_XD, /* 3277 */ >+ IC_VEX_L_W_XD, /* 3278 */ >+ IC_VEX_L_W_XD, /* 3279 */ >+ IC_VEX_L_OPSIZE, /* 3280 */ >+ IC_VEX_L_OPSIZE, /* 3281 */ >+ IC_VEX_L_OPSIZE, /* 3282 */ >+ IC_VEX_L_OPSIZE, /* 3283 */ >+ IC_VEX_L_OPSIZE, /* 3284 */ >+ IC_VEX_L_OPSIZE, /* 3285 */ >+ IC_VEX_L_OPSIZE, /* 3286 */ >+ IC_VEX_L_OPSIZE, /* 3287 */ >+ IC_VEX_L_W_OPSIZE, /* 3288 */ >+ IC_VEX_L_W_OPSIZE, /* 3289 */ >+ IC_VEX_L_W_OPSIZE, /* 3290 */ >+ IC_VEX_L_W_OPSIZE, /* 3291 */ >+ IC_VEX_L_W_OPSIZE, /* 3292 */ >+ IC_VEX_L_W_OPSIZE, /* 3293 */ >+ IC_VEX_L_W_OPSIZE, /* 3294 */ >+ IC_VEX_L_W_OPSIZE, /* 3295 */ >+ IC_VEX_L, /* 3296 */ >+ IC_VEX_L, /* 3297 */ >+ IC_VEX_L_XS, /* 3298 */ >+ IC_VEX_L_XS, /* 3299 */ >+ IC_VEX_L_XD, /* 3300 */ >+ IC_VEX_L_XD, /* 3301 */ >+ IC_VEX_L_XD, /* 3302 */ >+ IC_VEX_L_XD, /* 3303 */ >+ IC_VEX_L_W, /* 3304 */ >+ IC_VEX_L_W, /* 3305 */ >+ IC_VEX_L_W_XS, /* 3306 */ >+ IC_VEX_L_W_XS, /* 3307 */ >+ IC_VEX_L_W_XD, /* 3308 */ >+ IC_VEX_L_W_XD, /* 3309 */ >+ IC_VEX_L_W_XD, /* 3310 */ >+ IC_VEX_L_W_XD, /* 3311 */ >+ IC_VEX_L_OPSIZE, /* 3312 */ >+ IC_VEX_L_OPSIZE, /* 3313 */ >+ IC_VEX_L_OPSIZE, /* 3314 */ >+ IC_VEX_L_OPSIZE, /* 3315 */ >+ IC_VEX_L_OPSIZE, /* 3316 */ >+ IC_VEX_L_OPSIZE, /* 3317 */ >+ IC_VEX_L_OPSIZE, /* 3318 */ >+ IC_VEX_L_OPSIZE, /* 3319 */ >+ IC_VEX_L_W_OPSIZE, /* 3320 */ >+ IC_VEX_L_W_OPSIZE, /* 3321 */ >+ IC_VEX_L_W_OPSIZE, /* 3322 */ >+ IC_VEX_L_W_OPSIZE, /* 3323 */ >+ IC_VEX_L_W_OPSIZE, /* 3324 */ >+ IC_VEX_L_W_OPSIZE, /* 3325 */ >+ IC_VEX_L_W_OPSIZE, /* 3326 */ >+ IC_VEX_L_W_OPSIZE, /* 3327 */ >+ IC_EVEX_L2_K, /* 3328 */ >+ IC_EVEX_L2_K, /* 3329 */ >+ IC_EVEX_L2_XS_K, /* 3330 */ >+ IC_EVEX_L2_XS_K, /* 3331 */ >+ IC_EVEX_L2_XD_K, /* 3332 */ >+ IC_EVEX_L2_XD_K, /* 3333 */ >+ IC_EVEX_L2_XD_K, /* 3334 */ >+ IC_EVEX_L2_XD_K, /* 3335 */ >+ IC_EVEX_L2_W_K, /* 3336 */ >+ IC_EVEX_L2_W_K, /* 3337 */ >+ IC_EVEX_L2_W_XS_K, /* 3338 */ >+ IC_EVEX_L2_W_XS_K, /* 3339 */ >+ IC_EVEX_L2_W_XD_K, /* 3340 */ >+ IC_EVEX_L2_W_XD_K, /* 3341 */ >+ IC_EVEX_L2_W_XD_K, /* 3342 */ >+ IC_EVEX_L2_W_XD_K, /* 3343 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3344 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3345 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3346 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3347 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3348 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3349 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3350 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3351 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3352 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3353 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3354 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3355 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3356 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3357 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3358 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3359 */ >+ IC_EVEX_L2_K, /* 3360 */ >+ IC_EVEX_L2_K, /* 3361 */ >+ IC_EVEX_L2_XS_K, /* 3362 */ >+ IC_EVEX_L2_XS_K, /* 3363 */ >+ IC_EVEX_L2_XD_K, /* 3364 */ >+ IC_EVEX_L2_XD_K, /* 3365 */ >+ IC_EVEX_L2_XD_K, /* 3366 */ >+ IC_EVEX_L2_XD_K, /* 3367 */ >+ IC_EVEX_L2_W_K, /* 3368 */ >+ IC_EVEX_L2_W_K, /* 3369 */ >+ IC_EVEX_L2_W_XS_K, /* 3370 */ >+ IC_EVEX_L2_W_XS_K, /* 3371 */ >+ IC_EVEX_L2_W_XD_K, /* 3372 */ >+ IC_EVEX_L2_W_XD_K, /* 3373 */ >+ IC_EVEX_L2_W_XD_K, /* 3374 */ >+ IC_EVEX_L2_W_XD_K, /* 3375 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3376 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3377 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3378 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3379 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3380 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3381 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3382 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3383 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3384 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3385 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3386 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3387 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3388 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3389 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3390 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3391 */ >+ IC_EVEX_L2_K, /* 3392 */ >+ IC_EVEX_L2_K, /* 3393 */ >+ IC_EVEX_L2_XS_K, /* 3394 */ >+ IC_EVEX_L2_XS_K, /* 3395 */ >+ IC_EVEX_L2_XD_K, /* 3396 */ >+ IC_EVEX_L2_XD_K, /* 3397 */ >+ IC_EVEX_L2_XD_K, /* 3398 */ >+ IC_EVEX_L2_XD_K, /* 3399 */ >+ IC_EVEX_L2_W_K, /* 3400 */ >+ IC_EVEX_L2_W_K, /* 3401 */ >+ IC_EVEX_L2_W_XS_K, /* 3402 */ >+ IC_EVEX_L2_W_XS_K, /* 3403 */ >+ IC_EVEX_L2_W_XD_K, /* 3404 */ >+ IC_EVEX_L2_W_XD_K, /* 3405 */ >+ IC_EVEX_L2_W_XD_K, /* 3406 */ >+ IC_EVEX_L2_W_XD_K, /* 3407 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3408 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3409 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3410 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3411 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3412 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3413 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3414 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3415 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3416 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3417 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3418 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3419 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3420 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3421 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3422 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3423 */ >+ IC_EVEX_L2_K, /* 3424 */ >+ IC_EVEX_L2_K, /* 3425 */ >+ IC_EVEX_L2_XS_K, /* 3426 */ >+ IC_EVEX_L2_XS_K, /* 3427 */ >+ IC_EVEX_L2_XD_K, /* 3428 */ >+ IC_EVEX_L2_XD_K, /* 3429 */ >+ IC_EVEX_L2_XD_K, /* 3430 */ >+ IC_EVEX_L2_XD_K, /* 3431 */ >+ IC_EVEX_L2_W_K, /* 3432 */ >+ IC_EVEX_L2_W_K, /* 3433 */ >+ IC_EVEX_L2_W_XS_K, /* 3434 */ >+ IC_EVEX_L2_W_XS_K, /* 3435 */ >+ IC_EVEX_L2_W_XD_K, /* 3436 */ >+ IC_EVEX_L2_W_XD_K, /* 3437 */ >+ IC_EVEX_L2_W_XD_K, /* 3438 */ >+ IC_EVEX_L2_W_XD_K, /* 3439 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3440 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3441 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3442 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3443 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3444 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3445 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3446 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3447 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3448 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3449 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3450 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3451 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3452 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3453 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3454 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3455 */ >+ IC_EVEX_L2_K, /* 3456 */ >+ IC_EVEX_L2_K, /* 3457 */ >+ IC_EVEX_L2_XS_K, /* 3458 */ >+ IC_EVEX_L2_XS_K, /* 3459 */ >+ IC_EVEX_L2_XD_K, /* 3460 */ >+ IC_EVEX_L2_XD_K, /* 3461 */ >+ IC_EVEX_L2_XD_K, /* 3462 */ >+ IC_EVEX_L2_XD_K, /* 3463 */ >+ IC_EVEX_L2_W_K, /* 3464 */ >+ IC_EVEX_L2_W_K, /* 3465 */ >+ IC_EVEX_L2_W_XS_K, /* 3466 */ >+ IC_EVEX_L2_W_XS_K, /* 3467 */ >+ IC_EVEX_L2_W_XD_K, /* 3468 */ >+ IC_EVEX_L2_W_XD_K, /* 3469 */ >+ IC_EVEX_L2_W_XD_K, /* 3470 */ >+ IC_EVEX_L2_W_XD_K, /* 3471 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3472 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3473 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3474 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3475 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3476 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3477 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3478 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3479 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3480 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3481 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3482 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3483 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3484 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3485 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3486 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3487 */ >+ IC_EVEX_L2_K, /* 3488 */ >+ IC_EVEX_L2_K, /* 3489 */ >+ IC_EVEX_L2_XS_K, /* 3490 */ >+ IC_EVEX_L2_XS_K, /* 3491 */ >+ IC_EVEX_L2_XD_K, /* 3492 */ >+ IC_EVEX_L2_XD_K, /* 3493 */ >+ IC_EVEX_L2_XD_K, /* 3494 */ >+ IC_EVEX_L2_XD_K, /* 3495 */ >+ IC_EVEX_L2_W_K, /* 3496 */ >+ IC_EVEX_L2_W_K, /* 3497 */ >+ IC_EVEX_L2_W_XS_K, /* 3498 */ >+ IC_EVEX_L2_W_XS_K, /* 3499 */ >+ IC_EVEX_L2_W_XD_K, /* 3500 */ >+ IC_EVEX_L2_W_XD_K, /* 3501 */ >+ IC_EVEX_L2_W_XD_K, /* 3502 */ >+ IC_EVEX_L2_W_XD_K, /* 3503 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3504 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3505 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3506 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3507 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3508 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3509 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3510 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3511 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3512 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3513 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3514 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3515 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3516 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3517 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3518 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3519 */ >+ IC_EVEX_L2_K, /* 3520 */ >+ IC_EVEX_L2_K, /* 3521 */ >+ IC_EVEX_L2_XS_K, /* 3522 */ >+ IC_EVEX_L2_XS_K, /* 3523 */ >+ IC_EVEX_L2_XD_K, /* 3524 */ >+ IC_EVEX_L2_XD_K, /* 3525 */ >+ IC_EVEX_L2_XD_K, /* 3526 */ >+ IC_EVEX_L2_XD_K, /* 3527 */ >+ IC_EVEX_L2_W_K, /* 3528 */ >+ IC_EVEX_L2_W_K, /* 3529 */ >+ IC_EVEX_L2_W_XS_K, /* 3530 */ >+ IC_EVEX_L2_W_XS_K, /* 3531 */ >+ IC_EVEX_L2_W_XD_K, /* 3532 */ >+ IC_EVEX_L2_W_XD_K, /* 3533 */ >+ IC_EVEX_L2_W_XD_K, /* 3534 */ >+ IC_EVEX_L2_W_XD_K, /* 3535 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3536 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3537 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3538 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3539 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3540 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3541 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3542 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3543 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3544 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3545 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3546 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3547 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3548 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3549 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3550 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3551 */ >+ IC_EVEX_L2_K, /* 3552 */ >+ IC_EVEX_L2_K, /* 3553 */ >+ IC_EVEX_L2_XS_K, /* 3554 */ >+ IC_EVEX_L2_XS_K, /* 3555 */ >+ IC_EVEX_L2_XD_K, /* 3556 */ >+ IC_EVEX_L2_XD_K, /* 3557 */ >+ IC_EVEX_L2_XD_K, /* 3558 */ >+ IC_EVEX_L2_XD_K, /* 3559 */ >+ IC_EVEX_L2_W_K, /* 3560 */ >+ IC_EVEX_L2_W_K, /* 3561 */ >+ IC_EVEX_L2_W_XS_K, /* 3562 */ >+ IC_EVEX_L2_W_XS_K, /* 3563 */ >+ IC_EVEX_L2_W_XD_K, /* 3564 */ >+ IC_EVEX_L2_W_XD_K, /* 3565 */ >+ IC_EVEX_L2_W_XD_K, /* 3566 */ >+ IC_EVEX_L2_W_XD_K, /* 3567 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3568 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3569 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3570 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3571 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3572 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3573 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3574 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3575 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3576 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3577 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3578 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3579 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3580 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3581 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3582 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3583 */ >+ IC, /* 3584 */ >+ IC_64BIT, /* 3585 */ >+ IC_XS, /* 3586 */ >+ IC_64BIT_XS, /* 3587 */ >+ IC_XD, /* 3588 */ >+ IC_64BIT_XD, /* 3589 */ >+ IC_XS, /* 3590 */ >+ IC_64BIT_XS, /* 3591 */ >+ IC, /* 3592 */ >+ IC_64BIT_REXW, /* 3593 */ >+ IC_XS, /* 3594 */ >+ IC_64BIT_REXW_XS, /* 3595 */ >+ IC_XD, /* 3596 */ >+ IC_64BIT_REXW_XD, /* 3597 */ >+ IC_XS, /* 3598 */ >+ IC_64BIT_REXW_XS, /* 3599 */ >+ IC_OPSIZE, /* 3600 */ >+ IC_64BIT_OPSIZE, /* 3601 */ >+ IC_XS_OPSIZE, /* 3602 */ >+ IC_64BIT_XS_OPSIZE, /* 3603 */ >+ IC_XD_OPSIZE, /* 3604 */ >+ IC_64BIT_XD_OPSIZE, /* 3605 */ >+ IC_XS_OPSIZE, /* 3606 */ >+ IC_64BIT_XD_OPSIZE, /* 3607 */ >+ IC_OPSIZE, /* 3608 */ >+ IC_64BIT_REXW_OPSIZE, /* 3609 */ >+ IC_XS_OPSIZE, /* 3610 */ >+ IC_64BIT_REXW_XS, /* 3611 */ >+ IC_XD_OPSIZE, /* 3612 */ >+ IC_64BIT_REXW_XD, /* 3613 */ >+ IC_XS_OPSIZE, /* 3614 */ >+ IC_64BIT_REXW_XS, /* 3615 */ >+ IC_ADSIZE, /* 3616 */ >+ IC_64BIT_ADSIZE, /* 3617 */ >+ IC_XS, /* 3618 */ >+ IC_64BIT_XS, /* 3619 */ >+ IC_XD, /* 3620 */ >+ IC_64BIT_XD, /* 3621 */ >+ IC_XS, /* 3622 */ >+ IC_64BIT_XS, /* 3623 */ >+ IC_ADSIZE, /* 3624 */ >+ IC_64BIT_ADSIZE, /* 3625 */ >+ IC_XS, /* 3626 */ >+ IC_64BIT_REXW_XS, /* 3627 */ >+ IC_XD, /* 3628 */ >+ IC_64BIT_REXW_XD, /* 3629 */ >+ IC_XS, /* 3630 */ >+ IC_64BIT_REXW_XS, /* 3631 */ >+ IC_OPSIZE, /* 3632 */ >+ IC_64BIT_OPSIZE, /* 3633 */ >+ IC_XS_OPSIZE, /* 3634 */ >+ IC_64BIT_XS_OPSIZE, /* 3635 */ >+ IC_XD_OPSIZE, /* 3636 */ >+ IC_64BIT_XD_OPSIZE, /* 3637 */ >+ IC_XS_OPSIZE, /* 3638 */ >+ IC_64BIT_XD_OPSIZE, /* 3639 */ >+ IC_OPSIZE, /* 3640 */ >+ IC_64BIT_REXW_OPSIZE, /* 3641 */ >+ IC_XS_OPSIZE, /* 3642 */ >+ IC_64BIT_REXW_XS, /* 3643 */ >+ IC_XD_OPSIZE, /* 3644 */ >+ IC_64BIT_REXW_XD, /* 3645 */ >+ IC_XS_OPSIZE, /* 3646 */ >+ IC_64BIT_REXW_XS, /* 3647 */ >+ IC_VEX, /* 3648 */ >+ IC_VEX, /* 3649 */ >+ IC_VEX_XS, /* 3650 */ >+ IC_VEX_XS, /* 3651 */ >+ IC_VEX_XD, /* 3652 */ >+ IC_VEX_XD, /* 3653 */ >+ IC_VEX_XD, /* 3654 */ >+ IC_VEX_XD, /* 3655 */ >+ IC_VEX_W, /* 3656 */ >+ IC_VEX_W, /* 3657 */ >+ IC_VEX_W_XS, /* 3658 */ >+ IC_VEX_W_XS, /* 3659 */ >+ IC_VEX_W_XD, /* 3660 */ >+ IC_VEX_W_XD, /* 3661 */ >+ IC_VEX_W_XD, /* 3662 */ >+ IC_VEX_W_XD, /* 3663 */ >+ IC_VEX_OPSIZE, /* 3664 */ >+ IC_VEX_OPSIZE, /* 3665 */ >+ IC_VEX_OPSIZE, /* 3666 */ >+ IC_VEX_OPSIZE, /* 3667 */ >+ IC_VEX_OPSIZE, /* 3668 */ >+ IC_VEX_OPSIZE, /* 3669 */ >+ IC_VEX_OPSIZE, /* 3670 */ >+ IC_VEX_OPSIZE, /* 3671 */ >+ IC_VEX_W_OPSIZE, /* 3672 */ >+ IC_VEX_W_OPSIZE, /* 3673 */ >+ IC_VEX_W_OPSIZE, /* 3674 */ >+ IC_VEX_W_OPSIZE, /* 3675 */ >+ IC_VEX_W_OPSIZE, /* 3676 */ >+ IC_VEX_W_OPSIZE, /* 3677 */ >+ IC_VEX_W_OPSIZE, /* 3678 */ >+ IC_VEX_W_OPSIZE, /* 3679 */ >+ IC_VEX, /* 3680 */ >+ IC_VEX, /* 3681 */ >+ IC_VEX_XS, /* 3682 */ >+ IC_VEX_XS, /* 3683 */ >+ IC_VEX_XD, /* 3684 */ >+ IC_VEX_XD, /* 3685 */ >+ IC_VEX_XD, /* 3686 */ >+ IC_VEX_XD, /* 3687 */ >+ IC_VEX_W, /* 3688 */ >+ IC_VEX_W, /* 3689 */ >+ IC_VEX_W_XS, /* 3690 */ >+ IC_VEX_W_XS, /* 3691 */ >+ IC_VEX_W_XD, /* 3692 */ >+ IC_VEX_W_XD, /* 3693 */ >+ IC_VEX_W_XD, /* 3694 */ >+ IC_VEX_W_XD, /* 3695 */ >+ IC_VEX_OPSIZE, /* 3696 */ >+ IC_VEX_OPSIZE, /* 3697 */ >+ IC_VEX_OPSIZE, /* 3698 */ >+ IC_VEX_OPSIZE, /* 3699 */ >+ IC_VEX_OPSIZE, /* 3700 */ >+ IC_VEX_OPSIZE, /* 3701 */ >+ IC_VEX_OPSIZE, /* 3702 */ >+ IC_VEX_OPSIZE, /* 3703 */ >+ IC_VEX_W_OPSIZE, /* 3704 */ >+ IC_VEX_W_OPSIZE, /* 3705 */ >+ IC_VEX_W_OPSIZE, /* 3706 */ >+ IC_VEX_W_OPSIZE, /* 3707 */ >+ IC_VEX_W_OPSIZE, /* 3708 */ >+ IC_VEX_W_OPSIZE, /* 3709 */ >+ IC_VEX_W_OPSIZE, /* 3710 */ >+ IC_VEX_W_OPSIZE, /* 3711 */ >+ IC_VEX_L, /* 3712 */ >+ IC_VEX_L, /* 3713 */ >+ IC_VEX_L_XS, /* 3714 */ >+ IC_VEX_L_XS, /* 3715 */ >+ IC_VEX_L_XD, /* 3716 */ >+ IC_VEX_L_XD, /* 3717 */ >+ IC_VEX_L_XD, /* 3718 */ >+ IC_VEX_L_XD, /* 3719 */ >+ IC_VEX_L_W, /* 3720 */ >+ IC_VEX_L_W, /* 3721 */ >+ IC_VEX_L_W_XS, /* 3722 */ >+ IC_VEX_L_W_XS, /* 3723 */ >+ IC_VEX_L_W_XD, /* 3724 */ >+ IC_VEX_L_W_XD, /* 3725 */ >+ IC_VEX_L_W_XD, /* 3726 */ >+ IC_VEX_L_W_XD, /* 3727 */ >+ IC_VEX_L_OPSIZE, /* 3728 */ >+ IC_VEX_L_OPSIZE, /* 3729 */ >+ IC_VEX_L_OPSIZE, /* 3730 */ >+ IC_VEX_L_OPSIZE, /* 3731 */ >+ IC_VEX_L_OPSIZE, /* 3732 */ >+ IC_VEX_L_OPSIZE, /* 3733 */ >+ IC_VEX_L_OPSIZE, /* 3734 */ >+ IC_VEX_L_OPSIZE, /* 3735 */ >+ IC_VEX_L_W_OPSIZE, /* 3736 */ >+ IC_VEX_L_W_OPSIZE, /* 3737 */ >+ IC_VEX_L_W_OPSIZE, /* 3738 */ >+ IC_VEX_L_W_OPSIZE, /* 3739 */ >+ IC_VEX_L_W_OPSIZE, /* 3740 */ >+ IC_VEX_L_W_OPSIZE, /* 3741 */ >+ IC_VEX_L_W_OPSIZE, /* 3742 */ >+ IC_VEX_L_W_OPSIZE, /* 3743 */ >+ IC_VEX_L, /* 3744 */ >+ IC_VEX_L, /* 3745 */ >+ IC_VEX_L_XS, /* 3746 */ >+ IC_VEX_L_XS, /* 3747 */ >+ IC_VEX_L_XD, /* 3748 */ >+ IC_VEX_L_XD, /* 3749 */ >+ IC_VEX_L_XD, /* 3750 */ >+ IC_VEX_L_XD, /* 3751 */ >+ IC_VEX_L_W, /* 3752 */ >+ IC_VEX_L_W, /* 3753 */ >+ IC_VEX_L_W_XS, /* 3754 */ >+ IC_VEX_L_W_XS, /* 3755 */ >+ IC_VEX_L_W_XD, /* 3756 */ >+ IC_VEX_L_W_XD, /* 3757 */ >+ IC_VEX_L_W_XD, /* 3758 */ >+ IC_VEX_L_W_XD, /* 3759 */ >+ IC_VEX_L_OPSIZE, /* 3760 */ >+ IC_VEX_L_OPSIZE, /* 3761 */ >+ IC_VEX_L_OPSIZE, /* 3762 */ >+ IC_VEX_L_OPSIZE, /* 3763 */ >+ IC_VEX_L_OPSIZE, /* 3764 */ >+ IC_VEX_L_OPSIZE, /* 3765 */ >+ IC_VEX_L_OPSIZE, /* 3766 */ >+ IC_VEX_L_OPSIZE, /* 3767 */ >+ IC_VEX_L_W_OPSIZE, /* 3768 */ >+ IC_VEX_L_W_OPSIZE, /* 3769 */ >+ IC_VEX_L_W_OPSIZE, /* 3770 */ >+ IC_VEX_L_W_OPSIZE, /* 3771 */ >+ IC_VEX_L_W_OPSIZE, /* 3772 */ >+ IC_VEX_L_W_OPSIZE, /* 3773 */ >+ IC_VEX_L_W_OPSIZE, /* 3774 */ >+ IC_VEX_L_W_OPSIZE, /* 3775 */ >+ IC_VEX_L, /* 3776 */ >+ IC_VEX_L, /* 3777 */ >+ IC_VEX_L_XS, /* 3778 */ >+ IC_VEX_L_XS, /* 3779 */ >+ IC_VEX_L_XD, /* 3780 */ >+ IC_VEX_L_XD, /* 3781 */ >+ IC_VEX_L_XD, /* 3782 */ >+ IC_VEX_L_XD, /* 3783 */ >+ IC_VEX_L_W, /* 3784 */ >+ IC_VEX_L_W, /* 3785 */ >+ IC_VEX_L_W_XS, /* 3786 */ >+ IC_VEX_L_W_XS, /* 3787 */ >+ IC_VEX_L_W_XD, /* 3788 */ >+ IC_VEX_L_W_XD, /* 3789 */ >+ IC_VEX_L_W_XD, /* 3790 */ >+ IC_VEX_L_W_XD, /* 3791 */ >+ IC_VEX_L_OPSIZE, /* 3792 */ >+ IC_VEX_L_OPSIZE, /* 3793 */ >+ IC_VEX_L_OPSIZE, /* 3794 */ >+ IC_VEX_L_OPSIZE, /* 3795 */ >+ IC_VEX_L_OPSIZE, /* 3796 */ >+ IC_VEX_L_OPSIZE, /* 3797 */ >+ IC_VEX_L_OPSIZE, /* 3798 */ >+ IC_VEX_L_OPSIZE, /* 3799 */ >+ IC_VEX_L_W_OPSIZE, /* 3800 */ >+ IC_VEX_L_W_OPSIZE, /* 3801 */ >+ IC_VEX_L_W_OPSIZE, /* 3802 */ >+ IC_VEX_L_W_OPSIZE, /* 3803 */ >+ IC_VEX_L_W_OPSIZE, /* 3804 */ >+ IC_VEX_L_W_OPSIZE, /* 3805 */ >+ IC_VEX_L_W_OPSIZE, /* 3806 */ >+ IC_VEX_L_W_OPSIZE, /* 3807 */ >+ IC_VEX_L, /* 3808 */ >+ IC_VEX_L, /* 3809 */ >+ IC_VEX_L_XS, /* 3810 */ >+ IC_VEX_L_XS, /* 3811 */ >+ IC_VEX_L_XD, /* 3812 */ >+ IC_VEX_L_XD, /* 3813 */ >+ IC_VEX_L_XD, /* 3814 */ >+ IC_VEX_L_XD, /* 3815 */ >+ IC_VEX_L_W, /* 3816 */ >+ IC_VEX_L_W, /* 3817 */ >+ IC_VEX_L_W_XS, /* 3818 */ >+ IC_VEX_L_W_XS, /* 3819 */ >+ IC_VEX_L_W_XD, /* 3820 */ >+ IC_VEX_L_W_XD, /* 3821 */ >+ IC_VEX_L_W_XD, /* 3822 */ >+ IC_VEX_L_W_XD, /* 3823 */ >+ IC_VEX_L_OPSIZE, /* 3824 */ >+ IC_VEX_L_OPSIZE, /* 3825 */ >+ IC_VEX_L_OPSIZE, /* 3826 */ >+ IC_VEX_L_OPSIZE, /* 3827 */ >+ IC_VEX_L_OPSIZE, /* 3828 */ >+ IC_VEX_L_OPSIZE, /* 3829 */ >+ IC_VEX_L_OPSIZE, /* 3830 */ >+ IC_VEX_L_OPSIZE, /* 3831 */ >+ IC_VEX_L_W_OPSIZE, /* 3832 */ >+ IC_VEX_L_W_OPSIZE, /* 3833 */ >+ IC_VEX_L_W_OPSIZE, /* 3834 */ >+ IC_VEX_L_W_OPSIZE, /* 3835 */ >+ IC_VEX_L_W_OPSIZE, /* 3836 */ >+ IC_VEX_L_W_OPSIZE, /* 3837 */ >+ IC_VEX_L_W_OPSIZE, /* 3838 */ >+ IC_VEX_L_W_OPSIZE, /* 3839 */ >+ IC_EVEX_L2_K, /* 3840 */ >+ IC_EVEX_L2_K, /* 3841 */ >+ IC_EVEX_L2_XS_K, /* 3842 */ >+ IC_EVEX_L2_XS_K, /* 3843 */ >+ IC_EVEX_L2_XD_K, /* 3844 */ >+ IC_EVEX_L2_XD_K, /* 3845 */ >+ IC_EVEX_L2_XD_K, /* 3846 */ >+ IC_EVEX_L2_XD_K, /* 3847 */ >+ IC_EVEX_L2_W_K, /* 3848 */ >+ IC_EVEX_L2_W_K, /* 3849 */ >+ IC_EVEX_L2_W_XS_K, /* 3850 */ >+ IC_EVEX_L2_W_XS_K, /* 3851 */ >+ IC_EVEX_L2_W_XD_K, /* 3852 */ >+ IC_EVEX_L2_W_XD_K, /* 3853 */ >+ IC_EVEX_L2_W_XD_K, /* 3854 */ >+ IC_EVEX_L2_W_XD_K, /* 3855 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3856 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3857 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3858 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3859 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3860 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3861 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3862 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3863 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3864 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3865 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3866 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3867 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3868 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3869 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3870 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3871 */ >+ IC_EVEX_L2_K, /* 3872 */ >+ IC_EVEX_L2_K, /* 3873 */ >+ IC_EVEX_L2_XS_K, /* 3874 */ >+ IC_EVEX_L2_XS_K, /* 3875 */ >+ IC_EVEX_L2_XD_K, /* 3876 */ >+ IC_EVEX_L2_XD_K, /* 3877 */ >+ IC_EVEX_L2_XD_K, /* 3878 */ >+ IC_EVEX_L2_XD_K, /* 3879 */ >+ IC_EVEX_L2_W_K, /* 3880 */ >+ IC_EVEX_L2_W_K, /* 3881 */ >+ IC_EVEX_L2_W_XS_K, /* 3882 */ >+ IC_EVEX_L2_W_XS_K, /* 3883 */ >+ IC_EVEX_L2_W_XD_K, /* 3884 */ >+ IC_EVEX_L2_W_XD_K, /* 3885 */ >+ IC_EVEX_L2_W_XD_K, /* 3886 */ >+ IC_EVEX_L2_W_XD_K, /* 3887 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3888 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3889 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3890 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3891 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3892 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3893 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3894 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3895 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3896 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3897 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3898 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3899 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3900 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3901 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3902 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3903 */ >+ IC_EVEX_L2_K, /* 3904 */ >+ IC_EVEX_L2_K, /* 3905 */ >+ IC_EVEX_L2_XS_K, /* 3906 */ >+ IC_EVEX_L2_XS_K, /* 3907 */ >+ IC_EVEX_L2_XD_K, /* 3908 */ >+ IC_EVEX_L2_XD_K, /* 3909 */ >+ IC_EVEX_L2_XD_K, /* 3910 */ >+ IC_EVEX_L2_XD_K, /* 3911 */ >+ IC_EVEX_L2_W_K, /* 3912 */ >+ IC_EVEX_L2_W_K, /* 3913 */ >+ IC_EVEX_L2_W_XS_K, /* 3914 */ >+ IC_EVEX_L2_W_XS_K, /* 3915 */ >+ IC_EVEX_L2_W_XD_K, /* 3916 */ >+ IC_EVEX_L2_W_XD_K, /* 3917 */ >+ IC_EVEX_L2_W_XD_K, /* 3918 */ >+ IC_EVEX_L2_W_XD_K, /* 3919 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3920 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3921 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3922 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3923 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3924 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3925 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3926 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3927 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3928 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3929 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3930 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3931 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3932 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3933 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3934 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3935 */ >+ IC_EVEX_L2_K, /* 3936 */ >+ IC_EVEX_L2_K, /* 3937 */ >+ IC_EVEX_L2_XS_K, /* 3938 */ >+ IC_EVEX_L2_XS_K, /* 3939 */ >+ IC_EVEX_L2_XD_K, /* 3940 */ >+ IC_EVEX_L2_XD_K, /* 3941 */ >+ IC_EVEX_L2_XD_K, /* 3942 */ >+ IC_EVEX_L2_XD_K, /* 3943 */ >+ IC_EVEX_L2_W_K, /* 3944 */ >+ IC_EVEX_L2_W_K, /* 3945 */ >+ IC_EVEX_L2_W_XS_K, /* 3946 */ >+ IC_EVEX_L2_W_XS_K, /* 3947 */ >+ IC_EVEX_L2_W_XD_K, /* 3948 */ >+ IC_EVEX_L2_W_XD_K, /* 3949 */ >+ IC_EVEX_L2_W_XD_K, /* 3950 */ >+ IC_EVEX_L2_W_XD_K, /* 3951 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3952 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3953 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3954 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3955 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3956 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3957 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3958 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3959 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3960 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3961 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3962 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3963 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3964 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3965 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3966 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3967 */ >+ IC_EVEX_L2_K, /* 3968 */ >+ IC_EVEX_L2_K, /* 3969 */ >+ IC_EVEX_L2_XS_K, /* 3970 */ >+ IC_EVEX_L2_XS_K, /* 3971 */ >+ IC_EVEX_L2_XD_K, /* 3972 */ >+ IC_EVEX_L2_XD_K, /* 3973 */ >+ IC_EVEX_L2_XD_K, /* 3974 */ >+ IC_EVEX_L2_XD_K, /* 3975 */ >+ IC_EVEX_L2_W_K, /* 3976 */ >+ IC_EVEX_L2_W_K, /* 3977 */ >+ IC_EVEX_L2_W_XS_K, /* 3978 */ >+ IC_EVEX_L2_W_XS_K, /* 3979 */ >+ IC_EVEX_L2_W_XD_K, /* 3980 */ >+ IC_EVEX_L2_W_XD_K, /* 3981 */ >+ IC_EVEX_L2_W_XD_K, /* 3982 */ >+ IC_EVEX_L2_W_XD_K, /* 3983 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3984 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3985 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3986 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3987 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3988 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3989 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3990 */ >+ IC_EVEX_L2_OPSIZE_K, /* 3991 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3992 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3993 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3994 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3995 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3996 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3997 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3998 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 3999 */ >+ IC_EVEX_L2_K, /* 4000 */ >+ IC_EVEX_L2_K, /* 4001 */ >+ IC_EVEX_L2_XS_K, /* 4002 */ >+ IC_EVEX_L2_XS_K, /* 4003 */ >+ IC_EVEX_L2_XD_K, /* 4004 */ >+ IC_EVEX_L2_XD_K, /* 4005 */ >+ IC_EVEX_L2_XD_K, /* 4006 */ >+ IC_EVEX_L2_XD_K, /* 4007 */ >+ IC_EVEX_L2_W_K, /* 4008 */ >+ IC_EVEX_L2_W_K, /* 4009 */ >+ IC_EVEX_L2_W_XS_K, /* 4010 */ >+ IC_EVEX_L2_W_XS_K, /* 4011 */ >+ IC_EVEX_L2_W_XD_K, /* 4012 */ >+ IC_EVEX_L2_W_XD_K, /* 4013 */ >+ IC_EVEX_L2_W_XD_K, /* 4014 */ >+ IC_EVEX_L2_W_XD_K, /* 4015 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4016 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4017 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4018 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4019 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4020 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4021 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4022 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4023 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4024 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4025 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4026 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4027 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4028 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4029 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4030 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4031 */ >+ IC_EVEX_L2_K, /* 4032 */ >+ IC_EVEX_L2_K, /* 4033 */ >+ IC_EVEX_L2_XS_K, /* 4034 */ >+ IC_EVEX_L2_XS_K, /* 4035 */ >+ IC_EVEX_L2_XD_K, /* 4036 */ >+ IC_EVEX_L2_XD_K, /* 4037 */ >+ IC_EVEX_L2_XD_K, /* 4038 */ >+ IC_EVEX_L2_XD_K, /* 4039 */ >+ IC_EVEX_L2_W_K, /* 4040 */ >+ IC_EVEX_L2_W_K, /* 4041 */ >+ IC_EVEX_L2_W_XS_K, /* 4042 */ >+ IC_EVEX_L2_W_XS_K, /* 4043 */ >+ IC_EVEX_L2_W_XD_K, /* 4044 */ >+ IC_EVEX_L2_W_XD_K, /* 4045 */ >+ IC_EVEX_L2_W_XD_K, /* 4046 */ >+ IC_EVEX_L2_W_XD_K, /* 4047 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4048 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4049 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4050 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4051 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4052 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4053 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4054 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4055 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4056 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4057 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4058 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4059 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4060 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4061 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4062 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4063 */ >+ IC_EVEX_L2_K, /* 4064 */ >+ IC_EVEX_L2_K, /* 4065 */ >+ IC_EVEX_L2_XS_K, /* 4066 */ >+ IC_EVEX_L2_XS_K, /* 4067 */ >+ IC_EVEX_L2_XD_K, /* 4068 */ >+ IC_EVEX_L2_XD_K, /* 4069 */ >+ IC_EVEX_L2_XD_K, /* 4070 */ >+ IC_EVEX_L2_XD_K, /* 4071 */ >+ IC_EVEX_L2_W_K, /* 4072 */ >+ IC_EVEX_L2_W_K, /* 4073 */ >+ IC_EVEX_L2_W_XS_K, /* 4074 */ >+ IC_EVEX_L2_W_XS_K, /* 4075 */ >+ IC_EVEX_L2_W_XD_K, /* 4076 */ >+ IC_EVEX_L2_W_XD_K, /* 4077 */ >+ IC_EVEX_L2_W_XD_K, /* 4078 */ >+ IC_EVEX_L2_W_XD_K, /* 4079 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4080 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4081 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4082 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4083 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4084 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4085 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4086 */ >+ IC_EVEX_L2_OPSIZE_K, /* 4087 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4088 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4089 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4090 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4091 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4092 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4093 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4094 */ >+ IC_EVEX_L2_W_OPSIZE_K, /* 4095 */ >+ IC, /* 4096 */ >+ IC_64BIT, /* 4097 */ >+ IC_XS, /* 4098 */ >+ IC_64BIT_XS, /* 4099 */ >+ IC_XD, /* 4100 */ >+ IC_64BIT_XD, /* 4101 */ >+ IC_XS, /* 4102 */ >+ IC_64BIT_XS, /* 4103 */ >+ IC, /* 4104 */ >+ IC_64BIT_REXW, /* 4105 */ >+ IC_XS, /* 4106 */ >+ IC_64BIT_REXW_XS, /* 4107 */ >+ IC_XD, /* 4108 */ >+ IC_64BIT_REXW_XD, /* 4109 */ >+ IC_XS, /* 4110 */ >+ IC_64BIT_REXW_XS, /* 4111 */ >+ IC_OPSIZE, /* 4112 */ >+ IC_64BIT_OPSIZE, /* 4113 */ >+ IC_XS_OPSIZE, /* 4114 */ >+ IC_64BIT_XS_OPSIZE, /* 4115 */ >+ IC_XD_OPSIZE, /* 4116 */ >+ IC_64BIT_XD_OPSIZE, /* 4117 */ >+ IC_XS_OPSIZE, /* 4118 */ >+ IC_64BIT_XD_OPSIZE, /* 4119 */ >+ IC_OPSIZE, /* 4120 */ >+ IC_64BIT_REXW_OPSIZE, /* 4121 */ >+ IC_XS_OPSIZE, /* 4122 */ >+ IC_64BIT_REXW_XS, /* 4123 */ >+ IC_XD_OPSIZE, /* 4124 */ >+ IC_64BIT_REXW_XD, /* 4125 */ >+ IC_XS_OPSIZE, /* 4126 */ >+ IC_64BIT_REXW_XS, /* 4127 */ >+ IC_ADSIZE, /* 4128 */ >+ IC_64BIT_ADSIZE, /* 4129 */ >+ IC_XS, /* 4130 */ >+ IC_64BIT_XS, /* 4131 */ >+ IC_XD, /* 4132 */ >+ IC_64BIT_XD, /* 4133 */ >+ IC_XS, /* 4134 */ >+ IC_64BIT_XS, /* 4135 */ >+ IC_ADSIZE, /* 4136 */ >+ IC_64BIT_ADSIZE, /* 4137 */ >+ IC_XS, /* 4138 */ >+ IC_64BIT_REXW_XS, /* 4139 */ >+ IC_XD, /* 4140 */ >+ IC_64BIT_REXW_XD, /* 4141 */ >+ IC_XS, /* 4142 */ >+ IC_64BIT_REXW_XS, /* 4143 */ >+ IC_OPSIZE, /* 4144 */ >+ IC_64BIT_OPSIZE, /* 4145 */ >+ IC_XS_OPSIZE, /* 4146 */ >+ IC_64BIT_XS_OPSIZE, /* 4147 */ >+ IC_XD_OPSIZE, /* 4148 */ >+ IC_64BIT_XD_OPSIZE, /* 4149 */ >+ IC_XS_OPSIZE, /* 4150 */ >+ IC_64BIT_XD_OPSIZE, /* 4151 */ >+ IC_OPSIZE, /* 4152 */ >+ IC_64BIT_REXW_OPSIZE, /* 4153 */ >+ IC_XS_OPSIZE, /* 4154 */ >+ IC_64BIT_REXW_XS, /* 4155 */ >+ IC_XD_OPSIZE, /* 4156 */ >+ IC_64BIT_REXW_XD, /* 4157 */ >+ IC_XS_OPSIZE, /* 4158 */ >+ IC_64BIT_REXW_XS, /* 4159 */ >+ IC_VEX, /* 4160 */ >+ IC_VEX, /* 4161 */ >+ IC_VEX_XS, /* 4162 */ >+ IC_VEX_XS, /* 4163 */ >+ IC_VEX_XD, /* 4164 */ >+ IC_VEX_XD, /* 4165 */ >+ IC_VEX_XD, /* 4166 */ >+ IC_VEX_XD, /* 4167 */ >+ IC_VEX_W, /* 4168 */ >+ IC_VEX_W, /* 4169 */ >+ IC_VEX_W_XS, /* 4170 */ >+ IC_VEX_W_XS, /* 4171 */ >+ IC_VEX_W_XD, /* 4172 */ >+ IC_VEX_W_XD, /* 4173 */ >+ IC_VEX_W_XD, /* 4174 */ >+ IC_VEX_W_XD, /* 4175 */ >+ IC_VEX_OPSIZE, /* 4176 */ >+ IC_VEX_OPSIZE, /* 4177 */ >+ IC_VEX_OPSIZE, /* 4178 */ >+ IC_VEX_OPSIZE, /* 4179 */ >+ IC_VEX_OPSIZE, /* 4180 */ >+ IC_VEX_OPSIZE, /* 4181 */ >+ IC_VEX_OPSIZE, /* 4182 */ >+ IC_VEX_OPSIZE, /* 4183 */ >+ IC_VEX_W_OPSIZE, /* 4184 */ >+ IC_VEX_W_OPSIZE, /* 4185 */ >+ IC_VEX_W_OPSIZE, /* 4186 */ >+ IC_VEX_W_OPSIZE, /* 4187 */ >+ IC_VEX_W_OPSIZE, /* 4188 */ >+ IC_VEX_W_OPSIZE, /* 4189 */ >+ IC_VEX_W_OPSIZE, /* 4190 */ >+ IC_VEX_W_OPSIZE, /* 4191 */ >+ IC_VEX, /* 4192 */ >+ IC_VEX, /* 4193 */ >+ IC_VEX_XS, /* 4194 */ >+ IC_VEX_XS, /* 4195 */ >+ IC_VEX_XD, /* 4196 */ >+ IC_VEX_XD, /* 4197 */ >+ IC_VEX_XD, /* 4198 */ >+ IC_VEX_XD, /* 4199 */ >+ IC_VEX_W, /* 4200 */ >+ IC_VEX_W, /* 4201 */ >+ IC_VEX_W_XS, /* 4202 */ >+ IC_VEX_W_XS, /* 4203 */ >+ IC_VEX_W_XD, /* 4204 */ >+ IC_VEX_W_XD, /* 4205 */ >+ IC_VEX_W_XD, /* 4206 */ >+ IC_VEX_W_XD, /* 4207 */ >+ IC_VEX_OPSIZE, /* 4208 */ >+ IC_VEX_OPSIZE, /* 4209 */ >+ IC_VEX_OPSIZE, /* 4210 */ >+ IC_VEX_OPSIZE, /* 4211 */ >+ IC_VEX_OPSIZE, /* 4212 */ >+ IC_VEX_OPSIZE, /* 4213 */ >+ IC_VEX_OPSIZE, /* 4214 */ >+ IC_VEX_OPSIZE, /* 4215 */ >+ IC_VEX_W_OPSIZE, /* 4216 */ >+ IC_VEX_W_OPSIZE, /* 4217 */ >+ IC_VEX_W_OPSIZE, /* 4218 */ >+ IC_VEX_W_OPSIZE, /* 4219 */ >+ IC_VEX_W_OPSIZE, /* 4220 */ >+ IC_VEX_W_OPSIZE, /* 4221 */ >+ IC_VEX_W_OPSIZE, /* 4222 */ >+ IC_VEX_W_OPSIZE, /* 4223 */ >+ IC_VEX_L, /* 4224 */ >+ IC_VEX_L, /* 4225 */ >+ IC_VEX_L_XS, /* 4226 */ >+ IC_VEX_L_XS, /* 4227 */ >+ IC_VEX_L_XD, /* 4228 */ >+ IC_VEX_L_XD, /* 4229 */ >+ IC_VEX_L_XD, /* 4230 */ >+ IC_VEX_L_XD, /* 4231 */ >+ IC_VEX_L_W, /* 4232 */ >+ IC_VEX_L_W, /* 4233 */ >+ IC_VEX_L_W_XS, /* 4234 */ >+ IC_VEX_L_W_XS, /* 4235 */ >+ IC_VEX_L_W_XD, /* 4236 */ >+ IC_VEX_L_W_XD, /* 4237 */ >+ IC_VEX_L_W_XD, /* 4238 */ >+ IC_VEX_L_W_XD, /* 4239 */ >+ IC_VEX_L_OPSIZE, /* 4240 */ >+ IC_VEX_L_OPSIZE, /* 4241 */ >+ IC_VEX_L_OPSIZE, /* 4242 */ >+ IC_VEX_L_OPSIZE, /* 4243 */ >+ IC_VEX_L_OPSIZE, /* 4244 */ >+ IC_VEX_L_OPSIZE, /* 4245 */ >+ IC_VEX_L_OPSIZE, /* 4246 */ >+ IC_VEX_L_OPSIZE, /* 4247 */ >+ IC_VEX_L_W_OPSIZE, /* 4248 */ >+ IC_VEX_L_W_OPSIZE, /* 4249 */ >+ IC_VEX_L_W_OPSIZE, /* 4250 */ >+ IC_VEX_L_W_OPSIZE, /* 4251 */ >+ IC_VEX_L_W_OPSIZE, /* 4252 */ >+ IC_VEX_L_W_OPSIZE, /* 4253 */ >+ IC_VEX_L_W_OPSIZE, /* 4254 */ >+ IC_VEX_L_W_OPSIZE, /* 4255 */ >+ IC_VEX_L, /* 4256 */ >+ IC_VEX_L, /* 4257 */ >+ IC_VEX_L_XS, /* 4258 */ >+ IC_VEX_L_XS, /* 4259 */ >+ IC_VEX_L_XD, /* 4260 */ >+ IC_VEX_L_XD, /* 4261 */ >+ IC_VEX_L_XD, /* 4262 */ >+ IC_VEX_L_XD, /* 4263 */ >+ IC_VEX_L_W, /* 4264 */ >+ IC_VEX_L_W, /* 4265 */ >+ IC_VEX_L_W_XS, /* 4266 */ >+ IC_VEX_L_W_XS, /* 4267 */ >+ IC_VEX_L_W_XD, /* 4268 */ >+ IC_VEX_L_W_XD, /* 4269 */ >+ IC_VEX_L_W_XD, /* 4270 */ >+ IC_VEX_L_W_XD, /* 4271 */ >+ IC_VEX_L_OPSIZE, /* 4272 */ >+ IC_VEX_L_OPSIZE, /* 4273 */ >+ IC_VEX_L_OPSIZE, /* 4274 */ >+ IC_VEX_L_OPSIZE, /* 4275 */ >+ IC_VEX_L_OPSIZE, /* 4276 */ >+ IC_VEX_L_OPSIZE, /* 4277 */ >+ IC_VEX_L_OPSIZE, /* 4278 */ >+ IC_VEX_L_OPSIZE, /* 4279 */ >+ IC_VEX_L_W_OPSIZE, /* 4280 */ >+ IC_VEX_L_W_OPSIZE, /* 4281 */ >+ IC_VEX_L_W_OPSIZE, /* 4282 */ >+ IC_VEX_L_W_OPSIZE, /* 4283 */ >+ IC_VEX_L_W_OPSIZE, /* 4284 */ >+ IC_VEX_L_W_OPSIZE, /* 4285 */ >+ IC_VEX_L_W_OPSIZE, /* 4286 */ >+ IC_VEX_L_W_OPSIZE, /* 4287 */ >+ IC_VEX_L, /* 4288 */ >+ IC_VEX_L, /* 4289 */ >+ IC_VEX_L_XS, /* 4290 */ >+ IC_VEX_L_XS, /* 4291 */ >+ IC_VEX_L_XD, /* 4292 */ >+ IC_VEX_L_XD, /* 4293 */ >+ IC_VEX_L_XD, /* 4294 */ >+ IC_VEX_L_XD, /* 4295 */ >+ IC_VEX_L_W, /* 4296 */ >+ IC_VEX_L_W, /* 4297 */ >+ IC_VEX_L_W_XS, /* 4298 */ >+ IC_VEX_L_W_XS, /* 4299 */ >+ IC_VEX_L_W_XD, /* 4300 */ >+ IC_VEX_L_W_XD, /* 4301 */ >+ IC_VEX_L_W_XD, /* 4302 */ >+ IC_VEX_L_W_XD, /* 4303 */ >+ IC_VEX_L_OPSIZE, /* 4304 */ >+ IC_VEX_L_OPSIZE, /* 4305 */ >+ IC_VEX_L_OPSIZE, /* 4306 */ >+ IC_VEX_L_OPSIZE, /* 4307 */ >+ IC_VEX_L_OPSIZE, /* 4308 */ >+ IC_VEX_L_OPSIZE, /* 4309 */ >+ IC_VEX_L_OPSIZE, /* 4310 */ >+ IC_VEX_L_OPSIZE, /* 4311 */ >+ IC_VEX_L_W_OPSIZE, /* 4312 */ >+ IC_VEX_L_W_OPSIZE, /* 4313 */ >+ IC_VEX_L_W_OPSIZE, /* 4314 */ >+ IC_VEX_L_W_OPSIZE, /* 4315 */ >+ IC_VEX_L_W_OPSIZE, /* 4316 */ >+ IC_VEX_L_W_OPSIZE, /* 4317 */ >+ IC_VEX_L_W_OPSIZE, /* 4318 */ >+ IC_VEX_L_W_OPSIZE, /* 4319 */ >+ IC_VEX_L, /* 4320 */ >+ IC_VEX_L, /* 4321 */ >+ IC_VEX_L_XS, /* 4322 */ >+ IC_VEX_L_XS, /* 4323 */ >+ IC_VEX_L_XD, /* 4324 */ >+ IC_VEX_L_XD, /* 4325 */ >+ IC_VEX_L_XD, /* 4326 */ >+ IC_VEX_L_XD, /* 4327 */ >+ IC_VEX_L_W, /* 4328 */ >+ IC_VEX_L_W, /* 4329 */ >+ IC_VEX_L_W_XS, /* 4330 */ >+ IC_VEX_L_W_XS, /* 4331 */ >+ IC_VEX_L_W_XD, /* 4332 */ >+ IC_VEX_L_W_XD, /* 4333 */ >+ IC_VEX_L_W_XD, /* 4334 */ >+ IC_VEX_L_W_XD, /* 4335 */ >+ IC_VEX_L_OPSIZE, /* 4336 */ >+ IC_VEX_L_OPSIZE, /* 4337 */ >+ IC_VEX_L_OPSIZE, /* 4338 */ >+ IC_VEX_L_OPSIZE, /* 4339 */ >+ IC_VEX_L_OPSIZE, /* 4340 */ >+ IC_VEX_L_OPSIZE, /* 4341 */ >+ IC_VEX_L_OPSIZE, /* 4342 */ >+ IC_VEX_L_OPSIZE, /* 4343 */ >+ IC_VEX_L_W_OPSIZE, /* 4344 */ >+ IC_VEX_L_W_OPSIZE, /* 4345 */ >+ IC_VEX_L_W_OPSIZE, /* 4346 */ >+ IC_VEX_L_W_OPSIZE, /* 4347 */ >+ IC_VEX_L_W_OPSIZE, /* 4348 */ >+ IC_VEX_L_W_OPSIZE, /* 4349 */ >+ IC_VEX_L_W_OPSIZE, /* 4350 */ >+ IC_VEX_L_W_OPSIZE, /* 4351 */ >+ IC_EVEX_KZ, /* 4352 */ >+ IC_EVEX_KZ, /* 4353 */ >+ IC_EVEX_XS_KZ, /* 4354 */ >+ IC_EVEX_XS_KZ, /* 4355 */ >+ IC_EVEX_XD_KZ, /* 4356 */ >+ IC_EVEX_XD_KZ, /* 4357 */ >+ IC_EVEX_XD_KZ, /* 4358 */ >+ IC_EVEX_XD_KZ, /* 4359 */ >+ IC_EVEX_W_KZ, /* 4360 */ >+ IC_EVEX_W_KZ, /* 4361 */ >+ IC_EVEX_W_XS_KZ, /* 4362 */ >+ IC_EVEX_W_XS_KZ, /* 4363 */ >+ IC_EVEX_W_XD_KZ, /* 4364 */ >+ IC_EVEX_W_XD_KZ, /* 4365 */ >+ IC_EVEX_W_XD_KZ, /* 4366 */ >+ IC_EVEX_W_XD_KZ, /* 4367 */ >+ IC_EVEX_OPSIZE_KZ, /* 4368 */ >+ IC_EVEX_OPSIZE_KZ, /* 4369 */ >+ IC_EVEX_OPSIZE_KZ, /* 4370 */ >+ IC_EVEX_OPSIZE_KZ, /* 4371 */ >+ IC_EVEX_OPSIZE_KZ, /* 4372 */ >+ IC_EVEX_OPSIZE_KZ, /* 4373 */ >+ IC_EVEX_OPSIZE_KZ, /* 4374 */ >+ IC_EVEX_OPSIZE_KZ, /* 4375 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4376 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4377 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4378 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4379 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4380 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4381 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4382 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4383 */ >+ IC_EVEX_KZ, /* 4384 */ >+ IC_EVEX_KZ, /* 4385 */ >+ IC_EVEX_XS_KZ, /* 4386 */ >+ IC_EVEX_XS_KZ, /* 4387 */ >+ IC_EVEX_XD_KZ, /* 4388 */ >+ IC_EVEX_XD_KZ, /* 4389 */ >+ IC_EVEX_XD_KZ, /* 4390 */ >+ IC_EVEX_XD_KZ, /* 4391 */ >+ IC_EVEX_W_KZ, /* 4392 */ >+ IC_EVEX_W_KZ, /* 4393 */ >+ IC_EVEX_W_XS_KZ, /* 4394 */ >+ IC_EVEX_W_XS_KZ, /* 4395 */ >+ IC_EVEX_W_XD_KZ, /* 4396 */ >+ IC_EVEX_W_XD_KZ, /* 4397 */ >+ IC_EVEX_W_XD_KZ, /* 4398 */ >+ IC_EVEX_W_XD_KZ, /* 4399 */ >+ IC_EVEX_OPSIZE_KZ, /* 4400 */ >+ IC_EVEX_OPSIZE_KZ, /* 4401 */ >+ IC_EVEX_OPSIZE_KZ, /* 4402 */ >+ IC_EVEX_OPSIZE_KZ, /* 4403 */ >+ IC_EVEX_OPSIZE_KZ, /* 4404 */ >+ IC_EVEX_OPSIZE_KZ, /* 4405 */ >+ IC_EVEX_OPSIZE_KZ, /* 4406 */ >+ IC_EVEX_OPSIZE_KZ, /* 4407 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4408 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4409 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4410 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4411 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4412 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4413 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4414 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4415 */ >+ IC_EVEX_KZ, /* 4416 */ >+ IC_EVEX_KZ, /* 4417 */ >+ IC_EVEX_XS_KZ, /* 4418 */ >+ IC_EVEX_XS_KZ, /* 4419 */ >+ IC_EVEX_XD_KZ, /* 4420 */ >+ IC_EVEX_XD_KZ, /* 4421 */ >+ IC_EVEX_XD_KZ, /* 4422 */ >+ IC_EVEX_XD_KZ, /* 4423 */ >+ IC_EVEX_W_KZ, /* 4424 */ >+ IC_EVEX_W_KZ, /* 4425 */ >+ IC_EVEX_W_XS_KZ, /* 4426 */ >+ IC_EVEX_W_XS_KZ, /* 4427 */ >+ IC_EVEX_W_XD_KZ, /* 4428 */ >+ IC_EVEX_W_XD_KZ, /* 4429 */ >+ IC_EVEX_W_XD_KZ, /* 4430 */ >+ IC_EVEX_W_XD_KZ, /* 4431 */ >+ IC_EVEX_OPSIZE_KZ, /* 4432 */ >+ IC_EVEX_OPSIZE_KZ, /* 4433 */ >+ IC_EVEX_OPSIZE_KZ, /* 4434 */ >+ IC_EVEX_OPSIZE_KZ, /* 4435 */ >+ IC_EVEX_OPSIZE_KZ, /* 4436 */ >+ IC_EVEX_OPSIZE_KZ, /* 4437 */ >+ IC_EVEX_OPSIZE_KZ, /* 4438 */ >+ IC_EVEX_OPSIZE_KZ, /* 4439 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4440 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4441 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4442 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4443 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4444 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4445 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4446 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4447 */ >+ IC_EVEX_KZ, /* 4448 */ >+ IC_EVEX_KZ, /* 4449 */ >+ IC_EVEX_XS_KZ, /* 4450 */ >+ IC_EVEX_XS_KZ, /* 4451 */ >+ IC_EVEX_XD_KZ, /* 4452 */ >+ IC_EVEX_XD_KZ, /* 4453 */ >+ IC_EVEX_XD_KZ, /* 4454 */ >+ IC_EVEX_XD_KZ, /* 4455 */ >+ IC_EVEX_W_KZ, /* 4456 */ >+ IC_EVEX_W_KZ, /* 4457 */ >+ IC_EVEX_W_XS_KZ, /* 4458 */ >+ IC_EVEX_W_XS_KZ, /* 4459 */ >+ IC_EVEX_W_XD_KZ, /* 4460 */ >+ IC_EVEX_W_XD_KZ, /* 4461 */ >+ IC_EVEX_W_XD_KZ, /* 4462 */ >+ IC_EVEX_W_XD_KZ, /* 4463 */ >+ IC_EVEX_OPSIZE_KZ, /* 4464 */ >+ IC_EVEX_OPSIZE_KZ, /* 4465 */ >+ IC_EVEX_OPSIZE_KZ, /* 4466 */ >+ IC_EVEX_OPSIZE_KZ, /* 4467 */ >+ IC_EVEX_OPSIZE_KZ, /* 4468 */ >+ IC_EVEX_OPSIZE_KZ, /* 4469 */ >+ IC_EVEX_OPSIZE_KZ, /* 4470 */ >+ IC_EVEX_OPSIZE_KZ, /* 4471 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4472 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4473 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4474 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4475 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4476 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4477 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4478 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4479 */ >+ IC_EVEX_KZ, /* 4480 */ >+ IC_EVEX_KZ, /* 4481 */ >+ IC_EVEX_XS_KZ, /* 4482 */ >+ IC_EVEX_XS_KZ, /* 4483 */ >+ IC_EVEX_XD_KZ, /* 4484 */ >+ IC_EVEX_XD_KZ, /* 4485 */ >+ IC_EVEX_XD_KZ, /* 4486 */ >+ IC_EVEX_XD_KZ, /* 4487 */ >+ IC_EVEX_W_KZ, /* 4488 */ >+ IC_EVEX_W_KZ, /* 4489 */ >+ IC_EVEX_W_XS_KZ, /* 4490 */ >+ IC_EVEX_W_XS_KZ, /* 4491 */ >+ IC_EVEX_W_XD_KZ, /* 4492 */ >+ IC_EVEX_W_XD_KZ, /* 4493 */ >+ IC_EVEX_W_XD_KZ, /* 4494 */ >+ IC_EVEX_W_XD_KZ, /* 4495 */ >+ IC_EVEX_OPSIZE_KZ, /* 4496 */ >+ IC_EVEX_OPSIZE_KZ, /* 4497 */ >+ IC_EVEX_OPSIZE_KZ, /* 4498 */ >+ IC_EVEX_OPSIZE_KZ, /* 4499 */ >+ IC_EVEX_OPSIZE_KZ, /* 4500 */ >+ IC_EVEX_OPSIZE_KZ, /* 4501 */ >+ IC_EVEX_OPSIZE_KZ, /* 4502 */ >+ IC_EVEX_OPSIZE_KZ, /* 4503 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4504 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4505 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4506 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4507 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4508 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4509 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4510 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4511 */ >+ IC_EVEX_KZ, /* 4512 */ >+ IC_EVEX_KZ, /* 4513 */ >+ IC_EVEX_XS_KZ, /* 4514 */ >+ IC_EVEX_XS_KZ, /* 4515 */ >+ IC_EVEX_XD_KZ, /* 4516 */ >+ IC_EVEX_XD_KZ, /* 4517 */ >+ IC_EVEX_XD_KZ, /* 4518 */ >+ IC_EVEX_XD_KZ, /* 4519 */ >+ IC_EVEX_W_KZ, /* 4520 */ >+ IC_EVEX_W_KZ, /* 4521 */ >+ IC_EVEX_W_XS_KZ, /* 4522 */ >+ IC_EVEX_W_XS_KZ, /* 4523 */ >+ IC_EVEX_W_XD_KZ, /* 4524 */ >+ IC_EVEX_W_XD_KZ, /* 4525 */ >+ IC_EVEX_W_XD_KZ, /* 4526 */ >+ IC_EVEX_W_XD_KZ, /* 4527 */ >+ IC_EVEX_OPSIZE_KZ, /* 4528 */ >+ IC_EVEX_OPSIZE_KZ, /* 4529 */ >+ IC_EVEX_OPSIZE_KZ, /* 4530 */ >+ IC_EVEX_OPSIZE_KZ, /* 4531 */ >+ IC_EVEX_OPSIZE_KZ, /* 4532 */ >+ IC_EVEX_OPSIZE_KZ, /* 4533 */ >+ IC_EVEX_OPSIZE_KZ, /* 4534 */ >+ IC_EVEX_OPSIZE_KZ, /* 4535 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4536 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4537 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4538 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4539 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4540 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4541 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4542 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4543 */ >+ IC_EVEX_KZ, /* 4544 */ >+ IC_EVEX_KZ, /* 4545 */ >+ IC_EVEX_XS_KZ, /* 4546 */ >+ IC_EVEX_XS_KZ, /* 4547 */ >+ IC_EVEX_XD_KZ, /* 4548 */ >+ IC_EVEX_XD_KZ, /* 4549 */ >+ IC_EVEX_XD_KZ, /* 4550 */ >+ IC_EVEX_XD_KZ, /* 4551 */ >+ IC_EVEX_W_KZ, /* 4552 */ >+ IC_EVEX_W_KZ, /* 4553 */ >+ IC_EVEX_W_XS_KZ, /* 4554 */ >+ IC_EVEX_W_XS_KZ, /* 4555 */ >+ IC_EVEX_W_XD_KZ, /* 4556 */ >+ IC_EVEX_W_XD_KZ, /* 4557 */ >+ IC_EVEX_W_XD_KZ, /* 4558 */ >+ IC_EVEX_W_XD_KZ, /* 4559 */ >+ IC_EVEX_OPSIZE_KZ, /* 4560 */ >+ IC_EVEX_OPSIZE_KZ, /* 4561 */ >+ IC_EVEX_OPSIZE_KZ, /* 4562 */ >+ IC_EVEX_OPSIZE_KZ, /* 4563 */ >+ IC_EVEX_OPSIZE_KZ, /* 4564 */ >+ IC_EVEX_OPSIZE_KZ, /* 4565 */ >+ IC_EVEX_OPSIZE_KZ, /* 4566 */ >+ IC_EVEX_OPSIZE_KZ, /* 4567 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4568 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4569 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4570 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4571 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4572 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4573 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4574 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4575 */ >+ IC_EVEX_KZ, /* 4576 */ >+ IC_EVEX_KZ, /* 4577 */ >+ IC_EVEX_XS_KZ, /* 4578 */ >+ IC_EVEX_XS_KZ, /* 4579 */ >+ IC_EVEX_XD_KZ, /* 4580 */ >+ IC_EVEX_XD_KZ, /* 4581 */ >+ IC_EVEX_XD_KZ, /* 4582 */ >+ IC_EVEX_XD_KZ, /* 4583 */ >+ IC_EVEX_W_KZ, /* 4584 */ >+ IC_EVEX_W_KZ, /* 4585 */ >+ IC_EVEX_W_XS_KZ, /* 4586 */ >+ IC_EVEX_W_XS_KZ, /* 4587 */ >+ IC_EVEX_W_XD_KZ, /* 4588 */ >+ IC_EVEX_W_XD_KZ, /* 4589 */ >+ IC_EVEX_W_XD_KZ, /* 4590 */ >+ IC_EVEX_W_XD_KZ, /* 4591 */ >+ IC_EVEX_OPSIZE_KZ, /* 4592 */ >+ IC_EVEX_OPSIZE_KZ, /* 4593 */ >+ IC_EVEX_OPSIZE_KZ, /* 4594 */ >+ IC_EVEX_OPSIZE_KZ, /* 4595 */ >+ IC_EVEX_OPSIZE_KZ, /* 4596 */ >+ IC_EVEX_OPSIZE_KZ, /* 4597 */ >+ IC_EVEX_OPSIZE_KZ, /* 4598 */ >+ IC_EVEX_OPSIZE_KZ, /* 4599 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4600 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4601 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4602 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4603 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4604 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4605 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4606 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 4607 */ >+ IC, /* 4608 */ >+ IC_64BIT, /* 4609 */ >+ IC_XS, /* 4610 */ >+ IC_64BIT_XS, /* 4611 */ >+ IC_XD, /* 4612 */ >+ IC_64BIT_XD, /* 4613 */ >+ IC_XS, /* 4614 */ >+ IC_64BIT_XS, /* 4615 */ >+ IC, /* 4616 */ >+ IC_64BIT_REXW, /* 4617 */ >+ IC_XS, /* 4618 */ >+ IC_64BIT_REXW_XS, /* 4619 */ >+ IC_XD, /* 4620 */ >+ IC_64BIT_REXW_XD, /* 4621 */ >+ IC_XS, /* 4622 */ >+ IC_64BIT_REXW_XS, /* 4623 */ >+ IC_OPSIZE, /* 4624 */ >+ IC_64BIT_OPSIZE, /* 4625 */ >+ IC_XS_OPSIZE, /* 4626 */ >+ IC_64BIT_XS_OPSIZE, /* 4627 */ >+ IC_XD_OPSIZE, /* 4628 */ >+ IC_64BIT_XD_OPSIZE, /* 4629 */ >+ IC_XS_OPSIZE, /* 4630 */ >+ IC_64BIT_XD_OPSIZE, /* 4631 */ >+ IC_OPSIZE, /* 4632 */ >+ IC_64BIT_REXW_OPSIZE, /* 4633 */ >+ IC_XS_OPSIZE, /* 4634 */ >+ IC_64BIT_REXW_XS, /* 4635 */ >+ IC_XD_OPSIZE, /* 4636 */ >+ IC_64BIT_REXW_XD, /* 4637 */ >+ IC_XS_OPSIZE, /* 4638 */ >+ IC_64BIT_REXW_XS, /* 4639 */ >+ IC_ADSIZE, /* 4640 */ >+ IC_64BIT_ADSIZE, /* 4641 */ >+ IC_XS, /* 4642 */ >+ IC_64BIT_XS, /* 4643 */ >+ IC_XD, /* 4644 */ >+ IC_64BIT_XD, /* 4645 */ >+ IC_XS, /* 4646 */ >+ IC_64BIT_XS, /* 4647 */ >+ IC_ADSIZE, /* 4648 */ >+ IC_64BIT_ADSIZE, /* 4649 */ >+ IC_XS, /* 4650 */ >+ IC_64BIT_REXW_XS, /* 4651 */ >+ IC_XD, /* 4652 */ >+ IC_64BIT_REXW_XD, /* 4653 */ >+ IC_XS, /* 4654 */ >+ IC_64BIT_REXW_XS, /* 4655 */ >+ IC_OPSIZE, /* 4656 */ >+ IC_64BIT_OPSIZE, /* 4657 */ >+ IC_XS_OPSIZE, /* 4658 */ >+ IC_64BIT_XS_OPSIZE, /* 4659 */ >+ IC_XD_OPSIZE, /* 4660 */ >+ IC_64BIT_XD_OPSIZE, /* 4661 */ >+ IC_XS_OPSIZE, /* 4662 */ >+ IC_64BIT_XD_OPSIZE, /* 4663 */ >+ IC_OPSIZE, /* 4664 */ >+ IC_64BIT_REXW_OPSIZE, /* 4665 */ >+ IC_XS_OPSIZE, /* 4666 */ >+ IC_64BIT_REXW_XS, /* 4667 */ >+ IC_XD_OPSIZE, /* 4668 */ >+ IC_64BIT_REXW_XD, /* 4669 */ >+ IC_XS_OPSIZE, /* 4670 */ >+ IC_64BIT_REXW_XS, /* 4671 */ >+ IC_VEX, /* 4672 */ >+ IC_VEX, /* 4673 */ >+ IC_VEX_XS, /* 4674 */ >+ IC_VEX_XS, /* 4675 */ >+ IC_VEX_XD, /* 4676 */ >+ IC_VEX_XD, /* 4677 */ >+ IC_VEX_XD, /* 4678 */ >+ IC_VEX_XD, /* 4679 */ >+ IC_VEX_W, /* 4680 */ >+ IC_VEX_W, /* 4681 */ >+ IC_VEX_W_XS, /* 4682 */ >+ IC_VEX_W_XS, /* 4683 */ >+ IC_VEX_W_XD, /* 4684 */ >+ IC_VEX_W_XD, /* 4685 */ >+ IC_VEX_W_XD, /* 4686 */ >+ IC_VEX_W_XD, /* 4687 */ >+ IC_VEX_OPSIZE, /* 4688 */ >+ IC_VEX_OPSIZE, /* 4689 */ >+ IC_VEX_OPSIZE, /* 4690 */ >+ IC_VEX_OPSIZE, /* 4691 */ >+ IC_VEX_OPSIZE, /* 4692 */ >+ IC_VEX_OPSIZE, /* 4693 */ >+ IC_VEX_OPSIZE, /* 4694 */ >+ IC_VEX_OPSIZE, /* 4695 */ >+ IC_VEX_W_OPSIZE, /* 4696 */ >+ IC_VEX_W_OPSIZE, /* 4697 */ >+ IC_VEX_W_OPSIZE, /* 4698 */ >+ IC_VEX_W_OPSIZE, /* 4699 */ >+ IC_VEX_W_OPSIZE, /* 4700 */ >+ IC_VEX_W_OPSIZE, /* 4701 */ >+ IC_VEX_W_OPSIZE, /* 4702 */ >+ IC_VEX_W_OPSIZE, /* 4703 */ >+ IC_VEX, /* 4704 */ >+ IC_VEX, /* 4705 */ >+ IC_VEX_XS, /* 4706 */ >+ IC_VEX_XS, /* 4707 */ >+ IC_VEX_XD, /* 4708 */ >+ IC_VEX_XD, /* 4709 */ >+ IC_VEX_XD, /* 4710 */ >+ IC_VEX_XD, /* 4711 */ >+ IC_VEX_W, /* 4712 */ >+ IC_VEX_W, /* 4713 */ >+ IC_VEX_W_XS, /* 4714 */ >+ IC_VEX_W_XS, /* 4715 */ >+ IC_VEX_W_XD, /* 4716 */ >+ IC_VEX_W_XD, /* 4717 */ >+ IC_VEX_W_XD, /* 4718 */ >+ IC_VEX_W_XD, /* 4719 */ >+ IC_VEX_OPSIZE, /* 4720 */ >+ IC_VEX_OPSIZE, /* 4721 */ >+ IC_VEX_OPSIZE, /* 4722 */ >+ IC_VEX_OPSIZE, /* 4723 */ >+ IC_VEX_OPSIZE, /* 4724 */ >+ IC_VEX_OPSIZE, /* 4725 */ >+ IC_VEX_OPSIZE, /* 4726 */ >+ IC_VEX_OPSIZE, /* 4727 */ >+ IC_VEX_W_OPSIZE, /* 4728 */ >+ IC_VEX_W_OPSIZE, /* 4729 */ >+ IC_VEX_W_OPSIZE, /* 4730 */ >+ IC_VEX_W_OPSIZE, /* 4731 */ >+ IC_VEX_W_OPSIZE, /* 4732 */ >+ IC_VEX_W_OPSIZE, /* 4733 */ >+ IC_VEX_W_OPSIZE, /* 4734 */ >+ IC_VEX_W_OPSIZE, /* 4735 */ >+ IC_VEX_L, /* 4736 */ >+ IC_VEX_L, /* 4737 */ >+ IC_VEX_L_XS, /* 4738 */ >+ IC_VEX_L_XS, /* 4739 */ >+ IC_VEX_L_XD, /* 4740 */ >+ IC_VEX_L_XD, /* 4741 */ >+ IC_VEX_L_XD, /* 4742 */ >+ IC_VEX_L_XD, /* 4743 */ >+ IC_VEX_L_W, /* 4744 */ >+ IC_VEX_L_W, /* 4745 */ >+ IC_VEX_L_W_XS, /* 4746 */ >+ IC_VEX_L_W_XS, /* 4747 */ >+ IC_VEX_L_W_XD, /* 4748 */ >+ IC_VEX_L_W_XD, /* 4749 */ >+ IC_VEX_L_W_XD, /* 4750 */ >+ IC_VEX_L_W_XD, /* 4751 */ >+ IC_VEX_L_OPSIZE, /* 4752 */ >+ IC_VEX_L_OPSIZE, /* 4753 */ >+ IC_VEX_L_OPSIZE, /* 4754 */ >+ IC_VEX_L_OPSIZE, /* 4755 */ >+ IC_VEX_L_OPSIZE, /* 4756 */ >+ IC_VEX_L_OPSIZE, /* 4757 */ >+ IC_VEX_L_OPSIZE, /* 4758 */ >+ IC_VEX_L_OPSIZE, /* 4759 */ >+ IC_VEX_L_W_OPSIZE, /* 4760 */ >+ IC_VEX_L_W_OPSIZE, /* 4761 */ >+ IC_VEX_L_W_OPSIZE, /* 4762 */ >+ IC_VEX_L_W_OPSIZE, /* 4763 */ >+ IC_VEX_L_W_OPSIZE, /* 4764 */ >+ IC_VEX_L_W_OPSIZE, /* 4765 */ >+ IC_VEX_L_W_OPSIZE, /* 4766 */ >+ IC_VEX_L_W_OPSIZE, /* 4767 */ >+ IC_VEX_L, /* 4768 */ >+ IC_VEX_L, /* 4769 */ >+ IC_VEX_L_XS, /* 4770 */ >+ IC_VEX_L_XS, /* 4771 */ >+ IC_VEX_L_XD, /* 4772 */ >+ IC_VEX_L_XD, /* 4773 */ >+ IC_VEX_L_XD, /* 4774 */ >+ IC_VEX_L_XD, /* 4775 */ >+ IC_VEX_L_W, /* 4776 */ >+ IC_VEX_L_W, /* 4777 */ >+ IC_VEX_L_W_XS, /* 4778 */ >+ IC_VEX_L_W_XS, /* 4779 */ >+ IC_VEX_L_W_XD, /* 4780 */ >+ IC_VEX_L_W_XD, /* 4781 */ >+ IC_VEX_L_W_XD, /* 4782 */ >+ IC_VEX_L_W_XD, /* 4783 */ >+ IC_VEX_L_OPSIZE, /* 4784 */ >+ IC_VEX_L_OPSIZE, /* 4785 */ >+ IC_VEX_L_OPSIZE, /* 4786 */ >+ IC_VEX_L_OPSIZE, /* 4787 */ >+ IC_VEX_L_OPSIZE, /* 4788 */ >+ IC_VEX_L_OPSIZE, /* 4789 */ >+ IC_VEX_L_OPSIZE, /* 4790 */ >+ IC_VEX_L_OPSIZE, /* 4791 */ >+ IC_VEX_L_W_OPSIZE, /* 4792 */ >+ IC_VEX_L_W_OPSIZE, /* 4793 */ >+ IC_VEX_L_W_OPSIZE, /* 4794 */ >+ IC_VEX_L_W_OPSIZE, /* 4795 */ >+ IC_VEX_L_W_OPSIZE, /* 4796 */ >+ IC_VEX_L_W_OPSIZE, /* 4797 */ >+ IC_VEX_L_W_OPSIZE, /* 4798 */ >+ IC_VEX_L_W_OPSIZE, /* 4799 */ >+ IC_VEX_L, /* 4800 */ >+ IC_VEX_L, /* 4801 */ >+ IC_VEX_L_XS, /* 4802 */ >+ IC_VEX_L_XS, /* 4803 */ >+ IC_VEX_L_XD, /* 4804 */ >+ IC_VEX_L_XD, /* 4805 */ >+ IC_VEX_L_XD, /* 4806 */ >+ IC_VEX_L_XD, /* 4807 */ >+ IC_VEX_L_W, /* 4808 */ >+ IC_VEX_L_W, /* 4809 */ >+ IC_VEX_L_W_XS, /* 4810 */ >+ IC_VEX_L_W_XS, /* 4811 */ >+ IC_VEX_L_W_XD, /* 4812 */ >+ IC_VEX_L_W_XD, /* 4813 */ >+ IC_VEX_L_W_XD, /* 4814 */ >+ IC_VEX_L_W_XD, /* 4815 */ >+ IC_VEX_L_OPSIZE, /* 4816 */ >+ IC_VEX_L_OPSIZE, /* 4817 */ >+ IC_VEX_L_OPSIZE, /* 4818 */ >+ IC_VEX_L_OPSIZE, /* 4819 */ >+ IC_VEX_L_OPSIZE, /* 4820 */ >+ IC_VEX_L_OPSIZE, /* 4821 */ >+ IC_VEX_L_OPSIZE, /* 4822 */ >+ IC_VEX_L_OPSIZE, /* 4823 */ >+ IC_VEX_L_W_OPSIZE, /* 4824 */ >+ IC_VEX_L_W_OPSIZE, /* 4825 */ >+ IC_VEX_L_W_OPSIZE, /* 4826 */ >+ IC_VEX_L_W_OPSIZE, /* 4827 */ >+ IC_VEX_L_W_OPSIZE, /* 4828 */ >+ IC_VEX_L_W_OPSIZE, /* 4829 */ >+ IC_VEX_L_W_OPSIZE, /* 4830 */ >+ IC_VEX_L_W_OPSIZE, /* 4831 */ >+ IC_VEX_L, /* 4832 */ >+ IC_VEX_L, /* 4833 */ >+ IC_VEX_L_XS, /* 4834 */ >+ IC_VEX_L_XS, /* 4835 */ >+ IC_VEX_L_XD, /* 4836 */ >+ IC_VEX_L_XD, /* 4837 */ >+ IC_VEX_L_XD, /* 4838 */ >+ IC_VEX_L_XD, /* 4839 */ >+ IC_VEX_L_W, /* 4840 */ >+ IC_VEX_L_W, /* 4841 */ >+ IC_VEX_L_W_XS, /* 4842 */ >+ IC_VEX_L_W_XS, /* 4843 */ >+ IC_VEX_L_W_XD, /* 4844 */ >+ IC_VEX_L_W_XD, /* 4845 */ >+ IC_VEX_L_W_XD, /* 4846 */ >+ IC_VEX_L_W_XD, /* 4847 */ >+ IC_VEX_L_OPSIZE, /* 4848 */ >+ IC_VEX_L_OPSIZE, /* 4849 */ >+ IC_VEX_L_OPSIZE, /* 4850 */ >+ IC_VEX_L_OPSIZE, /* 4851 */ >+ IC_VEX_L_OPSIZE, /* 4852 */ >+ IC_VEX_L_OPSIZE, /* 4853 */ >+ IC_VEX_L_OPSIZE, /* 4854 */ >+ IC_VEX_L_OPSIZE, /* 4855 */ >+ IC_VEX_L_W_OPSIZE, /* 4856 */ >+ IC_VEX_L_W_OPSIZE, /* 4857 */ >+ IC_VEX_L_W_OPSIZE, /* 4858 */ >+ IC_VEX_L_W_OPSIZE, /* 4859 */ >+ IC_VEX_L_W_OPSIZE, /* 4860 */ >+ IC_VEX_L_W_OPSIZE, /* 4861 */ >+ IC_VEX_L_W_OPSIZE, /* 4862 */ >+ IC_VEX_L_W_OPSIZE, /* 4863 */ >+ IC_EVEX_L_KZ, /* 4864 */ >+ IC_EVEX_L_KZ, /* 4865 */ >+ IC_EVEX_L_XS_KZ, /* 4866 */ >+ IC_EVEX_L_XS_KZ, /* 4867 */ >+ IC_EVEX_L_XD_KZ, /* 4868 */ >+ IC_EVEX_L_XD_KZ, /* 4869 */ >+ IC_EVEX_L_XD_KZ, /* 4870 */ >+ IC_EVEX_L_XD_KZ, /* 4871 */ >+ IC_EVEX_L_W_KZ, /* 4872 */ >+ IC_EVEX_L_W_KZ, /* 4873 */ >+ IC_EVEX_L_W_XS_KZ, /* 4874 */ >+ IC_EVEX_L_W_XS_KZ, /* 4875 */ >+ IC_EVEX_L_W_XD_KZ, /* 4876 */ >+ IC_EVEX_L_W_XD_KZ, /* 4877 */ >+ IC_EVEX_L_W_XD_KZ, /* 4878 */ >+ IC_EVEX_L_W_XD_KZ, /* 4879 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4880 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4881 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4882 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4883 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4884 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4885 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4886 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4887 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4888 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4889 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4890 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4891 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4892 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4893 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4894 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4895 */ >+ IC_EVEX_L_KZ, /* 4896 */ >+ IC_EVEX_L_KZ, /* 4897 */ >+ IC_EVEX_L_XS_KZ, /* 4898 */ >+ IC_EVEX_L_XS_KZ, /* 4899 */ >+ IC_EVEX_L_XD_KZ, /* 4900 */ >+ IC_EVEX_L_XD_KZ, /* 4901 */ >+ IC_EVEX_L_XD_KZ, /* 4902 */ >+ IC_EVEX_L_XD_KZ, /* 4903 */ >+ IC_EVEX_L_W_KZ, /* 4904 */ >+ IC_EVEX_L_W_KZ, /* 4905 */ >+ IC_EVEX_L_W_XS_KZ, /* 4906 */ >+ IC_EVEX_L_W_XS_KZ, /* 4907 */ >+ IC_EVEX_L_W_XD_KZ, /* 4908 */ >+ IC_EVEX_L_W_XD_KZ, /* 4909 */ >+ IC_EVEX_L_W_XD_KZ, /* 4910 */ >+ IC_EVEX_L_W_XD_KZ, /* 4911 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4912 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4913 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4914 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4915 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4916 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4917 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4918 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4919 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4920 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4921 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4922 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4923 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4924 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4925 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4926 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4927 */ >+ IC_EVEX_L_KZ, /* 4928 */ >+ IC_EVEX_L_KZ, /* 4929 */ >+ IC_EVEX_L_XS_KZ, /* 4930 */ >+ IC_EVEX_L_XS_KZ, /* 4931 */ >+ IC_EVEX_L_XD_KZ, /* 4932 */ >+ IC_EVEX_L_XD_KZ, /* 4933 */ >+ IC_EVEX_L_XD_KZ, /* 4934 */ >+ IC_EVEX_L_XD_KZ, /* 4935 */ >+ IC_EVEX_L_W_KZ, /* 4936 */ >+ IC_EVEX_L_W_KZ, /* 4937 */ >+ IC_EVEX_L_W_XS_KZ, /* 4938 */ >+ IC_EVEX_L_W_XS_KZ, /* 4939 */ >+ IC_EVEX_L_W_XD_KZ, /* 4940 */ >+ IC_EVEX_L_W_XD_KZ, /* 4941 */ >+ IC_EVEX_L_W_XD_KZ, /* 4942 */ >+ IC_EVEX_L_W_XD_KZ, /* 4943 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4944 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4945 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4946 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4947 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4948 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4949 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4950 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4951 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4952 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4953 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4954 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4955 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4956 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4957 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4958 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4959 */ >+ IC_EVEX_L_KZ, /* 4960 */ >+ IC_EVEX_L_KZ, /* 4961 */ >+ IC_EVEX_L_XS_KZ, /* 4962 */ >+ IC_EVEX_L_XS_KZ, /* 4963 */ >+ IC_EVEX_L_XD_KZ, /* 4964 */ >+ IC_EVEX_L_XD_KZ, /* 4965 */ >+ IC_EVEX_L_XD_KZ, /* 4966 */ >+ IC_EVEX_L_XD_KZ, /* 4967 */ >+ IC_EVEX_L_W_KZ, /* 4968 */ >+ IC_EVEX_L_W_KZ, /* 4969 */ >+ IC_EVEX_L_W_XS_KZ, /* 4970 */ >+ IC_EVEX_L_W_XS_KZ, /* 4971 */ >+ IC_EVEX_L_W_XD_KZ, /* 4972 */ >+ IC_EVEX_L_W_XD_KZ, /* 4973 */ >+ IC_EVEX_L_W_XD_KZ, /* 4974 */ >+ IC_EVEX_L_W_XD_KZ, /* 4975 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4976 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4977 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4978 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4979 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4980 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4981 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4982 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 4983 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4984 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4985 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4986 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4987 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4988 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4989 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4990 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 4991 */ >+ IC_EVEX_L_KZ, /* 4992 */ >+ IC_EVEX_L_KZ, /* 4993 */ >+ IC_EVEX_L_XS_KZ, /* 4994 */ >+ IC_EVEX_L_XS_KZ, /* 4995 */ >+ IC_EVEX_L_XD_KZ, /* 4996 */ >+ IC_EVEX_L_XD_KZ, /* 4997 */ >+ IC_EVEX_L_XD_KZ, /* 4998 */ >+ IC_EVEX_L_XD_KZ, /* 4999 */ >+ IC_EVEX_L_W_KZ, /* 5000 */ >+ IC_EVEX_L_W_KZ, /* 5001 */ >+ IC_EVEX_L_W_XS_KZ, /* 5002 */ >+ IC_EVEX_L_W_XS_KZ, /* 5003 */ >+ IC_EVEX_L_W_XD_KZ, /* 5004 */ >+ IC_EVEX_L_W_XD_KZ, /* 5005 */ >+ IC_EVEX_L_W_XD_KZ, /* 5006 */ >+ IC_EVEX_L_W_XD_KZ, /* 5007 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5008 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5009 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5010 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5011 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5012 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5013 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5014 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5015 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5016 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5017 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5018 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5019 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5020 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5021 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5022 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5023 */ >+ IC_EVEX_L_KZ, /* 5024 */ >+ IC_EVEX_L_KZ, /* 5025 */ >+ IC_EVEX_L_XS_KZ, /* 5026 */ >+ IC_EVEX_L_XS_KZ, /* 5027 */ >+ IC_EVEX_L_XD_KZ, /* 5028 */ >+ IC_EVEX_L_XD_KZ, /* 5029 */ >+ IC_EVEX_L_XD_KZ, /* 5030 */ >+ IC_EVEX_L_XD_KZ, /* 5031 */ >+ IC_EVEX_L_W_KZ, /* 5032 */ >+ IC_EVEX_L_W_KZ, /* 5033 */ >+ IC_EVEX_L_W_XS_KZ, /* 5034 */ >+ IC_EVEX_L_W_XS_KZ, /* 5035 */ >+ IC_EVEX_L_W_XD_KZ, /* 5036 */ >+ IC_EVEX_L_W_XD_KZ, /* 5037 */ >+ IC_EVEX_L_W_XD_KZ, /* 5038 */ >+ IC_EVEX_L_W_XD_KZ, /* 5039 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5040 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5041 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5042 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5043 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5044 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5045 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5046 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5047 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5048 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5049 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5050 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5051 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5052 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5053 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5054 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5055 */ >+ IC_EVEX_L_KZ, /* 5056 */ >+ IC_EVEX_L_KZ, /* 5057 */ >+ IC_EVEX_L_XS_KZ, /* 5058 */ >+ IC_EVEX_L_XS_KZ, /* 5059 */ >+ IC_EVEX_L_XD_KZ, /* 5060 */ >+ IC_EVEX_L_XD_KZ, /* 5061 */ >+ IC_EVEX_L_XD_KZ, /* 5062 */ >+ IC_EVEX_L_XD_KZ, /* 5063 */ >+ IC_EVEX_L_W_KZ, /* 5064 */ >+ IC_EVEX_L_W_KZ, /* 5065 */ >+ IC_EVEX_L_W_XS_KZ, /* 5066 */ >+ IC_EVEX_L_W_XS_KZ, /* 5067 */ >+ IC_EVEX_L_W_XD_KZ, /* 5068 */ >+ IC_EVEX_L_W_XD_KZ, /* 5069 */ >+ IC_EVEX_L_W_XD_KZ, /* 5070 */ >+ IC_EVEX_L_W_XD_KZ, /* 5071 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5072 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5073 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5074 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5075 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5076 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5077 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5078 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5079 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5080 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5081 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5082 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5083 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5084 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5085 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5086 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5087 */ >+ IC_EVEX_L_KZ, /* 5088 */ >+ IC_EVEX_L_KZ, /* 5089 */ >+ IC_EVEX_L_XS_KZ, /* 5090 */ >+ IC_EVEX_L_XS_KZ, /* 5091 */ >+ IC_EVEX_L_XD_KZ, /* 5092 */ >+ IC_EVEX_L_XD_KZ, /* 5093 */ >+ IC_EVEX_L_XD_KZ, /* 5094 */ >+ IC_EVEX_L_XD_KZ, /* 5095 */ >+ IC_EVEX_L_W_KZ, /* 5096 */ >+ IC_EVEX_L_W_KZ, /* 5097 */ >+ IC_EVEX_L_W_XS_KZ, /* 5098 */ >+ IC_EVEX_L_W_XS_KZ, /* 5099 */ >+ IC_EVEX_L_W_XD_KZ, /* 5100 */ >+ IC_EVEX_L_W_XD_KZ, /* 5101 */ >+ IC_EVEX_L_W_XD_KZ, /* 5102 */ >+ IC_EVEX_L_W_XD_KZ, /* 5103 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5104 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5105 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5106 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5107 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5108 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5109 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5110 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 5111 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5112 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5113 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5114 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5115 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5116 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5117 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5118 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 5119 */ >+ IC, /* 5120 */ >+ IC_64BIT, /* 5121 */ >+ IC_XS, /* 5122 */ >+ IC_64BIT_XS, /* 5123 */ >+ IC_XD, /* 5124 */ >+ IC_64BIT_XD, /* 5125 */ >+ IC_XS, /* 5126 */ >+ IC_64BIT_XS, /* 5127 */ >+ IC, /* 5128 */ >+ IC_64BIT_REXW, /* 5129 */ >+ IC_XS, /* 5130 */ >+ IC_64BIT_REXW_XS, /* 5131 */ >+ IC_XD, /* 5132 */ >+ IC_64BIT_REXW_XD, /* 5133 */ >+ IC_XS, /* 5134 */ >+ IC_64BIT_REXW_XS, /* 5135 */ >+ IC_OPSIZE, /* 5136 */ >+ IC_64BIT_OPSIZE, /* 5137 */ >+ IC_XS_OPSIZE, /* 5138 */ >+ IC_64BIT_XS_OPSIZE, /* 5139 */ >+ IC_XD_OPSIZE, /* 5140 */ >+ IC_64BIT_XD_OPSIZE, /* 5141 */ >+ IC_XS_OPSIZE, /* 5142 */ >+ IC_64BIT_XD_OPSIZE, /* 5143 */ >+ IC_OPSIZE, /* 5144 */ >+ IC_64BIT_REXW_OPSIZE, /* 5145 */ >+ IC_XS_OPSIZE, /* 5146 */ >+ IC_64BIT_REXW_XS, /* 5147 */ >+ IC_XD_OPSIZE, /* 5148 */ >+ IC_64BIT_REXW_XD, /* 5149 */ >+ IC_XS_OPSIZE, /* 5150 */ >+ IC_64BIT_REXW_XS, /* 5151 */ >+ IC_ADSIZE, /* 5152 */ >+ IC_64BIT_ADSIZE, /* 5153 */ >+ IC_XS, /* 5154 */ >+ IC_64BIT_XS, /* 5155 */ >+ IC_XD, /* 5156 */ >+ IC_64BIT_XD, /* 5157 */ >+ IC_XS, /* 5158 */ >+ IC_64BIT_XS, /* 5159 */ >+ IC_ADSIZE, /* 5160 */ >+ IC_64BIT_ADSIZE, /* 5161 */ >+ IC_XS, /* 5162 */ >+ IC_64BIT_REXW_XS, /* 5163 */ >+ IC_XD, /* 5164 */ >+ IC_64BIT_REXW_XD, /* 5165 */ >+ IC_XS, /* 5166 */ >+ IC_64BIT_REXW_XS, /* 5167 */ >+ IC_OPSIZE, /* 5168 */ >+ IC_64BIT_OPSIZE, /* 5169 */ >+ IC_XS_OPSIZE, /* 5170 */ >+ IC_64BIT_XS_OPSIZE, /* 5171 */ >+ IC_XD_OPSIZE, /* 5172 */ >+ IC_64BIT_XD_OPSIZE, /* 5173 */ >+ IC_XS_OPSIZE, /* 5174 */ >+ IC_64BIT_XD_OPSIZE, /* 5175 */ >+ IC_OPSIZE, /* 5176 */ >+ IC_64BIT_REXW_OPSIZE, /* 5177 */ >+ IC_XS_OPSIZE, /* 5178 */ >+ IC_64BIT_REXW_XS, /* 5179 */ >+ IC_XD_OPSIZE, /* 5180 */ >+ IC_64BIT_REXW_XD, /* 5181 */ >+ IC_XS_OPSIZE, /* 5182 */ >+ IC_64BIT_REXW_XS, /* 5183 */ >+ IC_VEX, /* 5184 */ >+ IC_VEX, /* 5185 */ >+ IC_VEX_XS, /* 5186 */ >+ IC_VEX_XS, /* 5187 */ >+ IC_VEX_XD, /* 5188 */ >+ IC_VEX_XD, /* 5189 */ >+ IC_VEX_XD, /* 5190 */ >+ IC_VEX_XD, /* 5191 */ >+ IC_VEX_W, /* 5192 */ >+ IC_VEX_W, /* 5193 */ >+ IC_VEX_W_XS, /* 5194 */ >+ IC_VEX_W_XS, /* 5195 */ >+ IC_VEX_W_XD, /* 5196 */ >+ IC_VEX_W_XD, /* 5197 */ >+ IC_VEX_W_XD, /* 5198 */ >+ IC_VEX_W_XD, /* 5199 */ >+ IC_VEX_OPSIZE, /* 5200 */ >+ IC_VEX_OPSIZE, /* 5201 */ >+ IC_VEX_OPSIZE, /* 5202 */ >+ IC_VEX_OPSIZE, /* 5203 */ >+ IC_VEX_OPSIZE, /* 5204 */ >+ IC_VEX_OPSIZE, /* 5205 */ >+ IC_VEX_OPSIZE, /* 5206 */ >+ IC_VEX_OPSIZE, /* 5207 */ >+ IC_VEX_W_OPSIZE, /* 5208 */ >+ IC_VEX_W_OPSIZE, /* 5209 */ >+ IC_VEX_W_OPSIZE, /* 5210 */ >+ IC_VEX_W_OPSIZE, /* 5211 */ >+ IC_VEX_W_OPSIZE, /* 5212 */ >+ IC_VEX_W_OPSIZE, /* 5213 */ >+ IC_VEX_W_OPSIZE, /* 5214 */ >+ IC_VEX_W_OPSIZE, /* 5215 */ >+ IC_VEX, /* 5216 */ >+ IC_VEX, /* 5217 */ >+ IC_VEX_XS, /* 5218 */ >+ IC_VEX_XS, /* 5219 */ >+ IC_VEX_XD, /* 5220 */ >+ IC_VEX_XD, /* 5221 */ >+ IC_VEX_XD, /* 5222 */ >+ IC_VEX_XD, /* 5223 */ >+ IC_VEX_W, /* 5224 */ >+ IC_VEX_W, /* 5225 */ >+ IC_VEX_W_XS, /* 5226 */ >+ IC_VEX_W_XS, /* 5227 */ >+ IC_VEX_W_XD, /* 5228 */ >+ IC_VEX_W_XD, /* 5229 */ >+ IC_VEX_W_XD, /* 5230 */ >+ IC_VEX_W_XD, /* 5231 */ >+ IC_VEX_OPSIZE, /* 5232 */ >+ IC_VEX_OPSIZE, /* 5233 */ >+ IC_VEX_OPSIZE, /* 5234 */ >+ IC_VEX_OPSIZE, /* 5235 */ >+ IC_VEX_OPSIZE, /* 5236 */ >+ IC_VEX_OPSIZE, /* 5237 */ >+ IC_VEX_OPSIZE, /* 5238 */ >+ IC_VEX_OPSIZE, /* 5239 */ >+ IC_VEX_W_OPSIZE, /* 5240 */ >+ IC_VEX_W_OPSIZE, /* 5241 */ >+ IC_VEX_W_OPSIZE, /* 5242 */ >+ IC_VEX_W_OPSIZE, /* 5243 */ >+ IC_VEX_W_OPSIZE, /* 5244 */ >+ IC_VEX_W_OPSIZE, /* 5245 */ >+ IC_VEX_W_OPSIZE, /* 5246 */ >+ IC_VEX_W_OPSIZE, /* 5247 */ >+ IC_VEX_L, /* 5248 */ >+ IC_VEX_L, /* 5249 */ >+ IC_VEX_L_XS, /* 5250 */ >+ IC_VEX_L_XS, /* 5251 */ >+ IC_VEX_L_XD, /* 5252 */ >+ IC_VEX_L_XD, /* 5253 */ >+ IC_VEX_L_XD, /* 5254 */ >+ IC_VEX_L_XD, /* 5255 */ >+ IC_VEX_L_W, /* 5256 */ >+ IC_VEX_L_W, /* 5257 */ >+ IC_VEX_L_W_XS, /* 5258 */ >+ IC_VEX_L_W_XS, /* 5259 */ >+ IC_VEX_L_W_XD, /* 5260 */ >+ IC_VEX_L_W_XD, /* 5261 */ >+ IC_VEX_L_W_XD, /* 5262 */ >+ IC_VEX_L_W_XD, /* 5263 */ >+ IC_VEX_L_OPSIZE, /* 5264 */ >+ IC_VEX_L_OPSIZE, /* 5265 */ >+ IC_VEX_L_OPSIZE, /* 5266 */ >+ IC_VEX_L_OPSIZE, /* 5267 */ >+ IC_VEX_L_OPSIZE, /* 5268 */ >+ IC_VEX_L_OPSIZE, /* 5269 */ >+ IC_VEX_L_OPSIZE, /* 5270 */ >+ IC_VEX_L_OPSIZE, /* 5271 */ >+ IC_VEX_L_W_OPSIZE, /* 5272 */ >+ IC_VEX_L_W_OPSIZE, /* 5273 */ >+ IC_VEX_L_W_OPSIZE, /* 5274 */ >+ IC_VEX_L_W_OPSIZE, /* 5275 */ >+ IC_VEX_L_W_OPSIZE, /* 5276 */ >+ IC_VEX_L_W_OPSIZE, /* 5277 */ >+ IC_VEX_L_W_OPSIZE, /* 5278 */ >+ IC_VEX_L_W_OPSIZE, /* 5279 */ >+ IC_VEX_L, /* 5280 */ >+ IC_VEX_L, /* 5281 */ >+ IC_VEX_L_XS, /* 5282 */ >+ IC_VEX_L_XS, /* 5283 */ >+ IC_VEX_L_XD, /* 5284 */ >+ IC_VEX_L_XD, /* 5285 */ >+ IC_VEX_L_XD, /* 5286 */ >+ IC_VEX_L_XD, /* 5287 */ >+ IC_VEX_L_W, /* 5288 */ >+ IC_VEX_L_W, /* 5289 */ >+ IC_VEX_L_W_XS, /* 5290 */ >+ IC_VEX_L_W_XS, /* 5291 */ >+ IC_VEX_L_W_XD, /* 5292 */ >+ IC_VEX_L_W_XD, /* 5293 */ >+ IC_VEX_L_W_XD, /* 5294 */ >+ IC_VEX_L_W_XD, /* 5295 */ >+ IC_VEX_L_OPSIZE, /* 5296 */ >+ IC_VEX_L_OPSIZE, /* 5297 */ >+ IC_VEX_L_OPSIZE, /* 5298 */ >+ IC_VEX_L_OPSIZE, /* 5299 */ >+ IC_VEX_L_OPSIZE, /* 5300 */ >+ IC_VEX_L_OPSIZE, /* 5301 */ >+ IC_VEX_L_OPSIZE, /* 5302 */ >+ IC_VEX_L_OPSIZE, /* 5303 */ >+ IC_VEX_L_W_OPSIZE, /* 5304 */ >+ IC_VEX_L_W_OPSIZE, /* 5305 */ >+ IC_VEX_L_W_OPSIZE, /* 5306 */ >+ IC_VEX_L_W_OPSIZE, /* 5307 */ >+ IC_VEX_L_W_OPSIZE, /* 5308 */ >+ IC_VEX_L_W_OPSIZE, /* 5309 */ >+ IC_VEX_L_W_OPSIZE, /* 5310 */ >+ IC_VEX_L_W_OPSIZE, /* 5311 */ >+ IC_VEX_L, /* 5312 */ >+ IC_VEX_L, /* 5313 */ >+ IC_VEX_L_XS, /* 5314 */ >+ IC_VEX_L_XS, /* 5315 */ >+ IC_VEX_L_XD, /* 5316 */ >+ IC_VEX_L_XD, /* 5317 */ >+ IC_VEX_L_XD, /* 5318 */ >+ IC_VEX_L_XD, /* 5319 */ >+ IC_VEX_L_W, /* 5320 */ >+ IC_VEX_L_W, /* 5321 */ >+ IC_VEX_L_W_XS, /* 5322 */ >+ IC_VEX_L_W_XS, /* 5323 */ >+ IC_VEX_L_W_XD, /* 5324 */ >+ IC_VEX_L_W_XD, /* 5325 */ >+ IC_VEX_L_W_XD, /* 5326 */ >+ IC_VEX_L_W_XD, /* 5327 */ >+ IC_VEX_L_OPSIZE, /* 5328 */ >+ IC_VEX_L_OPSIZE, /* 5329 */ >+ IC_VEX_L_OPSIZE, /* 5330 */ >+ IC_VEX_L_OPSIZE, /* 5331 */ >+ IC_VEX_L_OPSIZE, /* 5332 */ >+ IC_VEX_L_OPSIZE, /* 5333 */ >+ IC_VEX_L_OPSIZE, /* 5334 */ >+ IC_VEX_L_OPSIZE, /* 5335 */ >+ IC_VEX_L_W_OPSIZE, /* 5336 */ >+ IC_VEX_L_W_OPSIZE, /* 5337 */ >+ IC_VEX_L_W_OPSIZE, /* 5338 */ >+ IC_VEX_L_W_OPSIZE, /* 5339 */ >+ IC_VEX_L_W_OPSIZE, /* 5340 */ >+ IC_VEX_L_W_OPSIZE, /* 5341 */ >+ IC_VEX_L_W_OPSIZE, /* 5342 */ >+ IC_VEX_L_W_OPSIZE, /* 5343 */ >+ IC_VEX_L, /* 5344 */ >+ IC_VEX_L, /* 5345 */ >+ IC_VEX_L_XS, /* 5346 */ >+ IC_VEX_L_XS, /* 5347 */ >+ IC_VEX_L_XD, /* 5348 */ >+ IC_VEX_L_XD, /* 5349 */ >+ IC_VEX_L_XD, /* 5350 */ >+ IC_VEX_L_XD, /* 5351 */ >+ IC_VEX_L_W, /* 5352 */ >+ IC_VEX_L_W, /* 5353 */ >+ IC_VEX_L_W_XS, /* 5354 */ >+ IC_VEX_L_W_XS, /* 5355 */ >+ IC_VEX_L_W_XD, /* 5356 */ >+ IC_VEX_L_W_XD, /* 5357 */ >+ IC_VEX_L_W_XD, /* 5358 */ >+ IC_VEX_L_W_XD, /* 5359 */ >+ IC_VEX_L_OPSIZE, /* 5360 */ >+ IC_VEX_L_OPSIZE, /* 5361 */ >+ IC_VEX_L_OPSIZE, /* 5362 */ >+ IC_VEX_L_OPSIZE, /* 5363 */ >+ IC_VEX_L_OPSIZE, /* 5364 */ >+ IC_VEX_L_OPSIZE, /* 5365 */ >+ IC_VEX_L_OPSIZE, /* 5366 */ >+ IC_VEX_L_OPSIZE, /* 5367 */ >+ IC_VEX_L_W_OPSIZE, /* 5368 */ >+ IC_VEX_L_W_OPSIZE, /* 5369 */ >+ IC_VEX_L_W_OPSIZE, /* 5370 */ >+ IC_VEX_L_W_OPSIZE, /* 5371 */ >+ IC_VEX_L_W_OPSIZE, /* 5372 */ >+ IC_VEX_L_W_OPSIZE, /* 5373 */ >+ IC_VEX_L_W_OPSIZE, /* 5374 */ >+ IC_VEX_L_W_OPSIZE, /* 5375 */ >+ IC_EVEX_L2_KZ, /* 5376 */ >+ IC_EVEX_L2_KZ, /* 5377 */ >+ IC_EVEX_L2_XS_KZ, /* 5378 */ >+ IC_EVEX_L2_XS_KZ, /* 5379 */ >+ IC_EVEX_L2_XD_KZ, /* 5380 */ >+ IC_EVEX_L2_XD_KZ, /* 5381 */ >+ IC_EVEX_L2_XD_KZ, /* 5382 */ >+ IC_EVEX_L2_XD_KZ, /* 5383 */ >+ IC_EVEX_L2_W_KZ, /* 5384 */ >+ IC_EVEX_L2_W_KZ, /* 5385 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5386 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5387 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5388 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5389 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5390 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5391 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5392 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5393 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5394 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5395 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5396 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5397 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5398 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5399 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5400 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5401 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5402 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5403 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5404 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5405 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5406 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5407 */ >+ IC_EVEX_L2_KZ, /* 5408 */ >+ IC_EVEX_L2_KZ, /* 5409 */ >+ IC_EVEX_L2_XS_KZ, /* 5410 */ >+ IC_EVEX_L2_XS_KZ, /* 5411 */ >+ IC_EVEX_L2_XD_KZ, /* 5412 */ >+ IC_EVEX_L2_XD_KZ, /* 5413 */ >+ IC_EVEX_L2_XD_KZ, /* 5414 */ >+ IC_EVEX_L2_XD_KZ, /* 5415 */ >+ IC_EVEX_L2_W_KZ, /* 5416 */ >+ IC_EVEX_L2_W_KZ, /* 5417 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5418 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5419 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5420 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5421 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5422 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5423 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5424 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5425 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5426 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5427 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5428 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5429 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5430 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5431 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5432 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5433 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5434 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5435 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5436 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5437 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5438 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5439 */ >+ IC_EVEX_L2_KZ, /* 5440 */ >+ IC_EVEX_L2_KZ, /* 5441 */ >+ IC_EVEX_L2_XS_KZ, /* 5442 */ >+ IC_EVEX_L2_XS_KZ, /* 5443 */ >+ IC_EVEX_L2_XD_KZ, /* 5444 */ >+ IC_EVEX_L2_XD_KZ, /* 5445 */ >+ IC_EVEX_L2_XD_KZ, /* 5446 */ >+ IC_EVEX_L2_XD_KZ, /* 5447 */ >+ IC_EVEX_L2_W_KZ, /* 5448 */ >+ IC_EVEX_L2_W_KZ, /* 5449 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5450 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5451 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5452 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5453 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5454 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5455 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5456 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5457 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5458 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5459 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5460 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5461 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5462 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5463 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5464 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5465 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5466 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5467 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5468 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5469 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5470 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5471 */ >+ IC_EVEX_L2_KZ, /* 5472 */ >+ IC_EVEX_L2_KZ, /* 5473 */ >+ IC_EVEX_L2_XS_KZ, /* 5474 */ >+ IC_EVEX_L2_XS_KZ, /* 5475 */ >+ IC_EVEX_L2_XD_KZ, /* 5476 */ >+ IC_EVEX_L2_XD_KZ, /* 5477 */ >+ IC_EVEX_L2_XD_KZ, /* 5478 */ >+ IC_EVEX_L2_XD_KZ, /* 5479 */ >+ IC_EVEX_L2_W_KZ, /* 5480 */ >+ IC_EVEX_L2_W_KZ, /* 5481 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5482 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5483 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5484 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5485 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5486 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5487 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5488 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5489 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5490 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5491 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5492 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5493 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5494 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5495 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5496 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5497 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5498 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5499 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5500 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5501 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5502 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5503 */ >+ IC_EVEX_L2_KZ, /* 5504 */ >+ IC_EVEX_L2_KZ, /* 5505 */ >+ IC_EVEX_L2_XS_KZ, /* 5506 */ >+ IC_EVEX_L2_XS_KZ, /* 5507 */ >+ IC_EVEX_L2_XD_KZ, /* 5508 */ >+ IC_EVEX_L2_XD_KZ, /* 5509 */ >+ IC_EVEX_L2_XD_KZ, /* 5510 */ >+ IC_EVEX_L2_XD_KZ, /* 5511 */ >+ IC_EVEX_L2_W_KZ, /* 5512 */ >+ IC_EVEX_L2_W_KZ, /* 5513 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5514 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5515 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5516 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5517 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5518 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5519 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5520 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5521 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5522 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5523 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5524 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5525 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5526 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5527 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5528 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5529 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5530 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5531 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5532 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5533 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5534 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5535 */ >+ IC_EVEX_L2_KZ, /* 5536 */ >+ IC_EVEX_L2_KZ, /* 5537 */ >+ IC_EVEX_L2_XS_KZ, /* 5538 */ >+ IC_EVEX_L2_XS_KZ, /* 5539 */ >+ IC_EVEX_L2_XD_KZ, /* 5540 */ >+ IC_EVEX_L2_XD_KZ, /* 5541 */ >+ IC_EVEX_L2_XD_KZ, /* 5542 */ >+ IC_EVEX_L2_XD_KZ, /* 5543 */ >+ IC_EVEX_L2_W_KZ, /* 5544 */ >+ IC_EVEX_L2_W_KZ, /* 5545 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5546 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5547 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5548 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5549 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5550 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5551 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5552 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5553 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5554 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5555 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5556 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5557 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5558 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5559 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5560 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5561 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5562 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5563 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5564 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5565 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5566 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5567 */ >+ IC_EVEX_L2_KZ, /* 5568 */ >+ IC_EVEX_L2_KZ, /* 5569 */ >+ IC_EVEX_L2_XS_KZ, /* 5570 */ >+ IC_EVEX_L2_XS_KZ, /* 5571 */ >+ IC_EVEX_L2_XD_KZ, /* 5572 */ >+ IC_EVEX_L2_XD_KZ, /* 5573 */ >+ IC_EVEX_L2_XD_KZ, /* 5574 */ >+ IC_EVEX_L2_XD_KZ, /* 5575 */ >+ IC_EVEX_L2_W_KZ, /* 5576 */ >+ IC_EVEX_L2_W_KZ, /* 5577 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5578 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5579 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5580 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5581 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5582 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5583 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5584 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5585 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5586 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5587 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5588 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5589 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5590 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5591 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5592 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5593 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5594 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5595 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5596 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5597 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5598 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5599 */ >+ IC_EVEX_L2_KZ, /* 5600 */ >+ IC_EVEX_L2_KZ, /* 5601 */ >+ IC_EVEX_L2_XS_KZ, /* 5602 */ >+ IC_EVEX_L2_XS_KZ, /* 5603 */ >+ IC_EVEX_L2_XD_KZ, /* 5604 */ >+ IC_EVEX_L2_XD_KZ, /* 5605 */ >+ IC_EVEX_L2_XD_KZ, /* 5606 */ >+ IC_EVEX_L2_XD_KZ, /* 5607 */ >+ IC_EVEX_L2_W_KZ, /* 5608 */ >+ IC_EVEX_L2_W_KZ, /* 5609 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5610 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5611 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5612 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5613 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5614 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5615 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5616 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5617 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5618 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5619 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5620 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5621 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5622 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5623 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5624 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5625 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5626 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5627 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5628 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5629 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5630 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5631 */ >+ IC, /* 5632 */ >+ IC_64BIT, /* 5633 */ >+ IC_XS, /* 5634 */ >+ IC_64BIT_XS, /* 5635 */ >+ IC_XD, /* 5636 */ >+ IC_64BIT_XD, /* 5637 */ >+ IC_XS, /* 5638 */ >+ IC_64BIT_XS, /* 5639 */ >+ IC, /* 5640 */ >+ IC_64BIT_REXW, /* 5641 */ >+ IC_XS, /* 5642 */ >+ IC_64BIT_REXW_XS, /* 5643 */ >+ IC_XD, /* 5644 */ >+ IC_64BIT_REXW_XD, /* 5645 */ >+ IC_XS, /* 5646 */ >+ IC_64BIT_REXW_XS, /* 5647 */ >+ IC_OPSIZE, /* 5648 */ >+ IC_64BIT_OPSIZE, /* 5649 */ >+ IC_XS_OPSIZE, /* 5650 */ >+ IC_64BIT_XS_OPSIZE, /* 5651 */ >+ IC_XD_OPSIZE, /* 5652 */ >+ IC_64BIT_XD_OPSIZE, /* 5653 */ >+ IC_XS_OPSIZE, /* 5654 */ >+ IC_64BIT_XD_OPSIZE, /* 5655 */ >+ IC_OPSIZE, /* 5656 */ >+ IC_64BIT_REXW_OPSIZE, /* 5657 */ >+ IC_XS_OPSIZE, /* 5658 */ >+ IC_64BIT_REXW_XS, /* 5659 */ >+ IC_XD_OPSIZE, /* 5660 */ >+ IC_64BIT_REXW_XD, /* 5661 */ >+ IC_XS_OPSIZE, /* 5662 */ >+ IC_64BIT_REXW_XS, /* 5663 */ >+ IC_ADSIZE, /* 5664 */ >+ IC_64BIT_ADSIZE, /* 5665 */ >+ IC_XS, /* 5666 */ >+ IC_64BIT_XS, /* 5667 */ >+ IC_XD, /* 5668 */ >+ IC_64BIT_XD, /* 5669 */ >+ IC_XS, /* 5670 */ >+ IC_64BIT_XS, /* 5671 */ >+ IC_ADSIZE, /* 5672 */ >+ IC_64BIT_ADSIZE, /* 5673 */ >+ IC_XS, /* 5674 */ >+ IC_64BIT_REXW_XS, /* 5675 */ >+ IC_XD, /* 5676 */ >+ IC_64BIT_REXW_XD, /* 5677 */ >+ IC_XS, /* 5678 */ >+ IC_64BIT_REXW_XS, /* 5679 */ >+ IC_OPSIZE, /* 5680 */ >+ IC_64BIT_OPSIZE, /* 5681 */ >+ IC_XS_OPSIZE, /* 5682 */ >+ IC_64BIT_XS_OPSIZE, /* 5683 */ >+ IC_XD_OPSIZE, /* 5684 */ >+ IC_64BIT_XD_OPSIZE, /* 5685 */ >+ IC_XS_OPSIZE, /* 5686 */ >+ IC_64BIT_XD_OPSIZE, /* 5687 */ >+ IC_OPSIZE, /* 5688 */ >+ IC_64BIT_REXW_OPSIZE, /* 5689 */ >+ IC_XS_OPSIZE, /* 5690 */ >+ IC_64BIT_REXW_XS, /* 5691 */ >+ IC_XD_OPSIZE, /* 5692 */ >+ IC_64BIT_REXW_XD, /* 5693 */ >+ IC_XS_OPSIZE, /* 5694 */ >+ IC_64BIT_REXW_XS, /* 5695 */ >+ IC_VEX, /* 5696 */ >+ IC_VEX, /* 5697 */ >+ IC_VEX_XS, /* 5698 */ >+ IC_VEX_XS, /* 5699 */ >+ IC_VEX_XD, /* 5700 */ >+ IC_VEX_XD, /* 5701 */ >+ IC_VEX_XD, /* 5702 */ >+ IC_VEX_XD, /* 5703 */ >+ IC_VEX_W, /* 5704 */ >+ IC_VEX_W, /* 5705 */ >+ IC_VEX_W_XS, /* 5706 */ >+ IC_VEX_W_XS, /* 5707 */ >+ IC_VEX_W_XD, /* 5708 */ >+ IC_VEX_W_XD, /* 5709 */ >+ IC_VEX_W_XD, /* 5710 */ >+ IC_VEX_W_XD, /* 5711 */ >+ IC_VEX_OPSIZE, /* 5712 */ >+ IC_VEX_OPSIZE, /* 5713 */ >+ IC_VEX_OPSIZE, /* 5714 */ >+ IC_VEX_OPSIZE, /* 5715 */ >+ IC_VEX_OPSIZE, /* 5716 */ >+ IC_VEX_OPSIZE, /* 5717 */ >+ IC_VEX_OPSIZE, /* 5718 */ >+ IC_VEX_OPSIZE, /* 5719 */ >+ IC_VEX_W_OPSIZE, /* 5720 */ >+ IC_VEX_W_OPSIZE, /* 5721 */ >+ IC_VEX_W_OPSIZE, /* 5722 */ >+ IC_VEX_W_OPSIZE, /* 5723 */ >+ IC_VEX_W_OPSIZE, /* 5724 */ >+ IC_VEX_W_OPSIZE, /* 5725 */ >+ IC_VEX_W_OPSIZE, /* 5726 */ >+ IC_VEX_W_OPSIZE, /* 5727 */ >+ IC_VEX, /* 5728 */ >+ IC_VEX, /* 5729 */ >+ IC_VEX_XS, /* 5730 */ >+ IC_VEX_XS, /* 5731 */ >+ IC_VEX_XD, /* 5732 */ >+ IC_VEX_XD, /* 5733 */ >+ IC_VEX_XD, /* 5734 */ >+ IC_VEX_XD, /* 5735 */ >+ IC_VEX_W, /* 5736 */ >+ IC_VEX_W, /* 5737 */ >+ IC_VEX_W_XS, /* 5738 */ >+ IC_VEX_W_XS, /* 5739 */ >+ IC_VEX_W_XD, /* 5740 */ >+ IC_VEX_W_XD, /* 5741 */ >+ IC_VEX_W_XD, /* 5742 */ >+ IC_VEX_W_XD, /* 5743 */ >+ IC_VEX_OPSIZE, /* 5744 */ >+ IC_VEX_OPSIZE, /* 5745 */ >+ IC_VEX_OPSIZE, /* 5746 */ >+ IC_VEX_OPSIZE, /* 5747 */ >+ IC_VEX_OPSIZE, /* 5748 */ >+ IC_VEX_OPSIZE, /* 5749 */ >+ IC_VEX_OPSIZE, /* 5750 */ >+ IC_VEX_OPSIZE, /* 5751 */ >+ IC_VEX_W_OPSIZE, /* 5752 */ >+ IC_VEX_W_OPSIZE, /* 5753 */ >+ IC_VEX_W_OPSIZE, /* 5754 */ >+ IC_VEX_W_OPSIZE, /* 5755 */ >+ IC_VEX_W_OPSIZE, /* 5756 */ >+ IC_VEX_W_OPSIZE, /* 5757 */ >+ IC_VEX_W_OPSIZE, /* 5758 */ >+ IC_VEX_W_OPSIZE, /* 5759 */ >+ IC_VEX_L, /* 5760 */ >+ IC_VEX_L, /* 5761 */ >+ IC_VEX_L_XS, /* 5762 */ >+ IC_VEX_L_XS, /* 5763 */ >+ IC_VEX_L_XD, /* 5764 */ >+ IC_VEX_L_XD, /* 5765 */ >+ IC_VEX_L_XD, /* 5766 */ >+ IC_VEX_L_XD, /* 5767 */ >+ IC_VEX_L_W, /* 5768 */ >+ IC_VEX_L_W, /* 5769 */ >+ IC_VEX_L_W_XS, /* 5770 */ >+ IC_VEX_L_W_XS, /* 5771 */ >+ IC_VEX_L_W_XD, /* 5772 */ >+ IC_VEX_L_W_XD, /* 5773 */ >+ IC_VEX_L_W_XD, /* 5774 */ >+ IC_VEX_L_W_XD, /* 5775 */ >+ IC_VEX_L_OPSIZE, /* 5776 */ >+ IC_VEX_L_OPSIZE, /* 5777 */ >+ IC_VEX_L_OPSIZE, /* 5778 */ >+ IC_VEX_L_OPSIZE, /* 5779 */ >+ IC_VEX_L_OPSIZE, /* 5780 */ >+ IC_VEX_L_OPSIZE, /* 5781 */ >+ IC_VEX_L_OPSIZE, /* 5782 */ >+ IC_VEX_L_OPSIZE, /* 5783 */ >+ IC_VEX_L_W_OPSIZE, /* 5784 */ >+ IC_VEX_L_W_OPSIZE, /* 5785 */ >+ IC_VEX_L_W_OPSIZE, /* 5786 */ >+ IC_VEX_L_W_OPSIZE, /* 5787 */ >+ IC_VEX_L_W_OPSIZE, /* 5788 */ >+ IC_VEX_L_W_OPSIZE, /* 5789 */ >+ IC_VEX_L_W_OPSIZE, /* 5790 */ >+ IC_VEX_L_W_OPSIZE, /* 5791 */ >+ IC_VEX_L, /* 5792 */ >+ IC_VEX_L, /* 5793 */ >+ IC_VEX_L_XS, /* 5794 */ >+ IC_VEX_L_XS, /* 5795 */ >+ IC_VEX_L_XD, /* 5796 */ >+ IC_VEX_L_XD, /* 5797 */ >+ IC_VEX_L_XD, /* 5798 */ >+ IC_VEX_L_XD, /* 5799 */ >+ IC_VEX_L_W, /* 5800 */ >+ IC_VEX_L_W, /* 5801 */ >+ IC_VEX_L_W_XS, /* 5802 */ >+ IC_VEX_L_W_XS, /* 5803 */ >+ IC_VEX_L_W_XD, /* 5804 */ >+ IC_VEX_L_W_XD, /* 5805 */ >+ IC_VEX_L_W_XD, /* 5806 */ >+ IC_VEX_L_W_XD, /* 5807 */ >+ IC_VEX_L_OPSIZE, /* 5808 */ >+ IC_VEX_L_OPSIZE, /* 5809 */ >+ IC_VEX_L_OPSIZE, /* 5810 */ >+ IC_VEX_L_OPSIZE, /* 5811 */ >+ IC_VEX_L_OPSIZE, /* 5812 */ >+ IC_VEX_L_OPSIZE, /* 5813 */ >+ IC_VEX_L_OPSIZE, /* 5814 */ >+ IC_VEX_L_OPSIZE, /* 5815 */ >+ IC_VEX_L_W_OPSIZE, /* 5816 */ >+ IC_VEX_L_W_OPSIZE, /* 5817 */ >+ IC_VEX_L_W_OPSIZE, /* 5818 */ >+ IC_VEX_L_W_OPSIZE, /* 5819 */ >+ IC_VEX_L_W_OPSIZE, /* 5820 */ >+ IC_VEX_L_W_OPSIZE, /* 5821 */ >+ IC_VEX_L_W_OPSIZE, /* 5822 */ >+ IC_VEX_L_W_OPSIZE, /* 5823 */ >+ IC_VEX_L, /* 5824 */ >+ IC_VEX_L, /* 5825 */ >+ IC_VEX_L_XS, /* 5826 */ >+ IC_VEX_L_XS, /* 5827 */ >+ IC_VEX_L_XD, /* 5828 */ >+ IC_VEX_L_XD, /* 5829 */ >+ IC_VEX_L_XD, /* 5830 */ >+ IC_VEX_L_XD, /* 5831 */ >+ IC_VEX_L_W, /* 5832 */ >+ IC_VEX_L_W, /* 5833 */ >+ IC_VEX_L_W_XS, /* 5834 */ >+ IC_VEX_L_W_XS, /* 5835 */ >+ IC_VEX_L_W_XD, /* 5836 */ >+ IC_VEX_L_W_XD, /* 5837 */ >+ IC_VEX_L_W_XD, /* 5838 */ >+ IC_VEX_L_W_XD, /* 5839 */ >+ IC_VEX_L_OPSIZE, /* 5840 */ >+ IC_VEX_L_OPSIZE, /* 5841 */ >+ IC_VEX_L_OPSIZE, /* 5842 */ >+ IC_VEX_L_OPSIZE, /* 5843 */ >+ IC_VEX_L_OPSIZE, /* 5844 */ >+ IC_VEX_L_OPSIZE, /* 5845 */ >+ IC_VEX_L_OPSIZE, /* 5846 */ >+ IC_VEX_L_OPSIZE, /* 5847 */ >+ IC_VEX_L_W_OPSIZE, /* 5848 */ >+ IC_VEX_L_W_OPSIZE, /* 5849 */ >+ IC_VEX_L_W_OPSIZE, /* 5850 */ >+ IC_VEX_L_W_OPSIZE, /* 5851 */ >+ IC_VEX_L_W_OPSIZE, /* 5852 */ >+ IC_VEX_L_W_OPSIZE, /* 5853 */ >+ IC_VEX_L_W_OPSIZE, /* 5854 */ >+ IC_VEX_L_W_OPSIZE, /* 5855 */ >+ IC_VEX_L, /* 5856 */ >+ IC_VEX_L, /* 5857 */ >+ IC_VEX_L_XS, /* 5858 */ >+ IC_VEX_L_XS, /* 5859 */ >+ IC_VEX_L_XD, /* 5860 */ >+ IC_VEX_L_XD, /* 5861 */ >+ IC_VEX_L_XD, /* 5862 */ >+ IC_VEX_L_XD, /* 5863 */ >+ IC_VEX_L_W, /* 5864 */ >+ IC_VEX_L_W, /* 5865 */ >+ IC_VEX_L_W_XS, /* 5866 */ >+ IC_VEX_L_W_XS, /* 5867 */ >+ IC_VEX_L_W_XD, /* 5868 */ >+ IC_VEX_L_W_XD, /* 5869 */ >+ IC_VEX_L_W_XD, /* 5870 */ >+ IC_VEX_L_W_XD, /* 5871 */ >+ IC_VEX_L_OPSIZE, /* 5872 */ >+ IC_VEX_L_OPSIZE, /* 5873 */ >+ IC_VEX_L_OPSIZE, /* 5874 */ >+ IC_VEX_L_OPSIZE, /* 5875 */ >+ IC_VEX_L_OPSIZE, /* 5876 */ >+ IC_VEX_L_OPSIZE, /* 5877 */ >+ IC_VEX_L_OPSIZE, /* 5878 */ >+ IC_VEX_L_OPSIZE, /* 5879 */ >+ IC_VEX_L_W_OPSIZE, /* 5880 */ >+ IC_VEX_L_W_OPSIZE, /* 5881 */ >+ IC_VEX_L_W_OPSIZE, /* 5882 */ >+ IC_VEX_L_W_OPSIZE, /* 5883 */ >+ IC_VEX_L_W_OPSIZE, /* 5884 */ >+ IC_VEX_L_W_OPSIZE, /* 5885 */ >+ IC_VEX_L_W_OPSIZE, /* 5886 */ >+ IC_VEX_L_W_OPSIZE, /* 5887 */ >+ IC_EVEX_L2_KZ, /* 5888 */ >+ IC_EVEX_L2_KZ, /* 5889 */ >+ IC_EVEX_L2_XS_KZ, /* 5890 */ >+ IC_EVEX_L2_XS_KZ, /* 5891 */ >+ IC_EVEX_L2_XD_KZ, /* 5892 */ >+ IC_EVEX_L2_XD_KZ, /* 5893 */ >+ IC_EVEX_L2_XD_KZ, /* 5894 */ >+ IC_EVEX_L2_XD_KZ, /* 5895 */ >+ IC_EVEX_L2_W_KZ, /* 5896 */ >+ IC_EVEX_L2_W_KZ, /* 5897 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5898 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5899 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5900 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5901 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5902 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5903 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5904 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5905 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5906 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5907 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5908 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5909 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5910 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5911 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5912 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5913 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5914 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5915 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5916 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5917 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5918 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5919 */ >+ IC_EVEX_L2_KZ, /* 5920 */ >+ IC_EVEX_L2_KZ, /* 5921 */ >+ IC_EVEX_L2_XS_KZ, /* 5922 */ >+ IC_EVEX_L2_XS_KZ, /* 5923 */ >+ IC_EVEX_L2_XD_KZ, /* 5924 */ >+ IC_EVEX_L2_XD_KZ, /* 5925 */ >+ IC_EVEX_L2_XD_KZ, /* 5926 */ >+ IC_EVEX_L2_XD_KZ, /* 5927 */ >+ IC_EVEX_L2_W_KZ, /* 5928 */ >+ IC_EVEX_L2_W_KZ, /* 5929 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5930 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5931 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5932 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5933 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5934 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5935 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5936 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5937 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5938 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5939 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5940 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5941 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5942 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5943 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5944 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5945 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5946 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5947 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5948 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5949 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5950 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5951 */ >+ IC_EVEX_L2_KZ, /* 5952 */ >+ IC_EVEX_L2_KZ, /* 5953 */ >+ IC_EVEX_L2_XS_KZ, /* 5954 */ >+ IC_EVEX_L2_XS_KZ, /* 5955 */ >+ IC_EVEX_L2_XD_KZ, /* 5956 */ >+ IC_EVEX_L2_XD_KZ, /* 5957 */ >+ IC_EVEX_L2_XD_KZ, /* 5958 */ >+ IC_EVEX_L2_XD_KZ, /* 5959 */ >+ IC_EVEX_L2_W_KZ, /* 5960 */ >+ IC_EVEX_L2_W_KZ, /* 5961 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5962 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5963 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5964 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5965 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5966 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5967 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5968 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5969 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5970 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5971 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5972 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5973 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5974 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 5975 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5976 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5977 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5978 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5979 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5980 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5981 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5982 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 5983 */ >+ IC_EVEX_L2_KZ, /* 5984 */ >+ IC_EVEX_L2_KZ, /* 5985 */ >+ IC_EVEX_L2_XS_KZ, /* 5986 */ >+ IC_EVEX_L2_XS_KZ, /* 5987 */ >+ IC_EVEX_L2_XD_KZ, /* 5988 */ >+ IC_EVEX_L2_XD_KZ, /* 5989 */ >+ IC_EVEX_L2_XD_KZ, /* 5990 */ >+ IC_EVEX_L2_XD_KZ, /* 5991 */ >+ IC_EVEX_L2_W_KZ, /* 5992 */ >+ IC_EVEX_L2_W_KZ, /* 5993 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5994 */ >+ IC_EVEX_L2_W_XS_KZ, /* 5995 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5996 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5997 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5998 */ >+ IC_EVEX_L2_W_XD_KZ, /* 5999 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6000 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6001 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6002 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6003 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6004 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6005 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6006 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6007 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6008 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6009 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6010 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6011 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6012 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6013 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6014 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6015 */ >+ IC_EVEX_L2_KZ, /* 6016 */ >+ IC_EVEX_L2_KZ, /* 6017 */ >+ IC_EVEX_L2_XS_KZ, /* 6018 */ >+ IC_EVEX_L2_XS_KZ, /* 6019 */ >+ IC_EVEX_L2_XD_KZ, /* 6020 */ >+ IC_EVEX_L2_XD_KZ, /* 6021 */ >+ IC_EVEX_L2_XD_KZ, /* 6022 */ >+ IC_EVEX_L2_XD_KZ, /* 6023 */ >+ IC_EVEX_L2_W_KZ, /* 6024 */ >+ IC_EVEX_L2_W_KZ, /* 6025 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6026 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6027 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6028 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6029 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6030 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6031 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6032 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6033 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6034 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6035 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6036 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6037 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6038 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6039 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6040 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6041 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6042 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6043 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6044 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6045 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6046 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6047 */ >+ IC_EVEX_L2_KZ, /* 6048 */ >+ IC_EVEX_L2_KZ, /* 6049 */ >+ IC_EVEX_L2_XS_KZ, /* 6050 */ >+ IC_EVEX_L2_XS_KZ, /* 6051 */ >+ IC_EVEX_L2_XD_KZ, /* 6052 */ >+ IC_EVEX_L2_XD_KZ, /* 6053 */ >+ IC_EVEX_L2_XD_KZ, /* 6054 */ >+ IC_EVEX_L2_XD_KZ, /* 6055 */ >+ IC_EVEX_L2_W_KZ, /* 6056 */ >+ IC_EVEX_L2_W_KZ, /* 6057 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6058 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6059 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6060 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6061 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6062 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6063 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6064 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6065 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6066 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6067 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6068 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6069 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6070 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6071 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6072 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6073 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6074 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6075 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6076 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6077 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6078 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6079 */ >+ IC_EVEX_L2_KZ, /* 6080 */ >+ IC_EVEX_L2_KZ, /* 6081 */ >+ IC_EVEX_L2_XS_KZ, /* 6082 */ >+ IC_EVEX_L2_XS_KZ, /* 6083 */ >+ IC_EVEX_L2_XD_KZ, /* 6084 */ >+ IC_EVEX_L2_XD_KZ, /* 6085 */ >+ IC_EVEX_L2_XD_KZ, /* 6086 */ >+ IC_EVEX_L2_XD_KZ, /* 6087 */ >+ IC_EVEX_L2_W_KZ, /* 6088 */ >+ IC_EVEX_L2_W_KZ, /* 6089 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6090 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6091 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6092 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6093 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6094 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6095 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6096 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6097 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6098 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6099 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6100 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6101 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6102 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6103 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6104 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6105 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6106 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6107 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6108 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6109 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6110 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6111 */ >+ IC_EVEX_L2_KZ, /* 6112 */ >+ IC_EVEX_L2_KZ, /* 6113 */ >+ IC_EVEX_L2_XS_KZ, /* 6114 */ >+ IC_EVEX_L2_XS_KZ, /* 6115 */ >+ IC_EVEX_L2_XD_KZ, /* 6116 */ >+ IC_EVEX_L2_XD_KZ, /* 6117 */ >+ IC_EVEX_L2_XD_KZ, /* 6118 */ >+ IC_EVEX_L2_XD_KZ, /* 6119 */ >+ IC_EVEX_L2_W_KZ, /* 6120 */ >+ IC_EVEX_L2_W_KZ, /* 6121 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6122 */ >+ IC_EVEX_L2_W_XS_KZ, /* 6123 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6124 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6125 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6126 */ >+ IC_EVEX_L2_W_XD_KZ, /* 6127 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6128 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6129 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6130 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6131 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6132 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6133 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6134 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 6135 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6136 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6137 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6138 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6139 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6140 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6141 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6142 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 6143 */ >+ IC, /* 6144 */ >+ IC_64BIT, /* 6145 */ >+ IC_XS, /* 6146 */ >+ IC_64BIT_XS, /* 6147 */ >+ IC_XD, /* 6148 */ >+ IC_64BIT_XD, /* 6149 */ >+ IC_XS, /* 6150 */ >+ IC_64BIT_XS, /* 6151 */ >+ IC, /* 6152 */ >+ IC_64BIT_REXW, /* 6153 */ >+ IC_XS, /* 6154 */ >+ IC_64BIT_REXW_XS, /* 6155 */ >+ IC_XD, /* 6156 */ >+ IC_64BIT_REXW_XD, /* 6157 */ >+ IC_XS, /* 6158 */ >+ IC_64BIT_REXW_XS, /* 6159 */ >+ IC_OPSIZE, /* 6160 */ >+ IC_64BIT_OPSIZE, /* 6161 */ >+ IC_XS_OPSIZE, /* 6162 */ >+ IC_64BIT_XS_OPSIZE, /* 6163 */ >+ IC_XD_OPSIZE, /* 6164 */ >+ IC_64BIT_XD_OPSIZE, /* 6165 */ >+ IC_XS_OPSIZE, /* 6166 */ >+ IC_64BIT_XD_OPSIZE, /* 6167 */ >+ IC_OPSIZE, /* 6168 */ >+ IC_64BIT_REXW_OPSIZE, /* 6169 */ >+ IC_XS_OPSIZE, /* 6170 */ >+ IC_64BIT_REXW_XS, /* 6171 */ >+ IC_XD_OPSIZE, /* 6172 */ >+ IC_64BIT_REXW_XD, /* 6173 */ >+ IC_XS_OPSIZE, /* 6174 */ >+ IC_64BIT_REXW_XS, /* 6175 */ >+ IC_ADSIZE, /* 6176 */ >+ IC_64BIT_ADSIZE, /* 6177 */ >+ IC_XS, /* 6178 */ >+ IC_64BIT_XS, /* 6179 */ >+ IC_XD, /* 6180 */ >+ IC_64BIT_XD, /* 6181 */ >+ IC_XS, /* 6182 */ >+ IC_64BIT_XS, /* 6183 */ >+ IC_ADSIZE, /* 6184 */ >+ IC_64BIT_ADSIZE, /* 6185 */ >+ IC_XS, /* 6186 */ >+ IC_64BIT_REXW_XS, /* 6187 */ >+ IC_XD, /* 6188 */ >+ IC_64BIT_REXW_XD, /* 6189 */ >+ IC_XS, /* 6190 */ >+ IC_64BIT_REXW_XS, /* 6191 */ >+ IC_OPSIZE, /* 6192 */ >+ IC_64BIT_OPSIZE, /* 6193 */ >+ IC_XS_OPSIZE, /* 6194 */ >+ IC_64BIT_XS_OPSIZE, /* 6195 */ >+ IC_XD_OPSIZE, /* 6196 */ >+ IC_64BIT_XD_OPSIZE, /* 6197 */ >+ IC_XS_OPSIZE, /* 6198 */ >+ IC_64BIT_XD_OPSIZE, /* 6199 */ >+ IC_OPSIZE, /* 6200 */ >+ IC_64BIT_REXW_OPSIZE, /* 6201 */ >+ IC_XS_OPSIZE, /* 6202 */ >+ IC_64BIT_REXW_XS, /* 6203 */ >+ IC_XD_OPSIZE, /* 6204 */ >+ IC_64BIT_REXW_XD, /* 6205 */ >+ IC_XS_OPSIZE, /* 6206 */ >+ IC_64BIT_REXW_XS, /* 6207 */ >+ IC_VEX, /* 6208 */ >+ IC_VEX, /* 6209 */ >+ IC_VEX_XS, /* 6210 */ >+ IC_VEX_XS, /* 6211 */ >+ IC_VEX_XD, /* 6212 */ >+ IC_VEX_XD, /* 6213 */ >+ IC_VEX_XD, /* 6214 */ >+ IC_VEX_XD, /* 6215 */ >+ IC_VEX_W, /* 6216 */ >+ IC_VEX_W, /* 6217 */ >+ IC_VEX_W_XS, /* 6218 */ >+ IC_VEX_W_XS, /* 6219 */ >+ IC_VEX_W_XD, /* 6220 */ >+ IC_VEX_W_XD, /* 6221 */ >+ IC_VEX_W_XD, /* 6222 */ >+ IC_VEX_W_XD, /* 6223 */ >+ IC_VEX_OPSIZE, /* 6224 */ >+ IC_VEX_OPSIZE, /* 6225 */ >+ IC_VEX_OPSIZE, /* 6226 */ >+ IC_VEX_OPSIZE, /* 6227 */ >+ IC_VEX_OPSIZE, /* 6228 */ >+ IC_VEX_OPSIZE, /* 6229 */ >+ IC_VEX_OPSIZE, /* 6230 */ >+ IC_VEX_OPSIZE, /* 6231 */ >+ IC_VEX_W_OPSIZE, /* 6232 */ >+ IC_VEX_W_OPSIZE, /* 6233 */ >+ IC_VEX_W_OPSIZE, /* 6234 */ >+ IC_VEX_W_OPSIZE, /* 6235 */ >+ IC_VEX_W_OPSIZE, /* 6236 */ >+ IC_VEX_W_OPSIZE, /* 6237 */ >+ IC_VEX_W_OPSIZE, /* 6238 */ >+ IC_VEX_W_OPSIZE, /* 6239 */ >+ IC_VEX, /* 6240 */ >+ IC_VEX, /* 6241 */ >+ IC_VEX_XS, /* 6242 */ >+ IC_VEX_XS, /* 6243 */ >+ IC_VEX_XD, /* 6244 */ >+ IC_VEX_XD, /* 6245 */ >+ IC_VEX_XD, /* 6246 */ >+ IC_VEX_XD, /* 6247 */ >+ IC_VEX_W, /* 6248 */ >+ IC_VEX_W, /* 6249 */ >+ IC_VEX_W_XS, /* 6250 */ >+ IC_VEX_W_XS, /* 6251 */ >+ IC_VEX_W_XD, /* 6252 */ >+ IC_VEX_W_XD, /* 6253 */ >+ IC_VEX_W_XD, /* 6254 */ >+ IC_VEX_W_XD, /* 6255 */ >+ IC_VEX_OPSIZE, /* 6256 */ >+ IC_VEX_OPSIZE, /* 6257 */ >+ IC_VEX_OPSIZE, /* 6258 */ >+ IC_VEX_OPSIZE, /* 6259 */ >+ IC_VEX_OPSIZE, /* 6260 */ >+ IC_VEX_OPSIZE, /* 6261 */ >+ IC_VEX_OPSIZE, /* 6262 */ >+ IC_VEX_OPSIZE, /* 6263 */ >+ IC_VEX_W_OPSIZE, /* 6264 */ >+ IC_VEX_W_OPSIZE, /* 6265 */ >+ IC_VEX_W_OPSIZE, /* 6266 */ >+ IC_VEX_W_OPSIZE, /* 6267 */ >+ IC_VEX_W_OPSIZE, /* 6268 */ >+ IC_VEX_W_OPSIZE, /* 6269 */ >+ IC_VEX_W_OPSIZE, /* 6270 */ >+ IC_VEX_W_OPSIZE, /* 6271 */ >+ IC_VEX_L, /* 6272 */ >+ IC_VEX_L, /* 6273 */ >+ IC_VEX_L_XS, /* 6274 */ >+ IC_VEX_L_XS, /* 6275 */ >+ IC_VEX_L_XD, /* 6276 */ >+ IC_VEX_L_XD, /* 6277 */ >+ IC_VEX_L_XD, /* 6278 */ >+ IC_VEX_L_XD, /* 6279 */ >+ IC_VEX_L_W, /* 6280 */ >+ IC_VEX_L_W, /* 6281 */ >+ IC_VEX_L_W_XS, /* 6282 */ >+ IC_VEX_L_W_XS, /* 6283 */ >+ IC_VEX_L_W_XD, /* 6284 */ >+ IC_VEX_L_W_XD, /* 6285 */ >+ IC_VEX_L_W_XD, /* 6286 */ >+ IC_VEX_L_W_XD, /* 6287 */ >+ IC_VEX_L_OPSIZE, /* 6288 */ >+ IC_VEX_L_OPSIZE, /* 6289 */ >+ IC_VEX_L_OPSIZE, /* 6290 */ >+ IC_VEX_L_OPSIZE, /* 6291 */ >+ IC_VEX_L_OPSIZE, /* 6292 */ >+ IC_VEX_L_OPSIZE, /* 6293 */ >+ IC_VEX_L_OPSIZE, /* 6294 */ >+ IC_VEX_L_OPSIZE, /* 6295 */ >+ IC_VEX_L_W_OPSIZE, /* 6296 */ >+ IC_VEX_L_W_OPSIZE, /* 6297 */ >+ IC_VEX_L_W_OPSIZE, /* 6298 */ >+ IC_VEX_L_W_OPSIZE, /* 6299 */ >+ IC_VEX_L_W_OPSIZE, /* 6300 */ >+ IC_VEX_L_W_OPSIZE, /* 6301 */ >+ IC_VEX_L_W_OPSIZE, /* 6302 */ >+ IC_VEX_L_W_OPSIZE, /* 6303 */ >+ IC_VEX_L, /* 6304 */ >+ IC_VEX_L, /* 6305 */ >+ IC_VEX_L_XS, /* 6306 */ >+ IC_VEX_L_XS, /* 6307 */ >+ IC_VEX_L_XD, /* 6308 */ >+ IC_VEX_L_XD, /* 6309 */ >+ IC_VEX_L_XD, /* 6310 */ >+ IC_VEX_L_XD, /* 6311 */ >+ IC_VEX_L_W, /* 6312 */ >+ IC_VEX_L_W, /* 6313 */ >+ IC_VEX_L_W_XS, /* 6314 */ >+ IC_VEX_L_W_XS, /* 6315 */ >+ IC_VEX_L_W_XD, /* 6316 */ >+ IC_VEX_L_W_XD, /* 6317 */ >+ IC_VEX_L_W_XD, /* 6318 */ >+ IC_VEX_L_W_XD, /* 6319 */ >+ IC_VEX_L_OPSIZE, /* 6320 */ >+ IC_VEX_L_OPSIZE, /* 6321 */ >+ IC_VEX_L_OPSIZE, /* 6322 */ >+ IC_VEX_L_OPSIZE, /* 6323 */ >+ IC_VEX_L_OPSIZE, /* 6324 */ >+ IC_VEX_L_OPSIZE, /* 6325 */ >+ IC_VEX_L_OPSIZE, /* 6326 */ >+ IC_VEX_L_OPSIZE, /* 6327 */ >+ IC_VEX_L_W_OPSIZE, /* 6328 */ >+ IC_VEX_L_W_OPSIZE, /* 6329 */ >+ IC_VEX_L_W_OPSIZE, /* 6330 */ >+ IC_VEX_L_W_OPSIZE, /* 6331 */ >+ IC_VEX_L_W_OPSIZE, /* 6332 */ >+ IC_VEX_L_W_OPSIZE, /* 6333 */ >+ IC_VEX_L_W_OPSIZE, /* 6334 */ >+ IC_VEX_L_W_OPSIZE, /* 6335 */ >+ IC_VEX_L, /* 6336 */ >+ IC_VEX_L, /* 6337 */ >+ IC_VEX_L_XS, /* 6338 */ >+ IC_VEX_L_XS, /* 6339 */ >+ IC_VEX_L_XD, /* 6340 */ >+ IC_VEX_L_XD, /* 6341 */ >+ IC_VEX_L_XD, /* 6342 */ >+ IC_VEX_L_XD, /* 6343 */ >+ IC_VEX_L_W, /* 6344 */ >+ IC_VEX_L_W, /* 6345 */ >+ IC_VEX_L_W_XS, /* 6346 */ >+ IC_VEX_L_W_XS, /* 6347 */ >+ IC_VEX_L_W_XD, /* 6348 */ >+ IC_VEX_L_W_XD, /* 6349 */ >+ IC_VEX_L_W_XD, /* 6350 */ >+ IC_VEX_L_W_XD, /* 6351 */ >+ IC_VEX_L_OPSIZE, /* 6352 */ >+ IC_VEX_L_OPSIZE, /* 6353 */ >+ IC_VEX_L_OPSIZE, /* 6354 */ >+ IC_VEX_L_OPSIZE, /* 6355 */ >+ IC_VEX_L_OPSIZE, /* 6356 */ >+ IC_VEX_L_OPSIZE, /* 6357 */ >+ IC_VEX_L_OPSIZE, /* 6358 */ >+ IC_VEX_L_OPSIZE, /* 6359 */ >+ IC_VEX_L_W_OPSIZE, /* 6360 */ >+ IC_VEX_L_W_OPSIZE, /* 6361 */ >+ IC_VEX_L_W_OPSIZE, /* 6362 */ >+ IC_VEX_L_W_OPSIZE, /* 6363 */ >+ IC_VEX_L_W_OPSIZE, /* 6364 */ >+ IC_VEX_L_W_OPSIZE, /* 6365 */ >+ IC_VEX_L_W_OPSIZE, /* 6366 */ >+ IC_VEX_L_W_OPSIZE, /* 6367 */ >+ IC_VEX_L, /* 6368 */ >+ IC_VEX_L, /* 6369 */ >+ IC_VEX_L_XS, /* 6370 */ >+ IC_VEX_L_XS, /* 6371 */ >+ IC_VEX_L_XD, /* 6372 */ >+ IC_VEX_L_XD, /* 6373 */ >+ IC_VEX_L_XD, /* 6374 */ >+ IC_VEX_L_XD, /* 6375 */ >+ IC_VEX_L_W, /* 6376 */ >+ IC_VEX_L_W, /* 6377 */ >+ IC_VEX_L_W_XS, /* 6378 */ >+ IC_VEX_L_W_XS, /* 6379 */ >+ IC_VEX_L_W_XD, /* 6380 */ >+ IC_VEX_L_W_XD, /* 6381 */ >+ IC_VEX_L_W_XD, /* 6382 */ >+ IC_VEX_L_W_XD, /* 6383 */ >+ IC_VEX_L_OPSIZE, /* 6384 */ >+ IC_VEX_L_OPSIZE, /* 6385 */ >+ IC_VEX_L_OPSIZE, /* 6386 */ >+ IC_VEX_L_OPSIZE, /* 6387 */ >+ IC_VEX_L_OPSIZE, /* 6388 */ >+ IC_VEX_L_OPSIZE, /* 6389 */ >+ IC_VEX_L_OPSIZE, /* 6390 */ >+ IC_VEX_L_OPSIZE, /* 6391 */ >+ IC_VEX_L_W_OPSIZE, /* 6392 */ >+ IC_VEX_L_W_OPSIZE, /* 6393 */ >+ IC_VEX_L_W_OPSIZE, /* 6394 */ >+ IC_VEX_L_W_OPSIZE, /* 6395 */ >+ IC_VEX_L_W_OPSIZE, /* 6396 */ >+ IC_VEX_L_W_OPSIZE, /* 6397 */ >+ IC_VEX_L_W_OPSIZE, /* 6398 */ >+ IC_VEX_L_W_OPSIZE, /* 6399 */ >+ IC_EVEX_KZ, /* 6400 */ >+ IC_EVEX_KZ, /* 6401 */ >+ IC_EVEX_XS_KZ, /* 6402 */ >+ IC_EVEX_XS_KZ, /* 6403 */ >+ IC_EVEX_XD_KZ, /* 6404 */ >+ IC_EVEX_XD_KZ, /* 6405 */ >+ IC_EVEX_XD_KZ, /* 6406 */ >+ IC_EVEX_XD_KZ, /* 6407 */ >+ IC_EVEX_W_KZ, /* 6408 */ >+ IC_EVEX_W_KZ, /* 6409 */ >+ IC_EVEX_W_XS_KZ, /* 6410 */ >+ IC_EVEX_W_XS_KZ, /* 6411 */ >+ IC_EVEX_W_XD_KZ, /* 6412 */ >+ IC_EVEX_W_XD_KZ, /* 6413 */ >+ IC_EVEX_W_XD_KZ, /* 6414 */ >+ IC_EVEX_W_XD_KZ, /* 6415 */ >+ IC_EVEX_OPSIZE_KZ, /* 6416 */ >+ IC_EVEX_OPSIZE_KZ, /* 6417 */ >+ IC_EVEX_OPSIZE_KZ, /* 6418 */ >+ IC_EVEX_OPSIZE_KZ, /* 6419 */ >+ IC_EVEX_OPSIZE_KZ, /* 6420 */ >+ IC_EVEX_OPSIZE_KZ, /* 6421 */ >+ IC_EVEX_OPSIZE_KZ, /* 6422 */ >+ IC_EVEX_OPSIZE_KZ, /* 6423 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6424 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6425 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6426 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6427 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6428 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6429 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6430 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6431 */ >+ IC_EVEX_KZ, /* 6432 */ >+ IC_EVEX_KZ, /* 6433 */ >+ IC_EVEX_XS_KZ, /* 6434 */ >+ IC_EVEX_XS_KZ, /* 6435 */ >+ IC_EVEX_XD_KZ, /* 6436 */ >+ IC_EVEX_XD_KZ, /* 6437 */ >+ IC_EVEX_XD_KZ, /* 6438 */ >+ IC_EVEX_XD_KZ, /* 6439 */ >+ IC_EVEX_W_KZ, /* 6440 */ >+ IC_EVEX_W_KZ, /* 6441 */ >+ IC_EVEX_W_XS_KZ, /* 6442 */ >+ IC_EVEX_W_XS_KZ, /* 6443 */ >+ IC_EVEX_W_XD_KZ, /* 6444 */ >+ IC_EVEX_W_XD_KZ, /* 6445 */ >+ IC_EVEX_W_XD_KZ, /* 6446 */ >+ IC_EVEX_W_XD_KZ, /* 6447 */ >+ IC_EVEX_OPSIZE_KZ, /* 6448 */ >+ IC_EVEX_OPSIZE_KZ, /* 6449 */ >+ IC_EVEX_OPSIZE_KZ, /* 6450 */ >+ IC_EVEX_OPSIZE_KZ, /* 6451 */ >+ IC_EVEX_OPSIZE_KZ, /* 6452 */ >+ IC_EVEX_OPSIZE_KZ, /* 6453 */ >+ IC_EVEX_OPSIZE_KZ, /* 6454 */ >+ IC_EVEX_OPSIZE_KZ, /* 6455 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6456 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6457 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6458 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6459 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6460 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6461 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6462 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6463 */ >+ IC_EVEX_KZ, /* 6464 */ >+ IC_EVEX_KZ, /* 6465 */ >+ IC_EVEX_XS_KZ, /* 6466 */ >+ IC_EVEX_XS_KZ, /* 6467 */ >+ IC_EVEX_XD_KZ, /* 6468 */ >+ IC_EVEX_XD_KZ, /* 6469 */ >+ IC_EVEX_XD_KZ, /* 6470 */ >+ IC_EVEX_XD_KZ, /* 6471 */ >+ IC_EVEX_W_KZ, /* 6472 */ >+ IC_EVEX_W_KZ, /* 6473 */ >+ IC_EVEX_W_XS_KZ, /* 6474 */ >+ IC_EVEX_W_XS_KZ, /* 6475 */ >+ IC_EVEX_W_XD_KZ, /* 6476 */ >+ IC_EVEX_W_XD_KZ, /* 6477 */ >+ IC_EVEX_W_XD_KZ, /* 6478 */ >+ IC_EVEX_W_XD_KZ, /* 6479 */ >+ IC_EVEX_OPSIZE_KZ, /* 6480 */ >+ IC_EVEX_OPSIZE_KZ, /* 6481 */ >+ IC_EVEX_OPSIZE_KZ, /* 6482 */ >+ IC_EVEX_OPSIZE_KZ, /* 6483 */ >+ IC_EVEX_OPSIZE_KZ, /* 6484 */ >+ IC_EVEX_OPSIZE_KZ, /* 6485 */ >+ IC_EVEX_OPSIZE_KZ, /* 6486 */ >+ IC_EVEX_OPSIZE_KZ, /* 6487 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6488 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6489 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6490 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6491 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6492 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6493 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6494 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6495 */ >+ IC_EVEX_KZ, /* 6496 */ >+ IC_EVEX_KZ, /* 6497 */ >+ IC_EVEX_XS_KZ, /* 6498 */ >+ IC_EVEX_XS_KZ, /* 6499 */ >+ IC_EVEX_XD_KZ, /* 6500 */ >+ IC_EVEX_XD_KZ, /* 6501 */ >+ IC_EVEX_XD_KZ, /* 6502 */ >+ IC_EVEX_XD_KZ, /* 6503 */ >+ IC_EVEX_W_KZ, /* 6504 */ >+ IC_EVEX_W_KZ, /* 6505 */ >+ IC_EVEX_W_XS_KZ, /* 6506 */ >+ IC_EVEX_W_XS_KZ, /* 6507 */ >+ IC_EVEX_W_XD_KZ, /* 6508 */ >+ IC_EVEX_W_XD_KZ, /* 6509 */ >+ IC_EVEX_W_XD_KZ, /* 6510 */ >+ IC_EVEX_W_XD_KZ, /* 6511 */ >+ IC_EVEX_OPSIZE_KZ, /* 6512 */ >+ IC_EVEX_OPSIZE_KZ, /* 6513 */ >+ IC_EVEX_OPSIZE_KZ, /* 6514 */ >+ IC_EVEX_OPSIZE_KZ, /* 6515 */ >+ IC_EVEX_OPSIZE_KZ, /* 6516 */ >+ IC_EVEX_OPSIZE_KZ, /* 6517 */ >+ IC_EVEX_OPSIZE_KZ, /* 6518 */ >+ IC_EVEX_OPSIZE_KZ, /* 6519 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6520 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6521 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6522 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6523 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6524 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6525 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6526 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6527 */ >+ IC_EVEX_KZ, /* 6528 */ >+ IC_EVEX_KZ, /* 6529 */ >+ IC_EVEX_XS_KZ, /* 6530 */ >+ IC_EVEX_XS_KZ, /* 6531 */ >+ IC_EVEX_XD_KZ, /* 6532 */ >+ IC_EVEX_XD_KZ, /* 6533 */ >+ IC_EVEX_XD_KZ, /* 6534 */ >+ IC_EVEX_XD_KZ, /* 6535 */ >+ IC_EVEX_W_KZ, /* 6536 */ >+ IC_EVEX_W_KZ, /* 6537 */ >+ IC_EVEX_W_XS_KZ, /* 6538 */ >+ IC_EVEX_W_XS_KZ, /* 6539 */ >+ IC_EVEX_W_XD_KZ, /* 6540 */ >+ IC_EVEX_W_XD_KZ, /* 6541 */ >+ IC_EVEX_W_XD_KZ, /* 6542 */ >+ IC_EVEX_W_XD_KZ, /* 6543 */ >+ IC_EVEX_OPSIZE_KZ, /* 6544 */ >+ IC_EVEX_OPSIZE_KZ, /* 6545 */ >+ IC_EVEX_OPSIZE_KZ, /* 6546 */ >+ IC_EVEX_OPSIZE_KZ, /* 6547 */ >+ IC_EVEX_OPSIZE_KZ, /* 6548 */ >+ IC_EVEX_OPSIZE_KZ, /* 6549 */ >+ IC_EVEX_OPSIZE_KZ, /* 6550 */ >+ IC_EVEX_OPSIZE_KZ, /* 6551 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6552 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6553 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6554 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6555 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6556 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6557 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6558 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6559 */ >+ IC_EVEX_KZ, /* 6560 */ >+ IC_EVEX_KZ, /* 6561 */ >+ IC_EVEX_XS_KZ, /* 6562 */ >+ IC_EVEX_XS_KZ, /* 6563 */ >+ IC_EVEX_XD_KZ, /* 6564 */ >+ IC_EVEX_XD_KZ, /* 6565 */ >+ IC_EVEX_XD_KZ, /* 6566 */ >+ IC_EVEX_XD_KZ, /* 6567 */ >+ IC_EVEX_W_KZ, /* 6568 */ >+ IC_EVEX_W_KZ, /* 6569 */ >+ IC_EVEX_W_XS_KZ, /* 6570 */ >+ IC_EVEX_W_XS_KZ, /* 6571 */ >+ IC_EVEX_W_XD_KZ, /* 6572 */ >+ IC_EVEX_W_XD_KZ, /* 6573 */ >+ IC_EVEX_W_XD_KZ, /* 6574 */ >+ IC_EVEX_W_XD_KZ, /* 6575 */ >+ IC_EVEX_OPSIZE_KZ, /* 6576 */ >+ IC_EVEX_OPSIZE_KZ, /* 6577 */ >+ IC_EVEX_OPSIZE_KZ, /* 6578 */ >+ IC_EVEX_OPSIZE_KZ, /* 6579 */ >+ IC_EVEX_OPSIZE_KZ, /* 6580 */ >+ IC_EVEX_OPSIZE_KZ, /* 6581 */ >+ IC_EVEX_OPSIZE_KZ, /* 6582 */ >+ IC_EVEX_OPSIZE_KZ, /* 6583 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6584 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6585 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6586 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6587 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6588 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6589 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6590 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6591 */ >+ IC_EVEX_KZ, /* 6592 */ >+ IC_EVEX_KZ, /* 6593 */ >+ IC_EVEX_XS_KZ, /* 6594 */ >+ IC_EVEX_XS_KZ, /* 6595 */ >+ IC_EVEX_XD_KZ, /* 6596 */ >+ IC_EVEX_XD_KZ, /* 6597 */ >+ IC_EVEX_XD_KZ, /* 6598 */ >+ IC_EVEX_XD_KZ, /* 6599 */ >+ IC_EVEX_W_KZ, /* 6600 */ >+ IC_EVEX_W_KZ, /* 6601 */ >+ IC_EVEX_W_XS_KZ, /* 6602 */ >+ IC_EVEX_W_XS_KZ, /* 6603 */ >+ IC_EVEX_W_XD_KZ, /* 6604 */ >+ IC_EVEX_W_XD_KZ, /* 6605 */ >+ IC_EVEX_W_XD_KZ, /* 6606 */ >+ IC_EVEX_W_XD_KZ, /* 6607 */ >+ IC_EVEX_OPSIZE_KZ, /* 6608 */ >+ IC_EVEX_OPSIZE_KZ, /* 6609 */ >+ IC_EVEX_OPSIZE_KZ, /* 6610 */ >+ IC_EVEX_OPSIZE_KZ, /* 6611 */ >+ IC_EVEX_OPSIZE_KZ, /* 6612 */ >+ IC_EVEX_OPSIZE_KZ, /* 6613 */ >+ IC_EVEX_OPSIZE_KZ, /* 6614 */ >+ IC_EVEX_OPSIZE_KZ, /* 6615 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6616 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6617 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6618 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6619 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6620 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6621 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6622 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6623 */ >+ IC_EVEX_KZ, /* 6624 */ >+ IC_EVEX_KZ, /* 6625 */ >+ IC_EVEX_XS_KZ, /* 6626 */ >+ IC_EVEX_XS_KZ, /* 6627 */ >+ IC_EVEX_XD_KZ, /* 6628 */ >+ IC_EVEX_XD_KZ, /* 6629 */ >+ IC_EVEX_XD_KZ, /* 6630 */ >+ IC_EVEX_XD_KZ, /* 6631 */ >+ IC_EVEX_W_KZ, /* 6632 */ >+ IC_EVEX_W_KZ, /* 6633 */ >+ IC_EVEX_W_XS_KZ, /* 6634 */ >+ IC_EVEX_W_XS_KZ, /* 6635 */ >+ IC_EVEX_W_XD_KZ, /* 6636 */ >+ IC_EVEX_W_XD_KZ, /* 6637 */ >+ IC_EVEX_W_XD_KZ, /* 6638 */ >+ IC_EVEX_W_XD_KZ, /* 6639 */ >+ IC_EVEX_OPSIZE_KZ, /* 6640 */ >+ IC_EVEX_OPSIZE_KZ, /* 6641 */ >+ IC_EVEX_OPSIZE_KZ, /* 6642 */ >+ IC_EVEX_OPSIZE_KZ, /* 6643 */ >+ IC_EVEX_OPSIZE_KZ, /* 6644 */ >+ IC_EVEX_OPSIZE_KZ, /* 6645 */ >+ IC_EVEX_OPSIZE_KZ, /* 6646 */ >+ IC_EVEX_OPSIZE_KZ, /* 6647 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6648 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6649 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6650 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6651 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6652 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6653 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6654 */ >+ IC_EVEX_W_OPSIZE_KZ, /* 6655 */ >+ IC, /* 6656 */ >+ IC_64BIT, /* 6657 */ >+ IC_XS, /* 6658 */ >+ IC_64BIT_XS, /* 6659 */ >+ IC_XD, /* 6660 */ >+ IC_64BIT_XD, /* 6661 */ >+ IC_XS, /* 6662 */ >+ IC_64BIT_XS, /* 6663 */ >+ IC, /* 6664 */ >+ IC_64BIT_REXW, /* 6665 */ >+ IC_XS, /* 6666 */ >+ IC_64BIT_REXW_XS, /* 6667 */ >+ IC_XD, /* 6668 */ >+ IC_64BIT_REXW_XD, /* 6669 */ >+ IC_XS, /* 6670 */ >+ IC_64BIT_REXW_XS, /* 6671 */ >+ IC_OPSIZE, /* 6672 */ >+ IC_64BIT_OPSIZE, /* 6673 */ >+ IC_XS_OPSIZE, /* 6674 */ >+ IC_64BIT_XS_OPSIZE, /* 6675 */ >+ IC_XD_OPSIZE, /* 6676 */ >+ IC_64BIT_XD_OPSIZE, /* 6677 */ >+ IC_XS_OPSIZE, /* 6678 */ >+ IC_64BIT_XD_OPSIZE, /* 6679 */ >+ IC_OPSIZE, /* 6680 */ >+ IC_64BIT_REXW_OPSIZE, /* 6681 */ >+ IC_XS_OPSIZE, /* 6682 */ >+ IC_64BIT_REXW_XS, /* 6683 */ >+ IC_XD_OPSIZE, /* 6684 */ >+ IC_64BIT_REXW_XD, /* 6685 */ >+ IC_XS_OPSIZE, /* 6686 */ >+ IC_64BIT_REXW_XS, /* 6687 */ >+ IC_ADSIZE, /* 6688 */ >+ IC_64BIT_ADSIZE, /* 6689 */ >+ IC_XS, /* 6690 */ >+ IC_64BIT_XS, /* 6691 */ >+ IC_XD, /* 6692 */ >+ IC_64BIT_XD, /* 6693 */ >+ IC_XS, /* 6694 */ >+ IC_64BIT_XS, /* 6695 */ >+ IC_ADSIZE, /* 6696 */ >+ IC_64BIT_ADSIZE, /* 6697 */ >+ IC_XS, /* 6698 */ >+ IC_64BIT_REXW_XS, /* 6699 */ >+ IC_XD, /* 6700 */ >+ IC_64BIT_REXW_XD, /* 6701 */ >+ IC_XS, /* 6702 */ >+ IC_64BIT_REXW_XS, /* 6703 */ >+ IC_OPSIZE, /* 6704 */ >+ IC_64BIT_OPSIZE, /* 6705 */ >+ IC_XS_OPSIZE, /* 6706 */ >+ IC_64BIT_XS_OPSIZE, /* 6707 */ >+ IC_XD_OPSIZE, /* 6708 */ >+ IC_64BIT_XD_OPSIZE, /* 6709 */ >+ IC_XS_OPSIZE, /* 6710 */ >+ IC_64BIT_XD_OPSIZE, /* 6711 */ >+ IC_OPSIZE, /* 6712 */ >+ IC_64BIT_REXW_OPSIZE, /* 6713 */ >+ IC_XS_OPSIZE, /* 6714 */ >+ IC_64BIT_REXW_XS, /* 6715 */ >+ IC_XD_OPSIZE, /* 6716 */ >+ IC_64BIT_REXW_XD, /* 6717 */ >+ IC_XS_OPSIZE, /* 6718 */ >+ IC_64BIT_REXW_XS, /* 6719 */ >+ IC_VEX, /* 6720 */ >+ IC_VEX, /* 6721 */ >+ IC_VEX_XS, /* 6722 */ >+ IC_VEX_XS, /* 6723 */ >+ IC_VEX_XD, /* 6724 */ >+ IC_VEX_XD, /* 6725 */ >+ IC_VEX_XD, /* 6726 */ >+ IC_VEX_XD, /* 6727 */ >+ IC_VEX_W, /* 6728 */ >+ IC_VEX_W, /* 6729 */ >+ IC_VEX_W_XS, /* 6730 */ >+ IC_VEX_W_XS, /* 6731 */ >+ IC_VEX_W_XD, /* 6732 */ >+ IC_VEX_W_XD, /* 6733 */ >+ IC_VEX_W_XD, /* 6734 */ >+ IC_VEX_W_XD, /* 6735 */ >+ IC_VEX_OPSIZE, /* 6736 */ >+ IC_VEX_OPSIZE, /* 6737 */ >+ IC_VEX_OPSIZE, /* 6738 */ >+ IC_VEX_OPSIZE, /* 6739 */ >+ IC_VEX_OPSIZE, /* 6740 */ >+ IC_VEX_OPSIZE, /* 6741 */ >+ IC_VEX_OPSIZE, /* 6742 */ >+ IC_VEX_OPSIZE, /* 6743 */ >+ IC_VEX_W_OPSIZE, /* 6744 */ >+ IC_VEX_W_OPSIZE, /* 6745 */ >+ IC_VEX_W_OPSIZE, /* 6746 */ >+ IC_VEX_W_OPSIZE, /* 6747 */ >+ IC_VEX_W_OPSIZE, /* 6748 */ >+ IC_VEX_W_OPSIZE, /* 6749 */ >+ IC_VEX_W_OPSIZE, /* 6750 */ >+ IC_VEX_W_OPSIZE, /* 6751 */ >+ IC_VEX, /* 6752 */ >+ IC_VEX, /* 6753 */ >+ IC_VEX_XS, /* 6754 */ >+ IC_VEX_XS, /* 6755 */ >+ IC_VEX_XD, /* 6756 */ >+ IC_VEX_XD, /* 6757 */ >+ IC_VEX_XD, /* 6758 */ >+ IC_VEX_XD, /* 6759 */ >+ IC_VEX_W, /* 6760 */ >+ IC_VEX_W, /* 6761 */ >+ IC_VEX_W_XS, /* 6762 */ >+ IC_VEX_W_XS, /* 6763 */ >+ IC_VEX_W_XD, /* 6764 */ >+ IC_VEX_W_XD, /* 6765 */ >+ IC_VEX_W_XD, /* 6766 */ >+ IC_VEX_W_XD, /* 6767 */ >+ IC_VEX_OPSIZE, /* 6768 */ >+ IC_VEX_OPSIZE, /* 6769 */ >+ IC_VEX_OPSIZE, /* 6770 */ >+ IC_VEX_OPSIZE, /* 6771 */ >+ IC_VEX_OPSIZE, /* 6772 */ >+ IC_VEX_OPSIZE, /* 6773 */ >+ IC_VEX_OPSIZE, /* 6774 */ >+ IC_VEX_OPSIZE, /* 6775 */ >+ IC_VEX_W_OPSIZE, /* 6776 */ >+ IC_VEX_W_OPSIZE, /* 6777 */ >+ IC_VEX_W_OPSIZE, /* 6778 */ >+ IC_VEX_W_OPSIZE, /* 6779 */ >+ IC_VEX_W_OPSIZE, /* 6780 */ >+ IC_VEX_W_OPSIZE, /* 6781 */ >+ IC_VEX_W_OPSIZE, /* 6782 */ >+ IC_VEX_W_OPSIZE, /* 6783 */ >+ IC_VEX_L, /* 6784 */ >+ IC_VEX_L, /* 6785 */ >+ IC_VEX_L_XS, /* 6786 */ >+ IC_VEX_L_XS, /* 6787 */ >+ IC_VEX_L_XD, /* 6788 */ >+ IC_VEX_L_XD, /* 6789 */ >+ IC_VEX_L_XD, /* 6790 */ >+ IC_VEX_L_XD, /* 6791 */ >+ IC_VEX_L_W, /* 6792 */ >+ IC_VEX_L_W, /* 6793 */ >+ IC_VEX_L_W_XS, /* 6794 */ >+ IC_VEX_L_W_XS, /* 6795 */ >+ IC_VEX_L_W_XD, /* 6796 */ >+ IC_VEX_L_W_XD, /* 6797 */ >+ IC_VEX_L_W_XD, /* 6798 */ >+ IC_VEX_L_W_XD, /* 6799 */ >+ IC_VEX_L_OPSIZE, /* 6800 */ >+ IC_VEX_L_OPSIZE, /* 6801 */ >+ IC_VEX_L_OPSIZE, /* 6802 */ >+ IC_VEX_L_OPSIZE, /* 6803 */ >+ IC_VEX_L_OPSIZE, /* 6804 */ >+ IC_VEX_L_OPSIZE, /* 6805 */ >+ IC_VEX_L_OPSIZE, /* 6806 */ >+ IC_VEX_L_OPSIZE, /* 6807 */ >+ IC_VEX_L_W_OPSIZE, /* 6808 */ >+ IC_VEX_L_W_OPSIZE, /* 6809 */ >+ IC_VEX_L_W_OPSIZE, /* 6810 */ >+ IC_VEX_L_W_OPSIZE, /* 6811 */ >+ IC_VEX_L_W_OPSIZE, /* 6812 */ >+ IC_VEX_L_W_OPSIZE, /* 6813 */ >+ IC_VEX_L_W_OPSIZE, /* 6814 */ >+ IC_VEX_L_W_OPSIZE, /* 6815 */ >+ IC_VEX_L, /* 6816 */ >+ IC_VEX_L, /* 6817 */ >+ IC_VEX_L_XS, /* 6818 */ >+ IC_VEX_L_XS, /* 6819 */ >+ IC_VEX_L_XD, /* 6820 */ >+ IC_VEX_L_XD, /* 6821 */ >+ IC_VEX_L_XD, /* 6822 */ >+ IC_VEX_L_XD, /* 6823 */ >+ IC_VEX_L_W, /* 6824 */ >+ IC_VEX_L_W, /* 6825 */ >+ IC_VEX_L_W_XS, /* 6826 */ >+ IC_VEX_L_W_XS, /* 6827 */ >+ IC_VEX_L_W_XD, /* 6828 */ >+ IC_VEX_L_W_XD, /* 6829 */ >+ IC_VEX_L_W_XD, /* 6830 */ >+ IC_VEX_L_W_XD, /* 6831 */ >+ IC_VEX_L_OPSIZE, /* 6832 */ >+ IC_VEX_L_OPSIZE, /* 6833 */ >+ IC_VEX_L_OPSIZE, /* 6834 */ >+ IC_VEX_L_OPSIZE, /* 6835 */ >+ IC_VEX_L_OPSIZE, /* 6836 */ >+ IC_VEX_L_OPSIZE, /* 6837 */ >+ IC_VEX_L_OPSIZE, /* 6838 */ >+ IC_VEX_L_OPSIZE, /* 6839 */ >+ IC_VEX_L_W_OPSIZE, /* 6840 */ >+ IC_VEX_L_W_OPSIZE, /* 6841 */ >+ IC_VEX_L_W_OPSIZE, /* 6842 */ >+ IC_VEX_L_W_OPSIZE, /* 6843 */ >+ IC_VEX_L_W_OPSIZE, /* 6844 */ >+ IC_VEX_L_W_OPSIZE, /* 6845 */ >+ IC_VEX_L_W_OPSIZE, /* 6846 */ >+ IC_VEX_L_W_OPSIZE, /* 6847 */ >+ IC_VEX_L, /* 6848 */ >+ IC_VEX_L, /* 6849 */ >+ IC_VEX_L_XS, /* 6850 */ >+ IC_VEX_L_XS, /* 6851 */ >+ IC_VEX_L_XD, /* 6852 */ >+ IC_VEX_L_XD, /* 6853 */ >+ IC_VEX_L_XD, /* 6854 */ >+ IC_VEX_L_XD, /* 6855 */ >+ IC_VEX_L_W, /* 6856 */ >+ IC_VEX_L_W, /* 6857 */ >+ IC_VEX_L_W_XS, /* 6858 */ >+ IC_VEX_L_W_XS, /* 6859 */ >+ IC_VEX_L_W_XD, /* 6860 */ >+ IC_VEX_L_W_XD, /* 6861 */ >+ IC_VEX_L_W_XD, /* 6862 */ >+ IC_VEX_L_W_XD, /* 6863 */ >+ IC_VEX_L_OPSIZE, /* 6864 */ >+ IC_VEX_L_OPSIZE, /* 6865 */ >+ IC_VEX_L_OPSIZE, /* 6866 */ >+ IC_VEX_L_OPSIZE, /* 6867 */ >+ IC_VEX_L_OPSIZE, /* 6868 */ >+ IC_VEX_L_OPSIZE, /* 6869 */ >+ IC_VEX_L_OPSIZE, /* 6870 */ >+ IC_VEX_L_OPSIZE, /* 6871 */ >+ IC_VEX_L_W_OPSIZE, /* 6872 */ >+ IC_VEX_L_W_OPSIZE, /* 6873 */ >+ IC_VEX_L_W_OPSIZE, /* 6874 */ >+ IC_VEX_L_W_OPSIZE, /* 6875 */ >+ IC_VEX_L_W_OPSIZE, /* 6876 */ >+ IC_VEX_L_W_OPSIZE, /* 6877 */ >+ IC_VEX_L_W_OPSIZE, /* 6878 */ >+ IC_VEX_L_W_OPSIZE, /* 6879 */ >+ IC_VEX_L, /* 6880 */ >+ IC_VEX_L, /* 6881 */ >+ IC_VEX_L_XS, /* 6882 */ >+ IC_VEX_L_XS, /* 6883 */ >+ IC_VEX_L_XD, /* 6884 */ >+ IC_VEX_L_XD, /* 6885 */ >+ IC_VEX_L_XD, /* 6886 */ >+ IC_VEX_L_XD, /* 6887 */ >+ IC_VEX_L_W, /* 6888 */ >+ IC_VEX_L_W, /* 6889 */ >+ IC_VEX_L_W_XS, /* 6890 */ >+ IC_VEX_L_W_XS, /* 6891 */ >+ IC_VEX_L_W_XD, /* 6892 */ >+ IC_VEX_L_W_XD, /* 6893 */ >+ IC_VEX_L_W_XD, /* 6894 */ >+ IC_VEX_L_W_XD, /* 6895 */ >+ IC_VEX_L_OPSIZE, /* 6896 */ >+ IC_VEX_L_OPSIZE, /* 6897 */ >+ IC_VEX_L_OPSIZE, /* 6898 */ >+ IC_VEX_L_OPSIZE, /* 6899 */ >+ IC_VEX_L_OPSIZE, /* 6900 */ >+ IC_VEX_L_OPSIZE, /* 6901 */ >+ IC_VEX_L_OPSIZE, /* 6902 */ >+ IC_VEX_L_OPSIZE, /* 6903 */ >+ IC_VEX_L_W_OPSIZE, /* 6904 */ >+ IC_VEX_L_W_OPSIZE, /* 6905 */ >+ IC_VEX_L_W_OPSIZE, /* 6906 */ >+ IC_VEX_L_W_OPSIZE, /* 6907 */ >+ IC_VEX_L_W_OPSIZE, /* 6908 */ >+ IC_VEX_L_W_OPSIZE, /* 6909 */ >+ IC_VEX_L_W_OPSIZE, /* 6910 */ >+ IC_VEX_L_W_OPSIZE, /* 6911 */ >+ IC_EVEX_L_KZ, /* 6912 */ >+ IC_EVEX_L_KZ, /* 6913 */ >+ IC_EVEX_L_XS_KZ, /* 6914 */ >+ IC_EVEX_L_XS_KZ, /* 6915 */ >+ IC_EVEX_L_XD_KZ, /* 6916 */ >+ IC_EVEX_L_XD_KZ, /* 6917 */ >+ IC_EVEX_L_XD_KZ, /* 6918 */ >+ IC_EVEX_L_XD_KZ, /* 6919 */ >+ IC_EVEX_L_W_KZ, /* 6920 */ >+ IC_EVEX_L_W_KZ, /* 6921 */ >+ IC_EVEX_L_W_XS_KZ, /* 6922 */ >+ IC_EVEX_L_W_XS_KZ, /* 6923 */ >+ IC_EVEX_L_W_XD_KZ, /* 6924 */ >+ IC_EVEX_L_W_XD_KZ, /* 6925 */ >+ IC_EVEX_L_W_XD_KZ, /* 6926 */ >+ IC_EVEX_L_W_XD_KZ, /* 6927 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6928 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6929 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6930 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6931 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6932 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6933 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6934 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6935 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6936 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6937 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6938 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6939 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6940 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6941 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6942 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6943 */ >+ IC_EVEX_L_KZ, /* 6944 */ >+ IC_EVEX_L_KZ, /* 6945 */ >+ IC_EVEX_L_XS_KZ, /* 6946 */ >+ IC_EVEX_L_XS_KZ, /* 6947 */ >+ IC_EVEX_L_XD_KZ, /* 6948 */ >+ IC_EVEX_L_XD_KZ, /* 6949 */ >+ IC_EVEX_L_XD_KZ, /* 6950 */ >+ IC_EVEX_L_XD_KZ, /* 6951 */ >+ IC_EVEX_L_W_KZ, /* 6952 */ >+ IC_EVEX_L_W_KZ, /* 6953 */ >+ IC_EVEX_L_W_XS_KZ, /* 6954 */ >+ IC_EVEX_L_W_XS_KZ, /* 6955 */ >+ IC_EVEX_L_W_XD_KZ, /* 6956 */ >+ IC_EVEX_L_W_XD_KZ, /* 6957 */ >+ IC_EVEX_L_W_XD_KZ, /* 6958 */ >+ IC_EVEX_L_W_XD_KZ, /* 6959 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6960 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6961 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6962 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6963 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6964 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6965 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6966 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6967 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6968 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6969 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6970 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6971 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6972 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6973 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6974 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 6975 */ >+ IC_EVEX_L_KZ, /* 6976 */ >+ IC_EVEX_L_KZ, /* 6977 */ >+ IC_EVEX_L_XS_KZ, /* 6978 */ >+ IC_EVEX_L_XS_KZ, /* 6979 */ >+ IC_EVEX_L_XD_KZ, /* 6980 */ >+ IC_EVEX_L_XD_KZ, /* 6981 */ >+ IC_EVEX_L_XD_KZ, /* 6982 */ >+ IC_EVEX_L_XD_KZ, /* 6983 */ >+ IC_EVEX_L_W_KZ, /* 6984 */ >+ IC_EVEX_L_W_KZ, /* 6985 */ >+ IC_EVEX_L_W_XS_KZ, /* 6986 */ >+ IC_EVEX_L_W_XS_KZ, /* 6987 */ >+ IC_EVEX_L_W_XD_KZ, /* 6988 */ >+ IC_EVEX_L_W_XD_KZ, /* 6989 */ >+ IC_EVEX_L_W_XD_KZ, /* 6990 */ >+ IC_EVEX_L_W_XD_KZ, /* 6991 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6992 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6993 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6994 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6995 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6996 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6997 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6998 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 6999 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7000 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7001 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7002 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7003 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7004 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7005 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7006 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7007 */ >+ IC_EVEX_L_KZ, /* 7008 */ >+ IC_EVEX_L_KZ, /* 7009 */ >+ IC_EVEX_L_XS_KZ, /* 7010 */ >+ IC_EVEX_L_XS_KZ, /* 7011 */ >+ IC_EVEX_L_XD_KZ, /* 7012 */ >+ IC_EVEX_L_XD_KZ, /* 7013 */ >+ IC_EVEX_L_XD_KZ, /* 7014 */ >+ IC_EVEX_L_XD_KZ, /* 7015 */ >+ IC_EVEX_L_W_KZ, /* 7016 */ >+ IC_EVEX_L_W_KZ, /* 7017 */ >+ IC_EVEX_L_W_XS_KZ, /* 7018 */ >+ IC_EVEX_L_W_XS_KZ, /* 7019 */ >+ IC_EVEX_L_W_XD_KZ, /* 7020 */ >+ IC_EVEX_L_W_XD_KZ, /* 7021 */ >+ IC_EVEX_L_W_XD_KZ, /* 7022 */ >+ IC_EVEX_L_W_XD_KZ, /* 7023 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7024 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7025 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7026 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7027 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7028 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7029 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7030 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7031 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7032 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7033 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7034 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7035 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7036 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7037 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7038 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7039 */ >+ IC_EVEX_L_KZ, /* 7040 */ >+ IC_EVEX_L_KZ, /* 7041 */ >+ IC_EVEX_L_XS_KZ, /* 7042 */ >+ IC_EVEX_L_XS_KZ, /* 7043 */ >+ IC_EVEX_L_XD_KZ, /* 7044 */ >+ IC_EVEX_L_XD_KZ, /* 7045 */ >+ IC_EVEX_L_XD_KZ, /* 7046 */ >+ IC_EVEX_L_XD_KZ, /* 7047 */ >+ IC_EVEX_L_W_KZ, /* 7048 */ >+ IC_EVEX_L_W_KZ, /* 7049 */ >+ IC_EVEX_L_W_XS_KZ, /* 7050 */ >+ IC_EVEX_L_W_XS_KZ, /* 7051 */ >+ IC_EVEX_L_W_XD_KZ, /* 7052 */ >+ IC_EVEX_L_W_XD_KZ, /* 7053 */ >+ IC_EVEX_L_W_XD_KZ, /* 7054 */ >+ IC_EVEX_L_W_XD_KZ, /* 7055 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7056 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7057 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7058 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7059 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7060 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7061 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7062 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7063 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7064 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7065 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7066 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7067 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7068 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7069 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7070 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7071 */ >+ IC_EVEX_L_KZ, /* 7072 */ >+ IC_EVEX_L_KZ, /* 7073 */ >+ IC_EVEX_L_XS_KZ, /* 7074 */ >+ IC_EVEX_L_XS_KZ, /* 7075 */ >+ IC_EVEX_L_XD_KZ, /* 7076 */ >+ IC_EVEX_L_XD_KZ, /* 7077 */ >+ IC_EVEX_L_XD_KZ, /* 7078 */ >+ IC_EVEX_L_XD_KZ, /* 7079 */ >+ IC_EVEX_L_W_KZ, /* 7080 */ >+ IC_EVEX_L_W_KZ, /* 7081 */ >+ IC_EVEX_L_W_XS_KZ, /* 7082 */ >+ IC_EVEX_L_W_XS_KZ, /* 7083 */ >+ IC_EVEX_L_W_XD_KZ, /* 7084 */ >+ IC_EVEX_L_W_XD_KZ, /* 7085 */ >+ IC_EVEX_L_W_XD_KZ, /* 7086 */ >+ IC_EVEX_L_W_XD_KZ, /* 7087 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7088 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7089 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7090 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7091 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7092 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7093 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7094 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7095 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7096 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7097 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7098 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7099 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7100 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7101 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7102 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7103 */ >+ IC_EVEX_L_KZ, /* 7104 */ >+ IC_EVEX_L_KZ, /* 7105 */ >+ IC_EVEX_L_XS_KZ, /* 7106 */ >+ IC_EVEX_L_XS_KZ, /* 7107 */ >+ IC_EVEX_L_XD_KZ, /* 7108 */ >+ IC_EVEX_L_XD_KZ, /* 7109 */ >+ IC_EVEX_L_XD_KZ, /* 7110 */ >+ IC_EVEX_L_XD_KZ, /* 7111 */ >+ IC_EVEX_L_W_KZ, /* 7112 */ >+ IC_EVEX_L_W_KZ, /* 7113 */ >+ IC_EVEX_L_W_XS_KZ, /* 7114 */ >+ IC_EVEX_L_W_XS_KZ, /* 7115 */ >+ IC_EVEX_L_W_XD_KZ, /* 7116 */ >+ IC_EVEX_L_W_XD_KZ, /* 7117 */ >+ IC_EVEX_L_W_XD_KZ, /* 7118 */ >+ IC_EVEX_L_W_XD_KZ, /* 7119 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7120 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7121 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7122 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7123 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7124 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7125 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7126 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7127 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7128 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7129 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7130 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7131 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7132 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7133 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7134 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7135 */ >+ IC_EVEX_L_KZ, /* 7136 */ >+ IC_EVEX_L_KZ, /* 7137 */ >+ IC_EVEX_L_XS_KZ, /* 7138 */ >+ IC_EVEX_L_XS_KZ, /* 7139 */ >+ IC_EVEX_L_XD_KZ, /* 7140 */ >+ IC_EVEX_L_XD_KZ, /* 7141 */ >+ IC_EVEX_L_XD_KZ, /* 7142 */ >+ IC_EVEX_L_XD_KZ, /* 7143 */ >+ IC_EVEX_L_W_KZ, /* 7144 */ >+ IC_EVEX_L_W_KZ, /* 7145 */ >+ IC_EVEX_L_W_XS_KZ, /* 7146 */ >+ IC_EVEX_L_W_XS_KZ, /* 7147 */ >+ IC_EVEX_L_W_XD_KZ, /* 7148 */ >+ IC_EVEX_L_W_XD_KZ, /* 7149 */ >+ IC_EVEX_L_W_XD_KZ, /* 7150 */ >+ IC_EVEX_L_W_XD_KZ, /* 7151 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7152 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7153 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7154 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7155 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7156 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7157 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7158 */ >+ IC_EVEX_L_OPSIZE_KZ, /* 7159 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7160 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7161 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7162 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7163 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7164 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7165 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7166 */ >+ IC_EVEX_L_W_OPSIZE_KZ, /* 7167 */ >+ IC, /* 7168 */ >+ IC_64BIT, /* 7169 */ >+ IC_XS, /* 7170 */ >+ IC_64BIT_XS, /* 7171 */ >+ IC_XD, /* 7172 */ >+ IC_64BIT_XD, /* 7173 */ >+ IC_XS, /* 7174 */ >+ IC_64BIT_XS, /* 7175 */ >+ IC, /* 7176 */ >+ IC_64BIT_REXW, /* 7177 */ >+ IC_XS, /* 7178 */ >+ IC_64BIT_REXW_XS, /* 7179 */ >+ IC_XD, /* 7180 */ >+ IC_64BIT_REXW_XD, /* 7181 */ >+ IC_XS, /* 7182 */ >+ IC_64BIT_REXW_XS, /* 7183 */ >+ IC_OPSIZE, /* 7184 */ >+ IC_64BIT_OPSIZE, /* 7185 */ >+ IC_XS_OPSIZE, /* 7186 */ >+ IC_64BIT_XS_OPSIZE, /* 7187 */ >+ IC_XD_OPSIZE, /* 7188 */ >+ IC_64BIT_XD_OPSIZE, /* 7189 */ >+ IC_XS_OPSIZE, /* 7190 */ >+ IC_64BIT_XD_OPSIZE, /* 7191 */ >+ IC_OPSIZE, /* 7192 */ >+ IC_64BIT_REXW_OPSIZE, /* 7193 */ >+ IC_XS_OPSIZE, /* 7194 */ >+ IC_64BIT_REXW_XS, /* 7195 */ >+ IC_XD_OPSIZE, /* 7196 */ >+ IC_64BIT_REXW_XD, /* 7197 */ >+ IC_XS_OPSIZE, /* 7198 */ >+ IC_64BIT_REXW_XS, /* 7199 */ >+ IC_ADSIZE, /* 7200 */ >+ IC_64BIT_ADSIZE, /* 7201 */ >+ IC_XS, /* 7202 */ >+ IC_64BIT_XS, /* 7203 */ >+ IC_XD, /* 7204 */ >+ IC_64BIT_XD, /* 7205 */ >+ IC_XS, /* 7206 */ >+ IC_64BIT_XS, /* 7207 */ >+ IC_ADSIZE, /* 7208 */ >+ IC_64BIT_ADSIZE, /* 7209 */ >+ IC_XS, /* 7210 */ >+ IC_64BIT_REXW_XS, /* 7211 */ >+ IC_XD, /* 7212 */ >+ IC_64BIT_REXW_XD, /* 7213 */ >+ IC_XS, /* 7214 */ >+ IC_64BIT_REXW_XS, /* 7215 */ >+ IC_OPSIZE, /* 7216 */ >+ IC_64BIT_OPSIZE, /* 7217 */ >+ IC_XS_OPSIZE, /* 7218 */ >+ IC_64BIT_XS_OPSIZE, /* 7219 */ >+ IC_XD_OPSIZE, /* 7220 */ >+ IC_64BIT_XD_OPSIZE, /* 7221 */ >+ IC_XS_OPSIZE, /* 7222 */ >+ IC_64BIT_XD_OPSIZE, /* 7223 */ >+ IC_OPSIZE, /* 7224 */ >+ IC_64BIT_REXW_OPSIZE, /* 7225 */ >+ IC_XS_OPSIZE, /* 7226 */ >+ IC_64BIT_REXW_XS, /* 7227 */ >+ IC_XD_OPSIZE, /* 7228 */ >+ IC_64BIT_REXW_XD, /* 7229 */ >+ IC_XS_OPSIZE, /* 7230 */ >+ IC_64BIT_REXW_XS, /* 7231 */ >+ IC_VEX, /* 7232 */ >+ IC_VEX, /* 7233 */ >+ IC_VEX_XS, /* 7234 */ >+ IC_VEX_XS, /* 7235 */ >+ IC_VEX_XD, /* 7236 */ >+ IC_VEX_XD, /* 7237 */ >+ IC_VEX_XD, /* 7238 */ >+ IC_VEX_XD, /* 7239 */ >+ IC_VEX_W, /* 7240 */ >+ IC_VEX_W, /* 7241 */ >+ IC_VEX_W_XS, /* 7242 */ >+ IC_VEX_W_XS, /* 7243 */ >+ IC_VEX_W_XD, /* 7244 */ >+ IC_VEX_W_XD, /* 7245 */ >+ IC_VEX_W_XD, /* 7246 */ >+ IC_VEX_W_XD, /* 7247 */ >+ IC_VEX_OPSIZE, /* 7248 */ >+ IC_VEX_OPSIZE, /* 7249 */ >+ IC_VEX_OPSIZE, /* 7250 */ >+ IC_VEX_OPSIZE, /* 7251 */ >+ IC_VEX_OPSIZE, /* 7252 */ >+ IC_VEX_OPSIZE, /* 7253 */ >+ IC_VEX_OPSIZE, /* 7254 */ >+ IC_VEX_OPSIZE, /* 7255 */ >+ IC_VEX_W_OPSIZE, /* 7256 */ >+ IC_VEX_W_OPSIZE, /* 7257 */ >+ IC_VEX_W_OPSIZE, /* 7258 */ >+ IC_VEX_W_OPSIZE, /* 7259 */ >+ IC_VEX_W_OPSIZE, /* 7260 */ >+ IC_VEX_W_OPSIZE, /* 7261 */ >+ IC_VEX_W_OPSIZE, /* 7262 */ >+ IC_VEX_W_OPSIZE, /* 7263 */ >+ IC_VEX, /* 7264 */ >+ IC_VEX, /* 7265 */ >+ IC_VEX_XS, /* 7266 */ >+ IC_VEX_XS, /* 7267 */ >+ IC_VEX_XD, /* 7268 */ >+ IC_VEX_XD, /* 7269 */ >+ IC_VEX_XD, /* 7270 */ >+ IC_VEX_XD, /* 7271 */ >+ IC_VEX_W, /* 7272 */ >+ IC_VEX_W, /* 7273 */ >+ IC_VEX_W_XS, /* 7274 */ >+ IC_VEX_W_XS, /* 7275 */ >+ IC_VEX_W_XD, /* 7276 */ >+ IC_VEX_W_XD, /* 7277 */ >+ IC_VEX_W_XD, /* 7278 */ >+ IC_VEX_W_XD, /* 7279 */ >+ IC_VEX_OPSIZE, /* 7280 */ >+ IC_VEX_OPSIZE, /* 7281 */ >+ IC_VEX_OPSIZE, /* 7282 */ >+ IC_VEX_OPSIZE, /* 7283 */ >+ IC_VEX_OPSIZE, /* 7284 */ >+ IC_VEX_OPSIZE, /* 7285 */ >+ IC_VEX_OPSIZE, /* 7286 */ >+ IC_VEX_OPSIZE, /* 7287 */ >+ IC_VEX_W_OPSIZE, /* 7288 */ >+ IC_VEX_W_OPSIZE, /* 7289 */ >+ IC_VEX_W_OPSIZE, /* 7290 */ >+ IC_VEX_W_OPSIZE, /* 7291 */ >+ IC_VEX_W_OPSIZE, /* 7292 */ >+ IC_VEX_W_OPSIZE, /* 7293 */ >+ IC_VEX_W_OPSIZE, /* 7294 */ >+ IC_VEX_W_OPSIZE, /* 7295 */ >+ IC_VEX_L, /* 7296 */ >+ IC_VEX_L, /* 7297 */ >+ IC_VEX_L_XS, /* 7298 */ >+ IC_VEX_L_XS, /* 7299 */ >+ IC_VEX_L_XD, /* 7300 */ >+ IC_VEX_L_XD, /* 7301 */ >+ IC_VEX_L_XD, /* 7302 */ >+ IC_VEX_L_XD, /* 7303 */ >+ IC_VEX_L_W, /* 7304 */ >+ IC_VEX_L_W, /* 7305 */ >+ IC_VEX_L_W_XS, /* 7306 */ >+ IC_VEX_L_W_XS, /* 7307 */ >+ IC_VEX_L_W_XD, /* 7308 */ >+ IC_VEX_L_W_XD, /* 7309 */ >+ IC_VEX_L_W_XD, /* 7310 */ >+ IC_VEX_L_W_XD, /* 7311 */ >+ IC_VEX_L_OPSIZE, /* 7312 */ >+ IC_VEX_L_OPSIZE, /* 7313 */ >+ IC_VEX_L_OPSIZE, /* 7314 */ >+ IC_VEX_L_OPSIZE, /* 7315 */ >+ IC_VEX_L_OPSIZE, /* 7316 */ >+ IC_VEX_L_OPSIZE, /* 7317 */ >+ IC_VEX_L_OPSIZE, /* 7318 */ >+ IC_VEX_L_OPSIZE, /* 7319 */ >+ IC_VEX_L_W_OPSIZE, /* 7320 */ >+ IC_VEX_L_W_OPSIZE, /* 7321 */ >+ IC_VEX_L_W_OPSIZE, /* 7322 */ >+ IC_VEX_L_W_OPSIZE, /* 7323 */ >+ IC_VEX_L_W_OPSIZE, /* 7324 */ >+ IC_VEX_L_W_OPSIZE, /* 7325 */ >+ IC_VEX_L_W_OPSIZE, /* 7326 */ >+ IC_VEX_L_W_OPSIZE, /* 7327 */ >+ IC_VEX_L, /* 7328 */ >+ IC_VEX_L, /* 7329 */ >+ IC_VEX_L_XS, /* 7330 */ >+ IC_VEX_L_XS, /* 7331 */ >+ IC_VEX_L_XD, /* 7332 */ >+ IC_VEX_L_XD, /* 7333 */ >+ IC_VEX_L_XD, /* 7334 */ >+ IC_VEX_L_XD, /* 7335 */ >+ IC_VEX_L_W, /* 7336 */ >+ IC_VEX_L_W, /* 7337 */ >+ IC_VEX_L_W_XS, /* 7338 */ >+ IC_VEX_L_W_XS, /* 7339 */ >+ IC_VEX_L_W_XD, /* 7340 */ >+ IC_VEX_L_W_XD, /* 7341 */ >+ IC_VEX_L_W_XD, /* 7342 */ >+ IC_VEX_L_W_XD, /* 7343 */ >+ IC_VEX_L_OPSIZE, /* 7344 */ >+ IC_VEX_L_OPSIZE, /* 7345 */ >+ IC_VEX_L_OPSIZE, /* 7346 */ >+ IC_VEX_L_OPSIZE, /* 7347 */ >+ IC_VEX_L_OPSIZE, /* 7348 */ >+ IC_VEX_L_OPSIZE, /* 7349 */ >+ IC_VEX_L_OPSIZE, /* 7350 */ >+ IC_VEX_L_OPSIZE, /* 7351 */ >+ IC_VEX_L_W_OPSIZE, /* 7352 */ >+ IC_VEX_L_W_OPSIZE, /* 7353 */ >+ IC_VEX_L_W_OPSIZE, /* 7354 */ >+ IC_VEX_L_W_OPSIZE, /* 7355 */ >+ IC_VEX_L_W_OPSIZE, /* 7356 */ >+ IC_VEX_L_W_OPSIZE, /* 7357 */ >+ IC_VEX_L_W_OPSIZE, /* 7358 */ >+ IC_VEX_L_W_OPSIZE, /* 7359 */ >+ IC_VEX_L, /* 7360 */ >+ IC_VEX_L, /* 7361 */ >+ IC_VEX_L_XS, /* 7362 */ >+ IC_VEX_L_XS, /* 7363 */ >+ IC_VEX_L_XD, /* 7364 */ >+ IC_VEX_L_XD, /* 7365 */ >+ IC_VEX_L_XD, /* 7366 */ >+ IC_VEX_L_XD, /* 7367 */ >+ IC_VEX_L_W, /* 7368 */ >+ IC_VEX_L_W, /* 7369 */ >+ IC_VEX_L_W_XS, /* 7370 */ >+ IC_VEX_L_W_XS, /* 7371 */ >+ IC_VEX_L_W_XD, /* 7372 */ >+ IC_VEX_L_W_XD, /* 7373 */ >+ IC_VEX_L_W_XD, /* 7374 */ >+ IC_VEX_L_W_XD, /* 7375 */ >+ IC_VEX_L_OPSIZE, /* 7376 */ >+ IC_VEX_L_OPSIZE, /* 7377 */ >+ IC_VEX_L_OPSIZE, /* 7378 */ >+ IC_VEX_L_OPSIZE, /* 7379 */ >+ IC_VEX_L_OPSIZE, /* 7380 */ >+ IC_VEX_L_OPSIZE, /* 7381 */ >+ IC_VEX_L_OPSIZE, /* 7382 */ >+ IC_VEX_L_OPSIZE, /* 7383 */ >+ IC_VEX_L_W_OPSIZE, /* 7384 */ >+ IC_VEX_L_W_OPSIZE, /* 7385 */ >+ IC_VEX_L_W_OPSIZE, /* 7386 */ >+ IC_VEX_L_W_OPSIZE, /* 7387 */ >+ IC_VEX_L_W_OPSIZE, /* 7388 */ >+ IC_VEX_L_W_OPSIZE, /* 7389 */ >+ IC_VEX_L_W_OPSIZE, /* 7390 */ >+ IC_VEX_L_W_OPSIZE, /* 7391 */ >+ IC_VEX_L, /* 7392 */ >+ IC_VEX_L, /* 7393 */ >+ IC_VEX_L_XS, /* 7394 */ >+ IC_VEX_L_XS, /* 7395 */ >+ IC_VEX_L_XD, /* 7396 */ >+ IC_VEX_L_XD, /* 7397 */ >+ IC_VEX_L_XD, /* 7398 */ >+ IC_VEX_L_XD, /* 7399 */ >+ IC_VEX_L_W, /* 7400 */ >+ IC_VEX_L_W, /* 7401 */ >+ IC_VEX_L_W_XS, /* 7402 */ >+ IC_VEX_L_W_XS, /* 7403 */ >+ IC_VEX_L_W_XD, /* 7404 */ >+ IC_VEX_L_W_XD, /* 7405 */ >+ IC_VEX_L_W_XD, /* 7406 */ >+ IC_VEX_L_W_XD, /* 7407 */ >+ IC_VEX_L_OPSIZE, /* 7408 */ >+ IC_VEX_L_OPSIZE, /* 7409 */ >+ IC_VEX_L_OPSIZE, /* 7410 */ >+ IC_VEX_L_OPSIZE, /* 7411 */ >+ IC_VEX_L_OPSIZE, /* 7412 */ >+ IC_VEX_L_OPSIZE, /* 7413 */ >+ IC_VEX_L_OPSIZE, /* 7414 */ >+ IC_VEX_L_OPSIZE, /* 7415 */ >+ IC_VEX_L_W_OPSIZE, /* 7416 */ >+ IC_VEX_L_W_OPSIZE, /* 7417 */ >+ IC_VEX_L_W_OPSIZE, /* 7418 */ >+ IC_VEX_L_W_OPSIZE, /* 7419 */ >+ IC_VEX_L_W_OPSIZE, /* 7420 */ >+ IC_VEX_L_W_OPSIZE, /* 7421 */ >+ IC_VEX_L_W_OPSIZE, /* 7422 */ >+ IC_VEX_L_W_OPSIZE, /* 7423 */ >+ IC_EVEX_L2_KZ, /* 7424 */ >+ IC_EVEX_L2_KZ, /* 7425 */ >+ IC_EVEX_L2_XS_KZ, /* 7426 */ >+ IC_EVEX_L2_XS_KZ, /* 7427 */ >+ IC_EVEX_L2_XD_KZ, /* 7428 */ >+ IC_EVEX_L2_XD_KZ, /* 7429 */ >+ IC_EVEX_L2_XD_KZ, /* 7430 */ >+ IC_EVEX_L2_XD_KZ, /* 7431 */ >+ IC_EVEX_L2_W_KZ, /* 7432 */ >+ IC_EVEX_L2_W_KZ, /* 7433 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7434 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7435 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7436 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7437 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7438 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7439 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7440 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7441 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7442 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7443 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7444 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7445 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7446 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7447 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7448 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7449 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7450 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7451 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7452 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7453 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7454 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7455 */ >+ IC_EVEX_L2_KZ, /* 7456 */ >+ IC_EVEX_L2_KZ, /* 7457 */ >+ IC_EVEX_L2_XS_KZ, /* 7458 */ >+ IC_EVEX_L2_XS_KZ, /* 7459 */ >+ IC_EVEX_L2_XD_KZ, /* 7460 */ >+ IC_EVEX_L2_XD_KZ, /* 7461 */ >+ IC_EVEX_L2_XD_KZ, /* 7462 */ >+ IC_EVEX_L2_XD_KZ, /* 7463 */ >+ IC_EVEX_L2_W_KZ, /* 7464 */ >+ IC_EVEX_L2_W_KZ, /* 7465 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7466 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7467 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7468 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7469 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7470 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7471 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7472 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7473 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7474 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7475 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7476 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7477 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7478 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7479 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7480 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7481 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7482 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7483 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7484 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7485 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7486 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7487 */ >+ IC_EVEX_L2_KZ, /* 7488 */ >+ IC_EVEX_L2_KZ, /* 7489 */ >+ IC_EVEX_L2_XS_KZ, /* 7490 */ >+ IC_EVEX_L2_XS_KZ, /* 7491 */ >+ IC_EVEX_L2_XD_KZ, /* 7492 */ >+ IC_EVEX_L2_XD_KZ, /* 7493 */ >+ IC_EVEX_L2_XD_KZ, /* 7494 */ >+ IC_EVEX_L2_XD_KZ, /* 7495 */ >+ IC_EVEX_L2_W_KZ, /* 7496 */ >+ IC_EVEX_L2_W_KZ, /* 7497 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7498 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7499 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7500 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7501 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7502 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7503 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7504 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7505 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7506 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7507 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7508 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7509 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7510 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7511 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7512 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7513 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7514 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7515 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7516 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7517 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7518 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7519 */ >+ IC_EVEX_L2_KZ, /* 7520 */ >+ IC_EVEX_L2_KZ, /* 7521 */ >+ IC_EVEX_L2_XS_KZ, /* 7522 */ >+ IC_EVEX_L2_XS_KZ, /* 7523 */ >+ IC_EVEX_L2_XD_KZ, /* 7524 */ >+ IC_EVEX_L2_XD_KZ, /* 7525 */ >+ IC_EVEX_L2_XD_KZ, /* 7526 */ >+ IC_EVEX_L2_XD_KZ, /* 7527 */ >+ IC_EVEX_L2_W_KZ, /* 7528 */ >+ IC_EVEX_L2_W_KZ, /* 7529 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7530 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7531 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7532 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7533 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7534 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7535 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7536 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7537 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7538 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7539 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7540 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7541 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7542 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7543 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7544 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7545 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7546 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7547 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7548 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7549 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7550 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7551 */ >+ IC_EVEX_L2_KZ, /* 7552 */ >+ IC_EVEX_L2_KZ, /* 7553 */ >+ IC_EVEX_L2_XS_KZ, /* 7554 */ >+ IC_EVEX_L2_XS_KZ, /* 7555 */ >+ IC_EVEX_L2_XD_KZ, /* 7556 */ >+ IC_EVEX_L2_XD_KZ, /* 7557 */ >+ IC_EVEX_L2_XD_KZ, /* 7558 */ >+ IC_EVEX_L2_XD_KZ, /* 7559 */ >+ IC_EVEX_L2_W_KZ, /* 7560 */ >+ IC_EVEX_L2_W_KZ, /* 7561 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7562 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7563 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7564 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7565 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7566 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7567 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7568 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7569 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7570 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7571 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7572 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7573 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7574 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7575 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7576 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7577 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7578 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7579 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7580 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7581 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7582 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7583 */ >+ IC_EVEX_L2_KZ, /* 7584 */ >+ IC_EVEX_L2_KZ, /* 7585 */ >+ IC_EVEX_L2_XS_KZ, /* 7586 */ >+ IC_EVEX_L2_XS_KZ, /* 7587 */ >+ IC_EVEX_L2_XD_KZ, /* 7588 */ >+ IC_EVEX_L2_XD_KZ, /* 7589 */ >+ IC_EVEX_L2_XD_KZ, /* 7590 */ >+ IC_EVEX_L2_XD_KZ, /* 7591 */ >+ IC_EVEX_L2_W_KZ, /* 7592 */ >+ IC_EVEX_L2_W_KZ, /* 7593 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7594 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7595 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7596 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7597 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7598 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7599 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7600 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7601 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7602 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7603 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7604 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7605 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7606 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7607 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7608 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7609 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7610 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7611 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7612 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7613 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7614 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7615 */ >+ IC_EVEX_L2_KZ, /* 7616 */ >+ IC_EVEX_L2_KZ, /* 7617 */ >+ IC_EVEX_L2_XS_KZ, /* 7618 */ >+ IC_EVEX_L2_XS_KZ, /* 7619 */ >+ IC_EVEX_L2_XD_KZ, /* 7620 */ >+ IC_EVEX_L2_XD_KZ, /* 7621 */ >+ IC_EVEX_L2_XD_KZ, /* 7622 */ >+ IC_EVEX_L2_XD_KZ, /* 7623 */ >+ IC_EVEX_L2_W_KZ, /* 7624 */ >+ IC_EVEX_L2_W_KZ, /* 7625 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7626 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7627 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7628 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7629 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7630 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7631 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7632 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7633 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7634 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7635 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7636 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7637 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7638 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7639 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7640 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7641 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7642 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7643 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7644 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7645 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7646 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7647 */ >+ IC_EVEX_L2_KZ, /* 7648 */ >+ IC_EVEX_L2_KZ, /* 7649 */ >+ IC_EVEX_L2_XS_KZ, /* 7650 */ >+ IC_EVEX_L2_XS_KZ, /* 7651 */ >+ IC_EVEX_L2_XD_KZ, /* 7652 */ >+ IC_EVEX_L2_XD_KZ, /* 7653 */ >+ IC_EVEX_L2_XD_KZ, /* 7654 */ >+ IC_EVEX_L2_XD_KZ, /* 7655 */ >+ IC_EVEX_L2_W_KZ, /* 7656 */ >+ IC_EVEX_L2_W_KZ, /* 7657 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7658 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7659 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7660 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7661 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7662 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7663 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7664 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7665 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7666 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7667 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7668 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7669 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7670 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7671 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7672 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7673 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7674 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7675 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7676 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7677 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7678 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7679 */ >+ IC, /* 7680 */ >+ IC_64BIT, /* 7681 */ >+ IC_XS, /* 7682 */ >+ IC_64BIT_XS, /* 7683 */ >+ IC_XD, /* 7684 */ >+ IC_64BIT_XD, /* 7685 */ >+ IC_XS, /* 7686 */ >+ IC_64BIT_XS, /* 7687 */ >+ IC, /* 7688 */ >+ IC_64BIT_REXW, /* 7689 */ >+ IC_XS, /* 7690 */ >+ IC_64BIT_REXW_XS, /* 7691 */ >+ IC_XD, /* 7692 */ >+ IC_64BIT_REXW_XD, /* 7693 */ >+ IC_XS, /* 7694 */ >+ IC_64BIT_REXW_XS, /* 7695 */ >+ IC_OPSIZE, /* 7696 */ >+ IC_64BIT_OPSIZE, /* 7697 */ >+ IC_XS_OPSIZE, /* 7698 */ >+ IC_64BIT_XS_OPSIZE, /* 7699 */ >+ IC_XD_OPSIZE, /* 7700 */ >+ IC_64BIT_XD_OPSIZE, /* 7701 */ >+ IC_XS_OPSIZE, /* 7702 */ >+ IC_64BIT_XD_OPSIZE, /* 7703 */ >+ IC_OPSIZE, /* 7704 */ >+ IC_64BIT_REXW_OPSIZE, /* 7705 */ >+ IC_XS_OPSIZE, /* 7706 */ >+ IC_64BIT_REXW_XS, /* 7707 */ >+ IC_XD_OPSIZE, /* 7708 */ >+ IC_64BIT_REXW_XD, /* 7709 */ >+ IC_XS_OPSIZE, /* 7710 */ >+ IC_64BIT_REXW_XS, /* 7711 */ >+ IC_ADSIZE, /* 7712 */ >+ IC_64BIT_ADSIZE, /* 7713 */ >+ IC_XS, /* 7714 */ >+ IC_64BIT_XS, /* 7715 */ >+ IC_XD, /* 7716 */ >+ IC_64BIT_XD, /* 7717 */ >+ IC_XS, /* 7718 */ >+ IC_64BIT_XS, /* 7719 */ >+ IC_ADSIZE, /* 7720 */ >+ IC_64BIT_ADSIZE, /* 7721 */ >+ IC_XS, /* 7722 */ >+ IC_64BIT_REXW_XS, /* 7723 */ >+ IC_XD, /* 7724 */ >+ IC_64BIT_REXW_XD, /* 7725 */ >+ IC_XS, /* 7726 */ >+ IC_64BIT_REXW_XS, /* 7727 */ >+ IC_OPSIZE, /* 7728 */ >+ IC_64BIT_OPSIZE, /* 7729 */ >+ IC_XS_OPSIZE, /* 7730 */ >+ IC_64BIT_XS_OPSIZE, /* 7731 */ >+ IC_XD_OPSIZE, /* 7732 */ >+ IC_64BIT_XD_OPSIZE, /* 7733 */ >+ IC_XS_OPSIZE, /* 7734 */ >+ IC_64BIT_XD_OPSIZE, /* 7735 */ >+ IC_OPSIZE, /* 7736 */ >+ IC_64BIT_REXW_OPSIZE, /* 7737 */ >+ IC_XS_OPSIZE, /* 7738 */ >+ IC_64BIT_REXW_XS, /* 7739 */ >+ IC_XD_OPSIZE, /* 7740 */ >+ IC_64BIT_REXW_XD, /* 7741 */ >+ IC_XS_OPSIZE, /* 7742 */ >+ IC_64BIT_REXW_XS, /* 7743 */ >+ IC_VEX, /* 7744 */ >+ IC_VEX, /* 7745 */ >+ IC_VEX_XS, /* 7746 */ >+ IC_VEX_XS, /* 7747 */ >+ IC_VEX_XD, /* 7748 */ >+ IC_VEX_XD, /* 7749 */ >+ IC_VEX_XD, /* 7750 */ >+ IC_VEX_XD, /* 7751 */ >+ IC_VEX_W, /* 7752 */ >+ IC_VEX_W, /* 7753 */ >+ IC_VEX_W_XS, /* 7754 */ >+ IC_VEX_W_XS, /* 7755 */ >+ IC_VEX_W_XD, /* 7756 */ >+ IC_VEX_W_XD, /* 7757 */ >+ IC_VEX_W_XD, /* 7758 */ >+ IC_VEX_W_XD, /* 7759 */ >+ IC_VEX_OPSIZE, /* 7760 */ >+ IC_VEX_OPSIZE, /* 7761 */ >+ IC_VEX_OPSIZE, /* 7762 */ >+ IC_VEX_OPSIZE, /* 7763 */ >+ IC_VEX_OPSIZE, /* 7764 */ >+ IC_VEX_OPSIZE, /* 7765 */ >+ IC_VEX_OPSIZE, /* 7766 */ >+ IC_VEX_OPSIZE, /* 7767 */ >+ IC_VEX_W_OPSIZE, /* 7768 */ >+ IC_VEX_W_OPSIZE, /* 7769 */ >+ IC_VEX_W_OPSIZE, /* 7770 */ >+ IC_VEX_W_OPSIZE, /* 7771 */ >+ IC_VEX_W_OPSIZE, /* 7772 */ >+ IC_VEX_W_OPSIZE, /* 7773 */ >+ IC_VEX_W_OPSIZE, /* 7774 */ >+ IC_VEX_W_OPSIZE, /* 7775 */ >+ IC_VEX, /* 7776 */ >+ IC_VEX, /* 7777 */ >+ IC_VEX_XS, /* 7778 */ >+ IC_VEX_XS, /* 7779 */ >+ IC_VEX_XD, /* 7780 */ >+ IC_VEX_XD, /* 7781 */ >+ IC_VEX_XD, /* 7782 */ >+ IC_VEX_XD, /* 7783 */ >+ IC_VEX_W, /* 7784 */ >+ IC_VEX_W, /* 7785 */ >+ IC_VEX_W_XS, /* 7786 */ >+ IC_VEX_W_XS, /* 7787 */ >+ IC_VEX_W_XD, /* 7788 */ >+ IC_VEX_W_XD, /* 7789 */ >+ IC_VEX_W_XD, /* 7790 */ >+ IC_VEX_W_XD, /* 7791 */ >+ IC_VEX_OPSIZE, /* 7792 */ >+ IC_VEX_OPSIZE, /* 7793 */ >+ IC_VEX_OPSIZE, /* 7794 */ >+ IC_VEX_OPSIZE, /* 7795 */ >+ IC_VEX_OPSIZE, /* 7796 */ >+ IC_VEX_OPSIZE, /* 7797 */ >+ IC_VEX_OPSIZE, /* 7798 */ >+ IC_VEX_OPSIZE, /* 7799 */ >+ IC_VEX_W_OPSIZE, /* 7800 */ >+ IC_VEX_W_OPSIZE, /* 7801 */ >+ IC_VEX_W_OPSIZE, /* 7802 */ >+ IC_VEX_W_OPSIZE, /* 7803 */ >+ IC_VEX_W_OPSIZE, /* 7804 */ >+ IC_VEX_W_OPSIZE, /* 7805 */ >+ IC_VEX_W_OPSIZE, /* 7806 */ >+ IC_VEX_W_OPSIZE, /* 7807 */ >+ IC_VEX_L, /* 7808 */ >+ IC_VEX_L, /* 7809 */ >+ IC_VEX_L_XS, /* 7810 */ >+ IC_VEX_L_XS, /* 7811 */ >+ IC_VEX_L_XD, /* 7812 */ >+ IC_VEX_L_XD, /* 7813 */ >+ IC_VEX_L_XD, /* 7814 */ >+ IC_VEX_L_XD, /* 7815 */ >+ IC_VEX_L_W, /* 7816 */ >+ IC_VEX_L_W, /* 7817 */ >+ IC_VEX_L_W_XS, /* 7818 */ >+ IC_VEX_L_W_XS, /* 7819 */ >+ IC_VEX_L_W_XD, /* 7820 */ >+ IC_VEX_L_W_XD, /* 7821 */ >+ IC_VEX_L_W_XD, /* 7822 */ >+ IC_VEX_L_W_XD, /* 7823 */ >+ IC_VEX_L_OPSIZE, /* 7824 */ >+ IC_VEX_L_OPSIZE, /* 7825 */ >+ IC_VEX_L_OPSIZE, /* 7826 */ >+ IC_VEX_L_OPSIZE, /* 7827 */ >+ IC_VEX_L_OPSIZE, /* 7828 */ >+ IC_VEX_L_OPSIZE, /* 7829 */ >+ IC_VEX_L_OPSIZE, /* 7830 */ >+ IC_VEX_L_OPSIZE, /* 7831 */ >+ IC_VEX_L_W_OPSIZE, /* 7832 */ >+ IC_VEX_L_W_OPSIZE, /* 7833 */ >+ IC_VEX_L_W_OPSIZE, /* 7834 */ >+ IC_VEX_L_W_OPSIZE, /* 7835 */ >+ IC_VEX_L_W_OPSIZE, /* 7836 */ >+ IC_VEX_L_W_OPSIZE, /* 7837 */ >+ IC_VEX_L_W_OPSIZE, /* 7838 */ >+ IC_VEX_L_W_OPSIZE, /* 7839 */ >+ IC_VEX_L, /* 7840 */ >+ IC_VEX_L, /* 7841 */ >+ IC_VEX_L_XS, /* 7842 */ >+ IC_VEX_L_XS, /* 7843 */ >+ IC_VEX_L_XD, /* 7844 */ >+ IC_VEX_L_XD, /* 7845 */ >+ IC_VEX_L_XD, /* 7846 */ >+ IC_VEX_L_XD, /* 7847 */ >+ IC_VEX_L_W, /* 7848 */ >+ IC_VEX_L_W, /* 7849 */ >+ IC_VEX_L_W_XS, /* 7850 */ >+ IC_VEX_L_W_XS, /* 7851 */ >+ IC_VEX_L_W_XD, /* 7852 */ >+ IC_VEX_L_W_XD, /* 7853 */ >+ IC_VEX_L_W_XD, /* 7854 */ >+ IC_VEX_L_W_XD, /* 7855 */ >+ IC_VEX_L_OPSIZE, /* 7856 */ >+ IC_VEX_L_OPSIZE, /* 7857 */ >+ IC_VEX_L_OPSIZE, /* 7858 */ >+ IC_VEX_L_OPSIZE, /* 7859 */ >+ IC_VEX_L_OPSIZE, /* 7860 */ >+ IC_VEX_L_OPSIZE, /* 7861 */ >+ IC_VEX_L_OPSIZE, /* 7862 */ >+ IC_VEX_L_OPSIZE, /* 7863 */ >+ IC_VEX_L_W_OPSIZE, /* 7864 */ >+ IC_VEX_L_W_OPSIZE, /* 7865 */ >+ IC_VEX_L_W_OPSIZE, /* 7866 */ >+ IC_VEX_L_W_OPSIZE, /* 7867 */ >+ IC_VEX_L_W_OPSIZE, /* 7868 */ >+ IC_VEX_L_W_OPSIZE, /* 7869 */ >+ IC_VEX_L_W_OPSIZE, /* 7870 */ >+ IC_VEX_L_W_OPSIZE, /* 7871 */ >+ IC_VEX_L, /* 7872 */ >+ IC_VEX_L, /* 7873 */ >+ IC_VEX_L_XS, /* 7874 */ >+ IC_VEX_L_XS, /* 7875 */ >+ IC_VEX_L_XD, /* 7876 */ >+ IC_VEX_L_XD, /* 7877 */ >+ IC_VEX_L_XD, /* 7878 */ >+ IC_VEX_L_XD, /* 7879 */ >+ IC_VEX_L_W, /* 7880 */ >+ IC_VEX_L_W, /* 7881 */ >+ IC_VEX_L_W_XS, /* 7882 */ >+ IC_VEX_L_W_XS, /* 7883 */ >+ IC_VEX_L_W_XD, /* 7884 */ >+ IC_VEX_L_W_XD, /* 7885 */ >+ IC_VEX_L_W_XD, /* 7886 */ >+ IC_VEX_L_W_XD, /* 7887 */ >+ IC_VEX_L_OPSIZE, /* 7888 */ >+ IC_VEX_L_OPSIZE, /* 7889 */ >+ IC_VEX_L_OPSIZE, /* 7890 */ >+ IC_VEX_L_OPSIZE, /* 7891 */ >+ IC_VEX_L_OPSIZE, /* 7892 */ >+ IC_VEX_L_OPSIZE, /* 7893 */ >+ IC_VEX_L_OPSIZE, /* 7894 */ >+ IC_VEX_L_OPSIZE, /* 7895 */ >+ IC_VEX_L_W_OPSIZE, /* 7896 */ >+ IC_VEX_L_W_OPSIZE, /* 7897 */ >+ IC_VEX_L_W_OPSIZE, /* 7898 */ >+ IC_VEX_L_W_OPSIZE, /* 7899 */ >+ IC_VEX_L_W_OPSIZE, /* 7900 */ >+ IC_VEX_L_W_OPSIZE, /* 7901 */ >+ IC_VEX_L_W_OPSIZE, /* 7902 */ >+ IC_VEX_L_W_OPSIZE, /* 7903 */ >+ IC_VEX_L, /* 7904 */ >+ IC_VEX_L, /* 7905 */ >+ IC_VEX_L_XS, /* 7906 */ >+ IC_VEX_L_XS, /* 7907 */ >+ IC_VEX_L_XD, /* 7908 */ >+ IC_VEX_L_XD, /* 7909 */ >+ IC_VEX_L_XD, /* 7910 */ >+ IC_VEX_L_XD, /* 7911 */ >+ IC_VEX_L_W, /* 7912 */ >+ IC_VEX_L_W, /* 7913 */ >+ IC_VEX_L_W_XS, /* 7914 */ >+ IC_VEX_L_W_XS, /* 7915 */ >+ IC_VEX_L_W_XD, /* 7916 */ >+ IC_VEX_L_W_XD, /* 7917 */ >+ IC_VEX_L_W_XD, /* 7918 */ >+ IC_VEX_L_W_XD, /* 7919 */ >+ IC_VEX_L_OPSIZE, /* 7920 */ >+ IC_VEX_L_OPSIZE, /* 7921 */ >+ IC_VEX_L_OPSIZE, /* 7922 */ >+ IC_VEX_L_OPSIZE, /* 7923 */ >+ IC_VEX_L_OPSIZE, /* 7924 */ >+ IC_VEX_L_OPSIZE, /* 7925 */ >+ IC_VEX_L_OPSIZE, /* 7926 */ >+ IC_VEX_L_OPSIZE, /* 7927 */ >+ IC_VEX_L_W_OPSIZE, /* 7928 */ >+ IC_VEX_L_W_OPSIZE, /* 7929 */ >+ IC_VEX_L_W_OPSIZE, /* 7930 */ >+ IC_VEX_L_W_OPSIZE, /* 7931 */ >+ IC_VEX_L_W_OPSIZE, /* 7932 */ >+ IC_VEX_L_W_OPSIZE, /* 7933 */ >+ IC_VEX_L_W_OPSIZE, /* 7934 */ >+ IC_VEX_L_W_OPSIZE, /* 7935 */ >+ IC_EVEX_L2_KZ, /* 7936 */ >+ IC_EVEX_L2_KZ, /* 7937 */ >+ IC_EVEX_L2_XS_KZ, /* 7938 */ >+ IC_EVEX_L2_XS_KZ, /* 7939 */ >+ IC_EVEX_L2_XD_KZ, /* 7940 */ >+ IC_EVEX_L2_XD_KZ, /* 7941 */ >+ IC_EVEX_L2_XD_KZ, /* 7942 */ >+ IC_EVEX_L2_XD_KZ, /* 7943 */ >+ IC_EVEX_L2_W_KZ, /* 7944 */ >+ IC_EVEX_L2_W_KZ, /* 7945 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7946 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7947 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7948 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7949 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7950 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7951 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7952 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7953 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7954 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7955 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7956 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7957 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7958 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7959 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7960 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7961 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7962 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7963 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7964 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7965 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7966 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7967 */ >+ IC_EVEX_L2_KZ, /* 7968 */ >+ IC_EVEX_L2_KZ, /* 7969 */ >+ IC_EVEX_L2_XS_KZ, /* 7970 */ >+ IC_EVEX_L2_XS_KZ, /* 7971 */ >+ IC_EVEX_L2_XD_KZ, /* 7972 */ >+ IC_EVEX_L2_XD_KZ, /* 7973 */ >+ IC_EVEX_L2_XD_KZ, /* 7974 */ >+ IC_EVEX_L2_XD_KZ, /* 7975 */ >+ IC_EVEX_L2_W_KZ, /* 7976 */ >+ IC_EVEX_L2_W_KZ, /* 7977 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7978 */ >+ IC_EVEX_L2_W_XS_KZ, /* 7979 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7980 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7981 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7982 */ >+ IC_EVEX_L2_W_XD_KZ, /* 7983 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7984 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7985 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7986 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7987 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7988 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7989 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7990 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 7991 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7992 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7993 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7994 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7995 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7996 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7997 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7998 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 7999 */ >+ IC_EVEX_L2_KZ, /* 8000 */ >+ IC_EVEX_L2_KZ, /* 8001 */ >+ IC_EVEX_L2_XS_KZ, /* 8002 */ >+ IC_EVEX_L2_XS_KZ, /* 8003 */ >+ IC_EVEX_L2_XD_KZ, /* 8004 */ >+ IC_EVEX_L2_XD_KZ, /* 8005 */ >+ IC_EVEX_L2_XD_KZ, /* 8006 */ >+ IC_EVEX_L2_XD_KZ, /* 8007 */ >+ IC_EVEX_L2_W_KZ, /* 8008 */ >+ IC_EVEX_L2_W_KZ, /* 8009 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8010 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8011 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8012 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8013 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8014 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8015 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8016 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8017 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8018 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8019 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8020 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8021 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8022 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8023 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8024 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8025 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8026 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8027 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8028 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8029 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8030 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8031 */ >+ IC_EVEX_L2_KZ, /* 8032 */ >+ IC_EVEX_L2_KZ, /* 8033 */ >+ IC_EVEX_L2_XS_KZ, /* 8034 */ >+ IC_EVEX_L2_XS_KZ, /* 8035 */ >+ IC_EVEX_L2_XD_KZ, /* 8036 */ >+ IC_EVEX_L2_XD_KZ, /* 8037 */ >+ IC_EVEX_L2_XD_KZ, /* 8038 */ >+ IC_EVEX_L2_XD_KZ, /* 8039 */ >+ IC_EVEX_L2_W_KZ, /* 8040 */ >+ IC_EVEX_L2_W_KZ, /* 8041 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8042 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8043 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8044 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8045 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8046 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8047 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8048 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8049 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8050 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8051 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8052 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8053 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8054 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8055 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8056 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8057 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8058 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8059 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8060 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8061 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8062 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8063 */ >+ IC_EVEX_L2_KZ, /* 8064 */ >+ IC_EVEX_L2_KZ, /* 8065 */ >+ IC_EVEX_L2_XS_KZ, /* 8066 */ >+ IC_EVEX_L2_XS_KZ, /* 8067 */ >+ IC_EVEX_L2_XD_KZ, /* 8068 */ >+ IC_EVEX_L2_XD_KZ, /* 8069 */ >+ IC_EVEX_L2_XD_KZ, /* 8070 */ >+ IC_EVEX_L2_XD_KZ, /* 8071 */ >+ IC_EVEX_L2_W_KZ, /* 8072 */ >+ IC_EVEX_L2_W_KZ, /* 8073 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8074 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8075 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8076 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8077 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8078 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8079 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8080 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8081 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8082 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8083 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8084 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8085 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8086 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8087 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8088 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8089 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8090 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8091 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8092 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8093 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8094 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8095 */ >+ IC_EVEX_L2_KZ, /* 8096 */ >+ IC_EVEX_L2_KZ, /* 8097 */ >+ IC_EVEX_L2_XS_KZ, /* 8098 */ >+ IC_EVEX_L2_XS_KZ, /* 8099 */ >+ IC_EVEX_L2_XD_KZ, /* 8100 */ >+ IC_EVEX_L2_XD_KZ, /* 8101 */ >+ IC_EVEX_L2_XD_KZ, /* 8102 */ >+ IC_EVEX_L2_XD_KZ, /* 8103 */ >+ IC_EVEX_L2_W_KZ, /* 8104 */ >+ IC_EVEX_L2_W_KZ, /* 8105 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8106 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8107 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8108 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8109 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8110 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8111 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8112 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8113 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8114 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8115 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8116 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8117 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8118 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8119 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8120 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8121 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8122 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8123 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8124 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8125 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8126 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8127 */ >+ IC_EVEX_L2_KZ, /* 8128 */ >+ IC_EVEX_L2_KZ, /* 8129 */ >+ IC_EVEX_L2_XS_KZ, /* 8130 */ >+ IC_EVEX_L2_XS_KZ, /* 8131 */ >+ IC_EVEX_L2_XD_KZ, /* 8132 */ >+ IC_EVEX_L2_XD_KZ, /* 8133 */ >+ IC_EVEX_L2_XD_KZ, /* 8134 */ >+ IC_EVEX_L2_XD_KZ, /* 8135 */ >+ IC_EVEX_L2_W_KZ, /* 8136 */ >+ IC_EVEX_L2_W_KZ, /* 8137 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8138 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8139 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8140 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8141 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8142 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8143 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8144 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8145 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8146 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8147 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8148 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8149 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8150 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8151 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8152 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8153 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8154 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8155 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8156 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8157 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8158 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8159 */ >+ IC_EVEX_L2_KZ, /* 8160 */ >+ IC_EVEX_L2_KZ, /* 8161 */ >+ IC_EVEX_L2_XS_KZ, /* 8162 */ >+ IC_EVEX_L2_XS_KZ, /* 8163 */ >+ IC_EVEX_L2_XD_KZ, /* 8164 */ >+ IC_EVEX_L2_XD_KZ, /* 8165 */ >+ IC_EVEX_L2_XD_KZ, /* 8166 */ >+ IC_EVEX_L2_XD_KZ, /* 8167 */ >+ IC_EVEX_L2_W_KZ, /* 8168 */ >+ IC_EVEX_L2_W_KZ, /* 8169 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8170 */ >+ IC_EVEX_L2_W_XS_KZ, /* 8171 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8172 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8173 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8174 */ >+ IC_EVEX_L2_W_XD_KZ, /* 8175 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8176 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8177 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8178 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8179 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8180 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8181 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8182 */ >+ IC_EVEX_L2_OPSIZE_KZ, /* 8183 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8184 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8185 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8186 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8187 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8188 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8189 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8190 */ >+ IC_EVEX_L2_W_OPSIZE_KZ, /* 8191 */ >+ IC, /* 8192 */ >+ IC_64BIT, /* 8193 */ >+ IC_XS, /* 8194 */ >+ IC_64BIT_XS, /* 8195 */ >+ IC_XD, /* 8196 */ >+ IC_64BIT_XD, /* 8197 */ >+ IC_XS, /* 8198 */ >+ IC_64BIT_XS, /* 8199 */ >+ IC, /* 8200 */ >+ IC_64BIT_REXW, /* 8201 */ >+ IC_XS, /* 8202 */ >+ IC_64BIT_REXW_XS, /* 8203 */ >+ IC_XD, /* 8204 */ >+ IC_64BIT_REXW_XD, /* 8205 */ >+ IC_XS, /* 8206 */ >+ IC_64BIT_REXW_XS, /* 8207 */ >+ IC_OPSIZE, /* 8208 */ >+ IC_64BIT_OPSIZE, /* 8209 */ >+ IC_XS_OPSIZE, /* 8210 */ >+ IC_64BIT_XS_OPSIZE, /* 8211 */ >+ IC_XD_OPSIZE, /* 8212 */ >+ IC_64BIT_XD_OPSIZE, /* 8213 */ >+ IC_XS_OPSIZE, /* 8214 */ >+ IC_64BIT_XD_OPSIZE, /* 8215 */ >+ IC_OPSIZE, /* 8216 */ >+ IC_64BIT_REXW_OPSIZE, /* 8217 */ >+ IC_XS_OPSIZE, /* 8218 */ >+ IC_64BIT_REXW_XS, /* 8219 */ >+ IC_XD_OPSIZE, /* 8220 */ >+ IC_64BIT_REXW_XD, /* 8221 */ >+ IC_XS_OPSIZE, /* 8222 */ >+ IC_64BIT_REXW_XS, /* 8223 */ >+ IC_ADSIZE, /* 8224 */ >+ IC_64BIT_ADSIZE, /* 8225 */ >+ IC_XS, /* 8226 */ >+ IC_64BIT_XS, /* 8227 */ >+ IC_XD, /* 8228 */ >+ IC_64BIT_XD, /* 8229 */ >+ IC_XS, /* 8230 */ >+ IC_64BIT_XS, /* 8231 */ >+ IC_ADSIZE, /* 8232 */ >+ IC_64BIT_ADSIZE, /* 8233 */ >+ IC_XS, /* 8234 */ >+ IC_64BIT_REXW_XS, /* 8235 */ >+ IC_XD, /* 8236 */ >+ IC_64BIT_REXW_XD, /* 8237 */ >+ IC_XS, /* 8238 */ >+ IC_64BIT_REXW_XS, /* 8239 */ >+ IC_OPSIZE, /* 8240 */ >+ IC_64BIT_OPSIZE, /* 8241 */ >+ IC_XS_OPSIZE, /* 8242 */ >+ IC_64BIT_XS_OPSIZE, /* 8243 */ >+ IC_XD_OPSIZE, /* 8244 */ >+ IC_64BIT_XD_OPSIZE, /* 8245 */ >+ IC_XS_OPSIZE, /* 8246 */ >+ IC_64BIT_XD_OPSIZE, /* 8247 */ >+ IC_OPSIZE, /* 8248 */ >+ IC_64BIT_REXW_OPSIZE, /* 8249 */ >+ IC_XS_OPSIZE, /* 8250 */ >+ IC_64BIT_REXW_XS, /* 8251 */ >+ IC_XD_OPSIZE, /* 8252 */ >+ IC_64BIT_REXW_XD, /* 8253 */ >+ IC_XS_OPSIZE, /* 8254 */ >+ IC_64BIT_REXW_XS, /* 8255 */ >+ IC_VEX, /* 8256 */ >+ IC_VEX, /* 8257 */ >+ IC_VEX_XS, /* 8258 */ >+ IC_VEX_XS, /* 8259 */ >+ IC_VEX_XD, /* 8260 */ >+ IC_VEX_XD, /* 8261 */ >+ IC_VEX_XD, /* 8262 */ >+ IC_VEX_XD, /* 8263 */ >+ IC_VEX_W, /* 8264 */ >+ IC_VEX_W, /* 8265 */ >+ IC_VEX_W_XS, /* 8266 */ >+ IC_VEX_W_XS, /* 8267 */ >+ IC_VEX_W_XD, /* 8268 */ >+ IC_VEX_W_XD, /* 8269 */ >+ IC_VEX_W_XD, /* 8270 */ >+ IC_VEX_W_XD, /* 8271 */ >+ IC_VEX_OPSIZE, /* 8272 */ >+ IC_VEX_OPSIZE, /* 8273 */ >+ IC_VEX_OPSIZE, /* 8274 */ >+ IC_VEX_OPSIZE, /* 8275 */ >+ IC_VEX_OPSIZE, /* 8276 */ >+ IC_VEX_OPSIZE, /* 8277 */ >+ IC_VEX_OPSIZE, /* 8278 */ >+ IC_VEX_OPSIZE, /* 8279 */ >+ IC_VEX_W_OPSIZE, /* 8280 */ >+ IC_VEX_W_OPSIZE, /* 8281 */ >+ IC_VEX_W_OPSIZE, /* 8282 */ >+ IC_VEX_W_OPSIZE, /* 8283 */ >+ IC_VEX_W_OPSIZE, /* 8284 */ >+ IC_VEX_W_OPSIZE, /* 8285 */ >+ IC_VEX_W_OPSIZE, /* 8286 */ >+ IC_VEX_W_OPSIZE, /* 8287 */ >+ IC_VEX, /* 8288 */ >+ IC_VEX, /* 8289 */ >+ IC_VEX_XS, /* 8290 */ >+ IC_VEX_XS, /* 8291 */ >+ IC_VEX_XD, /* 8292 */ >+ IC_VEX_XD, /* 8293 */ >+ IC_VEX_XD, /* 8294 */ >+ IC_VEX_XD, /* 8295 */ >+ IC_VEX_W, /* 8296 */ >+ IC_VEX_W, /* 8297 */ >+ IC_VEX_W_XS, /* 8298 */ >+ IC_VEX_W_XS, /* 8299 */ >+ IC_VEX_W_XD, /* 8300 */ >+ IC_VEX_W_XD, /* 8301 */ >+ IC_VEX_W_XD, /* 8302 */ >+ IC_VEX_W_XD, /* 8303 */ >+ IC_VEX_OPSIZE, /* 8304 */ >+ IC_VEX_OPSIZE, /* 8305 */ >+ IC_VEX_OPSIZE, /* 8306 */ >+ IC_VEX_OPSIZE, /* 8307 */ >+ IC_VEX_OPSIZE, /* 8308 */ >+ IC_VEX_OPSIZE, /* 8309 */ >+ IC_VEX_OPSIZE, /* 8310 */ >+ IC_VEX_OPSIZE, /* 8311 */ >+ IC_VEX_W_OPSIZE, /* 8312 */ >+ IC_VEX_W_OPSIZE, /* 8313 */ >+ IC_VEX_W_OPSIZE, /* 8314 */ >+ IC_VEX_W_OPSIZE, /* 8315 */ >+ IC_VEX_W_OPSIZE, /* 8316 */ >+ IC_VEX_W_OPSIZE, /* 8317 */ >+ IC_VEX_W_OPSIZE, /* 8318 */ >+ IC_VEX_W_OPSIZE, /* 8319 */ >+ IC_VEX_L, /* 8320 */ >+ IC_VEX_L, /* 8321 */ >+ IC_VEX_L_XS, /* 8322 */ >+ IC_VEX_L_XS, /* 8323 */ >+ IC_VEX_L_XD, /* 8324 */ >+ IC_VEX_L_XD, /* 8325 */ >+ IC_VEX_L_XD, /* 8326 */ >+ IC_VEX_L_XD, /* 8327 */ >+ IC_VEX_L_W, /* 8328 */ >+ IC_VEX_L_W, /* 8329 */ >+ IC_VEX_L_W_XS, /* 8330 */ >+ IC_VEX_L_W_XS, /* 8331 */ >+ IC_VEX_L_W_XD, /* 8332 */ >+ IC_VEX_L_W_XD, /* 8333 */ >+ IC_VEX_L_W_XD, /* 8334 */ >+ IC_VEX_L_W_XD, /* 8335 */ >+ IC_VEX_L_OPSIZE, /* 8336 */ >+ IC_VEX_L_OPSIZE, /* 8337 */ >+ IC_VEX_L_OPSIZE, /* 8338 */ >+ IC_VEX_L_OPSIZE, /* 8339 */ >+ IC_VEX_L_OPSIZE, /* 8340 */ >+ IC_VEX_L_OPSIZE, /* 8341 */ >+ IC_VEX_L_OPSIZE, /* 8342 */ >+ IC_VEX_L_OPSIZE, /* 8343 */ >+ IC_VEX_L_W_OPSIZE, /* 8344 */ >+ IC_VEX_L_W_OPSIZE, /* 8345 */ >+ IC_VEX_L_W_OPSIZE, /* 8346 */ >+ IC_VEX_L_W_OPSIZE, /* 8347 */ >+ IC_VEX_L_W_OPSIZE, /* 8348 */ >+ IC_VEX_L_W_OPSIZE, /* 8349 */ >+ IC_VEX_L_W_OPSIZE, /* 8350 */ >+ IC_VEX_L_W_OPSIZE, /* 8351 */ >+ IC_VEX_L, /* 8352 */ >+ IC_VEX_L, /* 8353 */ >+ IC_VEX_L_XS, /* 8354 */ >+ IC_VEX_L_XS, /* 8355 */ >+ IC_VEX_L_XD, /* 8356 */ >+ IC_VEX_L_XD, /* 8357 */ >+ IC_VEX_L_XD, /* 8358 */ >+ IC_VEX_L_XD, /* 8359 */ >+ IC_VEX_L_W, /* 8360 */ >+ IC_VEX_L_W, /* 8361 */ >+ IC_VEX_L_W_XS, /* 8362 */ >+ IC_VEX_L_W_XS, /* 8363 */ >+ IC_VEX_L_W_XD, /* 8364 */ >+ IC_VEX_L_W_XD, /* 8365 */ >+ IC_VEX_L_W_XD, /* 8366 */ >+ IC_VEX_L_W_XD, /* 8367 */ >+ IC_VEX_L_OPSIZE, /* 8368 */ >+ IC_VEX_L_OPSIZE, /* 8369 */ >+ IC_VEX_L_OPSIZE, /* 8370 */ >+ IC_VEX_L_OPSIZE, /* 8371 */ >+ IC_VEX_L_OPSIZE, /* 8372 */ >+ IC_VEX_L_OPSIZE, /* 8373 */ >+ IC_VEX_L_OPSIZE, /* 8374 */ >+ IC_VEX_L_OPSIZE, /* 8375 */ >+ IC_VEX_L_W_OPSIZE, /* 8376 */ >+ IC_VEX_L_W_OPSIZE, /* 8377 */ >+ IC_VEX_L_W_OPSIZE, /* 8378 */ >+ IC_VEX_L_W_OPSIZE, /* 8379 */ >+ IC_VEX_L_W_OPSIZE, /* 8380 */ >+ IC_VEX_L_W_OPSIZE, /* 8381 */ >+ IC_VEX_L_W_OPSIZE, /* 8382 */ >+ IC_VEX_L_W_OPSIZE, /* 8383 */ >+ IC_VEX_L, /* 8384 */ >+ IC_VEX_L, /* 8385 */ >+ IC_VEX_L_XS, /* 8386 */ >+ IC_VEX_L_XS, /* 8387 */ >+ IC_VEX_L_XD, /* 8388 */ >+ IC_VEX_L_XD, /* 8389 */ >+ IC_VEX_L_XD, /* 8390 */ >+ IC_VEX_L_XD, /* 8391 */ >+ IC_VEX_L_W, /* 8392 */ >+ IC_VEX_L_W, /* 8393 */ >+ IC_VEX_L_W_XS, /* 8394 */ >+ IC_VEX_L_W_XS, /* 8395 */ >+ IC_VEX_L_W_XD, /* 8396 */ >+ IC_VEX_L_W_XD, /* 8397 */ >+ IC_VEX_L_W_XD, /* 8398 */ >+ IC_VEX_L_W_XD, /* 8399 */ >+ IC_VEX_L_OPSIZE, /* 8400 */ >+ IC_VEX_L_OPSIZE, /* 8401 */ >+ IC_VEX_L_OPSIZE, /* 8402 */ >+ IC_VEX_L_OPSIZE, /* 8403 */ >+ IC_VEX_L_OPSIZE, /* 8404 */ >+ IC_VEX_L_OPSIZE, /* 8405 */ >+ IC_VEX_L_OPSIZE, /* 8406 */ >+ IC_VEX_L_OPSIZE, /* 8407 */ >+ IC_VEX_L_W_OPSIZE, /* 8408 */ >+ IC_VEX_L_W_OPSIZE, /* 8409 */ >+ IC_VEX_L_W_OPSIZE, /* 8410 */ >+ IC_VEX_L_W_OPSIZE, /* 8411 */ >+ IC_VEX_L_W_OPSIZE, /* 8412 */ >+ IC_VEX_L_W_OPSIZE, /* 8413 */ >+ IC_VEX_L_W_OPSIZE, /* 8414 */ >+ IC_VEX_L_W_OPSIZE, /* 8415 */ >+ IC_VEX_L, /* 8416 */ >+ IC_VEX_L, /* 8417 */ >+ IC_VEX_L_XS, /* 8418 */ >+ IC_VEX_L_XS, /* 8419 */ >+ IC_VEX_L_XD, /* 8420 */ >+ IC_VEX_L_XD, /* 8421 */ >+ IC_VEX_L_XD, /* 8422 */ >+ IC_VEX_L_XD, /* 8423 */ >+ IC_VEX_L_W, /* 8424 */ >+ IC_VEX_L_W, /* 8425 */ >+ IC_VEX_L_W_XS, /* 8426 */ >+ IC_VEX_L_W_XS, /* 8427 */ >+ IC_VEX_L_W_XD, /* 8428 */ >+ IC_VEX_L_W_XD, /* 8429 */ >+ IC_VEX_L_W_XD, /* 8430 */ >+ IC_VEX_L_W_XD, /* 8431 */ >+ IC_VEX_L_OPSIZE, /* 8432 */ >+ IC_VEX_L_OPSIZE, /* 8433 */ >+ IC_VEX_L_OPSIZE, /* 8434 */ >+ IC_VEX_L_OPSIZE, /* 8435 */ >+ IC_VEX_L_OPSIZE, /* 8436 */ >+ IC_VEX_L_OPSIZE, /* 8437 */ >+ IC_VEX_L_OPSIZE, /* 8438 */ >+ IC_VEX_L_OPSIZE, /* 8439 */ >+ IC_VEX_L_W_OPSIZE, /* 8440 */ >+ IC_VEX_L_W_OPSIZE, /* 8441 */ >+ IC_VEX_L_W_OPSIZE, /* 8442 */ >+ IC_VEX_L_W_OPSIZE, /* 8443 */ >+ IC_VEX_L_W_OPSIZE, /* 8444 */ >+ IC_VEX_L_W_OPSIZE, /* 8445 */ >+ IC_VEX_L_W_OPSIZE, /* 8446 */ >+ IC_VEX_L_W_OPSIZE, /* 8447 */ >+ IC_EVEX_B, /* 8448 */ >+ IC_EVEX_B, /* 8449 */ >+ IC_EVEX_XS_B, /* 8450 */ >+ IC_EVEX_XS_B, /* 8451 */ >+ IC_EVEX_XD_B, /* 8452 */ >+ IC_EVEX_XD_B, /* 8453 */ >+ IC_EVEX_XD_B, /* 8454 */ >+ IC_EVEX_XD_B, /* 8455 */ >+ IC_EVEX_W_B, /* 8456 */ >+ IC_EVEX_W_B, /* 8457 */ >+ IC_EVEX_W_XS_B, /* 8458 */ >+ IC_EVEX_W_XS_B, /* 8459 */ >+ IC_EVEX_W_XD_B, /* 8460 */ >+ IC_EVEX_W_XD_B, /* 8461 */ >+ IC_EVEX_W_XD_B, /* 8462 */ >+ IC_EVEX_W_XD_B, /* 8463 */ >+ IC_EVEX_OPSIZE_B, /* 8464 */ >+ IC_EVEX_OPSIZE_B, /* 8465 */ >+ IC_EVEX_OPSIZE_B, /* 8466 */ >+ IC_EVEX_OPSIZE_B, /* 8467 */ >+ IC_EVEX_OPSIZE_B, /* 8468 */ >+ IC_EVEX_OPSIZE_B, /* 8469 */ >+ IC_EVEX_OPSIZE_B, /* 8470 */ >+ IC_EVEX_OPSIZE_B, /* 8471 */ >+ IC_EVEX_W_OPSIZE_B, /* 8472 */ >+ IC_EVEX_W_OPSIZE_B, /* 8473 */ >+ IC_EVEX_W_OPSIZE_B, /* 8474 */ >+ IC_EVEX_W_OPSIZE_B, /* 8475 */ >+ IC_EVEX_W_OPSIZE_B, /* 8476 */ >+ IC_EVEX_W_OPSIZE_B, /* 8477 */ >+ IC_EVEX_W_OPSIZE_B, /* 8478 */ >+ IC_EVEX_W_OPSIZE_B, /* 8479 */ >+ IC_EVEX_B, /* 8480 */ >+ IC_EVEX_B, /* 8481 */ >+ IC_EVEX_XS_B, /* 8482 */ >+ IC_EVEX_XS_B, /* 8483 */ >+ IC_EVEX_XD_B, /* 8484 */ >+ IC_EVEX_XD_B, /* 8485 */ >+ IC_EVEX_XD_B, /* 8486 */ >+ IC_EVEX_XD_B, /* 8487 */ >+ IC_EVEX_W_B, /* 8488 */ >+ IC_EVEX_W_B, /* 8489 */ >+ IC_EVEX_W_XS_B, /* 8490 */ >+ IC_EVEX_W_XS_B, /* 8491 */ >+ IC_EVEX_W_XD_B, /* 8492 */ >+ IC_EVEX_W_XD_B, /* 8493 */ >+ IC_EVEX_W_XD_B, /* 8494 */ >+ IC_EVEX_W_XD_B, /* 8495 */ >+ IC_EVEX_OPSIZE_B, /* 8496 */ >+ IC_EVEX_OPSIZE_B, /* 8497 */ >+ IC_EVEX_OPSIZE_B, /* 8498 */ >+ IC_EVEX_OPSIZE_B, /* 8499 */ >+ IC_EVEX_OPSIZE_B, /* 8500 */ >+ IC_EVEX_OPSIZE_B, /* 8501 */ >+ IC_EVEX_OPSIZE_B, /* 8502 */ >+ IC_EVEX_OPSIZE_B, /* 8503 */ >+ IC_EVEX_W_OPSIZE_B, /* 8504 */ >+ IC_EVEX_W_OPSIZE_B, /* 8505 */ >+ IC_EVEX_W_OPSIZE_B, /* 8506 */ >+ IC_EVEX_W_OPSIZE_B, /* 8507 */ >+ IC_EVEX_W_OPSIZE_B, /* 8508 */ >+ IC_EVEX_W_OPSIZE_B, /* 8509 */ >+ IC_EVEX_W_OPSIZE_B, /* 8510 */ >+ IC_EVEX_W_OPSIZE_B, /* 8511 */ >+ IC_EVEX_B, /* 8512 */ >+ IC_EVEX_B, /* 8513 */ >+ IC_EVEX_XS_B, /* 8514 */ >+ IC_EVEX_XS_B, /* 8515 */ >+ IC_EVEX_XD_B, /* 8516 */ >+ IC_EVEX_XD_B, /* 8517 */ >+ IC_EVEX_XD_B, /* 8518 */ >+ IC_EVEX_XD_B, /* 8519 */ >+ IC_EVEX_W_B, /* 8520 */ >+ IC_EVEX_W_B, /* 8521 */ >+ IC_EVEX_W_XS_B, /* 8522 */ >+ IC_EVEX_W_XS_B, /* 8523 */ >+ IC_EVEX_W_XD_B, /* 8524 */ >+ IC_EVEX_W_XD_B, /* 8525 */ >+ IC_EVEX_W_XD_B, /* 8526 */ >+ IC_EVEX_W_XD_B, /* 8527 */ >+ IC_EVEX_OPSIZE_B, /* 8528 */ >+ IC_EVEX_OPSIZE_B, /* 8529 */ >+ IC_EVEX_OPSIZE_B, /* 8530 */ >+ IC_EVEX_OPSIZE_B, /* 8531 */ >+ IC_EVEX_OPSIZE_B, /* 8532 */ >+ IC_EVEX_OPSIZE_B, /* 8533 */ >+ IC_EVEX_OPSIZE_B, /* 8534 */ >+ IC_EVEX_OPSIZE_B, /* 8535 */ >+ IC_EVEX_W_OPSIZE_B, /* 8536 */ >+ IC_EVEX_W_OPSIZE_B, /* 8537 */ >+ IC_EVEX_W_OPSIZE_B, /* 8538 */ >+ IC_EVEX_W_OPSIZE_B, /* 8539 */ >+ IC_EVEX_W_OPSIZE_B, /* 8540 */ >+ IC_EVEX_W_OPSIZE_B, /* 8541 */ >+ IC_EVEX_W_OPSIZE_B, /* 8542 */ >+ IC_EVEX_W_OPSIZE_B, /* 8543 */ >+ IC_EVEX_B, /* 8544 */ >+ IC_EVEX_B, /* 8545 */ >+ IC_EVEX_XS_B, /* 8546 */ >+ IC_EVEX_XS_B, /* 8547 */ >+ IC_EVEX_XD_B, /* 8548 */ >+ IC_EVEX_XD_B, /* 8549 */ >+ IC_EVEX_XD_B, /* 8550 */ >+ IC_EVEX_XD_B, /* 8551 */ >+ IC_EVEX_W_B, /* 8552 */ >+ IC_EVEX_W_B, /* 8553 */ >+ IC_EVEX_W_XS_B, /* 8554 */ >+ IC_EVEX_W_XS_B, /* 8555 */ >+ IC_EVEX_W_XD_B, /* 8556 */ >+ IC_EVEX_W_XD_B, /* 8557 */ >+ IC_EVEX_W_XD_B, /* 8558 */ >+ IC_EVEX_W_XD_B, /* 8559 */ >+ IC_EVEX_OPSIZE_B, /* 8560 */ >+ IC_EVEX_OPSIZE_B, /* 8561 */ >+ IC_EVEX_OPSIZE_B, /* 8562 */ >+ IC_EVEX_OPSIZE_B, /* 8563 */ >+ IC_EVEX_OPSIZE_B, /* 8564 */ >+ IC_EVEX_OPSIZE_B, /* 8565 */ >+ IC_EVEX_OPSIZE_B, /* 8566 */ >+ IC_EVEX_OPSIZE_B, /* 8567 */ >+ IC_EVEX_W_OPSIZE_B, /* 8568 */ >+ IC_EVEX_W_OPSIZE_B, /* 8569 */ >+ IC_EVEX_W_OPSIZE_B, /* 8570 */ >+ IC_EVEX_W_OPSIZE_B, /* 8571 */ >+ IC_EVEX_W_OPSIZE_B, /* 8572 */ >+ IC_EVEX_W_OPSIZE_B, /* 8573 */ >+ IC_EVEX_W_OPSIZE_B, /* 8574 */ >+ IC_EVEX_W_OPSIZE_B, /* 8575 */ >+ IC_EVEX_B, /* 8576 */ >+ IC_EVEX_B, /* 8577 */ >+ IC_EVEX_XS_B, /* 8578 */ >+ IC_EVEX_XS_B, /* 8579 */ >+ IC_EVEX_XD_B, /* 8580 */ >+ IC_EVEX_XD_B, /* 8581 */ >+ IC_EVEX_XD_B, /* 8582 */ >+ IC_EVEX_XD_B, /* 8583 */ >+ IC_EVEX_W_B, /* 8584 */ >+ IC_EVEX_W_B, /* 8585 */ >+ IC_EVEX_W_XS_B, /* 8586 */ >+ IC_EVEX_W_XS_B, /* 8587 */ >+ IC_EVEX_W_XD_B, /* 8588 */ >+ IC_EVEX_W_XD_B, /* 8589 */ >+ IC_EVEX_W_XD_B, /* 8590 */ >+ IC_EVEX_W_XD_B, /* 8591 */ >+ IC_EVEX_OPSIZE_B, /* 8592 */ >+ IC_EVEX_OPSIZE_B, /* 8593 */ >+ IC_EVEX_OPSIZE_B, /* 8594 */ >+ IC_EVEX_OPSIZE_B, /* 8595 */ >+ IC_EVEX_OPSIZE_B, /* 8596 */ >+ IC_EVEX_OPSIZE_B, /* 8597 */ >+ IC_EVEX_OPSIZE_B, /* 8598 */ >+ IC_EVEX_OPSIZE_B, /* 8599 */ >+ IC_EVEX_W_OPSIZE_B, /* 8600 */ >+ IC_EVEX_W_OPSIZE_B, /* 8601 */ >+ IC_EVEX_W_OPSIZE_B, /* 8602 */ >+ IC_EVEX_W_OPSIZE_B, /* 8603 */ >+ IC_EVEX_W_OPSIZE_B, /* 8604 */ >+ IC_EVEX_W_OPSIZE_B, /* 8605 */ >+ IC_EVEX_W_OPSIZE_B, /* 8606 */ >+ IC_EVEX_W_OPSIZE_B, /* 8607 */ >+ IC_EVEX_B, /* 8608 */ >+ IC_EVEX_B, /* 8609 */ >+ IC_EVEX_XS_B, /* 8610 */ >+ IC_EVEX_XS_B, /* 8611 */ >+ IC_EVEX_XD_B, /* 8612 */ >+ IC_EVEX_XD_B, /* 8613 */ >+ IC_EVEX_XD_B, /* 8614 */ >+ IC_EVEX_XD_B, /* 8615 */ >+ IC_EVEX_W_B, /* 8616 */ >+ IC_EVEX_W_B, /* 8617 */ >+ IC_EVEX_W_XS_B, /* 8618 */ >+ IC_EVEX_W_XS_B, /* 8619 */ >+ IC_EVEX_W_XD_B, /* 8620 */ >+ IC_EVEX_W_XD_B, /* 8621 */ >+ IC_EVEX_W_XD_B, /* 8622 */ >+ IC_EVEX_W_XD_B, /* 8623 */ >+ IC_EVEX_OPSIZE_B, /* 8624 */ >+ IC_EVEX_OPSIZE_B, /* 8625 */ >+ IC_EVEX_OPSIZE_B, /* 8626 */ >+ IC_EVEX_OPSIZE_B, /* 8627 */ >+ IC_EVEX_OPSIZE_B, /* 8628 */ >+ IC_EVEX_OPSIZE_B, /* 8629 */ >+ IC_EVEX_OPSIZE_B, /* 8630 */ >+ IC_EVEX_OPSIZE_B, /* 8631 */ >+ IC_EVEX_W_OPSIZE_B, /* 8632 */ >+ IC_EVEX_W_OPSIZE_B, /* 8633 */ >+ IC_EVEX_W_OPSIZE_B, /* 8634 */ >+ IC_EVEX_W_OPSIZE_B, /* 8635 */ >+ IC_EVEX_W_OPSIZE_B, /* 8636 */ >+ IC_EVEX_W_OPSIZE_B, /* 8637 */ >+ IC_EVEX_W_OPSIZE_B, /* 8638 */ >+ IC_EVEX_W_OPSIZE_B, /* 8639 */ >+ IC_EVEX_B, /* 8640 */ >+ IC_EVEX_B, /* 8641 */ >+ IC_EVEX_XS_B, /* 8642 */ >+ IC_EVEX_XS_B, /* 8643 */ >+ IC_EVEX_XD_B, /* 8644 */ >+ IC_EVEX_XD_B, /* 8645 */ >+ IC_EVEX_XD_B, /* 8646 */ >+ IC_EVEX_XD_B, /* 8647 */ >+ IC_EVEX_W_B, /* 8648 */ >+ IC_EVEX_W_B, /* 8649 */ >+ IC_EVEX_W_XS_B, /* 8650 */ >+ IC_EVEX_W_XS_B, /* 8651 */ >+ IC_EVEX_W_XD_B, /* 8652 */ >+ IC_EVEX_W_XD_B, /* 8653 */ >+ IC_EVEX_W_XD_B, /* 8654 */ >+ IC_EVEX_W_XD_B, /* 8655 */ >+ IC_EVEX_OPSIZE_B, /* 8656 */ >+ IC_EVEX_OPSIZE_B, /* 8657 */ >+ IC_EVEX_OPSIZE_B, /* 8658 */ >+ IC_EVEX_OPSIZE_B, /* 8659 */ >+ IC_EVEX_OPSIZE_B, /* 8660 */ >+ IC_EVEX_OPSIZE_B, /* 8661 */ >+ IC_EVEX_OPSIZE_B, /* 8662 */ >+ IC_EVEX_OPSIZE_B, /* 8663 */ >+ IC_EVEX_W_OPSIZE_B, /* 8664 */ >+ IC_EVEX_W_OPSIZE_B, /* 8665 */ >+ IC_EVEX_W_OPSIZE_B, /* 8666 */ >+ IC_EVEX_W_OPSIZE_B, /* 8667 */ >+ IC_EVEX_W_OPSIZE_B, /* 8668 */ >+ IC_EVEX_W_OPSIZE_B, /* 8669 */ >+ IC_EVEX_W_OPSIZE_B, /* 8670 */ >+ IC_EVEX_W_OPSIZE_B, /* 8671 */ >+ IC_EVEX_B, /* 8672 */ >+ IC_EVEX_B, /* 8673 */ >+ IC_EVEX_XS_B, /* 8674 */ >+ IC_EVEX_XS_B, /* 8675 */ >+ IC_EVEX_XD_B, /* 8676 */ >+ IC_EVEX_XD_B, /* 8677 */ >+ IC_EVEX_XD_B, /* 8678 */ >+ IC_EVEX_XD_B, /* 8679 */ >+ IC_EVEX_W_B, /* 8680 */ >+ IC_EVEX_W_B, /* 8681 */ >+ IC_EVEX_W_XS_B, /* 8682 */ >+ IC_EVEX_W_XS_B, /* 8683 */ >+ IC_EVEX_W_XD_B, /* 8684 */ >+ IC_EVEX_W_XD_B, /* 8685 */ >+ IC_EVEX_W_XD_B, /* 8686 */ >+ IC_EVEX_W_XD_B, /* 8687 */ >+ IC_EVEX_OPSIZE_B, /* 8688 */ >+ IC_EVEX_OPSIZE_B, /* 8689 */ >+ IC_EVEX_OPSIZE_B, /* 8690 */ >+ IC_EVEX_OPSIZE_B, /* 8691 */ >+ IC_EVEX_OPSIZE_B, /* 8692 */ >+ IC_EVEX_OPSIZE_B, /* 8693 */ >+ IC_EVEX_OPSIZE_B, /* 8694 */ >+ IC_EVEX_OPSIZE_B, /* 8695 */ >+ IC_EVEX_W_OPSIZE_B, /* 8696 */ >+ IC_EVEX_W_OPSIZE_B, /* 8697 */ >+ IC_EVEX_W_OPSIZE_B, /* 8698 */ >+ IC_EVEX_W_OPSIZE_B, /* 8699 */ >+ IC_EVEX_W_OPSIZE_B, /* 8700 */ >+ IC_EVEX_W_OPSIZE_B, /* 8701 */ >+ IC_EVEX_W_OPSIZE_B, /* 8702 */ >+ IC_EVEX_W_OPSIZE_B, /* 8703 */ >+ IC, /* 8704 */ >+ IC_64BIT, /* 8705 */ >+ IC_XS, /* 8706 */ >+ IC_64BIT_XS, /* 8707 */ >+ IC_XD, /* 8708 */ >+ IC_64BIT_XD, /* 8709 */ >+ IC_XS, /* 8710 */ >+ IC_64BIT_XS, /* 8711 */ >+ IC, /* 8712 */ >+ IC_64BIT_REXW, /* 8713 */ >+ IC_XS, /* 8714 */ >+ IC_64BIT_REXW_XS, /* 8715 */ >+ IC_XD, /* 8716 */ >+ IC_64BIT_REXW_XD, /* 8717 */ >+ IC_XS, /* 8718 */ >+ IC_64BIT_REXW_XS, /* 8719 */ >+ IC_OPSIZE, /* 8720 */ >+ IC_64BIT_OPSIZE, /* 8721 */ >+ IC_XS_OPSIZE, /* 8722 */ >+ IC_64BIT_XS_OPSIZE, /* 8723 */ >+ IC_XD_OPSIZE, /* 8724 */ >+ IC_64BIT_XD_OPSIZE, /* 8725 */ >+ IC_XS_OPSIZE, /* 8726 */ >+ IC_64BIT_XD_OPSIZE, /* 8727 */ >+ IC_OPSIZE, /* 8728 */ >+ IC_64BIT_REXW_OPSIZE, /* 8729 */ >+ IC_XS_OPSIZE, /* 8730 */ >+ IC_64BIT_REXW_XS, /* 8731 */ >+ IC_XD_OPSIZE, /* 8732 */ >+ IC_64BIT_REXW_XD, /* 8733 */ >+ IC_XS_OPSIZE, /* 8734 */ >+ IC_64BIT_REXW_XS, /* 8735 */ >+ IC_ADSIZE, /* 8736 */ >+ IC_64BIT_ADSIZE, /* 8737 */ >+ IC_XS, /* 8738 */ >+ IC_64BIT_XS, /* 8739 */ >+ IC_XD, /* 8740 */ >+ IC_64BIT_XD, /* 8741 */ >+ IC_XS, /* 8742 */ >+ IC_64BIT_XS, /* 8743 */ >+ IC_ADSIZE, /* 8744 */ >+ IC_64BIT_ADSIZE, /* 8745 */ >+ IC_XS, /* 8746 */ >+ IC_64BIT_REXW_XS, /* 8747 */ >+ IC_XD, /* 8748 */ >+ IC_64BIT_REXW_XD, /* 8749 */ >+ IC_XS, /* 8750 */ >+ IC_64BIT_REXW_XS, /* 8751 */ >+ IC_OPSIZE, /* 8752 */ >+ IC_64BIT_OPSIZE, /* 8753 */ >+ IC_XS_OPSIZE, /* 8754 */ >+ IC_64BIT_XS_OPSIZE, /* 8755 */ >+ IC_XD_OPSIZE, /* 8756 */ >+ IC_64BIT_XD_OPSIZE, /* 8757 */ >+ IC_XS_OPSIZE, /* 8758 */ >+ IC_64BIT_XD_OPSIZE, /* 8759 */ >+ IC_OPSIZE, /* 8760 */ >+ IC_64BIT_REXW_OPSIZE, /* 8761 */ >+ IC_XS_OPSIZE, /* 8762 */ >+ IC_64BIT_REXW_XS, /* 8763 */ >+ IC_XD_OPSIZE, /* 8764 */ >+ IC_64BIT_REXW_XD, /* 8765 */ >+ IC_XS_OPSIZE, /* 8766 */ >+ IC_64BIT_REXW_XS, /* 8767 */ >+ IC_VEX, /* 8768 */ >+ IC_VEX, /* 8769 */ >+ IC_VEX_XS, /* 8770 */ >+ IC_VEX_XS, /* 8771 */ >+ IC_VEX_XD, /* 8772 */ >+ IC_VEX_XD, /* 8773 */ >+ IC_VEX_XD, /* 8774 */ >+ IC_VEX_XD, /* 8775 */ >+ IC_VEX_W, /* 8776 */ >+ IC_VEX_W, /* 8777 */ >+ IC_VEX_W_XS, /* 8778 */ >+ IC_VEX_W_XS, /* 8779 */ >+ IC_VEX_W_XD, /* 8780 */ >+ IC_VEX_W_XD, /* 8781 */ >+ IC_VEX_W_XD, /* 8782 */ >+ IC_VEX_W_XD, /* 8783 */ >+ IC_VEX_OPSIZE, /* 8784 */ >+ IC_VEX_OPSIZE, /* 8785 */ >+ IC_VEX_OPSIZE, /* 8786 */ >+ IC_VEX_OPSIZE, /* 8787 */ >+ IC_VEX_OPSIZE, /* 8788 */ >+ IC_VEX_OPSIZE, /* 8789 */ >+ IC_VEX_OPSIZE, /* 8790 */ >+ IC_VEX_OPSIZE, /* 8791 */ >+ IC_VEX_W_OPSIZE, /* 8792 */ >+ IC_VEX_W_OPSIZE, /* 8793 */ >+ IC_VEX_W_OPSIZE, /* 8794 */ >+ IC_VEX_W_OPSIZE, /* 8795 */ >+ IC_VEX_W_OPSIZE, /* 8796 */ >+ IC_VEX_W_OPSIZE, /* 8797 */ >+ IC_VEX_W_OPSIZE, /* 8798 */ >+ IC_VEX_W_OPSIZE, /* 8799 */ >+ IC_VEX, /* 8800 */ >+ IC_VEX, /* 8801 */ >+ IC_VEX_XS, /* 8802 */ >+ IC_VEX_XS, /* 8803 */ >+ IC_VEX_XD, /* 8804 */ >+ IC_VEX_XD, /* 8805 */ >+ IC_VEX_XD, /* 8806 */ >+ IC_VEX_XD, /* 8807 */ >+ IC_VEX_W, /* 8808 */ >+ IC_VEX_W, /* 8809 */ >+ IC_VEX_W_XS, /* 8810 */ >+ IC_VEX_W_XS, /* 8811 */ >+ IC_VEX_W_XD, /* 8812 */ >+ IC_VEX_W_XD, /* 8813 */ >+ IC_VEX_W_XD, /* 8814 */ >+ IC_VEX_W_XD, /* 8815 */ >+ IC_VEX_OPSIZE, /* 8816 */ >+ IC_VEX_OPSIZE, /* 8817 */ >+ IC_VEX_OPSIZE, /* 8818 */ >+ IC_VEX_OPSIZE, /* 8819 */ >+ IC_VEX_OPSIZE, /* 8820 */ >+ IC_VEX_OPSIZE, /* 8821 */ >+ IC_VEX_OPSIZE, /* 8822 */ >+ IC_VEX_OPSIZE, /* 8823 */ >+ IC_VEX_W_OPSIZE, /* 8824 */ >+ IC_VEX_W_OPSIZE, /* 8825 */ >+ IC_VEX_W_OPSIZE, /* 8826 */ >+ IC_VEX_W_OPSIZE, /* 8827 */ >+ IC_VEX_W_OPSIZE, /* 8828 */ >+ IC_VEX_W_OPSIZE, /* 8829 */ >+ IC_VEX_W_OPSIZE, /* 8830 */ >+ IC_VEX_W_OPSIZE, /* 8831 */ >+ IC_VEX_L, /* 8832 */ >+ IC_VEX_L, /* 8833 */ >+ IC_VEX_L_XS, /* 8834 */ >+ IC_VEX_L_XS, /* 8835 */ >+ IC_VEX_L_XD, /* 8836 */ >+ IC_VEX_L_XD, /* 8837 */ >+ IC_VEX_L_XD, /* 8838 */ >+ IC_VEX_L_XD, /* 8839 */ >+ IC_VEX_L_W, /* 8840 */ >+ IC_VEX_L_W, /* 8841 */ >+ IC_VEX_L_W_XS, /* 8842 */ >+ IC_VEX_L_W_XS, /* 8843 */ >+ IC_VEX_L_W_XD, /* 8844 */ >+ IC_VEX_L_W_XD, /* 8845 */ >+ IC_VEX_L_W_XD, /* 8846 */ >+ IC_VEX_L_W_XD, /* 8847 */ >+ IC_VEX_L_OPSIZE, /* 8848 */ >+ IC_VEX_L_OPSIZE, /* 8849 */ >+ IC_VEX_L_OPSIZE, /* 8850 */ >+ IC_VEX_L_OPSIZE, /* 8851 */ >+ IC_VEX_L_OPSIZE, /* 8852 */ >+ IC_VEX_L_OPSIZE, /* 8853 */ >+ IC_VEX_L_OPSIZE, /* 8854 */ >+ IC_VEX_L_OPSIZE, /* 8855 */ >+ IC_VEX_L_W_OPSIZE, /* 8856 */ >+ IC_VEX_L_W_OPSIZE, /* 8857 */ >+ IC_VEX_L_W_OPSIZE, /* 8858 */ >+ IC_VEX_L_W_OPSIZE, /* 8859 */ >+ IC_VEX_L_W_OPSIZE, /* 8860 */ >+ IC_VEX_L_W_OPSIZE, /* 8861 */ >+ IC_VEX_L_W_OPSIZE, /* 8862 */ >+ IC_VEX_L_W_OPSIZE, /* 8863 */ >+ IC_VEX_L, /* 8864 */ >+ IC_VEX_L, /* 8865 */ >+ IC_VEX_L_XS, /* 8866 */ >+ IC_VEX_L_XS, /* 8867 */ >+ IC_VEX_L_XD, /* 8868 */ >+ IC_VEX_L_XD, /* 8869 */ >+ IC_VEX_L_XD, /* 8870 */ >+ IC_VEX_L_XD, /* 8871 */ >+ IC_VEX_L_W, /* 8872 */ >+ IC_VEX_L_W, /* 8873 */ >+ IC_VEX_L_W_XS, /* 8874 */ >+ IC_VEX_L_W_XS, /* 8875 */ >+ IC_VEX_L_W_XD, /* 8876 */ >+ IC_VEX_L_W_XD, /* 8877 */ >+ IC_VEX_L_W_XD, /* 8878 */ >+ IC_VEX_L_W_XD, /* 8879 */ >+ IC_VEX_L_OPSIZE, /* 8880 */ >+ IC_VEX_L_OPSIZE, /* 8881 */ >+ IC_VEX_L_OPSIZE, /* 8882 */ >+ IC_VEX_L_OPSIZE, /* 8883 */ >+ IC_VEX_L_OPSIZE, /* 8884 */ >+ IC_VEX_L_OPSIZE, /* 8885 */ >+ IC_VEX_L_OPSIZE, /* 8886 */ >+ IC_VEX_L_OPSIZE, /* 8887 */ >+ IC_VEX_L_W_OPSIZE, /* 8888 */ >+ IC_VEX_L_W_OPSIZE, /* 8889 */ >+ IC_VEX_L_W_OPSIZE, /* 8890 */ >+ IC_VEX_L_W_OPSIZE, /* 8891 */ >+ IC_VEX_L_W_OPSIZE, /* 8892 */ >+ IC_VEX_L_W_OPSIZE, /* 8893 */ >+ IC_VEX_L_W_OPSIZE, /* 8894 */ >+ IC_VEX_L_W_OPSIZE, /* 8895 */ >+ IC_VEX_L, /* 8896 */ >+ IC_VEX_L, /* 8897 */ >+ IC_VEX_L_XS, /* 8898 */ >+ IC_VEX_L_XS, /* 8899 */ >+ IC_VEX_L_XD, /* 8900 */ >+ IC_VEX_L_XD, /* 8901 */ >+ IC_VEX_L_XD, /* 8902 */ >+ IC_VEX_L_XD, /* 8903 */ >+ IC_VEX_L_W, /* 8904 */ >+ IC_VEX_L_W, /* 8905 */ >+ IC_VEX_L_W_XS, /* 8906 */ >+ IC_VEX_L_W_XS, /* 8907 */ >+ IC_VEX_L_W_XD, /* 8908 */ >+ IC_VEX_L_W_XD, /* 8909 */ >+ IC_VEX_L_W_XD, /* 8910 */ >+ IC_VEX_L_W_XD, /* 8911 */ >+ IC_VEX_L_OPSIZE, /* 8912 */ >+ IC_VEX_L_OPSIZE, /* 8913 */ >+ IC_VEX_L_OPSIZE, /* 8914 */ >+ IC_VEX_L_OPSIZE, /* 8915 */ >+ IC_VEX_L_OPSIZE, /* 8916 */ >+ IC_VEX_L_OPSIZE, /* 8917 */ >+ IC_VEX_L_OPSIZE, /* 8918 */ >+ IC_VEX_L_OPSIZE, /* 8919 */ >+ IC_VEX_L_W_OPSIZE, /* 8920 */ >+ IC_VEX_L_W_OPSIZE, /* 8921 */ >+ IC_VEX_L_W_OPSIZE, /* 8922 */ >+ IC_VEX_L_W_OPSIZE, /* 8923 */ >+ IC_VEX_L_W_OPSIZE, /* 8924 */ >+ IC_VEX_L_W_OPSIZE, /* 8925 */ >+ IC_VEX_L_W_OPSIZE, /* 8926 */ >+ IC_VEX_L_W_OPSIZE, /* 8927 */ >+ IC_VEX_L, /* 8928 */ >+ IC_VEX_L, /* 8929 */ >+ IC_VEX_L_XS, /* 8930 */ >+ IC_VEX_L_XS, /* 8931 */ >+ IC_VEX_L_XD, /* 8932 */ >+ IC_VEX_L_XD, /* 8933 */ >+ IC_VEX_L_XD, /* 8934 */ >+ IC_VEX_L_XD, /* 8935 */ >+ IC_VEX_L_W, /* 8936 */ >+ IC_VEX_L_W, /* 8937 */ >+ IC_VEX_L_W_XS, /* 8938 */ >+ IC_VEX_L_W_XS, /* 8939 */ >+ IC_VEX_L_W_XD, /* 8940 */ >+ IC_VEX_L_W_XD, /* 8941 */ >+ IC_VEX_L_W_XD, /* 8942 */ >+ IC_VEX_L_W_XD, /* 8943 */ >+ IC_VEX_L_OPSIZE, /* 8944 */ >+ IC_VEX_L_OPSIZE, /* 8945 */ >+ IC_VEX_L_OPSIZE, /* 8946 */ >+ IC_VEX_L_OPSIZE, /* 8947 */ >+ IC_VEX_L_OPSIZE, /* 8948 */ >+ IC_VEX_L_OPSIZE, /* 8949 */ >+ IC_VEX_L_OPSIZE, /* 8950 */ >+ IC_VEX_L_OPSIZE, /* 8951 */ >+ IC_VEX_L_W_OPSIZE, /* 8952 */ >+ IC_VEX_L_W_OPSIZE, /* 8953 */ >+ IC_VEX_L_W_OPSIZE, /* 8954 */ >+ IC_VEX_L_W_OPSIZE, /* 8955 */ >+ IC_VEX_L_W_OPSIZE, /* 8956 */ >+ IC_VEX_L_W_OPSIZE, /* 8957 */ >+ IC_VEX_L_W_OPSIZE, /* 8958 */ >+ IC_VEX_L_W_OPSIZE, /* 8959 */ >+ IC_EVEX_L_B, /* 8960 */ >+ IC_EVEX_L_B, /* 8961 */ >+ IC_EVEX_L_XS_B, /* 8962 */ >+ IC_EVEX_L_XS_B, /* 8963 */ >+ IC_EVEX_L_XD_B, /* 8964 */ >+ IC_EVEX_L_XD_B, /* 8965 */ >+ IC_EVEX_L_XD_B, /* 8966 */ >+ IC_EVEX_L_XD_B, /* 8967 */ >+ IC_EVEX_L_W_B, /* 8968 */ >+ IC_EVEX_L_W_B, /* 8969 */ >+ IC_EVEX_L_W_XS_B, /* 8970 */ >+ IC_EVEX_L_W_XS_B, /* 8971 */ >+ IC_EVEX_L_W_XD_B, /* 8972 */ >+ IC_EVEX_L_W_XD_B, /* 8973 */ >+ IC_EVEX_L_W_XD_B, /* 8974 */ >+ IC_EVEX_L_W_XD_B, /* 8975 */ >+ IC_EVEX_L_OPSIZE_B, /* 8976 */ >+ IC_EVEX_L_OPSIZE_B, /* 8977 */ >+ IC_EVEX_L_OPSIZE_B, /* 8978 */ >+ IC_EVEX_L_OPSIZE_B, /* 8979 */ >+ IC_EVEX_L_OPSIZE_B, /* 8980 */ >+ IC_EVEX_L_OPSIZE_B, /* 8981 */ >+ IC_EVEX_L_OPSIZE_B, /* 8982 */ >+ IC_EVEX_L_OPSIZE_B, /* 8983 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8984 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8985 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8986 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8987 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8988 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8989 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8990 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 8991 */ >+ IC_EVEX_L_B, /* 8992 */ >+ IC_EVEX_L_B, /* 8993 */ >+ IC_EVEX_L_XS_B, /* 8994 */ >+ IC_EVEX_L_XS_B, /* 8995 */ >+ IC_EVEX_L_XD_B, /* 8996 */ >+ IC_EVEX_L_XD_B, /* 8997 */ >+ IC_EVEX_L_XD_B, /* 8998 */ >+ IC_EVEX_L_XD_B, /* 8999 */ >+ IC_EVEX_L_W_B, /* 9000 */ >+ IC_EVEX_L_W_B, /* 9001 */ >+ IC_EVEX_L_W_XS_B, /* 9002 */ >+ IC_EVEX_L_W_XS_B, /* 9003 */ >+ IC_EVEX_L_W_XD_B, /* 9004 */ >+ IC_EVEX_L_W_XD_B, /* 9005 */ >+ IC_EVEX_L_W_XD_B, /* 9006 */ >+ IC_EVEX_L_W_XD_B, /* 9007 */ >+ IC_EVEX_L_OPSIZE_B, /* 9008 */ >+ IC_EVEX_L_OPSIZE_B, /* 9009 */ >+ IC_EVEX_L_OPSIZE_B, /* 9010 */ >+ IC_EVEX_L_OPSIZE_B, /* 9011 */ >+ IC_EVEX_L_OPSIZE_B, /* 9012 */ >+ IC_EVEX_L_OPSIZE_B, /* 9013 */ >+ IC_EVEX_L_OPSIZE_B, /* 9014 */ >+ IC_EVEX_L_OPSIZE_B, /* 9015 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9016 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9017 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9018 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9019 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9020 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9021 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9022 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9023 */ >+ IC_EVEX_L_B, /* 9024 */ >+ IC_EVEX_L_B, /* 9025 */ >+ IC_EVEX_L_XS_B, /* 9026 */ >+ IC_EVEX_L_XS_B, /* 9027 */ >+ IC_EVEX_L_XD_B, /* 9028 */ >+ IC_EVEX_L_XD_B, /* 9029 */ >+ IC_EVEX_L_XD_B, /* 9030 */ >+ IC_EVEX_L_XD_B, /* 9031 */ >+ IC_EVEX_L_W_B, /* 9032 */ >+ IC_EVEX_L_W_B, /* 9033 */ >+ IC_EVEX_L_W_XS_B, /* 9034 */ >+ IC_EVEX_L_W_XS_B, /* 9035 */ >+ IC_EVEX_L_W_XD_B, /* 9036 */ >+ IC_EVEX_L_W_XD_B, /* 9037 */ >+ IC_EVEX_L_W_XD_B, /* 9038 */ >+ IC_EVEX_L_W_XD_B, /* 9039 */ >+ IC_EVEX_L_OPSIZE_B, /* 9040 */ >+ IC_EVEX_L_OPSIZE_B, /* 9041 */ >+ IC_EVEX_L_OPSIZE_B, /* 9042 */ >+ IC_EVEX_L_OPSIZE_B, /* 9043 */ >+ IC_EVEX_L_OPSIZE_B, /* 9044 */ >+ IC_EVEX_L_OPSIZE_B, /* 9045 */ >+ IC_EVEX_L_OPSIZE_B, /* 9046 */ >+ IC_EVEX_L_OPSIZE_B, /* 9047 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9048 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9049 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9050 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9051 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9052 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9053 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9054 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9055 */ >+ IC_EVEX_L_B, /* 9056 */ >+ IC_EVEX_L_B, /* 9057 */ >+ IC_EVEX_L_XS_B, /* 9058 */ >+ IC_EVEX_L_XS_B, /* 9059 */ >+ IC_EVEX_L_XD_B, /* 9060 */ >+ IC_EVEX_L_XD_B, /* 9061 */ >+ IC_EVEX_L_XD_B, /* 9062 */ >+ IC_EVEX_L_XD_B, /* 9063 */ >+ IC_EVEX_L_W_B, /* 9064 */ >+ IC_EVEX_L_W_B, /* 9065 */ >+ IC_EVEX_L_W_XS_B, /* 9066 */ >+ IC_EVEX_L_W_XS_B, /* 9067 */ >+ IC_EVEX_L_W_XD_B, /* 9068 */ >+ IC_EVEX_L_W_XD_B, /* 9069 */ >+ IC_EVEX_L_W_XD_B, /* 9070 */ >+ IC_EVEX_L_W_XD_B, /* 9071 */ >+ IC_EVEX_L_OPSIZE_B, /* 9072 */ >+ IC_EVEX_L_OPSIZE_B, /* 9073 */ >+ IC_EVEX_L_OPSIZE_B, /* 9074 */ >+ IC_EVEX_L_OPSIZE_B, /* 9075 */ >+ IC_EVEX_L_OPSIZE_B, /* 9076 */ >+ IC_EVEX_L_OPSIZE_B, /* 9077 */ >+ IC_EVEX_L_OPSIZE_B, /* 9078 */ >+ IC_EVEX_L_OPSIZE_B, /* 9079 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9080 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9081 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9082 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9083 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9084 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9085 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9086 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9087 */ >+ IC_EVEX_L_B, /* 9088 */ >+ IC_EVEX_L_B, /* 9089 */ >+ IC_EVEX_L_XS_B, /* 9090 */ >+ IC_EVEX_L_XS_B, /* 9091 */ >+ IC_EVEX_L_XD_B, /* 9092 */ >+ IC_EVEX_L_XD_B, /* 9093 */ >+ IC_EVEX_L_XD_B, /* 9094 */ >+ IC_EVEX_L_XD_B, /* 9095 */ >+ IC_EVEX_L_W_B, /* 9096 */ >+ IC_EVEX_L_W_B, /* 9097 */ >+ IC_EVEX_L_W_XS_B, /* 9098 */ >+ IC_EVEX_L_W_XS_B, /* 9099 */ >+ IC_EVEX_L_W_XD_B, /* 9100 */ >+ IC_EVEX_L_W_XD_B, /* 9101 */ >+ IC_EVEX_L_W_XD_B, /* 9102 */ >+ IC_EVEX_L_W_XD_B, /* 9103 */ >+ IC_EVEX_L_OPSIZE_B, /* 9104 */ >+ IC_EVEX_L_OPSIZE_B, /* 9105 */ >+ IC_EVEX_L_OPSIZE_B, /* 9106 */ >+ IC_EVEX_L_OPSIZE_B, /* 9107 */ >+ IC_EVEX_L_OPSIZE_B, /* 9108 */ >+ IC_EVEX_L_OPSIZE_B, /* 9109 */ >+ IC_EVEX_L_OPSIZE_B, /* 9110 */ >+ IC_EVEX_L_OPSIZE_B, /* 9111 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9112 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9113 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9114 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9115 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9116 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9117 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9118 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9119 */ >+ IC_EVEX_L_B, /* 9120 */ >+ IC_EVEX_L_B, /* 9121 */ >+ IC_EVEX_L_XS_B, /* 9122 */ >+ IC_EVEX_L_XS_B, /* 9123 */ >+ IC_EVEX_L_XD_B, /* 9124 */ >+ IC_EVEX_L_XD_B, /* 9125 */ >+ IC_EVEX_L_XD_B, /* 9126 */ >+ IC_EVEX_L_XD_B, /* 9127 */ >+ IC_EVEX_L_W_B, /* 9128 */ >+ IC_EVEX_L_W_B, /* 9129 */ >+ IC_EVEX_L_W_XS_B, /* 9130 */ >+ IC_EVEX_L_W_XS_B, /* 9131 */ >+ IC_EVEX_L_W_XD_B, /* 9132 */ >+ IC_EVEX_L_W_XD_B, /* 9133 */ >+ IC_EVEX_L_W_XD_B, /* 9134 */ >+ IC_EVEX_L_W_XD_B, /* 9135 */ >+ IC_EVEX_L_OPSIZE_B, /* 9136 */ >+ IC_EVEX_L_OPSIZE_B, /* 9137 */ >+ IC_EVEX_L_OPSIZE_B, /* 9138 */ >+ IC_EVEX_L_OPSIZE_B, /* 9139 */ >+ IC_EVEX_L_OPSIZE_B, /* 9140 */ >+ IC_EVEX_L_OPSIZE_B, /* 9141 */ >+ IC_EVEX_L_OPSIZE_B, /* 9142 */ >+ IC_EVEX_L_OPSIZE_B, /* 9143 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9144 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9145 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9146 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9147 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9148 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9149 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9150 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9151 */ >+ IC_EVEX_L_B, /* 9152 */ >+ IC_EVEX_L_B, /* 9153 */ >+ IC_EVEX_L_XS_B, /* 9154 */ >+ IC_EVEX_L_XS_B, /* 9155 */ >+ IC_EVEX_L_XD_B, /* 9156 */ >+ IC_EVEX_L_XD_B, /* 9157 */ >+ IC_EVEX_L_XD_B, /* 9158 */ >+ IC_EVEX_L_XD_B, /* 9159 */ >+ IC_EVEX_L_W_B, /* 9160 */ >+ IC_EVEX_L_W_B, /* 9161 */ >+ IC_EVEX_L_W_XS_B, /* 9162 */ >+ IC_EVEX_L_W_XS_B, /* 9163 */ >+ IC_EVEX_L_W_XD_B, /* 9164 */ >+ IC_EVEX_L_W_XD_B, /* 9165 */ >+ IC_EVEX_L_W_XD_B, /* 9166 */ >+ IC_EVEX_L_W_XD_B, /* 9167 */ >+ IC_EVEX_L_OPSIZE_B, /* 9168 */ >+ IC_EVEX_L_OPSIZE_B, /* 9169 */ >+ IC_EVEX_L_OPSIZE_B, /* 9170 */ >+ IC_EVEX_L_OPSIZE_B, /* 9171 */ >+ IC_EVEX_L_OPSIZE_B, /* 9172 */ >+ IC_EVEX_L_OPSIZE_B, /* 9173 */ >+ IC_EVEX_L_OPSIZE_B, /* 9174 */ >+ IC_EVEX_L_OPSIZE_B, /* 9175 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9176 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9177 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9178 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9179 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9180 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9181 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9182 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9183 */ >+ IC_EVEX_L_B, /* 9184 */ >+ IC_EVEX_L_B, /* 9185 */ >+ IC_EVEX_L_XS_B, /* 9186 */ >+ IC_EVEX_L_XS_B, /* 9187 */ >+ IC_EVEX_L_XD_B, /* 9188 */ >+ IC_EVEX_L_XD_B, /* 9189 */ >+ IC_EVEX_L_XD_B, /* 9190 */ >+ IC_EVEX_L_XD_B, /* 9191 */ >+ IC_EVEX_L_W_B, /* 9192 */ >+ IC_EVEX_L_W_B, /* 9193 */ >+ IC_EVEX_L_W_XS_B, /* 9194 */ >+ IC_EVEX_L_W_XS_B, /* 9195 */ >+ IC_EVEX_L_W_XD_B, /* 9196 */ >+ IC_EVEX_L_W_XD_B, /* 9197 */ >+ IC_EVEX_L_W_XD_B, /* 9198 */ >+ IC_EVEX_L_W_XD_B, /* 9199 */ >+ IC_EVEX_L_OPSIZE_B, /* 9200 */ >+ IC_EVEX_L_OPSIZE_B, /* 9201 */ >+ IC_EVEX_L_OPSIZE_B, /* 9202 */ >+ IC_EVEX_L_OPSIZE_B, /* 9203 */ >+ IC_EVEX_L_OPSIZE_B, /* 9204 */ >+ IC_EVEX_L_OPSIZE_B, /* 9205 */ >+ IC_EVEX_L_OPSIZE_B, /* 9206 */ >+ IC_EVEX_L_OPSIZE_B, /* 9207 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9208 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9209 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9210 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9211 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9212 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9213 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9214 */ >+ IC_EVEX_L_W_OPSIZE_B, /* 9215 */ >+ IC, /* 9216 */ >+ IC_64BIT, /* 9217 */ >+ IC_XS, /* 9218 */ >+ IC_64BIT_XS, /* 9219 */ >+ IC_XD, /* 9220 */ >+ IC_64BIT_XD, /* 9221 */ >+ IC_XS, /* 9222 */ >+ IC_64BIT_XS, /* 9223 */ >+ IC, /* 9224 */ >+ IC_64BIT_REXW, /* 9225 */ >+ IC_XS, /* 9226 */ >+ IC_64BIT_REXW_XS, /* 9227 */ >+ IC_XD, /* 9228 */ >+ IC_64BIT_REXW_XD, /* 9229 */ >+ IC_XS, /* 9230 */ >+ IC_64BIT_REXW_XS, /* 9231 */ >+ IC_OPSIZE, /* 9232 */ >+ IC_64BIT_OPSIZE, /* 9233 */ >+ IC_XS_OPSIZE, /* 9234 */ >+ IC_64BIT_XS_OPSIZE, /* 9235 */ >+ IC_XD_OPSIZE, /* 9236 */ >+ IC_64BIT_XD_OPSIZE, /* 9237 */ >+ IC_XS_OPSIZE, /* 9238 */ >+ IC_64BIT_XD_OPSIZE, /* 9239 */ >+ IC_OPSIZE, /* 9240 */ >+ IC_64BIT_REXW_OPSIZE, /* 9241 */ >+ IC_XS_OPSIZE, /* 9242 */ >+ IC_64BIT_REXW_XS, /* 9243 */ >+ IC_XD_OPSIZE, /* 9244 */ >+ IC_64BIT_REXW_XD, /* 9245 */ >+ IC_XS_OPSIZE, /* 9246 */ >+ IC_64BIT_REXW_XS, /* 9247 */ >+ IC_ADSIZE, /* 9248 */ >+ IC_64BIT_ADSIZE, /* 9249 */ >+ IC_XS, /* 9250 */ >+ IC_64BIT_XS, /* 9251 */ >+ IC_XD, /* 9252 */ >+ IC_64BIT_XD, /* 9253 */ >+ IC_XS, /* 9254 */ >+ IC_64BIT_XS, /* 9255 */ >+ IC_ADSIZE, /* 9256 */ >+ IC_64BIT_ADSIZE, /* 9257 */ >+ IC_XS, /* 9258 */ >+ IC_64BIT_REXW_XS, /* 9259 */ >+ IC_XD, /* 9260 */ >+ IC_64BIT_REXW_XD, /* 9261 */ >+ IC_XS, /* 9262 */ >+ IC_64BIT_REXW_XS, /* 9263 */ >+ IC_OPSIZE, /* 9264 */ >+ IC_64BIT_OPSIZE, /* 9265 */ >+ IC_XS_OPSIZE, /* 9266 */ >+ IC_64BIT_XS_OPSIZE, /* 9267 */ >+ IC_XD_OPSIZE, /* 9268 */ >+ IC_64BIT_XD_OPSIZE, /* 9269 */ >+ IC_XS_OPSIZE, /* 9270 */ >+ IC_64BIT_XD_OPSIZE, /* 9271 */ >+ IC_OPSIZE, /* 9272 */ >+ IC_64BIT_REXW_OPSIZE, /* 9273 */ >+ IC_XS_OPSIZE, /* 9274 */ >+ IC_64BIT_REXW_XS, /* 9275 */ >+ IC_XD_OPSIZE, /* 9276 */ >+ IC_64BIT_REXW_XD, /* 9277 */ >+ IC_XS_OPSIZE, /* 9278 */ >+ IC_64BIT_REXW_XS, /* 9279 */ >+ IC_VEX, /* 9280 */ >+ IC_VEX, /* 9281 */ >+ IC_VEX_XS, /* 9282 */ >+ IC_VEX_XS, /* 9283 */ >+ IC_VEX_XD, /* 9284 */ >+ IC_VEX_XD, /* 9285 */ >+ IC_VEX_XD, /* 9286 */ >+ IC_VEX_XD, /* 9287 */ >+ IC_VEX_W, /* 9288 */ >+ IC_VEX_W, /* 9289 */ >+ IC_VEX_W_XS, /* 9290 */ >+ IC_VEX_W_XS, /* 9291 */ >+ IC_VEX_W_XD, /* 9292 */ >+ IC_VEX_W_XD, /* 9293 */ >+ IC_VEX_W_XD, /* 9294 */ >+ IC_VEX_W_XD, /* 9295 */ >+ IC_VEX_OPSIZE, /* 9296 */ >+ IC_VEX_OPSIZE, /* 9297 */ >+ IC_VEX_OPSIZE, /* 9298 */ >+ IC_VEX_OPSIZE, /* 9299 */ >+ IC_VEX_OPSIZE, /* 9300 */ >+ IC_VEX_OPSIZE, /* 9301 */ >+ IC_VEX_OPSIZE, /* 9302 */ >+ IC_VEX_OPSIZE, /* 9303 */ >+ IC_VEX_W_OPSIZE, /* 9304 */ >+ IC_VEX_W_OPSIZE, /* 9305 */ >+ IC_VEX_W_OPSIZE, /* 9306 */ >+ IC_VEX_W_OPSIZE, /* 9307 */ >+ IC_VEX_W_OPSIZE, /* 9308 */ >+ IC_VEX_W_OPSIZE, /* 9309 */ >+ IC_VEX_W_OPSIZE, /* 9310 */ >+ IC_VEX_W_OPSIZE, /* 9311 */ >+ IC_VEX, /* 9312 */ >+ IC_VEX, /* 9313 */ >+ IC_VEX_XS, /* 9314 */ >+ IC_VEX_XS, /* 9315 */ >+ IC_VEX_XD, /* 9316 */ >+ IC_VEX_XD, /* 9317 */ >+ IC_VEX_XD, /* 9318 */ >+ IC_VEX_XD, /* 9319 */ >+ IC_VEX_W, /* 9320 */ >+ IC_VEX_W, /* 9321 */ >+ IC_VEX_W_XS, /* 9322 */ >+ IC_VEX_W_XS, /* 9323 */ >+ IC_VEX_W_XD, /* 9324 */ >+ IC_VEX_W_XD, /* 9325 */ >+ IC_VEX_W_XD, /* 9326 */ >+ IC_VEX_W_XD, /* 9327 */ >+ IC_VEX_OPSIZE, /* 9328 */ >+ IC_VEX_OPSIZE, /* 9329 */ >+ IC_VEX_OPSIZE, /* 9330 */ >+ IC_VEX_OPSIZE, /* 9331 */ >+ IC_VEX_OPSIZE, /* 9332 */ >+ IC_VEX_OPSIZE, /* 9333 */ >+ IC_VEX_OPSIZE, /* 9334 */ >+ IC_VEX_OPSIZE, /* 9335 */ >+ IC_VEX_W_OPSIZE, /* 9336 */ >+ IC_VEX_W_OPSIZE, /* 9337 */ >+ IC_VEX_W_OPSIZE, /* 9338 */ >+ IC_VEX_W_OPSIZE, /* 9339 */ >+ IC_VEX_W_OPSIZE, /* 9340 */ >+ IC_VEX_W_OPSIZE, /* 9341 */ >+ IC_VEX_W_OPSIZE, /* 9342 */ >+ IC_VEX_W_OPSIZE, /* 9343 */ >+ IC_VEX_L, /* 9344 */ >+ IC_VEX_L, /* 9345 */ >+ IC_VEX_L_XS, /* 9346 */ >+ IC_VEX_L_XS, /* 9347 */ >+ IC_VEX_L_XD, /* 9348 */ >+ IC_VEX_L_XD, /* 9349 */ >+ IC_VEX_L_XD, /* 9350 */ >+ IC_VEX_L_XD, /* 9351 */ >+ IC_VEX_L_W, /* 9352 */ >+ IC_VEX_L_W, /* 9353 */ >+ IC_VEX_L_W_XS, /* 9354 */ >+ IC_VEX_L_W_XS, /* 9355 */ >+ IC_VEX_L_W_XD, /* 9356 */ >+ IC_VEX_L_W_XD, /* 9357 */ >+ IC_VEX_L_W_XD, /* 9358 */ >+ IC_VEX_L_W_XD, /* 9359 */ >+ IC_VEX_L_OPSIZE, /* 9360 */ >+ IC_VEX_L_OPSIZE, /* 9361 */ >+ IC_VEX_L_OPSIZE, /* 9362 */ >+ IC_VEX_L_OPSIZE, /* 9363 */ >+ IC_VEX_L_OPSIZE, /* 9364 */ >+ IC_VEX_L_OPSIZE, /* 9365 */ >+ IC_VEX_L_OPSIZE, /* 9366 */ >+ IC_VEX_L_OPSIZE, /* 9367 */ >+ IC_VEX_L_W_OPSIZE, /* 9368 */ >+ IC_VEX_L_W_OPSIZE, /* 9369 */ >+ IC_VEX_L_W_OPSIZE, /* 9370 */ >+ IC_VEX_L_W_OPSIZE, /* 9371 */ >+ IC_VEX_L_W_OPSIZE, /* 9372 */ >+ IC_VEX_L_W_OPSIZE, /* 9373 */ >+ IC_VEX_L_W_OPSIZE, /* 9374 */ >+ IC_VEX_L_W_OPSIZE, /* 9375 */ >+ IC_VEX_L, /* 9376 */ >+ IC_VEX_L, /* 9377 */ >+ IC_VEX_L_XS, /* 9378 */ >+ IC_VEX_L_XS, /* 9379 */ >+ IC_VEX_L_XD, /* 9380 */ >+ IC_VEX_L_XD, /* 9381 */ >+ IC_VEX_L_XD, /* 9382 */ >+ IC_VEX_L_XD, /* 9383 */ >+ IC_VEX_L_W, /* 9384 */ >+ IC_VEX_L_W, /* 9385 */ >+ IC_VEX_L_W_XS, /* 9386 */ >+ IC_VEX_L_W_XS, /* 9387 */ >+ IC_VEX_L_W_XD, /* 9388 */ >+ IC_VEX_L_W_XD, /* 9389 */ >+ IC_VEX_L_W_XD, /* 9390 */ >+ IC_VEX_L_W_XD, /* 9391 */ >+ IC_VEX_L_OPSIZE, /* 9392 */ >+ IC_VEX_L_OPSIZE, /* 9393 */ >+ IC_VEX_L_OPSIZE, /* 9394 */ >+ IC_VEX_L_OPSIZE, /* 9395 */ >+ IC_VEX_L_OPSIZE, /* 9396 */ >+ IC_VEX_L_OPSIZE, /* 9397 */ >+ IC_VEX_L_OPSIZE, /* 9398 */ >+ IC_VEX_L_OPSIZE, /* 9399 */ >+ IC_VEX_L_W_OPSIZE, /* 9400 */ >+ IC_VEX_L_W_OPSIZE, /* 9401 */ >+ IC_VEX_L_W_OPSIZE, /* 9402 */ >+ IC_VEX_L_W_OPSIZE, /* 9403 */ >+ IC_VEX_L_W_OPSIZE, /* 9404 */ >+ IC_VEX_L_W_OPSIZE, /* 9405 */ >+ IC_VEX_L_W_OPSIZE, /* 9406 */ >+ IC_VEX_L_W_OPSIZE, /* 9407 */ >+ IC_VEX_L, /* 9408 */ >+ IC_VEX_L, /* 9409 */ >+ IC_VEX_L_XS, /* 9410 */ >+ IC_VEX_L_XS, /* 9411 */ >+ IC_VEX_L_XD, /* 9412 */ >+ IC_VEX_L_XD, /* 9413 */ >+ IC_VEX_L_XD, /* 9414 */ >+ IC_VEX_L_XD, /* 9415 */ >+ IC_VEX_L_W, /* 9416 */ >+ IC_VEX_L_W, /* 9417 */ >+ IC_VEX_L_W_XS, /* 9418 */ >+ IC_VEX_L_W_XS, /* 9419 */ >+ IC_VEX_L_W_XD, /* 9420 */ >+ IC_VEX_L_W_XD, /* 9421 */ >+ IC_VEX_L_W_XD, /* 9422 */ >+ IC_VEX_L_W_XD, /* 9423 */ >+ IC_VEX_L_OPSIZE, /* 9424 */ >+ IC_VEX_L_OPSIZE, /* 9425 */ >+ IC_VEX_L_OPSIZE, /* 9426 */ >+ IC_VEX_L_OPSIZE, /* 9427 */ >+ IC_VEX_L_OPSIZE, /* 9428 */ >+ IC_VEX_L_OPSIZE, /* 9429 */ >+ IC_VEX_L_OPSIZE, /* 9430 */ >+ IC_VEX_L_OPSIZE, /* 9431 */ >+ IC_VEX_L_W_OPSIZE, /* 9432 */ >+ IC_VEX_L_W_OPSIZE, /* 9433 */ >+ IC_VEX_L_W_OPSIZE, /* 9434 */ >+ IC_VEX_L_W_OPSIZE, /* 9435 */ >+ IC_VEX_L_W_OPSIZE, /* 9436 */ >+ IC_VEX_L_W_OPSIZE, /* 9437 */ >+ IC_VEX_L_W_OPSIZE, /* 9438 */ >+ IC_VEX_L_W_OPSIZE, /* 9439 */ >+ IC_VEX_L, /* 9440 */ >+ IC_VEX_L, /* 9441 */ >+ IC_VEX_L_XS, /* 9442 */ >+ IC_VEX_L_XS, /* 9443 */ >+ IC_VEX_L_XD, /* 9444 */ >+ IC_VEX_L_XD, /* 9445 */ >+ IC_VEX_L_XD, /* 9446 */ >+ IC_VEX_L_XD, /* 9447 */ >+ IC_VEX_L_W, /* 9448 */ >+ IC_VEX_L_W, /* 9449 */ >+ IC_VEX_L_W_XS, /* 9450 */ >+ IC_VEX_L_W_XS, /* 9451 */ >+ IC_VEX_L_W_XD, /* 9452 */ >+ IC_VEX_L_W_XD, /* 9453 */ >+ IC_VEX_L_W_XD, /* 9454 */ >+ IC_VEX_L_W_XD, /* 9455 */ >+ IC_VEX_L_OPSIZE, /* 9456 */ >+ IC_VEX_L_OPSIZE, /* 9457 */ >+ IC_VEX_L_OPSIZE, /* 9458 */ >+ IC_VEX_L_OPSIZE, /* 9459 */ >+ IC_VEX_L_OPSIZE, /* 9460 */ >+ IC_VEX_L_OPSIZE, /* 9461 */ >+ IC_VEX_L_OPSIZE, /* 9462 */ >+ IC_VEX_L_OPSIZE, /* 9463 */ >+ IC_VEX_L_W_OPSIZE, /* 9464 */ >+ IC_VEX_L_W_OPSIZE, /* 9465 */ >+ IC_VEX_L_W_OPSIZE, /* 9466 */ >+ IC_VEX_L_W_OPSIZE, /* 9467 */ >+ IC_VEX_L_W_OPSIZE, /* 9468 */ >+ IC_VEX_L_W_OPSIZE, /* 9469 */ >+ IC_VEX_L_W_OPSIZE, /* 9470 */ >+ IC_VEX_L_W_OPSIZE, /* 9471 */ >+ IC_EVEX_L2_B, /* 9472 */ >+ IC_EVEX_L2_B, /* 9473 */ >+ IC_EVEX_L2_XS_B, /* 9474 */ >+ IC_EVEX_L2_XS_B, /* 9475 */ >+ IC_EVEX_L2_XD_B, /* 9476 */ >+ IC_EVEX_L2_XD_B, /* 9477 */ >+ IC_EVEX_L2_XD_B, /* 9478 */ >+ IC_EVEX_L2_XD_B, /* 9479 */ >+ IC_EVEX_L2_W_B, /* 9480 */ >+ IC_EVEX_L2_W_B, /* 9481 */ >+ IC_EVEX_L2_W_XS_B, /* 9482 */ >+ IC_EVEX_L2_W_XS_B, /* 9483 */ >+ IC_EVEX_L2_W_XD_B, /* 9484 */ >+ IC_EVEX_L2_W_XD_B, /* 9485 */ >+ IC_EVEX_L2_W_XD_B, /* 9486 */ >+ IC_EVEX_L2_W_XD_B, /* 9487 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9488 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9489 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9490 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9491 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9492 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9493 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9494 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9495 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9496 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9497 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9498 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9499 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9500 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9501 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9502 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9503 */ >+ IC_EVEX_L2_B, /* 9504 */ >+ IC_EVEX_L2_B, /* 9505 */ >+ IC_EVEX_L2_XS_B, /* 9506 */ >+ IC_EVEX_L2_XS_B, /* 9507 */ >+ IC_EVEX_L2_XD_B, /* 9508 */ >+ IC_EVEX_L2_XD_B, /* 9509 */ >+ IC_EVEX_L2_XD_B, /* 9510 */ >+ IC_EVEX_L2_XD_B, /* 9511 */ >+ IC_EVEX_L2_W_B, /* 9512 */ >+ IC_EVEX_L2_W_B, /* 9513 */ >+ IC_EVEX_L2_W_XS_B, /* 9514 */ >+ IC_EVEX_L2_W_XS_B, /* 9515 */ >+ IC_EVEX_L2_W_XD_B, /* 9516 */ >+ IC_EVEX_L2_W_XD_B, /* 9517 */ >+ IC_EVEX_L2_W_XD_B, /* 9518 */ >+ IC_EVEX_L2_W_XD_B, /* 9519 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9520 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9521 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9522 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9523 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9524 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9525 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9526 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9527 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9528 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9529 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9530 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9531 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9532 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9533 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9534 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9535 */ >+ IC_EVEX_L2_B, /* 9536 */ >+ IC_EVEX_L2_B, /* 9537 */ >+ IC_EVEX_L2_XS_B, /* 9538 */ >+ IC_EVEX_L2_XS_B, /* 9539 */ >+ IC_EVEX_L2_XD_B, /* 9540 */ >+ IC_EVEX_L2_XD_B, /* 9541 */ >+ IC_EVEX_L2_XD_B, /* 9542 */ >+ IC_EVEX_L2_XD_B, /* 9543 */ >+ IC_EVEX_L2_W_B, /* 9544 */ >+ IC_EVEX_L2_W_B, /* 9545 */ >+ IC_EVEX_L2_W_XS_B, /* 9546 */ >+ IC_EVEX_L2_W_XS_B, /* 9547 */ >+ IC_EVEX_L2_W_XD_B, /* 9548 */ >+ IC_EVEX_L2_W_XD_B, /* 9549 */ >+ IC_EVEX_L2_W_XD_B, /* 9550 */ >+ IC_EVEX_L2_W_XD_B, /* 9551 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9552 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9553 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9554 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9555 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9556 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9557 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9558 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9559 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9560 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9561 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9562 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9563 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9564 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9565 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9566 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9567 */ >+ IC_EVEX_L2_B, /* 9568 */ >+ IC_EVEX_L2_B, /* 9569 */ >+ IC_EVEX_L2_XS_B, /* 9570 */ >+ IC_EVEX_L2_XS_B, /* 9571 */ >+ IC_EVEX_L2_XD_B, /* 9572 */ >+ IC_EVEX_L2_XD_B, /* 9573 */ >+ IC_EVEX_L2_XD_B, /* 9574 */ >+ IC_EVEX_L2_XD_B, /* 9575 */ >+ IC_EVEX_L2_W_B, /* 9576 */ >+ IC_EVEX_L2_W_B, /* 9577 */ >+ IC_EVEX_L2_W_XS_B, /* 9578 */ >+ IC_EVEX_L2_W_XS_B, /* 9579 */ >+ IC_EVEX_L2_W_XD_B, /* 9580 */ >+ IC_EVEX_L2_W_XD_B, /* 9581 */ >+ IC_EVEX_L2_W_XD_B, /* 9582 */ >+ IC_EVEX_L2_W_XD_B, /* 9583 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9584 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9585 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9586 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9587 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9588 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9589 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9590 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9591 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9592 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9593 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9594 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9595 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9596 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9597 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9598 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9599 */ >+ IC_EVEX_L2_B, /* 9600 */ >+ IC_EVEX_L2_B, /* 9601 */ >+ IC_EVEX_L2_XS_B, /* 9602 */ >+ IC_EVEX_L2_XS_B, /* 9603 */ >+ IC_EVEX_L2_XD_B, /* 9604 */ >+ IC_EVEX_L2_XD_B, /* 9605 */ >+ IC_EVEX_L2_XD_B, /* 9606 */ >+ IC_EVEX_L2_XD_B, /* 9607 */ >+ IC_EVEX_L2_W_B, /* 9608 */ >+ IC_EVEX_L2_W_B, /* 9609 */ >+ IC_EVEX_L2_W_XS_B, /* 9610 */ >+ IC_EVEX_L2_W_XS_B, /* 9611 */ >+ IC_EVEX_L2_W_XD_B, /* 9612 */ >+ IC_EVEX_L2_W_XD_B, /* 9613 */ >+ IC_EVEX_L2_W_XD_B, /* 9614 */ >+ IC_EVEX_L2_W_XD_B, /* 9615 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9616 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9617 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9618 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9619 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9620 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9621 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9622 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9623 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9624 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9625 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9626 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9627 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9628 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9629 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9630 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9631 */ >+ IC_EVEX_L2_B, /* 9632 */ >+ IC_EVEX_L2_B, /* 9633 */ >+ IC_EVEX_L2_XS_B, /* 9634 */ >+ IC_EVEX_L2_XS_B, /* 9635 */ >+ IC_EVEX_L2_XD_B, /* 9636 */ >+ IC_EVEX_L2_XD_B, /* 9637 */ >+ IC_EVEX_L2_XD_B, /* 9638 */ >+ IC_EVEX_L2_XD_B, /* 9639 */ >+ IC_EVEX_L2_W_B, /* 9640 */ >+ IC_EVEX_L2_W_B, /* 9641 */ >+ IC_EVEX_L2_W_XS_B, /* 9642 */ >+ IC_EVEX_L2_W_XS_B, /* 9643 */ >+ IC_EVEX_L2_W_XD_B, /* 9644 */ >+ IC_EVEX_L2_W_XD_B, /* 9645 */ >+ IC_EVEX_L2_W_XD_B, /* 9646 */ >+ IC_EVEX_L2_W_XD_B, /* 9647 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9648 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9649 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9650 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9651 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9652 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9653 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9654 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9655 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9656 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9657 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9658 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9659 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9660 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9661 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9662 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9663 */ >+ IC_EVEX_L2_B, /* 9664 */ >+ IC_EVEX_L2_B, /* 9665 */ >+ IC_EVEX_L2_XS_B, /* 9666 */ >+ IC_EVEX_L2_XS_B, /* 9667 */ >+ IC_EVEX_L2_XD_B, /* 9668 */ >+ IC_EVEX_L2_XD_B, /* 9669 */ >+ IC_EVEX_L2_XD_B, /* 9670 */ >+ IC_EVEX_L2_XD_B, /* 9671 */ >+ IC_EVEX_L2_W_B, /* 9672 */ >+ IC_EVEX_L2_W_B, /* 9673 */ >+ IC_EVEX_L2_W_XS_B, /* 9674 */ >+ IC_EVEX_L2_W_XS_B, /* 9675 */ >+ IC_EVEX_L2_W_XD_B, /* 9676 */ >+ IC_EVEX_L2_W_XD_B, /* 9677 */ >+ IC_EVEX_L2_W_XD_B, /* 9678 */ >+ IC_EVEX_L2_W_XD_B, /* 9679 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9680 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9681 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9682 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9683 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9684 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9685 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9686 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9687 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9688 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9689 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9690 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9691 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9692 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9693 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9694 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9695 */ >+ IC_EVEX_L2_B, /* 9696 */ >+ IC_EVEX_L2_B, /* 9697 */ >+ IC_EVEX_L2_XS_B, /* 9698 */ >+ IC_EVEX_L2_XS_B, /* 9699 */ >+ IC_EVEX_L2_XD_B, /* 9700 */ >+ IC_EVEX_L2_XD_B, /* 9701 */ >+ IC_EVEX_L2_XD_B, /* 9702 */ >+ IC_EVEX_L2_XD_B, /* 9703 */ >+ IC_EVEX_L2_W_B, /* 9704 */ >+ IC_EVEX_L2_W_B, /* 9705 */ >+ IC_EVEX_L2_W_XS_B, /* 9706 */ >+ IC_EVEX_L2_W_XS_B, /* 9707 */ >+ IC_EVEX_L2_W_XD_B, /* 9708 */ >+ IC_EVEX_L2_W_XD_B, /* 9709 */ >+ IC_EVEX_L2_W_XD_B, /* 9710 */ >+ IC_EVEX_L2_W_XD_B, /* 9711 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9712 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9713 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9714 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9715 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9716 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9717 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9718 */ >+ IC_EVEX_L2_OPSIZE_B, /* 9719 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9720 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9721 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9722 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9723 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9724 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9725 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9726 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 9727 */ >+ IC, /* 9728 */ >+ IC_64BIT, /* 9729 */ >+ IC_XS, /* 9730 */ >+ IC_64BIT_XS, /* 9731 */ >+ IC_XD, /* 9732 */ >+ IC_64BIT_XD, /* 9733 */ >+ IC_XS, /* 9734 */ >+ IC_64BIT_XS, /* 9735 */ >+ IC, /* 9736 */ >+ IC_64BIT_REXW, /* 9737 */ >+ IC_XS, /* 9738 */ >+ IC_64BIT_REXW_XS, /* 9739 */ >+ IC_XD, /* 9740 */ >+ IC_64BIT_REXW_XD, /* 9741 */ >+ IC_XS, /* 9742 */ >+ IC_64BIT_REXW_XS, /* 9743 */ >+ IC_OPSIZE, /* 9744 */ >+ IC_64BIT_OPSIZE, /* 9745 */ >+ IC_XS_OPSIZE, /* 9746 */ >+ IC_64BIT_XS_OPSIZE, /* 9747 */ >+ IC_XD_OPSIZE, /* 9748 */ >+ IC_64BIT_XD_OPSIZE, /* 9749 */ >+ IC_XS_OPSIZE, /* 9750 */ >+ IC_64BIT_XD_OPSIZE, /* 9751 */ >+ IC_OPSIZE, /* 9752 */ >+ IC_64BIT_REXW_OPSIZE, /* 9753 */ >+ IC_XS_OPSIZE, /* 9754 */ >+ IC_64BIT_REXW_XS, /* 9755 */ >+ IC_XD_OPSIZE, /* 9756 */ >+ IC_64BIT_REXW_XD, /* 9757 */ >+ IC_XS_OPSIZE, /* 9758 */ >+ IC_64BIT_REXW_XS, /* 9759 */ >+ IC_ADSIZE, /* 9760 */ >+ IC_64BIT_ADSIZE, /* 9761 */ >+ IC_XS, /* 9762 */ >+ IC_64BIT_XS, /* 9763 */ >+ IC_XD, /* 9764 */ >+ IC_64BIT_XD, /* 9765 */ >+ IC_XS, /* 9766 */ >+ IC_64BIT_XS, /* 9767 */ >+ IC_ADSIZE, /* 9768 */ >+ IC_64BIT_ADSIZE, /* 9769 */ >+ IC_XS, /* 9770 */ >+ IC_64BIT_REXW_XS, /* 9771 */ >+ IC_XD, /* 9772 */ >+ IC_64BIT_REXW_XD, /* 9773 */ >+ IC_XS, /* 9774 */ >+ IC_64BIT_REXW_XS, /* 9775 */ >+ IC_OPSIZE, /* 9776 */ >+ IC_64BIT_OPSIZE, /* 9777 */ >+ IC_XS_OPSIZE, /* 9778 */ >+ IC_64BIT_XS_OPSIZE, /* 9779 */ >+ IC_XD_OPSIZE, /* 9780 */ >+ IC_64BIT_XD_OPSIZE, /* 9781 */ >+ IC_XS_OPSIZE, /* 9782 */ >+ IC_64BIT_XD_OPSIZE, /* 9783 */ >+ IC_OPSIZE, /* 9784 */ >+ IC_64BIT_REXW_OPSIZE, /* 9785 */ >+ IC_XS_OPSIZE, /* 9786 */ >+ IC_64BIT_REXW_XS, /* 9787 */ >+ IC_XD_OPSIZE, /* 9788 */ >+ IC_64BIT_REXW_XD, /* 9789 */ >+ IC_XS_OPSIZE, /* 9790 */ >+ IC_64BIT_REXW_XS, /* 9791 */ >+ IC_VEX, /* 9792 */ >+ IC_VEX, /* 9793 */ >+ IC_VEX_XS, /* 9794 */ >+ IC_VEX_XS, /* 9795 */ >+ IC_VEX_XD, /* 9796 */ >+ IC_VEX_XD, /* 9797 */ >+ IC_VEX_XD, /* 9798 */ >+ IC_VEX_XD, /* 9799 */ >+ IC_VEX_W, /* 9800 */ >+ IC_VEX_W, /* 9801 */ >+ IC_VEX_W_XS, /* 9802 */ >+ IC_VEX_W_XS, /* 9803 */ >+ IC_VEX_W_XD, /* 9804 */ >+ IC_VEX_W_XD, /* 9805 */ >+ IC_VEX_W_XD, /* 9806 */ >+ IC_VEX_W_XD, /* 9807 */ >+ IC_VEX_OPSIZE, /* 9808 */ >+ IC_VEX_OPSIZE, /* 9809 */ >+ IC_VEX_OPSIZE, /* 9810 */ >+ IC_VEX_OPSIZE, /* 9811 */ >+ IC_VEX_OPSIZE, /* 9812 */ >+ IC_VEX_OPSIZE, /* 9813 */ >+ IC_VEX_OPSIZE, /* 9814 */ >+ IC_VEX_OPSIZE, /* 9815 */ >+ IC_VEX_W_OPSIZE, /* 9816 */ >+ IC_VEX_W_OPSIZE, /* 9817 */ >+ IC_VEX_W_OPSIZE, /* 9818 */ >+ IC_VEX_W_OPSIZE, /* 9819 */ >+ IC_VEX_W_OPSIZE, /* 9820 */ >+ IC_VEX_W_OPSIZE, /* 9821 */ >+ IC_VEX_W_OPSIZE, /* 9822 */ >+ IC_VEX_W_OPSIZE, /* 9823 */ >+ IC_VEX, /* 9824 */ >+ IC_VEX, /* 9825 */ >+ IC_VEX_XS, /* 9826 */ >+ IC_VEX_XS, /* 9827 */ >+ IC_VEX_XD, /* 9828 */ >+ IC_VEX_XD, /* 9829 */ >+ IC_VEX_XD, /* 9830 */ >+ IC_VEX_XD, /* 9831 */ >+ IC_VEX_W, /* 9832 */ >+ IC_VEX_W, /* 9833 */ >+ IC_VEX_W_XS, /* 9834 */ >+ IC_VEX_W_XS, /* 9835 */ >+ IC_VEX_W_XD, /* 9836 */ >+ IC_VEX_W_XD, /* 9837 */ >+ IC_VEX_W_XD, /* 9838 */ >+ IC_VEX_W_XD, /* 9839 */ >+ IC_VEX_OPSIZE, /* 9840 */ >+ IC_VEX_OPSIZE, /* 9841 */ >+ IC_VEX_OPSIZE, /* 9842 */ >+ IC_VEX_OPSIZE, /* 9843 */ >+ IC_VEX_OPSIZE, /* 9844 */ >+ IC_VEX_OPSIZE, /* 9845 */ >+ IC_VEX_OPSIZE, /* 9846 */ >+ IC_VEX_OPSIZE, /* 9847 */ >+ IC_VEX_W_OPSIZE, /* 9848 */ >+ IC_VEX_W_OPSIZE, /* 9849 */ >+ IC_VEX_W_OPSIZE, /* 9850 */ >+ IC_VEX_W_OPSIZE, /* 9851 */ >+ IC_VEX_W_OPSIZE, /* 9852 */ >+ IC_VEX_W_OPSIZE, /* 9853 */ >+ IC_VEX_W_OPSIZE, /* 9854 */ >+ IC_VEX_W_OPSIZE, /* 9855 */ >+ IC_VEX_L, /* 9856 */ >+ IC_VEX_L, /* 9857 */ >+ IC_VEX_L_XS, /* 9858 */ >+ IC_VEX_L_XS, /* 9859 */ >+ IC_VEX_L_XD, /* 9860 */ >+ IC_VEX_L_XD, /* 9861 */ >+ IC_VEX_L_XD, /* 9862 */ >+ IC_VEX_L_XD, /* 9863 */ >+ IC_VEX_L_W, /* 9864 */ >+ IC_VEX_L_W, /* 9865 */ >+ IC_VEX_L_W_XS, /* 9866 */ >+ IC_VEX_L_W_XS, /* 9867 */ >+ IC_VEX_L_W_XD, /* 9868 */ >+ IC_VEX_L_W_XD, /* 9869 */ >+ IC_VEX_L_W_XD, /* 9870 */ >+ IC_VEX_L_W_XD, /* 9871 */ >+ IC_VEX_L_OPSIZE, /* 9872 */ >+ IC_VEX_L_OPSIZE, /* 9873 */ >+ IC_VEX_L_OPSIZE, /* 9874 */ >+ IC_VEX_L_OPSIZE, /* 9875 */ >+ IC_VEX_L_OPSIZE, /* 9876 */ >+ IC_VEX_L_OPSIZE, /* 9877 */ >+ IC_VEX_L_OPSIZE, /* 9878 */ >+ IC_VEX_L_OPSIZE, /* 9879 */ >+ IC_VEX_L_W_OPSIZE, /* 9880 */ >+ IC_VEX_L_W_OPSIZE, /* 9881 */ >+ IC_VEX_L_W_OPSIZE, /* 9882 */ >+ IC_VEX_L_W_OPSIZE, /* 9883 */ >+ IC_VEX_L_W_OPSIZE, /* 9884 */ >+ IC_VEX_L_W_OPSIZE, /* 9885 */ >+ IC_VEX_L_W_OPSIZE, /* 9886 */ >+ IC_VEX_L_W_OPSIZE, /* 9887 */ >+ IC_VEX_L, /* 9888 */ >+ IC_VEX_L, /* 9889 */ >+ IC_VEX_L_XS, /* 9890 */ >+ IC_VEX_L_XS, /* 9891 */ >+ IC_VEX_L_XD, /* 9892 */ >+ IC_VEX_L_XD, /* 9893 */ >+ IC_VEX_L_XD, /* 9894 */ >+ IC_VEX_L_XD, /* 9895 */ >+ IC_VEX_L_W, /* 9896 */ >+ IC_VEX_L_W, /* 9897 */ >+ IC_VEX_L_W_XS, /* 9898 */ >+ IC_VEX_L_W_XS, /* 9899 */ >+ IC_VEX_L_W_XD, /* 9900 */ >+ IC_VEX_L_W_XD, /* 9901 */ >+ IC_VEX_L_W_XD, /* 9902 */ >+ IC_VEX_L_W_XD, /* 9903 */ >+ IC_VEX_L_OPSIZE, /* 9904 */ >+ IC_VEX_L_OPSIZE, /* 9905 */ >+ IC_VEX_L_OPSIZE, /* 9906 */ >+ IC_VEX_L_OPSIZE, /* 9907 */ >+ IC_VEX_L_OPSIZE, /* 9908 */ >+ IC_VEX_L_OPSIZE, /* 9909 */ >+ IC_VEX_L_OPSIZE, /* 9910 */ >+ IC_VEX_L_OPSIZE, /* 9911 */ >+ IC_VEX_L_W_OPSIZE, /* 9912 */ >+ IC_VEX_L_W_OPSIZE, /* 9913 */ >+ IC_VEX_L_W_OPSIZE, /* 9914 */ >+ IC_VEX_L_W_OPSIZE, /* 9915 */ >+ IC_VEX_L_W_OPSIZE, /* 9916 */ >+ IC_VEX_L_W_OPSIZE, /* 9917 */ >+ IC_VEX_L_W_OPSIZE, /* 9918 */ >+ IC_VEX_L_W_OPSIZE, /* 9919 */ >+ IC_VEX_L, /* 9920 */ >+ IC_VEX_L, /* 9921 */ >+ IC_VEX_L_XS, /* 9922 */ >+ IC_VEX_L_XS, /* 9923 */ >+ IC_VEX_L_XD, /* 9924 */ >+ IC_VEX_L_XD, /* 9925 */ >+ IC_VEX_L_XD, /* 9926 */ >+ IC_VEX_L_XD, /* 9927 */ >+ IC_VEX_L_W, /* 9928 */ >+ IC_VEX_L_W, /* 9929 */ >+ IC_VEX_L_W_XS, /* 9930 */ >+ IC_VEX_L_W_XS, /* 9931 */ >+ IC_VEX_L_W_XD, /* 9932 */ >+ IC_VEX_L_W_XD, /* 9933 */ >+ IC_VEX_L_W_XD, /* 9934 */ >+ IC_VEX_L_W_XD, /* 9935 */ >+ IC_VEX_L_OPSIZE, /* 9936 */ >+ IC_VEX_L_OPSIZE, /* 9937 */ >+ IC_VEX_L_OPSIZE, /* 9938 */ >+ IC_VEX_L_OPSIZE, /* 9939 */ >+ IC_VEX_L_OPSIZE, /* 9940 */ >+ IC_VEX_L_OPSIZE, /* 9941 */ >+ IC_VEX_L_OPSIZE, /* 9942 */ >+ IC_VEX_L_OPSIZE, /* 9943 */ >+ IC_VEX_L_W_OPSIZE, /* 9944 */ >+ IC_VEX_L_W_OPSIZE, /* 9945 */ >+ IC_VEX_L_W_OPSIZE, /* 9946 */ >+ IC_VEX_L_W_OPSIZE, /* 9947 */ >+ IC_VEX_L_W_OPSIZE, /* 9948 */ >+ IC_VEX_L_W_OPSIZE, /* 9949 */ >+ IC_VEX_L_W_OPSIZE, /* 9950 */ >+ IC_VEX_L_W_OPSIZE, /* 9951 */ >+ IC_VEX_L, /* 9952 */ >+ IC_VEX_L, /* 9953 */ >+ IC_VEX_L_XS, /* 9954 */ >+ IC_VEX_L_XS, /* 9955 */ >+ IC_VEX_L_XD, /* 9956 */ >+ IC_VEX_L_XD, /* 9957 */ >+ IC_VEX_L_XD, /* 9958 */ >+ IC_VEX_L_XD, /* 9959 */ >+ IC_VEX_L_W, /* 9960 */ >+ IC_VEX_L_W, /* 9961 */ >+ IC_VEX_L_W_XS, /* 9962 */ >+ IC_VEX_L_W_XS, /* 9963 */ >+ IC_VEX_L_W_XD, /* 9964 */ >+ IC_VEX_L_W_XD, /* 9965 */ >+ IC_VEX_L_W_XD, /* 9966 */ >+ IC_VEX_L_W_XD, /* 9967 */ >+ IC_VEX_L_OPSIZE, /* 9968 */ >+ IC_VEX_L_OPSIZE, /* 9969 */ >+ IC_VEX_L_OPSIZE, /* 9970 */ >+ IC_VEX_L_OPSIZE, /* 9971 */ >+ IC_VEX_L_OPSIZE, /* 9972 */ >+ IC_VEX_L_OPSIZE, /* 9973 */ >+ IC_VEX_L_OPSIZE, /* 9974 */ >+ IC_VEX_L_OPSIZE, /* 9975 */ >+ IC_VEX_L_W_OPSIZE, /* 9976 */ >+ IC_VEX_L_W_OPSIZE, /* 9977 */ >+ IC_VEX_L_W_OPSIZE, /* 9978 */ >+ IC_VEX_L_W_OPSIZE, /* 9979 */ >+ IC_VEX_L_W_OPSIZE, /* 9980 */ >+ IC_VEX_L_W_OPSIZE, /* 9981 */ >+ IC_VEX_L_W_OPSIZE, /* 9982 */ >+ IC_VEX_L_W_OPSIZE, /* 9983 */ >+ IC_EVEX_L2_B, /* 9984 */ >+ IC_EVEX_L2_B, /* 9985 */ >+ IC_EVEX_L2_XS_B, /* 9986 */ >+ IC_EVEX_L2_XS_B, /* 9987 */ >+ IC_EVEX_L2_XD_B, /* 9988 */ >+ IC_EVEX_L2_XD_B, /* 9989 */ >+ IC_EVEX_L2_XD_B, /* 9990 */ >+ IC_EVEX_L2_XD_B, /* 9991 */ >+ IC_EVEX_L2_W_B, /* 9992 */ >+ IC_EVEX_L2_W_B, /* 9993 */ >+ IC_EVEX_L2_W_XS_B, /* 9994 */ >+ IC_EVEX_L2_W_XS_B, /* 9995 */ >+ IC_EVEX_L2_W_XD_B, /* 9996 */ >+ IC_EVEX_L2_W_XD_B, /* 9997 */ >+ IC_EVEX_L2_W_XD_B, /* 9998 */ >+ IC_EVEX_L2_W_XD_B, /* 9999 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10000 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10001 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10002 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10003 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10004 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10005 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10006 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10007 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10008 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10009 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10010 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10011 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10012 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10013 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10014 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10015 */ >+ IC_EVEX_L2_B, /* 10016 */ >+ IC_EVEX_L2_B, /* 10017 */ >+ IC_EVEX_L2_XS_B, /* 10018 */ >+ IC_EVEX_L2_XS_B, /* 10019 */ >+ IC_EVEX_L2_XD_B, /* 10020 */ >+ IC_EVEX_L2_XD_B, /* 10021 */ >+ IC_EVEX_L2_XD_B, /* 10022 */ >+ IC_EVEX_L2_XD_B, /* 10023 */ >+ IC_EVEX_L2_W_B, /* 10024 */ >+ IC_EVEX_L2_W_B, /* 10025 */ >+ IC_EVEX_L2_W_XS_B, /* 10026 */ >+ IC_EVEX_L2_W_XS_B, /* 10027 */ >+ IC_EVEX_L2_W_XD_B, /* 10028 */ >+ IC_EVEX_L2_W_XD_B, /* 10029 */ >+ IC_EVEX_L2_W_XD_B, /* 10030 */ >+ IC_EVEX_L2_W_XD_B, /* 10031 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10032 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10033 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10034 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10035 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10036 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10037 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10038 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10039 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10040 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10041 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10042 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10043 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10044 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10045 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10046 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10047 */ >+ IC_EVEX_L2_B, /* 10048 */ >+ IC_EVEX_L2_B, /* 10049 */ >+ IC_EVEX_L2_XS_B, /* 10050 */ >+ IC_EVEX_L2_XS_B, /* 10051 */ >+ IC_EVEX_L2_XD_B, /* 10052 */ >+ IC_EVEX_L2_XD_B, /* 10053 */ >+ IC_EVEX_L2_XD_B, /* 10054 */ >+ IC_EVEX_L2_XD_B, /* 10055 */ >+ IC_EVEX_L2_W_B, /* 10056 */ >+ IC_EVEX_L2_W_B, /* 10057 */ >+ IC_EVEX_L2_W_XS_B, /* 10058 */ >+ IC_EVEX_L2_W_XS_B, /* 10059 */ >+ IC_EVEX_L2_W_XD_B, /* 10060 */ >+ IC_EVEX_L2_W_XD_B, /* 10061 */ >+ IC_EVEX_L2_W_XD_B, /* 10062 */ >+ IC_EVEX_L2_W_XD_B, /* 10063 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10064 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10065 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10066 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10067 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10068 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10069 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10070 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10071 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10072 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10073 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10074 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10075 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10076 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10077 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10078 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10079 */ >+ IC_EVEX_L2_B, /* 10080 */ >+ IC_EVEX_L2_B, /* 10081 */ >+ IC_EVEX_L2_XS_B, /* 10082 */ >+ IC_EVEX_L2_XS_B, /* 10083 */ >+ IC_EVEX_L2_XD_B, /* 10084 */ >+ IC_EVEX_L2_XD_B, /* 10085 */ >+ IC_EVEX_L2_XD_B, /* 10086 */ >+ IC_EVEX_L2_XD_B, /* 10087 */ >+ IC_EVEX_L2_W_B, /* 10088 */ >+ IC_EVEX_L2_W_B, /* 10089 */ >+ IC_EVEX_L2_W_XS_B, /* 10090 */ >+ IC_EVEX_L2_W_XS_B, /* 10091 */ >+ IC_EVEX_L2_W_XD_B, /* 10092 */ >+ IC_EVEX_L2_W_XD_B, /* 10093 */ >+ IC_EVEX_L2_W_XD_B, /* 10094 */ >+ IC_EVEX_L2_W_XD_B, /* 10095 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10096 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10097 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10098 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10099 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10100 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10101 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10102 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10103 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10104 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10105 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10106 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10107 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10108 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10109 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10110 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10111 */ >+ IC_EVEX_L2_B, /* 10112 */ >+ IC_EVEX_L2_B, /* 10113 */ >+ IC_EVEX_L2_XS_B, /* 10114 */ >+ IC_EVEX_L2_XS_B, /* 10115 */ >+ IC_EVEX_L2_XD_B, /* 10116 */ >+ IC_EVEX_L2_XD_B, /* 10117 */ >+ IC_EVEX_L2_XD_B, /* 10118 */ >+ IC_EVEX_L2_XD_B, /* 10119 */ >+ IC_EVEX_L2_W_B, /* 10120 */ >+ IC_EVEX_L2_W_B, /* 10121 */ >+ IC_EVEX_L2_W_XS_B, /* 10122 */ >+ IC_EVEX_L2_W_XS_B, /* 10123 */ >+ IC_EVEX_L2_W_XD_B, /* 10124 */ >+ IC_EVEX_L2_W_XD_B, /* 10125 */ >+ IC_EVEX_L2_W_XD_B, /* 10126 */ >+ IC_EVEX_L2_W_XD_B, /* 10127 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10128 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10129 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10130 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10131 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10132 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10133 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10134 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10135 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10136 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10137 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10138 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10139 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10140 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10141 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10142 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10143 */ >+ IC_EVEX_L2_B, /* 10144 */ >+ IC_EVEX_L2_B, /* 10145 */ >+ IC_EVEX_L2_XS_B, /* 10146 */ >+ IC_EVEX_L2_XS_B, /* 10147 */ >+ IC_EVEX_L2_XD_B, /* 10148 */ >+ IC_EVEX_L2_XD_B, /* 10149 */ >+ IC_EVEX_L2_XD_B, /* 10150 */ >+ IC_EVEX_L2_XD_B, /* 10151 */ >+ IC_EVEX_L2_W_B, /* 10152 */ >+ IC_EVEX_L2_W_B, /* 10153 */ >+ IC_EVEX_L2_W_XS_B, /* 10154 */ >+ IC_EVEX_L2_W_XS_B, /* 10155 */ >+ IC_EVEX_L2_W_XD_B, /* 10156 */ >+ IC_EVEX_L2_W_XD_B, /* 10157 */ >+ IC_EVEX_L2_W_XD_B, /* 10158 */ >+ IC_EVEX_L2_W_XD_B, /* 10159 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10160 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10161 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10162 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10163 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10164 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10165 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10166 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10167 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10168 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10169 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10170 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10171 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10172 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10173 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10174 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10175 */ >+ IC_EVEX_L2_B, /* 10176 */ >+ IC_EVEX_L2_B, /* 10177 */ >+ IC_EVEX_L2_XS_B, /* 10178 */ >+ IC_EVEX_L2_XS_B, /* 10179 */ >+ IC_EVEX_L2_XD_B, /* 10180 */ >+ IC_EVEX_L2_XD_B, /* 10181 */ >+ IC_EVEX_L2_XD_B, /* 10182 */ >+ IC_EVEX_L2_XD_B, /* 10183 */ >+ IC_EVEX_L2_W_B, /* 10184 */ >+ IC_EVEX_L2_W_B, /* 10185 */ >+ IC_EVEX_L2_W_XS_B, /* 10186 */ >+ IC_EVEX_L2_W_XS_B, /* 10187 */ >+ IC_EVEX_L2_W_XD_B, /* 10188 */ >+ IC_EVEX_L2_W_XD_B, /* 10189 */ >+ IC_EVEX_L2_W_XD_B, /* 10190 */ >+ IC_EVEX_L2_W_XD_B, /* 10191 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10192 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10193 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10194 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10195 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10196 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10197 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10198 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10199 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10200 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10201 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10202 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10203 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10204 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10205 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10206 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10207 */ >+ IC_EVEX_L2_B, /* 10208 */ >+ IC_EVEX_L2_B, /* 10209 */ >+ IC_EVEX_L2_XS_B, /* 10210 */ >+ IC_EVEX_L2_XS_B, /* 10211 */ >+ IC_EVEX_L2_XD_B, /* 10212 */ >+ IC_EVEX_L2_XD_B, /* 10213 */ >+ IC_EVEX_L2_XD_B, /* 10214 */ >+ IC_EVEX_L2_XD_B, /* 10215 */ >+ IC_EVEX_L2_W_B, /* 10216 */ >+ IC_EVEX_L2_W_B, /* 10217 */ >+ IC_EVEX_L2_W_XS_B, /* 10218 */ >+ IC_EVEX_L2_W_XS_B, /* 10219 */ >+ IC_EVEX_L2_W_XD_B, /* 10220 */ >+ IC_EVEX_L2_W_XD_B, /* 10221 */ >+ IC_EVEX_L2_W_XD_B, /* 10222 */ >+ IC_EVEX_L2_W_XD_B, /* 10223 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10224 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10225 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10226 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10227 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10228 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10229 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10230 */ >+ IC_EVEX_L2_OPSIZE_B, /* 10231 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10232 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10233 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10234 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10235 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10236 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10237 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10238 */ >+ IC_EVEX_L2_W_OPSIZE_B, /* 10239 */ >+ IC, /* 10240 */ >+ IC_64BIT, /* 10241 */ >+ IC_XS, /* 10242 */ >+ IC_64BIT_XS, /* 10243 */ >+ IC_XD, /* 10244 */ >+ IC_64BIT_XD, /* 10245 */ >+ IC_XS, /* 10246 */ >+ IC_64BIT_XS, /* 10247 */ >+ IC, /* 10248 */ >+ IC_64BIT_REXW, /* 10249 */ >+ IC_XS, /* 10250 */ >+ IC_64BIT_REXW_XS, /* 10251 */ >+ IC_XD, /* 10252 */ >+ IC_64BIT_REXW_XD, /* 10253 */ >+ IC_XS, /* 10254 */ >+ IC_64BIT_REXW_XS, /* 10255 */ >+ IC_OPSIZE, /* 10256 */ >+ IC_64BIT_OPSIZE, /* 10257 */ >+ IC_XS_OPSIZE, /* 10258 */ >+ IC_64BIT_XS_OPSIZE, /* 10259 */ >+ IC_XD_OPSIZE, /* 10260 */ >+ IC_64BIT_XD_OPSIZE, /* 10261 */ >+ IC_XS_OPSIZE, /* 10262 */ >+ IC_64BIT_XD_OPSIZE, /* 10263 */ >+ IC_OPSIZE, /* 10264 */ >+ IC_64BIT_REXW_OPSIZE, /* 10265 */ >+ IC_XS_OPSIZE, /* 10266 */ >+ IC_64BIT_REXW_XS, /* 10267 */ >+ IC_XD_OPSIZE, /* 10268 */ >+ IC_64BIT_REXW_XD, /* 10269 */ >+ IC_XS_OPSIZE, /* 10270 */ >+ IC_64BIT_REXW_XS, /* 10271 */ >+ IC_ADSIZE, /* 10272 */ >+ IC_64BIT_ADSIZE, /* 10273 */ >+ IC_XS, /* 10274 */ >+ IC_64BIT_XS, /* 10275 */ >+ IC_XD, /* 10276 */ >+ IC_64BIT_XD, /* 10277 */ >+ IC_XS, /* 10278 */ >+ IC_64BIT_XS, /* 10279 */ >+ IC_ADSIZE, /* 10280 */ >+ IC_64BIT_ADSIZE, /* 10281 */ >+ IC_XS, /* 10282 */ >+ IC_64BIT_REXW_XS, /* 10283 */ >+ IC_XD, /* 10284 */ >+ IC_64BIT_REXW_XD, /* 10285 */ >+ IC_XS, /* 10286 */ >+ IC_64BIT_REXW_XS, /* 10287 */ >+ IC_OPSIZE, /* 10288 */ >+ IC_64BIT_OPSIZE, /* 10289 */ >+ IC_XS_OPSIZE, /* 10290 */ >+ IC_64BIT_XS_OPSIZE, /* 10291 */ >+ IC_XD_OPSIZE, /* 10292 */ >+ IC_64BIT_XD_OPSIZE, /* 10293 */ >+ IC_XS_OPSIZE, /* 10294 */ >+ IC_64BIT_XD_OPSIZE, /* 10295 */ >+ IC_OPSIZE, /* 10296 */ >+ IC_64BIT_REXW_OPSIZE, /* 10297 */ >+ IC_XS_OPSIZE, /* 10298 */ >+ IC_64BIT_REXW_XS, /* 10299 */ >+ IC_XD_OPSIZE, /* 10300 */ >+ IC_64BIT_REXW_XD, /* 10301 */ >+ IC_XS_OPSIZE, /* 10302 */ >+ IC_64BIT_REXW_XS, /* 10303 */ >+ IC_VEX, /* 10304 */ >+ IC_VEX, /* 10305 */ >+ IC_VEX_XS, /* 10306 */ >+ IC_VEX_XS, /* 10307 */ >+ IC_VEX_XD, /* 10308 */ >+ IC_VEX_XD, /* 10309 */ >+ IC_VEX_XD, /* 10310 */ >+ IC_VEX_XD, /* 10311 */ >+ IC_VEX_W, /* 10312 */ >+ IC_VEX_W, /* 10313 */ >+ IC_VEX_W_XS, /* 10314 */ >+ IC_VEX_W_XS, /* 10315 */ >+ IC_VEX_W_XD, /* 10316 */ >+ IC_VEX_W_XD, /* 10317 */ >+ IC_VEX_W_XD, /* 10318 */ >+ IC_VEX_W_XD, /* 10319 */ >+ IC_VEX_OPSIZE, /* 10320 */ >+ IC_VEX_OPSIZE, /* 10321 */ >+ IC_VEX_OPSIZE, /* 10322 */ >+ IC_VEX_OPSIZE, /* 10323 */ >+ IC_VEX_OPSIZE, /* 10324 */ >+ IC_VEX_OPSIZE, /* 10325 */ >+ IC_VEX_OPSIZE, /* 10326 */ >+ IC_VEX_OPSIZE, /* 10327 */ >+ IC_VEX_W_OPSIZE, /* 10328 */ >+ IC_VEX_W_OPSIZE, /* 10329 */ >+ IC_VEX_W_OPSIZE, /* 10330 */ >+ IC_VEX_W_OPSIZE, /* 10331 */ >+ IC_VEX_W_OPSIZE, /* 10332 */ >+ IC_VEX_W_OPSIZE, /* 10333 */ >+ IC_VEX_W_OPSIZE, /* 10334 */ >+ IC_VEX_W_OPSIZE, /* 10335 */ >+ IC_VEX, /* 10336 */ >+ IC_VEX, /* 10337 */ >+ IC_VEX_XS, /* 10338 */ >+ IC_VEX_XS, /* 10339 */ >+ IC_VEX_XD, /* 10340 */ >+ IC_VEX_XD, /* 10341 */ >+ IC_VEX_XD, /* 10342 */ >+ IC_VEX_XD, /* 10343 */ >+ IC_VEX_W, /* 10344 */ >+ IC_VEX_W, /* 10345 */ >+ IC_VEX_W_XS, /* 10346 */ >+ IC_VEX_W_XS, /* 10347 */ >+ IC_VEX_W_XD, /* 10348 */ >+ IC_VEX_W_XD, /* 10349 */ >+ IC_VEX_W_XD, /* 10350 */ >+ IC_VEX_W_XD, /* 10351 */ >+ IC_VEX_OPSIZE, /* 10352 */ >+ IC_VEX_OPSIZE, /* 10353 */ >+ IC_VEX_OPSIZE, /* 10354 */ >+ IC_VEX_OPSIZE, /* 10355 */ >+ IC_VEX_OPSIZE, /* 10356 */ >+ IC_VEX_OPSIZE, /* 10357 */ >+ IC_VEX_OPSIZE, /* 10358 */ >+ IC_VEX_OPSIZE, /* 10359 */ >+ IC_VEX_W_OPSIZE, /* 10360 */ >+ IC_VEX_W_OPSIZE, /* 10361 */ >+ IC_VEX_W_OPSIZE, /* 10362 */ >+ IC_VEX_W_OPSIZE, /* 10363 */ >+ IC_VEX_W_OPSIZE, /* 10364 */ >+ IC_VEX_W_OPSIZE, /* 10365 */ >+ IC_VEX_W_OPSIZE, /* 10366 */ >+ IC_VEX_W_OPSIZE, /* 10367 */ >+ IC_VEX_L, /* 10368 */ >+ IC_VEX_L, /* 10369 */ >+ IC_VEX_L_XS, /* 10370 */ >+ IC_VEX_L_XS, /* 10371 */ >+ IC_VEX_L_XD, /* 10372 */ >+ IC_VEX_L_XD, /* 10373 */ >+ IC_VEX_L_XD, /* 10374 */ >+ IC_VEX_L_XD, /* 10375 */ >+ IC_VEX_L_W, /* 10376 */ >+ IC_VEX_L_W, /* 10377 */ >+ IC_VEX_L_W_XS, /* 10378 */ >+ IC_VEX_L_W_XS, /* 10379 */ >+ IC_VEX_L_W_XD, /* 10380 */ >+ IC_VEX_L_W_XD, /* 10381 */ >+ IC_VEX_L_W_XD, /* 10382 */ >+ IC_VEX_L_W_XD, /* 10383 */ >+ IC_VEX_L_OPSIZE, /* 10384 */ >+ IC_VEX_L_OPSIZE, /* 10385 */ >+ IC_VEX_L_OPSIZE, /* 10386 */ >+ IC_VEX_L_OPSIZE, /* 10387 */ >+ IC_VEX_L_OPSIZE, /* 10388 */ >+ IC_VEX_L_OPSIZE, /* 10389 */ >+ IC_VEX_L_OPSIZE, /* 10390 */ >+ IC_VEX_L_OPSIZE, /* 10391 */ >+ IC_VEX_L_W_OPSIZE, /* 10392 */ >+ IC_VEX_L_W_OPSIZE, /* 10393 */ >+ IC_VEX_L_W_OPSIZE, /* 10394 */ >+ IC_VEX_L_W_OPSIZE, /* 10395 */ >+ IC_VEX_L_W_OPSIZE, /* 10396 */ >+ IC_VEX_L_W_OPSIZE, /* 10397 */ >+ IC_VEX_L_W_OPSIZE, /* 10398 */ >+ IC_VEX_L_W_OPSIZE, /* 10399 */ >+ IC_VEX_L, /* 10400 */ >+ IC_VEX_L, /* 10401 */ >+ IC_VEX_L_XS, /* 10402 */ >+ IC_VEX_L_XS, /* 10403 */ >+ IC_VEX_L_XD, /* 10404 */ >+ IC_VEX_L_XD, /* 10405 */ >+ IC_VEX_L_XD, /* 10406 */ >+ IC_VEX_L_XD, /* 10407 */ >+ IC_VEX_L_W, /* 10408 */ >+ IC_VEX_L_W, /* 10409 */ >+ IC_VEX_L_W_XS, /* 10410 */ >+ IC_VEX_L_W_XS, /* 10411 */ >+ IC_VEX_L_W_XD, /* 10412 */ >+ IC_VEX_L_W_XD, /* 10413 */ >+ IC_VEX_L_W_XD, /* 10414 */ >+ IC_VEX_L_W_XD, /* 10415 */ >+ IC_VEX_L_OPSIZE, /* 10416 */ >+ IC_VEX_L_OPSIZE, /* 10417 */ >+ IC_VEX_L_OPSIZE, /* 10418 */ >+ IC_VEX_L_OPSIZE, /* 10419 */ >+ IC_VEX_L_OPSIZE, /* 10420 */ >+ IC_VEX_L_OPSIZE, /* 10421 */ >+ IC_VEX_L_OPSIZE, /* 10422 */ >+ IC_VEX_L_OPSIZE, /* 10423 */ >+ IC_VEX_L_W_OPSIZE, /* 10424 */ >+ IC_VEX_L_W_OPSIZE, /* 10425 */ >+ IC_VEX_L_W_OPSIZE, /* 10426 */ >+ IC_VEX_L_W_OPSIZE, /* 10427 */ >+ IC_VEX_L_W_OPSIZE, /* 10428 */ >+ IC_VEX_L_W_OPSIZE, /* 10429 */ >+ IC_VEX_L_W_OPSIZE, /* 10430 */ >+ IC_VEX_L_W_OPSIZE, /* 10431 */ >+ IC_VEX_L, /* 10432 */ >+ IC_VEX_L, /* 10433 */ >+ IC_VEX_L_XS, /* 10434 */ >+ IC_VEX_L_XS, /* 10435 */ >+ IC_VEX_L_XD, /* 10436 */ >+ IC_VEX_L_XD, /* 10437 */ >+ IC_VEX_L_XD, /* 10438 */ >+ IC_VEX_L_XD, /* 10439 */ >+ IC_VEX_L_W, /* 10440 */ >+ IC_VEX_L_W, /* 10441 */ >+ IC_VEX_L_W_XS, /* 10442 */ >+ IC_VEX_L_W_XS, /* 10443 */ >+ IC_VEX_L_W_XD, /* 10444 */ >+ IC_VEX_L_W_XD, /* 10445 */ >+ IC_VEX_L_W_XD, /* 10446 */ >+ IC_VEX_L_W_XD, /* 10447 */ >+ IC_VEX_L_OPSIZE, /* 10448 */ >+ IC_VEX_L_OPSIZE, /* 10449 */ >+ IC_VEX_L_OPSIZE, /* 10450 */ >+ IC_VEX_L_OPSIZE, /* 10451 */ >+ IC_VEX_L_OPSIZE, /* 10452 */ >+ IC_VEX_L_OPSIZE, /* 10453 */ >+ IC_VEX_L_OPSIZE, /* 10454 */ >+ IC_VEX_L_OPSIZE, /* 10455 */ >+ IC_VEX_L_W_OPSIZE, /* 10456 */ >+ IC_VEX_L_W_OPSIZE, /* 10457 */ >+ IC_VEX_L_W_OPSIZE, /* 10458 */ >+ IC_VEX_L_W_OPSIZE, /* 10459 */ >+ IC_VEX_L_W_OPSIZE, /* 10460 */ >+ IC_VEX_L_W_OPSIZE, /* 10461 */ >+ IC_VEX_L_W_OPSIZE, /* 10462 */ >+ IC_VEX_L_W_OPSIZE, /* 10463 */ >+ IC_VEX_L, /* 10464 */ >+ IC_VEX_L, /* 10465 */ >+ IC_VEX_L_XS, /* 10466 */ >+ IC_VEX_L_XS, /* 10467 */ >+ IC_VEX_L_XD, /* 10468 */ >+ IC_VEX_L_XD, /* 10469 */ >+ IC_VEX_L_XD, /* 10470 */ >+ IC_VEX_L_XD, /* 10471 */ >+ IC_VEX_L_W, /* 10472 */ >+ IC_VEX_L_W, /* 10473 */ >+ IC_VEX_L_W_XS, /* 10474 */ >+ IC_VEX_L_W_XS, /* 10475 */ >+ IC_VEX_L_W_XD, /* 10476 */ >+ IC_VEX_L_W_XD, /* 10477 */ >+ IC_VEX_L_W_XD, /* 10478 */ >+ IC_VEX_L_W_XD, /* 10479 */ >+ IC_VEX_L_OPSIZE, /* 10480 */ >+ IC_VEX_L_OPSIZE, /* 10481 */ >+ IC_VEX_L_OPSIZE, /* 10482 */ >+ IC_VEX_L_OPSIZE, /* 10483 */ >+ IC_VEX_L_OPSIZE, /* 10484 */ >+ IC_VEX_L_OPSIZE, /* 10485 */ >+ IC_VEX_L_OPSIZE, /* 10486 */ >+ IC_VEX_L_OPSIZE, /* 10487 */ >+ IC_VEX_L_W_OPSIZE, /* 10488 */ >+ IC_VEX_L_W_OPSIZE, /* 10489 */ >+ IC_VEX_L_W_OPSIZE, /* 10490 */ >+ IC_VEX_L_W_OPSIZE, /* 10491 */ >+ IC_VEX_L_W_OPSIZE, /* 10492 */ >+ IC_VEX_L_W_OPSIZE, /* 10493 */ >+ IC_VEX_L_W_OPSIZE, /* 10494 */ >+ IC_VEX_L_W_OPSIZE, /* 10495 */ >+ IC_EVEX_K_B, /* 10496 */ >+ IC_EVEX_K_B, /* 10497 */ >+ IC_EVEX_XS_K_B, /* 10498 */ >+ IC_EVEX_XS_K_B, /* 10499 */ >+ IC_EVEX_XD_K_B, /* 10500 */ >+ IC_EVEX_XD_K_B, /* 10501 */ >+ IC_EVEX_XD_K_B, /* 10502 */ >+ IC_EVEX_XD_K_B, /* 10503 */ >+ IC_EVEX_W_K_B, /* 10504 */ >+ IC_EVEX_W_K_B, /* 10505 */ >+ IC_EVEX_W_XS_K_B, /* 10506 */ >+ IC_EVEX_W_XS_K_B, /* 10507 */ >+ IC_EVEX_W_XD_K_B, /* 10508 */ >+ IC_EVEX_W_XD_K_B, /* 10509 */ >+ IC_EVEX_W_XD_K_B, /* 10510 */ >+ IC_EVEX_W_XD_K_B, /* 10511 */ >+ IC_EVEX_OPSIZE_K_B, /* 10512 */ >+ IC_EVEX_OPSIZE_K_B, /* 10513 */ >+ IC_EVEX_OPSIZE_K_B, /* 10514 */ >+ IC_EVEX_OPSIZE_K_B, /* 10515 */ >+ IC_EVEX_OPSIZE_K_B, /* 10516 */ >+ IC_EVEX_OPSIZE_K_B, /* 10517 */ >+ IC_EVEX_OPSIZE_K_B, /* 10518 */ >+ IC_EVEX_OPSIZE_K_B, /* 10519 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10520 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10521 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10522 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10523 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10524 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10525 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10526 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10527 */ >+ IC_EVEX_K_B, /* 10528 */ >+ IC_EVEX_K_B, /* 10529 */ >+ IC_EVEX_XS_K_B, /* 10530 */ >+ IC_EVEX_XS_K_B, /* 10531 */ >+ IC_EVEX_XD_K_B, /* 10532 */ >+ IC_EVEX_XD_K_B, /* 10533 */ >+ IC_EVEX_XD_K_B, /* 10534 */ >+ IC_EVEX_XD_K_B, /* 10535 */ >+ IC_EVEX_W_K_B, /* 10536 */ >+ IC_EVEX_W_K_B, /* 10537 */ >+ IC_EVEX_W_XS_K_B, /* 10538 */ >+ IC_EVEX_W_XS_K_B, /* 10539 */ >+ IC_EVEX_W_XD_K_B, /* 10540 */ >+ IC_EVEX_W_XD_K_B, /* 10541 */ >+ IC_EVEX_W_XD_K_B, /* 10542 */ >+ IC_EVEX_W_XD_K_B, /* 10543 */ >+ IC_EVEX_OPSIZE_K_B, /* 10544 */ >+ IC_EVEX_OPSIZE_K_B, /* 10545 */ >+ IC_EVEX_OPSIZE_K_B, /* 10546 */ >+ IC_EVEX_OPSIZE_K_B, /* 10547 */ >+ IC_EVEX_OPSIZE_K_B, /* 10548 */ >+ IC_EVEX_OPSIZE_K_B, /* 10549 */ >+ IC_EVEX_OPSIZE_K_B, /* 10550 */ >+ IC_EVEX_OPSIZE_K_B, /* 10551 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10552 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10553 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10554 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10555 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10556 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10557 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10558 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10559 */ >+ IC_EVEX_K_B, /* 10560 */ >+ IC_EVEX_K_B, /* 10561 */ >+ IC_EVEX_XS_K_B, /* 10562 */ >+ IC_EVEX_XS_K_B, /* 10563 */ >+ IC_EVEX_XD_K_B, /* 10564 */ >+ IC_EVEX_XD_K_B, /* 10565 */ >+ IC_EVEX_XD_K_B, /* 10566 */ >+ IC_EVEX_XD_K_B, /* 10567 */ >+ IC_EVEX_W_K_B, /* 10568 */ >+ IC_EVEX_W_K_B, /* 10569 */ >+ IC_EVEX_W_XS_K_B, /* 10570 */ >+ IC_EVEX_W_XS_K_B, /* 10571 */ >+ IC_EVEX_W_XD_K_B, /* 10572 */ >+ IC_EVEX_W_XD_K_B, /* 10573 */ >+ IC_EVEX_W_XD_K_B, /* 10574 */ >+ IC_EVEX_W_XD_K_B, /* 10575 */ >+ IC_EVEX_OPSIZE_K_B, /* 10576 */ >+ IC_EVEX_OPSIZE_K_B, /* 10577 */ >+ IC_EVEX_OPSIZE_K_B, /* 10578 */ >+ IC_EVEX_OPSIZE_K_B, /* 10579 */ >+ IC_EVEX_OPSIZE_K_B, /* 10580 */ >+ IC_EVEX_OPSIZE_K_B, /* 10581 */ >+ IC_EVEX_OPSIZE_K_B, /* 10582 */ >+ IC_EVEX_OPSIZE_K_B, /* 10583 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10584 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10585 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10586 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10587 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10588 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10589 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10590 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10591 */ >+ IC_EVEX_K_B, /* 10592 */ >+ IC_EVEX_K_B, /* 10593 */ >+ IC_EVEX_XS_K_B, /* 10594 */ >+ IC_EVEX_XS_K_B, /* 10595 */ >+ IC_EVEX_XD_K_B, /* 10596 */ >+ IC_EVEX_XD_K_B, /* 10597 */ >+ IC_EVEX_XD_K_B, /* 10598 */ >+ IC_EVEX_XD_K_B, /* 10599 */ >+ IC_EVEX_W_K_B, /* 10600 */ >+ IC_EVEX_W_K_B, /* 10601 */ >+ IC_EVEX_W_XS_K_B, /* 10602 */ >+ IC_EVEX_W_XS_K_B, /* 10603 */ >+ IC_EVEX_W_XD_K_B, /* 10604 */ >+ IC_EVEX_W_XD_K_B, /* 10605 */ >+ IC_EVEX_W_XD_K_B, /* 10606 */ >+ IC_EVEX_W_XD_K_B, /* 10607 */ >+ IC_EVEX_OPSIZE_K_B, /* 10608 */ >+ IC_EVEX_OPSIZE_K_B, /* 10609 */ >+ IC_EVEX_OPSIZE_K_B, /* 10610 */ >+ IC_EVEX_OPSIZE_K_B, /* 10611 */ >+ IC_EVEX_OPSIZE_K_B, /* 10612 */ >+ IC_EVEX_OPSIZE_K_B, /* 10613 */ >+ IC_EVEX_OPSIZE_K_B, /* 10614 */ >+ IC_EVEX_OPSIZE_K_B, /* 10615 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10616 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10617 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10618 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10619 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10620 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10621 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10622 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10623 */ >+ IC_EVEX_K_B, /* 10624 */ >+ IC_EVEX_K_B, /* 10625 */ >+ IC_EVEX_XS_K_B, /* 10626 */ >+ IC_EVEX_XS_K_B, /* 10627 */ >+ IC_EVEX_XD_K_B, /* 10628 */ >+ IC_EVEX_XD_K_B, /* 10629 */ >+ IC_EVEX_XD_K_B, /* 10630 */ >+ IC_EVEX_XD_K_B, /* 10631 */ >+ IC_EVEX_W_K_B, /* 10632 */ >+ IC_EVEX_W_K_B, /* 10633 */ >+ IC_EVEX_W_XS_K_B, /* 10634 */ >+ IC_EVEX_W_XS_K_B, /* 10635 */ >+ IC_EVEX_W_XD_K_B, /* 10636 */ >+ IC_EVEX_W_XD_K_B, /* 10637 */ >+ IC_EVEX_W_XD_K_B, /* 10638 */ >+ IC_EVEX_W_XD_K_B, /* 10639 */ >+ IC_EVEX_OPSIZE_K_B, /* 10640 */ >+ IC_EVEX_OPSIZE_K_B, /* 10641 */ >+ IC_EVEX_OPSIZE_K_B, /* 10642 */ >+ IC_EVEX_OPSIZE_K_B, /* 10643 */ >+ IC_EVEX_OPSIZE_K_B, /* 10644 */ >+ IC_EVEX_OPSIZE_K_B, /* 10645 */ >+ IC_EVEX_OPSIZE_K_B, /* 10646 */ >+ IC_EVEX_OPSIZE_K_B, /* 10647 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10648 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10649 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10650 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10651 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10652 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10653 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10654 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10655 */ >+ IC_EVEX_K_B, /* 10656 */ >+ IC_EVEX_K_B, /* 10657 */ >+ IC_EVEX_XS_K_B, /* 10658 */ >+ IC_EVEX_XS_K_B, /* 10659 */ >+ IC_EVEX_XD_K_B, /* 10660 */ >+ IC_EVEX_XD_K_B, /* 10661 */ >+ IC_EVEX_XD_K_B, /* 10662 */ >+ IC_EVEX_XD_K_B, /* 10663 */ >+ IC_EVEX_W_K_B, /* 10664 */ >+ IC_EVEX_W_K_B, /* 10665 */ >+ IC_EVEX_W_XS_K_B, /* 10666 */ >+ IC_EVEX_W_XS_K_B, /* 10667 */ >+ IC_EVEX_W_XD_K_B, /* 10668 */ >+ IC_EVEX_W_XD_K_B, /* 10669 */ >+ IC_EVEX_W_XD_K_B, /* 10670 */ >+ IC_EVEX_W_XD_K_B, /* 10671 */ >+ IC_EVEX_OPSIZE_K_B, /* 10672 */ >+ IC_EVEX_OPSIZE_K_B, /* 10673 */ >+ IC_EVEX_OPSIZE_K_B, /* 10674 */ >+ IC_EVEX_OPSIZE_K_B, /* 10675 */ >+ IC_EVEX_OPSIZE_K_B, /* 10676 */ >+ IC_EVEX_OPSIZE_K_B, /* 10677 */ >+ IC_EVEX_OPSIZE_K_B, /* 10678 */ >+ IC_EVEX_OPSIZE_K_B, /* 10679 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10680 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10681 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10682 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10683 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10684 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10685 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10686 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10687 */ >+ IC_EVEX_K_B, /* 10688 */ >+ IC_EVEX_K_B, /* 10689 */ >+ IC_EVEX_XS_K_B, /* 10690 */ >+ IC_EVEX_XS_K_B, /* 10691 */ >+ IC_EVEX_XD_K_B, /* 10692 */ >+ IC_EVEX_XD_K_B, /* 10693 */ >+ IC_EVEX_XD_K_B, /* 10694 */ >+ IC_EVEX_XD_K_B, /* 10695 */ >+ IC_EVEX_W_K_B, /* 10696 */ >+ IC_EVEX_W_K_B, /* 10697 */ >+ IC_EVEX_W_XS_K_B, /* 10698 */ >+ IC_EVEX_W_XS_K_B, /* 10699 */ >+ IC_EVEX_W_XD_K_B, /* 10700 */ >+ IC_EVEX_W_XD_K_B, /* 10701 */ >+ IC_EVEX_W_XD_K_B, /* 10702 */ >+ IC_EVEX_W_XD_K_B, /* 10703 */ >+ IC_EVEX_OPSIZE_K_B, /* 10704 */ >+ IC_EVEX_OPSIZE_K_B, /* 10705 */ >+ IC_EVEX_OPSIZE_K_B, /* 10706 */ >+ IC_EVEX_OPSIZE_K_B, /* 10707 */ >+ IC_EVEX_OPSIZE_K_B, /* 10708 */ >+ IC_EVEX_OPSIZE_K_B, /* 10709 */ >+ IC_EVEX_OPSIZE_K_B, /* 10710 */ >+ IC_EVEX_OPSIZE_K_B, /* 10711 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10712 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10713 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10714 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10715 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10716 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10717 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10718 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10719 */ >+ IC_EVEX_K_B, /* 10720 */ >+ IC_EVEX_K_B, /* 10721 */ >+ IC_EVEX_XS_K_B, /* 10722 */ >+ IC_EVEX_XS_K_B, /* 10723 */ >+ IC_EVEX_XD_K_B, /* 10724 */ >+ IC_EVEX_XD_K_B, /* 10725 */ >+ IC_EVEX_XD_K_B, /* 10726 */ >+ IC_EVEX_XD_K_B, /* 10727 */ >+ IC_EVEX_W_K_B, /* 10728 */ >+ IC_EVEX_W_K_B, /* 10729 */ >+ IC_EVEX_W_XS_K_B, /* 10730 */ >+ IC_EVEX_W_XS_K_B, /* 10731 */ >+ IC_EVEX_W_XD_K_B, /* 10732 */ >+ IC_EVEX_W_XD_K_B, /* 10733 */ >+ IC_EVEX_W_XD_K_B, /* 10734 */ >+ IC_EVEX_W_XD_K_B, /* 10735 */ >+ IC_EVEX_OPSIZE_K_B, /* 10736 */ >+ IC_EVEX_OPSIZE_K_B, /* 10737 */ >+ IC_EVEX_OPSIZE_K_B, /* 10738 */ >+ IC_EVEX_OPSIZE_K_B, /* 10739 */ >+ IC_EVEX_OPSIZE_K_B, /* 10740 */ >+ IC_EVEX_OPSIZE_K_B, /* 10741 */ >+ IC_EVEX_OPSIZE_K_B, /* 10742 */ >+ IC_EVEX_OPSIZE_K_B, /* 10743 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10744 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10745 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10746 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10747 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10748 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10749 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10750 */ >+ IC_EVEX_W_OPSIZE_K_B, /* 10751 */ >+ IC, /* 10752 */ >+ IC_64BIT, /* 10753 */ >+ IC_XS, /* 10754 */ >+ IC_64BIT_XS, /* 10755 */ >+ IC_XD, /* 10756 */ >+ IC_64BIT_XD, /* 10757 */ >+ IC_XS, /* 10758 */ >+ IC_64BIT_XS, /* 10759 */ >+ IC, /* 10760 */ >+ IC_64BIT_REXW, /* 10761 */ >+ IC_XS, /* 10762 */ >+ IC_64BIT_REXW_XS, /* 10763 */ >+ IC_XD, /* 10764 */ >+ IC_64BIT_REXW_XD, /* 10765 */ >+ IC_XS, /* 10766 */ >+ IC_64BIT_REXW_XS, /* 10767 */ >+ IC_OPSIZE, /* 10768 */ >+ IC_64BIT_OPSIZE, /* 10769 */ >+ IC_XS_OPSIZE, /* 10770 */ >+ IC_64BIT_XS_OPSIZE, /* 10771 */ >+ IC_XD_OPSIZE, /* 10772 */ >+ IC_64BIT_XD_OPSIZE, /* 10773 */ >+ IC_XS_OPSIZE, /* 10774 */ >+ IC_64BIT_XD_OPSIZE, /* 10775 */ >+ IC_OPSIZE, /* 10776 */ >+ IC_64BIT_REXW_OPSIZE, /* 10777 */ >+ IC_XS_OPSIZE, /* 10778 */ >+ IC_64BIT_REXW_XS, /* 10779 */ >+ IC_XD_OPSIZE, /* 10780 */ >+ IC_64BIT_REXW_XD, /* 10781 */ >+ IC_XS_OPSIZE, /* 10782 */ >+ IC_64BIT_REXW_XS, /* 10783 */ >+ IC_ADSIZE, /* 10784 */ >+ IC_64BIT_ADSIZE, /* 10785 */ >+ IC_XS, /* 10786 */ >+ IC_64BIT_XS, /* 10787 */ >+ IC_XD, /* 10788 */ >+ IC_64BIT_XD, /* 10789 */ >+ IC_XS, /* 10790 */ >+ IC_64BIT_XS, /* 10791 */ >+ IC_ADSIZE, /* 10792 */ >+ IC_64BIT_ADSIZE, /* 10793 */ >+ IC_XS, /* 10794 */ >+ IC_64BIT_REXW_XS, /* 10795 */ >+ IC_XD, /* 10796 */ >+ IC_64BIT_REXW_XD, /* 10797 */ >+ IC_XS, /* 10798 */ >+ IC_64BIT_REXW_XS, /* 10799 */ >+ IC_OPSIZE, /* 10800 */ >+ IC_64BIT_OPSIZE, /* 10801 */ >+ IC_XS_OPSIZE, /* 10802 */ >+ IC_64BIT_XS_OPSIZE, /* 10803 */ >+ IC_XD_OPSIZE, /* 10804 */ >+ IC_64BIT_XD_OPSIZE, /* 10805 */ >+ IC_XS_OPSIZE, /* 10806 */ >+ IC_64BIT_XD_OPSIZE, /* 10807 */ >+ IC_OPSIZE, /* 10808 */ >+ IC_64BIT_REXW_OPSIZE, /* 10809 */ >+ IC_XS_OPSIZE, /* 10810 */ >+ IC_64BIT_REXW_XS, /* 10811 */ >+ IC_XD_OPSIZE, /* 10812 */ >+ IC_64BIT_REXW_XD, /* 10813 */ >+ IC_XS_OPSIZE, /* 10814 */ >+ IC_64BIT_REXW_XS, /* 10815 */ >+ IC_VEX, /* 10816 */ >+ IC_VEX, /* 10817 */ >+ IC_VEX_XS, /* 10818 */ >+ IC_VEX_XS, /* 10819 */ >+ IC_VEX_XD, /* 10820 */ >+ IC_VEX_XD, /* 10821 */ >+ IC_VEX_XD, /* 10822 */ >+ IC_VEX_XD, /* 10823 */ >+ IC_VEX_W, /* 10824 */ >+ IC_VEX_W, /* 10825 */ >+ IC_VEX_W_XS, /* 10826 */ >+ IC_VEX_W_XS, /* 10827 */ >+ IC_VEX_W_XD, /* 10828 */ >+ IC_VEX_W_XD, /* 10829 */ >+ IC_VEX_W_XD, /* 10830 */ >+ IC_VEX_W_XD, /* 10831 */ >+ IC_VEX_OPSIZE, /* 10832 */ >+ IC_VEX_OPSIZE, /* 10833 */ >+ IC_VEX_OPSIZE, /* 10834 */ >+ IC_VEX_OPSIZE, /* 10835 */ >+ IC_VEX_OPSIZE, /* 10836 */ >+ IC_VEX_OPSIZE, /* 10837 */ >+ IC_VEX_OPSIZE, /* 10838 */ >+ IC_VEX_OPSIZE, /* 10839 */ >+ IC_VEX_W_OPSIZE, /* 10840 */ >+ IC_VEX_W_OPSIZE, /* 10841 */ >+ IC_VEX_W_OPSIZE, /* 10842 */ >+ IC_VEX_W_OPSIZE, /* 10843 */ >+ IC_VEX_W_OPSIZE, /* 10844 */ >+ IC_VEX_W_OPSIZE, /* 10845 */ >+ IC_VEX_W_OPSIZE, /* 10846 */ >+ IC_VEX_W_OPSIZE, /* 10847 */ >+ IC_VEX, /* 10848 */ >+ IC_VEX, /* 10849 */ >+ IC_VEX_XS, /* 10850 */ >+ IC_VEX_XS, /* 10851 */ >+ IC_VEX_XD, /* 10852 */ >+ IC_VEX_XD, /* 10853 */ >+ IC_VEX_XD, /* 10854 */ >+ IC_VEX_XD, /* 10855 */ >+ IC_VEX_W, /* 10856 */ >+ IC_VEX_W, /* 10857 */ >+ IC_VEX_W_XS, /* 10858 */ >+ IC_VEX_W_XS, /* 10859 */ >+ IC_VEX_W_XD, /* 10860 */ >+ IC_VEX_W_XD, /* 10861 */ >+ IC_VEX_W_XD, /* 10862 */ >+ IC_VEX_W_XD, /* 10863 */ >+ IC_VEX_OPSIZE, /* 10864 */ >+ IC_VEX_OPSIZE, /* 10865 */ >+ IC_VEX_OPSIZE, /* 10866 */ >+ IC_VEX_OPSIZE, /* 10867 */ >+ IC_VEX_OPSIZE, /* 10868 */ >+ IC_VEX_OPSIZE, /* 10869 */ >+ IC_VEX_OPSIZE, /* 10870 */ >+ IC_VEX_OPSIZE, /* 10871 */ >+ IC_VEX_W_OPSIZE, /* 10872 */ >+ IC_VEX_W_OPSIZE, /* 10873 */ >+ IC_VEX_W_OPSIZE, /* 10874 */ >+ IC_VEX_W_OPSIZE, /* 10875 */ >+ IC_VEX_W_OPSIZE, /* 10876 */ >+ IC_VEX_W_OPSIZE, /* 10877 */ >+ IC_VEX_W_OPSIZE, /* 10878 */ >+ IC_VEX_W_OPSIZE, /* 10879 */ >+ IC_VEX_L, /* 10880 */ >+ IC_VEX_L, /* 10881 */ >+ IC_VEX_L_XS, /* 10882 */ >+ IC_VEX_L_XS, /* 10883 */ >+ IC_VEX_L_XD, /* 10884 */ >+ IC_VEX_L_XD, /* 10885 */ >+ IC_VEX_L_XD, /* 10886 */ >+ IC_VEX_L_XD, /* 10887 */ >+ IC_VEX_L_W, /* 10888 */ >+ IC_VEX_L_W, /* 10889 */ >+ IC_VEX_L_W_XS, /* 10890 */ >+ IC_VEX_L_W_XS, /* 10891 */ >+ IC_VEX_L_W_XD, /* 10892 */ >+ IC_VEX_L_W_XD, /* 10893 */ >+ IC_VEX_L_W_XD, /* 10894 */ >+ IC_VEX_L_W_XD, /* 10895 */ >+ IC_VEX_L_OPSIZE, /* 10896 */ >+ IC_VEX_L_OPSIZE, /* 10897 */ >+ IC_VEX_L_OPSIZE, /* 10898 */ >+ IC_VEX_L_OPSIZE, /* 10899 */ >+ IC_VEX_L_OPSIZE, /* 10900 */ >+ IC_VEX_L_OPSIZE, /* 10901 */ >+ IC_VEX_L_OPSIZE, /* 10902 */ >+ IC_VEX_L_OPSIZE, /* 10903 */ >+ IC_VEX_L_W_OPSIZE, /* 10904 */ >+ IC_VEX_L_W_OPSIZE, /* 10905 */ >+ IC_VEX_L_W_OPSIZE, /* 10906 */ >+ IC_VEX_L_W_OPSIZE, /* 10907 */ >+ IC_VEX_L_W_OPSIZE, /* 10908 */ >+ IC_VEX_L_W_OPSIZE, /* 10909 */ >+ IC_VEX_L_W_OPSIZE, /* 10910 */ >+ IC_VEX_L_W_OPSIZE, /* 10911 */ >+ IC_VEX_L, /* 10912 */ >+ IC_VEX_L, /* 10913 */ >+ IC_VEX_L_XS, /* 10914 */ >+ IC_VEX_L_XS, /* 10915 */ >+ IC_VEX_L_XD, /* 10916 */ >+ IC_VEX_L_XD, /* 10917 */ >+ IC_VEX_L_XD, /* 10918 */ >+ IC_VEX_L_XD, /* 10919 */ >+ IC_VEX_L_W, /* 10920 */ >+ IC_VEX_L_W, /* 10921 */ >+ IC_VEX_L_W_XS, /* 10922 */ >+ IC_VEX_L_W_XS, /* 10923 */ >+ IC_VEX_L_W_XD, /* 10924 */ >+ IC_VEX_L_W_XD, /* 10925 */ >+ IC_VEX_L_W_XD, /* 10926 */ >+ IC_VEX_L_W_XD, /* 10927 */ >+ IC_VEX_L_OPSIZE, /* 10928 */ >+ IC_VEX_L_OPSIZE, /* 10929 */ >+ IC_VEX_L_OPSIZE, /* 10930 */ >+ IC_VEX_L_OPSIZE, /* 10931 */ >+ IC_VEX_L_OPSIZE, /* 10932 */ >+ IC_VEX_L_OPSIZE, /* 10933 */ >+ IC_VEX_L_OPSIZE, /* 10934 */ >+ IC_VEX_L_OPSIZE, /* 10935 */ >+ IC_VEX_L_W_OPSIZE, /* 10936 */ >+ IC_VEX_L_W_OPSIZE, /* 10937 */ >+ IC_VEX_L_W_OPSIZE, /* 10938 */ >+ IC_VEX_L_W_OPSIZE, /* 10939 */ >+ IC_VEX_L_W_OPSIZE, /* 10940 */ >+ IC_VEX_L_W_OPSIZE, /* 10941 */ >+ IC_VEX_L_W_OPSIZE, /* 10942 */ >+ IC_VEX_L_W_OPSIZE, /* 10943 */ >+ IC_VEX_L, /* 10944 */ >+ IC_VEX_L, /* 10945 */ >+ IC_VEX_L_XS, /* 10946 */ >+ IC_VEX_L_XS, /* 10947 */ >+ IC_VEX_L_XD, /* 10948 */ >+ IC_VEX_L_XD, /* 10949 */ >+ IC_VEX_L_XD, /* 10950 */ >+ IC_VEX_L_XD, /* 10951 */ >+ IC_VEX_L_W, /* 10952 */ >+ IC_VEX_L_W, /* 10953 */ >+ IC_VEX_L_W_XS, /* 10954 */ >+ IC_VEX_L_W_XS, /* 10955 */ >+ IC_VEX_L_W_XD, /* 10956 */ >+ IC_VEX_L_W_XD, /* 10957 */ >+ IC_VEX_L_W_XD, /* 10958 */ >+ IC_VEX_L_W_XD, /* 10959 */ >+ IC_VEX_L_OPSIZE, /* 10960 */ >+ IC_VEX_L_OPSIZE, /* 10961 */ >+ IC_VEX_L_OPSIZE, /* 10962 */ >+ IC_VEX_L_OPSIZE, /* 10963 */ >+ IC_VEX_L_OPSIZE, /* 10964 */ >+ IC_VEX_L_OPSIZE, /* 10965 */ >+ IC_VEX_L_OPSIZE, /* 10966 */ >+ IC_VEX_L_OPSIZE, /* 10967 */ >+ IC_VEX_L_W_OPSIZE, /* 10968 */ >+ IC_VEX_L_W_OPSIZE, /* 10969 */ >+ IC_VEX_L_W_OPSIZE, /* 10970 */ >+ IC_VEX_L_W_OPSIZE, /* 10971 */ >+ IC_VEX_L_W_OPSIZE, /* 10972 */ >+ IC_VEX_L_W_OPSIZE, /* 10973 */ >+ IC_VEX_L_W_OPSIZE, /* 10974 */ >+ IC_VEX_L_W_OPSIZE, /* 10975 */ >+ IC_VEX_L, /* 10976 */ >+ IC_VEX_L, /* 10977 */ >+ IC_VEX_L_XS, /* 10978 */ >+ IC_VEX_L_XS, /* 10979 */ >+ IC_VEX_L_XD, /* 10980 */ >+ IC_VEX_L_XD, /* 10981 */ >+ IC_VEX_L_XD, /* 10982 */ >+ IC_VEX_L_XD, /* 10983 */ >+ IC_VEX_L_W, /* 10984 */ >+ IC_VEX_L_W, /* 10985 */ >+ IC_VEX_L_W_XS, /* 10986 */ >+ IC_VEX_L_W_XS, /* 10987 */ >+ IC_VEX_L_W_XD, /* 10988 */ >+ IC_VEX_L_W_XD, /* 10989 */ >+ IC_VEX_L_W_XD, /* 10990 */ >+ IC_VEX_L_W_XD, /* 10991 */ >+ IC_VEX_L_OPSIZE, /* 10992 */ >+ IC_VEX_L_OPSIZE, /* 10993 */ >+ IC_VEX_L_OPSIZE, /* 10994 */ >+ IC_VEX_L_OPSIZE, /* 10995 */ >+ IC_VEX_L_OPSIZE, /* 10996 */ >+ IC_VEX_L_OPSIZE, /* 10997 */ >+ IC_VEX_L_OPSIZE, /* 10998 */ >+ IC_VEX_L_OPSIZE, /* 10999 */ >+ IC_VEX_L_W_OPSIZE, /* 11000 */ >+ IC_VEX_L_W_OPSIZE, /* 11001 */ >+ IC_VEX_L_W_OPSIZE, /* 11002 */ >+ IC_VEX_L_W_OPSIZE, /* 11003 */ >+ IC_VEX_L_W_OPSIZE, /* 11004 */ >+ IC_VEX_L_W_OPSIZE, /* 11005 */ >+ IC_VEX_L_W_OPSIZE, /* 11006 */ >+ IC_VEX_L_W_OPSIZE, /* 11007 */ >+ IC_EVEX_L_K_B, /* 11008 */ >+ IC_EVEX_L_K_B, /* 11009 */ >+ IC_EVEX_L_XS_K_B, /* 11010 */ >+ IC_EVEX_L_XS_K_B, /* 11011 */ >+ IC_EVEX_L_XD_K_B, /* 11012 */ >+ IC_EVEX_L_XD_K_B, /* 11013 */ >+ IC_EVEX_L_XD_K_B, /* 11014 */ >+ IC_EVEX_L_XD_K_B, /* 11015 */ >+ IC_EVEX_L_W_K_B, /* 11016 */ >+ IC_EVEX_L_W_K_B, /* 11017 */ >+ IC_EVEX_L_W_XS_K_B, /* 11018 */ >+ IC_EVEX_L_W_XS_K_B, /* 11019 */ >+ IC_EVEX_L_W_XD_K_B, /* 11020 */ >+ IC_EVEX_L_W_XD_K_B, /* 11021 */ >+ IC_EVEX_L_W_XD_K_B, /* 11022 */ >+ IC_EVEX_L_W_XD_K_B, /* 11023 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11024 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11025 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11026 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11027 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11028 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11029 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11030 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11031 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11032 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11033 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11034 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11035 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11036 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11037 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11038 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11039 */ >+ IC_EVEX_L_K_B, /* 11040 */ >+ IC_EVEX_L_K_B, /* 11041 */ >+ IC_EVEX_L_XS_K_B, /* 11042 */ >+ IC_EVEX_L_XS_K_B, /* 11043 */ >+ IC_EVEX_L_XD_K_B, /* 11044 */ >+ IC_EVEX_L_XD_K_B, /* 11045 */ >+ IC_EVEX_L_XD_K_B, /* 11046 */ >+ IC_EVEX_L_XD_K_B, /* 11047 */ >+ IC_EVEX_L_W_K_B, /* 11048 */ >+ IC_EVEX_L_W_K_B, /* 11049 */ >+ IC_EVEX_L_W_XS_K_B, /* 11050 */ >+ IC_EVEX_L_W_XS_K_B, /* 11051 */ >+ IC_EVEX_L_W_XD_K_B, /* 11052 */ >+ IC_EVEX_L_W_XD_K_B, /* 11053 */ >+ IC_EVEX_L_W_XD_K_B, /* 11054 */ >+ IC_EVEX_L_W_XD_K_B, /* 11055 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11056 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11057 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11058 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11059 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11060 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11061 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11062 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11063 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11064 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11065 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11066 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11067 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11068 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11069 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11070 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11071 */ >+ IC_EVEX_L_K_B, /* 11072 */ >+ IC_EVEX_L_K_B, /* 11073 */ >+ IC_EVEX_L_XS_K_B, /* 11074 */ >+ IC_EVEX_L_XS_K_B, /* 11075 */ >+ IC_EVEX_L_XD_K_B, /* 11076 */ >+ IC_EVEX_L_XD_K_B, /* 11077 */ >+ IC_EVEX_L_XD_K_B, /* 11078 */ >+ IC_EVEX_L_XD_K_B, /* 11079 */ >+ IC_EVEX_L_W_K_B, /* 11080 */ >+ IC_EVEX_L_W_K_B, /* 11081 */ >+ IC_EVEX_L_W_XS_K_B, /* 11082 */ >+ IC_EVEX_L_W_XS_K_B, /* 11083 */ >+ IC_EVEX_L_W_XD_K_B, /* 11084 */ >+ IC_EVEX_L_W_XD_K_B, /* 11085 */ >+ IC_EVEX_L_W_XD_K_B, /* 11086 */ >+ IC_EVEX_L_W_XD_K_B, /* 11087 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11088 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11089 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11090 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11091 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11092 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11093 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11094 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11095 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11096 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11097 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11098 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11099 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11100 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11101 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11102 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11103 */ >+ IC_EVEX_L_K_B, /* 11104 */ >+ IC_EVEX_L_K_B, /* 11105 */ >+ IC_EVEX_L_XS_K_B, /* 11106 */ >+ IC_EVEX_L_XS_K_B, /* 11107 */ >+ IC_EVEX_L_XD_K_B, /* 11108 */ >+ IC_EVEX_L_XD_K_B, /* 11109 */ >+ IC_EVEX_L_XD_K_B, /* 11110 */ >+ IC_EVEX_L_XD_K_B, /* 11111 */ >+ IC_EVEX_L_W_K_B, /* 11112 */ >+ IC_EVEX_L_W_K_B, /* 11113 */ >+ IC_EVEX_L_W_XS_K_B, /* 11114 */ >+ IC_EVEX_L_W_XS_K_B, /* 11115 */ >+ IC_EVEX_L_W_XD_K_B, /* 11116 */ >+ IC_EVEX_L_W_XD_K_B, /* 11117 */ >+ IC_EVEX_L_W_XD_K_B, /* 11118 */ >+ IC_EVEX_L_W_XD_K_B, /* 11119 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11120 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11121 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11122 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11123 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11124 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11125 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11126 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11127 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11128 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11129 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11130 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11131 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11132 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11133 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11134 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11135 */ >+ IC_EVEX_L_K_B, /* 11136 */ >+ IC_EVEX_L_K_B, /* 11137 */ >+ IC_EVEX_L_XS_K_B, /* 11138 */ >+ IC_EVEX_L_XS_K_B, /* 11139 */ >+ IC_EVEX_L_XD_K_B, /* 11140 */ >+ IC_EVEX_L_XD_K_B, /* 11141 */ >+ IC_EVEX_L_XD_K_B, /* 11142 */ >+ IC_EVEX_L_XD_K_B, /* 11143 */ >+ IC_EVEX_L_W_K_B, /* 11144 */ >+ IC_EVEX_L_W_K_B, /* 11145 */ >+ IC_EVEX_L_W_XS_K_B, /* 11146 */ >+ IC_EVEX_L_W_XS_K_B, /* 11147 */ >+ IC_EVEX_L_W_XD_K_B, /* 11148 */ >+ IC_EVEX_L_W_XD_K_B, /* 11149 */ >+ IC_EVEX_L_W_XD_K_B, /* 11150 */ >+ IC_EVEX_L_W_XD_K_B, /* 11151 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11152 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11153 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11154 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11155 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11156 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11157 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11158 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11159 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11160 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11161 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11162 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11163 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11164 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11165 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11166 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11167 */ >+ IC_EVEX_L_K_B, /* 11168 */ >+ IC_EVEX_L_K_B, /* 11169 */ >+ IC_EVEX_L_XS_K_B, /* 11170 */ >+ IC_EVEX_L_XS_K_B, /* 11171 */ >+ IC_EVEX_L_XD_K_B, /* 11172 */ >+ IC_EVEX_L_XD_K_B, /* 11173 */ >+ IC_EVEX_L_XD_K_B, /* 11174 */ >+ IC_EVEX_L_XD_K_B, /* 11175 */ >+ IC_EVEX_L_W_K_B, /* 11176 */ >+ IC_EVEX_L_W_K_B, /* 11177 */ >+ IC_EVEX_L_W_XS_K_B, /* 11178 */ >+ IC_EVEX_L_W_XS_K_B, /* 11179 */ >+ IC_EVEX_L_W_XD_K_B, /* 11180 */ >+ IC_EVEX_L_W_XD_K_B, /* 11181 */ >+ IC_EVEX_L_W_XD_K_B, /* 11182 */ >+ IC_EVEX_L_W_XD_K_B, /* 11183 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11184 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11185 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11186 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11187 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11188 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11189 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11190 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11191 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11192 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11193 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11194 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11195 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11196 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11197 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11198 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11199 */ >+ IC_EVEX_L_K_B, /* 11200 */ >+ IC_EVEX_L_K_B, /* 11201 */ >+ IC_EVEX_L_XS_K_B, /* 11202 */ >+ IC_EVEX_L_XS_K_B, /* 11203 */ >+ IC_EVEX_L_XD_K_B, /* 11204 */ >+ IC_EVEX_L_XD_K_B, /* 11205 */ >+ IC_EVEX_L_XD_K_B, /* 11206 */ >+ IC_EVEX_L_XD_K_B, /* 11207 */ >+ IC_EVEX_L_W_K_B, /* 11208 */ >+ IC_EVEX_L_W_K_B, /* 11209 */ >+ IC_EVEX_L_W_XS_K_B, /* 11210 */ >+ IC_EVEX_L_W_XS_K_B, /* 11211 */ >+ IC_EVEX_L_W_XD_K_B, /* 11212 */ >+ IC_EVEX_L_W_XD_K_B, /* 11213 */ >+ IC_EVEX_L_W_XD_K_B, /* 11214 */ >+ IC_EVEX_L_W_XD_K_B, /* 11215 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11216 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11217 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11218 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11219 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11220 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11221 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11222 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11223 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11224 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11225 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11226 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11227 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11228 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11229 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11230 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11231 */ >+ IC_EVEX_L_K_B, /* 11232 */ >+ IC_EVEX_L_K_B, /* 11233 */ >+ IC_EVEX_L_XS_K_B, /* 11234 */ >+ IC_EVEX_L_XS_K_B, /* 11235 */ >+ IC_EVEX_L_XD_K_B, /* 11236 */ >+ IC_EVEX_L_XD_K_B, /* 11237 */ >+ IC_EVEX_L_XD_K_B, /* 11238 */ >+ IC_EVEX_L_XD_K_B, /* 11239 */ >+ IC_EVEX_L_W_K_B, /* 11240 */ >+ IC_EVEX_L_W_K_B, /* 11241 */ >+ IC_EVEX_L_W_XS_K_B, /* 11242 */ >+ IC_EVEX_L_W_XS_K_B, /* 11243 */ >+ IC_EVEX_L_W_XD_K_B, /* 11244 */ >+ IC_EVEX_L_W_XD_K_B, /* 11245 */ >+ IC_EVEX_L_W_XD_K_B, /* 11246 */ >+ IC_EVEX_L_W_XD_K_B, /* 11247 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11248 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11249 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11250 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11251 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11252 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11253 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11254 */ >+ IC_EVEX_L_OPSIZE_K_B, /* 11255 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11256 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11257 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11258 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11259 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11260 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11261 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11262 */ >+ IC_EVEX_L_W_OPSIZE_K_B, /* 11263 */ >+ IC, /* 11264 */ >+ IC_64BIT, /* 11265 */ >+ IC_XS, /* 11266 */ >+ IC_64BIT_XS, /* 11267 */ >+ IC_XD, /* 11268 */ >+ IC_64BIT_XD, /* 11269 */ >+ IC_XS, /* 11270 */ >+ IC_64BIT_XS, /* 11271 */ >+ IC, /* 11272 */ >+ IC_64BIT_REXW, /* 11273 */ >+ IC_XS, /* 11274 */ >+ IC_64BIT_REXW_XS, /* 11275 */ >+ IC_XD, /* 11276 */ >+ IC_64BIT_REXW_XD, /* 11277 */ >+ IC_XS, /* 11278 */ >+ IC_64BIT_REXW_XS, /* 11279 */ >+ IC_OPSIZE, /* 11280 */ >+ IC_64BIT_OPSIZE, /* 11281 */ >+ IC_XS_OPSIZE, /* 11282 */ >+ IC_64BIT_XS_OPSIZE, /* 11283 */ >+ IC_XD_OPSIZE, /* 11284 */ >+ IC_64BIT_XD_OPSIZE, /* 11285 */ >+ IC_XS_OPSIZE, /* 11286 */ >+ IC_64BIT_XD_OPSIZE, /* 11287 */ >+ IC_OPSIZE, /* 11288 */ >+ IC_64BIT_REXW_OPSIZE, /* 11289 */ >+ IC_XS_OPSIZE, /* 11290 */ >+ IC_64BIT_REXW_XS, /* 11291 */ >+ IC_XD_OPSIZE, /* 11292 */ >+ IC_64BIT_REXW_XD, /* 11293 */ >+ IC_XS_OPSIZE, /* 11294 */ >+ IC_64BIT_REXW_XS, /* 11295 */ >+ IC_ADSIZE, /* 11296 */ >+ IC_64BIT_ADSIZE, /* 11297 */ >+ IC_XS, /* 11298 */ >+ IC_64BIT_XS, /* 11299 */ >+ IC_XD, /* 11300 */ >+ IC_64BIT_XD, /* 11301 */ >+ IC_XS, /* 11302 */ >+ IC_64BIT_XS, /* 11303 */ >+ IC_ADSIZE, /* 11304 */ >+ IC_64BIT_ADSIZE, /* 11305 */ >+ IC_XS, /* 11306 */ >+ IC_64BIT_REXW_XS, /* 11307 */ >+ IC_XD, /* 11308 */ >+ IC_64BIT_REXW_XD, /* 11309 */ >+ IC_XS, /* 11310 */ >+ IC_64BIT_REXW_XS, /* 11311 */ >+ IC_OPSIZE, /* 11312 */ >+ IC_64BIT_OPSIZE, /* 11313 */ >+ IC_XS_OPSIZE, /* 11314 */ >+ IC_64BIT_XS_OPSIZE, /* 11315 */ >+ IC_XD_OPSIZE, /* 11316 */ >+ IC_64BIT_XD_OPSIZE, /* 11317 */ >+ IC_XS_OPSIZE, /* 11318 */ >+ IC_64BIT_XD_OPSIZE, /* 11319 */ >+ IC_OPSIZE, /* 11320 */ >+ IC_64BIT_REXW_OPSIZE, /* 11321 */ >+ IC_XS_OPSIZE, /* 11322 */ >+ IC_64BIT_REXW_XS, /* 11323 */ >+ IC_XD_OPSIZE, /* 11324 */ >+ IC_64BIT_REXW_XD, /* 11325 */ >+ IC_XS_OPSIZE, /* 11326 */ >+ IC_64BIT_REXW_XS, /* 11327 */ >+ IC_VEX, /* 11328 */ >+ IC_VEX, /* 11329 */ >+ IC_VEX_XS, /* 11330 */ >+ IC_VEX_XS, /* 11331 */ >+ IC_VEX_XD, /* 11332 */ >+ IC_VEX_XD, /* 11333 */ >+ IC_VEX_XD, /* 11334 */ >+ IC_VEX_XD, /* 11335 */ >+ IC_VEX_W, /* 11336 */ >+ IC_VEX_W, /* 11337 */ >+ IC_VEX_W_XS, /* 11338 */ >+ IC_VEX_W_XS, /* 11339 */ >+ IC_VEX_W_XD, /* 11340 */ >+ IC_VEX_W_XD, /* 11341 */ >+ IC_VEX_W_XD, /* 11342 */ >+ IC_VEX_W_XD, /* 11343 */ >+ IC_VEX_OPSIZE, /* 11344 */ >+ IC_VEX_OPSIZE, /* 11345 */ >+ IC_VEX_OPSIZE, /* 11346 */ >+ IC_VEX_OPSIZE, /* 11347 */ >+ IC_VEX_OPSIZE, /* 11348 */ >+ IC_VEX_OPSIZE, /* 11349 */ >+ IC_VEX_OPSIZE, /* 11350 */ >+ IC_VEX_OPSIZE, /* 11351 */ >+ IC_VEX_W_OPSIZE, /* 11352 */ >+ IC_VEX_W_OPSIZE, /* 11353 */ >+ IC_VEX_W_OPSIZE, /* 11354 */ >+ IC_VEX_W_OPSIZE, /* 11355 */ >+ IC_VEX_W_OPSIZE, /* 11356 */ >+ IC_VEX_W_OPSIZE, /* 11357 */ >+ IC_VEX_W_OPSIZE, /* 11358 */ >+ IC_VEX_W_OPSIZE, /* 11359 */ >+ IC_VEX, /* 11360 */ >+ IC_VEX, /* 11361 */ >+ IC_VEX_XS, /* 11362 */ >+ IC_VEX_XS, /* 11363 */ >+ IC_VEX_XD, /* 11364 */ >+ IC_VEX_XD, /* 11365 */ >+ IC_VEX_XD, /* 11366 */ >+ IC_VEX_XD, /* 11367 */ >+ IC_VEX_W, /* 11368 */ >+ IC_VEX_W, /* 11369 */ >+ IC_VEX_W_XS, /* 11370 */ >+ IC_VEX_W_XS, /* 11371 */ >+ IC_VEX_W_XD, /* 11372 */ >+ IC_VEX_W_XD, /* 11373 */ >+ IC_VEX_W_XD, /* 11374 */ >+ IC_VEX_W_XD, /* 11375 */ >+ IC_VEX_OPSIZE, /* 11376 */ >+ IC_VEX_OPSIZE, /* 11377 */ >+ IC_VEX_OPSIZE, /* 11378 */ >+ IC_VEX_OPSIZE, /* 11379 */ >+ IC_VEX_OPSIZE, /* 11380 */ >+ IC_VEX_OPSIZE, /* 11381 */ >+ IC_VEX_OPSIZE, /* 11382 */ >+ IC_VEX_OPSIZE, /* 11383 */ >+ IC_VEX_W_OPSIZE, /* 11384 */ >+ IC_VEX_W_OPSIZE, /* 11385 */ >+ IC_VEX_W_OPSIZE, /* 11386 */ >+ IC_VEX_W_OPSIZE, /* 11387 */ >+ IC_VEX_W_OPSIZE, /* 11388 */ >+ IC_VEX_W_OPSIZE, /* 11389 */ >+ IC_VEX_W_OPSIZE, /* 11390 */ >+ IC_VEX_W_OPSIZE, /* 11391 */ >+ IC_VEX_L, /* 11392 */ >+ IC_VEX_L, /* 11393 */ >+ IC_VEX_L_XS, /* 11394 */ >+ IC_VEX_L_XS, /* 11395 */ >+ IC_VEX_L_XD, /* 11396 */ >+ IC_VEX_L_XD, /* 11397 */ >+ IC_VEX_L_XD, /* 11398 */ >+ IC_VEX_L_XD, /* 11399 */ >+ IC_VEX_L_W, /* 11400 */ >+ IC_VEX_L_W, /* 11401 */ >+ IC_VEX_L_W_XS, /* 11402 */ >+ IC_VEX_L_W_XS, /* 11403 */ >+ IC_VEX_L_W_XD, /* 11404 */ >+ IC_VEX_L_W_XD, /* 11405 */ >+ IC_VEX_L_W_XD, /* 11406 */ >+ IC_VEX_L_W_XD, /* 11407 */ >+ IC_VEX_L_OPSIZE, /* 11408 */ >+ IC_VEX_L_OPSIZE, /* 11409 */ >+ IC_VEX_L_OPSIZE, /* 11410 */ >+ IC_VEX_L_OPSIZE, /* 11411 */ >+ IC_VEX_L_OPSIZE, /* 11412 */ >+ IC_VEX_L_OPSIZE, /* 11413 */ >+ IC_VEX_L_OPSIZE, /* 11414 */ >+ IC_VEX_L_OPSIZE, /* 11415 */ >+ IC_VEX_L_W_OPSIZE, /* 11416 */ >+ IC_VEX_L_W_OPSIZE, /* 11417 */ >+ IC_VEX_L_W_OPSIZE, /* 11418 */ >+ IC_VEX_L_W_OPSIZE, /* 11419 */ >+ IC_VEX_L_W_OPSIZE, /* 11420 */ >+ IC_VEX_L_W_OPSIZE, /* 11421 */ >+ IC_VEX_L_W_OPSIZE, /* 11422 */ >+ IC_VEX_L_W_OPSIZE, /* 11423 */ >+ IC_VEX_L, /* 11424 */ >+ IC_VEX_L, /* 11425 */ >+ IC_VEX_L_XS, /* 11426 */ >+ IC_VEX_L_XS, /* 11427 */ >+ IC_VEX_L_XD, /* 11428 */ >+ IC_VEX_L_XD, /* 11429 */ >+ IC_VEX_L_XD, /* 11430 */ >+ IC_VEX_L_XD, /* 11431 */ >+ IC_VEX_L_W, /* 11432 */ >+ IC_VEX_L_W, /* 11433 */ >+ IC_VEX_L_W_XS, /* 11434 */ >+ IC_VEX_L_W_XS, /* 11435 */ >+ IC_VEX_L_W_XD, /* 11436 */ >+ IC_VEX_L_W_XD, /* 11437 */ >+ IC_VEX_L_W_XD, /* 11438 */ >+ IC_VEX_L_W_XD, /* 11439 */ >+ IC_VEX_L_OPSIZE, /* 11440 */ >+ IC_VEX_L_OPSIZE, /* 11441 */ >+ IC_VEX_L_OPSIZE, /* 11442 */ >+ IC_VEX_L_OPSIZE, /* 11443 */ >+ IC_VEX_L_OPSIZE, /* 11444 */ >+ IC_VEX_L_OPSIZE, /* 11445 */ >+ IC_VEX_L_OPSIZE, /* 11446 */ >+ IC_VEX_L_OPSIZE, /* 11447 */ >+ IC_VEX_L_W_OPSIZE, /* 11448 */ >+ IC_VEX_L_W_OPSIZE, /* 11449 */ >+ IC_VEX_L_W_OPSIZE, /* 11450 */ >+ IC_VEX_L_W_OPSIZE, /* 11451 */ >+ IC_VEX_L_W_OPSIZE, /* 11452 */ >+ IC_VEX_L_W_OPSIZE, /* 11453 */ >+ IC_VEX_L_W_OPSIZE, /* 11454 */ >+ IC_VEX_L_W_OPSIZE, /* 11455 */ >+ IC_VEX_L, /* 11456 */ >+ IC_VEX_L, /* 11457 */ >+ IC_VEX_L_XS, /* 11458 */ >+ IC_VEX_L_XS, /* 11459 */ >+ IC_VEX_L_XD, /* 11460 */ >+ IC_VEX_L_XD, /* 11461 */ >+ IC_VEX_L_XD, /* 11462 */ >+ IC_VEX_L_XD, /* 11463 */ >+ IC_VEX_L_W, /* 11464 */ >+ IC_VEX_L_W, /* 11465 */ >+ IC_VEX_L_W_XS, /* 11466 */ >+ IC_VEX_L_W_XS, /* 11467 */ >+ IC_VEX_L_W_XD, /* 11468 */ >+ IC_VEX_L_W_XD, /* 11469 */ >+ IC_VEX_L_W_XD, /* 11470 */ >+ IC_VEX_L_W_XD, /* 11471 */ >+ IC_VEX_L_OPSIZE, /* 11472 */ >+ IC_VEX_L_OPSIZE, /* 11473 */ >+ IC_VEX_L_OPSIZE, /* 11474 */ >+ IC_VEX_L_OPSIZE, /* 11475 */ >+ IC_VEX_L_OPSIZE, /* 11476 */ >+ IC_VEX_L_OPSIZE, /* 11477 */ >+ IC_VEX_L_OPSIZE, /* 11478 */ >+ IC_VEX_L_OPSIZE, /* 11479 */ >+ IC_VEX_L_W_OPSIZE, /* 11480 */ >+ IC_VEX_L_W_OPSIZE, /* 11481 */ >+ IC_VEX_L_W_OPSIZE, /* 11482 */ >+ IC_VEX_L_W_OPSIZE, /* 11483 */ >+ IC_VEX_L_W_OPSIZE, /* 11484 */ >+ IC_VEX_L_W_OPSIZE, /* 11485 */ >+ IC_VEX_L_W_OPSIZE, /* 11486 */ >+ IC_VEX_L_W_OPSIZE, /* 11487 */ >+ IC_VEX_L, /* 11488 */ >+ IC_VEX_L, /* 11489 */ >+ IC_VEX_L_XS, /* 11490 */ >+ IC_VEX_L_XS, /* 11491 */ >+ IC_VEX_L_XD, /* 11492 */ >+ IC_VEX_L_XD, /* 11493 */ >+ IC_VEX_L_XD, /* 11494 */ >+ IC_VEX_L_XD, /* 11495 */ >+ IC_VEX_L_W, /* 11496 */ >+ IC_VEX_L_W, /* 11497 */ >+ IC_VEX_L_W_XS, /* 11498 */ >+ IC_VEX_L_W_XS, /* 11499 */ >+ IC_VEX_L_W_XD, /* 11500 */ >+ IC_VEX_L_W_XD, /* 11501 */ >+ IC_VEX_L_W_XD, /* 11502 */ >+ IC_VEX_L_W_XD, /* 11503 */ >+ IC_VEX_L_OPSIZE, /* 11504 */ >+ IC_VEX_L_OPSIZE, /* 11505 */ >+ IC_VEX_L_OPSIZE, /* 11506 */ >+ IC_VEX_L_OPSIZE, /* 11507 */ >+ IC_VEX_L_OPSIZE, /* 11508 */ >+ IC_VEX_L_OPSIZE, /* 11509 */ >+ IC_VEX_L_OPSIZE, /* 11510 */ >+ IC_VEX_L_OPSIZE, /* 11511 */ >+ IC_VEX_L_W_OPSIZE, /* 11512 */ >+ IC_VEX_L_W_OPSIZE, /* 11513 */ >+ IC_VEX_L_W_OPSIZE, /* 11514 */ >+ IC_VEX_L_W_OPSIZE, /* 11515 */ >+ IC_VEX_L_W_OPSIZE, /* 11516 */ >+ IC_VEX_L_W_OPSIZE, /* 11517 */ >+ IC_VEX_L_W_OPSIZE, /* 11518 */ >+ IC_VEX_L_W_OPSIZE, /* 11519 */ >+ IC_EVEX_L2_K_B, /* 11520 */ >+ IC_EVEX_L2_K_B, /* 11521 */ >+ IC_EVEX_L2_XS_K_B, /* 11522 */ >+ IC_EVEX_L2_XS_K_B, /* 11523 */ >+ IC_EVEX_L2_XD_K_B, /* 11524 */ >+ IC_EVEX_L2_XD_K_B, /* 11525 */ >+ IC_EVEX_L2_XD_K_B, /* 11526 */ >+ IC_EVEX_L2_XD_K_B, /* 11527 */ >+ IC_EVEX_L2_W_K_B, /* 11528 */ >+ IC_EVEX_L2_W_K_B, /* 11529 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11530 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11531 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11532 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11533 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11534 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11535 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11536 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11537 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11538 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11539 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11540 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11541 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11542 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11543 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11544 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11545 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11546 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11547 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11548 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11549 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11550 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11551 */ >+ IC_EVEX_L2_K_B, /* 11552 */ >+ IC_EVEX_L2_K_B, /* 11553 */ >+ IC_EVEX_L2_XS_K_B, /* 11554 */ >+ IC_EVEX_L2_XS_K_B, /* 11555 */ >+ IC_EVEX_L2_XD_K_B, /* 11556 */ >+ IC_EVEX_L2_XD_K_B, /* 11557 */ >+ IC_EVEX_L2_XD_K_B, /* 11558 */ >+ IC_EVEX_L2_XD_K_B, /* 11559 */ >+ IC_EVEX_L2_W_K_B, /* 11560 */ >+ IC_EVEX_L2_W_K_B, /* 11561 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11562 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11563 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11564 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11565 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11566 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11567 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11568 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11569 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11570 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11571 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11572 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11573 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11574 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11575 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11576 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11577 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11578 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11579 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11580 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11581 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11582 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11583 */ >+ IC_EVEX_L2_K_B, /* 11584 */ >+ IC_EVEX_L2_K_B, /* 11585 */ >+ IC_EVEX_L2_XS_K_B, /* 11586 */ >+ IC_EVEX_L2_XS_K_B, /* 11587 */ >+ IC_EVEX_L2_XD_K_B, /* 11588 */ >+ IC_EVEX_L2_XD_K_B, /* 11589 */ >+ IC_EVEX_L2_XD_K_B, /* 11590 */ >+ IC_EVEX_L2_XD_K_B, /* 11591 */ >+ IC_EVEX_L2_W_K_B, /* 11592 */ >+ IC_EVEX_L2_W_K_B, /* 11593 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11594 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11595 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11596 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11597 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11598 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11599 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11600 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11601 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11602 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11603 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11604 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11605 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11606 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11607 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11608 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11609 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11610 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11611 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11612 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11613 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11614 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11615 */ >+ IC_EVEX_L2_K_B, /* 11616 */ >+ IC_EVEX_L2_K_B, /* 11617 */ >+ IC_EVEX_L2_XS_K_B, /* 11618 */ >+ IC_EVEX_L2_XS_K_B, /* 11619 */ >+ IC_EVEX_L2_XD_K_B, /* 11620 */ >+ IC_EVEX_L2_XD_K_B, /* 11621 */ >+ IC_EVEX_L2_XD_K_B, /* 11622 */ >+ IC_EVEX_L2_XD_K_B, /* 11623 */ >+ IC_EVEX_L2_W_K_B, /* 11624 */ >+ IC_EVEX_L2_W_K_B, /* 11625 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11626 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11627 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11628 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11629 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11630 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11631 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11632 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11633 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11634 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11635 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11636 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11637 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11638 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11639 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11640 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11641 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11642 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11643 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11644 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11645 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11646 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11647 */ >+ IC_EVEX_L2_K_B, /* 11648 */ >+ IC_EVEX_L2_K_B, /* 11649 */ >+ IC_EVEX_L2_XS_K_B, /* 11650 */ >+ IC_EVEX_L2_XS_K_B, /* 11651 */ >+ IC_EVEX_L2_XD_K_B, /* 11652 */ >+ IC_EVEX_L2_XD_K_B, /* 11653 */ >+ IC_EVEX_L2_XD_K_B, /* 11654 */ >+ IC_EVEX_L2_XD_K_B, /* 11655 */ >+ IC_EVEX_L2_W_K_B, /* 11656 */ >+ IC_EVEX_L2_W_K_B, /* 11657 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11658 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11659 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11660 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11661 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11662 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11663 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11664 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11665 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11666 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11667 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11668 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11669 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11670 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11671 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11672 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11673 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11674 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11675 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11676 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11677 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11678 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11679 */ >+ IC_EVEX_L2_K_B, /* 11680 */ >+ IC_EVEX_L2_K_B, /* 11681 */ >+ IC_EVEX_L2_XS_K_B, /* 11682 */ >+ IC_EVEX_L2_XS_K_B, /* 11683 */ >+ IC_EVEX_L2_XD_K_B, /* 11684 */ >+ IC_EVEX_L2_XD_K_B, /* 11685 */ >+ IC_EVEX_L2_XD_K_B, /* 11686 */ >+ IC_EVEX_L2_XD_K_B, /* 11687 */ >+ IC_EVEX_L2_W_K_B, /* 11688 */ >+ IC_EVEX_L2_W_K_B, /* 11689 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11690 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11691 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11692 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11693 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11694 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11695 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11696 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11697 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11698 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11699 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11700 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11701 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11702 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11703 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11704 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11705 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11706 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11707 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11708 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11709 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11710 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11711 */ >+ IC_EVEX_L2_K_B, /* 11712 */ >+ IC_EVEX_L2_K_B, /* 11713 */ >+ IC_EVEX_L2_XS_K_B, /* 11714 */ >+ IC_EVEX_L2_XS_K_B, /* 11715 */ >+ IC_EVEX_L2_XD_K_B, /* 11716 */ >+ IC_EVEX_L2_XD_K_B, /* 11717 */ >+ IC_EVEX_L2_XD_K_B, /* 11718 */ >+ IC_EVEX_L2_XD_K_B, /* 11719 */ >+ IC_EVEX_L2_W_K_B, /* 11720 */ >+ IC_EVEX_L2_W_K_B, /* 11721 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11722 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11723 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11724 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11725 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11726 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11727 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11728 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11729 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11730 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11731 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11732 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11733 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11734 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11735 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11736 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11737 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11738 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11739 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11740 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11741 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11742 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11743 */ >+ IC_EVEX_L2_K_B, /* 11744 */ >+ IC_EVEX_L2_K_B, /* 11745 */ >+ IC_EVEX_L2_XS_K_B, /* 11746 */ >+ IC_EVEX_L2_XS_K_B, /* 11747 */ >+ IC_EVEX_L2_XD_K_B, /* 11748 */ >+ IC_EVEX_L2_XD_K_B, /* 11749 */ >+ IC_EVEX_L2_XD_K_B, /* 11750 */ >+ IC_EVEX_L2_XD_K_B, /* 11751 */ >+ IC_EVEX_L2_W_K_B, /* 11752 */ >+ IC_EVEX_L2_W_K_B, /* 11753 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11754 */ >+ IC_EVEX_L2_W_XS_K_B, /* 11755 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11756 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11757 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11758 */ >+ IC_EVEX_L2_W_XD_K_B, /* 11759 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11760 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11761 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11762 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11763 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11764 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11765 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11766 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 11767 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11768 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11769 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11770 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11771 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11772 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11773 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11774 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 11775 */ >+ IC, /* 11776 */ >+ IC_64BIT, /* 11777 */ >+ IC_XS, /* 11778 */ >+ IC_64BIT_XS, /* 11779 */ >+ IC_XD, /* 11780 */ >+ IC_64BIT_XD, /* 11781 */ >+ IC_XS, /* 11782 */ >+ IC_64BIT_XS, /* 11783 */ >+ IC, /* 11784 */ >+ IC_64BIT_REXW, /* 11785 */ >+ IC_XS, /* 11786 */ >+ IC_64BIT_REXW_XS, /* 11787 */ >+ IC_XD, /* 11788 */ >+ IC_64BIT_REXW_XD, /* 11789 */ >+ IC_XS, /* 11790 */ >+ IC_64BIT_REXW_XS, /* 11791 */ >+ IC_OPSIZE, /* 11792 */ >+ IC_64BIT_OPSIZE, /* 11793 */ >+ IC_XS_OPSIZE, /* 11794 */ >+ IC_64BIT_XS_OPSIZE, /* 11795 */ >+ IC_XD_OPSIZE, /* 11796 */ >+ IC_64BIT_XD_OPSIZE, /* 11797 */ >+ IC_XS_OPSIZE, /* 11798 */ >+ IC_64BIT_XD_OPSIZE, /* 11799 */ >+ IC_OPSIZE, /* 11800 */ >+ IC_64BIT_REXW_OPSIZE, /* 11801 */ >+ IC_XS_OPSIZE, /* 11802 */ >+ IC_64BIT_REXW_XS, /* 11803 */ >+ IC_XD_OPSIZE, /* 11804 */ >+ IC_64BIT_REXW_XD, /* 11805 */ >+ IC_XS_OPSIZE, /* 11806 */ >+ IC_64BIT_REXW_XS, /* 11807 */ >+ IC_ADSIZE, /* 11808 */ >+ IC_64BIT_ADSIZE, /* 11809 */ >+ IC_XS, /* 11810 */ >+ IC_64BIT_XS, /* 11811 */ >+ IC_XD, /* 11812 */ >+ IC_64BIT_XD, /* 11813 */ >+ IC_XS, /* 11814 */ >+ IC_64BIT_XS, /* 11815 */ >+ IC_ADSIZE, /* 11816 */ >+ IC_64BIT_ADSIZE, /* 11817 */ >+ IC_XS, /* 11818 */ >+ IC_64BIT_REXW_XS, /* 11819 */ >+ IC_XD, /* 11820 */ >+ IC_64BIT_REXW_XD, /* 11821 */ >+ IC_XS, /* 11822 */ >+ IC_64BIT_REXW_XS, /* 11823 */ >+ IC_OPSIZE, /* 11824 */ >+ IC_64BIT_OPSIZE, /* 11825 */ >+ IC_XS_OPSIZE, /* 11826 */ >+ IC_64BIT_XS_OPSIZE, /* 11827 */ >+ IC_XD_OPSIZE, /* 11828 */ >+ IC_64BIT_XD_OPSIZE, /* 11829 */ >+ IC_XS_OPSIZE, /* 11830 */ >+ IC_64BIT_XD_OPSIZE, /* 11831 */ >+ IC_OPSIZE, /* 11832 */ >+ IC_64BIT_REXW_OPSIZE, /* 11833 */ >+ IC_XS_OPSIZE, /* 11834 */ >+ IC_64BIT_REXW_XS, /* 11835 */ >+ IC_XD_OPSIZE, /* 11836 */ >+ IC_64BIT_REXW_XD, /* 11837 */ >+ IC_XS_OPSIZE, /* 11838 */ >+ IC_64BIT_REXW_XS, /* 11839 */ >+ IC_VEX, /* 11840 */ >+ IC_VEX, /* 11841 */ >+ IC_VEX_XS, /* 11842 */ >+ IC_VEX_XS, /* 11843 */ >+ IC_VEX_XD, /* 11844 */ >+ IC_VEX_XD, /* 11845 */ >+ IC_VEX_XD, /* 11846 */ >+ IC_VEX_XD, /* 11847 */ >+ IC_VEX_W, /* 11848 */ >+ IC_VEX_W, /* 11849 */ >+ IC_VEX_W_XS, /* 11850 */ >+ IC_VEX_W_XS, /* 11851 */ >+ IC_VEX_W_XD, /* 11852 */ >+ IC_VEX_W_XD, /* 11853 */ >+ IC_VEX_W_XD, /* 11854 */ >+ IC_VEX_W_XD, /* 11855 */ >+ IC_VEX_OPSIZE, /* 11856 */ >+ IC_VEX_OPSIZE, /* 11857 */ >+ IC_VEX_OPSIZE, /* 11858 */ >+ IC_VEX_OPSIZE, /* 11859 */ >+ IC_VEX_OPSIZE, /* 11860 */ >+ IC_VEX_OPSIZE, /* 11861 */ >+ IC_VEX_OPSIZE, /* 11862 */ >+ IC_VEX_OPSIZE, /* 11863 */ >+ IC_VEX_W_OPSIZE, /* 11864 */ >+ IC_VEX_W_OPSIZE, /* 11865 */ >+ IC_VEX_W_OPSIZE, /* 11866 */ >+ IC_VEX_W_OPSIZE, /* 11867 */ >+ IC_VEX_W_OPSIZE, /* 11868 */ >+ IC_VEX_W_OPSIZE, /* 11869 */ >+ IC_VEX_W_OPSIZE, /* 11870 */ >+ IC_VEX_W_OPSIZE, /* 11871 */ >+ IC_VEX, /* 11872 */ >+ IC_VEX, /* 11873 */ >+ IC_VEX_XS, /* 11874 */ >+ IC_VEX_XS, /* 11875 */ >+ IC_VEX_XD, /* 11876 */ >+ IC_VEX_XD, /* 11877 */ >+ IC_VEX_XD, /* 11878 */ >+ IC_VEX_XD, /* 11879 */ >+ IC_VEX_W, /* 11880 */ >+ IC_VEX_W, /* 11881 */ >+ IC_VEX_W_XS, /* 11882 */ >+ IC_VEX_W_XS, /* 11883 */ >+ IC_VEX_W_XD, /* 11884 */ >+ IC_VEX_W_XD, /* 11885 */ >+ IC_VEX_W_XD, /* 11886 */ >+ IC_VEX_W_XD, /* 11887 */ >+ IC_VEX_OPSIZE, /* 11888 */ >+ IC_VEX_OPSIZE, /* 11889 */ >+ IC_VEX_OPSIZE, /* 11890 */ >+ IC_VEX_OPSIZE, /* 11891 */ >+ IC_VEX_OPSIZE, /* 11892 */ >+ IC_VEX_OPSIZE, /* 11893 */ >+ IC_VEX_OPSIZE, /* 11894 */ >+ IC_VEX_OPSIZE, /* 11895 */ >+ IC_VEX_W_OPSIZE, /* 11896 */ >+ IC_VEX_W_OPSIZE, /* 11897 */ >+ IC_VEX_W_OPSIZE, /* 11898 */ >+ IC_VEX_W_OPSIZE, /* 11899 */ >+ IC_VEX_W_OPSIZE, /* 11900 */ >+ IC_VEX_W_OPSIZE, /* 11901 */ >+ IC_VEX_W_OPSIZE, /* 11902 */ >+ IC_VEX_W_OPSIZE, /* 11903 */ >+ IC_VEX_L, /* 11904 */ >+ IC_VEX_L, /* 11905 */ >+ IC_VEX_L_XS, /* 11906 */ >+ IC_VEX_L_XS, /* 11907 */ >+ IC_VEX_L_XD, /* 11908 */ >+ IC_VEX_L_XD, /* 11909 */ >+ IC_VEX_L_XD, /* 11910 */ >+ IC_VEX_L_XD, /* 11911 */ >+ IC_VEX_L_W, /* 11912 */ >+ IC_VEX_L_W, /* 11913 */ >+ IC_VEX_L_W_XS, /* 11914 */ >+ IC_VEX_L_W_XS, /* 11915 */ >+ IC_VEX_L_W_XD, /* 11916 */ >+ IC_VEX_L_W_XD, /* 11917 */ >+ IC_VEX_L_W_XD, /* 11918 */ >+ IC_VEX_L_W_XD, /* 11919 */ >+ IC_VEX_L_OPSIZE, /* 11920 */ >+ IC_VEX_L_OPSIZE, /* 11921 */ >+ IC_VEX_L_OPSIZE, /* 11922 */ >+ IC_VEX_L_OPSIZE, /* 11923 */ >+ IC_VEX_L_OPSIZE, /* 11924 */ >+ IC_VEX_L_OPSIZE, /* 11925 */ >+ IC_VEX_L_OPSIZE, /* 11926 */ >+ IC_VEX_L_OPSIZE, /* 11927 */ >+ IC_VEX_L_W_OPSIZE, /* 11928 */ >+ IC_VEX_L_W_OPSIZE, /* 11929 */ >+ IC_VEX_L_W_OPSIZE, /* 11930 */ >+ IC_VEX_L_W_OPSIZE, /* 11931 */ >+ IC_VEX_L_W_OPSIZE, /* 11932 */ >+ IC_VEX_L_W_OPSIZE, /* 11933 */ >+ IC_VEX_L_W_OPSIZE, /* 11934 */ >+ IC_VEX_L_W_OPSIZE, /* 11935 */ >+ IC_VEX_L, /* 11936 */ >+ IC_VEX_L, /* 11937 */ >+ IC_VEX_L_XS, /* 11938 */ >+ IC_VEX_L_XS, /* 11939 */ >+ IC_VEX_L_XD, /* 11940 */ >+ IC_VEX_L_XD, /* 11941 */ >+ IC_VEX_L_XD, /* 11942 */ >+ IC_VEX_L_XD, /* 11943 */ >+ IC_VEX_L_W, /* 11944 */ >+ IC_VEX_L_W, /* 11945 */ >+ IC_VEX_L_W_XS, /* 11946 */ >+ IC_VEX_L_W_XS, /* 11947 */ >+ IC_VEX_L_W_XD, /* 11948 */ >+ IC_VEX_L_W_XD, /* 11949 */ >+ IC_VEX_L_W_XD, /* 11950 */ >+ IC_VEX_L_W_XD, /* 11951 */ >+ IC_VEX_L_OPSIZE, /* 11952 */ >+ IC_VEX_L_OPSIZE, /* 11953 */ >+ IC_VEX_L_OPSIZE, /* 11954 */ >+ IC_VEX_L_OPSIZE, /* 11955 */ >+ IC_VEX_L_OPSIZE, /* 11956 */ >+ IC_VEX_L_OPSIZE, /* 11957 */ >+ IC_VEX_L_OPSIZE, /* 11958 */ >+ IC_VEX_L_OPSIZE, /* 11959 */ >+ IC_VEX_L_W_OPSIZE, /* 11960 */ >+ IC_VEX_L_W_OPSIZE, /* 11961 */ >+ IC_VEX_L_W_OPSIZE, /* 11962 */ >+ IC_VEX_L_W_OPSIZE, /* 11963 */ >+ IC_VEX_L_W_OPSIZE, /* 11964 */ >+ IC_VEX_L_W_OPSIZE, /* 11965 */ >+ IC_VEX_L_W_OPSIZE, /* 11966 */ >+ IC_VEX_L_W_OPSIZE, /* 11967 */ >+ IC_VEX_L, /* 11968 */ >+ IC_VEX_L, /* 11969 */ >+ IC_VEX_L_XS, /* 11970 */ >+ IC_VEX_L_XS, /* 11971 */ >+ IC_VEX_L_XD, /* 11972 */ >+ IC_VEX_L_XD, /* 11973 */ >+ IC_VEX_L_XD, /* 11974 */ >+ IC_VEX_L_XD, /* 11975 */ >+ IC_VEX_L_W, /* 11976 */ >+ IC_VEX_L_W, /* 11977 */ >+ IC_VEX_L_W_XS, /* 11978 */ >+ IC_VEX_L_W_XS, /* 11979 */ >+ IC_VEX_L_W_XD, /* 11980 */ >+ IC_VEX_L_W_XD, /* 11981 */ >+ IC_VEX_L_W_XD, /* 11982 */ >+ IC_VEX_L_W_XD, /* 11983 */ >+ IC_VEX_L_OPSIZE, /* 11984 */ >+ IC_VEX_L_OPSIZE, /* 11985 */ >+ IC_VEX_L_OPSIZE, /* 11986 */ >+ IC_VEX_L_OPSIZE, /* 11987 */ >+ IC_VEX_L_OPSIZE, /* 11988 */ >+ IC_VEX_L_OPSIZE, /* 11989 */ >+ IC_VEX_L_OPSIZE, /* 11990 */ >+ IC_VEX_L_OPSIZE, /* 11991 */ >+ IC_VEX_L_W_OPSIZE, /* 11992 */ >+ IC_VEX_L_W_OPSIZE, /* 11993 */ >+ IC_VEX_L_W_OPSIZE, /* 11994 */ >+ IC_VEX_L_W_OPSIZE, /* 11995 */ >+ IC_VEX_L_W_OPSIZE, /* 11996 */ >+ IC_VEX_L_W_OPSIZE, /* 11997 */ >+ IC_VEX_L_W_OPSIZE, /* 11998 */ >+ IC_VEX_L_W_OPSIZE, /* 11999 */ >+ IC_VEX_L, /* 12000 */ >+ IC_VEX_L, /* 12001 */ >+ IC_VEX_L_XS, /* 12002 */ >+ IC_VEX_L_XS, /* 12003 */ >+ IC_VEX_L_XD, /* 12004 */ >+ IC_VEX_L_XD, /* 12005 */ >+ IC_VEX_L_XD, /* 12006 */ >+ IC_VEX_L_XD, /* 12007 */ >+ IC_VEX_L_W, /* 12008 */ >+ IC_VEX_L_W, /* 12009 */ >+ IC_VEX_L_W_XS, /* 12010 */ >+ IC_VEX_L_W_XS, /* 12011 */ >+ IC_VEX_L_W_XD, /* 12012 */ >+ IC_VEX_L_W_XD, /* 12013 */ >+ IC_VEX_L_W_XD, /* 12014 */ >+ IC_VEX_L_W_XD, /* 12015 */ >+ IC_VEX_L_OPSIZE, /* 12016 */ >+ IC_VEX_L_OPSIZE, /* 12017 */ >+ IC_VEX_L_OPSIZE, /* 12018 */ >+ IC_VEX_L_OPSIZE, /* 12019 */ >+ IC_VEX_L_OPSIZE, /* 12020 */ >+ IC_VEX_L_OPSIZE, /* 12021 */ >+ IC_VEX_L_OPSIZE, /* 12022 */ >+ IC_VEX_L_OPSIZE, /* 12023 */ >+ IC_VEX_L_W_OPSIZE, /* 12024 */ >+ IC_VEX_L_W_OPSIZE, /* 12025 */ >+ IC_VEX_L_W_OPSIZE, /* 12026 */ >+ IC_VEX_L_W_OPSIZE, /* 12027 */ >+ IC_VEX_L_W_OPSIZE, /* 12028 */ >+ IC_VEX_L_W_OPSIZE, /* 12029 */ >+ IC_VEX_L_W_OPSIZE, /* 12030 */ >+ IC_VEX_L_W_OPSIZE, /* 12031 */ >+ IC_EVEX_L2_K_B, /* 12032 */ >+ IC_EVEX_L2_K_B, /* 12033 */ >+ IC_EVEX_L2_XS_K_B, /* 12034 */ >+ IC_EVEX_L2_XS_K_B, /* 12035 */ >+ IC_EVEX_L2_XD_K_B, /* 12036 */ >+ IC_EVEX_L2_XD_K_B, /* 12037 */ >+ IC_EVEX_L2_XD_K_B, /* 12038 */ >+ IC_EVEX_L2_XD_K_B, /* 12039 */ >+ IC_EVEX_L2_W_K_B, /* 12040 */ >+ IC_EVEX_L2_W_K_B, /* 12041 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12042 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12043 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12044 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12045 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12046 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12047 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12048 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12049 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12050 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12051 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12052 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12053 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12054 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12055 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12056 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12057 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12058 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12059 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12060 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12061 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12062 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12063 */ >+ IC_EVEX_L2_K_B, /* 12064 */ >+ IC_EVEX_L2_K_B, /* 12065 */ >+ IC_EVEX_L2_XS_K_B, /* 12066 */ >+ IC_EVEX_L2_XS_K_B, /* 12067 */ >+ IC_EVEX_L2_XD_K_B, /* 12068 */ >+ IC_EVEX_L2_XD_K_B, /* 12069 */ >+ IC_EVEX_L2_XD_K_B, /* 12070 */ >+ IC_EVEX_L2_XD_K_B, /* 12071 */ >+ IC_EVEX_L2_W_K_B, /* 12072 */ >+ IC_EVEX_L2_W_K_B, /* 12073 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12074 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12075 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12076 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12077 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12078 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12079 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12080 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12081 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12082 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12083 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12084 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12085 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12086 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12087 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12088 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12089 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12090 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12091 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12092 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12093 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12094 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12095 */ >+ IC_EVEX_L2_K_B, /* 12096 */ >+ IC_EVEX_L2_K_B, /* 12097 */ >+ IC_EVEX_L2_XS_K_B, /* 12098 */ >+ IC_EVEX_L2_XS_K_B, /* 12099 */ >+ IC_EVEX_L2_XD_K_B, /* 12100 */ >+ IC_EVEX_L2_XD_K_B, /* 12101 */ >+ IC_EVEX_L2_XD_K_B, /* 12102 */ >+ IC_EVEX_L2_XD_K_B, /* 12103 */ >+ IC_EVEX_L2_W_K_B, /* 12104 */ >+ IC_EVEX_L2_W_K_B, /* 12105 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12106 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12107 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12108 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12109 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12110 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12111 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12112 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12113 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12114 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12115 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12116 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12117 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12118 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12119 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12120 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12121 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12122 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12123 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12124 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12125 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12126 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12127 */ >+ IC_EVEX_L2_K_B, /* 12128 */ >+ IC_EVEX_L2_K_B, /* 12129 */ >+ IC_EVEX_L2_XS_K_B, /* 12130 */ >+ IC_EVEX_L2_XS_K_B, /* 12131 */ >+ IC_EVEX_L2_XD_K_B, /* 12132 */ >+ IC_EVEX_L2_XD_K_B, /* 12133 */ >+ IC_EVEX_L2_XD_K_B, /* 12134 */ >+ IC_EVEX_L2_XD_K_B, /* 12135 */ >+ IC_EVEX_L2_W_K_B, /* 12136 */ >+ IC_EVEX_L2_W_K_B, /* 12137 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12138 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12139 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12140 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12141 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12142 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12143 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12144 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12145 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12146 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12147 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12148 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12149 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12150 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12151 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12152 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12153 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12154 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12155 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12156 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12157 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12158 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12159 */ >+ IC_EVEX_L2_K_B, /* 12160 */ >+ IC_EVEX_L2_K_B, /* 12161 */ >+ IC_EVEX_L2_XS_K_B, /* 12162 */ >+ IC_EVEX_L2_XS_K_B, /* 12163 */ >+ IC_EVEX_L2_XD_K_B, /* 12164 */ >+ IC_EVEX_L2_XD_K_B, /* 12165 */ >+ IC_EVEX_L2_XD_K_B, /* 12166 */ >+ IC_EVEX_L2_XD_K_B, /* 12167 */ >+ IC_EVEX_L2_W_K_B, /* 12168 */ >+ IC_EVEX_L2_W_K_B, /* 12169 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12170 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12171 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12172 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12173 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12174 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12175 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12176 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12177 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12178 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12179 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12180 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12181 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12182 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12183 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12184 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12185 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12186 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12187 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12188 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12189 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12190 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12191 */ >+ IC_EVEX_L2_K_B, /* 12192 */ >+ IC_EVEX_L2_K_B, /* 12193 */ >+ IC_EVEX_L2_XS_K_B, /* 12194 */ >+ IC_EVEX_L2_XS_K_B, /* 12195 */ >+ IC_EVEX_L2_XD_K_B, /* 12196 */ >+ IC_EVEX_L2_XD_K_B, /* 12197 */ >+ IC_EVEX_L2_XD_K_B, /* 12198 */ >+ IC_EVEX_L2_XD_K_B, /* 12199 */ >+ IC_EVEX_L2_W_K_B, /* 12200 */ >+ IC_EVEX_L2_W_K_B, /* 12201 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12202 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12203 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12204 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12205 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12206 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12207 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12208 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12209 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12210 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12211 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12212 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12213 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12214 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12215 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12216 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12217 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12218 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12219 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12220 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12221 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12222 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12223 */ >+ IC_EVEX_L2_K_B, /* 12224 */ >+ IC_EVEX_L2_K_B, /* 12225 */ >+ IC_EVEX_L2_XS_K_B, /* 12226 */ >+ IC_EVEX_L2_XS_K_B, /* 12227 */ >+ IC_EVEX_L2_XD_K_B, /* 12228 */ >+ IC_EVEX_L2_XD_K_B, /* 12229 */ >+ IC_EVEX_L2_XD_K_B, /* 12230 */ >+ IC_EVEX_L2_XD_K_B, /* 12231 */ >+ IC_EVEX_L2_W_K_B, /* 12232 */ >+ IC_EVEX_L2_W_K_B, /* 12233 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12234 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12235 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12236 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12237 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12238 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12239 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12240 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12241 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12242 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12243 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12244 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12245 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12246 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12247 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12248 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12249 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12250 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12251 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12252 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12253 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12254 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12255 */ >+ IC_EVEX_L2_K_B, /* 12256 */ >+ IC_EVEX_L2_K_B, /* 12257 */ >+ IC_EVEX_L2_XS_K_B, /* 12258 */ >+ IC_EVEX_L2_XS_K_B, /* 12259 */ >+ IC_EVEX_L2_XD_K_B, /* 12260 */ >+ IC_EVEX_L2_XD_K_B, /* 12261 */ >+ IC_EVEX_L2_XD_K_B, /* 12262 */ >+ IC_EVEX_L2_XD_K_B, /* 12263 */ >+ IC_EVEX_L2_W_K_B, /* 12264 */ >+ IC_EVEX_L2_W_K_B, /* 12265 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12266 */ >+ IC_EVEX_L2_W_XS_K_B, /* 12267 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12268 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12269 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12270 */ >+ IC_EVEX_L2_W_XD_K_B, /* 12271 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12272 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12273 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12274 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12275 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12276 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12277 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12278 */ >+ IC_EVEX_L2_OPSIZE_K_B, /* 12279 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12280 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12281 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12282 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12283 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12284 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12285 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12286 */ >+ IC_EVEX_L2_W_OPSIZE_K_B, /* 12287 */ >+ IC, /* 12288 */ >+ IC_64BIT, /* 12289 */ >+ IC_XS, /* 12290 */ >+ IC_64BIT_XS, /* 12291 */ >+ IC_XD, /* 12292 */ >+ IC_64BIT_XD, /* 12293 */ >+ IC_XS, /* 12294 */ >+ IC_64BIT_XS, /* 12295 */ >+ IC, /* 12296 */ >+ IC_64BIT_REXW, /* 12297 */ >+ IC_XS, /* 12298 */ >+ IC_64BIT_REXW_XS, /* 12299 */ >+ IC_XD, /* 12300 */ >+ IC_64BIT_REXW_XD, /* 12301 */ >+ IC_XS, /* 12302 */ >+ IC_64BIT_REXW_XS, /* 12303 */ >+ IC_OPSIZE, /* 12304 */ >+ IC_64BIT_OPSIZE, /* 12305 */ >+ IC_XS_OPSIZE, /* 12306 */ >+ IC_64BIT_XS_OPSIZE, /* 12307 */ >+ IC_XD_OPSIZE, /* 12308 */ >+ IC_64BIT_XD_OPSIZE, /* 12309 */ >+ IC_XS_OPSIZE, /* 12310 */ >+ IC_64BIT_XD_OPSIZE, /* 12311 */ >+ IC_OPSIZE, /* 12312 */ >+ IC_64BIT_REXW_OPSIZE, /* 12313 */ >+ IC_XS_OPSIZE, /* 12314 */ >+ IC_64BIT_REXW_XS, /* 12315 */ >+ IC_XD_OPSIZE, /* 12316 */ >+ IC_64BIT_REXW_XD, /* 12317 */ >+ IC_XS_OPSIZE, /* 12318 */ >+ IC_64BIT_REXW_XS, /* 12319 */ >+ IC_ADSIZE, /* 12320 */ >+ IC_64BIT_ADSIZE, /* 12321 */ >+ IC_XS, /* 12322 */ >+ IC_64BIT_XS, /* 12323 */ >+ IC_XD, /* 12324 */ >+ IC_64BIT_XD, /* 12325 */ >+ IC_XS, /* 12326 */ >+ IC_64BIT_XS, /* 12327 */ >+ IC_ADSIZE, /* 12328 */ >+ IC_64BIT_ADSIZE, /* 12329 */ >+ IC_XS, /* 12330 */ >+ IC_64BIT_REXW_XS, /* 12331 */ >+ IC_XD, /* 12332 */ >+ IC_64BIT_REXW_XD, /* 12333 */ >+ IC_XS, /* 12334 */ >+ IC_64BIT_REXW_XS, /* 12335 */ >+ IC_OPSIZE, /* 12336 */ >+ IC_64BIT_OPSIZE, /* 12337 */ >+ IC_XS_OPSIZE, /* 12338 */ >+ IC_64BIT_XS_OPSIZE, /* 12339 */ >+ IC_XD_OPSIZE, /* 12340 */ >+ IC_64BIT_XD_OPSIZE, /* 12341 */ >+ IC_XS_OPSIZE, /* 12342 */ >+ IC_64BIT_XD_OPSIZE, /* 12343 */ >+ IC_OPSIZE, /* 12344 */ >+ IC_64BIT_REXW_OPSIZE, /* 12345 */ >+ IC_XS_OPSIZE, /* 12346 */ >+ IC_64BIT_REXW_XS, /* 12347 */ >+ IC_XD_OPSIZE, /* 12348 */ >+ IC_64BIT_REXW_XD, /* 12349 */ >+ IC_XS_OPSIZE, /* 12350 */ >+ IC_64BIT_REXW_XS, /* 12351 */ >+ IC_VEX, /* 12352 */ >+ IC_VEX, /* 12353 */ >+ IC_VEX_XS, /* 12354 */ >+ IC_VEX_XS, /* 12355 */ >+ IC_VEX_XD, /* 12356 */ >+ IC_VEX_XD, /* 12357 */ >+ IC_VEX_XD, /* 12358 */ >+ IC_VEX_XD, /* 12359 */ >+ IC_VEX_W, /* 12360 */ >+ IC_VEX_W, /* 12361 */ >+ IC_VEX_W_XS, /* 12362 */ >+ IC_VEX_W_XS, /* 12363 */ >+ IC_VEX_W_XD, /* 12364 */ >+ IC_VEX_W_XD, /* 12365 */ >+ IC_VEX_W_XD, /* 12366 */ >+ IC_VEX_W_XD, /* 12367 */ >+ IC_VEX_OPSIZE, /* 12368 */ >+ IC_VEX_OPSIZE, /* 12369 */ >+ IC_VEX_OPSIZE, /* 12370 */ >+ IC_VEX_OPSIZE, /* 12371 */ >+ IC_VEX_OPSIZE, /* 12372 */ >+ IC_VEX_OPSIZE, /* 12373 */ >+ IC_VEX_OPSIZE, /* 12374 */ >+ IC_VEX_OPSIZE, /* 12375 */ >+ IC_VEX_W_OPSIZE, /* 12376 */ >+ IC_VEX_W_OPSIZE, /* 12377 */ >+ IC_VEX_W_OPSIZE, /* 12378 */ >+ IC_VEX_W_OPSIZE, /* 12379 */ >+ IC_VEX_W_OPSIZE, /* 12380 */ >+ IC_VEX_W_OPSIZE, /* 12381 */ >+ IC_VEX_W_OPSIZE, /* 12382 */ >+ IC_VEX_W_OPSIZE, /* 12383 */ >+ IC_VEX, /* 12384 */ >+ IC_VEX, /* 12385 */ >+ IC_VEX_XS, /* 12386 */ >+ IC_VEX_XS, /* 12387 */ >+ IC_VEX_XD, /* 12388 */ >+ IC_VEX_XD, /* 12389 */ >+ IC_VEX_XD, /* 12390 */ >+ IC_VEX_XD, /* 12391 */ >+ IC_VEX_W, /* 12392 */ >+ IC_VEX_W, /* 12393 */ >+ IC_VEX_W_XS, /* 12394 */ >+ IC_VEX_W_XS, /* 12395 */ >+ IC_VEX_W_XD, /* 12396 */ >+ IC_VEX_W_XD, /* 12397 */ >+ IC_VEX_W_XD, /* 12398 */ >+ IC_VEX_W_XD, /* 12399 */ >+ IC_VEX_OPSIZE, /* 12400 */ >+ IC_VEX_OPSIZE, /* 12401 */ >+ IC_VEX_OPSIZE, /* 12402 */ >+ IC_VEX_OPSIZE, /* 12403 */ >+ IC_VEX_OPSIZE, /* 12404 */ >+ IC_VEX_OPSIZE, /* 12405 */ >+ IC_VEX_OPSIZE, /* 12406 */ >+ IC_VEX_OPSIZE, /* 12407 */ >+ IC_VEX_W_OPSIZE, /* 12408 */ >+ IC_VEX_W_OPSIZE, /* 12409 */ >+ IC_VEX_W_OPSIZE, /* 12410 */ >+ IC_VEX_W_OPSIZE, /* 12411 */ >+ IC_VEX_W_OPSIZE, /* 12412 */ >+ IC_VEX_W_OPSIZE, /* 12413 */ >+ IC_VEX_W_OPSIZE, /* 12414 */ >+ IC_VEX_W_OPSIZE, /* 12415 */ >+ IC_VEX_L, /* 12416 */ >+ IC_VEX_L, /* 12417 */ >+ IC_VEX_L_XS, /* 12418 */ >+ IC_VEX_L_XS, /* 12419 */ >+ IC_VEX_L_XD, /* 12420 */ >+ IC_VEX_L_XD, /* 12421 */ >+ IC_VEX_L_XD, /* 12422 */ >+ IC_VEX_L_XD, /* 12423 */ >+ IC_VEX_L_W, /* 12424 */ >+ IC_VEX_L_W, /* 12425 */ >+ IC_VEX_L_W_XS, /* 12426 */ >+ IC_VEX_L_W_XS, /* 12427 */ >+ IC_VEX_L_W_XD, /* 12428 */ >+ IC_VEX_L_W_XD, /* 12429 */ >+ IC_VEX_L_W_XD, /* 12430 */ >+ IC_VEX_L_W_XD, /* 12431 */ >+ IC_VEX_L_OPSIZE, /* 12432 */ >+ IC_VEX_L_OPSIZE, /* 12433 */ >+ IC_VEX_L_OPSIZE, /* 12434 */ >+ IC_VEX_L_OPSIZE, /* 12435 */ >+ IC_VEX_L_OPSIZE, /* 12436 */ >+ IC_VEX_L_OPSIZE, /* 12437 */ >+ IC_VEX_L_OPSIZE, /* 12438 */ >+ IC_VEX_L_OPSIZE, /* 12439 */ >+ IC_VEX_L_W_OPSIZE, /* 12440 */ >+ IC_VEX_L_W_OPSIZE, /* 12441 */ >+ IC_VEX_L_W_OPSIZE, /* 12442 */ >+ IC_VEX_L_W_OPSIZE, /* 12443 */ >+ IC_VEX_L_W_OPSIZE, /* 12444 */ >+ IC_VEX_L_W_OPSIZE, /* 12445 */ >+ IC_VEX_L_W_OPSIZE, /* 12446 */ >+ IC_VEX_L_W_OPSIZE, /* 12447 */ >+ IC_VEX_L, /* 12448 */ >+ IC_VEX_L, /* 12449 */ >+ IC_VEX_L_XS, /* 12450 */ >+ IC_VEX_L_XS, /* 12451 */ >+ IC_VEX_L_XD, /* 12452 */ >+ IC_VEX_L_XD, /* 12453 */ >+ IC_VEX_L_XD, /* 12454 */ >+ IC_VEX_L_XD, /* 12455 */ >+ IC_VEX_L_W, /* 12456 */ >+ IC_VEX_L_W, /* 12457 */ >+ IC_VEX_L_W_XS, /* 12458 */ >+ IC_VEX_L_W_XS, /* 12459 */ >+ IC_VEX_L_W_XD, /* 12460 */ >+ IC_VEX_L_W_XD, /* 12461 */ >+ IC_VEX_L_W_XD, /* 12462 */ >+ IC_VEX_L_W_XD, /* 12463 */ >+ IC_VEX_L_OPSIZE, /* 12464 */ >+ IC_VEX_L_OPSIZE, /* 12465 */ >+ IC_VEX_L_OPSIZE, /* 12466 */ >+ IC_VEX_L_OPSIZE, /* 12467 */ >+ IC_VEX_L_OPSIZE, /* 12468 */ >+ IC_VEX_L_OPSIZE, /* 12469 */ >+ IC_VEX_L_OPSIZE, /* 12470 */ >+ IC_VEX_L_OPSIZE, /* 12471 */ >+ IC_VEX_L_W_OPSIZE, /* 12472 */ >+ IC_VEX_L_W_OPSIZE, /* 12473 */ >+ IC_VEX_L_W_OPSIZE, /* 12474 */ >+ IC_VEX_L_W_OPSIZE, /* 12475 */ >+ IC_VEX_L_W_OPSIZE, /* 12476 */ >+ IC_VEX_L_W_OPSIZE, /* 12477 */ >+ IC_VEX_L_W_OPSIZE, /* 12478 */ >+ IC_VEX_L_W_OPSIZE, /* 12479 */ >+ IC_VEX_L, /* 12480 */ >+ IC_VEX_L, /* 12481 */ >+ IC_VEX_L_XS, /* 12482 */ >+ IC_VEX_L_XS, /* 12483 */ >+ IC_VEX_L_XD, /* 12484 */ >+ IC_VEX_L_XD, /* 12485 */ >+ IC_VEX_L_XD, /* 12486 */ >+ IC_VEX_L_XD, /* 12487 */ >+ IC_VEX_L_W, /* 12488 */ >+ IC_VEX_L_W, /* 12489 */ >+ IC_VEX_L_W_XS, /* 12490 */ >+ IC_VEX_L_W_XS, /* 12491 */ >+ IC_VEX_L_W_XD, /* 12492 */ >+ IC_VEX_L_W_XD, /* 12493 */ >+ IC_VEX_L_W_XD, /* 12494 */ >+ IC_VEX_L_W_XD, /* 12495 */ >+ IC_VEX_L_OPSIZE, /* 12496 */ >+ IC_VEX_L_OPSIZE, /* 12497 */ >+ IC_VEX_L_OPSIZE, /* 12498 */ >+ IC_VEX_L_OPSIZE, /* 12499 */ >+ IC_VEX_L_OPSIZE, /* 12500 */ >+ IC_VEX_L_OPSIZE, /* 12501 */ >+ IC_VEX_L_OPSIZE, /* 12502 */ >+ IC_VEX_L_OPSIZE, /* 12503 */ >+ IC_VEX_L_W_OPSIZE, /* 12504 */ >+ IC_VEX_L_W_OPSIZE, /* 12505 */ >+ IC_VEX_L_W_OPSIZE, /* 12506 */ >+ IC_VEX_L_W_OPSIZE, /* 12507 */ >+ IC_VEX_L_W_OPSIZE, /* 12508 */ >+ IC_VEX_L_W_OPSIZE, /* 12509 */ >+ IC_VEX_L_W_OPSIZE, /* 12510 */ >+ IC_VEX_L_W_OPSIZE, /* 12511 */ >+ IC_VEX_L, /* 12512 */ >+ IC_VEX_L, /* 12513 */ >+ IC_VEX_L_XS, /* 12514 */ >+ IC_VEX_L_XS, /* 12515 */ >+ IC_VEX_L_XD, /* 12516 */ >+ IC_VEX_L_XD, /* 12517 */ >+ IC_VEX_L_XD, /* 12518 */ >+ IC_VEX_L_XD, /* 12519 */ >+ IC_VEX_L_W, /* 12520 */ >+ IC_VEX_L_W, /* 12521 */ >+ IC_VEX_L_W_XS, /* 12522 */ >+ IC_VEX_L_W_XS, /* 12523 */ >+ IC_VEX_L_W_XD, /* 12524 */ >+ IC_VEX_L_W_XD, /* 12525 */ >+ IC_VEX_L_W_XD, /* 12526 */ >+ IC_VEX_L_W_XD, /* 12527 */ >+ IC_VEX_L_OPSIZE, /* 12528 */ >+ IC_VEX_L_OPSIZE, /* 12529 */ >+ IC_VEX_L_OPSIZE, /* 12530 */ >+ IC_VEX_L_OPSIZE, /* 12531 */ >+ IC_VEX_L_OPSIZE, /* 12532 */ >+ IC_VEX_L_OPSIZE, /* 12533 */ >+ IC_VEX_L_OPSIZE, /* 12534 */ >+ IC_VEX_L_OPSIZE, /* 12535 */ >+ IC_VEX_L_W_OPSIZE, /* 12536 */ >+ IC_VEX_L_W_OPSIZE, /* 12537 */ >+ IC_VEX_L_W_OPSIZE, /* 12538 */ >+ IC_VEX_L_W_OPSIZE, /* 12539 */ >+ IC_VEX_L_W_OPSIZE, /* 12540 */ >+ IC_VEX_L_W_OPSIZE, /* 12541 */ >+ IC_VEX_L_W_OPSIZE, /* 12542 */ >+ IC_VEX_L_W_OPSIZE, /* 12543 */ >+ IC_EVEX_KZ_B, /* 12544 */ >+ IC_EVEX_KZ_B, /* 12545 */ >+ IC_EVEX_XS_KZ_B, /* 12546 */ >+ IC_EVEX_XS_KZ_B, /* 12547 */ >+ IC_EVEX_XD_KZ_B, /* 12548 */ >+ IC_EVEX_XD_KZ_B, /* 12549 */ >+ IC_EVEX_XD_KZ_B, /* 12550 */ >+ IC_EVEX_XD_KZ_B, /* 12551 */ >+ IC_EVEX_W_KZ_B, /* 12552 */ >+ IC_EVEX_W_KZ_B, /* 12553 */ >+ IC_EVEX_W_XS_KZ_B, /* 12554 */ >+ IC_EVEX_W_XS_KZ_B, /* 12555 */ >+ IC_EVEX_W_XD_KZ_B, /* 12556 */ >+ IC_EVEX_W_XD_KZ_B, /* 12557 */ >+ IC_EVEX_W_XD_KZ_B, /* 12558 */ >+ IC_EVEX_W_XD_KZ_B, /* 12559 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12560 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12561 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12562 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12563 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12564 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12565 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12566 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12567 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12568 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12569 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12570 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12571 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12572 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12573 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12574 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12575 */ >+ IC_EVEX_KZ_B, /* 12576 */ >+ IC_EVEX_KZ_B, /* 12577 */ >+ IC_EVEX_XS_KZ_B, /* 12578 */ >+ IC_EVEX_XS_KZ_B, /* 12579 */ >+ IC_EVEX_XD_KZ_B, /* 12580 */ >+ IC_EVEX_XD_KZ_B, /* 12581 */ >+ IC_EVEX_XD_KZ_B, /* 12582 */ >+ IC_EVEX_XD_KZ_B, /* 12583 */ >+ IC_EVEX_W_KZ_B, /* 12584 */ >+ IC_EVEX_W_KZ_B, /* 12585 */ >+ IC_EVEX_W_XS_KZ_B, /* 12586 */ >+ IC_EVEX_W_XS_KZ_B, /* 12587 */ >+ IC_EVEX_W_XD_KZ_B, /* 12588 */ >+ IC_EVEX_W_XD_KZ_B, /* 12589 */ >+ IC_EVEX_W_XD_KZ_B, /* 12590 */ >+ IC_EVEX_W_XD_KZ_B, /* 12591 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12592 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12593 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12594 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12595 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12596 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12597 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12598 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12599 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12600 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12601 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12602 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12603 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12604 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12605 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12606 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12607 */ >+ IC_EVEX_KZ_B, /* 12608 */ >+ IC_EVEX_KZ_B, /* 12609 */ >+ IC_EVEX_XS_KZ_B, /* 12610 */ >+ IC_EVEX_XS_KZ_B, /* 12611 */ >+ IC_EVEX_XD_KZ_B, /* 12612 */ >+ IC_EVEX_XD_KZ_B, /* 12613 */ >+ IC_EVEX_XD_KZ_B, /* 12614 */ >+ IC_EVEX_XD_KZ_B, /* 12615 */ >+ IC_EVEX_W_KZ_B, /* 12616 */ >+ IC_EVEX_W_KZ_B, /* 12617 */ >+ IC_EVEX_W_XS_KZ_B, /* 12618 */ >+ IC_EVEX_W_XS_KZ_B, /* 12619 */ >+ IC_EVEX_W_XD_KZ_B, /* 12620 */ >+ IC_EVEX_W_XD_KZ_B, /* 12621 */ >+ IC_EVEX_W_XD_KZ_B, /* 12622 */ >+ IC_EVEX_W_XD_KZ_B, /* 12623 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12624 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12625 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12626 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12627 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12628 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12629 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12630 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12631 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12632 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12633 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12634 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12635 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12636 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12637 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12638 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12639 */ >+ IC_EVEX_KZ_B, /* 12640 */ >+ IC_EVEX_KZ_B, /* 12641 */ >+ IC_EVEX_XS_KZ_B, /* 12642 */ >+ IC_EVEX_XS_KZ_B, /* 12643 */ >+ IC_EVEX_XD_KZ_B, /* 12644 */ >+ IC_EVEX_XD_KZ_B, /* 12645 */ >+ IC_EVEX_XD_KZ_B, /* 12646 */ >+ IC_EVEX_XD_KZ_B, /* 12647 */ >+ IC_EVEX_W_KZ_B, /* 12648 */ >+ IC_EVEX_W_KZ_B, /* 12649 */ >+ IC_EVEX_W_XS_KZ_B, /* 12650 */ >+ IC_EVEX_W_XS_KZ_B, /* 12651 */ >+ IC_EVEX_W_XD_KZ_B, /* 12652 */ >+ IC_EVEX_W_XD_KZ_B, /* 12653 */ >+ IC_EVEX_W_XD_KZ_B, /* 12654 */ >+ IC_EVEX_W_XD_KZ_B, /* 12655 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12656 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12657 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12658 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12659 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12660 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12661 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12662 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12663 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12664 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12665 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12666 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12667 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12668 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12669 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12670 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12671 */ >+ IC_EVEX_KZ_B, /* 12672 */ >+ IC_EVEX_KZ_B, /* 12673 */ >+ IC_EVEX_XS_KZ_B, /* 12674 */ >+ IC_EVEX_XS_KZ_B, /* 12675 */ >+ IC_EVEX_XD_KZ_B, /* 12676 */ >+ IC_EVEX_XD_KZ_B, /* 12677 */ >+ IC_EVEX_XD_KZ_B, /* 12678 */ >+ IC_EVEX_XD_KZ_B, /* 12679 */ >+ IC_EVEX_W_KZ_B, /* 12680 */ >+ IC_EVEX_W_KZ_B, /* 12681 */ >+ IC_EVEX_W_XS_KZ_B, /* 12682 */ >+ IC_EVEX_W_XS_KZ_B, /* 12683 */ >+ IC_EVEX_W_XD_KZ_B, /* 12684 */ >+ IC_EVEX_W_XD_KZ_B, /* 12685 */ >+ IC_EVEX_W_XD_KZ_B, /* 12686 */ >+ IC_EVEX_W_XD_KZ_B, /* 12687 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12688 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12689 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12690 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12691 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12692 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12693 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12694 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12695 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12696 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12697 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12698 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12699 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12700 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12701 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12702 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12703 */ >+ IC_EVEX_KZ_B, /* 12704 */ >+ IC_EVEX_KZ_B, /* 12705 */ >+ IC_EVEX_XS_KZ_B, /* 12706 */ >+ IC_EVEX_XS_KZ_B, /* 12707 */ >+ IC_EVEX_XD_KZ_B, /* 12708 */ >+ IC_EVEX_XD_KZ_B, /* 12709 */ >+ IC_EVEX_XD_KZ_B, /* 12710 */ >+ IC_EVEX_XD_KZ_B, /* 12711 */ >+ IC_EVEX_W_KZ_B, /* 12712 */ >+ IC_EVEX_W_KZ_B, /* 12713 */ >+ IC_EVEX_W_XS_KZ_B, /* 12714 */ >+ IC_EVEX_W_XS_KZ_B, /* 12715 */ >+ IC_EVEX_W_XD_KZ_B, /* 12716 */ >+ IC_EVEX_W_XD_KZ_B, /* 12717 */ >+ IC_EVEX_W_XD_KZ_B, /* 12718 */ >+ IC_EVEX_W_XD_KZ_B, /* 12719 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12720 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12721 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12722 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12723 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12724 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12725 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12726 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12727 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12728 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12729 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12730 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12731 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12732 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12733 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12734 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12735 */ >+ IC_EVEX_KZ_B, /* 12736 */ >+ IC_EVEX_KZ_B, /* 12737 */ >+ IC_EVEX_XS_KZ_B, /* 12738 */ >+ IC_EVEX_XS_KZ_B, /* 12739 */ >+ IC_EVEX_XD_KZ_B, /* 12740 */ >+ IC_EVEX_XD_KZ_B, /* 12741 */ >+ IC_EVEX_XD_KZ_B, /* 12742 */ >+ IC_EVEX_XD_KZ_B, /* 12743 */ >+ IC_EVEX_W_KZ_B, /* 12744 */ >+ IC_EVEX_W_KZ_B, /* 12745 */ >+ IC_EVEX_W_XS_KZ_B, /* 12746 */ >+ IC_EVEX_W_XS_KZ_B, /* 12747 */ >+ IC_EVEX_W_XD_KZ_B, /* 12748 */ >+ IC_EVEX_W_XD_KZ_B, /* 12749 */ >+ IC_EVEX_W_XD_KZ_B, /* 12750 */ >+ IC_EVEX_W_XD_KZ_B, /* 12751 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12752 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12753 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12754 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12755 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12756 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12757 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12758 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12759 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12760 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12761 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12762 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12763 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12764 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12765 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12766 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12767 */ >+ IC_EVEX_KZ_B, /* 12768 */ >+ IC_EVEX_KZ_B, /* 12769 */ >+ IC_EVEX_XS_KZ_B, /* 12770 */ >+ IC_EVEX_XS_KZ_B, /* 12771 */ >+ IC_EVEX_XD_KZ_B, /* 12772 */ >+ IC_EVEX_XD_KZ_B, /* 12773 */ >+ IC_EVEX_XD_KZ_B, /* 12774 */ >+ IC_EVEX_XD_KZ_B, /* 12775 */ >+ IC_EVEX_W_KZ_B, /* 12776 */ >+ IC_EVEX_W_KZ_B, /* 12777 */ >+ IC_EVEX_W_XS_KZ_B, /* 12778 */ >+ IC_EVEX_W_XS_KZ_B, /* 12779 */ >+ IC_EVEX_W_XD_KZ_B, /* 12780 */ >+ IC_EVEX_W_XD_KZ_B, /* 12781 */ >+ IC_EVEX_W_XD_KZ_B, /* 12782 */ >+ IC_EVEX_W_XD_KZ_B, /* 12783 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12784 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12785 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12786 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12787 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12788 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12789 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12790 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 12791 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12792 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12793 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12794 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12795 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12796 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12797 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12798 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 12799 */ >+ IC, /* 12800 */ >+ IC_64BIT, /* 12801 */ >+ IC_XS, /* 12802 */ >+ IC_64BIT_XS, /* 12803 */ >+ IC_XD, /* 12804 */ >+ IC_64BIT_XD, /* 12805 */ >+ IC_XS, /* 12806 */ >+ IC_64BIT_XS, /* 12807 */ >+ IC, /* 12808 */ >+ IC_64BIT_REXW, /* 12809 */ >+ IC_XS, /* 12810 */ >+ IC_64BIT_REXW_XS, /* 12811 */ >+ IC_XD, /* 12812 */ >+ IC_64BIT_REXW_XD, /* 12813 */ >+ IC_XS, /* 12814 */ >+ IC_64BIT_REXW_XS, /* 12815 */ >+ IC_OPSIZE, /* 12816 */ >+ IC_64BIT_OPSIZE, /* 12817 */ >+ IC_XS_OPSIZE, /* 12818 */ >+ IC_64BIT_XS_OPSIZE, /* 12819 */ >+ IC_XD_OPSIZE, /* 12820 */ >+ IC_64BIT_XD_OPSIZE, /* 12821 */ >+ IC_XS_OPSIZE, /* 12822 */ >+ IC_64BIT_XD_OPSIZE, /* 12823 */ >+ IC_OPSIZE, /* 12824 */ >+ IC_64BIT_REXW_OPSIZE, /* 12825 */ >+ IC_XS_OPSIZE, /* 12826 */ >+ IC_64BIT_REXW_XS, /* 12827 */ >+ IC_XD_OPSIZE, /* 12828 */ >+ IC_64BIT_REXW_XD, /* 12829 */ >+ IC_XS_OPSIZE, /* 12830 */ >+ IC_64BIT_REXW_XS, /* 12831 */ >+ IC_ADSIZE, /* 12832 */ >+ IC_64BIT_ADSIZE, /* 12833 */ >+ IC_XS, /* 12834 */ >+ IC_64BIT_XS, /* 12835 */ >+ IC_XD, /* 12836 */ >+ IC_64BIT_XD, /* 12837 */ >+ IC_XS, /* 12838 */ >+ IC_64BIT_XS, /* 12839 */ >+ IC_ADSIZE, /* 12840 */ >+ IC_64BIT_ADSIZE, /* 12841 */ >+ IC_XS, /* 12842 */ >+ IC_64BIT_REXW_XS, /* 12843 */ >+ IC_XD, /* 12844 */ >+ IC_64BIT_REXW_XD, /* 12845 */ >+ IC_XS, /* 12846 */ >+ IC_64BIT_REXW_XS, /* 12847 */ >+ IC_OPSIZE, /* 12848 */ >+ IC_64BIT_OPSIZE, /* 12849 */ >+ IC_XS_OPSIZE, /* 12850 */ >+ IC_64BIT_XS_OPSIZE, /* 12851 */ >+ IC_XD_OPSIZE, /* 12852 */ >+ IC_64BIT_XD_OPSIZE, /* 12853 */ >+ IC_XS_OPSIZE, /* 12854 */ >+ IC_64BIT_XD_OPSIZE, /* 12855 */ >+ IC_OPSIZE, /* 12856 */ >+ IC_64BIT_REXW_OPSIZE, /* 12857 */ >+ IC_XS_OPSIZE, /* 12858 */ >+ IC_64BIT_REXW_XS, /* 12859 */ >+ IC_XD_OPSIZE, /* 12860 */ >+ IC_64BIT_REXW_XD, /* 12861 */ >+ IC_XS_OPSIZE, /* 12862 */ >+ IC_64BIT_REXW_XS, /* 12863 */ >+ IC_VEX, /* 12864 */ >+ IC_VEX, /* 12865 */ >+ IC_VEX_XS, /* 12866 */ >+ IC_VEX_XS, /* 12867 */ >+ IC_VEX_XD, /* 12868 */ >+ IC_VEX_XD, /* 12869 */ >+ IC_VEX_XD, /* 12870 */ >+ IC_VEX_XD, /* 12871 */ >+ IC_VEX_W, /* 12872 */ >+ IC_VEX_W, /* 12873 */ >+ IC_VEX_W_XS, /* 12874 */ >+ IC_VEX_W_XS, /* 12875 */ >+ IC_VEX_W_XD, /* 12876 */ >+ IC_VEX_W_XD, /* 12877 */ >+ IC_VEX_W_XD, /* 12878 */ >+ IC_VEX_W_XD, /* 12879 */ >+ IC_VEX_OPSIZE, /* 12880 */ >+ IC_VEX_OPSIZE, /* 12881 */ >+ IC_VEX_OPSIZE, /* 12882 */ >+ IC_VEX_OPSIZE, /* 12883 */ >+ IC_VEX_OPSIZE, /* 12884 */ >+ IC_VEX_OPSIZE, /* 12885 */ >+ IC_VEX_OPSIZE, /* 12886 */ >+ IC_VEX_OPSIZE, /* 12887 */ >+ IC_VEX_W_OPSIZE, /* 12888 */ >+ IC_VEX_W_OPSIZE, /* 12889 */ >+ IC_VEX_W_OPSIZE, /* 12890 */ >+ IC_VEX_W_OPSIZE, /* 12891 */ >+ IC_VEX_W_OPSIZE, /* 12892 */ >+ IC_VEX_W_OPSIZE, /* 12893 */ >+ IC_VEX_W_OPSIZE, /* 12894 */ >+ IC_VEX_W_OPSIZE, /* 12895 */ >+ IC_VEX, /* 12896 */ >+ IC_VEX, /* 12897 */ >+ IC_VEX_XS, /* 12898 */ >+ IC_VEX_XS, /* 12899 */ >+ IC_VEX_XD, /* 12900 */ >+ IC_VEX_XD, /* 12901 */ >+ IC_VEX_XD, /* 12902 */ >+ IC_VEX_XD, /* 12903 */ >+ IC_VEX_W, /* 12904 */ >+ IC_VEX_W, /* 12905 */ >+ IC_VEX_W_XS, /* 12906 */ >+ IC_VEX_W_XS, /* 12907 */ >+ IC_VEX_W_XD, /* 12908 */ >+ IC_VEX_W_XD, /* 12909 */ >+ IC_VEX_W_XD, /* 12910 */ >+ IC_VEX_W_XD, /* 12911 */ >+ IC_VEX_OPSIZE, /* 12912 */ >+ IC_VEX_OPSIZE, /* 12913 */ >+ IC_VEX_OPSIZE, /* 12914 */ >+ IC_VEX_OPSIZE, /* 12915 */ >+ IC_VEX_OPSIZE, /* 12916 */ >+ IC_VEX_OPSIZE, /* 12917 */ >+ IC_VEX_OPSIZE, /* 12918 */ >+ IC_VEX_OPSIZE, /* 12919 */ >+ IC_VEX_W_OPSIZE, /* 12920 */ >+ IC_VEX_W_OPSIZE, /* 12921 */ >+ IC_VEX_W_OPSIZE, /* 12922 */ >+ IC_VEX_W_OPSIZE, /* 12923 */ >+ IC_VEX_W_OPSIZE, /* 12924 */ >+ IC_VEX_W_OPSIZE, /* 12925 */ >+ IC_VEX_W_OPSIZE, /* 12926 */ >+ IC_VEX_W_OPSIZE, /* 12927 */ >+ IC_VEX_L, /* 12928 */ >+ IC_VEX_L, /* 12929 */ >+ IC_VEX_L_XS, /* 12930 */ >+ IC_VEX_L_XS, /* 12931 */ >+ IC_VEX_L_XD, /* 12932 */ >+ IC_VEX_L_XD, /* 12933 */ >+ IC_VEX_L_XD, /* 12934 */ >+ IC_VEX_L_XD, /* 12935 */ >+ IC_VEX_L_W, /* 12936 */ >+ IC_VEX_L_W, /* 12937 */ >+ IC_VEX_L_W_XS, /* 12938 */ >+ IC_VEX_L_W_XS, /* 12939 */ >+ IC_VEX_L_W_XD, /* 12940 */ >+ IC_VEX_L_W_XD, /* 12941 */ >+ IC_VEX_L_W_XD, /* 12942 */ >+ IC_VEX_L_W_XD, /* 12943 */ >+ IC_VEX_L_OPSIZE, /* 12944 */ >+ IC_VEX_L_OPSIZE, /* 12945 */ >+ IC_VEX_L_OPSIZE, /* 12946 */ >+ IC_VEX_L_OPSIZE, /* 12947 */ >+ IC_VEX_L_OPSIZE, /* 12948 */ >+ IC_VEX_L_OPSIZE, /* 12949 */ >+ IC_VEX_L_OPSIZE, /* 12950 */ >+ IC_VEX_L_OPSIZE, /* 12951 */ >+ IC_VEX_L_W_OPSIZE, /* 12952 */ >+ IC_VEX_L_W_OPSIZE, /* 12953 */ >+ IC_VEX_L_W_OPSIZE, /* 12954 */ >+ IC_VEX_L_W_OPSIZE, /* 12955 */ >+ IC_VEX_L_W_OPSIZE, /* 12956 */ >+ IC_VEX_L_W_OPSIZE, /* 12957 */ >+ IC_VEX_L_W_OPSIZE, /* 12958 */ >+ IC_VEX_L_W_OPSIZE, /* 12959 */ >+ IC_VEX_L, /* 12960 */ >+ IC_VEX_L, /* 12961 */ >+ IC_VEX_L_XS, /* 12962 */ >+ IC_VEX_L_XS, /* 12963 */ >+ IC_VEX_L_XD, /* 12964 */ >+ IC_VEX_L_XD, /* 12965 */ >+ IC_VEX_L_XD, /* 12966 */ >+ IC_VEX_L_XD, /* 12967 */ >+ IC_VEX_L_W, /* 12968 */ >+ IC_VEX_L_W, /* 12969 */ >+ IC_VEX_L_W_XS, /* 12970 */ >+ IC_VEX_L_W_XS, /* 12971 */ >+ IC_VEX_L_W_XD, /* 12972 */ >+ IC_VEX_L_W_XD, /* 12973 */ >+ IC_VEX_L_W_XD, /* 12974 */ >+ IC_VEX_L_W_XD, /* 12975 */ >+ IC_VEX_L_OPSIZE, /* 12976 */ >+ IC_VEX_L_OPSIZE, /* 12977 */ >+ IC_VEX_L_OPSIZE, /* 12978 */ >+ IC_VEX_L_OPSIZE, /* 12979 */ >+ IC_VEX_L_OPSIZE, /* 12980 */ >+ IC_VEX_L_OPSIZE, /* 12981 */ >+ IC_VEX_L_OPSIZE, /* 12982 */ >+ IC_VEX_L_OPSIZE, /* 12983 */ >+ IC_VEX_L_W_OPSIZE, /* 12984 */ >+ IC_VEX_L_W_OPSIZE, /* 12985 */ >+ IC_VEX_L_W_OPSIZE, /* 12986 */ >+ IC_VEX_L_W_OPSIZE, /* 12987 */ >+ IC_VEX_L_W_OPSIZE, /* 12988 */ >+ IC_VEX_L_W_OPSIZE, /* 12989 */ >+ IC_VEX_L_W_OPSIZE, /* 12990 */ >+ IC_VEX_L_W_OPSIZE, /* 12991 */ >+ IC_VEX_L, /* 12992 */ >+ IC_VEX_L, /* 12993 */ >+ IC_VEX_L_XS, /* 12994 */ >+ IC_VEX_L_XS, /* 12995 */ >+ IC_VEX_L_XD, /* 12996 */ >+ IC_VEX_L_XD, /* 12997 */ >+ IC_VEX_L_XD, /* 12998 */ >+ IC_VEX_L_XD, /* 12999 */ >+ IC_VEX_L_W, /* 13000 */ >+ IC_VEX_L_W, /* 13001 */ >+ IC_VEX_L_W_XS, /* 13002 */ >+ IC_VEX_L_W_XS, /* 13003 */ >+ IC_VEX_L_W_XD, /* 13004 */ >+ IC_VEX_L_W_XD, /* 13005 */ >+ IC_VEX_L_W_XD, /* 13006 */ >+ IC_VEX_L_W_XD, /* 13007 */ >+ IC_VEX_L_OPSIZE, /* 13008 */ >+ IC_VEX_L_OPSIZE, /* 13009 */ >+ IC_VEX_L_OPSIZE, /* 13010 */ >+ IC_VEX_L_OPSIZE, /* 13011 */ >+ IC_VEX_L_OPSIZE, /* 13012 */ >+ IC_VEX_L_OPSIZE, /* 13013 */ >+ IC_VEX_L_OPSIZE, /* 13014 */ >+ IC_VEX_L_OPSIZE, /* 13015 */ >+ IC_VEX_L_W_OPSIZE, /* 13016 */ >+ IC_VEX_L_W_OPSIZE, /* 13017 */ >+ IC_VEX_L_W_OPSIZE, /* 13018 */ >+ IC_VEX_L_W_OPSIZE, /* 13019 */ >+ IC_VEX_L_W_OPSIZE, /* 13020 */ >+ IC_VEX_L_W_OPSIZE, /* 13021 */ >+ IC_VEX_L_W_OPSIZE, /* 13022 */ >+ IC_VEX_L_W_OPSIZE, /* 13023 */ >+ IC_VEX_L, /* 13024 */ >+ IC_VEX_L, /* 13025 */ >+ IC_VEX_L_XS, /* 13026 */ >+ IC_VEX_L_XS, /* 13027 */ >+ IC_VEX_L_XD, /* 13028 */ >+ IC_VEX_L_XD, /* 13029 */ >+ IC_VEX_L_XD, /* 13030 */ >+ IC_VEX_L_XD, /* 13031 */ >+ IC_VEX_L_W, /* 13032 */ >+ IC_VEX_L_W, /* 13033 */ >+ IC_VEX_L_W_XS, /* 13034 */ >+ IC_VEX_L_W_XS, /* 13035 */ >+ IC_VEX_L_W_XD, /* 13036 */ >+ IC_VEX_L_W_XD, /* 13037 */ >+ IC_VEX_L_W_XD, /* 13038 */ >+ IC_VEX_L_W_XD, /* 13039 */ >+ IC_VEX_L_OPSIZE, /* 13040 */ >+ IC_VEX_L_OPSIZE, /* 13041 */ >+ IC_VEX_L_OPSIZE, /* 13042 */ >+ IC_VEX_L_OPSIZE, /* 13043 */ >+ IC_VEX_L_OPSIZE, /* 13044 */ >+ IC_VEX_L_OPSIZE, /* 13045 */ >+ IC_VEX_L_OPSIZE, /* 13046 */ >+ IC_VEX_L_OPSIZE, /* 13047 */ >+ IC_VEX_L_W_OPSIZE, /* 13048 */ >+ IC_VEX_L_W_OPSIZE, /* 13049 */ >+ IC_VEX_L_W_OPSIZE, /* 13050 */ >+ IC_VEX_L_W_OPSIZE, /* 13051 */ >+ IC_VEX_L_W_OPSIZE, /* 13052 */ >+ IC_VEX_L_W_OPSIZE, /* 13053 */ >+ IC_VEX_L_W_OPSIZE, /* 13054 */ >+ IC_VEX_L_W_OPSIZE, /* 13055 */ >+ IC_EVEX_L_KZ_B, /* 13056 */ >+ IC_EVEX_L_KZ_B, /* 13057 */ >+ IC_EVEX_L_XS_KZ_B, /* 13058 */ >+ IC_EVEX_L_XS_KZ_B, /* 13059 */ >+ IC_EVEX_L_XD_KZ_B, /* 13060 */ >+ IC_EVEX_L_XD_KZ_B, /* 13061 */ >+ IC_EVEX_L_XD_KZ_B, /* 13062 */ >+ IC_EVEX_L_XD_KZ_B, /* 13063 */ >+ IC_EVEX_L_W_KZ_B, /* 13064 */ >+ IC_EVEX_L_W_KZ_B, /* 13065 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13066 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13067 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13068 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13069 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13070 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13071 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13072 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13073 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13074 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13075 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13076 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13077 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13078 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13079 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13080 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13081 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13082 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13083 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13084 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13085 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13086 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13087 */ >+ IC_EVEX_L_KZ_B, /* 13088 */ >+ IC_EVEX_L_KZ_B, /* 13089 */ >+ IC_EVEX_L_XS_KZ_B, /* 13090 */ >+ IC_EVEX_L_XS_KZ_B, /* 13091 */ >+ IC_EVEX_L_XD_KZ_B, /* 13092 */ >+ IC_EVEX_L_XD_KZ_B, /* 13093 */ >+ IC_EVEX_L_XD_KZ_B, /* 13094 */ >+ IC_EVEX_L_XD_KZ_B, /* 13095 */ >+ IC_EVEX_L_W_KZ_B, /* 13096 */ >+ IC_EVEX_L_W_KZ_B, /* 13097 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13098 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13099 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13100 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13101 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13102 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13103 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13104 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13105 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13106 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13107 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13108 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13109 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13110 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13111 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13112 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13113 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13114 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13115 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13116 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13117 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13118 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13119 */ >+ IC_EVEX_L_KZ_B, /* 13120 */ >+ IC_EVEX_L_KZ_B, /* 13121 */ >+ IC_EVEX_L_XS_KZ_B, /* 13122 */ >+ IC_EVEX_L_XS_KZ_B, /* 13123 */ >+ IC_EVEX_L_XD_KZ_B, /* 13124 */ >+ IC_EVEX_L_XD_KZ_B, /* 13125 */ >+ IC_EVEX_L_XD_KZ_B, /* 13126 */ >+ IC_EVEX_L_XD_KZ_B, /* 13127 */ >+ IC_EVEX_L_W_KZ_B, /* 13128 */ >+ IC_EVEX_L_W_KZ_B, /* 13129 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13130 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13131 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13132 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13133 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13134 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13135 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13136 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13137 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13138 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13139 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13140 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13141 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13142 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13143 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13144 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13145 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13146 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13147 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13148 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13149 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13150 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13151 */ >+ IC_EVEX_L_KZ_B, /* 13152 */ >+ IC_EVEX_L_KZ_B, /* 13153 */ >+ IC_EVEX_L_XS_KZ_B, /* 13154 */ >+ IC_EVEX_L_XS_KZ_B, /* 13155 */ >+ IC_EVEX_L_XD_KZ_B, /* 13156 */ >+ IC_EVEX_L_XD_KZ_B, /* 13157 */ >+ IC_EVEX_L_XD_KZ_B, /* 13158 */ >+ IC_EVEX_L_XD_KZ_B, /* 13159 */ >+ IC_EVEX_L_W_KZ_B, /* 13160 */ >+ IC_EVEX_L_W_KZ_B, /* 13161 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13162 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13163 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13164 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13165 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13166 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13167 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13168 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13169 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13170 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13171 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13172 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13173 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13174 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13175 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13176 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13177 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13178 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13179 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13180 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13181 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13182 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13183 */ >+ IC_EVEX_L_KZ_B, /* 13184 */ >+ IC_EVEX_L_KZ_B, /* 13185 */ >+ IC_EVEX_L_XS_KZ_B, /* 13186 */ >+ IC_EVEX_L_XS_KZ_B, /* 13187 */ >+ IC_EVEX_L_XD_KZ_B, /* 13188 */ >+ IC_EVEX_L_XD_KZ_B, /* 13189 */ >+ IC_EVEX_L_XD_KZ_B, /* 13190 */ >+ IC_EVEX_L_XD_KZ_B, /* 13191 */ >+ IC_EVEX_L_W_KZ_B, /* 13192 */ >+ IC_EVEX_L_W_KZ_B, /* 13193 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13194 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13195 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13196 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13197 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13198 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13199 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13200 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13201 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13202 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13203 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13204 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13205 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13206 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13207 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13208 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13209 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13210 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13211 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13212 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13213 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13214 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13215 */ >+ IC_EVEX_L_KZ_B, /* 13216 */ >+ IC_EVEX_L_KZ_B, /* 13217 */ >+ IC_EVEX_L_XS_KZ_B, /* 13218 */ >+ IC_EVEX_L_XS_KZ_B, /* 13219 */ >+ IC_EVEX_L_XD_KZ_B, /* 13220 */ >+ IC_EVEX_L_XD_KZ_B, /* 13221 */ >+ IC_EVEX_L_XD_KZ_B, /* 13222 */ >+ IC_EVEX_L_XD_KZ_B, /* 13223 */ >+ IC_EVEX_L_W_KZ_B, /* 13224 */ >+ IC_EVEX_L_W_KZ_B, /* 13225 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13226 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13227 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13228 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13229 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13230 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13231 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13232 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13233 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13234 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13235 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13236 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13237 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13238 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13239 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13240 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13241 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13242 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13243 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13244 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13245 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13246 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13247 */ >+ IC_EVEX_L_KZ_B, /* 13248 */ >+ IC_EVEX_L_KZ_B, /* 13249 */ >+ IC_EVEX_L_XS_KZ_B, /* 13250 */ >+ IC_EVEX_L_XS_KZ_B, /* 13251 */ >+ IC_EVEX_L_XD_KZ_B, /* 13252 */ >+ IC_EVEX_L_XD_KZ_B, /* 13253 */ >+ IC_EVEX_L_XD_KZ_B, /* 13254 */ >+ IC_EVEX_L_XD_KZ_B, /* 13255 */ >+ IC_EVEX_L_W_KZ_B, /* 13256 */ >+ IC_EVEX_L_W_KZ_B, /* 13257 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13258 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13259 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13260 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13261 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13262 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13263 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13264 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13265 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13266 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13267 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13268 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13269 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13270 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13271 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13272 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13273 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13274 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13275 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13276 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13277 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13278 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13279 */ >+ IC_EVEX_L_KZ_B, /* 13280 */ >+ IC_EVEX_L_KZ_B, /* 13281 */ >+ IC_EVEX_L_XS_KZ_B, /* 13282 */ >+ IC_EVEX_L_XS_KZ_B, /* 13283 */ >+ IC_EVEX_L_XD_KZ_B, /* 13284 */ >+ IC_EVEX_L_XD_KZ_B, /* 13285 */ >+ IC_EVEX_L_XD_KZ_B, /* 13286 */ >+ IC_EVEX_L_XD_KZ_B, /* 13287 */ >+ IC_EVEX_L_W_KZ_B, /* 13288 */ >+ IC_EVEX_L_W_KZ_B, /* 13289 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13290 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 13291 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13292 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13293 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13294 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 13295 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13296 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13297 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13298 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13299 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13300 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13301 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13302 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 13303 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13304 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13305 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13306 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13307 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13308 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13309 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13310 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 13311 */ >+ IC, /* 13312 */ >+ IC_64BIT, /* 13313 */ >+ IC_XS, /* 13314 */ >+ IC_64BIT_XS, /* 13315 */ >+ IC_XD, /* 13316 */ >+ IC_64BIT_XD, /* 13317 */ >+ IC_XS, /* 13318 */ >+ IC_64BIT_XS, /* 13319 */ >+ IC, /* 13320 */ >+ IC_64BIT_REXW, /* 13321 */ >+ IC_XS, /* 13322 */ >+ IC_64BIT_REXW_XS, /* 13323 */ >+ IC_XD, /* 13324 */ >+ IC_64BIT_REXW_XD, /* 13325 */ >+ IC_XS, /* 13326 */ >+ IC_64BIT_REXW_XS, /* 13327 */ >+ IC_OPSIZE, /* 13328 */ >+ IC_64BIT_OPSIZE, /* 13329 */ >+ IC_XS_OPSIZE, /* 13330 */ >+ IC_64BIT_XS_OPSIZE, /* 13331 */ >+ IC_XD_OPSIZE, /* 13332 */ >+ IC_64BIT_XD_OPSIZE, /* 13333 */ >+ IC_XS_OPSIZE, /* 13334 */ >+ IC_64BIT_XD_OPSIZE, /* 13335 */ >+ IC_OPSIZE, /* 13336 */ >+ IC_64BIT_REXW_OPSIZE, /* 13337 */ >+ IC_XS_OPSIZE, /* 13338 */ >+ IC_64BIT_REXW_XS, /* 13339 */ >+ IC_XD_OPSIZE, /* 13340 */ >+ IC_64BIT_REXW_XD, /* 13341 */ >+ IC_XS_OPSIZE, /* 13342 */ >+ IC_64BIT_REXW_XS, /* 13343 */ >+ IC_ADSIZE, /* 13344 */ >+ IC_64BIT_ADSIZE, /* 13345 */ >+ IC_XS, /* 13346 */ >+ IC_64BIT_XS, /* 13347 */ >+ IC_XD, /* 13348 */ >+ IC_64BIT_XD, /* 13349 */ >+ IC_XS, /* 13350 */ >+ IC_64BIT_XS, /* 13351 */ >+ IC_ADSIZE, /* 13352 */ >+ IC_64BIT_ADSIZE, /* 13353 */ >+ IC_XS, /* 13354 */ >+ IC_64BIT_REXW_XS, /* 13355 */ >+ IC_XD, /* 13356 */ >+ IC_64BIT_REXW_XD, /* 13357 */ >+ IC_XS, /* 13358 */ >+ IC_64BIT_REXW_XS, /* 13359 */ >+ IC_OPSIZE, /* 13360 */ >+ IC_64BIT_OPSIZE, /* 13361 */ >+ IC_XS_OPSIZE, /* 13362 */ >+ IC_64BIT_XS_OPSIZE, /* 13363 */ >+ IC_XD_OPSIZE, /* 13364 */ >+ IC_64BIT_XD_OPSIZE, /* 13365 */ >+ IC_XS_OPSIZE, /* 13366 */ >+ IC_64BIT_XD_OPSIZE, /* 13367 */ >+ IC_OPSIZE, /* 13368 */ >+ IC_64BIT_REXW_OPSIZE, /* 13369 */ >+ IC_XS_OPSIZE, /* 13370 */ >+ IC_64BIT_REXW_XS, /* 13371 */ >+ IC_XD_OPSIZE, /* 13372 */ >+ IC_64BIT_REXW_XD, /* 13373 */ >+ IC_XS_OPSIZE, /* 13374 */ >+ IC_64BIT_REXW_XS, /* 13375 */ >+ IC_VEX, /* 13376 */ >+ IC_VEX, /* 13377 */ >+ IC_VEX_XS, /* 13378 */ >+ IC_VEX_XS, /* 13379 */ >+ IC_VEX_XD, /* 13380 */ >+ IC_VEX_XD, /* 13381 */ >+ IC_VEX_XD, /* 13382 */ >+ IC_VEX_XD, /* 13383 */ >+ IC_VEX_W, /* 13384 */ >+ IC_VEX_W, /* 13385 */ >+ IC_VEX_W_XS, /* 13386 */ >+ IC_VEX_W_XS, /* 13387 */ >+ IC_VEX_W_XD, /* 13388 */ >+ IC_VEX_W_XD, /* 13389 */ >+ IC_VEX_W_XD, /* 13390 */ >+ IC_VEX_W_XD, /* 13391 */ >+ IC_VEX_OPSIZE, /* 13392 */ >+ IC_VEX_OPSIZE, /* 13393 */ >+ IC_VEX_OPSIZE, /* 13394 */ >+ IC_VEX_OPSIZE, /* 13395 */ >+ IC_VEX_OPSIZE, /* 13396 */ >+ IC_VEX_OPSIZE, /* 13397 */ >+ IC_VEX_OPSIZE, /* 13398 */ >+ IC_VEX_OPSIZE, /* 13399 */ >+ IC_VEX_W_OPSIZE, /* 13400 */ >+ IC_VEX_W_OPSIZE, /* 13401 */ >+ IC_VEX_W_OPSIZE, /* 13402 */ >+ IC_VEX_W_OPSIZE, /* 13403 */ >+ IC_VEX_W_OPSIZE, /* 13404 */ >+ IC_VEX_W_OPSIZE, /* 13405 */ >+ IC_VEX_W_OPSIZE, /* 13406 */ >+ IC_VEX_W_OPSIZE, /* 13407 */ >+ IC_VEX, /* 13408 */ >+ IC_VEX, /* 13409 */ >+ IC_VEX_XS, /* 13410 */ >+ IC_VEX_XS, /* 13411 */ >+ IC_VEX_XD, /* 13412 */ >+ IC_VEX_XD, /* 13413 */ >+ IC_VEX_XD, /* 13414 */ >+ IC_VEX_XD, /* 13415 */ >+ IC_VEX_W, /* 13416 */ >+ IC_VEX_W, /* 13417 */ >+ IC_VEX_W_XS, /* 13418 */ >+ IC_VEX_W_XS, /* 13419 */ >+ IC_VEX_W_XD, /* 13420 */ >+ IC_VEX_W_XD, /* 13421 */ >+ IC_VEX_W_XD, /* 13422 */ >+ IC_VEX_W_XD, /* 13423 */ >+ IC_VEX_OPSIZE, /* 13424 */ >+ IC_VEX_OPSIZE, /* 13425 */ >+ IC_VEX_OPSIZE, /* 13426 */ >+ IC_VEX_OPSIZE, /* 13427 */ >+ IC_VEX_OPSIZE, /* 13428 */ >+ IC_VEX_OPSIZE, /* 13429 */ >+ IC_VEX_OPSIZE, /* 13430 */ >+ IC_VEX_OPSIZE, /* 13431 */ >+ IC_VEX_W_OPSIZE, /* 13432 */ >+ IC_VEX_W_OPSIZE, /* 13433 */ >+ IC_VEX_W_OPSIZE, /* 13434 */ >+ IC_VEX_W_OPSIZE, /* 13435 */ >+ IC_VEX_W_OPSIZE, /* 13436 */ >+ IC_VEX_W_OPSIZE, /* 13437 */ >+ IC_VEX_W_OPSIZE, /* 13438 */ >+ IC_VEX_W_OPSIZE, /* 13439 */ >+ IC_VEX_L, /* 13440 */ >+ IC_VEX_L, /* 13441 */ >+ IC_VEX_L_XS, /* 13442 */ >+ IC_VEX_L_XS, /* 13443 */ >+ IC_VEX_L_XD, /* 13444 */ >+ IC_VEX_L_XD, /* 13445 */ >+ IC_VEX_L_XD, /* 13446 */ >+ IC_VEX_L_XD, /* 13447 */ >+ IC_VEX_L_W, /* 13448 */ >+ IC_VEX_L_W, /* 13449 */ >+ IC_VEX_L_W_XS, /* 13450 */ >+ IC_VEX_L_W_XS, /* 13451 */ >+ IC_VEX_L_W_XD, /* 13452 */ >+ IC_VEX_L_W_XD, /* 13453 */ >+ IC_VEX_L_W_XD, /* 13454 */ >+ IC_VEX_L_W_XD, /* 13455 */ >+ IC_VEX_L_OPSIZE, /* 13456 */ >+ IC_VEX_L_OPSIZE, /* 13457 */ >+ IC_VEX_L_OPSIZE, /* 13458 */ >+ IC_VEX_L_OPSIZE, /* 13459 */ >+ IC_VEX_L_OPSIZE, /* 13460 */ >+ IC_VEX_L_OPSIZE, /* 13461 */ >+ IC_VEX_L_OPSIZE, /* 13462 */ >+ IC_VEX_L_OPSIZE, /* 13463 */ >+ IC_VEX_L_W_OPSIZE, /* 13464 */ >+ IC_VEX_L_W_OPSIZE, /* 13465 */ >+ IC_VEX_L_W_OPSIZE, /* 13466 */ >+ IC_VEX_L_W_OPSIZE, /* 13467 */ >+ IC_VEX_L_W_OPSIZE, /* 13468 */ >+ IC_VEX_L_W_OPSIZE, /* 13469 */ >+ IC_VEX_L_W_OPSIZE, /* 13470 */ >+ IC_VEX_L_W_OPSIZE, /* 13471 */ >+ IC_VEX_L, /* 13472 */ >+ IC_VEX_L, /* 13473 */ >+ IC_VEX_L_XS, /* 13474 */ >+ IC_VEX_L_XS, /* 13475 */ >+ IC_VEX_L_XD, /* 13476 */ >+ IC_VEX_L_XD, /* 13477 */ >+ IC_VEX_L_XD, /* 13478 */ >+ IC_VEX_L_XD, /* 13479 */ >+ IC_VEX_L_W, /* 13480 */ >+ IC_VEX_L_W, /* 13481 */ >+ IC_VEX_L_W_XS, /* 13482 */ >+ IC_VEX_L_W_XS, /* 13483 */ >+ IC_VEX_L_W_XD, /* 13484 */ >+ IC_VEX_L_W_XD, /* 13485 */ >+ IC_VEX_L_W_XD, /* 13486 */ >+ IC_VEX_L_W_XD, /* 13487 */ >+ IC_VEX_L_OPSIZE, /* 13488 */ >+ IC_VEX_L_OPSIZE, /* 13489 */ >+ IC_VEX_L_OPSIZE, /* 13490 */ >+ IC_VEX_L_OPSIZE, /* 13491 */ >+ IC_VEX_L_OPSIZE, /* 13492 */ >+ IC_VEX_L_OPSIZE, /* 13493 */ >+ IC_VEX_L_OPSIZE, /* 13494 */ >+ IC_VEX_L_OPSIZE, /* 13495 */ >+ IC_VEX_L_W_OPSIZE, /* 13496 */ >+ IC_VEX_L_W_OPSIZE, /* 13497 */ >+ IC_VEX_L_W_OPSIZE, /* 13498 */ >+ IC_VEX_L_W_OPSIZE, /* 13499 */ >+ IC_VEX_L_W_OPSIZE, /* 13500 */ >+ IC_VEX_L_W_OPSIZE, /* 13501 */ >+ IC_VEX_L_W_OPSIZE, /* 13502 */ >+ IC_VEX_L_W_OPSIZE, /* 13503 */ >+ IC_VEX_L, /* 13504 */ >+ IC_VEX_L, /* 13505 */ >+ IC_VEX_L_XS, /* 13506 */ >+ IC_VEX_L_XS, /* 13507 */ >+ IC_VEX_L_XD, /* 13508 */ >+ IC_VEX_L_XD, /* 13509 */ >+ IC_VEX_L_XD, /* 13510 */ >+ IC_VEX_L_XD, /* 13511 */ >+ IC_VEX_L_W, /* 13512 */ >+ IC_VEX_L_W, /* 13513 */ >+ IC_VEX_L_W_XS, /* 13514 */ >+ IC_VEX_L_W_XS, /* 13515 */ >+ IC_VEX_L_W_XD, /* 13516 */ >+ IC_VEX_L_W_XD, /* 13517 */ >+ IC_VEX_L_W_XD, /* 13518 */ >+ IC_VEX_L_W_XD, /* 13519 */ >+ IC_VEX_L_OPSIZE, /* 13520 */ >+ IC_VEX_L_OPSIZE, /* 13521 */ >+ IC_VEX_L_OPSIZE, /* 13522 */ >+ IC_VEX_L_OPSIZE, /* 13523 */ >+ IC_VEX_L_OPSIZE, /* 13524 */ >+ IC_VEX_L_OPSIZE, /* 13525 */ >+ IC_VEX_L_OPSIZE, /* 13526 */ >+ IC_VEX_L_OPSIZE, /* 13527 */ >+ IC_VEX_L_W_OPSIZE, /* 13528 */ >+ IC_VEX_L_W_OPSIZE, /* 13529 */ >+ IC_VEX_L_W_OPSIZE, /* 13530 */ >+ IC_VEX_L_W_OPSIZE, /* 13531 */ >+ IC_VEX_L_W_OPSIZE, /* 13532 */ >+ IC_VEX_L_W_OPSIZE, /* 13533 */ >+ IC_VEX_L_W_OPSIZE, /* 13534 */ >+ IC_VEX_L_W_OPSIZE, /* 13535 */ >+ IC_VEX_L, /* 13536 */ >+ IC_VEX_L, /* 13537 */ >+ IC_VEX_L_XS, /* 13538 */ >+ IC_VEX_L_XS, /* 13539 */ >+ IC_VEX_L_XD, /* 13540 */ >+ IC_VEX_L_XD, /* 13541 */ >+ IC_VEX_L_XD, /* 13542 */ >+ IC_VEX_L_XD, /* 13543 */ >+ IC_VEX_L_W, /* 13544 */ >+ IC_VEX_L_W, /* 13545 */ >+ IC_VEX_L_W_XS, /* 13546 */ >+ IC_VEX_L_W_XS, /* 13547 */ >+ IC_VEX_L_W_XD, /* 13548 */ >+ IC_VEX_L_W_XD, /* 13549 */ >+ IC_VEX_L_W_XD, /* 13550 */ >+ IC_VEX_L_W_XD, /* 13551 */ >+ IC_VEX_L_OPSIZE, /* 13552 */ >+ IC_VEX_L_OPSIZE, /* 13553 */ >+ IC_VEX_L_OPSIZE, /* 13554 */ >+ IC_VEX_L_OPSIZE, /* 13555 */ >+ IC_VEX_L_OPSIZE, /* 13556 */ >+ IC_VEX_L_OPSIZE, /* 13557 */ >+ IC_VEX_L_OPSIZE, /* 13558 */ >+ IC_VEX_L_OPSIZE, /* 13559 */ >+ IC_VEX_L_W_OPSIZE, /* 13560 */ >+ IC_VEX_L_W_OPSIZE, /* 13561 */ >+ IC_VEX_L_W_OPSIZE, /* 13562 */ >+ IC_VEX_L_W_OPSIZE, /* 13563 */ >+ IC_VEX_L_W_OPSIZE, /* 13564 */ >+ IC_VEX_L_W_OPSIZE, /* 13565 */ >+ IC_VEX_L_W_OPSIZE, /* 13566 */ >+ IC_VEX_L_W_OPSIZE, /* 13567 */ >+ IC_EVEX_L2_KZ_B, /* 13568 */ >+ IC_EVEX_L2_KZ_B, /* 13569 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13570 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13571 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13572 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13573 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13574 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13575 */ >+ IC_EVEX_L2_W_KZ_B, /* 13576 */ >+ IC_EVEX_L2_W_KZ_B, /* 13577 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13578 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13579 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13580 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13581 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13582 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13583 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13584 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13585 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13586 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13587 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13588 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13589 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13590 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13591 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13592 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13593 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13594 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13595 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13596 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13597 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13598 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13599 */ >+ IC_EVEX_L2_KZ_B, /* 13600 */ >+ IC_EVEX_L2_KZ_B, /* 13601 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13602 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13603 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13604 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13605 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13606 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13607 */ >+ IC_EVEX_L2_W_KZ_B, /* 13608 */ >+ IC_EVEX_L2_W_KZ_B, /* 13609 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13610 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13611 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13612 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13613 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13614 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13615 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13616 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13617 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13618 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13619 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13620 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13621 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13622 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13623 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13624 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13625 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13626 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13627 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13628 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13629 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13630 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13631 */ >+ IC_EVEX_L2_KZ_B, /* 13632 */ >+ IC_EVEX_L2_KZ_B, /* 13633 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13634 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13635 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13636 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13637 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13638 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13639 */ >+ IC_EVEX_L2_W_KZ_B, /* 13640 */ >+ IC_EVEX_L2_W_KZ_B, /* 13641 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13642 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13643 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13644 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13645 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13646 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13647 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13648 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13649 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13650 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13651 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13652 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13653 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13654 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13655 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13656 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13657 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13658 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13659 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13660 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13661 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13662 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13663 */ >+ IC_EVEX_L2_KZ_B, /* 13664 */ >+ IC_EVEX_L2_KZ_B, /* 13665 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13666 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13667 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13668 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13669 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13670 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13671 */ >+ IC_EVEX_L2_W_KZ_B, /* 13672 */ >+ IC_EVEX_L2_W_KZ_B, /* 13673 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13674 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13675 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13676 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13677 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13678 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13679 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13680 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13681 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13682 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13683 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13684 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13685 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13686 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13687 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13688 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13689 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13690 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13691 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13692 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13693 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13694 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13695 */ >+ IC_EVEX_L2_KZ_B, /* 13696 */ >+ IC_EVEX_L2_KZ_B, /* 13697 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13698 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13699 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13700 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13701 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13702 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13703 */ >+ IC_EVEX_L2_W_KZ_B, /* 13704 */ >+ IC_EVEX_L2_W_KZ_B, /* 13705 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13706 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13707 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13708 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13709 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13710 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13711 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13712 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13713 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13714 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13715 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13716 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13717 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13718 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13719 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13720 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13721 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13722 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13723 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13724 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13725 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13726 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13727 */ >+ IC_EVEX_L2_KZ_B, /* 13728 */ >+ IC_EVEX_L2_KZ_B, /* 13729 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13730 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13731 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13732 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13733 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13734 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13735 */ >+ IC_EVEX_L2_W_KZ_B, /* 13736 */ >+ IC_EVEX_L2_W_KZ_B, /* 13737 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13738 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13739 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13740 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13741 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13742 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13743 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13744 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13745 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13746 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13747 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13748 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13749 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13750 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13751 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13752 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13753 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13754 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13755 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13756 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13757 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13758 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13759 */ >+ IC_EVEX_L2_KZ_B, /* 13760 */ >+ IC_EVEX_L2_KZ_B, /* 13761 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13762 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13763 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13764 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13765 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13766 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13767 */ >+ IC_EVEX_L2_W_KZ_B, /* 13768 */ >+ IC_EVEX_L2_W_KZ_B, /* 13769 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13770 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13771 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13772 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13773 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13774 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13775 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13776 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13777 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13778 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13779 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13780 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13781 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13782 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13783 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13784 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13785 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13786 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13787 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13788 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13789 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13790 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13791 */ >+ IC_EVEX_L2_KZ_B, /* 13792 */ >+ IC_EVEX_L2_KZ_B, /* 13793 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13794 */ >+ IC_EVEX_L2_XS_KZ_B, /* 13795 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13796 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13797 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13798 */ >+ IC_EVEX_L2_XD_KZ_B, /* 13799 */ >+ IC_EVEX_L2_W_KZ_B, /* 13800 */ >+ IC_EVEX_L2_W_KZ_B, /* 13801 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13802 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 13803 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13804 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13805 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13806 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 13807 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13808 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13809 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13810 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13811 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13812 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13813 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13814 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 13815 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13816 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13817 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13818 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13819 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13820 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13821 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13822 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 13823 */ >+ IC, /* 13824 */ >+ IC_64BIT, /* 13825 */ >+ IC_XS, /* 13826 */ >+ IC_64BIT_XS, /* 13827 */ >+ IC_XD, /* 13828 */ >+ IC_64BIT_XD, /* 13829 */ >+ IC_XS, /* 13830 */ >+ IC_64BIT_XS, /* 13831 */ >+ IC, /* 13832 */ >+ IC_64BIT_REXW, /* 13833 */ >+ IC_XS, /* 13834 */ >+ IC_64BIT_REXW_XS, /* 13835 */ >+ IC_XD, /* 13836 */ >+ IC_64BIT_REXW_XD, /* 13837 */ >+ IC_XS, /* 13838 */ >+ IC_64BIT_REXW_XS, /* 13839 */ >+ IC_OPSIZE, /* 13840 */ >+ IC_64BIT_OPSIZE, /* 13841 */ >+ IC_XS_OPSIZE, /* 13842 */ >+ IC_64BIT_XS_OPSIZE, /* 13843 */ >+ IC_XD_OPSIZE, /* 13844 */ >+ IC_64BIT_XD_OPSIZE, /* 13845 */ >+ IC_XS_OPSIZE, /* 13846 */ >+ IC_64BIT_XD_OPSIZE, /* 13847 */ >+ IC_OPSIZE, /* 13848 */ >+ IC_64BIT_REXW_OPSIZE, /* 13849 */ >+ IC_XS_OPSIZE, /* 13850 */ >+ IC_64BIT_REXW_XS, /* 13851 */ >+ IC_XD_OPSIZE, /* 13852 */ >+ IC_64BIT_REXW_XD, /* 13853 */ >+ IC_XS_OPSIZE, /* 13854 */ >+ IC_64BIT_REXW_XS, /* 13855 */ >+ IC_ADSIZE, /* 13856 */ >+ IC_64BIT_ADSIZE, /* 13857 */ >+ IC_XS, /* 13858 */ >+ IC_64BIT_XS, /* 13859 */ >+ IC_XD, /* 13860 */ >+ IC_64BIT_XD, /* 13861 */ >+ IC_XS, /* 13862 */ >+ IC_64BIT_XS, /* 13863 */ >+ IC_ADSIZE, /* 13864 */ >+ IC_64BIT_ADSIZE, /* 13865 */ >+ IC_XS, /* 13866 */ >+ IC_64BIT_REXW_XS, /* 13867 */ >+ IC_XD, /* 13868 */ >+ IC_64BIT_REXW_XD, /* 13869 */ >+ IC_XS, /* 13870 */ >+ IC_64BIT_REXW_XS, /* 13871 */ >+ IC_OPSIZE, /* 13872 */ >+ IC_64BIT_OPSIZE, /* 13873 */ >+ IC_XS_OPSIZE, /* 13874 */ >+ IC_64BIT_XS_OPSIZE, /* 13875 */ >+ IC_XD_OPSIZE, /* 13876 */ >+ IC_64BIT_XD_OPSIZE, /* 13877 */ >+ IC_XS_OPSIZE, /* 13878 */ >+ IC_64BIT_XD_OPSIZE, /* 13879 */ >+ IC_OPSIZE, /* 13880 */ >+ IC_64BIT_REXW_OPSIZE, /* 13881 */ >+ IC_XS_OPSIZE, /* 13882 */ >+ IC_64BIT_REXW_XS, /* 13883 */ >+ IC_XD_OPSIZE, /* 13884 */ >+ IC_64BIT_REXW_XD, /* 13885 */ >+ IC_XS_OPSIZE, /* 13886 */ >+ IC_64BIT_REXW_XS, /* 13887 */ >+ IC_VEX, /* 13888 */ >+ IC_VEX, /* 13889 */ >+ IC_VEX_XS, /* 13890 */ >+ IC_VEX_XS, /* 13891 */ >+ IC_VEX_XD, /* 13892 */ >+ IC_VEX_XD, /* 13893 */ >+ IC_VEX_XD, /* 13894 */ >+ IC_VEX_XD, /* 13895 */ >+ IC_VEX_W, /* 13896 */ >+ IC_VEX_W, /* 13897 */ >+ IC_VEX_W_XS, /* 13898 */ >+ IC_VEX_W_XS, /* 13899 */ >+ IC_VEX_W_XD, /* 13900 */ >+ IC_VEX_W_XD, /* 13901 */ >+ IC_VEX_W_XD, /* 13902 */ >+ IC_VEX_W_XD, /* 13903 */ >+ IC_VEX_OPSIZE, /* 13904 */ >+ IC_VEX_OPSIZE, /* 13905 */ >+ IC_VEX_OPSIZE, /* 13906 */ >+ IC_VEX_OPSIZE, /* 13907 */ >+ IC_VEX_OPSIZE, /* 13908 */ >+ IC_VEX_OPSIZE, /* 13909 */ >+ IC_VEX_OPSIZE, /* 13910 */ >+ IC_VEX_OPSIZE, /* 13911 */ >+ IC_VEX_W_OPSIZE, /* 13912 */ >+ IC_VEX_W_OPSIZE, /* 13913 */ >+ IC_VEX_W_OPSIZE, /* 13914 */ >+ IC_VEX_W_OPSIZE, /* 13915 */ >+ IC_VEX_W_OPSIZE, /* 13916 */ >+ IC_VEX_W_OPSIZE, /* 13917 */ >+ IC_VEX_W_OPSIZE, /* 13918 */ >+ IC_VEX_W_OPSIZE, /* 13919 */ >+ IC_VEX, /* 13920 */ >+ IC_VEX, /* 13921 */ >+ IC_VEX_XS, /* 13922 */ >+ IC_VEX_XS, /* 13923 */ >+ IC_VEX_XD, /* 13924 */ >+ IC_VEX_XD, /* 13925 */ >+ IC_VEX_XD, /* 13926 */ >+ IC_VEX_XD, /* 13927 */ >+ IC_VEX_W, /* 13928 */ >+ IC_VEX_W, /* 13929 */ >+ IC_VEX_W_XS, /* 13930 */ >+ IC_VEX_W_XS, /* 13931 */ >+ IC_VEX_W_XD, /* 13932 */ >+ IC_VEX_W_XD, /* 13933 */ >+ IC_VEX_W_XD, /* 13934 */ >+ IC_VEX_W_XD, /* 13935 */ >+ IC_VEX_OPSIZE, /* 13936 */ >+ IC_VEX_OPSIZE, /* 13937 */ >+ IC_VEX_OPSIZE, /* 13938 */ >+ IC_VEX_OPSIZE, /* 13939 */ >+ IC_VEX_OPSIZE, /* 13940 */ >+ IC_VEX_OPSIZE, /* 13941 */ >+ IC_VEX_OPSIZE, /* 13942 */ >+ IC_VEX_OPSIZE, /* 13943 */ >+ IC_VEX_W_OPSIZE, /* 13944 */ >+ IC_VEX_W_OPSIZE, /* 13945 */ >+ IC_VEX_W_OPSIZE, /* 13946 */ >+ IC_VEX_W_OPSIZE, /* 13947 */ >+ IC_VEX_W_OPSIZE, /* 13948 */ >+ IC_VEX_W_OPSIZE, /* 13949 */ >+ IC_VEX_W_OPSIZE, /* 13950 */ >+ IC_VEX_W_OPSIZE, /* 13951 */ >+ IC_VEX_L, /* 13952 */ >+ IC_VEX_L, /* 13953 */ >+ IC_VEX_L_XS, /* 13954 */ >+ IC_VEX_L_XS, /* 13955 */ >+ IC_VEX_L_XD, /* 13956 */ >+ IC_VEX_L_XD, /* 13957 */ >+ IC_VEX_L_XD, /* 13958 */ >+ IC_VEX_L_XD, /* 13959 */ >+ IC_VEX_L_W, /* 13960 */ >+ IC_VEX_L_W, /* 13961 */ >+ IC_VEX_L_W_XS, /* 13962 */ >+ IC_VEX_L_W_XS, /* 13963 */ >+ IC_VEX_L_W_XD, /* 13964 */ >+ IC_VEX_L_W_XD, /* 13965 */ >+ IC_VEX_L_W_XD, /* 13966 */ >+ IC_VEX_L_W_XD, /* 13967 */ >+ IC_VEX_L_OPSIZE, /* 13968 */ >+ IC_VEX_L_OPSIZE, /* 13969 */ >+ IC_VEX_L_OPSIZE, /* 13970 */ >+ IC_VEX_L_OPSIZE, /* 13971 */ >+ IC_VEX_L_OPSIZE, /* 13972 */ >+ IC_VEX_L_OPSIZE, /* 13973 */ >+ IC_VEX_L_OPSIZE, /* 13974 */ >+ IC_VEX_L_OPSIZE, /* 13975 */ >+ IC_VEX_L_W_OPSIZE, /* 13976 */ >+ IC_VEX_L_W_OPSIZE, /* 13977 */ >+ IC_VEX_L_W_OPSIZE, /* 13978 */ >+ IC_VEX_L_W_OPSIZE, /* 13979 */ >+ IC_VEX_L_W_OPSIZE, /* 13980 */ >+ IC_VEX_L_W_OPSIZE, /* 13981 */ >+ IC_VEX_L_W_OPSIZE, /* 13982 */ >+ IC_VEX_L_W_OPSIZE, /* 13983 */ >+ IC_VEX_L, /* 13984 */ >+ IC_VEX_L, /* 13985 */ >+ IC_VEX_L_XS, /* 13986 */ >+ IC_VEX_L_XS, /* 13987 */ >+ IC_VEX_L_XD, /* 13988 */ >+ IC_VEX_L_XD, /* 13989 */ >+ IC_VEX_L_XD, /* 13990 */ >+ IC_VEX_L_XD, /* 13991 */ >+ IC_VEX_L_W, /* 13992 */ >+ IC_VEX_L_W, /* 13993 */ >+ IC_VEX_L_W_XS, /* 13994 */ >+ IC_VEX_L_W_XS, /* 13995 */ >+ IC_VEX_L_W_XD, /* 13996 */ >+ IC_VEX_L_W_XD, /* 13997 */ >+ IC_VEX_L_W_XD, /* 13998 */ >+ IC_VEX_L_W_XD, /* 13999 */ >+ IC_VEX_L_OPSIZE, /* 14000 */ >+ IC_VEX_L_OPSIZE, /* 14001 */ >+ IC_VEX_L_OPSIZE, /* 14002 */ >+ IC_VEX_L_OPSIZE, /* 14003 */ >+ IC_VEX_L_OPSIZE, /* 14004 */ >+ IC_VEX_L_OPSIZE, /* 14005 */ >+ IC_VEX_L_OPSIZE, /* 14006 */ >+ IC_VEX_L_OPSIZE, /* 14007 */ >+ IC_VEX_L_W_OPSIZE, /* 14008 */ >+ IC_VEX_L_W_OPSIZE, /* 14009 */ >+ IC_VEX_L_W_OPSIZE, /* 14010 */ >+ IC_VEX_L_W_OPSIZE, /* 14011 */ >+ IC_VEX_L_W_OPSIZE, /* 14012 */ >+ IC_VEX_L_W_OPSIZE, /* 14013 */ >+ IC_VEX_L_W_OPSIZE, /* 14014 */ >+ IC_VEX_L_W_OPSIZE, /* 14015 */ >+ IC_VEX_L, /* 14016 */ >+ IC_VEX_L, /* 14017 */ >+ IC_VEX_L_XS, /* 14018 */ >+ IC_VEX_L_XS, /* 14019 */ >+ IC_VEX_L_XD, /* 14020 */ >+ IC_VEX_L_XD, /* 14021 */ >+ IC_VEX_L_XD, /* 14022 */ >+ IC_VEX_L_XD, /* 14023 */ >+ IC_VEX_L_W, /* 14024 */ >+ IC_VEX_L_W, /* 14025 */ >+ IC_VEX_L_W_XS, /* 14026 */ >+ IC_VEX_L_W_XS, /* 14027 */ >+ IC_VEX_L_W_XD, /* 14028 */ >+ IC_VEX_L_W_XD, /* 14029 */ >+ IC_VEX_L_W_XD, /* 14030 */ >+ IC_VEX_L_W_XD, /* 14031 */ >+ IC_VEX_L_OPSIZE, /* 14032 */ >+ IC_VEX_L_OPSIZE, /* 14033 */ >+ IC_VEX_L_OPSIZE, /* 14034 */ >+ IC_VEX_L_OPSIZE, /* 14035 */ >+ IC_VEX_L_OPSIZE, /* 14036 */ >+ IC_VEX_L_OPSIZE, /* 14037 */ >+ IC_VEX_L_OPSIZE, /* 14038 */ >+ IC_VEX_L_OPSIZE, /* 14039 */ >+ IC_VEX_L_W_OPSIZE, /* 14040 */ >+ IC_VEX_L_W_OPSIZE, /* 14041 */ >+ IC_VEX_L_W_OPSIZE, /* 14042 */ >+ IC_VEX_L_W_OPSIZE, /* 14043 */ >+ IC_VEX_L_W_OPSIZE, /* 14044 */ >+ IC_VEX_L_W_OPSIZE, /* 14045 */ >+ IC_VEX_L_W_OPSIZE, /* 14046 */ >+ IC_VEX_L_W_OPSIZE, /* 14047 */ >+ IC_VEX_L, /* 14048 */ >+ IC_VEX_L, /* 14049 */ >+ IC_VEX_L_XS, /* 14050 */ >+ IC_VEX_L_XS, /* 14051 */ >+ IC_VEX_L_XD, /* 14052 */ >+ IC_VEX_L_XD, /* 14053 */ >+ IC_VEX_L_XD, /* 14054 */ >+ IC_VEX_L_XD, /* 14055 */ >+ IC_VEX_L_W, /* 14056 */ >+ IC_VEX_L_W, /* 14057 */ >+ IC_VEX_L_W_XS, /* 14058 */ >+ IC_VEX_L_W_XS, /* 14059 */ >+ IC_VEX_L_W_XD, /* 14060 */ >+ IC_VEX_L_W_XD, /* 14061 */ >+ IC_VEX_L_W_XD, /* 14062 */ >+ IC_VEX_L_W_XD, /* 14063 */ >+ IC_VEX_L_OPSIZE, /* 14064 */ >+ IC_VEX_L_OPSIZE, /* 14065 */ >+ IC_VEX_L_OPSIZE, /* 14066 */ >+ IC_VEX_L_OPSIZE, /* 14067 */ >+ IC_VEX_L_OPSIZE, /* 14068 */ >+ IC_VEX_L_OPSIZE, /* 14069 */ >+ IC_VEX_L_OPSIZE, /* 14070 */ >+ IC_VEX_L_OPSIZE, /* 14071 */ >+ IC_VEX_L_W_OPSIZE, /* 14072 */ >+ IC_VEX_L_W_OPSIZE, /* 14073 */ >+ IC_VEX_L_W_OPSIZE, /* 14074 */ >+ IC_VEX_L_W_OPSIZE, /* 14075 */ >+ IC_VEX_L_W_OPSIZE, /* 14076 */ >+ IC_VEX_L_W_OPSIZE, /* 14077 */ >+ IC_VEX_L_W_OPSIZE, /* 14078 */ >+ IC_VEX_L_W_OPSIZE, /* 14079 */ >+ IC_EVEX_L2_KZ_B, /* 14080 */ >+ IC_EVEX_L2_KZ_B, /* 14081 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14082 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14083 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14084 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14085 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14086 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14087 */ >+ IC_EVEX_L2_W_KZ_B, /* 14088 */ >+ IC_EVEX_L2_W_KZ_B, /* 14089 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14090 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14091 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14092 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14093 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14094 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14095 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14096 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14097 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14098 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14099 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14100 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14101 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14102 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14103 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14104 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14105 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14106 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14107 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14108 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14109 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14110 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14111 */ >+ IC_EVEX_L2_KZ_B, /* 14112 */ >+ IC_EVEX_L2_KZ_B, /* 14113 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14114 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14115 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14116 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14117 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14118 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14119 */ >+ IC_EVEX_L2_W_KZ_B, /* 14120 */ >+ IC_EVEX_L2_W_KZ_B, /* 14121 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14122 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14123 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14124 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14125 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14126 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14127 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14128 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14129 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14130 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14131 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14132 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14133 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14134 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14135 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14136 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14137 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14138 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14139 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14140 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14141 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14142 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14143 */ >+ IC_EVEX_L2_KZ_B, /* 14144 */ >+ IC_EVEX_L2_KZ_B, /* 14145 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14146 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14147 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14148 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14149 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14150 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14151 */ >+ IC_EVEX_L2_W_KZ_B, /* 14152 */ >+ IC_EVEX_L2_W_KZ_B, /* 14153 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14154 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14155 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14156 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14157 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14158 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14159 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14160 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14161 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14162 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14163 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14164 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14165 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14166 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14167 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14168 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14169 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14170 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14171 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14172 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14173 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14174 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14175 */ >+ IC_EVEX_L2_KZ_B, /* 14176 */ >+ IC_EVEX_L2_KZ_B, /* 14177 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14178 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14179 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14180 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14181 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14182 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14183 */ >+ IC_EVEX_L2_W_KZ_B, /* 14184 */ >+ IC_EVEX_L2_W_KZ_B, /* 14185 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14186 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14187 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14188 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14189 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14190 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14191 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14192 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14193 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14194 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14195 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14196 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14197 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14198 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14199 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14200 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14201 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14202 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14203 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14204 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14205 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14206 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14207 */ >+ IC_EVEX_L2_KZ_B, /* 14208 */ >+ IC_EVEX_L2_KZ_B, /* 14209 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14210 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14211 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14212 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14213 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14214 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14215 */ >+ IC_EVEX_L2_W_KZ_B, /* 14216 */ >+ IC_EVEX_L2_W_KZ_B, /* 14217 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14218 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14219 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14220 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14221 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14222 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14223 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14224 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14225 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14226 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14227 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14228 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14229 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14230 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14231 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14232 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14233 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14234 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14235 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14236 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14237 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14238 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14239 */ >+ IC_EVEX_L2_KZ_B, /* 14240 */ >+ IC_EVEX_L2_KZ_B, /* 14241 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14242 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14243 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14244 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14245 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14246 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14247 */ >+ IC_EVEX_L2_W_KZ_B, /* 14248 */ >+ IC_EVEX_L2_W_KZ_B, /* 14249 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14250 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14251 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14252 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14253 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14254 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14255 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14256 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14257 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14258 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14259 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14260 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14261 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14262 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14263 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14264 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14265 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14266 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14267 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14268 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14269 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14270 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14271 */ >+ IC_EVEX_L2_KZ_B, /* 14272 */ >+ IC_EVEX_L2_KZ_B, /* 14273 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14274 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14275 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14276 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14277 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14278 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14279 */ >+ IC_EVEX_L2_W_KZ_B, /* 14280 */ >+ IC_EVEX_L2_W_KZ_B, /* 14281 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14282 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14283 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14284 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14285 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14286 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14287 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14288 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14289 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14290 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14291 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14292 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14293 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14294 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14295 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14296 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14297 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14298 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14299 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14300 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14301 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14302 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14303 */ >+ IC_EVEX_L2_KZ_B, /* 14304 */ >+ IC_EVEX_L2_KZ_B, /* 14305 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14306 */ >+ IC_EVEX_L2_XS_KZ_B, /* 14307 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14308 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14309 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14310 */ >+ IC_EVEX_L2_XD_KZ_B, /* 14311 */ >+ IC_EVEX_L2_W_KZ_B, /* 14312 */ >+ IC_EVEX_L2_W_KZ_B, /* 14313 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14314 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 14315 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14316 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14317 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14318 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 14319 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14320 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14321 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14322 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14323 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14324 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14325 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14326 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 14327 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14328 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14329 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14330 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14331 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14332 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14333 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14334 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 14335 */ >+ IC, /* 14336 */ >+ IC_64BIT, /* 14337 */ >+ IC_XS, /* 14338 */ >+ IC_64BIT_XS, /* 14339 */ >+ IC_XD, /* 14340 */ >+ IC_64BIT_XD, /* 14341 */ >+ IC_XS, /* 14342 */ >+ IC_64BIT_XS, /* 14343 */ >+ IC, /* 14344 */ >+ IC_64BIT_REXW, /* 14345 */ >+ IC_XS, /* 14346 */ >+ IC_64BIT_REXW_XS, /* 14347 */ >+ IC_XD, /* 14348 */ >+ IC_64BIT_REXW_XD, /* 14349 */ >+ IC_XS, /* 14350 */ >+ IC_64BIT_REXW_XS, /* 14351 */ >+ IC_OPSIZE, /* 14352 */ >+ IC_64BIT_OPSIZE, /* 14353 */ >+ IC_XS_OPSIZE, /* 14354 */ >+ IC_64BIT_XS_OPSIZE, /* 14355 */ >+ IC_XD_OPSIZE, /* 14356 */ >+ IC_64BIT_XD_OPSIZE, /* 14357 */ >+ IC_XS_OPSIZE, /* 14358 */ >+ IC_64BIT_XD_OPSIZE, /* 14359 */ >+ IC_OPSIZE, /* 14360 */ >+ IC_64BIT_REXW_OPSIZE, /* 14361 */ >+ IC_XS_OPSIZE, /* 14362 */ >+ IC_64BIT_REXW_XS, /* 14363 */ >+ IC_XD_OPSIZE, /* 14364 */ >+ IC_64BIT_REXW_XD, /* 14365 */ >+ IC_XS_OPSIZE, /* 14366 */ >+ IC_64BIT_REXW_XS, /* 14367 */ >+ IC_ADSIZE, /* 14368 */ >+ IC_64BIT_ADSIZE, /* 14369 */ >+ IC_XS, /* 14370 */ >+ IC_64BIT_XS, /* 14371 */ >+ IC_XD, /* 14372 */ >+ IC_64BIT_XD, /* 14373 */ >+ IC_XS, /* 14374 */ >+ IC_64BIT_XS, /* 14375 */ >+ IC_ADSIZE, /* 14376 */ >+ IC_64BIT_ADSIZE, /* 14377 */ >+ IC_XS, /* 14378 */ >+ IC_64BIT_REXW_XS, /* 14379 */ >+ IC_XD, /* 14380 */ >+ IC_64BIT_REXW_XD, /* 14381 */ >+ IC_XS, /* 14382 */ >+ IC_64BIT_REXW_XS, /* 14383 */ >+ IC_OPSIZE, /* 14384 */ >+ IC_64BIT_OPSIZE, /* 14385 */ >+ IC_XS_OPSIZE, /* 14386 */ >+ IC_64BIT_XS_OPSIZE, /* 14387 */ >+ IC_XD_OPSIZE, /* 14388 */ >+ IC_64BIT_XD_OPSIZE, /* 14389 */ >+ IC_XS_OPSIZE, /* 14390 */ >+ IC_64BIT_XD_OPSIZE, /* 14391 */ >+ IC_OPSIZE, /* 14392 */ >+ IC_64BIT_REXW_OPSIZE, /* 14393 */ >+ IC_XS_OPSIZE, /* 14394 */ >+ IC_64BIT_REXW_XS, /* 14395 */ >+ IC_XD_OPSIZE, /* 14396 */ >+ IC_64BIT_REXW_XD, /* 14397 */ >+ IC_XS_OPSIZE, /* 14398 */ >+ IC_64BIT_REXW_XS, /* 14399 */ >+ IC_VEX, /* 14400 */ >+ IC_VEX, /* 14401 */ >+ IC_VEX_XS, /* 14402 */ >+ IC_VEX_XS, /* 14403 */ >+ IC_VEX_XD, /* 14404 */ >+ IC_VEX_XD, /* 14405 */ >+ IC_VEX_XD, /* 14406 */ >+ IC_VEX_XD, /* 14407 */ >+ IC_VEX_W, /* 14408 */ >+ IC_VEX_W, /* 14409 */ >+ IC_VEX_W_XS, /* 14410 */ >+ IC_VEX_W_XS, /* 14411 */ >+ IC_VEX_W_XD, /* 14412 */ >+ IC_VEX_W_XD, /* 14413 */ >+ IC_VEX_W_XD, /* 14414 */ >+ IC_VEX_W_XD, /* 14415 */ >+ IC_VEX_OPSIZE, /* 14416 */ >+ IC_VEX_OPSIZE, /* 14417 */ >+ IC_VEX_OPSIZE, /* 14418 */ >+ IC_VEX_OPSIZE, /* 14419 */ >+ IC_VEX_OPSIZE, /* 14420 */ >+ IC_VEX_OPSIZE, /* 14421 */ >+ IC_VEX_OPSIZE, /* 14422 */ >+ IC_VEX_OPSIZE, /* 14423 */ >+ IC_VEX_W_OPSIZE, /* 14424 */ >+ IC_VEX_W_OPSIZE, /* 14425 */ >+ IC_VEX_W_OPSIZE, /* 14426 */ >+ IC_VEX_W_OPSIZE, /* 14427 */ >+ IC_VEX_W_OPSIZE, /* 14428 */ >+ IC_VEX_W_OPSIZE, /* 14429 */ >+ IC_VEX_W_OPSIZE, /* 14430 */ >+ IC_VEX_W_OPSIZE, /* 14431 */ >+ IC_VEX, /* 14432 */ >+ IC_VEX, /* 14433 */ >+ IC_VEX_XS, /* 14434 */ >+ IC_VEX_XS, /* 14435 */ >+ IC_VEX_XD, /* 14436 */ >+ IC_VEX_XD, /* 14437 */ >+ IC_VEX_XD, /* 14438 */ >+ IC_VEX_XD, /* 14439 */ >+ IC_VEX_W, /* 14440 */ >+ IC_VEX_W, /* 14441 */ >+ IC_VEX_W_XS, /* 14442 */ >+ IC_VEX_W_XS, /* 14443 */ >+ IC_VEX_W_XD, /* 14444 */ >+ IC_VEX_W_XD, /* 14445 */ >+ IC_VEX_W_XD, /* 14446 */ >+ IC_VEX_W_XD, /* 14447 */ >+ IC_VEX_OPSIZE, /* 14448 */ >+ IC_VEX_OPSIZE, /* 14449 */ >+ IC_VEX_OPSIZE, /* 14450 */ >+ IC_VEX_OPSIZE, /* 14451 */ >+ IC_VEX_OPSIZE, /* 14452 */ >+ IC_VEX_OPSIZE, /* 14453 */ >+ IC_VEX_OPSIZE, /* 14454 */ >+ IC_VEX_OPSIZE, /* 14455 */ >+ IC_VEX_W_OPSIZE, /* 14456 */ >+ IC_VEX_W_OPSIZE, /* 14457 */ >+ IC_VEX_W_OPSIZE, /* 14458 */ >+ IC_VEX_W_OPSIZE, /* 14459 */ >+ IC_VEX_W_OPSIZE, /* 14460 */ >+ IC_VEX_W_OPSIZE, /* 14461 */ >+ IC_VEX_W_OPSIZE, /* 14462 */ >+ IC_VEX_W_OPSIZE, /* 14463 */ >+ IC_VEX_L, /* 14464 */ >+ IC_VEX_L, /* 14465 */ >+ IC_VEX_L_XS, /* 14466 */ >+ IC_VEX_L_XS, /* 14467 */ >+ IC_VEX_L_XD, /* 14468 */ >+ IC_VEX_L_XD, /* 14469 */ >+ IC_VEX_L_XD, /* 14470 */ >+ IC_VEX_L_XD, /* 14471 */ >+ IC_VEX_L_W, /* 14472 */ >+ IC_VEX_L_W, /* 14473 */ >+ IC_VEX_L_W_XS, /* 14474 */ >+ IC_VEX_L_W_XS, /* 14475 */ >+ IC_VEX_L_W_XD, /* 14476 */ >+ IC_VEX_L_W_XD, /* 14477 */ >+ IC_VEX_L_W_XD, /* 14478 */ >+ IC_VEX_L_W_XD, /* 14479 */ >+ IC_VEX_L_OPSIZE, /* 14480 */ >+ IC_VEX_L_OPSIZE, /* 14481 */ >+ IC_VEX_L_OPSIZE, /* 14482 */ >+ IC_VEX_L_OPSIZE, /* 14483 */ >+ IC_VEX_L_OPSIZE, /* 14484 */ >+ IC_VEX_L_OPSIZE, /* 14485 */ >+ IC_VEX_L_OPSIZE, /* 14486 */ >+ IC_VEX_L_OPSIZE, /* 14487 */ >+ IC_VEX_L_W_OPSIZE, /* 14488 */ >+ IC_VEX_L_W_OPSIZE, /* 14489 */ >+ IC_VEX_L_W_OPSIZE, /* 14490 */ >+ IC_VEX_L_W_OPSIZE, /* 14491 */ >+ IC_VEX_L_W_OPSIZE, /* 14492 */ >+ IC_VEX_L_W_OPSIZE, /* 14493 */ >+ IC_VEX_L_W_OPSIZE, /* 14494 */ >+ IC_VEX_L_W_OPSIZE, /* 14495 */ >+ IC_VEX_L, /* 14496 */ >+ IC_VEX_L, /* 14497 */ >+ IC_VEX_L_XS, /* 14498 */ >+ IC_VEX_L_XS, /* 14499 */ >+ IC_VEX_L_XD, /* 14500 */ >+ IC_VEX_L_XD, /* 14501 */ >+ IC_VEX_L_XD, /* 14502 */ >+ IC_VEX_L_XD, /* 14503 */ >+ IC_VEX_L_W, /* 14504 */ >+ IC_VEX_L_W, /* 14505 */ >+ IC_VEX_L_W_XS, /* 14506 */ >+ IC_VEX_L_W_XS, /* 14507 */ >+ IC_VEX_L_W_XD, /* 14508 */ >+ IC_VEX_L_W_XD, /* 14509 */ >+ IC_VEX_L_W_XD, /* 14510 */ >+ IC_VEX_L_W_XD, /* 14511 */ >+ IC_VEX_L_OPSIZE, /* 14512 */ >+ IC_VEX_L_OPSIZE, /* 14513 */ >+ IC_VEX_L_OPSIZE, /* 14514 */ >+ IC_VEX_L_OPSIZE, /* 14515 */ >+ IC_VEX_L_OPSIZE, /* 14516 */ >+ IC_VEX_L_OPSIZE, /* 14517 */ >+ IC_VEX_L_OPSIZE, /* 14518 */ >+ IC_VEX_L_OPSIZE, /* 14519 */ >+ IC_VEX_L_W_OPSIZE, /* 14520 */ >+ IC_VEX_L_W_OPSIZE, /* 14521 */ >+ IC_VEX_L_W_OPSIZE, /* 14522 */ >+ IC_VEX_L_W_OPSIZE, /* 14523 */ >+ IC_VEX_L_W_OPSIZE, /* 14524 */ >+ IC_VEX_L_W_OPSIZE, /* 14525 */ >+ IC_VEX_L_W_OPSIZE, /* 14526 */ >+ IC_VEX_L_W_OPSIZE, /* 14527 */ >+ IC_VEX_L, /* 14528 */ >+ IC_VEX_L, /* 14529 */ >+ IC_VEX_L_XS, /* 14530 */ >+ IC_VEX_L_XS, /* 14531 */ >+ IC_VEX_L_XD, /* 14532 */ >+ IC_VEX_L_XD, /* 14533 */ >+ IC_VEX_L_XD, /* 14534 */ >+ IC_VEX_L_XD, /* 14535 */ >+ IC_VEX_L_W, /* 14536 */ >+ IC_VEX_L_W, /* 14537 */ >+ IC_VEX_L_W_XS, /* 14538 */ >+ IC_VEX_L_W_XS, /* 14539 */ >+ IC_VEX_L_W_XD, /* 14540 */ >+ IC_VEX_L_W_XD, /* 14541 */ >+ IC_VEX_L_W_XD, /* 14542 */ >+ IC_VEX_L_W_XD, /* 14543 */ >+ IC_VEX_L_OPSIZE, /* 14544 */ >+ IC_VEX_L_OPSIZE, /* 14545 */ >+ IC_VEX_L_OPSIZE, /* 14546 */ >+ IC_VEX_L_OPSIZE, /* 14547 */ >+ IC_VEX_L_OPSIZE, /* 14548 */ >+ IC_VEX_L_OPSIZE, /* 14549 */ >+ IC_VEX_L_OPSIZE, /* 14550 */ >+ IC_VEX_L_OPSIZE, /* 14551 */ >+ IC_VEX_L_W_OPSIZE, /* 14552 */ >+ IC_VEX_L_W_OPSIZE, /* 14553 */ >+ IC_VEX_L_W_OPSIZE, /* 14554 */ >+ IC_VEX_L_W_OPSIZE, /* 14555 */ >+ IC_VEX_L_W_OPSIZE, /* 14556 */ >+ IC_VEX_L_W_OPSIZE, /* 14557 */ >+ IC_VEX_L_W_OPSIZE, /* 14558 */ >+ IC_VEX_L_W_OPSIZE, /* 14559 */ >+ IC_VEX_L, /* 14560 */ >+ IC_VEX_L, /* 14561 */ >+ IC_VEX_L_XS, /* 14562 */ >+ IC_VEX_L_XS, /* 14563 */ >+ IC_VEX_L_XD, /* 14564 */ >+ IC_VEX_L_XD, /* 14565 */ >+ IC_VEX_L_XD, /* 14566 */ >+ IC_VEX_L_XD, /* 14567 */ >+ IC_VEX_L_W, /* 14568 */ >+ IC_VEX_L_W, /* 14569 */ >+ IC_VEX_L_W_XS, /* 14570 */ >+ IC_VEX_L_W_XS, /* 14571 */ >+ IC_VEX_L_W_XD, /* 14572 */ >+ IC_VEX_L_W_XD, /* 14573 */ >+ IC_VEX_L_W_XD, /* 14574 */ >+ IC_VEX_L_W_XD, /* 14575 */ >+ IC_VEX_L_OPSIZE, /* 14576 */ >+ IC_VEX_L_OPSIZE, /* 14577 */ >+ IC_VEX_L_OPSIZE, /* 14578 */ >+ IC_VEX_L_OPSIZE, /* 14579 */ >+ IC_VEX_L_OPSIZE, /* 14580 */ >+ IC_VEX_L_OPSIZE, /* 14581 */ >+ IC_VEX_L_OPSIZE, /* 14582 */ >+ IC_VEX_L_OPSIZE, /* 14583 */ >+ IC_VEX_L_W_OPSIZE, /* 14584 */ >+ IC_VEX_L_W_OPSIZE, /* 14585 */ >+ IC_VEX_L_W_OPSIZE, /* 14586 */ >+ IC_VEX_L_W_OPSIZE, /* 14587 */ >+ IC_VEX_L_W_OPSIZE, /* 14588 */ >+ IC_VEX_L_W_OPSIZE, /* 14589 */ >+ IC_VEX_L_W_OPSIZE, /* 14590 */ >+ IC_VEX_L_W_OPSIZE, /* 14591 */ >+ IC_EVEX_KZ_B, /* 14592 */ >+ IC_EVEX_KZ_B, /* 14593 */ >+ IC_EVEX_XS_KZ_B, /* 14594 */ >+ IC_EVEX_XS_KZ_B, /* 14595 */ >+ IC_EVEX_XD_KZ_B, /* 14596 */ >+ IC_EVEX_XD_KZ_B, /* 14597 */ >+ IC_EVEX_XD_KZ_B, /* 14598 */ >+ IC_EVEX_XD_KZ_B, /* 14599 */ >+ IC_EVEX_W_KZ_B, /* 14600 */ >+ IC_EVEX_W_KZ_B, /* 14601 */ >+ IC_EVEX_W_XS_KZ_B, /* 14602 */ >+ IC_EVEX_W_XS_KZ_B, /* 14603 */ >+ IC_EVEX_W_XD_KZ_B, /* 14604 */ >+ IC_EVEX_W_XD_KZ_B, /* 14605 */ >+ IC_EVEX_W_XD_KZ_B, /* 14606 */ >+ IC_EVEX_W_XD_KZ_B, /* 14607 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14608 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14609 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14610 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14611 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14612 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14613 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14614 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14615 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14616 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14617 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14618 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14619 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14620 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14621 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14622 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14623 */ >+ IC_EVEX_KZ_B, /* 14624 */ >+ IC_EVEX_KZ_B, /* 14625 */ >+ IC_EVEX_XS_KZ_B, /* 14626 */ >+ IC_EVEX_XS_KZ_B, /* 14627 */ >+ IC_EVEX_XD_KZ_B, /* 14628 */ >+ IC_EVEX_XD_KZ_B, /* 14629 */ >+ IC_EVEX_XD_KZ_B, /* 14630 */ >+ IC_EVEX_XD_KZ_B, /* 14631 */ >+ IC_EVEX_W_KZ_B, /* 14632 */ >+ IC_EVEX_W_KZ_B, /* 14633 */ >+ IC_EVEX_W_XS_KZ_B, /* 14634 */ >+ IC_EVEX_W_XS_KZ_B, /* 14635 */ >+ IC_EVEX_W_XD_KZ_B, /* 14636 */ >+ IC_EVEX_W_XD_KZ_B, /* 14637 */ >+ IC_EVEX_W_XD_KZ_B, /* 14638 */ >+ IC_EVEX_W_XD_KZ_B, /* 14639 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14640 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14641 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14642 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14643 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14644 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14645 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14646 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14647 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14648 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14649 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14650 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14651 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14652 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14653 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14654 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14655 */ >+ IC_EVEX_KZ_B, /* 14656 */ >+ IC_EVEX_KZ_B, /* 14657 */ >+ IC_EVEX_XS_KZ_B, /* 14658 */ >+ IC_EVEX_XS_KZ_B, /* 14659 */ >+ IC_EVEX_XD_KZ_B, /* 14660 */ >+ IC_EVEX_XD_KZ_B, /* 14661 */ >+ IC_EVEX_XD_KZ_B, /* 14662 */ >+ IC_EVEX_XD_KZ_B, /* 14663 */ >+ IC_EVEX_W_KZ_B, /* 14664 */ >+ IC_EVEX_W_KZ_B, /* 14665 */ >+ IC_EVEX_W_XS_KZ_B, /* 14666 */ >+ IC_EVEX_W_XS_KZ_B, /* 14667 */ >+ IC_EVEX_W_XD_KZ_B, /* 14668 */ >+ IC_EVEX_W_XD_KZ_B, /* 14669 */ >+ IC_EVEX_W_XD_KZ_B, /* 14670 */ >+ IC_EVEX_W_XD_KZ_B, /* 14671 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14672 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14673 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14674 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14675 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14676 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14677 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14678 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14679 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14680 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14681 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14682 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14683 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14684 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14685 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14686 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14687 */ >+ IC_EVEX_KZ_B, /* 14688 */ >+ IC_EVEX_KZ_B, /* 14689 */ >+ IC_EVEX_XS_KZ_B, /* 14690 */ >+ IC_EVEX_XS_KZ_B, /* 14691 */ >+ IC_EVEX_XD_KZ_B, /* 14692 */ >+ IC_EVEX_XD_KZ_B, /* 14693 */ >+ IC_EVEX_XD_KZ_B, /* 14694 */ >+ IC_EVEX_XD_KZ_B, /* 14695 */ >+ IC_EVEX_W_KZ_B, /* 14696 */ >+ IC_EVEX_W_KZ_B, /* 14697 */ >+ IC_EVEX_W_XS_KZ_B, /* 14698 */ >+ IC_EVEX_W_XS_KZ_B, /* 14699 */ >+ IC_EVEX_W_XD_KZ_B, /* 14700 */ >+ IC_EVEX_W_XD_KZ_B, /* 14701 */ >+ IC_EVEX_W_XD_KZ_B, /* 14702 */ >+ IC_EVEX_W_XD_KZ_B, /* 14703 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14704 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14705 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14706 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14707 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14708 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14709 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14710 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14711 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14712 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14713 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14714 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14715 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14716 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14717 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14718 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14719 */ >+ IC_EVEX_KZ_B, /* 14720 */ >+ IC_EVEX_KZ_B, /* 14721 */ >+ IC_EVEX_XS_KZ_B, /* 14722 */ >+ IC_EVEX_XS_KZ_B, /* 14723 */ >+ IC_EVEX_XD_KZ_B, /* 14724 */ >+ IC_EVEX_XD_KZ_B, /* 14725 */ >+ IC_EVEX_XD_KZ_B, /* 14726 */ >+ IC_EVEX_XD_KZ_B, /* 14727 */ >+ IC_EVEX_W_KZ_B, /* 14728 */ >+ IC_EVEX_W_KZ_B, /* 14729 */ >+ IC_EVEX_W_XS_KZ_B, /* 14730 */ >+ IC_EVEX_W_XS_KZ_B, /* 14731 */ >+ IC_EVEX_W_XD_KZ_B, /* 14732 */ >+ IC_EVEX_W_XD_KZ_B, /* 14733 */ >+ IC_EVEX_W_XD_KZ_B, /* 14734 */ >+ IC_EVEX_W_XD_KZ_B, /* 14735 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14736 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14737 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14738 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14739 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14740 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14741 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14742 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14743 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14744 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14745 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14746 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14747 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14748 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14749 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14750 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14751 */ >+ IC_EVEX_KZ_B, /* 14752 */ >+ IC_EVEX_KZ_B, /* 14753 */ >+ IC_EVEX_XS_KZ_B, /* 14754 */ >+ IC_EVEX_XS_KZ_B, /* 14755 */ >+ IC_EVEX_XD_KZ_B, /* 14756 */ >+ IC_EVEX_XD_KZ_B, /* 14757 */ >+ IC_EVEX_XD_KZ_B, /* 14758 */ >+ IC_EVEX_XD_KZ_B, /* 14759 */ >+ IC_EVEX_W_KZ_B, /* 14760 */ >+ IC_EVEX_W_KZ_B, /* 14761 */ >+ IC_EVEX_W_XS_KZ_B, /* 14762 */ >+ IC_EVEX_W_XS_KZ_B, /* 14763 */ >+ IC_EVEX_W_XD_KZ_B, /* 14764 */ >+ IC_EVEX_W_XD_KZ_B, /* 14765 */ >+ IC_EVEX_W_XD_KZ_B, /* 14766 */ >+ IC_EVEX_W_XD_KZ_B, /* 14767 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14768 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14769 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14770 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14771 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14772 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14773 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14774 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14775 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14776 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14777 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14778 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14779 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14780 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14781 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14782 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14783 */ >+ IC_EVEX_KZ_B, /* 14784 */ >+ IC_EVEX_KZ_B, /* 14785 */ >+ IC_EVEX_XS_KZ_B, /* 14786 */ >+ IC_EVEX_XS_KZ_B, /* 14787 */ >+ IC_EVEX_XD_KZ_B, /* 14788 */ >+ IC_EVEX_XD_KZ_B, /* 14789 */ >+ IC_EVEX_XD_KZ_B, /* 14790 */ >+ IC_EVEX_XD_KZ_B, /* 14791 */ >+ IC_EVEX_W_KZ_B, /* 14792 */ >+ IC_EVEX_W_KZ_B, /* 14793 */ >+ IC_EVEX_W_XS_KZ_B, /* 14794 */ >+ IC_EVEX_W_XS_KZ_B, /* 14795 */ >+ IC_EVEX_W_XD_KZ_B, /* 14796 */ >+ IC_EVEX_W_XD_KZ_B, /* 14797 */ >+ IC_EVEX_W_XD_KZ_B, /* 14798 */ >+ IC_EVEX_W_XD_KZ_B, /* 14799 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14800 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14801 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14802 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14803 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14804 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14805 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14806 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14807 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14808 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14809 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14810 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14811 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14812 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14813 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14814 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14815 */ >+ IC_EVEX_KZ_B, /* 14816 */ >+ IC_EVEX_KZ_B, /* 14817 */ >+ IC_EVEX_XS_KZ_B, /* 14818 */ >+ IC_EVEX_XS_KZ_B, /* 14819 */ >+ IC_EVEX_XD_KZ_B, /* 14820 */ >+ IC_EVEX_XD_KZ_B, /* 14821 */ >+ IC_EVEX_XD_KZ_B, /* 14822 */ >+ IC_EVEX_XD_KZ_B, /* 14823 */ >+ IC_EVEX_W_KZ_B, /* 14824 */ >+ IC_EVEX_W_KZ_B, /* 14825 */ >+ IC_EVEX_W_XS_KZ_B, /* 14826 */ >+ IC_EVEX_W_XS_KZ_B, /* 14827 */ >+ IC_EVEX_W_XD_KZ_B, /* 14828 */ >+ IC_EVEX_W_XD_KZ_B, /* 14829 */ >+ IC_EVEX_W_XD_KZ_B, /* 14830 */ >+ IC_EVEX_W_XD_KZ_B, /* 14831 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14832 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14833 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14834 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14835 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14836 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14837 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14838 */ >+ IC_EVEX_OPSIZE_KZ_B, /* 14839 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14840 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14841 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14842 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14843 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14844 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14845 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14846 */ >+ IC_EVEX_W_OPSIZE_KZ_B, /* 14847 */ >+ IC, /* 14848 */ >+ IC_64BIT, /* 14849 */ >+ IC_XS, /* 14850 */ >+ IC_64BIT_XS, /* 14851 */ >+ IC_XD, /* 14852 */ >+ IC_64BIT_XD, /* 14853 */ >+ IC_XS, /* 14854 */ >+ IC_64BIT_XS, /* 14855 */ >+ IC, /* 14856 */ >+ IC_64BIT_REXW, /* 14857 */ >+ IC_XS, /* 14858 */ >+ IC_64BIT_REXW_XS, /* 14859 */ >+ IC_XD, /* 14860 */ >+ IC_64BIT_REXW_XD, /* 14861 */ >+ IC_XS, /* 14862 */ >+ IC_64BIT_REXW_XS, /* 14863 */ >+ IC_OPSIZE, /* 14864 */ >+ IC_64BIT_OPSIZE, /* 14865 */ >+ IC_XS_OPSIZE, /* 14866 */ >+ IC_64BIT_XS_OPSIZE, /* 14867 */ >+ IC_XD_OPSIZE, /* 14868 */ >+ IC_64BIT_XD_OPSIZE, /* 14869 */ >+ IC_XS_OPSIZE, /* 14870 */ >+ IC_64BIT_XD_OPSIZE, /* 14871 */ >+ IC_OPSIZE, /* 14872 */ >+ IC_64BIT_REXW_OPSIZE, /* 14873 */ >+ IC_XS_OPSIZE, /* 14874 */ >+ IC_64BIT_REXW_XS, /* 14875 */ >+ IC_XD_OPSIZE, /* 14876 */ >+ IC_64BIT_REXW_XD, /* 14877 */ >+ IC_XS_OPSIZE, /* 14878 */ >+ IC_64BIT_REXW_XS, /* 14879 */ >+ IC_ADSIZE, /* 14880 */ >+ IC_64BIT_ADSIZE, /* 14881 */ >+ IC_XS, /* 14882 */ >+ IC_64BIT_XS, /* 14883 */ >+ IC_XD, /* 14884 */ >+ IC_64BIT_XD, /* 14885 */ >+ IC_XS, /* 14886 */ >+ IC_64BIT_XS, /* 14887 */ >+ IC_ADSIZE, /* 14888 */ >+ IC_64BIT_ADSIZE, /* 14889 */ >+ IC_XS, /* 14890 */ >+ IC_64BIT_REXW_XS, /* 14891 */ >+ IC_XD, /* 14892 */ >+ IC_64BIT_REXW_XD, /* 14893 */ >+ IC_XS, /* 14894 */ >+ IC_64BIT_REXW_XS, /* 14895 */ >+ IC_OPSIZE, /* 14896 */ >+ IC_64BIT_OPSIZE, /* 14897 */ >+ IC_XS_OPSIZE, /* 14898 */ >+ IC_64BIT_XS_OPSIZE, /* 14899 */ >+ IC_XD_OPSIZE, /* 14900 */ >+ IC_64BIT_XD_OPSIZE, /* 14901 */ >+ IC_XS_OPSIZE, /* 14902 */ >+ IC_64BIT_XD_OPSIZE, /* 14903 */ >+ IC_OPSIZE, /* 14904 */ >+ IC_64BIT_REXW_OPSIZE, /* 14905 */ >+ IC_XS_OPSIZE, /* 14906 */ >+ IC_64BIT_REXW_XS, /* 14907 */ >+ IC_XD_OPSIZE, /* 14908 */ >+ IC_64BIT_REXW_XD, /* 14909 */ >+ IC_XS_OPSIZE, /* 14910 */ >+ IC_64BIT_REXW_XS, /* 14911 */ >+ IC_VEX, /* 14912 */ >+ IC_VEX, /* 14913 */ >+ IC_VEX_XS, /* 14914 */ >+ IC_VEX_XS, /* 14915 */ >+ IC_VEX_XD, /* 14916 */ >+ IC_VEX_XD, /* 14917 */ >+ IC_VEX_XD, /* 14918 */ >+ IC_VEX_XD, /* 14919 */ >+ IC_VEX_W, /* 14920 */ >+ IC_VEX_W, /* 14921 */ >+ IC_VEX_W_XS, /* 14922 */ >+ IC_VEX_W_XS, /* 14923 */ >+ IC_VEX_W_XD, /* 14924 */ >+ IC_VEX_W_XD, /* 14925 */ >+ IC_VEX_W_XD, /* 14926 */ >+ IC_VEX_W_XD, /* 14927 */ >+ IC_VEX_OPSIZE, /* 14928 */ >+ IC_VEX_OPSIZE, /* 14929 */ >+ IC_VEX_OPSIZE, /* 14930 */ >+ IC_VEX_OPSIZE, /* 14931 */ >+ IC_VEX_OPSIZE, /* 14932 */ >+ IC_VEX_OPSIZE, /* 14933 */ >+ IC_VEX_OPSIZE, /* 14934 */ >+ IC_VEX_OPSIZE, /* 14935 */ >+ IC_VEX_W_OPSIZE, /* 14936 */ >+ IC_VEX_W_OPSIZE, /* 14937 */ >+ IC_VEX_W_OPSIZE, /* 14938 */ >+ IC_VEX_W_OPSIZE, /* 14939 */ >+ IC_VEX_W_OPSIZE, /* 14940 */ >+ IC_VEX_W_OPSIZE, /* 14941 */ >+ IC_VEX_W_OPSIZE, /* 14942 */ >+ IC_VEX_W_OPSIZE, /* 14943 */ >+ IC_VEX, /* 14944 */ >+ IC_VEX, /* 14945 */ >+ IC_VEX_XS, /* 14946 */ >+ IC_VEX_XS, /* 14947 */ >+ IC_VEX_XD, /* 14948 */ >+ IC_VEX_XD, /* 14949 */ >+ IC_VEX_XD, /* 14950 */ >+ IC_VEX_XD, /* 14951 */ >+ IC_VEX_W, /* 14952 */ >+ IC_VEX_W, /* 14953 */ >+ IC_VEX_W_XS, /* 14954 */ >+ IC_VEX_W_XS, /* 14955 */ >+ IC_VEX_W_XD, /* 14956 */ >+ IC_VEX_W_XD, /* 14957 */ >+ IC_VEX_W_XD, /* 14958 */ >+ IC_VEX_W_XD, /* 14959 */ >+ IC_VEX_OPSIZE, /* 14960 */ >+ IC_VEX_OPSIZE, /* 14961 */ >+ IC_VEX_OPSIZE, /* 14962 */ >+ IC_VEX_OPSIZE, /* 14963 */ >+ IC_VEX_OPSIZE, /* 14964 */ >+ IC_VEX_OPSIZE, /* 14965 */ >+ IC_VEX_OPSIZE, /* 14966 */ >+ IC_VEX_OPSIZE, /* 14967 */ >+ IC_VEX_W_OPSIZE, /* 14968 */ >+ IC_VEX_W_OPSIZE, /* 14969 */ >+ IC_VEX_W_OPSIZE, /* 14970 */ >+ IC_VEX_W_OPSIZE, /* 14971 */ >+ IC_VEX_W_OPSIZE, /* 14972 */ >+ IC_VEX_W_OPSIZE, /* 14973 */ >+ IC_VEX_W_OPSIZE, /* 14974 */ >+ IC_VEX_W_OPSIZE, /* 14975 */ >+ IC_VEX_L, /* 14976 */ >+ IC_VEX_L, /* 14977 */ >+ IC_VEX_L_XS, /* 14978 */ >+ IC_VEX_L_XS, /* 14979 */ >+ IC_VEX_L_XD, /* 14980 */ >+ IC_VEX_L_XD, /* 14981 */ >+ IC_VEX_L_XD, /* 14982 */ >+ IC_VEX_L_XD, /* 14983 */ >+ IC_VEX_L_W, /* 14984 */ >+ IC_VEX_L_W, /* 14985 */ >+ IC_VEX_L_W_XS, /* 14986 */ >+ IC_VEX_L_W_XS, /* 14987 */ >+ IC_VEX_L_W_XD, /* 14988 */ >+ IC_VEX_L_W_XD, /* 14989 */ >+ IC_VEX_L_W_XD, /* 14990 */ >+ IC_VEX_L_W_XD, /* 14991 */ >+ IC_VEX_L_OPSIZE, /* 14992 */ >+ IC_VEX_L_OPSIZE, /* 14993 */ >+ IC_VEX_L_OPSIZE, /* 14994 */ >+ IC_VEX_L_OPSIZE, /* 14995 */ >+ IC_VEX_L_OPSIZE, /* 14996 */ >+ IC_VEX_L_OPSIZE, /* 14997 */ >+ IC_VEX_L_OPSIZE, /* 14998 */ >+ IC_VEX_L_OPSIZE, /* 14999 */ >+ IC_VEX_L_W_OPSIZE, /* 15000 */ >+ IC_VEX_L_W_OPSIZE, /* 15001 */ >+ IC_VEX_L_W_OPSIZE, /* 15002 */ >+ IC_VEX_L_W_OPSIZE, /* 15003 */ >+ IC_VEX_L_W_OPSIZE, /* 15004 */ >+ IC_VEX_L_W_OPSIZE, /* 15005 */ >+ IC_VEX_L_W_OPSIZE, /* 15006 */ >+ IC_VEX_L_W_OPSIZE, /* 15007 */ >+ IC_VEX_L, /* 15008 */ >+ IC_VEX_L, /* 15009 */ >+ IC_VEX_L_XS, /* 15010 */ >+ IC_VEX_L_XS, /* 15011 */ >+ IC_VEX_L_XD, /* 15012 */ >+ IC_VEX_L_XD, /* 15013 */ >+ IC_VEX_L_XD, /* 15014 */ >+ IC_VEX_L_XD, /* 15015 */ >+ IC_VEX_L_W, /* 15016 */ >+ IC_VEX_L_W, /* 15017 */ >+ IC_VEX_L_W_XS, /* 15018 */ >+ IC_VEX_L_W_XS, /* 15019 */ >+ IC_VEX_L_W_XD, /* 15020 */ >+ IC_VEX_L_W_XD, /* 15021 */ >+ IC_VEX_L_W_XD, /* 15022 */ >+ IC_VEX_L_W_XD, /* 15023 */ >+ IC_VEX_L_OPSIZE, /* 15024 */ >+ IC_VEX_L_OPSIZE, /* 15025 */ >+ IC_VEX_L_OPSIZE, /* 15026 */ >+ IC_VEX_L_OPSIZE, /* 15027 */ >+ IC_VEX_L_OPSIZE, /* 15028 */ >+ IC_VEX_L_OPSIZE, /* 15029 */ >+ IC_VEX_L_OPSIZE, /* 15030 */ >+ IC_VEX_L_OPSIZE, /* 15031 */ >+ IC_VEX_L_W_OPSIZE, /* 15032 */ >+ IC_VEX_L_W_OPSIZE, /* 15033 */ >+ IC_VEX_L_W_OPSIZE, /* 15034 */ >+ IC_VEX_L_W_OPSIZE, /* 15035 */ >+ IC_VEX_L_W_OPSIZE, /* 15036 */ >+ IC_VEX_L_W_OPSIZE, /* 15037 */ >+ IC_VEX_L_W_OPSIZE, /* 15038 */ >+ IC_VEX_L_W_OPSIZE, /* 15039 */ >+ IC_VEX_L, /* 15040 */ >+ IC_VEX_L, /* 15041 */ >+ IC_VEX_L_XS, /* 15042 */ >+ IC_VEX_L_XS, /* 15043 */ >+ IC_VEX_L_XD, /* 15044 */ >+ IC_VEX_L_XD, /* 15045 */ >+ IC_VEX_L_XD, /* 15046 */ >+ IC_VEX_L_XD, /* 15047 */ >+ IC_VEX_L_W, /* 15048 */ >+ IC_VEX_L_W, /* 15049 */ >+ IC_VEX_L_W_XS, /* 15050 */ >+ IC_VEX_L_W_XS, /* 15051 */ >+ IC_VEX_L_W_XD, /* 15052 */ >+ IC_VEX_L_W_XD, /* 15053 */ >+ IC_VEX_L_W_XD, /* 15054 */ >+ IC_VEX_L_W_XD, /* 15055 */ >+ IC_VEX_L_OPSIZE, /* 15056 */ >+ IC_VEX_L_OPSIZE, /* 15057 */ >+ IC_VEX_L_OPSIZE, /* 15058 */ >+ IC_VEX_L_OPSIZE, /* 15059 */ >+ IC_VEX_L_OPSIZE, /* 15060 */ >+ IC_VEX_L_OPSIZE, /* 15061 */ >+ IC_VEX_L_OPSIZE, /* 15062 */ >+ IC_VEX_L_OPSIZE, /* 15063 */ >+ IC_VEX_L_W_OPSIZE, /* 15064 */ >+ IC_VEX_L_W_OPSIZE, /* 15065 */ >+ IC_VEX_L_W_OPSIZE, /* 15066 */ >+ IC_VEX_L_W_OPSIZE, /* 15067 */ >+ IC_VEX_L_W_OPSIZE, /* 15068 */ >+ IC_VEX_L_W_OPSIZE, /* 15069 */ >+ IC_VEX_L_W_OPSIZE, /* 15070 */ >+ IC_VEX_L_W_OPSIZE, /* 15071 */ >+ IC_VEX_L, /* 15072 */ >+ IC_VEX_L, /* 15073 */ >+ IC_VEX_L_XS, /* 15074 */ >+ IC_VEX_L_XS, /* 15075 */ >+ IC_VEX_L_XD, /* 15076 */ >+ IC_VEX_L_XD, /* 15077 */ >+ IC_VEX_L_XD, /* 15078 */ >+ IC_VEX_L_XD, /* 15079 */ >+ IC_VEX_L_W, /* 15080 */ >+ IC_VEX_L_W, /* 15081 */ >+ IC_VEX_L_W_XS, /* 15082 */ >+ IC_VEX_L_W_XS, /* 15083 */ >+ IC_VEX_L_W_XD, /* 15084 */ >+ IC_VEX_L_W_XD, /* 15085 */ >+ IC_VEX_L_W_XD, /* 15086 */ >+ IC_VEX_L_W_XD, /* 15087 */ >+ IC_VEX_L_OPSIZE, /* 15088 */ >+ IC_VEX_L_OPSIZE, /* 15089 */ >+ IC_VEX_L_OPSIZE, /* 15090 */ >+ IC_VEX_L_OPSIZE, /* 15091 */ >+ IC_VEX_L_OPSIZE, /* 15092 */ >+ IC_VEX_L_OPSIZE, /* 15093 */ >+ IC_VEX_L_OPSIZE, /* 15094 */ >+ IC_VEX_L_OPSIZE, /* 15095 */ >+ IC_VEX_L_W_OPSIZE, /* 15096 */ >+ IC_VEX_L_W_OPSIZE, /* 15097 */ >+ IC_VEX_L_W_OPSIZE, /* 15098 */ >+ IC_VEX_L_W_OPSIZE, /* 15099 */ >+ IC_VEX_L_W_OPSIZE, /* 15100 */ >+ IC_VEX_L_W_OPSIZE, /* 15101 */ >+ IC_VEX_L_W_OPSIZE, /* 15102 */ >+ IC_VEX_L_W_OPSIZE, /* 15103 */ >+ IC_EVEX_L_KZ_B, /* 15104 */ >+ IC_EVEX_L_KZ_B, /* 15105 */ >+ IC_EVEX_L_XS_KZ_B, /* 15106 */ >+ IC_EVEX_L_XS_KZ_B, /* 15107 */ >+ IC_EVEX_L_XD_KZ_B, /* 15108 */ >+ IC_EVEX_L_XD_KZ_B, /* 15109 */ >+ IC_EVEX_L_XD_KZ_B, /* 15110 */ >+ IC_EVEX_L_XD_KZ_B, /* 15111 */ >+ IC_EVEX_L_W_KZ_B, /* 15112 */ >+ IC_EVEX_L_W_KZ_B, /* 15113 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15114 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15115 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15116 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15117 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15118 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15119 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15120 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15121 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15122 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15123 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15124 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15125 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15126 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15127 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15128 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15129 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15130 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15131 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15132 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15133 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15134 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15135 */ >+ IC_EVEX_L_KZ_B, /* 15136 */ >+ IC_EVEX_L_KZ_B, /* 15137 */ >+ IC_EVEX_L_XS_KZ_B, /* 15138 */ >+ IC_EVEX_L_XS_KZ_B, /* 15139 */ >+ IC_EVEX_L_XD_KZ_B, /* 15140 */ >+ IC_EVEX_L_XD_KZ_B, /* 15141 */ >+ IC_EVEX_L_XD_KZ_B, /* 15142 */ >+ IC_EVEX_L_XD_KZ_B, /* 15143 */ >+ IC_EVEX_L_W_KZ_B, /* 15144 */ >+ IC_EVEX_L_W_KZ_B, /* 15145 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15146 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15147 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15148 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15149 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15150 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15151 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15152 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15153 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15154 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15155 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15156 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15157 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15158 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15159 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15160 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15161 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15162 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15163 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15164 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15165 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15166 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15167 */ >+ IC_EVEX_L_KZ_B, /* 15168 */ >+ IC_EVEX_L_KZ_B, /* 15169 */ >+ IC_EVEX_L_XS_KZ_B, /* 15170 */ >+ IC_EVEX_L_XS_KZ_B, /* 15171 */ >+ IC_EVEX_L_XD_KZ_B, /* 15172 */ >+ IC_EVEX_L_XD_KZ_B, /* 15173 */ >+ IC_EVEX_L_XD_KZ_B, /* 15174 */ >+ IC_EVEX_L_XD_KZ_B, /* 15175 */ >+ IC_EVEX_L_W_KZ_B, /* 15176 */ >+ IC_EVEX_L_W_KZ_B, /* 15177 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15178 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15179 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15180 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15181 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15182 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15183 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15184 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15185 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15186 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15187 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15188 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15189 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15190 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15191 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15192 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15193 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15194 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15195 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15196 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15197 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15198 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15199 */ >+ IC_EVEX_L_KZ_B, /* 15200 */ >+ IC_EVEX_L_KZ_B, /* 15201 */ >+ IC_EVEX_L_XS_KZ_B, /* 15202 */ >+ IC_EVEX_L_XS_KZ_B, /* 15203 */ >+ IC_EVEX_L_XD_KZ_B, /* 15204 */ >+ IC_EVEX_L_XD_KZ_B, /* 15205 */ >+ IC_EVEX_L_XD_KZ_B, /* 15206 */ >+ IC_EVEX_L_XD_KZ_B, /* 15207 */ >+ IC_EVEX_L_W_KZ_B, /* 15208 */ >+ IC_EVEX_L_W_KZ_B, /* 15209 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15210 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15211 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15212 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15213 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15214 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15215 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15216 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15217 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15218 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15219 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15220 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15221 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15222 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15223 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15224 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15225 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15226 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15227 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15228 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15229 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15230 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15231 */ >+ IC_EVEX_L_KZ_B, /* 15232 */ >+ IC_EVEX_L_KZ_B, /* 15233 */ >+ IC_EVEX_L_XS_KZ_B, /* 15234 */ >+ IC_EVEX_L_XS_KZ_B, /* 15235 */ >+ IC_EVEX_L_XD_KZ_B, /* 15236 */ >+ IC_EVEX_L_XD_KZ_B, /* 15237 */ >+ IC_EVEX_L_XD_KZ_B, /* 15238 */ >+ IC_EVEX_L_XD_KZ_B, /* 15239 */ >+ IC_EVEX_L_W_KZ_B, /* 15240 */ >+ IC_EVEX_L_W_KZ_B, /* 15241 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15242 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15243 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15244 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15245 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15246 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15247 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15248 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15249 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15250 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15251 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15252 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15253 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15254 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15255 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15256 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15257 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15258 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15259 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15260 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15261 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15262 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15263 */ >+ IC_EVEX_L_KZ_B, /* 15264 */ >+ IC_EVEX_L_KZ_B, /* 15265 */ >+ IC_EVEX_L_XS_KZ_B, /* 15266 */ >+ IC_EVEX_L_XS_KZ_B, /* 15267 */ >+ IC_EVEX_L_XD_KZ_B, /* 15268 */ >+ IC_EVEX_L_XD_KZ_B, /* 15269 */ >+ IC_EVEX_L_XD_KZ_B, /* 15270 */ >+ IC_EVEX_L_XD_KZ_B, /* 15271 */ >+ IC_EVEX_L_W_KZ_B, /* 15272 */ >+ IC_EVEX_L_W_KZ_B, /* 15273 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15274 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15275 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15276 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15277 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15278 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15279 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15280 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15281 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15282 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15283 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15284 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15285 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15286 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15287 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15288 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15289 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15290 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15291 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15292 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15293 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15294 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15295 */ >+ IC_EVEX_L_KZ_B, /* 15296 */ >+ IC_EVEX_L_KZ_B, /* 15297 */ >+ IC_EVEX_L_XS_KZ_B, /* 15298 */ >+ IC_EVEX_L_XS_KZ_B, /* 15299 */ >+ IC_EVEX_L_XD_KZ_B, /* 15300 */ >+ IC_EVEX_L_XD_KZ_B, /* 15301 */ >+ IC_EVEX_L_XD_KZ_B, /* 15302 */ >+ IC_EVEX_L_XD_KZ_B, /* 15303 */ >+ IC_EVEX_L_W_KZ_B, /* 15304 */ >+ IC_EVEX_L_W_KZ_B, /* 15305 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15306 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15307 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15308 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15309 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15310 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15311 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15312 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15313 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15314 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15315 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15316 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15317 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15318 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15319 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15320 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15321 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15322 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15323 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15324 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15325 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15326 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15327 */ >+ IC_EVEX_L_KZ_B, /* 15328 */ >+ IC_EVEX_L_KZ_B, /* 15329 */ >+ IC_EVEX_L_XS_KZ_B, /* 15330 */ >+ IC_EVEX_L_XS_KZ_B, /* 15331 */ >+ IC_EVEX_L_XD_KZ_B, /* 15332 */ >+ IC_EVEX_L_XD_KZ_B, /* 15333 */ >+ IC_EVEX_L_XD_KZ_B, /* 15334 */ >+ IC_EVEX_L_XD_KZ_B, /* 15335 */ >+ IC_EVEX_L_W_KZ_B, /* 15336 */ >+ IC_EVEX_L_W_KZ_B, /* 15337 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15338 */ >+ IC_EVEX_L_W_XS_KZ_B, /* 15339 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15340 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15341 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15342 */ >+ IC_EVEX_L_W_XD_KZ_B, /* 15343 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15344 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15345 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15346 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15347 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15348 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15349 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15350 */ >+ IC_EVEX_L_OPSIZE_KZ_B, /* 15351 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15352 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15353 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15354 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15355 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15356 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15357 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15358 */ >+ IC_EVEX_L_W_OPSIZE_KZ_B, /* 15359 */ >+ IC, /* 15360 */ >+ IC_64BIT, /* 15361 */ >+ IC_XS, /* 15362 */ >+ IC_64BIT_XS, /* 15363 */ >+ IC_XD, /* 15364 */ >+ IC_64BIT_XD, /* 15365 */ >+ IC_XS, /* 15366 */ >+ IC_64BIT_XS, /* 15367 */ >+ IC, /* 15368 */ >+ IC_64BIT_REXW, /* 15369 */ >+ IC_XS, /* 15370 */ >+ IC_64BIT_REXW_XS, /* 15371 */ >+ IC_XD, /* 15372 */ >+ IC_64BIT_REXW_XD, /* 15373 */ >+ IC_XS, /* 15374 */ >+ IC_64BIT_REXW_XS, /* 15375 */ >+ IC_OPSIZE, /* 15376 */ >+ IC_64BIT_OPSIZE, /* 15377 */ >+ IC_XS_OPSIZE, /* 15378 */ >+ IC_64BIT_XS_OPSIZE, /* 15379 */ >+ IC_XD_OPSIZE, /* 15380 */ >+ IC_64BIT_XD_OPSIZE, /* 15381 */ >+ IC_XS_OPSIZE, /* 15382 */ >+ IC_64BIT_XD_OPSIZE, /* 15383 */ >+ IC_OPSIZE, /* 15384 */ >+ IC_64BIT_REXW_OPSIZE, /* 15385 */ >+ IC_XS_OPSIZE, /* 15386 */ >+ IC_64BIT_REXW_XS, /* 15387 */ >+ IC_XD_OPSIZE, /* 15388 */ >+ IC_64BIT_REXW_XD, /* 15389 */ >+ IC_XS_OPSIZE, /* 15390 */ >+ IC_64BIT_REXW_XS, /* 15391 */ >+ IC_ADSIZE, /* 15392 */ >+ IC_64BIT_ADSIZE, /* 15393 */ >+ IC_XS, /* 15394 */ >+ IC_64BIT_XS, /* 15395 */ >+ IC_XD, /* 15396 */ >+ IC_64BIT_XD, /* 15397 */ >+ IC_XS, /* 15398 */ >+ IC_64BIT_XS, /* 15399 */ >+ IC_ADSIZE, /* 15400 */ >+ IC_64BIT_ADSIZE, /* 15401 */ >+ IC_XS, /* 15402 */ >+ IC_64BIT_REXW_XS, /* 15403 */ >+ IC_XD, /* 15404 */ >+ IC_64BIT_REXW_XD, /* 15405 */ >+ IC_XS, /* 15406 */ >+ IC_64BIT_REXW_XS, /* 15407 */ >+ IC_OPSIZE, /* 15408 */ >+ IC_64BIT_OPSIZE, /* 15409 */ >+ IC_XS_OPSIZE, /* 15410 */ >+ IC_64BIT_XS_OPSIZE, /* 15411 */ >+ IC_XD_OPSIZE, /* 15412 */ >+ IC_64BIT_XD_OPSIZE, /* 15413 */ >+ IC_XS_OPSIZE, /* 15414 */ >+ IC_64BIT_XD_OPSIZE, /* 15415 */ >+ IC_OPSIZE, /* 15416 */ >+ IC_64BIT_REXW_OPSIZE, /* 15417 */ >+ IC_XS_OPSIZE, /* 15418 */ >+ IC_64BIT_REXW_XS, /* 15419 */ >+ IC_XD_OPSIZE, /* 15420 */ >+ IC_64BIT_REXW_XD, /* 15421 */ >+ IC_XS_OPSIZE, /* 15422 */ >+ IC_64BIT_REXW_XS, /* 15423 */ >+ IC_VEX, /* 15424 */ >+ IC_VEX, /* 15425 */ >+ IC_VEX_XS, /* 15426 */ >+ IC_VEX_XS, /* 15427 */ >+ IC_VEX_XD, /* 15428 */ >+ IC_VEX_XD, /* 15429 */ >+ IC_VEX_XD, /* 15430 */ >+ IC_VEX_XD, /* 15431 */ >+ IC_VEX_W, /* 15432 */ >+ IC_VEX_W, /* 15433 */ >+ IC_VEX_W_XS, /* 15434 */ >+ IC_VEX_W_XS, /* 15435 */ >+ IC_VEX_W_XD, /* 15436 */ >+ IC_VEX_W_XD, /* 15437 */ >+ IC_VEX_W_XD, /* 15438 */ >+ IC_VEX_W_XD, /* 15439 */ >+ IC_VEX_OPSIZE, /* 15440 */ >+ IC_VEX_OPSIZE, /* 15441 */ >+ IC_VEX_OPSIZE, /* 15442 */ >+ IC_VEX_OPSIZE, /* 15443 */ >+ IC_VEX_OPSIZE, /* 15444 */ >+ IC_VEX_OPSIZE, /* 15445 */ >+ IC_VEX_OPSIZE, /* 15446 */ >+ IC_VEX_OPSIZE, /* 15447 */ >+ IC_VEX_W_OPSIZE, /* 15448 */ >+ IC_VEX_W_OPSIZE, /* 15449 */ >+ IC_VEX_W_OPSIZE, /* 15450 */ >+ IC_VEX_W_OPSIZE, /* 15451 */ >+ IC_VEX_W_OPSIZE, /* 15452 */ >+ IC_VEX_W_OPSIZE, /* 15453 */ >+ IC_VEX_W_OPSIZE, /* 15454 */ >+ IC_VEX_W_OPSIZE, /* 15455 */ >+ IC_VEX, /* 15456 */ >+ IC_VEX, /* 15457 */ >+ IC_VEX_XS, /* 15458 */ >+ IC_VEX_XS, /* 15459 */ >+ IC_VEX_XD, /* 15460 */ >+ IC_VEX_XD, /* 15461 */ >+ IC_VEX_XD, /* 15462 */ >+ IC_VEX_XD, /* 15463 */ >+ IC_VEX_W, /* 15464 */ >+ IC_VEX_W, /* 15465 */ >+ IC_VEX_W_XS, /* 15466 */ >+ IC_VEX_W_XS, /* 15467 */ >+ IC_VEX_W_XD, /* 15468 */ >+ IC_VEX_W_XD, /* 15469 */ >+ IC_VEX_W_XD, /* 15470 */ >+ IC_VEX_W_XD, /* 15471 */ >+ IC_VEX_OPSIZE, /* 15472 */ >+ IC_VEX_OPSIZE, /* 15473 */ >+ IC_VEX_OPSIZE, /* 15474 */ >+ IC_VEX_OPSIZE, /* 15475 */ >+ IC_VEX_OPSIZE, /* 15476 */ >+ IC_VEX_OPSIZE, /* 15477 */ >+ IC_VEX_OPSIZE, /* 15478 */ >+ IC_VEX_OPSIZE, /* 15479 */ >+ IC_VEX_W_OPSIZE, /* 15480 */ >+ IC_VEX_W_OPSIZE, /* 15481 */ >+ IC_VEX_W_OPSIZE, /* 15482 */ >+ IC_VEX_W_OPSIZE, /* 15483 */ >+ IC_VEX_W_OPSIZE, /* 15484 */ >+ IC_VEX_W_OPSIZE, /* 15485 */ >+ IC_VEX_W_OPSIZE, /* 15486 */ >+ IC_VEX_W_OPSIZE, /* 15487 */ >+ IC_VEX_L, /* 15488 */ >+ IC_VEX_L, /* 15489 */ >+ IC_VEX_L_XS, /* 15490 */ >+ IC_VEX_L_XS, /* 15491 */ >+ IC_VEX_L_XD, /* 15492 */ >+ IC_VEX_L_XD, /* 15493 */ >+ IC_VEX_L_XD, /* 15494 */ >+ IC_VEX_L_XD, /* 15495 */ >+ IC_VEX_L_W, /* 15496 */ >+ IC_VEX_L_W, /* 15497 */ >+ IC_VEX_L_W_XS, /* 15498 */ >+ IC_VEX_L_W_XS, /* 15499 */ >+ IC_VEX_L_W_XD, /* 15500 */ >+ IC_VEX_L_W_XD, /* 15501 */ >+ IC_VEX_L_W_XD, /* 15502 */ >+ IC_VEX_L_W_XD, /* 15503 */ >+ IC_VEX_L_OPSIZE, /* 15504 */ >+ IC_VEX_L_OPSIZE, /* 15505 */ >+ IC_VEX_L_OPSIZE, /* 15506 */ >+ IC_VEX_L_OPSIZE, /* 15507 */ >+ IC_VEX_L_OPSIZE, /* 15508 */ >+ IC_VEX_L_OPSIZE, /* 15509 */ >+ IC_VEX_L_OPSIZE, /* 15510 */ >+ IC_VEX_L_OPSIZE, /* 15511 */ >+ IC_VEX_L_W_OPSIZE, /* 15512 */ >+ IC_VEX_L_W_OPSIZE, /* 15513 */ >+ IC_VEX_L_W_OPSIZE, /* 15514 */ >+ IC_VEX_L_W_OPSIZE, /* 15515 */ >+ IC_VEX_L_W_OPSIZE, /* 15516 */ >+ IC_VEX_L_W_OPSIZE, /* 15517 */ >+ IC_VEX_L_W_OPSIZE, /* 15518 */ >+ IC_VEX_L_W_OPSIZE, /* 15519 */ >+ IC_VEX_L, /* 15520 */ >+ IC_VEX_L, /* 15521 */ >+ IC_VEX_L_XS, /* 15522 */ >+ IC_VEX_L_XS, /* 15523 */ >+ IC_VEX_L_XD, /* 15524 */ >+ IC_VEX_L_XD, /* 15525 */ >+ IC_VEX_L_XD, /* 15526 */ >+ IC_VEX_L_XD, /* 15527 */ >+ IC_VEX_L_W, /* 15528 */ >+ IC_VEX_L_W, /* 15529 */ >+ IC_VEX_L_W_XS, /* 15530 */ >+ IC_VEX_L_W_XS, /* 15531 */ >+ IC_VEX_L_W_XD, /* 15532 */ >+ IC_VEX_L_W_XD, /* 15533 */ >+ IC_VEX_L_W_XD, /* 15534 */ >+ IC_VEX_L_W_XD, /* 15535 */ >+ IC_VEX_L_OPSIZE, /* 15536 */ >+ IC_VEX_L_OPSIZE, /* 15537 */ >+ IC_VEX_L_OPSIZE, /* 15538 */ >+ IC_VEX_L_OPSIZE, /* 15539 */ >+ IC_VEX_L_OPSIZE, /* 15540 */ >+ IC_VEX_L_OPSIZE, /* 15541 */ >+ IC_VEX_L_OPSIZE, /* 15542 */ >+ IC_VEX_L_OPSIZE, /* 15543 */ >+ IC_VEX_L_W_OPSIZE, /* 15544 */ >+ IC_VEX_L_W_OPSIZE, /* 15545 */ >+ IC_VEX_L_W_OPSIZE, /* 15546 */ >+ IC_VEX_L_W_OPSIZE, /* 15547 */ >+ IC_VEX_L_W_OPSIZE, /* 15548 */ >+ IC_VEX_L_W_OPSIZE, /* 15549 */ >+ IC_VEX_L_W_OPSIZE, /* 15550 */ >+ IC_VEX_L_W_OPSIZE, /* 15551 */ >+ IC_VEX_L, /* 15552 */ >+ IC_VEX_L, /* 15553 */ >+ IC_VEX_L_XS, /* 15554 */ >+ IC_VEX_L_XS, /* 15555 */ >+ IC_VEX_L_XD, /* 15556 */ >+ IC_VEX_L_XD, /* 15557 */ >+ IC_VEX_L_XD, /* 15558 */ >+ IC_VEX_L_XD, /* 15559 */ >+ IC_VEX_L_W, /* 15560 */ >+ IC_VEX_L_W, /* 15561 */ >+ IC_VEX_L_W_XS, /* 15562 */ >+ IC_VEX_L_W_XS, /* 15563 */ >+ IC_VEX_L_W_XD, /* 15564 */ >+ IC_VEX_L_W_XD, /* 15565 */ >+ IC_VEX_L_W_XD, /* 15566 */ >+ IC_VEX_L_W_XD, /* 15567 */ >+ IC_VEX_L_OPSIZE, /* 15568 */ >+ IC_VEX_L_OPSIZE, /* 15569 */ >+ IC_VEX_L_OPSIZE, /* 15570 */ >+ IC_VEX_L_OPSIZE, /* 15571 */ >+ IC_VEX_L_OPSIZE, /* 15572 */ >+ IC_VEX_L_OPSIZE, /* 15573 */ >+ IC_VEX_L_OPSIZE, /* 15574 */ >+ IC_VEX_L_OPSIZE, /* 15575 */ >+ IC_VEX_L_W_OPSIZE, /* 15576 */ >+ IC_VEX_L_W_OPSIZE, /* 15577 */ >+ IC_VEX_L_W_OPSIZE, /* 15578 */ >+ IC_VEX_L_W_OPSIZE, /* 15579 */ >+ IC_VEX_L_W_OPSIZE, /* 15580 */ >+ IC_VEX_L_W_OPSIZE, /* 15581 */ >+ IC_VEX_L_W_OPSIZE, /* 15582 */ >+ IC_VEX_L_W_OPSIZE, /* 15583 */ >+ IC_VEX_L, /* 15584 */ >+ IC_VEX_L, /* 15585 */ >+ IC_VEX_L_XS, /* 15586 */ >+ IC_VEX_L_XS, /* 15587 */ >+ IC_VEX_L_XD, /* 15588 */ >+ IC_VEX_L_XD, /* 15589 */ >+ IC_VEX_L_XD, /* 15590 */ >+ IC_VEX_L_XD, /* 15591 */ >+ IC_VEX_L_W, /* 15592 */ >+ IC_VEX_L_W, /* 15593 */ >+ IC_VEX_L_W_XS, /* 15594 */ >+ IC_VEX_L_W_XS, /* 15595 */ >+ IC_VEX_L_W_XD, /* 15596 */ >+ IC_VEX_L_W_XD, /* 15597 */ >+ IC_VEX_L_W_XD, /* 15598 */ >+ IC_VEX_L_W_XD, /* 15599 */ >+ IC_VEX_L_OPSIZE, /* 15600 */ >+ IC_VEX_L_OPSIZE, /* 15601 */ >+ IC_VEX_L_OPSIZE, /* 15602 */ >+ IC_VEX_L_OPSIZE, /* 15603 */ >+ IC_VEX_L_OPSIZE, /* 15604 */ >+ IC_VEX_L_OPSIZE, /* 15605 */ >+ IC_VEX_L_OPSIZE, /* 15606 */ >+ IC_VEX_L_OPSIZE, /* 15607 */ >+ IC_VEX_L_W_OPSIZE, /* 15608 */ >+ IC_VEX_L_W_OPSIZE, /* 15609 */ >+ IC_VEX_L_W_OPSIZE, /* 15610 */ >+ IC_VEX_L_W_OPSIZE, /* 15611 */ >+ IC_VEX_L_W_OPSIZE, /* 15612 */ >+ IC_VEX_L_W_OPSIZE, /* 15613 */ >+ IC_VEX_L_W_OPSIZE, /* 15614 */ >+ IC_VEX_L_W_OPSIZE, /* 15615 */ >+ IC_EVEX_L2_KZ_B, /* 15616 */ >+ IC_EVEX_L2_KZ_B, /* 15617 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15618 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15619 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15620 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15621 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15622 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15623 */ >+ IC_EVEX_L2_W_KZ_B, /* 15624 */ >+ IC_EVEX_L2_W_KZ_B, /* 15625 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15626 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15627 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15628 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15629 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15630 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15631 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15632 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15633 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15634 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15635 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15636 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15637 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15638 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15639 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15640 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15641 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15642 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15643 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15644 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15645 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15646 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15647 */ >+ IC_EVEX_L2_KZ_B, /* 15648 */ >+ IC_EVEX_L2_KZ_B, /* 15649 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15650 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15651 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15652 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15653 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15654 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15655 */ >+ IC_EVEX_L2_W_KZ_B, /* 15656 */ >+ IC_EVEX_L2_W_KZ_B, /* 15657 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15658 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15659 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15660 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15661 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15662 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15663 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15664 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15665 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15666 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15667 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15668 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15669 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15670 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15671 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15672 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15673 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15674 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15675 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15676 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15677 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15678 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15679 */ >+ IC_EVEX_L2_KZ_B, /* 15680 */ >+ IC_EVEX_L2_KZ_B, /* 15681 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15682 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15683 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15684 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15685 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15686 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15687 */ >+ IC_EVEX_L2_W_KZ_B, /* 15688 */ >+ IC_EVEX_L2_W_KZ_B, /* 15689 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15690 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15691 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15692 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15693 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15694 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15695 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15696 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15697 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15698 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15699 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15700 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15701 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15702 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15703 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15704 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15705 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15706 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15707 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15708 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15709 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15710 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15711 */ >+ IC_EVEX_L2_KZ_B, /* 15712 */ >+ IC_EVEX_L2_KZ_B, /* 15713 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15714 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15715 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15716 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15717 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15718 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15719 */ >+ IC_EVEX_L2_W_KZ_B, /* 15720 */ >+ IC_EVEX_L2_W_KZ_B, /* 15721 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15722 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15723 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15724 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15725 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15726 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15727 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15728 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15729 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15730 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15731 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15732 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15733 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15734 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15735 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15736 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15737 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15738 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15739 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15740 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15741 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15742 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15743 */ >+ IC_EVEX_L2_KZ_B, /* 15744 */ >+ IC_EVEX_L2_KZ_B, /* 15745 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15746 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15747 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15748 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15749 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15750 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15751 */ >+ IC_EVEX_L2_W_KZ_B, /* 15752 */ >+ IC_EVEX_L2_W_KZ_B, /* 15753 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15754 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15755 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15756 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15757 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15758 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15759 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15760 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15761 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15762 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15763 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15764 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15765 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15766 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15767 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15768 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15769 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15770 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15771 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15772 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15773 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15774 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15775 */ >+ IC_EVEX_L2_KZ_B, /* 15776 */ >+ IC_EVEX_L2_KZ_B, /* 15777 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15778 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15779 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15780 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15781 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15782 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15783 */ >+ IC_EVEX_L2_W_KZ_B, /* 15784 */ >+ IC_EVEX_L2_W_KZ_B, /* 15785 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15786 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15787 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15788 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15789 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15790 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15791 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15792 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15793 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15794 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15795 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15796 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15797 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15798 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15799 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15800 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15801 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15802 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15803 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15804 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15805 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15806 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15807 */ >+ IC_EVEX_L2_KZ_B, /* 15808 */ >+ IC_EVEX_L2_KZ_B, /* 15809 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15810 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15811 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15812 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15813 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15814 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15815 */ >+ IC_EVEX_L2_W_KZ_B, /* 15816 */ >+ IC_EVEX_L2_W_KZ_B, /* 15817 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15818 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15819 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15820 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15821 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15822 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15823 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15824 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15825 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15826 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15827 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15828 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15829 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15830 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15831 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15832 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15833 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15834 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15835 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15836 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15837 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15838 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15839 */ >+ IC_EVEX_L2_KZ_B, /* 15840 */ >+ IC_EVEX_L2_KZ_B, /* 15841 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15842 */ >+ IC_EVEX_L2_XS_KZ_B, /* 15843 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15844 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15845 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15846 */ >+ IC_EVEX_L2_XD_KZ_B, /* 15847 */ >+ IC_EVEX_L2_W_KZ_B, /* 15848 */ >+ IC_EVEX_L2_W_KZ_B, /* 15849 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15850 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 15851 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15852 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15853 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15854 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 15855 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15856 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15857 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15858 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15859 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15860 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15861 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15862 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 15863 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15864 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15865 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15866 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15867 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15868 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15869 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15870 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 15871 */ >+ IC, /* 15872 */ >+ IC_64BIT, /* 15873 */ >+ IC_XS, /* 15874 */ >+ IC_64BIT_XS, /* 15875 */ >+ IC_XD, /* 15876 */ >+ IC_64BIT_XD, /* 15877 */ >+ IC_XS, /* 15878 */ >+ IC_64BIT_XS, /* 15879 */ >+ IC, /* 15880 */ >+ IC_64BIT_REXW, /* 15881 */ >+ IC_XS, /* 15882 */ >+ IC_64BIT_REXW_XS, /* 15883 */ >+ IC_XD, /* 15884 */ >+ IC_64BIT_REXW_XD, /* 15885 */ >+ IC_XS, /* 15886 */ >+ IC_64BIT_REXW_XS, /* 15887 */ >+ IC_OPSIZE, /* 15888 */ >+ IC_64BIT_OPSIZE, /* 15889 */ >+ IC_XS_OPSIZE, /* 15890 */ >+ IC_64BIT_XS_OPSIZE, /* 15891 */ >+ IC_XD_OPSIZE, /* 15892 */ >+ IC_64BIT_XD_OPSIZE, /* 15893 */ >+ IC_XS_OPSIZE, /* 15894 */ >+ IC_64BIT_XD_OPSIZE, /* 15895 */ >+ IC_OPSIZE, /* 15896 */ >+ IC_64BIT_REXW_OPSIZE, /* 15897 */ >+ IC_XS_OPSIZE, /* 15898 */ >+ IC_64BIT_REXW_XS, /* 15899 */ >+ IC_XD_OPSIZE, /* 15900 */ >+ IC_64BIT_REXW_XD, /* 15901 */ >+ IC_XS_OPSIZE, /* 15902 */ >+ IC_64BIT_REXW_XS, /* 15903 */ >+ IC_ADSIZE, /* 15904 */ >+ IC_64BIT_ADSIZE, /* 15905 */ >+ IC_XS, /* 15906 */ >+ IC_64BIT_XS, /* 15907 */ >+ IC_XD, /* 15908 */ >+ IC_64BIT_XD, /* 15909 */ >+ IC_XS, /* 15910 */ >+ IC_64BIT_XS, /* 15911 */ >+ IC_ADSIZE, /* 15912 */ >+ IC_64BIT_ADSIZE, /* 15913 */ >+ IC_XS, /* 15914 */ >+ IC_64BIT_REXW_XS, /* 15915 */ >+ IC_XD, /* 15916 */ >+ IC_64BIT_REXW_XD, /* 15917 */ >+ IC_XS, /* 15918 */ >+ IC_64BIT_REXW_XS, /* 15919 */ >+ IC_OPSIZE, /* 15920 */ >+ IC_64BIT_OPSIZE, /* 15921 */ >+ IC_XS_OPSIZE, /* 15922 */ >+ IC_64BIT_XS_OPSIZE, /* 15923 */ >+ IC_XD_OPSIZE, /* 15924 */ >+ IC_64BIT_XD_OPSIZE, /* 15925 */ >+ IC_XS_OPSIZE, /* 15926 */ >+ IC_64BIT_XD_OPSIZE, /* 15927 */ >+ IC_OPSIZE, /* 15928 */ >+ IC_64BIT_REXW_OPSIZE, /* 15929 */ >+ IC_XS_OPSIZE, /* 15930 */ >+ IC_64BIT_REXW_XS, /* 15931 */ >+ IC_XD_OPSIZE, /* 15932 */ >+ IC_64BIT_REXW_XD, /* 15933 */ >+ IC_XS_OPSIZE, /* 15934 */ >+ IC_64BIT_REXW_XS, /* 15935 */ >+ IC_VEX, /* 15936 */ >+ IC_VEX, /* 15937 */ >+ IC_VEX_XS, /* 15938 */ >+ IC_VEX_XS, /* 15939 */ >+ IC_VEX_XD, /* 15940 */ >+ IC_VEX_XD, /* 15941 */ >+ IC_VEX_XD, /* 15942 */ >+ IC_VEX_XD, /* 15943 */ >+ IC_VEX_W, /* 15944 */ >+ IC_VEX_W, /* 15945 */ >+ IC_VEX_W_XS, /* 15946 */ >+ IC_VEX_W_XS, /* 15947 */ >+ IC_VEX_W_XD, /* 15948 */ >+ IC_VEX_W_XD, /* 15949 */ >+ IC_VEX_W_XD, /* 15950 */ >+ IC_VEX_W_XD, /* 15951 */ >+ IC_VEX_OPSIZE, /* 15952 */ >+ IC_VEX_OPSIZE, /* 15953 */ >+ IC_VEX_OPSIZE, /* 15954 */ >+ IC_VEX_OPSIZE, /* 15955 */ >+ IC_VEX_OPSIZE, /* 15956 */ >+ IC_VEX_OPSIZE, /* 15957 */ >+ IC_VEX_OPSIZE, /* 15958 */ >+ IC_VEX_OPSIZE, /* 15959 */ >+ IC_VEX_W_OPSIZE, /* 15960 */ >+ IC_VEX_W_OPSIZE, /* 15961 */ >+ IC_VEX_W_OPSIZE, /* 15962 */ >+ IC_VEX_W_OPSIZE, /* 15963 */ >+ IC_VEX_W_OPSIZE, /* 15964 */ >+ IC_VEX_W_OPSIZE, /* 15965 */ >+ IC_VEX_W_OPSIZE, /* 15966 */ >+ IC_VEX_W_OPSIZE, /* 15967 */ >+ IC_VEX, /* 15968 */ >+ IC_VEX, /* 15969 */ >+ IC_VEX_XS, /* 15970 */ >+ IC_VEX_XS, /* 15971 */ >+ IC_VEX_XD, /* 15972 */ >+ IC_VEX_XD, /* 15973 */ >+ IC_VEX_XD, /* 15974 */ >+ IC_VEX_XD, /* 15975 */ >+ IC_VEX_W, /* 15976 */ >+ IC_VEX_W, /* 15977 */ >+ IC_VEX_W_XS, /* 15978 */ >+ IC_VEX_W_XS, /* 15979 */ >+ IC_VEX_W_XD, /* 15980 */ >+ IC_VEX_W_XD, /* 15981 */ >+ IC_VEX_W_XD, /* 15982 */ >+ IC_VEX_W_XD, /* 15983 */ >+ IC_VEX_OPSIZE, /* 15984 */ >+ IC_VEX_OPSIZE, /* 15985 */ >+ IC_VEX_OPSIZE, /* 15986 */ >+ IC_VEX_OPSIZE, /* 15987 */ >+ IC_VEX_OPSIZE, /* 15988 */ >+ IC_VEX_OPSIZE, /* 15989 */ >+ IC_VEX_OPSIZE, /* 15990 */ >+ IC_VEX_OPSIZE, /* 15991 */ >+ IC_VEX_W_OPSIZE, /* 15992 */ >+ IC_VEX_W_OPSIZE, /* 15993 */ >+ IC_VEX_W_OPSIZE, /* 15994 */ >+ IC_VEX_W_OPSIZE, /* 15995 */ >+ IC_VEX_W_OPSIZE, /* 15996 */ >+ IC_VEX_W_OPSIZE, /* 15997 */ >+ IC_VEX_W_OPSIZE, /* 15998 */ >+ IC_VEX_W_OPSIZE, /* 15999 */ >+ IC_VEX_L, /* 16000 */ >+ IC_VEX_L, /* 16001 */ >+ IC_VEX_L_XS, /* 16002 */ >+ IC_VEX_L_XS, /* 16003 */ >+ IC_VEX_L_XD, /* 16004 */ >+ IC_VEX_L_XD, /* 16005 */ >+ IC_VEX_L_XD, /* 16006 */ >+ IC_VEX_L_XD, /* 16007 */ >+ IC_VEX_L_W, /* 16008 */ >+ IC_VEX_L_W, /* 16009 */ >+ IC_VEX_L_W_XS, /* 16010 */ >+ IC_VEX_L_W_XS, /* 16011 */ >+ IC_VEX_L_W_XD, /* 16012 */ >+ IC_VEX_L_W_XD, /* 16013 */ >+ IC_VEX_L_W_XD, /* 16014 */ >+ IC_VEX_L_W_XD, /* 16015 */ >+ IC_VEX_L_OPSIZE, /* 16016 */ >+ IC_VEX_L_OPSIZE, /* 16017 */ >+ IC_VEX_L_OPSIZE, /* 16018 */ >+ IC_VEX_L_OPSIZE, /* 16019 */ >+ IC_VEX_L_OPSIZE, /* 16020 */ >+ IC_VEX_L_OPSIZE, /* 16021 */ >+ IC_VEX_L_OPSIZE, /* 16022 */ >+ IC_VEX_L_OPSIZE, /* 16023 */ >+ IC_VEX_L_W_OPSIZE, /* 16024 */ >+ IC_VEX_L_W_OPSIZE, /* 16025 */ >+ IC_VEX_L_W_OPSIZE, /* 16026 */ >+ IC_VEX_L_W_OPSIZE, /* 16027 */ >+ IC_VEX_L_W_OPSIZE, /* 16028 */ >+ IC_VEX_L_W_OPSIZE, /* 16029 */ >+ IC_VEX_L_W_OPSIZE, /* 16030 */ >+ IC_VEX_L_W_OPSIZE, /* 16031 */ >+ IC_VEX_L, /* 16032 */ >+ IC_VEX_L, /* 16033 */ >+ IC_VEX_L_XS, /* 16034 */ >+ IC_VEX_L_XS, /* 16035 */ >+ IC_VEX_L_XD, /* 16036 */ >+ IC_VEX_L_XD, /* 16037 */ >+ IC_VEX_L_XD, /* 16038 */ >+ IC_VEX_L_XD, /* 16039 */ >+ IC_VEX_L_W, /* 16040 */ >+ IC_VEX_L_W, /* 16041 */ >+ IC_VEX_L_W_XS, /* 16042 */ >+ IC_VEX_L_W_XS, /* 16043 */ >+ IC_VEX_L_W_XD, /* 16044 */ >+ IC_VEX_L_W_XD, /* 16045 */ >+ IC_VEX_L_W_XD, /* 16046 */ >+ IC_VEX_L_W_XD, /* 16047 */ >+ IC_VEX_L_OPSIZE, /* 16048 */ >+ IC_VEX_L_OPSIZE, /* 16049 */ >+ IC_VEX_L_OPSIZE, /* 16050 */ >+ IC_VEX_L_OPSIZE, /* 16051 */ >+ IC_VEX_L_OPSIZE, /* 16052 */ >+ IC_VEX_L_OPSIZE, /* 16053 */ >+ IC_VEX_L_OPSIZE, /* 16054 */ >+ IC_VEX_L_OPSIZE, /* 16055 */ >+ IC_VEX_L_W_OPSIZE, /* 16056 */ >+ IC_VEX_L_W_OPSIZE, /* 16057 */ >+ IC_VEX_L_W_OPSIZE, /* 16058 */ >+ IC_VEX_L_W_OPSIZE, /* 16059 */ >+ IC_VEX_L_W_OPSIZE, /* 16060 */ >+ IC_VEX_L_W_OPSIZE, /* 16061 */ >+ IC_VEX_L_W_OPSIZE, /* 16062 */ >+ IC_VEX_L_W_OPSIZE, /* 16063 */ >+ IC_VEX_L, /* 16064 */ >+ IC_VEX_L, /* 16065 */ >+ IC_VEX_L_XS, /* 16066 */ >+ IC_VEX_L_XS, /* 16067 */ >+ IC_VEX_L_XD, /* 16068 */ >+ IC_VEX_L_XD, /* 16069 */ >+ IC_VEX_L_XD, /* 16070 */ >+ IC_VEX_L_XD, /* 16071 */ >+ IC_VEX_L_W, /* 16072 */ >+ IC_VEX_L_W, /* 16073 */ >+ IC_VEX_L_W_XS, /* 16074 */ >+ IC_VEX_L_W_XS, /* 16075 */ >+ IC_VEX_L_W_XD, /* 16076 */ >+ IC_VEX_L_W_XD, /* 16077 */ >+ IC_VEX_L_W_XD, /* 16078 */ >+ IC_VEX_L_W_XD, /* 16079 */ >+ IC_VEX_L_OPSIZE, /* 16080 */ >+ IC_VEX_L_OPSIZE, /* 16081 */ >+ IC_VEX_L_OPSIZE, /* 16082 */ >+ IC_VEX_L_OPSIZE, /* 16083 */ >+ IC_VEX_L_OPSIZE, /* 16084 */ >+ IC_VEX_L_OPSIZE, /* 16085 */ >+ IC_VEX_L_OPSIZE, /* 16086 */ >+ IC_VEX_L_OPSIZE, /* 16087 */ >+ IC_VEX_L_W_OPSIZE, /* 16088 */ >+ IC_VEX_L_W_OPSIZE, /* 16089 */ >+ IC_VEX_L_W_OPSIZE, /* 16090 */ >+ IC_VEX_L_W_OPSIZE, /* 16091 */ >+ IC_VEX_L_W_OPSIZE, /* 16092 */ >+ IC_VEX_L_W_OPSIZE, /* 16093 */ >+ IC_VEX_L_W_OPSIZE, /* 16094 */ >+ IC_VEX_L_W_OPSIZE, /* 16095 */ >+ IC_VEX_L, /* 16096 */ >+ IC_VEX_L, /* 16097 */ >+ IC_VEX_L_XS, /* 16098 */ >+ IC_VEX_L_XS, /* 16099 */ >+ IC_VEX_L_XD, /* 16100 */ >+ IC_VEX_L_XD, /* 16101 */ >+ IC_VEX_L_XD, /* 16102 */ >+ IC_VEX_L_XD, /* 16103 */ >+ IC_VEX_L_W, /* 16104 */ >+ IC_VEX_L_W, /* 16105 */ >+ IC_VEX_L_W_XS, /* 16106 */ >+ IC_VEX_L_W_XS, /* 16107 */ >+ IC_VEX_L_W_XD, /* 16108 */ >+ IC_VEX_L_W_XD, /* 16109 */ >+ IC_VEX_L_W_XD, /* 16110 */ >+ IC_VEX_L_W_XD, /* 16111 */ >+ IC_VEX_L_OPSIZE, /* 16112 */ >+ IC_VEX_L_OPSIZE, /* 16113 */ >+ IC_VEX_L_OPSIZE, /* 16114 */ >+ IC_VEX_L_OPSIZE, /* 16115 */ >+ IC_VEX_L_OPSIZE, /* 16116 */ >+ IC_VEX_L_OPSIZE, /* 16117 */ >+ IC_VEX_L_OPSIZE, /* 16118 */ >+ IC_VEX_L_OPSIZE, /* 16119 */ >+ IC_VEX_L_W_OPSIZE, /* 16120 */ >+ IC_VEX_L_W_OPSIZE, /* 16121 */ >+ IC_VEX_L_W_OPSIZE, /* 16122 */ >+ IC_VEX_L_W_OPSIZE, /* 16123 */ >+ IC_VEX_L_W_OPSIZE, /* 16124 */ >+ IC_VEX_L_W_OPSIZE, /* 16125 */ >+ IC_VEX_L_W_OPSIZE, /* 16126 */ >+ IC_VEX_L_W_OPSIZE, /* 16127 */ >+ IC_EVEX_L2_KZ_B, /* 16128 */ >+ IC_EVEX_L2_KZ_B, /* 16129 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16130 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16131 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16132 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16133 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16134 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16135 */ >+ IC_EVEX_L2_W_KZ_B, /* 16136 */ >+ IC_EVEX_L2_W_KZ_B, /* 16137 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16138 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16139 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16140 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16141 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16142 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16143 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16144 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16145 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16146 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16147 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16148 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16149 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16150 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16151 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16152 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16153 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16154 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16155 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16156 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16157 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16158 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16159 */ >+ IC_EVEX_L2_KZ_B, /* 16160 */ >+ IC_EVEX_L2_KZ_B, /* 16161 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16162 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16163 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16164 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16165 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16166 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16167 */ >+ IC_EVEX_L2_W_KZ_B, /* 16168 */ >+ IC_EVEX_L2_W_KZ_B, /* 16169 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16170 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16171 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16172 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16173 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16174 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16175 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16176 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16177 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16178 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16179 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16180 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16181 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16182 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16183 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16184 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16185 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16186 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16187 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16188 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16189 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16190 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16191 */ >+ IC_EVEX_L2_KZ_B, /* 16192 */ >+ IC_EVEX_L2_KZ_B, /* 16193 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16194 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16195 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16196 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16197 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16198 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16199 */ >+ IC_EVEX_L2_W_KZ_B, /* 16200 */ >+ IC_EVEX_L2_W_KZ_B, /* 16201 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16202 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16203 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16204 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16205 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16206 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16207 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16208 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16209 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16210 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16211 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16212 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16213 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16214 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16215 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16216 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16217 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16218 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16219 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16220 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16221 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16222 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16223 */ >+ IC_EVEX_L2_KZ_B, /* 16224 */ >+ IC_EVEX_L2_KZ_B, /* 16225 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16226 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16227 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16228 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16229 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16230 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16231 */ >+ IC_EVEX_L2_W_KZ_B, /* 16232 */ >+ IC_EVEX_L2_W_KZ_B, /* 16233 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16234 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16235 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16236 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16237 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16238 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16239 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16240 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16241 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16242 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16243 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16244 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16245 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16246 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16247 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16248 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16249 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16250 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16251 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16252 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16253 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16254 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16255 */ >+ IC_EVEX_L2_KZ_B, /* 16256 */ >+ IC_EVEX_L2_KZ_B, /* 16257 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16258 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16259 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16260 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16261 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16262 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16263 */ >+ IC_EVEX_L2_W_KZ_B, /* 16264 */ >+ IC_EVEX_L2_W_KZ_B, /* 16265 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16266 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16267 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16268 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16269 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16270 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16271 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16272 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16273 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16274 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16275 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16276 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16277 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16278 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16279 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16280 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16281 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16282 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16283 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16284 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16285 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16286 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16287 */ >+ IC_EVEX_L2_KZ_B, /* 16288 */ >+ IC_EVEX_L2_KZ_B, /* 16289 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16290 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16291 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16292 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16293 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16294 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16295 */ >+ IC_EVEX_L2_W_KZ_B, /* 16296 */ >+ IC_EVEX_L2_W_KZ_B, /* 16297 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16298 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16299 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16300 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16301 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16302 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16303 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16304 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16305 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16306 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16307 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16308 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16309 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16310 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16311 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16312 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16313 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16314 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16315 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16316 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16317 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16318 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16319 */ >+ IC_EVEX_L2_KZ_B, /* 16320 */ >+ IC_EVEX_L2_KZ_B, /* 16321 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16322 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16323 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16324 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16325 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16326 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16327 */ >+ IC_EVEX_L2_W_KZ_B, /* 16328 */ >+ IC_EVEX_L2_W_KZ_B, /* 16329 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16330 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16331 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16332 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16333 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16334 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16335 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16336 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16337 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16338 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16339 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16340 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16341 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16342 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16343 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16344 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16345 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16346 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16347 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16348 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16349 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16350 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16351 */ >+ IC_EVEX_L2_KZ_B, /* 16352 */ >+ IC_EVEX_L2_KZ_B, /* 16353 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16354 */ >+ IC_EVEX_L2_XS_KZ_B, /* 16355 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16356 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16357 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16358 */ >+ IC_EVEX_L2_XD_KZ_B, /* 16359 */ >+ IC_EVEX_L2_W_KZ_B, /* 16360 */ >+ IC_EVEX_L2_W_KZ_B, /* 16361 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16362 */ >+ IC_EVEX_L2_W_XS_KZ_B, /* 16363 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16364 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16365 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16366 */ >+ IC_EVEX_L2_W_XD_KZ_B, /* 16367 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16368 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16369 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16370 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16371 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16372 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16373 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16374 */ >+ IC_EVEX_L2_OPSIZE_KZ_B, /* 16375 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16376 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16377 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16378 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16379 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16380 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16381 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B, /* 16382 */ >+ IC_EVEX_L2_W_OPSIZE_KZ_B /* 16383 */ >+}; >+ >+static const InstrUID modRMTable[] = { >+/* EmptyTable */ >+ 0x0, >+/* Table1 */ >+ 0x6c, /* ADD8mr */ >+ 0x70, /* ADD8rr */ >+/* Table3 */ >+ 0x55, /* ADD32mr */ >+ 0x5b, /* ADD32rr */ >+/* Table5 */ >+ 0x6f, /* ADD8rm */ >+ 0x71, /* ADD8rr_REV */ >+/* Table7 */ >+ 0x5a, /* ADD32rm */ >+ 0x5d, /* ADD32rr_REV */ >+/* Table9 */ >+ 0x6a, /* ADD8i8 */ >+/* Table10 */ >+ 0x52, /* ADD32i32 */ >+/* Table11 */ >+ 0x8e1, /* PUSHES32 */ >+/* Table12 */ >+ 0x86a, /* POPES32 */ >+/* Table13 */ >+ 0x75c, /* OR8mr */ >+ 0x760, /* OR8rr */ >+/* Table15 */ >+ 0x74a, /* OR32mr */ >+ 0x74f, /* OR32rr */ >+/* Table17 */ >+ 0x75f, /* OR8rm */ >+ 0x761, /* OR8rr_REV */ >+/* Table19 */ >+ 0x74e, /* OR32rm */ >+ 0x750, /* OR32rr_REV */ >+/* Table21 */ >+ 0x75a, /* OR8i8 */ >+/* Table22 */ >+ 0x747, /* OR32i32 */ >+/* Table23 */ >+ 0x8dd, /* PUSHCS32 */ >+/* Table24 */ >+ 0x3d, /* ADC8mr */ >+ 0x40, /* ADC8rr */ >+/* Table26 */ >+ 0x2c, /* ADC32mr */ >+ 0x30, /* ADC32rr */ >+/* Table28 */ >+ 0x3f, /* ADC8rm */ >+ 0x41, /* ADC8rr_REV */ >+/* Table30 */ >+ 0x2f, /* ADC32rm */ >+ 0x31, /* ADC32rr_REV */ >+/* Table32 */ >+ 0x3b, /* ADC8i8 */ >+/* Table33 */ >+ 0x29, /* ADC32i32 */ >+/* Table34 */ >+ 0x8ec, /* PUSHSS32 */ >+/* Table35 */ >+ 0x875, /* POPSS32 */ >+/* Table36 */ >+ 0x9ec, /* SBB8mr */ >+ 0x9ef, /* SBB8rr */ >+/* Table38 */ >+ 0x9db, /* SBB32mr */ >+ 0x9df, /* SBB32rr */ >+/* Table40 */ >+ 0x9ee, /* SBB8rm */ >+ 0x9f0, /* SBB8rr_REV */ >+/* Table42 */ >+ 0x9de, /* SBB32rm */ >+ 0x9e0, /* SBB32rr_REV */ >+/* Table44 */ >+ 0x9ea, /* SBB8i8 */ >+/* Table45 */ >+ 0x9d8, /* SBB32i32 */ >+/* Table46 */ >+ 0x8df, /* PUSHDS32 */ >+/* Table47 */ >+ 0x868, /* POPDS32 */ >+/* Table48 */ >+ 0xc8, /* AND8mr */ >+ 0xcc, /* AND8rr */ >+/* Table50 */ >+ 0xb7, /* AND32mr */ >+ 0xbb, /* AND32rr */ >+/* Table52 */ >+ 0xcb, /* AND8rm */ >+ 0xcd, /* AND8rr_REV */ >+/* Table54 */ >+ 0xba, /* AND32rm */ >+ 0xbc, /* AND32rr_REV */ >+/* Table56 */ >+ 0xc6, /* AND8i8 */ >+/* Table57 */ >+ 0xb4, /* AND32i32 */ >+/* Table58 */ >+ 0x28b, /* DAA */ >+/* Table59 */ >+ 0xaef, /* SUB8mr */ >+ 0xaf3, /* SUB8rr */ >+/* Table61 */ >+ 0xade, /* SUB32mr */ >+ 0xae2, /* SUB32rr */ >+/* Table63 */ >+ 0xaf2, /* SUB8rm */ >+ 0xaf4, /* SUB8rr_REV */ >+/* Table65 */ >+ 0xae1, /* SUB32rm */ >+ 0xae3, /* SUB32rr_REV */ >+/* Table67 */ >+ 0xaed, /* SUB8i8 */ >+/* Table68 */ >+ 0xadb, /* SUB32i32 */ >+/* Table69 */ >+ 0x28c, /* DAS */ >+/* Table70 */ >+ 0x1865, /* XOR8mr */ >+ 0x1869, /* XOR8rr */ >+/* Table72 */ >+ 0x1854, /* XOR32mr */ >+ 0x1858, /* XOR32rr */ >+/* Table74 */ >+ 0x1868, /* XOR8rm */ >+ 0x186a, /* XOR8rr_REV */ >+/* Table76 */ >+ 0x1857, /* XOR32rm */ >+ 0x1859, /* XOR32rr_REV */ >+/* Table78 */ >+ 0x1863, /* XOR8i8 */ >+/* Table79 */ >+ 0x1851, /* XOR32i32 */ >+/* Table80 */ >+ 0x14, /* AAA */ >+/* Table81 */ >+ 0x221, /* CMP8mr */ >+ 0x224, /* CMP8rr */ >+/* Table83 */ >+ 0x210, /* CMP32mr */ >+ 0x214, /* CMP32rr */ >+/* Table85 */ >+ 0x223, /* CMP8rm */ >+ 0x225, /* CMP8rr_REV */ >+/* Table87 */ >+ 0x213, /* CMP32rm */ >+ 0x215, /* CMP32rr_REV */ >+/* Table89 */ >+ 0x21f, /* CMP8i8 */ >+/* Table90 */ >+ 0x20d, /* CMP32i32 */ >+/* Table91 */ >+ 0x17, /* AAS */ >+/* Table92 */ >+ 0x385, /* INC32r */ >+/* Table93 */ >+ 0x293, /* DEC32r */ >+/* Table94 */ >+ 0x8d1, /* PUSH32r */ >+/* Table95 */ >+ 0x859, /* POP32r */ >+/* Table96 */ >+ 0x8db, /* PUSHA32 */ >+/* Table97 */ >+ 0x860, /* POPA32 */ >+/* Table98 */ >+ 0x118, /* BOUNDS32rm */ >+ 0x0, /* */ >+/* Table100 */ >+ 0xda, /* ARPL16mr */ >+ 0xdb, /* ARPL16rr */ >+/* Table102 */ >+ 0x28d, /* DATA16_PREFIX */ >+/* Table103 */ >+ 0x8ee, /* PUSHi32 */ >+/* Table104 */ >+ 0x36b, /* IMUL32rmi */ >+ 0x36e, /* IMUL32rri */ >+/* Table106 */ >+ 0x8d0, /* PUSH32i8 */ >+/* Table107 */ >+ 0x36c, /* IMUL32rmi8 */ >+ 0x36f, /* IMUL32rri8 */ >+/* Table109 */ >+ 0x38e, /* INSB */ >+/* Table110 */ >+ 0x393, /* INSL */ >+/* Table111 */ >+ 0x76c, /* OUTSB */ >+/* Table112 */ >+ 0x76d, /* OUTSL */ >+/* Table113 */ >+ 0x45c, /* JO_1 */ >+/* Table114 */ >+ 0x453, /* JNO_1 */ >+/* Table115 */ >+ 0x432, /* JB_1 */ >+/* Table116 */ >+ 0x429, /* JAE_1 */ >+/* Table117 */ >+ 0x438, /* JE_1 */ >+/* Table118 */ >+ 0x450, /* JNE_1 */ >+/* Table119 */ >+ 0x42f, /* JBE_1 */ >+/* Table120 */ >+ 0x42c, /* JA_1 */ >+/* Table121 */ >+ 0x463, /* JS_1 */ >+/* Table122 */ >+ 0x459, /* JNS_1 */ >+/* Table123 */ >+ 0x45f, /* JP_1 */ >+/* Table124 */ >+ 0x456, /* JNP_1 */ >+/* Table125 */ >+ 0x444, /* JL_1 */ >+/* Table126 */ >+ 0x43b, /* JGE_1 */ >+/* Table127 */ >+ 0x441, /* JLE_1 */ >+/* Table128 */ >+ 0x43e, /* JG_1 */ >+/* Table129 */ >+ 0x6b, /* ADD8mi */ >+ 0x75b, /* OR8mi */ >+ 0x3c, /* ADC8mi */ >+ 0x9eb, /* SBB8mi */ >+ 0xc7, /* AND8mi */ >+ 0xaee, /* SUB8mi */ >+ 0x1864, /* XOR8mi */ >+ 0x220, /* CMP8mi */ >+ 0x6d, /* ADD8ri */ >+ 0x75d, /* OR8ri */ >+ 0x3e, /* ADC8ri */ >+ 0x9ed, /* SBB8ri */ >+ 0xc9, /* AND8ri */ >+ 0xaf0, /* SUB8ri */ >+ 0x1866, /* XOR8ri */ >+ 0x222, /* CMP8ri */ >+/* Table145 */ >+ 0x53, /* ADD32mi */ >+ 0x748, /* OR32mi */ >+ 0x2a, /* ADC32mi */ >+ 0x9d9, /* SBB32mi */ >+ 0xb5, /* AND32mi */ >+ 0xadc, /* SUB32mi */ >+ 0x1852, /* XOR32mi */ >+ 0x20e, /* CMP32mi */ >+ 0x56, /* ADD32ri */ >+ 0x74c, /* OR32ri */ >+ 0x2d, /* ADC32ri */ >+ 0x9dc, /* SBB32ri */ >+ 0xb8, /* AND32ri */ >+ 0xadf, /* SUB32ri */ >+ 0x1855, /* XOR32ri */ >+ 0x211, /* CMP32ri */ >+/* Table161 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x6e, /* ADD8ri8 */ >+ 0x75e, /* OR8ri8 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xca, /* AND8ri8 */ >+ 0xaf1, /* SUB8ri8 */ >+ 0x1867, /* XOR8ri8 */ >+ 0x0, /* */ >+/* Table177 */ >+ 0x54, /* ADD32mi8 */ >+ 0x749, /* OR32mi8 */ >+ 0x2b, /* ADC32mi8 */ >+ 0x9da, /* SBB32mi8 */ >+ 0xb6, /* AND32mi8 */ >+ 0xadd, /* SUB32mi8 */ >+ 0x1853, /* XOR32mi8 */ >+ 0x20f, /* CMP32mi8 */ >+ 0x57, /* ADD32ri8 */ >+ 0x74d, /* OR32ri8 */ >+ 0x2e, /* ADC32ri8 */ >+ 0x9dd, /* SBB32ri8 */ >+ 0xb9, /* AND32ri8 */ >+ 0xae0, /* SUB32ri8 */ >+ 0x1856, /* XOR32ri8 */ >+ 0x212, /* CMP32ri8 */ >+/* Table193 */ >+ 0xb5a, /* TEST8rm */ >+ 0xb5b, /* TEST8rr */ >+/* Table195 */ >+ 0xb4b, /* TEST32rm */ >+ 0xb4c, /* TEST32rr */ >+/* Table197 */ >+ 0x183d, /* XCHG8rm */ >+ 0x183e, /* XCHG8rr */ >+/* Table199 */ >+ 0x1838, /* XCHG32rm */ >+ 0x1839, /* XCHG32rr */ >+/* Table201 */ >+ 0x663, /* MOV8mr */ >+ 0x66b, /* MOV8rr */ >+/* Table203 */ >+ 0x636, /* MOV32mr */ >+ 0x641, /* MOV32rr */ >+/* Table205 */ >+ 0x669, /* MOV8rm */ >+ 0x66d, /* MOV8rr_REV */ >+/* Table207 */ >+ 0x640, /* MOV32rm */ >+ 0x642, /* MOV32rr_REV */ >+/* Table209 */ >+ 0x637, /* MOV32ms */ >+ 0x643, /* MOV32rs */ >+/* Table211 */ >+ 0x4be, /* LEA32r */ >+ 0x0, /* */ >+/* Table213 */ >+ 0x644, /* MOV32sm */ >+ 0x645, /* MOV32sr */ >+/* Table215 */ >+ 0x85a, /* POP32rmm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x85b, /* POP32rmr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table231 */ >+ 0x716, /* NOOP */ >+/* Table232 */ >+ 0x1836, /* XCHG32ar */ >+/* Table233 */ >+ 0x28a, /* CWDE */ >+/* Table234 */ >+ 0x165, /* CDQ */ >+/* Table235 */ >+ 0x2ec, /* FARCALL32i */ >+/* Table236 */ >+ 0x181d, /* WAIT */ >+/* Table237 */ >+ 0x8e3, /* PUSHF32 */ >+/* Table238 */ >+ 0x86c, /* POPF32 */ >+/* Table239 */ >+ 0x999, /* SAHF */ >+/* Table240 */ >+ 0x49a, /* LAHF */ >+/* Table241 */ >+ 0x665, /* MOV8o8a */ >+/* Table242 */ >+ 0x638, /* MOV32o32a */ >+/* Table243 */ >+ 0x660, /* MOV8ao8 */ >+/* Table244 */ >+ 0x631, /* MOV32ao32 */ >+/* Table245 */ >+ 0x6a5, /* MOVSB */ >+/* Table246 */ >+ 0x6ae, /* MOVSL */ >+/* Table247 */ >+ 0x22e, /* CMPSB */ >+/* Table248 */ >+ 0x233, /* CMPSL */ >+/* Table249 */ >+ 0xb54, /* TEST8i8 */ >+/* Table250 */ >+ 0xb46, /* TEST32i32 */ >+/* Table251 */ >+ 0xab0, /* STOSB */ >+/* Table252 */ >+ 0xab1, /* STOSL */ >+/* Table253 */ >+ 0x516, /* LODSB */ >+/* Table254 */ >+ 0x517, /* LODSL */ >+/* Table255 */ >+ 0x9f1, /* SCASB */ >+/* Table256 */ >+ 0x9f2, /* SCASL */ >+/* Table257 */ >+ 0x667, /* MOV8ri */ >+/* Table258 */ >+ 0x63d, /* MOV32ri */ >+/* Table259 */ >+ 0x966, /* ROL8mi */ >+ 0x97e, /* ROR8mi */ >+ 0x905, /* RCL8mi */ >+ 0x925, /* RCR8mi */ >+ 0xa49, /* SHL8mi */ >+ 0xa71, /* SHR8mi */ >+ 0x9ae, /* SAL8mi */ >+ 0x9c7, /* SAR8mi */ >+ 0x969, /* ROL8ri */ >+ 0x981, /* ROR8ri */ >+ 0x908, /* RCL8ri */ >+ 0x928, /* RCR8ri */ >+ 0xa4c, /* SHL8ri */ >+ 0xa74, /* SHR8ri */ >+ 0x9b1, /* SAL8ri */ >+ 0x9ca, /* SAR8ri */ >+/* Table275 */ >+ 0x95a, /* ROL32mi */ >+ 0x972, /* ROR32mi */ >+ 0x8f9, /* RCL32mi */ >+ 0x919, /* RCR32mi */ >+ 0xa3d, /* SHL32mi */ >+ 0xa65, /* SHR32mi */ >+ 0x9a2, /* SAL32mi */ >+ 0x9bb, /* SAR32mi */ >+ 0x95d, /* ROL32ri */ >+ 0x975, /* ROR32ri */ >+ 0x8fc, /* RCL32ri */ >+ 0x91c, /* RCR32ri */ >+ 0xa40, /* SHL32ri */ >+ 0xa68, /* SHR32ri */ >+ 0x9a5, /* SAL32ri */ >+ 0x9be, /* SAR32ri */ >+/* Table291 */ >+ 0x94b, /* RETIL */ >+/* Table292 */ >+ 0x94e, /* RETL */ >+/* Table293 */ >+ 0x4c4, /* LES32rm */ >+ 0x0, /* */ >+/* Table295 */ >+ 0x4aa, /* LDS32rm */ >+ 0x0, /* */ >+/* Table297 */ >+ 0x662, /* MOV8mi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x668, /* MOV8ri_alt */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1827, /* XABORT */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table369 */ >+ 0x635, /* MOV32mi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x63f, /* MOV32ri_alt */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1832, /* XBEGIN_4 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table441 */ >+ 0x2e4, /* ENTER */ >+/* Table442 */ >+ 0x4c1, /* LEAVE */ >+/* Table443 */ >+ 0x51d, /* LRETIL */ >+/* Table444 */ >+ 0x520, /* LRETL */ >+/* Table445 */ >+ 0x397, /* INT3 */ >+/* Table446 */ >+ 0x395, /* INT */ >+/* Table447 */ >+ 0x398, /* INTO */ >+/* Table448 */ >+ 0x3a4, /* IRET32 */ >+/* Table449 */ >+ 0x964, /* ROL8m1 */ >+ 0x97c, /* ROR8m1 */ >+ 0x903, /* RCL8m1 */ >+ 0x923, /* RCR8m1 */ >+ 0xa47, /* SHL8m1 */ >+ 0xa6f, /* SHR8m1 */ >+ 0x9ac, /* SAL8m1 */ >+ 0x9c5, /* SAR8m1 */ >+ 0x967, /* ROL8r1 */ >+ 0x97f, /* ROR8r1 */ >+ 0x906, /* RCL8r1 */ >+ 0x926, /* RCR8r1 */ >+ 0xa4a, /* SHL8r1 */ >+ 0xa72, /* SHR8r1 */ >+ 0x9af, /* SAL8r1 */ >+ 0x9c8, /* SAR8r1 */ >+/* Table465 */ >+ 0x958, /* ROL32m1 */ >+ 0x970, /* ROR32m1 */ >+ 0x8f7, /* RCL32m1 */ >+ 0x917, /* RCR32m1 */ >+ 0xa3b, /* SHL32m1 */ >+ 0xa63, /* SHR32m1 */ >+ 0x9a0, /* SAL32m1 */ >+ 0x9b9, /* SAR32m1 */ >+ 0x95b, /* ROL32r1 */ >+ 0x973, /* ROR32r1 */ >+ 0x8fa, /* RCL32r1 */ >+ 0x91a, /* RCR32r1 */ >+ 0xa3e, /* SHL32r1 */ >+ 0xa66, /* SHR32r1 */ >+ 0x9a3, /* SAL32r1 */ >+ 0x9bc, /* SAR32r1 */ >+/* Table481 */ >+ 0x965, /* ROL8mCL */ >+ 0x97d, /* ROR8mCL */ >+ 0x904, /* RCL8mCL */ >+ 0x924, /* RCR8mCL */ >+ 0xa48, /* SHL8mCL */ >+ 0xa70, /* SHR8mCL */ >+ 0x9ad, /* SAL8mCL */ >+ 0x9c6, /* SAR8mCL */ >+ 0x968, /* ROL8rCL */ >+ 0x980, /* ROR8rCL */ >+ 0x907, /* RCL8rCL */ >+ 0x927, /* RCR8rCL */ >+ 0xa4b, /* SHL8rCL */ >+ 0xa73, /* SHR8rCL */ >+ 0x9b0, /* SAL8rCL */ >+ 0x9c9, /* SAR8rCL */ >+/* Table497 */ >+ 0x959, /* ROL32mCL */ >+ 0x971, /* ROR32mCL */ >+ 0x8f8, /* RCL32mCL */ >+ 0x918, /* RCR32mCL */ >+ 0xa3c, /* SHL32mCL */ >+ 0xa64, /* SHR32mCL */ >+ 0x9a1, /* SAL32mCL */ >+ 0x9ba, /* SAR32mCL */ >+ 0x95c, /* ROL32rCL */ >+ 0x974, /* ROR32rCL */ >+ 0x8fb, /* RCL32rCL */ >+ 0x91b, /* RCR32rCL */ >+ 0xa3f, /* SHL32rCL */ >+ 0xa67, /* SHR32rCL */ >+ 0x9a4, /* SAL32rCL */ >+ 0x9bd, /* SAR32rCL */ >+/* Table513 */ >+ 0x16, /* AAM8i8 */ >+/* Table514 */ >+ 0x15, /* AAD8i8 */ >+/* Table515 */ >+ 0x9b2, /* SALC */ >+/* Table516 */ >+ 0x1847, /* XLAT */ >+/* Table517 */ >+ 0x82, /* ADD_F32m */ >+ 0x6f8, /* MUL_F32m */ >+ 0x2f6, /* FCOM32m */ >+ 0x2f8, /* FCOMP32m */ >+ 0xb13, /* SUB_F32m */ >+ 0xaf9, /* SUBR_F32m */ >+ 0x2c2, /* DIV_F32m */ >+ 0x2a8, /* DIVR_F32m */ >+ 0x87, /* ADD_FST0r */ >+ 0x6fd, /* MUL_FST0r */ >+ 0x24b, /* COM_FST0r */ >+ 0x248, /* COMP_FST0r */ >+ 0xb18, /* SUB_FST0r */ >+ 0xafe, /* SUBR_FST0r */ >+ 0x2c7, /* DIV_FST0r */ >+ 0x2ad, /* DIVR_FST0r */ >+/* Table533 */ >+ 0x4ad, /* LD_F32m */ >+ 0x0, /* */ >+ 0xab8, /* ST_F32m */ >+ 0xabd, /* ST_FP32m */ >+ 0x304, /* FLDENVm */ >+ 0x303, /* FLDCW16m */ >+ 0x323, /* FSTENVm */ >+ 0x30d, /* FNSTCW16m */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x4bc, /* LD_Frr */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x183f, /* XCH_F */ >+ 0x30c, /* FNOP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0xac0, /* ST_FPNCEST0r */ >+ 0x167, /* CHS_F */ >+ 0x18, /* ABS_F */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xb63, /* TST_F */ >+ 0x324, /* FXAM */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4ac, /* LD_F1 */ >+ 0x306, /* FLDL2T */ >+ 0x305, /* FLDL2E */ >+ 0x309, /* FLDPI */ >+ 0x307, /* FLDLG2 */ >+ 0x308, /* FLDLN2 */ >+ 0x4ab, /* LD_F0 */ >+ 0x0, /* */ >+ 0x2e9, /* F2XM1 */ >+ 0x32a, /* FYL2X */ >+ 0x31c, /* FPTAN */ >+ 0x319, /* FPATAN */ >+ 0x329, /* FXTRACT */ >+ 0x31b, /* FPREM1 */ >+ 0x2fb, /* FDECSTP */ >+ 0x302, /* FINCSTP */ >+ 0x31a, /* FPREM */ >+ 0x32b, /* FYL2XP1 */ >+ 0xaa6, /* SQRT_F */ >+ 0x322, /* FSINCOS */ >+ 0x31d, /* FRNDINT */ >+ 0x320, /* FSCALE */ >+ 0xa8c, /* SIN_F */ >+ 0x24c, /* COS_F */ >+/* Table605 */ >+ 0x85, /* ADD_FI32m */ >+ 0x6fb, /* MUL_FI32m */ >+ 0x2ff, /* FICOM32m */ >+ 0x301, /* FICOMP32m */ >+ 0xb16, /* SUB_FI32m */ >+ 0xafc, /* SUBR_FI32m */ >+ 0x2c5, /* DIV_FI32m */ >+ 0x2ab, /* DIVR_FI32m */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x18f, /* CMOVB_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x199, /* CMOVE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x18b, /* CMOVBE_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x1e9, /* CMOVP_F */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xb77, /* UCOM_FPPr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table677 */ >+ 0x355, /* ILD_F32m */ >+ 0x3a7, /* ISTT_FP32m */ >+ 0x3b3, /* IST_F32m */ >+ 0x3b5, /* IST_FP32m */ >+ 0x0, /* */ >+ 0x4af, /* LD_F80m */ >+ 0x0, /* */ >+ 0xabf, /* ST_FP80m */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1b9, /* CMOVNB_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1c3, /* CMOVNE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1b5, /* CMOVNBE_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x1d3, /* CMOVNP_F */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x30a, /* FNCLEX */ >+ 0x30b, /* FNINIT */ >+ 0x321, /* FSETPM */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0xb76, /* UCOM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x24a, /* COM_FIr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table749 */ >+ 0x83, /* ADD_F64m */ >+ 0x6f9, /* MUL_F64m */ >+ 0x2f7, /* FCOM64m */ >+ 0x2f9, /* FCOMP64m */ >+ 0xb14, /* SUB_F64m */ >+ 0xafa, /* SUBR_F64m */ >+ 0x2c3, /* DIV_F64m */ >+ 0x2a9, /* DIVR_F64m */ >+ 0x96, /* ADD_FrST0 */ >+ 0x70c, /* MUL_FrST0 */ >+ 0xabc, /* ST_FCOMST0r */ >+ 0xaba, /* ST_FCOMPST0r */ >+ 0xb0a, /* SUBR_FrST0 */ >+ 0xb27, /* SUB_FrST0 */ >+ 0x2b9, /* DIVR_FrST0 */ >+ 0x2d6, /* DIV_FrST0 */ >+/* Table765 */ >+ 0x4ae, /* LD_F64m */ >+ 0x3a8, /* ISTT_FP64m */ >+ 0xab9, /* ST_F64m */ >+ 0xabe, /* ST_FP64m */ >+ 0x31e, /* FRSTORm */ >+ 0x0, /* */ >+ 0x31f, /* FSAVEm */ >+ 0x30f, /* FNSTSWm */ >+ 0x2fd, /* FFREE */ >+ 0xac4, /* ST_FXCHST0r */ >+ 0xad1, /* ST_Frr */ >+ 0xac3, /* ST_FPrr */ >+ 0xb7f, /* UCOM_Fr */ >+ 0xb78, /* UCOM_FPr */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table781 */ >+ 0x84, /* ADD_FI16m */ >+ 0x6fa, /* MUL_FI16m */ >+ 0x2fe, /* FICOM16m */ >+ 0x300, /* FICOMP16m */ >+ 0xb15, /* SUB_FI16m */ >+ 0xafb, /* SUBR_FI16m */ >+ 0x2c4, /* DIV_FI16m */ >+ 0x2aa, /* DIVR_FI16m */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x86, /* ADD_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0x6fc, /* MUL_FPrST0 */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0xabb, /* ST_FCOMPST0r_alt */ >+ 0x0, /* */ >+ 0x2fa, /* FCOMPP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xafd, /* SUBR_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0xb17, /* SUB_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2ac, /* DIVR_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+ 0x2c6, /* DIV_FPrST0 */ >+/* Table853 */ >+ 0x354, /* ILD_F16m */ >+ 0x3a6, /* ISTT_FP16m */ >+ 0x3b2, /* IST_F16m */ >+ 0x3b4, /* IST_FP16m */ >+ 0x2f4, /* FBLDm */ >+ 0x356, /* ILD_F64m */ >+ 0x2f5, /* FBSTPm */ >+ 0x3b6, /* IST_FP64m */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac5, /* ST_FXCHST0r_alt */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac1, /* ST_FPST0r */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0xac2, /* ST_FPST0r_alt */ >+ 0x30e, /* FNSTSW16r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0xb75, /* UCOM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x249, /* COM_FIPr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table925 */ >+ 0x51c, /* LOOPNE */ >+/* Table926 */ >+ 0x51b, /* LOOPE */ >+/* Table927 */ >+ 0x51a, /* LOOP */ >+/* Table928 */ >+ 0x436, /* JECXZ_32 */ >+/* Table929 */ >+ 0x37e, /* IN8ri */ >+/* Table930 */ >+ 0x37c, /* IN32ri */ >+/* Table931 */ >+ 0x76a, /* OUT8ir */ >+/* Table932 */ >+ 0x768, /* OUT32ir */ >+/* Table933 */ >+ 0x163, /* CALLpcrel32 */ >+/* Table934 */ >+ 0x44f, /* JMP_4 */ >+/* Table935 */ >+ 0x2f1, /* FARJMP32i */ >+/* Table936 */ >+ 0x44d, /* JMP_1 */ >+/* Table937 */ >+ 0x37f, /* IN8rr */ >+/* Table938 */ >+ 0x37d, /* IN32rr */ >+/* Table939 */ >+ 0x76b, /* OUT8rr */ >+/* Table940 */ >+ 0x769, /* OUT32rr */ >+/* Table941 */ >+ 0x4ff, /* LOCK_PREFIX */ >+/* Table942 */ >+ 0x396, /* INT1 */ >+/* Table943 */ >+ 0x93b, /* REPNE_PREFIX */ >+/* Table944 */ >+ 0x943, /* REP_PREFIX */ >+/* Table945 */ >+ 0x347, /* HLT */ >+/* Table946 */ >+ 0x172, /* CMC */ >+/* Table947 */ >+ 0xb55, /* TEST8mi */ >+ 0xb56, /* TEST8mi_alt */ >+ 0x73c, /* NOT8m */ >+ 0x714, /* NEG8m */ >+ 0x6e6, /* MUL8m */ >+ 0x378, /* IMUL8m */ >+ 0x2a2, /* DIV8m */ >+ 0x352, /* IDIV8m */ >+ 0xb57, /* TEST8ri */ >+ 0xb59, /* TEST8ri_alt */ >+ 0x73d, /* NOT8r */ >+ 0x715, /* NEG8r */ >+ 0x6e7, /* MUL8r */ >+ 0x379, /* IMUL8r */ >+ 0x2a3, /* DIV8r */ >+ 0x353, /* IDIV8r */ >+/* Table963 */ >+ 0xb47, /* TEST32mi */ >+ 0xb48, /* TEST32mi_alt */ >+ 0x738, /* NOT32m */ >+ 0x710, /* NEG32m */ >+ 0x6e2, /* MUL32m */ >+ 0x368, /* IMUL32m */ >+ 0x29e, /* DIV32m */ >+ 0x34e, /* IDIV32m */ >+ 0xb49, /* TEST32ri */ >+ 0xb4a, /* TEST32ri_alt */ >+ 0x739, /* NOT32r */ >+ 0x711, /* NEG32r */ >+ 0x6e3, /* MUL32r */ >+ 0x369, /* IMUL32r */ >+ 0x29f, /* DIV32r */ >+ 0x34f, /* IDIV32r */ >+/* Table979 */ >+ 0x16c, /* CLC */ >+/* Table980 */ >+ 0xaab, /* STC */ >+/* Table981 */ >+ 0x170, /* CLI */ >+/* Table982 */ >+ 0xaae, /* STI */ >+/* Table983 */ >+ 0x16d, /* CLD */ >+/* Table984 */ >+ 0xaac, /* STD */ >+/* Table985 */ >+ 0x38c, /* INC8m */ >+ 0x29a, /* DEC8m */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x38d, /* INC8r */ >+ 0x29b, /* DEC8r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1001 */ >+ 0x384, /* INC32m */ >+ 0x292, /* DEC32m */ >+ 0x15d, /* CALL32m */ >+ 0x2ed, /* FARCALL32m */ >+ 0x449, /* JMP32m */ >+ 0x2f2, /* FARJMP32m */ >+ 0x8d2, /* PUSH32rmm */ >+ 0x0, /* */ >+ 0x383, /* INC32_32r */ >+ 0x291, /* DEC32_32r */ >+ 0x15e, /* CALL32r */ >+ 0x0, /* */ >+ 0x44a, /* JMP32r */ >+ 0x0, /* */ >+ 0x8d3, /* PUSH32rmr */ >+ 0x0, /* */ >+/* Table1017 */ >+ 0x951, /* REX64_PREFIX */ >+/* Table1018 */ >+ 0x8d7, /* PUSH64r */ >+/* Table1019 */ >+ 0x85c, /* POP64r */ >+/* Table1020 */ >+ 0x0, /* */ >+ 0x6bf, /* MOVSX64_NOREXrr32 */ >+/* Table1022 */ >+ 0x8d5, /* PUSH64i32 */ >+/* Table1023 */ >+ 0x8d6, /* PUSH64i8 */ >+/* Table1024 */ >+ 0x4bf, /* LEA64_32r */ >+ 0x0, /* */ >+/* Table1026 */ >+ 0x85d, /* POP64rmm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x85e, /* POP64rmr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1042 */ >+ 0x1837, /* XCHG32ar64 */ >+/* Table1043 */ >+ 0x8e4, /* PUSHF64 */ >+/* Table1044 */ >+ 0x86d, /* POPF64 */ >+/* Table1045 */ >+ 0x652, /* MOV64o8a */ >+/* Table1046 */ >+ 0x650, /* MOV64o32a */ >+/* Table1047 */ >+ 0x649, /* MOV64ao8 */ >+/* Table1048 */ >+ 0x647, /* MOV64ao32 */ >+/* Table1049 */ >+ 0x94c, /* RETIQ */ >+/* Table1050 */ >+ 0x94f, /* RETQ */ >+/* Table1051 */ >+ 0x4c2, /* LEAVE64 */ >+/* Table1052 */ >+ 0x462, /* JRCXZ */ >+/* Table1053 */ >+ 0x160, /* CALL64pcrel32 */ >+/* Table1054 */ >+ 0x388, /* INC64_32m */ >+ 0x296, /* DEC64_32m */ >+ 0x15f, /* CALL64m */ >+ 0x2ed, /* FARCALL32m */ >+ 0x44b, /* JMP64m */ >+ 0x2f2, /* FARJMP32m */ >+ 0x8d8, /* PUSH64rmm */ >+ 0x0, /* */ >+ 0x389, /* INC64_32r */ >+ 0x297, /* DEC64_32r */ >+ 0x161, /* CALL64r */ >+ 0x0, /* */ >+ 0x44c, /* JMP64r */ >+ 0x0, /* */ >+ 0x8d9, /* PUSH64rmr */ >+ 0x0, /* */ >+/* Table1070 */ >+ 0x49, /* ADD16mr */ >+ 0x4f, /* ADD16rr */ >+/* Table1072 */ >+ 0x4e, /* ADD16rm */ >+ 0x51, /* ADD16rr_REV */ >+/* Table1074 */ >+ 0x46, /* ADD16i16 */ >+/* Table1075 */ >+ 0x8e0, /* PUSHES16 */ >+/* Table1076 */ >+ 0x869, /* POPES16 */ >+/* Table1077 */ >+ 0x741, /* OR16mr */ >+ 0x745, /* OR16rr */ >+/* Table1079 */ >+ 0x744, /* OR16rm */ >+ 0x746, /* OR16rr_REV */ >+/* Table1081 */ >+ 0x73e, /* OR16i16 */ >+/* Table1082 */ >+ 0x8dc, /* PUSHCS16 */ >+/* Table1083 */ >+ 0x23, /* ADC16mr */ >+ 0x27, /* ADC16rr */ >+/* Table1085 */ >+ 0x26, /* ADC16rm */ >+ 0x28, /* ADC16rr_REV */ >+/* Table1087 */ >+ 0x20, /* ADC16i16 */ >+/* Table1088 */ >+ 0x8eb, /* PUSHSS16 */ >+/* Table1089 */ >+ 0x874, /* POPSS16 */ >+/* Table1090 */ >+ 0x9d2, /* SBB16mr */ >+ 0x9d6, /* SBB16rr */ >+/* Table1092 */ >+ 0x9d5, /* SBB16rm */ >+ 0x9d7, /* SBB16rr_REV */ >+/* Table1094 */ >+ 0x9cf, /* SBB16i16 */ >+/* Table1095 */ >+ 0x8de, /* PUSHDS16 */ >+/* Table1096 */ >+ 0x867, /* POPDS16 */ >+/* Table1097 */ >+ 0xae, /* AND16mr */ >+ 0xb2, /* AND16rr */ >+/* Table1099 */ >+ 0xb1, /* AND16rm */ >+ 0xb3, /* AND16rr_REV */ >+/* Table1101 */ >+ 0xab, /* AND16i16 */ >+/* Table1102 */ >+ 0xad5, /* SUB16mr */ >+ 0xad9, /* SUB16rr */ >+/* Table1104 */ >+ 0xad8, /* SUB16rm */ >+ 0xada, /* SUB16rr_REV */ >+/* Table1106 */ >+ 0xad2, /* SUB16i16 */ >+/* Table1107 */ >+ 0x184b, /* XOR16mr */ >+ 0x184f, /* XOR16rr */ >+/* Table1109 */ >+ 0x184e, /* XOR16rm */ >+ 0x1850, /* XOR16rr_REV */ >+/* Table1111 */ >+ 0x1848, /* XOR16i16 */ >+/* Table1112 */ >+ 0x207, /* CMP16mr */ >+ 0x20b, /* CMP16rr */ >+/* Table1114 */ >+ 0x20a, /* CMP16rm */ >+ 0x20c, /* CMP16rr_REV */ >+/* Table1116 */ >+ 0x204, /* CMP16i16 */ >+/* Table1117 */ >+ 0x381, /* INC16r */ >+/* Table1118 */ >+ 0x28f, /* DEC16r */ >+/* Table1119 */ >+ 0x8cd, /* PUSH16r */ >+/* Table1120 */ >+ 0x856, /* POP16r */ >+/* Table1121 */ >+ 0x8da, /* PUSHA16 */ >+/* Table1122 */ >+ 0x85f, /* POPA16 */ >+/* Table1123 */ >+ 0x117, /* BOUNDS16rm */ >+ 0x0, /* */ >+/* Table1125 */ >+ 0x8ed, /* PUSHi16 */ >+/* Table1126 */ >+ 0x363, /* IMUL16rmi */ >+ 0x366, /* IMUL16rri */ >+/* Table1128 */ >+ 0x8cc, /* PUSH16i8 */ >+/* Table1129 */ >+ 0x364, /* IMUL16rmi8 */ >+ 0x367, /* IMUL16rri8 */ >+/* Table1131 */ >+ 0x394, /* INSW */ >+/* Table1132 */ >+ 0x76e, /* OUTSW */ >+/* Table1133 */ >+ 0x47, /* ADD16mi */ >+ 0x73f, /* OR16mi */ >+ 0x21, /* ADC16mi */ >+ 0x9d0, /* SBB16mi */ >+ 0xac, /* AND16mi */ >+ 0xad3, /* SUB16mi */ >+ 0x1849, /* XOR16mi */ >+ 0x205, /* CMP16mi */ >+ 0x4a, /* ADD16ri */ >+ 0x742, /* OR16ri */ >+ 0x24, /* ADC16ri */ >+ 0x9d3, /* SBB16ri */ >+ 0xaf, /* AND16ri */ >+ 0xad6, /* SUB16ri */ >+ 0x184c, /* XOR16ri */ >+ 0x208, /* CMP16ri */ >+/* Table1149 */ >+ 0x48, /* ADD16mi8 */ >+ 0x740, /* OR16mi8 */ >+ 0x22, /* ADC16mi8 */ >+ 0x9d1, /* SBB16mi8 */ >+ 0xad, /* AND16mi8 */ >+ 0xad4, /* SUB16mi8 */ >+ 0x184a, /* XOR16mi8 */ >+ 0x206, /* CMP16mi8 */ >+ 0x4b, /* ADD16ri8 */ >+ 0x743, /* OR16ri8 */ >+ 0x25, /* ADC16ri8 */ >+ 0x9d4, /* SBB16ri8 */ >+ 0xb0, /* AND16ri8 */ >+ 0xad7, /* SUB16ri8 */ >+ 0x184d, /* XOR16ri8 */ >+ 0x209, /* CMP16ri8 */ >+/* Table1165 */ >+ 0xb44, /* TEST16rm */ >+ 0xb45, /* TEST16rr */ >+/* Table1167 */ >+ 0x1834, /* XCHG16rm */ >+ 0x1835, /* XCHG16rr */ >+/* Table1169 */ >+ 0x625, /* MOV16mr */ >+ 0x62c, /* MOV16rr */ >+/* Table1171 */ >+ 0x62b, /* MOV16rm */ >+ 0x62d, /* MOV16rr_REV */ >+/* Table1173 */ >+ 0x626, /* MOV16ms */ >+ 0x62e, /* MOV16rs */ >+/* Table1175 */ >+ 0x4bd, /* LEA16r */ >+ 0x0, /* */ >+/* Table1177 */ >+ 0x62f, /* MOV16sm */ >+ 0x630, /* MOV16sr */ >+/* Table1179 */ >+ 0x857, /* POP16rmm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x858, /* POP16rmr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1195 */ >+ 0x1833, /* XCHG16ar */ >+/* Table1196 */ >+ 0x164, /* CBW */ >+/* Table1197 */ >+ 0x289, /* CWD */ >+/* Table1198 */ >+ 0x2ea, /* FARCALL16i */ >+/* Table1199 */ >+ 0x8e2, /* PUSHF16 */ >+/* Table1200 */ >+ 0x86b, /* POPF16 */ >+/* Table1201 */ >+ 0x627, /* MOV16o16a */ >+/* Table1202 */ >+ 0x622, /* MOV16ao16 */ >+/* Table1203 */ >+ 0x6b8, /* MOVSW */ >+/* Table1204 */ >+ 0x239, /* CMPSW */ >+/* Table1205 */ >+ 0xb3f, /* TEST16i16 */ >+/* Table1206 */ >+ 0xab3, /* STOSW */ >+/* Table1207 */ >+ 0x519, /* LODSW */ >+/* Table1208 */ >+ 0x9f4, /* SCASW */ >+/* Table1209 */ >+ 0x629, /* MOV16ri */ >+/* Table1210 */ >+ 0x954, /* ROL16mi */ >+ 0x96c, /* ROR16mi */ >+ 0x8f3, /* RCL16mi */ >+ 0x913, /* RCR16mi */ >+ 0xa37, /* SHL16mi */ >+ 0xa5f, /* SHR16mi */ >+ 0x99c, /* SAL16mi */ >+ 0x9b5, /* SAR16mi */ >+ 0x957, /* ROL16ri */ >+ 0x96f, /* ROR16ri */ >+ 0x8f6, /* RCL16ri */ >+ 0x916, /* RCR16ri */ >+ 0xa3a, /* SHL16ri */ >+ 0xa62, /* SHR16ri */ >+ 0x99f, /* SAL16ri */ >+ 0x9b8, /* SAR16ri */ >+/* Table1226 */ >+ 0x94d, /* RETIW */ >+/* Table1227 */ >+ 0x950, /* RETW */ >+/* Table1228 */ >+ 0x4c3, /* LES16rm */ >+ 0x0, /* */ >+/* Table1230 */ >+ 0x4a9, /* LDS16rm */ >+ 0x0, /* */ >+/* Table1232 */ >+ 0x624, /* MOV16mi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x62a, /* MOV16ri_alt */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1832, /* XBEGIN_4 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1304 */ >+ 0x51f, /* LRETIW */ >+/* Table1305 */ >+ 0x522, /* LRETW */ >+/* Table1306 */ >+ 0x3a3, /* IRET16 */ >+/* Table1307 */ >+ 0x952, /* ROL16m1 */ >+ 0x96a, /* ROR16m1 */ >+ 0x8f1, /* RCL16m1 */ >+ 0x911, /* RCR16m1 */ >+ 0xa35, /* SHL16m1 */ >+ 0xa5d, /* SHR16m1 */ >+ 0x99a, /* SAL16m1 */ >+ 0x9b3, /* SAR16m1 */ >+ 0x955, /* ROL16r1 */ >+ 0x96d, /* ROR16r1 */ >+ 0x8f4, /* RCL16r1 */ >+ 0x914, /* RCR16r1 */ >+ 0xa38, /* SHL16r1 */ >+ 0xa60, /* SHR16r1 */ >+ 0x99d, /* SAL16r1 */ >+ 0x9b6, /* SAR16r1 */ >+/* Table1323 */ >+ 0x953, /* ROL16mCL */ >+ 0x96b, /* ROR16mCL */ >+ 0x8f2, /* RCL16mCL */ >+ 0x912, /* RCR16mCL */ >+ 0xa36, /* SHL16mCL */ >+ 0xa5e, /* SHR16mCL */ >+ 0x99b, /* SAL16mCL */ >+ 0x9b4, /* SAR16mCL */ >+ 0x956, /* ROL16rCL */ >+ 0x96e, /* ROR16rCL */ >+ 0x8f5, /* RCL16rCL */ >+ 0x915, /* RCR16rCL */ >+ 0xa39, /* SHL16rCL */ >+ 0xa61, /* SHR16rCL */ >+ 0x99e, /* SAL16rCL */ >+ 0x9b7, /* SAR16rCL */ >+/* Table1339 */ >+ 0x37a, /* IN16ri */ >+/* Table1340 */ >+ 0x766, /* OUT16ir */ >+/* Table1341 */ >+ 0x162, /* CALLpcrel16 */ >+/* Table1342 */ >+ 0x44e, /* JMP_2 */ >+/* Table1343 */ >+ 0x2ef, /* FARJMP16i */ >+/* Table1344 */ >+ 0x37b, /* IN16rr */ >+/* Table1345 */ >+ 0x767, /* OUT16rr */ >+/* Table1346 */ >+ 0xb40, /* TEST16mi */ >+ 0xb41, /* TEST16mi_alt */ >+ 0x736, /* NOT16m */ >+ 0x70e, /* NEG16m */ >+ 0x6e0, /* MUL16m */ >+ 0x360, /* IMUL16m */ >+ 0x29c, /* DIV16m */ >+ 0x34c, /* IDIV16m */ >+ 0xb42, /* TEST16ri */ >+ 0xb43, /* TEST16ri_alt */ >+ 0x737, /* NOT16r */ >+ 0x70f, /* NEG16r */ >+ 0x6e1, /* MUL16r */ >+ 0x361, /* IMUL16r */ >+ 0x29d, /* DIV16r */ >+ 0x34d, /* IDIV16r */ >+/* Table1362 */ >+ 0x380, /* INC16m */ >+ 0x28e, /* DEC16m */ >+ 0x15b, /* CALL16m */ >+ 0x2eb, /* FARCALL16m */ >+ 0x447, /* JMP16m */ >+ 0x2f0, /* FARJMP16m */ >+ 0x8ce, /* PUSH16rmm */ >+ 0x0, /* */ >+ 0x382, /* INC32_16r */ >+ 0x290, /* DEC32_16r */ >+ 0x15c, /* CALL16r */ >+ 0x0, /* */ >+ 0x448, /* JMP16r */ >+ 0x0, /* */ >+ 0x8cf, /* PUSH16rmr */ >+ 0x0, /* */ >+/* Table1378 */ >+ 0x435, /* JCXZ */ >+/* Table1379 */ >+ 0x793, /* PAUSE */ >+/* Table1380 */ >+ 0x61, /* ADD64mr */ >+ 0x67, /* ADD64rr */ >+/* Table1382 */ >+ 0x66, /* ADD64rm */ >+ 0x69, /* ADD64rr_REV */ >+/* Table1384 */ >+ 0x5e, /* ADD64i32 */ >+/* Table1385 */ >+ 0x754, /* OR64mr */ >+ 0x758, /* OR64rr */ >+/* Table1387 */ >+ 0x757, /* OR64rm */ >+ 0x759, /* OR64rr_REV */ >+/* Table1389 */ >+ 0x751, /* OR64i32 */ >+/* Table1390 */ >+ 0x35, /* ADC64mr */ >+ 0x39, /* ADC64rr */ >+/* Table1392 */ >+ 0x38, /* ADC64rm */ >+ 0x3a, /* ADC64rr_REV */ >+/* Table1394 */ >+ 0x32, /* ADC64i32 */ >+/* Table1395 */ >+ 0x9e4, /* SBB64mr */ >+ 0x9e8, /* SBB64rr */ >+/* Table1397 */ >+ 0x9e7, /* SBB64rm */ >+ 0x9e9, /* SBB64rr_REV */ >+/* Table1399 */ >+ 0x9e1, /* SBB64i32 */ >+/* Table1400 */ >+ 0xc0, /* AND64mr */ >+ 0xc4, /* AND64rr */ >+/* Table1402 */ >+ 0xc3, /* AND64rm */ >+ 0xc5, /* AND64rr_REV */ >+/* Table1404 */ >+ 0xbd, /* AND64i32 */ >+/* Table1405 */ >+ 0xae7, /* SUB64mr */ >+ 0xaeb, /* SUB64rr */ >+/* Table1407 */ >+ 0xaea, /* SUB64rm */ >+ 0xaec, /* SUB64rr_REV */ >+/* Table1409 */ >+ 0xae4, /* SUB64i32 */ >+/* Table1410 */ >+ 0x185d, /* XOR64mr */ >+ 0x1861, /* XOR64rr */ >+/* Table1412 */ >+ 0x1860, /* XOR64rm */ >+ 0x1862, /* XOR64rr_REV */ >+/* Table1414 */ >+ 0x185a, /* XOR64i32 */ >+/* Table1415 */ >+ 0x219, /* CMP64mr */ >+ 0x21d, /* CMP64rr */ >+/* Table1417 */ >+ 0x21c, /* CMP64rm */ >+ 0x21e, /* CMP64rr_REV */ >+/* Table1419 */ >+ 0x216, /* CMP64i32 */ >+/* Table1420 */ >+ 0x6c1, /* MOVSX64rm32 */ >+ 0x6c4, /* MOVSX64rr32 */ >+/* Table1422 */ >+ 0x373, /* IMUL64rmi32 */ >+ 0x376, /* IMUL64rri32 */ >+/* Table1424 */ >+ 0x374, /* IMUL64rmi8 */ >+ 0x377, /* IMUL64rri8 */ >+/* Table1426 */ >+ 0x5f, /* ADD64mi32 */ >+ 0x752, /* OR64mi32 */ >+ 0x33, /* ADC64mi32 */ >+ 0x9e2, /* SBB64mi32 */ >+ 0xbe, /* AND64mi32 */ >+ 0xae5, /* SUB64mi32 */ >+ 0x185b, /* XOR64mi32 */ >+ 0x217, /* CMP64mi32 */ >+ 0x62, /* ADD64ri32 */ >+ 0x755, /* OR64ri32 */ >+ 0x36, /* ADC64ri32 */ >+ 0x9e5, /* SBB64ri32 */ >+ 0xc1, /* AND64ri32 */ >+ 0xae8, /* SUB64ri32 */ >+ 0x185e, /* XOR64ri32 */ >+ 0x21a, /* CMP64ri32 */ >+/* Table1442 */ >+ 0x60, /* ADD64mi8 */ >+ 0x753, /* OR64mi8 */ >+ 0x34, /* ADC64mi8 */ >+ 0x9e3, /* SBB64mi8 */ >+ 0xbf, /* AND64mi8 */ >+ 0xae6, /* SUB64mi8 */ >+ 0x185c, /* XOR64mi8 */ >+ 0x218, /* CMP64mi8 */ >+ 0x64, /* ADD64ri8 */ >+ 0x756, /* OR64ri8 */ >+ 0x37, /* ADC64ri8 */ >+ 0x9e6, /* SBB64ri8 */ >+ 0xc2, /* AND64ri8 */ >+ 0xae9, /* SUB64ri8 */ >+ 0x185f, /* XOR64ri8 */ >+ 0x21b, /* CMP64ri8 */ >+/* Table1458 */ >+ 0xb52, /* TEST64rm */ >+ 0xb53, /* TEST64rr */ >+/* Table1460 */ >+ 0x183b, /* XCHG64rm */ >+ 0x183c, /* XCHG64rr */ >+/* Table1462 */ >+ 0x64d, /* MOV64mr */ >+ 0x658, /* MOV64rr */ >+/* Table1464 */ >+ 0x657, /* MOV64rm */ >+ 0x659, /* MOV64rr_REV */ >+/* Table1466 */ >+ 0x64e, /* MOV64ms */ >+ 0x65a, /* MOV64rs */ >+/* Table1468 */ >+ 0x4c0, /* LEA64r */ >+ 0x0, /* */ >+/* Table1470 */ >+ 0x65b, /* MOV64sm */ >+ 0x65c, /* MOV64sr */ >+/* Table1472 */ >+ 0x183a, /* XCHG64ar */ >+/* Table1473 */ >+ 0x166, /* CDQE */ >+/* Table1474 */ >+ 0x252, /* CQO */ >+/* Table1475 */ >+ 0x651, /* MOV64o64a */ >+/* Table1476 */ >+ 0x648, /* MOV64ao64 */ >+/* Table1477 */ >+ 0x6b1, /* MOVSQ */ >+/* Table1478 */ >+ 0x234, /* CMPSQ */ >+/* Table1479 */ >+ 0xb4d, /* TEST64i32 */ >+/* Table1480 */ >+ 0xab2, /* STOSQ */ >+/* Table1481 */ >+ 0x518, /* LODSQ */ >+/* Table1482 */ >+ 0x9f3, /* SCASQ */ >+/* Table1483 */ >+ 0x655, /* MOV64ri */ >+/* Table1484 */ >+ 0x960, /* ROL64mi */ >+ 0x978, /* ROR64mi */ >+ 0x8ff, /* RCL64mi */ >+ 0x91f, /* RCR64mi */ >+ 0xa43, /* SHL64mi */ >+ 0xa6b, /* SHR64mi */ >+ 0x9a8, /* SAL64mi */ >+ 0x9c1, /* SAR64mi */ >+ 0x963, /* ROL64ri */ >+ 0x97b, /* ROR64ri */ >+ 0x902, /* RCL64ri */ >+ 0x922, /* RCR64ri */ >+ 0xa46, /* SHL64ri */ >+ 0xa6e, /* SHR64ri */ >+ 0x9ab, /* SAL64ri */ >+ 0x9c4, /* SAR64ri */ >+/* Table1500 */ >+ 0x64c, /* MOV64mi32 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x656, /* MOV64ri32 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1832, /* XBEGIN_4 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1572 */ >+ 0x51e, /* LRETIQ */ >+/* Table1573 */ >+ 0x521, /* LRETQ */ >+/* Table1574 */ >+ 0x3a5, /* IRET64 */ >+/* Table1575 */ >+ 0x95e, /* ROL64m1 */ >+ 0x976, /* ROR64m1 */ >+ 0x8fd, /* RCL64m1 */ >+ 0x91d, /* RCR64m1 */ >+ 0xa41, /* SHL64m1 */ >+ 0xa69, /* SHR64m1 */ >+ 0x9a6, /* SAL64m1 */ >+ 0x9bf, /* SAR64m1 */ >+ 0x961, /* ROL64r1 */ >+ 0x979, /* ROR64r1 */ >+ 0x900, /* RCL64r1 */ >+ 0x920, /* RCR64r1 */ >+ 0xa44, /* SHL64r1 */ >+ 0xa6c, /* SHR64r1 */ >+ 0x9a9, /* SAL64r1 */ >+ 0x9c2, /* SAR64r1 */ >+/* Table1591 */ >+ 0x95f, /* ROL64mCL */ >+ 0x977, /* ROR64mCL */ >+ 0x8fe, /* RCL64mCL */ >+ 0x91e, /* RCR64mCL */ >+ 0xa42, /* SHL64mCL */ >+ 0xa6a, /* SHR64mCL */ >+ 0x9a7, /* SAL64mCL */ >+ 0x9c0, /* SAR64mCL */ >+ 0x962, /* ROL64rCL */ >+ 0x97a, /* ROR64rCL */ >+ 0x901, /* RCL64rCL */ >+ 0x921, /* RCR64rCL */ >+ 0xa45, /* SHL64rCL */ >+ 0xa6d, /* SHR64rCL */ >+ 0x9aa, /* SAL64rCL */ >+ 0x9c3, /* SAR64rCL */ >+/* Table1607 */ >+ 0xb4e, /* TEST64mi32 */ >+ 0xb4f, /* TEST64mi32_alt */ >+ 0x73a, /* NOT64m */ >+ 0x712, /* NEG64m */ >+ 0x6e4, /* MUL64m */ >+ 0x370, /* IMUL64m */ >+ 0x2a0, /* DIV64m */ >+ 0x350, /* IDIV64m */ >+ 0xb50, /* TEST64ri32 */ >+ 0xb51, /* TEST64ri32_alt */ >+ 0x73b, /* NOT64r */ >+ 0x713, /* NEG64r */ >+ 0x6e5, /* MUL64r */ >+ 0x371, /* IMUL64r */ >+ 0x2a1, /* DIV64r */ >+ 0x351, /* IDIV64r */ >+/* Table1623 */ >+ 0x38a, /* INC64m */ >+ 0x298, /* DEC64m */ >+ 0x15f, /* CALL64m */ >+ 0x2ee, /* FARCALL64 */ >+ 0x44b, /* JMP64m */ >+ 0x2f3, /* FARJMP64 */ >+ 0x8d8, /* PUSH64rmm */ >+ 0x0, /* */ >+ 0x38b, /* INC64r */ >+ 0x299, /* DEC64r */ >+ 0x161, /* CALL64r */ >+ 0x0, /* */ >+ 0x44c, /* JMP64r */ >+ 0x0, /* */ >+ 0x8d9, /* PUSH64rmr */ >+ 0x0, /* */ >+/* Table1639 */ >+ 0x8d4, /* PUSH64i16 */ >+/* Table1640 */ >+ 0x64f, /* MOV64o16a */ >+/* Table1641 */ >+ 0x646, /* MOV64ao16 */ >+/* Table1642 */ >+ 0x386, /* INC64_16m */ >+ 0x294, /* DEC64_16m */ >+ 0x15f, /* CALL64m */ >+ 0x2eb, /* FARCALL16m */ >+ 0x44b, /* JMP64m */ >+ 0x2f0, /* FARJMP16m */ >+ 0x8ce, /* PUSH16rmm */ >+ 0x0, /* */ >+ 0x387, /* INC64_16r */ >+ 0x295, /* DEC64_16r */ >+ 0x161, /* CALL64r */ >+ 0x0, /* */ >+ 0x44c, /* JMP64r */ >+ 0x0, /* */ >+ 0x8cf, /* PUSH16rmr */ >+ 0x0, /* */ >+/* Table1658 */ >+ 0x437, /* JECXZ_64 */ >+/* Table1659 */ >+ 0x38a, /* INC64m */ >+ 0x298, /* DEC64m */ >+ 0x15f, /* CALL64m */ >+ 0x2ee, /* FARCALL64 */ >+ 0x44b, /* JMP64m */ >+ 0x2f3, /* FARJMP64 */ >+ 0x8ce, /* PUSH16rmm */ >+ 0x0, /* */ >+ 0x38b, /* INC64r */ >+ 0x299, /* DEC64r */ >+ 0x161, /* CALL64r */ >+ 0x0, /* */ >+ 0x44c, /* JMP64r */ >+ 0x0, /* */ >+ 0x8cf, /* PUSH16rmr */ >+ 0x0, /* */ >+/* Table1675 */ >+ 0xa91, /* SLDT16m */ >+ 0xab7, /* STRm */ >+ 0x4d2, /* LLDT16m */ >+ 0x52c, /* LTRm */ >+ 0xcfe, /* VERRm */ >+ 0xd00, /* VERWm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa93, /* SLDT32r */ >+ 0xab5, /* STR32r */ >+ 0x4d3, /* LLDT16r */ >+ 0x52d, /* LTRr */ >+ 0xcff, /* VERRr */ >+ 0xd01, /* VERWr */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1691 */ >+ 0xa25, /* SGDT32m */ >+ 0xa8a, /* SIDT32m */ >+ 0x4ca, /* LGDT32m */ >+ 0x4d0, /* LIDT32m */ >+ 0xa96, /* SMSW16m */ >+ 0x0, /* */ >+ 0x4d4, /* LMSW16m */ >+ 0x39c, /* INVLPG */ >+ 0x0, /* */ >+ 0xf5d, /* VMCALL */ >+ 0xf92, /* VMLAUNCH */ >+ 0x1188, /* VMRESUME */ >+ 0x11b7, /* VMXOFF */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61e, /* MONITORrrr */ >+ 0x70d, /* MWAITrr */ >+ 0x16b, /* CLAC */ >+ 0xaaa, /* STAC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x2e2, /* ENCLS */ >+ 0x1846, /* XGETBV */ >+ 0x1876, /* XSETBV */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5f, /* VMFUNC */ >+ 0x1845, /* XEND */ >+ 0x187a, /* XTEST */ >+ 0x2e3, /* ENCLU */ >+ 0x1189, /* VMRUN32 */ >+ 0xf95, /* VMMCALL */ >+ 0xf93, /* VMLOAD32 */ >+ 0x118b, /* VMSAVE32 */ >+ 0xaad, /* STGI */ >+ 0x16f, /* CLGI */ >+ 0xa90, /* SKINIT */ >+ 0x39d, /* INVLPGA32 */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0xb28, /* SWAPGS */ >+ 0x936, /* RDTSCP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1763 */ >+ 0x49d, /* LAR32rm */ >+ 0x49e, /* LAR32rr */ >+/* Table1765 */ >+ 0x525, /* LSL32rm */ >+ 0x526, /* LSL32rr */ >+/* Table1767 */ >+ 0xb29, /* SYSCALL */ >+/* Table1768 */ >+ 0x171, /* CLTS */ >+/* Table1769 */ >+ 0xb2d, /* SYSRET */ >+/* Table1770 */ >+ 0x399, /* INVD */ >+/* Table1771 */ >+ 0x181e, /* WBINVD */ >+/* Table1772 */ >+ 0xb62, /* TRAP */ >+/* Table1773 */ >+ 0x0, /* */ >+ 0x87d, /* PREFETCHW */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table1789 */ >+ 0x6cb, /* MOVUPSrm */ >+ 0x6cc, /* MOVUPSrr */ >+/* Table1791 */ >+ 0x6ca, /* MOVUPSmr */ >+ 0x6cd, /* MOVUPSrr_REV */ >+/* Table1793 */ >+ 0x693, /* MOVLPSrm */ >+ 0x68a, /* MOVHLPSrr */ >+/* Table1795 */ >+ 0x692, /* MOVLPSmr */ >+ 0x0, /* */ >+/* Table1797 */ >+ 0xb87, /* UNPCKLPSrm */ >+ 0xb88, /* UNPCKLPSrr */ >+/* Table1799 */ >+ 0xb83, /* UNPCKHPSrm */ >+ 0xb84, /* UNPCKHPSrr */ >+/* Table1801 */ >+ 0x68e, /* MOVHPSrm */ >+ 0x68f, /* MOVLHPSrr */ >+/* Table1803 */ >+ 0x68d, /* MOVHPSmr */ >+ 0x0, /* */ >+/* Table1805 */ >+ 0x879, /* PREFETCHNTA */ >+ 0x87a, /* PREFETCHT0 */ >+ 0x87b, /* PREFETCHT1 */ >+ 0x87c, /* PREFETCHT2 */ >+ 0x71f, /* NOOP18_m4 */ >+ 0x720, /* NOOP18_m5 */ >+ 0x721, /* NOOP18_m6 */ >+ 0x722, /* NOOP18_m7 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x723, /* NOOP18_r4 */ >+ 0x724, /* NOOP18_r5 */ >+ 0x725, /* NOOP18_r6 */ >+ 0x726, /* NOOP18_r7 */ >+/* Table1821 */ >+ 0x729, /* NOOPL_19 */ >+ 0x727, /* NOOP19rr */ >+/* Table1823 */ >+ 0x72a, /* NOOPL_1a */ >+ 0x0, /* */ >+/* Table1825 */ >+ 0x72b, /* NOOPL_1b */ >+ 0x0, /* */ >+/* Table1827 */ >+ 0x72c, /* NOOPL_1c */ >+ 0x0, /* */ >+/* Table1829 */ >+ 0x72d, /* NOOPL_1d */ >+ 0x0, /* */ >+/* Table1831 */ >+ 0x72e, /* NOOPL_1e */ >+ 0x0, /* */ >+/* Table1833 */ >+ 0x728, /* NOOPL */ >+ 0x0, /* */ >+/* Table1835 */ >+ 0x0, /* */ >+ 0x63b, /* MOV32rc */ >+/* Table1837 */ >+ 0x0, /* */ >+ 0x63c, /* MOV32rd */ >+/* Table1839 */ >+ 0x0, /* */ >+ 0x633, /* MOV32cr */ >+/* Table1841 */ >+ 0x0, /* */ >+ 0x634, /* MOV32dr */ >+/* Table1843 */ >+ 0x673, /* MOVAPSrm */ >+ 0x674, /* MOVAPSrr */ >+/* Table1845 */ >+ 0x672, /* MOVAPSmr */ >+ 0x675, /* MOVAPSrr_REV */ >+/* Table1847 */ >+ 0x567, /* MMX_CVTPI2PSirm */ >+ 0x568, /* MMX_CVTPI2PSirr */ >+/* Table1849 */ >+ 0x69b, /* MOVNTPSmr */ >+ 0x0, /* */ >+/* Table1851 */ >+ 0x56d, /* MMX_CVTTPS2PIirm */ >+ 0x56e, /* MMX_CVTTPS2PIirr */ >+/* Table1853 */ >+ 0x569, /* MMX_CVTPS2PIirm */ >+ 0x56a, /* MMX_CVTPS2PIirr */ >+/* Table1855 */ >+ 0xb73, /* UCOMISSrm */ >+ 0xb74, /* UCOMISSrr */ >+/* Table1857 */ >+ 0x246, /* COMISSrm */ >+ 0x247, /* COMISSrr */ >+/* Table1859 */ >+ 0x1826, /* WRMSR */ >+/* Table1860 */ >+ 0x935, /* RDTSC */ >+/* Table1861 */ >+ 0x92d, /* RDMSR */ >+/* Table1862 */ >+ 0x92e, /* RDPMC */ >+/* Table1863 */ >+ 0xb2a, /* SYSENTER */ >+/* Table1864 */ >+ 0xb2b, /* SYSEXIT */ >+/* Table1865 */ >+ 0x342, /* GETSEC */ >+/* Table1866 */ >+ 0x1df, /* CMOVO32rm */ >+ 0x1e0, /* CMOVO32rr */ >+/* Table1868 */ >+ 0x1c9, /* CMOVNO32rm */ >+ 0x1ca, /* CMOVNO32rr */ >+/* Table1870 */ >+ 0x181, /* CMOVB32rm */ >+ 0x182, /* CMOVB32rr */ >+/* Table1872 */ >+ 0x17b, /* CMOVAE32rm */ >+ 0x17c, /* CMOVAE32rr */ >+/* Table1874 */ >+ 0x195, /* CMOVE32rm */ >+ 0x196, /* CMOVE32rr */ >+/* Table1876 */ >+ 0x1bf, /* CMOVNE32rm */ >+ 0x1c0, /* CMOVNE32rr */ >+/* Table1878 */ >+ 0x187, /* CMOVBE32rm */ >+ 0x188, /* CMOVBE32rr */ >+/* Table1880 */ >+ 0x175, /* CMOVA32rm */ >+ 0x176, /* CMOVA32rr */ >+/* Table1882 */ >+ 0x1ef, /* CMOVS32rm */ >+ 0x1f0, /* CMOVS32rr */ >+/* Table1884 */ >+ 0x1d9, /* CMOVNS32rm */ >+ 0x1da, /* CMOVNS32rr */ >+/* Table1886 */ >+ 0x1e5, /* CMOVP32rm */ >+ 0x1e6, /* CMOVP32rr */ >+/* Table1888 */ >+ 0x1cf, /* CMOVNP32rm */ >+ 0x1d0, /* CMOVNP32rr */ >+/* Table1890 */ >+ 0x1ab, /* CMOVL32rm */ >+ 0x1ac, /* CMOVL32rr */ >+/* Table1892 */ >+ 0x1a5, /* CMOVGE32rm */ >+ 0x1a6, /* CMOVGE32rr */ >+/* Table1894 */ >+ 0x1b1, /* CMOVLE32rm */ >+ 0x1b2, /* CMOVLE32rr */ >+/* Table1896 */ >+ 0x19f, /* CMOVG32rm */ >+ 0x1a0, /* CMOVG32rr */ >+/* Table1898 */ >+ 0x0, /* */ >+ 0x695, /* MOVMSKPSrr */ >+/* Table1900 */ >+ 0xa9c, /* SQRTPSm */ >+ 0xa9d, /* SQRTPSr */ >+/* Table1902 */ >+ 0x991, /* RSQRTPSm */ >+ 0x993, /* RSQRTPSr */ >+/* Table1904 */ >+ 0x909, /* RCPPSm */ >+ 0x90b, /* RCPPSr */ >+/* Table1906 */ >+ 0xd8, /* ANDPSrm */ >+ 0xd9, /* ANDPSrr */ >+/* Table1908 */ >+ 0xd4, /* ANDNPSrm */ >+ 0xd5, /* ANDNPSrr */ >+/* Table1910 */ >+ 0x764, /* ORPSrm */ >+ 0x765, /* ORPSrr */ >+/* Table1912 */ >+ 0x186d, /* XORPSrm */ >+ 0x186e, /* XORPSrr */ >+/* Table1914 */ >+ 0x74, /* ADDPSrm */ >+ 0x75, /* ADDPSrr */ >+/* Table1916 */ >+ 0x6ea, /* MULPSrm */ >+ 0x6eb, /* MULPSrr */ >+/* Table1918 */ >+ 0x267, /* CVTPS2PDrm */ >+ 0x268, /* CVTPS2PDrr */ >+/* Table1920 */ >+ 0x25f, /* CVTDQ2PSrm */ >+ 0x260, /* CVTDQ2PSrr */ >+/* Table1922 */ >+ 0xaf7, /* SUBPSrm */ >+ 0xaf8, /* SUBPSrr */ >+/* Table1924 */ >+ 0x559, /* MINPSrm */ >+ 0x55a, /* MINPSrr */ >+/* Table1926 */ >+ 0x2a6, /* DIVPSrm */ >+ 0x2a7, /* DIVPSrr */ >+/* Table1928 */ >+ 0x544, /* MAXPSrm */ >+ 0x545, /* MAXPSrr */ >+/* Table1930 */ >+ 0x615, /* MMX_PUNPCKLBWirm */ >+ 0x616, /* MMX_PUNPCKLBWirr */ >+/* Table1932 */ >+ 0x619, /* MMX_PUNPCKLWDirm */ >+ 0x61a, /* MMX_PUNPCKLWDirr */ >+/* Table1934 */ >+ 0x617, /* MMX_PUNPCKLDQirm */ >+ 0x618, /* MMX_PUNPCKLDQirr */ >+/* Table1936 */ >+ 0x589, /* MMX_PACKSSWBirm */ >+ 0x58a, /* MMX_PACKSSWBirr */ >+/* Table1938 */ >+ 0x5ad, /* MMX_PCMPGTBirm */ >+ 0x5ae, /* MMX_PCMPGTBirr */ >+/* Table1940 */ >+ 0x5b1, /* MMX_PCMPGTWirm */ >+ 0x5b2, /* MMX_PCMPGTWirr */ >+/* Table1942 */ >+ 0x5af, /* MMX_PCMPGTDirm */ >+ 0x5b0, /* MMX_PCMPGTDirr */ >+/* Table1944 */ >+ 0x58b, /* MMX_PACKUSWBirm */ >+ 0x58c, /* MMX_PACKUSWBirr */ >+/* Table1946 */ >+ 0x60f, /* MMX_PUNPCKHBWirm */ >+ 0x610, /* MMX_PUNPCKHBWirr */ >+/* Table1948 */ >+ 0x613, /* MMX_PUNPCKHWDirm */ >+ 0x614, /* MMX_PUNPCKHWDirr */ >+/* Table1950 */ >+ 0x611, /* MMX_PUNPCKHDQirm */ >+ 0x612, /* MMX_PUNPCKHDQirr */ >+/* Table1952 */ >+ 0x587, /* MMX_PACKSSDWirm */ >+ 0x588, /* MMX_PACKSSDWirr */ >+/* Table1954 */ >+ 0x575, /* MMX_MOVD64rm */ >+ 0x576, /* MMX_MOVD64rr */ >+/* Table1956 */ >+ 0x57e, /* MMX_MOVQ64rm */ >+ 0x57f, /* MMX_MOVQ64rr */ >+/* Table1958 */ >+ 0x5df, /* MMX_PSHUFWmi */ >+ 0x5e0, /* MMX_PSHUFWri */ >+/* Table1960 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x5fc, /* MMX_PSRLWri */ >+ 0x0, /* */ >+ 0x5f3, /* MMX_PSRAWri */ >+ 0x0, /* */ >+ 0x5ed, /* MMX_PSLLWri */ >+ 0x0, /* */ >+/* Table1976 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x5f6, /* MMX_PSRLDri */ >+ 0x0, /* */ >+ 0x5f0, /* MMX_PSRADri */ >+ 0x0, /* */ >+ 0x5e7, /* MMX_PSLLDri */ >+ 0x0, /* */ >+/* Table1992 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x5f9, /* MMX_PSRLQri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x5ea, /* MMX_PSLLQri */ >+ 0x0, /* */ >+/* Table2008 */ >+ 0x5a7, /* MMX_PCMPEQBirm */ >+ 0x5a8, /* MMX_PCMPEQBirr */ >+/* Table2010 */ >+ 0x5ab, /* MMX_PCMPEQWirm */ >+ 0x5ac, /* MMX_PCMPEQWirr */ >+/* Table2012 */ >+ 0x5a9, /* MMX_PCMPEQDirm */ >+ 0x5aa, /* MMX_PCMPEQDirr */ >+/* Table2014 */ >+ 0x56f, /* MMX_EMMS */ >+/* Table2015 */ >+ 0x1184, /* VMREAD32rm */ >+ 0x1185, /* VMREAD32rr */ >+/* Table2017 */ >+ 0x11b3, /* VMWRITE32rm */ >+ 0x11b4, /* VMWRITE32rr */ >+/* Table2019 */ >+ 0x574, /* MMX_MOVD64mr */ >+ 0x573, /* MMX_MOVD64grr */ >+/* Table2021 */ >+ 0x57d, /* MMX_MOVQ64mr */ >+ 0x580, /* MMX_MOVQ64rr_REV */ >+/* Table2023 */ >+ 0x45e, /* JO_4 */ >+/* Table2024 */ >+ 0x455, /* JNO_4 */ >+/* Table2025 */ >+ 0x434, /* JB_4 */ >+/* Table2026 */ >+ 0x42b, /* JAE_4 */ >+/* Table2027 */ >+ 0x43a, /* JE_4 */ >+/* Table2028 */ >+ 0x452, /* JNE_4 */ >+/* Table2029 */ >+ 0x431, /* JBE_4 */ >+/* Table2030 */ >+ 0x42e, /* JA_4 */ >+/* Table2031 */ >+ 0x465, /* JS_4 */ >+/* Table2032 */ >+ 0x45b, /* JNS_4 */ >+/* Table2033 */ >+ 0x461, /* JP_4 */ >+/* Table2034 */ >+ 0x458, /* JNP_4 */ >+/* Table2035 */ >+ 0x446, /* JL_4 */ >+/* Table2036 */ >+ 0x43d, /* JGE_4 */ >+/* Table2037 */ >+ 0x443, /* JLE_4 */ >+/* Table2038 */ >+ 0x440, /* JG_4 */ >+/* Table2039 */ >+ 0xa1d, /* SETOm */ >+ 0xa1e, /* SETOr */ >+/* Table2041 */ >+ 0xa17, /* SETNOm */ >+ 0xa18, /* SETNOr */ >+/* Table2043 */ >+ 0xa09, /* SETBm */ >+ 0xa0a, /* SETBr */ >+/* Table2045 */ >+ 0x9ff, /* SETAEm */ >+ 0xa00, /* SETAEr */ >+/* Table2047 */ >+ 0xa0b, /* SETEm */ >+ 0xa0c, /* SETEr */ >+/* Table2049 */ >+ 0xa15, /* SETNEm */ >+ 0xa16, /* SETNEr */ >+/* Table2051 */ >+ 0xa03, /* SETBEm */ >+ 0xa04, /* SETBEr */ >+/* Table2053 */ >+ 0xa01, /* SETAm */ >+ 0xa02, /* SETAr */ >+/* Table2055 */ >+ 0xa21, /* SETSm */ >+ 0xa22, /* SETSr */ >+/* Table2057 */ >+ 0xa1b, /* SETNSm */ >+ 0xa1c, /* SETNSr */ >+/* Table2059 */ >+ 0xa1f, /* SETPm */ >+ 0xa20, /* SETPr */ >+/* Table2061 */ >+ 0xa19, /* SETNPm */ >+ 0xa1a, /* SETNPr */ >+/* Table2063 */ >+ 0xa13, /* SETLm */ >+ 0xa14, /* SETLr */ >+/* Table2065 */ >+ 0xa0d, /* SETGEm */ >+ 0xa0e, /* SETGEr */ >+/* Table2067 */ >+ 0xa11, /* SETLEm */ >+ 0xa12, /* SETLEr */ >+/* Table2069 */ >+ 0xa0f, /* SETGm */ >+ 0xa10, /* SETGr */ >+/* Table2071 */ >+ 0x8e6, /* PUSHFS32 */ >+/* Table2072 */ >+ 0x86f, /* POPFS32 */ >+/* Table2073 */ >+ 0x250, /* CPUID32 */ >+/* Table2074 */ >+ 0x12c, /* BT32mr */ >+ 0x12e, /* BT32rr */ >+/* Table2076 */ >+ 0xa52, /* SHLD32mri8 */ >+ 0xa54, /* SHLD32rri8 */ >+/* Table2078 */ >+ 0xa51, /* SHLD32mrCL */ >+ 0xa53, /* SHLD32rrCL */ >+/* Table2080 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61f, /* MONTMUL */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1877, /* XSHA1 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1878, /* XSHA256 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2152 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1879, /* XSTORE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1843, /* XCRYPTECB */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1840, /* XCRYPTCBC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1842, /* XCRYPTCTR */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1841, /* XCRYPTCFB */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1844, /* XCRYPTOFB */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2224 */ >+ 0x8e9, /* PUSHGS32 */ >+/* Table2225 */ >+ 0x872, /* POPGS32 */ >+/* Table2226 */ >+ 0x990, /* RSM */ >+/* Table2227 */ >+ 0x150, /* BTS32mr */ >+ 0x152, /* BTS32rr */ >+/* Table2229 */ >+ 0xa7a, /* SHRD32mri8 */ >+ 0xa7c, /* SHRD32rri8 */ >+/* Table2231 */ >+ 0xa79, /* SHRD32mrCL */ >+ 0xa7b, /* SHRD32rrCL */ >+/* Table2233 */ >+ 0x327, /* FXSAVE */ >+ 0x325, /* FXRSTOR */ >+ 0x4a8, /* LDMXCSR */ >+ 0xaaf, /* STMXCSR */ >+ 0x1872, /* XSAVE */ >+ 0x1870, /* XRSTOR */ >+ 0x1874, /* XSAVEOPT */ >+ 0x16e, /* CLFLUSH */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4c5, /* LFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x54e, /* MFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa23, /* SFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2305 */ >+ 0x36a, /* IMUL32rm */ >+ 0x36d, /* IMUL32rr */ >+/* Table2307 */ >+ 0x242, /* CMPXCHG8rm */ >+ 0x243, /* CMPXCHG8rr */ >+/* Table2309 */ >+ 0x23d, /* CMPXCHG32rm */ >+ 0x23e, /* CMPXCHG32rr */ >+/* Table2311 */ >+ 0x52a, /* LSS32rm */ >+ 0x0, /* */ >+/* Table2313 */ >+ 0x144, /* BTR32mr */ >+ 0x146, /* BTR32rr */ >+/* Table2315 */ >+ 0x4c7, /* LFS32rm */ >+ 0x0, /* */ >+/* Table2317 */ >+ 0x4cd, /* LGS32rm */ >+ 0x0, /* */ >+/* Table2319 */ >+ 0x6d7, /* MOVZX32rm8 */ >+ 0x6d9, /* MOVZX32rr8 */ >+/* Table2321 */ >+ 0x6d6, /* MOVZX32rm16 */ >+ 0x6d8, /* MOVZX32rr16 */ >+/* Table2323 */ >+ 0xb80, /* UD2B */ >+/* Table2324 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x12b, /* BT32mi8 */ >+ 0x14f, /* BTS32mi8 */ >+ 0x143, /* BTR32mi8 */ >+ 0x137, /* BTC32mi8 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x12d, /* BT32ri8 */ >+ 0x151, /* BTS32ri8 */ >+ 0x145, /* BTR32ri8 */ >+ 0x139, /* BTC32ri8 */ >+/* Table2340 */ >+ 0x138, /* BTC32mr */ >+ 0x13a, /* BTC32rr */ >+/* Table2342 */ >+ 0x11b, /* BSF32rm */ >+ 0x11c, /* BSF32rr */ >+/* Table2344 */ >+ 0x121, /* BSR32rm */ >+ 0x122, /* BSR32rr */ >+/* Table2346 */ >+ 0x6bc, /* MOVSX32rm8 */ >+ 0x6be, /* MOVSX32rr8 */ >+/* Table2348 */ >+ 0x6bb, /* MOVSX32rm16 */ >+ 0x6bd, /* MOVSX32rr16 */ >+/* Table2350 */ >+ 0x182f, /* XADD8rm */ >+ 0x1830, /* XADD8rr */ >+/* Table2352 */ >+ 0x182b, /* XADD32rm */ >+ 0x182c, /* XADD32rr */ >+/* Table2354 */ >+ 0x22a, /* CMPPSrmi */ >+ 0x22c, /* CMPPSrri */ >+/* Table2356 */ >+ 0x699, /* MOVNTImr */ >+ 0x0, /* */ >+/* Table2358 */ >+ 0x5c0, /* MMX_PINSRWirmi */ >+ 0x5c1, /* MMX_PINSRWirri */ >+/* Table2360 */ >+ 0x0, /* */ >+ 0x5b3, /* MMX_PEXTRWirri */ >+/* Table2362 */ >+ 0xa87, /* SHUFPSrmi */ >+ 0xa88, /* SHUFPSrri */ >+/* Table2364 */ >+ 0x0, /* */ >+ 0x241, /* CMPXCHG8B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1182, /* VMPTRLDm */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x930, /* RDRAND32r */ >+ 0x933, /* RDSEED32r */ >+/* Table2380 */ >+ 0x125, /* BSWAP32r */ >+/* Table2381 */ >+ 0x5fd, /* MMX_PSRLWrm */ >+ 0x5fe, /* MMX_PSRLWrr */ >+/* Table2383 */ >+ 0x5f7, /* MMX_PSRLDrm */ >+ 0x5f8, /* MMX_PSRLDrr */ >+/* Table2385 */ >+ 0x5fa, /* MMX_PSRLQrm */ >+ 0x5fb, /* MMX_PSRLQrr */ >+/* Table2387 */ >+ 0x591, /* MMX_PADDQirm */ >+ 0x592, /* MMX_PADDQirr */ >+/* Table2389 */ >+ 0x5d5, /* MMX_PMULLWirm */ >+ 0x5d6, /* MMX_PMULLWirr */ >+/* Table2391 */ >+ 0x0, /* */ >+ 0x5ce, /* MMX_PMOVMSKBrr */ >+/* Table2393 */ >+ 0x609, /* MMX_PSUBUSBirm */ >+ 0x60a, /* MMX_PSUBUSBirr */ >+/* Table2395 */ >+ 0x60b, /* MMX_PSUBUSWirm */ >+ 0x60c, /* MMX_PSUBUSWirr */ >+/* Table2397 */ >+ 0x5cc, /* MMX_PMINUBirm */ >+ 0x5cd, /* MMX_PMINUBirr */ >+/* Table2399 */ >+ 0x5a1, /* MMX_PANDirm */ >+ 0x5a2, /* MMX_PANDirr */ >+/* Table2401 */ >+ 0x597, /* MMX_PADDUSBirm */ >+ 0x598, /* MMX_PADDUSBirr */ >+/* Table2403 */ >+ 0x599, /* MMX_PADDUSWirm */ >+ 0x59a, /* MMX_PADDUSWirr */ >+/* Table2405 */ >+ 0x5c8, /* MMX_PMAXUBirm */ >+ 0x5c9, /* MMX_PMAXUBirr */ >+/* Table2407 */ >+ 0x59f, /* MMX_PANDNirm */ >+ 0x5a0, /* MMX_PANDNirr */ >+/* Table2409 */ >+ 0x5a3, /* MMX_PAVGBirm */ >+ 0x5a4, /* MMX_PAVGBirr */ >+/* Table2411 */ >+ 0x5f4, /* MMX_PSRAWrm */ >+ 0x5f5, /* MMX_PSRAWrr */ >+/* Table2413 */ >+ 0x5f1, /* MMX_PSRADrm */ >+ 0x5f2, /* MMX_PSRADrr */ >+/* Table2415 */ >+ 0x5a5, /* MMX_PAVGWirm */ >+ 0x5a6, /* MMX_PAVGWirr */ >+/* Table2417 */ >+ 0x5d1, /* MMX_PMULHUWirm */ >+ 0x5d2, /* MMX_PMULHUWirr */ >+/* Table2419 */ >+ 0x5d3, /* MMX_PMULHWirm */ >+ 0x5d4, /* MMX_PMULHWirr */ >+/* Table2421 */ >+ 0x57a, /* MMX_MOVNTQmr */ >+ 0x0, /* */ >+/* Table2423 */ >+ 0x605, /* MMX_PSUBSBirm */ >+ 0x606, /* MMX_PSUBSBirr */ >+/* Table2425 */ >+ 0x607, /* MMX_PSUBSWirm */ >+ 0x608, /* MMX_PSUBSWirr */ >+/* Table2427 */ >+ 0x5ca, /* MMX_PMINSWirm */ >+ 0x5cb, /* MMX_PMINSWirr */ >+/* Table2429 */ >+ 0x5d9, /* MMX_PORirm */ >+ 0x5da, /* MMX_PORirr */ >+/* Table2431 */ >+ 0x593, /* MMX_PADDSBirm */ >+ 0x594, /* MMX_PADDSBirr */ >+/* Table2433 */ >+ 0x595, /* MMX_PADDSWirm */ >+ 0x596, /* MMX_PADDSWirr */ >+/* Table2435 */ >+ 0x5c6, /* MMX_PMAXSWirm */ >+ 0x5c7, /* MMX_PMAXSWirr */ >+/* Table2437 */ >+ 0x61b, /* MMX_PXORirm */ >+ 0x61c, /* MMX_PXORirr */ >+/* Table2439 */ >+ 0x5ee, /* MMX_PSLLWrm */ >+ 0x5ef, /* MMX_PSLLWrr */ >+/* Table2441 */ >+ 0x5e8, /* MMX_PSLLDrm */ >+ 0x5e9, /* MMX_PSLLDrr */ >+/* Table2443 */ >+ 0x5eb, /* MMX_PSLLQrm */ >+ 0x5ec, /* MMX_PSLLQrr */ >+/* Table2445 */ >+ 0x5d7, /* MMX_PMULUDQirm */ >+ 0x5d8, /* MMX_PMULUDQirr */ >+/* Table2447 */ >+ 0x5c4, /* MMX_PMADDWDirm */ >+ 0x5c5, /* MMX_PMADDWDirr */ >+/* Table2449 */ >+ 0x5db, /* MMX_PSADBWirm */ >+ 0x5dc, /* MMX_PSADBWirr */ >+/* Table2451 */ >+ 0x0, /* */ >+ 0x570, /* MMX_MASKMOVQ */ >+/* Table2453 */ >+ 0x5ff, /* MMX_PSUBBirm */ >+ 0x600, /* MMX_PSUBBirr */ >+/* Table2455 */ >+ 0x60d, /* MMX_PSUBWirm */ >+ 0x60e, /* MMX_PSUBWirr */ >+/* Table2457 */ >+ 0x601, /* MMX_PSUBDirm */ >+ 0x602, /* MMX_PSUBDirr */ >+/* Table2459 */ >+ 0x603, /* MMX_PSUBQirm */ >+ 0x604, /* MMX_PSUBQirr */ >+/* Table2461 */ >+ 0x58d, /* MMX_PADDBirm */ >+ 0x58e, /* MMX_PADDBirr */ >+/* Table2463 */ >+ 0x59b, /* MMX_PADDWirm */ >+ 0x59c, /* MMX_PADDWirr */ >+/* Table2465 */ >+ 0x58f, /* MMX_PADDDirm */ >+ 0x590, /* MMX_PADDDirr */ >+/* Table2467 */ >+ 0xa26, /* SGDT64m */ >+ 0xa8b, /* SIDT64m */ >+ 0x4cb, /* LGDT64m */ >+ 0x4d1, /* LIDT64m */ >+ 0xa96, /* SMSW16m */ >+ 0x0, /* */ >+ 0x4d4, /* LMSW16m */ >+ 0x39c, /* INVLPG */ >+ 0x0, /* */ >+ 0xf5d, /* VMCALL */ >+ 0xf92, /* VMLAUNCH */ >+ 0x1188, /* VMRESUME */ >+ 0x11b7, /* VMXOFF */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61e, /* MONITORrrr */ >+ 0x70d, /* MWAITrr */ >+ 0x16b, /* CLAC */ >+ 0xaaa, /* STAC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x2e2, /* ENCLS */ >+ 0x1846, /* XGETBV */ >+ 0x1876, /* XSETBV */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5f, /* VMFUNC */ >+ 0x1845, /* XEND */ >+ 0x187a, /* XTEST */ >+ 0x2e3, /* ENCLU */ >+ 0x118a, /* VMRUN64 */ >+ 0xf95, /* VMMCALL */ >+ 0xf94, /* VMLOAD64 */ >+ 0x118c, /* VMSAVE64 */ >+ 0xaad, /* STGI */ >+ 0x16f, /* CLGI */ >+ 0xa90, /* SKINIT */ >+ 0x39e, /* INVLPGA64 */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0xa98, /* SMSW32r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0xb28, /* SWAPGS */ >+ 0x936, /* RDTSCP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2539 */ >+ 0x0, /* */ >+ 0x653, /* MOV64rc */ >+/* Table2541 */ >+ 0x0, /* */ >+ 0x654, /* MOV64rd */ >+/* Table2543 */ >+ 0x0, /* */ >+ 0x64a, /* MOV64cr */ >+/* Table2545 */ >+ 0x0, /* */ >+ 0x64b, /* MOV64dr */ >+/* Table2547 */ >+ 0x1186, /* VMREAD64rm */ >+ 0x1187, /* VMREAD64rr */ >+/* Table2549 */ >+ 0x11b5, /* VMWRITE64rm */ >+ 0x11b6, /* VMWRITE64rr */ >+/* Table2551 */ >+ 0x8e7, /* PUSHFS64 */ >+/* Table2552 */ >+ 0x870, /* POPFS64 */ >+/* Table2553 */ >+ 0x251, /* CPUID64 */ >+/* Table2554 */ >+ 0x8ea, /* PUSHGS64 */ >+/* Table2555 */ >+ 0x873, /* POPGS64 */ >+/* Table2556 */ >+ 0x0, /* */ >+ 0x571, /* MMX_MASKMOVQ64 */ >+/* Table2558 */ >+ 0xa91, /* SLDT16m */ >+ 0xab7, /* STRm */ >+ 0x4d2, /* LLDT16m */ >+ 0x52c, /* LTRm */ >+ 0xcfe, /* VERRm */ >+ 0xd00, /* VERWm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa92, /* SLDT16r */ >+ 0xab4, /* STR16r */ >+ 0x4d3, /* LLDT16r */ >+ 0x52d, /* LTRr */ >+ 0xcff, /* VERRr */ >+ 0xd01, /* VERWr */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2574 */ >+ 0xa24, /* SGDT16m */ >+ 0xa89, /* SIDT16m */ >+ 0x4c9, /* LGDT16m */ >+ 0x4cf, /* LIDT16m */ >+ 0xa96, /* SMSW16m */ >+ 0x0, /* */ >+ 0x4d4, /* LMSW16m */ >+ 0x39c, /* INVLPG */ >+ 0x0, /* */ >+ 0xf5d, /* VMCALL */ >+ 0xf92, /* VMLAUNCH */ >+ 0x1188, /* VMRESUME */ >+ 0x11b7, /* VMXOFF */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61e, /* MONITORrrr */ >+ 0x70d, /* MWAITrr */ >+ 0x16b, /* CLAC */ >+ 0xaaa, /* STAC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x2e2, /* ENCLS */ >+ 0x1846, /* XGETBV */ >+ 0x1876, /* XSETBV */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5f, /* VMFUNC */ >+ 0x1845, /* XEND */ >+ 0x187a, /* XTEST */ >+ 0x2e3, /* ENCLU */ >+ 0x1189, /* VMRUN32 */ >+ 0xf95, /* VMMCALL */ >+ 0xf93, /* VMLOAD32 */ >+ 0x118b, /* VMSAVE32 */ >+ 0xaad, /* STGI */ >+ 0x16f, /* CLGI */ >+ 0xa90, /* SKINIT */ >+ 0x39d, /* INVLPGA32 */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0xb28, /* SWAPGS */ >+ 0x936, /* RDTSCP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table2646 */ >+ 0x49b, /* LAR16rm */ >+ 0x49c, /* LAR16rr */ >+/* Table2648 */ >+ 0x523, /* LSL16rm */ >+ 0x524, /* LSL16rr */ >+/* Table2650 */ >+ 0x6c7, /* MOVUPDrm */ >+ 0x6c8, /* MOVUPDrr */ >+/* Table2652 */ >+ 0x6c6, /* MOVUPDmr */ >+ 0x6c9, /* MOVUPDrr_REV */ >+/* Table2654 */ >+ 0x691, /* MOVLPDrm */ >+ 0x68a, /* MOVHLPSrr */ >+/* Table2656 */ >+ 0x690, /* MOVLPDmr */ >+ 0x0, /* */ >+/* Table2658 */ >+ 0xb85, /* UNPCKLPDrm */ >+ 0xb86, /* UNPCKLPDrr */ >+/* Table2660 */ >+ 0xb81, /* UNPCKHPDrm */ >+ 0xb82, /* UNPCKHPDrr */ >+/* Table2662 */ >+ 0x68c, /* MOVHPDrm */ >+ 0x68f, /* MOVLHPSrr */ >+/* Table2664 */ >+ 0x68b, /* MOVHPDmr */ >+ 0x0, /* */ >+/* Table2666 */ >+ 0x879, /* PREFETCHNTA */ >+ 0x87a, /* PREFETCHT0 */ >+ 0x87b, /* PREFETCHT1 */ >+ 0x87c, /* PREFETCHT2 */ >+ 0x717, /* NOOP18_16m4 */ >+ 0x718, /* NOOP18_16m5 */ >+ 0x719, /* NOOP18_16m6 */ >+ 0x71a, /* NOOP18_16m7 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x71b, /* NOOP18_16r4 */ >+ 0x71c, /* NOOP18_16r5 */ >+ 0x71d, /* NOOP18_16r6 */ >+ 0x71e, /* NOOP18_16r7 */ >+/* Table2682 */ >+ 0x730, /* NOOPW_19 */ >+ 0x727, /* NOOP19rr */ >+/* Table2684 */ >+ 0x731, /* NOOPW_1a */ >+ 0x0, /* */ >+/* Table2686 */ >+ 0x732, /* NOOPW_1b */ >+ 0x0, /* */ >+/* Table2688 */ >+ 0x733, /* NOOPW_1c */ >+ 0x0, /* */ >+/* Table2690 */ >+ 0x734, /* NOOPW_1d */ >+ 0x0, /* */ >+/* Table2692 */ >+ 0x735, /* NOOPW_1e */ >+ 0x0, /* */ >+/* Table2694 */ >+ 0x72f, /* NOOPW */ >+ 0x0, /* */ >+/* Table2696 */ >+ 0x66f, /* MOVAPDrm */ >+ 0x670, /* MOVAPDrr */ >+/* Table2698 */ >+ 0x66e, /* MOVAPDmr */ >+ 0x671, /* MOVAPDrr_REV */ >+/* Table2700 */ >+ 0x565, /* MMX_CVTPI2PDirm */ >+ 0x566, /* MMX_CVTPI2PDirr */ >+/* Table2702 */ >+ 0x69a, /* MOVNTPDmr */ >+ 0x0, /* */ >+/* Table2704 */ >+ 0x56b, /* MMX_CVTTPD2PIirm */ >+ 0x56c, /* MMX_CVTTPD2PIirr */ >+/* Table2706 */ >+ 0x563, /* MMX_CVTPD2PIirm */ >+ 0x564, /* MMX_CVTPD2PIirr */ >+/* Table2708 */ >+ 0xb71, /* UCOMISDrm */ >+ 0xb72, /* UCOMISDrr */ >+/* Table2710 */ >+ 0x244, /* COMISDrm */ >+ 0x245, /* COMISDrr */ >+/* Table2712 */ >+ 0x1dd, /* CMOVO16rm */ >+ 0x1de, /* CMOVO16rr */ >+/* Table2714 */ >+ 0x1c7, /* CMOVNO16rm */ >+ 0x1c8, /* CMOVNO16rr */ >+/* Table2716 */ >+ 0x17f, /* CMOVB16rm */ >+ 0x180, /* CMOVB16rr */ >+/* Table2718 */ >+ 0x179, /* CMOVAE16rm */ >+ 0x17a, /* CMOVAE16rr */ >+/* Table2720 */ >+ 0x193, /* CMOVE16rm */ >+ 0x194, /* CMOVE16rr */ >+/* Table2722 */ >+ 0x1bd, /* CMOVNE16rm */ >+ 0x1be, /* CMOVNE16rr */ >+/* Table2724 */ >+ 0x185, /* CMOVBE16rm */ >+ 0x186, /* CMOVBE16rr */ >+/* Table2726 */ >+ 0x173, /* CMOVA16rm */ >+ 0x174, /* CMOVA16rr */ >+/* Table2728 */ >+ 0x1ed, /* CMOVS16rm */ >+ 0x1ee, /* CMOVS16rr */ >+/* Table2730 */ >+ 0x1d7, /* CMOVNS16rm */ >+ 0x1d8, /* CMOVNS16rr */ >+/* Table2732 */ >+ 0x1e3, /* CMOVP16rm */ >+ 0x1e4, /* CMOVP16rr */ >+/* Table2734 */ >+ 0x1cd, /* CMOVNP16rm */ >+ 0x1ce, /* CMOVNP16rr */ >+/* Table2736 */ >+ 0x1a9, /* CMOVL16rm */ >+ 0x1aa, /* CMOVL16rr */ >+/* Table2738 */ >+ 0x1a3, /* CMOVGE16rm */ >+ 0x1a4, /* CMOVGE16rr */ >+/* Table2740 */ >+ 0x1af, /* CMOVLE16rm */ >+ 0x1b0, /* CMOVLE16rr */ >+/* Table2742 */ >+ 0x19d, /* CMOVG16rm */ >+ 0x19e, /* CMOVG16rr */ >+/* Table2744 */ >+ 0x0, /* */ >+ 0x694, /* MOVMSKPDrr */ >+/* Table2746 */ >+ 0xa9a, /* SQRTPDm */ >+ 0xa9b, /* SQRTPDr */ >+/* Table2748 */ >+ 0xd6, /* ANDPDrm */ >+ 0xd7, /* ANDPDrr */ >+/* Table2750 */ >+ 0xd2, /* ANDNPDrm */ >+ 0xd3, /* ANDNPDrr */ >+/* Table2752 */ >+ 0x762, /* ORPDrm */ >+ 0x763, /* ORPDrr */ >+/* Table2754 */ >+ 0x186b, /* XORPDrm */ >+ 0x186c, /* XORPDrr */ >+/* Table2756 */ >+ 0x72, /* ADDPDrm */ >+ 0x73, /* ADDPDrr */ >+/* Table2758 */ >+ 0x6e8, /* MULPDrm */ >+ 0x6e9, /* MULPDrr */ >+/* Table2760 */ >+ 0x263, /* CVTPD2PSrm */ >+ 0x264, /* CVTPD2PSrr */ >+/* Table2762 */ >+ 0x265, /* CVTPS2DQrm */ >+ 0x266, /* CVTPS2DQrr */ >+/* Table2764 */ >+ 0xaf5, /* SUBPDrm */ >+ 0xaf6, /* SUBPDrr */ >+/* Table2766 */ >+ 0x557, /* MINPDrm */ >+ 0x558, /* MINPDrr */ >+/* Table2768 */ >+ 0x2a4, /* DIVPDrm */ >+ 0x2a5, /* DIVPDrr */ >+/* Table2770 */ >+ 0x542, /* MAXPDrm */ >+ 0x543, /* MAXPDrr */ >+/* Table2772 */ >+ 0x8c4, /* PUNPCKLBWrm */ >+ 0x8c5, /* PUNPCKLBWrr */ >+/* Table2774 */ >+ 0x8ca, /* PUNPCKLWDrm */ >+ 0x8cb, /* PUNPCKLWDrr */ >+/* Table2776 */ >+ 0x8c6, /* PUNPCKLDQrm */ >+ 0x8c7, /* PUNPCKLDQrr */ >+/* Table2778 */ >+ 0x777, /* PACKSSWBrm */ >+ 0x778, /* PACKSSWBrr */ >+/* Table2780 */ >+ 0x7b0, /* PCMPGTBrm */ >+ 0x7b1, /* PCMPGTBrr */ >+/* Table2782 */ >+ 0x7b6, /* PCMPGTWrm */ >+ 0x7b7, /* PCMPGTWrr */ >+/* Table2784 */ >+ 0x7b2, /* PCMPGTDrm */ >+ 0x7b3, /* PCMPGTDrr */ >+/* Table2786 */ >+ 0x77b, /* PACKUSWBrm */ >+ 0x77c, /* PACKUSWBrr */ >+/* Table2788 */ >+ 0x8bc, /* PUNPCKHBWrm */ >+ 0x8bd, /* PUNPCKHBWrr */ >+/* Table2790 */ >+ 0x8c2, /* PUNPCKHWDrm */ >+ 0x8c3, /* PUNPCKHWDrr */ >+/* Table2792 */ >+ 0x8be, /* PUNPCKHDQrm */ >+ 0x8bf, /* PUNPCKHDQrr */ >+/* Table2794 */ >+ 0x775, /* PACKSSDWrm */ >+ 0x776, /* PACKSSDWrr */ >+/* Table2796 */ >+ 0x8c8, /* PUNPCKLQDQrm */ >+ 0x8c9, /* PUNPCKLQDQrr */ >+/* Table2798 */ >+ 0x8c0, /* PUNPCKHQDQrm */ >+ 0x8c1, /* PUNPCKHQDQrr */ >+/* Table2800 */ >+ 0x67e, /* MOVDI2PDIrm */ >+ 0x67f, /* MOVDI2PDIrr */ >+/* Table2802 */ >+ 0x683, /* MOVDQArm */ >+ 0x684, /* MOVDQArr */ >+/* Table2804 */ >+ 0x882, /* PSHUFDmi */ >+ 0x883, /* PSHUFDri */ >+/* Table2806 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x8a5, /* PSRLWri */ >+ 0x0, /* */ >+ 0x89b, /* PSRAWri */ >+ 0x0, /* */ >+ 0x895, /* PSLLWri */ >+ 0x0, /* */ >+/* Table2822 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x89f, /* PSRLDri */ >+ 0x0, /* */ >+ 0x898, /* PSRADri */ >+ 0x0, /* */ >+ 0x88f, /* PSLLDri */ >+ 0x0, /* */ >+/* Table2838 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x8a2, /* PSRLQri */ >+ 0x89e, /* PSRLDQri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x892, /* PSLLQri */ >+ 0x88e, /* PSLLDQri */ >+/* Table2854 */ >+ 0x7a0, /* PCMPEQBrm */ >+ 0x7a1, /* PCMPEQBrr */ >+/* Table2856 */ >+ 0x7a6, /* PCMPEQWrm */ >+ 0x7a7, /* PCMPEQWrr */ >+/* Table2858 */ >+ 0x7a2, /* PCMPEQDrm */ >+ 0x7a3, /* PCMPEQDrr */ >+/* Table2860 */ >+ 0x1184, /* VMREAD32rm */ >+ 0x2e8, /* EXTRQI */ >+/* Table2862 */ >+ 0x11b3, /* VMWRITE32rm */ >+ 0x2e7, /* EXTRQ */ >+/* Table2864 */ >+ 0x343, /* HADDPDrm */ >+ 0x344, /* HADDPDrr */ >+/* Table2866 */ >+ 0x348, /* HSUBPDrm */ >+ 0x349, /* HSUBPDrr */ >+/* Table2868 */ >+ 0x69f, /* MOVPDI2DImr */ >+ 0x6a0, /* MOVPDI2DIrr */ >+/* Table2870 */ >+ 0x682, /* MOVDQAmr */ >+ 0x685, /* MOVDQArr_REV */ >+/* Table2872 */ >+ 0x45d, /* JO_2 */ >+/* Table2873 */ >+ 0x454, /* JNO_2 */ >+/* Table2874 */ >+ 0x433, /* JB_2 */ >+/* Table2875 */ >+ 0x42a, /* JAE_2 */ >+/* Table2876 */ >+ 0x439, /* JE_2 */ >+/* Table2877 */ >+ 0x451, /* JNE_2 */ >+/* Table2878 */ >+ 0x430, /* JBE_2 */ >+/* Table2879 */ >+ 0x42d, /* JA_2 */ >+/* Table2880 */ >+ 0x464, /* JS_2 */ >+/* Table2881 */ >+ 0x45a, /* JNS_2 */ >+/* Table2882 */ >+ 0x460, /* JP_2 */ >+/* Table2883 */ >+ 0x457, /* JNP_2 */ >+/* Table2884 */ >+ 0x445, /* JL_2 */ >+/* Table2885 */ >+ 0x43c, /* JGE_2 */ >+/* Table2886 */ >+ 0x442, /* JLE_2 */ >+/* Table2887 */ >+ 0x43f, /* JG_2 */ >+/* Table2888 */ >+ 0x8e5, /* PUSHFS16 */ >+/* Table2889 */ >+ 0x86e, /* POPFS16 */ >+/* Table2890 */ >+ 0x128, /* BT16mr */ >+ 0x12a, /* BT16rr */ >+/* Table2892 */ >+ 0xa4e, /* SHLD16mri8 */ >+ 0xa50, /* SHLD16rri8 */ >+/* Table2894 */ >+ 0xa4d, /* SHLD16mrCL */ >+ 0xa4f, /* SHLD16rrCL */ >+/* Table2896 */ >+ 0x8e8, /* PUSHGS16 */ >+/* Table2897 */ >+ 0x871, /* POPGS16 */ >+/* Table2898 */ >+ 0x14c, /* BTS16mr */ >+ 0x14e, /* BTS16rr */ >+/* Table2900 */ >+ 0xa76, /* SHRD16mri8 */ >+ 0xa78, /* SHRD16rri8 */ >+/* Table2902 */ >+ 0xa75, /* SHRD16mrCL */ >+ 0xa77, /* SHRD16rrCL */ >+/* Table2904 */ >+ 0x362, /* IMUL16rm */ >+ 0x365, /* IMUL16rr */ >+/* Table2906 */ >+ 0x23b, /* CMPXCHG16rm */ >+ 0x23c, /* CMPXCHG16rr */ >+/* Table2908 */ >+ 0x529, /* LSS16rm */ >+ 0x0, /* */ >+/* Table2910 */ >+ 0x140, /* BTR16mr */ >+ 0x142, /* BTR16rr */ >+/* Table2912 */ >+ 0x4c6, /* LFS16rm */ >+ 0x0, /* */ >+/* Table2914 */ >+ 0x4cc, /* LGS16rm */ >+ 0x0, /* */ >+/* Table2916 */ >+ 0x6d2, /* MOVZX16rm8 */ >+ 0x6d3, /* MOVZX16rr8 */ >+/* Table2918 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x127, /* BT16mi8 */ >+ 0x14b, /* BTS16mi8 */ >+ 0x13f, /* BTR16mi8 */ >+ 0x133, /* BTC16mi8 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x129, /* BT16ri8 */ >+ 0x14d, /* BTS16ri8 */ >+ 0x141, /* BTR16ri8 */ >+ 0x135, /* BTC16ri8 */ >+/* Table2934 */ >+ 0x134, /* BTC16mr */ >+ 0x136, /* BTC16rr */ >+/* Table2936 */ >+ 0x119, /* BSF16rm */ >+ 0x11a, /* BSF16rr */ >+/* Table2938 */ >+ 0x11f, /* BSR16rm */ >+ 0x120, /* BSR16rr */ >+/* Table2940 */ >+ 0x6b9, /* MOVSX16rm8 */ >+ 0x6ba, /* MOVSX16rr8 */ >+/* Table2942 */ >+ 0x1829, /* XADD16rm */ >+ 0x182a, /* XADD16rr */ >+/* Table2944 */ >+ 0x226, /* CMPPDrmi */ >+ 0x228, /* CMPPDrri */ >+/* Table2946 */ >+ 0x80f, /* PINSRWrmi */ >+ 0x810, /* PINSRWrri */ >+/* Table2948 */ >+ 0x0, /* */ >+ 0x7cf, /* PEXTRWri */ >+/* Table2950 */ >+ 0xa85, /* SHUFPDrmi */ >+ 0xa86, /* SHUFPDrri */ >+/* Table2952 */ >+ 0x0, /* */ >+ 0x241, /* CMPXCHG8B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5e, /* VMCLEARm */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x92f, /* RDRAND16r */ >+ 0x932, /* RDSEED16r */ >+/* Table2968 */ >+ 0x7e, /* ADDSUBPDrm */ >+ 0x7f, /* ADDSUBPDrr */ >+/* Table2970 */ >+ 0x8a6, /* PSRLWrm */ >+ 0x8a7, /* PSRLWrr */ >+/* Table2972 */ >+ 0x8a0, /* PSRLDrm */ >+ 0x8a1, /* PSRLDrr */ >+/* Table2974 */ >+ 0x8a3, /* PSRLQrm */ >+ 0x8a4, /* PSRLQrr */ >+/* Table2976 */ >+ 0x781, /* PADDQrm */ >+ 0x782, /* PADDQrr */ >+/* Table2978 */ >+ 0x852, /* PMULLWrm */ >+ 0x853, /* PMULLWrr */ >+/* Table2980 */ >+ 0x6a1, /* MOVPQI2QImr */ >+ 0x6a2, /* MOVPQI2QIrr */ >+/* Table2982 */ >+ 0x0, /* */ >+ 0x82d, /* PMOVMSKBrr */ >+/* Table2984 */ >+ 0x8b2, /* PSUBUSBrm */ >+ 0x8b3, /* PSUBUSBrr */ >+/* Table2986 */ >+ 0x8b4, /* PSUBUSWrm */ >+ 0x8b5, /* PSUBUSWrr */ >+/* Table2988 */ >+ 0x827, /* PMINUBrm */ >+ 0x828, /* PMINUBrr */ >+/* Table2990 */ >+ 0x791, /* PANDrm */ >+ 0x792, /* PANDrr */ >+/* Table2992 */ >+ 0x787, /* PADDUSBrm */ >+ 0x788, /* PADDUSBrr */ >+/* Table2994 */ >+ 0x789, /* PADDUSWrm */ >+ 0x78a, /* PADDUSWrr */ >+/* Table2996 */ >+ 0x81b, /* PMAXUBrm */ >+ 0x81c, /* PMAXUBrr */ >+/* Table2998 */ >+ 0x78f, /* PANDNrm */ >+ 0x790, /* PANDNrr */ >+/* Table3000 */ >+ 0x794, /* PAVGBrm */ >+ 0x795, /* PAVGBrr */ >+/* Table3002 */ >+ 0x89c, /* PSRAWrm */ >+ 0x89d, /* PSRAWrr */ >+/* Table3004 */ >+ 0x899, /* PSRADrm */ >+ 0x89a, /* PSRADrr */ >+/* Table3006 */ >+ 0x798, /* PAVGWrm */ >+ 0x799, /* PAVGWrr */ >+/* Table3008 */ >+ 0x84c, /* PMULHUWrm */ >+ 0x84d, /* PMULHUWrr */ >+/* Table3010 */ >+ 0x84e, /* PMULHWrm */ >+ 0x84f, /* PMULHWrr */ >+/* Table3012 */ >+ 0x27d, /* CVTTPD2DQrm */ >+ 0x27e, /* CVTTPD2DQrr */ >+/* Table3014 */ >+ 0x697, /* MOVNTDQmr */ >+ 0x0, /* */ >+/* Table3016 */ >+ 0x8ae, /* PSUBSBrm */ >+ 0x8af, /* PSUBSBrr */ >+/* Table3018 */ >+ 0x8b0, /* PSUBSWrm */ >+ 0x8b1, /* PSUBSWrr */ >+/* Table3020 */ >+ 0x825, /* PMINSWrm */ >+ 0x826, /* PMINSWrr */ >+/* Table3022 */ >+ 0x876, /* PORrm */ >+ 0x877, /* PORrr */ >+/* Table3024 */ >+ 0x783, /* PADDSBrm */ >+ 0x784, /* PADDSBrr */ >+/* Table3026 */ >+ 0x785, /* PADDSWrm */ >+ 0x786, /* PADDSWrr */ >+/* Table3028 */ >+ 0x819, /* PMAXSWrm */ >+ 0x81a, /* PMAXSWrr */ >+/* Table3030 */ >+ 0x8ef, /* PXORrm */ >+ 0x8f0, /* PXORrr */ >+/* Table3032 */ >+ 0x896, /* PSLLWrm */ >+ 0x897, /* PSLLWrr */ >+/* Table3034 */ >+ 0x890, /* PSLLDrm */ >+ 0x891, /* PSLLDrr */ >+/* Table3036 */ >+ 0x893, /* PSLLQrm */ >+ 0x894, /* PSLLQrr */ >+/* Table3038 */ >+ 0x854, /* PMULUDQrm */ >+ 0x855, /* PMULUDQrr */ >+/* Table3040 */ >+ 0x813, /* PMADDWDrm */ >+ 0x814, /* PMADDWDrr */ >+/* Table3042 */ >+ 0x87e, /* PSADBWrm */ >+ 0x87f, /* PSADBWrr */ >+/* Table3044 */ >+ 0x0, /* */ >+ 0x538, /* MASKMOVDQU */ >+/* Table3046 */ >+ 0x8a8, /* PSUBBrm */ >+ 0x8a9, /* PSUBBrr */ >+/* Table3048 */ >+ 0x8b6, /* PSUBWrm */ >+ 0x8b7, /* PSUBWrr */ >+/* Table3050 */ >+ 0x8aa, /* PSUBDrm */ >+ 0x8ab, /* PSUBDrr */ >+/* Table3052 */ >+ 0x8ac, /* PSUBQrm */ >+ 0x8ad, /* PSUBQrr */ >+/* Table3054 */ >+ 0x77d, /* PADDBrm */ >+ 0x77e, /* PADDBrr */ >+/* Table3056 */ >+ 0x78b, /* PADDWrm */ >+ 0x78c, /* PADDWrr */ >+/* Table3058 */ >+ 0x77f, /* PADDDrm */ >+ 0x780, /* PADDDrr */ >+/* Table3060 */ >+ 0x6a7, /* MOVSDrm */ >+ 0x6a8, /* MOVSDrr */ >+/* Table3062 */ >+ 0x6a6, /* MOVSDmr */ >+ 0x6a9, /* MOVSDrr_REV */ >+/* Table3064 */ >+ 0x67c, /* MOVDDUPrm */ >+ 0x67d, /* MOVDDUPrr */ >+/* Table3066 */ >+ 0x271, /* CVTSI2SDrm */ >+ 0x272, /* CVTSI2SDrr */ >+/* Table3068 */ >+ 0x69c, /* MOVNTSD */ >+ 0x0, /* */ >+/* Table3070 */ >+ 0x283, /* CVTTSD2SIrm */ >+ 0x284, /* CVTTSD2SIrr */ >+/* Table3072 */ >+ 0x26b, /* CVTSD2SIrm */ >+ 0x26c, /* CVTSD2SIrr */ >+/* Table3074 */ >+ 0xa9e, /* SQRTSDm */ >+ 0xaa0, /* SQRTSDr */ >+/* Table3076 */ >+ 0x76, /* ADDSDrm */ >+ 0x78, /* ADDSDrr */ >+/* Table3078 */ >+ 0x6ec, /* MULSDrm */ >+ 0x6ee, /* MULSDrr */ >+/* Table3080 */ >+ 0x26d, /* CVTSD2SSrm */ >+ 0x26e, /* CVTSD2SSrr */ >+/* Table3082 */ >+ 0xb0b, /* SUBSDrm */ >+ 0xb0d, /* SUBSDrr */ >+/* Table3084 */ >+ 0x55b, /* MINSDrm */ >+ 0x55d, /* MINSDrr */ >+/* Table3086 */ >+ 0x2ba, /* DIVSDrm */ >+ 0x2bc, /* DIVSDrr */ >+/* Table3088 */ >+ 0x546, /* MAXSDrm */ >+ 0x548, /* MAXSDrr */ >+/* Table3090 */ >+ 0x886, /* PSHUFLWmi */ >+ 0x887, /* PSHUFLWri */ >+/* Table3092 */ >+ 0x1184, /* VMREAD32rm */ >+ 0x392, /* INSERTQI */ >+/* Table3094 */ >+ 0x11b3, /* VMWRITE32rm */ >+ 0x391, /* INSERTQ */ >+/* Table3096 */ >+ 0x345, /* HADDPSrm */ >+ 0x346, /* HADDPSrr */ >+/* Table3098 */ >+ 0x34a, /* HSUBPSrm */ >+ 0x34b, /* HSUBPSrr */ >+/* Table3100 */ >+ 0x22f, /* CMPSDrm */ >+ 0x231, /* CMPSDrr */ >+/* Table3102 */ >+ 0x80, /* ADDSUBPSrm */ >+ 0x81, /* ADDSUBPSrr */ >+/* Table3104 */ >+ 0x0, /* */ >+ 0x578, /* MMX_MOVDQ2Qrr */ >+/* Table3106 */ >+ 0x261, /* CVTPD2DQrm */ >+ 0x262, /* CVTPD2DQrr */ >+/* Table3108 */ >+ 0x4a7, /* LDDQUrm */ >+ 0x0, /* */ >+/* Table3110 */ >+ 0x6b5, /* MOVSSrm */ >+ 0x6b6, /* MOVSSrr */ >+/* Table3112 */ >+ 0x6b4, /* MOVSSmr */ >+ 0x6b7, /* MOVSSrr_REV */ >+/* Table3114 */ >+ 0x6af, /* MOVSLDUPrm */ >+ 0x6b0, /* MOVSLDUPrr */ >+/* Table3116 */ >+ 0x6ac, /* MOVSHDUPrm */ >+ 0x6ad, /* MOVSHDUPrr */ >+/* Table3118 */ >+ 0x275, /* CVTSI2SSrm */ >+ 0x276, /* CVTSI2SSrr */ >+/* Table3120 */ >+ 0x69d, /* MOVNTSS */ >+ 0x0, /* */ >+/* Table3122 */ >+ 0x287, /* CVTTSS2SIrm */ >+ 0x288, /* CVTTSS2SIrr */ >+/* Table3124 */ >+ 0x27b, /* CVTSS2SIrm */ >+ 0x27c, /* CVTSS2SIrr */ >+/* Table3126 */ >+ 0xaa2, /* SQRTSSm */ >+ 0xaa4, /* SQRTSSr */ >+/* Table3128 */ >+ 0x995, /* RSQRTSSm */ >+ 0x997, /* RSQRTSSr */ >+/* Table3130 */ >+ 0x90d, /* RCPSSm */ >+ 0x90f, /* RCPSSr */ >+/* Table3132 */ >+ 0x7a, /* ADDSSrm */ >+ 0x7c, /* ADDSSrr */ >+/* Table3134 */ >+ 0x6f0, /* MULSSrm */ >+ 0x6f2, /* MULSSrr */ >+/* Table3136 */ >+ 0x277, /* CVTSS2SDrm */ >+ 0x278, /* CVTSS2SDrr */ >+/* Table3138 */ >+ 0x27f, /* CVTTPS2DQrm */ >+ 0x280, /* CVTTPS2DQrr */ >+/* Table3140 */ >+ 0xb0f, /* SUBSSrm */ >+ 0xb11, /* SUBSSrr */ >+/* Table3142 */ >+ 0x55f, /* MINSSrm */ >+ 0x561, /* MINSSrr */ >+/* Table3144 */ >+ 0x2be, /* DIVSSrm */ >+ 0x2c0, /* DIVSSrr */ >+/* Table3146 */ >+ 0x54a, /* MAXSSrm */ >+ 0x54c, /* MAXSSrr */ >+/* Table3148 */ >+ 0x687, /* MOVDQUrm */ >+ 0x688, /* MOVDQUrr */ >+/* Table3150 */ >+ 0x884, /* PSHUFHWmi */ >+ 0x885, /* PSHUFHWri */ >+/* Table3152 */ >+ 0x6a4, /* MOVQI2PQIrm */ >+ 0x6cf, /* MOVZPQILo2PQIrr */ >+/* Table3154 */ >+ 0x686, /* MOVDQUmr */ >+ 0x689, /* MOVDQUrr_REV */ >+/* Table3156 */ >+ 0x863, /* POPCNT32rm */ >+ 0x864, /* POPCNT32rr */ >+/* Table3158 */ >+ 0xb69, /* TZCNT32rm */ >+ 0xb6a, /* TZCNT32rr */ >+/* Table3160 */ >+ 0x534, /* LZCNT32rm */ >+ 0x535, /* LZCNT32rr */ >+/* Table3162 */ >+ 0x235, /* CMPSSrm */ >+ 0x237, /* CMPSSrr */ >+/* Table3164 */ >+ 0x0, /* */ >+ 0x241, /* CMPXCHG8B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x11b8, /* VMXON */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x930, /* RDRAND32r */ >+ 0x933, /* RDSEED32r */ >+/* Table3180 */ >+ 0x0, /* */ >+ 0x57b, /* MMX_MOVQ2DQrr */ >+/* Table3182 */ >+ 0x25d, /* CVTDQ2PDrm */ >+ 0x25e, /* CVTDQ2PDrr */ >+/* Table3184 */ >+ 0x861, /* POPCNT16rm */ >+ 0x862, /* POPCNT16rr */ >+/* Table3186 */ >+ 0xb67, /* TZCNT16rm */ >+ 0xb68, /* TZCNT16rr */ >+/* Table3188 */ >+ 0x532, /* LZCNT16rm */ >+ 0x533, /* LZCNT16rr */ >+/* Table3190 */ >+ 0xa94, /* SLDT64m */ >+ 0xab7, /* STRm */ >+ 0x4d2, /* LLDT16m */ >+ 0x52c, /* LTRm */ >+ 0xcfe, /* VERRm */ >+ 0xd00, /* VERWm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa95, /* SLDT64r */ >+ 0xab6, /* STR64r */ >+ 0x4d3, /* LLDT16r */ >+ 0x52d, /* LTRr */ >+ 0xcff, /* VERRr */ >+ 0xd01, /* VERWr */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3206 */ >+ 0xa26, /* SGDT64m */ >+ 0xa8b, /* SIDT64m */ >+ 0x4cb, /* LGDT64m */ >+ 0x4d1, /* LIDT64m */ >+ 0xa96, /* SMSW16m */ >+ 0x0, /* */ >+ 0x4d4, /* LMSW16m */ >+ 0x39c, /* INVLPG */ >+ 0x0, /* */ >+ 0xf5d, /* VMCALL */ >+ 0xf92, /* VMLAUNCH */ >+ 0x1188, /* VMRESUME */ >+ 0x11b7, /* VMXOFF */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61e, /* MONITORrrr */ >+ 0x70d, /* MWAITrr */ >+ 0x16b, /* CLAC */ >+ 0xaaa, /* STAC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x2e2, /* ENCLS */ >+ 0x1846, /* XGETBV */ >+ 0x1876, /* XSETBV */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5f, /* VMFUNC */ >+ 0x1845, /* XEND */ >+ 0x187a, /* XTEST */ >+ 0x2e3, /* ENCLU */ >+ 0x118a, /* VMRUN64 */ >+ 0xf95, /* VMMCALL */ >+ 0xf94, /* VMLOAD64 */ >+ 0x118c, /* VMSAVE64 */ >+ 0xaad, /* STGI */ >+ 0x16f, /* CLGI */ >+ 0xa90, /* SKINIT */ >+ 0x39e, /* INVLPGA64 */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0xa99, /* SMSW64r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0xb28, /* SWAPGS */ >+ 0x936, /* RDTSCP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3278 */ >+ 0x49f, /* LAR64rm */ >+ 0x4a0, /* LAR64rr */ >+/* Table3280 */ >+ 0x527, /* LSL64rm */ >+ 0x528, /* LSL64rr */ >+/* Table3282 */ >+ 0xb2e, /* SYSRET64 */ >+/* Table3283 */ >+ 0xb2c, /* SYSEXIT64 */ >+/* Table3284 */ >+ 0x1e1, /* CMOVO64rm */ >+ 0x1e2, /* CMOVO64rr */ >+/* Table3286 */ >+ 0x1cb, /* CMOVNO64rm */ >+ 0x1cc, /* CMOVNO64rr */ >+/* Table3288 */ >+ 0x183, /* CMOVB64rm */ >+ 0x184, /* CMOVB64rr */ >+/* Table3290 */ >+ 0x17d, /* CMOVAE64rm */ >+ 0x17e, /* CMOVAE64rr */ >+/* Table3292 */ >+ 0x197, /* CMOVE64rm */ >+ 0x198, /* CMOVE64rr */ >+/* Table3294 */ >+ 0x1c1, /* CMOVNE64rm */ >+ 0x1c2, /* CMOVNE64rr */ >+/* Table3296 */ >+ 0x189, /* CMOVBE64rm */ >+ 0x18a, /* CMOVBE64rr */ >+/* Table3298 */ >+ 0x177, /* CMOVA64rm */ >+ 0x178, /* CMOVA64rr */ >+/* Table3300 */ >+ 0x1f1, /* CMOVS64rm */ >+ 0x1f2, /* CMOVS64rr */ >+/* Table3302 */ >+ 0x1db, /* CMOVNS64rm */ >+ 0x1dc, /* CMOVNS64rr */ >+/* Table3304 */ >+ 0x1e7, /* CMOVP64rm */ >+ 0x1e8, /* CMOVP64rr */ >+/* Table3306 */ >+ 0x1d1, /* CMOVNP64rm */ >+ 0x1d2, /* CMOVNP64rr */ >+/* Table3308 */ >+ 0x1ad, /* CMOVL64rm */ >+ 0x1ae, /* CMOVL64rr */ >+/* Table3310 */ >+ 0x1a7, /* CMOVGE64rm */ >+ 0x1a8, /* CMOVGE64rr */ >+/* Table3312 */ >+ 0x1b3, /* CMOVLE64rm */ >+ 0x1b4, /* CMOVLE64rr */ >+/* Table3314 */ >+ 0x1a1, /* CMOVG64rm */ >+ 0x1a2, /* CMOVG64rr */ >+/* Table3316 */ >+ 0x575, /* MMX_MOVD64rm */ >+ 0x577, /* MMX_MOVD64to64rr */ >+/* Table3318 */ >+ 0x574, /* MMX_MOVD64mr */ >+ 0x572, /* MMX_MOVD64from64rr */ >+/* Table3320 */ >+ 0x130, /* BT64mr */ >+ 0x132, /* BT64rr */ >+/* Table3322 */ >+ 0xa56, /* SHLD64mri8 */ >+ 0xa58, /* SHLD64rri8 */ >+/* Table3324 */ >+ 0xa55, /* SHLD64mrCL */ >+ 0xa57, /* SHLD64rrCL */ >+/* Table3326 */ >+ 0x154, /* BTS64mr */ >+ 0x156, /* BTS64rr */ >+/* Table3328 */ >+ 0xa7e, /* SHRD64mri8 */ >+ 0xa80, /* SHRD64rri8 */ >+/* Table3330 */ >+ 0xa7d, /* SHRD64mrCL */ >+ 0xa7f, /* SHRD64rrCL */ >+/* Table3332 */ >+ 0x328, /* FXSAVE64 */ >+ 0x326, /* FXRSTOR64 */ >+ 0x4a8, /* LDMXCSR */ >+ 0xaaf, /* STMXCSR */ >+ 0x1873, /* XSAVE64 */ >+ 0x1871, /* XRSTOR64 */ >+ 0x1875, /* XSAVEOPT64 */ >+ 0x16e, /* CLFLUSH */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4c5, /* LFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x54e, /* MFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa23, /* SFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3404 */ >+ 0x372, /* IMUL64rm */ >+ 0x375, /* IMUL64rr */ >+/* Table3406 */ >+ 0x23f, /* CMPXCHG64rm */ >+ 0x240, /* CMPXCHG64rr */ >+/* Table3408 */ >+ 0x52b, /* LSS64rm */ >+ 0x0, /* */ >+/* Table3410 */ >+ 0x148, /* BTR64mr */ >+ 0x14a, /* BTR64rr */ >+/* Table3412 */ >+ 0x4c8, /* LFS64rm */ >+ 0x0, /* */ >+/* Table3414 */ >+ 0x4ce, /* LGS64rm */ >+ 0x0, /* */ >+/* Table3416 */ >+ 0x6db, /* MOVZX64rm8_Q */ >+ 0x6dd, /* MOVZX64rr8_Q */ >+/* Table3418 */ >+ 0x6da, /* MOVZX64rm16_Q */ >+ 0x6dc, /* MOVZX64rr16_Q */ >+/* Table3420 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x12f, /* BT64mi8 */ >+ 0x153, /* BTS64mi8 */ >+ 0x147, /* BTR64mi8 */ >+ 0x13b, /* BTC64mi8 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x131, /* BT64ri8 */ >+ 0x155, /* BTS64ri8 */ >+ 0x149, /* BTR64ri8 */ >+ 0x13d, /* BTC64ri8 */ >+/* Table3436 */ >+ 0x13c, /* BTC64mr */ >+ 0x13e, /* BTC64rr */ >+/* Table3438 */ >+ 0x11d, /* BSF64rm */ >+ 0x11e, /* BSF64rr */ >+/* Table3440 */ >+ 0x123, /* BSR64rm */ >+ 0x124, /* BSR64rr */ >+/* Table3442 */ >+ 0x6c2, /* MOVSX64rm8 */ >+ 0x6c5, /* MOVSX64rr8 */ >+/* Table3444 */ >+ 0x6c0, /* MOVSX64rm16 */ >+ 0x6c3, /* MOVSX64rr16 */ >+/* Table3446 */ >+ 0x182d, /* XADD64rm */ >+ 0x182e, /* XADD64rr */ >+/* Table3448 */ >+ 0x698, /* MOVNTI_64mr */ >+ 0x0, /* */ >+/* Table3450 */ >+ 0x0, /* */ >+ 0x23a, /* CMPXCHG16B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1182, /* VMPTRLDm */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x931, /* RDRAND64r */ >+ 0x934, /* RDSEED64r */ >+/* Table3466 */ >+ 0x126, /* BSWAP64r */ >+/* Table3467 */ >+ 0xa26, /* SGDT64m */ >+ 0xa8b, /* SIDT64m */ >+ 0x4cb, /* LGDT64m */ >+ 0x4d1, /* LIDT64m */ >+ 0xa96, /* SMSW16m */ >+ 0x0, /* */ >+ 0x4d4, /* LMSW16m */ >+ 0x39c, /* INVLPG */ >+ 0x0, /* */ >+ 0xf5d, /* VMCALL */ >+ 0xf92, /* VMLAUNCH */ >+ 0x1188, /* VMRESUME */ >+ 0x11b7, /* VMXOFF */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x61e, /* MONITORrrr */ >+ 0x70d, /* MWAITrr */ >+ 0x16b, /* CLAC */ >+ 0xaaa, /* STAC */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x2e2, /* ENCLS */ >+ 0x1846, /* XGETBV */ >+ 0x1876, /* XSETBV */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5f, /* VMFUNC */ >+ 0x1845, /* XEND */ >+ 0x187a, /* XTEST */ >+ 0x2e3, /* ENCLU */ >+ 0x118a, /* VMRUN64 */ >+ 0xf95, /* VMMCALL */ >+ 0xf94, /* VMLOAD64 */ >+ 0x118c, /* VMSAVE64 */ >+ 0xaad, /* STGI */ >+ 0x16f, /* CLGI */ >+ 0xa90, /* SKINIT */ >+ 0x39e, /* INVLPGA64 */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0xa97, /* SMSW16r */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0x4d5, /* LMSW16r */ >+ 0xb28, /* SWAPGS */ >+ 0x936, /* RDTSCP */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3539 */ >+ 0x1186, /* VMREAD64rm */ >+ 0x2e8, /* EXTRQI */ >+/* Table3541 */ >+ 0x11b5, /* VMWRITE64rm */ >+ 0x2e7, /* EXTRQ */ >+/* Table3543 */ >+ 0x0, /* */ >+ 0x539, /* MASKMOVDQU64 */ >+/* Table3545 */ >+ 0x1186, /* VMREAD64rm */ >+ 0x392, /* INSERTQI */ >+/* Table3547 */ >+ 0x11b5, /* VMWRITE64rm */ >+ 0x391, /* INSERTQ */ >+/* Table3549 */ >+ 0x327, /* FXSAVE */ >+ 0x325, /* FXRSTOR */ >+ 0x4a8, /* LDMXCSR */ >+ 0xaaf, /* STMXCSR */ >+ 0x1872, /* XSAVE */ >+ 0x1870, /* XRSTOR */ >+ 0x1874, /* XSAVEOPT */ >+ 0x16e, /* CLFLUSH */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x929, /* RDFSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x92b, /* RDGSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1822, /* WRFSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x1824, /* WRGSBASE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4c5, /* LFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x54e, /* MFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa23, /* SFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3621 */ >+ 0x273, /* CVTSI2SS64rm */ >+ 0x274, /* CVTSI2SS64rr */ >+/* Table3623 */ >+ 0x285, /* CVTTSS2SI64rm */ >+ 0x286, /* CVTTSS2SI64rr */ >+/* Table3625 */ >+ 0x279, /* CVTSS2SI64rm */ >+ 0x27a, /* CVTSS2SI64rr */ >+/* Table3627 */ >+ 0x6a4, /* MOVQI2PQIrm */ >+ 0x572, /* MMX_MOVD64from64rr */ >+/* Table3629 */ >+ 0x328, /* FXSAVE64 */ >+ 0x326, /* FXRSTOR64 */ >+ 0x4a8, /* LDMXCSR */ >+ 0xaaf, /* STMXCSR */ >+ 0x1873, /* XSAVE64 */ >+ 0x1871, /* XRSTOR64 */ >+ 0x1875, /* XSAVEOPT64 */ >+ 0x16e, /* CLFLUSH */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92a, /* RDFSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x92c, /* RDGSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1823, /* WRFSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x1825, /* WRGSBASE64 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x4c5, /* LFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x54e, /* MFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xa23, /* SFENCE */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3701 */ >+ 0x865, /* POPCNT64rm */ >+ 0x866, /* POPCNT64rr */ >+/* Table3703 */ >+ 0xb6b, /* TZCNT64rm */ >+ 0xb6c, /* TZCNT64rr */ >+/* Table3705 */ >+ 0x536, /* LZCNT64rm */ >+ 0x537, /* LZCNT64rr */ >+/* Table3707 */ >+ 0x0, /* */ >+ 0x23a, /* CMPXCHG16B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x11b8, /* VMXON */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x931, /* RDRAND64r */ >+ 0x934, /* RDSEED64r */ >+/* Table3723 */ >+ 0x26f, /* CVTSI2SD64rm */ >+ 0x270, /* CVTSI2SD64rr */ >+/* Table3725 */ >+ 0x281, /* CVTTSD2SI64rm */ >+ 0x282, /* CVTTSD2SI64rr */ >+/* Table3727 */ >+ 0x269, /* CVTSD2SI64rm */ >+ 0x26a, /* CVTSD2SI64rr */ >+/* Table3729 */ >+ 0x67e, /* MOVDI2PDIrm */ >+ 0x65d, /* MOV64toPQIrr */ >+/* Table3731 */ >+ 0x69f, /* MOVPDI2DImr */ >+ 0x6a3, /* MOVPQIto64rr */ >+/* Table3733 */ >+ 0x0, /* */ >+ 0x23a, /* CMPXCHG16B */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf5e, /* VMCLEARm */ >+ 0x1183, /* VMPTRSTm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x931, /* RDRAND64r */ >+ 0x934, /* RDSEED64r */ >+/* Table3749 */ >+ 0x1175, /* VMOVUPSrm */ >+ 0x1176, /* VMOVUPSrr */ >+/* Table3751 */ >+ 0x1174, /* VMOVUPSmr */ >+ 0x1177, /* VMOVUPSrr_REV */ >+/* Table3753 */ >+ 0x10dc, /* VMOVLPSrm */ >+ 0x10d2, /* VMOVHLPSrr */ >+/* Table3755 */ >+ 0x10db, /* VMOVLPSmr */ >+ 0x0, /* */ >+/* Table3757 */ >+ 0x180e, /* VUNPCKLPSrm */ >+ 0x180f, /* VUNPCKLPSrr */ >+/* Table3759 */ >+ 0x1802, /* VUNPCKHPSrm */ >+ 0x1803, /* VUNPCKHPSrr */ >+/* Table3761 */ >+ 0x10d6, /* VMOVHPSrm */ >+ 0x10d8, /* VMOVLHPSrr */ >+/* Table3763 */ >+ 0x10d5, /* VMOVHPSmr */ >+ 0x0, /* */ >+/* Table3765 */ >+ 0xfea, /* VMOVAPSrm */ >+ 0xfeb, /* VMOVAPSrr */ >+/* Table3767 */ >+ 0xfe9, /* VMOVAPSmr */ >+ 0xfec, /* VMOVAPSrr_REV */ >+/* Table3769 */ >+ 0x10f4, /* VMOVNTPSmr */ >+ 0x0, /* */ >+/* Table3771 */ >+ 0x17f6, /* VUCOMISSrm */ >+ 0x17f7, /* VUCOMISSrr */ >+/* Table3773 */ >+ 0xc31, /* VCOMISSrm */ >+ 0xc32, /* VCOMISSrr */ >+/* Table3775 */ >+ 0x0, /* */ >+ 0x485, /* KNOTWrr */ >+/* Table3777 */ >+ 0x0, /* */ >+ 0x10e0, /* VMOVMSKPSrr */ >+/* Table3779 */ >+ 0x17b1, /* VSQRTPSm */ >+ 0x17b2, /* VSQRTPSr */ >+/* Table3781 */ >+ 0x1788, /* VRSQRTPSm */ >+ 0x178a, /* VRSQRTPSr */ >+/* Table3783 */ >+ 0x1753, /* VRCPPSm */ >+ 0x1755, /* VRCPPSr */ >+/* Table3785 */ >+ 0xbda, /* VANDPSrm */ >+ 0xbdb, /* VANDPSrr */ >+/* Table3787 */ >+ 0xbd2, /* VANDNPSrm */ >+ 0xbd3, /* VANDNPSrr */ >+/* Table3789 */ >+ 0x11bf, /* VORPSrm */ >+ 0x11c0, /* VORPSrr */ >+/* Table3791 */ >+ 0x1816, /* VXORPSrm */ >+ 0x1817, /* VXORPSrr */ >+/* Table3793 */ >+ 0xba2, /* VADDPSrm */ >+ 0xba3, /* VADDPSrr */ >+/* Table3795 */ >+ 0x11a5, /* VMULPSrm */ >+ 0x11a6, /* VMULPSrr */ >+/* Table3797 */ >+ 0xc62, /* VCVTPS2PDrm */ >+ 0xc63, /* VCVTPS2PDrr */ >+/* Table3799 */ >+ 0xc3e, /* VCVTDQ2PSrm */ >+ 0xc3f, /* VCVTDQ2PSrr */ >+/* Table3801 */ >+ 0x17da, /* VSUBPSrm */ >+ 0x17db, /* VSUBPSrr */ >+/* Table3803 */ >+ 0xf84, /* VMINPSrm */ >+ 0xf85, /* VMINPSrr */ >+/* Table3805 */ >+ 0xcea, /* VDIVPSrm */ >+ 0xceb, /* VDIVPSrr */ >+/* Table3807 */ >+ 0xf4f, /* VMAXPSrm */ >+ 0xf50, /* VMAXPSrr */ >+/* Table3809 */ >+ 0x1819, /* VZEROUPPER */ >+/* Table3810 */ >+ 0x47e, /* KMOVWkm */ >+ 0x47d, /* KMOVWkk */ >+/* Table3812 */ >+ 0x480, /* KMOVWmk */ >+ 0x0, /* */ >+/* Table3814 */ >+ 0x0, /* */ >+ 0x47f, /* KMOVWkr */ >+/* Table3816 */ >+ 0x0, /* */ >+ 0x481, /* KMOVWrk */ >+/* Table3818 */ >+ 0x0, /* */ >+ 0x489, /* KORTESTWrr */ >+/* Table3820 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf20, /* VLDMXCSR */ >+ 0x17c1, /* VSTMXCSR */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table3836 */ >+ 0xc17, /* VCMPPSrmi */ >+ 0xc19, /* VCMPPSrri */ >+/* Table3838 */ >+ 0x17a5, /* VSHUFPSrmi */ >+ 0x17a6, /* VSHUFPSrri */ >+/* Table3840 */ >+ 0x1123, /* VMOVSSrm */ >+ 0x1124, /* VMOVSSrr */ >+/* Table3842 */ >+ 0x1122, /* VMOVSSmr */ >+ 0x1125, /* VMOVSSrr_REV */ >+/* Table3844 */ >+ 0x1117, /* VMOVSLDUPrm */ >+ 0x1118, /* VMOVSLDUPrr */ >+/* Table3846 */ >+ 0x1111, /* VMOVSHDUPrm */ >+ 0x1112, /* VMOVSHDUPrr */ >+/* Table3848 */ >+ 0xc87, /* VCVTSI2SSrm */ >+ 0xc88, /* VCVTSI2SSrr */ >+/* Table3850 */ >+ 0xcbf, /* VCVTTSS2SIrm */ >+ 0xcc0, /* VCVTTSS2SIrr */ >+/* Table3852 */ >+ 0xc97, /* VCVTSS2SIrm */ >+ 0xc98, /* VCVTSS2SIrr */ >+/* Table3854 */ >+ 0x17be, /* VSQRTSSm */ >+ 0x17c0, /* VSQRTSSr */ >+/* Table3856 */ >+ 0x178c, /* VRSQRTSSm */ >+ 0x178e, /* VRSQRTSSr */ >+/* Table3858 */ >+ 0x1757, /* VRCPSSm */ >+ 0x1759, /* VRCPSSr */ >+/* Table3860 */ >+ 0xbac, /* VADDSSrm */ >+ 0xbae, /* VADDSSrr */ >+/* Table3862 */ >+ 0x11af, /* VMULSSrm */ >+ 0x11b1, /* VMULSSrr */ >+/* Table3864 */ >+ 0xc8f, /* VCVTSS2SDrm */ >+ 0xc90, /* VCVTSS2SDrr */ >+/* Table3866 */ >+ 0xca9, /* VCVTTPS2DQrm */ >+ 0xcaa, /* VCVTTPS2DQrr */ >+/* Table3868 */ >+ 0x17e4, /* VSUBSSrm */ >+ 0x17e6, /* VSUBSSrr */ >+/* Table3870 */ >+ 0xf8e, /* VMINSSrm */ >+ 0xf90, /* VMINSSrr */ >+/* Table3872 */ >+ 0xcf4, /* VDIVSSrm */ >+ 0xcf6, /* VDIVSSrr */ >+/* Table3874 */ >+ 0xf59, /* VMAXSSrm */ >+ 0xf5b, /* VMAXSSrr */ >+/* Table3876 */ >+ 0x10ce, /* VMOVDQUrm */ >+ 0x10cf, /* VMOVDQUrr */ >+/* Table3878 */ >+ 0x1629, /* VPSHUFHWmi */ >+ 0x162a, /* VPSHUFHWri */ >+/* Table3880 */ >+ 0x10ff, /* VMOVQI2PQIrm */ >+ 0x117b, /* VMOVZPQILo2PQIrr */ >+/* Table3882 */ >+ 0x10cd, /* VMOVDQUmr */ >+ 0x10d0, /* VMOVDQUrr_REV */ >+/* Table3884 */ >+ 0xc27, /* VCMPSSrm */ >+ 0xc29, /* VCMPSSrr */ >+/* Table3886 */ >+ 0xc37, /* VCVTDQ2PDrm */ >+ 0xc38, /* VCVTDQ2PDrr */ >+/* Table3888 */ >+ 0x1106, /* VMOVSDrm */ >+ 0x1107, /* VMOVSDrr */ >+/* Table3890 */ >+ 0x1105, /* VMOVSDmr */ >+ 0x1108, /* VMOVSDrr_REV */ >+/* Table3892 */ >+ 0xff1, /* VMOVDDUPrm */ >+ 0xff2, /* VMOVDDUPrr */ >+/* Table3894 */ >+ 0xc81, /* VCVTSI2SDrm */ >+ 0xc82, /* VCVTSI2SDrr */ >+/* Table3896 */ >+ 0xcb3, /* VCVTTSD2SIrm */ >+ 0xcb4, /* VCVTTSD2SIrr */ >+/* Table3898 */ >+ 0xc73, /* VCVTSD2SIrm */ >+ 0xc74, /* VCVTSD2SIrr */ >+/* Table3900 */ >+ 0x17b7, /* VSQRTSDm */ >+ 0x17b9, /* VSQRTSDr */ >+/* Table3902 */ >+ 0xba6, /* VADDSDrm */ >+ 0xba8, /* VADDSDrr */ >+/* Table3904 */ >+ 0x11a9, /* VMULSDrm */ >+ 0x11ab, /* VMULSDrr */ >+/* Table3906 */ >+ 0xc77, /* VCVTSD2SSrm */ >+ 0xc78, /* VCVTSD2SSrr */ >+/* Table3908 */ >+ 0x17de, /* VSUBSDrm */ >+ 0x17e0, /* VSUBSDrr */ >+/* Table3910 */ >+ 0xf88, /* VMINSDrm */ >+ 0xf8a, /* VMINSDrr */ >+/* Table3912 */ >+ 0xcee, /* VDIVSDrm */ >+ 0xcf0, /* VDIVSDrr */ >+/* Table3914 */ >+ 0xf53, /* VMAXSDrm */ >+ 0xf55, /* VMAXSDrr */ >+/* Table3916 */ >+ 0x162d, /* VPSHUFLWmi */ >+ 0x162e, /* VPSHUFLWri */ >+/* Table3918 */ >+ 0xf04, /* VHADDPSrm */ >+ 0xf05, /* VHADDPSrr */ >+/* Table3920 */ >+ 0xf0c, /* VHSUBPSrm */ >+ 0xf0d, /* VHSUBPSrr */ >+/* Table3922 */ >+ 0x0, /* */ >+ 0x475, /* KMOVDkr */ >+/* Table3924 */ >+ 0x0, /* */ >+ 0x477, /* KMOVDrk */ >+/* Table3926 */ >+ 0xc1f, /* VCMPSDrm */ >+ 0xc21, /* VCMPSDrr */ >+/* Table3928 */ >+ 0xbb6, /* VADDSUBPSrm */ >+ 0xbb7, /* VADDSUBPSrr */ >+/* Table3930 */ >+ 0xc40, /* VCVTPD2DQXrm */ >+ 0xc46, /* VCVTPD2DQrr */ >+/* Table3932 */ >+ 0xf1f, /* VLDDQUrm */ >+ 0x0, /* */ >+/* Table3934 */ >+ 0x114c, /* VMOVUPDrm */ >+ 0x114d, /* VMOVUPDrr */ >+/* Table3936 */ >+ 0x114b, /* VMOVUPDmr */ >+ 0x114e, /* VMOVUPDrr_REV */ >+/* Table3938 */ >+ 0x10da, /* VMOVLPDrm */ >+ 0x0, /* */ >+/* Table3940 */ >+ 0x10d9, /* VMOVLPDmr */ >+ 0x0, /* */ >+/* Table3942 */ >+ 0x1808, /* VUNPCKLPDrm */ >+ 0x1809, /* VUNPCKLPDrr */ >+/* Table3944 */ >+ 0x17fc, /* VUNPCKHPDrm */ >+ 0x17fd, /* VUNPCKHPDrr */ >+/* Table3946 */ >+ 0x10d4, /* VMOVHPDrm */ >+ 0x0, /* */ >+/* Table3948 */ >+ 0x10d3, /* VMOVHPDmr */ >+ 0x0, /* */ >+/* Table3950 */ >+ 0xfc1, /* VMOVAPDrm */ >+ 0xfc2, /* VMOVAPDrr */ >+/* Table3952 */ >+ 0xfc0, /* VMOVAPDmr */ >+ 0xfc3, /* VMOVAPDrr_REV */ >+/* Table3954 */ >+ 0x10ef, /* VMOVNTPDmr */ >+ 0x0, /* */ >+/* Table3956 */ >+ 0x17f2, /* VUCOMISDrm */ >+ 0x17f3, /* VUCOMISDrr */ >+/* Table3958 */ >+ 0xc2d, /* VCOMISDrm */ >+ 0xc2e, /* VCOMISDrr */ >+/* Table3960 */ >+ 0x0, /* */ >+ 0x482, /* KNOTBrr */ >+/* Table3962 */ >+ 0x0, /* */ >+ 0x10de, /* VMOVMSKPDrr */ >+/* Table3964 */ >+ 0x17ab, /* VSQRTPDm */ >+ 0x17ac, /* VSQRTPDr */ >+/* Table3966 */ >+ 0xbd6, /* VANDPDrm */ >+ 0xbd7, /* VANDPDrr */ >+/* Table3968 */ >+ 0xbce, /* VANDNPDrm */ >+ 0xbcf, /* VANDNPDrr */ >+/* Table3970 */ >+ 0x11bb, /* VORPDrm */ >+ 0x11bc, /* VORPDrr */ >+/* Table3972 */ >+ 0x1812, /* VXORPDrm */ >+ 0x1813, /* VXORPDrr */ >+/* Table3974 */ >+ 0xb95, /* VADDPDrm */ >+ 0xb96, /* VADDPDrr */ >+/* Table3976 */ >+ 0x1198, /* VMULPDrm */ >+ 0x1199, /* VMULPDrr */ >+/* Table3978 */ >+ 0xc47, /* VCVTPD2PSXrm */ >+ 0xc4d, /* VCVTPD2PSrr */ >+/* Table3980 */ >+ 0xc5c, /* VCVTPS2DQrm */ >+ 0xc5d, /* VCVTPS2DQrr */ >+/* Table3982 */ >+ 0x17cd, /* VSUBPDrm */ >+ 0x17ce, /* VSUBPDrr */ >+/* Table3984 */ >+ 0xf77, /* VMINPDrm */ >+ 0xf78, /* VMINPDrr */ >+/* Table3986 */ >+ 0xcdd, /* VDIVPDrm */ >+ 0xcde, /* VDIVPDrr */ >+/* Table3988 */ >+ 0xf42, /* VMAXPDrm */ >+ 0xf43, /* VMAXPDrr */ >+/* Table3990 */ >+ 0x1713, /* VPUNPCKLBWrm */ >+ 0x1714, /* VPUNPCKLBWrr */ >+/* Table3992 */ >+ 0x1723, /* VPUNPCKLWDrm */ >+ 0x1724, /* VPUNPCKLWDrr */ >+/* Table3994 */ >+ 0x1719, /* VPUNPCKLDQrm */ >+ 0x171a, /* VPUNPCKLDQrr */ >+/* Table3996 */ >+ 0x11e5, /* VPACKSSWBrm */ >+ 0x11e6, /* VPACKSSWBrr */ >+/* Table3998 */ >+ 0x12f7, /* VPCMPGTBrm */ >+ 0x12f8, /* VPCMPGTBrr */ >+/* Table4000 */ >+ 0x1333, /* VPCMPGTWrm */ >+ 0x1334, /* VPCMPGTWrr */ >+/* Table4002 */ >+ 0x130d, /* VPCMPGTDrm */ >+ 0x130e, /* VPCMPGTDrr */ >+/* Table4004 */ >+ 0x11ed, /* VPACKUSWBrm */ >+ 0x11ee, /* VPACKUSWBrr */ >+/* Table4006 */ >+ 0x16ff, /* VPUNPCKHBWrm */ >+ 0x1700, /* VPUNPCKHBWrr */ >+/* Table4008 */ >+ 0x170f, /* VPUNPCKHWDrm */ >+ 0x1710, /* VPUNPCKHWDrr */ >+/* Table4010 */ >+ 0x1705, /* VPUNPCKHDQrm */ >+ 0x1706, /* VPUNPCKHDQrr */ >+/* Table4012 */ >+ 0x11e1, /* VPACKSSDWrm */ >+ 0x11e2, /* VPACKSSDWrr */ >+/* Table4014 */ >+ 0x171f, /* VPUNPCKLQDQrm */ >+ 0x1720, /* VPUNPCKLQDQrr */ >+/* Table4016 */ >+ 0x170b, /* VPUNPCKHQDQrm */ >+ 0x170c, /* VPUNPCKHQDQrr */ >+/* Table4018 */ >+ 0xff5, /* VMOVDI2PDIrm */ >+ 0xff6, /* VMOVDI2PDIrr */ >+/* Table4020 */ >+ 0x1042, /* VMOVDQArm */ >+ 0x1043, /* VMOVDQArr */ >+/* Table4022 */ >+ 0x1625, /* VPSHUFDmi */ >+ 0x1626, /* VPSHUFDri */ >+/* Table4024 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16bc, /* VPSRLWri */ >+ 0x0, /* */ >+ 0x168c, /* VPSRAWri */ >+ 0x0, /* */ >+ 0x1668, /* VPSLLWri */ >+ 0x0, /* */ >+/* Table4040 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x169c, /* VPSRLDri */ >+ 0x0, /* */ >+ 0x1676, /* VPSRADri */ >+ 0x0, /* */ >+ 0x1648, /* VPSLLDri */ >+ 0x0, /* */ >+/* Table4056 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16aa, /* VPSRLQri */ >+ 0x1690, /* VPSRLDQri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1656, /* VPSLLQri */ >+ 0x163c, /* VPSLLDQri */ >+/* Table4072 */ >+ 0x12a3, /* VPCMPEQBrm */ >+ 0x12a4, /* VPCMPEQBrr */ >+/* Table4074 */ >+ 0x12df, /* VPCMPEQWrm */ >+ 0x12e0, /* VPCMPEQWrr */ >+/* Table4076 */ >+ 0x12b9, /* VPCMPEQDrm */ >+ 0x12ba, /* VPCMPEQDrr */ >+/* Table4078 */ >+ 0xf00, /* VHADDPDrm */ >+ 0xf01, /* VHADDPDrr */ >+/* Table4080 */ >+ 0xf08, /* VHSUBPDrm */ >+ 0xf09, /* VHSUBPDrr */ >+/* Table4082 */ >+ 0x10f7, /* VMOVPDI2DImr */ >+ 0x10f8, /* VMOVPDI2DIrr */ >+/* Table4084 */ >+ 0x1041, /* VMOVDQAmr */ >+ 0x1044, /* VMOVDQArr_REV */ >+/* Table4086 */ >+ 0x46f, /* KMOVBkm */ >+ 0x46e, /* KMOVBkk */ >+/* Table4088 */ >+ 0x471, /* KMOVBmk */ >+ 0x0, /* */ >+/* Table4090 */ >+ 0x0, /* */ >+ 0x470, /* KMOVBkr */ >+/* Table4092 */ >+ 0x0, /* */ >+ 0x472, /* KMOVBrk */ >+/* Table4094 */ >+ 0xc0a, /* VCMPPDrmi */ >+ 0xc0c, /* VCMPPDrri */ >+/* Table4096 */ >+ 0x142c, /* VPINSRWrmi */ >+ 0x142d, /* VPINSRWrri */ >+/* Table4098 */ >+ 0x0, /* */ >+ 0x13e0, /* VPEXTRWri */ >+/* Table4100 */ >+ 0x179f, /* VSHUFPDrmi */ >+ 0x17a0, /* VSHUFPDrri */ >+/* Table4102 */ >+ 0xbb2, /* VADDSUBPDrm */ >+ 0xbb3, /* VADDSUBPDrr */ >+/* Table4104 */ >+ 0x16bd, /* VPSRLWrm */ >+ 0x16be, /* VPSRLWrr */ >+/* Table4106 */ >+ 0x169d, /* VPSRLDrm */ >+ 0x169e, /* VPSRLDrr */ >+/* Table4108 */ >+ 0x16ab, /* VPSRLQrm */ >+ 0x16ac, /* VPSRLQrr */ >+/* Table4110 */ >+ 0x120b, /* VPADDQrm */ >+ 0x120c, /* VPADDQrr */ >+/* Table4112 */ >+ 0x15c1, /* VPMULLWrm */ >+ 0x15c2, /* VPMULLWrr */ >+/* Table4114 */ >+ 0x10f9, /* VMOVPQI2QImr */ >+ 0x10fa, /* VMOVPQI2QIrr */ >+/* Table4116 */ >+ 0x0, /* */ >+ 0x14eb, /* VPMOVMSKBrr */ >+/* Table4118 */ >+ 0x16e7, /* VPSUBUSBrm */ >+ 0x16e8, /* VPSUBUSBrr */ >+/* Table4120 */ >+ 0x16eb, /* VPSUBUSWrm */ >+ 0x16ec, /* VPSUBUSWrr */ >+/* Table4122 */ >+ 0x14c4, /* VPMINUBrm */ >+ 0x14c5, /* VPMINUBrr */ >+/* Table4124 */ >+ 0x124f, /* VPANDrm */ >+ 0x1250, /* VPANDrr */ >+/* Table4126 */ >+ 0x1217, /* VPADDUSBrm */ >+ 0x1218, /* VPADDUSBrr */ >+/* Table4128 */ >+ 0x121b, /* VPADDUSWrm */ >+ 0x121c, /* VPADDUSWrr */ >+/* Table4130 */ >+ 0x1488, /* VPMAXUBrm */ >+ 0x1489, /* VPMAXUBrr */ >+/* Table4132 */ >+ 0x1242, /* VPANDNrm */ >+ 0x1243, /* VPANDNrr */ >+/* Table4134 */ >+ 0x1253, /* VPAVGBrm */ >+ 0x1254, /* VPAVGBrr */ >+/* Table4136 */ >+ 0x168d, /* VPSRAWrm */ >+ 0x168e, /* VPSRAWrr */ >+/* Table4138 */ >+ 0x1677, /* VPSRADrm */ >+ 0x1678, /* VPSRADrr */ >+/* Table4140 */ >+ 0x1257, /* VPAVGWrm */ >+ 0x1258, /* VPAVGWrr */ >+/* Table4142 */ >+ 0x15ac, /* VPMULHUWrm */ >+ 0x15ad, /* VPMULHUWrr */ >+/* Table4144 */ >+ 0x15b0, /* VPMULHWrm */ >+ 0x15b1, /* VPMULHWrr */ >+/* Table4146 */ >+ 0xc9d, /* VCVTTPD2DQXrm */ >+ 0xca2, /* VCVTTPD2DQrr */ >+/* Table4148 */ >+ 0x10ea, /* VMOVNTDQmr */ >+ 0x0, /* */ >+/* Table4150 */ >+ 0x16df, /* VPSUBSBrm */ >+ 0x16e0, /* VPSUBSBrr */ >+/* Table4152 */ >+ 0x16e3, /* VPSUBSWrm */ >+ 0x16e4, /* VPSUBSWrr */ >+/* Table4154 */ >+ 0x14c0, /* VPMINSWrm */ >+ 0x14c1, /* VPMINSWrr */ >+/* Table4156 */ >+ 0x15e4, /* VPORrm */ >+ 0x15e5, /* VPORrr */ >+/* Table4158 */ >+ 0x120f, /* VPADDSBrm */ >+ 0x1210, /* VPADDSBrr */ >+/* Table4160 */ >+ 0x1213, /* VPADDSWrm */ >+ 0x1214, /* VPADDSWrr */ >+/* Table4162 */ >+ 0x1484, /* VPMAXSWrm */ >+ 0x1485, /* VPMAXSWrr */ >+/* Table4164 */ >+ 0x1739, /* VPXORrm */ >+ 0x173a, /* VPXORrr */ >+/* Table4166 */ >+ 0x1669, /* VPSLLWrm */ >+ 0x166a, /* VPSLLWrr */ >+/* Table4168 */ >+ 0x1649, /* VPSLLDrm */ >+ 0x164a, /* VPSLLDrr */ >+/* Table4170 */ >+ 0x1657, /* VPSLLQrm */ >+ 0x1658, /* VPSLLQrr */ >+/* Table4172 */ >+ 0x15ce, /* VPMULUDQrm */ >+ 0x15cf, /* VPMULUDQrr */ >+/* Table4174 */ >+ 0x145e, /* VPMADDWDrm */ >+ 0x145f, /* VPMADDWDrr */ >+/* Table4176 */ >+ 0x15ff, /* VPSADBWrm */ >+ 0x1600, /* VPSADBWrr */ >+/* Table4178 */ >+ 0x0, /* */ >+ 0xf21, /* VMASKMOVDQU */ >+/* Table4180 */ >+ 0x16c1, /* VPSUBBrm */ >+ 0x16c2, /* VPSUBBrr */ >+/* Table4182 */ >+ 0x16ef, /* VPSUBWrm */ >+ 0x16f0, /* VPSUBWrr */ >+/* Table4184 */ >+ 0x16ce, /* VPSUBDrm */ >+ 0x16cf, /* VPSUBDrr */ >+/* Table4186 */ >+ 0x16db, /* VPSUBQrm */ >+ 0x16dc, /* VPSUBQrr */ >+/* Table4188 */ >+ 0x11f1, /* VPADDBrm */ >+ 0x11f2, /* VPADDBrr */ >+/* Table4190 */ >+ 0x121f, /* VPADDWrm */ >+ 0x1220, /* VPADDWrr */ >+/* Table4192 */ >+ 0x11fe, /* VPADDDrm */ >+ 0x11ff, /* VPADDDrr */ >+/* Table4194 */ >+ 0x0, /* */ >+ 0x484, /* KNOTQrr */ >+/* Table4196 */ >+ 0x479, /* KMOVQkm */ >+ 0x478, /* KMOVQkk */ >+/* Table4198 */ >+ 0x47b, /* KMOVQmk */ >+ 0x0, /* */ >+/* Table4200 */ >+ 0xc83, /* VCVTSI2SS64rm */ >+ 0xc84, /* VCVTSI2SS64rr */ >+/* Table4202 */ >+ 0xcbb, /* VCVTTSS2SI64rm */ >+ 0xcbc, /* VCVTTSS2SI64rr */ >+/* Table4204 */ >+ 0xc93, /* VCVTSS2SI64rm */ >+ 0xc94, /* VCVTSS2SI64rr */ >+/* Table4206 */ >+ 0xc7d, /* VCVTSI2SD64rm */ >+ 0xc7e, /* VCVTSI2SD64rr */ >+/* Table4208 */ >+ 0xcaf, /* VCVTTSD2SI64rm */ >+ 0xcb0, /* VCVTTSD2SI64rr */ >+/* Table4210 */ >+ 0xc6f, /* VCVTSD2SI64rm */ >+ 0xc70, /* VCVTSD2SI64rr */ >+/* Table4212 */ >+ 0x0, /* */ >+ 0x47a, /* KMOVQkr */ >+/* Table4214 */ >+ 0x0, /* */ >+ 0x47c, /* KMOVQrk */ >+/* Table4216 */ >+ 0x0, /* */ >+ 0x483, /* KNOTDrr */ >+/* Table4218 */ >+ 0xff5, /* VMOVDI2PDIrm */ >+ 0xf97, /* VMOV64toPQIrr */ >+/* Table4220 */ >+ 0x10f7, /* VMOVPDI2DImr */ >+ 0x10fd, /* VMOVPQIto64rr */ >+/* Table4222 */ >+ 0x474, /* KMOVDkm */ >+ 0x473, /* KMOVDkk */ >+/* Table4224 */ >+ 0x476, /* KMOVDmk */ >+ 0x0, /* */ >+/* Table4226 */ >+ 0x1150, /* VMOVUPSYrm */ >+ 0x1151, /* VMOVUPSYrr */ >+/* Table4228 */ >+ 0x114f, /* VMOVUPSYmr */ >+ 0x1152, /* VMOVUPSYrr_REV */ >+/* Table4230 */ >+ 0x180a, /* VUNPCKLPSYrm */ >+ 0x180b, /* VUNPCKLPSYrr */ >+/* Table4232 */ >+ 0x17fe, /* VUNPCKHPSYrm */ >+ 0x17ff, /* VUNPCKHPSYrr */ >+/* Table4234 */ >+ 0xfc5, /* VMOVAPSYrm */ >+ 0xfc6, /* VMOVAPSYrr */ >+/* Table4236 */ >+ 0xfc4, /* VMOVAPSYmr */ >+ 0xfc7, /* VMOVAPSYrr_REV */ >+/* Table4238 */ >+ 0x10f0, /* VMOVNTPSYmr */ >+ 0x0, /* */ >+/* Table4240 */ >+ 0x0, /* */ >+ 0x46d, /* KANDWrr */ >+/* Table4242 */ >+ 0x0, /* */ >+ 0x46b, /* KANDNWrr */ >+/* Table4244 */ >+ 0x0, /* */ >+ 0x48a, /* KORWrr */ >+/* Table4246 */ >+ 0x0, /* */ >+ 0x495, /* KXNORWrr */ >+/* Table4248 */ >+ 0x0, /* */ >+ 0x499, /* KXORWrr */ >+/* Table4250 */ >+ 0x0, /* */ >+ 0x10df, /* VMOVMSKPSYrr */ >+/* Table4252 */ >+ 0x17ad, /* VSQRTPSYm */ >+ 0x17ae, /* VSQRTPSYr */ >+/* Table4254 */ >+ 0x1784, /* VRSQRTPSYm */ >+ 0x1786, /* VRSQRTPSYr */ >+/* Table4256 */ >+ 0x174f, /* VRCPPSYm */ >+ 0x1751, /* VRCPPSYr */ >+/* Table4258 */ >+ 0xbd8, /* VANDPSYrm */ >+ 0xbd9, /* VANDPSYrr */ >+/* Table4260 */ >+ 0xbd0, /* VANDNPSYrm */ >+ 0xbd1, /* VANDNPSYrr */ >+/* Table4262 */ >+ 0x11bd, /* VORPSYrm */ >+ 0x11be, /* VORPSYrr */ >+/* Table4264 */ >+ 0x1814, /* VXORPSYrm */ >+ 0x1815, /* VXORPSYrr */ >+/* Table4266 */ >+ 0xb97, /* VADDPSYrm */ >+ 0xb98, /* VADDPSYrr */ >+/* Table4268 */ >+ 0x119a, /* VMULPSYrm */ >+ 0x119b, /* VMULPSYrr */ >+/* Table4270 */ >+ 0xc5e, /* VCVTPS2PDYrm */ >+ 0xc5f, /* VCVTPS2PDYrr */ >+/* Table4272 */ >+ 0xc39, /* VCVTDQ2PSYrm */ >+ 0xc3a, /* VCVTDQ2PSYrr */ >+/* Table4274 */ >+ 0x17cf, /* VSUBPSYrm */ >+ 0x17d0, /* VSUBPSYrr */ >+/* Table4276 */ >+ 0xf79, /* VMINPSYrm */ >+ 0xf7a, /* VMINPSYrr */ >+/* Table4278 */ >+ 0xcdf, /* VDIVPSYrm */ >+ 0xce0, /* VDIVPSYrr */ >+/* Table4280 */ >+ 0xf44, /* VMAXPSYrm */ >+ 0xf45, /* VMAXPSYrr */ >+/* Table4282 */ >+ 0x1818, /* VZEROALL */ >+/* Table4283 */ >+ 0xc0e, /* VCMPPSYrmi */ >+ 0xc10, /* VCMPPSYrri */ >+/* Table4285 */ >+ 0x17a1, /* VSHUFPSYrmi */ >+ 0x17a2, /* VSHUFPSYrri */ >+/* Table4287 */ >+ 0x1113, /* VMOVSLDUPYrm */ >+ 0x1114, /* VMOVSLDUPYrr */ >+/* Table4289 */ >+ 0x110d, /* VMOVSHDUPYrm */ >+ 0x110e, /* VMOVSHDUPYrr */ >+/* Table4291 */ >+ 0xca5, /* VCVTTPS2DQYrm */ >+ 0xca6, /* VCVTTPS2DQYrr */ >+/* Table4293 */ >+ 0x10ca, /* VMOVDQUYrm */ >+ 0x10cb, /* VMOVDQUYrr */ >+/* Table4295 */ >+ 0x1627, /* VPSHUFHWYmi */ >+ 0x1628, /* VPSHUFHWYri */ >+/* Table4297 */ >+ 0x10c9, /* VMOVDQUYmr */ >+ 0x10cc, /* VMOVDQUYrr_REV */ >+/* Table4299 */ >+ 0xc33, /* VCVTDQ2PDYrm */ >+ 0xc34, /* VCVTDQ2PDYrr */ >+/* Table4301 */ >+ 0xfed, /* VMOVDDUPYrm */ >+ 0xfee, /* VMOVDDUPYrr */ >+/* Table4303 */ >+ 0x162b, /* VPSHUFLWYmi */ >+ 0x162c, /* VPSHUFLWYri */ >+/* Table4305 */ >+ 0xf02, /* VHADDPSYrm */ >+ 0xf03, /* VHADDPSYrr */ >+/* Table4307 */ >+ 0xf0a, /* VHSUBPSYrm */ >+ 0xf0b, /* VHSUBPSYrr */ >+/* Table4309 */ >+ 0xbb4, /* VADDSUBPSYrm */ >+ 0xbb5, /* VADDSUBPSYrr */ >+/* Table4311 */ >+ 0xc41, /* VCVTPD2DQYrm */ >+ 0xc42, /* VCVTPD2DQYrr */ >+/* Table4313 */ >+ 0xf1e, /* VLDDQUYrm */ >+ 0x0, /* */ >+/* Table4315 */ >+ 0x1127, /* VMOVUPDYrm */ >+ 0x1128, /* VMOVUPDYrr */ >+/* Table4317 */ >+ 0x1126, /* VMOVUPDYmr */ >+ 0x1129, /* VMOVUPDYrr_REV */ >+/* Table4319 */ >+ 0x1804, /* VUNPCKLPDYrm */ >+ 0x1805, /* VUNPCKLPDYrr */ >+/* Table4321 */ >+ 0x17f8, /* VUNPCKHPDYrm */ >+ 0x17f9, /* VUNPCKHPDYrr */ >+/* Table4323 */ >+ 0xf9c, /* VMOVAPDYrm */ >+ 0xf9d, /* VMOVAPDYrr */ >+/* Table4325 */ >+ 0xf9b, /* VMOVAPDYmr */ >+ 0xf9e, /* VMOVAPDYrr_REV */ >+/* Table4327 */ >+ 0x10eb, /* VMOVNTPDYmr */ >+ 0x0, /* */ >+/* Table4329 */ >+ 0x0, /* */ >+ 0x466, /* KANDBrr */ >+/* Table4331 */ >+ 0x0, /* */ >+ 0x468, /* KANDNBrr */ >+/* Table4333 */ >+ 0x0, /* */ >+ 0x486, /* KORBrr */ >+/* Table4335 */ >+ 0x0, /* */ >+ 0x492, /* KXNORBrr */ >+/* Table4337 */ >+ 0x0, /* */ >+ 0x496, /* KXORBrr */ >+/* Table4339 */ >+ 0x0, /* */ >+ 0x491, /* KUNPCKBWrr */ >+/* Table4341 */ >+ 0x0, /* */ >+ 0x10dd, /* VMOVMSKPDYrr */ >+/* Table4343 */ >+ 0x17a7, /* VSQRTPDYm */ >+ 0x17a8, /* VSQRTPDYr */ >+/* Table4345 */ >+ 0xbd4, /* VANDPDYrm */ >+ 0xbd5, /* VANDPDYrr */ >+/* Table4347 */ >+ 0xbcc, /* VANDNPDYrm */ >+ 0xbcd, /* VANDNPDYrr */ >+/* Table4349 */ >+ 0x11b9, /* VORPDYrm */ >+ 0x11ba, /* VORPDYrr */ >+/* Table4351 */ >+ 0x1810, /* VXORPDYrm */ >+ 0x1811, /* VXORPDYrr */ >+/* Table4353 */ >+ 0xb8a, /* VADDPDYrm */ >+ 0xb8b, /* VADDPDYrr */ >+/* Table4355 */ >+ 0x118d, /* VMULPDYrm */ >+ 0x118e, /* VMULPDYrr */ >+/* Table4357 */ >+ 0xc48, /* VCVTPD2PSYrm */ >+ 0xc49, /* VCVTPD2PSYrr */ >+/* Table4359 */ >+ 0xc57, /* VCVTPS2DQYrm */ >+ 0xc58, /* VCVTPS2DQYrr */ >+/* Table4361 */ >+ 0x17c2, /* VSUBPDYrm */ >+ 0x17c3, /* VSUBPDYrr */ >+/* Table4363 */ >+ 0xf6c, /* VMINPDYrm */ >+ 0xf6d, /* VMINPDYrr */ >+/* Table4365 */ >+ 0xcd2, /* VDIVPDYrm */ >+ 0xcd3, /* VDIVPDYrr */ >+/* Table4367 */ >+ 0xf37, /* VMAXPDYrm */ >+ 0xf38, /* VMAXPDYrr */ >+/* Table4369 */ >+ 0x1711, /* VPUNPCKLBWYrm */ >+ 0x1712, /* VPUNPCKLBWYrr */ >+/* Table4371 */ >+ 0x1721, /* VPUNPCKLWDYrm */ >+ 0x1722, /* VPUNPCKLWDYrr */ >+/* Table4373 */ >+ 0x1715, /* VPUNPCKLDQYrm */ >+ 0x1716, /* VPUNPCKLDQYrr */ >+/* Table4375 */ >+ 0x11e3, /* VPACKSSWBYrm */ >+ 0x11e4, /* VPACKSSWBYrr */ >+/* Table4377 */ >+ 0x12e9, /* VPCMPGTBYrm */ >+ 0x12ea, /* VPCMPGTBYrr */ >+/* Table4379 */ >+ 0x1325, /* VPCMPGTWYrm */ >+ 0x1326, /* VPCMPGTWYrr */ >+/* Table4381 */ >+ 0x12f9, /* VPCMPGTDYrm */ >+ 0x12fa, /* VPCMPGTDYrr */ >+/* Table4383 */ >+ 0x11eb, /* VPACKUSWBYrm */ >+ 0x11ec, /* VPACKUSWBYrr */ >+/* Table4385 */ >+ 0x16fd, /* VPUNPCKHBWYrm */ >+ 0x16fe, /* VPUNPCKHBWYrr */ >+/* Table4387 */ >+ 0x170d, /* VPUNPCKHWDYrm */ >+ 0x170e, /* VPUNPCKHWDYrr */ >+/* Table4389 */ >+ 0x1701, /* VPUNPCKHDQYrm */ >+ 0x1702, /* VPUNPCKHDQYrr */ >+/* Table4391 */ >+ 0x11df, /* VPACKSSDWYrm */ >+ 0x11e0, /* VPACKSSDWYrr */ >+/* Table4393 */ >+ 0x171b, /* VPUNPCKLQDQYrm */ >+ 0x171c, /* VPUNPCKLQDQYrr */ >+/* Table4395 */ >+ 0x1707, /* VPUNPCKHQDQYrm */ >+ 0x1708, /* VPUNPCKHQDQYrr */ >+/* Table4397 */ >+ 0x103e, /* VMOVDQAYrm */ >+ 0x103f, /* VMOVDQAYrr */ >+/* Table4399 */ >+ 0x1621, /* VPSHUFDYmi */ >+ 0x1622, /* VPSHUFDYri */ >+/* Table4401 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16b9, /* VPSRLWYri */ >+ 0x0, /* */ >+ 0x1689, /* VPSRAWYri */ >+ 0x0, /* */ >+ 0x1665, /* VPSLLWYri */ >+ 0x0, /* */ >+/* Table4417 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1691, /* VPSRLDYri */ >+ 0x0, /* */ >+ 0x166b, /* VPSRADYri */ >+ 0x0, /* */ >+ 0x163d, /* VPSLLDYri */ >+ 0x0, /* */ >+/* Table4433 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x169f, /* VPSRLQYri */ >+ 0x168f, /* VPSRLDQYri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x164b, /* VPSLLQYri */ >+ 0x163b, /* VPSLLDQYri */ >+/* Table4449 */ >+ 0x1295, /* VPCMPEQBYrm */ >+ 0x1296, /* VPCMPEQBYrr */ >+/* Table4451 */ >+ 0x12d1, /* VPCMPEQWYrm */ >+ 0x12d2, /* VPCMPEQWYrr */ >+/* Table4453 */ >+ 0x12a5, /* VPCMPEQDYrm */ >+ 0x12a6, /* VPCMPEQDYrr */ >+/* Table4455 */ >+ 0xefe, /* VHADDPDYrm */ >+ 0xeff, /* VHADDPDYrr */ >+/* Table4457 */ >+ 0xf06, /* VHSUBPDYrm */ >+ 0xf07, /* VHSUBPDYrr */ >+/* Table4459 */ >+ 0x103d, /* VMOVDQAYmr */ >+ 0x1040, /* VMOVDQAYrr_REV */ >+/* Table4461 */ >+ 0xc01, /* VCMPPDYrmi */ >+ 0xc03, /* VCMPPDYrri */ >+/* Table4463 */ >+ 0x179b, /* VSHUFPDYrmi */ >+ 0x179c, /* VSHUFPDYrri */ >+/* Table4465 */ >+ 0xbb0, /* VADDSUBPDYrm */ >+ 0xbb1, /* VADDSUBPDYrr */ >+/* Table4467 */ >+ 0x16ba, /* VPSRLWYrm */ >+ 0x16bb, /* VPSRLWYrr */ >+/* Table4469 */ >+ 0x1692, /* VPSRLDYrm */ >+ 0x1693, /* VPSRLDYrr */ >+/* Table4471 */ >+ 0x16a0, /* VPSRLQYrm */ >+ 0x16a1, /* VPSRLQYrr */ >+/* Table4473 */ >+ 0x1200, /* VPADDQYrm */ >+ 0x1201, /* VPADDQYrr */ >+/* Table4475 */ >+ 0x15bf, /* VPMULLWYrm */ >+ 0x15c0, /* VPMULLWYrr */ >+/* Table4477 */ >+ 0x0, /* */ >+ 0x14ea, /* VPMOVMSKBYrr */ >+/* Table4479 */ >+ 0x16e5, /* VPSUBUSBYrm */ >+ 0x16e6, /* VPSUBUSBYrr */ >+/* Table4481 */ >+ 0x16e9, /* VPSUBUSWYrm */ >+ 0x16ea, /* VPSUBUSWYrr */ >+/* Table4483 */ >+ 0x14c2, /* VPMINUBYrm */ >+ 0x14c3, /* VPMINUBYrr */ >+/* Table4485 */ >+ 0x124d, /* VPANDYrm */ >+ 0x124e, /* VPANDYrr */ >+/* Table4487 */ >+ 0x1215, /* VPADDUSBYrm */ >+ 0x1216, /* VPADDUSBYrr */ >+/* Table4489 */ >+ 0x1219, /* VPADDUSWYrm */ >+ 0x121a, /* VPADDUSWYrr */ >+/* Table4491 */ >+ 0x1486, /* VPMAXUBYrm */ >+ 0x1487, /* VPMAXUBYrr */ >+/* Table4493 */ >+ 0x1240, /* VPANDNYrm */ >+ 0x1241, /* VPANDNYrr */ >+/* Table4495 */ >+ 0x1251, /* VPAVGBYrm */ >+ 0x1252, /* VPAVGBYrr */ >+/* Table4497 */ >+ 0x168a, /* VPSRAWYrm */ >+ 0x168b, /* VPSRAWYrr */ >+/* Table4499 */ >+ 0x166c, /* VPSRADYrm */ >+ 0x166d, /* VPSRADYrr */ >+/* Table4501 */ >+ 0x1255, /* VPAVGWYrm */ >+ 0x1256, /* VPAVGWYrr */ >+/* Table4503 */ >+ 0x15aa, /* VPMULHUWYrm */ >+ 0x15ab, /* VPMULHUWYrr */ >+/* Table4505 */ >+ 0x15ae, /* VPMULHWYrm */ >+ 0x15af, /* VPMULHWYrr */ >+/* Table4507 */ >+ 0xc9e, /* VCVTTPD2DQYrm */ >+ 0xc9f, /* VCVTTPD2DQYrr */ >+/* Table4509 */ >+ 0x10e6, /* VMOVNTDQYmr */ >+ 0x0, /* */ >+/* Table4511 */ >+ 0x16dd, /* VPSUBSBYrm */ >+ 0x16de, /* VPSUBSBYrr */ >+/* Table4513 */ >+ 0x16e1, /* VPSUBSWYrm */ >+ 0x16e2, /* VPSUBSWYrr */ >+/* Table4515 */ >+ 0x14be, /* VPMINSWYrm */ >+ 0x14bf, /* VPMINSWYrr */ >+/* Table4517 */ >+ 0x15e2, /* VPORYrm */ >+ 0x15e3, /* VPORYrr */ >+/* Table4519 */ >+ 0x120d, /* VPADDSBYrm */ >+ 0x120e, /* VPADDSBYrr */ >+/* Table4521 */ >+ 0x1211, /* VPADDSWYrm */ >+ 0x1212, /* VPADDSWYrr */ >+/* Table4523 */ >+ 0x1482, /* VPMAXSWYrm */ >+ 0x1483, /* VPMAXSWYrr */ >+/* Table4525 */ >+ 0x1737, /* VPXORYrm */ >+ 0x1738, /* VPXORYrr */ >+/* Table4527 */ >+ 0x1666, /* VPSLLWYrm */ >+ 0x1667, /* VPSLLWYrr */ >+/* Table4529 */ >+ 0x163e, /* VPSLLDYrm */ >+ 0x163f, /* VPSLLDYrr */ >+/* Table4531 */ >+ 0x164c, /* VPSLLQYrm */ >+ 0x164d, /* VPSLLQYrr */ >+/* Table4533 */ >+ 0x15c3, /* VPMULUDQYrm */ >+ 0x15c4, /* VPMULUDQYrr */ >+/* Table4535 */ >+ 0x145c, /* VPMADDWDYrm */ >+ 0x145d, /* VPMADDWDYrr */ >+/* Table4537 */ >+ 0x15fd, /* VPSADBWYrm */ >+ 0x15fe, /* VPSADBWYrr */ >+/* Table4539 */ >+ 0x16bf, /* VPSUBBYrm */ >+ 0x16c0, /* VPSUBBYrr */ >+/* Table4541 */ >+ 0x16ed, /* VPSUBWYrm */ >+ 0x16ee, /* VPSUBWYrr */ >+/* Table4543 */ >+ 0x16c3, /* VPSUBDYrm */ >+ 0x16c4, /* VPSUBDYrr */ >+/* Table4545 */ >+ 0x16d0, /* VPSUBQYrm */ >+ 0x16d1, /* VPSUBQYrr */ >+/* Table4547 */ >+ 0x11ef, /* VPADDBYrm */ >+ 0x11f0, /* VPADDBYrr */ >+/* Table4549 */ >+ 0x121d, /* VPADDWYrm */ >+ 0x121e, /* VPADDWYrr */ >+/* Table4551 */ >+ 0x11f3, /* VPADDDYrm */ >+ 0x11f4, /* VPADDDYrr */ >+/* Table4553 */ >+ 0x0, /* */ >+ 0x46c, /* KANDQrr */ >+/* Table4555 */ >+ 0x0, /* */ >+ 0x46a, /* KANDNQrr */ >+/* Table4557 */ >+ 0x0, /* */ >+ 0x488, /* KORQrr */ >+/* Table4559 */ >+ 0x0, /* */ >+ 0x494, /* KXNORQrr */ >+/* Table4561 */ >+ 0x0, /* */ >+ 0x498, /* KXORQrr */ >+/* Table4563 */ >+ 0x0, /* */ >+ 0x467, /* KANDDrr */ >+/* Table4565 */ >+ 0x0, /* */ >+ 0x469, /* KANDNDrr */ >+/* Table4567 */ >+ 0x0, /* */ >+ 0x487, /* KORDrr */ >+/* Table4569 */ >+ 0x0, /* */ >+ 0x493, /* KXNORDrr */ >+/* Table4571 */ >+ 0x0, /* */ >+ 0x497, /* KXORDrr */ >+/* Table4573 */ >+ 0x1155, /* VMOVUPSZ128rm */ >+ 0x1158, /* VMOVUPSZ128rr */ >+/* Table4575 */ >+ 0x1153, /* VMOVUPSZ128mr */ >+ 0x0, /* */ >+/* Table4577 */ >+ 0x0, /* */ >+ 0x10d1, /* VMOVHLPSZrr */ >+/* Table4579 */ >+ 0x0, /* */ >+ 0x10d7, /* VMOVLHPSZrr */ >+/* Table4581 */ >+ 0xfca, /* VMOVAPSZ128rm */ >+ 0xfcd, /* VMOVAPSZ128rr */ >+/* Table4583 */ >+ 0xfc8, /* VMOVAPSZ128mr */ >+ 0x0, /* */ >+/* Table4585 */ >+ 0x10f1, /* VMOVNTPSZ128mr */ >+ 0x0, /* */ >+/* Table4587 */ >+ 0x17f4, /* VUCOMISSZrm */ >+ 0x17f5, /* VUCOMISSZrr */ >+/* Table4589 */ >+ 0xc2f, /* VCOMISSZrm */ >+ 0xc30, /* VCOMISSZrr */ >+/* Table4591 */ >+ 0x111e, /* VMOVSSZrm */ >+ 0x111f, /* VMOVSSZrr */ >+/* Table4593 */ >+ 0x111d, /* VMOVSSZmr */ >+ 0x1120, /* VMOVSSZrr_REV */ >+/* Table4595 */ >+ 0xc85, /* VCVTSI2SSZrm */ >+ 0xc86, /* VCVTSI2SSZrr */ >+/* Table4597 */ >+ 0xcbd, /* VCVTTSS2SIZrm */ >+ 0xcbe, /* VCVTTSS2SIZrr */ >+/* Table4599 */ >+ 0xc95, /* VCVTSS2SIZrm */ >+ 0xc96, /* VCVTSS2SIZrr */ >+/* Table4601 */ >+ 0x17ba, /* VSQRTSSZm */ >+ 0x17bc, /* VSQRTSSZr */ >+/* Table4603 */ >+ 0xbaa, /* VADDSSZrm */ >+ 0xbab, /* VADDSSZrr */ >+/* Table4605 */ >+ 0x11ad, /* VMULSSZrm */ >+ 0x11ae, /* VMULSSZrr */ >+/* Table4607 */ >+ 0xc8d, /* VCVTSS2SDZrm */ >+ 0xc8e, /* VCVTSS2SDZrr */ >+/* Table4609 */ >+ 0x17e2, /* VSUBSSZrm */ >+ 0x17e3, /* VSUBSSZrr */ >+/* Table4611 */ >+ 0xf8c, /* VMINSSZrm */ >+ 0xf8d, /* VMINSSZrr */ >+/* Table4613 */ >+ 0xcf2, /* VDIVSSZrm */ >+ 0xcf3, /* VDIVSSZrr */ >+/* Table4615 */ >+ 0xf57, /* VMAXSSZrm */ >+ 0xf58, /* VMAXSSZrr */ >+/* Table4617 */ >+ 0x1068, /* VMOVDQU32Z128rm */ >+ 0x106b, /* VMOVDQU32Z128rr */ >+/* Table4619 */ >+ 0xcc3, /* VCVTTSS2USIZrm */ >+ 0xcc4, /* VCVTTSS2USIZrr */ >+/* Table4621 */ >+ 0xc9b, /* VCVTSS2USIZrm */ >+ 0xc9c, /* VCVTSS2USIZrr */ >+/* Table4623 */ >+ 0xccc, /* VCVTUSI2SSZrm */ >+ 0xccd, /* VCVTUSI2SSZrr */ >+/* Table4625 */ >+ 0x1066, /* VMOVDQU32Z128mr */ >+ 0x0, /* */ >+/* Table4627 */ >+ 0xc23, /* VCMPSSZrm */ >+ 0xc25, /* VCMPSSZrr */ >+/* Table4629 */ >+ 0xc7f, /* VCVTSI2SDZrm */ >+ 0xc80, /* VCVTSI2SDZrr */ >+/* Table4631 */ >+ 0xcb1, /* VCVTTSD2SIZrm */ >+ 0xcb2, /* VCVTTSD2SIZrr */ >+/* Table4633 */ >+ 0xc71, /* VCVTSD2SIZrm */ >+ 0xc72, /* VCVTSD2SIZrr */ >+/* Table4635 */ >+ 0x10aa, /* VMOVDQU8Z128rm */ >+ 0x10ad, /* VMOVDQU8Z128rr */ >+/* Table4637 */ >+ 0xcb7, /* VCVTTSD2USIZrm */ >+ 0xcb8, /* VCVTTSD2USIZrr */ >+/* Table4639 */ >+ 0xc7b, /* VCVTSD2USIZrm */ >+ 0xc7c, /* VCVTSD2USIZrr */ >+/* Table4641 */ >+ 0xcca, /* VCVTUSI2SDZrm */ >+ 0xccb, /* VCVTUSI2SDZrr */ >+/* Table4643 */ >+ 0x10a8, /* VMOVDQU8Z128mr */ >+ 0x0, /* */ >+/* Table4645 */ >+ 0x12eb, /* VPCMPGTBZ128rm */ >+ 0x12ed, /* VPCMPGTBZ128rr */ >+/* Table4647 */ >+ 0x1327, /* VPCMPGTWZ128rm */ >+ 0x1329, /* VPCMPGTWZ128rr */ >+/* Table4649 */ >+ 0x12fb, /* VPCMPGTDZ128rm */ >+ 0x12ff, /* VPCMPGTDZ128rr */ >+/* Table4651 */ >+ 0xff3, /* VMOVDI2PDIZrm */ >+ 0xff4, /* VMOVDI2PDIZrr */ >+/* Table4653 */ >+ 0xffd, /* VMOVDQA32Z128rm */ >+ 0x1000, /* VMOVDQA32Z128rr */ >+/* Table4655 */ >+ 0x1297, /* VPCMPEQBZ128rm */ >+ 0x1299, /* VPCMPEQBZ128rr */ >+/* Table4657 */ >+ 0x12d3, /* VPCMPEQWZ128rm */ >+ 0x12d5, /* VPCMPEQWZ128rr */ >+/* Table4659 */ >+ 0x12a7, /* VPCMPEQDZ128rm */ >+ 0x12ab, /* VPCMPEQDZ128rr */ >+/* Table4661 */ >+ 0x10f5, /* VMOVPDI2DIZmr */ >+ 0x10f6, /* VMOVPDI2DIZrr */ >+/* Table4663 */ >+ 0xffb, /* VMOVDQA32Z128mr */ >+ 0x0, /* */ >+/* Table4665 */ >+ 0x10e7, /* VMOVNTDQZ128mr */ >+ 0x0, /* */ >+/* Table4667 */ >+ 0xc8b, /* VCVTSI642SSZrm */ >+ 0xc8c, /* VCVTSI642SSZrr */ >+/* Table4669 */ >+ 0xcb9, /* VCVTTSS2SI64Zrm */ >+ 0xcba, /* VCVTTSS2SI64Zrr */ >+/* Table4671 */ >+ 0xc91, /* VCVTSS2SI64Zrm */ >+ 0xc92, /* VCVTSS2SI64Zrr */ >+/* Table4673 */ >+ 0x1089, /* VMOVDQU64Z128rm */ >+ 0x108c, /* VMOVDQU64Z128rr */ >+/* Table4675 */ >+ 0xcc1, /* VCVTTSS2USI64Zrm */ >+ 0xcc2, /* VCVTTSS2USI64Zrr */ >+/* Table4677 */ >+ 0xc99, /* VCVTSS2USI64Zrm */ >+ 0xc9a, /* VCVTSS2USI64Zrr */ >+/* Table4679 */ >+ 0xcd0, /* VCVTUSI642SSZrm */ >+ 0xcd1, /* VCVTUSI642SSZrr */ >+/* Table4681 */ >+ 0x1178, /* VMOVZPQILo2PQIZrm */ >+ 0x1179, /* VMOVZPQILo2PQIZrr */ >+/* Table4683 */ >+ 0x1087, /* VMOVDQU64Z128mr */ >+ 0x0, /* */ >+/* Table4685 */ >+ 0x1101, /* VMOVSDZrm */ >+ 0x1102, /* VMOVSDZrr */ >+/* Table4687 */ >+ 0x1100, /* VMOVSDZmr */ >+ 0x1103, /* VMOVSDZrr_REV */ >+/* Table4689 */ >+ 0xc89, /* VCVTSI642SDZrm */ >+ 0xc8a, /* VCVTSI642SDZrr */ >+/* Table4691 */ >+ 0xcad, /* VCVTTSD2SI64Zrm */ >+ 0xcae, /* VCVTTSD2SI64Zrr */ >+/* Table4693 */ >+ 0xc6d, /* VCVTSD2SI64Zrm */ >+ 0xc6e, /* VCVTSD2SI64Zrr */ >+/* Table4695 */ >+ 0x17b3, /* VSQRTSDZm */ >+ 0x17b5, /* VSQRTSDZr */ >+/* Table4697 */ >+ 0xba4, /* VADDSDZrm */ >+ 0xba5, /* VADDSDZrr */ >+/* Table4699 */ >+ 0x11a7, /* VMULSDZrm */ >+ 0x11a8, /* VMULSDZrr */ >+/* Table4701 */ >+ 0xc75, /* VCVTSD2SSZrm */ >+ 0xc76, /* VCVTSD2SSZrr */ >+/* Table4703 */ >+ 0x17dc, /* VSUBSDZrm */ >+ 0x17dd, /* VSUBSDZrr */ >+/* Table4705 */ >+ 0xf86, /* VMINSDZrm */ >+ 0xf87, /* VMINSDZrr */ >+/* Table4707 */ >+ 0xcec, /* VDIVSDZrm */ >+ 0xced, /* VDIVSDZrr */ >+/* Table4709 */ >+ 0xf51, /* VMAXSDZrm */ >+ 0xf52, /* VMAXSDZrr */ >+/* Table4711 */ >+ 0x1047, /* VMOVDQU16Z128rm */ >+ 0x104a, /* VMOVDQU16Z128rr */ >+/* Table4713 */ >+ 0xcb5, /* VCVTTSD2USI64Zrm */ >+ 0xcb6, /* VCVTTSD2USI64Zrr */ >+/* Table4715 */ >+ 0xc79, /* VCVTSD2USI64Zrm */ >+ 0xc7a, /* VCVTSD2USI64Zrr */ >+/* Table4717 */ >+ 0xcce, /* VCVTUSI642SDZrm */ >+ 0xccf, /* VCVTUSI642SDZrr */ >+/* Table4719 */ >+ 0x1045, /* VMOVDQU16Z128mr */ >+ 0x0, /* */ >+/* Table4721 */ >+ 0xc1b, /* VCMPSDZrm */ >+ 0xc1d, /* VCMPSDZrr */ >+/* Table4723 */ >+ 0x112c, /* VMOVUPDZ128rm */ >+ 0x112f, /* VMOVUPDZ128rr */ >+/* Table4725 */ >+ 0x112a, /* VMOVUPDZ128mr */ >+ 0x0, /* */ >+/* Table4727 */ >+ 0xfa1, /* VMOVAPDZ128rm */ >+ 0xfa4, /* VMOVAPDZ128rr */ >+/* Table4729 */ >+ 0xf9f, /* VMOVAPDZ128mr */ >+ 0x0, /* */ >+/* Table4731 */ >+ 0x10ec, /* VMOVNTPDZ128mr */ >+ 0x0, /* */ >+/* Table4733 */ >+ 0x17f0, /* VUCOMISDZrm */ >+ 0x17f1, /* VUCOMISDZrr */ >+/* Table4735 */ >+ 0xc2b, /* VCOMISDZrm */ >+ 0xc2c, /* VCOMISDZrr */ >+/* Table4737 */ >+ 0x10fe, /* VMOVQI2PQIZrm */ >+ 0xf96, /* VMOV64toPQIZrr */ >+/* Table4739 */ >+ 0x101e, /* VMOVDQA64Z128rm */ >+ 0x1021, /* VMOVDQA64Z128rr */ >+/* Table4741 */ >+ 0x1109, /* VMOVSDto64Zmr */ >+ 0x10fc, /* VMOVPQIto64Zrr */ >+/* Table4743 */ >+ 0x101c, /* VMOVDQA64Z128mr */ >+ 0x0, /* */ >+/* Table4745 */ >+ 0x10fb, /* VMOVPQIto64Zmr */ >+ 0x0, /* */ >+/* Table4747 */ >+ 0x1160, /* VMOVUPSZ256rm */ >+ 0x1163, /* VMOVUPSZ256rr */ >+/* Table4749 */ >+ 0x115e, /* VMOVUPSZ256mr */ >+ 0x0, /* */ >+/* Table4751 */ >+ 0xfd5, /* VMOVAPSZ256rm */ >+ 0xfd8, /* VMOVAPSZ256rr */ >+/* Table4753 */ >+ 0xfd3, /* VMOVAPSZ256mr */ >+ 0x0, /* */ >+/* Table4755 */ >+ 0x10f2, /* VMOVNTPSZ256mr */ >+ 0x0, /* */ >+/* Table4757 */ >+ 0x1073, /* VMOVDQU32Z256rm */ >+ 0x1076, /* VMOVDQU32Z256rr */ >+/* Table4759 */ >+ 0x1071, /* VMOVDQU32Z256mr */ >+ 0x0, /* */ >+/* Table4761 */ >+ 0x10b5, /* VMOVDQU8Z256rm */ >+ 0x10b8, /* VMOVDQU8Z256rr */ >+/* Table4763 */ >+ 0x10b3, /* VMOVDQU8Z256mr */ >+ 0x0, /* */ >+/* Table4765 */ >+ 0x12ef, /* VPCMPGTBZ256rm */ >+ 0x12f1, /* VPCMPGTBZ256rr */ >+/* Table4767 */ >+ 0x132b, /* VPCMPGTWZ256rm */ >+ 0x132d, /* VPCMPGTWZ256rr */ >+/* Table4769 */ >+ 0x1301, /* VPCMPGTDZ256rm */ >+ 0x1305, /* VPCMPGTDZ256rr */ >+/* Table4771 */ >+ 0x1008, /* VMOVDQA32Z256rm */ >+ 0x100b, /* VMOVDQA32Z256rr */ >+/* Table4773 */ >+ 0x129b, /* VPCMPEQBZ256rm */ >+ 0x129d, /* VPCMPEQBZ256rr */ >+/* Table4775 */ >+ 0x12d7, /* VPCMPEQWZ256rm */ >+ 0x12d9, /* VPCMPEQWZ256rr */ >+/* Table4777 */ >+ 0x12ad, /* VPCMPEQDZ256rm */ >+ 0x12b1, /* VPCMPEQDZ256rr */ >+/* Table4779 */ >+ 0x1006, /* VMOVDQA32Z256mr */ >+ 0x0, /* */ >+/* Table4781 */ >+ 0x10e8, /* VMOVNTDQZ256mr */ >+ 0x0, /* */ >+/* Table4783 */ >+ 0x1094, /* VMOVDQU64Z256rm */ >+ 0x1097, /* VMOVDQU64Z256rr */ >+/* Table4785 */ >+ 0x1092, /* VMOVDQU64Z256mr */ >+ 0x0, /* */ >+/* Table4787 */ >+ 0x1052, /* VMOVDQU16Z256rm */ >+ 0x1055, /* VMOVDQU16Z256rr */ >+/* Table4789 */ >+ 0x1050, /* VMOVDQU16Z256mr */ >+ 0x0, /* */ >+/* Table4791 */ >+ 0x1137, /* VMOVUPDZ256rm */ >+ 0x113a, /* VMOVUPDZ256rr */ >+/* Table4793 */ >+ 0x1135, /* VMOVUPDZ256mr */ >+ 0x0, /* */ >+/* Table4795 */ >+ 0xfac, /* VMOVAPDZ256rm */ >+ 0xfaf, /* VMOVAPDZ256rr */ >+/* Table4797 */ >+ 0xfaa, /* VMOVAPDZ256mr */ >+ 0x0, /* */ >+/* Table4799 */ >+ 0x10ed, /* VMOVNTPDZ256mr */ >+ 0x0, /* */ >+/* Table4801 */ >+ 0x1029, /* VMOVDQA64Z256rm */ >+ 0x102c, /* VMOVDQA64Z256rr */ >+/* Table4803 */ >+ 0x1027, /* VMOVDQA64Z256mr */ >+ 0x0, /* */ >+/* Table4805 */ >+ 0x116b, /* VMOVUPSZrm */ >+ 0x116e, /* VMOVUPSZrr */ >+/* Table4807 */ >+ 0x1169, /* VMOVUPSZmr */ >+ 0x0, /* */ >+/* Table4809 */ >+ 0x180c, /* VUNPCKLPSZrm */ >+ 0x180d, /* VUNPCKLPSZrr */ >+/* Table4811 */ >+ 0x1800, /* VUNPCKHPSZrm */ >+ 0x1801, /* VUNPCKHPSZrr */ >+/* Table4813 */ >+ 0xfe0, /* VMOVAPSZrm */ >+ 0xfe3, /* VMOVAPSZrr */ >+/* Table4815 */ >+ 0xfde, /* VMOVAPSZmr */ >+ 0x0, /* */ >+/* Table4817 */ >+ 0x10f3, /* VMOVNTPSZmr */ >+ 0x0, /* */ >+/* Table4819 */ >+ 0x17af, /* VSQRTPSZrm */ >+ 0x17b0, /* VSQRTPSZrr */ >+/* Table4821 */ >+ 0xb99, /* VADDPSZrm */ >+ 0xb9f, /* VADDPSZrr */ >+/* Table4823 */ >+ 0x119c, /* VMULPSZrm */ >+ 0x11a2, /* VMULPSZrr */ >+/* Table4825 */ >+ 0xc60, /* VCVTPS2PDZrm */ >+ 0xc61, /* VCVTPS2PDZrr */ >+/* Table4827 */ >+ 0xc3b, /* VCVTDQ2PSZrm */ >+ 0xc3c, /* VCVTDQ2PSZrr */ >+/* Table4829 */ >+ 0x17d1, /* VSUBPSZrm */ >+ 0x17d7, /* VSUBPSZrr */ >+/* Table4831 */ >+ 0xf7b, /* VMINPSZrm */ >+ 0xf81, /* VMINPSZrr */ >+/* Table4833 */ >+ 0xce1, /* VDIVPSZrm */ >+ 0xce7, /* VDIVPSZrr */ >+/* Table4835 */ >+ 0xf46, /* VMAXPSZrm */ >+ 0xf4c, /* VMAXPSZrr */ >+/* Table4837 */ >+ 0xcab, /* VCVTTPS2UDQZrm */ >+ 0xcac, /* VCVTTPS2UDQZrr */ >+/* Table4839 */ >+ 0xc6a, /* VCVTPS2UDQZrm */ >+ 0xc6b, /* VCVTPS2UDQZrr */ >+/* Table4841 */ >+ 0xc12, /* VCMPPSZrmi */ >+ 0xc14, /* VCMPPSZrri */ >+/* Table4843 */ >+ 0x17a3, /* VSHUFPSZrmi */ >+ 0x17a4, /* VSHUFPSZrri */ >+/* Table4845 */ >+ 0x1115, /* VMOVSLDUPZrm */ >+ 0x1116, /* VMOVSLDUPZrr */ >+/* Table4847 */ >+ 0x110f, /* VMOVSHDUPZrm */ >+ 0x1110, /* VMOVSHDUPZrr */ >+/* Table4849 */ >+ 0xca7, /* VCVTTPS2DQZrm */ >+ 0xca8, /* VCVTTPS2DQZrr */ >+/* Table4851 */ >+ 0x107e, /* VMOVDQU32Zrm */ >+ 0x1081, /* VMOVDQU32Zrr */ >+/* Table4853 */ >+ 0xcc5, /* VCVTUDQ2PDZrm */ >+ 0xcc6, /* VCVTUDQ2PDZrr */ >+/* Table4855 */ >+ 0x107c, /* VMOVDQU32Zmr */ >+ 0x0, /* */ >+/* Table4857 */ >+ 0xc35, /* VCVTDQ2PDZrm */ >+ 0xc36, /* VCVTDQ2PDZrr */ >+/* Table4859 */ >+ 0x10c0, /* VMOVDQU8Zrm */ >+ 0x10c3, /* VMOVDQU8Zrr */ >+/* Table4861 */ >+ 0xcc7, /* VCVTUDQ2PSZrm */ >+ 0xcc8, /* VCVTUDQ2PSZrr */ >+/* Table4863 */ >+ 0x10be, /* VMOVDQU8Zmr */ >+ 0x0, /* */ >+/* Table4865 */ >+ 0x17a9, /* VSQRTPDZrm */ >+ 0x17aa, /* VSQRTPDZrr */ >+/* Table4867 */ >+ 0xc59, /* VCVTPS2DQZrm */ >+ 0xc5a, /* VCVTPS2DQZrr */ >+/* Table4869 */ >+ 0x1717, /* VPUNPCKLDQZrm */ >+ 0x1718, /* VPUNPCKLDQZrr */ >+/* Table4871 */ >+ 0x12f3, /* VPCMPGTBZrm */ >+ 0x12f5, /* VPCMPGTBZrr */ >+/* Table4873 */ >+ 0x132f, /* VPCMPGTWZrm */ >+ 0x1331, /* VPCMPGTWZrr */ >+/* Table4875 */ >+ 0x1307, /* VPCMPGTDZrm */ >+ 0x130b, /* VPCMPGTDZrr */ >+/* Table4877 */ >+ 0x1703, /* VPUNPCKHDQZrm */ >+ 0x1704, /* VPUNPCKHDQZrr */ >+/* Table4879 */ >+ 0x1013, /* VMOVDQA32Zrm */ >+ 0x1016, /* VMOVDQA32Zrr */ >+/* Table4881 */ >+ 0x1623, /* VPSHUFDZmi */ >+ 0x1624, /* VPSHUFDZri */ >+/* Table4883 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1694, /* VPSRLDZmi */ >+ 0x0, /* */ >+ 0x166e, /* VPSRADZmi */ >+ 0x0, /* */ >+ 0x1640, /* VPSLLDZmi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1696, /* VPSRLDZri */ >+ 0x0, /* */ >+ 0x1670, /* VPSRADZri */ >+ 0x0, /* */ >+ 0x1642, /* VPSLLDZri */ >+ 0x0, /* */ >+/* Table4899 */ >+ 0x129f, /* VPCMPEQBZrm */ >+ 0x12a1, /* VPCMPEQBZrr */ >+/* Table4901 */ >+ 0x12db, /* VPCMPEQWZrm */ >+ 0x12dd, /* VPCMPEQWZrr */ >+/* Table4903 */ >+ 0x12b3, /* VPCMPEQDZrm */ >+ 0x12b7, /* VPCMPEQDZrr */ >+/* Table4905 */ >+ 0x1011, /* VMOVDQA32Zmr */ >+ 0x0, /* */ >+/* Table4907 */ >+ 0x1698, /* VPSRLDZrm */ >+ 0x169a, /* VPSRLDZrr */ >+/* Table4909 */ >+ 0x1225, /* VPANDDZrm */ >+ 0x122b, /* VPANDDZrr */ >+/* Table4911 */ >+ 0x122e, /* VPANDNDZrm */ >+ 0x1234, /* VPANDNDZrr */ >+/* Table4913 */ >+ 0x1672, /* VPSRADZrm */ >+ 0x1674, /* VPSRADZrr */ >+/* Table4915 */ >+ 0x10e9, /* VMOVNTDQZmr */ >+ 0x0, /* */ >+/* Table4917 */ >+ 0x15d0, /* VPORDZrm */ >+ 0x15d6, /* VPORDZrr */ >+/* Table4919 */ >+ 0x1725, /* VPXORDZrm */ >+ 0x172b, /* VPXORDZrr */ >+/* Table4921 */ >+ 0x1644, /* VPSLLDZrm */ >+ 0x1646, /* VPSLLDZrr */ >+/* Table4923 */ >+ 0x16c5, /* VPSUBDZrm */ >+ 0x16cb, /* VPSUBDZrr */ >+/* Table4925 */ >+ 0x11f5, /* VPADDDZrm */ >+ 0x11fb, /* VPADDDZrr */ >+/* Table4927 */ >+ 0xca3, /* VCVTTPD2UDQZrm */ >+ 0xca4, /* VCVTTPD2UDQZrr */ >+/* Table4929 */ >+ 0xc4e, /* VCVTPD2UDQZrm */ >+ 0xc4f, /* VCVTPD2UDQZrr */ >+/* Table4931 */ >+ 0x109f, /* VMOVDQU64Zrm */ >+ 0x10a2, /* VMOVDQU64Zrr */ >+/* Table4933 */ >+ 0x109d, /* VMOVDQU64Zmr */ >+ 0x0, /* */ >+/* Table4935 */ >+ 0x105d, /* VMOVDQU16Zrm */ >+ 0x1060, /* VMOVDQU16Zrr */ >+/* Table4937 */ >+ 0x105b, /* VMOVDQU16Zmr */ >+ 0x0, /* */ >+/* Table4939 */ >+ 0xc43, /* VCVTPD2DQZrm */ >+ 0xc44, /* VCVTPD2DQZrr */ >+/* Table4941 */ >+ 0x1142, /* VMOVUPDZrm */ >+ 0x1145, /* VMOVUPDZrr */ >+/* Table4943 */ >+ 0x1140, /* VMOVUPDZmr */ >+ 0x0, /* */ >+/* Table4945 */ >+ 0xfef, /* VMOVDDUPZrm */ >+ 0xff0, /* VMOVDDUPZrr */ >+/* Table4947 */ >+ 0x1806, /* VUNPCKLPDZrm */ >+ 0x1807, /* VUNPCKLPDZrr */ >+/* Table4949 */ >+ 0x17fa, /* VUNPCKHPDZrm */ >+ 0x17fb, /* VUNPCKHPDZrr */ >+/* Table4951 */ >+ 0xfb7, /* VMOVAPDZrm */ >+ 0xfba, /* VMOVAPDZrr */ >+/* Table4953 */ >+ 0xfb5, /* VMOVAPDZmr */ >+ 0x0, /* */ >+/* Table4955 */ >+ 0x10ee, /* VMOVNTPDZmr */ >+ 0x0, /* */ >+/* Table4957 */ >+ 0xb8c, /* VADDPDZrm */ >+ 0xb92, /* VADDPDZrr */ >+/* Table4959 */ >+ 0x118f, /* VMULPDZrm */ >+ 0x1195, /* VMULPDZrr */ >+/* Table4961 */ >+ 0xc4a, /* VCVTPD2PSZrm */ >+ 0xc4b, /* VCVTPD2PSZrr */ >+/* Table4963 */ >+ 0x17c4, /* VSUBPDZrm */ >+ 0x17ca, /* VSUBPDZrr */ >+/* Table4965 */ >+ 0xf6e, /* VMINPDZrm */ >+ 0xf74, /* VMINPDZrr */ >+/* Table4967 */ >+ 0xcd4, /* VDIVPDZrm */ >+ 0xcda, /* VDIVPDZrr */ >+/* Table4969 */ >+ 0xf39, /* VMAXPDZrm */ >+ 0xf3f, /* VMAXPDZrr */ >+/* Table4971 */ >+ 0x171d, /* VPUNPCKLQDQZrm */ >+ 0x171e, /* VPUNPCKLQDQZrr */ >+/* Table4973 */ >+ 0x1709, /* VPUNPCKHQDQZrm */ >+ 0x170a, /* VPUNPCKHQDQZrr */ >+/* Table4975 */ >+ 0x1034, /* VMOVDQA64Zrm */ >+ 0x1037, /* VMOVDQA64Zrr */ >+/* Table4977 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1679, /* VPSRAQZmi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x167b, /* VPSRAQZri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table4993 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16a2, /* VPSRLQZmi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x164e, /* VPSLLQZmi */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16a4, /* VPSRLQZri */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1650, /* VPSLLQZri */ >+ 0x0, /* */ >+/* Table5009 */ >+ 0x1032, /* VMOVDQA64Zmr */ >+ 0x0, /* */ >+/* Table5011 */ >+ 0xc05, /* VCMPPDZrmi */ >+ 0xc07, /* VCMPPDZrri */ >+/* Table5013 */ >+ 0x179d, /* VSHUFPDZrmi */ >+ 0x179e, /* VSHUFPDZrri */ >+/* Table5015 */ >+ 0x16a6, /* VPSRLQZrm */ >+ 0x16a8, /* VPSRLQZrr */ >+/* Table5017 */ >+ 0x1202, /* VPADDQZrm */ >+ 0x1208, /* VPADDQZrr */ >+/* Table5019 */ >+ 0x1244, /* VPANDQZrm */ >+ 0x124a, /* VPANDQZrr */ >+/* Table5021 */ >+ 0x1237, /* VPANDNQZrm */ >+ 0x123d, /* VPANDNQZrr */ >+/* Table5023 */ >+ 0x167d, /* VPSRAQZrm */ >+ 0x167f, /* VPSRAQZrr */ >+/* Table5025 */ >+ 0xca0, /* VCVTTPD2DQZrm */ >+ 0xca1, /* VCVTTPD2DQZrr */ >+/* Table5027 */ >+ 0x15d9, /* VPORQZrm */ >+ 0x15df, /* VPORQZrr */ >+/* Table5029 */ >+ 0x172e, /* VPXORQZrm */ >+ 0x1734, /* VPXORQZrr */ >+/* Table5031 */ >+ 0x1652, /* VPSLLQZrm */ >+ 0x1654, /* VPSLLQZrr */ >+/* Table5033 */ >+ 0x15c5, /* VPMULUDQZrm */ >+ 0x15cb, /* VPMULUDQZrr */ >+/* Table5035 */ >+ 0x16d2, /* VPSUBQZrm */ >+ 0x16d8, /* VPSUBQZrr */ >+/* Table5037 */ >+ 0x1156, /* VMOVUPSZ128rmk */ >+ 0x115a, /* VMOVUPSZ128rrk */ >+/* Table5039 */ >+ 0x1154, /* VMOVUPSZ128mrk */ >+ 0x0, /* */ >+/* Table5041 */ >+ 0xfcb, /* VMOVAPSZ128rmk */ >+ 0xfcf, /* VMOVAPSZ128rrk */ >+/* Table5043 */ >+ 0xfc9, /* VMOVAPSZ128mrk */ >+ 0x0, /* */ >+/* Table5045 */ >+ 0x0, /* */ >+ 0x1121, /* VMOVSSZrrk */ >+/* Table5047 */ >+ 0x1069, /* VMOVDQU32Z128rmk */ >+ 0x106d, /* VMOVDQU32Z128rrk */ >+/* Table5049 */ >+ 0x1067, /* VMOVDQU32Z128mrk */ >+ 0x0, /* */ >+/* Table5051 */ >+ 0x10ab, /* VMOVDQU8Z128rmk */ >+ 0x10af, /* VMOVDQU8Z128rrk */ >+/* Table5053 */ >+ 0x10a9, /* VMOVDQU8Z128mrk */ >+ 0x0, /* */ >+/* Table5055 */ >+ 0x12ec, /* VPCMPGTBZ128rmk */ >+ 0x12ee, /* VPCMPGTBZ128rrk */ >+/* Table5057 */ >+ 0x1328, /* VPCMPGTWZ128rmk */ >+ 0x132a, /* VPCMPGTWZ128rrk */ >+/* Table5059 */ >+ 0x12fe, /* VPCMPGTDZ128rmk */ >+ 0x1300, /* VPCMPGTDZ128rrk */ >+/* Table5061 */ >+ 0xffe, /* VMOVDQA32Z128rmk */ >+ 0x1002, /* VMOVDQA32Z128rrk */ >+/* Table5063 */ >+ 0x1298, /* VPCMPEQBZ128rmk */ >+ 0x129a, /* VPCMPEQBZ128rrk */ >+/* Table5065 */ >+ 0x12d4, /* VPCMPEQWZ128rmk */ >+ 0x12d6, /* VPCMPEQWZ128rrk */ >+/* Table5067 */ >+ 0x12aa, /* VPCMPEQDZ128rmk */ >+ 0x12ac, /* VPCMPEQDZ128rrk */ >+/* Table5069 */ >+ 0xffc, /* VMOVDQA32Z128mrk */ >+ 0x0, /* */ >+/* Table5071 */ >+ 0x108a, /* VMOVDQU64Z128rmk */ >+ 0x108e, /* VMOVDQU64Z128rrk */ >+/* Table5073 */ >+ 0x1088, /* VMOVDQU64Z128mrk */ >+ 0x0, /* */ >+/* Table5075 */ >+ 0x0, /* */ >+ 0x1104, /* VMOVSDZrrk */ >+/* Table5077 */ >+ 0x1048, /* VMOVDQU16Z128rmk */ >+ 0x104c, /* VMOVDQU16Z128rrk */ >+/* Table5079 */ >+ 0x1046, /* VMOVDQU16Z128mrk */ >+ 0x0, /* */ >+/* Table5081 */ >+ 0x112d, /* VMOVUPDZ128rmk */ >+ 0x1131, /* VMOVUPDZ128rrk */ >+/* Table5083 */ >+ 0x112b, /* VMOVUPDZ128mrk */ >+ 0x0, /* */ >+/* Table5085 */ >+ 0xfa2, /* VMOVAPDZ128rmk */ >+ 0xfa6, /* VMOVAPDZ128rrk */ >+/* Table5087 */ >+ 0xfa0, /* VMOVAPDZ128mrk */ >+ 0x0, /* */ >+/* Table5089 */ >+ 0x101f, /* VMOVDQA64Z128rmk */ >+ 0x1023, /* VMOVDQA64Z128rrk */ >+/* Table5091 */ >+ 0x101d, /* VMOVDQA64Z128mrk */ >+ 0x0, /* */ >+/* Table5093 */ >+ 0x1161, /* VMOVUPSZ256rmk */ >+ 0x1165, /* VMOVUPSZ256rrk */ >+/* Table5095 */ >+ 0x115f, /* VMOVUPSZ256mrk */ >+ 0x0, /* */ >+/* Table5097 */ >+ 0xfd6, /* VMOVAPSZ256rmk */ >+ 0xfda, /* VMOVAPSZ256rrk */ >+/* Table5099 */ >+ 0xfd4, /* VMOVAPSZ256mrk */ >+ 0x0, /* */ >+/* Table5101 */ >+ 0x1074, /* VMOVDQU32Z256rmk */ >+ 0x1078, /* VMOVDQU32Z256rrk */ >+/* Table5103 */ >+ 0x1072, /* VMOVDQU32Z256mrk */ >+ 0x0, /* */ >+/* Table5105 */ >+ 0x10b6, /* VMOVDQU8Z256rmk */ >+ 0x10ba, /* VMOVDQU8Z256rrk */ >+/* Table5107 */ >+ 0x10b4, /* VMOVDQU8Z256mrk */ >+ 0x0, /* */ >+/* Table5109 */ >+ 0x12f0, /* VPCMPGTBZ256rmk */ >+ 0x12f2, /* VPCMPGTBZ256rrk */ >+/* Table5111 */ >+ 0x132c, /* VPCMPGTWZ256rmk */ >+ 0x132e, /* VPCMPGTWZ256rrk */ >+/* Table5113 */ >+ 0x1304, /* VPCMPGTDZ256rmk */ >+ 0x1306, /* VPCMPGTDZ256rrk */ >+/* Table5115 */ >+ 0x1009, /* VMOVDQA32Z256rmk */ >+ 0x100d, /* VMOVDQA32Z256rrk */ >+/* Table5117 */ >+ 0x129c, /* VPCMPEQBZ256rmk */ >+ 0x129e, /* VPCMPEQBZ256rrk */ >+/* Table5119 */ >+ 0x12d8, /* VPCMPEQWZ256rmk */ >+ 0x12da, /* VPCMPEQWZ256rrk */ >+/* Table5121 */ >+ 0x12b0, /* VPCMPEQDZ256rmk */ >+ 0x12b2, /* VPCMPEQDZ256rrk */ >+/* Table5123 */ >+ 0x1007, /* VMOVDQA32Z256mrk */ >+ 0x0, /* */ >+/* Table5125 */ >+ 0x1095, /* VMOVDQU64Z256rmk */ >+ 0x1099, /* VMOVDQU64Z256rrk */ >+/* Table5127 */ >+ 0x1093, /* VMOVDQU64Z256mrk */ >+ 0x0, /* */ >+/* Table5129 */ >+ 0x1053, /* VMOVDQU16Z256rmk */ >+ 0x1057, /* VMOVDQU16Z256rrk */ >+/* Table5131 */ >+ 0x1051, /* VMOVDQU16Z256mrk */ >+ 0x0, /* */ >+/* Table5133 */ >+ 0x1138, /* VMOVUPDZ256rmk */ >+ 0x113c, /* VMOVUPDZ256rrk */ >+/* Table5135 */ >+ 0x1136, /* VMOVUPDZ256mrk */ >+ 0x0, /* */ >+/* Table5137 */ >+ 0xfad, /* VMOVAPDZ256rmk */ >+ 0xfb1, /* VMOVAPDZ256rrk */ >+/* Table5139 */ >+ 0xfab, /* VMOVAPDZ256mrk */ >+ 0x0, /* */ >+/* Table5141 */ >+ 0x102a, /* VMOVDQA64Z256rmk */ >+ 0x102e, /* VMOVDQA64Z256rrk */ >+/* Table5143 */ >+ 0x1028, /* VMOVDQA64Z256mrk */ >+ 0x0, /* */ >+/* Table5145 */ >+ 0x116c, /* VMOVUPSZrmk */ >+ 0x1170, /* VMOVUPSZrrk */ >+/* Table5147 */ >+ 0x116a, /* VMOVUPSZmrk */ >+ 0x0, /* */ >+/* Table5149 */ >+ 0xfe1, /* VMOVAPSZrmk */ >+ 0xfe5, /* VMOVAPSZrrk */ >+/* Table5151 */ >+ 0xfdf, /* VMOVAPSZmrk */ >+ 0x0, /* */ >+/* Table5153 */ >+ 0xb9d, /* VADDPSZrmk */ >+ 0xba0, /* VADDPSZrrk */ >+/* Table5155 */ >+ 0x11a0, /* VMULPSZrmk */ >+ 0x11a3, /* VMULPSZrrk */ >+/* Table5157 */ >+ 0x17d5, /* VSUBPSZrmk */ >+ 0x17d8, /* VSUBPSZrrk */ >+/* Table5159 */ >+ 0xf7f, /* VMINPSZrmk */ >+ 0xf82, /* VMINPSZrrk */ >+/* Table5161 */ >+ 0xce5, /* VDIVPSZrmk */ >+ 0xce8, /* VDIVPSZrrk */ >+/* Table5163 */ >+ 0xf4a, /* VMAXPSZrmk */ >+ 0xf4d, /* VMAXPSZrrk */ >+/* Table5165 */ >+ 0x107f, /* VMOVDQU32Zrmk */ >+ 0x1083, /* VMOVDQU32Zrrk */ >+/* Table5167 */ >+ 0x107d, /* VMOVDQU32Zmrk */ >+ 0x0, /* */ >+/* Table5169 */ >+ 0x10c1, /* VMOVDQU8Zrmk */ >+ 0x10c5, /* VMOVDQU8Zrrk */ >+/* Table5171 */ >+ 0x10bf, /* VMOVDQU8Zmrk */ >+ 0x0, /* */ >+/* Table5173 */ >+ 0x12f4, /* VPCMPGTBZrmk */ >+ 0x12f6, /* VPCMPGTBZrrk */ >+/* Table5175 */ >+ 0x1330, /* VPCMPGTWZrmk */ >+ 0x1332, /* VPCMPGTWZrrk */ >+/* Table5177 */ >+ 0x130a, /* VPCMPGTDZrmk */ >+ 0x130c, /* VPCMPGTDZrrk */ >+/* Table5179 */ >+ 0x1014, /* VMOVDQA32Zrmk */ >+ 0x1018, /* VMOVDQA32Zrrk */ >+/* Table5181 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1695, /* VPSRLDZmik */ >+ 0x0, /* */ >+ 0x166f, /* VPSRADZmik */ >+ 0x0, /* */ >+ 0x1641, /* VPSLLDZmik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1697, /* VPSRLDZrik */ >+ 0x0, /* */ >+ 0x1671, /* VPSRADZrik */ >+ 0x0, /* */ >+ 0x1643, /* VPSLLDZrik */ >+ 0x0, /* */ >+/* Table5197 */ >+ 0x12a0, /* VPCMPEQBZrmk */ >+ 0x12a2, /* VPCMPEQBZrrk */ >+/* Table5199 */ >+ 0x12dc, /* VPCMPEQWZrmk */ >+ 0x12de, /* VPCMPEQWZrrk */ >+/* Table5201 */ >+ 0x12b6, /* VPCMPEQDZrmk */ >+ 0x12b8, /* VPCMPEQDZrrk */ >+/* Table5203 */ >+ 0x1012, /* VMOVDQA32Zmrk */ >+ 0x0, /* */ >+/* Table5205 */ >+ 0x1699, /* VPSRLDZrmk */ >+ 0x169b, /* VPSRLDZrrk */ >+/* Table5207 */ >+ 0x1229, /* VPANDDZrmk */ >+ 0x122c, /* VPANDDZrrk */ >+/* Table5209 */ >+ 0x1232, /* VPANDNDZrmk */ >+ 0x1235, /* VPANDNDZrrk */ >+/* Table5211 */ >+ 0x1673, /* VPSRADZrmk */ >+ 0x1675, /* VPSRADZrrk */ >+/* Table5213 */ >+ 0x15d4, /* VPORDZrmk */ >+ 0x15d7, /* VPORDZrrk */ >+/* Table5215 */ >+ 0x1729, /* VPXORDZrmk */ >+ 0x172c, /* VPXORDZrrk */ >+/* Table5217 */ >+ 0x1645, /* VPSLLDZrmk */ >+ 0x1647, /* VPSLLDZrrk */ >+/* Table5219 */ >+ 0x16c9, /* VPSUBDZrmk */ >+ 0x16cc, /* VPSUBDZrrk */ >+/* Table5221 */ >+ 0x11f9, /* VPADDDZrmk */ >+ 0x11fc, /* VPADDDZrrk */ >+/* Table5223 */ >+ 0x10a0, /* VMOVDQU64Zrmk */ >+ 0x10a4, /* VMOVDQU64Zrrk */ >+/* Table5225 */ >+ 0x109e, /* VMOVDQU64Zmrk */ >+ 0x0, /* */ >+/* Table5227 */ >+ 0x105e, /* VMOVDQU16Zrmk */ >+ 0x1062, /* VMOVDQU16Zrrk */ >+/* Table5229 */ >+ 0x105c, /* VMOVDQU16Zmrk */ >+ 0x0, /* */ >+/* Table5231 */ >+ 0x1143, /* VMOVUPDZrmk */ >+ 0x1147, /* VMOVUPDZrrk */ >+/* Table5233 */ >+ 0x1141, /* VMOVUPDZmrk */ >+ 0x0, /* */ >+/* Table5235 */ >+ 0xfb8, /* VMOVAPDZrmk */ >+ 0xfbc, /* VMOVAPDZrrk */ >+/* Table5237 */ >+ 0xfb6, /* VMOVAPDZmrk */ >+ 0x0, /* */ >+/* Table5239 */ >+ 0xb90, /* VADDPDZrmk */ >+ 0xb93, /* VADDPDZrrk */ >+/* Table5241 */ >+ 0x1193, /* VMULPDZrmk */ >+ 0x1196, /* VMULPDZrrk */ >+/* Table5243 */ >+ 0x17c8, /* VSUBPDZrmk */ >+ 0x17cb, /* VSUBPDZrrk */ >+/* Table5245 */ >+ 0xf72, /* VMINPDZrmk */ >+ 0xf75, /* VMINPDZrrk */ >+/* Table5247 */ >+ 0xcd8, /* VDIVPDZrmk */ >+ 0xcdb, /* VDIVPDZrrk */ >+/* Table5249 */ >+ 0xf3d, /* VMAXPDZrmk */ >+ 0xf40, /* VMAXPDZrrk */ >+/* Table5251 */ >+ 0x1035, /* VMOVDQA64Zrmk */ >+ 0x1039, /* VMOVDQA64Zrrk */ >+/* Table5253 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x167a, /* VPSRAQZmik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x167c, /* VPSRAQZrik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table5269 */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16a3, /* VPSRLQZmik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x164f, /* VPSLLQZmik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x16a5, /* VPSRLQZrik */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1651, /* VPSLLQZrik */ >+ 0x0, /* */ >+/* Table5285 */ >+ 0x1033, /* VMOVDQA64Zmrk */ >+ 0x0, /* */ >+/* Table5287 */ >+ 0x16a7, /* VPSRLQZrmk */ >+ 0x16a9, /* VPSRLQZrrk */ >+/* Table5289 */ >+ 0x1206, /* VPADDQZrmk */ >+ 0x1209, /* VPADDQZrrk */ >+/* Table5291 */ >+ 0x1248, /* VPANDQZrmk */ >+ 0x124b, /* VPANDQZrrk */ >+/* Table5293 */ >+ 0x123b, /* VPANDNQZrmk */ >+ 0x123e, /* VPANDNQZrrk */ >+/* Table5295 */ >+ 0x167e, /* VPSRAQZrmk */ >+ 0x1680, /* VPSRAQZrrk */ >+/* Table5297 */ >+ 0x15dd, /* VPORQZrmk */ >+ 0x15e0, /* VPORQZrrk */ >+/* Table5299 */ >+ 0x1732, /* VPXORQZrmk */ >+ 0x1735, /* VPXORQZrrk */ >+/* Table5301 */ >+ 0x1653, /* VPSLLQZrmk */ >+ 0x1655, /* VPSLLQZrrk */ >+/* Table5303 */ >+ 0x15c9, /* VPMULUDQZrmk */ >+ 0x15cc, /* VPMULUDQZrrk */ >+/* Table5305 */ >+ 0x16d6, /* VPSUBQZrmk */ >+ 0x16d9, /* VPSUBQZrrk */ >+/* Table5307 */ >+ 0x12fc, /* VPCMPGTDZ128rmb */ >+ 0x0, /* */ >+/* Table5309 */ >+ 0x12a8, /* VPCMPEQDZ128rmb */ >+ 0x0, /* */ >+/* Table5311 */ >+ 0x1302, /* VPCMPGTDZ256rmb */ >+ 0x0, /* */ >+/* Table5313 */ >+ 0x12ae, /* VPCMPEQDZ256rmb */ >+ 0x0, /* */ >+/* Table5315 */ >+ 0xb9a, /* VADDPSZrmb */ >+ 0x0, /* */ >+/* Table5317 */ >+ 0x119d, /* VMULPSZrmb */ >+ 0x0, /* */ >+/* Table5319 */ >+ 0x0, /* */ >+ 0xc3d, /* VCVTDQ2PSZrrb */ >+/* Table5321 */ >+ 0x17d2, /* VSUBPSZrmb */ >+ 0x0, /* */ >+/* Table5323 */ >+ 0xf7c, /* VMINPSZrmb */ >+ 0x0, /* */ >+/* Table5325 */ >+ 0xce2, /* VDIVPSZrmb */ >+ 0x0, /* */ >+/* Table5327 */ >+ 0xf47, /* VMAXPSZrmb */ >+ 0x0, /* */ >+/* Table5329 */ >+ 0x0, /* */ >+ 0xc6c, /* VCVTPS2UDQZrrb */ >+/* Table5331 */ >+ 0x0, /* */ >+ 0xc16, /* VCMPPSZrrib */ >+/* Table5333 */ >+ 0x0, /* */ >+ 0xcc9, /* VCVTUDQ2PSZrrb */ >+/* Table5335 */ >+ 0x0, /* */ >+ 0xc5b, /* VCVTPS2DQZrrb */ >+/* Table5337 */ >+ 0x1308, /* VPCMPGTDZrmb */ >+ 0x0, /* */ >+/* Table5339 */ >+ 0x12b4, /* VPCMPEQDZrmb */ >+ 0x0, /* */ >+/* Table5341 */ >+ 0x1226, /* VPANDDZrmb */ >+ 0x0, /* */ >+/* Table5343 */ >+ 0x122f, /* VPANDNDZrmb */ >+ 0x0, /* */ >+/* Table5345 */ >+ 0x15d1, /* VPORDZrmb */ >+ 0x0, /* */ >+/* Table5347 */ >+ 0x1726, /* VPXORDZrmb */ >+ 0x0, /* */ >+/* Table5349 */ >+ 0x16c6, /* VPSUBDZrmb */ >+ 0x0, /* */ >+/* Table5351 */ >+ 0x11f6, /* VPADDDZrmb */ >+ 0x0, /* */ >+/* Table5353 */ >+ 0x0, /* */ >+ 0xc50, /* VCVTPD2UDQZrrb */ >+/* Table5355 */ >+ 0x0, /* */ >+ 0xc45, /* VCVTPD2DQZrrb */ >+/* Table5357 */ >+ 0xb8d, /* VADDPDZrmb */ >+ 0x0, /* */ >+/* Table5359 */ >+ 0x1190, /* VMULPDZrmb */ >+ 0x0, /* */ >+/* Table5361 */ >+ 0x0, /* */ >+ 0xc4c, /* VCVTPD2PSZrrb */ >+/* Table5363 */ >+ 0x17c5, /* VSUBPDZrmb */ >+ 0x0, /* */ >+/* Table5365 */ >+ 0xf6f, /* VMINPDZrmb */ >+ 0x0, /* */ >+/* Table5367 */ >+ 0xcd5, /* VDIVPDZrmb */ >+ 0x0, /* */ >+/* Table5369 */ >+ 0xf3a, /* VMAXPDZrmb */ >+ 0x0, /* */ >+/* Table5371 */ >+ 0x0, /* */ >+ 0xc09, /* VCMPPDZrrib */ >+/* Table5373 */ >+ 0x1203, /* VPADDQZrmb */ >+ 0x0, /* */ >+/* Table5375 */ >+ 0x1245, /* VPANDQZrmb */ >+ 0x0, /* */ >+/* Table5377 */ >+ 0x1238, /* VPANDNQZrmb */ >+ 0x0, /* */ >+/* Table5379 */ >+ 0x15da, /* VPORQZrmb */ >+ 0x0, /* */ >+/* Table5381 */ >+ 0x172f, /* VPXORQZrmb */ >+ 0x0, /* */ >+/* Table5383 */ >+ 0x15c6, /* VPMULUDQZrmb */ >+ 0x0, /* */ >+/* Table5385 */ >+ 0x16d3, /* VPSUBQZrmb */ >+ 0x0, /* */ >+/* Table5387 */ >+ 0x12fd, /* VPCMPGTDZ128rmbk */ >+ 0x0, /* */ >+/* Table5389 */ >+ 0x12a9, /* VPCMPEQDZ128rmbk */ >+ 0x0, /* */ >+/* Table5391 */ >+ 0x1303, /* VPCMPGTDZ256rmbk */ >+ 0x0, /* */ >+/* Table5393 */ >+ 0x12af, /* VPCMPEQDZ256rmbk */ >+ 0x0, /* */ >+/* Table5395 */ >+ 0xb9b, /* VADDPSZrmbk */ >+ 0x0, /* */ >+/* Table5397 */ >+ 0x119e, /* VMULPSZrmbk */ >+ 0x0, /* */ >+/* Table5399 */ >+ 0x17d3, /* VSUBPSZrmbk */ >+ 0x0, /* */ >+/* Table5401 */ >+ 0xf7d, /* VMINPSZrmbk */ >+ 0x0, /* */ >+/* Table5403 */ >+ 0xce3, /* VDIVPSZrmbk */ >+ 0x0, /* */ >+/* Table5405 */ >+ 0xf48, /* VMAXPSZrmbk */ >+ 0x0, /* */ >+/* Table5407 */ >+ 0x1309, /* VPCMPGTDZrmbk */ >+ 0x0, /* */ >+/* Table5409 */ >+ 0x12b5, /* VPCMPEQDZrmbk */ >+ 0x0, /* */ >+/* Table5411 */ >+ 0x1227, /* VPANDDZrmbk */ >+ 0x0, /* */ >+/* Table5413 */ >+ 0x1230, /* VPANDNDZrmbk */ >+ 0x0, /* */ >+/* Table5415 */ >+ 0x15d2, /* VPORDZrmbk */ >+ 0x0, /* */ >+/* Table5417 */ >+ 0x1727, /* VPXORDZrmbk */ >+ 0x0, /* */ >+/* Table5419 */ >+ 0x16c7, /* VPSUBDZrmbk */ >+ 0x0, /* */ >+/* Table5421 */ >+ 0x11f7, /* VPADDDZrmbk */ >+ 0x0, /* */ >+/* Table5423 */ >+ 0xb8e, /* VADDPDZrmbk */ >+ 0x0, /* */ >+/* Table5425 */ >+ 0x1191, /* VMULPDZrmbk */ >+ 0x0, /* */ >+/* Table5427 */ >+ 0x17c6, /* VSUBPDZrmbk */ >+ 0x0, /* */ >+/* Table5429 */ >+ 0xf70, /* VMINPDZrmbk */ >+ 0x0, /* */ >+/* Table5431 */ >+ 0xcd6, /* VDIVPDZrmbk */ >+ 0x0, /* */ >+/* Table5433 */ >+ 0xf3b, /* VMAXPDZrmbk */ >+ 0x0, /* */ >+/* Table5435 */ >+ 0x1204, /* VPADDQZrmbk */ >+ 0x0, /* */ >+/* Table5437 */ >+ 0x1246, /* VPANDQZrmbk */ >+ 0x0, /* */ >+/* Table5439 */ >+ 0x1239, /* VPANDNQZrmbk */ >+ 0x0, /* */ >+/* Table5441 */ >+ 0x15db, /* VPORQZrmbk */ >+ 0x0, /* */ >+/* Table5443 */ >+ 0x1730, /* VPXORQZrmbk */ >+ 0x0, /* */ >+/* Table5445 */ >+ 0x15c7, /* VPMULUDQZrmbk */ >+ 0x0, /* */ >+/* Table5447 */ >+ 0x16d4, /* VPSUBQZrmbk */ >+ 0x0, /* */ >+/* Table5449 */ >+ 0xb9c, /* VADDPSZrmbkz */ >+ 0x0, /* */ >+/* Table5451 */ >+ 0x119f, /* VMULPSZrmbkz */ >+ 0x0, /* */ >+/* Table5453 */ >+ 0x17d4, /* VSUBPSZrmbkz */ >+ 0x0, /* */ >+/* Table5455 */ >+ 0xf7e, /* VMINPSZrmbkz */ >+ 0x0, /* */ >+/* Table5457 */ >+ 0xce4, /* VDIVPSZrmbkz */ >+ 0x0, /* */ >+/* Table5459 */ >+ 0xf49, /* VMAXPSZrmbkz */ >+ 0x0, /* */ >+/* Table5461 */ >+ 0x1228, /* VPANDDZrmbkz */ >+ 0x0, /* */ >+/* Table5463 */ >+ 0x1231, /* VPANDNDZrmbkz */ >+ 0x0, /* */ >+/* Table5465 */ >+ 0x15d3, /* VPORDZrmbkz */ >+ 0x0, /* */ >+/* Table5467 */ >+ 0x1728, /* VPXORDZrmbkz */ >+ 0x0, /* */ >+/* Table5469 */ >+ 0x16c8, /* VPSUBDZrmbkz */ >+ 0x0, /* */ >+/* Table5471 */ >+ 0x11f8, /* VPADDDZrmbkz */ >+ 0x0, /* */ >+/* Table5473 */ >+ 0xb8f, /* VADDPDZrmbkz */ >+ 0x0, /* */ >+/* Table5475 */ >+ 0x1192, /* VMULPDZrmbkz */ >+ 0x0, /* */ >+/* Table5477 */ >+ 0x17c7, /* VSUBPDZrmbkz */ >+ 0x0, /* */ >+/* Table5479 */ >+ 0xf71, /* VMINPDZrmbkz */ >+ 0x0, /* */ >+/* Table5481 */ >+ 0xcd7, /* VDIVPDZrmbkz */ >+ 0x0, /* */ >+/* Table5483 */ >+ 0xf3c, /* VMAXPDZrmbkz */ >+ 0x0, /* */ >+/* Table5485 */ >+ 0x1205, /* VPADDQZrmbkz */ >+ 0x0, /* */ >+/* Table5487 */ >+ 0x1247, /* VPANDQZrmbkz */ >+ 0x0, /* */ >+/* Table5489 */ >+ 0x123a, /* VPANDNQZrmbkz */ >+ 0x0, /* */ >+/* Table5491 */ >+ 0x15dc, /* VPORQZrmbkz */ >+ 0x0, /* */ >+/* Table5493 */ >+ 0x1731, /* VPXORQZrmbkz */ >+ 0x0, /* */ >+/* Table5495 */ >+ 0x15c8, /* VPMULUDQZrmbkz */ >+ 0x0, /* */ >+/* Table5497 */ >+ 0x16d5, /* VPSUBQZrmbkz */ >+ 0x0, /* */ >+/* Table5499 */ >+ 0x1157, /* VMOVUPSZ128rmkz */ >+ 0x115c, /* VMOVUPSZ128rrkz */ >+/* Table5501 */ >+ 0xfcc, /* VMOVAPSZ128rmkz */ >+ 0xfd1, /* VMOVAPSZ128rrkz */ >+/* Table5503 */ >+ 0x106a, /* VMOVDQU32Z128rmkz */ >+ 0x106f, /* VMOVDQU32Z128rrkz */ >+/* Table5505 */ >+ 0x10ac, /* VMOVDQU8Z128rmkz */ >+ 0x10b1, /* VMOVDQU8Z128rrkz */ >+/* Table5507 */ >+ 0xfff, /* VMOVDQA32Z128rmkz */ >+ 0x1004, /* VMOVDQA32Z128rrkz */ >+/* Table5509 */ >+ 0x108b, /* VMOVDQU64Z128rmkz */ >+ 0x1090, /* VMOVDQU64Z128rrkz */ >+/* Table5511 */ >+ 0x1049, /* VMOVDQU16Z128rmkz */ >+ 0x104e, /* VMOVDQU16Z128rrkz */ >+/* Table5513 */ >+ 0x112e, /* VMOVUPDZ128rmkz */ >+ 0x1133, /* VMOVUPDZ128rrkz */ >+/* Table5515 */ >+ 0xfa3, /* VMOVAPDZ128rmkz */ >+ 0xfa8, /* VMOVAPDZ128rrkz */ >+/* Table5517 */ >+ 0x1020, /* VMOVDQA64Z128rmkz */ >+ 0x1025, /* VMOVDQA64Z128rrkz */ >+/* Table5519 */ >+ 0x1162, /* VMOVUPSZ256rmkz */ >+ 0x1167, /* VMOVUPSZ256rrkz */ >+/* Table5521 */ >+ 0xfd7, /* VMOVAPSZ256rmkz */ >+ 0xfdc, /* VMOVAPSZ256rrkz */ >+/* Table5523 */ >+ 0x1075, /* VMOVDQU32Z256rmkz */ >+ 0x107a, /* VMOVDQU32Z256rrkz */ >+/* Table5525 */ >+ 0x10b7, /* VMOVDQU8Z256rmkz */ >+ 0x10bc, /* VMOVDQU8Z256rrkz */ >+/* Table5527 */ >+ 0x100a, /* VMOVDQA32Z256rmkz */ >+ 0x100f, /* VMOVDQA32Z256rrkz */ >+/* Table5529 */ >+ 0x1096, /* VMOVDQU64Z256rmkz */ >+ 0x109b, /* VMOVDQU64Z256rrkz */ >+/* Table5531 */ >+ 0x1054, /* VMOVDQU16Z256rmkz */ >+ 0x1059, /* VMOVDQU16Z256rrkz */ >+/* Table5533 */ >+ 0x1139, /* VMOVUPDZ256rmkz */ >+ 0x113e, /* VMOVUPDZ256rrkz */ >+/* Table5535 */ >+ 0xfae, /* VMOVAPDZ256rmkz */ >+ 0xfb3, /* VMOVAPDZ256rrkz */ >+/* Table5537 */ >+ 0x102b, /* VMOVDQA64Z256rmkz */ >+ 0x1030, /* VMOVDQA64Z256rrkz */ >+/* Table5539 */ >+ 0x116d, /* VMOVUPSZrmkz */ >+ 0x1172, /* VMOVUPSZrrkz */ >+/* Table5541 */ >+ 0xfe2, /* VMOVAPSZrmkz */ >+ 0xfe7, /* VMOVAPSZrrkz */ >+/* Table5543 */ >+ 0xb9e, /* VADDPSZrmkz */ >+ 0xba1, /* VADDPSZrrkz */ >+/* Table5545 */ >+ 0x11a1, /* VMULPSZrmkz */ >+ 0x11a4, /* VMULPSZrrkz */ >+/* Table5547 */ >+ 0x17d6, /* VSUBPSZrmkz */ >+ 0x17d9, /* VSUBPSZrrkz */ >+/* Table5549 */ >+ 0xf80, /* VMINPSZrmkz */ >+ 0xf83, /* VMINPSZrrkz */ >+/* Table5551 */ >+ 0xce6, /* VDIVPSZrmkz */ >+ 0xce9, /* VDIVPSZrrkz */ >+/* Table5553 */ >+ 0xf4b, /* VMAXPSZrmkz */ >+ 0xf4e, /* VMAXPSZrrkz */ >+/* Table5555 */ >+ 0x1080, /* VMOVDQU32Zrmkz */ >+ 0x1085, /* VMOVDQU32Zrrkz */ >+/* Table5557 */ >+ 0x10c2, /* VMOVDQU8Zrmkz */ >+ 0x10c7, /* VMOVDQU8Zrrkz */ >+/* Table5559 */ >+ 0x1015, /* VMOVDQA32Zrmkz */ >+ 0x101a, /* VMOVDQA32Zrrkz */ >+/* Table5561 */ >+ 0x122a, /* VPANDDZrmkz */ >+ 0x122d, /* VPANDDZrrkz */ >+/* Table5563 */ >+ 0x1233, /* VPANDNDZrmkz */ >+ 0x1236, /* VPANDNDZrrkz */ >+/* Table5565 */ >+ 0x15d5, /* VPORDZrmkz */ >+ 0x15d8, /* VPORDZrrkz */ >+/* Table5567 */ >+ 0x172a, /* VPXORDZrmkz */ >+ 0x172d, /* VPXORDZrrkz */ >+/* Table5569 */ >+ 0x16ca, /* VPSUBDZrmkz */ >+ 0x16cd, /* VPSUBDZrrkz */ >+/* Table5571 */ >+ 0x11fa, /* VPADDDZrmkz */ >+ 0x11fd, /* VPADDDZrrkz */ >+/* Table5573 */ >+ 0x10a1, /* VMOVDQU64Zrmkz */ >+ 0x10a6, /* VMOVDQU64Zrrkz */ >+/* Table5575 */ >+ 0x105f, /* VMOVDQU16Zrmkz */ >+ 0x1064, /* VMOVDQU16Zrrkz */ >+/* Table5577 */ >+ 0x1144, /* VMOVUPDZrmkz */ >+ 0x1149, /* VMOVUPDZrrkz */ >+/* Table5579 */ >+ 0xfb9, /* VMOVAPDZrmkz */ >+ 0xfbe, /* VMOVAPDZrrkz */ >+/* Table5581 */ >+ 0xb91, /* VADDPDZrmkz */ >+ 0xb94, /* VADDPDZrrkz */ >+/* Table5583 */ >+ 0x1194, /* VMULPDZrmkz */ >+ 0x1197, /* VMULPDZrrkz */ >+/* Table5585 */ >+ 0x17c9, /* VSUBPDZrmkz */ >+ 0x17cc, /* VSUBPDZrrkz */ >+/* Table5587 */ >+ 0xf73, /* VMINPDZrmkz */ >+ 0xf76, /* VMINPDZrrkz */ >+/* Table5589 */ >+ 0xcd9, /* VDIVPDZrmkz */ >+ 0xcdc, /* VDIVPDZrrkz */ >+/* Table5591 */ >+ 0xf3e, /* VMAXPDZrmkz */ >+ 0xf41, /* VMAXPDZrrkz */ >+/* Table5593 */ >+ 0x1036, /* VMOVDQA64Zrmkz */ >+ 0x103b, /* VMOVDQA64Zrrkz */ >+/* Table5595 */ >+ 0x1207, /* VPADDQZrmkz */ >+ 0x120a, /* VPADDQZrrkz */ >+/* Table5597 */ >+ 0x1249, /* VPANDQZrmkz */ >+ 0x124c, /* VPANDQZrrkz */ >+/* Table5599 */ >+ 0x123c, /* VPANDNQZrmkz */ >+ 0x123f, /* VPANDNQZrrkz */ >+/* Table5601 */ >+ 0x15de, /* VPORQZrmkz */ >+ 0x15e1, /* VPORQZrrkz */ >+/* Table5603 */ >+ 0x1733, /* VPXORQZrmkz */ >+ 0x1736, /* VPXORQZrrkz */ >+/* Table5605 */ >+ 0x15ca, /* VPMULUDQZrmkz */ >+ 0x15cd, /* VPMULUDQZrrkz */ >+/* Table5607 */ >+ 0x16d7, /* VPSUBQZrmkz */ >+ 0x16da, /* VPSUBQZrrkz */ >+/* Table5609 */ >+ 0x5dd, /* MMX_PSHUFBrm64 */ >+ 0x5de, /* MMX_PSHUFBrr64 */ >+/* Table5611 */ >+ 0x5b6, /* MMX_PHADDWrm64 */ >+ 0x5b7, /* MMX_PHADDWrr64 */ >+/* Table5613 */ >+ 0x5b8, /* MMX_PHADDrm64 */ >+ 0x5b9, /* MMX_PHADDrr64 */ >+/* Table5615 */ >+ 0x5b4, /* MMX_PHADDSWrm64 */ >+ 0x5b5, /* MMX_PHADDSWrr64 */ >+/* Table5617 */ >+ 0x5c2, /* MMX_PMADDUBSWrm64 */ >+ 0x5c3, /* MMX_PMADDUBSWrr64 */ >+/* Table5619 */ >+ 0x5be, /* MMX_PHSUBWrm64 */ >+ 0x5bf, /* MMX_PHSUBWrr64 */ >+/* Table5621 */ >+ 0x5ba, /* MMX_PHSUBDrm64 */ >+ 0x5bb, /* MMX_PHSUBDrr64 */ >+/* Table5623 */ >+ 0x5bc, /* MMX_PHSUBSWrm64 */ >+ 0x5bd, /* MMX_PHSUBSWrr64 */ >+/* Table5625 */ >+ 0x5e1, /* MMX_PSIGNBrm64 */ >+ 0x5e2, /* MMX_PSIGNBrr64 */ >+/* Table5627 */ >+ 0x5e5, /* MMX_PSIGNWrm64 */ >+ 0x5e6, /* MMX_PSIGNWrr64 */ >+/* Table5629 */ >+ 0x5e3, /* MMX_PSIGNDrm64 */ >+ 0x5e4, /* MMX_PSIGNDrr64 */ >+/* Table5631 */ >+ 0x5cf, /* MMX_PMULHRSWrm64 */ >+ 0x5d0, /* MMX_PMULHRSWrr64 */ >+/* Table5633 */ >+ 0x581, /* MMX_PABSBrm64 */ >+ 0x582, /* MMX_PABSBrr64 */ >+/* Table5635 */ >+ 0x585, /* MMX_PABSWrm64 */ >+ 0x586, /* MMX_PABSWrr64 */ >+/* Table5637 */ >+ 0x583, /* MMX_PABSDrm64 */ >+ 0x584, /* MMX_PABSDrr64 */ >+/* Table5639 */ >+ 0xa2b, /* SHA1NEXTErm */ >+ 0xa2c, /* SHA1NEXTErr */ >+/* Table5641 */ >+ 0xa27, /* SHA1MSG1rm */ >+ 0xa28, /* SHA1MSG1rr */ >+/* Table5643 */ >+ 0xa29, /* SHA1MSG2rm */ >+ 0xa2a, /* SHA1MSG2rr */ >+/* Table5645 */ >+ 0xa33, /* SHA256RNDS2rm */ >+ 0xa34, /* SHA256RNDS2rr */ >+/* Table5647 */ >+ 0xa2f, /* SHA256MSG1rm */ >+ 0xa30, /* SHA256MSG1rr */ >+/* Table5649 */ >+ 0xa31, /* SHA256MSG2rm */ >+ 0xa32, /* SHA256MSG2rr */ >+/* Table5651 */ >+ 0x679, /* MOVBE32rm */ >+ 0x0, /* */ >+/* Table5653 */ >+ 0x678, /* MOVBE32mr */ >+ 0x0, /* */ >+/* Table5655 */ >+ 0x880, /* PSHUFBrm */ >+ 0x881, /* PSHUFBrr */ >+/* Table5657 */ >+ 0x7fb, /* PHADDWrm */ >+ 0x7fc, /* PHADDWrr */ >+/* Table5659 */ >+ 0x7f7, /* PHADDDrm */ >+ 0x7f8, /* PHADDDrr */ >+/* Table5661 */ >+ 0x7f9, /* PHADDSWrm128 */ >+ 0x7fa, /* PHADDSWrr128 */ >+/* Table5663 */ >+ 0x811, /* PMADDUBSWrm128 */ >+ 0x812, /* PMADDUBSWrr128 */ >+/* Table5665 */ >+ 0x803, /* PHSUBWrm */ >+ 0x804, /* PHSUBWrr */ >+/* Table5667 */ >+ 0x7ff, /* PHSUBDrm */ >+ 0x800, /* PHSUBDrr */ >+/* Table5669 */ >+ 0x801, /* PHSUBSWrm128 */ >+ 0x802, /* PHSUBSWrr128 */ >+/* Table5671 */ >+ 0x888, /* PSIGNBrm */ >+ 0x889, /* PSIGNBrr */ >+/* Table5673 */ >+ 0x88c, /* PSIGNWrm */ >+ 0x88d, /* PSIGNWrr */ >+/* Table5675 */ >+ 0x88a, /* PSIGNDrm */ >+ 0x88b, /* PSIGNDrr */ >+/* Table5677 */ >+ 0x848, /* PMULHRSWrm128 */ >+ 0x849, /* PMULHRSWrr128 */ >+/* Table5679 */ >+ 0x79a, /* PBLENDVBrm0 */ >+ 0x79b, /* PBLENDVBrr0 */ >+/* Table5681 */ >+ 0x101, /* BLENDVPSrm0 */ >+ 0x102, /* BLENDVPSrr0 */ >+/* Table5683 */ >+ 0xff, /* BLENDVPDrm0 */ >+ 0x100, /* BLENDVPDrr0 */ >+/* Table5685 */ >+ 0x8ba, /* PTESTrm */ >+ 0x8bb, /* PTESTrr */ >+/* Table5687 */ >+ 0x76f, /* PABSBrm128 */ >+ 0x770, /* PABSBrr128 */ >+/* Table5689 */ >+ 0x773, /* PABSWrm128 */ >+ 0x774, /* PABSWrr128 */ >+/* Table5691 */ >+ 0x771, /* PABSDrm128 */ >+ 0x772, /* PABSDrr128 */ >+/* Table5693 */ >+ 0x832, /* PMOVSXBWrm */ >+ 0x833, /* PMOVSXBWrr */ >+/* Table5695 */ >+ 0x82e, /* PMOVSXBDrm */ >+ 0x82f, /* PMOVSXBDrr */ >+/* Table5697 */ >+ 0x830, /* PMOVSXBQrm */ >+ 0x831, /* PMOVSXBQrr */ >+/* Table5699 */ >+ 0x836, /* PMOVSXWDrm */ >+ 0x837, /* PMOVSXWDrr */ >+/* Table5701 */ >+ 0x838, /* PMOVSXWQrm */ >+ 0x839, /* PMOVSXWQrr */ >+/* Table5703 */ >+ 0x834, /* PMOVSXDQrm */ >+ 0x835, /* PMOVSXDQrr */ >+/* Table5705 */ >+ 0x846, /* PMULDQrm */ >+ 0x847, /* PMULDQrr */ >+/* Table5707 */ >+ 0x7a4, /* PCMPEQQrm */ >+ 0x7a5, /* PCMPEQQrr */ >+/* Table5709 */ >+ 0x696, /* MOVNTDQArm */ >+ 0x0, /* */ >+/* Table5711 */ >+ 0x779, /* PACKUSDWrm */ >+ 0x77a, /* PACKUSDWrr */ >+/* Table5713 */ >+ 0x83e, /* PMOVZXBWrm */ >+ 0x83f, /* PMOVZXBWrr */ >+/* Table5715 */ >+ 0x83a, /* PMOVZXBDrm */ >+ 0x83b, /* PMOVZXBDrr */ >+/* Table5717 */ >+ 0x83c, /* PMOVZXBQrm */ >+ 0x83d, /* PMOVZXBQrr */ >+/* Table5719 */ >+ 0x842, /* PMOVZXWDrm */ >+ 0x843, /* PMOVZXWDrr */ >+/* Table5721 */ >+ 0x844, /* PMOVZXWQrm */ >+ 0x845, /* PMOVZXWQrr */ >+/* Table5723 */ >+ 0x840, /* PMOVZXDQrm */ >+ 0x841, /* PMOVZXDQrr */ >+/* Table5725 */ >+ 0x7b4, /* PCMPGTQrm */ >+ 0x7b5, /* PCMPGTQrr */ >+/* Table5727 */ >+ 0x821, /* PMINSBrm */ >+ 0x822, /* PMINSBrr */ >+/* Table5729 */ >+ 0x823, /* PMINSDrm */ >+ 0x824, /* PMINSDrr */ >+/* Table5731 */ >+ 0x82b, /* PMINUWrm */ >+ 0x82c, /* PMINUWrr */ >+/* Table5733 */ >+ 0x829, /* PMINUDrm */ >+ 0x82a, /* PMINUDrr */ >+/* Table5735 */ >+ 0x815, /* PMAXSBrm */ >+ 0x816, /* PMAXSBrr */ >+/* Table5737 */ >+ 0x817, /* PMAXSDrm */ >+ 0x818, /* PMAXSDrr */ >+/* Table5739 */ >+ 0x81f, /* PMAXUWrm */ >+ 0x820, /* PMAXUWrr */ >+/* Table5741 */ >+ 0x81d, /* PMAXUDrm */ >+ 0x81e, /* PMAXUDrr */ >+/* Table5743 */ >+ 0x850, /* PMULLDrm */ >+ 0x851, /* PMULLDrr */ >+/* Table5745 */ >+ 0x7fd, /* PHMINPOSUWrm128 */ >+ 0x7fe, /* PHMINPOSUWrr128 */ >+/* Table5747 */ >+ 0x39a, /* INVEPT32 */ >+ 0x0, /* */ >+/* Table5749 */ >+ 0x3a1, /* INVVPID32 */ >+ 0x0, /* */ >+/* Table5751 */ >+ 0x39f, /* INVPCID32 */ >+ 0x0, /* */ >+/* Table5753 */ >+ 0xa7, /* AESIMCrm */ >+ 0xa8, /* AESIMCrr */ >+/* Table5755 */ >+ 0xa5, /* AESENCrm */ >+ 0xa6, /* AESENCrr */ >+/* Table5757 */ >+ 0xa3, /* AESENCLASTrm */ >+ 0xa4, /* AESENCLASTrr */ >+/* Table5759 */ >+ 0xa1, /* AESDECrm */ >+ 0xa2, /* AESDECrr */ >+/* Table5761 */ >+ 0x9f, /* AESDECLASTrm */ >+ 0xa0, /* AESDECLASTrr */ >+/* Table5763 */ >+ 0x677, /* MOVBE16rm */ >+ 0x0, /* */ >+/* Table5765 */ >+ 0x676, /* MOVBE16mr */ >+ 0x0, /* */ >+/* Table5767 */ >+ 0x42, /* ADCX32rm */ >+ 0x43, /* ADCX32rr */ >+/* Table5769 */ >+ 0x255, /* CRC32r32m8 */ >+ 0x258, /* CRC32r32r8 */ >+/* Table5771 */ >+ 0x254, /* CRC32r32m32 */ >+ 0x257, /* CRC32r32r32 */ >+/* Table5773 */ >+ 0x9b, /* ADOX32rm */ >+ 0x9c, /* ADOX32rr */ >+/* Table5775 */ >+ 0x253, /* CRC32r32m16 */ >+ 0x256, /* CRC32r32r16 */ >+/* Table5777 */ >+ 0x67b, /* MOVBE64rm */ >+ 0x0, /* */ >+/* Table5779 */ >+ 0x67a, /* MOVBE64mr */ >+ 0x0, /* */ >+/* Table5781 */ >+ 0x39b, /* INVEPT64 */ >+ 0x0, /* */ >+/* Table5783 */ >+ 0x3a2, /* INVVPID64 */ >+ 0x0, /* */ >+/* Table5785 */ >+ 0x3a0, /* INVPCID64 */ >+ 0x0, /* */ >+/* Table5787 */ >+ 0x9d, /* ADOX64rm */ >+ 0x9e, /* ADOX64rr */ >+/* Table5789 */ >+ 0x25a, /* CRC32r64m8 */ >+ 0x25c, /* CRC32r64r8 */ >+/* Table5791 */ >+ 0x259, /* CRC32r64m64 */ >+ 0x25b, /* CRC32r64r64 */ >+/* Table5793 */ >+ 0x44, /* ADCX64rm */ >+ 0x45, /* ADCX64rr */ >+/* Table5795 */ >+ 0xce, /* ANDN32rm */ >+ 0xcf, /* ANDN32rr */ >+/* Table5797 */ >+ 0x0, /* */ >+ 0x113, /* BLSR32rm */ >+ 0x10f, /* BLSMSK32rm */ >+ 0x107, /* BLSI32rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x114, /* BLSR32rr */ >+ 0x110, /* BLSMSK32rr */ >+ 0x108, /* BLSI32rr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table5813 */ >+ 0x157, /* BZHI32rm */ >+ 0x158, /* BZHI32rr */ >+/* Table5815 */ >+ 0xdf, /* BEXTR32rm */ >+ 0xe0, /* BEXTR32rr */ >+/* Table5817 */ >+ 0x7c4, /* PEXT32rm */ >+ 0x7c5, /* PEXT32rr */ >+/* Table5819 */ >+ 0x9cb, /* SARX32rm */ >+ 0x9cc, /* SARX32rr */ >+/* Table5821 */ >+ 0x7c0, /* PDEP32rm */ >+ 0x7c1, /* PDEP32rr */ >+/* Table5823 */ >+ 0x6f4, /* MULX32rm */ >+ 0x6f5, /* MULX32rr */ >+/* Table5825 */ >+ 0xa81, /* SHRX32rm */ >+ 0xa82, /* SHRX32rr */ >+/* Table5827 */ >+ 0x161f, /* VPSHUFBrm */ >+ 0x1620, /* VPSHUFBrr */ >+/* Table5829 */ >+ 0x1410, /* VPHADDWrm */ >+ 0x1411, /* VPHADDWrr */ >+/* Table5831 */ >+ 0x13f8, /* VPHADDDrm */ >+ 0x13f9, /* VPHADDDrr */ >+/* Table5833 */ >+ 0x13fa, /* VPHADDSWrm128 */ >+ 0x13fc, /* VPHADDSWrr128 */ >+/* Table5835 */ >+ 0x1458, /* VPMADDUBSWrm128 */ >+ 0x145a, /* VPMADDUBSWrr128 */ >+/* Table5837 */ >+ 0x1424, /* VPHSUBWrm */ >+ 0x1425, /* VPHSUBWrr */ >+/* Table5839 */ >+ 0x141a, /* VPHSUBDrm */ >+ 0x141b, /* VPHSUBDrr */ >+/* Table5841 */ >+ 0x141c, /* VPHSUBSWrm128 */ >+ 0x141e, /* VPHSUBSWrr128 */ >+/* Table5843 */ >+ 0x1631, /* VPSIGNBrm */ >+ 0x1632, /* VPSIGNBrr */ >+/* Table5845 */ >+ 0x1639, /* VPSIGNWrm */ >+ 0x163a, /* VPSIGNWrr */ >+/* Table5847 */ >+ 0x1635, /* VPSIGNDrm */ >+ 0x1636, /* VPSIGNDrr */ >+/* Table5849 */ >+ 0x15a6, /* VPMULHRSWrm128 */ >+ 0x15a8, /* VPMULHRSWrr128 */ >+/* Table5851 */ >+ 0x13af, /* VPERMILPSrm */ >+ 0x13b0, /* VPERMILPSrr */ >+/* Table5853 */ >+ 0x13a5, /* VPERMILPDrm */ >+ 0x13a6, /* VPERMILPDrr */ >+/* Table5855 */ >+ 0x17ee, /* VTESTPSrm */ >+ 0x17ef, /* VTESTPSrr */ >+/* Table5857 */ >+ 0x17ea, /* VTESTPDrm */ >+ 0x17eb, /* VTESTPDrr */ >+/* Table5859 */ >+ 0xc55, /* VCVTPH2PSrm */ >+ 0xc56, /* VCVTPH2PSrr */ >+/* Table5861 */ >+ 0x16fb, /* VPTESTrm */ >+ 0x16fc, /* VPTESTrr */ >+/* Table5863 */ >+ 0xbff, /* VBROADCASTSSrm */ >+ 0xc00, /* VBROADCASTSSrr */ >+/* Table5865 */ >+ 0x11c1, /* VPABSBrm128 */ >+ 0x11c3, /* VPABSBrr128 */ >+/* Table5867 */ >+ 0x11db, /* VPABSWrm128 */ >+ 0x11dd, /* VPABSWrr128 */ >+/* Table5869 */ >+ 0x11ce, /* VPABSDrm128 */ >+ 0x11d0, /* VPABSDrr128 */ >+/* Table5871 */ >+ 0x152a, /* VPMOVSXBWrm */ >+ 0x152b, /* VPMOVSXBWrr */ >+/* Table5873 */ >+ 0x151c, /* VPMOVSXBDrm */ >+ 0x151d, /* VPMOVSXBDrr */ >+/* Table5875 */ >+ 0x1526, /* VPMOVSXBQrm */ >+ 0x1527, /* VPMOVSXBQrr */ >+/* Table5877 */ >+ 0x153e, /* VPMOVSXWDrm */ >+ 0x153f, /* VPMOVSXWDrr */ >+/* Table5879 */ >+ 0x1548, /* VPMOVSXWQrm */ >+ 0x1549, /* VPMOVSXWQrr */ >+/* Table5881 */ >+ 0x1534, /* VPMOVSXDQrm */ >+ 0x1535, /* VPMOVSXDQrr */ >+/* Table5883 */ >+ 0x15a4, /* VPMULDQrm */ >+ 0x15a5, /* VPMULDQrr */ >+/* Table5885 */ >+ 0x12cf, /* VPCMPEQQrm */ >+ 0x12d0, /* VPCMPEQQrr */ >+/* Table5887 */ >+ 0x10e5, /* VMOVNTDQArm */ >+ 0x0, /* */ >+/* Table5889 */ >+ 0x11e9, /* VPACKUSDWrm */ >+ 0x11ea, /* VPACKUSDWrr */ >+/* Table5891 */ >+ 0xf2a, /* VMASKMOVPSrm */ >+ 0x0, /* */ >+/* Table5893 */ >+ 0xf26, /* VMASKMOVPDrm */ >+ 0x0, /* */ >+/* Table5895 */ >+ 0xf29, /* VMASKMOVPSmr */ >+ 0x0, /* */ >+/* Table5897 */ >+ 0xf25, /* VMASKMOVPDmr */ >+ 0x0, /* */ >+/* Table5899 */ >+ 0x1579, /* VPMOVZXBWrm */ >+ 0x157a, /* VPMOVZXBWrr */ >+/* Table5901 */ >+ 0x156b, /* VPMOVZXBDrm */ >+ 0x156c, /* VPMOVZXBDrr */ >+/* Table5903 */ >+ 0x1575, /* VPMOVZXBQrm */ >+ 0x1576, /* VPMOVZXBQrr */ >+/* Table5905 */ >+ 0x158d, /* VPMOVZXWDrm */ >+ 0x158e, /* VPMOVZXWDrr */ >+/* Table5907 */ >+ 0x1597, /* VPMOVZXWQrm */ >+ 0x1598, /* VPMOVZXWQrr */ >+/* Table5909 */ >+ 0x1583, /* VPMOVZXDQrm */ >+ 0x1584, /* VPMOVZXDQrr */ >+/* Table5911 */ >+ 0x1323, /* VPCMPGTQrm */ >+ 0x1324, /* VPCMPGTQrr */ >+/* Table5913 */ >+ 0x14a6, /* VPMINSBrm */ >+ 0x14a7, /* VPMINSBrr */ >+/* Table5915 */ >+ 0x14b3, /* VPMINSDrm */ >+ 0x14b4, /* VPMINSDrr */ >+/* Table5917 */ >+ 0x14de, /* VPMINUWrm */ >+ 0x14df, /* VPMINUWrr */ >+/* Table5919 */ >+ 0x14d1, /* VPMINUDrm */ >+ 0x14d2, /* VPMINUDrr */ >+/* Table5921 */ >+ 0x146a, /* VPMAXSBrm */ >+ 0x146b, /* VPMAXSBrr */ >+/* Table5923 */ >+ 0x1477, /* VPMAXSDrm */ >+ 0x1478, /* VPMAXSDrr */ >+/* Table5925 */ >+ 0x14a2, /* VPMAXUWrm */ >+ 0x14a3, /* VPMAXUWrr */ >+/* Table5927 */ >+ 0x1495, /* VPMAXUDrm */ >+ 0x1496, /* VPMAXUDrr */ >+/* Table5929 */ >+ 0x15bd, /* VPMULLDrm */ >+ 0x15be, /* VPMULLDrr */ >+/* Table5931 */ >+ 0x1412, /* VPHMINPOSUWrm128 */ >+ 0x1413, /* VPHMINPOSUWrr128 */ >+/* Table5933 */ >+ 0x16b1, /* VPSRLVDrm */ >+ 0x16b2, /* VPSRLVDrr */ >+/* Table5935 */ >+ 0x1685, /* VPSRAVDrm */ >+ 0x1686, /* VPSRAVDrr */ >+/* Table5937 */ >+ 0x165d, /* VPSLLVDrm */ >+ 0x165e, /* VPSLLVDrr */ >+/* Table5939 */ >+ 0x1275, /* VPBROADCASTDrm */ >+ 0x1276, /* VPBROADCASTDrr */ >+/* Table5941 */ >+ 0x1281, /* VPBROADCASTQrm */ >+ 0x1282, /* VPBROADCASTQrr */ >+/* Table5943 */ >+ 0x126b, /* VPBROADCASTBrm */ >+ 0x126c, /* VPBROADCASTBrr */ >+/* Table5945 */ >+ 0x1285, /* VPBROADCASTWrm */ >+ 0x1286, /* VPBROADCASTWrr */ >+/* Table5947 */ >+ 0x1463, /* VPMASKMOVDrm */ >+ 0x0, /* */ >+/* Table5949 */ >+ 0x1462, /* VPMASKMOVDmr */ >+ 0x0, /* */ >+/* Table5951 */ >+ 0x13e4, /* VPGATHERDDrm */ >+ 0x0, /* */ >+/* Table5953 */ >+ 0x13ea, /* VPGATHERQDrm */ >+ 0x0, /* */ >+/* Table5955 */ >+ 0xeef, /* VGATHERDPSrm */ >+ 0x0, /* */ >+/* Table5957 */ >+ 0xefd, /* VGATHERQPSrm */ >+ 0x0, /* */ >+/* Table5959 */ >+ 0xd90, /* VFMADDSUBPSr132m */ >+ 0xd92, /* VFMADDSUBPSr132r */ >+/* Table5961 */ >+ 0xdd4, /* VFMSUBADDPSr132m */ >+ 0xdd6, /* VFMSUBADDPSr132r */ >+/* Table5963 */ >+ 0xd3c, /* VFMADDPSr132m */ >+ 0xd3e, /* VFMADDPSr132r */ >+/* Table5965 */ >+ 0xd60, /* VFMADDSSr132m */ >+ 0xd61, /* VFMADDSSr132r */ >+/* Table5967 */ >+ 0xdfc, /* VFMSUBPSr132m */ >+ 0xdfe, /* VFMSUBPSr132r */ >+/* Table5969 */ >+ 0xe20, /* VFMSUBSSr132m */ >+ 0xe21, /* VFMSUBSSr132r */ >+/* Table5971 */ >+ 0xe50, /* VFNMADDPSr132m */ >+ 0xe52, /* VFNMADDPSr132r */ >+/* Table5973 */ >+ 0xe74, /* VFNMADDSSr132m */ >+ 0xe75, /* VFNMADDSSr132r */ >+/* Table5975 */ >+ 0xea4, /* VFNMSUBPSr132m */ >+ 0xea6, /* VFNMSUBPSr132r */ >+/* Table5977 */ >+ 0xec8, /* VFNMSUBSSr132m */ >+ 0xec9, /* VFNMSUBSSr132r */ >+/* Table5979 */ >+ 0xd94, /* VFMADDSUBPSr213m */ >+ 0xd96, /* VFMADDSUBPSr213r */ >+/* Table5981 */ >+ 0xdd8, /* VFMSUBADDPSr213m */ >+ 0xdda, /* VFMSUBADDPSr213r */ >+/* Table5983 */ >+ 0xd40, /* VFMADDPSr213m */ >+ 0xd42, /* VFMADDPSr213r */ >+/* Table5985 */ >+ 0xd62, /* VFMADDSSr213m */ >+ 0xd63, /* VFMADDSSr213r */ >+/* Table5987 */ >+ 0xe00, /* VFMSUBPSr213m */ >+ 0xe02, /* VFMSUBPSr213r */ >+/* Table5989 */ >+ 0xe22, /* VFMSUBSSr213m */ >+ 0xe23, /* VFMSUBSSr213r */ >+/* Table5991 */ >+ 0xe54, /* VFNMADDPSr213m */ >+ 0xe56, /* VFNMADDPSr213r */ >+/* Table5993 */ >+ 0xe76, /* VFNMADDSSr213m */ >+ 0xe77, /* VFNMADDSSr213r */ >+/* Table5995 */ >+ 0xea8, /* VFNMSUBPSr213m */ >+ 0xeaa, /* VFNMSUBPSr213r */ >+/* Table5997 */ >+ 0xeca, /* VFNMSUBSSr213m */ >+ 0xecb, /* VFNMSUBSSr213r */ >+/* Table5999 */ >+ 0xd98, /* VFMADDSUBPSr231m */ >+ 0xd9a, /* VFMADDSUBPSr231r */ >+/* Table6001 */ >+ 0xddc, /* VFMSUBADDPSr231m */ >+ 0xdde, /* VFMSUBADDPSr231r */ >+/* Table6003 */ >+ 0xd44, /* VFMADDPSr231m */ >+ 0xd46, /* VFMADDPSr231r */ >+/* Table6005 */ >+ 0xd64, /* VFMADDSSr231m */ >+ 0xd65, /* VFMADDSSr231r */ >+/* Table6007 */ >+ 0xe04, /* VFMSUBPSr231m */ >+ 0xe06, /* VFMSUBPSr231r */ >+/* Table6009 */ >+ 0xe24, /* VFMSUBSSr231m */ >+ 0xe25, /* VFMSUBSSr231r */ >+/* Table6011 */ >+ 0xe58, /* VFNMADDPSr231m */ >+ 0xe5a, /* VFNMADDPSr231r */ >+/* Table6013 */ >+ 0xe78, /* VFNMADDSSr231m */ >+ 0xe79, /* VFNMADDSSr231r */ >+/* Table6015 */ >+ 0xeac, /* VFNMSUBPSr231m */ >+ 0xeae, /* VFNMSUBPSr231r */ >+/* Table6017 */ >+ 0xecc, /* VFNMSUBSSr231m */ >+ 0xecd, /* VFNMSUBSSr231r */ >+/* Table6019 */ >+ 0xbc0, /* VAESIMCrm */ >+ 0xbc1, /* VAESIMCrr */ >+/* Table6021 */ >+ 0xbbe, /* VAESENCrm */ >+ 0xbbf, /* VAESENCrr */ >+/* Table6023 */ >+ 0xbbc, /* VAESENCLASTrm */ >+ 0xbbd, /* VAESENCLASTrr */ >+/* Table6025 */ >+ 0xbba, /* VAESDECrm */ >+ 0xbbb, /* VAESDECrr */ >+/* Table6027 */ >+ 0xbb8, /* VAESDECLASTrm */ >+ 0xbb9, /* VAESDECLASTrr */ >+/* Table6029 */ >+ 0xa59, /* SHLX32rm */ >+ 0xa5a, /* SHLX32rr */ >+/* Table6031 */ >+ 0xd0, /* ANDN64rm */ >+ 0xd1, /* ANDN64rr */ >+/* Table6033 */ >+ 0x0, /* */ >+ 0x115, /* BLSR64rm */ >+ 0x111, /* BLSMSK64rm */ >+ 0x109, /* BLSI64rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x116, /* BLSR64rr */ >+ 0x112, /* BLSMSK64rr */ >+ 0x10a, /* BLSI64rr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table6049 */ >+ 0x159, /* BZHI64rm */ >+ 0x15a, /* BZHI64rr */ >+/* Table6051 */ >+ 0xe1, /* BEXTR64rm */ >+ 0xe2, /* BEXTR64rr */ >+/* Table6053 */ >+ 0x7c6, /* PEXT64rm */ >+ 0x7c7, /* PEXT64rr */ >+/* Table6055 */ >+ 0x9cd, /* SARX64rm */ >+ 0x9ce, /* SARX64rr */ >+/* Table6057 */ >+ 0x7c2, /* PDEP64rm */ >+ 0x7c3, /* PDEP64rr */ >+/* Table6059 */ >+ 0x6f6, /* MULX64rm */ >+ 0x6f7, /* MULX64rr */ >+/* Table6061 */ >+ 0xa83, /* SHRX64rm */ >+ 0xa84, /* SHRX64rr */ >+/* Table6063 */ >+ 0x16b7, /* VPSRLVQrm */ >+ 0x16b8, /* VPSRLVQrr */ >+/* Table6065 */ >+ 0x1663, /* VPSLLVQrm */ >+ 0x1664, /* VPSLLVQrr */ >+/* Table6067 */ >+ 0x1467, /* VPMASKMOVQrm */ >+ 0x0, /* */ >+/* Table6069 */ >+ 0x1466, /* VPMASKMOVQmr */ >+ 0x0, /* */ >+/* Table6071 */ >+ 0x13e7, /* VPGATHERDQrm */ >+ 0x0, /* */ >+/* Table6073 */ >+ 0x13ed, /* VPGATHERQQrm */ >+ 0x0, /* */ >+/* Table6075 */ >+ 0xeec, /* VGATHERDPDrm */ >+ 0x0, /* */ >+/* Table6077 */ >+ 0xefa, /* VGATHERQPDrm */ >+ 0x0, /* */ >+/* Table6079 */ >+ 0xd7c, /* VFMADDSUBPDr132m */ >+ 0xd7e, /* VFMADDSUBPDr132r */ >+/* Table6081 */ >+ 0xdc0, /* VFMSUBADDPDr132m */ >+ 0xdc2, /* VFMSUBADDPDr132r */ >+/* Table6083 */ >+ 0xd28, /* VFMADDPDr132m */ >+ 0xd2a, /* VFMADDPDr132r */ >+/* Table6085 */ >+ 0xd51, /* VFMADDSDr132m */ >+ 0xd52, /* VFMADDSDr132r */ >+/* Table6087 */ >+ 0xde8, /* VFMSUBPDr132m */ >+ 0xdea, /* VFMSUBPDr132r */ >+/* Table6089 */ >+ 0xe11, /* VFMSUBSDr132m */ >+ 0xe12, /* VFMSUBSDr132r */ >+/* Table6091 */ >+ 0xe3c, /* VFNMADDPDr132m */ >+ 0xe3e, /* VFNMADDPDr132r */ >+/* Table6093 */ >+ 0xe65, /* VFNMADDSDr132m */ >+ 0xe66, /* VFNMADDSDr132r */ >+/* Table6095 */ >+ 0xe90, /* VFNMSUBPDr132m */ >+ 0xe92, /* VFNMSUBPDr132r */ >+/* Table6097 */ >+ 0xeb9, /* VFNMSUBSDr132m */ >+ 0xeba, /* VFNMSUBSDr132r */ >+/* Table6099 */ >+ 0xd80, /* VFMADDSUBPDr213m */ >+ 0xd82, /* VFMADDSUBPDr213r */ >+/* Table6101 */ >+ 0xdc4, /* VFMSUBADDPDr213m */ >+ 0xdc6, /* VFMSUBADDPDr213r */ >+/* Table6103 */ >+ 0xd2c, /* VFMADDPDr213m */ >+ 0xd2e, /* VFMADDPDr213r */ >+/* Table6105 */ >+ 0xd53, /* VFMADDSDr213m */ >+ 0xd54, /* VFMADDSDr213r */ >+/* Table6107 */ >+ 0xdec, /* VFMSUBPDr213m */ >+ 0xdee, /* VFMSUBPDr213r */ >+/* Table6109 */ >+ 0xe13, /* VFMSUBSDr213m */ >+ 0xe14, /* VFMSUBSDr213r */ >+/* Table6111 */ >+ 0xe40, /* VFNMADDPDr213m */ >+ 0xe42, /* VFNMADDPDr213r */ >+/* Table6113 */ >+ 0xe67, /* VFNMADDSDr213m */ >+ 0xe68, /* VFNMADDSDr213r */ >+/* Table6115 */ >+ 0xe94, /* VFNMSUBPDr213m */ >+ 0xe96, /* VFNMSUBPDr213r */ >+/* Table6117 */ >+ 0xebb, /* VFNMSUBSDr213m */ >+ 0xebc, /* VFNMSUBSDr213r */ >+/* Table6119 */ >+ 0xd84, /* VFMADDSUBPDr231m */ >+ 0xd86, /* VFMADDSUBPDr231r */ >+/* Table6121 */ >+ 0xdc8, /* VFMSUBADDPDr231m */ >+ 0xdca, /* VFMSUBADDPDr231r */ >+/* Table6123 */ >+ 0xd30, /* VFMADDPDr231m */ >+ 0xd32, /* VFMADDPDr231r */ >+/* Table6125 */ >+ 0xd55, /* VFMADDSDr231m */ >+ 0xd56, /* VFMADDSDr231r */ >+/* Table6127 */ >+ 0xdf0, /* VFMSUBPDr231m */ >+ 0xdf2, /* VFMSUBPDr231r */ >+/* Table6129 */ >+ 0xe15, /* VFMSUBSDr231m */ >+ 0xe16, /* VFMSUBSDr231r */ >+/* Table6131 */ >+ 0xe44, /* VFNMADDPDr231m */ >+ 0xe46, /* VFNMADDPDr231r */ >+/* Table6133 */ >+ 0xe69, /* VFNMADDSDr231m */ >+ 0xe6a, /* VFNMADDSDr231r */ >+/* Table6135 */ >+ 0xe98, /* VFNMSUBPDr231m */ >+ 0xe9a, /* VFNMSUBPDr231r */ >+/* Table6137 */ >+ 0xebd, /* VFNMSUBSDr231m */ >+ 0xebe, /* VFNMSUBSDr231r */ >+/* Table6139 */ >+ 0xa5b, /* SHLX64rm */ >+ 0xa5c, /* SHLX64rr */ >+/* Table6141 */ >+ 0x161d, /* VPSHUFBYrm */ >+ 0x161e, /* VPSHUFBYrr */ >+/* Table6143 */ >+ 0x140e, /* VPHADDWYrm */ >+ 0x140f, /* VPHADDWYrr */ >+/* Table6145 */ >+ 0x13f6, /* VPHADDDYrm */ >+ 0x13f7, /* VPHADDDYrr */ >+/* Table6147 */ >+ 0x13fb, /* VPHADDSWrm256 */ >+ 0x13fd, /* VPHADDSWrr256 */ >+/* Table6149 */ >+ 0x1459, /* VPMADDUBSWrm256 */ >+ 0x145b, /* VPMADDUBSWrr256 */ >+/* Table6151 */ >+ 0x1422, /* VPHSUBWYrm */ >+ 0x1423, /* VPHSUBWYrr */ >+/* Table6153 */ >+ 0x1418, /* VPHSUBDYrm */ >+ 0x1419, /* VPHSUBDYrr */ >+/* Table6155 */ >+ 0x141d, /* VPHSUBSWrm256 */ >+ 0x141f, /* VPHSUBSWrr256 */ >+/* Table6157 */ >+ 0x162f, /* VPSIGNBYrm */ >+ 0x1630, /* VPSIGNBYrr */ >+/* Table6159 */ >+ 0x1637, /* VPSIGNWYrm */ >+ 0x1638, /* VPSIGNWYrr */ >+/* Table6161 */ >+ 0x1633, /* VPSIGNDYrm */ >+ 0x1634, /* VPSIGNDYrr */ >+/* Table6163 */ >+ 0x15a7, /* VPMULHRSWrm256 */ >+ 0x15a9, /* VPMULHRSWrr256 */ >+/* Table6165 */ >+ 0x13a9, /* VPERMILPSYrm */ >+ 0x13aa, /* VPERMILPSYrr */ >+/* Table6167 */ >+ 0x139f, /* VPERMILPDYrm */ >+ 0x13a0, /* VPERMILPDYrr */ >+/* Table6169 */ >+ 0x17ec, /* VTESTPSYrm */ >+ 0x17ed, /* VTESTPSYrr */ >+/* Table6171 */ >+ 0x17e8, /* VTESTPDYrm */ >+ 0x17e9, /* VTESTPDYrr */ >+/* Table6173 */ >+ 0xc51, /* VCVTPH2PSYrm */ >+ 0xc52, /* VCVTPH2PSYrr */ >+/* Table6175 */ >+ 0x13b7, /* VPERMPSYrm */ >+ 0x13b8, /* VPERMPSYrr */ >+/* Table6177 */ >+ 0x16f9, /* VPTESTYrm */ >+ 0x16fa, /* VPTESTYrr */ >+/* Table6179 */ >+ 0xbfb, /* VBROADCASTSSYrm */ >+ 0xbfc, /* VBROADCASTSSYrr */ >+/* Table6181 */ >+ 0xbf7, /* VBROADCASTSDYrm */ >+ 0xbf8, /* VBROADCASTSDYrr */ >+/* Table6183 */ >+ 0xbf1, /* VBROADCASTF128 */ >+ 0x0, /* */ >+/* Table6185 */ >+ 0x11c2, /* VPABSBrm256 */ >+ 0x11c4, /* VPABSBrr256 */ >+/* Table6187 */ >+ 0x11dc, /* VPABSWrm256 */ >+ 0x11de, /* VPABSWrr256 */ >+/* Table6189 */ >+ 0x11cf, /* VPABSDrm256 */ >+ 0x11d1, /* VPABSDrr256 */ >+/* Table6191 */ >+ 0x1528, /* VPMOVSXBWYrm */ >+ 0x1529, /* VPMOVSXBWYrr */ >+/* Table6193 */ >+ 0x1514, /* VPMOVSXBDYrm */ >+ 0x1515, /* VPMOVSXBDYrr */ >+/* Table6195 */ >+ 0x151e, /* VPMOVSXBQYrm */ >+ 0x151f, /* VPMOVSXBQYrr */ >+/* Table6197 */ >+ 0x1536, /* VPMOVSXWDYrm */ >+ 0x1537, /* VPMOVSXWDYrr */ >+/* Table6199 */ >+ 0x1540, /* VPMOVSXWQYrm */ >+ 0x1541, /* VPMOVSXWQYrr */ >+/* Table6201 */ >+ 0x152c, /* VPMOVSXDQYrm */ >+ 0x152d, /* VPMOVSXDQYrr */ >+/* Table6203 */ >+ 0x1599, /* VPMULDQYrm */ >+ 0x159a, /* VPMULDQYrr */ >+/* Table6205 */ >+ 0x12bb, /* VPCMPEQQYrm */ >+ 0x12bc, /* VPCMPEQQYrr */ >+/* Table6207 */ >+ 0x10e1, /* VMOVNTDQAYrm */ >+ 0x0, /* */ >+/* Table6209 */ >+ 0x11e7, /* VPACKUSDWYrm */ >+ 0x11e8, /* VPACKUSDWYrr */ >+/* Table6211 */ >+ 0xf28, /* VMASKMOVPSYrm */ >+ 0x0, /* */ >+/* Table6213 */ >+ 0xf24, /* VMASKMOVPDYrm */ >+ 0x0, /* */ >+/* Table6215 */ >+ 0xf27, /* VMASKMOVPSYmr */ >+ 0x0, /* */ >+/* Table6217 */ >+ 0xf23, /* VMASKMOVPDYmr */ >+ 0x0, /* */ >+/* Table6219 */ >+ 0x1577, /* VPMOVZXBWYrm */ >+ 0x1578, /* VPMOVZXBWYrr */ >+/* Table6221 */ >+ 0x1563, /* VPMOVZXBDYrm */ >+ 0x1564, /* VPMOVZXBDYrr */ >+/* Table6223 */ >+ 0x156d, /* VPMOVZXBQYrm */ >+ 0x156e, /* VPMOVZXBQYrr */ >+/* Table6225 */ >+ 0x1585, /* VPMOVZXWDYrm */ >+ 0x1586, /* VPMOVZXWDYrr */ >+/* Table6227 */ >+ 0x158f, /* VPMOVZXWQYrm */ >+ 0x1590, /* VPMOVZXWQYrr */ >+/* Table6229 */ >+ 0x157b, /* VPMOVZXDQYrm */ >+ 0x157c, /* VPMOVZXDQYrr */ >+/* Table6231 */ >+ 0x1375, /* VPERMDYrm */ >+ 0x1376, /* VPERMDYrr */ >+/* Table6233 */ >+ 0x130f, /* VPCMPGTQYrm */ >+ 0x1310, /* VPCMPGTQYrr */ >+/* Table6235 */ >+ 0x14a4, /* VPMINSBYrm */ >+ 0x14a5, /* VPMINSBYrr */ >+/* Table6237 */ >+ 0x14a8, /* VPMINSDYrm */ >+ 0x14a9, /* VPMINSDYrr */ >+/* Table6239 */ >+ 0x14dc, /* VPMINUWYrm */ >+ 0x14dd, /* VPMINUWYrr */ >+/* Table6241 */ >+ 0x14c6, /* VPMINUDYrm */ >+ 0x14c7, /* VPMINUDYrr */ >+/* Table6243 */ >+ 0x1468, /* VPMAXSBYrm */ >+ 0x1469, /* VPMAXSBYrr */ >+/* Table6245 */ >+ 0x146c, /* VPMAXSDYrm */ >+ 0x146d, /* VPMAXSDYrr */ >+/* Table6247 */ >+ 0x14a0, /* VPMAXUWYrm */ >+ 0x14a1, /* VPMAXUWYrr */ >+/* Table6249 */ >+ 0x148a, /* VPMAXUDYrm */ >+ 0x148b, /* VPMAXUDYrr */ >+/* Table6251 */ >+ 0x15b2, /* VPMULLDYrm */ >+ 0x15b3, /* VPMULLDYrr */ >+/* Table6253 */ >+ 0x16ad, /* VPSRLVDYrm */ >+ 0x16ae, /* VPSRLVDYrr */ >+/* Table6255 */ >+ 0x1681, /* VPSRAVDYrm */ >+ 0x1682, /* VPSRAVDYrr */ >+/* Table6257 */ >+ 0x1659, /* VPSLLVDYrm */ >+ 0x165a, /* VPSLLVDYrr */ >+/* Table6259 */ >+ 0x126d, /* VPBROADCASTDYrm */ >+ 0x126e, /* VPBROADCASTDYrr */ >+/* Table6261 */ >+ 0x1279, /* VPBROADCASTQYrm */ >+ 0x127a, /* VPBROADCASTQYrr */ >+/* Table6263 */ >+ 0xbf2, /* VBROADCASTI128 */ >+ 0x0, /* */ >+/* Table6265 */ >+ 0x1269, /* VPBROADCASTBYrm */ >+ 0x126a, /* VPBROADCASTBYrr */ >+/* Table6267 */ >+ 0x1283, /* VPBROADCASTWYrm */ >+ 0x1284, /* VPBROADCASTWYrr */ >+/* Table6269 */ >+ 0x1461, /* VPMASKMOVDYrm */ >+ 0x0, /* */ >+/* Table6271 */ >+ 0x1460, /* VPMASKMOVDYmr */ >+ 0x0, /* */ >+/* Table6273 */ >+ 0x13e2, /* VPGATHERDDYrm */ >+ 0x0, /* */ >+/* Table6275 */ >+ 0x13e8, /* VPGATHERQDYrm */ >+ 0x0, /* */ >+/* Table6277 */ >+ 0xeed, /* VGATHERDPSYrm */ >+ 0x0, /* */ >+/* Table6279 */ >+ 0xefb, /* VGATHERQPSYrm */ >+ 0x0, /* */ >+/* Table6281 */ >+ 0xd91, /* VFMADDSUBPSr132mY */ >+ 0xd93, /* VFMADDSUBPSr132rY */ >+/* Table6283 */ >+ 0xdd5, /* VFMSUBADDPSr132mY */ >+ 0xdd7, /* VFMSUBADDPSr132rY */ >+/* Table6285 */ >+ 0xd3d, /* VFMADDPSr132mY */ >+ 0xd3f, /* VFMADDPSr132rY */ >+/* Table6287 */ >+ 0xdfd, /* VFMSUBPSr132mY */ >+ 0xdff, /* VFMSUBPSr132rY */ >+/* Table6289 */ >+ 0xe51, /* VFNMADDPSr132mY */ >+ 0xe53, /* VFNMADDPSr132rY */ >+/* Table6291 */ >+ 0xea5, /* VFNMSUBPSr132mY */ >+ 0xea7, /* VFNMSUBPSr132rY */ >+/* Table6293 */ >+ 0xd95, /* VFMADDSUBPSr213mY */ >+ 0xd97, /* VFMADDSUBPSr213rY */ >+/* Table6295 */ >+ 0xdd9, /* VFMSUBADDPSr213mY */ >+ 0xddb, /* VFMSUBADDPSr213rY */ >+/* Table6297 */ >+ 0xd41, /* VFMADDPSr213mY */ >+ 0xd43, /* VFMADDPSr213rY */ >+/* Table6299 */ >+ 0xe01, /* VFMSUBPSr213mY */ >+ 0xe03, /* VFMSUBPSr213rY */ >+/* Table6301 */ >+ 0xe55, /* VFNMADDPSr213mY */ >+ 0xe57, /* VFNMADDPSr213rY */ >+/* Table6303 */ >+ 0xea9, /* VFNMSUBPSr213mY */ >+ 0xeab, /* VFNMSUBPSr213rY */ >+/* Table6305 */ >+ 0xd99, /* VFMADDSUBPSr231mY */ >+ 0xd9b, /* VFMADDSUBPSr231rY */ >+/* Table6307 */ >+ 0xddd, /* VFMSUBADDPSr231mY */ >+ 0xddf, /* VFMSUBADDPSr231rY */ >+/* Table6309 */ >+ 0xd45, /* VFMADDPSr231mY */ >+ 0xd47, /* VFMADDPSr231rY */ >+/* Table6311 */ >+ 0xe05, /* VFMSUBPSr231mY */ >+ 0xe07, /* VFMSUBPSr231rY */ >+/* Table6313 */ >+ 0xe59, /* VFNMADDPSr231mY */ >+ 0xe5b, /* VFNMADDPSr231rY */ >+/* Table6315 */ >+ 0xead, /* VFNMSUBPSr231mY */ >+ 0xeaf, /* VFNMSUBPSr231rY */ >+/* Table6317 */ >+ 0x16b3, /* VPSRLVQYrm */ >+ 0x16b4, /* VPSRLVQYrr */ >+/* Table6319 */ >+ 0x165f, /* VPSLLVQYrm */ >+ 0x1660, /* VPSLLVQYrr */ >+/* Table6321 */ >+ 0x1465, /* VPMASKMOVQYrm */ >+ 0x0, /* */ >+/* Table6323 */ >+ 0x1464, /* VPMASKMOVQYmr */ >+ 0x0, /* */ >+/* Table6325 */ >+ 0x13e5, /* VPGATHERDQYrm */ >+ 0x0, /* */ >+/* Table6327 */ >+ 0x13eb, /* VPGATHERQQYrm */ >+ 0x0, /* */ >+/* Table6329 */ >+ 0xeea, /* VGATHERDPDYrm */ >+ 0x0, /* */ >+/* Table6331 */ >+ 0xef8, /* VGATHERQPDYrm */ >+ 0x0, /* */ >+/* Table6333 */ >+ 0xd7d, /* VFMADDSUBPDr132mY */ >+ 0xd7f, /* VFMADDSUBPDr132rY */ >+/* Table6335 */ >+ 0xdc1, /* VFMSUBADDPDr132mY */ >+ 0xdc3, /* VFMSUBADDPDr132rY */ >+/* Table6337 */ >+ 0xd29, /* VFMADDPDr132mY */ >+ 0xd2b, /* VFMADDPDr132rY */ >+/* Table6339 */ >+ 0xde9, /* VFMSUBPDr132mY */ >+ 0xdeb, /* VFMSUBPDr132rY */ >+/* Table6341 */ >+ 0xe3d, /* VFNMADDPDr132mY */ >+ 0xe3f, /* VFNMADDPDr132rY */ >+/* Table6343 */ >+ 0xe91, /* VFNMSUBPDr132mY */ >+ 0xe93, /* VFNMSUBPDr132rY */ >+/* Table6345 */ >+ 0xd81, /* VFMADDSUBPDr213mY */ >+ 0xd83, /* VFMADDSUBPDr213rY */ >+/* Table6347 */ >+ 0xdc5, /* VFMSUBADDPDr213mY */ >+ 0xdc7, /* VFMSUBADDPDr213rY */ >+/* Table6349 */ >+ 0xd2d, /* VFMADDPDr213mY */ >+ 0xd2f, /* VFMADDPDr213rY */ >+/* Table6351 */ >+ 0xded, /* VFMSUBPDr213mY */ >+ 0xdef, /* VFMSUBPDr213rY */ >+/* Table6353 */ >+ 0xe41, /* VFNMADDPDr213mY */ >+ 0xe43, /* VFNMADDPDr213rY */ >+/* Table6355 */ >+ 0xe95, /* VFNMSUBPDr213mY */ >+ 0xe97, /* VFNMSUBPDr213rY */ >+/* Table6357 */ >+ 0xd85, /* VFMADDSUBPDr231mY */ >+ 0xd87, /* VFMADDSUBPDr231rY */ >+/* Table6359 */ >+ 0xdc9, /* VFMSUBADDPDr231mY */ >+ 0xdcb, /* VFMSUBADDPDr231rY */ >+/* Table6361 */ >+ 0xd31, /* VFMADDPDr231mY */ >+ 0xd33, /* VFMADDPDr231rY */ >+/* Table6363 */ >+ 0xdf1, /* VFMSUBPDr231mY */ >+ 0xdf3, /* VFMSUBPDr231rY */ >+/* Table6365 */ >+ 0xe45, /* VFNMADDPDr231mY */ >+ 0xe47, /* VFNMADDPDr231rY */ >+/* Table6367 */ >+ 0xe99, /* VFNMSUBPDr231mY */ >+ 0xe9b, /* VFNMSUBPDr231rY */ >+/* Table6369 */ >+ 0x10e2, /* VMOVNTDQAZ128rm */ >+ 0x0, /* */ >+/* Table6371 */ >+ 0x1741, /* VRCP14SSrm */ >+ 0x1742, /* VRCP14SSrr */ >+/* Table6373 */ >+ 0x1776, /* VRSQRT14SSrm */ >+ 0x1777, /* VRSQRT14SSrr */ >+/* Table6375 */ >+ 0xd5e, /* VFMADDSSZm */ >+ 0xd5f, /* VFMADDSSZr */ >+/* Table6377 */ >+ 0xe1e, /* VFMSUBSSZm */ >+ 0xe1f, /* VFMSUBSSZr */ >+/* Table6379 */ >+ 0xe72, /* VFNMADDSSZm */ >+ 0xe73, /* VFNMADDSSZr */ >+/* Table6381 */ >+ 0xec6, /* VFNMSUBSSZm */ >+ 0xec7, /* VFNMSUBSSZr */ >+/* Table6383 */ >+ 0x174c, /* VRCP28SSrm */ >+ 0x174d, /* VRCP28SSrr */ >+/* Table6385 */ >+ 0x1781, /* VRSQRT28SSrm */ >+ 0x1782, /* VRSQRT28SSrr */ >+/* Table6387 */ >+ 0x12bd, /* VPCMPEQQZ128rm */ >+ 0x12c1, /* VPCMPEQQZ128rr */ >+/* Table6389 */ >+ 0x1311, /* VPCMPGTQZ128rm */ >+ 0x1315, /* VPCMPGTQZ128rr */ >+/* Table6391 */ >+ 0x173f, /* VRCP14SDrm */ >+ 0x1740, /* VRCP14SDrr */ >+/* Table6393 */ >+ 0x1774, /* VRSQRT14SDrm */ >+ 0x1775, /* VRSQRT14SDrr */ >+/* Table6395 */ >+ 0xd4f, /* VFMADDSDZm */ >+ 0xd50, /* VFMADDSDZr */ >+/* Table6397 */ >+ 0xe0f, /* VFMSUBSDZm */ >+ 0xe10, /* VFMSUBSDZr */ >+/* Table6399 */ >+ 0xe63, /* VFNMADDSDZm */ >+ 0xe64, /* VFNMADDSDZr */ >+/* Table6401 */ >+ 0xeb7, /* VFNMSUBSDZm */ >+ 0xeb8, /* VFNMSUBSDZr */ >+/* Table6403 */ >+ 0x1749, /* VRCP28SDrm */ >+ 0x174a, /* VRCP28SDrr */ >+/* Table6405 */ >+ 0x177e, /* VRSQRT28SDrm */ >+ 0x177f, /* VRSQRT28SDrr */ >+/* Table6407 */ >+ 0x10e3, /* VMOVNTDQAZ256rm */ >+ 0x0, /* */ >+/* Table6409 */ >+ 0x12c3, /* VPCMPEQQZ256rm */ >+ 0x12c7, /* VPCMPEQQZ256rr */ >+/* Table6411 */ >+ 0x1317, /* VPCMPGTQZ256rm */ >+ 0x131b, /* VPCMPGTQZ256rr */ >+/* Table6413 */ >+ 0x154a, /* VPMOVUSDBmr */ >+ 0x154c, /* VPMOVUSDBrr */ >+/* Table6415 */ >+ 0x1554, /* VPMOVUSQBmr */ >+ 0x1556, /* VPMOVUSQBrr */ >+/* Table6417 */ >+ 0x154f, /* VPMOVUSDWmr */ >+ 0x1551, /* VPMOVUSDWrr */ >+/* Table6419 */ >+ 0x155e, /* VPMOVUSQWmr */ >+ 0x1560, /* VPMOVUSQWrr */ >+/* Table6421 */ >+ 0x1559, /* VPMOVUSQDmr */ >+ 0x155b, /* VPMOVUSQDrr */ >+/* Table6423 */ >+ 0x14fb, /* VPMOVSDBmr */ >+ 0x14fd, /* VPMOVSDBrr */ >+/* Table6425 */ >+ 0x1505, /* VPMOVSQBmr */ >+ 0x1507, /* VPMOVSQBrr */ >+/* Table6427 */ >+ 0x1500, /* VPMOVSDWmr */ >+ 0x1502, /* VPMOVSDWrr */ >+/* Table6429 */ >+ 0x150f, /* VPMOVSQWmr */ >+ 0x1511, /* VPMOVSQWrr */ >+/* Table6431 */ >+ 0x150a, /* VPMOVSQDmr */ >+ 0x150c, /* VPMOVSQDrr */ >+/* Table6433 */ >+ 0x16f5, /* VPTESTNMDZrm */ >+ 0x16f6, /* VPTESTNMDZrr */ >+/* Table6435 */ >+ 0x14e0, /* VPMOVDBmr */ >+ 0x14e2, /* VPMOVDBrr */ >+/* Table6437 */ >+ 0x14ec, /* VPMOVQBmr */ >+ 0x14ee, /* VPMOVQBrr */ >+/* Table6439 */ >+ 0x14e5, /* VPMOVDWmr */ >+ 0x14e7, /* VPMOVDWrr */ >+/* Table6441 */ >+ 0x14f6, /* VPMOVQWmr */ >+ 0x14f8, /* VPMOVQWrr */ >+/* Table6443 */ >+ 0x14f1, /* VPMOVQDmr */ >+ 0x14f3, /* VPMOVQDrr */ >+/* Table6445 */ >+ 0x0, /* */ >+ 0x1278, /* VPBROADCASTMW2Drr */ >+/* Table6447 */ >+ 0xc53, /* VCVTPH2PSZrm */ >+ 0xc54, /* VCVTPH2PSZrr */ >+/* Table6449 */ >+ 0x13b9, /* VPERMPSZrm */ >+ 0x13ba, /* VPERMPSZrr */ >+/* Table6451 */ >+ 0xbfd, /* VBROADCASTSSZrm */ >+ 0xbfe, /* VBROADCASTSSZrr */ >+/* Table6453 */ >+ 0x11c5, /* VPABSDZrm */ >+ 0x11cb, /* VPABSDZrr */ >+/* Table6455 */ >+ 0x1516, /* VPMOVSXBDZrm */ >+ 0x1519, /* VPMOVSXBDZrr */ >+/* Table6457 */ >+ 0x1520, /* VPMOVSXBQZrm */ >+ 0x1523, /* VPMOVSXBQZrr */ >+/* Table6459 */ >+ 0x1538, /* VPMOVSXWDZrm */ >+ 0x153b, /* VPMOVSXWDZrr */ >+/* Table6461 */ >+ 0x1542, /* VPMOVSXWQZrm */ >+ 0x1545, /* VPMOVSXWQZrr */ >+/* Table6463 */ >+ 0x152e, /* VPMOVSXDQZrm */ >+ 0x1531, /* VPMOVSXDQZrr */ >+/* Table6465 */ >+ 0x16f1, /* VPTESTMDZrm */ >+ 0x16f2, /* VPTESTMDZrr */ >+/* Table6467 */ >+ 0x10e4, /* VMOVNTDQAZrm */ >+ 0x0, /* */ >+/* Table6469 */ >+ 0x1565, /* VPMOVZXBDZrm */ >+ 0x1568, /* VPMOVZXBDZrr */ >+/* Table6471 */ >+ 0x156f, /* VPMOVZXBQZrm */ >+ 0x1572, /* VPMOVZXBQZrr */ >+/* Table6473 */ >+ 0x1587, /* VPMOVZXWDZrm */ >+ 0x158a, /* VPMOVZXWDZrr */ >+/* Table6475 */ >+ 0x1591, /* VPMOVZXWQZrm */ >+ 0x1594, /* VPMOVZXWQZrr */ >+/* Table6477 */ >+ 0x157d, /* VPMOVZXDQZrm */ >+ 0x1580, /* VPMOVZXDQZrr */ >+/* Table6479 */ >+ 0x1377, /* VPERMDZrm */ >+ 0x1378, /* VPERMDZrr */ >+/* Table6481 */ >+ 0x14aa, /* VPMINSDZrm */ >+ 0x14b0, /* VPMINSDZrr */ >+/* Table6483 */ >+ 0x14c8, /* VPMINUDZrm */ >+ 0x14ce, /* VPMINUDZrr */ >+/* Table6485 */ >+ 0x146e, /* VPMAXSDZrm */ >+ 0x1474, /* VPMAXSDZrr */ >+/* Table6487 */ >+ 0x148c, /* VPMAXUDZrm */ >+ 0x1492, /* VPMAXUDZrr */ >+/* Table6489 */ >+ 0x15b4, /* VPMULLDZrm */ >+ 0x15ba, /* VPMULLDZrr */ >+/* Table6491 */ >+ 0x142e, /* VPLZCNTDrm */ >+ 0x1434, /* VPLZCNTDrr */ >+/* Table6493 */ >+ 0x16af, /* VPSRLVDZrm */ >+ 0x16b0, /* VPSRLVDZrr */ >+/* Table6495 */ >+ 0x1683, /* VPSRAVDZrm */ >+ 0x1684, /* VPSRAVDZrr */ >+/* Table6497 */ >+ 0x165b, /* VPSLLVDZrm */ >+ 0x165c, /* VPSLLVDZrr */ >+/* Table6499 */ >+ 0x173d, /* VRCP14PSZm */ >+ 0x173e, /* VRCP14PSZr */ >+/* Table6501 */ >+ 0x1772, /* VRSQRT14PSZm */ >+ 0x1773, /* VRSQRT14PSZr */ >+/* Table6503 */ >+ 0x1271, /* VPBROADCASTDZrm */ >+ 0x1272, /* VPBROADCASTDZrr */ >+/* Table6505 */ >+ 0xbf4, /* VBROADCASTI32X4rm */ >+ 0x0, /* */ >+/* Table6507 */ >+ 0x1379, /* VPERMI2Drm */ >+ 0x137c, /* VPERMI2Drr */ >+/* Table6509 */ >+ 0x1385, /* VPERMI2PSrm */ >+ 0x1388, /* VPERMI2PSrr */ >+/* Table6511 */ >+ 0x0, /* */ >+ 0x1274, /* VPBROADCASTDrZrr */ >+/* Table6513 */ >+ 0x13c1, /* VPERMT2Drm */ >+ 0x13c4, /* VPERMT2Drr */ >+/* Table6515 */ >+ 0x13cd, /* VPERMT2PSrm */ >+ 0x13d0, /* VPERMT2PSrr */ >+/* Table6517 */ >+ 0xd68, /* VFMADDSUB132PSZm */ >+ 0x0, /* */ >+/* Table6519 */ >+ 0xdac, /* VFMSUBADD132PSZm */ >+ 0x0, /* */ >+/* Table6521 */ >+ 0xd14, /* VFMADD132PSZm */ >+ 0x0, /* */ >+/* Table6523 */ >+ 0xd9e, /* VFMSUB132PSZm */ >+ 0x0, /* */ >+/* Table6525 */ >+ 0xe28, /* VFNMADD132PSZm */ >+ 0x0, /* */ >+/* Table6527 */ >+ 0xe7c, /* VFNMSUB132PSZm */ >+ 0x0, /* */ >+/* Table6529 */ >+ 0xd6f, /* VFMADDSUB213PSZm */ >+ 0xd71, /* VFMADDSUB213PSZr */ >+/* Table6531 */ >+ 0xdb3, /* VFMSUBADD213PSZm */ >+ 0xdb5, /* VFMSUBADD213PSZr */ >+/* Table6533 */ >+ 0xd1b, /* VFMADD213PSZm */ >+ 0xd1d, /* VFMADD213PSZr */ >+/* Table6535 */ >+ 0xda5, /* VFMSUB213PSZm */ >+ 0xda7, /* VFMSUB213PSZr */ >+/* Table6537 */ >+ 0xe2f, /* VFNMADD213PSZm */ >+ 0xe31, /* VFNMADD213PSZr */ >+/* Table6539 */ >+ 0xe83, /* VFNMSUB213PSZm */ >+ 0xe85, /* VFNMSUB213PSZr */ >+/* Table6541 */ >+ 0x135f, /* VPCONFLICTDrm */ >+ 0x1365, /* VPCONFLICTDrr */ >+/* Table6543 */ >+ 0x1746, /* VRCP28PSZm */ >+ 0x1747, /* VRCP28PSZr */ >+/* Table6545 */ >+ 0x177b, /* VRSQRT28PSZm */ >+ 0x177c, /* VRSQRT28PSZr */ >+/* Table6547 */ >+ 0x16f7, /* VPTESTNMQZrm */ >+ 0x16f8, /* VPTESTNMQZrr */ >+/* Table6549 */ >+ 0x0, /* */ >+ 0x1277, /* VPBROADCASTMB2Qrr */ >+/* Table6551 */ >+ 0x13b5, /* VPERMPDZrm */ >+ 0x13b6, /* VPERMPDZrr */ >+/* Table6553 */ >+ 0xbf9, /* VBROADCASTSDZrm */ >+ 0xbfa, /* VBROADCASTSDZrr */ >+/* Table6555 */ >+ 0x11d2, /* VPABSQZrm */ >+ 0x11d8, /* VPABSQZrr */ >+/* Table6557 */ >+ 0x16f3, /* VPTESTMQZrm */ >+ 0x16f4, /* VPTESTMQZrr */ >+/* Table6559 */ >+ 0x159b, /* VPMULDQZrm */ >+ 0x15a1, /* VPMULDQZrr */ >+/* Table6561 */ >+ 0x12c9, /* VPCMPEQQZrm */ >+ 0x12cd, /* VPCMPEQQZrr */ >+/* Table6563 */ >+ 0x13bf, /* VPERMQZrm */ >+ 0x13c0, /* VPERMQZrr */ >+/* Table6565 */ >+ 0x131d, /* VPCMPGTQZrm */ >+ 0x1321, /* VPCMPGTQZrr */ >+/* Table6567 */ >+ 0x14b5, /* VPMINSQZrm */ >+ 0x14bb, /* VPMINSQZrr */ >+/* Table6569 */ >+ 0x14d3, /* VPMINUQZrm */ >+ 0x14d9, /* VPMINUQZrr */ >+/* Table6571 */ >+ 0x1479, /* VPMAXSQZrm */ >+ 0x147f, /* VPMAXSQZrr */ >+/* Table6573 */ >+ 0x1497, /* VPMAXUQZrm */ >+ 0x149d, /* VPMAXUQZrr */ >+/* Table6575 */ >+ 0x1437, /* VPLZCNTQrm */ >+ 0x143d, /* VPLZCNTQrr */ >+/* Table6577 */ >+ 0x16b5, /* VPSRLVQZrm */ >+ 0x16b6, /* VPSRLVQZrr */ >+/* Table6579 */ >+ 0x1687, /* VPSRAVQZrm */ >+ 0x1688, /* VPSRAVQZrr */ >+/* Table6581 */ >+ 0x1661, /* VPSLLVQZrm */ >+ 0x1662, /* VPSLLVQZrr */ >+/* Table6583 */ >+ 0x173b, /* VRCP14PDZm */ >+ 0x173c, /* VRCP14PDZr */ >+/* Table6585 */ >+ 0x1770, /* VRSQRT14PDZm */ >+ 0x1771, /* VRSQRT14PDZr */ >+/* Table6587 */ >+ 0x127d, /* VPBROADCASTQZrm */ >+ 0x127e, /* VPBROADCASTQZrr */ >+/* Table6589 */ >+ 0xbf6, /* VBROADCASTI64X4rm */ >+ 0x0, /* */ >+/* Table6591 */ >+ 0x138b, /* VPERMI2Qrm */ >+ 0x138e, /* VPERMI2Qrr */ >+/* Table6593 */ >+ 0x137f, /* VPERMI2PDrm */ >+ 0x1382, /* VPERMI2PDrr */ >+/* Table6595 */ >+ 0x0, /* */ >+ 0x1280, /* VPBROADCASTQrZrr */ >+/* Table6597 */ >+ 0x13d3, /* VPERMT2Qrm */ >+ 0x13d6, /* VPERMT2Qrr */ >+/* Table6599 */ >+ 0x13c7, /* VPERMT2PDrm */ >+ 0x13ca, /* VPERMT2PDrr */ >+/* Table6601 */ >+ 0xd66, /* VFMADDSUB132PDZm */ >+ 0x0, /* */ >+/* Table6603 */ >+ 0xdaa, /* VFMSUBADD132PDZm */ >+ 0x0, /* */ >+/* Table6605 */ >+ 0xd12, /* VFMADD132PDZm */ >+ 0x0, /* */ >+/* Table6607 */ >+ 0xd9c, /* VFMSUB132PDZm */ >+ 0x0, /* */ >+/* Table6609 */ >+ 0xe26, /* VFNMADD132PDZm */ >+ 0x0, /* */ >+/* Table6611 */ >+ 0xe7a, /* VFNMSUB132PDZm */ >+ 0x0, /* */ >+/* Table6613 */ >+ 0xd6a, /* VFMADDSUB213PDZm */ >+ 0xd6c, /* VFMADDSUB213PDZr */ >+/* Table6615 */ >+ 0xdae, /* VFMSUBADD213PDZm */ >+ 0xdb0, /* VFMSUBADD213PDZr */ >+/* Table6617 */ >+ 0xd16, /* VFMADD213PDZm */ >+ 0xd18, /* VFMADD213PDZr */ >+/* Table6619 */ >+ 0xda0, /* VFMSUB213PDZm */ >+ 0xda2, /* VFMSUB213PDZr */ >+/* Table6621 */ >+ 0xe2a, /* VFNMADD213PDZm */ >+ 0xe2c, /* VFNMADD213PDZr */ >+/* Table6623 */ >+ 0xe7e, /* VFNMSUB213PDZm */ >+ 0xe80, /* VFNMSUB213PDZr */ >+/* Table6625 */ >+ 0x1368, /* VPCONFLICTQrm */ >+ 0x136e, /* VPCONFLICTQrr */ >+/* Table6627 */ >+ 0x1743, /* VRCP28PDZm */ >+ 0x1744, /* VRCP28PDZr */ >+/* Table6629 */ >+ 0x1778, /* VRSQRT28PDZm */ >+ 0x1779, /* VRSQRT28PDZr */ >+/* Table6631 */ >+ 0x12c0, /* VPCMPEQQZ128rmk */ >+ 0x12c2, /* VPCMPEQQZ128rrk */ >+/* Table6633 */ >+ 0x1314, /* VPCMPGTQZ128rmk */ >+ 0x1316, /* VPCMPGTQZ128rrk */ >+/* Table6635 */ >+ 0x12c6, /* VPCMPEQQZ256rmk */ >+ 0x12c8, /* VPCMPEQQZ256rrk */ >+/* Table6637 */ >+ 0x131a, /* VPCMPGTQZ256rmk */ >+ 0x131c, /* VPCMPGTQZ256rrk */ >+/* Table6639 */ >+ 0x154b, /* VPMOVUSDBmrk */ >+ 0x154d, /* VPMOVUSDBrrk */ >+/* Table6641 */ >+ 0x1555, /* VPMOVUSQBmrk */ >+ 0x1557, /* VPMOVUSQBrrk */ >+/* Table6643 */ >+ 0x1550, /* VPMOVUSDWmrk */ >+ 0x1552, /* VPMOVUSDWrrk */ >+/* Table6645 */ >+ 0x155f, /* VPMOVUSQWmrk */ >+ 0x1561, /* VPMOVUSQWrrk */ >+/* Table6647 */ >+ 0x155a, /* VPMOVUSQDmrk */ >+ 0x155c, /* VPMOVUSQDrrk */ >+/* Table6649 */ >+ 0x14fc, /* VPMOVSDBmrk */ >+ 0x14fe, /* VPMOVSDBrrk */ >+/* Table6651 */ >+ 0x1506, /* VPMOVSQBmrk */ >+ 0x1508, /* VPMOVSQBrrk */ >+/* Table6653 */ >+ 0x1501, /* VPMOVSDWmrk */ >+ 0x1503, /* VPMOVSDWrrk */ >+/* Table6655 */ >+ 0x1510, /* VPMOVSQWmrk */ >+ 0x1512, /* VPMOVSQWrrk */ >+/* Table6657 */ >+ 0x150b, /* VPMOVSQDmrk */ >+ 0x150d, /* VPMOVSQDrrk */ >+/* Table6659 */ >+ 0x14e1, /* VPMOVDBmrk */ >+ 0x14e3, /* VPMOVDBrrk */ >+/* Table6661 */ >+ 0x14ed, /* VPMOVQBmrk */ >+ 0x14ef, /* VPMOVQBrrk */ >+/* Table6663 */ >+ 0x14e6, /* VPMOVDWmrk */ >+ 0x14e8, /* VPMOVDWrrk */ >+/* Table6665 */ >+ 0x14f7, /* VPMOVQWmrk */ >+ 0x14f9, /* VPMOVQWrrk */ >+/* Table6667 */ >+ 0x14f2, /* VPMOVQDmrk */ >+ 0x14f4, /* VPMOVQDrrk */ >+/* Table6669 */ >+ 0x11c9, /* VPABSDZrmk */ >+ 0x11cc, /* VPABSDZrrk */ >+/* Table6671 */ >+ 0x1517, /* VPMOVSXBDZrmk */ >+ 0x151a, /* VPMOVSXBDZrrk */ >+/* Table6673 */ >+ 0x1521, /* VPMOVSXBQZrmk */ >+ 0x1524, /* VPMOVSXBQZrrk */ >+/* Table6675 */ >+ 0x1539, /* VPMOVSXWDZrmk */ >+ 0x153c, /* VPMOVSXWDZrrk */ >+/* Table6677 */ >+ 0x1543, /* VPMOVSXWQZrmk */ >+ 0x1546, /* VPMOVSXWQZrrk */ >+/* Table6679 */ >+ 0x152f, /* VPMOVSXDQZrmk */ >+ 0x1532, /* VPMOVSXDQZrrk */ >+/* Table6681 */ >+ 0x1566, /* VPMOVZXBDZrmk */ >+ 0x1569, /* VPMOVZXBDZrrk */ >+/* Table6683 */ >+ 0x1570, /* VPMOVZXBQZrmk */ >+ 0x1573, /* VPMOVZXBQZrrk */ >+/* Table6685 */ >+ 0x1588, /* VPMOVZXWDZrmk */ >+ 0x158b, /* VPMOVZXWDZrrk */ >+/* Table6687 */ >+ 0x1592, /* VPMOVZXWQZrmk */ >+ 0x1595, /* VPMOVZXWQZrrk */ >+/* Table6689 */ >+ 0x157e, /* VPMOVZXDQZrmk */ >+ 0x1581, /* VPMOVZXDQZrrk */ >+/* Table6691 */ >+ 0x14ae, /* VPMINSDZrmk */ >+ 0x14b1, /* VPMINSDZrrk */ >+/* Table6693 */ >+ 0x14cc, /* VPMINUDZrmk */ >+ 0x14cf, /* VPMINUDZrrk */ >+/* Table6695 */ >+ 0x1472, /* VPMAXSDZrmk */ >+ 0x1475, /* VPMAXSDZrrk */ >+/* Table6697 */ >+ 0x1490, /* VPMAXUDZrmk */ >+ 0x1493, /* VPMAXUDZrrk */ >+/* Table6699 */ >+ 0x15b8, /* VPMULLDZrmk */ >+ 0x15bb, /* VPMULLDZrrk */ >+/* Table6701 */ >+ 0x1432, /* VPLZCNTDrmk */ >+ 0x1435, /* VPLZCNTDrrk */ >+/* Table6703 */ >+ 0x125d, /* VPBLENDMDZrm */ >+ 0x125e, /* VPBLENDMDZrr */ >+/* Table6705 */ >+ 0xbdf, /* VBLENDMPSZrm */ >+ 0xbe0, /* VBLENDMPSZrr */ >+/* Table6707 */ >+ 0x137a, /* VPERMI2Drmk */ >+ 0x137d, /* VPERMI2Drrk */ >+/* Table6709 */ >+ 0x1386, /* VPERMI2PSrmk */ >+ 0x1389, /* VPERMI2PSrrk */ >+/* Table6711 */ >+ 0x13c2, /* VPERMT2Drmk */ >+ 0x13c5, /* VPERMT2Drrk */ >+/* Table6713 */ >+ 0x13ce, /* VPERMT2PSrmk */ >+ 0x13d1, /* VPERMT2PSrrk */ >+/* Table6715 */ >+ 0x13e3, /* VPGATHERDDZrm */ >+ 0x0, /* */ >+/* Table6717 */ >+ 0x13e9, /* VPGATHERQDZrm */ >+ 0x0, /* */ >+/* Table6719 */ >+ 0xeee, /* VGATHERDPSZrm */ >+ 0x0, /* */ >+/* Table6721 */ >+ 0xefc, /* VGATHERQPSZrm */ >+ 0x0, /* */ >+/* Table6723 */ >+ 0x1601, /* VPSCATTERDDZmr */ >+ 0x0, /* */ >+/* Table6725 */ >+ 0x1603, /* VPSCATTERQDZmr */ >+ 0x0, /* */ >+/* Table6727 */ >+ 0x1790, /* VSCATTERDPSZmr */ >+ 0x0, /* */ >+/* Table6729 */ >+ 0x179a, /* VSCATTERQPSZmr */ >+ 0x0, /* */ >+/* Table6731 */ >+ 0x0, /* */ >+ 0xd72, /* VFMADDSUB213PSZrk */ >+/* Table6733 */ >+ 0x0, /* */ >+ 0xdb6, /* VFMSUBADD213PSZrk */ >+/* Table6735 */ >+ 0x0, /* */ >+ 0xd1e, /* VFMADD213PSZrk */ >+/* Table6737 */ >+ 0x0, /* */ >+ 0xda8, /* VFMSUB213PSZrk */ >+/* Table6739 */ >+ 0x0, /* */ >+ 0xe32, /* VFNMADD213PSZrk */ >+/* Table6741 */ >+ 0x0, /* */ >+ 0xe86, /* VFNMSUB213PSZrk */ >+/* Table6743 */ >+ 0x1363, /* VPCONFLICTDrmk */ >+ 0x1366, /* VPCONFLICTDrrk */ >+/* Table6745 */ >+ 0x0, /* */ >+ 0xef1, /* VGATHERPF0DPSm */ >+ 0xef5, /* VGATHERPF1DPSm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1792, /* VSCATTERPF0DPSm */ >+ 0x1796, /* VSCATTERPF1DPSm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table6761 */ >+ 0x0, /* */ >+ 0xef3, /* VGATHERPF0QPSm */ >+ 0xef7, /* VGATHERPF1QPSm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1794, /* VSCATTERPF0QPSm */ >+ 0x1798, /* VSCATTERPF1QPSm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table6777 */ >+ 0x11d6, /* VPABSQZrmk */ >+ 0x11d9, /* VPABSQZrrk */ >+/* Table6779 */ >+ 0x159f, /* VPMULDQZrmk */ >+ 0x15a2, /* VPMULDQZrrk */ >+/* Table6781 */ >+ 0x12cc, /* VPCMPEQQZrmk */ >+ 0x12ce, /* VPCMPEQQZrrk */ >+/* Table6783 */ >+ 0x1320, /* VPCMPGTQZrmk */ >+ 0x1322, /* VPCMPGTQZrrk */ >+/* Table6785 */ >+ 0x14b9, /* VPMINSQZrmk */ >+ 0x14bc, /* VPMINSQZrrk */ >+/* Table6787 */ >+ 0x14d7, /* VPMINUQZrmk */ >+ 0x14da, /* VPMINUQZrrk */ >+/* Table6789 */ >+ 0x147d, /* VPMAXSQZrmk */ >+ 0x1480, /* VPMAXSQZrrk */ >+/* Table6791 */ >+ 0x149b, /* VPMAXUQZrmk */ >+ 0x149e, /* VPMAXUQZrrk */ >+/* Table6793 */ >+ 0x143b, /* VPLZCNTQrmk */ >+ 0x143e, /* VPLZCNTQrrk */ >+/* Table6795 */ >+ 0x125f, /* VPBLENDMQZrm */ >+ 0x1260, /* VPBLENDMQZrr */ >+/* Table6797 */ >+ 0xbdd, /* VBLENDMPDZrm */ >+ 0xbde, /* VBLENDMPDZrr */ >+/* Table6799 */ >+ 0x138c, /* VPERMI2Qrmk */ >+ 0x138f, /* VPERMI2Qrrk */ >+/* Table6801 */ >+ 0x1380, /* VPERMI2PDrmk */ >+ 0x1383, /* VPERMI2PDrrk */ >+/* Table6803 */ >+ 0x13d4, /* VPERMT2Qrmk */ >+ 0x13d7, /* VPERMT2Qrrk */ >+/* Table6805 */ >+ 0x13c8, /* VPERMT2PDrmk */ >+ 0x13cb, /* VPERMT2PDrrk */ >+/* Table6807 */ >+ 0x13e6, /* VPGATHERDQZrm */ >+ 0x0, /* */ >+/* Table6809 */ >+ 0x13ec, /* VPGATHERQQZrm */ >+ 0x0, /* */ >+/* Table6811 */ >+ 0xeeb, /* VGATHERDPDZrm */ >+ 0x0, /* */ >+/* Table6813 */ >+ 0xef9, /* VGATHERQPDZrm */ >+ 0x0, /* */ >+/* Table6815 */ >+ 0x1602, /* VPSCATTERDQZmr */ >+ 0x0, /* */ >+/* Table6817 */ >+ 0x1604, /* VPSCATTERQQZmr */ >+ 0x0, /* */ >+/* Table6819 */ >+ 0x178f, /* VSCATTERDPDZmr */ >+ 0x0, /* */ >+/* Table6821 */ >+ 0x1799, /* VSCATTERQPDZmr */ >+ 0x0, /* */ >+/* Table6823 */ >+ 0x0, /* */ >+ 0xd6d, /* VFMADDSUB213PDZrk */ >+/* Table6825 */ >+ 0x0, /* */ >+ 0xdb1, /* VFMSUBADD213PDZrk */ >+/* Table6827 */ >+ 0x0, /* */ >+ 0xd19, /* VFMADD213PDZrk */ >+/* Table6829 */ >+ 0x0, /* */ >+ 0xda3, /* VFMSUB213PDZrk */ >+/* Table6831 */ >+ 0x0, /* */ >+ 0xe2d, /* VFNMADD213PDZrk */ >+/* Table6833 */ >+ 0x0, /* */ >+ 0xe81, /* VFNMSUB213PDZrk */ >+/* Table6835 */ >+ 0x136c, /* VPCONFLICTQrmk */ >+ 0x136f, /* VPCONFLICTQrrk */ >+/* Table6837 */ >+ 0x0, /* */ >+ 0xef0, /* VGATHERPF0DPDm */ >+ 0xef4, /* VGATHERPF1DPDm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1791, /* VSCATTERPF0DPDm */ >+ 0x1795, /* VSCATTERPF1DPDm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table6853 */ >+ 0x0, /* */ >+ 0xef2, /* VGATHERPF0QPDm */ >+ 0xef6, /* VGATHERPF1QPDm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x1793, /* VSCATTERPF0QPDm */ >+ 0x1797, /* VSCATTERPF1QPDm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table6869 */ >+ 0x0, /* */ >+ 0x174e, /* VRCP28SSrrb */ >+/* Table6871 */ >+ 0x0, /* */ >+ 0x1783, /* VRSQRT28SSrrb */ >+/* Table6873 */ >+ 0x12be, /* VPCMPEQQZ128rmb */ >+ 0x0, /* */ >+/* Table6875 */ >+ 0x1312, /* VPCMPGTQZ128rmb */ >+ 0x0, /* */ >+/* Table6877 */ >+ 0x0, /* */ >+ 0x174b, /* VRCP28SDrrb */ >+/* Table6879 */ >+ 0x0, /* */ >+ 0x1780, /* VRSQRT28SDrrb */ >+/* Table6881 */ >+ 0x12c4, /* VPCMPEQQZ256rmb */ >+ 0x0, /* */ >+/* Table6883 */ >+ 0x1318, /* VPCMPGTQZ256rmb */ >+ 0x0, /* */ >+/* Table6885 */ >+ 0x11c6, /* VPABSDZrmb */ >+ 0x0, /* */ >+/* Table6887 */ >+ 0x14ab, /* VPMINSDZrmb */ >+ 0x0, /* */ >+/* Table6889 */ >+ 0x14c9, /* VPMINUDZrmb */ >+ 0x0, /* */ >+/* Table6891 */ >+ 0x146f, /* VPMAXSDZrmb */ >+ 0x0, /* */ >+/* Table6893 */ >+ 0x148d, /* VPMAXUDZrmb */ >+ 0x0, /* */ >+/* Table6895 */ >+ 0x15b5, /* VPMULLDZrmb */ >+ 0x0, /* */ >+/* Table6897 */ >+ 0x142f, /* VPLZCNTDrmb */ >+ 0x0, /* */ >+/* Table6899 */ >+ 0xd69, /* VFMADDSUB132PSZmb */ >+ 0x0, /* */ >+/* Table6901 */ >+ 0xdad, /* VFMSUBADD132PSZmb */ >+ 0x0, /* */ >+/* Table6903 */ >+ 0xd15, /* VFMADD132PSZmb */ >+ 0x0, /* */ >+/* Table6905 */ >+ 0xd9f, /* VFMSUB132PSZmb */ >+ 0x0, /* */ >+/* Table6907 */ >+ 0xe29, /* VFNMADD132PSZmb */ >+ 0x0, /* */ >+/* Table6909 */ >+ 0xe7d, /* VFNMSUB132PSZmb */ >+ 0x0, /* */ >+/* Table6911 */ >+ 0xd70, /* VFMADDSUB213PSZmb */ >+ 0x0, /* */ >+/* Table6913 */ >+ 0xdb4, /* VFMSUBADD213PSZmb */ >+ 0x0, /* */ >+/* Table6915 */ >+ 0xd1c, /* VFMADD213PSZmb */ >+ 0x0, /* */ >+/* Table6917 */ >+ 0xda6, /* VFMSUB213PSZmb */ >+ 0x0, /* */ >+/* Table6919 */ >+ 0xe30, /* VFNMADD213PSZmb */ >+ 0x0, /* */ >+/* Table6921 */ >+ 0xe84, /* VFNMSUB213PSZmb */ >+ 0x0, /* */ >+/* Table6923 */ >+ 0x1360, /* VPCONFLICTDrmb */ >+ 0x0, /* */ >+/* Table6925 */ >+ 0x0, /* */ >+ 0x1748, /* VRCP28PSZrb */ >+/* Table6927 */ >+ 0x0, /* */ >+ 0x177d, /* VRSQRT28PSZrb */ >+/* Table6929 */ >+ 0x11d3, /* VPABSQZrmb */ >+ 0x0, /* */ >+/* Table6931 */ >+ 0x159c, /* VPMULDQZrmb */ >+ 0x0, /* */ >+/* Table6933 */ >+ 0x12ca, /* VPCMPEQQZrmb */ >+ 0x0, /* */ >+/* Table6935 */ >+ 0x131e, /* VPCMPGTQZrmb */ >+ 0x0, /* */ >+/* Table6937 */ >+ 0x14b6, /* VPMINSQZrmb */ >+ 0x0, /* */ >+/* Table6939 */ >+ 0x14d4, /* VPMINUQZrmb */ >+ 0x0, /* */ >+/* Table6941 */ >+ 0x147a, /* VPMAXSQZrmb */ >+ 0x0, /* */ >+/* Table6943 */ >+ 0x1498, /* VPMAXUQZrmb */ >+ 0x0, /* */ >+/* Table6945 */ >+ 0x1438, /* VPLZCNTQrmb */ >+ 0x0, /* */ >+/* Table6947 */ >+ 0xd67, /* VFMADDSUB132PDZmb */ >+ 0x0, /* */ >+/* Table6949 */ >+ 0xdab, /* VFMSUBADD132PDZmb */ >+ 0x0, /* */ >+/* Table6951 */ >+ 0xd13, /* VFMADD132PDZmb */ >+ 0x0, /* */ >+/* Table6953 */ >+ 0xd9d, /* VFMSUB132PDZmb */ >+ 0x0, /* */ >+/* Table6955 */ >+ 0xe27, /* VFNMADD132PDZmb */ >+ 0x0, /* */ >+/* Table6957 */ >+ 0xe7b, /* VFNMSUB132PDZmb */ >+ 0x0, /* */ >+/* Table6959 */ >+ 0xd6b, /* VFMADDSUB213PDZmb */ >+ 0x0, /* */ >+/* Table6961 */ >+ 0xdaf, /* VFMSUBADD213PDZmb */ >+ 0x0, /* */ >+/* Table6963 */ >+ 0xd17, /* VFMADD213PDZmb */ >+ 0x0, /* */ >+/* Table6965 */ >+ 0xda1, /* VFMSUB213PDZmb */ >+ 0x0, /* */ >+/* Table6967 */ >+ 0xe2b, /* VFNMADD213PDZmb */ >+ 0x0, /* */ >+/* Table6969 */ >+ 0xe7f, /* VFNMSUB213PDZmb */ >+ 0x0, /* */ >+/* Table6971 */ >+ 0x1369, /* VPCONFLICTQrmb */ >+ 0x0, /* */ >+/* Table6973 */ >+ 0x0, /* */ >+ 0x1745, /* VRCP28PDZrb */ >+/* Table6975 */ >+ 0x0, /* */ >+ 0x177a, /* VRSQRT28PDZrb */ >+/* Table6977 */ >+ 0x12bf, /* VPCMPEQQZ128rmbk */ >+ 0x0, /* */ >+/* Table6979 */ >+ 0x1313, /* VPCMPGTQZ128rmbk */ >+ 0x0, /* */ >+/* Table6981 */ >+ 0x12c5, /* VPCMPEQQZ256rmbk */ >+ 0x0, /* */ >+/* Table6983 */ >+ 0x1319, /* VPCMPGTQZ256rmbk */ >+ 0x0, /* */ >+/* Table6985 */ >+ 0x11c7, /* VPABSDZrmbk */ >+ 0x0, /* */ >+/* Table6987 */ >+ 0x14ac, /* VPMINSDZrmbk */ >+ 0x0, /* */ >+/* Table6989 */ >+ 0x14ca, /* VPMINUDZrmbk */ >+ 0x0, /* */ >+/* Table6991 */ >+ 0x1470, /* VPMAXSDZrmbk */ >+ 0x0, /* */ >+/* Table6993 */ >+ 0x148e, /* VPMAXUDZrmbk */ >+ 0x0, /* */ >+/* Table6995 */ >+ 0x15b6, /* VPMULLDZrmbk */ >+ 0x0, /* */ >+/* Table6997 */ >+ 0x1430, /* VPLZCNTDrmbk */ >+ 0x0, /* */ >+/* Table6999 */ >+ 0x1361, /* VPCONFLICTDrmbk */ >+ 0x0, /* */ >+/* Table7001 */ >+ 0x11d4, /* VPABSQZrmbk */ >+ 0x0, /* */ >+/* Table7003 */ >+ 0x159d, /* VPMULDQZrmbk */ >+ 0x0, /* */ >+/* Table7005 */ >+ 0x12cb, /* VPCMPEQQZrmbk */ >+ 0x0, /* */ >+/* Table7007 */ >+ 0x131f, /* VPCMPGTQZrmbk */ >+ 0x0, /* */ >+/* Table7009 */ >+ 0x14b7, /* VPMINSQZrmbk */ >+ 0x0, /* */ >+/* Table7011 */ >+ 0x14d5, /* VPMINUQZrmbk */ >+ 0x0, /* */ >+/* Table7013 */ >+ 0x147b, /* VPMAXSQZrmbk */ >+ 0x0, /* */ >+/* Table7015 */ >+ 0x1499, /* VPMAXUQZrmbk */ >+ 0x0, /* */ >+/* Table7017 */ >+ 0x1439, /* VPLZCNTQrmbk */ >+ 0x0, /* */ >+/* Table7019 */ >+ 0x136a, /* VPCONFLICTQrmbk */ >+ 0x0, /* */ >+/* Table7021 */ >+ 0x11c8, /* VPABSDZrmbkz */ >+ 0x0, /* */ >+/* Table7023 */ >+ 0x14ad, /* VPMINSDZrmbkz */ >+ 0x0, /* */ >+/* Table7025 */ >+ 0x14cb, /* VPMINUDZrmbkz */ >+ 0x0, /* */ >+/* Table7027 */ >+ 0x1471, /* VPMAXSDZrmbkz */ >+ 0x0, /* */ >+/* Table7029 */ >+ 0x148f, /* VPMAXUDZrmbkz */ >+ 0x0, /* */ >+/* Table7031 */ >+ 0x15b7, /* VPMULLDZrmbkz */ >+ 0x0, /* */ >+/* Table7033 */ >+ 0x1431, /* VPLZCNTDrmbkz */ >+ 0x0, /* */ >+/* Table7035 */ >+ 0x1362, /* VPCONFLICTDrmbkz */ >+ 0x0, /* */ >+/* Table7037 */ >+ 0x11d5, /* VPABSQZrmbkz */ >+ 0x0, /* */ >+/* Table7039 */ >+ 0x159e, /* VPMULDQZrmbkz */ >+ 0x0, /* */ >+/* Table7041 */ >+ 0x14b8, /* VPMINSQZrmbkz */ >+ 0x0, /* */ >+/* Table7043 */ >+ 0x14d6, /* VPMINUQZrmbkz */ >+ 0x0, /* */ >+/* Table7045 */ >+ 0x147c, /* VPMAXSQZrmbkz */ >+ 0x0, /* */ >+/* Table7047 */ >+ 0x149a, /* VPMAXUQZrmbkz */ >+ 0x0, /* */ >+/* Table7049 */ >+ 0x143a, /* VPLZCNTQrmbkz */ >+ 0x0, /* */ >+/* Table7051 */ >+ 0x136b, /* VPCONFLICTQrmbkz */ >+ 0x0, /* */ >+/* Table7053 */ >+ 0x0, /* */ >+ 0x154e, /* VPMOVUSDBrrkz */ >+/* Table7055 */ >+ 0x0, /* */ >+ 0x1558, /* VPMOVUSQBrrkz */ >+/* Table7057 */ >+ 0x0, /* */ >+ 0x1553, /* VPMOVUSDWrrkz */ >+/* Table7059 */ >+ 0x0, /* */ >+ 0x1562, /* VPMOVUSQWrrkz */ >+/* Table7061 */ >+ 0x0, /* */ >+ 0x155d, /* VPMOVUSQDrrkz */ >+/* Table7063 */ >+ 0x0, /* */ >+ 0x14ff, /* VPMOVSDBrrkz */ >+/* Table7065 */ >+ 0x0, /* */ >+ 0x1509, /* VPMOVSQBrrkz */ >+/* Table7067 */ >+ 0x0, /* */ >+ 0x1504, /* VPMOVSDWrrkz */ >+/* Table7069 */ >+ 0x0, /* */ >+ 0x1513, /* VPMOVSQWrrkz */ >+/* Table7071 */ >+ 0x0, /* */ >+ 0x150e, /* VPMOVSQDrrkz */ >+/* Table7073 */ >+ 0x0, /* */ >+ 0x14e4, /* VPMOVDBrrkz */ >+/* Table7075 */ >+ 0x0, /* */ >+ 0x14f0, /* VPMOVQBrrkz */ >+/* Table7077 */ >+ 0x0, /* */ >+ 0x14e9, /* VPMOVDWrrkz */ >+/* Table7079 */ >+ 0x0, /* */ >+ 0x14fa, /* VPMOVQWrrkz */ >+/* Table7081 */ >+ 0x0, /* */ >+ 0x14f5, /* VPMOVQDrrkz */ >+/* Table7083 */ >+ 0x11ca, /* VPABSDZrmkz */ >+ 0x11cd, /* VPABSDZrrkz */ >+/* Table7085 */ >+ 0x1518, /* VPMOVSXBDZrmkz */ >+ 0x151b, /* VPMOVSXBDZrrkz */ >+/* Table7087 */ >+ 0x1522, /* VPMOVSXBQZrmkz */ >+ 0x1525, /* VPMOVSXBQZrrkz */ >+/* Table7089 */ >+ 0x153a, /* VPMOVSXWDZrmkz */ >+ 0x153d, /* VPMOVSXWDZrrkz */ >+/* Table7091 */ >+ 0x1544, /* VPMOVSXWQZrmkz */ >+ 0x1547, /* VPMOVSXWQZrrkz */ >+/* Table7093 */ >+ 0x1530, /* VPMOVSXDQZrmkz */ >+ 0x1533, /* VPMOVSXDQZrrkz */ >+/* Table7095 */ >+ 0x1567, /* VPMOVZXBDZrmkz */ >+ 0x156a, /* VPMOVZXBDZrrkz */ >+/* Table7097 */ >+ 0x1571, /* VPMOVZXBQZrmkz */ >+ 0x1574, /* VPMOVZXBQZrrkz */ >+/* Table7099 */ >+ 0x1589, /* VPMOVZXWDZrmkz */ >+ 0x158c, /* VPMOVZXWDZrrkz */ >+/* Table7101 */ >+ 0x1593, /* VPMOVZXWQZrmkz */ >+ 0x1596, /* VPMOVZXWQZrrkz */ >+/* Table7103 */ >+ 0x157f, /* VPMOVZXDQZrmkz */ >+ 0x1582, /* VPMOVZXDQZrrkz */ >+/* Table7105 */ >+ 0x14af, /* VPMINSDZrmkz */ >+ 0x14b2, /* VPMINSDZrrkz */ >+/* Table7107 */ >+ 0x14cd, /* VPMINUDZrmkz */ >+ 0x14d0, /* VPMINUDZrrkz */ >+/* Table7109 */ >+ 0x1473, /* VPMAXSDZrmkz */ >+ 0x1476, /* VPMAXSDZrrkz */ >+/* Table7111 */ >+ 0x1491, /* VPMAXUDZrmkz */ >+ 0x1494, /* VPMAXUDZrrkz */ >+/* Table7113 */ >+ 0x15b9, /* VPMULLDZrmkz */ >+ 0x15bc, /* VPMULLDZrrkz */ >+/* Table7115 */ >+ 0x1433, /* VPLZCNTDrmkz */ >+ 0x1436, /* VPLZCNTDrrkz */ >+/* Table7117 */ >+ 0x126f, /* VPBROADCASTDZkrm */ >+ 0x1270, /* VPBROADCASTDZkrr */ >+/* Table7119 */ >+ 0xbf3, /* VBROADCASTI32X4krm */ >+ 0x0, /* */ >+/* Table7121 */ >+ 0x137b, /* VPERMI2Drmkz */ >+ 0x137e, /* VPERMI2Drrkz */ >+/* Table7123 */ >+ 0x1387, /* VPERMI2PSrmkz */ >+ 0x138a, /* VPERMI2PSrrkz */ >+/* Table7125 */ >+ 0x0, /* */ >+ 0x1273, /* VPBROADCASTDrZkrr */ >+/* Table7127 */ >+ 0x13c3, /* VPERMT2Drmkz */ >+ 0x13c6, /* VPERMT2Drrkz */ >+/* Table7129 */ >+ 0x13cf, /* VPERMT2PSrmkz */ >+ 0x13d2, /* VPERMT2PSrrkz */ >+/* Table7131 */ >+ 0x0, /* */ >+ 0xd73, /* VFMADDSUB213PSZrkz */ >+/* Table7133 */ >+ 0x0, /* */ >+ 0xdb7, /* VFMSUBADD213PSZrkz */ >+/* Table7135 */ >+ 0x0, /* */ >+ 0xd1f, /* VFMADD213PSZrkz */ >+/* Table7137 */ >+ 0x0, /* */ >+ 0xda9, /* VFMSUB213PSZrkz */ >+/* Table7139 */ >+ 0x0, /* */ >+ 0xe33, /* VFNMADD213PSZrkz */ >+/* Table7141 */ >+ 0x0, /* */ >+ 0xe87, /* VFNMSUB213PSZrkz */ >+/* Table7143 */ >+ 0x1364, /* VPCONFLICTDrmkz */ >+ 0x1367, /* VPCONFLICTDrrkz */ >+/* Table7145 */ >+ 0x11d7, /* VPABSQZrmkz */ >+ 0x11da, /* VPABSQZrrkz */ >+/* Table7147 */ >+ 0x15a0, /* VPMULDQZrmkz */ >+ 0x15a3, /* VPMULDQZrrkz */ >+/* Table7149 */ >+ 0x14ba, /* VPMINSQZrmkz */ >+ 0x14bd, /* VPMINSQZrrkz */ >+/* Table7151 */ >+ 0x14d8, /* VPMINUQZrmkz */ >+ 0x14db, /* VPMINUQZrrkz */ >+/* Table7153 */ >+ 0x147e, /* VPMAXSQZrmkz */ >+ 0x1481, /* VPMAXSQZrrkz */ >+/* Table7155 */ >+ 0x149c, /* VPMAXUQZrmkz */ >+ 0x149f, /* VPMAXUQZrrkz */ >+/* Table7157 */ >+ 0x143c, /* VPLZCNTQrmkz */ >+ 0x143f, /* VPLZCNTQrrkz */ >+/* Table7159 */ >+ 0x127b, /* VPBROADCASTQZkrm */ >+ 0x127c, /* VPBROADCASTQZkrr */ >+/* Table7161 */ >+ 0xbf5, /* VBROADCASTI64X4krm */ >+ 0x0, /* */ >+/* Table7163 */ >+ 0x138d, /* VPERMI2Qrmkz */ >+ 0x1390, /* VPERMI2Qrrkz */ >+/* Table7165 */ >+ 0x1381, /* VPERMI2PDrmkz */ >+ 0x1384, /* VPERMI2PDrrkz */ >+/* Table7167 */ >+ 0x0, /* */ >+ 0x127f, /* VPBROADCASTQrZkrr */ >+/* Table7169 */ >+ 0x13d5, /* VPERMT2Qrmkz */ >+ 0x13d8, /* VPERMT2Qrrkz */ >+/* Table7171 */ >+ 0x13c9, /* VPERMT2PDrmkz */ >+ 0x13cc, /* VPERMT2PDrrkz */ >+/* Table7173 */ >+ 0x0, /* */ >+ 0xd6e, /* VFMADDSUB213PDZrkz */ >+/* Table7175 */ >+ 0x0, /* */ >+ 0xdb2, /* VFMSUBADD213PDZrkz */ >+/* Table7177 */ >+ 0x0, /* */ >+ 0xd1a, /* VFMADD213PDZrkz */ >+/* Table7179 */ >+ 0x0, /* */ >+ 0xda4, /* VFMSUB213PDZrkz */ >+/* Table7181 */ >+ 0x0, /* */ >+ 0xe2e, /* VFNMADD213PDZrkz */ >+/* Table7183 */ >+ 0x0, /* */ >+ 0xe82, /* VFNMSUB213PDZrkz */ >+/* Table7185 */ >+ 0x136d, /* VPCONFLICTQrmkz */ >+ 0x1370, /* VPCONFLICTQrrkz */ >+/* Table7187 */ >+ 0x59d, /* MMX_PALIGNR64irm */ >+ 0x59e, /* MMX_PALIGNR64irr */ >+/* Table7189 */ >+ 0xa2d, /* SHA1RNDS4rmi */ >+ 0xa2e, /* SHA1RNDS4rri */ >+/* Table7191 */ >+ 0x988, /* ROUNDPSm */ >+ 0x989, /* ROUNDPSr */ >+/* Table7193 */ >+ 0x986, /* ROUNDPDm */ >+ 0x987, /* ROUNDPDr */ >+/* Table7195 */ >+ 0x98d, /* ROUNDSSm */ >+ 0x98e, /* ROUNDSSr */ >+/* Table7197 */ >+ 0x98a, /* ROUNDSDm */ >+ 0x98b, /* ROUNDSDr */ >+/* Table7199 */ >+ 0xfd, /* BLENDPSrmi */ >+ 0xfe, /* BLENDPSrri */ >+/* Table7201 */ >+ 0xfb, /* BLENDPDrmi */ >+ 0xfc, /* BLENDPDrri */ >+/* Table7203 */ >+ 0x79c, /* PBLENDWrmi */ >+ 0x79d, /* PBLENDWrri */ >+/* Table7205 */ >+ 0x78d, /* PALIGNR128rm */ >+ 0x78e, /* PALIGNR128rr */ >+/* Table7207 */ >+ 0x7c8, /* PEXTRBmr */ >+ 0x7c9, /* PEXTRBrr */ >+/* Table7209 */ >+ 0x7ce, /* PEXTRWmr */ >+ 0x7d0, /* PEXTRWrr_REV */ >+/* Table7211 */ >+ 0x7ca, /* PEXTRDmr */ >+ 0x7cb, /* PEXTRDrr */ >+/* Table7213 */ >+ 0x2e5, /* EXTRACTPSmr */ >+ 0x2e6, /* EXTRACTPSrr */ >+/* Table7215 */ >+ 0x809, /* PINSRBrm */ >+ 0x80a, /* PINSRBrr */ >+/* Table7217 */ >+ 0x38f, /* INSERTPSrm */ >+ 0x390, /* INSERTPSrr */ >+/* Table7219 */ >+ 0x80b, /* PINSRDrm */ >+ 0x80c, /* PINSRDrr */ >+/* Table7221 */ >+ 0x2d9, /* DPPSrmi */ >+ 0x2da, /* DPPSrri */ >+/* Table7223 */ >+ 0x2d7, /* DPPDrmi */ >+ 0x2d8, /* DPPDrri */ >+/* Table7225 */ >+ 0x6de, /* MPSADBWrmi */ >+ 0x6df, /* MPSADBWrri */ >+/* Table7227 */ >+ 0x79e, /* PCLMULQDQrm */ >+ 0x79f, /* PCLMULQDQrr */ >+/* Table7229 */ >+ 0x7ae, /* PCMPESTRM128rm */ >+ 0x7af, /* PCMPESTRM128rr */ >+/* Table7231 */ >+ 0x7aa, /* PCMPESTRIrm */ >+ 0x7ab, /* PCMPESTRIrr */ >+/* Table7233 */ >+ 0x7be, /* PCMPISTRM128rm */ >+ 0x7bf, /* PCMPISTRM128rr */ >+/* Table7235 */ >+ 0x7ba, /* PCMPISTRIrm */ >+ 0x7bb, /* PCMPISTRIrr */ >+/* Table7237 */ >+ 0xa9, /* AESKEYGENASSIST128rm */ >+ 0xaa, /* AESKEYGENASSIST128rr */ >+/* Table7239 */ >+ 0x7cc, /* PEXTRQmr */ >+ 0x7cd, /* PEXTRQrr */ >+/* Table7241 */ >+ 0x80d, /* PINSRQrm */ >+ 0x80e, /* PINSRQrr */ >+/* Table7243 */ >+ 0x982, /* RORX32mi */ >+ 0x983, /* RORX32ri */ >+/* Table7245 */ >+ 0x125b, /* VPBLENDDrmi */ >+ 0x125c, /* VPBLENDDrri */ >+/* Table7247 */ >+ 0x13ad, /* VPERMILPSmi */ >+ 0x13ae, /* VPERMILPSri */ >+/* Table7249 */ >+ 0x13a3, /* VPERMILPDmi */ >+ 0x13a4, /* VPERMILPDri */ >+/* Table7251 */ >+ 0x1764, /* VROUNDPSm */ >+ 0x1765, /* VROUNDPSr */ >+/* Table7253 */ >+ 0x1762, /* VROUNDPDm */ >+ 0x1763, /* VROUNDPDr */ >+/* Table7255 */ >+ 0x1769, /* VROUNDSSm */ >+ 0x176a, /* VROUNDSSr */ >+/* Table7257 */ >+ 0x1766, /* VROUNDSDm */ >+ 0x1767, /* VROUNDSDr */ >+/* Table7259 */ >+ 0xbe7, /* VBLENDPSrmi */ >+ 0xbe8, /* VBLENDPSrri */ >+/* Table7261 */ >+ 0xbe3, /* VBLENDPDrmi */ >+ 0xbe4, /* VBLENDPDrri */ >+/* Table7263 */ >+ 0x1267, /* VPBLENDWrmi */ >+ 0x1268, /* VPBLENDWrri */ >+/* Table7265 */ >+ 0x1221, /* VPALIGNR128rm */ >+ 0x1222, /* VPALIGNR128rr */ >+/* Table7267 */ >+ 0x13d9, /* VPEXTRBmr */ >+ 0x13da, /* VPEXTRBrr */ >+/* Table7269 */ >+ 0x13df, /* VPEXTRWmr */ >+ 0x13e1, /* VPEXTRWrr_REV */ >+/* Table7271 */ >+ 0x13db, /* VPEXTRDmr */ >+ 0x13dc, /* VPEXTRDrr */ >+/* Table7273 */ >+ 0xd0e, /* VEXTRACTPSmr */ >+ 0xd0f, /* VEXTRACTPSrr */ >+/* Table7275 */ >+ 0xc68, /* VCVTPS2PHmr */ >+ 0xc69, /* VCVTPS2PHrr */ >+/* Table7277 */ >+ 0x1426, /* VPINSRBrm */ >+ 0x1427, /* VPINSRBrr */ >+/* Table7279 */ >+ 0xf1a, /* VINSERTPSrm */ >+ 0xf1b, /* VINSERTPSrr */ >+/* Table7281 */ >+ 0x1428, /* VPINSRDrm */ >+ 0x1429, /* VPINSRDrr */ >+/* Table7283 */ >+ 0xcfc, /* VDPPSrmi */ >+ 0xcfd, /* VDPPSrri */ >+/* Table7285 */ >+ 0xcf8, /* VDPPDrmi */ >+ 0xcf9, /* VDPPDrri */ >+/* Table7287 */ >+ 0x1180, /* VMPSADBWrmi */ >+ 0x1181, /* VMPSADBWrri */ >+/* Table7289 */ >+ 0x1287, /* VPCLMULQDQrm */ >+ 0x1288, /* VPCLMULQDQrr */ >+/* Table7291 */ >+ 0x1397, /* VPERMIL2PSmr */ >+ 0x139b, /* VPERMIL2PSrr */ >+/* Table7293 */ >+ 0x1391, /* VPERMIL2PDmr */ >+ 0x1395, /* VPERMIL2PDrr */ >+/* Table7295 */ >+ 0xbef, /* VBLENDVPSrm */ >+ 0xbf0, /* VBLENDVPSrr */ >+/* Table7297 */ >+ 0xbeb, /* VBLENDVPDrm */ >+ 0xbec, /* VBLENDVPDrr */ >+/* Table7299 */ >+ 0x1263, /* VPBLENDVBrm */ >+ 0x1264, /* VPBLENDVBrr */ >+/* Table7301 */ >+ 0xd88, /* VFMADDSUBPS4mr */ >+ 0xd8f, /* VFMADDSUBPS4rr_REV */ >+/* Table7303 */ >+ 0xd74, /* VFMADDSUBPD4mr */ >+ 0xd7b, /* VFMADDSUBPD4rr_REV */ >+/* Table7305 */ >+ 0xdcc, /* VFMSUBADDPS4mr */ >+ 0xdd3, /* VFMSUBADDPS4rr_REV */ >+/* Table7307 */ >+ 0xdb8, /* VFMSUBADDPD4mr */ >+ 0xdbf, /* VFMSUBADDPD4rr_REV */ >+/* Table7309 */ >+ 0x12e7, /* VPCMPESTRM128rm */ >+ 0x12e8, /* VPCMPESTRM128rr */ >+/* Table7311 */ >+ 0x12e3, /* VPCMPESTRIrm */ >+ 0x12e4, /* VPCMPESTRIrr */ >+/* Table7313 */ >+ 0x133b, /* VPCMPISTRM128rm */ >+ 0x133c, /* VPCMPISTRM128rr */ >+/* Table7315 */ >+ 0x1337, /* VPCMPISTRIrm */ >+ 0x1338, /* VPCMPISTRIrr */ >+/* Table7317 */ >+ 0xd34, /* VFMADDPS4mr */ >+ 0xd3b, /* VFMADDPS4rr_REV */ >+/* Table7319 */ >+ 0xd20, /* VFMADDPD4mr */ >+ 0xd27, /* VFMADDPD4rr_REV */ >+/* Table7321 */ >+ 0xd57, /* VFMADDSS4mr */ >+ 0xd5d, /* VFMADDSS4rr_REV */ >+/* Table7323 */ >+ 0xd48, /* VFMADDSD4mr */ >+ 0xd4e, /* VFMADDSD4rr_REV */ >+/* Table7325 */ >+ 0xdf4, /* VFMSUBPS4mr */ >+ 0xdfb, /* VFMSUBPS4rr_REV */ >+/* Table7327 */ >+ 0xde0, /* VFMSUBPD4mr */ >+ 0xde7, /* VFMSUBPD4rr_REV */ >+/* Table7329 */ >+ 0xe17, /* VFMSUBSS4mr */ >+ 0xe1d, /* VFMSUBSS4rr_REV */ >+/* Table7331 */ >+ 0xe08, /* VFMSUBSD4mr */ >+ 0xe0e, /* VFMSUBSD4rr_REV */ >+/* Table7333 */ >+ 0xe48, /* VFNMADDPS4mr */ >+ 0xe4f, /* VFNMADDPS4rr_REV */ >+/* Table7335 */ >+ 0xe34, /* VFNMADDPD4mr */ >+ 0xe3b, /* VFNMADDPD4rr_REV */ >+/* Table7337 */ >+ 0xe6b, /* VFNMADDSS4mr */ >+ 0xe71, /* VFNMADDSS4rr_REV */ >+/* Table7339 */ >+ 0xe5c, /* VFNMADDSD4mr */ >+ 0xe62, /* VFNMADDSD4rr_REV */ >+/* Table7341 */ >+ 0xe9c, /* VFNMSUBPS4mr */ >+ 0xea3, /* VFNMSUBPS4rr_REV */ >+/* Table7343 */ >+ 0xe88, /* VFNMSUBPD4mr */ >+ 0xe8f, /* VFNMSUBPD4rr_REV */ >+/* Table7345 */ >+ 0xebf, /* VFNMSUBSS4mr */ >+ 0xec5, /* VFNMSUBSS4rr_REV */ >+/* Table7347 */ >+ 0xeb0, /* VFNMSUBSD4mr */ >+ 0xeb6, /* VFNMSUBSD4rr_REV */ >+/* Table7349 */ >+ 0xbc2, /* VAESKEYGENASSIST128rm */ >+ 0xbc3, /* VAESKEYGENASSIST128rr */ >+/* Table7351 */ >+ 0x984, /* RORX64mi */ >+ 0x985, /* RORX64ri */ >+/* Table7353 */ >+ 0x13dd, /* VPEXTRQmr */ >+ 0x13de, /* VPEXTRQrr */ >+/* Table7355 */ >+ 0x142a, /* VPINSRQrm */ >+ 0x142b, /* VPINSRQrr */ >+/* Table7357 */ >+ 0x0, /* */ >+ 0x490, /* KSHIFTRWri */ >+/* Table7359 */ >+ 0x0, /* */ >+ 0x48f, /* KSHIFTLWri */ >+/* Table7361 */ >+ 0x1399, /* VPERMIL2PSrm */ >+ 0x139b, /* VPERMIL2PSrr */ >+/* Table7363 */ >+ 0x1393, /* VPERMIL2PDrm */ >+ 0x1395, /* VPERMIL2PDrr */ >+/* Table7365 */ >+ 0xd8a, /* VFMADDSUBPS4rm */ >+ 0xd8c, /* VFMADDSUBPS4rr */ >+/* Table7367 */ >+ 0xd76, /* VFMADDSUBPD4rm */ >+ 0xd78, /* VFMADDSUBPD4rr */ >+/* Table7369 */ >+ 0xdce, /* VFMSUBADDPS4rm */ >+ 0xdd0, /* VFMSUBADDPS4rr */ >+/* Table7371 */ >+ 0xdba, /* VFMSUBADDPD4rm */ >+ 0xdbc, /* VFMSUBADDPD4rr */ >+/* Table7373 */ >+ 0xd36, /* VFMADDPS4rm */ >+ 0xd38, /* VFMADDPS4rr */ >+/* Table7375 */ >+ 0xd22, /* VFMADDPD4rm */ >+ 0xd24, /* VFMADDPD4rr */ >+/* Table7377 */ >+ 0xd59, /* VFMADDSS4rm */ >+ 0xd5b, /* VFMADDSS4rr */ >+/* Table7379 */ >+ 0xd4a, /* VFMADDSD4rm */ >+ 0xd4c, /* VFMADDSD4rr */ >+/* Table7381 */ >+ 0xdf6, /* VFMSUBPS4rm */ >+ 0xdf8, /* VFMSUBPS4rr */ >+/* Table7383 */ >+ 0xde2, /* VFMSUBPD4rm */ >+ 0xde4, /* VFMSUBPD4rr */ >+/* Table7385 */ >+ 0xe19, /* VFMSUBSS4rm */ >+ 0xe1b, /* VFMSUBSS4rr */ >+/* Table7387 */ >+ 0xe0a, /* VFMSUBSD4rm */ >+ 0xe0c, /* VFMSUBSD4rr */ >+/* Table7389 */ >+ 0xe4a, /* VFNMADDPS4rm */ >+ 0xe4c, /* VFNMADDPS4rr */ >+/* Table7391 */ >+ 0xe36, /* VFNMADDPD4rm */ >+ 0xe38, /* VFNMADDPD4rr */ >+/* Table7393 */ >+ 0xe6d, /* VFNMADDSS4rm */ >+ 0xe6f, /* VFNMADDSS4rr */ >+/* Table7395 */ >+ 0xe5e, /* VFNMADDSD4rm */ >+ 0xe60, /* VFNMADDSD4rr */ >+/* Table7397 */ >+ 0xe9e, /* VFNMSUBPS4rm */ >+ 0xea0, /* VFNMSUBPS4rr */ >+/* Table7399 */ >+ 0xe8a, /* VFNMSUBPD4rm */ >+ 0xe8c, /* VFNMSUBPD4rr */ >+/* Table7401 */ >+ 0xec1, /* VFNMSUBSS4rm */ >+ 0xec3, /* VFNMSUBSS4rr */ >+/* Table7403 */ >+ 0xeb2, /* VFNMSUBSD4rm */ >+ 0xeb4, /* VFNMSUBSD4rr */ >+/* Table7405 */ >+ 0x1259, /* VPBLENDDYrmi */ >+ 0x125a, /* VPBLENDDYrri */ >+/* Table7407 */ >+ 0x13a7, /* VPERMILPSYmi */ >+ 0x13a8, /* VPERMILPSYri */ >+/* Table7409 */ >+ 0x139d, /* VPERMILPDYmi */ >+ 0x139e, /* VPERMILPDYri */ >+/* Table7411 */ >+ 0x1371, /* VPERM2F128rm */ >+ 0x1372, /* VPERM2F128rr */ >+/* Table7413 */ >+ 0x176e, /* VROUNDYPSm */ >+ 0x176f, /* VROUNDYPSr */ >+/* Table7415 */ >+ 0x176c, /* VROUNDYPDm */ >+ 0x176d, /* VROUNDYPDr */ >+/* Table7417 */ >+ 0xbe5, /* VBLENDPSYrmi */ >+ 0xbe6, /* VBLENDPSYrri */ >+/* Table7419 */ >+ 0xbe1, /* VBLENDPDYrmi */ >+ 0xbe2, /* VBLENDPDYrri */ >+/* Table7421 */ >+ 0x1265, /* VPBLENDWYrmi */ >+ 0x1266, /* VPBLENDWYrri */ >+/* Table7423 */ >+ 0x1223, /* VPALIGNR256rm */ >+ 0x1224, /* VPALIGNR256rr */ >+/* Table7425 */ >+ 0xf0e, /* VINSERTF128rm */ >+ 0xf0f, /* VINSERTF128rr */ >+/* Table7427 */ >+ 0xd02, /* VEXTRACTF128mr */ >+ 0xd03, /* VEXTRACTF128rr */ >+/* Table7429 */ >+ 0xc64, /* VCVTPS2PHYmr */ >+ 0xc65, /* VCVTPS2PHYrr */ >+/* Table7431 */ >+ 0xf14, /* VINSERTI128rm */ >+ 0xf15, /* VINSERTI128rr */ >+/* Table7433 */ >+ 0xd08, /* VEXTRACTI128mr */ >+ 0xd09, /* VEXTRACTI128rr */ >+/* Table7435 */ >+ 0xcfa, /* VDPPSYrmi */ >+ 0xcfb, /* VDPPSYrri */ >+/* Table7437 */ >+ 0x117e, /* VMPSADBWYrmi */ >+ 0x117f, /* VMPSADBWYrri */ >+/* Table7439 */ >+ 0x1373, /* VPERM2I128rm */ >+ 0x1374, /* VPERM2I128rr */ >+/* Table7441 */ >+ 0x1398, /* VPERMIL2PSmrY */ >+ 0x139c, /* VPERMIL2PSrrY */ >+/* Table7443 */ >+ 0x1392, /* VPERMIL2PDmrY */ >+ 0x1396, /* VPERMIL2PDrrY */ >+/* Table7445 */ >+ 0xbed, /* VBLENDVPSYrm */ >+ 0xbee, /* VBLENDVPSYrr */ >+/* Table7447 */ >+ 0xbe9, /* VBLENDVPDYrm */ >+ 0xbea, /* VBLENDVPDYrr */ >+/* Table7449 */ >+ 0x1261, /* VPBLENDVBYrm */ >+ 0x1262, /* VPBLENDVBYrr */ >+/* Table7451 */ >+ 0xd89, /* VFMADDSUBPS4mrY */ >+ 0xd8e, /* VFMADDSUBPS4rrY_REV */ >+/* Table7453 */ >+ 0xd75, /* VFMADDSUBPD4mrY */ >+ 0xd7a, /* VFMADDSUBPD4rrY_REV */ >+/* Table7455 */ >+ 0xdcd, /* VFMSUBADDPS4mrY */ >+ 0xdd2, /* VFMSUBADDPS4rrY_REV */ >+/* Table7457 */ >+ 0xdb9, /* VFMSUBADDPD4mrY */ >+ 0xdbe, /* VFMSUBADDPD4rrY_REV */ >+/* Table7459 */ >+ 0xd35, /* VFMADDPS4mrY */ >+ 0xd3a, /* VFMADDPS4rrY_REV */ >+/* Table7461 */ >+ 0xd21, /* VFMADDPD4mrY */ >+ 0xd26, /* VFMADDPD4rrY_REV */ >+/* Table7463 */ >+ 0xdf5, /* VFMSUBPS4mrY */ >+ 0xdfa, /* VFMSUBPS4rrY_REV */ >+/* Table7465 */ >+ 0xde1, /* VFMSUBPD4mrY */ >+ 0xde6, /* VFMSUBPD4rrY_REV */ >+/* Table7467 */ >+ 0xe49, /* VFNMADDPS4mrY */ >+ 0xe4e, /* VFNMADDPS4rrY_REV */ >+/* Table7469 */ >+ 0xe35, /* VFNMADDPD4mrY */ >+ 0xe3a, /* VFNMADDPD4rrY_REV */ >+/* Table7471 */ >+ 0xe9d, /* VFNMSUBPS4mrY */ >+ 0xea2, /* VFNMSUBPS4rrY_REV */ >+/* Table7473 */ >+ 0xe89, /* VFNMSUBPD4mrY */ >+ 0xe8e, /* VFNMSUBPD4rrY_REV */ >+/* Table7475 */ >+ 0x13bb, /* VPERMQYmi */ >+ 0x13bc, /* VPERMQYri */ >+/* Table7477 */ >+ 0x13b1, /* VPERMPDYmi */ >+ 0x13b2, /* VPERMPDYri */ >+/* Table7479 */ >+ 0x139a, /* VPERMIL2PSrmY */ >+ 0x139c, /* VPERMIL2PSrrY */ >+/* Table7481 */ >+ 0x1394, /* VPERMIL2PDrmY */ >+ 0x1396, /* VPERMIL2PDrrY */ >+/* Table7483 */ >+ 0xd8b, /* VFMADDSUBPS4rmY */ >+ 0xd8d, /* VFMADDSUBPS4rrY */ >+/* Table7485 */ >+ 0xd77, /* VFMADDSUBPD4rmY */ >+ 0xd79, /* VFMADDSUBPD4rrY */ >+/* Table7487 */ >+ 0xdcf, /* VFMSUBADDPS4rmY */ >+ 0xdd1, /* VFMSUBADDPS4rrY */ >+/* Table7489 */ >+ 0xdbb, /* VFMSUBADDPD4rmY */ >+ 0xdbd, /* VFMSUBADDPD4rrY */ >+/* Table7491 */ >+ 0xd37, /* VFMADDPS4rmY */ >+ 0xd39, /* VFMADDPS4rrY */ >+/* Table7493 */ >+ 0xd23, /* VFMADDPD4rmY */ >+ 0xd25, /* VFMADDPD4rrY */ >+/* Table7495 */ >+ 0xdf7, /* VFMSUBPS4rmY */ >+ 0xdf9, /* VFMSUBPS4rrY */ >+/* Table7497 */ >+ 0xde3, /* VFMSUBPD4rmY */ >+ 0xde5, /* VFMSUBPD4rrY */ >+/* Table7499 */ >+ 0xe4b, /* VFNMADDPS4rmY */ >+ 0xe4d, /* VFNMADDPS4rrY */ >+/* Table7501 */ >+ 0xe37, /* VFNMADDPD4rmY */ >+ 0xe39, /* VFNMADDPD4rrY */ >+/* Table7503 */ >+ 0xe9f, /* VFNMSUBPS4rmY */ >+ 0xea1, /* VFNMSUBPS4rrY */ >+/* Table7505 */ >+ 0xe8b, /* VFNMSUBPD4rmY */ >+ 0xe8d, /* VFNMSUBPD4rrY */ >+/* Table7507 */ >+ 0x1760, /* VRNDSCALESSm */ >+ 0x1761, /* VRNDSCALESSr */ >+/* Table7509 */ >+ 0x175e, /* VRNDSCALESDm */ >+ 0x175f, /* VRNDSCALESDr */ >+/* Table7511 */ >+ 0xd10, /* VEXTRACTPSzmr */ >+ 0xd11, /* VEXTRACTPSzrr */ >+/* Table7513 */ >+ 0xf1c, /* VINSERTPSzrm */ >+ 0xf1d, /* VINSERTPSzrr */ >+/* Table7515 */ >+ 0xbc4, /* VALIGNDrmi */ >+ 0xbc5, /* VALIGNDrri */ >+/* Table7517 */ >+ 0x13ab, /* VPERMILPSZmi */ >+ 0x13ac, /* VPERMILPSZri */ >+/* Table7519 */ >+ 0x175c, /* VRNDSCALEPSZm */ >+ 0x175d, /* VRNDSCALEPSZr */ >+/* Table7521 */ >+ 0xf10, /* VINSERTF32x4rm */ >+ 0xf11, /* VINSERTF32x4rr */ >+/* Table7523 */ >+ 0xd04, /* VEXTRACTF32x4mr */ >+ 0xd05, /* VEXTRACTF32x4rr */ >+/* Table7525 */ >+ 0xc66, /* VCVTPS2PHZmr */ >+ 0xc67, /* VCVTPS2PHZrr */ >+/* Table7527 */ >+ 0x1343, /* VPCMPUDZrmi */ >+ 0x1346, /* VPCMPUDZrri */ >+/* Table7529 */ >+ 0x128f, /* VPCMPDZrmi */ >+ 0x1292, /* VPCMPDZrri */ >+/* Table7531 */ >+ 0xf16, /* VINSERTI32x4rm */ >+ 0xf17, /* VINSERTI32x4rr */ >+/* Table7533 */ >+ 0xd0a, /* VEXTRACTI32x4mr */ >+ 0xd0b, /* VEXTRACTI32x4rr */ >+/* Table7535 */ >+ 0x13bd, /* VPERMQZmi */ >+ 0x13be, /* VPERMQZri */ >+/* Table7537 */ >+ 0x13b3, /* VPERMPDZmi */ >+ 0x13b4, /* VPERMPDZri */ >+/* Table7539 */ >+ 0xbc8, /* VALIGNQrmi */ >+ 0xbc9, /* VALIGNQrri */ >+/* Table7541 */ >+ 0x13a1, /* VPERMILPDZmi */ >+ 0x13a2, /* VPERMILPDZri */ >+/* Table7543 */ >+ 0x175a, /* VRNDSCALEPDZm */ >+ 0x175b, /* VRNDSCALEPDZr */ >+/* Table7545 */ >+ 0xf12, /* VINSERTF64x4rm */ >+ 0xf13, /* VINSERTF64x4rr */ >+/* Table7547 */ >+ 0xd06, /* VEXTRACTF64x4mr */ >+ 0xd07, /* VEXTRACTF64x4rr */ >+/* Table7549 */ >+ 0x1349, /* VPCMPUQZrmi */ >+ 0x134c, /* VPCMPUQZrri */ >+/* Table7551 */ >+ 0x133d, /* VPCMPQZrmi */ >+ 0x1340, /* VPCMPQZrri */ >+/* Table7553 */ >+ 0xf18, /* VINSERTI64x4rm */ >+ 0xf19, /* VINSERTI64x4rr */ >+/* Table7555 */ >+ 0xd0c, /* VEXTRACTI64x4mr */ >+ 0xd0d, /* VEXTRACTI64x4rr */ >+/* Table7557 */ >+ 0x0, /* */ >+ 0xbc6, /* VALIGNDrrik */ >+/* Table7559 */ >+ 0x0, /* */ >+ 0xbca, /* VALIGNQrrik */ >+/* Table7561 */ >+ 0x0, /* */ >+ 0xbc7, /* VALIGNDrrikz */ >+/* Table7563 */ >+ 0x0, /* */ >+ 0xbcb, /* VALIGNQrrikz */ >+/* Table7565 */ >+ 0x144e, /* VPMACSSWWrm */ >+ 0x144f, /* VPMACSSWWrr */ >+/* Table7567 */ >+ 0x144c, /* VPMACSSWDrm */ >+ 0x144d, /* VPMACSSWDrr */ >+/* Table7569 */ >+ 0x144a, /* VPMACSSDQLrm */ >+ 0x144b, /* VPMACSSDQLrr */ >+/* Table7571 */ >+ 0x1446, /* VPMACSSDDrm */ >+ 0x1447, /* VPMACSSDDrr */ >+/* Table7573 */ >+ 0x1448, /* VPMACSSDQHrm */ >+ 0x1449, /* VPMACSSDQHrr */ >+/* Table7575 */ >+ 0x1452, /* VPMACSWWrm */ >+ 0x1453, /* VPMACSWWrr */ >+/* Table7577 */ >+ 0x1450, /* VPMACSWDrm */ >+ 0x1451, /* VPMACSWDrr */ >+/* Table7579 */ >+ 0x1444, /* VPMACSDQLrm */ >+ 0x1445, /* VPMACSDQLrr */ >+/* Table7581 */ >+ 0x1440, /* VPMACSDDrm */ >+ 0x1441, /* VPMACSDDrr */ >+/* Table7583 */ >+ 0x1442, /* VPMACSDQHrm */ >+ 0x1443, /* VPMACSDQHrr */ >+/* Table7585 */ >+ 0x1289, /* VPCMOVmr */ >+ 0x128d, /* VPCMOVrr */ >+/* Table7587 */ >+ 0x15e6, /* VPPERMmr */ >+ 0x15e8, /* VPPERMrr */ >+/* Table7589 */ >+ 0x1454, /* VPMADCSSWDrm */ >+ 0x1455, /* VPMADCSSWDrr */ >+/* Table7591 */ >+ 0x1456, /* VPMADCSWDrm */ >+ 0x1457, /* VPMADCSWDrr */ >+/* Table7593 */ >+ 0x15e9, /* VPROTBmi */ >+ 0x15eb, /* VPROTBri */ >+/* Table7595 */ >+ 0x15f8, /* VPROTWmi */ >+ 0x15fa, /* VPROTWri */ >+/* Table7597 */ >+ 0x15ee, /* VPROTDmi */ >+ 0x15f0, /* VPROTDri */ >+/* Table7599 */ >+ 0x15f3, /* VPROTQmi */ >+ 0x15f5, /* VPROTQri */ >+/* Table7601 */ >+ 0x134f, /* VPCOMBmi */ >+ 0x1350, /* VPCOMBri */ >+/* Table7603 */ >+ 0x135d, /* VPCOMWmi */ >+ 0x135e, /* VPCOMWri */ >+/* Table7605 */ >+ 0x1351, /* VPCOMDmi */ >+ 0x1352, /* VPCOMDri */ >+/* Table7607 */ >+ 0x1353, /* VPCOMQmi */ >+ 0x1354, /* VPCOMQri */ >+/* Table7609 */ >+ 0x1355, /* VPCOMUBmi */ >+ 0x1356, /* VPCOMUBri */ >+/* Table7611 */ >+ 0x135b, /* VPCOMUWmi */ >+ 0x135c, /* VPCOMUWri */ >+/* Table7613 */ >+ 0x1357, /* VPCOMUDmi */ >+ 0x1358, /* VPCOMUDri */ >+/* Table7615 */ >+ 0x1359, /* VPCOMUQmi */ >+ 0x135a, /* VPCOMUQri */ >+/* Table7617 */ >+ 0x128b, /* VPCMOVrm */ >+ 0x128d, /* VPCMOVrr */ >+/* Table7619 */ >+ 0x15e7, /* VPPERMrm */ >+ 0x15e8, /* VPPERMrr */ >+/* Table7621 */ >+ 0x128a, /* VPCMOVmrY */ >+ 0x128e, /* VPCMOVrrY */ >+/* Table7623 */ >+ 0x128c, /* VPCMOVrmY */ >+ 0x128e, /* VPCMOVrrY */ >+/* Table7625 */ >+ 0x0, /* */ >+ 0xe7, /* BLCFILL32rm */ >+ 0x103, /* BLSFILL32rm */ >+ 0xf7, /* BLCS32rm */ >+ 0xb6d, /* TZMSK32rm */ >+ 0xef, /* BLCIC32rm */ >+ 0x10b, /* BLSIC32rm */ >+ 0xb2f, /* T1MSKC32rm */ >+ 0x0, /* */ >+ 0xe8, /* BLCFILL32rr */ >+ 0x104, /* BLSFILL32rr */ >+ 0xf8, /* BLCS32rr */ >+ 0xb6e, /* TZMSK32rr */ >+ 0xf0, /* BLCIC32rr */ >+ 0x10c, /* BLSIC32rr */ >+ 0xb30, /* T1MSKC32rr */ >+/* Table7641 */ >+ 0x0, /* */ >+ 0xf3, /* BLCMSK32rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xeb, /* BLCI32rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf4, /* BLCMSK32rr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xec, /* BLCI32rr */ >+ 0x0, /* */ >+/* Table7657 */ >+ 0xed2, /* VFRCZPSrm */ >+ 0xed4, /* VFRCZPSrr */ >+/* Table7659 */ >+ 0xece, /* VFRCZPDrm */ >+ 0xed0, /* VFRCZPDrr */ >+/* Table7661 */ >+ 0xed8, /* VFRCZSSrm */ >+ 0xed9, /* VFRCZSSrr */ >+/* Table7663 */ >+ 0xed6, /* VFRCZSDrm */ >+ 0xed7, /* VFRCZSDrr */ >+/* Table7665 */ >+ 0x15ea, /* VPROTBmr */ >+ 0x15ed, /* VPROTBrr */ >+/* Table7667 */ >+ 0x15f9, /* VPROTWmr */ >+ 0x15fc, /* VPROTWrr */ >+/* Table7669 */ >+ 0x15ef, /* VPROTDmr */ >+ 0x15f2, /* VPROTDrr */ >+/* Table7671 */ >+ 0x15f4, /* VPROTQmr */ >+ 0x15f7, /* VPROTQrr */ >+/* Table7673 */ >+ 0x1611, /* VPSHLBmr */ >+ 0x1613, /* VPSHLBrr */ >+/* Table7675 */ >+ 0x161a, /* VPSHLWmr */ >+ 0x161c, /* VPSHLWrr */ >+/* Table7677 */ >+ 0x1614, /* VPSHLDmr */ >+ 0x1616, /* VPSHLDrr */ >+/* Table7679 */ >+ 0x1617, /* VPSHLQmr */ >+ 0x1619, /* VPSHLQrr */ >+/* Table7681 */ >+ 0x1605, /* VPSHABmr */ >+ 0x1607, /* VPSHABrr */ >+/* Table7683 */ >+ 0x160e, /* VPSHAWmr */ >+ 0x1610, /* VPSHAWrr */ >+/* Table7685 */ >+ 0x1608, /* VPSHADmr */ >+ 0x160a, /* VPSHADrr */ >+/* Table7687 */ >+ 0x160b, /* VPSHAQmr */ >+ 0x160d, /* VPSHAQrr */ >+/* Table7689 */ >+ 0x13f2, /* VPHADDBWrm */ >+ 0x13f3, /* VPHADDBWrr */ >+/* Table7691 */ >+ 0x13ee, /* VPHADDBDrm */ >+ 0x13ef, /* VPHADDBDrr */ >+/* Table7693 */ >+ 0x13f0, /* VPHADDBQrm */ >+ 0x13f1, /* VPHADDBQrr */ >+/* Table7695 */ >+ 0x140a, /* VPHADDWDrm */ >+ 0x140b, /* VPHADDWDrr */ >+/* Table7697 */ >+ 0x140c, /* VPHADDWQrm */ >+ 0x140d, /* VPHADDWQrr */ >+/* Table7699 */ >+ 0x13f4, /* VPHADDDQrm */ >+ 0x13f5, /* VPHADDDQrr */ >+/* Table7701 */ >+ 0x1402, /* VPHADDUBWrm */ >+ 0x1403, /* VPHADDUBWrr */ >+/* Table7703 */ >+ 0x13fe, /* VPHADDUBDrm */ >+ 0x13ff, /* VPHADDUBDrr */ >+/* Table7705 */ >+ 0x1400, /* VPHADDUBQrm */ >+ 0x1401, /* VPHADDUBQrr */ >+/* Table7707 */ >+ 0x1406, /* VPHADDUWDrm */ >+ 0x1407, /* VPHADDUWDrr */ >+/* Table7709 */ >+ 0x1408, /* VPHADDUWQrm */ >+ 0x1409, /* VPHADDUWQrr */ >+/* Table7711 */ >+ 0x1404, /* VPHADDUDQrm */ >+ 0x1405, /* VPHADDUDQrr */ >+/* Table7713 */ >+ 0x1414, /* VPHSUBBWrm */ >+ 0x1415, /* VPHSUBBWrr */ >+/* Table7715 */ >+ 0x1420, /* VPHSUBWDrm */ >+ 0x1421, /* VPHSUBWDrr */ >+/* Table7717 */ >+ 0x1416, /* VPHSUBDQrm */ >+ 0x1417, /* VPHSUBDQrr */ >+/* Table7719 */ >+ 0x0, /* */ >+ 0xe9, /* BLCFILL64rm */ >+ 0x105, /* BLSFILL64rm */ >+ 0xf9, /* BLCS64rm */ >+ 0xb6f, /* TZMSK64rm */ >+ 0xf1, /* BLCIC64rm */ >+ 0x10d, /* BLSIC64rm */ >+ 0xb31, /* T1MSKC64rm */ >+ 0x0, /* */ >+ 0xea, /* BLCFILL64rr */ >+ 0x106, /* BLSFILL64rr */ >+ 0xfa, /* BLCS64rr */ >+ 0xb70, /* TZMSK64rr */ >+ 0xf2, /* BLCIC64rr */ >+ 0x10e, /* BLSIC64rr */ >+ 0xb32, /* T1MSKC64rr */ >+/* Table7735 */ >+ 0x0, /* */ >+ 0xf5, /* BLCMSK64rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xed, /* BLCI64rm */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xf6, /* BLCMSK64rr */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0xee, /* BLCI64rr */ >+ 0x0, /* */ >+/* Table7751 */ >+ 0x15ec, /* VPROTBrm */ >+ 0x15ed, /* VPROTBrr */ >+/* Table7753 */ >+ 0x15fb, /* VPROTWrm */ >+ 0x15fc, /* VPROTWrr */ >+/* Table7755 */ >+ 0x15f1, /* VPROTDrm */ >+ 0x15f2, /* VPROTDrr */ >+/* Table7757 */ >+ 0x15f6, /* VPROTQrm */ >+ 0x15f7, /* VPROTQrr */ >+/* Table7759 */ >+ 0x1612, /* VPSHLBrm */ >+ 0x1613, /* VPSHLBrr */ >+/* Table7761 */ >+ 0x161b, /* VPSHLWrm */ >+ 0x161c, /* VPSHLWrr */ >+/* Table7763 */ >+ 0x1615, /* VPSHLDrm */ >+ 0x1616, /* VPSHLDrr */ >+/* Table7765 */ >+ 0x1618, /* VPSHLQrm */ >+ 0x1619, /* VPSHLQrr */ >+/* Table7767 */ >+ 0x1606, /* VPSHABrm */ >+ 0x1607, /* VPSHABrr */ >+/* Table7769 */ >+ 0x160f, /* VPSHAWrm */ >+ 0x1610, /* VPSHAWrr */ >+/* Table7771 */ >+ 0x1609, /* VPSHADrm */ >+ 0x160a, /* VPSHADrr */ >+/* Table7773 */ >+ 0x160c, /* VPSHAQrm */ >+ 0x160d, /* VPSHAQrr */ >+/* Table7775 */ >+ 0xed3, /* VFRCZPSrmY */ >+ 0xed5, /* VFRCZPSrrY */ >+/* Table7777 */ >+ 0xecf, /* VFRCZPDrmY */ >+ 0xed1, /* VFRCZPDrrY */ >+/* Table7779 */ >+ 0xe3, /* BEXTRI32mi */ >+ 0xe4, /* BEXTRI32ri */ >+/* Table7781 */ >+ 0xe5, /* BEXTRI64mi */ >+ 0xe6, /* BEXTRI64ri */ >+/* Table7783 */ >+ 0x878, /* PREFETCH */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+ 0x0, /* */ >+/* Table7799 */ >+ 0x2fc, /* FEMMS */ >+/* Table7800 */ >+ 0x807, /* PI2FWrm */ >+ 0x808, /* PI2FWrr */ >+/* Table7802 */ >+ 0x805, /* PI2FDrm */ >+ 0x806, /* PI2FDrr */ >+/* Table7804 */ >+ 0x7d3, /* PF2IWrm */ >+ 0x7d4, /* PF2IWrr */ >+/* Table7806 */ >+ 0x7d1, /* PF2IDrm */ >+ 0x7d2, /* PF2IDrr */ >+/* Table7808 */ >+ 0x7e5, /* PFNACCrm */ >+ 0x7e6, /* PFNACCrr */ >+/* Table7810 */ >+ 0x7e7, /* PFPNACCrm */ >+ 0x7e8, /* PFPNACCrr */ >+/* Table7812 */ >+ 0x7db, /* PFCMPGErm */ >+ 0x7dc, /* PFCMPGErr */ >+/* Table7814 */ >+ 0x7e1, /* PFMINrm */ >+ 0x7e2, /* PFMINrr */ >+/* Table7816 */ >+ 0x7ed, /* PFRCPrm */ >+ 0x7ee, /* PFRCPrr */ >+/* Table7818 */ >+ 0x7f1, /* PFRSQRTrm */ >+ 0x7f2, /* PFRSQRTrr */ >+/* Table7820 */ >+ 0x7f5, /* PFSUBrm */ >+ 0x7f6, /* PFSUBrr */ >+/* Table7822 */ >+ 0x7d7, /* PFADDrm */ >+ 0x7d8, /* PFADDrr */ >+/* Table7824 */ >+ 0x7dd, /* PFCMPGTrm */ >+ 0x7de, /* PFCMPGTrr */ >+/* Table7826 */ >+ 0x7df, /* PFMAXrm */ >+ 0x7e0, /* PFMAXrr */ >+/* Table7828 */ >+ 0x7e9, /* PFRCPIT1rm */ >+ 0x7ea, /* PFRCPIT1rr */ >+/* Table7830 */ >+ 0x7ef, /* PFRSQIT1rm */ >+ 0x7f0, /* PFRSQIT1rr */ >+/* Table7832 */ >+ 0x7f3, /* PFSUBRrm */ >+ 0x7f4, /* PFSUBRrr */ >+/* Table7834 */ >+ 0x7d5, /* PFACCrm */ >+ 0x7d6, /* PFACCrr */ >+/* Table7836 */ >+ 0x7d9, /* PFCMPEQrm */ >+ 0x7da, /* PFCMPEQrr */ >+/* Table7838 */ >+ 0x7e3, /* PFMULrm */ >+ 0x7e4, /* PFMULrr */ >+/* Table7840 */ >+ 0x7eb, /* PFRCPIT2rm */ >+ 0x7ec, /* PFRCPIT2rr */ >+/* Table7842 */ >+ 0x84a, /* PMULHRWrm */ >+ 0x84b, /* PMULHRWrr */ >+/* Table7844 */ >+ 0x8b8, /* PSWAPDrm */ >+ 0x8b9, /* PSWAPDrr */ >+/* Table7846 */ >+ 0x796, /* PAVGUSBrm */ >+ 0x797, /* PAVGUSBrr */ >+ 0x0 >+}; >+ >+static const struct OpcodeDecision x86DisassemblerOneByteOpcodes[] = { >+ /* IC */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 11 /* Table11 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 12 /* Table12 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 23 /* Table23 */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 34 /* Table34 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 35 /* Table35 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 46 /* Table46 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 47 /* Table47 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 58 /* Table58 */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 69 /* Table69 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 80 /* Table80 */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 91 /* Table91 */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 96 /* Table96 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 97 /* Table97 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 98 /* Table98 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 100 /* Table100 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 103 /* Table103 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 106 /* Table106 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 161 /* Table161 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 211 /* Table211 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 215 /* Table215 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 235 /* Table235 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 237 /* Table237 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 238 /* Table238 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 241 /* Table241 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 242 /* Table242 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 243 /* Table243 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 244 /* Table244 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 291 /* Table291 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 292 /* Table292 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 442 /* Table442 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 447 /* Table447 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 513 /* Table513 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 514 /* Table514 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 928 /* Table928 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 933 /* Table933 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 935 /* Table935 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1001 /* Table1001 */ >+ } >+ } >+ } >+, /* IC_64BIT */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1020 /* Table1020 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1024 /* Table1024 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1046 /* Table1046 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1048 /* Table1048 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1054 /* Table1054 */ >+ } >+ } >+ } >+, /* IC_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1070 /* Table1070 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1072 /* Table1072 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1074 /* Table1074 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1075 /* Table1075 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1076 /* Table1076 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1077 /* Table1077 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1079 /* Table1079 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1081 /* Table1081 */ >+ }, >+ /* 0x0e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1082 /* Table1082 */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1083 /* Table1083 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1085 /* Table1085 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1087 /* Table1087 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1088 /* Table1088 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1089 /* Table1089 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1090 /* Table1090 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1092 /* Table1092 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1094 /* Table1094 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1095 /* Table1095 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1096 /* Table1096 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1097 /* Table1097 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1099 /* Table1099 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1101 /* Table1101 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 58 /* Table58 */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1102 /* Table1102 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1104 /* Table1104 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1106 /* Table1106 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 69 /* Table69 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1107 /* Table1107 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1109 /* Table1109 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1111 /* Table1111 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 80 /* Table80 */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1112 /* Table1112 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1114 /* Table1114 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1116 /* Table1116 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 91 /* Table91 */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1117 /* Table1117 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1118 /* Table1118 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1121 /* Table1121 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1122 /* Table1122 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1123 /* Table1123 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 100 /* Table100 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1125 /* Table1125 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1126 /* Table1126 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1128 /* Table1128 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1129 /* Table1129 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1131 /* Table1131 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1132 /* Table1132 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1133 /* Table1133 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 161 /* Table161 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1149 /* Table1149 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1165 /* Table1165 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1167 /* Table1167 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1169 /* Table1169 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1171 /* Table1171 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1173 /* Table1173 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1175 /* Table1175 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1177 /* Table1177 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1179 /* Table1179 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1196 /* Table1196 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1197 /* Table1197 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1198 /* Table1198 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1199 /* Table1199 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1200 /* Table1200 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 241 /* Table241 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1201 /* Table1201 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 243 /* Table243 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1202 /* Table1202 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1203 /* Table1203 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1204 /* Table1204 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1205 /* Table1205 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1206 /* Table1206 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1207 /* Table1207 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1208 /* Table1208 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1210 /* Table1210 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1226 /* Table1226 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1227 /* Table1227 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1228 /* Table1228 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1230 /* Table1230 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1232 /* Table1232 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 442 /* Table442 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1304 /* Table1304 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1305 /* Table1305 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 447 /* Table447 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1306 /* Table1306 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1307 /* Table1307 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1323 /* Table1323 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 513 /* Table513 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 514 /* Table514 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 928 /* Table928 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1339 /* Table1339 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1340 /* Table1340 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1341 /* Table1341 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1342 /* Table1342 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1343 /* Table1343 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1344 /* Table1344 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1345 /* Table1345 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1346 /* Table1346 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1362 /* Table1362 */ >+ } >+ } >+ } >+, /* IC_ADSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 11 /* Table11 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 12 /* Table12 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 23 /* Table23 */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 34 /* Table34 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 35 /* Table35 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 46 /* Table46 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 47 /* Table47 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 58 /* Table58 */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 69 /* Table69 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 80 /* Table80 */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 91 /* Table91 */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 96 /* Table96 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 97 /* Table97 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 98 /* Table98 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 100 /* Table100 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 103 /* Table103 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 106 /* Table106 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 161 /* Table161 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 211 /* Table211 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 215 /* Table215 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 235 /* Table235 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 237 /* Table237 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 238 /* Table238 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 241 /* Table241 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 242 /* Table242 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 243 /* Table243 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 244 /* Table244 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 291 /* Table291 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 292 /* Table292 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 442 /* Table442 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 447 /* Table447 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 513 /* Table513 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 514 /* Table514 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1378 /* Table1378 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 933 /* Table933 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 935 /* Table935 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1001 /* Table1001 */ >+ } >+ } >+ } >+, /* IC_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 11 /* Table11 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 12 /* Table12 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 23 /* Table23 */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 34 /* Table34 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 35 /* Table35 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 46 /* Table46 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 47 /* Table47 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 58 /* Table58 */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 69 /* Table69 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 80 /* Table80 */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 91 /* Table91 */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 96 /* Table96 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 97 /* Table97 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 98 /* Table98 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 100 /* Table100 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 103 /* Table103 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 106 /* Table106 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 161 /* Table161 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 211 /* Table211 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 215 /* Table215 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 235 /* Table235 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 237 /* Table237 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 238 /* Table238 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 241 /* Table241 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 242 /* Table242 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 243 /* Table243 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 244 /* Table244 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 291 /* Table291 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 292 /* Table292 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 442 /* Table442 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 447 /* Table447 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 513 /* Table513 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 514 /* Table514 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 928 /* Table928 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 933 /* Table933 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 935 /* Table935 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1001 /* Table1001 */ >+ } >+ } >+ } >+, /* IC_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 11 /* Table11 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 12 /* Table12 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 23 /* Table23 */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 34 /* Table34 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 35 /* Table35 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 46 /* Table46 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 47 /* Table47 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 58 /* Table58 */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 69 /* Table69 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 80 /* Table80 */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 91 /* Table91 */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 92 /* Table92 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 93 /* Table93 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 94 /* Table94 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 95 /* Table95 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 96 /* Table96 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 97 /* Table97 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 98 /* Table98 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 100 /* Table100 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 103 /* Table103 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 106 /* Table106 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 161 /* Table161 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 211 /* Table211 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 215 /* Table215 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1379 /* Table1379 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 232 /* Table232 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 235 /* Table235 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 237 /* Table237 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 238 /* Table238 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 241 /* Table241 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 242 /* Table242 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 243 /* Table243 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 244 /* Table244 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 291 /* Table291 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 292 /* Table292 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 442 /* Table442 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 447 /* Table447 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 513 /* Table513 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 514 /* Table514 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 928 /* Table928 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 933 /* Table933 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 935 /* Table935 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1001 /* Table1001 */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1380 /* Table1380 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1382 /* Table1382 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1384 /* Table1384 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1385 /* Table1385 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1387 /* Table1387 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1389 /* Table1389 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1390 /* Table1390 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1392 /* Table1392 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1394 /* Table1394 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1395 /* Table1395 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1397 /* Table1397 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1399 /* Table1399 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1400 /* Table1400 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1402 /* Table1402 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1404 /* Table1404 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1405 /* Table1405 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1407 /* Table1407 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1409 /* Table1409 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1410 /* Table1410 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1412 /* Table1412 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1414 /* Table1414 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1415 /* Table1415 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1417 /* Table1417 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1419 /* Table1419 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1420 /* Table1420 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1422 /* Table1422 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1424 /* Table1424 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1426 /* Table1426 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1442 /* Table1442 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1458 /* Table1458 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1460 /* Table1460 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1462 /* Table1462 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1464 /* Table1464 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1466 /* Table1466 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1468 /* Table1468 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1470 /* Table1470 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1473 /* Table1473 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1474 /* Table1474 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1475 /* Table1475 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1476 /* Table1476 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1477 /* Table1477 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1478 /* Table1478 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1479 /* Table1479 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1480 /* Table1480 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1481 /* Table1481 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1482 /* Table1482 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1484 /* Table1484 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1500 /* Table1500 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1572 /* Table1572 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1573 /* Table1573 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1574 /* Table1574 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1575 /* Table1575 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1591 /* Table1591 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1607 /* Table1607 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1623 /* Table1623 */ >+ } >+ } >+ } >+, /* IC_64BIT_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1070 /* Table1070 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1072 /* Table1072 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1074 /* Table1074 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1077 /* Table1077 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1079 /* Table1079 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1081 /* Table1081 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1083 /* Table1083 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1085 /* Table1085 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1087 /* Table1087 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1090 /* Table1090 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1092 /* Table1092 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1094 /* Table1094 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1097 /* Table1097 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1099 /* Table1099 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1101 /* Table1101 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1102 /* Table1102 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1104 /* Table1104 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1106 /* Table1106 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1107 /* Table1107 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1109 /* Table1109 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1111 /* Table1111 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1112 /* Table1112 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1114 /* Table1114 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1116 /* Table1116 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1020 /* Table1020 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1639 /* Table1639 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1126 /* Table1126 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1129 /* Table1129 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1131 /* Table1131 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1132 /* Table1132 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1133 /* Table1133 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1149 /* Table1149 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1165 /* Table1165 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1167 /* Table1167 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1169 /* Table1169 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1171 /* Table1171 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1173 /* Table1173 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1175 /* Table1175 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1177 /* Table1177 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1179 /* Table1179 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1195 /* Table1195 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1196 /* Table1196 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1197 /* Table1197 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1199 /* Table1199 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1200 /* Table1200 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1640 /* Table1640 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1641 /* Table1641 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1203 /* Table1203 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1204 /* Table1204 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1205 /* Table1205 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1206 /* Table1206 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1207 /* Table1207 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1208 /* Table1208 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1209 /* Table1209 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1210 /* Table1210 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1226 /* Table1226 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1227 /* Table1227 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1228 /* Table1228 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1230 /* Table1230 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1232 /* Table1232 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1304 /* Table1304 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1305 /* Table1305 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1306 /* Table1306 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1307 /* Table1307 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1323 /* Table1323 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1339 /* Table1339 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1340 /* Table1340 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1341 /* Table1341 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1342 /* Table1342 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1344 /* Table1344 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1345 /* Table1345 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1346 /* Table1346 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1642 /* Table1642 */ >+ } >+ } >+ } >+, /* IC_64BIT_ADSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1020 /* Table1020 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1024 /* Table1024 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1046 /* Table1046 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1048 /* Table1048 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1658 /* Table1658 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1054 /* Table1054 */ >+ } >+ } >+ } >+, /* IC_64BIT_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1020 /* Table1020 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1024 /* Table1024 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1046 /* Table1046 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1048 /* Table1048 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1054 /* Table1054 */ >+ } >+ } >+ } >+, /* IC_64BIT_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3 /* Table3 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 7 /* Table7 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 10 /* Table10 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 15 /* Table15 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 19 /* Table19 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 22 /* Table22 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 26 /* Table26 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 30 /* Table30 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 33 /* Table33 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 38 /* Table38 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 42 /* Table42 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 45 /* Table45 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 50 /* Table50 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 54 /* Table54 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 57 /* Table57 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 61 /* Table61 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 65 /* Table65 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 68 /* Table68 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 72 /* Table72 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 76 /* Table76 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 79 /* Table79 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 83 /* Table83 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 87 /* Table87 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 90 /* Table90 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1020 /* Table1020 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 104 /* Table104 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 107 /* Table107 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 145 /* Table145 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 177 /* Table177 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 195 /* Table195 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 199 /* Table199 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 203 /* Table203 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 207 /* Table207 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 209 /* Table209 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1024 /* Table1024 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 213 /* Table213 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1379 /* Table1379 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1042 /* Table1042 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 233 /* Table233 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 234 /* Table234 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1046 /* Table1046 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1048 /* Table1048 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 246 /* Table246 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 248 /* Table248 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 250 /* Table250 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 252 /* Table252 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 254 /* Table254 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 256 /* Table256 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 258 /* Table258 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 275 /* Table275 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 369 /* Table369 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 443 /* Table443 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 444 /* Table444 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 448 /* Table448 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 465 /* Table465 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 497 /* Table497 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 963 /* Table963 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1054 /* Table1054 */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1380 /* Table1380 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1382 /* Table1382 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1384 /* Table1384 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1385 /* Table1385 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1387 /* Table1387 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1389 /* Table1389 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1390 /* Table1390 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1392 /* Table1392 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1394 /* Table1394 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1395 /* Table1395 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1397 /* Table1397 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1399 /* Table1399 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1400 /* Table1400 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1402 /* Table1402 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1404 /* Table1404 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1405 /* Table1405 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1407 /* Table1407 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1409 /* Table1409 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1410 /* Table1410 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1412 /* Table1412 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1414 /* Table1414 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1415 /* Table1415 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1417 /* Table1417 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1419 /* Table1419 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1420 /* Table1420 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1422 /* Table1422 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1424 /* Table1424 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1426 /* Table1426 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1442 /* Table1442 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1458 /* Table1458 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1460 /* Table1460 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1462 /* Table1462 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1464 /* Table1464 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1466 /* Table1466 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1468 /* Table1468 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1470 /* Table1470 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1473 /* Table1473 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1474 /* Table1474 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1475 /* Table1475 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1476 /* Table1476 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1477 /* Table1477 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1478 /* Table1478 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1479 /* Table1479 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1480 /* Table1480 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1481 /* Table1481 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1482 /* Table1482 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1484 /* Table1484 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1500 /* Table1500 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1572 /* Table1572 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1573 /* Table1573 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1574 /* Table1574 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1575 /* Table1575 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1591 /* Table1591 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1607 /* Table1607 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1623 /* Table1623 */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1380 /* Table1380 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1382 /* Table1382 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1384 /* Table1384 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1385 /* Table1385 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1387 /* Table1387 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1389 /* Table1389 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1390 /* Table1390 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1392 /* Table1392 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1394 /* Table1394 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1395 /* Table1395 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1397 /* Table1397 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1399 /* Table1399 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1400 /* Table1400 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1402 /* Table1402 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1404 /* Table1404 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1405 /* Table1405 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1407 /* Table1407 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1409 /* Table1409 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1410 /* Table1410 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1412 /* Table1412 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1414 /* Table1414 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1415 /* Table1415 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1417 /* Table1417 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1419 /* Table1419 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1018 /* Table1018 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1019 /* Table1019 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1420 /* Table1420 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1022 /* Table1022 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1422 /* Table1422 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1424 /* Table1424 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 110 /* Table110 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 112 /* Table112 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1426 /* Table1426 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1442 /* Table1442 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1458 /* Table1458 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1460 /* Table1460 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1462 /* Table1462 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1464 /* Table1464 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1466 /* Table1466 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1468 /* Table1468 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1470 /* Table1470 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1026 /* Table1026 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1473 /* Table1473 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1474 /* Table1474 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1043 /* Table1043 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1044 /* Table1044 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1475 /* Table1475 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1476 /* Table1476 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1477 /* Table1477 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1478 /* Table1478 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1479 /* Table1479 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1480 /* Table1480 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1481 /* Table1481 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1482 /* Table1482 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1484 /* Table1484 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1049 /* Table1049 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1050 /* Table1050 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 293 /* Table293 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 295 /* Table295 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1500 /* Table1500 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1572 /* Table1572 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1573 /* Table1573 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1574 /* Table1574 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1575 /* Table1575 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1591 /* Table1591 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 930 /* Table930 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 932 /* Table932 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1053 /* Table1053 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 934 /* Table934 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 938 /* Table938 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 940 /* Table940 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1607 /* Table1607 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1623 /* Table1623 */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1 /* Table1 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1380 /* Table1380 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 5 /* Table5 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1382 /* Table1382 */ >+ }, >+ /* 0x04 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 9 /* Table9 */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1384 /* Table1384 */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 13 /* Table13 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1385 /* Table1385 */ >+ }, >+ /* 0x0a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 17 /* Table17 */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1387 /* Table1387 */ >+ }, >+ /* 0x0c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 21 /* Table21 */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1389 /* Table1389 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 24 /* Table24 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1390 /* Table1390 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 28 /* Table28 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1392 /* Table1392 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 32 /* Table32 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1394 /* Table1394 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 36 /* Table36 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1395 /* Table1395 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 40 /* Table40 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1397 /* Table1397 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 44 /* Table44 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1399 /* Table1399 */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 48 /* Table48 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1400 /* Table1400 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 52 /* Table52 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1402 /* Table1402 */ >+ }, >+ /* 0x24 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 56 /* Table56 */ >+ }, >+ /* 0x25 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1404 /* Table1404 */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 59 /* Table59 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1405 /* Table1405 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 63 /* Table63 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1407 /* Table1407 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 67 /* Table67 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1409 /* Table1409 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 70 /* Table70 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1410 /* Table1410 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 74 /* Table74 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1412 /* Table1412 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 78 /* Table78 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1414 /* Table1414 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 81 /* Table81 */ >+ }, >+ /* 0x39 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1415 /* Table1415 */ >+ }, >+ /* 0x3a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 85 /* Table85 */ >+ }, >+ /* 0x3b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1417 /* Table1417 */ >+ }, >+ /* 0x3c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 89 /* Table89 */ >+ }, >+ /* 0x3d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1419 /* Table1419 */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1017 /* Table1017 */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1119 /* Table1119 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1120 /* Table1120 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1420 /* Table1420 */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 102 /* Table102 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1639 /* Table1639 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1422 /* Table1422 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1023 /* Table1023 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1424 /* Table1424 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 109 /* Table109 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1131 /* Table1131 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 111 /* Table111 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1132 /* Table1132 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 113 /* Table113 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 114 /* Table114 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 115 /* Table115 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 116 /* Table116 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 117 /* Table117 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 118 /* Table118 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 119 /* Table119 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 120 /* Table120 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 121 /* Table121 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 122 /* Table122 */ >+ }, >+ /* 0x7a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 123 /* Table123 */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 124 /* Table124 */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 125 /* Table125 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 126 /* Table126 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 127 /* Table127 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 128 /* Table128 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 129 /* Table129 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1426 /* Table1426 */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1442 /* Table1442 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 193 /* Table193 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1458 /* Table1458 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 197 /* Table197 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1460 /* Table1460 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 201 /* Table201 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1462 /* Table1462 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 205 /* Table205 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1464 /* Table1464 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1466 /* Table1466 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1468 /* Table1468 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1470 /* Table1470 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1179 /* Table1179 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 231 /* Table231 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1472 /* Table1472 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1473 /* Table1473 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1474 /* Table1474 */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 236 /* Table236 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1199 /* Table1199 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1200 /* Table1200 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 239 /* Table239 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 240 /* Table240 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1045 /* Table1045 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1475 /* Table1475 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1047 /* Table1047 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1476 /* Table1476 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 245 /* Table245 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1477 /* Table1477 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 247 /* Table247 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1478 /* Table1478 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 249 /* Table249 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1479 /* Table1479 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 251 /* Table251 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1480 /* Table1480 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 253 /* Table253 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1481 /* Table1481 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 255 /* Table255 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1482 /* Table1482 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 257 /* Table257 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1483 /* Table1483 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 259 /* Table259 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1484 /* Table1484 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1226 /* Table1226 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1227 /* Table1227 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1228 /* Table1228 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1230 /* Table1230 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 297 /* Table297 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1500 /* Table1500 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 441 /* Table441 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1051 /* Table1051 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1572 /* Table1572 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1573 /* Table1573 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 445 /* Table445 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 446 /* Table446 */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1574 /* Table1574 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 449 /* Table449 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1575 /* Table1575 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 481 /* Table481 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1591 /* Table1591 */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 515 /* Table515 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 516 /* Table516 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 517 /* Table517 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 533 /* Table533 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 605 /* Table605 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 677 /* Table677 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 749 /* Table749 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 765 /* Table765 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 781 /* Table781 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 853 /* Table853 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 925 /* Table925 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 926 /* Table926 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 927 /* Table927 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1052 /* Table1052 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 929 /* Table929 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1339 /* Table1339 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 931 /* Table931 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1340 /* Table1340 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1341 /* Table1341 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1342 /* Table1342 */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 936 /* Table936 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 937 /* Table937 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1344 /* Table1344 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 939 /* Table939 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1345 /* Table1345 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 941 /* Table941 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 942 /* Table942 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 943 /* Table943 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 944 /* Table944 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 945 /* Table945 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 946 /* Table946 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 947 /* Table947 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1607 /* Table1607 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 979 /* Table979 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 980 /* Table980 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 981 /* Table981 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 982 /* Table982 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 983 /* Table983 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 984 /* Table984 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 985 /* Table985 */ >+ }, >+ /* 0xff */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1659 /* Table1659 */ >+ } >+ } >+ } >+, /* IC_OF */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, }; >+static const uint8_t index_x86DisassemblerOneByteOpcodes[] = { >+1, 2, 3, 4, 0, 5, 6, 0, 0, 7, 8, 9, 10, 11, 0, 0, 12, 13, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; >+static const struct OpcodeDecision x86DisassemblerTwoByteOpcodes[] = { >+ /* IC */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1691 /* Table1691 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1789 /* Table1789 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1791 /* Table1791 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1793 /* Table1793 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1835 /* Table1835 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1837 /* Table1837 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1839 /* Table1839 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1841 /* Table1841 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1847 /* Table1847 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1849 /* Table1849 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1851 /* Table1851 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1853 /* Table1853 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1900 /* Table1900 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1914 /* Table1914 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1916 /* Table1916 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1918 /* Table1918 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1922 /* Table1922 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1924 /* Table1924 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1926 /* Table1926 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1928 /* Table1928 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1958 /* Table1958 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2015 /* Table2015 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2017 /* Table2017 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2071 /* Table2071 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2072 /* Table2072 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2073 /* Table2073 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2224 /* Table2224 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2225 /* Table2225 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2354 /* Table2354 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2451 /* Table2451 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2467 /* Table2467 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1789 /* Table1789 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1791 /* Table1791 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1793 /* Table1793 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1847 /* Table1847 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1849 /* Table1849 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1851 /* Table1851 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1853 /* Table1853 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1900 /* Table1900 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1914 /* Table1914 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1916 /* Table1916 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1918 /* Table1918 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1922 /* Table1922 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1924 /* Table1924 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1926 /* Table1926 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1928 /* Table1928 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1958 /* Table1958 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2547 /* Table2547 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2549 /* Table2549 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2354 /* Table2354 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2558 /* Table2558 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2574 /* Table2574 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2646 /* Table2646 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2648 /* Table2648 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2650 /* Table2650 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2652 /* Table2652 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2654 /* Table2654 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2656 /* Table2656 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2658 /* Table2658 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2660 /* Table2660 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2662 /* Table2662 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2664 /* Table2664 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2666 /* Table2666 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2682 /* Table2682 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2684 /* Table2684 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2686 /* Table2686 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2688 /* Table2688 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2690 /* Table2690 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2692 /* Table2692 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2694 /* Table2694 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1835 /* Table1835 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1837 /* Table1837 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1839 /* Table1839 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1841 /* Table1841 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2696 /* Table2696 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2698 /* Table2698 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2700 /* Table2700 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2702 /* Table2702 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2704 /* Table2704 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2706 /* Table2706 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2708 /* Table2708 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2710 /* Table2710 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2712 /* Table2712 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2714 /* Table2714 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2716 /* Table2716 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2718 /* Table2718 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2720 /* Table2720 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2722 /* Table2722 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2724 /* Table2724 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2726 /* Table2726 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2728 /* Table2728 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2730 /* Table2730 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2732 /* Table2732 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2734 /* Table2734 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2736 /* Table2736 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2738 /* Table2738 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2740 /* Table2740 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2742 /* Table2742 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2744 /* Table2744 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2746 /* Table2746 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2748 /* Table2748 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2750 /* Table2750 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2752 /* Table2752 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2754 /* Table2754 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2756 /* Table2756 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2758 /* Table2758 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2760 /* Table2760 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2762 /* Table2762 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2764 /* Table2764 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2766 /* Table2766 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2768 /* Table2768 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2770 /* Table2770 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2772 /* Table2772 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2774 /* Table2774 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2776 /* Table2776 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2778 /* Table2778 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2780 /* Table2780 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2782 /* Table2782 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2784 /* Table2784 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2786 /* Table2786 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2788 /* Table2788 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2790 /* Table2790 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2792 /* Table2792 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2794 /* Table2794 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2796 /* Table2796 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2798 /* Table2798 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2800 /* Table2800 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2802 /* Table2802 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2804 /* Table2804 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2806 /* Table2806 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2822 /* Table2822 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2838 /* Table2838 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2854 /* Table2854 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2856 /* Table2856 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2858 /* Table2858 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2860 /* Table2860 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2862 /* Table2862 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2864 /* Table2864 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2866 /* Table2866 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2868 /* Table2868 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2870 /* Table2870 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2872 /* Table2872 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2873 /* Table2873 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2874 /* Table2874 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2875 /* Table2875 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2876 /* Table2876 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2877 /* Table2877 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2878 /* Table2878 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2879 /* Table2879 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2880 /* Table2880 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2881 /* Table2881 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2882 /* Table2882 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2883 /* Table2883 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2884 /* Table2884 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2885 /* Table2885 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2886 /* Table2886 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2887 /* Table2887 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2888 /* Table2888 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2889 /* Table2889 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2073 /* Table2073 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2890 /* Table2890 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2892 /* Table2892 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2894 /* Table2894 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2896 /* Table2896 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2897 /* Table2897 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2898 /* Table2898 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2900 /* Table2900 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2902 /* Table2902 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2904 /* Table2904 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2906 /* Table2906 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2908 /* Table2908 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2910 /* Table2910 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2912 /* Table2912 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2914 /* Table2914 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2916 /* Table2916 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2918 /* Table2918 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2934 /* Table2934 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2936 /* Table2936 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2938 /* Table2938 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2940 /* Table2940 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2942 /* Table2942 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2944 /* Table2944 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2946 /* Table2946 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2948 /* Table2948 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2950 /* Table2950 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2952 /* Table2952 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2968 /* Table2968 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2970 /* Table2970 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2972 /* Table2972 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2974 /* Table2974 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2976 /* Table2976 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2978 /* Table2978 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2980 /* Table2980 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2982 /* Table2982 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2984 /* Table2984 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2986 /* Table2986 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2988 /* Table2988 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2990 /* Table2990 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2992 /* Table2992 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2994 /* Table2994 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2996 /* Table2996 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2998 /* Table2998 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3000 /* Table3000 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3002 /* Table3002 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3004 /* Table3004 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3006 /* Table3006 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3008 /* Table3008 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3010 /* Table3010 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3012 /* Table3012 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3014 /* Table3014 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3016 /* Table3016 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3018 /* Table3018 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3020 /* Table3020 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3022 /* Table3022 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3024 /* Table3024 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3026 /* Table3026 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3028 /* Table3028 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3030 /* Table3030 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3032 /* Table3032 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3034 /* Table3034 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3036 /* Table3036 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3038 /* Table3038 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3040 /* Table3040 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3042 /* Table3042 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3044 /* Table3044 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3046 /* Table3046 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3048 /* Table3048 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3050 /* Table3050 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3052 /* Table3052 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3054 /* Table3054 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3056 /* Table3056 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3058 /* Table3058 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_ADSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1691 /* Table1691 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1789 /* Table1789 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1791 /* Table1791 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1793 /* Table1793 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1835 /* Table1835 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1837 /* Table1837 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1839 /* Table1839 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1841 /* Table1841 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1847 /* Table1847 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1849 /* Table1849 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1851 /* Table1851 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1853 /* Table1853 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1900 /* Table1900 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1914 /* Table1914 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1916 /* Table1916 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1918 /* Table1918 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1922 /* Table1922 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1924 /* Table1924 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1926 /* Table1926 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1928 /* Table1928 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1958 /* Table1958 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2015 /* Table2015 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2017 /* Table2017 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2071 /* Table2071 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2072 /* Table2072 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2073 /* Table2073 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2224 /* Table2224 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2225 /* Table2225 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2354 /* Table2354 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2451 /* Table2451 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1691 /* Table1691 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3060 /* Table3060 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3062 /* Table3062 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3064 /* Table3064 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1835 /* Table1835 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1837 /* Table1837 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1839 /* Table1839 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1841 /* Table1841 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3066 /* Table3066 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3068 /* Table3068 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3070 /* Table3070 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3072 /* Table3072 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3074 /* Table3074 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3076 /* Table3076 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3078 /* Table3078 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3080 /* Table3080 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3082 /* Table3082 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3084 /* Table3084 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3086 /* Table3086 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3088 /* Table3088 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3090 /* Table3090 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3092 /* Table3092 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3094 /* Table3094 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3096 /* Table3096 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3098 /* Table3098 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2071 /* Table2071 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2072 /* Table2072 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2073 /* Table2073 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2224 /* Table2224 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2225 /* Table2225 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3100 /* Table3100 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3102 /* Table3102 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3104 /* Table3104 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3106 /* Table3106 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3108 /* Table3108 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2451 /* Table2451 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 1691 /* Table1691 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3110 /* Table3110 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3112 /* Table3112 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3114 /* Table3114 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3116 /* Table3116 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1835 /* Table1835 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1837 /* Table1837 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1839 /* Table1839 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1841 /* Table1841 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3118 /* Table3118 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3120 /* Table3120 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3122 /* Table3122 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3124 /* Table3124 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3126 /* Table3126 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3128 /* Table3128 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3130 /* Table3130 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3132 /* Table3132 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3134 /* Table3134 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3136 /* Table3136 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3138 /* Table3138 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3140 /* Table3140 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3142 /* Table3142 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3144 /* Table3144 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3146 /* Table3146 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3148 /* Table3148 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3150 /* Table3150 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2015 /* Table2015 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2017 /* Table2017 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3152 /* Table3152 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3154 /* Table3154 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2071 /* Table2071 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2072 /* Table2072 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2073 /* Table2073 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2224 /* Table2224 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2225 /* Table2225 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3156 /* Table3156 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3158 /* Table3158 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3160 /* Table3160 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3162 /* Table3162 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3164 /* Table3164 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3180 /* Table3180 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3182 /* Table3182 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2451 /* Table2451 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_XS_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3184 /* Table3184 */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3186 /* Table3186 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3188 /* Table3188 */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3190 /* Table3190 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3206 /* Table3206 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3278 /* Table3278 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3280 /* Table3280 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3282 /* Table3282 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1789 /* Table1789 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1791 /* Table1791 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1793 /* Table1793 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1847 /* Table1847 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1849 /* Table1849 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1851 /* Table1851 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1853 /* Table1853 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3283 /* Table3283 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3284 /* Table3284 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3286 /* Table3286 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3288 /* Table3288 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3290 /* Table3290 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3292 /* Table3292 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3294 /* Table3294 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3296 /* Table3296 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3298 /* Table3298 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3300 /* Table3300 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3302 /* Table3302 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3304 /* Table3304 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3306 /* Table3306 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3308 /* Table3308 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3310 /* Table3310 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3312 /* Table3312 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3314 /* Table3314 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1900 /* Table1900 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1914 /* Table1914 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1916 /* Table1916 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1918 /* Table1918 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1922 /* Table1922 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1924 /* Table1924 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1926 /* Table1926 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1928 /* Table1928 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3316 /* Table3316 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1958 /* Table1958 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2547 /* Table2547 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2549 /* Table2549 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3318 /* Table3318 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3320 /* Table3320 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3322 /* Table3322 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3324 /* Table3324 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3326 /* Table3326 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3328 /* Table3328 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3330 /* Table3330 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3332 /* Table3332 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3404 /* Table3404 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3406 /* Table3406 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3408 /* Table3408 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3410 /* Table3410 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3412 /* Table3412 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3414 /* Table3414 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3416 /* Table3416 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3418 /* Table3418 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3420 /* Table3420 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3436 /* Table3436 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3438 /* Table3438 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3440 /* Table3440 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3442 /* Table3442 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3444 /* Table3444 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3446 /* Table3446 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2354 /* Table2354 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3448 /* Table3448 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3450 /* Table3450 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2558 /* Table2558 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3467 /* Table3467 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2646 /* Table2646 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2648 /* Table2648 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2650 /* Table2650 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2652 /* Table2652 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2654 /* Table2654 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2656 /* Table2656 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2658 /* Table2658 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2660 /* Table2660 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2662 /* Table2662 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2664 /* Table2664 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2666 /* Table2666 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2682 /* Table2682 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2684 /* Table2684 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2686 /* Table2686 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2688 /* Table2688 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2690 /* Table2690 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2692 /* Table2692 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2694 /* Table2694 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2696 /* Table2696 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2698 /* Table2698 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2700 /* Table2700 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2702 /* Table2702 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2704 /* Table2704 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2706 /* Table2706 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2708 /* Table2708 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2710 /* Table2710 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2712 /* Table2712 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2714 /* Table2714 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2716 /* Table2716 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2718 /* Table2718 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2720 /* Table2720 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2722 /* Table2722 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2724 /* Table2724 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2726 /* Table2726 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2728 /* Table2728 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2730 /* Table2730 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2732 /* Table2732 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2734 /* Table2734 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2736 /* Table2736 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2738 /* Table2738 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2740 /* Table2740 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2742 /* Table2742 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2744 /* Table2744 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2746 /* Table2746 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2748 /* Table2748 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2750 /* Table2750 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2752 /* Table2752 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2754 /* Table2754 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2756 /* Table2756 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2758 /* Table2758 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2760 /* Table2760 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2762 /* Table2762 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2764 /* Table2764 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2766 /* Table2766 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2768 /* Table2768 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2770 /* Table2770 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2772 /* Table2772 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2774 /* Table2774 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2776 /* Table2776 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2778 /* Table2778 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2780 /* Table2780 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2782 /* Table2782 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2784 /* Table2784 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2786 /* Table2786 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2788 /* Table2788 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2790 /* Table2790 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2792 /* Table2792 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2794 /* Table2794 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2796 /* Table2796 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2798 /* Table2798 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2800 /* Table2800 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2802 /* Table2802 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2804 /* Table2804 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2806 /* Table2806 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2822 /* Table2822 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2838 /* Table2838 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2854 /* Table2854 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2856 /* Table2856 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2858 /* Table2858 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3539 /* Table3539 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3541 /* Table3541 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2864 /* Table2864 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2866 /* Table2866 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2868 /* Table2868 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2870 /* Table2870 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2872 /* Table2872 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2873 /* Table2873 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2874 /* Table2874 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2875 /* Table2875 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2876 /* Table2876 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2877 /* Table2877 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2878 /* Table2878 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2879 /* Table2879 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2880 /* Table2880 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2881 /* Table2881 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2882 /* Table2882 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2883 /* Table2883 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2884 /* Table2884 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2885 /* Table2885 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2886 /* Table2886 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2887 /* Table2887 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2888 /* Table2888 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2889 /* Table2889 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2890 /* Table2890 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2892 /* Table2892 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2894 /* Table2894 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2896 /* Table2896 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2897 /* Table2897 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2898 /* Table2898 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2900 /* Table2900 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2902 /* Table2902 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2904 /* Table2904 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2906 /* Table2906 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2908 /* Table2908 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2910 /* Table2910 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2912 /* Table2912 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2914 /* Table2914 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2916 /* Table2916 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2918 /* Table2918 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2934 /* Table2934 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2936 /* Table2936 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2938 /* Table2938 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2940 /* Table2940 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2942 /* Table2942 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2944 /* Table2944 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2946 /* Table2946 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2948 /* Table2948 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2950 /* Table2950 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2952 /* Table2952 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2968 /* Table2968 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2970 /* Table2970 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2972 /* Table2972 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2974 /* Table2974 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2976 /* Table2976 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2978 /* Table2978 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2980 /* Table2980 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2982 /* Table2982 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2984 /* Table2984 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2986 /* Table2986 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2988 /* Table2988 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2990 /* Table2990 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2992 /* Table2992 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2994 /* Table2994 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2996 /* Table2996 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2998 /* Table2998 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3000 /* Table3000 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3002 /* Table3002 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3004 /* Table3004 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3006 /* Table3006 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3008 /* Table3008 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3010 /* Table3010 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3012 /* Table3012 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3014 /* Table3014 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3016 /* Table3016 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3018 /* Table3018 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3020 /* Table3020 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3022 /* Table3022 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3024 /* Table3024 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3026 /* Table3026 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3028 /* Table3028 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3030 /* Table3030 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3032 /* Table3032 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3034 /* Table3034 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3036 /* Table3036 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3038 /* Table3038 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3040 /* Table3040 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3042 /* Table3042 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3543 /* Table3543 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3046 /* Table3046 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3048 /* Table3048 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3050 /* Table3050 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3052 /* Table3052 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3054 /* Table3054 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3056 /* Table3056 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3058 /* Table3058 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_ADSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2467 /* Table2467 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1789 /* Table1789 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1791 /* Table1791 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1793 /* Table1793 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1847 /* Table1847 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1849 /* Table1849 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1851 /* Table1851 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1853 /* Table1853 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1900 /* Table1900 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1914 /* Table1914 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1916 /* Table1916 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1918 /* Table1918 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1922 /* Table1922 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1924 /* Table1924 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1926 /* Table1926 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1928 /* Table1928 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1958 /* Table1958 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2547 /* Table2547 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2549 /* Table2549 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2354 /* Table2354 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2467 /* Table2467 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3060 /* Table3060 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3062 /* Table3062 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3064 /* Table3064 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3066 /* Table3066 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3068 /* Table3068 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3070 /* Table3070 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3072 /* Table3072 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3074 /* Table3074 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3076 /* Table3076 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3078 /* Table3078 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3080 /* Table3080 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3082 /* Table3082 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3084 /* Table3084 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3086 /* Table3086 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3088 /* Table3088 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3090 /* Table3090 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3545 /* Table3545 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3547 /* Table3547 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3096 /* Table3096 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3098 /* Table3098 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2019 /* Table2019 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2233 /* Table2233 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2342 /* Table2342 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2344 /* Table2344 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3100 /* Table3100 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2364 /* Table2364 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3102 /* Table3102 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3104 /* Table3104 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3106 /* Table3106 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3108 /* Table3108 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1675 /* Table1675 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2467 /* Table2467 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1763 /* Table1763 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1765 /* Table1765 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1769 /* Table1769 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3110 /* Table3110 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3112 /* Table3112 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3114 /* Table3114 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3116 /* Table3116 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3118 /* Table3118 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3120 /* Table3120 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3122 /* Table3122 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3124 /* Table3124 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1864 /* Table1864 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1866 /* Table1866 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1868 /* Table1868 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1870 /* Table1870 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1872 /* Table1872 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1874 /* Table1874 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1876 /* Table1876 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1878 /* Table1878 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1880 /* Table1880 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1882 /* Table1882 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1884 /* Table1884 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1886 /* Table1886 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1888 /* Table1888 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1890 /* Table1890 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1892 /* Table1892 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1894 /* Table1894 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1896 /* Table1896 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3126 /* Table3126 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3128 /* Table3128 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3130 /* Table3130 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3132 /* Table3132 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3134 /* Table3134 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3136 /* Table3136 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3138 /* Table3138 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3140 /* Table3140 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3142 /* Table3142 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3144 /* Table3144 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3146 /* Table3146 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1954 /* Table1954 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3148 /* Table3148 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3150 /* Table3150 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2547 /* Table2547 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2549 /* Table2549 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3152 /* Table3152 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3154 /* Table3154 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2074 /* Table2074 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2076 /* Table2076 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2078 /* Table2078 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2227 /* Table2227 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2229 /* Table2229 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2231 /* Table2231 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3549 /* Table3549 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2305 /* Table2305 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2309 /* Table2309 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2311 /* Table2311 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2313 /* Table2313 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2315 /* Table2315 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2317 /* Table2317 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2319 /* Table2319 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2321 /* Table2321 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3156 /* Table3156 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2324 /* Table2324 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2340 /* Table2340 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3158 /* Table3158 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3160 /* Table3160 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2346 /* Table2346 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2348 /* Table2348 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2352 /* Table2352 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3162 /* Table3162 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2356 /* Table2356 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3164 /* Table3164 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2380 /* Table2380 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3180 /* Table3180 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3182 /* Table3182 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_XS_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3184 /* Table3184 */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3186 /* Table3186 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3188 /* Table3188 */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3190 /* Table3190 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3206 /* Table3206 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3278 /* Table3278 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3280 /* Table3280 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3282 /* Table3282 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3110 /* Table3110 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3112 /* Table3112 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3114 /* Table3114 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3116 /* Table3116 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3621 /* Table3621 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3120 /* Table3120 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3623 /* Table3623 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3625 /* Table3625 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3283 /* Table3283 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3284 /* Table3284 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3286 /* Table3286 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3288 /* Table3288 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3290 /* Table3290 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3292 /* Table3292 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3294 /* Table3294 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3296 /* Table3296 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3298 /* Table3298 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3300 /* Table3300 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3302 /* Table3302 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3304 /* Table3304 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3306 /* Table3306 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3308 /* Table3308 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3310 /* Table3310 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3312 /* Table3312 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3314 /* Table3314 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3126 /* Table3126 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3128 /* Table3128 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3130 /* Table3130 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3132 /* Table3132 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3134 /* Table3134 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3136 /* Table3136 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3138 /* Table3138 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3140 /* Table3140 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3142 /* Table3142 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3144 /* Table3144 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3146 /* Table3146 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3316 /* Table3316 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3148 /* Table3148 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3150 /* Table3150 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2547 /* Table2547 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2549 /* Table2549 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3627 /* Table3627 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3154 /* Table3154 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3320 /* Table3320 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3322 /* Table3322 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3324 /* Table3324 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3326 /* Table3326 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3328 /* Table3328 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3330 /* Table3330 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3629 /* Table3629 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3404 /* Table3404 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3406 /* Table3406 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3408 /* Table3408 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3410 /* Table3410 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3412 /* Table3412 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3414 /* Table3414 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3416 /* Table3416 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3418 /* Table3418 */ >+ }, >+ /* 0xb8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3701 /* Table3701 */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3420 /* Table3420 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3436 /* Table3436 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3703 /* Table3703 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3705 /* Table3705 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3442 /* Table3442 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3444 /* Table3444 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3446 /* Table3446 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3162 /* Table3162 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3448 /* Table3448 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3707 /* Table3707 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3180 /* Table3180 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3182 /* Table3182 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3190 /* Table3190 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3206 /* Table3206 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3278 /* Table3278 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3280 /* Table3280 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3282 /* Table3282 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3060 /* Table3060 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3062 /* Table3062 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3064 /* Table3064 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1795 /* Table1795 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1797 /* Table1797 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1799 /* Table1799 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1801 /* Table1801 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1803 /* Table1803 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1805 /* Table1805 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1821 /* Table1821 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1823 /* Table1823 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1825 /* Table1825 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1827 /* Table1827 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1829 /* Table1829 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1831 /* Table1831 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1833 /* Table1833 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1843 /* Table1843 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1845 /* Table1845 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3723 /* Table3723 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3068 /* Table3068 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3725 /* Table3725 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3727 /* Table3727 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1855 /* Table1855 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1857 /* Table1857 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3283 /* Table3283 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3284 /* Table3284 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3286 /* Table3286 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3288 /* Table3288 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3290 /* Table3290 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3292 /* Table3292 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3294 /* Table3294 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3296 /* Table3296 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3298 /* Table3298 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3300 /* Table3300 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3302 /* Table3302 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3304 /* Table3304 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3306 /* Table3306 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3308 /* Table3308 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3310 /* Table3310 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3312 /* Table3312 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3314 /* Table3314 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1898 /* Table1898 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3074 /* Table3074 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1906 /* Table1906 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1908 /* Table1908 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1910 /* Table1910 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1912 /* Table1912 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3076 /* Table3076 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3078 /* Table3078 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3080 /* Table3080 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1920 /* Table1920 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3082 /* Table3082 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3084 /* Table3084 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3086 /* Table3086 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3088 /* Table3088 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1930 /* Table1930 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1932 /* Table1932 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1934 /* Table1934 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1936 /* Table1936 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1938 /* Table1938 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1940 /* Table1940 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1942 /* Table1942 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1944 /* Table1944 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1946 /* Table1946 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1948 /* Table1948 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1950 /* Table1950 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1952 /* Table1952 */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3316 /* Table3316 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1956 /* Table1956 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3090 /* Table3090 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1960 /* Table1960 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1976 /* Table1976 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1992 /* Table1992 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2008 /* Table2008 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2010 /* Table2010 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2012 /* Table2012 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3545 /* Table3545 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3547 /* Table3547 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3096 /* Table3096 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3098 /* Table3098 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3318 /* Table3318 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2021 /* Table2021 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2023 /* Table2023 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2024 /* Table2024 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2025 /* Table2025 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2026 /* Table2026 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2027 /* Table2027 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2028 /* Table2028 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2029 /* Table2029 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2030 /* Table2030 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2031 /* Table2031 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2032 /* Table2032 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2033 /* Table2033 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2034 /* Table2034 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2035 /* Table2035 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2036 /* Table2036 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2037 /* Table2037 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2038 /* Table2038 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2551 /* Table2551 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2552 /* Table2552 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3320 /* Table3320 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3322 /* Table3322 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3324 /* Table3324 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2554 /* Table2554 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2555 /* Table2555 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3326 /* Table3326 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3328 /* Table3328 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3330 /* Table3330 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3332 /* Table3332 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3404 /* Table3404 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3406 /* Table3406 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3408 /* Table3408 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3410 /* Table3410 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3412 /* Table3412 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3414 /* Table3414 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3416 /* Table3416 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3418 /* Table3418 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3420 /* Table3420 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3436 /* Table3436 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3438 /* Table3438 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3440 /* Table3440 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3442 /* Table3442 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3444 /* Table3444 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3446 /* Table3446 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3100 /* Table3100 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3448 /* Table3448 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2358 /* Table2358 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2360 /* Table2360 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2362 /* Table2362 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3450 /* Table3450 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3102 /* Table3102 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2381 /* Table2381 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2383 /* Table2383 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2385 /* Table2385 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2387 /* Table2387 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2389 /* Table2389 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3104 /* Table3104 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2391 /* Table2391 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2393 /* Table2393 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2395 /* Table2395 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2397 /* Table2397 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2399 /* Table2399 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2401 /* Table2401 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2403 /* Table2403 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2405 /* Table2405 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2407 /* Table2407 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2409 /* Table2409 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2411 /* Table2411 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2413 /* Table2413 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2415 /* Table2415 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2417 /* Table2417 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2419 /* Table2419 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3106 /* Table3106 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2421 /* Table2421 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2423 /* Table2423 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2425 /* Table2425 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2427 /* Table2427 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2429 /* Table2429 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2431 /* Table2431 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2433 /* Table2433 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2435 /* Table2435 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2437 /* Table2437 */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3108 /* Table3108 */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2439 /* Table2439 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2441 /* Table2441 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2443 /* Table2443 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2445 /* Table2445 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2447 /* Table2447 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2449 /* Table2449 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2556 /* Table2556 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2453 /* Table2453 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2455 /* Table2455 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2457 /* Table2457 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2459 /* Table2459 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2461 /* Table2461 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2463 /* Table2463 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2465 /* Table2465 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_64BIT_REXW_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3190 /* Table3190 */ >+ }, >+ /* 0x01 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3206 /* Table3206 */ >+ }, >+ /* 0x02 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3278 /* Table3278 */ >+ }, >+ /* 0x03 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3280 /* Table3280 */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1767 /* Table1767 */ >+ }, >+ /* 0x06 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1768 /* Table1768 */ >+ }, >+ /* 0x07 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3282 /* Table3282 */ >+ }, >+ /* 0x08 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1770 /* Table1770 */ >+ }, >+ /* 0x09 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1771 /* Table1771 */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1772 /* Table1772 */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 1773 /* Table1773 */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2650 /* Table2650 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2652 /* Table2652 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2654 /* Table2654 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2656 /* Table2656 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2658 /* Table2658 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2660 /* Table2660 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2662 /* Table2662 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2664 /* Table2664 */ >+ }, >+ /* 0x18 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2666 /* Table2666 */ >+ }, >+ /* 0x19 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2682 /* Table2682 */ >+ }, >+ /* 0x1a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2684 /* Table2684 */ >+ }, >+ /* 0x1b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2686 /* Table2686 */ >+ }, >+ /* 0x1c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2688 /* Table2688 */ >+ }, >+ /* 0x1d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2690 /* Table2690 */ >+ }, >+ /* 0x1e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2692 /* Table2692 */ >+ }, >+ /* 0x1f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2694 /* Table2694 */ >+ }, >+ /* 0x20 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2539 /* Table2539 */ >+ }, >+ /* 0x21 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2541 /* Table2541 */ >+ }, >+ /* 0x22 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2543 /* Table2543 */ >+ }, >+ /* 0x23 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2545 /* Table2545 */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2696 /* Table2696 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2698 /* Table2698 */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2700 /* Table2700 */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2702 /* Table2702 */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2704 /* Table2704 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2706 /* Table2706 */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2708 /* Table2708 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2710 /* Table2710 */ >+ }, >+ /* 0x30 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1859 /* Table1859 */ >+ }, >+ /* 0x31 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1860 /* Table1860 */ >+ }, >+ /* 0x32 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1861 /* Table1861 */ >+ }, >+ /* 0x33 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1862 /* Table1862 */ >+ }, >+ /* 0x34 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1863 /* Table1863 */ >+ }, >+ /* 0x35 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3283 /* Table3283 */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 1865 /* Table1865 */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3284 /* Table3284 */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3286 /* Table3286 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3288 /* Table3288 */ >+ }, >+ /* 0x43 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3290 /* Table3290 */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3292 /* Table3292 */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3294 /* Table3294 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3296 /* Table3296 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3298 /* Table3298 */ >+ }, >+ /* 0x48 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3300 /* Table3300 */ >+ }, >+ /* 0x49 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3302 /* Table3302 */ >+ }, >+ /* 0x4a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3304 /* Table3304 */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3306 /* Table3306 */ >+ }, >+ /* 0x4c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3308 /* Table3308 */ >+ }, >+ /* 0x4d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3310 /* Table3310 */ >+ }, >+ /* 0x4e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3312 /* Table3312 */ >+ }, >+ /* 0x4f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3314 /* Table3314 */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2744 /* Table2744 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2746 /* Table2746 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1902 /* Table1902 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 1904 /* Table1904 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2748 /* Table2748 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2750 /* Table2750 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2752 /* Table2752 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2754 /* Table2754 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2756 /* Table2756 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2758 /* Table2758 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2760 /* Table2760 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2762 /* Table2762 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2764 /* Table2764 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2766 /* Table2766 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2768 /* Table2768 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2770 /* Table2770 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2772 /* Table2772 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2774 /* Table2774 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2776 /* Table2776 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2778 /* Table2778 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2780 /* Table2780 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2782 /* Table2782 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2784 /* Table2784 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2786 /* Table2786 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2788 /* Table2788 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2790 /* Table2790 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2792 /* Table2792 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2794 /* Table2794 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2796 /* Table2796 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2798 /* Table2798 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3729 /* Table3729 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2802 /* Table2802 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2804 /* Table2804 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2806 /* Table2806 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2822 /* Table2822 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 2838 /* Table2838 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2854 /* Table2854 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2856 /* Table2856 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2858 /* Table2858 */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2014 /* Table2014 */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3539 /* Table3539 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3541 /* Table3541 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2864 /* Table2864 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2866 /* Table2866 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3731 /* Table3731 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2870 /* Table2870 */ >+ }, >+ /* 0x80 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2872 /* Table2872 */ >+ }, >+ /* 0x81 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2873 /* Table2873 */ >+ }, >+ /* 0x82 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2874 /* Table2874 */ >+ }, >+ /* 0x83 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2875 /* Table2875 */ >+ }, >+ /* 0x84 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2876 /* Table2876 */ >+ }, >+ /* 0x85 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2877 /* Table2877 */ >+ }, >+ /* 0x86 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2878 /* Table2878 */ >+ }, >+ /* 0x87 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2879 /* Table2879 */ >+ }, >+ /* 0x88 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2880 /* Table2880 */ >+ }, >+ /* 0x89 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2881 /* Table2881 */ >+ }, >+ /* 0x8a */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2882 /* Table2882 */ >+ }, >+ /* 0x8b */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2883 /* Table2883 */ >+ }, >+ /* 0x8c */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2884 /* Table2884 */ >+ }, >+ /* 0x8d */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2885 /* Table2885 */ >+ }, >+ /* 0x8e */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2886 /* Table2886 */ >+ }, >+ /* 0x8f */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2887 /* Table2887 */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2039 /* Table2039 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2041 /* Table2041 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2043 /* Table2043 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2045 /* Table2045 */ >+ }, >+ /* 0x94 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2047 /* Table2047 */ >+ }, >+ /* 0x95 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2049 /* Table2049 */ >+ }, >+ /* 0x96 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2051 /* Table2051 */ >+ }, >+ /* 0x97 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2053 /* Table2053 */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2055 /* Table2055 */ >+ }, >+ /* 0x99 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2057 /* Table2057 */ >+ }, >+ /* 0x9a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2059 /* Table2059 */ >+ }, >+ /* 0x9b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2061 /* Table2061 */ >+ }, >+ /* 0x9c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2063 /* Table2063 */ >+ }, >+ /* 0x9d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2065 /* Table2065 */ >+ }, >+ /* 0x9e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2067 /* Table2067 */ >+ }, >+ /* 0x9f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2069 /* Table2069 */ >+ }, >+ /* 0xa0 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2888 /* Table2888 */ >+ }, >+ /* 0xa1 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2889 /* Table2889 */ >+ }, >+ /* 0xa2 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2553 /* Table2553 */ >+ }, >+ /* 0xa3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3320 /* Table3320 */ >+ }, >+ /* 0xa4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3322 /* Table3322 */ >+ }, >+ /* 0xa5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3324 /* Table3324 */ >+ }, >+ /* 0xa6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2080 /* Table2080 */ >+ }, >+ /* 0xa7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 2152 /* Table2152 */ >+ }, >+ /* 0xa8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2896 /* Table2896 */ >+ }, >+ /* 0xa9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2897 /* Table2897 */ >+ }, >+ /* 0xaa */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2226 /* Table2226 */ >+ }, >+ /* 0xab */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3326 /* Table3326 */ >+ }, >+ /* 0xac */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3328 /* Table3328 */ >+ }, >+ /* 0xad */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3330 /* Table3330 */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITMISC, >+ 3332 /* Table3332 */ >+ }, >+ /* 0xaf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3404 /* Table3404 */ >+ }, >+ /* 0xb0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2307 /* Table2307 */ >+ }, >+ /* 0xb1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3406 /* Table3406 */ >+ }, >+ /* 0xb2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3408 /* Table3408 */ >+ }, >+ /* 0xb3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3410 /* Table3410 */ >+ }, >+ /* 0xb4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3412 /* Table3412 */ >+ }, >+ /* 0xb5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3414 /* Table3414 */ >+ }, >+ /* 0xb6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3416 /* Table3416 */ >+ }, >+ /* 0xb7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3418 /* Table3418 */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 2323 /* Table2323 */ >+ }, >+ /* 0xba */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3420 /* Table3420 */ >+ }, >+ /* 0xbb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3436 /* Table3436 */ >+ }, >+ /* 0xbc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3438 /* Table3438 */ >+ }, >+ /* 0xbd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3440 /* Table3440 */ >+ }, >+ /* 0xbe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3442 /* Table3442 */ >+ }, >+ /* 0xbf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3444 /* Table3444 */ >+ }, >+ /* 0xc0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2350 /* Table2350 */ >+ }, >+ /* 0xc1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3446 /* Table3446 */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2944 /* Table2944 */ >+ }, >+ /* 0xc3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3448 /* Table3448 */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2946 /* Table2946 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2948 /* Table2948 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2950 /* Table2950 */ >+ }, >+ /* 0xc7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3733 /* Table3733 */ >+ }, >+ /* 0xc8 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xc9 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xca */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcb */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcc */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcd */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xce */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xcf */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3466 /* Table3466 */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2968 /* Table2968 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2970 /* Table2970 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2972 /* Table2972 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2974 /* Table2974 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2976 /* Table2976 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2978 /* Table2978 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2980 /* Table2980 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2982 /* Table2982 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2984 /* Table2984 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2986 /* Table2986 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2988 /* Table2988 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2990 /* Table2990 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2992 /* Table2992 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2994 /* Table2994 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2996 /* Table2996 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 2998 /* Table2998 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3000 /* Table3000 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3002 /* Table3002 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3004 /* Table3004 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3006 /* Table3006 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3008 /* Table3008 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3010 /* Table3010 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3012 /* Table3012 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3014 /* Table3014 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3016 /* Table3016 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3018 /* Table3018 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3020 /* Table3020 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3022 /* Table3022 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3024 /* Table3024 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3026 /* Table3026 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3028 /* Table3028 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3030 /* Table3030 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3032 /* Table3032 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3034 /* Table3034 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3036 /* Table3036 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3038 /* Table3038 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3040 /* Table3040 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3042 /* Table3042 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3543 /* Table3543 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3046 /* Table3046 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3048 /* Table3048 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3050 /* Table3050 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3052 /* Table3052 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3054 /* Table3054 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3056 /* Table3056 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3058 /* Table3058 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3749 /* Table3749 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3751 /* Table3751 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3753 /* Table3753 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3755 /* Table3755 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3757 /* Table3757 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3759 /* Table3759 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3761 /* Table3761 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3763 /* Table3763 */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3765 /* Table3765 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3767 /* Table3767 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3769 /* Table3769 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3771 /* Table3771 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3773 /* Table3773 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3775 /* Table3775 */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3777 /* Table3777 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3779 /* Table3779 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3781 /* Table3781 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3783 /* Table3783 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3785 /* Table3785 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3787 /* Table3787 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3789 /* Table3789 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3791 /* Table3791 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3793 /* Table3793 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3795 /* Table3795 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3797 /* Table3797 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3799 /* Table3799 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3801 /* Table3801 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3803 /* Table3803 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3805 /* Table3805 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3807 /* Table3807 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3809 /* Table3809 */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3810 /* Table3810 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3812 /* Table3812 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3814 /* Table3814 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3816 /* Table3816 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3818 /* Table3818 */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3820 /* Table3820 */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3836 /* Table3836 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3838 /* Table3838 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3840 /* Table3840 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3842 /* Table3842 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3844 /* Table3844 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3846 /* Table3846 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3848 /* Table3848 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3850 /* Table3850 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3852 /* Table3852 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3854 /* Table3854 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3856 /* Table3856 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3858 /* Table3858 */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3860 /* Table3860 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3862 /* Table3862 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3864 /* Table3864 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3866 /* Table3866 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3868 /* Table3868 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3870 /* Table3870 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3872 /* Table3872 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3874 /* Table3874 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3876 /* Table3876 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3878 /* Table3878 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3880 /* Table3880 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3882 /* Table3882 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3884 /* Table3884 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3886 /* Table3886 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3888 /* Table3888 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3890 /* Table3890 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3892 /* Table3892 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3894 /* Table3894 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3896 /* Table3896 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3898 /* Table3898 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3900 /* Table3900 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3902 /* Table3902 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3904 /* Table3904 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3906 /* Table3906 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3908 /* Table3908 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3910 /* Table3910 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3912 /* Table3912 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3914 /* Table3914 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3916 /* Table3916 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3918 /* Table3918 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3920 /* Table3920 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3922 /* Table3922 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3924 /* Table3924 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3926 /* Table3926 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3928 /* Table3928 */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3930 /* Table3930 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3932 /* Table3932 */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3934 /* Table3934 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3936 /* Table3936 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3938 /* Table3938 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3940 /* Table3940 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3942 /* Table3942 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3944 /* Table3944 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3946 /* Table3946 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3948 /* Table3948 */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3950 /* Table3950 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3952 /* Table3952 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3954 /* Table3954 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3956 /* Table3956 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3958 /* Table3958 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3960 /* Table3960 */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3962 /* Table3962 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3964 /* Table3964 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3966 /* Table3966 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3968 /* Table3968 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3970 /* Table3970 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3972 /* Table3972 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3974 /* Table3974 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3976 /* Table3976 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3978 /* Table3978 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3980 /* Table3980 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3982 /* Table3982 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3984 /* Table3984 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3986 /* Table3986 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3988 /* Table3988 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3990 /* Table3990 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3992 /* Table3992 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3994 /* Table3994 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3996 /* Table3996 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3998 /* Table3998 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4000 /* Table4000 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4002 /* Table4002 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4004 /* Table4004 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4006 /* Table4006 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4008 /* Table4008 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4010 /* Table4010 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4012 /* Table4012 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4014 /* Table4014 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4016 /* Table4016 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4018 /* Table4018 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4020 /* Table4020 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4022 /* Table4022 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4024 /* Table4024 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4040 /* Table4040 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4056 /* Table4056 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4072 /* Table4072 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4074 /* Table4074 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4076 /* Table4076 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4078 /* Table4078 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4080 /* Table4080 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4082 /* Table4082 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4084 /* Table4084 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4086 /* Table4086 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4088 /* Table4088 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4090 /* Table4090 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4092 /* Table4092 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4094 /* Table4094 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4096 /* Table4096 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4098 /* Table4098 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4100 /* Table4100 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4102 /* Table4102 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4104 /* Table4104 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4106 /* Table4106 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4108 /* Table4108 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4110 /* Table4110 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4112 /* Table4112 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4114 /* Table4114 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4116 /* Table4116 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4118 /* Table4118 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4120 /* Table4120 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4122 /* Table4122 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4124 /* Table4124 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4126 /* Table4126 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4128 /* Table4128 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4130 /* Table4130 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4132 /* Table4132 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4134 /* Table4134 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4136 /* Table4136 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4138 /* Table4138 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4140 /* Table4140 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4142 /* Table4142 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4144 /* Table4144 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4146 /* Table4146 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4148 /* Table4148 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4150 /* Table4150 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4152 /* Table4152 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4154 /* Table4154 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4156 /* Table4156 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4158 /* Table4158 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4160 /* Table4160 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4162 /* Table4162 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4164 /* Table4164 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4166 /* Table4166 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4168 /* Table4168 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4170 /* Table4170 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4172 /* Table4172 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4174 /* Table4174 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4176 /* Table4176 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4178 /* Table4178 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4180 /* Table4180 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4182 /* Table4182 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4184 /* Table4184 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4186 /* Table4186 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4188 /* Table4188 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4190 /* Table4190 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4192 /* Table4192 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_W */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3749 /* Table3749 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3751 /* Table3751 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3753 /* Table3753 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3755 /* Table3755 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3757 /* Table3757 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3759 /* Table3759 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3761 /* Table3761 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3763 /* Table3763 */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3765 /* Table3765 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3767 /* Table3767 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3769 /* Table3769 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3771 /* Table3771 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3773 /* Table3773 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4194 /* Table4194 */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3777 /* Table3777 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3779 /* Table3779 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3781 /* Table3781 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3783 /* Table3783 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3785 /* Table3785 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3787 /* Table3787 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3789 /* Table3789 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3791 /* Table3791 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3793 /* Table3793 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3795 /* Table3795 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3797 /* Table3797 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3799 /* Table3799 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3801 /* Table3801 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3803 /* Table3803 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3805 /* Table3805 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3807 /* Table3807 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 3809 /* Table3809 */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4196 /* Table4196 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4198 /* Table4198 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3814 /* Table3814 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3816 /* Table3816 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3818 /* Table3818 */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 3820 /* Table3820 */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3836 /* Table3836 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3838 /* Table3838 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_W_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3840 /* Table3840 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3842 /* Table3842 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3844 /* Table3844 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3846 /* Table3846 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4200 /* Table4200 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4202 /* Table4202 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4204 /* Table4204 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3854 /* Table3854 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3856 /* Table3856 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3858 /* Table3858 */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3860 /* Table3860 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3862 /* Table3862 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3864 /* Table3864 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3866 /* Table3866 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3868 /* Table3868 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3870 /* Table3870 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3872 /* Table3872 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3874 /* Table3874 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3876 /* Table3876 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3878 /* Table3878 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3880 /* Table3880 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3882 /* Table3882 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3884 /* Table3884 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3886 /* Table3886 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_W_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3888 /* Table3888 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3890 /* Table3890 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3892 /* Table3892 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4206 /* Table4206 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4208 /* Table4208 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4210 /* Table4210 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3900 /* Table3900 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3902 /* Table3902 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3904 /* Table3904 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3906 /* Table3906 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3908 /* Table3908 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3910 /* Table3910 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3912 /* Table3912 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3914 /* Table3914 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3916 /* Table3916 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3918 /* Table3918 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3920 /* Table3920 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4212 /* Table4212 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4214 /* Table4214 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3926 /* Table3926 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3928 /* Table3928 */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3930 /* Table3930 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3932 /* Table3932 */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_W_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3934 /* Table3934 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3936 /* Table3936 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3938 /* Table3938 */ >+ }, >+ /* 0x13 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3940 /* Table3940 */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3942 /* Table3942 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3944 /* Table3944 */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3946 /* Table3946 */ >+ }, >+ /* 0x17 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3948 /* Table3948 */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3950 /* Table3950 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3952 /* Table3952 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3954 /* Table3954 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3956 /* Table3956 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3958 /* Table3958 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4216 /* Table4216 */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3962 /* Table3962 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3964 /* Table3964 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3966 /* Table3966 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3968 /* Table3968 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3970 /* Table3970 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3972 /* Table3972 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3974 /* Table3974 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3976 /* Table3976 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3978 /* Table3978 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3980 /* Table3980 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3982 /* Table3982 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3984 /* Table3984 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3986 /* Table3986 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3988 /* Table3988 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3990 /* Table3990 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3992 /* Table3992 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3994 /* Table3994 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3996 /* Table3996 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3998 /* Table3998 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4000 /* Table4000 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4002 /* Table4002 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4004 /* Table4004 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4006 /* Table4006 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4008 /* Table4008 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4010 /* Table4010 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4012 /* Table4012 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4014 /* Table4014 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4016 /* Table4016 */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4218 /* Table4218 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4020 /* Table4020 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4022 /* Table4022 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4024 /* Table4024 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4040 /* Table4040 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4056 /* Table4056 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4072 /* Table4072 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4074 /* Table4074 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4076 /* Table4076 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4078 /* Table4078 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4080 /* Table4080 */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4220 /* Table4220 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4084 /* Table4084 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4222 /* Table4222 */ >+ }, >+ /* 0x91 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4224 /* Table4224 */ >+ }, >+ /* 0x92 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4090 /* Table4090 */ >+ }, >+ /* 0x93 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4092 /* Table4092 */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4094 /* Table4094 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4096 /* Table4096 */ >+ }, >+ /* 0xc5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4098 /* Table4098 */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4100 /* Table4100 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4102 /* Table4102 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4104 /* Table4104 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4106 /* Table4106 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4108 /* Table4108 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4110 /* Table4110 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4112 /* Table4112 */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4114 /* Table4114 */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4116 /* Table4116 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4118 /* Table4118 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4120 /* Table4120 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4122 /* Table4122 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4124 /* Table4124 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4126 /* Table4126 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4128 /* Table4128 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4130 /* Table4130 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4132 /* Table4132 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4134 /* Table4134 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4136 /* Table4136 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4138 /* Table4138 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4140 /* Table4140 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4142 /* Table4142 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4144 /* Table4144 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4146 /* Table4146 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4148 /* Table4148 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4150 /* Table4150 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4152 /* Table4152 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4154 /* Table4154 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4156 /* Table4156 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4158 /* Table4158 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4160 /* Table4160 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4162 /* Table4162 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4164 /* Table4164 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4166 /* Table4166 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4168 /* Table4168 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4170 /* Table4170 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4172 /* Table4172 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4174 /* Table4174 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4176 /* Table4176 */ >+ }, >+ /* 0xf7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4178 /* Table4178 */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4180 /* Table4180 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4182 /* Table4182 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4184 /* Table4184 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4186 /* Table4186 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4188 /* Table4188 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4190 /* Table4190 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4192 /* Table4192 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4226 /* Table4226 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4228 /* Table4228 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4230 /* Table4230 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4232 /* Table4232 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4234 /* Table4234 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4236 /* Table4236 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4238 /* Table4238 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3771 /* Table3771 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3773 /* Table3773 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4240 /* Table4240 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4242 /* Table4242 */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4244 /* Table4244 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4246 /* Table4246 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4248 /* Table4248 */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4250 /* Table4250 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4252 /* Table4252 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4254 /* Table4254 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4256 /* Table4256 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4258 /* Table4258 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4260 /* Table4260 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4262 /* Table4262 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4264 /* Table4264 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4266 /* Table4266 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4268 /* Table4268 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4270 /* Table4270 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4272 /* Table4272 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4274 /* Table4274 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4276 /* Table4276 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4278 /* Table4278 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4280 /* Table4280 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 4282 /* Table4282 */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4283 /* Table4283 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4285 /* Table4285 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3840 /* Table3840 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3842 /* Table3842 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4287 /* Table4287 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4289 /* Table4289 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3848 /* Table3848 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3850 /* Table3850 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3852 /* Table3852 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3854 /* Table3854 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3856 /* Table3856 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3858 /* Table3858 */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3860 /* Table3860 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3862 /* Table3862 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3864 /* Table3864 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4291 /* Table4291 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3868 /* Table3868 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3870 /* Table3870 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3872 /* Table3872 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3874 /* Table3874 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4293 /* Table4293 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4295 /* Table4295 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4297 /* Table4297 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3884 /* Table3884 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4299 /* Table4299 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3888 /* Table3888 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3890 /* Table3890 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4301 /* Table4301 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3894 /* Table3894 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3896 /* Table3896 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3898 /* Table3898 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3900 /* Table3900 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3902 /* Table3902 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3904 /* Table3904 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3906 /* Table3906 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3908 /* Table3908 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3910 /* Table3910 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3912 /* Table3912 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3914 /* Table3914 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4303 /* Table4303 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4305 /* Table4305 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4307 /* Table4307 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3926 /* Table3926 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4309 /* Table4309 */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4311 /* Table4311 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4313 /* Table4313 */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4315 /* Table4315 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4317 /* Table4317 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4319 /* Table4319 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4321 /* Table4321 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4323 /* Table4323 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4325 /* Table4325 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4327 /* Table4327 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3956 /* Table3956 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3958 /* Table3958 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4329 /* Table4329 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4331 /* Table4331 */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4333 /* Table4333 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4335 /* Table4335 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4337 /* Table4337 */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4339 /* Table4339 */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4341 /* Table4341 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4343 /* Table4343 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4345 /* Table4345 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4347 /* Table4347 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4349 /* Table4349 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4351 /* Table4351 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4353 /* Table4353 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4355 /* Table4355 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4357 /* Table4357 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4359 /* Table4359 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4361 /* Table4361 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4363 /* Table4363 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4365 /* Table4365 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4367 /* Table4367 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4369 /* Table4369 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4371 /* Table4371 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4373 /* Table4373 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4375 /* Table4375 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4377 /* Table4377 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4379 /* Table4379 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4381 /* Table4381 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4383 /* Table4383 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4385 /* Table4385 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4387 /* Table4387 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4389 /* Table4389 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4391 /* Table4391 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4393 /* Table4393 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4395 /* Table4395 */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4397 /* Table4397 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4399 /* Table4399 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4401 /* Table4401 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4417 /* Table4417 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4433 /* Table4433 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4449 /* Table4449 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4451 /* Table4451 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4453 /* Table4453 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4455 /* Table4455 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4457 /* Table4457 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4459 /* Table4459 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4461 /* Table4461 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4463 /* Table4463 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4465 /* Table4465 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4467 /* Table4467 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4469 /* Table4469 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4471 /* Table4471 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4473 /* Table4473 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4475 /* Table4475 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4477 /* Table4477 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4479 /* Table4479 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4481 /* Table4481 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4483 /* Table4483 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4485 /* Table4485 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4487 /* Table4487 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4489 /* Table4489 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4491 /* Table4491 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4493 /* Table4493 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4495 /* Table4495 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4497 /* Table4497 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4499 /* Table4499 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4501 /* Table4501 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4503 /* Table4503 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4505 /* Table4505 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4507 /* Table4507 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4509 /* Table4509 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4511 /* Table4511 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4513 /* Table4513 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4515 /* Table4515 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4517 /* Table4517 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4519 /* Table4519 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4521 /* Table4521 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4523 /* Table4523 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4525 /* Table4525 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4527 /* Table4527 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4529 /* Table4529 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4531 /* Table4531 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4533 /* Table4533 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4535 /* Table4535 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4537 /* Table4537 */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4539 /* Table4539 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4541 /* Table4541 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4543 /* Table4543 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4545 /* Table4545 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4547 /* Table4547 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4549 /* Table4549 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4551 /* Table4551 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_W */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4226 /* Table4226 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4228 /* Table4228 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4230 /* Table4230 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4232 /* Table4232 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4234 /* Table4234 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4236 /* Table4236 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4238 /* Table4238 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3771 /* Table3771 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3773 /* Table3773 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4553 /* Table4553 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4555 /* Table4555 */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4557 /* Table4557 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4559 /* Table4559 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4561 /* Table4561 */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4250 /* Table4250 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4252 /* Table4252 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4254 /* Table4254 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4256 /* Table4256 */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4258 /* Table4258 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4260 /* Table4260 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4262 /* Table4262 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4264 /* Table4264 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4266 /* Table4266 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4268 /* Table4268 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4270 /* Table4270 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4272 /* Table4272 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4274 /* Table4274 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4276 /* Table4276 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4278 /* Table4278 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4280 /* Table4280 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* struct ModRMDecision */ >+ MODRM_ONEENTRY, >+ 4282 /* Table4282 */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4283 /* Table4283 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4285 /* Table4285 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_W_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3840 /* Table3840 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3842 /* Table3842 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4287 /* Table4287 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4289 /* Table4289 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4200 /* Table4200 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4202 /* Table4202 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4204 /* Table4204 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3854 /* Table3854 */ >+ }, >+ /* 0x52 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3856 /* Table3856 */ >+ }, >+ /* 0x53 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3858 /* Table3858 */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3860 /* Table3860 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3862 /* Table3862 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3864 /* Table3864 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4291 /* Table4291 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3868 /* Table3868 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3870 /* Table3870 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3872 /* Table3872 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3874 /* Table3874 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4293 /* Table4293 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4295 /* Table4295 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4297 /* Table4297 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3884 /* Table3884 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4299 /* Table4299 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_W_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3888 /* Table3888 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3890 /* Table3890 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4301 /* Table4301 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4206 /* Table4206 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4208 /* Table4208 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4210 /* Table4210 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3900 /* Table3900 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3902 /* Table3902 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3904 /* Table3904 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3906 /* Table3906 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3908 /* Table3908 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3910 /* Table3910 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3912 /* Table3912 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3914 /* Table3914 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4303 /* Table4303 */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4305 /* Table4305 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4307 /* Table4307 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3926 /* Table3926 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4309 /* Table4309 */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4311 /* Table4311 */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4313 /* Table4313 */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_VEX_L_W_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4315 /* Table4315 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4317 /* Table4317 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4319 /* Table4319 */ >+ }, >+ /* 0x15 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4321 /* Table4321 */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4323 /* Table4323 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4325 /* Table4325 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4327 /* Table4327 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3956 /* Table3956 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 3958 /* Table3958 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4563 /* Table4563 */ >+ }, >+ /* 0x42 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4565 /* Table4565 */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4567 /* Table4567 */ >+ }, >+ /* 0x46 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4569 /* Table4569 */ >+ }, >+ /* 0x47 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4571 /* Table4571 */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4339 /* Table4339 */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4341 /* Table4341 */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4343 /* Table4343 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4345 /* Table4345 */ >+ }, >+ /* 0x55 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4347 /* Table4347 */ >+ }, >+ /* 0x56 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4349 /* Table4349 */ >+ }, >+ /* 0x57 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4351 /* Table4351 */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4353 /* Table4353 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4355 /* Table4355 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4357 /* Table4357 */ >+ }, >+ /* 0x5b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4359 /* Table4359 */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4361 /* Table4361 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4363 /* Table4363 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4365 /* Table4365 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4367 /* Table4367 */ >+ }, >+ /* 0x60 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4369 /* Table4369 */ >+ }, >+ /* 0x61 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4371 /* Table4371 */ >+ }, >+ /* 0x62 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4373 /* Table4373 */ >+ }, >+ /* 0x63 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4375 /* Table4375 */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4377 /* Table4377 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4379 /* Table4379 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4381 /* Table4381 */ >+ }, >+ /* 0x67 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4383 /* Table4383 */ >+ }, >+ /* 0x68 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4385 /* Table4385 */ >+ }, >+ /* 0x69 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4387 /* Table4387 */ >+ }, >+ /* 0x6a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4389 /* Table4389 */ >+ }, >+ /* 0x6b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4391 /* Table4391 */ >+ }, >+ /* 0x6c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4393 /* Table4393 */ >+ }, >+ /* 0x6d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4395 /* Table4395 */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4397 /* Table4397 */ >+ }, >+ /* 0x70 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4399 /* Table4399 */ >+ }, >+ /* 0x71 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4401 /* Table4401 */ >+ }, >+ /* 0x72 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4417 /* Table4417 */ >+ }, >+ /* 0x73 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITREG, >+ 4433 /* Table4433 */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4449 /* Table4449 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4451 /* Table4451 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4453 /* Table4453 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4455 /* Table4455 */ >+ }, >+ /* 0x7d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4457 /* Table4457 */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4459 /* Table4459 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4461 /* Table4461 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4463 /* Table4463 */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4465 /* Table4465 */ >+ }, >+ /* 0xd1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4467 /* Table4467 */ >+ }, >+ /* 0xd2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4469 /* Table4469 */ >+ }, >+ /* 0xd3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4471 /* Table4471 */ >+ }, >+ /* 0xd4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4473 /* Table4473 */ >+ }, >+ /* 0xd5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4475 /* Table4475 */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4477 /* Table4477 */ >+ }, >+ /* 0xd8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4479 /* Table4479 */ >+ }, >+ /* 0xd9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4481 /* Table4481 */ >+ }, >+ /* 0xda */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4483 /* Table4483 */ >+ }, >+ /* 0xdb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4485 /* Table4485 */ >+ }, >+ /* 0xdc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4487 /* Table4487 */ >+ }, >+ /* 0xdd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4489 /* Table4489 */ >+ }, >+ /* 0xde */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4491 /* Table4491 */ >+ }, >+ /* 0xdf */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4493 /* Table4493 */ >+ }, >+ /* 0xe0 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4495 /* Table4495 */ >+ }, >+ /* 0xe1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4497 /* Table4497 */ >+ }, >+ /* 0xe2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4499 /* Table4499 */ >+ }, >+ /* 0xe3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4501 /* Table4501 */ >+ }, >+ /* 0xe4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4503 /* Table4503 */ >+ }, >+ /* 0xe5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4505 /* Table4505 */ >+ }, >+ /* 0xe6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4507 /* Table4507 */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4509 /* Table4509 */ >+ }, >+ /* 0xe8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4511 /* Table4511 */ >+ }, >+ /* 0xe9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4513 /* Table4513 */ >+ }, >+ /* 0xea */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4515 /* Table4515 */ >+ }, >+ /* 0xeb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4517 /* Table4517 */ >+ }, >+ /* 0xec */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4519 /* Table4519 */ >+ }, >+ /* 0xed */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4521 /* Table4521 */ >+ }, >+ /* 0xee */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4523 /* Table4523 */ >+ }, >+ /* 0xef */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4525 /* Table4525 */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4527 /* Table4527 */ >+ }, >+ /* 0xf2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4529 /* Table4529 */ >+ }, >+ /* 0xf3 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4531 /* Table4531 */ >+ }, >+ /* 0xf4 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4533 /* Table4533 */ >+ }, >+ /* 0xf5 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4535 /* Table4535 */ >+ }, >+ /* 0xf6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4537 /* Table4537 */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4539 /* Table4539 */ >+ }, >+ /* 0xf9 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4541 /* Table4541 */ >+ }, >+ /* 0xfa */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4543 /* Table4543 */ >+ }, >+ /* 0xfb */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4545 /* Table4545 */ >+ }, >+ /* 0xfc */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4547 /* Table4547 */ >+ }, >+ /* 0xfd */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4549 /* Table4549 */ >+ }, >+ /* 0xfe */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4551 /* Table4551 */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4573 /* Table4573 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4575 /* Table4575 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4577 /* Table4577 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4579 /* Table4579 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4581 /* Table4581 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4583 /* Table4583 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4585 /* Table4585 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4587 /* Table4587 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4589 /* Table4589 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4591 /* Table4591 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4593 /* Table4593 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4595 /* Table4595 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4597 /* Table4597 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4599 /* Table4599 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4601 /* Table4601 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4603 /* Table4603 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4605 /* Table4605 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4607 /* Table4607 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4609 /* Table4609 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4611 /* Table4611 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4613 /* Table4613 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4615 /* Table4615 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4617 /* Table4617 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4619 /* Table4619 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4621 /* Table4621 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4623 /* Table4623 */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4625 /* Table4625 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4627 /* Table4627 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4629 /* Table4629 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4631 /* Table4631 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4633 /* Table4633 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4635 /* Table4635 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4637 /* Table4637 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4639 /* Table4639 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4641 /* Table4641 */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4643 /* Table4643 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4645 /* Table4645 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4647 /* Table4647 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4649 /* Table4649 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4651 /* Table4651 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4653 /* Table4653 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4655 /* Table4655 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4657 /* Table4657 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4659 /* Table4659 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4661 /* Table4661 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4663 /* Table4663 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4665 /* Table4665 */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_W */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4573 /* Table4573 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4575 /* Table4575 */ >+ }, >+ /* 0x12 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4577 /* Table4577 */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4579 /* Table4579 */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4581 /* Table4581 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4583 /* Table4583 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4585 /* Table4585 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4587 /* Table4587 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4589 /* Table4589 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_W_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4591 /* Table4591 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4593 /* Table4593 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4667 /* Table4667 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4669 /* Table4669 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4671 /* Table4671 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4601 /* Table4601 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4603 /* Table4603 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4605 /* Table4605 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4607 /* Table4607 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4609 /* Table4609 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4611 /* Table4611 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4613 /* Table4613 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4615 /* Table4615 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4673 /* Table4673 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4675 /* Table4675 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4677 /* Table4677 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4679 /* Table4679 */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4681 /* Table4681 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4683 /* Table4683 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4627 /* Table4627 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_W_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4685 /* Table4685 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4687 /* Table4687 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4689 /* Table4689 */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4691 /* Table4691 */ >+ }, >+ /* 0x2d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4693 /* Table4693 */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4695 /* Table4695 */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4697 /* Table4697 */ >+ }, >+ /* 0x59 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4699 /* Table4699 */ >+ }, >+ /* 0x5a */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4701 /* Table4701 */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4703 /* Table4703 */ >+ }, >+ /* 0x5d */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4705 /* Table4705 */ >+ }, >+ /* 0x5e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4707 /* Table4707 */ >+ }, >+ /* 0x5f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4709 /* Table4709 */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4711 /* Table4711 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4713 /* Table4713 */ >+ }, >+ /* 0x79 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4715 /* Table4715 */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4717 /* Table4717 */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4719 /* Table4719 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4721 /* Table4721 */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_W_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4723 /* Table4723 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4725 /* Table4725 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4727 /* Table4727 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4729 /* Table4729 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4731 /* Table4731 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4733 /* Table4733 */ >+ }, >+ /* 0x2f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4735 /* Table4735 */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4645 /* Table4645 */ >+ }, >+ /* 0x65 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4647 /* Table4647 */ >+ }, >+ /* 0x66 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4649 /* Table4649 */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4737 /* Table4737 */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4739 /* Table4739 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4655 /* Table4655 */ >+ }, >+ /* 0x75 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4657 /* Table4657 */ >+ }, >+ /* 0x76 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4659 /* Table4659 */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4741 /* Table4741 */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4743 /* Table4743 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4745 /* Table4745 */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4665 /* Table4665 */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_L */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4747 /* Table4747 */ >+ }, >+ /* 0x11 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4749 /* Table4749 */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4751 /* Table4751 */ >+ }, >+ /* 0x29 */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4753 /* Table4753 */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4755 /* Table4755 */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_L_XS */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4757 /* Table4757 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4759 /* Table4759 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_L_XD */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x64 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x65 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x66 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x67 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x68 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x69 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x6f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4761 /* Table4761 */ >+ }, >+ /* 0x70 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x71 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x72 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x73 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x74 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x75 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x76 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x77 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x78 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x79 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x7f */ >+ { /* struct ModRMDecision */ >+ MODRM_SPLITRM, >+ 4763 /* Table4763 */ >+ }, >+ /* 0x80 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x81 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x82 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x83 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x84 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x85 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x86 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x87 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x88 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x89 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x8f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x90 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x91 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x92 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x93 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x94 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x95 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x96 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x97 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x98 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x99 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x9f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xa9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xab */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xac */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xad */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xae */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xaf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xb9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xba */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xbf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xc9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xca */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xce */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xcf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xd9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xda */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xde */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xdf */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xe9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xea */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xeb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xec */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xed */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xee */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xef */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf0 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf1 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf2 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf3 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf4 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf5 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf6 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf7 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf8 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xf9 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfa */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfb */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfc */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfd */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xfe */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0xff */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ } >+ } >+ } >+, /* IC_EVEX_L_OPSIZE */ >+ { /* struct OpcodeDecision */ >+ { >+ /* 0x00 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x01 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x02 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x03 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x04 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x05 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x06 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x07 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x08 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x09 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x0f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x10 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x11 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x12 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x13 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x14 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x15 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x16 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x17 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x18 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x19 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x1f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x20 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x21 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x22 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x23 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x24 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x25 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x26 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x27 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x28 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x29 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x2f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x30 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x31 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x32 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x33 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x34 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x35 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x36 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x37 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x38 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x39 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x3f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x40 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x41 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x42 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x43 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x44 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x45 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x46 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x47 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x48 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x49 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x4f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x50 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x51 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x52 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x53 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x54 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x55 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x56 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x57 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x58 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x59 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5a */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5b */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5c */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5d */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5e */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x5f */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x60 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x61 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x62 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >+ /* 0x63 */ >+ { /* ModRMDecision */ >+ MODRM_ONEENTRY, >+ 0 /* EmptyTable */ >+ }, >