Attachment 339239 Details for Bug 185106 – patch

[patch] patch

0001-Macro-assembler-micro-optimizations-for-x86-64-and-A.patch (text/plain), 23.42 KB, created by JF Bastien on 2018-05-01 16:28:07 PDT

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Creator: JF Bastien

Created: 2018-05-01 16:28:07 PDT

Size: 23.42 KB

patch

obsolete

>From 5077e08a55b5dceecb834c3f28d89f10737ae126 Mon Sep 17 00:00:00 2001
>From: JF Bastien <jfbastien@apple.com>
>Date: Fri, 27 Apr 2018 21:11:16 -0700
>Subject: [PATCH] Macro assembler micro-optimizations for x86-64 and ARM64
>
>---
> Source/JavaScriptCore/ChangeLog                    |  49 ++++++++
> Source/JavaScriptCore/assembler/MacroAssembler.h   | 134 ++++++++++++++++++---
> .../JavaScriptCore/assembler/MacroAssemblerARM64.h |  97 +++++++++++----
> .../assembler/MacroAssemblerX86Common.h            |  12 ++
> .../assembler/MacroAssemblerX86_64.h               | 103 +++++++++++++++-
> Source/JavaScriptCore/assembler/X86Assembler.h     |  12 +-
> 6 files changed, 359 insertions(+), 48 deletions(-)
>
>diff --git a/Source/JavaScriptCore/ChangeLog b/Source/JavaScriptCore/ChangeLog
>index cadf6a9..3701dc1 100644
>--- a/Source/JavaScriptCore/ChangeLog
>+++ b/Source/JavaScriptCore/ChangeLog
>@@ -1,5 +1,54 @@
> 2018-04-27  JF Bastien  <jfbastien@apple.com>
> 
>+        Macro assembler micro-optimizations for x86-64 and ARM64
>+        https://bugs.webkit.org/show_bug.cgi?id=185106
>+
>+        Reviewed by NOBODY (OOPS!).
>+
>+        Micro-optimizations, and a few annoying missing permutations of
>+        existing macro-ops. Most optimizations avoid using an extra
>+        register, use smaller immediates, smaller instruction encodings,
>+        etc.
>+
>+        * assembler/MacroAssembler.h:
>+        (JSC::MacroAssembler::trustedImm32ForShift):
>+        (JSC::MacroAssembler::compare32):
>+        (JSC::MacroAssembler::lshiftPtr):
>+        (JSC::MacroAssembler::rshiftPtr):
>+        (JSC::MacroAssembler::urshiftPtr):
>+        (JSC::MacroAssembler::branchPtr):
>+        (JSC::MacroAssembler::mulPtr):
>+        (JSC::MacroAssembler::andPtr):
>+        (JSC::MacroAssembler::subPtr):
>+        (JSC::MacroAssembler::comparePtr):
>+        (JSC::MacroAssembler::mul32):
>+        * assembler/MacroAssemblerARM64.h:
>+        (JSC::MacroAssemblerARM64::add64):
>+        (JSC::MacroAssemblerARM64::and32):
>+        (JSC::MacroAssemblerARM64::and64):
>+        (JSC::MacroAssemblerARM64::mul32):
>+        (JSC::MacroAssemblerARM64::or32):
>+        (JSC::MacroAssemblerARM64::or64):
>+        (JSC::MacroAssemblerARM64::sub64):
>+        (JSC::MacroAssemblerARM64::xor32):
>+        (JSC::MacroAssemblerARM64::xor64):
>+        (JSC::MacroAssemblerARM64::compare32):
>+        (JSC::MacroAssemblerARM64::compare64):
>+        (JSC::MacroAssemblerARM64::test64):
>+        * assembler/MacroAssemblerX86Common.h:
>+        (JSC::MacroAssemblerX86Common::compare32):
>+        * assembler/MacroAssemblerX86_64.h:
>+        (JSC::MacroAssemblerX86_64::and64):
>+        (JSC::MacroAssemblerX86_64::mul64):
>+        (JSC::MacroAssemblerX86_64::sub64):
>+        (JSC::MacroAssemblerX86_64::compare64):
>+        (JSC::MacroAssemblerX86_64::branch64):
>+        * assembler/X86Assembler.h:
>+        (JSC::X86Assembler::imull_i32r):
>+        (JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
>+
>+2018-04-27  JF Bastien  <jfbastien@apple.com>
>+
>         Make the first 64 bits of JSString look like a double JSValue
>         https://bugs.webkit.org/show_bug.cgi?id=185081
> 
>diff --git a/Source/JavaScriptCore/assembler/MacroAssembler.h b/Source/JavaScriptCore/assembler/MacroAssembler.h
>index d25da3c..c23b0a6 100644
>--- a/Source/JavaScriptCore/assembler/MacroAssembler.h
>+++ b/Source/JavaScriptCore/assembler/MacroAssembler.h
>@@ -356,14 +356,17 @@ public:
>     }
> #endif
> 
>-    // Immediate shifts only have 5 controllable bits
>-    // so we'll consider them safe for now.
>     TrustedImm32 trustedImm32ForShift(Imm32 imm)
>     {
>         return TrustedImm32(imm.asTrustedImm32().m_value & 31);
>     }
> 
>-    // Backwards banches, these are currently all implemented using existing forwards branch mechanisms.
>+    TrustedImm32 trustedImm32ForShift(TrustedImm32 imm)
>+    {
>+        return TrustedImm32(imm.m_value & 31);
>+    }
>+
>+    // Backwards branches, these are currently all implemented using existing forwards branch mechanisms.
>     void branchPtr(RelationalCondition cond, RegisterID op1, TrustedImmPtr imm, Label target)
>     {
>         branchPtr(cond, op1, imm).linkTo(target, this);
>@@ -412,7 +415,7 @@ public:
>     {
>         compare32(commute(cond), right, left, dest);
>     }
>-
>+    
>     void branchTestPtr(ResultCondition cond, RegisterID reg, Label target)
>     {
>         branchTestPtr(cond, reg).linkTo(target, this);
>@@ -604,21 +607,11 @@ public:
>         lshift32(trustedImm32ForShift(imm), srcDest);
>     }
>     
>-    void lshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>-    {
>-        lshift32(imm, srcDest);
>-    }
>-    
>     void rshiftPtr(Imm32 imm, RegisterID srcDest)
>     {
>         rshift32(trustedImm32ForShift(imm), srcDest);
>     }
> 
>-    void rshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>-    {
>-        rshift32(imm, srcDest);
>-    }
>-
>     void urshiftPtr(Imm32 imm, RegisterID srcDest)
>     {
>         urshift32(trustedImm32ForShift(imm), srcDest);
>@@ -628,6 +621,21 @@ public:
>     {
>         urshift32(shiftAmmount, srcDest);
>     }
>+    
>+    void lshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>+    {
>+        lshift32(trustedImm32ForShift(imm), srcDest);
>+    }
>+    
>+    void rshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>+    {
>+        rshift32(trustedImm32ForShift(imm), srcDest);
>+    }
>+    
>+    void urshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>+    {
>+        urshift32(trustedImm32ForShift(imm), srcDest);
>+    }
> 
>     void negPtr(RegisterID dest)
>     {
>@@ -826,9 +834,9 @@ public:
>         return branch32(cond, left, TrustedImm32(right));
>     }
>     
>-    Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, TrustedImmPtr right)
>+    Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
>     {
>-        return branch32(cond, left, TrustedImm32(right));
>+        return branch32(cond, left, right);
>     }
> 
>     Jump branchSubPtr(ResultCondition cond, RegisterID src, RegisterID dest)
>@@ -917,22 +925,57 @@ public:
>     {
>         add64(imm, address);
>     }
>-
>+    
>     void andPtr(RegisterID src, RegisterID dest)
>     {
>         and64(src, dest);
>     }
> 
>+    void andPtr(RegisterID left, RegisterID right, RegisterID dest)
>+    {
>+        and64(left, right, dest);
>+    }
>+
>     void andPtr(TrustedImm32 imm, RegisterID srcDest)
>     {
>         and64(imm, srcDest);
>     }
>+
>+    void andPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        and64(imm, src, dest);
>+    }
>+    
>+    void andPtr(TrustedImm64 imm, RegisterID srcDest)
>+    {
>+        and64(imm, srcDest, srcDest);
>+    }
>+    
>+    void andPtr(TrustedImm64 imm, RegisterID src, RegisterID dest)
>+    {
>+        and64(imm, src, dest);
>+    }
>+    
>+    void andPtr(RegisterID src, TrustedImm32 imm, RegisterID dest)
>+    {
>+        and64(imm, src, dest);
>+    }
>     
>     void andPtr(TrustedImmPtr imm, RegisterID srcDest)
>     {
>         and64(imm, srcDest);
>     }
>     
>+    void andPtr(TrustedImmPtr imm, RegisterID src, RegisterID dest)
>+    {
>+        and64(imm, src, dest);
>+    }
>+    
>+    void andPtr(RegisterID src, TrustedImmPtr imm, RegisterID dest)
>+    {
>+        and64(imm, src, dest);
>+    }
>+    
>     void lshiftPtr(Imm32 imm, RegisterID srcDest)
>     {
>         lshift64(trustedImm32ForShift(imm), srcDest);
>@@ -962,6 +1005,11 @@ public:
>     {
>         urshift64(shiftAmmount, srcDest);
>     }
>+    
>+    void urshiftPtr(TrustedImm32 imm, RegisterID srcDest)
>+    {
>+        urshift64(trustedImm32ForShift(imm), srcDest);
>+    }
> 
>     void negPtr(RegisterID dest)
>     {
>@@ -1007,16 +1055,41 @@ public:
>     {
>         sub64(src, dest);
>     }
>-    
>+
>+    void subPtr(RegisterID left, RegisterID right, RegisterID dest)
>+    {
>+        sub64(left, right, dest);
>+    }
>+
>     void subPtr(TrustedImm32 imm, RegisterID dest)
>     {
>         sub64(imm, dest);
>     }
>     
>+    void subPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        sub64(imm, src, dest);
>+    }
>+    
>+    void subPtr(RegisterID src, TrustedImm32 imm, RegisterID dest)
>+    {
>+        sub64(src, imm, dest);
>+    }
>+    
>     void subPtr(TrustedImmPtr imm, RegisterID dest)
>     {
>         sub64(TrustedImm64(imm), dest);
>     }
>+    
>+    void subPtr(TrustedImmPtr imm, RegisterID src, RegisterID dest)
>+    {
>+        sub64(TrustedImm64(imm), src, dest);
>+    }
>+    
>+    void subPtr(RegisterID src, TrustedImmPtr imm, RegisterID dest)
>+    {
>+        sub64(src, TrustedImm64(imm), dest);
>+    }
> 
>     void xorPtr(RegisterID src, RegisterID dest)
>     {
>@@ -1145,6 +1218,16 @@ public:
>         return branch64(cond, left, TrustedImm64(right));
>     }
>     
>+    Jump branchPtr(RelationalCondition cond, RegisterID left, TrustedImm32 right)
>+    {
>+        return branch64(cond, left, right);
>+    }
>+    
>+    Jump branchPtr(RelationalCondition cond, RegisterID left, TrustedImm64 right)
>+    {
>+        return branch64(cond, left, right);
>+    }
>+    
>     Jump branchPtr(RelationalCondition cond, RegisterID left, Address right)
>     {
>         return branch64(cond, left, right);
>@@ -1164,6 +1247,11 @@ public:
>     {
>         return branch64(cond, left, TrustedImm64(right));
>     }
>+    
>+    Jump branchPtr(RelationalCondition cond, RegisterID left, BaseIndex right)
>+    {
>+        return branch64(commute(cond), right, left);
>+    }
> 
>     Jump branchTestPtr(ResultCondition cond, RegisterID reg, RegisterID mask)
>     {
>@@ -1645,6 +1733,16 @@ public:
>         mul32(imm.asTrustedImm32(), src, dest);
>     }
> 
>+    void mul32(Imm32 imm, RegisterID srcDest)
>+    {
>+        mul32(imm, srcDest, srcDest);
>+    }
>+    
>+    void mul32(TrustedImm32 imm, RegisterID srcDest)
>+    {
>+        mul32(imm, srcDest, srcDest);
>+    }
>+
>     void and32(Imm32 imm, RegisterID dest)
>     {
>         if (shouldBlind(imm)) {
>diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
>index bbf38dc..29ebed4 100644
>--- a/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
>+++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
>@@ -401,32 +401,42 @@ public:
>         m_assembler.and_<64>(dest, dest, src);
>     }
> 
>-    void and64(TrustedImm32 imm, RegisterID dest)
>+    void and64(TrustedImm32 imm, RegisterID src, RegisterID dest)
>     {
>         LogicalImmediate logicalImm = LogicalImmediate::create64(static_cast<intptr_t>(static_cast<int64_t>(imm.m_value)));
> 
>         if (logicalImm.isValid()) {
>-            m_assembler.and_<64>(dest, dest, logicalImm);
>+            m_assembler.and_<64>(dest, src, logicalImm);
>             return;
>         }
> 
>         signExtend32ToPtr(imm, getCachedDataTempRegisterIDAndInvalidate());
>-        m_assembler.and_<64>(dest, dest, dataTempRegister);
>+        m_assembler.and_<64>(dest, src, dataTempRegister);
>     }
> 
>-    void and64(TrustedImmPtr imm, RegisterID dest)
>+    void and64(TrustedImm32 imm, RegisterID dest)
>+    {
>+        and64(imm, dest, dest);
>+    }
>+
>+    void and64(TrustedImmPtr imm, RegisterID src, RegisterID dest)
>     {
>         LogicalImmediate logicalImm = LogicalImmediate::create64(reinterpret_cast<uint64_t>(imm.m_value));
> 
>         if (logicalImm.isValid()) {
>-            m_assembler.and_<64>(dest, dest, logicalImm);
>+            m_assembler.and_<64>(dest, src, logicalImm);
>             return;
>         }
> 
>         move(imm, getCachedDataTempRegisterIDAndInvalidate());
>-        m_assembler.and_<64>(dest, dest, dataTempRegister);
>+        m_assembler.and_<64>(dest, src, dataTempRegister);
>     }
>-    
>+
>+    void and64(TrustedImmPtr imm, RegisterID dest)
>+    {
>+        return and64(imm, dest, dest);
>+    }
>+
>     void countLeadingZeros32(RegisterID src, RegisterID dest)
>     {
>         m_assembler.clz<32>(dest, src);
>@@ -617,7 +627,6 @@ public:
>             return;
>         }
> 
>-        ASSERT(src != dataTempRegister);
>         move(imm, getCachedDataTempRegisterIDAndInvalidate());
>         m_assembler.orr<32>(dest, src, dataTempRegister);
>     }
>@@ -854,34 +863,76 @@ public:
>     
>     void sub64(TrustedImm32 imm, RegisterID dest)
>     {
>+        sub64(dest, imm, dest);
>+    }
>+    
>+    void sub64(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        if (isUInt12(-imm.m_value)) {
>+            m_assembler.add<64>(dest, src, UInt12(-imm.m_value));
>+            return;
>+        }
>         if (isUInt12(imm.m_value)) {
>-            m_assembler.sub<64>(dest, dest, UInt12(imm.m_value));
>+            m_assembler.sub<64>(dest, src, UInt12(imm.m_value));
>+            return;
>+        }
>+
>+        signExtend32ToPtr(TrustedImm32(-imm.m_value), getCachedDataTempRegisterIDAndInvalidate());
>+        m_assembler.add<64>(dest, src, dataTempRegister);
>+    }
>+
>+    void sub64(RegisterID src, TrustedImm32 imm, RegisterID dest)
>+    {
>+        if (isUInt12(imm.m_value)) {
>+            m_assembler.sub<64>(dest, src, UInt12(imm.m_value));
>             return;
>         }
>         if (isUInt12(-imm.m_value)) {
>-            m_assembler.add<64>(dest, dest, UInt12(-imm.m_value));
>+            m_assembler.add<64>(dest, src, UInt12(-imm.m_value));
>             return;
>         }
>-
>+        
>         signExtend32ToPtr(imm, getCachedDataTempRegisterIDAndInvalidate());
>-        m_assembler.sub<64>(dest, dest, dataTempRegister);
>+        m_assembler.sub<64>(dest, src, dataTempRegister);
>     }
>-    
>+
>     void sub64(TrustedImm64 imm, RegisterID dest)
>     {
>-        intptr_t immediate = imm.m_value;
>+        sub64(dest, imm, dest);
>+    }
> 
>+    void sub64(TrustedImm64 imm, RegisterID src, RegisterID dest)
>+    {
>+        intptr_t immediate = imm.m_value;
>+        
>+        if (isUInt12(-immediate)) {
>+            m_assembler.add<64>(dest, src, UInt12(static_cast<int32_t>(-immediate)));
>+            return;
>+        }
>         if (isUInt12(immediate)) {
>-            m_assembler.sub<64>(dest, dest, UInt12(static_cast<int32_t>(immediate)));
>+            m_assembler.sub<64>(dest, src, UInt12(static_cast<int32_t>(immediate)));
>+            return;
>+        }
>+        
>+        move(TrustedImm64(-immediate), getCachedDataTempRegisterIDAndInvalidate());
>+        m_assembler.add<64>(dest, src, dataTempRegister);
>+    }
>+    
>+    void sub64(RegisterID src, TrustedImm64 imm, RegisterID dest)
>+    {
>+        intptr_t immediate = imm.m_value;
>+        
>+        if (isUInt12(immediate)) {
>+            m_assembler.sub<64>(dest, src, UInt12(static_cast<int32_t>(immediate)));
>             return;
>         }
>         if (isUInt12(-immediate)) {
>-            m_assembler.add<64>(dest, dest, UInt12(static_cast<int32_t>(-immediate)));
>+            m_assembler.add<64>(dest, src, UInt12(static_cast<int32_t>(-immediate)));
>             return;
>         }
>-
>+        
>         move(imm, getCachedDataTempRegisterIDAndInvalidate());
>-        m_assembler.sub<64>(dest, dest, dataTempRegister);
>+        m_assembler.sub<64>(dest, src, dataTempRegister);
>     }
> 
>     void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
>@@ -3221,13 +3272,14 @@ public:
>             }
>         }
> 
>+        RegisterID scratch = left != dest ? dest : getCachedDataTempRegisterIDAndInvalidate();
>         if (isUInt12(right.m_value))
>             m_assembler.cmp<32>(left, UInt12(right.m_value));
>         else if (isUInt12(-right.m_value))
>             m_assembler.cmn<32>(left, UInt12(-right.m_value));
>         else {
>-            move(right, getCachedDataTempRegisterIDAndInvalidate());
>-            m_assembler.cmp<32>(left, dataTempRegister);
>+            move(right, scratch);
>+            m_assembler.cmp<32>(left, scratch);
>         }
>         m_assembler.cset<32>(dest, ARM64Condition(cond));
>     }
>@@ -3247,8 +3299,9 @@ public:
>             }
>         }
> 
>-        signExtend32ToPtr(right, getCachedDataTempRegisterIDAndInvalidate());
>-        m_assembler.cmp<64>(left, dataTempRegister);
>+        RegisterID scratch = left != dest ? dest : getCachedDataTempRegisterIDAndInvalidate();
>+        signExtend32ToPtr(right, scratch);
>+        m_assembler.cmp<64>(left, scratch);
>         m_assembler.cset<32>(dest, ARM64Condition(cond));
>     }
> 
>diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h b/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h
>index 3b2233a..e4bb48e 100644
>--- a/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h
>+++ b/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h
>@@ -2971,6 +2971,18 @@ public:
>         m_assembler.cmpl_ir(right.m_value, left);
>         set32(x86Condition(cond), dest);
>     }
>+    
>+    void compare32(RelationalCondition cond, RegisterID left, Address right, RegisterID dest)
>+    {
>+        m_assembler.cmpl_mr(right.offset, right.base, left);
>+        set32(x86Condition(cond), dest);
>+    }
>+
>+    void compare32(RelationalCondition cond, TrustedImm32 left, Address right, RegisterID dest)
>+    {
>+        m_assembler.cmpl_im(left.m_value, right.offset, right.base);
>+        set32(x86Condition(cond), dest);
>+    }
> 
>     // FIXME:
>     // The mask should be optional... perhaps the argument order should be
>diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h b/Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h
>index d4428cc..e635f94 100644
>--- a/Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h
>+++ b/Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h
>@@ -418,9 +418,9 @@ public:
>         m_assembler.andq_im(imm.m_value, dest.offset, dest.base, dest.index, dest.scale);
>     }
> 
>-    void and64(TrustedImmPtr imm, RegisterID srcDest)
>+    void and64(TrustedImm64 imm, RegisterID srcDest)
>     {
>-        intptr_t intValue = imm.asIntptr();
>+        int64_t intValue = imm.m_value;
>         if (intValue <= std::numeric_limits<int32_t>::max()
>             && intValue >= std::numeric_limits<int32_t>::min()) {
>             and64(TrustedImm32(static_cast<int32_t>(intValue)), srcDest);
>@@ -430,6 +430,11 @@ public:
>         and64(scratchRegister(), srcDest);
>     }
> 
>+    void and64(TrustedImmPtr imm, RegisterID srcDest)
>+    {
>+        and64(TrustedImm64(imm.asIntptr()), srcDest);
>+    }
>+
>     void and64(RegisterID op1, RegisterID op2, RegisterID dest)
>     {
>         if (op1 == op2 && op1 != dest && op2 != dest)
>@@ -441,6 +446,34 @@ public:
>             and64(op1, dest);
>         }
>     }
>+    
>+    void and64(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        if (src != dest)
>+            move(src, dest);
>+        and64(imm, dest);
>+    }
>+
>+    void and64(TrustedImm64 imm, RegisterID src, RegisterID dest)
>+    {
>+        if (src == dest)
>+            return and64(imm, dest);
>+
>+        int64_t intValue = imm.m_value;
>+        if (intValue <= std::numeric_limits<int32_t>::max()
>+            && intValue >= std::numeric_limits<int32_t>::min()) {
>+            move(src, dest);
>+            return and64(TrustedImm32(static_cast<int32_t>(intValue)), dest);
>+        }
>+
>+        move(imm, dest);
>+        and64(src, dest);
>+    }
>+    
>+    void and64(TrustedImmPtr imm, RegisterID src, RegisterID dest)
>+    {
>+        and64(TrustedImm64(imm.asIntptr()), src, dest);
>+    }
> 
>     void countLeadingZeros64(RegisterID src, RegisterID dst)
>     {
>@@ -578,6 +611,11 @@ public:
>             swap(src, X86Registers::ecx);
>         }
>     }
>+    
>+    void mul64(TrustedImm32 imm, RegisterID dest)
>+    {
>+        mul64(imm, dest, dest);
>+    }
> 
>     void mul64(RegisterID src, RegisterID dest)
>     {
>@@ -594,6 +632,11 @@ public:
>         m_assembler.imulq_rr(src2, dest);
>     }
>     
>+    void mul64(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        m_assembler.imull_i32r(src, imm.m_value, dest);
>+    }
>+    
>     void x86ConvertToQuadWord64()
>     {
>         m_assembler.cqo();
>@@ -724,7 +767,23 @@ public:
>     {
>         m_assembler.subq_rr(src, dest);
>     }
>-    
>+
>+    void sub64(RegisterID left, RegisterID right, RegisterID dest)
>+    {
>+        if (left == right)
>+            move(TrustedImm32(0), dest);
>+        else if (left == dest)
>+            sub64(right, dest);
>+        else if (right != dest) {
>+            move(left, dest);
>+            sub64(right, dest);
>+        } else {
>+            move(right, scratchRegister());
>+            move(left, dest);
>+            sub64(scratchRegister(), dest);
>+        }
>+    }
>+
>     void sub64(TrustedImm32 imm, RegisterID dest)
>     {
>         if (imm.m_value == 1)
>@@ -733,6 +792,21 @@ public:
>             m_assembler.subq_ir(imm.m_value, dest);
>     }
>     
>+    void sub64(TrustedImm32 imm, RegisterID src, RegisterID dest)
>+    {
>+        add64(TrustedImm32(-imm.m_value), src, dest);
>+    }
>+
>+    void sub64(RegisterID src, TrustedImm32 imm, RegisterID dest)
>+    {
>+        if (src == dest)
>+            sub64(imm, dest);
>+        else {
>+            move(src, dest);
>+            sub64(imm, dest);
>+        }
>+    }
>+
>     void sub64(TrustedImm64 imm, RegisterID dest)
>     {
>         if (imm.m_value == 1)
>@@ -743,6 +817,19 @@ public:
>         }
>     }
> 
>+    void sub64(TrustedImm64 imm, RegisterID src, RegisterID dest)
>+    {
>+        move(imm, scratchRegister());
>+        sub64(src, scratchRegister());
>+        move(scratchRegister(), dest);
>+    }
>+
>+    void sub64(RegisterID src, TrustedImm64 imm, RegisterID dest)
>+    {
>+        move(src, dest);
>+        sub64(imm, dest);
>+    }
>+
>     void sub64(TrustedImm32 imm, Address address)
>     {
>         m_assembler.subq_im(imm.m_value, address.offset, address.base);
>@@ -982,6 +1069,12 @@ public:
>         m_assembler.cmpq_rr(right, left);
>         set32(x86Condition(cond), dest);
>     }
>+    
>+    void compare64(RelationalCondition cond, RegisterID left, Address right, RegisterID dest)
>+    {
>+        m_assembler.cmpq_mr(right.offset, right.base, left);
>+        set32(x86Condition(cond), dest);
>+    }
> 
>     void compareDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID dest)
>     {
>@@ -1073,9 +1166,9 @@ public:
>         return branch64(cond, left, scratchRegister());
>     }
> 
>-    Jump branch64(RelationalCondition cond, BaseIndex address, RegisterID right)
>+    Jump branch64(RelationalCondition cond, BaseIndex index, RegisterID right)
>     {
>-        m_assembler.cmpq_rm(right, address.offset, address.base, address.index, address.scale);
>+        m_assembler.cmpq_rm(right, index.offset, index.base, index.index, index.scale);
>         return Jump(m_assembler.jCC(x86Condition(cond)));
>     }
>     
>diff --git a/Source/JavaScriptCore/assembler/X86Assembler.h b/Source/JavaScriptCore/assembler/X86Assembler.h
>index 51fb333..9958672 100644
>--- a/Source/JavaScriptCore/assembler/X86Assembler.h
>+++ b/Source/JavaScriptCore/assembler/X86Assembler.h
>@@ -246,6 +246,7 @@ private:
>         PRE_SSE_66                      = 0x66,
>         OP_PUSH_Iz                      = 0x68,
>         OP_IMUL_GvEvIz                  = 0x69,
>+        OP_IMUL_GvEvIb                  = 0x6B,
>         OP_GROUP1_EbIb                  = 0x80,
>         OP_GROUP1_EvIz                  = 0x81,
>         OP_GROUP1_EvIb                  = 0x83,
>@@ -1836,8 +1837,13 @@ public:
> 
>     void imull_i32r(RegisterID src, int32_t value, RegisterID dst)
>     {
>-        m_formatter.oneByteOp(OP_IMUL_GvEvIz, dst, src);
>-        m_formatter.immediate32(value);
>+        if (CAN_SIGN_EXTEND_8_32(value)) {
>+            m_formatter.oneByteOp(OP_IMUL_GvEvIb, dst, src);
>+            m_formatter.immediate8(value);
>+        } else {
>+            m_formatter.oneByteOp(OP_IMUL_GvEvIz, dst, src);
>+            m_formatter.immediate32(value);
>+        }
>     }
> 
>     void divl_r(RegisterID dst)
>@@ -4619,7 +4625,7 @@ private:
> 
>         // Immediates:
>         //
>-        // An immedaite should be appended where appropriate after an op has been emitted.
>+        // An immediate should be appended where appropriate after an op has been emitted.
>         // The writes are unchecked since the opcode formatters above will have ensured space.
> 
>         void immediate8(int imm)
>-- 
>2.9.3
>

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Attachments on bug 185106: 339056 | 339058 | 339149 | 339206 | 339217 | 339239