Source/JavaScriptCore/ChangeLog

 12012-06-17 Filip Pizlo <fpizlo@apple.com>
 2
 3 It should be possible to look at disassembly
 4 https://bugs.webkit.org/show_bug.cgi?id=89319
 5
 6 Reviewed by Sam Weinig.
 7
 8 This imports the udis86 disassembler library. The library is placed
 9 behind an abstraction in disassembler/Disassembler.h, so that we can
 10 in the future use other disassemblers (for other platforms) whenever
 11 appropriate. As a first step, the disassembler is being invoked for
 12 DFG verbose dumps.
 13
 14 If we ever want to merge a new version of udis86 in the future, I've
 15 made notes about changes I made to the library in
 16 disassembler/udis86/differences.txt.
 17
 18 * CMakeLists.txt:
 19 * DerivedSources.make:
 20 * GNUmakefile.list.am:
 21 * JavaScriptCore.pri:
 22 * JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCore.vcproj:
 23 * JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCoreCommon.vsprops:
 24 * JavaScriptCore.xcodeproj/project.pbxproj:
 25 * dfg/DFGJITCompiler.cpp:
 26 (JSC::DFG::JITCompiler::compile):
 27 (JSC::DFG::JITCompiler::compileFunction):
 28 * disassembler: Added.
 29 * disassembler/Disassembler.h: Added.
 30 (JSC):
 31 (JSC::tryToDisassemble):
 32 * disassembler/UDis86Disassembler.cpp: Added.
 33 (JSC):
 34 (JSC::tryToDisassemble):
 35 * disassembler/udis86: Added.
 36 * disassembler/udis86/differences.txt: Added.
 37 * disassembler/udis86/itab.py: Added.
 38 (UdItabGenerator):
 39 (UdItabGenerator.__init__):
 40 (UdItabGenerator.toGroupId):
 41 (UdItabGenerator.genLookupTable):
 42 (UdItabGenerator.genLookupTableList):
 43 (UdItabGenerator.genInsnTable):
 44 (genItabH):
 45 (genItabH.UD_ITAB_H):
 46 (genItabC):
 47 (genItab):
 48 (main):
 49 * disassembler/udis86/optable.xml: Added.
 50 * disassembler/udis86/ud_opcode.py: Added.
 51 (UdOpcodeTables):
 52 (UdOpcodeTables.sizeOfTable):
 53 (UdOpcodeTables.nameOfTable):
 54 (UdOpcodeTables.updateTable):
 55 (UdOpcodeTables.Insn):
 56 (UdOpcodeTables.Insn.__init__):
 57 (UdOpcodeTables.Insn.__init__.opcode):
 58 (UdOpcodeTables.parse):
 59 (UdOpcodeTables.addInsnDef):
 60 (UdOpcodeTables.print_table):
 61 (UdOpcodeTables.print_tree):
 62 * disassembler/udis86/ud_optable.py: Added.
 63 (UdOptableXmlParser):
 64 (UdOptableXmlParser.parseDef):
 65 (UdOptableXmlParser.parse):
 66 (printFn):
 67 (parse):
 68 (main):
 69 * disassembler/udis86/udis86.c: Added.
 70 (ud_init):
 71 (ud_disassemble):
 72 (ud_set_mode):
 73 (ud_set_vendor):
 74 (ud_set_pc):
 75 (ud):
 76 (ud_insn_asm):
 77 (ud_insn_off):
 78 (ud_insn_hex):
 79 (ud_insn_ptr):
 80 (ud_insn_len):
 81 * disassembler/udis86/udis86.h: Added.
 82 * disassembler/udis86/udis86_decode.c: Added.
 83 (eff_adr_mode):
 84 (ud_lookup_mnemonic):
 85 (decode_prefixes):
 86 (modrm):
 87 (resolve_operand_size):
 88 (resolve_mnemonic):
 89 (decode_a):
 90 (decode_gpr):
 91 (resolve_gpr64):
 92 (resolve_gpr32):
 93 (resolve_reg):
 94 (decode_imm):
 95 (decode_modrm_reg):
 96 (decode_modrm_rm):
 97 (decode_o):
 98 (decode_operand):
 99 (decode_operands):
 100 (clear_insn):
 101 (resolve_mode):
 102 (gen_hex):
 103 (decode_insn):
 104 (decode_3dnow):
 105 (decode_ssepfx):
 106 (decode_ext):
 107 (decode_opcode):
 108 (ud_decode):
 109 * disassembler/udis86/udis86_decode.h: Added.
 110 (ud_itab_entry_operand):
 111 (ud_itab_entry):
 112 (ud_lookup_table_list_entry):
 113 (sse_pfx_idx):
 114 (mode_idx):
 115 (modrm_mod_idx):
 116 (vendor_idx):
 117 (is_group_ptr):
 118 (group_idx):
 119 * disassembler/udis86/udis86_extern.h: Added.
 120 * disassembler/udis86/udis86_input.c: Added.
 121 (inp_buff_hook):
 122 (inp_file_hook):
 123 (ud):
 124 (ud_set_user_opaque_data):
 125 (ud_get_user_opaque_data):
 126 (ud_set_input_buffer):
 127 (ud_set_input_file):
 128 (ud_input_skip):
 129 (ud_input_end):
 130 (ud_inp_next):
 131 (ud_inp_back):
 132 (ud_inp_peek):
 133 (ud_inp_move):
 134 (ud_inp_uint8):
 135 (ud_inp_uint16):
 136 (ud_inp_uint32):
 137 (ud_inp_uint64):
 138 * disassembler/udis86/udis86_input.h: Added.
 139 * disassembler/udis86/udis86_itab_holder.c: Added.
 140 * disassembler/udis86/udis86_syn-att.c: Added.
 141 (opr_cast):
 142 (gen_operand):
 143 (ud_translate_att):
 144 * disassembler/udis86/udis86_syn-intel.c: Added.
 145 (opr_cast):
 146 (gen_operand):
 147 (ud_translate_intel):
 148 * disassembler/udis86/udis86_syn.c: Added.
 149 * disassembler/udis86/udis86_syn.h: Added.
 150 (mkasm):
 151 * disassembler/udis86/udis86_types.h: Added.
 152 (ud_operand):
 153 (ud):
 154 * jit/JITCode.h:
 155 (JITCode):
 156 (JSC::JITCode::tryToDisassemble):
 157
11582012-06-17 Filip Pizlo <fpizlo@apple.com>
2159
3160 DFG should attempt to use structure watchpoints for all inlined get_by_id's and put_by_id's
120562

Source/JavaScriptCore/CMakeLists.txt

@@SET(JavaScriptCore_INCLUDE_DIRECTORIES
77 "${JAVASCRIPTCORE_DIR}/bytecode"
88 "${JAVASCRIPTCORE_DIR}/bytecompiler"
99 "${JAVASCRIPTCORE_DIR}/dfg"
 10 "${JAVASCRIPTCORE_DIR}/disassembler"
1011 "${JAVASCRIPTCORE_DIR}/heap"
1112 "${JAVASCRIPTCORE_DIR}/debugger"
1213 "${JAVASCRIPTCORE_DIR}/interpreter"
120550

Source/JavaScriptCore/DerivedSources.make

@@all : \
5959 StringConstructor.lut.h \
6060 StringPrototype.lut.h \
6161 docs/bytecode.html \
 62 udis86_itab.h \
6263#
6364
6465# lookup tables for classes

@@RegExpJitTables.h: create_regex_tables
7980KeywordLookup.h: KeywordLookupGenerator.py Keywords.table
8081 python $^ > $@
8182
 83# udis86 instruction tables
 84
 85udis86_itab.h: $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml
 86 (PYTHONPATH=$(JavaScriptCore)/disassembler/udis86 python $(JavaScriptCore)/disassembler/udis86/itab.py $(JavaScriptCore)/disassembler/udis86/optable.xml || exit 1)
 87
8288# header detection
8389
8490ifeq ($(OS),MACOS)
120550

Source/JavaScriptCore/GNUmakefile.list.am

@@javascriptcore_sources += \
221221 Source/JavaScriptCore/dfg/DFGVariableAccessData.h \
222222 Source/JavaScriptCore/dfg/DFGVirtualRegisterAllocationPhase.cpp \
223223 Source/JavaScriptCore/dfg/DFGVirtualRegisterAllocationPhase.h \
 224 Source/JavaScriptCore/disassembler/Disassembler.h \
224225 Source/JavaScriptCore/heap/CopiedAllocator.h \
225226 Source/JavaScriptCore/heap/CopiedBlock.h \
226227 Source/JavaScriptCore/heap/CopiedSpace.cpp \
120550

Source/JavaScriptCore/JavaScriptCore.pri

@@INCLUDEPATH += \
1919 $$SOURCE_DIR/heap \
2020 $$SOURCE_DIR/dfg \
2121 $$SOURCE_DIR/debugger \
 22 $$SOURCE_DIR/disassembler \
2223 $$SOURCE_DIR/interpreter \
2324 $$SOURCE_DIR/jit \
2425 $$SOURCE_DIR/llint \
120550

Source/JavaScriptCore/JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCore.vcproj

19391939 </File>
19401940 </Filter>
19411941 <Filter
 1942 Name="disassembler"
 1943 >
 1944 <File
 1945 RelativePath="..\..\disassembler\Disassembler.h"
 1946 >
 1947 </File>
 1948 </Filter>
 1949 <Filter
19421950 Name="interpreter"
19431951 >
19441952 <File
120550

Source/JavaScriptCore/JavaScriptCore.vcproj/JavaScriptCore/JavaScriptCoreCommon.vsprops

66 >
77 <Tool
88 Name="VCCLCompilerTool"
9  AdditionalIncludeDirectories="&quot;$(ConfigurationBuildDir)\obj\JavaScriptCore\DerivedSources\&quot;;../../;../../API/;../../parser/;../../bytecompiler/;../../dfg/;../../jit/;../../llint/;../../runtime/;../../tools/;../../bytecode/;../../interpreter/;../../wtf/;../../profiler;../../assembler/;../../debugger/;../../heap/;&quot;$(WebKitLibrariesDir)\include&quot;;&quot;$(WebKitLibrariesDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include&quot;;&quot;$(ConfigurationBuildDir)\include\JavaScriptCore&quot;;&quot;$(ConfigurationBuildDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include\private\JavaScriptCore&quot;;&quot;$(WebKitLibrariesDir)\include\pthreads&quot;"
 9 AdditionalIncludeDirectories="&quot;$(ConfigurationBuildDir)\obj\JavaScriptCore\DerivedSources\&quot;;../../;../../API/;../../parser/;../../bytecompiler/;../../dfg/;../../disassembler;../../jit/;../../llint/;../../runtime/;../../tools/;../../bytecode/;../../interpreter/;../../wtf/;../../profiler;../../assembler/;../../debugger/;../../heap/;&quot;$(WebKitLibrariesDir)\include&quot;;&quot;$(WebKitLibrariesDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include&quot;;&quot;$(ConfigurationBuildDir)\include\JavaScriptCore&quot;;&quot;$(ConfigurationBuildDir)\include\private&quot;;&quot;$(ConfigurationBuildDir)\include\private\JavaScriptCore&quot;;&quot;$(WebKitLibrariesDir)\include\pthreads&quot;"
1010 PreprocessorDefinitions="__STD_C"
1111 ForcedIncludeFiles="ICUVersion.h"
1212 />
120550

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29623030 shellPath = /bin/sh;
2963  shellScript = "mkdir -p \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore/docs\"\ncd \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore\"\n\n/bin/ln -sfh \"${SRCROOT}\" JavaScriptCore\nexport JavaScriptCore=\"JavaScriptCore\"\nexport BUILT_PRODUCTS_DIR=\"../..\"\n\nmake --no-builtin-rules -f \"JavaScriptCore/DerivedSources.make\" -j `/usr/sbin/sysctl -n hw.ncpu`\n\n/usr/bin/env ruby JavaScriptCore/offlineasm/asm.rb JavaScriptCore/llint/LowLevelInterpreter.asm ${BUILT_PRODUCTS_DIR}/JSCLLIntOffsetsExtractor LLIntAssembly.h\n";
 3031 shellScript = "mkdir -p \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore/docs\"\ncd \"${BUILT_PRODUCTS_DIR}/DerivedSources/JavaScriptCore\"\n\n/bin/ln -sfh \"${SRCROOT}\" JavaScriptCore\nexport JavaScriptCore=\"JavaScriptCore\"\nexport BUILT_PRODUCTS_DIR=\"../..\"\n\nmake --no-builtin-rules -f \"JavaScriptCore/DerivedSources.make\" -j `/usr/sbin/sysctl -n hw.ncpu` || exit 1\n\n/usr/bin/env ruby JavaScriptCore/offlineasm/asm.rb JavaScriptCore/llint/LowLevelInterpreter.asm ${BUILT_PRODUCTS_DIR}/JSCLLIntOffsetsExtractor LLIntAssembly.h || exit 1\n";
29643032 };
29653033 9319586B09D9F91A00A56FD4 /* Check For Global Initializers */ = {
29663034 isa = PBXShellScriptBuildPhase;

32573325 0F919D10157F3329004A4E7D /* JSSegmentedVariableObject.cpp in Sources */,
32583326 0F919D2515853CE0004A4E7D /* Watchpoint.cpp in Sources */,
32593327 0F919D2815856773004A4E7D /* SymbolTable.cpp in Sources */,
 3328 0FF42732158EBD58004CB9FF /* UDis86Disassembler.cpp in Sources */,
 3329 0FF42740158EBE8B004CB9FF /* udis86_decode.c in Sources */,
 3330 0FF42743158EBE91004CB9FF /* udis86_input.c in Sources */,
 3331 0FF42745158EBE91004CB9FF /* udis86_syn-att.c in Sources */,
 3332 0FF42746158EBE91004CB9FF /* udis86_syn-intel.c in Sources */,
 3333 0FF42747158EBE91004CB9FF /* udis86_syn.c in Sources */,
 3334 0FF4274A158EBE91004CB9FF /* udis86.c in Sources */,
 3335 0FF4274D158EBFE6004CB9FF /* udis86_itab_holder.c in Sources */,
32603336 );
32613337 runOnlyForDeploymentPostprocessing = 0;
32623338 };
120550

Source/JavaScriptCore/dfg/DFGJITCompiler.cpp

@@bool JITCompiler::compile(JITCode& entry
223223 speculative.linkOSREntries(linkBuffer);
224224
225225 entry = JITCode(linkBuffer.finalizeCode(), JITCode::DFGJIT);
 226#if DFG_ENABLE(DEBUG_VERBOSE)
 227 entry.tryToDisassemble();
 228#endif
226229 return true;
227230}
228231

@@bool JITCompiler::compileFunction(JITCod
305308
306309 entryWithArityCheck = linkBuffer.locationOf(arityCheck);
307310 entry = JITCode(linkBuffer.finalizeCode(), JITCode::DFGJIT);
 311#if DFG_ENABLE(DEBUG_VERBOSE)
 312 entry.tryToDisassemble();
 313#endif
308314 return true;
309315}
310316
120550

Source/JavaScriptCore/disassembler/Disassembler.h

 1/*
 2 * Copyright (C) 2012 Apple Inc. All rights reserved.
 3 *
 4 * Redistribution and use in source and binary forms, with or without
 5 * modification, are permitted provided that the following conditions
 6 * are met:
 7 * 1. Redistributions of source code must retain the above copyright
 8 * notice, this list of conditions and the following disclaimer.
 9 * 2. Redistributions in binary form must reproduce the above copyright
 10 * notice, this list of conditions and the following disclaimer in the
 11 * documentation and/or other materials provided with the distribution.
 12 *
 13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
 14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
 17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 24 */
 25
 26#ifndef Disassembler_h
 27#define Disassembler_h
 28
 29#include <wtf/Platform.h>
 30#include <wtf/StdLibExtras.h>
 31
 32namespace JSC {
 33
 34#if ENABLE(DISASSEMBLER)
 35bool tryToDisassemble(void* instructionStart, size_t size, FILE* out);
 36#else
 37inline bool tryToDisassemble(void*, size_t, FILE*)
 38{
 39 return false;
 40}
 41#endif
 42
 43} // namespace JSC
 44
 45#endif // Disassembler_h
 46
0

Source/JavaScriptCore/disassembler/UDis86Disassembler.cpp

 1/*
 2 * Copyright (C) 2012 Apple Inc. All rights reserved.
 3 *
 4 * Redistribution and use in source and binary forms, with or without
 5 * modification, are permitted provided that the following conditions
 6 * are met:
 7 * 1. Redistributions of source code must retain the above copyright
 8 * notice, this list of conditions and the following disclaimer.
 9 * 2. Redistributions in binary form must reproduce the above copyright
 10 * notice, this list of conditions and the following disclaimer in the
 11 * documentation and/or other materials provided with the distribution.
 12 *
 13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
 14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
 17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 24 */
 25
 26#include "config.h"
 27#include "Disassembler.h"
 28
 29#if USE(UDIS86)
 30
 31#include "udis86.h"
 32
 33namespace JSC {
 34
 35bool tryToDisassemble(void* instructionStart, size_t size, FILE* out)
 36{
 37 ud_t disassembler;
 38 ud_init(&disassembler);
 39 ud_set_input_buffer(&disassembler, static_cast<unsigned char*>(instructionStart), size);
 40#if CPU(X86_64)
 41 ud_set_mode(&disassembler, 64);
 42#else
 43 ud_set_mode(&disassembler, 32);
 44#endif
 45 ud_set_syntax(&disassembler, UD_SYN_ATT);
 46
 47 while (ud_disassemble(&disassembler))
 48 fprintf(out, "\t%s\n", ud_insn_asm(&disassembler));
 49
 50 return true;
 51}
 52
 53} // namespace JSC
 54
 55#endif // USE(UDIS86)
 56
0

Source/JavaScriptCore/disassembler/udis86/differences.txt

 1This documents the differences between the stock version of udis86 and the one found
 2here:
 3
 4- All files not named "udis86" were prefixed with "udis86".
 5
 6- assert() has been changed to ASSERT()
 7
 8- Mass rename of udis86_input.h inp_ prefixed functions and macros to ud_inp_ to
 9 avoid namespace pollution.
 10
 11- Removal of KERNEL checks.
 12
 13- Added #include of udis86_extern.h in udis86_decode.c.
 14
 15- Removed s_ie__pause and s_ie__nop from udis86_decode.c, since they weren't used.
 16
0

Source/JavaScriptCore/disassembler/udis86/itab.py

 1# udis86 - scripts/itab.py
 2#
 3# Copyright (c) 2009 Vivek Thampi
 4# All rights reserved.
 5#
 6# Redistribution and use in source and binary forms, with or without modification,
 7# are permitted provided that the following conditions are met:
 8#
 9# * Redistributions of source code must retain the above copyright notice,
 10# this list of conditions and the following disclaimer.
 11# * Redistributions in binary form must reproduce the above copyright notice,
 12# this list of conditions and the following disclaimer in the documentation
 13# and/or other materials provided with the distribution.
 14#
 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25
 26import sys
 27
 28sys.path.append( '../scripts' );
 29
 30import ud_optable
 31import ud_opcode
 32
 33class UdItabGenerator( ud_opcode.UdOpcodeTables ):
 34
 35 OperandDict = {
 36 "Ap" : [ "OP_A" , "SZ_P" ],
 37 "E" : [ "OP_E" , "SZ_NA" ],
 38 "Eb" : [ "OP_E" , "SZ_B" ],
 39 "Ew" : [ "OP_E" , "SZ_W" ],
 40 "Ev" : [ "OP_E" , "SZ_V" ],
 41 "Ed" : [ "OP_E" , "SZ_D" ],
 42 "Eq" : [ "OP_E" , "SZ_Q" ],
 43 "Ez" : [ "OP_E" , "SZ_Z" ],
 44 "Ex" : [ "OP_E" , "SZ_MDQ" ],
 45 "Ep" : [ "OP_E" , "SZ_P" ],
 46 "G" : [ "OP_G" , "SZ_NA" ],
 47 "Gb" : [ "OP_G" , "SZ_B" ],
 48 "Gw" : [ "OP_G" , "SZ_W" ],
 49 "Gv" : [ "OP_G" , "SZ_V" ],
 50 "Gy" : [ "OP_G" , "SZ_MDQ" ],
 51 "Gy" : [ "OP_G" , "SZ_MDQ" ],
 52 "Gd" : [ "OP_G" , "SZ_D" ],
 53 "Gq" : [ "OP_G" , "SZ_Q" ],
 54 "Gx" : [ "OP_G" , "SZ_MDQ" ],
 55 "Gz" : [ "OP_G" , "SZ_Z" ],
 56 "M" : [ "OP_M" , "SZ_NA" ],
 57 "Mb" : [ "OP_M" , "SZ_B" ],
 58 "Mw" : [ "OP_M" , "SZ_W" ],
 59 "Ms" : [ "OP_M" , "SZ_W" ],
 60 "Md" : [ "OP_M" , "SZ_D" ],
 61 "Mq" : [ "OP_M" , "SZ_Q" ],
 62 "Mt" : [ "OP_M" , "SZ_T" ],
 63 "Mo" : [ "OP_M" , "SZ_O" ],
 64 "MwRv" : [ "OP_MR" , "SZ_WV" ],
 65 "MdRy" : [ "OP_MR" , "SZ_DY" ],
 66 "MbRv" : [ "OP_MR" , "SZ_BV" ],
 67 "I1" : [ "OP_I1" , "SZ_NA" ],
 68 "I3" : [ "OP_I3" , "SZ_NA" ],
 69 "Ib" : [ "OP_I" , "SZ_B" ],
 70 "Isb" : [ "OP_I" , "SZ_SB" ],
 71 "Iw" : [ "OP_I" , "SZ_W" ],
 72 "Iv" : [ "OP_I" , "SZ_V" ],
 73 "Iz" : [ "OP_I" , "SZ_Z" ],
 74 "Jv" : [ "OP_J" , "SZ_V" ],
 75 "Jz" : [ "OP_J" , "SZ_Z" ],
 76 "Jb" : [ "OP_J" , "SZ_B" ],
 77 "R" : [ "OP_R" , "SZ_RDQ" ],
 78 "C" : [ "OP_C" , "SZ_NA" ],
 79 "D" : [ "OP_D" , "SZ_NA" ],
 80 "S" : [ "OP_S" , "SZ_NA" ],
 81 "Ob" : [ "OP_O" , "SZ_B" ],
 82 "Ow" : [ "OP_O" , "SZ_W" ],
 83 "Ov" : [ "OP_O" , "SZ_V" ],
 84 "V" : [ "OP_V" , "SZ_O" ],
 85 "W" : [ "OP_W" , "SZ_O" ],
 86 "Wsd" : [ "OP_W" , "SZ_O" ],
 87 "Wss" : [ "OP_W" , "SZ_O" ],
 88 "P" : [ "OP_P" , "SZ_Q" ],
 89 "Q" : [ "OP_Q" , "SZ_Q" ],
 90 "VR" : [ "OP_VR" , "SZ_O" ],
 91 "PR" : [ "OP_PR" , "SZ_Q" ],
 92 "AL" : [ "OP_AL" , "SZ_NA" ],
 93 "CL" : [ "OP_CL" , "SZ_NA" ],
 94 "DL" : [ "OP_DL" , "SZ_NA" ],
 95 "BL" : [ "OP_BL" , "SZ_NA" ],
 96 "AH" : [ "OP_AH" , "SZ_NA" ],
 97 "CH" : [ "OP_CH" , "SZ_NA" ],
 98 "DH" : [ "OP_DH" , "SZ_NA" ],
 99 "BH" : [ "OP_BH" , "SZ_NA" ],
 100 "AX" : [ "OP_AX" , "SZ_NA" ],
 101 "CX" : [ "OP_CX" , "SZ_NA" ],
 102 "DX" : [ "OP_DX" , "SZ_NA" ],
 103 "BX" : [ "OP_BX" , "SZ_NA" ],
 104 "SI" : [ "OP_SI" , "SZ_NA" ],
 105 "DI" : [ "OP_DI" , "SZ_NA" ],
 106 "SP" : [ "OP_SP" , "SZ_NA" ],
 107 "BP" : [ "OP_BP" , "SZ_NA" ],
 108 "eAX" : [ "OP_eAX" , "SZ_NA" ],
 109 "eCX" : [ "OP_eCX" , "SZ_NA" ],
 110 "eDX" : [ "OP_eDX" , "SZ_NA" ],
 111 "eBX" : [ "OP_eBX" , "SZ_NA" ],
 112 "eSI" : [ "OP_eSI" , "SZ_NA" ],
 113 "eDI" : [ "OP_eDI" , "SZ_NA" ],
 114 "eSP" : [ "OP_eSP" , "SZ_NA" ],
 115 "eBP" : [ "OP_eBP" , "SZ_NA" ],
 116 "rAX" : [ "OP_rAX" , "SZ_NA" ],
 117 "rCX" : [ "OP_rCX" , "SZ_NA" ],
 118 "rBX" : [ "OP_rBX" , "SZ_NA" ],
 119 "rDX" : [ "OP_rDX" , "SZ_NA" ],
 120 "rSI" : [ "OP_rSI" , "SZ_NA" ],
 121 "rDI" : [ "OP_rDI" , "SZ_NA" ],
 122 "rSP" : [ "OP_rSP" , "SZ_NA" ],
 123 "rBP" : [ "OP_rBP" , "SZ_NA" ],
 124 "ES" : [ "OP_ES" , "SZ_NA" ],
 125 "CS" : [ "OP_CS" , "SZ_NA" ],
 126 "DS" : [ "OP_DS" , "SZ_NA" ],
 127 "SS" : [ "OP_SS" , "SZ_NA" ],
 128 "GS" : [ "OP_GS" , "SZ_NA" ],
 129 "FS" : [ "OP_FS" , "SZ_NA" ],
 130 "ST0" : [ "OP_ST0" , "SZ_NA" ],
 131 "ST1" : [ "OP_ST1" , "SZ_NA" ],
 132 "ST2" : [ "OP_ST2" , "SZ_NA" ],
 133 "ST3" : [ "OP_ST3" , "SZ_NA" ],
 134 "ST4" : [ "OP_ST4" , "SZ_NA" ],
 135 "ST5" : [ "OP_ST5" , "SZ_NA" ],
 136 "ST6" : [ "OP_ST6" , "SZ_NA" ],
 137 "ST7" : [ "OP_ST7" , "SZ_NA" ],
 138 "NONE" : [ "OP_NONE" , "SZ_NA" ],
 139 "ALr8b" : [ "OP_ALr8b" , "SZ_NA" ],
 140 "CLr9b" : [ "OP_CLr9b" , "SZ_NA" ],
 141 "DLr10b" : [ "OP_DLr10b" , "SZ_NA" ],
 142 "BLr11b" : [ "OP_BLr11b" , "SZ_NA" ],
 143 "AHr12b" : [ "OP_AHr12b" , "SZ_NA" ],
 144 "CHr13b" : [ "OP_CHr13b" , "SZ_NA" ],
 145 "DHr14b" : [ "OP_DHr14b" , "SZ_NA" ],
 146 "BHr15b" : [ "OP_BHr15b" , "SZ_NA" ],
 147 "rAXr8" : [ "OP_rAXr8" , "SZ_NA" ],
 148 "rCXr9" : [ "OP_rCXr9" , "SZ_NA" ],
 149 "rDXr10" : [ "OP_rDXr10" , "SZ_NA" ],
 150 "rBXr11" : [ "OP_rBXr11" , "SZ_NA" ],
 151 "rSPr12" : [ "OP_rSPr12" , "SZ_NA" ],
 152 "rBPr13" : [ "OP_rBPr13" , "SZ_NA" ],
 153 "rSIr14" : [ "OP_rSIr14" , "SZ_NA" ],
 154 "rDIr15" : [ "OP_rDIr15" , "SZ_NA" ],
 155 "jWP" : [ "OP_J" , "SZ_WP" ],
 156 "jDP" : [ "OP_J" , "SZ_DP" ],
 157
 158 }
 159
 160 #
 161 # opcode prefix dictionary
 162 #
 163 PrefixDict = {
 164 "aso" : "P_aso",
 165 "oso" : "P_oso",
 166 "rexw" : "P_rexw",
 167 "rexb" : "P_rexb",
 168 "rexx" : "P_rexx",
 169 "rexr" : "P_rexr",
 170 "seg" : "P_seg",
 171 "inv64" : "P_inv64",
 172 "def64" : "P_def64",
 173 "depM" : "P_depM",
 174 "cast1" : "P_c1",
 175 "cast2" : "P_c2",
 176 "cast3" : "P_c3",
 177 "cast" : "P_cast",
 178 "sext" : "P_sext"
 179 }
 180
 181 InvalidEntryIdx = 0
 182 InvalidEntry = { 'type' : 'invalid',
 183 'mnemonic' : 'invalid',
 184 'operands' : '',
 185 'prefixes' : '',
 186 'meta' : '' }
 187
 188 Itab = [] # instruction table
 189 ItabIdx = 1 # instruction table index
 190 GtabIdx = 0 # group table index
 191 GtabMeta = []
 192
 193 ItabLookup = {}
 194
 195 MnemonicAliases = ( "invalid", "3dnow", "none", "db", "pause" )
 196
 197 def __init__( self ):
 198 # first itab entry (0) is Invalid
 199 self.Itab.append( self.InvalidEntry )
 200 self.MnemonicsTable.extend( self.MnemonicAliases )
 201
 202 def toGroupId( self, id ):
 203 return 0x8000 | id
 204
 205 def genLookupTable( self, table, scope = '' ):
 206 idxArray = [ ]
 207 ( tabIdx, self.GtabIdx ) = ( self.GtabIdx, self.GtabIdx + 1 )
 208 self.GtabMeta.append( { 'type' : table[ 'type' ], 'meta' : table[ 'meta' ] } )
 209
 210 for _idx in range( self.sizeOfTable( table[ 'type' ] ) ):
 211 idx = "%02x" % _idx
 212
 213 e = self.InvalidEntry
 214 i = self.InvalidEntryIdx
 215
 216 if idx in table[ 'entries' ].keys():
 217 e = table[ 'entries' ][ idx ]
 218
 219 # leaf node (insn)
 220 if e[ 'type' ] == 'insn':
 221 ( i, self.ItabIdx ) = ( self.ItabIdx, self.ItabIdx + 1 )
 222 self.Itab.append( e )
 223 elif e[ 'type' ] != 'invalid':
 224 i = self.genLookupTable( e, 'static' )
 225
 226 idxArray.append( i )
 227
 228 name = "ud_itab__%s" % tabIdx
 229 self.ItabLookup[ tabIdx ] = name
 230
 231 self.ItabC.write( "\n" );
 232 if len( scope ):
 233 self.ItabC.write( scope + ' ' )
 234 self.ItabC.write( "const uint16_t %s[] = {\n" % name )
 235 for i in range( len( idxArray ) ):
 236 if i > 0 and i % 4 == 0:
 237 self.ItabC.write( "\n" )
 238 if ( i%4 == 0 ):
 239 self.ItabC.write( " /* %2x */" % i)
 240 if idxArray[ i ] >= 0x8000:
 241 self.ItabC.write( "%12s," % ("GROUP(%d)" % ( ~0x8000 & idxArray[ i ] )))
 242 else:
 243 self.ItabC.write( "%12d," % ( idxArray[ i ] ))
 244 self.ItabC.write( "\n" )
 245 self.ItabC.write( "};\n" )
 246
 247 return self.toGroupId( tabIdx )
 248
 249 def genLookupTableList( self ):
 250 self.ItabC.write( "\n\n" );
 251 self.ItabC.write( "struct ud_lookup_table_list_entry ud_lookup_table_list[] = {\n" )
 252 for i in range( len( self.GtabMeta ) ):
 253 f0 = self.ItabLookup[ i ] + ","
 254 f1 = ( self.nameOfTable( self.GtabMeta[ i ][ 'type' ] ) ) + ","
 255 f2 = "\"%s\"" % self.GtabMeta[ i ][ 'meta' ]
 256 self.ItabC.write( " /* %03d */ { %s %s %s },\n" % ( i, f0, f1, f2 ) )
 257 self.ItabC.write( "};" )
 258
 259 def genInsnTable( self ):
 260 self.ItabC.write( "struct ud_itab_entry ud_itab[] = {\n" );
 261 idx = 0
 262 for e in self.Itab:
 263 opr_c = [ "O_NONE", "O_NONE", "O_NONE" ]
 264 pfx_c = []
 265 opr = e[ 'operands' ]
 266 for i in range(len(opr)):
 267 if not (opr[i] in self.OperandDict.keys()):
 268 print "error: invalid operand declaration: %s\n" % opr[i]
 269 opr_c[i] = "O_" + opr[i]
 270 opr = "%s %s %s" % (opr_c[0] + ",", opr_c[1] + ",", opr_c[2])
 271
 272 for p in e['prefixes']:
 273 if not ( p in self.PrefixDict.keys() ):
 274 print "error: invalid prefix specification: %s \n" % pfx
 275 pfx_c.append( self.PrefixDict[p] )
 276 if len(e['prefixes']) == 0:
 277 pfx_c.append( "P_none" )
 278 pfx = "|".join( pfx_c )
 279
 280 self.ItabC.write( " /* %04d */ { UD_I%s %s, %s },\n" \
 281 % ( idx, e[ 'mnemonic' ] + ',', opr, pfx ) )
 282 idx += 1
 283 self.ItabC.write( "};\n" )
 284
 285 self.ItabC.write( "\n\n" );
 286 self.ItabC.write( "const char * ud_mnemonics_str[] = {\n" )
 287 self.ItabC.write( ",\n ".join( [ "\"%s\"" % m for m in self.MnemonicsTable ] ) )
 288 self.ItabC.write( "\n};\n" )
 289
 290
 291 def genItabH( self ):
 292 self.ItabH = open( "udis86_itab.h", "w" )
 293
 294 # Generate Table Type Enumeration
 295 self.ItabH.write( "#ifndef UD_ITAB_H\n" )
 296 self.ItabH.write( "#define UD_ITAB_H\n\n" )
 297
 298 # table type enumeration
 299 self.ItabH.write( "/* ud_table_type -- lookup table types (see lookup.c) */\n" )
 300 self.ItabH.write( "enum ud_table_type {\n " )
 301 enum = [ self.TableInfo[ k ][ 'name' ] for k in self.TableInfo.keys() ]
 302 self.ItabH.write( ",\n ".join( enum ) )
 303 self.ItabH.write( "\n};\n\n" );
 304
 305 # mnemonic enumeration
 306 self.ItabH.write( "/* ud_mnemonic -- mnemonic constants */\n" )
 307 enum = "enum ud_mnemonic_code {\n "
 308 enum += ",\n ".join( [ "UD_I%s" % m for m in self.MnemonicsTable ] )
 309 enum += "\n} UD_ATTR_PACKED;\n"
 310 self.ItabH.write( enum )
 311 self.ItabH.write( "\n" )
 312
 313 self.ItabH.write("\n/* itab entry operand definitions */\n");
 314 operands = self.OperandDict.keys()
 315 operands.sort()
 316 for o in operands:
 317 self.ItabH.write("#define O_%-7s { %-12s %-8s }\n" %
 318 (o, self.OperandDict[o][0] + ",", self.OperandDict[o][1]));
 319 self.ItabH.write("\n\n");
 320
 321 self.ItabH.write( "extern const char * ud_mnemonics_str[];\n" )
 322
 323 self.ItabH.write( "#define GROUP(n) (0x8000 | (n))" )
 324
 325 self.ItabH.write( "\n#endif /* UD_ITAB_H */\n" )
 326
 327 self.ItabH.close()
 328
 329
 330 def genItabC( self ):
 331 self.ItabC = open( "udis86_itab.c", "w" )
 332 self.ItabC.write( "/* itab.c -- generated by itab.py, do no edit" )
 333 self.ItabC.write( " */\n" );
 334 self.ItabC.write( "#include \"udis86_decode.h\"\n\n" );
 335
 336 self.genLookupTable( self.OpcodeTable0 )
 337 self.genLookupTableList()
 338 self.genInsnTable()
 339
 340 self.ItabC.close()
 341
 342 def genItab( self ):
 343 self.genItabC()
 344 self.genItabH()
 345
 346def main():
 347 generator = UdItabGenerator()
 348 optableXmlParser = ud_optable.UdOptableXmlParser()
 349 optableXmlParser.parse( sys.argv[ 1 ], generator.addInsnDef )
 350
 351 generator.genItab()
 352
 353if __name__ == '__main__':
 354 main()
0

Source/JavaScriptCore/disassembler/udis86/optable.xml

 1<?xml version="1.0"?>
 2<?xml-stylesheet href="optable.xsl" type="text/xsl"?>
 3<x86optable>
 4
 5 <instruction>
 6 <mnemonic>aaa</mnemonic>
 7 <def>
 8 <opc>37</opc>
 9 <mode>inv64</mode>
 10 </def>
 11 </instruction>
 12
 13 <instruction>
 14 <mnemonic>aad</mnemonic>
 15 <def>
 16 <opc>d5</opc>
 17 <opr>Ib</opr>
 18 <mode>inv64</mode>
 19 </def>
 20 </instruction>
 21
 22 <instruction>
 23 <mnemonic>aam</mnemonic>
 24 <def>
 25 <opc>d4</opc>
 26 <opr>Ib</opr>
 27 <mode>inv64</mode>
 28 </def>
 29 </instruction>
 30
 31 <instruction>
 32 <mnemonic>aas</mnemonic>
 33 <def>
 34 <opc>3f</opc>
 35 <mode>inv64</mode>
 36 </def>
 37 </instruction>
 38
 39 <instruction>
 40 <mnemonic>adc</mnemonic>
 41 <def>
 42 <pfx>aso rexr rexx rexb</pfx>
 43 <opc>10</opc>
 44 <opr>Eb Gb</opr>
 45 </def>
 46 <def>
 47 <pfx>aso oso rexw rexr rexx rexb</pfx>
 48 <opc>11</opc>
 49 <opr>Ev Gv</opr>
 50 </def>
 51 <def>
 52 <pfx>aso rexr rexx rexb</pfx>
 53 <opc>12</opc>
 54 <opr>Gb Eb</opr>
 55 </def>
 56 <def>
 57 <pfx>aso oso rexw rexr rexx rexb</pfx>
 58 <opc>13</opc>
 59 <opr>Gv Ev</opr>
 60 </def>
 61 <def>
 62 <opc>14</opc>
 63 <opr>AL Ib</opr>
 64 </def>
 65 <def>
 66 <pfx>oso rexw</pfx>
 67 <opc>15</opc>
 68 <opr>rAX Iz</opr>
 69 <syn>sext</syn>
 70 </def>
 71 <def>
 72 <pfx>aso rexr rexx rexb</pfx>
 73 <opc>80 /reg=2</opc>
 74 <opr>Eb Ib</opr>
 75 </def>
 76 <def>
 77 <pfx>aso rexr rexx rexb</pfx>
 78 <opc>82 /reg=2</opc>
 79 <opr>Eb Ib</opr>
 80 <mode>inv64</mode>
 81 </def>
 82 <def>
 83 <pfx>aso oso rexw rexr rexx rexb</pfx>
 84 <opc>81 /reg=2</opc>
 85 <opr>Ev Iz</opr>
 86 <syn>sext</syn>
 87 </def>
 88 <def>
 89 <pfx>aso oso rexw rexr rexx rexb</pfx>
 90 <opc>83 /reg=2</opc>
 91 <opr>Ev Ib</opr>
 92 <syn>sext</syn>
 93 </def>
 94 </instruction>
 95
 96 <instruction>
 97 <mnemonic>add</mnemonic>
 98 <def>
 99 <pfx>aso rexr rexx rexb</pfx>
 100 <opc>00</opc>
 101 <opr>Eb Gb</opr>
 102 </def>
 103 <def>
 104 <pfx>aso oso rexw rexr rexx rexb</pfx>
 105 <opc>01</opc>
 106 <opr>Ev Gv</opr>
 107 </def>
 108 <def>
 109 <pfx>aso rexr rexx rexb</pfx>
 110 <opc>02</opc>
 111 <opr>Gb Eb</opr>
 112 </def>
 113 <def>
 114 <pfx>aso oso rexw rexr rexx rexb</pfx>
 115 <opc>03</opc>
 116 <opr>Gv Ev</opr>
 117 </def>
 118 <def>
 119 <opc>04</opc>
 120 <opr>AL Ib</opr>
 121 </def>
 122 <def>
 123 <pfx>oso rexw</pfx>
 124 <opc>05</opc>
 125 <opr>rAX Iz</opr>
 126 <syn>sext</syn>
 127 </def>
 128 <def>
 129 <pfx>aso rexr rexx rexb</pfx>
 130 <opc>80 /reg=0</opc>
 131 <opr>Eb Ib</opr>
 132 </def>
 133 <def>
 134 <pfx>aso rexr rexx rexb</pfx>
 135 <opc>82 /reg=0</opc>
 136 <opr>Eb Ib</opr>
 137 <mode>inv64</mode>
 138 </def>
 139 <def>
 140 <pfx>aso oso rexw rexr rexx rexb</pfx>
 141 <opc>81 /reg=0</opc>
 142 <opr>Ev Iz</opr>
 143 <syn>sext</syn>
 144 </def>
 145 <def>
 146 <pfx>aso oso rexw rexr rexx rexb</pfx>
 147 <opc>83 /reg=0</opc>
 148 <opr>Ev Ib</opr>
 149 <syn>sext</syn>
 150 </def>
 151 </instruction>
 152
 153 <!--
 154 SSE2
 155 -->
 156
 157 <instruction>
 158 <mnemonic>addpd</mnemonic>
 159 <def>
 160 <pfx>aso rexr rexx rexb</pfx>
 161 <opc>sse66 0f 58</opc>
 162 <opr>V W</opr>
 163 </def>
 164 </instruction>
 165
 166 <instruction>
 167 <mnemonic>addps</mnemonic>
 168 <def>
 169 <pfx>aso rexr rexx rexb</pfx>
 170 <opc>0f 58</opc>
 171 <opr>V W</opr>
 172 </def>
 173 </instruction>
 174
 175 <instruction>
 176 <mnemonic>addsd</mnemonic>
 177 <def>
 178 <pfx>aso rexr rexx rexb</pfx>
 179 <opc>ssef2 0f 58</opc>
 180 <opr>V W</opr>
 181 </def>
 182 </instruction>
 183
 184 <instruction>
 185 <mnemonic>addss</mnemonic>
 186 <def>
 187 <pfx>aso rexr rexx rexb</pfx>
 188 <opc>ssef3 0f 58</opc>
 189 <opr>V W</opr>
 190 </def>
 191 </instruction>
 192
 193 <instruction>
 194 <mnemonic>and</mnemonic>
 195 <def>
 196 <pfx>aso rexr rexx rexb</pfx>
 197 <opc>20</opc>
 198 <opr>Eb Gb</opr>
 199 </def>
 200 <def>
 201 <pfx>aso oso rexw rexr rexx rexb</pfx>
 202 <opc>21</opc>
 203 <opr>Ev Gv</opr>
 204 </def>
 205 <def>
 206 <pfx>aso rexr rexx rexb</pfx>
 207 <opc>22</opc>
 208 <opr>Gb Eb</opr>
 209 </def>
 210 <def>
 211 <pfx>aso oso rexw rexr rexx rexb</pfx>
 212 <opc>23</opc>
 213 <opr>Gv Ev</opr>
 214 </def>
 215 <def>
 216 <opc>24</opc>
 217 <opr>AL Ib</opr>
 218 </def>
 219 <def>
 220 <pfx>oso rexw</pfx>
 221 <opc>25</opc>
 222 <opr>rAX Iz</opr>
 223 <syn>sext</syn>
 224 </def>
 225 <def>
 226 <pfx>aso rexw rexr rexx rexb</pfx>
 227 <opc>80 /reg=4</opc>
 228 <opr>Eb Ib</opr>
 229 </def>
 230 <def>
 231 <pfx>aso rexr rexx rexb</pfx>
 232 <opc>82 /reg=4</opc>
 233 <opr>Eb Ib</opr>
 234 <mode>inv64</mode>
 235 </def>
 236 <def>
 237 <pfx>aso oso rexw rexr rexx rexb</pfx>
 238 <opc>81 /reg=4</opc>
 239 <opr>Ev Iz</opr>
 240 <syn>sext</syn>
 241 </def>
 242 <def>
 243 <pfx>aso oso rexw rexr rexx rexb</pfx>
 244 <opc>83 /reg=4</opc>
 245 <opr>Ev Ib</opr>
 246 <syn>sext</syn>
 247 </def>
 248 </instruction>
 249
 250 <instruction>
 251 <mnemonic>andpd</mnemonic>
 252 <def>
 253 <pfx>aso rexr rexx rexb</pfx>
 254 <opc>sse66 0f 54</opc>
 255 <opr>V W</opr>
 256 </def>
 257 </instruction>
 258
 259 <instruction>
 260 <mnemonic>andps</mnemonic>
 261 <def>
 262 <pfx>aso rexr rexx rexb</pfx>
 263 <opc>0f 54</opc>
 264 <opr>V W</opr>
 265 </def>
 266 </instruction>
 267
 268 <instruction>
 269 <mnemonic>andnpd</mnemonic>
 270 <def>
 271 <pfx>aso rexr rexx rexb</pfx>
 272 <opc>sse66 0f 55</opc>
 273 <opr>V W</opr>
 274 </def>
 275 </instruction>
 276
 277 <instruction>
 278 <mnemonic>andnps</mnemonic>
 279 <def>
 280 <pfx>aso rexr rexx rexb</pfx>
 281 <opc>0f 55</opc>
 282 <opr>V W</opr>
 283 </def>
 284 </instruction>
 285
 286 <instruction>
 287 <mnemonic>arpl</mnemonic>
 288 <def>
 289 <pfx>aso</pfx>
 290 <opc>63 /m=16</opc>
 291 <opr>Ew Gw</opr>
 292 <mode>inv64</mode>
 293 </def>
 294 <def>
 295 <pfx>aso</pfx>
 296 <opc>63 /m=32</opc>
 297 <opr>Ew Gw</opr>
 298 <mode>inv64</mode>
 299 </def>
 300 </instruction>
 301
 302 <instruction>
 303 <mnemonic>movsxd</mnemonic>
 304 <def>
 305 <pfx>aso oso rexw rexx rexr rexb</pfx>
 306 <opc>63 /m=64</opc>
 307 <opr>Gv Ed</opr>
 308 </def>
 309 </instruction>
 310
 311 <instruction>
 312 <mnemonic>bound</mnemonic>
 313 <def>
 314 <pfx>aso oso</pfx>
 315 <opc>62</opc>
 316 <opr>Gv M</opr>
 317 <mode>inv64</mode>
 318 </def>
 319 </instruction>
 320
 321 <instruction>
 322 <mnemonic>bsf</mnemonic>
 323 <def>
 324 <pfx>aso oso rexw rexr rexx rexb</pfx>
 325 <opc>0f bc</opc>
 326 <opr>Gv Ev</opr>
 327 </def>
 328 </instruction>
 329
 330 <instruction>
 331 <mnemonic>bsr</mnemonic>
 332 <def>
 333 <pfx>aso oso rexw rexr rexx rexb</pfx>
 334 <opc>0f bd</opc>
 335 <opr>Gv Ev</opr>
 336 </def>
 337 </instruction>
 338
 339 <instruction>
 340 <mnemonic>bswap</mnemonic>
 341 <def>
 342 <pfx>oso rexw rexb</pfx>
 343 <opc>0f c8</opc>
 344 <opr>rAXr8</opr>
 345 </def>
 346 <def>
 347 <pfx>oso rexw rexb</pfx>
 348 <opc>0f c9</opc>
 349 <opr>rCXr9</opr>
 350 </def>
 351 <def>
 352 <pfx>oso rexw rexb</pfx>
 353 <opc>0f ca</opc>
 354 <opr>rDXr10</opr>
 355 </def>
 356 <def>
 357 <pfx>oso rexw rexb</pfx>
 358 <opc>0f cb</opc>
 359 <opr>rBXr11</opr>
 360 </def>
 361 <def>
 362 <pfx>oso rexw rexb</pfx>
 363 <opc>0f cc</opc>
 364 <opr>rSPr12</opr>
 365 </def>
 366 <def>
 367 <pfx>oso rexw rexb</pfx>
 368 <opc>0f cd</opc>
 369 <opr>rBPr13</opr>
 370 </def>
 371 <def>
 372 <pfx>oso rexw rexb</pfx>
 373 <opc>0f ce</opc>
 374 <opr>rSIr14</opr>
 375 </def>
 376 <def>
 377 <pfx>oso rexw rexb</pfx>
 378 <opc>0f cf</opc>
 379 <opr>rDIr15</opr>
 380 </def>
 381 </instruction>
 382
 383 <instruction>
 384 <mnemonic>bt</mnemonic>
 385 <def>
 386 <pfx>aso oso rexw rexr rexx rexb</pfx>
 387 <opc>0f ba /reg=4</opc>
 388 <opr>Ev Ib</opr>
 389 </def>
 390 <def>
 391 <pfx>aso oso rexw rexr rexx rexb</pfx>
 392 <opc>0f a3</opc>
 393 <opr>Ev Gv</opr>
 394 </def>
 395 </instruction>
 396
 397 <instruction>
 398 <mnemonic>btc</mnemonic>
 399 <def>
 400 <pfx>aso oso rexw rexr rexx rexb</pfx>
 401 <opc>0f bb</opc>
 402 <opr>Ev Gv</opr>
 403 </def>
 404 <def>
 405 <pfx>aso oso rexw rexr rexx rexb</pfx>
 406 <opc>0f ba /reg=7</opc>
 407 <opr>Ev Ib</opr>
 408 </def>
 409 </instruction>
 410
 411 <instruction>
 412 <mnemonic>btr</mnemonic>
 413 <def>
 414 <pfx>aso oso rexw rexr rexx rexb</pfx>
 415 <opc>0f b3</opc>
 416 <opr>Ev Gv</opr>
 417 </def>
 418 <def>
 419 <pfx>aso oso rexw rexr rexx rexb</pfx>
 420 <opc>0f ba /reg=6</opc>
 421 <opr>Ev Ib</opr>
 422 </def>
 423 </instruction>
 424
 425 <instruction>
 426 <mnemonic>bts</mnemonic>
 427 <def>
 428 <pfx>aso oso rexw rexr rexx rexb</pfx>
 429 <opc>0f ab</opc>
 430 <opr>Ev Gv</opr>
 431 </def>
 432 <def>
 433 <pfx>aso oso rexw rexr rexx rexb</pfx>
 434 <opc>0f ba /reg=5</opc>
 435 <opr>Ev Ib</opr>
 436 </def>
 437 </instruction>
 438
 439 <instruction>
 440 <mnemonic>call</mnemonic>
 441 <def>
 442 <pfx>aso oso rexw rexr rexx rexb</pfx>
 443 <opc>ff /reg=2</opc>
 444 <opr>Ev</opr>
 445 <mode>def64</mode>
 446 </def>
 447 <def>
 448 <pfx>aso oso rexw rexr rexx rexb</pfx>
 449 <opc>ff /reg=3</opc>
 450 <opr>Ep</opr>
 451 </def>
 452 <def>
 453 <pfx>oso</pfx>
 454 <opc>e8</opc>
 455 <opr>Jz</opr>
 456 <mode>def64</mode>
 457 </def>
 458 <def>
 459 <pfx>oso</pfx>
 460 <opc>9a</opc>
 461 <opr>Ap</opr>
 462 <mode>inv64</mode>
 463 </def>
 464 </instruction>
 465
 466 <instruction>
 467 <mnemonic>cbw</mnemonic>
 468 <def>
 469 <pfx>oso rexw</pfx>
 470 <opc>98 /o=16</opc>
 471 </def>
 472 </instruction>
 473
 474 <instruction>
 475 <mnemonic>cwde</mnemonic>
 476 <def>
 477 <pfx>oso rexw</pfx>
 478 <opc>98 /o=32</opc>
 479 </def>
 480 </instruction>
 481
 482 <instruction>
 483 <mnemonic>cdqe</mnemonic>
 484 <def>
 485 <pfx>oso rexw</pfx>
 486 <opc>98 /o=64</opc>
 487 </def>
 488 </instruction>
 489
 490 <instruction>
 491 <mnemonic>clc</mnemonic>
 492 <def>
 493 <opc>f8</opc>
 494 </def>
 495 </instruction>
 496
 497 <instruction>
 498 <mnemonic>cld</mnemonic>
 499 <def>
 500 <opc>fc</opc>
 501 </def>
 502 </instruction>
 503
 504 <instruction>
 505 <mnemonic>clflush</mnemonic>
 506 <def>
 507 <pfx>aso rexw rexr rexx rexb</pfx>
 508 <opc>0f ae /reg=7 /mod=!11</opc>
 509 <opr>M</opr>
 510 </def>
 511 </instruction>
 512
 513 <instruction>
 514 <mnemonic>clgi</mnemonic>
 515 <vendor>amd</vendor>
 516 <def>
 517 <opc>0f 01 /reg=3 /mod=11 /rm=5</opc>
 518 </def>
 519 </instruction>
 520
 521 <instruction>
 522 <mnemonic>cli</mnemonic>
 523 <def>
 524 <opc>fa</opc>
 525 </def>
 526 </instruction>
 527
 528 <instruction>
 529 <mnemonic>clts</mnemonic>
 530 <def>
 531 <opc>0f 06</opc>
 532 </def>
 533 </instruction>
 534
 535 <instruction>
 536 <mnemonic>cmc</mnemonic>
 537 <def>
 538 <opc>f5</opc>
 539 </def>
 540 </instruction>
 541
 542 <instruction>
 543 <mnemonic>cmovo</mnemonic>
 544 <def>
 545 <pfx>aso oso rexw rexr rexx rexb</pfx>
 546 <opc>0f 40</opc>
 547 <opr>Gv Ev</opr>
 548 </def>
 549 </instruction>
 550
 551 <instruction>
 552 <mnemonic>cmovno</mnemonic>
 553 <def>
 554 <pfx>aso oso rexw rexr rexx rexb</pfx>
 555 <opc>0f 41</opc>
 556 <opr>Gv Ev</opr>
 557 </def>
 558 </instruction>
 559
 560 <instruction>
 561 <mnemonic>cmovb</mnemonic>
 562 <def>
 563 <pfx>aso oso rexw rexr rexx rexb</pfx>
 564 <opc>0f 42</opc>
 565 <opr>Gv Ev</opr>
 566 </def>
 567 </instruction>
 568
 569 <instruction>
 570 <mnemonic>cmovae</mnemonic>
 571 <def>
 572 <pfx>aso oso rexw rexr rexx rexb</pfx>
 573 <opc>0f 43</opc>
 574 <opr>Gv Ev</opr>
 575 </def>
 576 </instruction>
 577
 578 <instruction>
 579 <mnemonic>cmovz</mnemonic>
 580 <def>
 581 <pfx>aso oso rexw rexr rexx rexb</pfx>
 582 <opc>0f 44</opc>
 583 <opr>Gv Ev</opr>
 584 </def>
 585 </instruction>
 586
 587 <instruction>
 588 <mnemonic>cmovnz</mnemonic>
 589 <def>
 590 <pfx>aso oso rexw rexr rexx rexb</pfx>
 591 <opc>0f 45</opc>
 592 <opr>Gv Ev</opr>
 593 </def>
 594 </instruction>
 595
 596 <instruction>
 597 <mnemonic>cmovbe</mnemonic>
 598 <def>
 599 <pfx>aso oso rexw rexr rexx rexb</pfx>
 600 <opc>0f 46</opc>
 601 <opr>Gv Ev</opr>
 602 </def>
 603 </instruction>
 604
 605 <instruction>
 606 <mnemonic>cmova</mnemonic>
 607 <def>
 608 <pfx>aso oso rexw rexr rexx rexb</pfx>
 609 <opc>0f 47</opc>
 610 <opr>Gv Ev</opr>
 611 </def>
 612 </instruction>
 613
 614 <instruction>
 615 <mnemonic>cmovs</mnemonic>
 616 <def>
 617 <pfx>aso oso rexw rexr rexx rexb</pfx>
 618 <opc>0f 48</opc>
 619 <opr>Gv Ev</opr>
 620 </def>
 621 </instruction>
 622
 623 <instruction>
 624 <mnemonic>cmovns</mnemonic>
 625 <def>
 626 <pfx>aso oso rexw rexr rexx rexb</pfx>
 627 <opc>0f 49</opc>
 628 <opr>Gv Ev</opr>
 629 </def>
 630 </instruction>
 631
 632 <instruction>
 633 <mnemonic>cmovp</mnemonic>
 634 <def>
 635 <pfx>aso oso rexw rexr rexx rexb</pfx>
 636 <opc>0f 4a</opc>
 637 <opr>Gv Ev</opr>
 638 </def>
 639 </instruction>
 640
 641 <instruction>
 642 <mnemonic>cmovnp</mnemonic>
 643 <def>
 644 <pfx>aso oso rexw rexr rexx rexb</pfx>
 645 <opc>0f 4b</opc>
 646 <opr>Gv Ev</opr>
 647 </def>
 648 </instruction>
 649
 650 <instruction>
 651 <mnemonic>cmovl</mnemonic>
 652 <def>
 653 <pfx>aso oso rexw rexr rexx rexb</pfx>
 654 <opc>0f 4c</opc>
 655 <opr>Gv Ev</opr>
 656 </def>
 657 </instruction>
 658
 659 <instruction>
 660 <mnemonic>cmovge</mnemonic>
 661 <def>
 662 <pfx>aso oso rexw rexr rexx rexb</pfx>
 663 <opc>0f 4d</opc>
 664 <opr>Gv Ev</opr>
 665 </def>
 666 </instruction>
 667
 668 <instruction>
 669 <mnemonic>cmovle</mnemonic>
 670 <def>
 671 <pfx>aso oso rexw rexr rexx rexb</pfx>
 672 <opc>0f 4e</opc>
 673 <opr>Gv Ev</opr>
 674 </def>
 675 </instruction>
 676
 677 <instruction>
 678 <mnemonic>cmovg</mnemonic>
 679 <def>
 680 <pfx>aso oso rexw rexr rexx rexb</pfx>
 681 <opc>0f 4f</opc>
 682 <opr>Gv Ev</opr>
 683 </def>
 684 </instruction>
 685
 686 <instruction>
 687 <mnemonic>cmp</mnemonic>
 688 <def>
 689 <pfx>aso rexr rexx rexb</pfx>
 690 <opc>38</opc>
 691 <opr>Eb Gb</opr>
 692 </def>
 693 <def>
 694 <pfx>aso oso rexw rexr rexx rexb</pfx>
 695 <opc>39</opc>
 696 <opr>Ev Gv</opr>
 697 </def>
 698 <def>
 699 <pfx>aso rexr rexx rexb</pfx>
 700 <opc>3a</opc>
 701 <opr>Gb Eb</opr>
 702 </def>
 703 <def>
 704 <pfx>aso oso rexw rexr rexx rexb</pfx>
 705 <opc>3b</opc>
 706 <opr>Gv Ev</opr>
 707 </def>
 708 <def>
 709 <opc>3c</opc>
 710 <opr>AL Ib</opr>
 711 </def>
 712 <def>
 713 <pfx>oso rexw</pfx>
 714 <opc>3d</opc>
 715 <opr>rAX Iz</opr>
 716 </def>
 717 <def>
 718 <pfx>aso rexr rexx rexb</pfx>
 719 <opc>80 /reg=7</opc>
 720 <opr>Eb Ib</opr>
 721 </def>
 722 <def>
 723 <pfx>aso rexr rexx rexb</pfx>
 724 <opc>82 /reg=7</opc>
 725 <opr>Eb Ib</opr>
 726 <mode>inv64</mode>
 727 </def>
 728 <def>
 729 <pfx>aso oso rexw rexr rexx rexb</pfx>
 730 <opc>81 /reg=7</opc>
 731 <opr>Ev Iz</opr>
 732 </def>
 733 <def>
 734 <pfx>aso oso rexw rexr rexx rexb</pfx>
 735 <opc>83 /reg=7</opc>
 736 <opr>Ev Ib</opr>
 737 </def>
 738 </instruction>
 739
 740 <instruction>
 741 <mnemonic>cmppd</mnemonic>
 742 <def>
 743 <pfx>aso rexr rexx rexb</pfx>
 744 <opc>sse66 0f c2</opc>
 745 <opr>V W Ib</opr>
 746 </def>
 747 </instruction>
 748
 749 <instruction>
 750 <mnemonic>cmpps</mnemonic>
 751 <def>
 752 <pfx>aso rexr rexx rexb</pfx>
 753 <opc>0f c2</opc>
 754 <opr>V W Ib</opr>
 755 </def>
 756 </instruction>
 757
 758 <instruction>
 759 <mnemonic>cmpsb</mnemonic>
 760 <def>
 761 <opc>a6</opc>
 762 </def>
 763 </instruction>
 764
 765 <instruction>
 766 <mnemonic>cmpsw</mnemonic>
 767 <def>
 768 <pfx>oso rexw</pfx>
 769 <opc>a7 /o=16</opc>
 770 </def>
 771 </instruction>
 772
 773 <instruction>
 774 <mnemonic>cmpsd</mnemonic>
 775 <def>
 776 <pfx>oso rexw</pfx>
 777 <opc>a7 /o=32</opc>
 778 </def>
 779 <def>
 780 <pfx>aso rexr rexx rexb</pfx>
 781 <opc>ssef2 0f c2</opc>
 782 <opr>V W Ib</opr>
 783 </def>
 784 </instruction>
 785
 786 <instruction>
 787 <mnemonic>cmpsq</mnemonic>
 788 <def>
 789 <pfx>oso rexw</pfx>
 790 <opc>a7 /o=64</opc>
 791 </def>
 792 </instruction>
 793
 794 <instruction>
 795 <mnemonic>cmpss</mnemonic>
 796 <def>
 797 <pfx>aso rexr rexx rexb</pfx>
 798 <opc>ssef3 0f c2</opc>
 799 <opr>V W Ib</opr>
 800 </def>
 801 </instruction>
 802
 803 <instruction>
 804 <mnemonic>cmpxchg</mnemonic>
 805 <def>
 806 <pfx>aso rexr rexx rexb</pfx>
 807 <opc>0f b0</opc>
 808 <opr>Eb Gb</opr>
 809 </def>
 810 <def>
 811 <pfx>aso oso rexw rexr rexx rexb</pfx>
 812 <opc>0f b1</opc>
 813 <opr>Ev Gv</opr>
 814 </def>
 815 </instruction>
 816
 817 <instruction>
 818 <mnemonic>cmpxchg8b</mnemonic>
 819 <def>
 820 <pfx>aso rexr rexx rexb</pfx>
 821 <opc>0f c7 /reg=1</opc>
 822 <opr>M</opr>
 823 </def>
 824 </instruction>
 825
 826 <instruction>
 827 <mnemonic>comisd</mnemonic>
 828 <def>
 829 <pfx>aso rexr rexx rexb</pfx>
 830 <opc>sse66 0f 2f</opc>
 831 <opr>V W</opr>
 832 </def>
 833 </instruction>
 834
 835 <instruction>
 836 <mnemonic>comiss</mnemonic>
 837 <def>
 838 <pfx>aso rexr rexx rexb</pfx>
 839 <opc>0f 2f</opc>
 840 <opr>V W</opr>
 841 </def>
 842 </instruction>
 843
 844 <instruction>
 845 <mnemonic>cpuid</mnemonic>
 846 <def>
 847 <opc>0f a2</opc>
 848 </def>
 849 </instruction>
 850
 851 <instruction>
 852 <mnemonic>cvtdq2pd</mnemonic>
 853 <def>
 854 <pfx>aso rexr rexx rexb</pfx>
 855 <opc>ssef3 0f e6</opc>
 856 <opr>V W</opr>
 857 </def>
 858 </instruction>
 859
 860 <instruction>
 861 <mnemonic>cvtdq2ps</mnemonic>
 862 <def>
 863 <pfx>aso rexr rexx rexb</pfx>
 864 <opc>0f 5b</opc>
 865 <opr>V W</opr>
 866 </def>
 867 </instruction>
 868
 869 <instruction>
 870 <mnemonic>cvtpd2dq</mnemonic>
 871 <def>
 872 <pfx>aso rexr rexx rexb</pfx>
 873 <opc>ssef2 0f e6</opc>
 874 <opr>V W</opr>
 875 </def>
 876 </instruction>
 877
 878 <instruction>
 879 <mnemonic>cvtpd2pi</mnemonic>
 880 <def>
 881 <pfx>aso rexr rexx rexb</pfx>
 882 <opc>sse66 0f 2d</opc>
 883 <opr>P W</opr>
 884 </def>
 885 </instruction>
 886
 887 <instruction>
 888 <mnemonic>cvtpd2ps</mnemonic>
 889 <def>
 890 <pfx>aso rexr rexx rexb</pfx>
 891 <opc>sse66 0f 5a</opc>
 892 <opr>V W</opr>
 893 </def>
 894 </instruction>
 895
 896 <instruction>
 897 <mnemonic>cvtpi2ps</mnemonic>
 898 <def>
 899 <pfx>aso rexr rexx rexb</pfx>
 900 <opc>0f 2a</opc>
 901 <opr>V Q</opr>
 902 </def>
 903 </instruction>
 904
 905 <instruction>
 906 <mnemonic>cvtpi2pd</mnemonic>
 907 <def>
 908 <pfx>aso rexr rexx rexb</pfx>
 909 <opc>sse66 0f 2a</opc>
 910 <opr>V Q</opr>
 911 </def>
 912 </instruction>
 913
 914 <instruction>
 915 <mnemonic>cvtps2dq</mnemonic>
 916 <def>
 917 <pfx>aso rexr rexx rexb</pfx>
 918 <opc>sse66 0f 5b</opc>
 919 <opr>V W</opr>
 920 </def>
 921 </instruction>
 922
 923 <instruction>
 924 <mnemonic>cvtps2pi</mnemonic>
 925 <def>
 926 <pfx>aso rexr rexx rexb</pfx>
 927 <opc>0f 2d</opc>
 928 <opr>P W</opr>
 929 </def>
 930 </instruction>
 931
 932 <instruction>
 933 <mnemonic>cvtps2pd</mnemonic>
 934 <def>
 935 <pfx>aso rexr rexx rexb</pfx>
 936 <opc>0f 5a</opc>
 937 <opr>V W</opr>
 938 </def>
 939 </instruction>
 940
 941 <instruction>
 942 <mnemonic>cvtsd2si</mnemonic>
 943 <def>
 944 <pfx>aso rexw rexr rexx rexb</pfx>
 945 <opc>ssef2 0f 2d</opc>
 946 <opr>Gy W</opr>
 947 </def>
 948 </instruction>
 949
 950 <instruction>
 951 <mnemonic>cvtsd2ss</mnemonic>
 952 <def>
 953 <pfx>aso rexr rexx rexb</pfx>
 954 <opc>ssef2 0f 5a</opc>
 955 <opr>V W</opr>
 956 </def>
 957 </instruction>
 958
 959 <instruction>
 960 <mnemonic>cvtsi2ss</mnemonic>
 961 <def>
 962 <pfx>aso rexw rexr rexx rexb</pfx>
 963 <opc>ssef3 0f 2a</opc>
 964 <opr>V Ex</opr>
 965 </def>
 966 </instruction>
 967
 968 <instruction>
 969 <mnemonic>cvtss2si</mnemonic>
 970 <def>
 971 <pfx>aso rexw rexr rexx rexb</pfx>
 972 <opc>ssef3 0f 2d</opc>
 973 <opr>Gy W</opr>
 974 </def>
 975 </instruction>
 976
 977 <instruction>
 978 <mnemonic>cvtss2sd</mnemonic>
 979 <def>
 980 <pfx>aso rexr rexx rexb</pfx>
 981 <opc>ssef3 0f 5a</opc>
 982 <opr>V W</opr>
 983 </def>
 984 </instruction>
 985
 986 <instruction>
 987 <mnemonic>cvttpd2pi</mnemonic>
 988 <def>
 989 <pfx>aso rexr rexx rexb</pfx>
 990 <opc>sse66 0f 2c</opc>
 991 <opr>P W</opr>
 992 </def>
 993 </instruction>
 994
 995 <instruction>
 996 <mnemonic>cvttpd2dq</mnemonic>
 997 <def>
 998 <pfx>aso rexr rexx rexb</pfx>
 999 <opc>sse66 0f e6</opc>
 1000 <opr>V W</opr>
 1001 </def>
 1002 </instruction>
 1003
 1004 <instruction>
 1005 <mnemonic>cvttps2dq</mnemonic>
 1006 <def>
 1007 <pfx>aso rexr rexx rexb</pfx>
 1008 <opc>ssef3 0f 5b</opc>
 1009 <opr>V W</opr>
 1010 </def>
 1011 </instruction>
 1012
 1013 <instruction>
 1014 <mnemonic>cvttps2pi</mnemonic>
 1015 <def>
 1016 <pfx>aso rexr rexx rexb</pfx>
 1017 <opc>0f 2c</opc>
 1018 <opr>P W</opr>
 1019 </def>
 1020 </instruction>
 1021
 1022 <instruction>
 1023 <mnemonic>cvttsd2si</mnemonic>
 1024 <def>
 1025 <pfx>aso rexw rexr rexx rexb</pfx>
 1026 <opc>ssef2 0f 2c</opc>
 1027 <opr>Gy Wsd</opr>
 1028 </def>
 1029 </instruction>
 1030
 1031 <instruction>
 1032 <mnemonic>cvtsi2sd</mnemonic>
 1033 <def>
 1034 <pfx>aso rexw rexr rexx rexb</pfx>
 1035 <opc>ssef2 0f 2a</opc>
 1036 <opr>V Ex</opr>
 1037 </def>
 1038 </instruction>
 1039
 1040 <instruction>
 1041 <mnemonic>cvttss2si</mnemonic>
 1042 <def>
 1043 <pfx>aso rexw rexr rexx rexb</pfx>
 1044 <opc>ssef3 0f 2c</opc>
 1045 <opr>Gy Wsd</opr>
 1046 </def>
 1047 </instruction>
 1048
 1049 <instruction>
 1050 <mnemonic>cwd</mnemonic>
 1051 <def>
 1052 <pfx>oso rexw</pfx>
 1053 <opc>99 /o=16</opc>
 1054 </def>
 1055 </instruction>
 1056
 1057 <instruction>
 1058 <mnemonic>cdq</mnemonic>
 1059 <def>
 1060 <pfx>oso rexw</pfx>
 1061 <opc>99 /o=32</opc>
 1062 </def>
 1063 </instruction>
 1064
 1065 <instruction>
 1066 <mnemonic>cqo</mnemonic>
 1067 <def>
 1068 <pfx>oso rexw</pfx>
 1069 <opc>99 /o=64</opc>
 1070 </def>
 1071 </instruction>
 1072
 1073 <instruction>
 1074 <mnemonic>daa</mnemonic>
 1075 <def>
 1076 <opc>27</opc>
 1077 <mode>inv64</mode>
 1078 </def>
 1079 </instruction>
 1080
 1081 <instruction>
 1082 <mnemonic>das</mnemonic>
 1083 <def>
 1084 <opc>2f</opc>
 1085 <mode>inv64</mode>
 1086 </def>
 1087 </instruction>
 1088
 1089 <instruction>
 1090 <mnemonic>dec</mnemonic>
 1091 <def>
 1092 <pfx>oso</pfx>
 1093 <opc>48</opc>
 1094 <opr>eAX</opr>
 1095 </def>
 1096 <def>
 1097 <pfx>oso</pfx>
 1098 <opc>49</opc>
 1099 <opr>eCX</opr>
 1100 </def>
 1101 <def>
 1102 <pfx>oso</pfx>
 1103 <opc>4a</opc>
 1104 <opr>eDX</opr>
 1105 </def>
 1106 <def>
 1107 <pfx>oso</pfx>
 1108 <opc>4b</opc>
 1109 <opr>eBX</opr>
 1110 </def>
 1111 <def>
 1112 <pfx>oso</pfx>
 1113 <opc>4c</opc>
 1114 <opr>eSP</opr>
 1115 </def>
 1116 <def>
 1117 <pfx>oso</pfx>
 1118 <opc>4d</opc>
 1119 <opr>eBP</opr>
 1120 </def>
 1121 <def>
 1122 <pfx>oso</pfx>
 1123 <opc>4e</opc>
 1124 <opr>eSI</opr>
 1125 </def>
 1126 <def>
 1127 <pfx>oso</pfx>
 1128 <opc>4f</opc>
 1129 <opr>eDI</opr>
 1130 </def>
 1131 <def>
 1132 <pfx>aso rexw rexr rexx rexb</pfx>
 1133 <opc>fe /reg=1</opc>
 1134 <opr>Eb</opr>
 1135 </def>
 1136 <def>
 1137 <pfx>aso oso rexw rexr rexx rexb</pfx>
 1138 <opc>ff /reg=1</opc>
 1139 <opr>Ev</opr>
 1140 </def>
 1141 </instruction>
 1142
 1143 <instruction>
 1144 <mnemonic>div</mnemonic>
 1145 <def>
 1146 <pfx>aso oso rexw rexr rexx rexb</pfx>
 1147 <opc>f7 /reg=6</opc>
 1148 <opr>Ev</opr>
 1149 </def>
 1150 <def>
 1151 <pfx>aso rexw rexr rexx rexb</pfx>
 1152 <opc>f6 /reg=6</opc>
 1153 <opr>Eb</opr>
 1154 </def>
 1155 </instruction>
 1156
 1157 <instruction>
 1158 <mnemonic>divpd</mnemonic>
 1159 <def>
 1160 <pfx>aso rexr rexx rexb</pfx>
 1161 <opc>sse66 0f 5e</opc>
 1162 <opr>V W</opr>
 1163 </def>
 1164 </instruction>
 1165
 1166 <instruction>
 1167 <mnemonic>divps</mnemonic>
 1168 <def>
 1169 <pfx>aso rexr rexx rexb</pfx>
 1170 <opc>0f 5e</opc>
 1171 <opr>V W</opr>
 1172 </def>
 1173 </instruction>
 1174
 1175 <instruction>
 1176 <mnemonic>divsd</mnemonic>
 1177 <def>
 1178 <pfx>aso rexr rexx rexb</pfx>
 1179 <opc>ssef2 0f 5e</opc>
 1180 <opr>V W</opr>
 1181 </def>
 1182 </instruction>
 1183
 1184 <instruction>
 1185 <mnemonic>divss</mnemonic>
 1186 <def>
 1187 <pfx>aso rexr rexx rexb</pfx>
 1188 <opc>ssef3 0f 5e</opc>
 1189 <opr>V W</opr>
 1190 </def>
 1191 </instruction>
 1192
 1193 <instruction>
 1194 <mnemonic>emms</mnemonic>
 1195 <def>
 1196 <opc>0f 77</opc>
 1197 </def>
 1198 </instruction>
 1199
 1200 <instruction>
 1201 <mnemonic>enter</mnemonic>
 1202 <def>
 1203 <opc>c8</opc>
 1204 <opr>Iw Ib</opr>
 1205 <mode>def64 depM</mode>
 1206 </def>
 1207 </instruction>
 1208
 1209 <instruction>
 1210 <mnemonic>f2xm1</mnemonic>
 1211 <class>X87</class>
 1212 <def>
 1213 <opc>d9 /mod=11 /x87=30</opc>
 1214 </def>
 1215 </instruction>
 1216
 1217 <instruction>
 1218 <mnemonic>fabs</mnemonic>
 1219 <class>X87</class>
 1220 <def>
 1221 <opc>d9 /mod=11 /x87=21</opc>
 1222 </def>
 1223 </instruction>
 1224
 1225 <instruction>
 1226 <mnemonic>fadd</mnemonic>
 1227 <class>X87</class>
 1228 <def>
 1229 <pfx>aso rexr rexx rexb</pfx>
 1230 <opc>dc /mod=!11 /reg=0</opc>
 1231 <opr>Mq</opr>
 1232 </def>
 1233 <def>
 1234 <pfx>aso rexr rexx rexb</pfx>
 1235 <opc>d8 /mod=!11 /reg=0</opc>
 1236 <opr>Md</opr>
 1237 </def>
 1238 <def>
 1239 <opc>dc /mod=11 /x87=00</opc>
 1240 <opr>ST0 ST0</opr>
 1241 </def>
 1242 <def>
 1243 <opc>dc /mod=11 /x87=01</opc>
 1244 <opr>ST1 ST0</opr>
 1245 </def>
 1246 <def>
 1247 <opc>dc /mod=11 /x87=02</opc>
 1248 <opr>ST2 ST0</opr>
 1249 </def>
 1250 <def>
 1251 <opc>dc /mod=11 /x87=03</opc>
 1252 <opr>ST3 ST0</opr>
 1253 </def>
 1254 <def>
 1255 <opc>dc /mod=11 /x87=04</opc>
 1256 <opr>ST4 ST0</opr>
 1257 </def>
 1258 <def>
 1259 <opc>dc /mod=11 /x87=05</opc>
 1260 <opr>ST5 ST0</opr>
 1261 </def>
 1262 <def>
 1263 <opc>dc /mod=11 /x87=06</opc>
 1264 <opr>ST6 ST0</opr>
 1265 </def>
 1266 <def>
 1267 <opc>dc /mod=11 /x87=07</opc>
 1268 <opr>ST7 ST0</opr>
 1269 </def>
 1270 <def>
 1271 <opc>d8 /mod=11 /x87=00</opc>
 1272 <opr>ST0 ST0</opr>
 1273 </def>
 1274 <def>
 1275 <opc>d8 /mod=11 /x87=01</opc>
 1276 <opr>ST0 ST1</opr>
 1277 </def>
 1278 <def>
 1279 <opc>d8 /mod=11 /x87=02</opc>
 1280 <opr>ST0 ST2</opr>
 1281 </def>
 1282 <def>
 1283 <opc>d8 /mod=11 /x87=03</opc>
 1284 <opr>ST0 ST3</opr>
 1285 </def>
 1286 <def>
 1287 <opc>d8 /mod=11 /x87=04</opc>
 1288 <opr>ST0 ST4</opr>
 1289 </def>
 1290 <def>
 1291 <opc>d8 /mod=11 /x87=05</opc>
 1292 <opr>ST0 ST5</opr>
 1293 </def>
 1294 <def>
 1295 <opc>d8 /mod=11 /x87=06</opc>
 1296 <opr>ST0 ST6</opr>
 1297 </def>
 1298 <def>
 1299 <opc>d8 /mod=11 /x87=07</opc>
 1300 <opr>ST0 ST7</opr>
 1301 </def>
 1302 </instruction>
 1303
 1304 <instruction>
 1305 <mnemonic>faddp</mnemonic>
 1306 <class>X87</class>
 1307 <def>
 1308 <opc>de /mod=11 /x87=00</opc>
 1309 <opr>ST0 ST0</opr>
 1310 </def>
 1311 <def>
 1312 <opc>de /mod=11 /x87=01</opc>
 1313 <opr>ST1 ST0</opr>
 1314 </def>
 1315 <def>
 1316 <opc>de /mod=11 /x87=02</opc>
 1317 <opr>ST2 ST0</opr>
 1318 </def>
 1319 <def>
 1320 <opc>de /mod=11 /x87=03</opc>
 1321 <opr>ST3 ST0</opr>
 1322 </def>
 1323 <def>
 1324 <opc>de /mod=11 /x87=04</opc>
 1325 <opr>ST4 ST0</opr>
 1326 </def>
 1327 <def>
 1328 <opc>de /mod=11 /x87=05</opc>
 1329 <opr>ST5 ST0</opr>
 1330 </def>
 1331 <def>
 1332 <opc>de /mod=11 /x87=06</opc>
 1333 <opr>ST6 ST0</opr>
 1334 </def>
 1335 <def>
 1336 <opc>de /mod=11 /x87=07</opc>
 1337 <opr>ST7 ST0</opr>
 1338 </def>
 1339 </instruction>
 1340
 1341 <instruction>
 1342 <mnemonic>fbld</mnemonic>
 1343 <class>X87</class>
 1344 <def>
 1345 <pfx>aso rexr rexx rexb</pfx>
 1346 <opc>df /mod=!11 /reg=4</opc>
 1347 <opr>Mt</opr>
 1348 </def>
 1349 </instruction>
 1350
 1351 <instruction>
 1352 <mnemonic>fbstp</mnemonic>
 1353 <class>X87</class>
 1354 <def>
 1355 <pfx>aso rexr rexx rexb</pfx>
 1356 <opc>df /mod=!11 /reg=6</opc>
 1357 <opr>Mt</opr>
 1358 </def>
 1359 </instruction>
 1360
 1361 <instruction>
 1362 <mnemonic>fchs</mnemonic>
 1363 <class>X87</class>
 1364 <def>
 1365 <opc>d9 /mod=11 /x87=20</opc>
 1366 </def>
 1367 </instruction>
 1368
 1369 <instruction>
 1370 <mnemonic>fclex</mnemonic>
 1371 <class>X87</class>
 1372 <def>
 1373 <opc>db /mod=11 /x87=22</opc>
 1374 </def>
 1375 </instruction>
 1376
 1377 <instruction>
 1378 <mnemonic>fcmovb</mnemonic>
 1379 <class>X87</class>
 1380 <def>
 1381 <opc>da /mod=11 /x87=00</opc>
 1382 <opr>ST0 ST0</opr>
 1383 </def>
 1384 <def>
 1385 <opc>da /mod=11 /x87=01</opc>
 1386 <opr>ST0 ST1</opr>
 1387 </def>
 1388 <def>
 1389 <opc>da /mod=11 /x87=02</opc>
 1390 <opr>ST0 ST2</opr>
 1391 </def>
 1392 <def>
 1393 <opc>da /mod=11 /x87=03</opc>
 1394 <opr>ST0 ST3</opr>
 1395 </def>
 1396 <def>
 1397 <opc>da /mod=11 /x87=04</opc>
 1398 <opr>ST0 ST4</opr>
 1399 </def>
 1400 <def>
 1401 <opc>da /mod=11 /x87=05</opc>
 1402 <opr>ST0 ST5</opr>
 1403 </def>
 1404 <def>
 1405 <opc>da /mod=11 /x87=06</opc>
 1406 <opr>ST0 ST6</opr>
 1407 </def>
 1408 <def>
 1409 <opc>da /mod=11 /x87=07</opc>
 1410 <opr>ST0 ST7</opr>
 1411 </def>
 1412 </instruction>
 1413
 1414 <instruction>
 1415 <mnemonic>fcmove</mnemonic>
 1416 <class>X87</class>
 1417 <def>
 1418 <opc>da /mod=11 /x87=08</opc>
 1419 <opr>ST0 ST0</opr>
 1420 </def>
 1421 <def>
 1422 <opc>da /mod=11 /x87=09</opc>
 1423 <opr>ST0 ST1</opr>
 1424 </def>
 1425 <def>
 1426 <opc>da /mod=11 /x87=0a</opc>
 1427 <opr>ST0 ST2</opr>
 1428 </def>
 1429 <def>
 1430 <opc>da /mod=11 /x87=0b</opc>
 1431 <opr>ST0 ST3</opr>
 1432 </def>
 1433 <def>
 1434 <opc>da /mod=11 /x87=0c</opc>
 1435 <opr>ST0 ST4</opr>
 1436 </def>
 1437 <def>
 1438 <opc>da /mod=11 /x87=0d</opc>
 1439 <opr>ST0 ST5</opr>
 1440 </def>
 1441 <def>
 1442 <opc>da /mod=11 /x87=0e</opc>
 1443 <opr>ST0 ST6</opr>
 1444 </def>
 1445 <def>
 1446 <opc>da /mod=11 /x87=0f</opc>
 1447 <opr>ST0 ST7</opr>
 1448 </def>
 1449 </instruction>
 1450
 1451 <instruction>
 1452 <mnemonic>fcmovbe</mnemonic>
 1453 <class>X87</class>
 1454 <def>
 1455 <opc>da /mod=11 /x87=10</opc>
 1456 <opr>ST0 ST0</opr>
 1457 </def>
 1458 <def>
 1459 <opc>da /mod=11 /x87=11</opc>
 1460 <opr>ST0 ST1</opr>
 1461 </def>
 1462 <def>
 1463 <opc>da /mod=11 /x87=12</opc>
 1464 <opr>ST0 ST2</opr>
 1465 </def>
 1466 <def>
 1467 <opc>da /mod=11 /x87=13</opc>
 1468 <opr>ST0 ST3</opr>
 1469 </def>
 1470 <def>
 1471 <opc>da /mod=11 /x87=14</opc>
 1472 <opr>ST0 ST4</opr>
 1473 </def>
 1474 <def>
 1475 <opc>da /mod=11 /x87=15</opc>
 1476 <opr>ST0 ST5</opr>
 1477 </def>
 1478 <def>
 1479 <opc>da /mod=11 /x87=16</opc>
 1480 <opr>ST0 ST6</opr>
 1481 </def>
 1482 <def>
 1483 <opc>da /mod=11 /x87=17</opc>
 1484 <opr>ST0 ST7</opr>
 1485 </def>
 1486 </instruction>
 1487
 1488 <instruction>
 1489 <mnemonic>fcmovu</mnemonic>
 1490 <class>X87</class>
 1491 <def>
 1492 <opc>da /mod=11 /x87=18</opc>
 1493 <opr>ST0 ST0</opr>
 1494 </def>
 1495 <def>
 1496 <opc>da /mod=11 /x87=19</opc>
 1497 <opr>ST0 ST1</opr>
 1498 </def>
 1499 <def>
 1500 <opc>da /mod=11 /x87=1a</opc>
 1501 <opr>ST0 ST2</opr>
 1502 </def>
 1503 <def>
 1504 <opc>da /mod=11 /x87=1b</opc>
 1505 <opr>ST0 ST3</opr>
 1506 </def>
 1507 <def>
 1508 <opc>da /mod=11 /x87=1c</opc>
 1509 <opr>ST0 ST4</opr>
 1510 </def>
 1511 <def>
 1512 <opc>da /mod=11 /x87=1d</opc>
 1513 <opr>ST0 ST5</opr>
 1514 </def>
 1515 <def>
 1516 <opc>da /mod=11 /x87=1e</opc>
 1517 <opr>ST0 ST6</opr>
 1518 </def>
 1519 <def>
 1520 <opc>da /mod=11 /x87=1f</opc>
 1521 <opr>ST0 ST7</opr>
 1522 </def>
 1523 </instruction>
 1524
 1525 <instruction>
 1526 <mnemonic>fcmovnb</mnemonic>
 1527 <class>X87</class>
 1528 <def>
 1529 <opc>db /mod=11 /x87=00</opc>
 1530 <opr>ST0 ST0</opr>
 1531 </def>
 1532 <def>
 1533 <opc>db /mod=11 /x87=01</opc>
 1534 <opr>ST0 ST1</opr>
 1535 </def>
 1536 <def>
 1537 <opc>db /mod=11 /x87=02</opc>
 1538 <opr>ST0 ST2</opr>
 1539 </def>
 1540 <def>
 1541 <opc>db /mod=11 /x87=03</opc>
 1542 <opr>ST0 ST3</opr>
 1543 </def>
 1544 <def>
 1545 <opc>db /mod=11 /x87=04</opc>
 1546 <opr>ST0 ST4</opr>
 1547 </def>
 1548 <def>
 1549 <opc>db /mod=11 /x87=05</opc>
 1550 <opr>ST0 ST5</opr>
 1551 </def>
 1552 <def>
 1553 <opc>db /mod=11 /x87=06</opc>
 1554 <opr>ST0 ST6</opr>
 1555 </def>
 1556 <def>
 1557 <opc>db /mod=11 /x87=07</opc>
 1558 <opr>ST0 ST7</opr>
 1559 </def>
 1560 </instruction>
 1561
 1562 <instruction>
 1563 <mnemonic>fcmovne</mnemonic>
 1564 <class>X87</class>
 1565 <def>
 1566 <opc>db /mod=11 /x87=08</opc>
 1567 <opr>ST0 ST0</opr>
 1568 </def>
 1569 <def>
 1570 <opc>db /mod=11 /x87=09</opc>
 1571 <opr>ST0 ST1</opr>
 1572 </def>
 1573 <def>
 1574 <opc>db /mod=11 /x87=0a</opc>
 1575 <opr>ST0 ST2</opr>
 1576 </def>
 1577 <def>
 1578 <opc>db /mod=11 /x87=0b</opc>
 1579 <opr>ST0 ST3</opr>
 1580 </def>
 1581 <def>
 1582 <opc>db /mod=11 /x87=0c</opc>
 1583 <opr>ST0 ST4</opr>
 1584 </def>
 1585 <def>
 1586 <opc>db /mod=11 /x87=0d</opc>
 1587 <opr>ST0 ST5</opr>
 1588 </def>
 1589 <def>
 1590 <opc>db /mod=11 /x87=0e</opc>
 1591 <opr>ST0 ST6</opr>
 1592 </def>
 1593 <def>
 1594 <opc>db /mod=11 /x87=0f</opc>
 1595 <opr>ST0 ST7</opr>
 1596 </def>
 1597 </instruction>
 1598
 1599 <instruction>
 1600 <mnemonic>fcmovnbe</mnemonic>
 1601 <class>X87</class>
 1602 <def>
 1603 <opc>db /mod=11 /x87=10</opc>
 1604 <opr>ST0 ST0</opr>
 1605 </def>
 1606 <def>
 1607 <opc>db /mod=11 /x87=11</opc>
 1608 <opr>ST0 ST1</opr>
 1609 </def>
 1610 <def>
 1611 <opc>db /mod=11 /x87=12</opc>
 1612 <opr>ST0 ST2</opr>
 1613 </def>
 1614 <def>
 1615 <opc>db /mod=11 /x87=13</opc>
 1616 <opr>ST0 ST3</opr>
 1617 </def>
 1618 <def>
 1619 <opc>db /mod=11 /x87=14</opc>
 1620 <opr>ST0 ST4</opr>
 1621 </def>
 1622 <def>
 1623 <opc>db /mod=11 /x87=15</opc>
 1624 <opr>ST0 ST5</opr>
 1625 </def>
 1626 <def>
 1627 <opc>db /mod=11 /x87=16</opc>
 1628 <opr>ST0 ST6</opr>
 1629 </def>
 1630 <def>
 1631 <opc>db /mod=11 /x87=17</opc>
 1632 <opr>ST0 ST7</opr>
 1633 </def>
 1634 </instruction>
 1635
 1636 <instruction>
 1637 <mnemonic>fcmovnu</mnemonic>
 1638 <class>X87</class>
 1639 <def>
 1640 <opc>db /mod=11 /x87=18</opc>
 1641 <opr>ST0 ST0</opr>
 1642 </def>
 1643 <def>
 1644 <opc>db /mod=11 /x87=19</opc>
 1645 <opr>ST0 ST1</opr>
 1646 </def>
 1647 <def>
 1648 <opc>db /mod=11 /x87=1a</opc>
 1649 <opr>ST0 ST2</opr>
 1650 </def>
 1651 <def>
 1652 <opc>db /mod=11 /x87=1b</opc>
 1653 <opr>ST0 ST3</opr>
 1654 </def>
 1655 <def>
 1656 <opc>db /mod=11 /x87=1c</opc>
 1657 <opr>ST0 ST4</opr>
 1658 </def>
 1659 <def>
 1660 <opc>db /mod=11 /x87=1d</opc>
 1661 <opr>ST0 ST5</opr>
 1662 </def>
 1663 <def>
 1664 <opc>db /mod=11 /x87=1e</opc>
 1665 <opr>ST0 ST6</opr>
 1666 </def>
 1667 <def>
 1668 <opc>db /mod=11 /x87=1f</opc>
 1669 <opr>ST0 ST7</opr>
 1670 </def>
 1671 </instruction>
 1672
 1673 <instruction>
 1674 <mnemonic>fucomi</mnemonic>
 1675 <class>X87</class>
 1676 <def>
 1677 <opc>db /mod=11 /x87=28</opc>
 1678 <opr>ST0 ST0</opr>
 1679 </def>
 1680 <def>
 1681 <opc>db /mod=11 /x87=29</opc>
 1682 <opr>ST0 ST1</opr>
 1683 </def>
 1684 <def>
 1685 <opc>db /mod=11 /x87=2a</opc>
 1686 <opr>ST0 ST2</opr>
 1687 </def>
 1688 <def>
 1689 <opc>db /mod=11 /x87=2b</opc>
 1690 <opr>ST0 ST3</opr>
 1691 </def>
 1692 <def>
 1693 <opc>db /mod=11 /x87=2c</opc>
 1694 <opr>ST0 ST4</opr>
 1695 </def>
 1696 <def>
 1697 <opc>db /mod=11 /x87=2d</opc>
 1698 <opr>ST0 ST5</opr>
 1699 </def>
 1700 <def>
 1701 <opc>db /mod=11 /x87=2e</opc>
 1702 <opr>ST0 ST6</opr>
 1703 </def>
 1704 <def>
 1705 <opc>db /mod=11 /x87=2f</opc>
 1706 <opr>ST0 ST7</opr>
 1707 </def>
 1708 </instruction>
 1709
 1710 <instruction>
 1711 <mnemonic>fcom</mnemonic>
 1712 <class>X87</class>
 1713 <def>
 1714 <pfx>aso rexr rexx rexb</pfx>
 1715 <opc>d8 /mod=!11 /reg=2</opc>
 1716 <opr>Md</opr>
 1717 </def>
 1718 <def>
 1719 <pfx>aso rexr rexx rexb</pfx>
 1720 <opc>dc /mod=!11 /reg=2</opc>
 1721 <opr>Mq</opr>
 1722 </def>
 1723 <def>
 1724 <opc>d8 /mod=11 /x87=10</opc>
 1725 <opr>ST0 ST0</opr>
 1726 </def>
 1727 <def>
 1728 <opc>d8 /mod=11 /x87=11</opc>
 1729 <opr>ST0 ST1</opr>
 1730 </def>
 1731 <def>
 1732 <opc>d8 /mod=11 /x87=12</opc>
 1733 <opr>ST0 ST2</opr>
 1734 </def>
 1735 <def>
 1736 <opc>d8 /mod=11 /x87=13</opc>
 1737 <opr>ST0 ST3</opr>
 1738 </def>
 1739 <def>
 1740 <opc>d8 /mod=11 /x87=14</opc>
 1741 <opr>ST0 ST4</opr>
 1742 </def>
 1743 <def>
 1744 <opc>d8 /mod=11 /x87=15</opc>
 1745 <opr>ST0 ST5</opr>
 1746 </def>
 1747 <def>
 1748 <opc>d8 /mod=11 /x87=16</opc>
 1749 <opr>ST0 ST6</opr>
 1750 </def>
 1751 <def>
 1752 <opc>d8 /mod=11 /x87=17</opc>
 1753 <opr>ST0 ST7</opr>
 1754 </def>
 1755 </instruction>
 1756
 1757 <instruction>
 1758 <mnemonic>fcom2</mnemonic>
 1759 <class>X87 UNDOC</class>
 1760 <def>
 1761 <opc>dc /mod=11 /x87=10</opc>
 1762 <opr>ST0</opr>
 1763 </def>
 1764 <def>
 1765 <opc>dc /mod=11 /x87=11</opc>
 1766 <opr>ST1</opr>
 1767 </def>
 1768 <def>
 1769 <opc>dc /mod=11 /x87=12</opc>
 1770 <opr>ST2</opr>
 1771 </def>
 1772 <def>
 1773 <opc>dc /mod=11 /x87=13</opc>
 1774 <opr>ST3</opr>
 1775 </def>
 1776 <def>
 1777 <opc>dc /mod=11 /x87=14</opc>
 1778 <opr>ST4</opr>
 1779 </def>
 1780 <def>
 1781 <opc>dc /mod=11 /x87=15</opc>
 1782 <opr>ST5</opr>
 1783 </def>
 1784 <def>
 1785 <opc>dc /mod=11 /x87=16</opc>
 1786 <opr>ST6</opr>
 1787 </def>
 1788 <def>
 1789 <opc>dc /mod=11 /x87=17</opc>
 1790 <opr>ST7</opr>
 1791 </def>
 1792 </instruction>
 1793
 1794 <instruction>
 1795 <mnemonic>fcomp3</mnemonic>
 1796 <class>X87 UNDOC</class>
 1797 <def>
 1798 <opc>dc /mod=11 /x87=18</opc>
 1799 <opr>ST0</opr>
 1800 </def>
 1801 <def>
 1802 <opc>dc /mod=11 /x87=19</opc>
 1803 <opr>ST1</opr>
 1804 </def>
 1805 <def>
 1806 <opc>dc /mod=11 /x87=1a</opc>
 1807 <opr>ST2</opr>
 1808 </def>
 1809 <def>
 1810 <opc>dc /mod=11 /x87=1b</opc>
 1811 <opr>ST3</opr>
 1812 </def>
 1813 <def>
 1814 <opc>dc /mod=11 /x87=1c</opc>
 1815 <opr>ST4</opr>
 1816 </def>
 1817 <def>
 1818 <opc>dc /mod=11 /x87=1d</opc>
 1819 <opr>ST5</opr>
 1820 </def>
 1821 <def>
 1822 <opc>dc /mod=11 /x87=1e</opc>
 1823 <opr>ST6</opr>
 1824 </def>
 1825 <def>
 1826 <opc>dc /mod=11 /x87=1f</opc>
 1827 <opr>ST7</opr>
 1828 </def>
 1829 </instruction>
 1830
 1831 <instruction>
 1832 <mnemonic>fcomi</mnemonic>
 1833 <class>X87</class>
 1834 <def>
 1835 <opc>db /mod=11 /x87=30</opc>
 1836 <opr>ST0 ST0</opr>
 1837 </def>
 1838 <def>
 1839 <opc>db /mod=11 /x87=31</opc>
 1840 <opr>ST0 ST1</opr>
 1841 </def>
 1842 <def>
 1843 <opc>db /mod=11 /x87=32</opc>
 1844 <opr>ST0 ST2</opr>
 1845 </def>
 1846 <def>
 1847 <opc>db /mod=11 /x87=33</opc>
 1848 <opr>ST0 ST3</opr>
 1849 </def>
 1850 <def>
 1851 <opc>db /mod=11 /x87=34</opc>
 1852 <opr>ST0 ST4</opr>
 1853 </def>
 1854 <def>
 1855 <opc>db /mod=11 /x87=35</opc>
 1856 <opr>ST0 ST5</opr>
 1857 </def>
 1858 <def>
 1859 <opc>db /mod=11 /x87=36</opc>
 1860 <opr>ST0 ST6</opr>
 1861 </def>
 1862 <def>
 1863 <opc>db /mod=11 /x87=37</opc>
 1864 <opr>ST0 ST7</opr>
 1865 </def>
 1866 </instruction>
 1867
 1868 <instruction>
 1869 <mnemonic>fucomip</mnemonic>
 1870 <class>X87</class>
 1871 <def>
 1872 <opc>df /mod=11 /x87=28</opc>
 1873 <opr>ST0 ST0</opr>
 1874 </def>
 1875 <def>
 1876 <opc>df /mod=11 /x87=29</opc>
 1877 <opr>ST0 ST1</opr>
 1878 </def>
 1879 <def>
 1880 <opc>df /mod=11 /x87=2a</opc>
 1881 <opr>ST0 ST2</opr>
 1882 </def>
 1883 <def>
 1884 <opc>df /mod=11 /x87=2b</opc>
 1885 <opr>ST0 ST3</opr>
 1886 </def>
 1887 <def>
 1888 <opc>df /mod=11 /x87=2c</opc>
 1889 <opr>ST0 ST4</opr>
 1890 </def>
 1891 <def>
 1892 <opc>df /mod=11 /x87=2d</opc>
 1893 <opr>ST0 ST5</opr>
 1894 </def>
 1895 <def>
 1896 <opc>df /mod=11 /x87=2e</opc>
 1897 <opr>ST0 ST6</opr>
 1898 </def>
 1899 <def>
 1900 <opc>df /mod=11 /x87=2f</opc>
 1901 <opr>ST0 ST7</opr>
 1902 </def>
 1903 </instruction>
 1904
 1905 <instruction>
 1906 <mnemonic>fcomip</mnemonic>
 1907 <class>X87</class>
 1908 <def>
 1909 <opc>df /mod=11 /x87=30</opc>
 1910 <opr>ST0 ST0</opr>
 1911 </def>
 1912 <def>
 1913 <opc>df /mod=11 /x87=31</opc>
 1914 <opr>ST0 ST1</opr>
 1915 </def>
 1916 <def>
 1917 <opc>df /mod=11 /x87=32</opc>
 1918 <opr>ST0 ST2</opr>
 1919 </def>
 1920 <def>
 1921 <opc>df /mod=11 /x87=33</opc>
 1922 <opr>ST0 ST3</opr>
 1923 </def>
 1924 <def>
 1925 <opc>df /mod=11 /x87=34</opc>
 1926 <opr>ST0 ST4</opr>
 1927 </def>
 1928 <def>
 1929 <opc>df /mod=11 /x87=35</opc>
 1930 <opr>ST0 ST5</opr>
 1931 </def>
 1932 <def>
 1933 <opc>df /mod=11 /x87=36</opc>
 1934 <opr>ST0 ST6</opr>
 1935 </def>
 1936 <def>
 1937 <opc>df /mod=11 /x87=37</opc>
 1938 <opr>ST0 ST7</opr>
 1939 </def>
 1940 </instruction>
 1941
 1942 <instruction>
 1943 <mnemonic>fcomp</mnemonic>
 1944 <class>X87</class>
 1945 <def>
 1946 <pfx>aso rexr rexx rexb</pfx>
 1947 <opc>d8 /mod=!11 /reg=3</opc>
 1948 <opr>Md</opr>
 1949 </def>
 1950 <def>
 1951 <pfx>aso rexr rexx rexb</pfx>
 1952 <opc>dc /mod=!11 /reg=3</opc>
 1953 <opr>Mq</opr>
 1954 </def>
 1955 <def>
 1956 <opc>d8 /mod=11 /x87=18</opc>
 1957 <opr>ST0 ST0</opr>
 1958 </def>
 1959 <def>
 1960 <opc>d8 /mod=11 /x87=19</opc>
 1961 <opr>ST0 ST1</opr>
 1962 </def>
 1963 <def>
 1964 <opc>d8 /mod=11 /x87=1a</opc>
 1965 <opr>ST0 ST2</opr>
 1966 </def>
 1967 <def>
 1968 <opc>d8 /mod=11 /x87=1b</opc>
 1969 <opr>ST0 ST3</opr>
 1970 </def>
 1971 <def>
 1972 <opc>d8 /mod=11 /x87=1c</opc>
 1973 <opr>ST0 ST4</opr>
 1974 </def>
 1975 <def>
 1976 <opc>d8 /mod=11 /x87=1d</opc>
 1977 <opr>ST0 ST5</opr>
 1978 </def>
 1979 <def>
 1980 <opc>d8 /mod=11 /x87=1e</opc>
 1981 <opr>ST0 ST6</opr>
 1982 </def>
 1983 <def>
 1984 <opc>d8 /mod=11 /x87=1f</opc>
 1985 <opr>ST0 ST7</opr>
 1986 </def>
 1987 </instruction>
 1988
 1989 <instruction>
 1990 <mnemonic>fcomp5</mnemonic>
 1991 <class>X87 UNDOC</class>
 1992 <def>
 1993 <opc>de /mod=11 /x87=10</opc>
 1994 <opr>ST0</opr>
 1995 </def>
 1996 <def>
 1997 <opc>de /mod=11 /x87=11</opc>
 1998 <opr>ST1</opr>
 1999 </def>
 2000 <def>
 2001 <opc>de /mod=11 /x87=12</opc>
 2002 <opr>ST2</opr>
 2003 </def>
 2004 <def>
 2005 <opc>de /mod=11 /x87=13</opc>
 2006 <opr>ST3</opr>
 2007 </def>
 2008 <def>
 2009 <opc>de /mod=11 /x87=14</opc>
 2010 <opr>ST4</opr>
 2011 </def>
 2012 <def>
 2013 <opc>de /mod=11 /x87=15</opc>
 2014 <opr>ST5</opr>
 2015 </def>
 2016 <def>
 2017 <opc>de /mod=11 /x87=16</opc>
 2018 <opr>ST6</opr>
 2019 </def>
 2020 <def>
 2021 <opc>de /mod=11 /x87=17</opc>
 2022 <opr>ST7</opr>
 2023 </def>
 2024 </instruction>
 2025
 2026 <instruction>
 2027 <mnemonic>fcompp</mnemonic>
 2028 <class>X87</class>
 2029 <def>
 2030 <opc>de /mod=11 /x87=19</opc>
 2031 </def>
 2032 </instruction>
 2033
 2034 <instruction>
 2035 <mnemonic>fcos</mnemonic>
 2036 <class>X87</class>
 2037 <def>
 2038 <opc>d9 /mod=11 /x87=3f</opc>
 2039 </def>
 2040 </instruction>
 2041
 2042 <instruction>
 2043 <mnemonic>fdecstp</mnemonic>
 2044 <class>X87</class>
 2045 <def>
 2046 <opc>d9 /mod=11 /x87=36</opc>
 2047 </def>
 2048 </instruction>
 2049
 2050 <instruction>
 2051 <mnemonic>fdiv</mnemonic>
 2052 <class>X87</class>
 2053 <def>
 2054 <pfx>aso rexr rexx rexb</pfx>
 2055 <opc>dc /mod=!11 /reg=6</opc>
 2056 <opr>Mq</opr>
 2057 </def>
 2058 <def>
 2059 <opc>dc /mod=11 /x87=38</opc>
 2060 <opr>ST0 ST0</opr>
 2061 </def>
 2062 <def>
 2063 <opc>dc /mod=11 /x87=39</opc>
 2064 <opr>ST1 ST0</opr>
 2065 </def>
 2066 <def>
 2067 <opc>dc /mod=11 /x87=3a</opc>
 2068 <opr>ST2 ST0</opr>
 2069 </def>
 2070 <def>
 2071 <opc>dc /mod=11 /x87=3b</opc>
 2072 <opr>ST3 ST0</opr>
 2073 </def>
 2074 <def>
 2075 <opc>dc /mod=11 /x87=3c</opc>
 2076 <opr>ST4 ST0</opr>
 2077 </def>
 2078 <def>
 2079 <opc>dc /mod=11 /x87=3d</opc>
 2080 <opr>ST5 ST0</opr>
 2081 </def>
 2082 <def>
 2083 <opc>dc /mod=11 /x87=3e</opc>
 2084 <opr>ST6 ST0</opr>
 2085 </def>
 2086 <def>
 2087 <opc>dc /mod=11 /x87=3f</opc>
 2088 <opr>ST7 ST0</opr>
 2089 </def>
 2090 <def>
 2091 <pfx>aso rexr rexx rexb</pfx>
 2092 <opc>d8 /mod=!11 /reg=6</opc>
 2093 <opr>Md</opr>
 2094 </def>
 2095 <def>
 2096 <opc>d8 /mod=11 /x87=30</opc>
 2097 <opr>ST0 ST0</opr>
 2098 </def>
 2099 <def>
 2100 <opc>d8 /mod=11 /x87=31</opc>
 2101 <opr>ST0 ST1</opr>
 2102 </def>
 2103 <def>
 2104 <opc>d8 /mod=11 /x87=32</opc>
 2105 <opr>ST0 ST2</opr>
 2106 </def>
 2107 <def>
 2108 <opc>d8 /mod=11 /x87=33</opc>
 2109 <opr>ST0 ST3</opr>
 2110 </def>
 2111 <def>
 2112 <opc>d8 /mod=11 /x87=34</opc>
 2113 <opr>ST0 ST4</opr>
 2114 </def>
 2115 <def>
 2116 <opc>d8 /mod=11 /x87=35</opc>
 2117 <opr>ST0 ST5</opr>
 2118 </def>
 2119 <def>
 2120 <opc>d8 /mod=11 /x87=36</opc>
 2121 <opr>ST0 ST6</opr>
 2122 </def>
 2123 <def>
 2124 <opc>d8 /mod=11 /x87=37</opc>
 2125 <opr>ST0 ST7</opr>
 2126 </def>
 2127 </instruction>
 2128
 2129 <instruction>
 2130 <mnemonic>fdivp</mnemonic>
 2131 <class>X87</class>
 2132 <def>
 2133 <opc>de /mod=11 /x87=38</opc>
 2134 <opr>ST0 ST0</opr>
 2135 </def>
 2136 <def>
 2137 <opc>de /mod=11 /x87=39</opc>
 2138 <opr>ST1 ST0</opr>
 2139 </def>
 2140 <def>
 2141 <opc>de /mod=11 /x87=3a</opc>
 2142 <opr>ST2 ST0</opr>
 2143 </def>
 2144 <def>
 2145 <opc>de /mod=11 /x87=3b</opc>
 2146 <opr>ST3 ST0</opr>
 2147 </def>
 2148 <def>
 2149 <opc>de /mod=11 /x87=3c</opc>
 2150 <opr>ST4 ST0</opr>
 2151 </def>
 2152 <def>
 2153 <opc>de /mod=11 /x87=3d</opc>
 2154 <opr>ST5 ST0</opr>
 2155 </def>
 2156 <def>
 2157 <opc>de /mod=11 /x87=3e</opc>
 2158 <opr>ST6 ST0</opr>
 2159 </def>
 2160 <def>
 2161 <opc>de /mod=11 /x87=3f</opc>
 2162 <opr>ST7 ST0</opr>
 2163 </def>
 2164 </instruction>
 2165
 2166 <instruction>
 2167 <mnemonic>fdivr</mnemonic>
 2168 <class>X87</class>
 2169 <def>
 2170 <pfx>aso rexr rexx rexb</pfx>
 2171 <opc>dc /mod=!11 /reg=7</opc>
 2172 <opr>Mq</opr>
 2173 </def>
 2174 <def>
 2175 <opc>dc /mod=11 /x87=30</opc>
 2176 <opr>ST0 ST0</opr>
 2177 </def>
 2178 <def>
 2179 <opc>dc /mod=11 /x87=31</opc>
 2180 <opr>ST1 ST0</opr>
 2181 </def>
 2182 <def>
 2183 <opc>dc /mod=11 /x87=32</opc>
 2184 <opr>ST2 ST0</opr>
 2185 </def>
 2186 <def>
 2187 <opc>dc /mod=11 /x87=33</opc>
 2188 <opr>ST3 ST0</opr>
 2189 </def>
 2190 <def>
 2191 <opc>dc /mod=11 /x87=34</opc>
 2192 <opr>ST4 ST0</opr>
 2193 </def>
 2194 <def>
 2195 <opc>dc /mod=11 /x87=35</opc>
 2196 <opr>ST5 ST0</opr>
 2197 </def>
 2198 <def>
 2199 <opc>dc /mod=11 /x87=36</opc>
 2200 <opr>ST6 ST0</opr>
 2201 </def>
 2202 <def>
 2203 <opc>dc /mod=11 /x87=37</opc>
 2204 <opr>ST7 ST0</opr>
 2205 </def>
 2206 <def>
 2207 <pfx>aso rexr rexx rexb</pfx>
 2208 <opc>d8 /mod=!11 /reg=7</opc>
 2209 <opr>Md</opr>
 2210 </def>
 2211 <def>
 2212 <opc>d8 /mod=11 /x87=38</opc>
 2213 <opr>ST0 ST0</opr>
 2214 </def>
 2215 <def>
 2216 <opc>d8 /mod=11 /x87=39</opc>
 2217 <opr>ST0 ST1</opr>
 2218 </def>
 2219 <def>
 2220 <opc>d8 /mod=11 /x87=3a</opc>
 2221 <opr>ST0 ST2</opr>
 2222 </def>
 2223 <def>
 2224 <opc>d8 /mod=11 /x87=3b</opc>
 2225 <opr>ST0 ST3</opr>
 2226 </def>
 2227 <def>
 2228 <opc>d8 /mod=11 /x87=3c</opc>
 2229 <opr>ST0 ST4</opr>
 2230 </def>
 2231 <def>
 2232 <opc>d8 /mod=11 /x87=3d</opc>
 2233 <opr>ST0 ST5</opr>
 2234 </def>
 2235 <def>
 2236 <opc>d8 /mod=11 /x87=3e</opc>
 2237 <opr>ST0 ST6</opr>
 2238 </def>
 2239 <def>
 2240 <opc>d8 /mod=11 /x87=3f</opc>
 2241 <opr>ST0 ST7</opr>
 2242 </def>
 2243 </instruction>
 2244
 2245 <instruction>
 2246 <mnemonic>fdivrp</mnemonic>
 2247 <class>X87</class>
 2248 <def>
 2249 <opc>de /mod=11 /x87=30</opc>
 2250 <opr>ST0 ST0</opr>
 2251 </def>
 2252 <def>
 2253 <opc>de /mod=11 /x87=31</opc>
 2254 <opr>ST1 ST0</opr>
 2255 </def>
 2256 <def>
 2257 <opc>de /mod=11 /x87=32</opc>
 2258 <opr>ST2 ST0</opr>
 2259 </def>
 2260 <def>
 2261 <opc>de /mod=11 /x87=33</opc>
 2262 <opr>ST3 ST0</opr>
 2263 </def>
 2264 <def>
 2265 <opc>de /mod=11 /x87=34</opc>
 2266 <opr>ST4 ST0</opr>
 2267 </def>
 2268 <def>
 2269 <opc>de /mod=11 /x87=35</opc>
 2270 <opr>ST5 ST0</opr>
 2271 </def>
 2272 <def>
 2273 <opc>de /mod=11 /x87=36</opc>
 2274 <opr>ST6 ST0</opr>
 2275 </def>
 2276 <def>
 2277 <opc>de /mod=11 /x87=37</opc>
 2278 <opr>ST7 ST0</opr>
 2279 </def>
 2280 </instruction>
 2281
 2282 <instruction>
 2283 <mnemonic>femms</mnemonic>
 2284 <def>
 2285 <opc>0f 0e</opc>
 2286 </def>
 2287 </instruction>
 2288
 2289 <instruction>
 2290 <mnemonic>ffree</mnemonic>
 2291 <class>X87</class>
 2292 <def>
 2293 <opc>dd /mod=11 /x87=00</opc>
 2294 <opr>ST0</opr>
 2295 </def>
 2296 <def>
 2297 <opc>dd /mod=11 /x87=01</opc>
 2298 <opr>ST1</opr>
 2299 </def>
 2300 <def>
 2301 <opc>dd /mod=11 /x87=02</opc>
 2302 <opr>ST2</opr>
 2303 </def>
 2304 <def>
 2305 <opc>dd /mod=11 /x87=03</opc>
 2306 <opr>ST3</opr>
 2307 </def>
 2308 <def>
 2309 <opc>dd /mod=11 /x87=04</opc>
 2310 <opr>ST4</opr>
 2311 </def>
 2312 <def>
 2313 <opc>dd /mod=11 /x87=05</opc>
 2314 <opr>ST5</opr>
 2315 </def>
 2316 <def>
 2317 <opc>dd /mod=11 /x87=06</opc>
 2318 <opr>ST6</opr>
 2319 </def>
 2320 <def>
 2321 <opc>dd /mod=11 /x87=07</opc>
 2322 <opr>ST7</opr>
 2323 </def>
 2324 </instruction>
 2325
 2326 <instruction>
 2327 <mnemonic>ffreep</mnemonic>
 2328 <class>X87</class>
 2329 <def>
 2330 <opc>df /mod=11 /x87=00</opc>
 2331 <opr>ST0</opr>
 2332 </def>
 2333 <def>
 2334 <opc>df /mod=11 /x87=01</opc>
 2335 <opr>ST1</opr>
 2336 </def>
 2337 <def>
 2338 <opc>df /mod=11 /x87=02</opc>
 2339 <opr>ST2</opr>
 2340 </def>
 2341 <def>
 2342 <opc>df /mod=11 /x87=03</opc>
 2343 <opr>ST3</opr>
 2344 </def>
 2345 <def>
 2346 <opc>df /mod=11 /x87=04</opc>
 2347 <opr>ST4</opr>
 2348 </def>
 2349 <def>
 2350 <opc>df /mod=11 /x87=05</opc>
 2351 <opr>ST5</opr>
 2352 </def>
 2353 <def>
 2354 <opc>df /mod=11 /x87=06</opc>
 2355 <opr>ST6</opr>
 2356 </def>
 2357 <def>
 2358 <opc>df /mod=11 /x87=07</opc>
 2359 <opr>ST7</opr>
 2360 </def>
 2361 </instruction>
 2362
 2363 <instruction>
 2364 <mnemonic>ficom</mnemonic>
 2365 <class>X87</class>
 2366 <def>
 2367 <pfx>aso rexr rexx rexb</pfx>
 2368 <opc>de /mod=!11 /reg=2</opc>
 2369 <opr>Mw</opr>
 2370 </def>
 2371 <def>
 2372 <pfx>aso rexr rexx rexb</pfx>
 2373 <opc>da /mod=!11 /reg=2</opc>
 2374 <opr>Md</opr>
 2375 </def>
 2376 </instruction>
 2377
 2378 <instruction>
 2379 <mnemonic>ficomp</mnemonic>
 2380 <class>X87</class>
 2381 <def>
 2382 <pfx>aso rexr rexx rexb</pfx>
 2383 <opc>de /mod=!11 /reg=3</opc>
 2384 <opr>Mw</opr>
 2385 </def>
 2386 <def>
 2387 <pfx>aso rexr rexx rexb</pfx>
 2388 <opc>da /mod=!11 /reg=3</opc>
 2389 <opr>Md</opr>
 2390 </def>
 2391 </instruction>
 2392
 2393 <instruction>
 2394 <mnemonic>fild</mnemonic>
 2395 <class>X87</class>
 2396 <def>
 2397 <pfx>aso rexr rexx rexb</pfx>
 2398 <opc>df /mod=!11 /reg=0</opc>
 2399 <opr>Mw</opr>
 2400 </def>
 2401 <def>
 2402 <pfx>aso rexr rexx rexb</pfx>
 2403 <opc>df /mod=!11 /reg=5</opc>
 2404 <opr>Mq</opr>
 2405 </def>
 2406 <def>
 2407 <pfx>aso rexr rexx rexb</pfx>
 2408 <opc>db /mod=!11 /reg=0</opc>
 2409 <opr>Md</opr>
 2410 </def>
 2411 </instruction>
 2412
 2413 <instruction>
 2414 <mnemonic>fncstp</mnemonic>
 2415 <class>X87</class>
 2416 <def>
 2417 <opc>d9 /mod=11 /x87=37</opc>
 2418 </def>
 2419 </instruction>
 2420
 2421 <instruction>
 2422 <mnemonic>fninit</mnemonic>
 2423 <class>X87</class>
 2424 <def>
 2425 <opc>db /mod=11 /x87=23</opc>
 2426 </def>
 2427 </instruction>
 2428
 2429 <instruction>
 2430 <mnemonic>fiadd</mnemonic>
 2431 <class>X87</class>
 2432 <def>
 2433 <pfx>aso rexr rexx rexb</pfx>
 2434 <opc>da /mod=!11 /reg=0</opc>
 2435 <opr>Md</opr>
 2436 </def>
 2437 <def>
 2438 <pfx>aso rexr rexx rexb</pfx>
 2439 <opc>de /mod=!11 /reg=0</opc>
 2440 <opr>Mw</opr>
 2441 </def>
 2442 </instruction>
 2443
 2444 <instruction>
 2445 <mnemonic>fidivr</mnemonic>
 2446 <class>X87</class>
 2447 <def>
 2448 <pfx>aso rexr rexx rexb</pfx>
 2449 <opc>da /mod=!11 /reg=7</opc>
 2450 <opr>Md</opr>
 2451 </def>
 2452 <def>
 2453 <pfx>aso rexr rexx rexb</pfx>
 2454 <opc>de /mod=!11 /reg=7</opc>
 2455 <opr>Mw</opr>
 2456 </def>
 2457 </instruction>
 2458
 2459 <instruction>
 2460 <mnemonic>fidiv</mnemonic>
 2461 <class>X87</class>
 2462 <def>
 2463 <pfx>aso rexr rexx rexb</pfx>
 2464 <opc>da /mod=!11 /reg=6</opc>
 2465 <opr>Md</opr>
 2466 </def>
 2467 <def>
 2468 <pfx>aso rexr rexx rexb</pfx>
 2469 <opc>de /mod=!11 /reg=6</opc>
 2470 <opr>Mw</opr>
 2471 </def>
 2472 </instruction>
 2473
 2474 <instruction>
 2475 <mnemonic>fisub</mnemonic>
 2476 <class>X87</class>
 2477 <def>
 2478 <pfx>aso rexr rexx rexb</pfx>
 2479 <opc>da /mod=!11 /reg=4</opc>
 2480 <opr>Md</opr>
 2481 </def>
 2482 <def>
 2483 <pfx>aso rexr rexx rexb</pfx>
 2484 <opc>de /mod=!11 /reg=4</opc>
 2485 <opr>Mw</opr>
 2486 </def>
 2487 </instruction>
 2488
 2489 <instruction>
 2490 <mnemonic>fisubr</mnemonic>
 2491 <class>X87</class>
 2492 <def>
 2493 <pfx>aso rexr rexx rexb</pfx>
 2494 <opc>da /mod=!11 /reg=5</opc>
 2495 <opr>Md</opr>
 2496 </def>
 2497 <def>
 2498 <pfx>aso rexr rexx rexb</pfx>
 2499 <opc>de /mod=!11 /reg=5</opc>
 2500 <opr>Mw</opr>
 2501 </def>
 2502 </instruction>
 2503
 2504 <instruction>
 2505 <mnemonic>fist</mnemonic>
 2506 <class>X87</class>
 2507 <def>
 2508 <pfx>aso rexr rexx rexb</pfx>
 2509 <opc>df /mod=!11 /reg=2</opc>
 2510 <opr>Mw</opr>
 2511 </def>
 2512 <def>
 2513 <pfx>aso rexr rexx rexb</pfx>
 2514 <opc>db /mod=!11 /reg=2</opc>
 2515 <opr>Md</opr>
 2516 </def>
 2517 </instruction>
 2518
 2519 <instruction>
 2520 <mnemonic>fistp</mnemonic>
 2521 <class>X87</class>
 2522 <def>
 2523 <pfx>aso rexr rexx rexb</pfx>
 2524 <opc>df /mod=!11 /reg=3</opc>
 2525 <opr>Mw</opr>
 2526 </def>
 2527 <def>
 2528 <pfx>aso rexr rexx rexb</pfx>
 2529 <opc>df /mod=!11 /reg=7</opc>
 2530 <opr>Mq</opr>
 2531 </def>
 2532 <def>
 2533 <pfx>aso rexr rexx rexb</pfx>
 2534 <opc>db /mod=!11 /reg=3</opc>
 2535 <opr>Md</opr>
 2536 </def>
 2537 </instruction>
 2538
 2539 <instruction>
 2540 <mnemonic>fisttp</mnemonic>
 2541 <class>X87</class>
 2542 <def>
 2543 <pfx>aso rexr rexx rexb</pfx>
 2544 <opc>db /mod=!11 /reg=1</opc>
 2545 <opr>Md</opr>
 2546 </def>
 2547 <def>
 2548 <pfx>aso rexr rexx rexb</pfx>
 2549 <opc>dd /mod=!11 /reg=1</opc>
 2550 <opr>Mq</opr>
 2551 </def>
 2552 <def>
 2553 <pfx>aso rexr rexx rexb</pfx>
 2554 <opc>df /mod=!11 /reg=1</opc>
 2555 <opr>Mw</opr>
 2556 </def>
 2557 </instruction>
 2558
 2559 <instruction>
 2560 <mnemonic>fld</mnemonic>
 2561 <class>X87</class>
 2562 <def>
 2563 <pfx>aso rexr rexx rexb</pfx>
 2564 <opc>db /mod=!11 /reg=5</opc>
 2565 <opr>Mt</opr>
 2566 </def>
 2567 <def>
 2568 <pfx>aso rexr rexx rexb</pfx>
 2569 <opc>dd /mod=!11 /reg=0</opc>
 2570 <opr>Mq</opr>
 2571 </def>
 2572 <def>
 2573 <pfx>aso rexr rexx rexb</pfx>
 2574 <opc>d9 /mod=!11 /reg=0</opc>
 2575 <opr>Md</opr>
 2576 </def>
 2577 <def>
 2578 <opc>d9 /mod=11 /x87=00</opc>
 2579 <opr>ST0</opr>
 2580 </def>
 2581 <def>
 2582 <opc>d9 /mod=11 /x87=01</opc>
 2583 <opr>ST1</opr>
 2584 </def>
 2585 <def>
 2586 <opc>d9 /mod=11 /x87=02</opc>
 2587 <opr>ST2</opr>
 2588 </def>
 2589 <def>
 2590 <opc>d9 /mod=11 /x87=03</opc>
 2591 <opr>ST3</opr>
 2592 </def>
 2593 <def>
 2594 <opc>d9 /mod=11 /x87=04</opc>
 2595 <opr>ST4</opr>
 2596 </def>
 2597 <def>
 2598 <opc>d9 /mod=11 /x87=05</opc>
 2599 <opr>ST5</opr>
 2600 </def>
 2601 <def>
 2602 <opc>d9 /mod=11 /x87=06</opc>
 2603 <opr>ST6</opr>
 2604 </def>
 2605 <def>
 2606 <opc>d9 /mod=11 /x87=07</opc>
 2607 <opr>ST7</opr>
 2608 </def>
 2609 </instruction>
 2610
 2611 <instruction>
 2612 <mnemonic>fld1</mnemonic>
 2613 <class>X87</class>
 2614 <def>
 2615 <opc>d9 /mod=11 /x87=28</opc>
 2616 </def>
 2617 </instruction>
 2618
 2619 <instruction>
 2620 <mnemonic>fldl2t</mnemonic>
 2621 <class>X87</class>
 2622 <def>
 2623 <opc>d9 /mod=11 /x87=29</opc>
 2624 </def>
 2625 </instruction>
 2626
 2627 <instruction>
 2628 <mnemonic>fldl2e</mnemonic>
 2629 <class>X87</class>
 2630 <def>
 2631 <opc>d9 /mod=11 /x87=2a</opc>
 2632 </def>
 2633 </instruction>
 2634
 2635 <instruction>
 2636 <mnemonic>fldlpi</mnemonic>
 2637 <class>X87</class>
 2638 <def>
 2639 <opc>d9 /mod=11 /x87=2b</opc>
 2640 </def>
 2641 </instruction>
 2642
 2643 <instruction>
 2644 <mnemonic>fldlg2</mnemonic>
 2645 <class>X87</class>
 2646 <def>
 2647 <opc>d9 /mod=11 /x87=2c</opc>
 2648 </def>
 2649 </instruction>
 2650
 2651 <instruction>
 2652 <mnemonic>fldln2</mnemonic>
 2653 <class>X87</class>
 2654 <def>
 2655 <opc>d9 /mod=11 /x87=2d</opc>
 2656 </def>
 2657 </instruction>
 2658
 2659 <instruction>
 2660 <mnemonic>fldz</mnemonic>
 2661 <class>X87</class>
 2662 <def>
 2663 <opc>d9 /mod=11 /x87=2e</opc>
 2664 </def>
 2665 </instruction>
 2666
 2667 <instruction>
 2668 <mnemonic>fldcw</mnemonic>
 2669 <class>X87</class>
 2670 <def>
 2671 <pfx>aso rexr rexx rexb</pfx>
 2672 <opc>d9 /mod=!11 /reg=5</opc>
 2673 <opr>Mw</opr>
 2674 </def>
 2675 </instruction>
 2676
 2677 <instruction>
 2678 <mnemonic>fldenv</mnemonic>
 2679 <class>X87</class>
 2680 <def>
 2681 <pfx>aso rexr rexx rexb</pfx>
 2682 <opc>d9 /mod=!11 /reg=4</opc>
 2683 <opr>M</opr>
 2684 </def>
 2685 </instruction>
 2686
 2687 <instruction>
 2688 <mnemonic>fmul</mnemonic>
 2689 <class>X87</class>
 2690 <def>
 2691 <pfx>aso rexr rexx rexb</pfx>
 2692 <opc>dc /mod=!11 /reg=1</opc>
 2693 <opr>Mq</opr>
 2694 </def>
 2695 <def>
 2696 <opc>dc /mod=11 /x87=08</opc>
 2697 <opr>ST0 ST0</opr>
 2698 </def>
 2699 <def>
 2700 <opc>dc /mod=11 /x87=09</opc>
 2701 <opr>ST1 ST0</opr>
 2702 </def>
 2703 <def>
 2704 <opc>dc /mod=11 /x87=0a</opc>
 2705 <opr>ST2 ST0</opr>
 2706 </def>
 2707 <def>
 2708 <opc>dc /mod=11 /x87=0b</opc>
 2709 <opr>ST3 ST0</opr>
 2710 </def>
 2711 <def>
 2712 <opc>dc /mod=11 /x87=0c</opc>
 2713 <opr>ST4 ST0</opr>
 2714 </def>
 2715 <def>
 2716 <opc>dc /mod=11 /x87=0d</opc>
 2717 <opr>ST5 ST0</opr>
 2718 </def>
 2719 <def>
 2720 <opc>dc /mod=11 /x87=0e</opc>
 2721 <opr>ST6 ST0</opr>
 2722 </def>
 2723 <def>
 2724 <opc>dc /mod=11 /x87=0f</opc>
 2725 <opr>ST7 ST0</opr>
 2726 </def>
 2727 <def>
 2728 <pfx>aso rexr rexx rexb</pfx>
 2729 <opc>d8 /mod=!11 /reg=1</opc>
 2730 <opr>Md</opr>
 2731 </def>
 2732 <def>
 2733 <opc>d8 /mod=11 /x87=08</opc>
 2734 <opr>ST0 ST0</opr>
 2735 </def>
 2736 <def>
 2737 <opc>d8 /mod=11 /x87=09</opc>
 2738 <opr>ST0 ST1</opr>
 2739 </def>
 2740 <def>
 2741 <opc>d8 /mod=11 /x87=0a</opc>
 2742 <opr>ST0 ST2</opr>
 2743 </def>
 2744 <def>
 2745 <opc>d8 /mod=11 /x87=0b</opc>
 2746 <opr>ST0 ST3</opr>
 2747 </def>
 2748 <def>
 2749 <opc>d8 /mod=11 /x87=0c</opc>
 2750 <opr>ST0 ST4</opr>
 2751 </def>
 2752 <def>
 2753 <opc>d8 /mod=11 /x87=0d</opc>
 2754 <opr>ST0 ST5</opr>
 2755 </def>
 2756 <def>
 2757 <opc>d8 /mod=11 /x87=0e</opc>
 2758 <opr>ST0 ST6</opr>
 2759 </def>
 2760 <def>
 2761 <opc>d8 /mod=11 /x87=0f</opc>
 2762 <opr>ST0 ST7</opr>
 2763 </def>
 2764 </instruction>
 2765
 2766 <instruction>
 2767 <mnemonic>fmulp</mnemonic>
 2768 <class>X87</class>
 2769 <def>
 2770 <opc>de /mod=11 /x87=08</opc>
 2771 <opr>ST0 ST0</opr>
 2772 </def>
 2773 <def>
 2774 <opc>de /mod=11 /x87=09</opc>
 2775 <opr>ST1 ST0</opr>
 2776 </def>
 2777 <def>
 2778 <opc>de /mod=11 /x87=0a</opc>
 2779 <opr>ST2 ST0</opr>
 2780 </def>
 2781 <def>
 2782 <opc>de /mod=11 /x87=0b</opc>
 2783 <opr>ST3 ST0</opr>
 2784 </def>
 2785 <def>
 2786 <opc>de /mod=11 /x87=0c</opc>
 2787 <opr>ST4 ST0</opr>
 2788 </def>
 2789 <def>
 2790 <opc>de /mod=11 /x87=0d</opc>
 2791 <opr>ST5 ST0</opr>
 2792 </def>
 2793 <def>
 2794 <opc>de /mod=11 /x87=0e</opc>
 2795 <opr>ST6 ST0</opr>
 2796 </def>
 2797 <def>
 2798 <opc>de /mod=11 /x87=0f</opc>
 2799 <opr>ST7 ST0</opr>
 2800 </def>
 2801 </instruction>
 2802
 2803 <instruction>
 2804 <mnemonic>fimul</mnemonic>
 2805 <class>X87</class>
 2806 <def>
 2807 <pfx>aso rexr rexx rexb</pfx>
 2808 <opc>da /mod=!11 /reg=1</opc>
 2809 <opr>Md</opr>
 2810 </def>
 2811 <def>
 2812 <pfx>aso rexr rexx rexb</pfx>
 2813 <opc>de /mod=!11 /reg=1</opc>
 2814 <opr>Mw</opr>
 2815 </def>
 2816 </instruction>
 2817
 2818 <instruction>
 2819 <mnemonic>fnop</mnemonic>
 2820 <class>X87</class>
 2821 <def>
 2822 <opc>d9 /mod=11 /x87=10</opc>
 2823 </def>
 2824 </instruction>
 2825
 2826 <instruction>
 2827 <mnemonic>fpatan</mnemonic>
 2828 <class>X87</class>
 2829 <def>
 2830 <opc>d9 /mod=11 /x87=33</opc>
 2831 </def>
 2832 </instruction>
 2833
 2834 <instruction>
 2835 <mnemonic>fprem</mnemonic>
 2836 <class>X87</class>
 2837 <def>
 2838 <opc>d9 /mod=11 /x87=38</opc>
 2839 </def>
 2840 </instruction>
 2841
 2842 <instruction>
 2843 <mnemonic>fprem1</mnemonic>
 2844 <class>X87</class>
 2845 <def>
 2846 <opc>d9 /mod=11 /x87=35</opc>
 2847 </def>
 2848 </instruction>
 2849
 2850 <instruction>
 2851 <mnemonic>fptan</mnemonic>
 2852 <class>X87</class>
 2853 <def>
 2854 <opc>d9 /mod=11 /x87=32</opc>
 2855 </def>
 2856 </instruction>
 2857
 2858 <instruction>
 2859 <mnemonic>frndint</mnemonic>
 2860 <class>X87</class>
 2861 <def>
 2862 <opc>d9 /mod=11 /x87=3c</opc>
 2863 </def>
 2864 </instruction>
 2865
 2866 <instruction>
 2867 <mnemonic>frstor</mnemonic>
 2868 <class>X87</class>
 2869 <def>
 2870 <pfx>aso rexr rexx rexb</pfx>
 2871 <opc>dd /mod=!11 /reg=4</opc>
 2872 <opr>M</opr>
 2873 </def>
 2874 </instruction>
 2875
 2876 <instruction>
 2877 <mnemonic>fnsave</mnemonic>
 2878 <class>X87</class>
 2879 <def>
 2880 <pfx>aso rexr rexx rexb</pfx>
 2881 <opc>dd /mod=!11 /reg=6</opc>
 2882 <opr>M</opr>
 2883 </def>
 2884 </instruction>
 2885
 2886 <instruction>
 2887 <mnemonic>fscale</mnemonic>
 2888 <class>X87</class>
 2889 <def>
 2890 <opc>d9 /mod=11 /x87=3d</opc>
 2891 </def>
 2892 </instruction>
 2893
 2894 <instruction>
 2895 <mnemonic>fsin</mnemonic>
 2896 <class>X87</class>
 2897 <def>
 2898 <opc>d9 /mod=11 /x87=3e</opc>
 2899 </def>
 2900 </instruction>
 2901
 2902 <instruction>
 2903 <mnemonic>fsincos</mnemonic>
 2904 <class>X87</class>
 2905 <def>
 2906 <opc>d9 /mod=11 /x87=3b</opc>
 2907 </def>
 2908 </instruction>
 2909
 2910 <instruction>
 2911 <mnemonic>fsqrt</mnemonic>
 2912 <class>X87</class>
 2913 <def>
 2914 <opc>d9 /mod=11 /x87=3a</opc>
 2915 </def>
 2916 </instruction>
 2917
 2918 <instruction>
 2919 <mnemonic>fstp</mnemonic>
 2920 <class>X87</class>
 2921 <def>
 2922 <pfx>aso rexr rexx rexb</pfx>
 2923 <opc>db /mod=!11 /reg=7</opc>
 2924 <opr>Mt</opr>
 2925 </def>
 2926 <def>
 2927 <pfx>aso rexr rexx rexb</pfx>
 2928 <opc>dd /mod=!11 /reg=3</opc>
 2929 <opr>Mq</opr>
 2930 </def>
 2931 <def>
 2932 <pfx>aso rexr rexx rexb</pfx>
 2933 <opc>d9 /mod=!11 /reg=3</opc>
 2934 <opr>Md</opr>
 2935 </def>
 2936 <def>
 2937 <opc>dd /mod=11 /x87=18</opc>
 2938 <opr>ST0</opr>
 2939 </def>
 2940 <def>
 2941 <opc>dd /mod=11 /x87=19</opc>
 2942 <opr>ST1</opr>
 2943 </def>
 2944 <def>
 2945 <opc>dd /mod=11 /x87=1a</opc>
 2946 <opr>ST2</opr>
 2947 </def>
 2948 <def>
 2949 <opc>dd /mod=11 /x87=1b</opc>
 2950 <opr>ST3</opr>
 2951 </def>
 2952 <def>
 2953 <opc>dd /mod=11 /x87=1c</opc>
 2954 <opr>ST4</opr>
 2955 </def>
 2956 <def>
 2957 <opc>dd /mod=11 /x87=1d</opc>
 2958 <opr>ST5</opr>
 2959 </def>
 2960 <def>
 2961 <opc>dd /mod=11 /x87=1e</opc>
 2962 <opr>ST6</opr>
 2963 </def>
 2964 <def>
 2965 <opc>dd /mod=11 /x87=1f</opc>
 2966 <opr>ST7</opr>
 2967 </def>
 2968 </instruction>
 2969
 2970 <instruction>
 2971 <mnemonic>fstp1</mnemonic>
 2972 <def>
 2973 <opc>d9 /mod=11 /x87=18</opc>
 2974 <opr>ST0</opr>
 2975 </def>
 2976 <def>
 2977 <opc>d9 /mod=11 /x87=19</opc>
 2978 <opr>ST1</opr>
 2979 </def>
 2980 <def>
 2981 <opc>d9 /mod=11 /x87=1a</opc>
 2982 <opr>ST2</opr>
 2983 </def>
 2984 <def>
 2985 <opc>d9 /mod=11 /x87=1b</opc>
 2986 <opr>ST3</opr>
 2987 </def>
 2988 <def>
 2989 <opc>d9 /mod=11 /x87=1c</opc>
 2990 <opr>ST4</opr>
 2991 </def>
 2992 <def>
 2993 <opc>d9 /mod=11 /x87=1d</opc>
 2994 <opr>ST5</opr>
 2995 </def>
 2996 <def>
 2997 <opc>d9 /mod=11 /x87=1e</opc>
 2998 <opr>ST6</opr>
 2999 </def>
 3000 <def>
 3001 <opc>d9 /mod=11 /x87=1f</opc>
 3002 <opr>ST7</opr>
 3003 </def>
 3004 </instruction>
 3005
 3006 <instruction>
 3007 <mnemonic>fstp8</mnemonic>
 3008 <def>
 3009 <opc>df /mod=11 /x87=10</opc>
 3010 <opr>ST0</opr>
 3011 </def>
 3012 <def>
 3013 <opc>df /mod=11 /x87=11</opc>
 3014 <opr>ST1</opr>
 3015 </def>
 3016 <def>
 3017 <opc>df /mod=11 /x87=12</opc>
 3018 <opr>ST2</opr>
 3019 </def>
 3020 <def>
 3021 <opc>df /mod=11 /x87=13</opc>
 3022 <opr>ST3</opr>
 3023 </def>
 3024 <def>
 3025 <opc>df /mod=11 /x87=14</opc>
 3026 <opr>ST4</opr>
 3027 </def>
 3028 <def>
 3029 <opc>df /mod=11 /x87=15</opc>
 3030 <opr>ST5</opr>
 3031 </def>
 3032 <def>
 3033 <opc>df /mod=11 /x87=16</opc>
 3034 <opr>ST6</opr>
 3035 </def>
 3036 <def>
 3037 <opc>df /mod=11 /x87=17</opc>
 3038 <opr>ST7</opr>
 3039 </def>
 3040 </instruction>
 3041
 3042 <instruction>
 3043 <mnemonic>fstp9</mnemonic>
 3044 <def>
 3045 <opc>df /mod=11 /x87=18</opc>
 3046 <opr>ST0</opr>
 3047 </def>
 3048 <def>
 3049 <opc>df /mod=11 /x87=19</opc>
 3050 <opr>ST1</opr>
 3051 </def>
 3052 <def>
 3053 <opc>df /mod=11 /x87=1a</opc>
 3054 <opr>ST2</opr>
 3055 </def>
 3056 <def>
 3057 <opc>df /mod=11 /x87=1b</opc>
 3058 <opr>ST3</opr>
 3059 </def>
 3060 <def>
 3061 <opc>df /mod=11 /x87=1c</opc>
 3062 <opr>ST4</opr>
 3063 </def>
 3064 <def>
 3065 <opc>df /mod=11 /x87=1d</opc>
 3066 <opr>ST5</opr>
 3067 </def>
 3068 <def>
 3069 <opc>df /mod=11 /x87=1e</opc>
 3070 <opr>ST6</opr>
 3071 </def>
 3072 <def>
 3073 <opc>df /mod=11 /x87=1f</opc>
 3074 <opr>ST7</opr>
 3075 </def>
 3076 </instruction>
 3077
 3078 <instruction>
 3079 <mnemonic>fst</mnemonic>
 3080 <class>X87</class>
 3081 <def>
 3082 <pfx>aso rexr rexx rexb</pfx>
 3083 <opc>d9 /mod=!11 /reg=2</opc>
 3084 <opr>Md</opr>
 3085 </def>
 3086 <def>
 3087 <pfx>aso rexr rexx rexb</pfx>
 3088 <opc>dd /mod=!11 /reg=2</opc>
 3089 <opr>Mq</opr>
 3090 </def>
 3091 <def>
 3092 <opc>dd /mod=11 /x87=10</opc>
 3093 <opr>ST0</opr>
 3094 </def>
 3095 <def>
 3096 <opc>dd /mod=11 /x87=11</opc>
 3097 <opr>ST1</opr>
 3098 </def>
 3099 <def>
 3100 <opc>dd /mod=11 /x87=12</opc>
 3101 <opr>ST2</opr>
 3102 </def>
 3103 <def>
 3104 <opc>dd /mod=11 /x87=13</opc>
 3105 <opr>ST3</opr>
 3106 </def>
 3107 <def>
 3108 <opc>dd /mod=11 /x87=14</opc>
 3109 <opr>ST4</opr>
 3110 </def>
 3111 <def>
 3112 <opc>dd /mod=11 /x87=15</opc>
 3113 <opr>ST5</opr>
 3114 </def>
 3115 <def>
 3116 <opc>dd /mod=11 /x87=16</opc>
 3117 <opr>ST6</opr>
 3118 </def>
 3119 <def>
 3120 <opc>dd /mod=11 /x87=17</opc>
 3121 <opr>ST7</opr>
 3122 </def>
 3123 </instruction>
 3124
 3125 <instruction>
 3126 <mnemonic>fnstcw</mnemonic>
 3127 <class>X87</class>
 3128 <def>
 3129 <pfx>aso rexr rexx rexb</pfx>
 3130 <opc>d9 /mod=!11 /reg=7</opc>
 3131 <opr>Mw</opr>
 3132 </def>
 3133 </instruction>
 3134
 3135 <instruction>
 3136 <mnemonic>fnstenv</mnemonic>
 3137 <class>X87</class>
 3138 <def>
 3139 <pfx>aso rexr rexx rexb</pfx>
 3140 <opc>d9 /mod=!11 /reg=6</opc>
 3141 <opr>M</opr>
 3142 </def>
 3143 </instruction>
 3144
 3145 <instruction>
 3146 <mnemonic>fnstsw</mnemonic>
 3147 <class>X87</class>
 3148 <def>
 3149 <pfx>aso rexr rexx rexb</pfx>
 3150 <opc>dd /mod=!11 /reg=7</opc>
 3151 <opr>Mw</opr>
 3152 </def>
 3153 <def>
 3154 <opc>df /mod=11 /x87=20</opc>
 3155 <opr>AX</opr>
 3156 </def>
 3157 </instruction>
 3158
 3159 <instruction>
 3160 <mnemonic>fsub</mnemonic>
 3161 <class>X87</class>
 3162 <def>
 3163 <pfx>aso rexr rexx rexb</pfx>
 3164 <opc>d8 /mod=!11 /reg=4</opc>
 3165 <opr>Md</opr>
 3166 </def>
 3167 <def>
 3168 <pfx>aso rexr rexx rexb</pfx>
 3169 <opc>dc /mod=!11 /reg=4</opc>
 3170 <opr>Mq</opr>
 3171 </def>
 3172 <def>
 3173 <opc>d8 /mod=11 /x87=20</opc>
 3174 <opr>ST0 ST0</opr>
 3175 </def>
 3176 <def>
 3177 <opc>d8 /mod=11 /x87=21</opc>
 3178 <opr>ST0 ST1</opr>
 3179 </def>
 3180 <def>
 3181 <opc>d8 /mod=11 /x87=22</opc>
 3182 <opr>ST0 ST2</opr>
 3183 </def>
 3184 <def>
 3185 <opc>d8 /mod=11 /x87=23</opc>
 3186 <opr>ST0 ST3</opr>
 3187 </def>
 3188 <def>
 3189 <opc>d8 /mod=11 /x87=24</opc>
 3190 <opr>ST0 ST4</opr>
 3191 </def>
 3192 <def>
 3193 <opc>d8 /mod=11 /x87=25</opc>
 3194 <opr>ST0 ST5</opr>
 3195 </def>
 3196 <def>
 3197 <opc>d8 /mod=11 /x87=26</opc>
 3198 <opr>ST0 ST6</opr>
 3199 </def>
 3200 <def>
 3201 <opc>d8 /mod=11 /x87=27</opc>
 3202 <opr>ST0 ST7</opr>
 3203 </def>
 3204 <def>
 3205 <opc>dc /mod=11 /x87=28</opc>
 3206 <opr>ST0 ST0</opr>
 3207 </def>
 3208 <def>
 3209 <opc>dc /mod=11 /x87=29</opc>
 3210 <opr>ST1 ST0</opr>
 3211 </def>
 3212 <def>
 3213 <opc>dc /mod=11 /x87=2a</opc>
 3214 <opr>ST2 ST0</opr>
 3215 </def>
 3216 <def>
 3217 <opc>dc /mod=11 /x87=2b</opc>
 3218 <opr>ST3 ST0</opr>
 3219 </def>
 3220 <def>
 3221 <opc>dc /mod=11 /x87=2c</opc>
 3222 <opr>ST4 ST0</opr>
 3223 </def>
 3224 <def>
 3225 <opc>dc /mod=11 /x87=2d</opc>
 3226 <opr>ST5 ST0</opr>
 3227 </def>
 3228 <def>
 3229 <opc>dc /mod=11 /x87=2e</opc>
 3230 <opr>ST6 ST0</opr>
 3231 </def>
 3232 <def>
 3233 <opc>dc /mod=11 /x87=2f</opc>
 3234 <opr>ST7 ST0</opr>
 3235 </def>
 3236 </instruction>
 3237
 3238 <instruction>
 3239 <mnemonic>fsubp</mnemonic>
 3240 <class>X87</class>
 3241 <def>
 3242 <opc>de /mod=11 /x87=28</opc>
 3243 <opr>ST0 ST0</opr>
 3244 </def>
 3245 <def>
 3246 <opc>de /mod=11 /x87=29</opc>
 3247 <opr>ST1 ST0</opr>
 3248 </def>
 3249 <def>
 3250 <opc>de /mod=11 /x87=2a</opc>
 3251 <opr>ST2 ST0</opr>
 3252 </def>
 3253 <def>
 3254 <opc>de /mod=11 /x87=2b</opc>
 3255 <opr>ST3 ST0</opr>
 3256 </def>
 3257 <def>
 3258 <opc>de /mod=11 /x87=2c</opc>
 3259 <opr>ST4 ST0</opr>
 3260 </def>
 3261 <def>
 3262 <opc>de /mod=11 /x87=2d</opc>
 3263 <opr>ST5 ST0</opr>
 3264 </def>
 3265 <def>
 3266 <opc>de /mod=11 /x87=2e</opc>
 3267 <opr>ST6 ST0</opr>
 3268 </def>
 3269 <def>
 3270 <opc>de /mod=11 /x87=2f</opc>
 3271 <opr>ST7 ST0</opr>
 3272 </def>
 3273 </instruction>
 3274
 3275 <instruction>
 3276 <mnemonic>fsubr</mnemonic>
 3277 <class>X87</class>
 3278 <def>
 3279 <pfx>aso rexr rexx rexb</pfx>
 3280 <opc>dc /mod=!11 /reg=5</opc>
 3281 <opr>Mq</opr>
 3282 </def>
 3283 <def>
 3284 <opc>d8 /mod=11 /x87=28</opc>
 3285 <opr>ST0 ST0</opr>
 3286 </def>
 3287 <def>
 3288 <opc>d8 /mod=11 /x87=29</opc>
 3289 <opr>ST0 ST1</opr>
 3290 </def>
 3291 <def>
 3292 <opc>d8 /mod=11 /x87=2a</opc>
 3293 <opr>ST0 ST2</opr>
 3294 </def>
 3295 <def>
 3296 <opc>d8 /mod=11 /x87=2b</opc>
 3297 <opr>ST0 ST3</opr>
 3298 </def>
 3299 <def>
 3300 <opc>d8 /mod=11 /x87=2c</opc>
 3301 <opr>ST0 ST4</opr>
 3302 </def>
 3303 <def>
 3304 <opc>d8 /mod=11 /x87=2d</opc>
 3305 <opr>ST0 ST5</opr>
 3306 </def>
 3307 <def>
 3308 <opc>d8 /mod=11 /x87=2e</opc>
 3309 <opr>ST0 ST6</opr>
 3310 </def>
 3311 <def>
 3312 <opc>d8 /mod=11 /x87=2f</opc>
 3313 <opr>ST0 ST7</opr>
 3314 </def>
 3315 <def>
 3316 <opc>dc /mod=11 /x87=20</opc>
 3317 <opr>ST0 ST0</opr>
 3318 </def>
 3319 <def>
 3320 <opc>dc /mod=11 /x87=21</opc>
 3321 <opr>ST1 ST0</opr>
 3322 </def>
 3323 <def>
 3324 <opc>dc /mod=11 /x87=22</opc>
 3325 <opr>ST2 ST0</opr>
 3326 </def>
 3327 <def>
 3328 <opc>dc /mod=11 /x87=23</opc>
 3329 <opr>ST3 ST0</opr>
 3330 </def>
 3331 <def>
 3332 <opc>dc /mod=11 /x87=24</opc>
 3333 <opr>ST4 ST0</opr>
 3334 </def>
 3335 <def>
 3336 <opc>dc /mod=11 /x87=25</opc>
 3337 <opr>ST5 ST0</opr>
 3338 </def>
 3339 <def>
 3340 <opc>dc /mod=11 /x87=26</opc>
 3341 <opr>ST6 ST0</opr>
 3342 </def>
 3343 <def>
 3344 <opc>dc /mod=11 /x87=27</opc>
 3345 <opr>ST7 ST0</opr>
 3346 </def>
 3347 <def>
 3348 <pfx>aso rexr rexx rexb</pfx>
 3349 <opc>d8 /mod=!11 /reg=5</opc>
 3350 <opr>Md</opr>
 3351 </def>
 3352 </instruction>
 3353
 3354 <instruction>
 3355 <mnemonic>fsubrp</mnemonic>
 3356 <class>X87</class>
 3357 <def>
 3358 <opc>de /mod=11 /x87=20</opc>
 3359 <opr>ST0 ST0</opr>
 3360 </def>
 3361 <def>
 3362 <opc>de /mod=11 /x87=21</opc>
 3363 <opr>ST1 ST0</opr>
 3364 </def>
 3365 <def>
 3366 <opc>de /mod=11 /x87=22</opc>
 3367 <opr>ST2 ST0</opr>
 3368 </def>
 3369 <def>
 3370 <opc>de /mod=11 /x87=23</opc>
 3371 <opr>ST3 ST0</opr>
 3372 </def>
 3373 <def>
 3374 <opc>de /mod=11 /x87=24</opc>
 3375 <opr>ST4 ST0</opr>
 3376 </def>
 3377 <def>
 3378 <opc>de /mod=11 /x87=25</opc>
 3379 <opr>ST5 ST0</opr>
 3380 </def>
 3381 <def>
 3382 <opc>de /mod=11 /x87=26</opc>
 3383 <opr>ST6 ST0</opr>
 3384 </def>
 3385 <def>
 3386 <opc>de /mod=11 /x87=27</opc>
 3387 <opr>ST7 ST0</opr>
 3388 </def>
 3389 </instruction>
 3390
 3391 <instruction>
 3392 <mnemonic>ftst</mnemonic>
 3393 <class>X87</class>
 3394 <def>
 3395 <opc>d9 /mod=11 /x87=24</opc>
 3396 </def>
 3397 </instruction>
 3398
 3399 <instruction>
 3400 <mnemonic>fucom</mnemonic>
 3401 <class>X87</class>
 3402 <def>
 3403 <opc>dd /mod=11 /x87=20</opc>
 3404 <opr>ST0</opr>
 3405 </def>
 3406 <def>
 3407 <opc>dd /mod=11 /x87=21</opc>
 3408 <opr>ST1</opr>
 3409 </def>
 3410 <def>
 3411 <opc>dd /mod=11 /x87=22</opc>
 3412 <opr>ST2</opr>
 3413 </def>
 3414 <def>
 3415 <opc>dd /mod=11 /x87=23</opc>
 3416 <opr>ST3</opr>
 3417 </def>
 3418 <def>
 3419 <opc>dd /mod=11 /x87=24</opc>
 3420 <opr>ST4</opr>
 3421 </def>
 3422 <def>
 3423 <opc>dd /mod=11 /x87=25</opc>
 3424 <opr>ST5</opr>
 3425 </def>
 3426 <def>
 3427 <opc>dd /mod=11 /x87=26</opc>
 3428 <opr>ST6</opr>
 3429 </def>
 3430 <def>
 3431 <opc>dd /mod=11 /x87=27</opc>
 3432 <opr>ST7</opr>
 3433 </def>
 3434 </instruction>
 3435
 3436 <instruction>
 3437 <mnemonic>fucomp</mnemonic>
 3438 <class>X87</class>
 3439 <def>
 3440 <opc>dd /mod=11 /x87=28</opc>
 3441 <opr>ST0</opr>
 3442 </def>
 3443 <def>
 3444 <opc>dd /mod=11 /x87=29</opc>
 3445 <opr>ST1</opr>
 3446 </def>
 3447 <def>
 3448 <opc>dd /mod=11 /x87=2a</opc>
 3449 <opr>ST2</opr>
 3450 </def>
 3451 <def>
 3452 <opc>dd /mod=11 /x87=2b</opc>
 3453 <opr>ST3</opr>
 3454 </def>
 3455 <def>
 3456 <opc>dd /mod=11 /x87=2c</opc>
 3457 <opr>ST4</opr>
 3458 </def>
 3459 <def>
 3460 <opc>dd /mod=11 /x87=2d</opc>
 3461 <opr>ST5</opr>
 3462 </def>
 3463 <def>
 3464 <opc>dd /mod=11 /x87=2e</opc>
 3465 <opr>ST6</opr>
 3466 </def>
 3467 <def>
 3468 <opc>dd /mod=11 /x87=2f</opc>
 3469 <opr>ST7</opr>
 3470 </def>
 3471 </instruction>
 3472
 3473 <instruction>
 3474 <mnemonic>fucompp</mnemonic>
 3475 <class>X87</class>
 3476 <def>
 3477 <opc>da /mod=11 /x87=29</opc>
 3478 </def>
 3479 </instruction>
 3480
 3481 <instruction>
 3482 <mnemonic>fxam</mnemonic>
 3483 <class>X87</class>
 3484 <def>
 3485 <opc>d9 /mod=11 /x87=25</opc>
 3486 </def>
 3487 </instruction>
 3488
 3489 <instruction>
 3490 <mnemonic>fxch</mnemonic>
 3491 <class>X87</class>
 3492 <def>
 3493 <opc>d9 /mod=11 /x87=08</opc>
 3494 <opr>ST0 ST0</opr>
 3495 </def>
 3496 <def>
 3497 <opc>d9 /mod=11 /x87=09</opc>
 3498 <opr>ST0 ST1</opr>
 3499 </def>
 3500 <def>
 3501 <opc>d9 /mod=11 /x87=0a</opc>
 3502 <opr>ST0 ST2</opr>
 3503 </def>
 3504 <def>
 3505 <opc>d9 /mod=11 /x87=0b</opc>
 3506 <opr>ST0 ST3</opr>
 3507 </def>
 3508 <def>
 3509 <opc>d9 /mod=11 /x87=0c</opc>
 3510 <opr>ST0 ST4</opr>
 3511 </def>
 3512 <def>
 3513 <opc>d9 /mod=11 /x87=0d</opc>
 3514 <opr>ST0 ST5</opr>
 3515 </def>
 3516 <def>
 3517 <opc>d9 /mod=11 /x87=0e</opc>
 3518 <opr>ST0 ST6</opr>
 3519 </def>
 3520 <def>
 3521 <opc>d9 /mod=11 /x87=0f</opc>
 3522 <opr>ST0 ST7</opr>
 3523 </def>
 3524 </instruction>
 3525
 3526 <instruction>
 3527 <mnemonic>fxch4</mnemonic>
 3528 <class>X87</class>
 3529 <def>
 3530 <opc>dd /mod=11 /x87=08</opc>
 3531 <opr>ST0</opr>
 3532 </def>
 3533 <def>
 3534 <opc>dd /mod=11 /x87=09</opc>
 3535 <opr>ST1</opr>
 3536 </def>
 3537 <def>
 3538 <opc>dd /mod=11 /x87=0a</opc>
 3539 <opr>ST2</opr>
 3540 </def>
 3541 <def>
 3542 <opc>dd /mod=11 /x87=0b</opc>
 3543 <opr>ST3</opr>
 3544 </def>
 3545 <def>
 3546 <opc>dd /mod=11 /x87=0c</opc>
 3547 <opr>ST4</opr>
 3548 </def>
 3549 <def>
 3550 <opc>dd /mod=11 /x87=0d</opc>
 3551 <opr>ST5</opr>
 3552 </def>
 3553 <def>
 3554 <opc>dd /mod=11 /x87=0e</opc>
 3555 <opr>ST6</opr>
 3556 </def>
 3557 <def>
 3558 <opc>dd /mod=11 /x87=0f</opc>
 3559 <opr>ST7</opr>
 3560 </def>
 3561 </instruction>
 3562
 3563 <instruction>
 3564 <mnemonic>fxch7</mnemonic>
 3565 <class>X87</class>
 3566 <def>
 3567 <opc>df /mod=11 /x87=08</opc>
 3568 <opr>ST0</opr>
 3569 </def>
 3570 <def>
 3571 <opc>df /mod=11 /x87=09</opc>
 3572 <opr>ST1</opr>
 3573 </def>
 3574 <def>
 3575 <opc>df /mod=11 /x87=0a</opc>
 3576 <opr>ST2</opr>
 3577 </def>
 3578 <def>
 3579 <opc>df /mod=11 /x87=0b</opc>
 3580 <opr>ST3</opr>
 3581 </def>
 3582 <def>
 3583 <opc>df /mod=11 /x87=0c</opc>
 3584 <opr>ST4</opr>
 3585 </def>
 3586 <def>
 3587 <opc>df /mod=11 /x87=0d</opc>
 3588 <opr>ST5</opr>
 3589 </def>
 3590 <def>
 3591 <opc>df /mod=11 /x87=0e</opc>
 3592 <opr>ST6</opr>
 3593 </def>
 3594 <def>
 3595 <opc>df /mod=11 /x87=0f</opc>
 3596 <opr>ST7</opr>
 3597 </def>
 3598 </instruction>
 3599
 3600 <instruction>
 3601 <mnemonic>fxrstor</mnemonic>
 3602 <def>
 3603 <pfx>aso rexw rexr rexx rexb</pfx>
 3604 <opc>0f ae /mod=11 /reg=1</opc>
 3605 <opr>M</opr>
 3606 </def>
 3607 </instruction>
 3608
 3609 <instruction>
 3610 <mnemonic>fxsave</mnemonic>
 3611 <def>
 3612 <pfx>aso rexw rexr rexx rexb</pfx>
 3613 <opc>0f ae /mod=11 /reg=0</opc>
 3614 <opr>M</opr>
 3615 </def>
 3616 </instruction>
 3617
 3618 <instruction>
 3619 <mnemonic>fpxtract</mnemonic>
 3620 <class>X87</class>
 3621 <def>
 3622 <opc>d9 /mod=11 /x87=34</opc>
 3623 </def>
 3624 </instruction>
 3625
 3626 <instruction>
 3627 <mnemonic>fyl2x</mnemonic>
 3628 <class>X87</class>
 3629 <def>
 3630 <opc>d9 /mod=11 /x87=31</opc>
 3631 </def>
 3632 </instruction>
 3633
 3634 <instruction>
 3635 <mnemonic>fyl2xp1</mnemonic>
 3636 <class>X87</class>
 3637 <def>
 3638 <opc>d9 /mod=11 /x87=39</opc>
 3639 </def>
 3640 </instruction>
 3641
 3642 <instruction>
 3643 <mnemonic>hlt</mnemonic>
 3644 <def>
 3645 <opc>f4</opc>
 3646 </def>
 3647 </instruction>
 3648
 3649 <instruction>
 3650 <mnemonic>idiv</mnemonic>
 3651 <def>
 3652 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3653 <opc>f7 /reg=7</opc>
 3654 <opr>Ev</opr>
 3655 </def>
 3656 <def>
 3657 <pfx>aso rexw rexr rexx rexb</pfx>
 3658 <opc>f6 /reg=7</opc>
 3659 <opr>Eb</opr>
 3660 </def>
 3661 </instruction>
 3662
 3663 <instruction>
 3664 <mnemonic>in</mnemonic>
 3665 <def>
 3666 <opc>e4</opc>
 3667 <opr>AL Ib</opr>
 3668 </def>
 3669 <def>
 3670 <pfx>oso</pfx>
 3671 <opc>e5</opc>
 3672 <opr>eAX Ib</opr>
 3673 </def>
 3674 <def>
 3675 <opc>ec</opc>
 3676 <opr>AL DX</opr>
 3677 </def>
 3678 <def>
 3679 <pfx>oso</pfx>
 3680 <opc>ed</opc>
 3681 <opr>eAX DX</opr>
 3682 </def>
 3683 </instruction>
 3684
 3685 <instruction>
 3686 <mnemonic>imul</mnemonic>
 3687 <def>
 3688 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3689 <opc>0f af</opc>
 3690 <opr>Gv Ev</opr>
 3691 </def>
 3692 <def>
 3693 <pfx>aso rexw rexr rexx rexb</pfx>
 3694 <opc>f6 /reg=5</opc>
 3695 <opr>Eb</opr>
 3696 </def>
 3697 <def>
 3698 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3699 <opc>f7 /reg=5</opc>
 3700 <opr>Ev</opr>
 3701 </def>
 3702 <def>
 3703 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3704 <opc>69</opc>
 3705 <opr>Gv Ev Iz</opr>
 3706 <syn>sext</syn>
 3707 </def>
 3708 <def>
 3709 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3710 <opc>6b</opc>
 3711 <opr>Gv Ev Ib</opr>
 3712 <syn>sext</syn>
 3713 </def>
 3714 </instruction>
 3715
 3716 <instruction>
 3717 <mnemonic>inc</mnemonic>
 3718 <def>
 3719 <pfx>oso</pfx>
 3720 <opc>40</opc>
 3721 <opr>eAX</opr>
 3722 </def>
 3723 <def>
 3724 <pfx>oso</pfx>
 3725 <opc>41</opc>
 3726 <opr>eCX</opr>
 3727 </def>
 3728 <def>
 3729 <pfx>oso</pfx>
 3730 <opc>42</opc>
 3731 <opr>eDX</opr>
 3732 </def>
 3733 <def>
 3734 <pfx>oso</pfx>
 3735 <opc>43</opc>
 3736 <opr>eBX</opr>
 3737 </def>
 3738 <def>
 3739 <pfx>oso</pfx>
 3740 <opc>44</opc>
 3741 <opr>eSP</opr>
 3742 </def>
 3743 <def>
 3744 <pfx>oso</pfx>
 3745 <opc>45</opc>
 3746 <opr>eBP</opr>
 3747 </def>
 3748 <def>
 3749 <pfx>oso</pfx>
 3750 <opc>46</opc>
 3751 <opr>eSI</opr>
 3752 </def>
 3753 <def>
 3754 <pfx>oso</pfx>
 3755 <opc>47</opc>
 3756 <opr>eDI</opr>
 3757 </def>
 3758 <def>
 3759 <pfx>aso oso rexw rexr rexx rexb</pfx>
 3760 <opc>ff /reg=0</opc>
 3761 <opr>Ev</opr>
 3762 </def>
 3763 <def>
 3764 <pfx>aso rexw rexr rexx rexb</pfx>
 3765 <opc>fe /reg=0</opc>
 3766 <opr>Eb</opr>
 3767 </def>
 3768 </instruction>
 3769
 3770 <instruction>
 3771 <mnemonic>insb</mnemonic>
 3772 <def>
 3773 <opc>6c</opc>
 3774 </def>
 3775 </instruction>
 3776
 3777 <instruction>
 3778 <mnemonic>insw</mnemonic>
 3779 <def>
 3780 <pfx>oso</pfx>
 3781 <opc>6d /o=16</opc>
 3782 </def>
 3783 </instruction>
 3784
 3785 <instruction>
 3786 <mnemonic>insd</mnemonic>
 3787 <def>
 3788 <pfx>oso</pfx>
 3789 <opc>6d /o=32</opc>
 3790 </def>
 3791 </instruction>
 3792
 3793 <instruction>
 3794 <mnemonic>int1</mnemonic>
 3795 <def>
 3796 <opc>f1</opc>
 3797 </def>
 3798 </instruction>
 3799
 3800 <instruction>
 3801 <mnemonic>int3</mnemonic>
 3802 <def>
 3803 <opc>cc</opc>
 3804 </def>
 3805 </instruction>
 3806
 3807 <instruction>
 3808 <mnemonic>int</mnemonic>
 3809 <def>
 3810 <opc>cd</opc>
 3811 <opr>Ib</opr>
 3812 </def>
 3813 </instruction>
 3814
 3815 <instruction>
 3816 <mnemonic>into</mnemonic>
 3817 <def>
 3818 <opc>ce</opc>
 3819 <mode>inv64</mode>
 3820 </def>
 3821 </instruction>
 3822
 3823 <instruction>
 3824 <mnemonic>invd</mnemonic>
 3825 <def>
 3826 <opc>0f 08</opc>
 3827 </def>
 3828 </instruction>
 3829
 3830 <instruction>
 3831 <mnemonic>invept</mnemonic>
 3832 <vendor>intel</vendor>
 3833 <def>
 3834 <opc>sse66 0f 38 80 /m=32</opc>
 3835 <opr>Gd Mo</opr>
 3836 </def>
 3837 <def>
 3838 <opc>sse66 0f 38 80 /m=64</opc>
 3839 <opr>Gq Mo</opr>
 3840 </def>
 3841 </instruction>
 3842
 3843 <instruction>
 3844 <mnemonic>invlpg</mnemonic>
 3845 <def>
 3846 <pfx>aso rexr rexx rexb</pfx>
 3847 <opc>0f 01 /reg=7 /mod=!11</opc>
 3848 <opr>M</opr>
 3849 </def>
 3850 </instruction>
 3851
 3852 <instruction>
 3853 <mnemonic>invlpga</mnemonic>
 3854 <vendor>amd</vendor>
 3855 <def>
 3856 <opc>0f 01 /reg=3 /mod=11 /rm=7</opc>
 3857 </def>
 3858 </instruction>
 3859
 3860 <instruction>
 3861 <mnemonic>invvpid</mnemonic>
 3862 <vendor>intel</vendor>
 3863 <def>
 3864 <opc>sse66 0f 38 81 /m=32</opc>
 3865 <opr>Gd Mo</opr>
 3866 </def>
 3867 <def>
 3868 <opc>sse66 0f 38 81 /m=64</opc>
 3869 <opr>Gq Mo</opr>
 3870 </def>
 3871 </instruction>
 3872
 3873 <instruction>
 3874 <mnemonic>iretw</mnemonic>
 3875 <def>
 3876 <pfx>oso rexw</pfx>
 3877 <opc>cf /o=16</opc>
 3878 </def>
 3879 </instruction>
 3880
 3881 <instruction>
 3882 <mnemonic>iretd</mnemonic>
 3883 <def>
 3884 <pfx>oso rexw</pfx>
 3885 <opc>cf /o=32</opc>
 3886 </def>
 3887 </instruction>
 3888
 3889 <instruction>
 3890 <mnemonic>iretq</mnemonic>
 3891 <def>
 3892 <pfx>oso rexw</pfx>
 3893 <opc>cf /o=64</opc>
 3894 </def>
 3895 </instruction>
 3896
 3897 <instruction>
 3898 <mnemonic>jo</mnemonic>
 3899 <def>
 3900 <opc>70</opc>
 3901 <opr>Jb</opr>
 3902 </def>
 3903 <def>
 3904 <pfx>oso</pfx>
 3905 <opc>0f 80</opc>
 3906 <opr>Jz</opr>
 3907 <mode>def64 depM</mode>
 3908 </def>
 3909 </instruction>
 3910
 3911 <instruction>
 3912 <mnemonic>jno</mnemonic>
 3913 <def>
 3914 <opc>71</opc>
 3915 <opr>Jb</opr>
 3916 </def>
 3917 <def>
 3918 <pfx>oso</pfx>
 3919 <opc>0f 81</opc>
 3920 <opr>Jz</opr>
 3921 <mode>def64 depM</mode>
 3922 </def>
 3923 </instruction>
 3924
 3925 <instruction>
 3926 <mnemonic>jb</mnemonic>
 3927 <def>
 3928 <opc>72</opc>
 3929 <opr>Jb</opr>
 3930 </def>
 3931 <def>
 3932 <pfx>oso</pfx>
 3933 <opc>0f 82</opc>
 3934 <opr>Jz</opr>
 3935 <mode>def64 depM</mode>
 3936 </def>
 3937 </instruction>
 3938
 3939 <instruction>
 3940 <mnemonic>jae</mnemonic>
 3941 <def>
 3942 <opc>73</opc>
 3943 <opr>Jb</opr>
 3944 </def>
 3945 <def>
 3946 <pfx>oso</pfx>
 3947 <opc>0f 83</opc>
 3948 <opr>Jz</opr>
 3949 <mode>def64 depM</mode>
 3950 </def>
 3951 </instruction>
 3952
 3953 <instruction>
 3954 <mnemonic>jz</mnemonic>
 3955 <def>
 3956 <opc>74</opc>
 3957 <opr>Jb</opr>
 3958 </def>
 3959 <def>
 3960 <pfx>oso</pfx>
 3961 <opc>0f 84</opc>
 3962 <opr>Jz</opr>
 3963 <mode>def64 depM</mode>
 3964 </def>
 3965 </instruction>
 3966
 3967 <instruction>
 3968 <mnemonic>jnz</mnemonic>
 3969 <def>
 3970 <opc>75</opc>
 3971 <opr>Jb</opr>
 3972 </def>
 3973 <def>
 3974 <pfx>oso</pfx>
 3975 <opc>0f 85</opc>
 3976 <opr>Jz</opr>
 3977 <mode>def64 depM</mode>
 3978 </def>
 3979 </instruction>
 3980
 3981 <instruction>
 3982 <mnemonic>jbe</mnemonic>
 3983 <def>
 3984 <opc>76</opc>
 3985 <opr>Jb</opr>
 3986 </def>
 3987 <def>
 3988 <pfx>oso</pfx>
 3989 <opc>0f 86</opc>
 3990 <opr>Jz</opr>
 3991 <mode>def64 depM</mode>
 3992 </def>
 3993 </instruction>
 3994
 3995 <instruction>
 3996 <mnemonic>ja</mnemonic>
 3997 <def>
 3998 <opc>77</opc>
 3999 <opr>Jb</opr>
 4000 </def>
 4001 <def>
 4002 <pfx>oso</pfx>
 4003 <opc>0f 87</opc>
 4004 <opr>Jz</opr>
 4005 <mode>def64 depM</mode>
 4006 </def>
 4007 </instruction>
 4008
 4009 <instruction>
 4010 <mnemonic>js</mnemonic>
 4011 <def>
 4012 <opc>78</opc>
 4013 <opr>Jb</opr>
 4014 </def>
 4015 <def>
 4016 <pfx>oso</pfx>
 4017 <opc>0f 88</opc>
 4018 <opr>Jz</opr>
 4019 <mode>def64 depM</mode>
 4020 </def>
 4021 </instruction>
 4022
 4023 <instruction>
 4024 <mnemonic>jns</mnemonic>
 4025 <def>
 4026 <opc>79</opc>
 4027 <opr>Jb</opr>
 4028 </def>
 4029 <def>
 4030 <pfx>oso</pfx>
 4031 <opc>0f 89</opc>
 4032 <opr>Jz</opr>
 4033 <mode>def64 depM</mode>
 4034 </def>
 4035 </instruction>
 4036
 4037 <instruction>
 4038 <mnemonic>jp</mnemonic>
 4039 <def>
 4040 <opc>7a</opc>
 4041 <opr>Jb</opr>
 4042 </def>
 4043 <def>
 4044 <pfx>oso</pfx>
 4045 <opc>0f 8a</opc>
 4046 <opr>Jz</opr>
 4047 <mode>def64 depM</mode>
 4048 </def>
 4049 </instruction>
 4050
 4051 <instruction>
 4052 <mnemonic>jnp</mnemonic>
 4053 <def>
 4054 <opc>7b</opc>
 4055 <opr>Jb</opr>
 4056 </def>
 4057 <def>
 4058 <pfx>oso</pfx>
 4059 <opc>0f 8b</opc>
 4060 <opr>Jz</opr>
 4061 <mode>def64 depM</mode>
 4062 </def>
 4063 </instruction>
 4064
 4065 <instruction>
 4066 <mnemonic>jl</mnemonic>
 4067 <def>
 4068 <opc>7c</opc>
 4069 <opr>Jb</opr>
 4070 </def>
 4071 <def>
 4072 <pfx>oso</pfx>
 4073 <opc>0f 8c</opc>
 4074 <opr>Jz</opr>
 4075 <mode>def64 depM</mode>
 4076 </def>
 4077 </instruction>
 4078
 4079 <instruction>
 4080 <mnemonic>jge</mnemonic>
 4081 <def>
 4082 <opc>7d</opc>
 4083 <opr>Jb</opr>
 4084 </def>
 4085 <def>
 4086 <pfx>oso</pfx>
 4087 <opc>0f 8d</opc>
 4088 <opr>Jz</opr>
 4089 <mode>def64 depM</mode>
 4090 </def>
 4091 </instruction>
 4092
 4093 <instruction>
 4094 <mnemonic>jle</mnemonic>
 4095 <def>
 4096 <opc>7e</opc>
 4097 <opr>Jb</opr>
 4098 </def>
 4099 <def>
 4100 <pfx>oso</pfx>
 4101 <opc>0f 8e</opc>
 4102 <opr>Jz</opr>
 4103 <mode>def64 depM</mode>
 4104 </def>
 4105 </instruction>
 4106
 4107 <instruction>
 4108 <mnemonic>jg</mnemonic>
 4109 <def>
 4110 <opc>7f</opc>
 4111 <opr>Jb</opr>
 4112 </def>
 4113 <def>
 4114 <pfx>oso</pfx>
 4115 <opc>0f 8f</opc>
 4116 <opr>Jz</opr>
 4117 <mode>def64 depM</mode>
 4118 </def>
 4119 </instruction>
 4120
 4121 <instruction>
 4122 <mnemonic>jcxz</mnemonic>
 4123 <def>
 4124 <pfx>aso</pfx>
 4125 <opc>e3 /a=16</opc>
 4126 <opr>Jb</opr>
 4127 </def>
 4128 </instruction>
 4129
 4130 <instruction>
 4131 <mnemonic>jecxz</mnemonic>
 4132 <def>
 4133 <pfx>aso</pfx>
 4134 <opc>e3 /a=32</opc>
 4135 <opr>Jb</opr>
 4136 </def>
 4137 </instruction>
 4138
 4139 <instruction>
 4140 <mnemonic>jrcxz</mnemonic>
 4141 <def>
 4142 <pfx>aso</pfx>
 4143 <opc>e3 /a=64</opc>
 4144 <opr>Jb</opr>
 4145 </def>
 4146 </instruction>
 4147
 4148 <instruction>
 4149 <mnemonic>jmp</mnemonic>
 4150 <def>
 4151 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4152 <opc>ff /reg=4</opc>
 4153 <opr>Ev</opr>
 4154 <mode>def64 depM</mode>
 4155 </def>
 4156 <def>
 4157 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4158 <opc>ff /reg=5</opc>
 4159 <opr>Ep</opr>
 4160 </def>
 4161 <def>
 4162 <pfx>oso</pfx>
 4163 <opc>e9</opc>
 4164 <opr>Jz</opr>
 4165 <mode>def64 depM</mode>
 4166 <syn>cast</syn>
 4167 </def>
 4168 <def>
 4169 <opc>ea</opc>
 4170 <opr>Ap</opr>
 4171 <mode>inv64</mode>
 4172 </def>
 4173 <def>
 4174 <opc>eb</opc>
 4175 <opr>Jb</opr>
 4176 </def>
 4177 </instruction>
 4178
 4179 <instruction>
 4180 <mnemonic>lahf</mnemonic>
 4181 <def>
 4182 <opc>9f</opc>
 4183 </def>
 4184 </instruction>
 4185
 4186 <instruction>
 4187 <mnemonic>lar</mnemonic>
 4188 <def>
 4189 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4190 <opc>0f 02</opc>
 4191 <opr>Gv Ew</opr>
 4192 </def>
 4193 </instruction>
 4194
 4195 <instruction>
 4196 <mnemonic>lddqu</mnemonic>
 4197 <def>
 4198 <pfx>aso rexr rexx rexb</pfx>
 4199 <opc>ssef2 0f f0</opc>
 4200 <opr>V M</opr>
 4201 </def>
 4202 </instruction>
 4203
 4204 <instruction>
 4205 <mnemonic>ldmxcsr</mnemonic>
 4206 <def>
 4207 <pfx>aso rexw rexr rexx rexb</pfx>
 4208 <opc>0f ae /reg=2 /mod=11</opc>
 4209 <opr>Md</opr>
 4210 </def>
 4211 </instruction>
 4212
 4213 <instruction>
 4214 <mnemonic>lds</mnemonic>
 4215 <def>
 4216 <pfx>aso oso</pfx>
 4217 <opc>c5</opc>
 4218 <opr>Gv M</opr>
 4219 <mode>inv64</mode>
 4220 </def>
 4221 </instruction>
 4222
 4223 <instruction>
 4224 <mnemonic>lea</mnemonic>
 4225 <def>
 4226 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4227 <opc>8d</opc>
 4228 <opr>Gv M</opr>
 4229 </def>
 4230 </instruction>
 4231
 4232 <instruction>
 4233 <mnemonic>les</mnemonic>
 4234 <def>
 4235 <pfx>aso oso</pfx>
 4236 <opc>c4</opc>
 4237 <opr>Gv M</opr>
 4238 <mode>inv64</mode>
 4239 </def>
 4240 </instruction>
 4241
 4242 <instruction>
 4243 <mnemonic>lfs</mnemonic>
 4244 <def>
 4245 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4246 <opc>0f b4</opc>
 4247 <opr>Gz M</opr>
 4248 </def>
 4249 </instruction>
 4250
 4251 <instruction>
 4252 <mnemonic>lgs</mnemonic>
 4253 <def>
 4254 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4255 <opc>0f b5</opc>
 4256 <opr>Gz M</opr>
 4257 </def>
 4258 </instruction>
 4259
 4260 <instruction>
 4261 <mnemonic>lidt</mnemonic>
 4262 <def>
 4263 <pfx>aso rexr rexx rexb</pfx>
 4264 <opc>0f 01 /reg=3 /mod=!11</opc>
 4265 <opr>M</opr>
 4266 </def>
 4267 </instruction>
 4268
 4269 <instruction>
 4270 <mnemonic>lss</mnemonic>
 4271 <def>
 4272 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4273 <opc>0f b2</opc>
 4274 <opr>Gz M</opr>
 4275 </def>
 4276 </instruction>
 4277
 4278 <instruction>
 4279 <mnemonic>leave</mnemonic>
 4280 <def>
 4281 <opc>c9</opc>
 4282 </def>
 4283 </instruction>
 4284
 4285 <instruction>
 4286 <mnemonic>lfence</mnemonic>
 4287 <def>
 4288 <opc>0f ae /reg=5 /mod=11 /rm=0</opc>
 4289 </def>
 4290 <def>
 4291 <opc>0f ae /reg=5 /mod=11 /rm=1</opc>
 4292 </def>
 4293 <def>
 4294 <opc>0f ae /reg=5 /mod=11 /rm=2</opc>
 4295 </def>
 4296 <def>
 4297 <opc>0f ae /reg=5 /mod=11 /rm=3</opc>
 4298 </def>
 4299 <def>
 4300 <opc>0f ae /reg=5 /mod=11 /rm=4</opc>
 4301 </def>
 4302 <def>
 4303 <opc>0f ae /reg=5 /mod=11 /rm=5</opc>
 4304 </def>
 4305 <def>
 4306 <opc>0f ae /reg=5 /mod=11 /rm=6</opc>
 4307 </def>
 4308 <def>
 4309 <opc>0f ae /reg=5 /mod=11 /rm=7</opc>
 4310 </def>
 4311 </instruction>
 4312
 4313 <instruction>
 4314 <mnemonic>lgdt</mnemonic>
 4315 <def>
 4316 <pfx>aso rexr rexx rexb</pfx>
 4317 <opc>0f 01 /reg=2 /mod=!11</opc>
 4318 <opr>M</opr>
 4319 </def>
 4320 </instruction>
 4321
 4322 <instruction>
 4323 <mnemonic>lldt</mnemonic>
 4324 <def>
 4325 <pfx>aso rexr rexx rexb</pfx>
 4326 <opc>0f 00 /reg=2</opc>
 4327 <opr>Ew</opr>
 4328 </def>
 4329 </instruction>
 4330
 4331 <instruction>
 4332 <mnemonic>lmsw</mnemonic>
 4333 <def>
 4334 <pfx>aso rexr rexx rexb</pfx>
 4335 <opc>0f 01 /reg=6 /mod=!11</opc>
 4336 <opr>Ew</opr>
 4337 </def>
 4338 </instruction>
 4339
 4340 <instruction>
 4341 <mnemonic>lock</mnemonic>
 4342 <def>
 4343 <opc>f0</opc>
 4344 </def>
 4345 </instruction>
 4346
 4347 <instruction>
 4348 <mnemonic>lodsb</mnemonic>
 4349 <def>
 4350 <pfx>seg</pfx>
 4351 <opc>ac</opc>
 4352 </def>
 4353 </instruction>
 4354
 4355 <instruction>
 4356 <mnemonic>lodsw</mnemonic>
 4357 <def>
 4358 <pfx>seg oso rexw</pfx>
 4359 <opc>ad /o=16</opc>
 4360 </def>
 4361 </instruction>
 4362
 4363 <instruction>
 4364 <mnemonic>lodsd</mnemonic>
 4365 <def>
 4366 <pfx>seg oso rexw</pfx>
 4367 <opc>ad /o=32</opc>
 4368 </def>
 4369 </instruction>
 4370
 4371 <instruction>
 4372 <mnemonic>lodsq</mnemonic>
 4373 <def>
 4374 <pfx>seg oso rexw</pfx>
 4375 <opc>ad /o=64</opc>
 4376 </def>
 4377 </instruction>
 4378
 4379 <instruction>
 4380 <mnemonic>loopnz</mnemonic>
 4381 <def>
 4382 <opc>e0</opc>
 4383 <opr>Jb</opr>
 4384 </def>
 4385 </instruction>
 4386
 4387 <instruction>
 4388 <mnemonic>loope</mnemonic>
 4389 <def>
 4390 <opc>e1</opc>
 4391 <opr>Jb</opr>
 4392 </def>
 4393 </instruction>
 4394
 4395 <instruction>
 4396 <mnemonic>loop</mnemonic>
 4397 <def>
 4398 <opc>e2</opc>
 4399 <opr>Jb</opr>
 4400 </def>
 4401 </instruction>
 4402
 4403 <instruction>
 4404 <mnemonic>lsl</mnemonic>
 4405 <def>
 4406 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4407 <opc>0f 03</opc>
 4408 <opr>Gv Ew</opr>
 4409 </def>
 4410 </instruction>
 4411
 4412 <instruction>
 4413 <mnemonic>ltr</mnemonic>
 4414 <def>
 4415 <pfx>aso rexr rexx rexb</pfx>
 4416 <opc>0f 00 /reg=3</opc>
 4417 <opr>Ew</opr>
 4418 </def>
 4419 </instruction>
 4420
 4421 <instruction>
 4422 <mnemonic>maskmovq</mnemonic>
 4423 <def>
 4424 <pfx>aso rexr rexx rexb</pfx>
 4425 <opc>0f f7</opc>
 4426 <opr>P PR</opr>
 4427 </def>
 4428 </instruction>
 4429
 4430 <instruction>
 4431 <mnemonic>maxpd</mnemonic>
 4432 <def>
 4433 <pfx>aso rexr rexx rexb</pfx>
 4434 <opc>sse66 0f 5f</opc>
 4435 <opr>V W</opr>
 4436 </def>
 4437 </instruction>
 4438
 4439 <instruction>
 4440 <mnemonic>maxps</mnemonic>
 4441 <def>
 4442 <pfx>aso rexr rexx rexb</pfx>
 4443 <opc>0f 5f</opc>
 4444 <opr>V W</opr>
 4445 </def>
 4446 </instruction>
 4447
 4448 <instruction>
 4449 <mnemonic>maxsd</mnemonic>
 4450 <def>
 4451 <pfx>aso rexr rexx rexb</pfx>
 4452 <opc>ssef2 0f 5f</opc>
 4453 <opr>V W</opr>
 4454 </def>
 4455 </instruction>
 4456
 4457 <instruction>
 4458 <mnemonic>maxss</mnemonic>
 4459 <def>
 4460 <pfx>aso rexr rexx rexb</pfx>
 4461 <opc>ssef3 0f 5f</opc>
 4462 <opr>V W</opr>
 4463 </def>
 4464 </instruction>
 4465
 4466 <instruction>
 4467 <mnemonic>mfence</mnemonic>
 4468 <def>
 4469 <opc>0f ae /reg=6 /mod=11 /rm=0</opc>
 4470 </def>
 4471 <def>
 4472 <opc>0f ae /reg=6 /mod=11 /rm=1</opc>
 4473 </def>
 4474 <def>
 4475 <opc>0f ae /reg=6 /mod=11 /rm=2</opc>
 4476 </def>
 4477 <def>
 4478 <opc>0f ae /reg=6 /mod=11 /rm=3</opc>
 4479 </def>
 4480 <def>
 4481 <opc>0f ae /reg=6 /mod=11 /rm=4</opc>
 4482 </def>
 4483 <def>
 4484 <opc>0f ae /reg=6 /mod=11 /rm=5</opc>
 4485 </def>
 4486 <def>
 4487 <opc>0f ae /reg=6 /mod=11 /rm=6</opc>
 4488 </def>
 4489 <def>
 4490 <opc>0f ae /reg=6 /mod=11 /rm=7</opc>
 4491 </def>
 4492 </instruction>
 4493
 4494 <instruction>
 4495 <mnemonic>minpd</mnemonic>
 4496 <def>
 4497 <pfx>aso rexr rexx rexb</pfx>
 4498 <opc>sse66 0f 5d</opc>
 4499 <opr>V W</opr>
 4500 </def>
 4501 </instruction>
 4502
 4503 <instruction>
 4504 <mnemonic>minps</mnemonic>
 4505 <def>
 4506 <pfx>aso rexr rexx rexb</pfx>
 4507 <opc>0f 5d</opc>
 4508 <opr>V W</opr>
 4509 </def>
 4510 </instruction>
 4511
 4512 <instruction>
 4513 <mnemonic>minsd</mnemonic>
 4514 <def>
 4515 <pfx>aso rexr rexx rexb</pfx>
 4516 <opc>ssef2 0f 5d</opc>
 4517 <opr>V W</opr>
 4518 </def>
 4519 </instruction>
 4520
 4521 <instruction>
 4522 <mnemonic>minss</mnemonic>
 4523 <def>
 4524 <pfx>aso rexr rexx rexb</pfx>
 4525 <opc>ssef3 0f 5d</opc>
 4526 <opr>V W</opr>
 4527 </def>
 4528 </instruction>
 4529
 4530 <instruction>
 4531 <mnemonic>monitor</mnemonic>
 4532 <def>
 4533 <opc>0f 01 /reg=1 /mod=11 /rm=0</opc>
 4534 </def>
 4535 </instruction>
 4536
 4537 <instruction>
 4538 <mnemonic>montmul</mnemonic>
 4539 <def>
 4540 <opc>0f a6 /mod=11 /rm=0 /reg=0</opc>
 4541 </def>
 4542 </instruction>
 4543
 4544 <instruction>
 4545 <mnemonic>mov</mnemonic>
 4546 <def>
 4547 <pfx>aso rexw rexr rexx rexb</pfx>
 4548 <opc>c6 /reg=0</opc>
 4549 <opr>Eb Ib</opr>
 4550 </def>
 4551 <def>
 4552 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4553 <opc>c7 /reg=0</opc>
 4554 <opr>Ev Iz</opr>
 4555 </def>
 4556 <def>
 4557 <pfx>aso rexr rexx rexb</pfx>
 4558 <opc>88</opc>
 4559 <opr>Eb Gb</opr>
 4560 </def>
 4561 <def>
 4562 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4563 <opc>89</opc>
 4564 <opr>Ev Gv</opr>
 4565 </def>
 4566 <def>
 4567 <pfx>aso rexr rexx rexb</pfx>
 4568 <opc>8a</opc>
 4569 <opr>Gb Eb</opr>
 4570 </def>
 4571 <def>
 4572 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4573 <opc>8b</opc>
 4574 <opr>Gv Ev</opr>
 4575 </def>
 4576 <def>
 4577 <pfx>aso oso rexr rexx rexb</pfx>
 4578 <opc>8c</opc>
 4579 <opr>Ev S</opr>
 4580 </def>
 4581 <def>
 4582 <pfx>aso oso rexr rexx rexb</pfx>
 4583 <opc>8e</opc>
 4584 <opr>S Ev</opr>
 4585 </def>
 4586 <def>
 4587 <opc>a0</opc>
 4588 <opr>AL Ob</opr>
 4589 </def>
 4590 <def>
 4591 <pfx>aso oso rexw</pfx>
 4592 <opc>a1</opc>
 4593 <opr>rAX Ov</opr>
 4594 </def>
 4595 <def>
 4596 <opc>a2</opc>
 4597 <opr>Ob AL</opr>
 4598 </def>
 4599 <def>
 4600 <pfx>aso oso rexw</pfx>
 4601 <opc>a3</opc>
 4602 <opr>Ov rAX</opr>
 4603 </def>
 4604 <def>
 4605 <pfx>rexb</pfx>
 4606 <opc>b0</opc>
 4607 <opr>ALr8b Ib</opr>
 4608 </def>
 4609 <def>
 4610 <pfx>rexb</pfx>
 4611 <opc>b1</opc>
 4612 <opr>CLr9b Ib</opr>
 4613 </def>
 4614 <def>
 4615 <pfx>rexb</pfx>
 4616 <opc>b2</opc>
 4617 <opr>DLr10b Ib</opr>
 4618 </def>
 4619 <def>
 4620 <pfx>rexb</pfx>
 4621 <opc>b3</opc>
 4622 <opr>BLr11b Ib</opr>
 4623 </def>
 4624 <def>
 4625 <pfx>rexb</pfx>
 4626 <opc>b4</opc>
 4627 <opr>AHr12b Ib</opr>
 4628 </def>
 4629 <def>
 4630 <pfx>rexb</pfx>
 4631 <opc>b5</opc>
 4632 <opr>CHr13b Ib</opr>
 4633 </def>
 4634 <def>
 4635 <pfx>rexb</pfx>
 4636 <opc>b6</opc>
 4637 <opr>DHr14b Ib</opr>
 4638 </def>
 4639 <def>
 4640 <pfx>rexb</pfx>
 4641 <opc>b7</opc>
 4642 <opr>BHr15b Ib</opr>
 4643 </def>
 4644 <def>
 4645 <pfx>oso rexw rexb</pfx>
 4646 <opc>b8</opc>
 4647 <opr>rAXr8 Iv</opr>
 4648 </def>
 4649 <def>
 4650 <pfx>oso rexw rexb</pfx>
 4651 <opc>b9</opc>
 4652 <opr>rCXr9 Iv</opr>
 4653 </def>
 4654 <def>
 4655 <pfx>oso rexw rexb</pfx>
 4656 <opc>ba</opc>
 4657 <opr>rDXr10 Iv</opr>
 4658 </def>
 4659 <def>
 4660 <pfx>oso rexw rexb</pfx>
 4661 <opc>bb</opc>
 4662 <opr>rBXr11 Iv</opr>
 4663 </def>
 4664 <def>
 4665 <pfx>oso rexw rexb</pfx>
 4666 <opc>bc</opc>
 4667 <opr>rSPr12 Iv</opr>
 4668 </def>
 4669 <def>
 4670 <pfx>oso rexw rexb</pfx>
 4671 <opc>bd</opc>
 4672 <opr>rBPr13 Iv</opr>
 4673 </def>
 4674 <def>
 4675 <pfx>oso rexw rexb</pfx>
 4676 <opc>be</opc>
 4677 <opr>rSIr14 Iv</opr>
 4678 </def>
 4679 <def>
 4680 <pfx>oso rexw rexb</pfx>
 4681 <opc>bf</opc>
 4682 <opr>rDIr15 Iv</opr>
 4683 </def>
 4684 <def>
 4685 <pfx>rexr</pfx>
 4686 <opc>0f 20</opc>
 4687 <opr>R C</opr>
 4688 </def>
 4689 <def>
 4690 <pfx>rexr</pfx>
 4691 <opc>0f 21</opc>
 4692 <opr>R D</opr>
 4693 </def>
 4694 <def>
 4695 <pfx>rexr</pfx>
 4696 <opc>0f 22</opc>
 4697 <opr>C R</opr>
 4698 </def>
 4699 <def>
 4700 <pfx>rexr</pfx>
 4701 <opc>0f 23</opc>
 4702 <opr>D R</opr>
 4703 </def>
 4704 </instruction>
 4705
 4706 <instruction>
 4707 <mnemonic>movapd</mnemonic>
 4708 <def>
 4709 <pfx>aso rexr rexx rexb</pfx>
 4710 <opc>sse66 0f 28</opc>
 4711 <opr>V W</opr>
 4712 </def>
 4713 <def>
 4714 <pfx>aso rexr rexx rexb</pfx>
 4715 <opc>sse66 0f 29</opc>
 4716 <opr>W V</opr>
 4717 </def>
 4718 </instruction>
 4719
 4720 <instruction>
 4721 <mnemonic>movaps</mnemonic>
 4722 <def>
 4723 <pfx>aso rexr rexx rexb</pfx>
 4724 <opc>0f 28</opc>
 4725 <opr>V W</opr>
 4726 </def>
 4727 <def>
 4728 <pfx>aso rexr rexx rexb</pfx>
 4729 <opc>0f 29</opc>
 4730 <opr>W V</opr>
 4731 </def>
 4732 </instruction>
 4733
 4734 <instruction>
 4735 <mnemonic>movd</mnemonic>
 4736 <def>
 4737 <pfx>aso rexw rexr rexx rexb</pfx>
 4738 <opc>sse66 0f 6e</opc>
 4739 <opr>V Ex</opr>
 4740 </def>
 4741 <def>
 4742 <pfx>aso rexr rexx rexb</pfx>
 4743 <opc>0f 6e</opc>
 4744 <opr>P Ex</opr>
 4745 </def>
 4746 <def>
 4747 <pfx>aso rexw rexr rexx rexb</pfx>
 4748 <opc>sse66 0f 7e</opc>
 4749 <opr>Ex V</opr>
 4750 </def>
 4751 <def>
 4752 <pfx>aso rexr rexx rexb</pfx>
 4753 <opc>0f 7e</opc>
 4754 <opr>Ex P</opr>
 4755 </def>
 4756 </instruction>
 4757
 4758 <instruction>
 4759 <mnemonic>movhpd</mnemonic>
 4760 <def>
 4761 <pfx>aso rexr rexx rexb</pfx>
 4762 <opc>sse66 0f 16 /mod=!11</opc>
 4763 <opr>V M</opr>
 4764 </def>
 4765 <def>
 4766 <pfx>aso rexr rexx rexb</pfx>
 4767 <opc>sse66 0f 17</opc>
 4768 <opr>M V</opr>
 4769 </def>
 4770 </instruction>
 4771
 4772 <instruction>
 4773 <mnemonic>movhps</mnemonic>
 4774 <def>
 4775 <pfx>aso rexr rexx rexb</pfx>
 4776 <opc>0f 16 /mod=!11</opc>
 4777 <opr>V M</opr>
 4778 </def>
 4779 <def>
 4780 <pfx>aso rexr rexx rexb</pfx>
 4781 <opc>0f 17</opc>
 4782 <opr>M V</opr>
 4783 </def>
 4784 </instruction>
 4785
 4786 <instruction>
 4787 <mnemonic>movlhps</mnemonic>
 4788 <def>
 4789 <pfx>aso rexr rexx rexb</pfx>
 4790 <opc>0f 16 /mod=11</opc>
 4791 <opr>V VR</opr>
 4792 </def>
 4793 </instruction>
 4794
 4795 <instruction>
 4796 <mnemonic>movlpd</mnemonic>
 4797 <def>
 4798 <pfx>aso rexr rexx rexb</pfx>
 4799 <opc>sse66 0f 12 /mod=!11</opc>
 4800 <opr>V M</opr>
 4801 </def>
 4802 <def>
 4803 <pfx>aso rexr rexx rexb</pfx>
 4804 <opc>sse66 0f 13</opc>
 4805 <opr>M V</opr>
 4806 </def>
 4807 </instruction>
 4808
 4809 <instruction>
 4810 <mnemonic>movlps</mnemonic>
 4811 <def>
 4812 <pfx>aso rexr rexx rexb</pfx>
 4813 <opc>0f 12 /mod=!11</opc>
 4814 <opr>V M</opr>
 4815 </def>
 4816 <def>
 4817 <pfx>aso rexr rexx rexb</pfx>
 4818 <opc>0f 13</opc>
 4819 <opr>M V</opr>
 4820 </def>
 4821 </instruction>
 4822
 4823 <instruction>
 4824 <mnemonic>movhlps</mnemonic>
 4825 <def>
 4826 <pfx>aso rexr rexx rexb</pfx>
 4827 <opc>0f 12 /mod=11</opc>
 4828 <opr>V VR</opr>
 4829 </def>
 4830 </instruction>
 4831
 4832 <instruction>
 4833 <mnemonic>movmskpd</mnemonic>
 4834 <def>
 4835 <pfx>oso rexr rexb</pfx>
 4836 <opc>sse66 0f 50</opc>
 4837 <opr>Gd VR</opr>
 4838 </def>
 4839 </instruction>
 4840
 4841 <instruction>
 4842 <mnemonic>movmskps</mnemonic>
 4843 <def>
 4844 <pfx>oso rexr rexb</pfx>
 4845 <opc>0f 50</opc>
 4846 <opr>Gd VR</opr>
 4847 </def>
 4848 </instruction>
 4849
 4850 <instruction>
 4851 <mnemonic>movntdq</mnemonic>
 4852 <def>
 4853 <pfx>aso rexr rexx rexb</pfx>
 4854 <opc>sse66 0f e7</opc>
 4855 <opr>M V</opr>
 4856 </def>
 4857 </instruction>
 4858
 4859 <instruction>
 4860 <mnemonic>movnti</mnemonic>
 4861 <def>
 4862 <pfx>aso rexw rexr rexx rexb</pfx>
 4863 <opc>0f c3</opc>
 4864 <opr>M Gy</opr>
 4865 </def>
 4866 </instruction>
 4867
 4868 <instruction>
 4869 <mnemonic>movntpd</mnemonic>
 4870 <def>
 4871 <pfx>aso rexr rexx rexb</pfx>
 4872 <opc>sse66 0f 2b</opc>
 4873 <opr>M V</opr>
 4874 </def>
 4875 </instruction>
 4876
 4877 <instruction>
 4878 <mnemonic>movntps</mnemonic>
 4879 <def>
 4880 <pfx>aso rexr rexx rexb</pfx>
 4881 <opc>0f 2b</opc>
 4882 <opr>M V</opr>
 4883 </def>
 4884 </instruction>
 4885
 4886 <instruction>
 4887 <mnemonic>movntq</mnemonic>
 4888 <def>
 4889 <opc>0f e7</opc>
 4890 <opr>M P</opr>
 4891 </def>
 4892 </instruction>
 4893
 4894 <instruction>
 4895 <mnemonic>movq</mnemonic>
 4896 <def>
 4897 <pfx>aso rexr rexx rexb</pfx>
 4898 <opc>0f 6f</opc>
 4899 <opr>P Q</opr>
 4900 </def>
 4901 <def>
 4902 <pfx>aso rexr rexx rexb</pfx>
 4903 <opc>sse66 0f d6</opc>
 4904 <opr>W V</opr>
 4905 </def>
 4906 <def>
 4907 <pfx>aso rexr rexx rexb</pfx>
 4908 <opc>ssef3 0f 7e</opc>
 4909 <opr>V W</opr>
 4910 </def>
 4911 <def>
 4912 <pfx>aso rexr rexx rexb</pfx>
 4913 <opc>0f 7f</opc>
 4914 <opr>Q P</opr>
 4915 </def>
 4916 </instruction>
 4917
 4918 <instruction>
 4919 <mnemonic>movsb</mnemonic>
 4920 <def>
 4921 <pfx>seg</pfx>
 4922 <opc>a4</opc>
 4923 </def>
 4924 </instruction>
 4925
 4926 <instruction>
 4927 <mnemonic>movsw</mnemonic>
 4928 <def>
 4929 <pfx>seg oso rexw</pfx>
 4930 <opc>a5 /o=16</opc>
 4931 </def>
 4932 </instruction>
 4933
 4934 <instruction>
 4935 <mnemonic>movsd</mnemonic>
 4936 <def>
 4937 <pfx>seg oso rexw</pfx>
 4938 <opc>a5 /o=32</opc>
 4939 </def>
 4940 <def>
 4941 <pfx>aso rexr rexx rexb</pfx>
 4942 <opc>ssef2 0f 10</opc>
 4943 <opr>V W</opr>
 4944 </def>
 4945 <def>
 4946 <pfx>aso rexr rexx rexb</pfx>
 4947 <opc>ssef2 0f 11</opc>
 4948 <opr>W V</opr>
 4949 </def>
 4950 </instruction>
 4951
 4952 <instruction>
 4953 <mnemonic>movsq</mnemonic>
 4954 <def>
 4955 <pfx>seg oso rexw</pfx>
 4956 <opc>a5 /o=64</opc>
 4957 </def>
 4958 </instruction>
 4959
 4960 <instruction>
 4961 <mnemonic>movss</mnemonic>
 4962 <def>
 4963 <pfx>aso rexr rexx rexb</pfx>
 4964 <opc>ssef3 0f 10</opc>
 4965 <opr>V W</opr>
 4966 </def>
 4967 <def>
 4968 <pfx>aso rexr rexx rexb</pfx>
 4969 <opc>ssef3 0f 11</opc>
 4970 <opr>W V</opr>
 4971 </def>
 4972 </instruction>
 4973
 4974 <instruction>
 4975 <mnemonic>movsx</mnemonic>
 4976 <def>
 4977 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4978 <opc>0f be</opc>
 4979 <opr>Gv Eb</opr>
 4980 </def>
 4981 <def>
 4982 <pfx>aso oso rexw rexr rexx rexb</pfx>
 4983 <opc>0f bf</opc>
 4984 <opr>Gv Ew</opr>
 4985 </def>
 4986 </instruction>
 4987
 4988 <instruction>
 4989 <mnemonic>movupd</mnemonic>
 4990 <def>
 4991 <pfx>aso rexr rexx rexb</pfx>
 4992 <opc>sse66 0f 10</opc>
 4993 <opr>V W</opr>
 4994 </def>
 4995 <def>
 4996 <pfx>aso rexr rexx rexb</pfx>
 4997 <opc>sse66 0f 11</opc>
 4998 <opr>W V</opr>
 4999 </def>
 5000 </instruction>
 5001
 5002 <instruction>
 5003 <mnemonic>movups</mnemonic>
 5004 <def>
 5005 <pfx>aso rexr rexx rexb</pfx>
 5006 <opc>0f 10</opc>
 5007 <opr>V W</opr>
 5008 </def>
 5009 <def>
 5010 <pfx>aso rexr rexx rexb</pfx>
 5011 <opc>0f 11</opc>
 5012 <opr>W V</opr>
 5013 </def>
 5014 </instruction>
 5015
 5016 <instruction>
 5017 <mnemonic>movzx</mnemonic>
 5018 <def>
 5019 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5020 <opc>0f b6</opc>
 5021 <opr>Gv Eb</opr>
 5022 </def>
 5023 <def>
 5024 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5025 <opc>0f b7</opc>
 5026 <opr>Gv Ew</opr>
 5027 </def>
 5028 </instruction>
 5029
 5030 <instruction>
 5031 <mnemonic>mul</mnemonic>
 5032 <def>
 5033 <pfx>aso rexw rexr rexx rexb</pfx>
 5034 <opc>f6 /reg=4</opc>
 5035 <opr>Eb</opr>
 5036 </def>
 5037 <def>
 5038 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5039 <opc>f7 /reg=4</opc>
 5040 <opr>Ev</opr>
 5041 </def>
 5042 </instruction>
 5043
 5044 <instruction>
 5045 <mnemonic>mulpd</mnemonic>
 5046 <def>
 5047 <pfx>aso rexr rexx rexb</pfx>
 5048 <opc>sse66 0f 59</opc>
 5049 <opr>V W</opr>
 5050 </def>
 5051 </instruction>
 5052
 5053 <instruction>
 5054 <mnemonic>mulps</mnemonic>
 5055 <def>
 5056 <pfx>aso rexr rexx rexb</pfx>
 5057 <opc>0f 59</opc>
 5058 <opr>V W</opr>
 5059 </def>
 5060 </instruction>
 5061
 5062 <instruction>
 5063 <mnemonic>mulsd</mnemonic>
 5064 <def>
 5065 <pfx>aso rexr rexx rexb</pfx>
 5066 <opc>ssef2 0f 59</opc>
 5067 <opr>V W</opr>
 5068 </def>
 5069 </instruction>
 5070
 5071 <instruction>
 5072 <mnemonic>mulss</mnemonic>
 5073 <def>
 5074 <pfx>aso rexr rexx rexb</pfx>
 5075 <opc>ssef3 0f 59</opc>
 5076 <opr>V W</opr>
 5077 </def>
 5078 </instruction>
 5079
 5080 <instruction>
 5081 <mnemonic>mwait</mnemonic>
 5082 <def>
 5083 <opc>0f 01 /reg=1 /mod=11 /rm=1</opc>
 5084 </def>
 5085 </instruction>
 5086
 5087 <instruction>
 5088 <mnemonic>neg</mnemonic>
 5089 <def>
 5090 <pfx>aso rexw rexr rexx rexb</pfx>
 5091 <opc>f6 /reg=3</opc>
 5092 <opr>Eb</opr>
 5093 </def>
 5094 <def>
 5095 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5096 <opc>f7 /reg=3</opc>
 5097 <opr>Ev</opr>
 5098 </def>
 5099 </instruction>
 5100
 5101 <instruction>
 5102 <mnemonic>nop</mnemonic>
 5103 <def>
 5104 <opc>90</opc>
 5105 </def>
 5106 <def>
 5107 <pfx>aso rexr rexx rexb</pfx>
 5108 <opc>0f 19</opc>
 5109 <opr>M</opr>
 5110 </def>
 5111 <def>
 5112 <pfx>aso rexr rexx rexb</pfx>
 5113 <opc>0f 1a</opc>
 5114 <opr>M</opr>
 5115 </def>
 5116 <def>
 5117 <pfx>aso rexr rexx rexb</pfx>
 5118 <opc>0f 1b</opc>
 5119 <opr>M</opr>
 5120 </def>
 5121 <def>
 5122 <pfx>aso rexr rexx rexb</pfx>
 5123 <opc>0f 1c</opc>
 5124 <opr>M</opr>
 5125 </def>
 5126 <def>
 5127 <pfx>aso rexr rexx rexb</pfx>
 5128 <opc>0f 1d</opc>
 5129 <opr>M</opr>
 5130 </def>
 5131 <def>
 5132 <pfx>aso rexr rexx rexb</pfx>
 5133 <opc>0f 1e</opc>
 5134 <opr>M</opr>
 5135 </def>
 5136 <def>
 5137 <pfx>aso rexr rexx rexb</pfx>
 5138 <opc>0f 1f</opc>
 5139 <opr>M</opr>
 5140 </def>
 5141 </instruction>
 5142
 5143 <instruction>
 5144 <mnemonic>not</mnemonic>
 5145 <def>
 5146 <pfx>aso rexw rexr rexx rexb</pfx>
 5147 <opc>f6 /reg=2</opc>
 5148 <opr>Eb</opr>
 5149 </def>
 5150 <def>
 5151 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5152 <opc>f7 /reg=2</opc>
 5153 <opr>Ev</opr>
 5154 </def>
 5155 </instruction>
 5156
 5157 <instruction>
 5158 <mnemonic>or</mnemonic>
 5159 <def>
 5160 <pfx>aso rexr rexx rexb</pfx>
 5161 <opc>08</opc>
 5162 <opr>Eb Gb</opr>
 5163 </def>
 5164 <def>
 5165 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5166 <opc>09</opc>
 5167 <opr>Ev Gv</opr>
 5168 </def>
 5169 <def>
 5170 <pfx>aso rexr rexx rexb</pfx>
 5171 <opc>0a</opc>
 5172 <opr>Gb Eb</opr>
 5173 </def>
 5174 <def>
 5175 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5176 <opc>0b</opc>
 5177 <opr>Gv Ev</opr>
 5178 </def>
 5179 <def>
 5180 <opc>0c</opc>
 5181 <opr>AL Ib</opr>
 5182 </def>
 5183 <def>
 5184 <pfx>oso rexw</pfx>
 5185 <opc>0d</opc>
 5186 <opr>rAX Iz</opr>
 5187 <syn>sext</syn>
 5188 </def>
 5189 <def>
 5190 <pfx>aso rexr rexx rexb</pfx>
 5191 <opc>80 /reg=1</opc>
 5192 <opr>Eb Ib</opr>
 5193 </def>
 5194 <def>
 5195 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5196 <opc>81 /reg=1</opc>
 5197 <opr>Ev Iz</opr>
 5198 <syn>sext</syn>
 5199 </def>
 5200 <def>
 5201 <pfx>aso rexr rexx rexb</pfx>
 5202 <opc>82 /reg=1</opc>
 5203 <opr>Eb Ib</opr>
 5204 <mode>inv64</mode>
 5205 </def>
 5206 <def>
 5207 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5208 <opc>83 /reg=1</opc>
 5209 <opr>Ev Ib</opr>
 5210 <syn>sext</syn>
 5211 </def>
 5212 </instruction>
 5213
 5214 <instruction>
 5215 <mnemonic>orpd</mnemonic>
 5216 <def>
 5217 <pfx>aso rexr rexx rexb</pfx>
 5218 <opc>sse66 0f 56</opc>
 5219 <opr>V W</opr>
 5220 </def>
 5221 </instruction>
 5222
 5223 <instruction>
 5224 <mnemonic>orps</mnemonic>
 5225 <def>
 5226 <pfx>aso rexr rexx rexb</pfx>
 5227 <opc>0f 56</opc>
 5228 <opr>V W</opr>
 5229 </def>
 5230 </instruction>
 5231
 5232 <instruction>
 5233 <mnemonic>out</mnemonic>
 5234 <def>
 5235 <opc>e6</opc>
 5236 <opr>Ib AL</opr>
 5237 </def>
 5238 <def>
 5239 <pfx>oso</pfx>
 5240 <opc>e7</opc>
 5241 <opr>Ib eAX</opr>
 5242 </def>
 5243 <def>
 5244 <opc>ee</opc>
 5245 <opr>DX AL</opr>
 5246 </def>
 5247 <def>
 5248 <pfx>oso</pfx>
 5249 <opc>ef</opc>
 5250 <opr>DX eAX</opr>
 5251 </def>
 5252 </instruction>
 5253
 5254 <instruction>
 5255 <mnemonic>outsb</mnemonic>
 5256 <def>
 5257 <opc>6e</opc>
 5258 </def>
 5259 </instruction>
 5260
 5261 <instruction>
 5262 <mnemonic>outsw</mnemonic>
 5263 <def>
 5264 <pfx>oso</pfx>
 5265 <opc>6f /o=16</opc>
 5266 </def>
 5267 </instruction>
 5268
 5269 <instruction>
 5270 <mnemonic>outsd</mnemonic>
 5271 <def>
 5272 <pfx>oso</pfx>
 5273 <opc>6f /o=32</opc>
 5274 </def>
 5275 </instruction>
 5276
 5277 <instruction>
 5278 <mnemonic>outsq</mnemonic>
 5279 <def>
 5280 <pfx>oso</pfx>
 5281 <opc>6f /o=64</opc>
 5282 </def>
 5283 </instruction>
 5284
 5285 <instruction>
 5286 <mnemonic>packsswb</mnemonic>
 5287 <def>
 5288 <pfx>aso rexr rexx rexb</pfx>
 5289 <opc>sse66 0f 63</opc>
 5290 <opr>V W</opr>
 5291 </def>
 5292 <def>
 5293 <pfx>aso rexr rexx rexb</pfx>
 5294 <opc>0f 63</opc>
 5295 <opr>P Q</opr>
 5296 </def>
 5297 </instruction>
 5298
 5299 <instruction>
 5300 <mnemonic>packssdw</mnemonic>
 5301 <def>
 5302 <pfx>aso rexr rexx rexb</pfx>
 5303 <opc>sse66 0f 6b</opc>
 5304 <opr>V W</opr>
 5305 </def>
 5306 <def>
 5307 <pfx>aso rexr rexx rexb</pfx>
 5308 <opc>0f 6b</opc>
 5309 <opr>P Q</opr>
 5310 </def>
 5311 </instruction>
 5312
 5313 <instruction>
 5314 <mnemonic>packuswb</mnemonic>
 5315 <def>
 5316 <pfx>aso rexr rexx rexb</pfx>
 5317 <opc>sse66 0f 67</opc>
 5318 <opr>V W</opr>
 5319 </def>
 5320 <def>
 5321 <pfx>aso rexr rexx rexb</pfx>
 5322 <opc>0f 67</opc>
 5323 <opr>P Q</opr>
 5324 </def>
 5325 </instruction>
 5326
 5327 <instruction>
 5328 <mnemonic>paddb</mnemonic>
 5329 <def>
 5330 <pfx>aso rexr rexx rexb</pfx>
 5331 <opc>sse66 0f fc</opc>
 5332 <opr>V W</opr>
 5333 </def>
 5334 <def>
 5335 <pfx>aso rexr rexx rexb</pfx>
 5336 <opc>0f fc</opc>
 5337 <opr>P Q</opr>
 5338 </def>
 5339 </instruction>
 5340
 5341 <instruction>
 5342 <mnemonic>paddw</mnemonic>
 5343 <def>
 5344 <pfx>aso rexr rexx rexb</pfx>
 5345 <opc>0f fd</opc>
 5346 <opr>P Q</opr>
 5347 </def>
 5348 <def>
 5349 <pfx>aso rexr rexx rexb</pfx>
 5350 <opc>sse66 0f fd</opc>
 5351 <opr>V W</opr>
 5352 </def>
 5353 </instruction>
 5354
 5355 <instruction>
 5356 <mnemonic>paddd</mnemonic>
 5357 <def>
 5358 <pfx>aso rexr rexx rexb</pfx>
 5359 <opc>0f fe</opc>
 5360 <opr>P Q</opr>
 5361 </def>
 5362 <def>
 5363 <pfx>aso rexr rexx rexb</pfx>
 5364 <opc>sse66 0f fe</opc>
 5365 <opr>V W</opr>
 5366 </def>
 5367 </instruction>
 5368
 5369
 5370 <instruction>
 5371 <mnemonic>paddsb</mnemonic>
 5372 <def>
 5373 <pfx>aso rexr rexx rexb</pfx>
 5374 <opc>0f ec</opc>
 5375 <opr>P Q</opr>
 5376 </def>
 5377 <def>
 5378 <pfx>aso rexr rexx rexb</pfx>
 5379 <opc>sse66 0f ec</opc>
 5380 <opr>V W</opr>
 5381 </def>
 5382 </instruction>
 5383
 5384 <instruction>
 5385 <mnemonic>paddsw</mnemonic>
 5386 <def>
 5387 <pfx>aso rexr rexx rexb</pfx>
 5388 <opc>0f ed</opc>
 5389 <opr>P Q</opr>
 5390 </def>
 5391 <def>
 5392 <pfx>aso rexr rexx rexb</pfx>
 5393 <opc>sse66 0f ed</opc>
 5394 <opr>V W</opr>
 5395 </def>
 5396 </instruction>
 5397
 5398 <instruction>
 5399 <mnemonic>paddusb</mnemonic>
 5400 <def>
 5401 <pfx>aso rexr rexx rexb</pfx>
 5402 <opc>0f dc</opc>
 5403 <opr>P Q</opr>
 5404 </def>
 5405 <def>
 5406 <pfx>aso rexr rexx rexb</pfx>
 5407 <opc>sse66 0f dc</opc>
 5408 <opr>V W</opr>
 5409 </def>
 5410 </instruction>
 5411
 5412 <instruction>
 5413 <mnemonic>paddusw</mnemonic>
 5414 <def>
 5415 <pfx>aso rexr rexx rexb</pfx>
 5416 <opc>0f dd</opc>
 5417 <opr>P Q</opr>
 5418 </def>
 5419 <def>
 5420 <pfx>aso rexr rexx rexb</pfx>
 5421 <opc>sse66 0f dd</opc>
 5422 <opr>V W</opr>
 5423 </def>
 5424 </instruction>
 5425
 5426 <instruction>
 5427 <mnemonic>pand</mnemonic>
 5428 <def>
 5429 <pfx>aso rexr rexx rexb</pfx>
 5430 <opc>sse66 0f db</opc>
 5431 <opr>V W</opr>
 5432 </def>
 5433 <def>
 5434 <pfx>aso rexr rexx rexb</pfx>
 5435 <opc>0f db</opc>
 5436 <opr>P Q</opr>
 5437 </def>
 5438 </instruction>
 5439
 5440 <instruction>
 5441 <mnemonic>pandn</mnemonic>
 5442 <def>
 5443 <pfx>aso rexr rexx rexb</pfx>
 5444 <opc>sse66 0f df</opc>
 5445 <opr>V W</opr>
 5446 </def>
 5447 <def>
 5448 <pfx>aso rexr rexx rexb</pfx>
 5449 <opc>0f df</opc>
 5450 <opr>P Q</opr>
 5451 </def>
 5452 </instruction>
 5453
 5454 <instruction>
 5455 <mnemonic>pavgb</mnemonic>
 5456 <def>
 5457 <pfx>aso rexr rexx rexb</pfx>
 5458 <opc>sse66 0f e0</opc>
 5459 <opr>V W</opr>
 5460 </def>
 5461 <def>
 5462 <pfx>aso rexr rexx rexb</pfx>
 5463 <opc>0f e0</opc>
 5464 <opr>P Q</opr>
 5465 </def>
 5466 </instruction>
 5467
 5468 <instruction>
 5469 <mnemonic>pavgw</mnemonic>
 5470 <def>
 5471 <pfx>aso rexr rexx rexb</pfx>
 5472 <opc>sse66 0f e3</opc>
 5473 <opr>V W</opr>
 5474 </def>
 5475 <def>
 5476 <pfx>aso rexr rexx rexb</pfx>
 5477 <opc>0f e3</opc>
 5478 <opr>P Q</opr>
 5479 </def>
 5480 </instruction>
 5481
 5482 <instruction>
 5483 <mnemonic>pcmpeqb</mnemonic>
 5484 <def>
 5485 <pfx>aso rexr rexx rexb</pfx>
 5486 <opc>0f 74</opc>
 5487 <opr>P Q</opr>
 5488 </def>
 5489 <def>
 5490 <pfx>aso rexr rexx rexb</pfx>
 5491 <opc>sse66 0f 74</opc>
 5492 <opr>V W</opr>
 5493 </def>
 5494 </instruction>
 5495
 5496 <instruction>
 5497 <mnemonic>pcmpeqw</mnemonic>
 5498 <def>
 5499 <pfx>aso rexr rexx rexb</pfx>
 5500 <opc>0f 75</opc>
 5501 <opr>P Q</opr>
 5502 </def>
 5503 <def>
 5504 <pfx>aso rexr rexx rexb</pfx>
 5505 <opc>sse66 0f 75</opc>
 5506 <opr>V W</opr>
 5507 </def>
 5508 </instruction>
 5509
 5510 <instruction>
 5511 <mnemonic>pcmpeqd</mnemonic>
 5512 <def>
 5513 <pfx>aso rexr rexx rexb</pfx>
 5514 <opc>0f 76</opc>
 5515 <opr>P Q</opr>
 5516 </def>
 5517 <def>
 5518 <pfx>aso rexr rexx rexb</pfx>
 5519 <opc>sse66 0f 76</opc>
 5520 <opr>V W</opr>
 5521 </def>
 5522 </instruction>
 5523
 5524 <instruction>
 5525 <mnemonic>pcmpgtb</mnemonic>
 5526 <def>
 5527 <pfx>aso rexr rexx rexb</pfx>
 5528 <opc>sse66 0f 64</opc>
 5529 <opr>V W</opr>
 5530 </def>
 5531 <def>
 5532 <pfx>aso rexr rexx rexb</pfx>
 5533 <opc>0f 64</opc>
 5534 <opr>P Q</opr>
 5535 </def>
 5536 </instruction>
 5537
 5538 <instruction>
 5539 <mnemonic>pcmpgtw</mnemonic>
 5540 <def>
 5541 <pfx>aso rexr rexx rexb</pfx>
 5542 <opc>sse66 0f 65</opc>
 5543 <opr>V W</opr>
 5544 </def>
 5545 <def>
 5546 <pfx>aso rexr rexx rexb</pfx>
 5547 <opc>0f 65</opc>
 5548 <opr>P Q</opr>
 5549 </def>
 5550 </instruction>
 5551
 5552 <instruction>
 5553 <mnemonic>pcmpgtd</mnemonic>
 5554 <def>
 5555 <pfx>aso rexr rexx rexb</pfx>
 5556 <opc>sse66 0f 66</opc>
 5557 <opr>V W</opr>
 5558 </def>
 5559 <def>
 5560 <pfx>aso rexr rexx rexb</pfx>
 5561 <opc>0f 66</opc>
 5562 <opr>P Q</opr>
 5563 </def>
 5564 </instruction>
 5565
 5566 <instruction>
 5567 <mnemonic>pextrb</mnemonic>
 5568 <def>
 5569 <pfx>aso rexr rexb</pfx>
 5570 <opc>sse66 0f 3a 14</opc>
 5571 <opr>MbRv V Ib</opr>
 5572 <mode>def64</mode>
 5573 </def>
 5574 </instruction>
 5575
 5576 <instruction>
 5577 <mnemonic>pextrd</mnemonic>
 5578 <def>
 5579 <pfx>aso rexr rexw rexb</pfx>
 5580 <opc>sse66 0f 3a 16 /o=16</opc>
 5581 <opr>Ev V Ib</opr>
 5582 </def>
 5583 <def>
 5584 <pfx>aso rexr rexw rexb</pfx>
 5585 <opc>sse66 0f 3a 16 /o=32</opc>
 5586 <opr>Ev V Ib</opr>
 5587 </def>
 5588 </instruction>
 5589
 5590 <instruction>
 5591 <mnemonic>pextrq</mnemonic>
 5592 <def>
 5593 <pfx>aso rexr rexw rexb</pfx>
 5594 <opc>sse66 0f 3a 16 /o=64</opc>
 5595 <opr>Ev V Ib</opr>
 5596 <mode>def64</mode>
 5597 </def>
 5598 </instruction>
 5599
 5600 <instruction>
 5601 <mnemonic>pextrw</mnemonic>
 5602 <def>
 5603 <pfx>aso rexr rexb</pfx>
 5604 <opc>sse66 0f c5</opc>
 5605 <opr>Gd VR Ib</opr>
 5606 </def>
 5607 <def>
 5608 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5609 <opc>0f c5</opc>
 5610 <opr>Gd PR Ib</opr>
 5611 </def>
 5612 </instruction>
 5613
 5614 <instruction>
 5615 <mnemonic>pinsrw</mnemonic>
 5616 <def>
 5617 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5618 <opc>0f c4</opc>
 5619 <opr>P Ew Ib</opr>
 5620 </def>
 5621 <def>
 5622 <pfx>aso rexw rexr rexx rexb</pfx>
 5623 <opc>sse66 0f c4</opc>
 5624 <opr>V Ew Ib</opr>
 5625 </def>
 5626 </instruction>
 5627
 5628 <instruction>
 5629 <mnemonic>pmaddwd</mnemonic>
 5630 <def>
 5631 <pfx>aso rexr rexx rexb</pfx>
 5632 <opc>0f f5</opc>
 5633 <opr>P Q</opr>
 5634 </def>
 5635 <def>
 5636 <pfx>aso rexr rexx rexb</pfx>
 5637 <opc>sse66 0f f5</opc>
 5638 <opr>V W</opr>
 5639 </def>
 5640 </instruction>
 5641
 5642 <instruction>
 5643 <mnemonic>pmaxsw</mnemonic>
 5644 <def>
 5645 <pfx>aso rexr rexx rexb</pfx>
 5646 <opc>sse66 0f ee</opc>
 5647 <opr>V W</opr>
 5648 </def>
 5649 <def>
 5650 <pfx>aso rexr rexx rexb</pfx>
 5651 <opc>0f ee</opc>
 5652 <opr>P Q</opr>
 5653 </def>
 5654 </instruction>
 5655
 5656 <instruction>
 5657 <mnemonic>pmaxub</mnemonic>
 5658 <def>
 5659 <pfx>aso rexr rexx rexb</pfx>
 5660 <opc>0f de</opc>
 5661 <opr>P Q</opr>
 5662 </def>
 5663 <def>
 5664 <pfx>aso rexr rexx rexb</pfx>
 5665 <opc>sse66 0f de</opc>
 5666 <opr>V W</opr>
 5667 </def>
 5668 </instruction>
 5669
 5670 <instruction>
 5671 <mnemonic>pminsw</mnemonic>
 5672 <def>
 5673 <pfx>aso rexr rexx rexb</pfx>
 5674 <opc>sse66 0f ea</opc>
 5675 <opr>V W</opr>
 5676 </def>
 5677 <def>
 5678 <pfx>aso rexr rexx rexb</pfx>
 5679 <opc>0f ea</opc>
 5680 <opr>P Q</opr>
 5681 </def>
 5682 </instruction>
 5683
 5684 <instruction>
 5685 <mnemonic>pminub</mnemonic>
 5686 <def>
 5687 <pfx>aso rexr rexx rexb</pfx>
 5688 <opc>sse66 0f da</opc>
 5689 <opr>V W</opr>
 5690 </def>
 5691 <def>
 5692 <pfx>aso rexr rexx rexb</pfx>
 5693 <opc>0f da</opc>
 5694 <opr>P Q</opr>
 5695 </def>
 5696 </instruction>
 5697
 5698 <instruction>
 5699 <mnemonic>pmovmskb</mnemonic>
 5700 <def>
 5701 <pfx>rexr rexb</pfx>
 5702 <opc>sse66 0f d7</opc>
 5703 <opr>Gd VR</opr>
 5704 </def>
 5705 <def>
 5706 <pfx>oso rexr rexb</pfx>
 5707 <opc>0f d7</opc>
 5708 <opr>Gd PR</opr>
 5709 </def>
 5710 </instruction>
 5711
 5712 <instruction>
 5713 <mnemonic>pmulhuw</mnemonic>
 5714 <def>
 5715 <pfx>aso rexr rexx rexb</pfx>
 5716 <opc>0f e4</opc>
 5717 <opr>P Q</opr>
 5718 </def>
 5719 <def>
 5720 <pfx>aso rexr rexx rexb</pfx>
 5721 <opc>sse66 0f e4</opc>
 5722 <opr>V W</opr>
 5723 </def>
 5724 </instruction>
 5725
 5726 <instruction>
 5727 <mnemonic>pmulhw</mnemonic>
 5728 <def>
 5729 <pfx>aso rexr rexx rexb</pfx>
 5730 <opc>sse66 0f e5</opc>
 5731 <opr>V W</opr>
 5732 </def>
 5733 <def>
 5734 <pfx>aso rexr rexx rexb</pfx>
 5735 <opc>0f e5</opc>
 5736 <opr>P Q</opr>
 5737 </def>
 5738 </instruction>
 5739
 5740 <instruction>
 5741 <mnemonic>pmullw</mnemonic>
 5742 <def>
 5743 <pfx>aso rexr rexx rexb</pfx>
 5744 <opc>0f d5</opc>
 5745 <opr>P Q</opr>
 5746 </def>
 5747 <def>
 5748 <pfx>aso rexr rexx rexb</pfx>
 5749 <opc>sse66 0f d5</opc>
 5750 <opr>V W</opr>
 5751 </def>
 5752 </instruction>
 5753
 5754 <instruction>
 5755 <mnemonic>pop</mnemonic>
 5756 <def>
 5757 <opc>07</opc>
 5758 <opr>ES</opr>
 5759 <mode>inv64</mode>
 5760 </def>
 5761 <def>
 5762 <opc>17</opc>
 5763 <opr>SS</opr>
 5764 <mode>inv64</mode>
 5765 </def>
 5766 <def>
 5767 <opc>1f</opc>
 5768 <opr>DS</opr>
 5769 <mode>inv64</mode>
 5770 </def>
 5771 <def>
 5772 <opc>0f a9</opc>
 5773 <opr>GS</opr>
 5774 </def>
 5775 <def>
 5776 <opc>0f a1</opc>
 5777 <opr>FS</opr>
 5778 </def>
 5779 <def>
 5780 <pfx>oso rexb</pfx>
 5781 <opc>58</opc>
 5782 <opr>rAXr8</opr>
 5783 <mode>def64 depM</mode>
 5784 </def>
 5785 <def>
 5786 <pfx>oso rexb</pfx>
 5787 <opc>59</opc>
 5788 <opr>rCXr9</opr>
 5789 <mode>def64 depM</mode>
 5790 </def>
 5791 <def>
 5792 <pfx>oso rexb</pfx>
 5793 <opc>5a</opc>
 5794 <opr>rDXr10</opr>
 5795 <mode>def64 depM</mode>
 5796 </def>
 5797 <def>
 5798 <pfx>oso rexb</pfx>
 5799 <opc>5b</opc>
 5800 <opr>rBXr11</opr>
 5801 <mode>def64 depM</mode>
 5802 </def>
 5803 <def>
 5804 <pfx>oso rexb</pfx>
 5805 <opc>5c</opc>
 5806 <opr>rSPr12</opr>
 5807 <mode>def64 depM</mode>
 5808 </def>
 5809 <def>
 5810 <pfx>oso rexb</pfx>
 5811 <opc>5d</opc>
 5812 <opr>rBPr13</opr>
 5813 <mode>def64 depM</mode>
 5814 </def>
 5815 <def>
 5816 <pfx>oso rexb</pfx>
 5817 <opc>5e</opc>
 5818 <opr>rSIr14</opr>
 5819 <mode>def64 depM</mode>
 5820 </def>
 5821 <def>
 5822 <pfx>oso rexb</pfx>
 5823 <opc>5f</opc>
 5824 <opr>rDIr15</opr>
 5825 <mode>def64 depM</mode>
 5826 </def>
 5827 <def>
 5828 <pfx>aso oso rexw rexr rexx rexb</pfx>
 5829 <opc>8f /reg=0</opc>
 5830 <opr>Ev</opr>
 5831 <mode>def64 depM</mode>
 5832 </def>
 5833 </instruction>
 5834
 5835 <instruction>
 5836 <mnemonic>popa</mnemonic>
 5837 <def>
 5838 <pfx>oso</pfx>
 5839 <opc>61 /o=16</opc>
 5840 <mode>inv64</mode>
 5841 </def>
 5842 </instruction>
 5843
 5844 <instruction>
 5845 <mnemonic>popad</mnemonic>
 5846 <def>
 5847 <pfx>oso</pfx>
 5848 <opc>61 /o=32</opc>
 5849 <mode>inv64</mode>
 5850 </def>
 5851 </instruction>
 5852
 5853 <instruction>
 5854 <mnemonic>popfw</mnemonic>
 5855 <def>
 5856 <pfx>oso</pfx>
 5857 <opc>9d /m=32 /o=16</opc>
 5858 <mode>def64 depM</mode>
 5859 </def>
 5860 <def>
 5861 <pfx>oso</pfx>
 5862 <opc>9d /m=16 /o=16</opc>
 5863 <mode>def64 depM</mode>
 5864 </def>
 5865 </instruction>
 5866
 5867 <instruction>
 5868 <mnemonic>popfd</mnemonic>
 5869 <def>
 5870 <pfx>oso</pfx>
 5871 <opc>9d /m=16 /o=32</opc>
 5872 <mode>def64 depM</mode>
 5873 </def>
 5874 <def>
 5875 <pfx>oso</pfx>
 5876 <opc>9d /m=32 /o=32</opc>
 5877 <mode>def64 depM</mode>
 5878 </def>
 5879 </instruction>
 5880
 5881 <instruction>
 5882 <mnemonic>popfq</mnemonic>
 5883 <def>
 5884 <pfx>oso</pfx>
 5885 <opc>9d /m=64 /o=64</opc>
 5886 <mode>def64 depM</mode>
 5887 </def>
 5888 </instruction>
 5889
 5890 <instruction>
 5891 <mnemonic>por</mnemonic>
 5892 <def>
 5893 <pfx>aso rexr rexx rexb</pfx>
 5894 <opc>sse66 0f eb</opc>
 5895 <opr>V W</opr>
 5896 </def>
 5897 <def>
 5898 <pfx>aso rexr rexx rexb</pfx>
 5899 <opc>0f eb</opc>
 5900 <opr>P Q</opr>
 5901 </def>
 5902 </instruction>
 5903
 5904 <instruction>
 5905 <mnemonic>prefetch</mnemonic>
 5906 <def>
 5907 <pfx>aso rexw rexr rexx rexb</pfx>
 5908 <opc>0f 0d /reg=0</opc>
 5909 <opr>M</opr>
 5910 </def>
 5911 <def>
 5912 <pfx>aso rexw rexr rexx rexb</pfx>
 5913 <opc>0f 0d /reg=1</opc>
 5914 <opr>M</opr>
 5915 </def>
 5916 <def>
 5917 <pfx>aso rexw rexr rexx rexb</pfx>
 5918 <opc>0f 0d /reg=2</opc>
 5919 <opr>M</opr>
 5920 </def>
 5921 <def>
 5922 <pfx>aso rexw rexr rexx rexb</pfx>
 5923 <opc>0f 0d /reg=3</opc>
 5924 <opr>M</opr>
 5925 </def>
 5926 <def>
 5927 <pfx>aso rexw rexr rexx rexb</pfx>
 5928 <opc>0f 0d /reg=4</opc>
 5929 <opr>M</opr>
 5930 </def>
 5931 <def>
 5932 <pfx>aso rexw rexr rexx rexb</pfx>
 5933 <opc>0f 0d /reg=5</opc>
 5934 <opr>M</opr>
 5935 </def>
 5936 <def>
 5937 <pfx>aso rexw rexr rexx rexb</pfx>
 5938 <opc>0f 0d /reg=6</opc>
 5939 <opr>M</opr>
 5940 </def>
 5941 <def>
 5942 <pfx>aso rexw rexr rexx rexb</pfx>
 5943 <opc>0f 0d /reg=7</opc>
 5944 <opr>M</opr>
 5945 </def>
 5946 </instruction>
 5947
 5948 <instruction>
 5949 <mnemonic>prefetchnta</mnemonic>
 5950 <def>
 5951 <pfx>aso rexw rexr rexx rexb</pfx>
 5952 <opc>0f 18 /reg=0</opc>
 5953 <opr>M</opr>
 5954 </def>
 5955 </instruction>
 5956
 5957 <instruction>
 5958 <mnemonic>prefetcht0</mnemonic>
 5959 <def>
 5960 <pfx>aso rexw rexr rexx rexb</pfx>
 5961 <opc>0f 18 /reg=1</opc>
 5962 <opr>M</opr>
 5963 </def>
 5964 </instruction>
 5965
 5966 <instruction>
 5967 <mnemonic>prefetcht1</mnemonic>
 5968 <def>
 5969 <pfx>aso rexw rexr rexx rexb</pfx>
 5970 <opc>0f 18 /reg=2</opc>
 5971 <opr>M</opr>
 5972 </def>
 5973 </instruction>
 5974
 5975 <instruction>
 5976 <mnemonic>prefetcht2</mnemonic>
 5977 <def>
 5978 <pfx>aso rexw rexr rexx rexb</pfx>
 5979 <opc>0f 18 /reg=3</opc>
 5980 <opr>M</opr>
 5981 </def>
 5982 </instruction>
 5983
 5984 <instruction>
 5985 <mnemonic>psadbw</mnemonic>
 5986 <def>
 5987 <pfx>aso rexr rexx rexb</pfx>
 5988 <opc>sse66 0f f6</opc>
 5989 <opr>V W</opr>
 5990 </def>
 5991 <def>
 5992 <pfx>aso rexr rexx rexb</pfx>
 5993 <opc>0f f6</opc>
 5994 <opr>P Q</opr>
 5995 </def>
 5996 </instruction>
 5997
 5998 <instruction>
 5999 <mnemonic>pshufw</mnemonic>
 6000 <def>
 6001 <pfx>aso rexr rexx rexb</pfx>
 6002 <opc>0f 70</opc>
 6003 <opr>P Q Ib</opr>
 6004 </def>
 6005 </instruction>
 6006
 6007 <instruction>
 6008 <mnemonic>psllw</mnemonic>
 6009 <def>
 6010 <pfx>aso rexr rexx rexb</pfx>
 6011 <opc>sse66 0f f1</opc>
 6012 <opr>V W</opr>
 6013 </def>
 6014 <def>
 6015 <pfx>aso rexr rexx rexb</pfx>
 6016 <opc>0f f1</opc>
 6017 <opr>P Q</opr>
 6018 </def>
 6019 <def>
 6020 <pfx>rexb</pfx>
 6021 <opc>sse66 0f 71 /reg=6</opc>
 6022 <opr>VR Ib</opr>
 6023 </def>
 6024 <def>
 6025 <opc>0f 71 /reg=6</opc>
 6026 <opr>PR Ib</opr>
 6027 </def>
 6028 </instruction>
 6029
 6030 <instruction>
 6031 <mnemonic>pslld</mnemonic>
 6032 <def>
 6033 <pfx>aso rexr rexx rexb</pfx>
 6034 <opc>sse66 0f f2</opc>
 6035 <opr>V W</opr>
 6036 </def>
 6037 <def>
 6038 <pfx>aso rexr rexx rexb</pfx>
 6039 <opc>0f f2</opc>
 6040 <opr>P Q</opr>
 6041 </def>
 6042 <def>
 6043 <pfx>rexb</pfx>
 6044 <opc>sse66 0f 72 /reg=6</opc>
 6045 <opr>VR Ib</opr>
 6046 </def>
 6047 <def>
 6048 <opc>0f 72 /reg=6</opc>
 6049 <opr>PR Ib</opr>
 6050 </def>
 6051 </instruction>
 6052
 6053 <instruction>
 6054 <mnemonic>psllq</mnemonic>
 6055 <def>
 6056 <pfx>aso rexr rexx rexb</pfx>
 6057 <opc>sse66 0f f3</opc>
 6058 <opr>V W</opr>
 6059 </def>
 6060 <def>
 6061 <pfx>aso rexr rexx rexb</pfx>
 6062 <opc>0f f3</opc>
 6063 <opr>P Q</opr>
 6064 </def>
 6065 <def>
 6066 <pfx>rexb</pfx>
 6067 <opc>sse66 0f 73 /reg=6</opc>
 6068 <opr>VR Ib</opr>
 6069 </def>
 6070 <def>
 6071 <opc>0f 73 /reg=6</opc>
 6072 <opr>PR Ib</opr>
 6073 </def>
 6074 </instruction>
 6075
 6076 <instruction>
 6077 <mnemonic>psraw</mnemonic>
 6078 <def>
 6079 <pfx>aso rexr rexx rexb</pfx>
 6080 <opc>0f e1</opc>
 6081 <opr>P Q</opr>
 6082 </def>
 6083 <def>
 6084 <pfx>aso rexr rexx rexb</pfx>
 6085 <opc>sse66 0f e1</opc>
 6086 <opr>V W</opr>
 6087 </def>
 6088 <def>
 6089 <pfx>rexb</pfx>
 6090 <opc>sse66 0f 71 /reg=4</opc>
 6091 <opr>VR Ib</opr>
 6092 </def>
 6093 <def>
 6094 <opc>0f 71 /reg=4</opc>
 6095 <opr>PR Ib</opr>
 6096 </def>
 6097 </instruction>
 6098
 6099 <instruction>
 6100 <mnemonic>psrad</mnemonic>
 6101 <def>
 6102 <opc>0f 72 /reg=4</opc>
 6103 <opr>PR Ib</opr>
 6104 </def>
 6105 <def>
 6106 <pfx>aso rexr rexx rexb</pfx>
 6107 <opc>sse66 0f e2</opc>
 6108 <opr>V W</opr>
 6109 </def>
 6110 <def>
 6111 <pfx>aso rexr rexx rexb</pfx>
 6112 <opc>0f e2</opc>
 6113 <opr>P Q</opr>
 6114 </def>
 6115 <def>
 6116 <pfx>rexb</pfx>
 6117 <opc>sse66 0f 72 /reg=4</opc>
 6118 <opr>VR Ib</opr>
 6119 </def>
 6120 </instruction>
 6121
 6122 <instruction>
 6123 <mnemonic>psrlw</mnemonic>
 6124 <def>
 6125 <opc>0f 71 /reg=2</opc>
 6126 <opr>PR Ib</opr>
 6127 </def>
 6128 <def>
 6129 <pfx>aso rexr rexx rexb</pfx>
 6130 <opc>0f d1</opc>
 6131 <opr>P Q</opr>
 6132 </def>
 6133 <def>
 6134 <pfx>aso rexr rexx rexb</pfx>
 6135 <opc>sse66 0f d1</opc>
 6136 <opr>V W</opr>
 6137 </def>
 6138 <def>
 6139 <pfx>rexb</pfx>
 6140 <opc>sse66 0f 71 /reg=2</opc>
 6141 <opr>VR Ib</opr>
 6142 </def>
 6143 </instruction>
 6144
 6145 <instruction>
 6146 <mnemonic>psrld</mnemonic>
 6147 <def>
 6148 <opc>0f 72 /reg=2</opc>
 6149 <opr>PR Ib</opr>
 6150 </def>
 6151 <def>
 6152 <pfx>aso rexr rexx rexb</pfx>
 6153 <opc>0f d2</opc>
 6154 <opr>P Q</opr>
 6155 </def>
 6156 <def>
 6157 <pfx>aso rexr rexx rexb</pfx>
 6158 <opc>sse66 0f d2</opc>
 6159 <opr>V W</opr>
 6160 </def>
 6161 <def>
 6162 <pfx>rexb</pfx>
 6163 <opc>sse66 0f 72 /reg=2</opc>
 6164 <opr>VR Ib</opr>
 6165 </def>
 6166 </instruction>
 6167
 6168 <instruction>
 6169 <mnemonic>psrlq</mnemonic>
 6170 <def>
 6171 <opc>0f 73 /reg=2</opc>
 6172 <opr>PR Ib</opr>
 6173 </def>
 6174 <def>
 6175 <pfx>aso rexr rexx rexb</pfx>
 6176 <opc>0f d3</opc>
 6177 <opr>P Q</opr>
 6178 </def>
 6179 <def>
 6180 <pfx>aso rexr rexx rexb</pfx>
 6181 <opc>sse66 0f d3</opc>
 6182 <opr>V W</opr>
 6183 </def>
 6184 <def>
 6185 <pfx>rexb</pfx>
 6186 <opc>sse66 0f 73 /reg=2</opc>
 6187 <opr>VR Ib</opr>
 6188 </def>
 6189 </instruction>
 6190
 6191 <instruction>
 6192 <mnemonic>psubb</mnemonic>
 6193 <def>
 6194 <pfx>aso rexr rexx rexb</pfx>
 6195 <opc>sse66 0f f8</opc>
 6196 <opr>V W</opr>
 6197 </def>
 6198 <def>
 6199 <pfx>aso rexr rexx rexb</pfx>
 6200 <opc>0f f8</opc>
 6201 <opr>P Q</opr>
 6202 </def>
 6203 </instruction>
 6204
 6205 <instruction>
 6206 <mnemonic>psubw</mnemonic>
 6207 <def>
 6208 <pfx>aso rexr rexx rexb</pfx>
 6209 <opc>sse66 0f f9</opc>
 6210 <opr>V W</opr>
 6211 </def>
 6212 <def>
 6213 <pfx>aso rexr rexx rexb</pfx>
 6214 <opc>0f f9</opc>
 6215 <opr>P Q</opr>
 6216 </def>
 6217 </instruction>
 6218
 6219 <instruction>
 6220 <mnemonic>psubd</mnemonic>
 6221 <def>
 6222 <pfx>aso rexr rexx rexb</pfx>
 6223 <opc>0f fa</opc>
 6224 <opr>P Q</opr>
 6225 </def>
 6226 <def>
 6227 <pfx>aso rexr rexx rexb</pfx>
 6228 <opc>sse66 0f fa</opc>
 6229 <opr>V W</opr>
 6230 </def>
 6231 </instruction>
 6232
 6233 <instruction>
 6234 <mnemonic>psubsb</mnemonic>
 6235 <def>
 6236 <pfx>aso rexr rexx rexb</pfx>
 6237 <opc>0f e8</opc>
 6238 <opr>P Q</opr>
 6239 </def>
 6240 <def>
 6241 <pfx>aso rexr rexx rexb</pfx>
 6242 <opc>sse66 0f e8</opc>
 6243 <opr>V W</opr>
 6244 </def>
 6245 </instruction>
 6246
 6247 <instruction>
 6248 <mnemonic>psubsw</mnemonic>
 6249 <def>
 6250 <pfx>aso rexr rexx rexb</pfx>
 6251 <opc>0f e9</opc>
 6252 <opr>P Q</opr>
 6253 </def>
 6254 <def>
 6255 <pfx>aso rexr rexx rexb</pfx>
 6256 <opc>sse66 0f e9</opc>
 6257 <opr>V W</opr>
 6258 </def>
 6259 </instruction>
 6260
 6261 <instruction>
 6262 <mnemonic>psubusb</mnemonic>
 6263 <def>
 6264 <pfx>aso rexr rexx rexb</pfx>
 6265 <opc>0f d8</opc>
 6266 <opr>P Q</opr>
 6267 </def>
 6268 <def>
 6269 <pfx>aso rexr rexx rexb</pfx>
 6270 <opc>sse66 0f d8</opc>
 6271 <opr>V W</opr>
 6272 </def>
 6273 </instruction>
 6274
 6275 <instruction>
 6276 <mnemonic>psubusw</mnemonic>
 6277 <def>
 6278 <pfx>aso rexr rexx rexb</pfx>
 6279 <opc>0f d9</opc>
 6280 <opr>P Q</opr>
 6281 </def>
 6282 <def>
 6283 <pfx>aso rexr rexx rexb</pfx>
 6284 <opc>sse66 0f d9</opc>
 6285 <opr>V W</opr>
 6286 </def>
 6287 </instruction>
 6288
 6289 <instruction>
 6290 <mnemonic>punpckhbw</mnemonic>
 6291 <def>
 6292 <pfx>aso rexr rexx rexb</pfx>
 6293 <opc>sse66 0f 68</opc>
 6294 <opr>V W</opr>
 6295 </def>
 6296 <def>
 6297 <pfx>aso rexr rexx rexb</pfx>
 6298 <opc>0f 68</opc>
 6299 <opr>P Q</opr>
 6300 </def>
 6301 </instruction>
 6302
 6303 <instruction>
 6304 <mnemonic>punpckhwd</mnemonic>
 6305 <def>
 6306 <pfx>aso rexr rexx rexb</pfx>
 6307 <opc>sse66 0f 69</opc>
 6308 <opr>V W</opr>
 6309 </def>
 6310 <def>
 6311 <pfx>aso rexr rexx rexb</pfx>
 6312 <opc>0f 69</opc>
 6313 <opr>P Q</opr>
 6314 </def>
 6315 </instruction>
 6316
 6317 <instruction>
 6318 <mnemonic>punpckhdq</mnemonic>
 6319 <def>
 6320 <pfx>aso rexr rexx rexb</pfx>
 6321 <opc>sse66 0f 6a</opc>
 6322 <opr>V W</opr>
 6323 </def>
 6324 <def>
 6325 <pfx>aso rexr rexx rexb</pfx>
 6326 <opc>0f 6a</opc>
 6327 <opr>P Q</opr>
 6328 </def>
 6329 </instruction>
 6330
 6331 <instruction>
 6332 <mnemonic>punpcklbw</mnemonic>
 6333 <def>
 6334 <pfx>aso rexr rexx rexb</pfx>
 6335 <opc>sse66 0f 60</opc>
 6336 <opr>V W</opr>
 6337 </def>
 6338 <def>
 6339 <pfx>aso rexr rexx rexb</pfx>
 6340 <opc>0f 60</opc>
 6341 <opr>P Q</opr>
 6342 </def>
 6343 </instruction>
 6344
 6345 <instruction>
 6346 <mnemonic>punpcklwd</mnemonic>
 6347 <def>
 6348 <pfx>aso rexr rexx rexb</pfx>
 6349 <opc>sse66 0f 61</opc>
 6350 <opr>V W</opr>
 6351 </def>
 6352 <def>
 6353 <pfx>aso rexr rexx rexb</pfx>
 6354 <opc>0f 61</opc>
 6355 <opr>P Q</opr>
 6356 </def>
 6357 </instruction>
 6358
 6359 <instruction>
 6360 <mnemonic>punpckldq</mnemonic>
 6361 <def>
 6362 <pfx>aso rexr rexx rexb</pfx>
 6363 <opc>sse66 0f 62</opc>
 6364 <opr>V W</opr>
 6365 </def>
 6366 <def>
 6367 <pfx>aso rexr rexx rexb</pfx>
 6368 <opc>0f 62</opc>
 6369 <opr>P Q</opr>
 6370 </def>
 6371 </instruction>
 6372
 6373 <instruction>
 6374 <mnemonic>pi2fw</mnemonic>
 6375 <def>
 6376 <opc>0f 0f /3dnow=0c</opc>
 6377 <opr>P Q</opr>
 6378 </def>
 6379 </instruction>
 6380
 6381 <instruction>
 6382 <mnemonic>pi2fd</mnemonic>
 6383 <def>
 6384 <opc>0f 0f /3dnow=0d</opc>
 6385 <opr>P Q</opr>
 6386 </def>
 6387 </instruction>
 6388
 6389 <instruction>
 6390 <mnemonic>pf2iw</mnemonic>
 6391 <def>
 6392 <opc>0f 0f /3dnow=1c</opc>
 6393 <opr>P Q</opr>
 6394 </def>
 6395 </instruction>
 6396
 6397 <instruction>
 6398 <mnemonic>pf2id</mnemonic>
 6399 <def>
 6400 <opc>0f 0f /3dnow=1d</opc>
 6401 <opr>P Q</opr>
 6402 </def>
 6403 </instruction>
 6404
 6405 <instruction>
 6406 <mnemonic>pfnacc</mnemonic>
 6407 <def>
 6408 <opc>0f 0f /3dnow=8a</opc>
 6409 <opr>P Q</opr>
 6410 </def>
 6411 </instruction>
 6412
 6413 <instruction>
 6414 <mnemonic>pfpnacc</mnemonic>
 6415 <def>
 6416 <opc>0f 0f /3dnow=8e</opc>
 6417 <opr>P Q</opr>
 6418 </def>
 6419 </instruction>
 6420
 6421 <instruction>
 6422 <mnemonic>pfcmpge</mnemonic>
 6423 <def>
 6424 <opc>0f 0f /3dnow=90</opc>
 6425 <opr>P Q</opr>
 6426 </def>
 6427 </instruction>
 6428
 6429 <instruction>
 6430 <mnemonic>pfmin</mnemonic>
 6431 <def>
 6432 <opc>0f 0f /3dnow=94</opc>
 6433 <opr>P Q</opr>
 6434 </def>
 6435 </instruction>
 6436
 6437 <instruction>
 6438 <mnemonic>pfrcp</mnemonic>
 6439 <def>
 6440 <opc>0f 0f /3dnow=96</opc>
 6441 <opr>P Q</opr>
 6442 </def>
 6443 </instruction>
 6444
 6445 <instruction>
 6446 <mnemonic>pfrsqrt</mnemonic>
 6447 <def>
 6448 <opc>0f 0f /3dnow=97</opc>
 6449 <opr>P Q</opr>
 6450 </def>
 6451 </instruction>
 6452
 6453 <instruction>
 6454 <mnemonic>pfsub</mnemonic>
 6455 <def>
 6456 <opc>0f 0f /3dnow=9a</opc>
 6457 <opr>P Q</opr>
 6458 </def>
 6459 </instruction>
 6460
 6461 <instruction>
 6462 <mnemonic>pfadd</mnemonic>
 6463 <def>
 6464 <opc>0f 0f /3dnow=9e</opc>
 6465 <opr>P Q</opr>
 6466 </def>
 6467 </instruction>
 6468
 6469 <instruction>
 6470 <mnemonic>pfcmpgt</mnemonic>
 6471 <def>
 6472 <opc>0f 0f /3dnow=a0</opc>
 6473 <opr>P Q</opr>
 6474 </def>
 6475 </instruction>
 6476
 6477 <instruction>
 6478 <mnemonic>pfmax</mnemonic>
 6479 <def>
 6480 <opc>0f 0f /3dnow=a4</opc>
 6481 <opr>P Q</opr>
 6482 </def>
 6483 </instruction>
 6484
 6485 <instruction>
 6486 <mnemonic>pfrcpit1</mnemonic>
 6487 <def>
 6488 <opc>0f 0f /3dnow=a6</opc>
 6489 <opr>P Q</opr>
 6490 </def>
 6491 </instruction>
 6492
 6493 <instruction>
 6494 <mnemonic>pfrsqit1</mnemonic>
 6495 <def>
 6496 <opc>0f 0f /3dnow=a7</opc>
 6497 <opr>P Q</opr>
 6498 </def>
 6499 </instruction>
 6500
 6501 <instruction>
 6502 <mnemonic>pfsubr</mnemonic>
 6503 <def>
 6504 <opc>0f 0f /3dnow=aa</opc>
 6505 <opr>P Q</opr>
 6506 </def>
 6507 </instruction>
 6508
 6509 <instruction>
 6510 <mnemonic>pfacc</mnemonic>
 6511 <def>
 6512 <opc>0f 0f /3dnow=ae</opc>
 6513 <opr>P Q</opr>
 6514 </def>
 6515 </instruction>
 6516
 6517 <instruction>
 6518 <mnemonic>pfcmpeq</mnemonic>
 6519 <def>
 6520 <opc>0f 0f /3dnow=b0</opc>
 6521 <opr>P Q</opr>
 6522 </def>
 6523 </instruction>
 6524
 6525 <instruction>
 6526 <mnemonic>pfmul</mnemonic>
 6527 <def>
 6528 <opc>0f 0f /3dnow=b4</opc>
 6529 <opr>P Q</opr>
 6530 </def>
 6531 </instruction>
 6532
 6533 <instruction>
 6534 <mnemonic>pfrcpit2</mnemonic>
 6535 <def>
 6536 <opc>0f 0f /3dnow=b6</opc>
 6537 <opr>P Q</opr>
 6538 </def>
 6539 </instruction>
 6540
 6541 <instruction>
 6542 <mnemonic>pmulhrw</mnemonic>
 6543 <def>
 6544 <opc>0f 0f /3dnow=b7</opc>
 6545 <opr>P Q</opr>
 6546 </def>
 6547 </instruction>
 6548
 6549 <instruction>
 6550 <mnemonic>pswapd</mnemonic>
 6551 <def>
 6552 <opc>0f 0f /3dnow=bb</opc>
 6553 <opr>P Q</opr>
 6554 </def>
 6555 </instruction>
 6556
 6557 <instruction>
 6558 <mnemonic>pavgusb</mnemonic>
 6559 <def>
 6560 <opc>0f 0f /3dnow=bf</opc>
 6561 <opr>P Q</opr>
 6562 </def>
 6563 </instruction>
 6564
 6565 <instruction>
 6566 <mnemonic>push</mnemonic>
 6567 <def>
 6568 <opc>06</opc>
 6569 <opr>ES</opr>
 6570 <mode>inv64</mode>
 6571 </def>
 6572 <def>
 6573 <opc>0e</opc>
 6574 <opr>CS</opr>
 6575 <mode>inv64</mode>
 6576 </def>
 6577 <def>
 6578 <opc>16</opc>
 6579 <opr>SS</opr>
 6580 <mode>inv64</mode>
 6581 </def>
 6582 <def>
 6583 <opc>1e</opc>
 6584 <opr>DS</opr>
 6585 <mode>inv64</mode>
 6586 </def>
 6587 <def>
 6588 <opc>0f a8</opc>
 6589 <opr>GS</opr>
 6590 </def>
 6591 <def>
 6592 <opc>0f a0</opc>
 6593 <opr>FS</opr>
 6594 </def>
 6595 <def>
 6596 <pfx>oso rexb</pfx>
 6597 <opc>50</opc>
 6598 <opr>rAXr8</opr>
 6599 <mode>def64 depM</mode>
 6600 </def>
 6601 <def>
 6602 <pfx>oso rexb</pfx>
 6603 <opc>51</opc>
 6604 <opr>rCXr9</opr>
 6605 <mode>def64 depM</mode>
 6606 </def>
 6607 <def>
 6608 <pfx>oso rexb</pfx>
 6609 <opc>52</opc>
 6610 <opr>rDXr10</opr>
 6611 <mode>def64 depM</mode>
 6612 </def>
 6613 <def>
 6614 <pfx>oso rexb</pfx>
 6615 <opc>53</opc>
 6616 <opr>rBXr11</opr>
 6617 <mode>def64 depM</mode>
 6618 </def>
 6619 <def>
 6620 <pfx>oso rexb</pfx>
 6621 <opc>54</opc>
 6622 <opr>rSPr12</opr>
 6623 <mode>def64 depM</mode>
 6624 </def>
 6625 <def>
 6626 <pfx>oso rexb</pfx>
 6627 <opc>55</opc>
 6628 <opr>rBPr13</opr>
 6629 <mode>def64 depM</mode>
 6630 </def>
 6631 <def>
 6632 <pfx>oso rexb</pfx>
 6633 <opc>56</opc>
 6634 <opr>rSIr14</opr>
 6635 <mode>def64 depM</mode>
 6636 </def>
 6637 <def>
 6638 <pfx>oso rexb</pfx>
 6639 <opc>57</opc>
 6640 <opr>rDIr15</opr>
 6641 <mode>def64 depM</mode>
 6642 </def>
 6643 <def>
 6644 <pfx>oso</pfx>
 6645 <opc>68</opc>
 6646 <opr>Iz</opr>
 6647 <syn>cast</syn>
 6648 </def>
 6649 <def>
 6650 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6651 <opc>ff /reg=6</opc>
 6652 <opr>Ev</opr>
 6653 <mode>def64</mode>
 6654 </def>
 6655 <def>
 6656 <opc>6a</opc>
 6657 <opr>Ib</opr>
 6658 <syn>sext</syn>
 6659 </def>
 6660 </instruction>
 6661
 6662 <instruction>
 6663 <mnemonic>pusha</mnemonic>
 6664 <def>
 6665 <pfx>oso</pfx>
 6666 <opc>60 /o=16</opc>
 6667 <mode>inv64</mode>
 6668 </def>
 6669 </instruction>
 6670
 6671 <instruction>
 6672 <mnemonic>pushad</mnemonic>
 6673 <def>
 6674 <pfx>oso</pfx>
 6675 <opc>60 /o=32</opc>
 6676 <mode>inv64</mode>
 6677 </def>
 6678 </instruction>
 6679
 6680 <instruction>
 6681 <mnemonic>pushfw</mnemonic>
 6682 <def>
 6683 <pfx>oso</pfx>
 6684 <opc>9c /m=32 /o=16</opc>
 6685 <mode>def64</mode>
 6686 </def>
 6687 <def>
 6688 <pfx>oso</pfx>
 6689 <opc>9c /m=16 /o=16</opc>
 6690 <mode>def64</mode>
 6691 </def>
 6692 <def>
 6693 <pfx>oso rexw</pfx>
 6694 <opc>9c /m=64 /o=16</opc>
 6695 <mode>def64</mode>
 6696 </def>
 6697 </instruction>
 6698
 6699 <instruction>
 6700 <mnemonic>pushfd</mnemonic>
 6701 <def>
 6702 <pfx>oso</pfx>
 6703 <opc>9c /m=16 /o=32</opc>
 6704 <mode>def64</mode>
 6705 </def>
 6706 <def>
 6707 <pfx>oso</pfx>
 6708 <opc>9c /m=32 /o=32</opc>
 6709 <mode>def64</mode>
 6710 </def>
 6711 </instruction>
 6712
 6713 <instruction>
 6714 <mnemonic>pushfq</mnemonic>
 6715 <def>
 6716 <pfx>oso rexw</pfx>
 6717 <opc>9c /m=64 /o=32</opc>
 6718 <mode>def64</mode>
 6719 </def>
 6720 <def>
 6721 <pfx>oso rexw</pfx>
 6722 <opc>9c /m=64 /o=64</opc>
 6723 <mode>def64</mode>
 6724 </def>
 6725 </instruction>
 6726
 6727 <instruction>
 6728 <mnemonic>pxor</mnemonic>
 6729 <def>
 6730 <pfx>aso rexr rexx rexb</pfx>
 6731 <opc>sse66 0f ef</opc>
 6732 <opr>V W</opr>
 6733 </def>
 6734 <def>
 6735 <pfx>aso rexr rexx rexb</pfx>
 6736 <opc>0f ef</opc>
 6737 <opr>P Q</opr>
 6738 </def>
 6739 </instruction>
 6740
 6741 <instruction>
 6742 <mnemonic>rcl</mnemonic>
 6743 <def>
 6744 <pfx>aso rexw rexr rexx rexb</pfx>
 6745 <opc>c0 /reg=2</opc>
 6746 <opr>Eb Ib</opr>
 6747 </def>
 6748 <def>
 6749 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6750 <opc>c1 /reg=2</opc>
 6751 <opr>Ev Ib</opr>
 6752 </def>
 6753 <def>
 6754 <pfx>aso rexw rexr rexx rexb</pfx>
 6755 <opc>d0 /reg=2</opc>
 6756 <opr>Eb I1</opr>
 6757 </def>
 6758 <def>
 6759 <pfx>aso rexw rexr rexx rexb</pfx>
 6760 <opc>d2 /reg=2</opc>
 6761 <opr>Eb CL</opr>
 6762 <syn>cast</syn>
 6763 </def>
 6764 <def>
 6765 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6766 <opc>d3 /reg=2</opc>
 6767 <opr>Ev CL</opr>
 6768 <syn>cast</syn>
 6769 </def>
 6770 <def>
 6771 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6772 <opc>d1 /reg=2</opc>
 6773 <opr>Ev I1</opr>
 6774 </def>
 6775 </instruction>
 6776
 6777 <instruction>
 6778 <mnemonic>rcr</mnemonic>
 6779 <def>
 6780 <pfx>aso rexw rexr rexx rexb</pfx>
 6781 <opc>d0 /reg=3</opc>
 6782 <opr>Eb I1</opr>
 6783 </def>
 6784 <def>
 6785 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6786 <opc>c1 /reg=3</opc>
 6787 <opr>Ev Ib</opr>
 6788 </def>
 6789 <def>
 6790 <pfx>aso rexw rexr rexx rexb</pfx>
 6791 <opc>c0 /reg=3</opc>
 6792 <opr>Eb Ib</opr>
 6793 </def>
 6794 <def>
 6795 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6796 <opc>d1 /reg=3</opc>
 6797 <opr>Ev I1</opr>
 6798 </def>
 6799 <def>
 6800 <pfx>aso rexw rexr rexx rexb</pfx>
 6801 <opc>d2 /reg=3</opc>
 6802 <opr>Eb CL</opr>
 6803 <syn>cast</syn>
 6804 </def>
 6805 <def>
 6806 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6807 <opc>d3 /reg=3</opc>
 6808 <opr>Ev CL</opr>
 6809 <syn>cast</syn>
 6810 </def>
 6811 </instruction>
 6812
 6813 <instruction>
 6814 <mnemonic>rol</mnemonic>
 6815 <def>
 6816 <pfx>aso rexw rexr rexx rexb</pfx>
 6817 <opc>c0 /reg=0</opc>
 6818 <opr>Eb Ib</opr>
 6819 </def>
 6820 <def>
 6821 <pfx>aso rexw rexr rexx rexb</pfx>
 6822 <opc>d0 /reg=0</opc>
 6823 <opr>Eb I1</opr>
 6824 </def>
 6825 <def>
 6826 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6827 <opc>d1 /reg=0</opc>
 6828 <opr>Ev I1</opr>
 6829 </def>
 6830 <def>
 6831 <pfx>aso rexw rexr rexx rexb</pfx>
 6832 <opc>d2 /reg=0</opc>
 6833 <opr>Eb CL</opr>
 6834 <syn>cast</syn>
 6835 </def>
 6836 <def>
 6837 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6838 <opc>d3 /reg=0</opc>
 6839 <opr>Ev CL</opr>
 6840 <syn>cast</syn>
 6841 </def>
 6842 <def>
 6843 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6844 <opc>c1 /reg=0</opc>
 6845 <opr>Ev Ib</opr>
 6846 </def>
 6847 </instruction>
 6848
 6849 <instruction>
 6850 <mnemonic>ror</mnemonic>
 6851 <def>
 6852 <pfx>aso rexw rexr rexx rexb</pfx>
 6853 <opc>d0 /reg=1</opc>
 6854 <opr>Eb I1</opr>
 6855 </def>
 6856 <def>
 6857 <pfx>aso rexw rexr rexx rexb</pfx>
 6858 <opc>c0 /reg=1</opc>
 6859 <opr>Eb Ib</opr>
 6860 </def>
 6861 <def>
 6862 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6863 <opc>c1 /reg=1</opc>
 6864 <opr>Ev Ib</opr>
 6865 </def>
 6866 <def>
 6867 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6868 <opc>d1 /reg=1</opc>
 6869 <opr>Ev I1</opr>
 6870 </def>
 6871 <def>
 6872 <pfx>aso rexw rexr rexx rexb</pfx>
 6873 <opc>d2 /reg=1</opc>
 6874 <opr>Eb CL</opr>
 6875 <syn>cast</syn>
 6876 </def>
 6877 <def>
 6878 <pfx>aso oso rexw rexr rexx rexb</pfx>
 6879 <opc>d3 /reg=1</opc>
 6880 <opr>Ev CL</opr>
 6881 <syn>cast</syn>
 6882 </def>
 6883 </instruction>
 6884
 6885 <instruction>
 6886 <mnemonic>rcpps</mnemonic>
 6887 <def>
 6888 <pfx>aso rexr rexx rexb</pfx>
 6889 <opc>0f 53</opc>
 6890 <opr>V W</opr>
 6891 </def>
 6892 </instruction>
 6893
 6894 <instruction>
 6895 <mnemonic>rcpss</mnemonic>
 6896 <def>
 6897 <pfx>aso rexr rexx rexb</pfx>
 6898 <opc>ssef3 0f 53</opc>
 6899 <opr>V W</opr>
 6900 </def>
 6901 </instruction>
 6902
 6903 <instruction>
 6904 <mnemonic>rdmsr</mnemonic>
 6905 <def>
 6906 <opc>0f 32</opc>
 6907 </def>
 6908 </instruction>
 6909
 6910 <instruction>
 6911 <mnemonic>rdpmc</mnemonic>
 6912 <def>
 6913 <opc>0f 33</opc>
 6914 </def>
 6915 </instruction>
 6916
 6917 <instruction>
 6918 <mnemonic>rdtsc</mnemonic>
 6919 <def>
 6920 <opc>0f 31</opc>
 6921 </def>
 6922 </instruction>
 6923
 6924 <instruction>
 6925 <mnemonic>rdtscp</mnemonic>
 6926 <vendor>amd</vendor>
 6927 <def>
 6928 <opc>0f 01 /reg=7 /mod=11 /rm=1</opc>
 6929 </def>
 6930 </instruction>
 6931
 6932 <instruction>
 6933 <mnemonic>repne</mnemonic>
 6934 <def>
 6935 <opc>f2</opc>
 6936 </def>
 6937 </instruction>
 6938
 6939 <instruction>
 6940 <mnemonic>rep</mnemonic>
 6941 <def>
 6942 <opc>f3</opc>
 6943 </def>
 6944 </instruction>
 6945
 6946 <instruction>
 6947 <mnemonic>ret</mnemonic>
 6948 <def>
 6949 <opc>c2</opc>
 6950 <opr>Iw</opr>
 6951 </def>
 6952 <def>
 6953 <opc>c3</opc>
 6954 </def>
 6955 </instruction>
 6956
 6957 <instruction>
 6958 <mnemonic>retf</mnemonic>
 6959 <def>
 6960 <opc>ca</opc>
 6961 <opr>Iw</opr>
 6962 </def>
 6963 <def>
 6964 <opc>cb</opc>
 6965 </def>
 6966 </instruction>
 6967
 6968 <instruction>
 6969 <mnemonic>rsm</mnemonic>
 6970 <def>
 6971 <opc>0f aa</opc>
 6972 </def>
 6973 </instruction>
 6974
 6975 <instruction>
 6976 <mnemonic>rsqrtps</mnemonic>
 6977 <def>
 6978 <pfx>aso rexr rexx rexb</pfx>
 6979 <opc>0f 52</opc>
 6980 <opr>V W</opr>
 6981 </def>
 6982 </instruction>
 6983
 6984 <instruction>
 6985 <mnemonic>rsqrtss</mnemonic>
 6986 <def>
 6987 <pfx>aso rexr rexx rexb</pfx>
 6988 <opc>ssef3 0f 52</opc>
 6989 <opr>V W</opr>
 6990 </def>
 6991 </instruction>
 6992
 6993 <instruction>
 6994 <mnemonic>sahf</mnemonic>
 6995 <def>
 6996 <opc>9e</opc>
 6997 </def>
 6998 </instruction>
 6999
 7000 <instruction>
 7001 <mnemonic>sal</mnemonic>
 7002 </instruction>
 7003
 7004 <instruction>
 7005 <mnemonic>salc</mnemonic>
 7006 <def>
 7007 <opc>d6</opc>
 7008 <mode>inv64</mode>
 7009 </def>
 7010 </instruction>
 7011
 7012 <instruction>
 7013 <mnemonic>sar</mnemonic>
 7014 <def>
 7015 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7016 <opc>d1 /reg=7</opc>
 7017 <opr>Ev I1</opr>
 7018 </def>
 7019 <def>
 7020 <pfx>aso rexw rexr rexx rexb</pfx>
 7021 <opc>c0 /reg=7</opc>
 7022 <opr>Eb Ib</opr>
 7023 </def>
 7024 <def>
 7025 <pfx>aso rexw rexr rexx rexb</pfx>
 7026 <opc>d0 /reg=7</opc>
 7027 <opr>Eb I1</opr>
 7028 </def>
 7029 <def>
 7030 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7031 <opc>c1 /reg=7</opc>
 7032 <opr>Ev Ib</opr>
 7033 </def>
 7034 <def>
 7035 <pfx>aso rexw rexr rexx rexb</pfx>
 7036 <opc>d2 /reg=7</opc>
 7037 <opr>Eb CL</opr>
 7038 <syn>cast</syn>
 7039 </def>
 7040 <def>
 7041 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7042 <opc>d3 /reg=7</opc>
 7043 <opr>Ev CL</opr>
 7044 <syn>cast</syn>
 7045 </def>
 7046 </instruction>
 7047
 7048 <instruction>
 7049 <mnemonic>shl</mnemonic>
 7050 <def>
 7051 <pfx>aso rexw rexr rexx rexb</pfx>
 7052 <opc>c0 /reg=6</opc>
 7053 <opr>Eb Ib</opr>
 7054 </def>
 7055 <def>
 7056 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7057 <opc>c1 /reg=6</opc>
 7058 <opr>Ev Ib</opr>
 7059 </def>
 7060 <def>
 7061 <pfx>aso rexw rexr rexx rexb</pfx>
 7062 <opc>d0 /reg=6</opc>
 7063 <opr>Eb I1</opr>
 7064 </def>
 7065 <def>
 7066 <pfx>aso rexw rexr rexx rexb</pfx>
 7067 <opc>d2 /reg=6</opc>
 7068 <opr>Eb CL</opr>
 7069 <syn>cast</syn>
 7070 </def>
 7071 <def>
 7072 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7073 <opc>d3 /reg=6</opc>
 7074 <opr>Ev CL</opr>
 7075 <syn>cast</syn>
 7076 </def>
 7077 <def>
 7078 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7079 <opc>c1 /reg=4</opc>
 7080 <opr>Ev Ib</opr>
 7081 </def>
 7082 <def>
 7083 <pfx>aso rexr rexx rexb</pfx>
 7084 <opc>d2 /reg=4</opc>
 7085 <opr>Eb CL</opr>
 7086 <syn>cast</syn>
 7087 </def>
 7088 <def>
 7089 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7090 <opc>d1 /reg=4</opc>
 7091 <opr>Ev I1</opr>
 7092 </def>
 7093 <def>
 7094 <pfx>aso rexw rexr rexx rexb</pfx>
 7095 <opc>d0 /reg=4</opc>
 7096 <opr>Eb I1</opr>
 7097 </def>
 7098 <def>
 7099 <pfx>aso rexw rexr rexx rexb</pfx>
 7100 <opc>c0 /reg=4</opc>
 7101 <opr>Eb Ib</opr>
 7102 </def>
 7103 <def>
 7104 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7105 <opc>d3 /reg=4</opc>
 7106 <opr>Ev CL</opr>
 7107 </def>
 7108 <def>
 7109 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7110 <opc>d1 /reg=6</opc>
 7111 <opr>Ev I1</opr>
 7112 </def>
 7113 </instruction>
 7114
 7115 <instruction>
 7116 <mnemonic>shr</mnemonic>
 7117 <def>
 7118 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7119 <opc>c1 /reg=5</opc>
 7120 <opr>Ev Ib</opr>
 7121 </def>
 7122 <def>
 7123 <pfx>aso rexw rexr rexx rexb</pfx>
 7124 <opc>d2 /reg=5</opc>
 7125 <opr>Eb CL</opr>
 7126 <syn>cast</syn>
 7127 </def>
 7128 <def>
 7129 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7130 <opc>d1 /reg=5</opc>
 7131 <opr>Ev I1</opr>
 7132 </def>
 7133 <def>
 7134 <pfx>aso rexw rexr rexx rexb</pfx>
 7135 <opc>d0 /reg=5</opc>
 7136 <opr>Eb I1</opr>
 7137 </def>
 7138 <def>
 7139 <pfx>aso rexw rexr rexx rexb</pfx>
 7140 <opc>c0 /reg=5</opc>
 7141 <opr>Eb Ib</opr>
 7142 </def>
 7143 <def>
 7144 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7145 <opc>d3 /reg=5</opc>
 7146 <opr>Ev CL</opr>
 7147 <syn>cast</syn>
 7148 </def>
 7149 </instruction>
 7150
 7151 <instruction>
 7152 <mnemonic>sbb</mnemonic>
 7153 <def>
 7154 <pfx>aso rexr rexx rexb</pfx>
 7155 <opc>18</opc>
 7156 <opr>Eb Gb</opr>
 7157 </def>
 7158 <def>
 7159 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7160 <opc>19</opc>
 7161 <opr>Ev Gv</opr>
 7162 </def>
 7163 <def>
 7164 <pfx>aso rexr rexx rexb</pfx>
 7165 <opc>1a</opc>
 7166 <opr>Gb Eb</opr>
 7167 </def>
 7168 <def>
 7169 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7170 <opc>1b</opc>
 7171 <opr>Gv Ev</opr>
 7172 </def>
 7173 <def>
 7174 <opc>1c</opc>
 7175 <opr>AL Ib</opr>
 7176 </def>
 7177 <def>
 7178 <pfx>oso rexw</pfx>
 7179 <opc>1d</opc>
 7180 <opr>rAX Iz</opr>
 7181 <syn>sext</syn>
 7182 </def>
 7183 <def>
 7184 <pfx>aso rexr rexx rexb</pfx>
 7185 <opc>80 /reg=3</opc>
 7186 <opr>Eb Ib</opr>
 7187 </def>
 7188 <def>
 7189 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7190 <opc>81 /reg=3</opc>
 7191 <opr>Ev Iz</opr>
 7192 <syn>sext</syn>
 7193 </def>
 7194 <def>
 7195 <pfx>aso rexr rexx rexb</pfx>
 7196 <opc>82 /reg=3</opc>
 7197 <opr>Eb Ib</opr>
 7198 <mode>inv64</mode>
 7199 </def>
 7200 <def>
 7201 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7202 <opc>83 /reg=3</opc>
 7203 <opr>Ev Ib</opr>
 7204 <syn>sext</syn>
 7205 </def>
 7206 </instruction>
 7207
 7208 <instruction>
 7209 <mnemonic>scasb</mnemonic>
 7210 <def>
 7211 <opc>ae</opc>
 7212 </def>
 7213 </instruction>
 7214
 7215 <instruction>
 7216 <mnemonic>scasw</mnemonic>
 7217 <def>
 7218 <pfx>oso rexw</pfx>
 7219 <opc>af /o=16</opc>
 7220 </def>
 7221 </instruction>
 7222
 7223 <instruction>
 7224 <mnemonic>scasd</mnemonic>
 7225 <def>
 7226 <pfx>oso rexw</pfx>
 7227 <opc>af /o=32</opc>
 7228 </def>
 7229 </instruction>
 7230
 7231 <instruction>
 7232 <mnemonic>scasq</mnemonic>
 7233 <def>
 7234 <pfx>oso rexw</pfx>
 7235 <opc>af /o=64</opc>
 7236 </def>
 7237 </instruction>
 7238
 7239 <instruction>
 7240 <mnemonic>seto</mnemonic>
 7241 <def>
 7242 <pfx>aso rexr rexx rexb</pfx>
 7243 <opc>0f 90</opc>
 7244 <opr>Eb</opr>
 7245 </def>
 7246 </instruction>
 7247
 7248 <instruction>
 7249 <mnemonic>setno</mnemonic>
 7250 <def>
 7251 <pfx>aso rexr rexx rexb</pfx>
 7252 <opc>0f 91</opc>
 7253 <opr>Eb</opr>
 7254 </def>
 7255 </instruction>
 7256
 7257 <instruction>
 7258 <mnemonic>setb</mnemonic>
 7259 <def>
 7260 <pfx>aso rexr rexx rexb</pfx>
 7261 <opc>0f 92</opc>
 7262 <opr>Eb</opr>
 7263 </def>
 7264 </instruction>
 7265
 7266 <instruction>
 7267 <mnemonic>setnb</mnemonic>
 7268 <def>
 7269 <pfx>aso rexr rexx rexb</pfx>
 7270 <opc>0f 93</opc>
 7271 <opr>Eb</opr>
 7272 </def>
 7273 </instruction>
 7274
 7275 <instruction>
 7276 <mnemonic>setz</mnemonic>
 7277 <def>
 7278 <pfx>aso rexr rexx rexb</pfx>
 7279 <opc>0f 94</opc>
 7280 <opr>Eb</opr>
 7281 </def>
 7282 </instruction>
 7283
 7284 <instruction>
 7285 <mnemonic>setnz</mnemonic>
 7286 <def>
 7287 <pfx>aso rexr rexx rexb</pfx>
 7288 <opc>0f 95</opc>
 7289 <opr>Eb</opr>
 7290 </def>
 7291 </instruction>
 7292
 7293 <instruction>
 7294 <mnemonic>setbe</mnemonic>
 7295 <def>
 7296 <pfx>aso rexr rexx rexb</pfx>
 7297 <opc>0f 96</opc>
 7298 <opr>Eb</opr>
 7299 </def>
 7300 </instruction>
 7301
 7302 <instruction>
 7303 <mnemonic>seta</mnemonic>
 7304 <def>
 7305 <pfx>aso rexr rexx rexb</pfx>
 7306 <opc>0f 97</opc>
 7307 <opr>Eb</opr>
 7308 </def>
 7309 </instruction>
 7310
 7311 <instruction>
 7312 <mnemonic>sets</mnemonic>
 7313 <def>
 7314 <pfx>aso rexr rexx rexb</pfx>
 7315 <opc>0f 98</opc>
 7316 <opr>Eb</opr>
 7317 </def>
 7318 </instruction>
 7319
 7320 <instruction>
 7321 <mnemonic>setns</mnemonic>
 7322 <def>
 7323 <pfx>aso rexr rexx rexb</pfx>
 7324 <opc>0f 99</opc>
 7325 <opr>Eb</opr>
 7326 </def>
 7327 </instruction>
 7328
 7329 <instruction>
 7330 <mnemonic>setp</mnemonic>
 7331 <def>
 7332 <pfx>aso rexr rexx rexb</pfx>
 7333 <opc>0f 9a</opc>
 7334 <opr>Eb</opr>
 7335 </def>
 7336 </instruction>
 7337
 7338 <instruction>
 7339 <mnemonic>setnp</mnemonic>
 7340 <def>
 7341 <pfx>aso rexr rexx rexb</pfx>
 7342 <opc>0f 9b</opc>
 7343 <opr>Eb</opr>
 7344 </def>
 7345 </instruction>
 7346
 7347 <instruction>
 7348 <mnemonic>setl</mnemonic>
 7349 <def>
 7350 <pfx>aso rexr rexx rexb</pfx>
 7351 <opc>0f 9c</opc>
 7352 <opr>Eb</opr>
 7353 </def>
 7354 </instruction>
 7355
 7356 <instruction>
 7357 <mnemonic>setge</mnemonic>
 7358 <def>
 7359 <pfx>aso rexr rexx rexb</pfx>
 7360 <opc>0f 9d</opc>
 7361 <opr>Eb</opr>
 7362 </def>
 7363 </instruction>
 7364
 7365 <instruction>
 7366 <mnemonic>setle</mnemonic>
 7367 <def>
 7368 <pfx>aso rexr rexx rexb</pfx>
 7369 <opc>0f 9e</opc>
 7370 <opr>Eb</opr>
 7371 </def>
 7372 </instruction>
 7373
 7374 <instruction>
 7375 <mnemonic>setg</mnemonic>
 7376 <def>
 7377 <pfx>aso rexr rexx rexb</pfx>
 7378 <opc>0f 9f</opc>
 7379 <opr>Eb</opr>
 7380 </def>
 7381 </instruction>
 7382
 7383 <instruction>
 7384 <mnemonic>sfence</mnemonic>
 7385 <def>
 7386 <opc>0f ae /reg=7 /mod=11 /rm=0</opc>
 7387 </def>
 7388 <def>
 7389 <opc>0f ae /reg=7 /mod=11 /rm=1</opc>
 7390 </def>
 7391 <def>
 7392 <opc>0f ae /reg=7 /mod=11 /rm=2</opc>
 7393 </def>
 7394 <def>
 7395 <opc>0f ae /reg=7 /mod=11 /rm=3</opc>
 7396 </def>
 7397 <def>
 7398 <opc>0f ae /reg=7 /mod=11 /rm=4</opc>
 7399 </def>
 7400 <def>
 7401 <opc>0f ae /reg=7 /mod=11 /rm=5</opc>
 7402 </def>
 7403 <def>
 7404 <opc>0f ae /reg=7 /mod=11 /rm=6</opc>
 7405 </def>
 7406 <def>
 7407 <opc>0f ae /reg=7 /mod=11 /rm=7</opc>
 7408 </def>
 7409 </instruction>
 7410
 7411 <instruction>
 7412 <mnemonic>sgdt</mnemonic>
 7413 <def>
 7414 <pfx>aso rexr rexx rexb</pfx>
 7415 <opc>0f 01 /reg=0 /mod=!11</opc>
 7416 <opr>M</opr>
 7417 </def>
 7418 </instruction>
 7419
 7420 <instruction>
 7421 <mnemonic>shld</mnemonic>
 7422 <def>
 7423 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7424 <opc>0f a4</opc>
 7425 <opr>Ev Gv Ib</opr>
 7426 </def>
 7427 <def>
 7428 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7429 <opc>0f a5</opc>
 7430 <opr>Ev Gv CL</opr>
 7431 </def>
 7432 </instruction>
 7433
 7434 <instruction>
 7435 <mnemonic>shrd</mnemonic>
 7436 <def>
 7437 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7438 <opc>0f ac</opc>
 7439 <opr>Ev Gv Ib</opr>
 7440 </def>
 7441 <def>
 7442 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7443 <opc>0f ad</opc>
 7444 <opr>Ev Gv CL</opr>
 7445 </def>
 7446 </instruction>
 7447
 7448 <instruction>
 7449 <mnemonic>shufpd</mnemonic>
 7450 <def>
 7451 <pfx>aso rexr rexx rexb</pfx>
 7452 <opc>sse66 0f c6</opc>
 7453 <opr>V W Ib</opr>
 7454 </def>
 7455 </instruction>
 7456
 7457 <instruction>
 7458 <mnemonic>shufps</mnemonic>
 7459 <def>
 7460 <pfx>aso rexr rexx rexb</pfx>
 7461 <opc>0f c6</opc>
 7462 <opr>V W Ib</opr>
 7463 </def>
 7464 </instruction>
 7465
 7466 <instruction>
 7467 <mnemonic>sidt</mnemonic>
 7468 <def>
 7469 <pfx>aso rexr rexx rexb</pfx>
 7470 <opc>0f 01 /reg=1 /mod=!11</opc>
 7471 <opr>M</opr>
 7472 </def>
 7473 </instruction>
 7474
 7475 <instruction>
 7476 <mnemonic>sldt</mnemonic>
 7477 <def>
 7478 <pfx>aso oso rexr rexx rexb</pfx>
 7479 <opc>0f 00 /reg=0</opc>
 7480 <opr>MwRv</opr>
 7481 </def>
 7482 </instruction>
 7483
 7484 <instruction>
 7485 <mnemonic>smsw</mnemonic>
 7486 <def>
 7487 <pfx>aso rexr rexx rexb</pfx>
 7488 <opc>0f 01 /reg=4 /mod=!11</opc>
 7489 <opr>M</opr>
 7490 </def>
 7491 </instruction>
 7492
 7493 <instruction>
 7494 <mnemonic>sqrtps</mnemonic>
 7495 <def>
 7496 <pfx>aso rexr rexx rexb</pfx>
 7497 <opc>0f 51</opc>
 7498 <opr>V W</opr>
 7499 </def>
 7500 </instruction>
 7501
 7502 <instruction>
 7503 <mnemonic>sqrtpd</mnemonic>
 7504 <def>
 7505 <pfx>aso rexr rexx rexb</pfx>
 7506 <opc>sse66 0f 51</opc>
 7507 <opr>V W</opr>
 7508 </def>
 7509 </instruction>
 7510
 7511 <instruction>
 7512 <mnemonic>sqrtsd</mnemonic>
 7513 <def>
 7514 <pfx>aso rexr rexx rexb</pfx>
 7515 <opc>ssef2 0f 51</opc>
 7516 <opr>V W</opr>
 7517 </def>
 7518 </instruction>
 7519
 7520 <instruction>
 7521 <mnemonic>sqrtss</mnemonic>
 7522 <def>
 7523 <pfx>aso rexr rexx rexb</pfx>
 7524 <opc>ssef3 0f 51</opc>
 7525 <opr>V W</opr>
 7526 </def>
 7527 </instruction>
 7528
 7529 <instruction>
 7530 <mnemonic>stc</mnemonic>
 7531 <def>
 7532 <opc>f9</opc>
 7533 </def>
 7534 </instruction>
 7535
 7536 <instruction>
 7537 <mnemonic>std</mnemonic>
 7538 <def>
 7539 <opc>fd</opc>
 7540 </def>
 7541 </instruction>
 7542
 7543 <instruction>
 7544 <mnemonic>stgi</mnemonic>
 7545 <vendor>amd</vendor>
 7546 <def>
 7547 <opc>0f 01 /reg=3 /mod=11 /rm=4</opc>
 7548 </def>
 7549 </instruction>
 7550
 7551 <instruction>
 7552 <mnemonic>sti</mnemonic>
 7553 <def>
 7554 <opc>fb</opc>
 7555 </def>
 7556 </instruction>
 7557
 7558 <instruction>
 7559 <mnemonic>skinit</mnemonic>
 7560 <vendor>amd</vendor>
 7561 <def>
 7562 <opc>0f 01 /reg=3 /mod=11 /rm=6</opc>
 7563 </def>
 7564 </instruction>
 7565
 7566 <instruction>
 7567 <mnemonic>stmxcsr</mnemonic>
 7568 <def>
 7569 <pfx>aso rexw rexr rexx rexb</pfx>
 7570 <opc>0f ae /mod=11 /reg=3</opc>
 7571 <opr>Md</opr>
 7572 </def>
 7573 </instruction>
 7574
 7575 <instruction>
 7576 <mnemonic>stosb</mnemonic>
 7577 <def>
 7578 <pfx>seg</pfx>
 7579 <opc>aa</opc>
 7580 </def>
 7581 </instruction>
 7582
 7583 <instruction>
 7584 <mnemonic>stosw</mnemonic>
 7585 <def>
 7586 <pfx>seg oso rexw</pfx>
 7587 <opc>ab /o=16</opc>
 7588 </def>
 7589 </instruction>
 7590
 7591 <instruction>
 7592 <mnemonic>stosd</mnemonic>
 7593 <def>
 7594 <pfx>seg oso rexw</pfx>
 7595 <opc>ab /o=32</opc>
 7596 </def>
 7597 </instruction>
 7598
 7599 <instruction>
 7600 <mnemonic>stosq</mnemonic>
 7601 <def>
 7602 <pfx>seg oso rexw</pfx>
 7603 <opc>ab /o=64</opc>
 7604 </def>
 7605 </instruction>
 7606
 7607 <instruction>
 7608 <mnemonic>str</mnemonic>
 7609 <def>
 7610 <pfx>aso oso rexr rexx rexb</pfx>
 7611 <opc>0f 00 /reg=1</opc>
 7612 <opr>Ev</opr>
 7613 </def>
 7614 </instruction>
 7615
 7616 <instruction>
 7617 <mnemonic>sub</mnemonic>
 7618 <def>
 7619 <pfx>aso rexr rexx rexb</pfx>
 7620 <opc>28</opc>
 7621 <opr>Eb Gb</opr>
 7622 </def>
 7623 <def>
 7624 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7625 <opc>29</opc>
 7626 <opr>Ev Gv</opr>
 7627 </def>
 7628 <def>
 7629 <pfx>aso rexr rexx rexb</pfx>
 7630 <opc>2a</opc>
 7631 <opr>Gb Eb</opr>
 7632 </def>
 7633 <def>
 7634 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7635 <opc>2b</opc>
 7636 <opr>Gv Ev</opr>
 7637 </def>
 7638 <def>
 7639 <opc>2c</opc>
 7640 <opr>AL Ib</opr>
 7641 </def>
 7642 <def>
 7643 <pfx>oso rexw</pfx>
 7644 <opc>2d</opc>
 7645 <opr>rAX Iz</opr>
 7646 <syn>sext</syn>
 7647 </def>
 7648 <def>
 7649 <pfx>aso rexr rexx rexb</pfx>
 7650 <opc>80 /reg=5</opc>
 7651 <opr>Eb Ib</opr>
 7652 </def>
 7653 <def>
 7654 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7655 <opc>81 /reg=5</opc>
 7656 <opr>Ev Iz</opr>
 7657 <syn>sext</syn>
 7658 </def>
 7659 <def>
 7660 <pfx>aso rexr rexx rexb</pfx>
 7661 <opc>82 /reg=5</opc>
 7662 <opr>Eb Ib</opr>
 7663 <mode>inv64</mode>
 7664 </def>
 7665 <def>
 7666 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7667 <opc>83 /reg=5</opc>
 7668 <opr>Ev Ib</opr>
 7669 <syn>sext</syn>
 7670 </def>
 7671 </instruction>
 7672
 7673 <instruction>
 7674 <mnemonic>subpd</mnemonic>
 7675 <def>
 7676 <pfx>aso rexr rexx rexb</pfx>
 7677 <opc>sse66 0f 5c</opc>
 7678 <opr>V W</opr>
 7679 </def>
 7680 </instruction>
 7681
 7682 <instruction>
 7683 <mnemonic>subps</mnemonic>
 7684 <def>
 7685 <pfx>aso rexr rexx rexb</pfx>
 7686 <opc>0f 5c</opc>
 7687 <opr>V W</opr>
 7688 </def>
 7689 </instruction>
 7690
 7691 <instruction>
 7692 <mnemonic>subsd</mnemonic>
 7693 <def>
 7694 <pfx>aso rexr rexx rexb</pfx>
 7695 <opc>ssef2 0f 5c</opc>
 7696 <opr>V W</opr>
 7697 </def>
 7698 </instruction>
 7699
 7700 <instruction>
 7701 <mnemonic>subss</mnemonic>
 7702 <def>
 7703 <pfx>aso rexr rexx rexb</pfx>
 7704 <opc>ssef3 0f 5c</opc>
 7705 <opr>V W</opr>
 7706 </def>
 7707 </instruction>
 7708
 7709 <instruction>
 7710 <mnemonic>swapgs</mnemonic>
 7711 <def>
 7712 <opc>0f 01 /reg=7 /mod=11 /rm=0</opc>
 7713 </def>
 7714 </instruction>
 7715
 7716 <instruction>
 7717 <mnemonic>syscall</mnemonic>
 7718 <def>
 7719 <opc>0f 05</opc>
 7720 </def>
 7721 </instruction>
 7722
 7723 <instruction>
 7724 <mnemonic>sysenter</mnemonic>
 7725 <def>
 7726 <opc>0f 34</opc>
 7727 <mode>inv64</mode>
 7728 </def>
 7729 </instruction>
 7730
 7731 <instruction>
 7732 <mnemonic>sysexit</mnemonic>
 7733 <def>
 7734 <opc>0f 35</opc>
 7735 </def>
 7736 </instruction>
 7737
 7738 <instruction>
 7739 <mnemonic>sysret</mnemonic>
 7740 <def>
 7741 <opc>0f 07</opc>
 7742 </def>
 7743 </instruction>
 7744
 7745 <instruction>
 7746 <mnemonic>test</mnemonic>
 7747 <def>
 7748 <pfx>aso rexw rexr rexx rexb</pfx>
 7749 <opc>f6 /reg=0</opc>
 7750 <opr>Eb Ib</opr>
 7751 </def>
 7752 <def>
 7753 <pfx>aso rexr rexx rexb</pfx>
 7754 <opc>84</opc>
 7755 <opr>Eb Gb</opr>
 7756 </def>
 7757 <def>
 7758 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7759 <opc>85</opc>
 7760 <opr>Ev Gv</opr>
 7761 </def>
 7762 <def>
 7763 <opc>a8</opc>
 7764 <opr>AL Ib</opr>
 7765 </def>
 7766 <def>
 7767 <pfx>oso rexw</pfx>
 7768 <opc>a9</opc>
 7769 <opr>rAX Iz</opr>
 7770 <syn>sext</syn>
 7771 </def>
 7772 <def>
 7773 <pfx>aso rexw rexr rexx rexb</pfx>
 7774 <opc>f6 /reg=1</opc>
 7775 <opr>Eb Ib</opr>
 7776 </def>
 7777 <def>
 7778 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7779 <opc>f7 /reg=0</opc>
 7780 <opr>Ev Iz</opr>
 7781 <syn>sext</syn>
 7782 </def>
 7783 <def>
 7784 <pfx>aso oso rexw rexr rexx rexb</pfx>
 7785 <opc>f7 /reg=1</opc>
 7786 <opr>Ev Iz</opr>
 7787 <syn>sext</syn>
 7788 </def>
 7789 </instruction>
 7790
 7791 <instruction>
 7792 <mnemonic>ucomisd</mnemonic>
 7793 <def>
 7794 <pfx>aso rexr rexx rexb</pfx>
 7795 <opc>sse66 0f 2e</opc>
 7796 <opr>V W</opr>
 7797 </def>
 7798 </instruction>
 7799
 7800 <instruction>
 7801 <mnemonic>ucomiss</mnemonic>
 7802 <def>
 7803 <pfx>aso rexr rexx rexb</pfx>
 7804 <opc>0f 2e</opc>
 7805 <opr>V W</opr>
 7806 </def>
 7807 </instruction>
 7808
 7809 <instruction>
 7810 <mnemonic>ud2</mnemonic>
 7811 <def>
 7812 <opc>0f 0b</opc>
 7813 </def>
 7814 </instruction>
 7815
 7816 <instruction>
 7817 <mnemonic>unpckhpd</mnemonic>
 7818 <def>
 7819 <pfx>aso rexr rexx rexb</pfx>
 7820 <opc>sse66 0f 15</opc>
 7821 <opr>V W</opr>
 7822 </def>
 7823 </instruction>
 7824
 7825 <instruction>
 7826 <mnemonic>unpckhps</mnemonic>
 7827 <def>
 7828 <pfx>aso rexr rexx rexb</pfx>
 7829 <opc>0f 15</opc>
 7830 <opr>V W</opr>
 7831 </def>
 7832 </instruction>
 7833
 7834 <instruction>
 7835 <mnemonic>unpcklps</mnemonic>
 7836 <def>
 7837 <pfx>aso rexr rexx rexb</pfx>
 7838 <opc>0f 14</opc>
 7839 <opr>V W</opr>
 7840 </def>
 7841 </instruction>
 7842
 7843 <instruction>
 7844 <mnemonic>unpcklpd</mnemonic>
 7845 <def>
 7846 <pfx>aso rexr rexx rexb</pfx>
 7847 <opc>sse66 0f 14</opc>
 7848 <opr>V W</opr>
 7849 </def>
 7850 </instruction>
 7851
 7852 <instruction>
 7853 <mnemonic>verr</mnemonic>
 7854 <def>
 7855 <pfx>aso rexr rexx rexb</pfx>
 7856 <opc>0f 00 /reg=4</opc>
 7857 <opr>Ew</opr>
 7858 </def>
 7859 </instruction>
 7860
 7861 <instruction>
 7862 <mnemonic>verw</mnemonic>
 7863 <def>
 7864 <pfx>aso rexr rexx rexb</pfx>
 7865 <opc>0f 00 /reg=5</opc>
 7866 <opr>Ew</opr>
 7867 </def>
 7868 </instruction>
 7869
 7870 <instruction>
 7871 <mnemonic>vmcall</mnemonic>
 7872 <vendor>intel</vendor>
 7873 <def>
 7874 <opc>0f 01 /reg=0 /mod=11 /rm=1</opc>
 7875 </def>
 7876 </instruction>
 7877
 7878 <instruction>
 7879 <mnemonic>vmclear</mnemonic>
 7880 <vendor>intel</vendor>
 7881 <def>
 7882 <pfx>aso rexr rexx rexb</pfx>
 7883 <opc>sse66 0f c7 /reg=6</opc>
 7884 <opr>Mq</opr>
 7885 </def>
 7886 </instruction>
 7887
 7888 <instruction>
 7889 <mnemonic>vmxon</mnemonic>
 7890 <vendor>intel</vendor>
 7891 <def>
 7892 <pfx>aso rexr rexx rexb</pfx>
 7893 <opc>ssef3 0f c7 /reg=6</opc>
 7894 <opr>Mq</opr>
 7895 </def>
 7896 </instruction>
 7897
 7898 <instruction>
 7899 <mnemonic>vmptrld</mnemonic>
 7900 <vendor>intel</vendor>
 7901 <def>
 7902 <pfx>aso rexr rexx rexb</pfx>
 7903 <opc>0f c7 /reg=6</opc>
 7904 <opr>Mq</opr>
 7905 </def>
 7906 </instruction>
 7907
 7908 <instruction>
 7909 <mnemonic>vmptrst</mnemonic>
 7910 <vendor>intel</vendor>
 7911 <def>
 7912 <pfx>aso rexr rexx rexb</pfx>
 7913 <opc>0f c7 /reg=7</opc>
 7914 <opr>Mq</opr>
 7915 </def>
 7916 </instruction>
 7917
 7918 <instruction>
 7919 <mnemonic>vmlaunch</mnemonic>
 7920 <vendor>intel</vendor>
 7921 <def>
 7922 <opc>0f 01 /reg=0 /mod=11 /rm=2</opc>
 7923 </def>
 7924 </instruction>
 7925
 7926 <instruction>
 7927 <mnemonic>vmresume</mnemonic>
 7928 <vendor>intel</vendor>
 7929 <def>
 7930 <opc>0f 01 /reg=0 /mod=11 /rm=3</opc>
 7931 </def>
 7932 </instruction>
 7933
 7934 <instruction>
 7935 <mnemonic>vmxoff</mnemonic>
 7936 <vendor>intel</vendor>
 7937 <def>
 7938 <opc>0f 01 /reg=0 /mod=11 /rm=4</opc>
 7939 </def>
 7940 </instruction>
 7941
 7942 <instruction>
 7943 <mnemonic>vmread</mnemonic>
 7944 <vendor>intel</vendor>
 7945 <def>
 7946 <pfx>aso rexr rexx rexb</pfx>
 7947 <opc>0f 78 /m=16</opc>
 7948 <opr>Ed Gd</opr>
 7949 <mode>def64</mode>
 7950 </def>
 7951 <def>
 7952 <pfx>aso rexr rexx rexb</pfx>
 7953 <opc>0f 78 /m=32</opc>
 7954 <opr>Ed Gd</opr>
 7955 <mode>def64</mode>
 7956 </def>
 7957 <def>
 7958 <pfx>aso rexr rexx rexb</pfx>
 7959 <opc>0f 78 /m=64</opc>
 7960 <opr>Eq Gq</opr>
 7961 <mode>def64</mode>
 7962 </def>
 7963 </instruction>
 7964
 7965 <instruction>
 7966 <mnemonic>vmwrite</mnemonic>
 7967 <vendor>intel</vendor>
 7968 <def>
 7969 <pfx>aso rexr rexx rexb</pfx>
 7970 <opc>0f 79 /m=16</opc>
 7971 <opr>Gd Ed</opr>
 7972 <mode>def64</mode>
 7973 </def>
 7974 <def>
 7975 <pfx>aso rexr rexx rexb</pfx>
 7976 <opc>0f 79 /m=32</opc>
 7977 <opr>Gd Ed</opr>
 7978 <mode>def64</mode>
 7979 </def>
 7980 <def>
 7981 <pfx>aso rexr rexx rexb</pfx>
 7982 <opc>0f 79 /m=64</opc>
 7983 <opr>Gq Eq</opr>
 7984 <mode>def64</mode>
 7985 </def>
 7986 </instruction>
 7987
 7988 <instruction>
 7989 <mnemonic>vmrun</mnemonic>
 7990 <vendor>amd</vendor>
 7991 <def>
 7992 <opc>0f 01 /reg=3 /mod=11 /rm=0</opc>
 7993 </def>
 7994 </instruction>
 7995
 7996 <instruction>
 7997 <mnemonic>vmmcall</mnemonic>
 7998 <vendor>amd</vendor>
 7999 <def>
 8000 <opc>0f 01 /reg=3 /mod=11 /rm=1</opc>
 8001 </def>
 8002 </instruction>
 8003
 8004 <instruction>
 8005 <mnemonic>vmload</mnemonic>
 8006 <vendor>amd</vendor>
 8007 <def>
 8008 <opc>0f 01 /reg=3 /mod=11 /rm=2</opc>
 8009 </def>
 8010 </instruction>
 8011
 8012 <instruction>
 8013 <mnemonic>vmsave</mnemonic>
 8014 <vendor>amd</vendor>
 8015 <def>
 8016 <opc>0f 01 /reg=3 /mod=11 /rm=3</opc>
 8017 </def>
 8018 </instruction>
 8019
 8020 <instruction>
 8021 <mnemonic>wait</mnemonic>
 8022 <def>
 8023 <opc>9b</opc>
 8024 </def>
 8025 </instruction>
 8026
 8027 <instruction>
 8028 <mnemonic>wbinvd</mnemonic>
 8029 <def>
 8030 <opc>0f 09</opc>
 8031 </def>
 8032 </instruction>
 8033
 8034 <instruction>
 8035 <mnemonic>wrmsr</mnemonic>
 8036 <def>
 8037 <opc>0f 30</opc>
 8038 </def>
 8039 </instruction>
 8040
 8041 <instruction>
 8042 <mnemonic>xadd</mnemonic>
 8043 <def>
 8044 <pfx>aso oso rexr rexx rexb</pfx>
 8045 <opc>0f c0</opc>
 8046 <opr>Eb Gb</opr>
 8047 </def>
 8048 <def>
 8049 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8050 <opc>0f c1</opc>
 8051 <opr>Ev Gv</opr>
 8052 </def>
 8053 </instruction>
 8054
 8055 <instruction>
 8056 <mnemonic>xchg</mnemonic>
 8057 <def>
 8058 <pfx>aso rexr rexx rexb</pfx>
 8059 <opc>86</opc>
 8060 <opr>Eb Gb</opr>
 8061 </def>
 8062 <def>
 8063 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8064 <opc>87</opc>
 8065 <opr>Ev Gv</opr>
 8066 </def>
 8067 <def>
 8068 <pfx>oso rexw rexb</pfx>
 8069 <opc>90</opc>
 8070 <opr>rAXr8 rAX</opr>
 8071 </def>
 8072 <def>
 8073 <pfx>oso rexw rexb</pfx>
 8074 <opc>91</opc>
 8075 <opr>rCXr9 rAX</opr>
 8076 </def>
 8077 <def>
 8078 <pfx>oso rexw rexb</pfx>
 8079 <opc>92</opc>
 8080 <opr>rDXr10 rAX</opr>
 8081 </def>
 8082 <def>
 8083 <pfx>oso rexw rexb</pfx>
 8084 <opc>93</opc>
 8085 <opr>rBXr11 rAX</opr>
 8086 </def>
 8087 <def>
 8088 <pfx>oso rexw rexb</pfx>
 8089 <opc>94</opc>
 8090 <opr>rSPr12 rAX</opr>
 8091 </def>
 8092 <def>
 8093 <pfx>oso rexw rexb</pfx>
 8094 <opc>95</opc>
 8095 <opr>rBPr13 rAX</opr>
 8096 </def>
 8097 <def>
 8098 <pfx>oso rexw rexb</pfx>
 8099 <opc>96</opc>
 8100 <opr>rSIr14 rAX</opr>
 8101 </def>
 8102 <def>
 8103 <pfx>oso rexw rexb</pfx>
 8104 <opc>97</opc>
 8105 <opr>rDIr15 rAX</opr>
 8106 </def>
 8107 </instruction>
 8108
 8109 <instruction>
 8110 <mnemonic>xlatb</mnemonic>
 8111 <def>
 8112 <pfx>rexw</pfx>
 8113 <opc>d7</opc>
 8114 </def>
 8115 </instruction>
 8116
 8117 <instruction>
 8118 <mnemonic>xor</mnemonic>
 8119 <def>
 8120 <pfx>aso rexr rexx rexb</pfx>
 8121 <opc>30</opc>
 8122 <opr>Eb Gb</opr>
 8123 </def>
 8124 <def>
 8125 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8126 <opc>31</opc>
 8127 <opr>Ev Gv</opr>
 8128 </def>
 8129 <def>
 8130 <pfx>aso rexr rexx rexb</pfx>
 8131 <opc>32</opc>
 8132 <opr>Gb Eb</opr>
 8133 </def>
 8134 <def>
 8135 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8136 <opc>33</opc>
 8137 <opr>Gv Ev</opr>
 8138 </def>
 8139 <def>
 8140 <opc>34</opc>
 8141 <opr>AL Ib</opr>
 8142 </def>
 8143 <def>
 8144 <pfx>oso rexw</pfx>
 8145 <opc>35</opc>
 8146 <opr>rAX Iz</opr>
 8147 <syn>sext</syn>
 8148 </def>
 8149 <def>
 8150 <pfx>aso rexr rexx rexb</pfx>
 8151 <opc>80 /reg=6</opc>
 8152 <opr>Eb Ib</opr>
 8153 </def>
 8154 <def>
 8155 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8156 <opc>81 /reg=6</opc>
 8157 <opr>Ev Iz</opr>
 8158 <syn>sext</syn>
 8159 </def>
 8160 <def>
 8161 <pfx>aso rexr rexx rexb</pfx>
 8162 <opc>82 /reg=6</opc>
 8163 <opr>Eb Ib</opr>
 8164 <mode>inv64</mode>
 8165 </def>
 8166 <def>
 8167 <pfx>aso oso rexw rexr rexx rexb</pfx>
 8168 <opc>83 /reg=6</opc>
 8169 <opr>Ev Ib</opr>
 8170 <syn>sext</syn>
 8171 </def>
 8172 </instruction>
 8173
 8174 <instruction>
 8175 <mnemonic>xorpd</mnemonic>
 8176 <def>
 8177 <pfx>aso rexr rexx rexb</pfx>
 8178 <opc>sse66 0f 57</opc>
 8179 <opr>V W</opr>
 8180 </def>
 8181 </instruction>
 8182
 8183 <instruction>
 8184 <mnemonic>xorps</mnemonic>
 8185 <def>
 8186 <pfx>aso rexr rexx rexb</pfx>
 8187 <opc>0f 57</opc>
 8188 <opr>V W</opr>
 8189 </def>
 8190 </instruction>
 8191
 8192 <instruction>
 8193 <mnemonic>xcryptecb</mnemonic>
 8194 <def>
 8195 <opc>0f a7 /mod=11 /rm=0 /reg=1</opc>
 8196 </def>
 8197 </instruction>
 8198
 8199 <instruction>
 8200 <mnemonic>xcryptcbc</mnemonic>
 8201 <def>
 8202 <opc>0f a7 /mod=11 /rm=0 /reg=2</opc>
 8203 </def>
 8204 </instruction>
 8205
 8206 <instruction>
 8207 <mnemonic>xcryptctr</mnemonic>
 8208 <def>
 8209 <opc>0f a7 /mod=11 /rm=0 /reg=3</opc>
 8210 </def>
 8211 </instruction>
 8212
 8213 <instruction>
 8214 <mnemonic>xcryptcfb</mnemonic>
 8215 <def>
 8216 <opc>0f a7 /mod=11 /rm=0 /reg=4</opc>
 8217 </def>
 8218 </instruction>
 8219
 8220 <instruction>
 8221 <mnemonic>xcryptofb</mnemonic>
 8222 <def>
 8223 <opc>0f a7 /mod=11 /rm=0 /reg=5</opc>
 8224 </def>
 8225 </instruction>
 8226
 8227 <instruction>
 8228 <mnemonic>xsha1</mnemonic>
 8229 <def>
 8230 <opc>0f a6 /mod=11 /rm=0 /reg=1</opc>
 8231 </def>
 8232 </instruction>
 8233
 8234 <instruction>
 8235 <mnemonic>xsha256</mnemonic>
 8236 <def>
 8237 <opc>0f a6 /mod=11 /rm=0 /reg=2</opc>
 8238 </def>
 8239 </instruction>
 8240
 8241 <instruction>
 8242 <mnemonic>xstore</mnemonic>
 8243 <def>
 8244 <opc>0f a7 /mod=11 /rm=0 /reg=0</opc>
 8245 </def>
 8246 </instruction>
 8247
 8248 <instruction>
 8249 <mnemonic>db</mnemonic>
 8250 </instruction>
 8251
 8252 <!--
 8253 SSE 2
 8254 -->
 8255
 8256 <instruction>
 8257 <mnemonic>movdqa</mnemonic>
 8258 <def>
 8259 <pfx>aso rexr rexx rexb</pfx>
 8260 <opc>sse66 0f 7f</opc>
 8261 <opr>W V</opr>
 8262 </def>
 8263 <def>
 8264 <pfx>aso rexr rexx rexb</pfx>
 8265 <opc>sse66 0f 6f</opc>
 8266 <opr>V W</opr>
 8267 </def>
 8268 </instruction>
 8269
 8270 <instruction>
 8271 <mnemonic>movdq2q</mnemonic>
 8272 <def>
 8273 <pfx>aso rexb</pfx>
 8274 <opc>ssef2 0f d6</opc>
 8275 <opr>P VR</opr>
 8276 </def>
 8277 </instruction>
 8278
 8279 <instruction>
 8280 <mnemonic>movdqu</mnemonic>
 8281 <def>
 8282 <pfx>aso rexr rexx rexb</pfx>
 8283 <opc>ssef3 0f 6f</opc>
 8284 <opr>V W</opr>
 8285 </def>
 8286 <def>
 8287 <pfx>aso rexr rexx rexb</pfx>
 8288 <opc>ssef3 0f 7f</opc>
 8289 <opr>W V</opr>
 8290 </def>
 8291 </instruction>
 8292
 8293 <instruction>
 8294 <mnemonic>movq2dq</mnemonic>
 8295 <def>
 8296 <pfx>aso</pfx>
 8297 <opc>ssef3 0f d6</opc>
 8298 <opr>V PR</opr>
 8299 </def>
 8300 </instruction>
 8301
 8302 <instruction>
 8303 <mnemonic>paddq</mnemonic>
 8304 <def>
 8305 <pfx>aso rexr rexx rexb</pfx>
 8306 <opc>0f d4</opc>
 8307 <opr>P Q</opr>
 8308 </def>
 8309 <def>
 8310 <pfx>aso rexr rexx rexb</pfx>
 8311 <opc>sse66 0f d4</opc>
 8312 <opr>V W</opr>
 8313 </def>
 8314 </instruction>
 8315
 8316 <instruction>
 8317 <mnemonic>psubq</mnemonic>
 8318 <def>
 8319 <pfx>aso rexr rexx rexb</pfx>
 8320 <opc>sse66 0f fb</opc>
 8321 <opr>V W</opr>
 8322 </def>
 8323 <def>
 8324 <pfx>aso rexr rexx rexb</pfx>
 8325 <opc>0f fb</opc>
 8326 <opr>P Q</opr>
 8327 </def>
 8328 </instruction>
 8329
 8330 <instruction>
 8331 <mnemonic>pmuludq</mnemonic>
 8332 <def>
 8333 <pfx>aso rexr rexx rexb</pfx>
 8334 <opc>0f f4</opc>
 8335 <opr>P Q</opr>
 8336 </def>
 8337 <def>
 8338 <pfx>aso rexr rexx rexb</pfx>
 8339 <opc>sse66 0f f4</opc>
 8340 <opr>V W</opr>
 8341 </def>
 8342 </instruction>
 8343
 8344 <instruction>
 8345 <mnemonic>pshufhw</mnemonic>
 8346 <def>
 8347 <pfx>aso rexr rexx rexb</pfx>
 8348 <opc>ssef3 0f 70</opc>
 8349 <opr>V W Ib</opr>
 8350 </def>
 8351 </instruction>
 8352
 8353 <instruction>
 8354 <mnemonic>pshuflw</mnemonic>
 8355 <def>
 8356 <pfx>aso rexr rexx rexb</pfx>
 8357 <opc>ssef2 0f 70</opc>
 8358 <opr>V W Ib</opr>
 8359 </def>
 8360 </instruction>
 8361
 8362 <instruction>
 8363 <mnemonic>pshufd</mnemonic>
 8364 <def>
 8365 <pfx>aso rexr rexx rexb</pfx>
 8366 <opc>sse66 0f 70</opc>
 8367 <opr>V W Ib</opr>
 8368 </def>
 8369 </instruction>
 8370
 8371 <instruction>
 8372 <mnemonic>pslldq</mnemonic>
 8373 <def>
 8374 <pfx>rexb</pfx>
 8375 <opc>sse66 0f 73 /reg=7</opc>
 8376 <opr>VR Ib</opr>
 8377 </def>
 8378 </instruction>
 8379
 8380 <instruction>
 8381 <mnemonic>psrldq</mnemonic>
 8382 <def>
 8383 <pfx>rexb</pfx>
 8384 <opc>sse66 0f 73 /reg=3</opc>
 8385 <opr>VR Ib</opr>
 8386 </def>
 8387 </instruction>
 8388
 8389 <instruction>
 8390 <mnemonic>punpckhqdq</mnemonic>
 8391 <def>
 8392 <pfx>aso rexr rexx rexb</pfx>
 8393 <opc>sse66 0f 6d</opc>
 8394 <opr>V W</opr>
 8395 </def>
 8396 </instruction>
 8397
 8398 <instruction>
 8399 <mnemonic>punpcklqdq</mnemonic>
 8400 <def>
 8401 <pfx>aso rexr rexx rexb</pfx>
 8402 <opc>sse66 0f 6c</opc>
 8403 <opr>V W</opr>
 8404 </def>
 8405 </instruction>
 8406
 8407 <!--
 8408 SSE 3
 8409 -->
 8410
 8411 <instruction>
 8412 <mnemonic>addsubpd</mnemonic>
 8413 <def>
 8414 <pfx>aso rexr rexx rexb</pfx>
 8415 <opc>sse66 0f d0</opc>
 8416 <opr>V W</opr>
 8417 </def>
 8418 </instruction>
 8419
 8420 <instruction>
 8421 <mnemonic>addsubps</mnemonic>
 8422 <def>
 8423 <pfx>aso rexr rexx rexb</pfx>
 8424 <opc>ssef2 0f d0</opc>
 8425 <opr>V W</opr>
 8426 </def>
 8427 </instruction>
 8428
 8429 <instruction>
 8430 <mnemonic>haddpd</mnemonic>
 8431 <def>
 8432 <pfx>aso rexr rexx rexb</pfx>
 8433 <opc>sse66 0f 7c</opc>
 8434 <opr>V W</opr>
 8435 </def>
 8436 </instruction>
 8437
 8438 <instruction>
 8439 <mnemonic>haddps</mnemonic>
 8440 <def>
 8441 <pfx>aso rexr rexx rexb</pfx>
 8442 <opc>ssef2 0f 7c</opc>
 8443 <opr>V W</opr>
 8444 </def>
 8445 </instruction>
 8446
 8447 <instruction>
 8448 <mnemonic>hsubpd</mnemonic>
 8449 <def>
 8450 <pfx>aso rexr rexx rexb</pfx>
 8451 <opc>sse66 0f 7d</opc>
 8452 <opr>V W</opr>
 8453 </def>
 8454 </instruction>
 8455
 8456 <instruction>
 8457 <mnemonic>hsubps</mnemonic>
 8458 <def>
 8459 <pfx>aso rexr rexx rexb</pfx>
 8460 <opc>ssef2 0f 7d</opc>
 8461 <opr>V W</opr>
 8462 </def>
 8463 </instruction>
 8464
 8465 <instruction>
 8466 <mnemonic>movddup</mnemonic>
 8467 <def>
 8468 <pfx>aso rexr rexx rexb</pfx>
 8469 <opc>ssef2 0f 12 /mod=11</opc>
 8470 <opr>V W</opr>
 8471 </def>
 8472 <def>
 8473 <pfx>aso rexr rexx rexb</pfx>
 8474 <opc>ssef2 0f 12 /mod=!11</opc>
 8475 <opr>V W</opr>
 8476 </def>
 8477 </instruction>
 8478
 8479 <instruction>
 8480 <mnemonic>movshdup</mnemonic>
 8481 <def>
 8482 <pfx>aso rexr rexx rexb</pfx>
 8483 <opc>ssef3 0f 16 /mod=11</opc>
 8484 <opr>V W</opr>
 8485 </def>
 8486 <def>
 8487 <pfx>aso rexr rexx rexb</pfx>
 8488 <opc>ssef3 0f 16 /mod=!11</opc>
 8489 <opr>V W</opr>
 8490 </def>
 8491 </instruction>
 8492
 8493 <instruction>
 8494 <mnemonic>movsldup</mnemonic>
 8495 <def>
 8496 <pfx>aso rexr rexx rexb</pfx>
 8497 <opc>ssef3 0f 12 /mod=11</opc>
 8498 <opr>V W</opr>
 8499 </def>
 8500 <def>
 8501 <pfx>aso rexr rexx rexb</pfx>
 8502 <opc>ssef3 0f 12 /mod=!11</opc>
 8503 <opr>V W</opr>
 8504 </def>
 8505 </instruction>
 8506
 8507 <!--
 8508 SSSE 3
 8509 -->
 8510
 8511 <instruction>
 8512 <mnemonic>pabsb</mnemonic>
 8513 <def>
 8514 <pfx>aso rexr rexx rexb</pfx>
 8515 <opc>0f 38 1c</opc>
 8516 <opr>P Q</opr>
 8517 </def>
 8518 <def>
 8519 <pfx>aso rexr rexx rexb</pfx>
 8520 <opc>sse66 0f 38 1c</opc>
 8521 <opr>V W</opr>
 8522 </def>
 8523 </instruction>
 8524
 8525 <instruction>
 8526 <mnemonic>pabsw</mnemonic>
 8527 <def>
 8528 <pfx>aso rexr rexx rexb</pfx>
 8529 <opc>0f 38 1d</opc>
 8530 <opr>P Q</opr>
 8531 </def>
 8532 <def>
 8533 <pfx>aso rexr rexx rexb</pfx>
 8534 <opc>sse66 0f 38 1d</opc>
 8535 <opr>V W</opr>
 8536 </def>
 8537 </instruction>
 8538
 8539 <instruction>
 8540 <mnemonic>pabsd</mnemonic>
 8541 <def>
 8542 <pfx>aso rexr rexx rexb</pfx>
 8543 <opc>0f 38 1e</opc>
 8544 <opr>P Q</opr>
 8545 </def>
 8546 <def>
 8547 <pfx>aso rexr rexx rexb</pfx>
 8548 <opc>sse66 0f 38 1e</opc>
 8549 <opr>V W</opr>
 8550 </def>
 8551 </instruction>
 8552
 8553 <instruction>
 8554 <mnemonic>psignb</mnemonic>
 8555 <def>
 8556 <pfx>aso rexr rexx rexb</pfx>
 8557 <opc>0f 38 00</opc>
 8558 <opr>P Q</opr>
 8559 </def>
 8560 <def>
 8561 <pfx>aso rexr rexx rexb</pfx>
 8562 <opc>sse66 0f 38 00</opc>
 8563 <opr>V W</opr>
 8564 </def>
 8565 </instruction>
 8566
 8567 <instruction>
 8568 <mnemonic>phaddw</mnemonic>
 8569 <def>
 8570 <pfx>aso rexr rexx rexb</pfx>
 8571 <opc>0f 38 01</opc>
 8572 <opr>P Q</opr>
 8573 </def>
 8574 <def>
 8575 <pfx>aso rexr rexx rexb</pfx>
 8576 <opc>sse66 0f 38 01</opc>
 8577 <opr>V W</opr>
 8578 </def>
 8579 </instruction>
 8580
 8581 <instruction>
 8582 <mnemonic>phaddd</mnemonic>
 8583 <def>
 8584 <pfx>aso rexr rexx rexb</pfx>
 8585 <opc>0f 38 02</opc>
 8586 <opr>P Q</opr>
 8587 </def>
 8588 <def>
 8589 <pfx>aso rexr rexx rexb</pfx>
 8590 <opc>sse66 0f 38 02</opc>
 8591 <opr>V W</opr>
 8592 </def>
 8593 </instruction>
 8594
 8595 <instruction>
 8596 <mnemonic>phaddsw</mnemonic>
 8597 <def>
 8598 <pfx>aso rexr rexx rexb</pfx>
 8599 <opc>0f 38 03</opc>
 8600 <opr>P Q</opr>
 8601 </def>
 8602 <def>
 8603 <pfx>aso rexr rexx rexb</pfx>
 8604 <opc>sse66 0f 38 03</opc>
 8605 <opr>V W</opr>
 8606 </def>
 8607 </instruction>
 8608
 8609 <instruction>
 8610 <mnemonic>pmaddubsw</mnemonic>
 8611 <def>
 8612 <pfx>aso rexr rexx rexb</pfx>
 8613 <opc>0f 38 04</opc>
 8614 <opr>P Q</opr>
 8615 </def>
 8616 <def>
 8617 <pfx>aso rexr rexx rexb</pfx>
 8618 <opc>sse66 0f 38 04</opc>
 8619 <opr>V W</opr>
 8620 </def>
 8621 </instruction>
 8622
 8623 <instruction>
 8624 <mnemonic>phsubw</mnemonic>
 8625 <def>
 8626 <pfx>aso rexr rexx rexb</pfx>
 8627 <opc>0f 38 05</opc>
 8628 <opr>P Q</opr>
 8629 </def>
 8630 <def>
 8631 <pfx>aso rexr rexx rexb</pfx>
 8632 <opc>sse66 0f 38 05</opc>
 8633 <opr>V W</opr>
 8634 </def>
 8635 </instruction>
 8636
 8637 <instruction>
 8638 <mnemonic>phsubd</mnemonic>
 8639 <def>
 8640 <pfx>aso rexr rexx rexb</pfx>
 8641 <opc>0f 38 06</opc>
 8642 <opr>P Q</opr>
 8643 </def>
 8644 <def>
 8645 <pfx>aso rexr rexx rexb</pfx>
 8646 <opc>sse66 0f 38 06</opc>
 8647 <opr>V W</opr>
 8648 </def>
 8649 </instruction>
 8650
 8651 <instruction>
 8652 <mnemonic>phsubsw</mnemonic>
 8653 <def>
 8654 <pfx>aso rexr rexx rexb</pfx>
 8655 <opc>0f 38 07</opc>
 8656 <opr>P Q</opr>
 8657 </def>
 8658 <def>
 8659 <pfx>aso rexr rexx rexb</pfx>
 8660 <opc>sse66 0f 38 07</opc>
 8661 <opr>V W</opr>
 8662 </def>
 8663 </instruction>
 8664
 8665 <instruction>
 8666 <mnemonic>psignb</mnemonic>
 8667 <def>
 8668 <pfx>aso rexr rexx rexb</pfx>
 8669 <opc>0f 38 08</opc>
 8670 <opr>P Q</opr>
 8671 </def>
 8672 <def>
 8673 <pfx>aso rexr rexx rexb</pfx>
 8674 <opc>sse66 0f 38 08</opc>
 8675 <opr>V W</opr>
 8676 </def>
 8677 </instruction>
 8678
 8679 <instruction>
 8680 <mnemonic>psignd</mnemonic>
 8681 <def>
 8682 <pfx>aso rexr rexx rexb</pfx>
 8683 <opc>0f 38 0a</opc>
 8684 <opr>P Q</opr>
 8685 </def>
 8686 <def>
 8687 <pfx>aso rexr rexx rexb</pfx>
 8688 <opc>sse66 0f 38 0a</opc>
 8689 <opr>V W</opr>
 8690 </def>
 8691 </instruction>
 8692
 8693 <instruction>
 8694 <mnemonic>psignw</mnemonic>
 8695 <def>
 8696 <pfx>aso rexr rexx rexb</pfx>
 8697 <opc>0f 38 09</opc>
 8698 <opr>P Q</opr>
 8699 </def>
 8700 <def>
 8701 <pfx>aso rexr rexx rexb</pfx>
 8702 <opc>sse66 0f 38 09</opc>
 8703 <opr>V W</opr>
 8704 </def>
 8705 </instruction>
 8706
 8707 <instruction>
 8708 <mnemonic>pmulhrsw</mnemonic>
 8709 <def>
 8710 <pfx>aso rexr rexx rexb</pfx>
 8711 <opc>0f 38 0b</opc>
 8712 <opr>P Q</opr>
 8713 </def>
 8714 <def>
 8715 <pfx>aso rexr rexx rexb</pfx>
 8716 <opc>sse66 0f 38 0b</opc>
 8717 <opr>V W</opr>
 8718 </def>
 8719 </instruction>
 8720
 8721 <instruction>
 8722 <mnemonic>palignr</mnemonic>
 8723 <def>
 8724 <pfx>aso rexr rexx rexb</pfx>
 8725 <opc>0f 3a 0f</opc>
 8726 <opr>P Q Ib</opr>
 8727 </def>
 8728 <def>
 8729 <pfx>aso rexr rexx rexb</pfx>
 8730 <opc>sse66 0f 3a 0f</opc>
 8731 <opr>V W Ib</opr>
 8732 </def>
 8733 </instruction>
 8734
 8735 <!--
 8736 SSE 4.1
 8737 -->
 8738
 8739 <instruction>
 8740 <mnemonic>pblendvb</mnemonic>
 8741 <def>
 8742 <pfx>aso rexr rexx rexb</pfx>
 8743 <opc>sse66 0f 38 10</opc>
 8744 <opr>V W</opr>
 8745 </def>
 8746 </instruction>
 8747
 8748 <instruction>
 8749 <mnemonic>pmuldq</mnemonic>
 8750 <def>
 8751 <pfx>aso rexr rexx rexb</pfx>
 8752 <opc>sse66 0f 38 28</opc>
 8753 <opr>V W</opr>
 8754 </def>
 8755 </instruction>
 8756
 8757 <instruction>
 8758 <mnemonic>pminsb</mnemonic>
 8759 <def>
 8760 <pfx>aso rexr rexx rexb</pfx>
 8761 <opc>sse66 0f 38 38</opc>
 8762 <opr>V W</opr>
 8763 </def>
 8764 </instruction>
 8765
 8766 <instruction>
 8767 <mnemonic>pminsd</mnemonic>
 8768 <def>
 8769 <pfx>aso rexr rexx rexb</pfx>
 8770 <opc>sse66 0f 38 39</opc>
 8771 <opr>V W</opr>
 8772 </def>
 8773 </instruction>
 8774
 8775 <instruction>
 8776 <mnemonic>pminuw</mnemonic>
 8777 <def>
 8778 <pfx>aso rexr rexx rexb</pfx>
 8779 <opc>sse66 0f 38 3a</opc>
 8780 <opr>V W</opr>
 8781 </def>
 8782 </instruction>
 8783
 8784 <instruction>
 8785 <mnemonic>pminud</mnemonic>
 8786 <def>
 8787 <pfx>aso rexr rexx rexb</pfx>
 8788 <opc>sse66 0f 38 3b</opc>
 8789 <opr>V W</opr>
 8790 </def>
 8791 </instruction>
 8792
 8793 <instruction>
 8794 <mnemonic>pmaxsb</mnemonic>
 8795 <def>
 8796 <pfx>aso rexr rexx rexb</pfx>
 8797 <opc>sse66 0f 38 3c</opc>
 8798 <opr>V W</opr>
 8799 </def>
 8800 </instruction>
 8801
 8802 <instruction>
 8803 <mnemonic>pmaxsd</mnemonic>
 8804 <def>
 8805 <pfx>aso rexr rexx rexb</pfx>
 8806 <opc>sse66 0f 38 3d</opc>
 8807 <opr>V W</opr>
 8808 </def>
 8809 </instruction>
 8810
 8811 <instruction>
 8812 <mnemonic>pmaxud</mnemonic>
 8813 <def>
 8814 <pfx>aso rexr rexx rexb</pfx>
 8815 <opc>sse66 0f 38 3f</opc>
 8816 <opr>V W</opr>
 8817 </def>
 8818 </instruction>
 8819
 8820 <instruction>
 8821 <mnemonic>pmulld</mnemonic>
 8822 <def>
 8823 <pfx>aso rexr rexx rexb</pfx>
 8824 <opc>sse66 0f 38 40</opc>
 8825 <opr>V W</opr>
 8826 </def>
 8827 </instruction>
 8828
 8829 <instruction>
 8830 <mnemonic>phminposuw</mnemonic>
 8831 <def>
 8832 <pfx>aso rexr rexx rexb</pfx>
 8833 <opc>sse66 0f 38 41</opc>
 8834 <opr>V W</opr>
 8835 </def>
 8836 </instruction>
 8837
 8838 <instruction>
 8839 <mnemonic>roundps</mnemonic>
 8840 <def>
 8841 <pfx>aso rexr rexx rexb</pfx>
 8842 <opc>sse66 0f 3a 08</opc>
 8843 <opr>V W Ib</opr>
 8844 </def>
 8845 </instruction>
 8846
 8847 <instruction>
 8848 <mnemonic>roundpd</mnemonic>
 8849 <def>
 8850 <pfx>aso rexr rexx rexb</pfx>
 8851 <opc>sse66 0f 3a 09</opc>
 8852 <opr>V W Ib</opr>
 8853 </def>
 8854 </instruction>
 8855
 8856 <instruction>
 8857 <mnemonic>roundss</mnemonic>
 8858 <def>
 8859 <pfx>aso rexr rexx rexb</pfx>
 8860 <opc>sse66 0f 3a 0a</opc>
 8861 <opr>V W Ib</opr>
 8862 </def>
 8863 </instruction>
 8864
 8865 <instruction>
 8866 <mnemonic>roundsd</mnemonic>
 8867 <def>
 8868 <pfx>aso rexr rexx rexb</pfx>
 8869 <opc>sse66 0f 3a 0b</opc>
 8870 <opr>V W Ib</opr>
 8871 </def>
 8872 </instruction>
 8873
 8874 <instruction>
 8875 <mnemonic>blendpd</mnemonic>
 8876 <def>
 8877 <pfx>aso rexr rexx rexb</pfx>
 8878 <opc>sse66 0f 3a 0d</opc>
 8879 <opr>V W Ib</opr>
 8880 </def>
 8881 </instruction>
 8882
 8883 <instruction>
 8884 <mnemonic>pblendw</mnemonic>
 8885 <def>
 8886 <pfx>aso rexr rexx rexb</pfx>
 8887 <opc>sse66 0f 3a 0e</opc>
 8888 <opr>V W Ib</opr>
 8889 </def>
 8890 </instruction>
 8891
 8892 <instruction>
 8893 <mnemonic>blendps</mnemonic>
 8894 <def>
 8895 <pfx>aso rexr rexx rexb</pfx>
 8896 <opc>sse66 0f 3a 0c</opc>
 8897 <opr>V W Ib</opr>
 8898 </def>
 8899 </instruction>
 8900
 8901 <instruction>
 8902 <mnemonic>blendvpd</mnemonic>
 8903 <def>
 8904 <pfx>aso rexr rexx rexb</pfx>
 8905 <opc>sse66 0f 38 15</opc>
 8906 <opr>V W</opr>
 8907 </def>
 8908 </instruction>
 8909
 8910 <instruction>
 8911 <mnemonic>blendvps</mnemonic>
 8912 <def>
 8913 <pfx>aso rexr rexx rexb</pfx>
 8914 <opc>sse66 0f 38 14</opc>
 8915 <opr>V W</opr>
 8916 </def>
 8917 </instruction>
 8918
 8919 <instruction>
 8920 <mnemonic>dpps</mnemonic>
 8921 <def>
 8922 <pfx>aso rexr rexx rexb</pfx>
 8923 <opc>sse66 0f 3a 40</opc>
 8924 <opr>V W Ib</opr>
 8925 </def>
 8926 </instruction>
 8927
 8928 <instruction>
 8929 <mnemonic>dppd</mnemonic>
 8930 <def>
 8931 <pfx>aso rexr rexx rexb</pfx>
 8932 <opc>sse66 0f 3a 41</opc>
 8933 <opr>V W Ib</opr>
 8934 </def>
 8935 </instruction>
 8936
 8937 <instruction>
 8938 <mnemonic>mpsadbw</mnemonic>
 8939 <def>
 8940 <pfx>aso rexr rexx rexb</pfx>
 8941 <opc>sse66 0f 3a 42</opc>
 8942 <opr>V W Ib</opr>
 8943 </def>
 8944 </instruction>
 8945
 8946 <instruction>
 8947 <mnemonic>extractps</mnemonic>
 8948 <def>
 8949 <pfx>aso rexr rexw rexb</pfx>
 8950 <opc>sse66 0f 3a 17</opc>
 8951 <opr>MdRy V Ib</opr>
 8952 </def>
 8953 </instruction>
 8954
 8955 <instruction>
 8956 <mnemonic>invalid</mnemonic>
 8957 </instruction>
 8958
 8959</x86optable>
0

Source/JavaScriptCore/disassembler/udis86/ud_opcode.py

 1# udis86 - scripts/ud_opcode.py
 2#
 3# Copyright (c) 2009 Vivek Thampi
 4# All rights reserved.
 5#
 6# Redistribution and use in source and binary forms, with or without modification,
 7# are permitted provided that the following conditions are met:
 8#
 9# * Redistributions of source code must retain the above copyright notice,
 10# this list of conditions and the following disclaimer.
 11# * Redistributions in binary form must reproduce the above copyright notice,
 12# this list of conditions and the following disclaimer in the documentation
 13# and/or other materials provided with the distribution.
 14#
 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25
 26class UdOpcodeTables:
 27
 28 TableInfo = {
 29 'opctbl' : { 'name' : 'UD_TAB__OPC_TABLE', 'size' : 256 },
 30 '/sse' : { 'name' : 'UD_TAB__OPC_SSE', 'size' : 4 },
 31 '/reg' : { 'name' : 'UD_TAB__OPC_REG', 'size' : 8 },
 32 '/rm' : { 'name' : 'UD_TAB__OPC_RM', 'size' : 8 },
 33 '/mod' : { 'name' : 'UD_TAB__OPC_MOD', 'size' : 2 },
 34 '/m' : { 'name' : 'UD_TAB__OPC_MODE', 'size' : 3 },
 35 '/x87' : { 'name' : 'UD_TAB__OPC_X87', 'size' : 64 },
 36 '/a' : { 'name' : 'UD_TAB__OPC_ASIZE', 'size' : 3 },
 37 '/o' : { 'name' : 'UD_TAB__OPC_OSIZE', 'size' : 3 },
 38 '/3dnow' : { 'name' : 'UD_TAB__OPC_3DNOW', 'size' : 256 },
 39 'vendor' : { 'name' : 'UD_TAB__OPC_VENDOR', 'size' : 3 },
 40 }
 41
 42 OpcodeTable0 = {
 43 'type' : 'opctbl',
 44 'entries' : {},
 45 'meta' : 'table0'
 46 }
 47
 48 OpcExtIndex = {
 49
 50 # ssef2, ssef3, sse66
 51 'sse': {
 52 'none' : '00',
 53 'f2' : '01',
 54 'f3' : '02',
 55 '66' : '03'
 56 },
 57
 58 # /mod=
 59 'mod': {
 60 '!11' : '00',
 61 '11' : '01'
 62 },
 63
 64 # /m=, /o=, /a=
 65 'mode': {
 66 '16' : '00',
 67 '32' : '01',
 68 '64' : '02'
 69 },
 70
 71 'vendor' : {
 72 'amd' : '00',
 73 'intel' : '01',
 74 'any' : '02'
 75 }
 76 }
 77
 78 InsnTable = []
 79 MnemonicsTable = []
 80
 81 ThreeDNowTable = {}
 82
 83 def sizeOfTable( self, t ):
 84 return self.TableInfo[ t ][ 'size' ]
 85
 86 def nameOfTable( self, t ):
 87 return self.TableInfo[ t ][ 'name' ]
 88
 89 #
 90 # Updates a table entry: If the entry doesn't exist
 91 # it will create the entry, otherwise, it will walk
 92 # while validating the path.
 93 #
 94 def updateTable( self, table, index, type, meta ):
 95 if not index in table[ 'entries' ]:
 96 table[ 'entries' ][ index ] = { 'type' : type, 'entries' : {}, 'meta' : meta }
 97 if table[ 'entries' ][ index ][ 'type' ] != type:
 98 raise NameError( "error: violation in opcode mapping (overwrite) %s with %s." %
 99 ( table[ 'entries' ][ index ][ 'type' ], type) )
 100 return table[ 'entries' ][ index ]
 101
 102 class Insn:
 103 """An abstract type representing an instruction in the opcode map.
 104 """
 105
 106 # A mapping of opcode extensions to their representational
 107 # values used in the opcode map.
 108 OpcExtMap = {
 109 '/rm' : lambda v: "%02x" % int(v, 16),
 110 '/x87' : lambda v: "%02x" % int(v, 16),
 111 '/3dnow' : lambda v: "%02x" % int(v, 16),
 112 '/reg' : lambda v: "%02x" % int(v, 16),
 113 # modrm.mod
 114 # (!11, 11) => (00, 01)
 115 '/mod' : lambda v: '00' if v == '!11' else '01',
 116 # Mode extensions:
 117 # (16, 32, 64) => (00, 01, 02)
 118 '/o' : lambda v: "%02x" % (int(v) / 32),
 119 '/a' : lambda v: "%02x" % (int(v) / 32),
 120 '/m' : lambda v: "%02x" % (int(v) / 32),
 121 '/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v]
 122 }
 123
 124 def __init__(self, prefixes, mnemonic, opcodes, operands, vendor):
 125 self.opcodes = opcodes
 126 self.prefixes = prefixes
 127 self.mnemonic = mnemonic
 128 self.operands = operands
 129 self.vendor = vendor
 130 self.opcext = {}
 131
 132 ssePrefix = None
 133 if self.opcodes[0] in ('ssef2', 'ssef3', 'sse66'):
 134 ssePrefix = self.opcodes[0][3:]
 135 self.opcodes.pop(0)
 136
 137 # do some preliminary decoding of the instruction type
 138 # 1byte, 2byte or 3byte instruction?
 139 self.nByteInsn = 1
 140 if self.opcodes[0] == '0f': # 2byte
 141 # 2+ byte opcodes are always disambiguated by an
 142 # sse prefix, unless it is a 3d now instruction
 143 # which is 0f 0f ...
 144 if self.opcodes[1] != '0f' and ssePrefix is None:
 145 ssePrefix = 'none'
 146 if self.opcodes[1] in ('38', '3a'): # 3byte
 147 self.nByteInsn = 3
 148 else:
 149 self.nByteInsn = 2
 150
 151 # The opcode that indexes into the opcode table.
 152 self.opcode = self.opcodes[self.nByteInsn - 1]
 153
 154 # Record opcode extensions
 155 for opcode in self.opcodes[self.nByteInsn:]:
 156 arg, val = opcode.split('=')
 157 self.opcext[arg] = self.OpcExtMap[arg](val)
 158
 159 # Record sse extension: the reason sse extension is handled
 160 # separately is that historically sse was handled as a first
 161 # class opcode, not as an extension. Now that sse is handled
 162 # as an extension, we do the manual conversion here, as opposed
 163 # to modifying the opcode xml file.
 164 if ssePrefix is not None:
 165 self.opcext['/sse'] = self.OpcExtMap['/sse'](ssePrefix)
 166
 167 def parse(self, table, insn):
 168 index = insn.opcodes[0];
 169 if insn.nByteInsn > 1:
 170 assert index == '0f'
 171 table = self.updateTable(table, index, 'opctbl', '0f')
 172 index = insn.opcodes[1]
 173
 174 if insn.nByteInsn == 3:
 175 table = self.updateTable(table, index, 'opctbl', index)
 176 index = insn.opcodes[2]
 177
 178 # Walk down the tree, create levels as needed, for opcode
 179 # extensions. The order is important, and determines how
 180 # well the opcode table is packed. Also note, /sse must be
 181 # before /o, because /sse may consume operand size prefix
 182 # affect the outcome of /o.
 183 for ext in ('/mod', '/x87', '/reg', '/rm', '/sse',
 184 '/o', '/a', '/m', '/3dnow'):
 185 if ext in insn.opcext:
 186 table = self.updateTable(table, index, ext, ext)
 187 index = insn.opcext[ext]
 188
 189 # additional table for disambiguating vendor
 190 if len(insn.vendor):
 191 table = self.updateTable(table, index, 'vendor', insn.vendor)
 192 index = self.OpcExtIndex['vendor'][insn.vendor]
 193
 194 # make leaf node entries
 195 leaf = self.updateTable(table, index, 'insn', '')
 196
 197 leaf['mnemonic'] = insn.mnemonic
 198 leaf['prefixes'] = insn.prefixes
 199 leaf['operands'] = insn.operands
 200
 201 # add instruction to linear table of instruction forms
 202 self.InsnTable.append({ 'prefixes' : insn.prefixes,
 203 'mnemonic' : insn.mnemonic,
 204 'operands' : insn.operands })
 205
 206 # add mnemonic to mnemonic table
 207 if not insn.mnemonic in self.MnemonicsTable:
 208 self.MnemonicsTable.append(insn.mnemonic)
 209
 210
 211 # Adds an instruction definition to the opcode tables
 212 def addInsnDef( self, prefixes, mnemonic, opcodes, operands, vendor ):
 213 insn = self.Insn(prefixes=prefixes,
 214 mnemonic=mnemonic,
 215 opcodes=opcodes,
 216 operands=operands,
 217 vendor=vendor)
 218 self.parse(self.OpcodeTable0, insn)
 219
 220 def print_table( self, table, pfxs ):
 221 print "%s |" % pfxs
 222 keys = table[ 'entries' ].keys()
 223 if ( len( keys ) ):
 224 keys.sort()
 225 for idx in keys:
 226 e = table[ 'entries' ][ idx ]
 227 if e[ 'type' ] == 'insn':
 228 print "%s |-<%s>" % ( pfxs, idx ),
 229 print "%s %s" % ( e[ 'mnemonic' ], ' '.join( e[ 'operands'] ) )
 230 else:
 231 print "%s |-<%s> %s" % ( pfxs, idx, e['type'] )
 232 self.print_table( e, pfxs + ' |' )
 233
 234 def print_tree( self ):
 235 self.print_table( self.OpcodeTable0, '' )
0

Source/JavaScriptCore/disassembler/udis86/ud_optable.py

 1# udis86 - scripts/ud_optable.py (optable.xml parser)
 2#
 3# Copyright (c) 2009 Vivek Thampi
 4# All rights reserved.
 5#
 6# Redistribution and use in source and binary forms, with or without modification,
 7# are permitted provided that the following conditions are met:
 8#
 9# * Redistributions of source code must retain the above copyright notice,
 10# this list of conditions and the following disclaimer.
 11# * Redistributions in binary form must reproduce the above copyright notice,
 12# this list of conditions and the following disclaimer in the documentation
 13# and/or other materials provided with the distribution.
 14#
 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25
 26import os
 27import sys
 28from xml.dom import minidom
 29
 30class UdOptableXmlParser:
 31
 32 def parseDef( self, node ):
 33 ven = ''
 34 pfx = []
 35 opc = []
 36 opr = []
 37 for def_node in node.childNodes:
 38 if not def_node.localName:
 39 continue
 40 if def_node.localName == 'pfx':
 41 pfx = def_node.firstChild.data.split();
 42 elif def_node.localName == 'opc':
 43 opc = def_node.firstChild.data.split();
 44 elif def_node.localName == 'opr':
 45 opr = def_node.firstChild.data.split();
 46 elif def_node.localName == 'mode':
 47 pfx.extend( def_node.firstChild.data.split() );
 48 elif def_node.localName == 'syn':
 49 pfx.extend( def_node.firstChild.data.split() );
 50 elif def_node.localName == 'vendor':
 51 ven = ( def_node.firstChild.data );
 52 else:
 53 print "warning: invalid node - %s" % def_node.localName
 54 continue
 55 return ( pfx, opc, opr, ven )
 56
 57 def parse( self, xml, fn ):
 58 xmlDoc = minidom.parse( xml )
 59 self.TlNode = xmlDoc.firstChild
 60
 61 while self.TlNode and self.TlNode.localName != "x86optable":
 62 self.TlNode = self.TlNode.nextSibling
 63
 64 for insnNode in self.TlNode.childNodes:
 65 if not insnNode.localName:
 66 continue
 67 if insnNode.localName != "instruction":
 68 print "warning: invalid insn node - %s" % insnNode.localName
 69 continue
 70
 71 mnemonic = insnNode.getElementsByTagName( 'mnemonic' )[ 0 ].firstChild.data
 72 vendor = ''
 73
 74 for node in insnNode.childNodes:
 75 if node.localName == 'vendor':
 76 vendor = node.firstChild.data
 77 elif node.localName == 'def':
 78 ( prefixes, opcodes, operands, local_vendor ) = \
 79 self.parseDef( node )
 80 if ( len( local_vendor ) ):
 81 vendor = local_vendor
 82 # callback
 83 fn( prefixes, mnemonic, opcodes, operands, vendor )
 84
 85
 86def printFn( pfx, mnm, opc, opr, ven ):
 87 print 'def: ',
 88 if len( pfx ):
 89 print ' '.join( pfx ),
 90 print "%s %s %s %s" % \
 91 ( mnm, ' '.join( opc ), ' '.join( opr ), ven )
 92
 93
 94def parse( xml, callback ):
 95 parser = UdOptableXmlParser()
 96 parser.parse( xml, callback )
 97
 98def main():
 99 parser = UdOptableXmlParser()
 100 parser.parse( sys.argv[ 1 ], printFn )
 101
 102if __name__ == "__main__":
 103 main()
0

Source/JavaScriptCore/disassembler/udis86/udis86.c

 1/* udis86 - libudis86/udis86.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26
 27#include "config.h"
 28#include <wtf/Platform.h>
 29
 30#if USE(UDIS86)
 31
 32#include "udis86_input.h"
 33#include "udis86_extern.h"
 34
 35#ifndef __UD_STANDALONE__
 36# include <stdlib.h>
 37# include <string.h>
 38#endif /* __UD_STANDALONE__ */
 39
 40/* =============================================================================
 41 * ud_init() - Initializes ud_t object.
 42 * =============================================================================
 43 */
 44extern void
 45ud_init(struct ud* u)
 46{
 47 memset((void*)u, 0, sizeof(struct ud));
 48 ud_set_mode(u, 16);
 49 u->mnemonic = UD_Iinvalid;
 50 ud_set_pc(u, 0);
 51#ifndef __UD_STANDALONE__
 52 ud_set_input_file(u, stdin);
 53#endif /* __UD_STANDALONE__ */
 54}
 55
 56/* =============================================================================
 57 * ud_disassemble() - disassembles one instruction and returns the number of
 58 * bytes disassembled. A zero means end of disassembly.
 59 * =============================================================================
 60 */
 61extern unsigned int
 62ud_disassemble(struct ud* u)
 63{
 64 if (ud_input_end(u))
 65 return 0;
 66
 67
 68 u->insn_buffer[0] = u->insn_hexcode[0] = 0;
 69
 70
 71 if (ud_decode(u) == 0)
 72 return 0;
 73 if (u->translator)
 74 u->translator(u);
 75 return ud_insn_len(u);
 76}
 77
 78/* =============================================================================
 79 * ud_set_mode() - Set Disassemly Mode.
 80 * =============================================================================
 81 */
 82extern void
 83ud_set_mode(struct ud* u, uint8_t m)
 84{
 85 switch(m) {
 86 case 16:
 87 case 32:
 88 case 64: u->dis_mode = m ; return;
 89 default: u->dis_mode = 16; return;
 90 }
 91}
 92
 93/* =============================================================================
 94 * ud_set_vendor() - Set vendor.
 95 * =============================================================================
 96 */
 97extern void
 98ud_set_vendor(struct ud* u, unsigned v)
 99{
 100 switch(v) {
 101 case UD_VENDOR_INTEL:
 102 u->vendor = v;
 103 break;
 104 case UD_VENDOR_ANY:
 105 u->vendor = v;
 106 break;
 107 default:
 108 u->vendor = UD_VENDOR_AMD;
 109 }
 110}
 111
 112/* =============================================================================
 113 * ud_set_pc() - Sets code origin.
 114 * =============================================================================
 115 */
 116extern void
 117ud_set_pc(struct ud* u, uint64_t o)
 118{
 119 u->pc = o;
 120}
 121
 122/* =============================================================================
 123 * ud_set_syntax() - Sets the output syntax.
 124 * =============================================================================
 125 */
 126extern void
 127ud_set_syntax(struct ud* u, void (*t)(struct ud*))
 128{
 129 u->translator = t;
 130}
 131
 132/* =============================================================================
 133 * ud_insn() - returns the disassembled instruction
 134 * =============================================================================
 135 */
 136extern char*
 137ud_insn_asm(struct ud* u)
 138{
 139 return u->insn_buffer;
 140}
 141
 142/* =============================================================================
 143 * ud_insn_offset() - Returns the offset.
 144 * =============================================================================
 145 */
 146extern uint64_t
 147ud_insn_off(struct ud* u)
 148{
 149 return u->insn_offset;
 150}
 151
 152
 153/* =============================================================================
 154 * ud_insn_hex() - Returns hex form of disassembled instruction.
 155 * =============================================================================
 156 */
 157extern char*
 158ud_insn_hex(struct ud* u)
 159{
 160 return u->insn_hexcode;
 161}
 162
 163/* =============================================================================
 164 * ud_insn_ptr() - Returns code disassembled.
 165 * =============================================================================
 166 */
 167extern uint8_t*
 168ud_insn_ptr(struct ud* u)
 169{
 170 return u->inp_sess;
 171}
 172
 173/* =============================================================================
 174 * ud_insn_len() - Returns the count of bytes disassembled.
 175 * =============================================================================
 176 */
 177extern unsigned int
 178ud_insn_len(struct ud* u)
 179{
 180 return u->inp_ctr;
 181}
 182
 183#endif // USE(UDIS86)
0

Source/JavaScriptCore/disassembler/udis86/udis86.h

 1/* udis86 - udis86.h
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UDIS86_H
 27#define UDIS86_H
 28
 29#include "udis86_types.h"
 30#include "udis86_extern.h"
 31#include "udis86_itab.h"
 32
 33#endif
0

Source/JavaScriptCore/disassembler/udis86/udis86_decode.c

 1/* udis86 - libudis86/decode.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26
 27#include "config.h"
 28#include <wtf/Platform.h>
 29
 30#if USE(UDIS86)
 31
 32#include "udis86_extern.h"
 33#include "udis86_types.h"
 34#include "udis86_input.h"
 35#include "udis86_decode.h"
 36#include <wtf/Assertions.h>
 37
 38#define dbg(x, n...)
 39/* #define dbg printf */
 40
 41#ifndef __UD_STANDALONE__
 42# include <string.h>
 43#endif /* __UD_STANDALONE__ */
 44
 45/* The max number of prefixes to an instruction */
 46#define MAX_PREFIXES 15
 47
 48/* instruction aliases and special cases */
 49static struct ud_itab_entry s_ie__invalid =
 50 { UD_Iinvalid, O_NONE, O_NONE, O_NONE, P_none };
 51
 52static int
 53decode_ext(struct ud *u, uint16_t ptr);
 54
 55
 56static inline int
 57eff_opr_mode(int dis_mode, int rex_w, int pfx_opr)
 58{
 59 if (dis_mode == 64) {
 60 return rex_w ? 64 : (pfx_opr ? 16 : 32);
 61 } else if (dis_mode == 32) {
 62 return pfx_opr ? 16 : 32;
 63 } else {
 64 ASSERT(dis_mode == 16);
 65 return pfx_opr ? 32 : 16;
 66 }
 67}
 68
 69
 70static inline int
 71eff_adr_mode(int dis_mode, int pfx_adr)
 72{
 73 if (dis_mode == 64) {
 74 return pfx_adr ? 32 : 64;
 75 } else if (dis_mode == 32) {
 76 return pfx_adr ? 16 : 32;
 77 } else {
 78 ASSERT(dis_mode == 16);
 79 return pfx_adr ? 32 : 16;
 80 }
 81}
 82
 83
 84/* Looks up mnemonic code in the mnemonic string table
 85 * Returns NULL if the mnemonic code is invalid
 86 */
 87const char * ud_lookup_mnemonic( enum ud_mnemonic_code c )
 88{
 89 return ud_mnemonics_str[ c ];
 90}
 91
 92
 93/*
 94 * decode_prefixes
 95 *
 96 * Extracts instruction prefixes.
 97 */
 98static int
 99decode_prefixes(struct ud *u)
 100{
 101 unsigned int have_pfx = 1;
 102 unsigned int i;
 103 uint8_t curr;
 104
 105 /* if in error state, bail out */
 106 if ( u->error )
 107 return -1;
 108
 109 /* keep going as long as there are prefixes available */
 110 for ( i = 0; have_pfx ; ++i ) {
 111
 112 /* Get next byte. */
 113 ud_inp_next(u);
 114 if ( u->error )
 115 return -1;
 116 curr = ud_inp_curr( u );
 117
 118 /* rex prefixes in 64bit mode */
 119 if ( u->dis_mode == 64 && ( curr & 0xF0 ) == 0x40 ) {
 120 u->pfx_rex = curr;
 121 } else {
 122 switch ( curr )
 123 {
 124 case 0x2E :
 125 u->pfx_seg = UD_R_CS;
 126 u->pfx_rex = 0;
 127 break;
 128 case 0x36 :
 129 u->pfx_seg = UD_R_SS;
 130 u->pfx_rex = 0;
 131 break;
 132 case 0x3E :
 133 u->pfx_seg = UD_R_DS;
 134 u->pfx_rex = 0;
 135 break;
 136 case 0x26 :
 137 u->pfx_seg = UD_R_ES;
 138 u->pfx_rex = 0;
 139 break;
 140 case 0x64 :
 141 u->pfx_seg = UD_R_FS;
 142 u->pfx_rex = 0;
 143 break;
 144 case 0x65 :
 145 u->pfx_seg = UD_R_GS;
 146 u->pfx_rex = 0;
 147 break;
 148 case 0x67 : /* adress-size override prefix */
 149 u->pfx_adr = 0x67;
 150 u->pfx_rex = 0;
 151 break;
 152 case 0xF0 :
 153 u->pfx_lock = 0xF0;
 154 u->pfx_rex = 0;
 155 break;
 156 case 0x66:
 157 /* the 0x66 sse prefix is only effective if no other sse prefix
 158 * has already been specified.
 159 */
 160 if ( !u->pfx_insn ) u->pfx_insn = 0x66;
 161 u->pfx_opr = 0x66;
 162 u->pfx_rex = 0;
 163 break;
 164 case 0xF2:
 165 u->pfx_insn = 0xF2;
 166 u->pfx_repne = 0xF2;
 167 u->pfx_rex = 0;
 168 break;
 169 case 0xF3:
 170 u->pfx_insn = 0xF3;
 171 u->pfx_rep = 0xF3;
 172 u->pfx_repe = 0xF3;
 173 u->pfx_rex = 0;
 174 break;
 175 default :
 176 /* No more prefixes */
 177 have_pfx = 0;
 178 break;
 179 }
 180 }
 181
 182 /* check if we reached max instruction length */
 183 if ( i + 1 == MAX_INSN_LENGTH ) {
 184 u->error = 1;
 185 break;
 186 }
 187 }
 188
 189 /* return status */
 190 if ( u->error )
 191 return -1;
 192
 193 /* rewind back one byte in stream, since the above loop
 194 * stops with a non-prefix byte.
 195 */
 196 ud_inp_back(u);
 197 return 0;
 198}
 199
 200
 201static inline unsigned int modrm( struct ud * u )
 202{
 203 if ( !u->have_modrm ) {
 204 u->modrm = ud_inp_next( u );
 205 u->have_modrm = 1;
 206 }
 207 return u->modrm;
 208}
 209
 210
 211static unsigned int resolve_operand_size( const struct ud * u, unsigned int s )
 212{
 213 switch ( s )
 214 {
 215 case SZ_V:
 216 return ( u->opr_mode );
 217 case SZ_Z:
 218 return ( u->opr_mode == 16 ) ? 16 : 32;
 219 case SZ_P:
 220 return ( u->opr_mode == 16 ) ? SZ_WP : SZ_DP;
 221 case SZ_MDQ:
 222 return ( u->opr_mode == 16 ) ? 32 : u->opr_mode;
 223 case SZ_RDQ:
 224 return ( u->dis_mode == 64 ) ? 64 : 32;
 225 default:
 226 return s;
 227 }
 228}
 229
 230
 231static int resolve_mnemonic( struct ud* u )
 232{
 233 /* far/near flags */
 234 u->br_far = 0;
 235 u->br_near = 0;
 236 /* readjust operand sizes for call/jmp instrcutions */
 237 if ( u->mnemonic == UD_Icall || u->mnemonic == UD_Ijmp ) {
 238 /* WP: 16:16 pointer */
 239 if ( u->operand[ 0 ].size == SZ_WP ) {
 240 u->operand[ 0 ].size = 16;
 241 u->br_far = 1;
 242 u->br_near= 0;
 243 /* DP: 32:32 pointer */
 244 } else if ( u->operand[ 0 ].size == SZ_DP ) {
 245 u->operand[ 0 ].size = 32;
 246 u->br_far = 1;
 247 u->br_near= 0;
 248 } else {
 249 u->br_far = 0;
 250 u->br_near= 1;
 251 }
 252 /* resolve 3dnow weirdness. */
 253 } else if ( u->mnemonic == UD_I3dnow ) {
 254 u->mnemonic = ud_itab[ u->le->table[ ud_inp_curr( u ) ] ].mnemonic;
 255 }
 256 /* SWAPGS is only valid in 64bits mode */
 257 if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) {
 258 u->error = 1;
 259 return -1;
 260 }
 261
 262 if (u->mnemonic == UD_Ixchg) {
 263 if ((u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_AX &&
 264 u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_AX) ||
 265 (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_EAX &&
 266 u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_EAX)) {
 267 u->operand[0].type = UD_NONE;
 268 u->operand[1].type = UD_NONE;
 269 u->mnemonic = UD_Inop;
 270 }
 271 }
 272
 273 if (u->mnemonic == UD_Inop && u->pfx_rep) {
 274 u->pfx_rep = 0;
 275 u->mnemonic = UD_Ipause;
 276 }
 277 return 0;
 278}
 279
 280
 281/* -----------------------------------------------------------------------------
 282 * decode_a()- Decodes operands of the type seg:offset
 283 * -----------------------------------------------------------------------------
 284 */
 285static void
 286decode_a(struct ud* u, struct ud_operand *op)
 287{
 288 if (u->opr_mode == 16) {
 289 /* seg16:off16 */
 290 op->type = UD_OP_PTR;
 291 op->size = 32;
 292 op->lval.ptr.off = ud_inp_uint16(u);
 293 op->lval.ptr.seg = ud_inp_uint16(u);
 294 } else {
 295 /* seg16:off32 */
 296 op->type = UD_OP_PTR;
 297 op->size = 48;
 298 op->lval.ptr.off = ud_inp_uint32(u);
 299 op->lval.ptr.seg = ud_inp_uint16(u);
 300 }
 301}
 302
 303/* -----------------------------------------------------------------------------
 304 * decode_gpr() - Returns decoded General Purpose Register
 305 * -----------------------------------------------------------------------------
 306 */
 307static enum ud_type
 308decode_gpr(register struct ud* u, unsigned int s, unsigned char rm)
 309{
 310 s = resolve_operand_size(u, s);
 311
 312 switch (s) {
 313 case 64:
 314 return UD_R_RAX + rm;
 315 case SZ_DP:
 316 case 32:
 317 return UD_R_EAX + rm;
 318 case SZ_WP:
 319 case 16:
 320 return UD_R_AX + rm;
 321 case 8:
 322 if (u->dis_mode == 64 && u->pfx_rex) {
 323 if (rm >= 4)
 324 return UD_R_SPL + (rm-4);
 325 return UD_R_AL + rm;
 326 } else return UD_R_AL + rm;
 327 default:
 328 return 0;
 329 }
 330}
 331
 332/* -----------------------------------------------------------------------------
 333 * resolve_gpr64() - 64bit General Purpose Register-Selection.
 334 * -----------------------------------------------------------------------------
 335 */
 336static enum ud_type
 337resolve_gpr64(struct ud* u, enum ud_operand_code gpr_op, enum ud_operand_size * size)
 338{
 339 if (gpr_op >= OP_rAXr8 && gpr_op <= OP_rDIr15)
 340 gpr_op = (gpr_op - OP_rAXr8) | (REX_B(u->pfx_rex) << 3);
 341 else gpr_op = (gpr_op - OP_rAX);
 342
 343 if (u->opr_mode == 16) {
 344 *size = 16;
 345 return gpr_op + UD_R_AX;
 346 }
 347 if (u->dis_mode == 32 ||
 348 (u->opr_mode == 32 && ! (REX_W(u->pfx_rex) || u->default64))) {
 349 *size = 32;
 350 return gpr_op + UD_R_EAX;
 351 }
 352
 353 *size = 64;
 354 return gpr_op + UD_R_RAX;
 355}
 356
 357/* -----------------------------------------------------------------------------
 358 * resolve_gpr32 () - 32bit General Purpose Register-Selection.
 359 * -----------------------------------------------------------------------------
 360 */
 361static enum ud_type
 362resolve_gpr32(struct ud* u, enum ud_operand_code gpr_op)
 363{
 364 gpr_op = gpr_op - OP_eAX;
 365
 366 if (u->opr_mode == 16)
 367 return gpr_op + UD_R_AX;
 368
 369 return gpr_op + UD_R_EAX;
 370}
 371
 372/* -----------------------------------------------------------------------------
 373 * resolve_reg() - Resolves the register type
 374 * -----------------------------------------------------------------------------
 375 */
 376static enum ud_type
 377resolve_reg(struct ud* u, unsigned int type, unsigned char i)
 378{
 379 switch (type) {
 380 case T_MMX : return UD_R_MM0 + (i & 7);
 381 case T_XMM : return UD_R_XMM0 + i;
 382 case T_CRG : return UD_R_CR0 + i;
 383 case T_DBG : return UD_R_DR0 + i;
 384 case T_SEG : {
 385 /*
 386 * Only 6 segment registers, anything else is an error.
 387 */
 388 if ((i & 7) > 5) {
 389 u->error = 1;
 390 } else {
 391 return UD_R_ES + (i & 7);
 392 }
 393 }
 394 case T_NONE:
 395 default: return UD_NONE;
 396 }
 397}
 398
 399/* -----------------------------------------------------------------------------
 400 * decode_imm() - Decodes Immediate values.
 401 * -----------------------------------------------------------------------------
 402 */
 403static void
 404decode_imm(struct ud* u, unsigned int s, struct ud_operand *op)
 405{
 406 op->size = resolve_operand_size(u, s);
 407 op->type = UD_OP_IMM;
 408
 409 switch (op->size) {
 410 case 8: op->lval.sbyte = ud_inp_uint8(u); break;
 411 case 16: op->lval.uword = ud_inp_uint16(u); break;
 412 case 32: op->lval.udword = ud_inp_uint32(u); break;
 413 case 64: op->lval.uqword = ud_inp_uint64(u); break;
 414 default: return;
 415 }
 416}
 417
 418
 419/*
 420 * decode_modrm_reg
 421 *
 422 * Decodes reg field of mod/rm byte
 423 *
 424 */
 425static void
 426decode_modrm_reg(struct ud *u,
 427 struct ud_operand *operand,
 428 unsigned int type,
 429 unsigned int size)
 430{
 431 uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));
 432 operand->type = UD_OP_REG;
 433 operand->size = resolve_operand_size(u, size);
 434
 435 if (type == T_GPR) {
 436 operand->base = decode_gpr(u, operand->size, reg);
 437 } else {
 438 operand->base = resolve_reg(u, type, reg);
 439 }
 440}
 441
 442
 443/*
 444 * decode_modrm_rm
 445 *
 446 * Decodes rm field of mod/rm byte
 447 *
 448 */
 449static void
 450decode_modrm_rm(struct ud *u,
 451 struct ud_operand *op,
 452 unsigned char type,
 453 unsigned int size)
 454
 455{
 456 unsigned char mod, rm, reg;
 457
 458 /* get mod, r/m and reg fields */
 459 mod = MODRM_MOD(modrm(u));
 460 rm = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u));
 461 reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));
 462
 463 op->size = resolve_operand_size(u, size);
 464
 465 /*
 466 * If mod is 11b, then the modrm.rm specifies a register.
 467 *
 468 */
 469 if (mod == 3) {
 470 op->type = UD_OP_REG;
 471 if (type == T_GPR) {
 472 op->base = decode_gpr(u, op->size, rm);
 473 } else {
 474 op->base = resolve_reg(u, type, (REX_B(u->pfx_rex) << 3) | (rm & 7));
 475 }
 476 return;
 477 }
 478
 479
 480 /*
 481 * !11 => Memory Address
 482 */
 483 op->type = UD_OP_MEM;
 484
 485 if (u->adr_mode == 64) {
 486 op->base = UD_R_RAX + rm;
 487 if (mod == 1) {
 488 op->offset = 8;
 489 } else if (mod == 2) {
 490 op->offset = 32;
 491 } else if (mod == 0 && (rm & 7) == 5) {
 492 op->base = UD_R_RIP;
 493 op->offset = 32;
 494 } else {
 495 op->offset = 0;
 496 }
 497 /*
 498 * Scale-Index-Base (SIB)
 499 */
 500 if ((rm & 7) == 4) {
 501 ud_inp_next(u);
 502
 503 op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1;
 504 op->index = UD_R_RAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
 505 op->base = UD_R_RAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
 506
 507 /* special conditions for base reference */
 508 if (op->index == UD_R_RSP) {
 509 op->index = UD_NONE;
 510 op->scale = UD_NONE;
 511 }
 512
 513 if (op->base == UD_R_RBP || op->base == UD_R_R13) {
 514 if (mod == 0) {
 515 op->base = UD_NONE;
 516 }
 517 if (mod == 1) {
 518 op->offset = 8;
 519 } else {
 520 op->offset = 32;
 521 }
 522 }
 523 }
 524 } else if (u->adr_mode == 32) {
 525 op->base = UD_R_EAX + rm;
 526 if (mod == 1) {
 527 op->offset = 8;
 528 } else if (mod == 2) {
 529 op->offset = 32;
 530 } else if (mod == 0 && rm == 5) {
 531 op->base = UD_NONE;
 532 op->offset = 32;
 533 } else {
 534 op->offset = 0;
 535 }
 536
 537 /* Scale-Index-Base (SIB) */
 538 if ((rm & 7) == 4) {
 539 ud_inp_next(u);
 540
 541 op->scale = (1 << SIB_S(ud_inp_curr(u))) & ~1;
 542 op->index = UD_R_EAX + (SIB_I(ud_inp_curr(u)) | (REX_X(u->pfx_rex) << 3));
 543 op->base = UD_R_EAX + (SIB_B(ud_inp_curr(u)) | (REX_B(u->pfx_rex) << 3));
 544
 545 if (op->index == UD_R_ESP) {
 546 op->index = UD_NONE;
 547 op->scale = UD_NONE;
 548 }
 549
 550 /* special condition for base reference */
 551 if (op->base == UD_R_EBP) {
 552 if (mod == 0) {
 553 op->base = UD_NONE;
 554 }
 555 if (mod == 1) {
 556 op->offset = 8;
 557 } else {
 558 op->offset = 32;
 559 }
 560 }
 561 }
 562 } else {
 563 const unsigned int bases[] = { UD_R_BX, UD_R_BX, UD_R_BP, UD_R_BP,
 564 UD_R_SI, UD_R_DI, UD_R_BP, UD_R_BX };
 565 const unsigned int indices[] = { UD_R_SI, UD_R_DI, UD_R_SI, UD_R_DI,
 566 UD_NONE, UD_NONE, UD_NONE, UD_NONE };
 567 op->base = bases[rm & 7];
 568 op->index = indices[rm & 7];
 569 if (mod == 0 && rm == 6) {
 570 op->offset= 16;
 571 op->base = UD_NONE;
 572 } else if (mod == 1) {
 573 op->offset = 8;
 574 } else if (mod == 2) {
 575 op->offset = 16;
 576 }
 577 }
 578
 579 /*
 580 * extract offset, if any
 581 */
 582 switch (op->offset) {
 583 case 8 : op->lval.ubyte = ud_inp_uint8(u); break;
 584 case 16: op->lval.uword = ud_inp_uint16(u); break;
 585 case 32: op->lval.udword = ud_inp_uint32(u); break;
 586 case 64: op->lval.uqword = ud_inp_uint64(u); break;
 587 default: break;
 588 }
 589}
 590
 591/* -----------------------------------------------------------------------------
 592 * decode_o() - Decodes offset
 593 * -----------------------------------------------------------------------------
 594 */
 595static void
 596decode_o(struct ud* u, unsigned int s, struct ud_operand *op)
 597{
 598 switch (u->adr_mode) {
 599 case 64:
 600 op->offset = 64;
 601 op->lval.uqword = ud_inp_uint64(u);
 602 break;
 603 case 32:
 604 op->offset = 32;
 605 op->lval.udword = ud_inp_uint32(u);
 606 break;
 607 case 16:
 608 op->offset = 16;
 609 op->lval.uword = ud_inp_uint16(u);
 610 break;
 611 default:
 612 return;
 613 }
 614 op->type = UD_OP_MEM;
 615 op->size = resolve_operand_size(u, s);
 616}
 617
 618/* -----------------------------------------------------------------------------
 619 * decode_operands() - Disassembles Operands.
 620 * -----------------------------------------------------------------------------
 621 */
 622static int
 623decode_operand(struct ud *u,
 624 struct ud_operand *operand,
 625 enum ud_operand_code type,
 626 unsigned int size)
 627{
 628 switch (type) {
 629 case OP_A :
 630 decode_a(u, operand);
 631 break;
 632 case OP_MR:
 633 if (MODRM_MOD(modrm(u)) == 3) {
 634 decode_modrm_rm(u, operand, T_GPR,
 635 size == SZ_DY ? SZ_MDQ : SZ_V);
 636 } else if (size == SZ_WV) {
 637 decode_modrm_rm( u, operand, T_GPR, SZ_W);
 638 } else if (size == SZ_BV) {
 639 decode_modrm_rm( u, operand, T_GPR, SZ_B);
 640 } else if (size == SZ_DY) {
 641 decode_modrm_rm( u, operand, T_GPR, SZ_D);
 642 } else {
 643 ASSERT(!"unexpected size");
 644 }
 645 break;
 646 case OP_M:
 647 if (MODRM_MOD(modrm(u)) == 3) {
 648 u->error = 1;
 649 }
 650 /* intended fall through */
 651 case OP_E:
 652 decode_modrm_rm(u, operand, T_GPR, size);
 653 break;
 654 break;
 655 case OP_G:
 656 decode_modrm_reg(u, operand, T_GPR, size);
 657 break;
 658 case OP_I:
 659 decode_imm(u, size, operand);
 660 break;
 661 case OP_I1:
 662 operand->type = UD_OP_CONST;
 663 operand->lval.udword = 1;
 664 break;
 665 case OP_PR:
 666 if (MODRM_MOD(modrm(u)) != 3) {
 667 u->error = 1;
 668 }
 669 decode_modrm_rm(u, operand, T_MMX, size);
 670 break;
 671 case OP_P:
 672 decode_modrm_reg(u, operand, T_MMX, size);
 673 break;
 674 case OP_VR:
 675 if (MODRM_MOD(modrm(u)) != 3) {
 676 u->error = 1;
 677 }
 678 /* intended fall through */
 679 case OP_W:
 680 decode_modrm_rm(u, operand, T_XMM, size);
 681 break;
 682 case OP_V:
 683 decode_modrm_reg(u, operand, T_XMM, size);
 684 break;
 685 case OP_S:
 686 decode_modrm_reg(u, operand, T_SEG, size);
 687 break;
 688 case OP_AL:
 689 case OP_CL:
 690 case OP_DL:
 691 case OP_BL:
 692 case OP_AH:
 693 case OP_CH:
 694 case OP_DH:
 695 case OP_BH:
 696 operand->type = UD_OP_REG;
 697 operand->base = UD_R_AL + (type - OP_AL);
 698 operand->size = 8;
 699 break;
 700 case OP_DX:
 701 operand->type = UD_OP_REG;
 702 operand->base = UD_R_DX;
 703 operand->size = 16;
 704 break;
 705 case OP_O:
 706 decode_o(u, size, operand);
 707 break;
 708 case OP_rAXr8:
 709 case OP_rCXr9:
 710 case OP_rDXr10:
 711 case OP_rBXr11:
 712 case OP_rSPr12:
 713 case OP_rBPr13:
 714 case OP_rSIr14:
 715 case OP_rDIr15:
 716 case OP_rAX:
 717 case OP_rCX:
 718 case OP_rDX:
 719 case OP_rBX:
 720 case OP_rSP:
 721 case OP_rBP:
 722 case OP_rSI:
 723 case OP_rDI:
 724 operand->type = UD_OP_REG;
 725 operand->base = resolve_gpr64(u, type, &operand->size);
 726 break;
 727 case OP_ALr8b:
 728 case OP_CLr9b:
 729 case OP_DLr10b:
 730 case OP_BLr11b:
 731 case OP_AHr12b:
 732 case OP_CHr13b:
 733 case OP_DHr14b:
 734 case OP_BHr15b: {
 735 ud_type_t gpr = (type - OP_ALr8b) + UD_R_AL
 736 + (REX_B(u->pfx_rex) << 3);
 737 if (UD_R_AH <= gpr && u->pfx_rex) {
 738 gpr = gpr + 4;
 739 }
 740 operand->type = UD_OP_REG;
 741 operand->base = gpr;
 742 break;
 743 }
 744 case OP_eAX:
 745 case OP_eCX:
 746 case OP_eDX:
 747 case OP_eBX:
 748 case OP_eSP:
 749 case OP_eBP:
 750 case OP_eSI:
 751 case OP_eDI:
 752 operand->type = UD_OP_REG;
 753 operand->base = resolve_gpr32(u, type);
 754 operand->size = u->opr_mode == 16 ? 16 : 32;
 755 break;
 756 case OP_ES:
 757 case OP_CS:
 758 case OP_DS:
 759 case OP_SS:
 760 case OP_FS:
 761 case OP_GS:
 762 /* in 64bits mode, only fs and gs are allowed */
 763 if (u->dis_mode == 64) {
 764 if (type != OP_FS && type != OP_GS) {
 765 u->error= 1;
 766 }
 767 }
 768 operand->type = UD_OP_REG;
 769 operand->base = (type - OP_ES) + UD_R_ES;
 770 operand->size = 16;
 771 break;
 772 case OP_J :
 773 decode_imm(u, size, operand);
 774 operand->type = UD_OP_JIMM;
 775 break ;
 776 case OP_Q:
 777 decode_modrm_rm(u, operand, T_MMX, size);
 778 break;
 779 case OP_R :
 780 decode_modrm_rm(u, operand, T_GPR, size);
 781 break;
 782 case OP_C:
 783 decode_modrm_reg(u, operand, T_CRG, size);
 784 break;
 785 case OP_D:
 786 decode_modrm_reg(u, operand, T_DBG, size);
 787 break;
 788 case OP_I3 :
 789 operand->type = UD_OP_CONST;
 790 operand->lval.sbyte = 3;
 791 break;
 792 case OP_ST0:
 793 case OP_ST1:
 794 case OP_ST2:
 795 case OP_ST3:
 796 case OP_ST4:
 797 case OP_ST5:
 798 case OP_ST6:
 799 case OP_ST7:
 800 operand->type = UD_OP_REG;
 801 operand->base = (type - OP_ST0) + UD_R_ST0;
 802 operand->size = 0;
 803 break;
 804 case OP_AX:
 805 operand->type = UD_OP_REG;
 806 operand->base = UD_R_AX;
 807 operand->size = 16;
 808 break;
 809 default :
 810 operand->type = UD_NONE;
 811 break;
 812 }
 813 return 0;
 814}
 815
 816
 817/*
 818 * decode_operands
 819 *
 820 * Disassemble upto 3 operands of the current instruction being
 821 * disassembled. By the end of the function, the operand fields
 822 * of the ud structure will have been filled.
 823 */
 824static int
 825decode_operands(struct ud* u)
 826{
 827 decode_operand(u, &u->operand[0],
 828 u->itab_entry->operand1.type,
 829 u->itab_entry->operand1.size);
 830 decode_operand(u, &u->operand[1],
 831 u->itab_entry->operand2.type,
 832 u->itab_entry->operand2.size);
 833 decode_operand(u, &u->operand[2],
 834 u->itab_entry->operand3.type,
 835 u->itab_entry->operand3.size);
 836 return 0;
 837}
 838
 839/* -----------------------------------------------------------------------------
 840 * clear_insn() - clear instruction structure
 841 * -----------------------------------------------------------------------------
 842 */
 843static void
 844clear_insn(register struct ud* u)
 845{
 846 u->error = 0;
 847 u->pfx_seg = 0;
 848 u->pfx_opr = 0;
 849 u->pfx_adr = 0;
 850 u->pfx_lock = 0;
 851 u->pfx_repne = 0;
 852 u->pfx_rep = 0;
 853 u->pfx_repe = 0;
 854 u->pfx_rex = 0;
 855 u->pfx_insn = 0;
 856 u->mnemonic = UD_Inone;
 857 u->itab_entry = NULL;
 858 u->have_modrm = 0;
 859
 860 memset( &u->operand[ 0 ], 0, sizeof( struct ud_operand ) );
 861 memset( &u->operand[ 1 ], 0, sizeof( struct ud_operand ) );
 862 memset( &u->operand[ 2 ], 0, sizeof( struct ud_operand ) );
 863}
 864
 865static int
 866resolve_mode( struct ud* u )
 867{
 868 /* if in error state, bail out */
 869 if ( u->error ) return -1;
 870
 871 /* propagate prefix effects */
 872 if ( u->dis_mode == 64 ) { /* set 64bit-mode flags */
 873
 874 /* Check validity of instruction m64 */
 875 if ( P_INV64( u->itab_entry->prefix ) ) {
 876 u->error = 1;
 877 return -1;
 878 }
 879
 880 /* effective rex prefix is the effective mask for the
 881 * instruction hard-coded in the opcode map.
 882 */
 883 u->pfx_rex = ( u->pfx_rex & 0x40 ) |
 884 ( u->pfx_rex & REX_PFX_MASK( u->itab_entry->prefix ) );
 885
 886 /* whether this instruction has a default operand size of
 887 * 64bit, also hardcoded into the opcode map.
 888 */
 889 u->default64 = P_DEF64( u->itab_entry->prefix );
 890 /* calculate effective operand size */
 891 if ( REX_W( u->pfx_rex ) ) {
 892 u->opr_mode = 64;
 893 } else if ( u->pfx_opr ) {
 894 u->opr_mode = 16;
 895 } else {
 896 /* unless the default opr size of instruction is 64,
 897 * the effective operand size in the absence of rex.w
 898 * prefix is 32.
 899 */
 900 u->opr_mode = ( u->default64 ) ? 64 : 32;
 901 }
 902
 903 /* calculate effective address size */
 904 u->adr_mode = (u->pfx_adr) ? 32 : 64;
 905 } else if ( u->dis_mode == 32 ) { /* set 32bit-mode flags */
 906 u->opr_mode = ( u->pfx_opr ) ? 16 : 32;
 907 u->adr_mode = ( u->pfx_adr ) ? 16 : 32;
 908 } else if ( u->dis_mode == 16 ) { /* set 16bit-mode flags */
 909 u->opr_mode = ( u->pfx_opr ) ? 32 : 16;
 910 u->adr_mode = ( u->pfx_adr ) ? 32 : 16;
 911 }
 912
 913 /* These flags determine which operand to apply the operand size
 914 * cast to.
 915 */
 916 u->c1 = ( P_C1( u->itab_entry->prefix ) ) ? 1 : 0;
 917 u->c2 = ( P_C2( u->itab_entry->prefix ) ) ? 1 : 0;
 918 u->c3 = ( P_C3( u->itab_entry->prefix ) ) ? 1 : 0;
 919
 920 /* set flags for implicit addressing */
 921 u->implicit_addr = P_IMPADDR( u->itab_entry->prefix );
 922
 923 return 0;
 924}
 925
 926static int gen_hex( struct ud *u )
 927{
 928 unsigned int i;
 929 unsigned char *src_ptr = ud_inp_sess( u );
 930 char* src_hex;
 931
 932 /* bail out if in error stat. */
 933 if ( u->error ) return -1;
 934 /* output buffer pointe */
 935 src_hex = ( char* ) u->insn_hexcode;
 936 /* for each byte used to decode instruction */
 937 for ( i = 0; i < u->inp_ctr; ++i, ++src_ptr) {
 938 sprintf( src_hex, "%02x", *src_ptr & 0xFF );
 939 src_hex += 2;
 940 }
 941 return 0;
 942}
 943
 944
 945static inline int
 946decode_insn(struct ud *u, uint16_t ptr)
 947{
 948 ASSERT((ptr & 0x8000) == 0);
 949 u->itab_entry = &ud_itab[ ptr ];
 950 u->mnemonic = u->itab_entry->mnemonic;
 951 return (resolve_mode(u) == 0 &&
 952 decode_operands(u) == 0 &&
 953 resolve_mnemonic(u) == 0) ? 0 : -1;
 954}
 955
 956
 957/*
 958 * decode_3dnow()
 959 *
 960 * Decoding 3dnow is a little tricky because of its strange opcode
 961 * structure. The final opcode disambiguation depends on the last
 962 * byte that comes after the operands have been decoded. Fortunately,
 963 * all 3dnow instructions have the same set of operand types. So we
 964 * go ahead and decode the instruction by picking an arbitrarily chosen
 965 * valid entry in the table, decode the operands, and read the final
 966 * byte to resolve the menmonic.
 967 */
 968static inline int
 969decode_3dnow(struct ud* u)
 970{
 971 uint16_t ptr;
 972 ASSERT(u->le->type == UD_TAB__OPC_3DNOW);
 973 ASSERT(u->le->table[0xc] != 0);
 974 decode_insn(u, u->le->table[0xc]);
 975 ud_inp_next(u);
 976 if (u->error) {
 977 return -1;
 978 }
 979 ptr = u->le->table[ud_inp_curr(u)];
 980 ASSERT((ptr & 0x8000) == 0);
 981 u->mnemonic = ud_itab[ptr].mnemonic;
 982 return 0;
 983}
 984
 985
 986static int
 987decode_ssepfx(struct ud *u)
 988{
 989 uint8_t idx = ((u->pfx_insn & 0xf) + 1) / 2;
 990 if (u->le->table[idx] == 0) {
 991 idx = 0;
 992 }
 993 if (idx && u->le->table[idx] != 0) {
 994 /*
 995 * "Consume" the prefix as a part of the opcode, so it is no
 996 * longer exported as an instruction prefix.
 997 */
 998 switch (u->pfx_insn) {
 999 case 0xf2:
 1000 u->pfx_repne = 0;
 1001 break;
 1002 case 0xf3:
 1003 u->pfx_rep = 0;
 1004 u->pfx_repe = 0;
 1005 break;
 1006 case 0x66:
 1007 u->pfx_opr = 0;
 1008 break;
 1009 }
 1010 }
 1011 return decode_ext(u, u->le->table[idx]);
 1012}
 1013
 1014
 1015/*
 1016 * decode_ext()
 1017 *
 1018 * Decode opcode extensions (if any)
 1019 */
 1020static int
 1021decode_ext(struct ud *u, uint16_t ptr)
 1022{
 1023 uint8_t idx = 0;
 1024 if ((ptr & 0x8000) == 0) {
 1025 return decode_insn(u, ptr);
 1026 }
 1027 u->le = &ud_lookup_table_list[(~0x8000 & ptr)];
 1028 if (u->le->type == UD_TAB__OPC_3DNOW) {
 1029 return decode_3dnow(u);
 1030 }
 1031
 1032 switch (u->le->type) {
 1033 case UD_TAB__OPC_MOD:
 1034 /* !11 = 0, 11 = 1 */
 1035 idx = (MODRM_MOD(modrm(u)) + 1) / 4;
 1036 break;
 1037 /* disassembly mode/operand size/address size based tables.
 1038 * 16 = 0,, 32 = 1, 64 = 2
 1039 */
 1040 case UD_TAB__OPC_MODE:
 1041 idx = u->dis_mode / 32;
 1042 break;
 1043 case UD_TAB__OPC_OSIZE:
 1044 idx = eff_opr_mode(u->dis_mode, REX_W(u->pfx_rex), u->pfx_opr) / 32;
 1045 break;
 1046 case UD_TAB__OPC_ASIZE:
 1047 idx = eff_adr_mode(u->dis_mode, u->pfx_adr) / 32;
 1048 break;
 1049 case UD_TAB__OPC_X87:
 1050 idx = modrm(u) - 0xC0;
 1051 break;
 1052 case UD_TAB__OPC_VENDOR:
 1053 if (u->vendor == UD_VENDOR_ANY) {
 1054 /* choose a valid entry */
 1055 idx = (u->le->table[idx] != 0) ? 0 : 1;
 1056 } else if (u->vendor == UD_VENDOR_AMD) {
 1057 idx = 0;
 1058 } else {
 1059 idx = 1;
 1060 }
 1061 break;
 1062 case UD_TAB__OPC_RM:
 1063 idx = MODRM_RM(modrm(u));
 1064 break;
 1065 case UD_TAB__OPC_REG:
 1066 idx = MODRM_REG(modrm(u));
 1067 break;
 1068 case UD_TAB__OPC_SSE:
 1069 return decode_ssepfx(u);
 1070 default:
 1071 ASSERT(!"not reached");
 1072 break;
 1073 }
 1074
 1075 return decode_ext(u, u->le->table[idx]);
 1076}
 1077
 1078
 1079static inline int
 1080decode_opcode(struct ud *u)
 1081{
 1082 uint16_t ptr;
 1083 ASSERT(u->le->type == UD_TAB__OPC_TABLE);
 1084 ud_inp_next(u);
 1085 if (u->error) {
 1086 return -1;
 1087 }
 1088 ptr = u->le->table[ud_inp_curr(u)];
 1089 if (ptr & 0x8000) {
 1090 u->le = &ud_lookup_table_list[ptr & ~0x8000];
 1091 if (u->le->type == UD_TAB__OPC_TABLE) {
 1092 return decode_opcode(u);
 1093 }
 1094 }
 1095 return decode_ext(u, ptr);
 1096}
 1097
 1098
 1099/* =============================================================================
 1100 * ud_decode() - Instruction decoder. Returns the number of bytes decoded.
 1101 * =============================================================================
 1102 */
 1103unsigned int
 1104ud_decode(struct ud *u)
 1105{
 1106 ud_inp_start(u);
 1107 clear_insn(u);
 1108 u->le = &ud_lookup_table_list[0];
 1109 u->error = decode_prefixes(u) == -1 ||
 1110 decode_opcode(u) == -1 ||
 1111 u->error;
 1112 /* Handle decode error. */
 1113 if (u->error) {
 1114 /* clear out the decode data. */
 1115 clear_insn(u);
 1116 /* mark the sequence of bytes as invalid. */
 1117 u->itab_entry = & s_ie__invalid;
 1118 u->mnemonic = u->itab_entry->mnemonic;
 1119 }
 1120
 1121 /* maybe this stray segment override byte
 1122 * should be spewed out?
 1123 */
 1124 if ( !P_SEG( u->itab_entry->prefix ) &&
 1125 u->operand[0].type != UD_OP_MEM &&
 1126 u->operand[1].type != UD_OP_MEM )
 1127 u->pfx_seg = 0;
 1128
 1129 u->insn_offset = u->pc; /* set offset of instruction */
 1130 u->insn_fill = 0; /* set translation buffer index to 0 */
 1131 u->pc += u->inp_ctr; /* move program counter by bytes decoded */
 1132 gen_hex( u ); /* generate hex code */
 1133
 1134 /* return number of bytes disassembled. */
 1135 return u->inp_ctr;
 1136}
 1137
 1138/*
 1139vim: set ts=2 sw=2 expandtab
 1140*/
 1141
 1142#endif // USE(UDIS86)
0

Source/JavaScriptCore/disassembler/udis86/udis86_decode.h

 1/* udis86 - libudis86/decode.h
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UD_DECODE_H
 27#define UD_DECODE_H
 28
 29#include "udis86_types.h"
 30#include "udis86_itab.h"
 31
 32#define MAX_INSN_LENGTH 15
 33
 34/* register classes */
 35#define T_NONE 0
 36#define T_GPR 1
 37#define T_MMX 2
 38#define T_CRG 3
 39#define T_DBG 4
 40#define T_SEG 5
 41#define T_XMM 6
 42
 43/* itab prefix bits */
 44#define P_none ( 0 )
 45#define P_cast ( 1 << 0 )
 46#define P_CAST(n) ( ( n >> 0 ) & 1 )
 47#define P_c1 ( 1 << 0 )
 48#define P_C1(n) ( ( n >> 0 ) & 1 )
 49#define P_rexb ( 1 << 1 )
 50#define P_REXB(n) ( ( n >> 1 ) & 1 )
 51#define P_depM ( 1 << 2 )
 52#define P_DEPM(n) ( ( n >> 2 ) & 1 )
 53#define P_c3 ( 1 << 3 )
 54#define P_C3(n) ( ( n >> 3 ) & 1 )
 55#define P_inv64 ( 1 << 4 )
 56#define P_INV64(n) ( ( n >> 4 ) & 1 )
 57#define P_rexw ( 1 << 5 )
 58#define P_REXW(n) ( ( n >> 5 ) & 1 )
 59#define P_c2 ( 1 << 6 )
 60#define P_C2(n) ( ( n >> 6 ) & 1 )
 61#define P_def64 ( 1 << 7 )
 62#define P_DEF64(n) ( ( n >> 7 ) & 1 )
 63#define P_rexr ( 1 << 8 )
 64#define P_REXR(n) ( ( n >> 8 ) & 1 )
 65#define P_oso ( 1 << 9 )
 66#define P_OSO(n) ( ( n >> 9 ) & 1 )
 67#define P_aso ( 1 << 10 )
 68#define P_ASO(n) ( ( n >> 10 ) & 1 )
 69#define P_rexx ( 1 << 11 )
 70#define P_REXX(n) ( ( n >> 11 ) & 1 )
 71#define P_ImpAddr ( 1 << 12 )
 72#define P_IMPADDR(n) ( ( n >> 12 ) & 1 )
 73#define P_seg ( 1 << 13 )
 74#define P_SEG(n) ( ( n >> 13 ) & 1 )
 75#define P_sext ( 1 << 14 )
 76#define P_SEXT(n) ( ( n >> 14 ) & 1 )
 77
 78/* rex prefix bits */
 79#define REX_W(r) ( ( 0xF & ( r ) ) >> 3 )
 80#define REX_R(r) ( ( 0x7 & ( r ) ) >> 2 )
 81#define REX_X(r) ( ( 0x3 & ( r ) ) >> 1 )
 82#define REX_B(r) ( ( 0x1 & ( r ) ) >> 0 )
 83#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \
 84 ( P_REXR(n) << 2 ) | \
 85 ( P_REXX(n) << 1 ) | \
 86 ( P_REXB(n) << 0 ) )
 87
 88/* scable-index-base bits */
 89#define SIB_S(b) ( ( b ) >> 6 )
 90#define SIB_I(b) ( ( ( b ) >> 3 ) & 7 )
 91#define SIB_B(b) ( ( b ) & 7 )
 92
 93/* modrm bits */
 94#define MODRM_REG(b) ( ( ( b ) >> 3 ) & 7 )
 95#define MODRM_NNN(b) ( ( ( b ) >> 3 ) & 7 )
 96#define MODRM_MOD(b) ( ( ( b ) >> 6 ) & 3 )
 97#define MODRM_RM(b) ( ( b ) & 7 )
 98
 99/* operand type constants -- order is important! */
 100
 101enum ud_operand_code {
 102 OP_NONE,
 103
 104 OP_A, OP_E, OP_M, OP_G,
 105 OP_I,
 106
 107 OP_AL, OP_CL, OP_DL, OP_BL,
 108 OP_AH, OP_CH, OP_DH, OP_BH,
 109
 110 OP_ALr8b, OP_CLr9b, OP_DLr10b, OP_BLr11b,
 111 OP_AHr12b, OP_CHr13b, OP_DHr14b, OP_BHr15b,
 112
 113 OP_AX, OP_CX, OP_DX, OP_BX,
 114 OP_SI, OP_DI, OP_SP, OP_BP,
 115
 116 OP_rAX, OP_rCX, OP_rDX, OP_rBX,
 117 OP_rSP, OP_rBP, OP_rSI, OP_rDI,
 118
 119 OP_rAXr8, OP_rCXr9, OP_rDXr10, OP_rBXr11,
 120 OP_rSPr12, OP_rBPr13, OP_rSIr14, OP_rDIr15,
 121
 122 OP_eAX, OP_eCX, OP_eDX, OP_eBX,
 123 OP_eSP, OP_eBP, OP_eSI, OP_eDI,
 124
 125 OP_ES, OP_CS, OP_SS, OP_DS,
 126 OP_FS, OP_GS,
 127
 128 OP_ST0, OP_ST1, OP_ST2, OP_ST3,
 129 OP_ST4, OP_ST5, OP_ST6, OP_ST7,
 130
 131 OP_J, OP_S, OP_O,
 132 OP_I1, OP_I3,
 133
 134 OP_V, OP_W, OP_Q, OP_P,
 135
 136 OP_R, OP_C, OP_D, OP_VR, OP_PR,
 137
 138 OP_MR
 139} UD_ATTR_PACKED;
 140
 141
 142/* operand size constants */
 143
 144enum ud_operand_size {
 145 SZ_NA = 0,
 146 SZ_Z = 1,
 147 SZ_V = 2,
 148 SZ_P = 3,
 149 SZ_WP = 4,
 150 SZ_DP = 5,
 151 SZ_MDQ = 6,
 152 SZ_RDQ = 7,
 153
 154 /* the following values are used as is,
 155 * and thus hard-coded. changing them
 156 * will break internals
 157 */
 158 SZ_B = 8,
 159 SZ_W = 16,
 160 SZ_D = 32,
 161 SZ_Q = 64,
 162 SZ_T = 80,
 163 SZ_O = 128,
 164
 165 SZ_WV = 17,
 166 SZ_BV = 18,
 167 SZ_DY = 19
 168
 169} UD_ATTR_PACKED;
 170
 171
 172/* A single operand of an entry in the instruction table.
 173 * (internal use only)
 174 */
 175struct ud_itab_entry_operand
 176{
 177 enum ud_operand_code type;
 178 enum ud_operand_size size;
 179};
 180
 181
 182/* A single entry in an instruction table.
 183 *(internal use only)
 184 */
 185struct ud_itab_entry
 186{
 187 enum ud_mnemonic_code mnemonic;
 188 struct ud_itab_entry_operand operand1;
 189 struct ud_itab_entry_operand operand2;
 190 struct ud_itab_entry_operand operand3;
 191 uint32_t prefix;
 192};
 193
 194struct ud_lookup_table_list_entry {
 195 const uint16_t *table;
 196 enum ud_table_type type;
 197 const char *meta;
 198};
 199
 200
 201static inline unsigned int sse_pfx_idx( const unsigned int pfx )
 202{
 203 /* 00 = 0
 204 * f2 = 1
 205 * f3 = 2
 206 * 66 = 3
 207 */
 208 return ( ( pfx & 0xf ) + 1 ) / 2;
 209}
 210
 211static inline unsigned int mode_idx( const unsigned int mode )
 212{
 213 /* 16 = 0
 214 * 32 = 1
 215 * 64 = 2
 216 */
 217 return ( mode / 32 );
 218}
 219
 220static inline unsigned int modrm_mod_idx( const unsigned int mod )
 221{
 222 /* !11 = 0
 223 * 11 = 1
 224 */
 225 return ( mod + 1 ) / 4;
 226}
 227
 228static inline unsigned int vendor_idx( const unsigned int vendor )
 229{
 230 switch ( vendor ) {
 231 case UD_VENDOR_AMD: return 0;
 232 case UD_VENDOR_INTEL: return 1;
 233 case UD_VENDOR_ANY: return 2;
 234 default: return 2;
 235 }
 236}
 237
 238static inline unsigned int is_group_ptr( uint16_t ptr )
 239{
 240 return ( 0x8000 & ptr );
 241}
 242
 243static inline unsigned int group_idx( uint16_t ptr )
 244{
 245 return ( ~0x8000 & ptr );
 246}
 247
 248
 249extern struct ud_itab_entry ud_itab[];
 250extern struct ud_lookup_table_list_entry ud_lookup_table_list[];
 251
 252#endif /* UD_DECODE_H */
 253
 254/* vim:cindent
 255 * vim:expandtab
 256 * vim:ts=4
 257 * vim:sw=4
 258 */
0

Source/JavaScriptCore/disassembler/udis86/udis86_extern.h

 1/* udis86 - libudis86/extern.h
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UD_EXTERN_H
 27#define UD_EXTERN_H
 28
 29#ifdef __cplusplus
 30extern "C" {
 31#endif
 32
 33#include "udis86_types.h"
 34
 35/* ============================= PUBLIC API ================================= */
 36
 37extern void ud_init(struct ud*);
 38
 39extern void ud_set_mode(struct ud*, uint8_t);
 40
 41extern void ud_set_pc(struct ud*, uint64_t);
 42
 43extern void ud_set_input_hook(struct ud*, int (*)(struct ud*));
 44
 45extern void ud_set_input_buffer(struct ud*, uint8_t*, size_t);
 46
 47#ifndef __UD_STANDALONE__
 48extern void ud_set_input_file(struct ud*, FILE*);
 49#endif /* __UD_STANDALONE__ */
 50
 51extern void ud_set_vendor(struct ud*, unsigned);
 52
 53extern void ud_set_syntax(struct ud*, void (*)(struct ud*));
 54
 55extern void ud_input_skip(struct ud*, size_t);
 56
 57extern int ud_input_end(struct ud*);
 58
 59extern unsigned int ud_decode(struct ud*);
 60
 61extern unsigned int ud_disassemble(struct ud*);
 62
 63extern void ud_translate_intel(struct ud*);
 64
 65extern void ud_translate_att(struct ud*);
 66
 67extern char* ud_insn_asm(struct ud* u);
 68
 69extern uint8_t* ud_insn_ptr(struct ud* u);
 70
 71extern uint64_t ud_insn_off(struct ud*);
 72
 73extern char* ud_insn_hex(struct ud*);
 74
 75extern unsigned int ud_insn_len(struct ud* u);
 76
 77extern const char* ud_lookup_mnemonic(enum ud_mnemonic_code c);
 78
 79extern void ud_set_user_opaque_data(struct ud*, void*);
 80
 81extern void *ud_get_user_opaque_data(struct ud*);
 82
 83/* ========================================================================== */
 84
 85#ifdef __cplusplus
 86}
 87#endif
 88#endif
0

Source/JavaScriptCore/disassembler/udis86/udis86_input.c

 1/* udis86 - libudis86/input.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#include "config.h"
 27#include <wtf/Platform.h>
 28
 29#if USE(UDIS86)
 30
 31#include "udis86_extern.h"
 32#include "udis86_types.h"
 33#include "udis86_input.h"
 34
 35/* -----------------------------------------------------------------------------
 36 * inp_buff_hook() - Hook for buffered inputs.
 37 * -----------------------------------------------------------------------------
 38 */
 39static int
 40inp_buff_hook(struct ud* u)
 41{
 42 if (u->inp_buff < u->inp_buff_end)
 43 return *u->inp_buff++;
 44 else return -1;
 45}
 46
 47#ifndef __UD_STANDALONE__
 48/* -----------------------------------------------------------------------------
 49 * inp_file_hook() - Hook for FILE inputs.
 50 * -----------------------------------------------------------------------------
 51 */
 52static int
 53inp_file_hook(struct ud* u)
 54{
 55 return fgetc(u->inp_file);
 56}
 57#endif /* __UD_STANDALONE__*/
 58
 59/* =============================================================================
 60 * ud_inp_set_hook() - Sets input hook.
 61 * =============================================================================
 62 */
 63extern void
 64ud_set_input_hook(register struct ud* u, int (*hook)(struct ud*))
 65{
 66 u->inp_hook = hook;
 67 ud_inp_init(u);
 68}
 69
 70extern void
 71ud_set_user_opaque_data( struct ud * u, void * opaque )
 72{
 73 u->user_opaque_data = opaque;
 74}
 75
 76extern void *
 77ud_get_user_opaque_data( struct ud * u )
 78{
 79 return u->user_opaque_data;
 80}
 81
 82/* =============================================================================
 83 * ud_inp_set_buffer() - Set buffer as input.
 84 * =============================================================================
 85 */
 86extern void
 87ud_set_input_buffer(register struct ud* u, uint8_t* buf, size_t len)
 88{
 89 u->inp_hook = inp_buff_hook;
 90 u->inp_buff = buf;
 91 u->inp_buff_end = buf + len;
 92 ud_inp_init(u);
 93}
 94
 95#ifndef __UD_STANDALONE__
 96/* =============================================================================
 97 * ud_input_set_file() - Set buffer as input.
 98 * =============================================================================
 99 */
 100extern void
 101ud_set_input_file(register struct ud* u, FILE* f)
 102{
 103 u->inp_hook = inp_file_hook;
 104 u->inp_file = f;
 105 ud_inp_init(u);
 106}
 107#endif /* __UD_STANDALONE__ */
 108
 109/* =============================================================================
 110 * ud_input_skip() - Skip n input bytes.
 111 * =============================================================================
 112 */
 113extern void
 114ud_input_skip(struct ud* u, size_t n)
 115{
 116 while (n--) {
 117 u->inp_hook(u);
 118 }
 119}
 120
 121/* =============================================================================
 122 * ud_input_end() - Test for end of input.
 123 * =============================================================================
 124 */
 125extern int
 126ud_input_end(struct ud* u)
 127{
 128 return (u->inp_curr == u->inp_fill) && u->inp_end;
 129}
 130
 131/* -----------------------------------------------------------------------------
 132 * ud_inp_next() - Loads and returns the next byte from input.
 133 *
 134 * inp_curr and inp_fill are pointers to the cache. The program is written based
 135 * on the property that they are 8-bits in size, and will eventually wrap around
 136 * forming a circular buffer. So, the size of the cache is 256 in size, kind of
 137 * unnecessary yet optimized.
 138 *
 139 * A buffer inp_sess stores the bytes disassembled for a single session.
 140 * -----------------------------------------------------------------------------
 141 */
 142extern uint8_t ud_inp_next(struct ud* u)
 143{
 144 int c = -1;
 145 /* if current pointer is not upto the fill point in the
 146 * input cache.
 147 */
 148 if ( u->inp_curr != u->inp_fill ) {
 149 c = u->inp_cache[ ++u->inp_curr ];
 150 /* if !end-of-input, call the input hook and get a byte */
 151 } else if ( u->inp_end || ( c = u->inp_hook( u ) ) == -1 ) {
 152 /* end-of-input, mark it as an error, since the decoder,
 153 * expected a byte more.
 154 */
 155 u->error = 1;
 156 /* flag end of input */
 157 u->inp_end = 1;
 158 return 0;
 159 } else {
 160 /* increment pointers, we have a new byte. */
 161 u->inp_curr = ++u->inp_fill;
 162 /* add the byte to the cache */
 163 u->inp_cache[ u->inp_fill ] = c;
 164 }
 165 /* record bytes input per decode-session. */
 166 u->inp_sess[ u->inp_ctr++ ] = c;
 167 /* return byte */
 168 return ( uint8_t ) c;
 169}
 170
 171/* -----------------------------------------------------------------------------
 172 * ud_inp_back() - Move back a single byte in the stream.
 173 * -----------------------------------------------------------------------------
 174 */
 175extern void
 176ud_inp_back(struct ud* u)
 177{
 178 if ( u->inp_ctr > 0 ) {
 179 --u->inp_curr;
 180 --u->inp_ctr;
 181 }
 182}
 183
 184/* -----------------------------------------------------------------------------
 185 * ud_inp_peek() - Peek into the next byte in source.
 186 * -----------------------------------------------------------------------------
 187 */
 188extern uint8_t
 189ud_inp_peek(struct ud* u)
 190{
 191 uint8_t r = ud_inp_next(u);
 192 if ( !u->error ) ud_inp_back(u); /* Don't backup if there was an error */
 193 return r;
 194}
 195
 196/* -----------------------------------------------------------------------------
 197 * ud_inp_move() - Move ahead n input bytes.
 198 * -----------------------------------------------------------------------------
 199 */
 200extern void
 201ud_inp_move(struct ud* u, size_t n)
 202{
 203 while (n--)
 204 ud_inp_next(u);
 205}
 206
 207/*------------------------------------------------------------------------------
 208 * ud_inp_uintN() - return uintN from source.
 209 *------------------------------------------------------------------------------
 210 */
 211extern uint8_t
 212ud_inp_uint8(struct ud* u)
 213{
 214 return ud_inp_next(u);
 215}
 216
 217extern uint16_t
 218ud_inp_uint16(struct ud* u)
 219{
 220 uint16_t r, ret;
 221
 222 ret = ud_inp_next(u);
 223 r = ud_inp_next(u);
 224 return ret | (r << 8);
 225}
 226
 227extern uint32_t
 228ud_inp_uint32(struct ud* u)
 229{
 230 uint32_t r, ret;
 231
 232 ret = ud_inp_next(u);
 233 r = ud_inp_next(u);
 234 ret = ret | (r << 8);
 235 r = ud_inp_next(u);
 236 ret = ret | (r << 16);
 237 r = ud_inp_next(u);
 238 return ret | (r << 24);
 239}
 240
 241extern uint64_t
 242ud_inp_uint64(struct ud* u)
 243{
 244 uint64_t r, ret;
 245
 246 ret = ud_inp_next(u);
 247 r = ud_inp_next(u);
 248 ret = ret | (r << 8);
 249 r = ud_inp_next(u);
 250 ret = ret | (r << 16);
 251 r = ud_inp_next(u);
 252 ret = ret | (r << 24);
 253 r = ud_inp_next(u);
 254 ret = ret | (r << 32);
 255 r = ud_inp_next(u);
 256 ret = ret | (r << 40);
 257 r = ud_inp_next(u);
 258 ret = ret | (r << 48);
 259 r = ud_inp_next(u);
 260 return ret | (r << 56);
 261}
 262
 263#endif // USE(UDIS86)
0

Source/JavaScriptCore/disassembler/udis86/udis86_input.h

 1/* udis86 - libudis86/input.h
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UD_INPUT_H
 27#define UD_INPUT_H
 28
 29#include "udis86_types.h"
 30
 31uint8_t ud_inp_next(struct ud*);
 32uint8_t ud_inp_peek(struct ud*);
 33uint8_t ud_inp_uint8(struct ud*);
 34uint16_t ud_inp_uint16(struct ud*);
 35uint32_t ud_inp_uint32(struct ud*);
 36uint64_t ud_inp_uint64(struct ud*);
 37void ud_inp_move(struct ud*, size_t);
 38void ud_inp_back(struct ud*);
 39
 40/* ud_inp_init() - Initializes the input system. */
 41#define ud_inp_init(u) \
 42do { \
 43 u->inp_curr = 0; \
 44 u->inp_fill = 0; \
 45 u->inp_ctr = 0; \
 46 u->inp_end = 0; \
 47} while (0)
 48
 49/* ud_inp_start() - Should be called before each de-code operation. */
 50#define ud_inp_start(u) u->inp_ctr = 0
 51
 52/* ud_inp_back() - Resets the current pointer to its position before the current
 53 * instruction disassembly was started.
 54 */
 55#define ud_inp_reset(u) \
 56do { \
 57 u->inp_curr -= u->inp_ctr; \
 58 u->inp_ctr = 0; \
 59} while (0)
 60
 61/* ud_inp_sess() - Returns the pointer to current session. */
 62#define ud_inp_sess(u) (u->inp_sess)
 63
 64/* inp_cur() - Returns the current input byte. */
 65#define ud_inp_curr(u) ((u)->inp_cache[(u)->inp_curr])
 66
 67#endif
0

Source/JavaScriptCore/disassembler/udis86/udis86_itab_holder.c

 1/*
 2 * Copyright (C) 2012 Apple Inc. All rights reserved.
 3 *
 4 * Redistribution and use in source and binary forms, with or without
 5 * modification, are permitted provided that the following conditions
 6 * are met:
 7 * 1. Redistributions of source code must retain the above copyright
 8 * notice, this list of conditions and the following disclaimer.
 9 * 2. Redistributions in binary form must reproduce the above copyright
 10 * notice, this list of conditions and the following disclaimer in the
 11 * documentation and/or other materials provided with the distribution.
 12 *
 13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
 14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
 17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 24 */
 25
 26#include "config.h"
 27#include <wtf/Platform.h>
 28
 29#if USE(UDIS86)
 30
 31#include "udis86_itab.c"
 32
 33#endif
 34
0

Source/JavaScriptCore/disassembler/udis86/udis86_syn-att.c

 1/* udis86 - libudis86/syn-att.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#include "config.h"
 27#include <wtf/Platform.h>
 28
 29#if USE(UDIS86)
 30
 31#include "udis86_types.h"
 32#include "udis86_extern.h"
 33#include "udis86_decode.h"
 34#include "udis86_itab.h"
 35#include "udis86_syn.h"
 36
 37/* -----------------------------------------------------------------------------
 38 * opr_cast() - Prints an operand cast.
 39 * -----------------------------------------------------------------------------
 40 */
 41static void
 42opr_cast(struct ud* u, struct ud_operand* op)
 43{
 44 switch(op->size) {
 45 case 16 : case 32 :
 46 mkasm(u, "*"); break;
 47 default: break;
 48 }
 49}
 50
 51/* -----------------------------------------------------------------------------
 52 * gen_operand() - Generates assembly output for each operand.
 53 * -----------------------------------------------------------------------------
 54 */
 55static void
 56gen_operand(struct ud* u, struct ud_operand* op)
 57{
 58 switch(op->type) {
 59 case UD_OP_REG:
 60 mkasm(u, "%%%s", ud_reg_tab[op->base - UD_R_AL]);
 61 break;
 62
 63 case UD_OP_MEM:
 64 if (u->br_far) opr_cast(u, op);
 65 if (u->pfx_seg)
 66 mkasm(u, "%%%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
 67 if (op->offset == 8) {
 68 if (op->lval.sbyte < 0)
 69 mkasm(u, "-0x%x", (-op->lval.sbyte) & 0xff);
 70 else mkasm(u, "0x%x", op->lval.sbyte);
 71 }
 72 else if (op->offset == 16)
 73 mkasm(u, "0x%x", op->lval.uword);
 74 else if (op->offset == 32)
 75 mkasm(u, "0x%lx", op->lval.udword);
 76 else if (op->offset == 64)
 77 mkasm(u, "0x" FMT64 "x", op->lval.uqword);
 78
 79 if (op->base)
 80 mkasm(u, "(%%%s", ud_reg_tab[op->base - UD_R_AL]);
 81 if (op->index) {
 82 if (op->base)
 83 mkasm(u, ",");
 84 else mkasm(u, "(");
 85 mkasm(u, "%%%s", ud_reg_tab[op->index - UD_R_AL]);
 86 }
 87 if (op->scale)
 88 mkasm(u, ",%d", op->scale);
 89 if (op->base || op->index)
 90 mkasm(u, ")");
 91 break;
 92
 93 case UD_OP_IMM: {
 94 int64_t imm = 0;
 95 uint64_t sext_mask = 0xffffffffffffffffull;
 96 unsigned sext_size = op->size;
 97
 98 switch (op->size) {
 99 case 8: imm = op->lval.sbyte; break;
 100 case 16: imm = op->lval.sword; break;
 101 case 32: imm = op->lval.sdword; break;
 102 case 64: imm = op->lval.sqword; break;
 103 }
 104 if ( P_SEXT( u->itab_entry->prefix ) ) {
 105 sext_size = u->operand[ 0 ].size;
 106 if ( u->mnemonic == UD_Ipush )
 107 /* push sign-extends to operand size */
 108 sext_size = u->opr_mode;
 109 }
 110 if ( sext_size < 64 )
 111 sext_mask = ( 1ull << sext_size ) - 1;
 112 mkasm( u, "0x" FMT64 "x", imm & sext_mask );
 113
 114 break;
 115 }
 116
 117 case UD_OP_JIMM:
 118 switch (op->size) {
 119 case 8:
 120 mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sbyte);
 121 break;
 122 case 16:
 123 mkasm(u, "0x" FMT64 "x", ( u->pc + op->lval.sword ) & 0xffff );
 124 break;
 125 case 32:
 126 mkasm(u, "0x" FMT64 "x", ( u->pc + op->lval.sdword ) & 0xfffffffful );
 127 break;
 128 default:break;
 129 }
 130 break;
 131
 132 case UD_OP_PTR:
 133 switch (op->size) {
 134 case 32:
 135 mkasm(u, "$0x%x, $0x%x", op->lval.ptr.seg,
 136 op->lval.ptr.off & 0xFFFF);
 137 break;
 138 case 48:
 139 mkasm(u, "$0x%x, $0x%lx", op->lval.ptr.seg,
 140 op->lval.ptr.off);
 141 break;
 142 }
 143 break;
 144
 145 default: return;
 146 }
 147}
 148
 149/* =============================================================================
 150 * translates to AT&T syntax
 151 * =============================================================================
 152 */
 153extern void
 154ud_translate_att(struct ud *u)
 155{
 156 int size = 0;
 157
 158 /* check if P_OSO prefix is used */
 159 if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
 160 switch (u->dis_mode) {
 161 case 16:
 162 mkasm(u, "o32 ");
 163 break;
 164 case 32:
 165 case 64:
 166 mkasm(u, "o16 ");
 167 break;
 168 }
 169 }
 170
 171 /* check if P_ASO prefix was used */
 172 if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
 173 switch (u->dis_mode) {
 174 case 16:
 175 mkasm(u, "a32 ");
 176 break;
 177 case 32:
 178 mkasm(u, "a16 ");
 179 break;
 180 case 64:
 181 mkasm(u, "a32 ");
 182 break;
 183 }
 184 }
 185
 186 if (u->pfx_lock)
 187 mkasm(u, "lock ");
 188 if (u->pfx_rep)
 189 mkasm(u, "rep ");
 190 if (u->pfx_repne)
 191 mkasm(u, "repne ");
 192
 193 /* special instructions */
 194 switch (u->mnemonic) {
 195 case UD_Iretf:
 196 mkasm(u, "lret ");
 197 break;
 198 case UD_Idb:
 199 mkasm(u, ".byte 0x%x", u->operand[0].lval.ubyte);
 200 return;
 201 case UD_Ijmp:
 202 case UD_Icall:
 203 if (u->br_far) mkasm(u, "l");
 204 mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
 205 break;
 206 case UD_Ibound:
 207 case UD_Ienter:
 208 if (u->operand[0].type != UD_NONE)
 209 gen_operand(u, &u->operand[0]);
 210 if (u->operand[1].type != UD_NONE) {
 211 mkasm(u, ",");
 212 gen_operand(u, &u->operand[1]);
 213 }
 214 return;
 215 default:
 216 mkasm(u, "%s", ud_lookup_mnemonic(u->mnemonic));
 217 }
 218
 219 if (u->c1)
 220 size = u->operand[0].size;
 221 else if (u->c2)
 222 size = u->operand[1].size;
 223 else if (u->c3)
 224 size = u->operand[2].size;
 225
 226 if (size == 8)
 227 mkasm(u, "b");
 228 else if (size == 16)
 229 mkasm(u, "w");
 230 else if (size == 64)
 231 mkasm(u, "q");
 232
 233 mkasm(u, " ");
 234
 235 if (u->operand[2].type != UD_NONE) {
 236 gen_operand(u, &u->operand[2]);
 237 mkasm(u, ", ");
 238 }
 239
 240 if (u->operand[1].type != UD_NONE) {
 241 gen_operand(u, &u->operand[1]);
 242 mkasm(u, ", ");
 243 }
 244
 245 if (u->operand[0].type != UD_NONE)
 246 gen_operand(u, &u->operand[0]);
 247}
 248
 249#endif // USE(UDIS86)
 250
0

Source/JavaScriptCore/disassembler/udis86/udis86_syn-intel.c

 1/* udis86 - libudis86/syn-intel.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#include "config.h"
 27#include <wtf/Platform.h>
 28
 29#if USE(UDIS86)
 30
 31#include "udis86_types.h"
 32#include "udis86_extern.h"
 33#include "udis86_decode.h"
 34#include "udis86_itab.h"
 35#include "udis86_syn.h"
 36
 37/* -----------------------------------------------------------------------------
 38 * opr_cast() - Prints an operand cast.
 39 * -----------------------------------------------------------------------------
 40 */
 41static void
 42opr_cast(struct ud* u, struct ud_operand* op)
 43{
 44 switch(op->size) {
 45 case 8: mkasm(u, "byte " ); break;
 46 case 16: mkasm(u, "word " ); break;
 47 case 32: mkasm(u, "dword "); break;
 48 case 64: mkasm(u, "qword "); break;
 49 case 80: mkasm(u, "tword "); break;
 50 default: break;
 51 }
 52 if (u->br_far)
 53 mkasm(u, "far ");
 54}
 55
 56/* -----------------------------------------------------------------------------
 57 * gen_operand() - Generates assembly output for each operand.
 58 * -----------------------------------------------------------------------------
 59 */
 60static void gen_operand(struct ud* u, struct ud_operand* op, int syn_cast)
 61{
 62 switch(op->type) {
 63 case UD_OP_REG:
 64 mkasm(u, ud_reg_tab[op->base - UD_R_AL]);
 65 break;
 66
 67 case UD_OP_MEM: {
 68
 69 int op_f = 0;
 70
 71 if (syn_cast)
 72 opr_cast(u, op);
 73
 74 mkasm(u, "[");
 75
 76 if (u->pfx_seg)
 77 mkasm(u, "%s:", ud_reg_tab[u->pfx_seg - UD_R_AL]);
 78
 79 if (op->base) {
 80 mkasm(u, "%s", ud_reg_tab[op->base - UD_R_AL]);
 81 op_f = 1;
 82 }
 83
 84 if (op->index) {
 85 if (op_f)
 86 mkasm(u, "+");
 87 mkasm(u, "%s", ud_reg_tab[op->index - UD_R_AL]);
 88 op_f = 1;
 89 }
 90
 91 if (op->scale)
 92 mkasm(u, "*%d", op->scale);
 93
 94 if (op->offset == 8) {
 95 if (op->lval.sbyte < 0)
 96 mkasm(u, "-0x%x", -op->lval.sbyte);
 97 else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sbyte);
 98 }
 99 else if (op->offset == 16)
 100 mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.uword);
 101 else if (op->offset == 32) {
 102 if (u->adr_mode == 64) {
 103 if (op->lval.sdword < 0)
 104 mkasm(u, "-0x%x", -op->lval.sdword);
 105 else mkasm(u, "%s0x%x", (op_f) ? "+" : "", op->lval.sdword);
 106 }
 107 else mkasm(u, "%s0x%lx", (op_f) ? "+" : "", op->lval.udword);
 108 }
 109 else if (op->offset == 64)
 110 mkasm(u, "%s0x" FMT64 "x", (op_f) ? "+" : "", op->lval.uqword);
 111
 112 mkasm(u, "]");
 113 break;
 114 }
 115
 116 case UD_OP_IMM: {
 117 int64_t imm = 0;
 118 uint64_t sext_mask = 0xffffffffffffffffull;
 119 unsigned sext_size = op->size;
 120
 121 if (syn_cast)
 122 opr_cast(u, op);
 123 switch (op->size) {
 124 case 8: imm = op->lval.sbyte; break;
 125 case 16: imm = op->lval.sword; break;
 126 case 32: imm = op->lval.sdword; break;
 127 case 64: imm = op->lval.sqword; break;
 128 }
 129 if ( P_SEXT( u->itab_entry->prefix ) ) {
 130 sext_size = u->operand[ 0 ].size;
 131 if ( u->mnemonic == UD_Ipush )
 132 /* push sign-extends to operand size */
 133 sext_size = u->opr_mode;
 134 }
 135 if ( sext_size < 64 )
 136 sext_mask = ( 1ull << sext_size ) - 1;
 137 mkasm( u, "0x" FMT64 "x", imm & sext_mask );
 138
 139 break;
 140 }
 141
 142
 143 case UD_OP_JIMM:
 144 if (syn_cast) opr_cast(u, op);
 145 switch (op->size) {
 146 case 8:
 147 mkasm(u, "0x" FMT64 "x", u->pc + op->lval.sbyte);
 148 break;
 149 case 16:
 150 mkasm(u, "0x" FMT64 "x", ( u->pc + op->lval.sword ) & 0xffff );
 151 break;
 152 case 32:
 153 mkasm(u, "0x" FMT64 "x", ( u->pc + op->lval.sdword ) & 0xfffffffful );
 154 break;
 155 default:break;
 156 }
 157 break;
 158
 159 case UD_OP_PTR:
 160 switch (op->size) {
 161 case 32:
 162 mkasm(u, "word 0x%x:0x%x", op->lval.ptr.seg,
 163 op->lval.ptr.off & 0xFFFF);
 164 break;
 165 case 48:
 166 mkasm(u, "dword 0x%x:0x%lx", op->lval.ptr.seg,
 167 op->lval.ptr.off);
 168 break;
 169 }
 170 break;
 171
 172 case UD_OP_CONST:
 173 if (syn_cast) opr_cast(u, op);
 174 mkasm(u, "%d", op->lval.udword);
 175 break;
 176
 177 default: return;
 178 }
 179}
 180
 181/* =============================================================================
 182 * translates to intel syntax
 183 * =============================================================================
 184 */
 185extern void ud_translate_intel(struct ud* u)
 186{
 187 /* -- prefixes -- */
 188
 189 /* check if P_OSO prefix is used */
 190 if (! P_OSO(u->itab_entry->prefix) && u->pfx_opr) {
 191 switch (u->dis_mode) {
 192 case 16:
 193 mkasm(u, "o32 ");
 194 break;
 195 case 32:
 196 case 64:
 197 mkasm(u, "o16 ");
 198 break;
 199 }
 200 }
 201
 202 /* check if P_ASO prefix was used */
 203 if (! P_ASO(u->itab_entry->prefix) && u->pfx_adr) {
 204 switch (u->dis_mode) {
 205 case 16:
 206 mkasm(u, "a32 ");
 207 break;
 208 case 32:
 209 mkasm(u, "a16 ");
 210 break;
 211 case 64:
 212 mkasm(u, "a32 ");
 213 break;
 214 }
 215 }
 216
 217 if ( u->pfx_seg &&
 218 u->operand[0].type != UD_OP_MEM &&
 219 u->operand[1].type != UD_OP_MEM ) {
 220 mkasm(u, "%s ", ud_reg_tab[u->pfx_seg - UD_R_AL]);
 221 }
 222 if (u->pfx_lock)
 223 mkasm(u, "lock ");
 224 if (u->pfx_rep)
 225 mkasm(u, "rep ");
 226 if (u->pfx_repne)
 227 mkasm(u, "repne ");
 228
 229 /* print the instruction mnemonic */
 230 mkasm(u, "%s ", ud_lookup_mnemonic(u->mnemonic));
 231
 232 /* operand 1 */
 233 if (u->operand[0].type != UD_NONE) {
 234 int cast = 0;
 235 if ( u->operand[0].type == UD_OP_IMM &&
 236 u->operand[1].type == UD_NONE )
 237 cast = u->c1;
 238 if ( u->operand[0].type == UD_OP_MEM ) {
 239 cast = u->c1;
 240 if ( u->operand[1].type == UD_OP_IMM ||
 241 u->operand[1].type == UD_OP_CONST )
 242 cast = 1;
 243 if ( u->operand[1].type == UD_NONE )
 244 cast = 1;
 245 if ( ( u->operand[0].size != u->operand[1].size ) && u->operand[1].size )
 246 cast = 1;
 247 } else if ( u->operand[ 0 ].type == UD_OP_JIMM ) {
 248 if ( u->operand[ 0 ].size > 8 ) cast = 1;
 249 }
 250 gen_operand(u, &u->operand[0], cast);
 251 }
 252 /* operand 2 */
 253 if (u->operand[1].type != UD_NONE) {
 254 int cast = 0;
 255 mkasm(u, ", ");
 256 if ( u->operand[1].type == UD_OP_MEM ) {
 257 cast = u->c1;
 258
 259 if ( u->operand[0].type != UD_OP_REG )
 260 cast = 1;
 261 if ( u->operand[0].size != u->operand[1].size && u->operand[1].size )
 262 cast = 1;
 263 if ( u->operand[0].type == UD_OP_REG &&
 264 u->operand[0].base >= UD_R_ES &&
 265 u->operand[0].base <= UD_R_GS )
 266 cast = 0;
 267 }
 268 gen_operand(u, &u->operand[1], cast );
 269 }
 270
 271 /* operand 3 */
 272 if (u->operand[2].type != UD_NONE) {
 273 mkasm(u, ", ");
 274 gen_operand(u, &u->operand[2], u->c3);
 275 }
 276}
 277
 278#endif // USE(UDIS86)
 279
0

Source/JavaScriptCore/disassembler/udis86/udis86_syn.c

 1/* udis86 - libudis86/syn.c
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26
 27#include "config.h"
 28#include <wtf/Platform.h>
 29
 30#if USE(UDIS86)
 31
 32/* -----------------------------------------------------------------------------
 33 * Intel Register Table - Order Matters (types.h)!
 34 * -----------------------------------------------------------------------------
 35 */
 36const char* ud_reg_tab[] =
 37{
 38 "al", "cl", "dl", "bl",
 39 "ah", "ch", "dh", "bh",
 40 "spl", "bpl", "sil", "dil",
 41 "r8b", "r9b", "r10b", "r11b",
 42 "r12b", "r13b", "r14b", "r15b",
 43
 44 "ax", "cx", "dx", "bx",
 45 "sp", "bp", "si", "di",
 46 "r8w", "r9w", "r10w", "r11w",
 47 "r12w", "r13W" , "r14w", "r15w",
 48
 49 "eax", "ecx", "edx", "ebx",
 50 "esp", "ebp", "esi", "edi",
 51 "r8d", "r9d", "r10d", "r11d",
 52 "r12d", "r13d", "r14d", "r15d",
 53
 54 "rax", "rcx", "rdx", "rbx",
 55 "rsp", "rbp", "rsi", "rdi",
 56 "r8", "r9", "r10", "r11",
 57 "r12", "r13", "r14", "r15",
 58
 59 "es", "cs", "ss", "ds",
 60 "fs", "gs",
 61
 62 "cr0", "cr1", "cr2", "cr3",
 63 "cr4", "cr5", "cr6", "cr7",
 64 "cr8", "cr9", "cr10", "cr11",
 65 "cr12", "cr13", "cr14", "cr15",
 66
 67 "dr0", "dr1", "dr2", "dr3",
 68 "dr4", "dr5", "dr6", "dr7",
 69 "dr8", "dr9", "dr10", "dr11",
 70 "dr12", "dr13", "dr14", "dr15",
 71
 72 "mm0", "mm1", "mm2", "mm3",
 73 "mm4", "mm5", "mm6", "mm7",
 74
 75 "st0", "st1", "st2", "st3",
 76 "st4", "st5", "st6", "st7",
 77
 78 "xmm0", "xmm1", "xmm2", "xmm3",
 79 "xmm4", "xmm5", "xmm6", "xmm7",
 80 "xmm8", "xmm9", "xmm10", "xmm11",
 81 "xmm12", "xmm13", "xmm14", "xmm15",
 82
 83 "rip"
 84};
 85
 86#endif // USE(UDIS86)
 87
0

Source/JavaScriptCore/disassembler/udis86/udis86_syn.h

 1/* udis86 - libudis86/syn.h
 2 *
 3 * Copyright (c) 2002-2009
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UD_SYN_H
 27#define UD_SYN_H
 28
 29#include "udis86_types.h"
 30#ifndef __UD_STANDALONE__
 31# include <stdarg.h>
 32#endif /* __UD_STANDALONE__ */
 33
 34extern const char* ud_reg_tab[];
 35
 36static void mkasm(struct ud* u, const char* fmt, ...)
 37{
 38 va_list ap;
 39 va_start(ap, fmt);
 40 u->insn_fill += vsprintf((char*) u->insn_buffer + u->insn_fill, fmt, ap);
 41 va_end(ap);
 42}
 43
 44#endif
0

Source/JavaScriptCore/disassembler/udis86/udis86_types.h

 1/* udis86 - libudis86/types.h
 2 *
 3 * Copyright (c) 2002-2009 Vivek Thampi
 4 * All rights reserved.
 5 *
 6 * Redistribution and use in source and binary forms, with or without modification,
 7 * are permitted provided that the following conditions are met:
 8 *
 9 * * Redistributions of source code must retain the above copyright notice,
 10 * this list of conditions and the following disclaimer.
 11 * * Redistributions in binary form must reproduce the above copyright notice,
 12 * this list of conditions and the following disclaimer in the documentation
 13 * and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 18 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26#ifndef UD_TYPES_H
 27#define UD_TYPES_H
 28
 29#ifndef __UD_STANDALONE__
 30# include <stdio.h>
 31#endif /* __UD_STANDALONE__ */
 32
 33/* gcc specific extensions */
 34#ifdef __GNUC__
 35# define UD_ATTR_PACKED __attribute__((packed))
 36#else
 37# define UD_ATTR_PACKED
 38#endif /* UD_ATTR_PACKED */
 39
 40#ifdef _MSC_VER
 41# define FMT64 "%I64"
 42 typedef unsigned __int8 uint8_t;
 43 typedef unsigned __int16 uint16_t;
 44 typedef unsigned __int32 uint32_t;
 45 typedef unsigned __int64 uint64_t;
 46 typedef __int8 int8_t;
 47 typedef __int16 int16_t;
 48 typedef __int32 int32_t;
 49 typedef __int64 int64_t;
 50#else
 51# define FMT64 "%ll"
 52# ifndef __UD_STANDALONE__
 53# include <inttypes.h>
 54# endif /* __UD_STANDALONE__ */
 55#endif
 56
 57/* -----------------------------------------------------------------------------
 58 * All possible "types" of objects in udis86. Order is Important!
 59 * -----------------------------------------------------------------------------
 60 */
 61enum ud_type
 62{
 63 UD_NONE,
 64
 65 /* 8 bit GPRs */
 66 UD_R_AL, UD_R_CL, UD_R_DL, UD_R_BL,
 67 UD_R_AH, UD_R_CH, UD_R_DH, UD_R_BH,
 68 UD_R_SPL, UD_R_BPL, UD_R_SIL, UD_R_DIL,
 69 UD_R_R8B, UD_R_R9B, UD_R_R10B, UD_R_R11B,
 70 UD_R_R12B, UD_R_R13B, UD_R_R14B, UD_R_R15B,
 71
 72 /* 16 bit GPRs */
 73 UD_R_AX, UD_R_CX, UD_R_DX, UD_R_BX,
 74 UD_R_SP, UD_R_BP, UD_R_SI, UD_R_DI,
 75 UD_R_R8W, UD_R_R9W, UD_R_R10W, UD_R_R11W,
 76 UD_R_R12W, UD_R_R13W, UD_R_R14W, UD_R_R15W,
 77
 78 /* 32 bit GPRs */
 79 UD_R_EAX, UD_R_ECX, UD_R_EDX, UD_R_EBX,
 80 UD_R_ESP, UD_R_EBP, UD_R_ESI, UD_R_EDI,
 81 UD_R_R8D, UD_R_R9D, UD_R_R10D, UD_R_R11D,
 82 UD_R_R12D, UD_R_R13D, UD_R_R14D, UD_R_R15D,
 83
 84 /* 64 bit GPRs */
 85 UD_R_RAX, UD_R_RCX, UD_R_RDX, UD_R_RBX,
 86 UD_R_RSP, UD_R_RBP, UD_R_RSI, UD_R_RDI,
 87 UD_R_R8, UD_R_R9, UD_R_R10, UD_R_R11,
 88 UD_R_R12, UD_R_R13, UD_R_R14, UD_R_R15,
 89
 90 /* segment registers */
 91 UD_R_ES, UD_R_CS, UD_R_SS, UD_R_DS,
 92 UD_R_FS, UD_R_GS,
 93
 94 /* control registers*/
 95 UD_R_CR0, UD_R_CR1, UD_R_CR2, UD_R_CR3,
 96 UD_R_CR4, UD_R_CR5, UD_R_CR6, UD_R_CR7,
 97 UD_R_CR8, UD_R_CR9, UD_R_CR10, UD_R_CR11,
 98 UD_R_CR12, UD_R_CR13, UD_R_CR14, UD_R_CR15,
 99
 100 /* debug registers */
 101 UD_R_DR0, UD_R_DR1, UD_R_DR2, UD_R_DR3,
 102 UD_R_DR4, UD_R_DR5, UD_R_DR6, UD_R_DR7,
 103 UD_R_DR8, UD_R_DR9, UD_R_DR10, UD_R_DR11,
 104 UD_R_DR12, UD_R_DR13, UD_R_DR14, UD_R_DR15,
 105
 106 /* mmx registers */
 107 UD_R_MM0, UD_R_MM1, UD_R_MM2, UD_R_MM3,
 108 UD_R_MM4, UD_R_MM5, UD_R_MM6, UD_R_MM7,
 109
 110 /* x87 registers */
 111 UD_R_ST0, UD_R_ST1, UD_R_ST2, UD_R_ST3,
 112 UD_R_ST4, UD_R_ST5, UD_R_ST6, UD_R_ST7,
 113
 114 /* extended multimedia registers */
 115 UD_R_XMM0, UD_R_XMM1, UD_R_XMM2, UD_R_XMM3,
 116 UD_R_XMM4, UD_R_XMM5, UD_R_XMM6, UD_R_XMM7,
 117 UD_R_XMM8, UD_R_XMM9, UD_R_XMM10, UD_R_XMM11,
 118 UD_R_XMM12, UD_R_XMM13, UD_R_XMM14, UD_R_XMM15,
 119
 120 UD_R_RIP,
 121
 122 /* Operand Types */
 123 UD_OP_REG, UD_OP_MEM, UD_OP_PTR, UD_OP_IMM,
 124 UD_OP_JIMM, UD_OP_CONST
 125};
 126
 127#include "udis86_itab.h"
 128
 129/* -----------------------------------------------------------------------------
 130 * struct ud_operand - Disassembled instruction Operand.
 131 * -----------------------------------------------------------------------------
 132 */
 133struct ud_operand
 134{
 135 enum ud_type type;
 136 uint8_t size;
 137 union {
 138 int8_t sbyte;
 139 uint8_t ubyte;
 140 int16_t sword;
 141 uint16_t uword;
 142 int32_t sdword;
 143 uint32_t udword;
 144 int64_t sqword;
 145 uint64_t uqword;
 146
 147 struct {
 148 uint16_t seg;
 149 uint32_t off;
 150 } ptr;
 151 } lval;
 152
 153 enum ud_type base;
 154 enum ud_type index;
 155 uint8_t offset;
 156 uint8_t scale;
 157};
 158
 159/* -----------------------------------------------------------------------------
 160 * struct ud - The udis86 object.
 161 * -----------------------------------------------------------------------------
 162 */
 163struct ud
 164{
 165 int (*inp_hook) (struct ud*);
 166 uint8_t inp_curr;
 167 uint8_t inp_fill;
 168#ifndef __UD_STANDALONE__
 169 FILE* inp_file;
 170#endif
 171 uint8_t inp_ctr;
 172 uint8_t* inp_buff;
 173 uint8_t* inp_buff_end;
 174 uint8_t inp_end;
 175 void (*translator)(struct ud*);
 176 uint64_t insn_offset;
 177 char insn_hexcode[32];
 178 char insn_buffer[64];
 179 unsigned int insn_fill;
 180 uint8_t dis_mode;
 181 uint64_t pc;
 182 uint8_t vendor;
 183 struct map_entry* mapen;
 184 enum ud_mnemonic_code mnemonic;
 185 struct ud_operand operand[3];
 186 uint8_t error;
 187 uint8_t pfx_rex;
 188 uint8_t pfx_seg;
 189 uint8_t pfx_opr;
 190 uint8_t pfx_adr;
 191 uint8_t pfx_lock;
 192 uint8_t pfx_rep;
 193 uint8_t pfx_repe;
 194 uint8_t pfx_repne;
 195 uint8_t pfx_insn;
 196 uint8_t default64;
 197 uint8_t opr_mode;
 198 uint8_t adr_mode;
 199 uint8_t br_far;
 200 uint8_t br_near;
 201 uint8_t implicit_addr;
 202 uint8_t c1;
 203 uint8_t c2;
 204 uint8_t c3;
 205 uint8_t inp_cache[256];
 206 uint8_t inp_sess[64];
 207 uint8_t have_modrm;
 208 uint8_t modrm;
 209 void * user_opaque_data;
 210 struct ud_itab_entry * itab_entry;
 211 struct ud_lookup_table_list_entry *le;
 212};
 213
 214/* -----------------------------------------------------------------------------
 215 * Type-definitions
 216 * -----------------------------------------------------------------------------
 217 */
 218typedef enum ud_type ud_type_t;
 219typedef enum ud_mnemonic_code ud_mnemonic_code_t;
 220
 221typedef struct ud ud_t;
 222typedef struct ud_operand ud_operand_t;
 223
 224#define UD_SYN_INTEL ud_translate_intel
 225#define UD_SYN_ATT ud_translate_att
 226#define UD_EOI -1
 227#define UD_INP_CACHE_SZ 32
 228#define UD_VENDOR_AMD 0
 229#define UD_VENDOR_INTEL 1
 230#define UD_VENDOR_ANY 2
 231
 232#define bail_out(ud,error_code) longjmp( (ud)->bailout, error_code )
 233#define try_decode(ud) if ( setjmp( (ud)->bailout ) == 0 )
 234#define catch_error() else
 235
 236#endif
0

Source/JavaScriptCore/jit/JITCode.h

2929#if ENABLE(JIT)
3030#include "CallFrame.h"
3131#include "JSValue.h"
 32#include "Disassembler.h"
3233#include "MacroAssemblerCodeRef.h"
3334#include "Profiler.h"
3435#endif

@@namespace JSC {
138139 ASSERT(m_ref.code().executableAddress());
139140 return m_ref.size();
140141 }
 142
 143 bool tryToDisassemble() const
 144 {
 145 return JSC::tryToDisassemble(start(), size(), WTF::dataFile());
 146 }
141147
142148 ExecutableMemoryHandle* getExecutableMemory()
143149 {
120550

Source/WTF/ChangeLog

 12012-06-17 Filip Pizlo <fpizlo@apple.com>
 2
 3 It should be possible to look at disassembly
 4 https://bugs.webkit.org/show_bug.cgi?id=89319
 5
 6 Reviewed by Sam Weinig.
 7
 8 Made changes to Assertions.h to make it friendly to C code again.
 9
 10 Added ENABLE(DISASSEMBLER) and USE(UDIS86) logic to Platform.h.
 11
 12 * wtf/Assertions.h:
 13 * wtf/Platform.h:
 14
1152012-06-17 Patrick Gansterer <paroga@webkit.org>
216
317 [WIN] Simplify implementation of currentTime()
120559

Source/WTF/wtf/Assertions.h

@@WTF_EXPORT_PRIVATE void WTFInvokeCrashHo
172172 WTFInvokeCrashHook(); \
173173 *(int *)(uintptr_t)0xbbadbeef = 0; \
174174 __builtin_trap(); \
175 } while (false)
 175} while (0)
176176#else
177177#define CRASH() do { \
178178 WTFReportBacktrace(); \
179179 WTFInvokeCrashHook(); \
180180 *(int *)(uintptr_t)0xbbadbeef = 0; \
181181 ((void(*)())0)(); /* More reliable, but doesn't say BBADBEEF */ \
182 } while (false)
 182} while (0)
183183#endif
184184#endif
185185
120550

Source/WTF/wtf/Platform.h

880880#define ENABLE_JIT 1
881881#endif
882882
 883/* If possible, try to enable a disassembler. This is optional. We proceed in two
 884 steps: first we try to find some disassembler that we can use, and then we
 885 decide if the high-level disassembler API can be enabled. */
 886#if !defined(WTF_USE_UDIS86) && ENABLE(JIT) && PLATFORM(MAC) && (CPU(X86) || CPU(X86_64))
 887#define WTF_USE_UDIS86 1
 888#endif
 889
 890#if !defined(ENABLE_DISASSEMBLER) && USE(UDIS86)
 891#define ENABLE_DISASSEMBLER 1
 892#endif
 893
883894/* On some of the platforms where we have a JIT, we want to also have the
884895 low-level interpreter. */
885896#if !defined(ENABLE_LLINT) \
120550